Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 30
- Boot result: PASS
- Errors: 1
- Warnings: 1
- Kernel Warnings: 13
1 20:14:18.814095 lava-dispatcher, installed at version: 2024.01
2 20:14:18.814299 start: 0 validate
3 20:14:18.814482 Start time: 2024-03-03 20:14:18.814474+00:00 (UTC)
4 20:14:18.814607 Using caching service: 'http://localhost/cache/?uri=%s'
5 20:14:18.814739 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 20:14:19.082951 Using caching service: 'http://localhost/cache/?uri=%s'
7 20:14:19.083114 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 20:14:19.348412 Using caching service: 'http://localhost/cache/?uri=%s'
9 20:14:19.348664 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 20:14:19.615596 Using caching service: 'http://localhost/cache/?uri=%s'
11 20:14:19.615865 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.78-cip15-547-gb5450675e67c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 20:14:19.884463 validate duration: 1.07
14 20:14:19.884921 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:14:19.885093 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:14:19.885239 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:14:19.885427 Not decompressing ramdisk as can be used compressed.
18 20:14:19.885568 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 20:14:19.885680 saving as /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/ramdisk/rootfs.cpio.gz
20 20:14:19.885806 total size: 26246609 (25 MB)
21 20:14:19.887453 progress 0 % (0 MB)
22 20:14:19.898341 progress 5 % (1 MB)
23 20:14:19.908852 progress 10 % (2 MB)
24 20:14:19.919296 progress 15 % (3 MB)
25 20:14:19.929594 progress 20 % (5 MB)
26 20:14:19.938183 progress 25 % (6 MB)
27 20:14:19.945110 progress 30 % (7 MB)
28 20:14:19.952103 progress 35 % (8 MB)
29 20:14:19.958983 progress 40 % (10 MB)
30 20:14:19.965864 progress 45 % (11 MB)
31 20:14:19.972722 progress 50 % (12 MB)
32 20:14:19.979575 progress 55 % (13 MB)
33 20:14:19.986373 progress 60 % (15 MB)
34 20:14:19.993241 progress 65 % (16 MB)
35 20:14:20.000855 progress 70 % (17 MB)
36 20:14:20.008183 progress 75 % (18 MB)
37 20:14:20.015153 progress 80 % (20 MB)
38 20:14:20.022288 progress 85 % (21 MB)
39 20:14:20.029943 progress 90 % (22 MB)
40 20:14:20.037361 progress 95 % (23 MB)
41 20:14:20.044394 progress 100 % (25 MB)
42 20:14:20.044679 25 MB downloaded in 0.16 s (157.54 MB/s)
43 20:14:20.044865 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:14:20.045156 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:14:20.045274 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:14:20.045387 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:14:20.045568 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 20:14:20.045653 saving as /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/kernel/Image
50 20:14:20.045715 total size: 51601920 (49 MB)
51 20:14:20.045810 No compression specified
52 20:14:20.047215 progress 0 % (0 MB)
53 20:14:20.060672 progress 5 % (2 MB)
54 20:14:20.074246 progress 10 % (4 MB)
55 20:14:20.087918 progress 15 % (7 MB)
56 20:14:20.101893 progress 20 % (9 MB)
57 20:14:20.115853 progress 25 % (12 MB)
58 20:14:20.129904 progress 30 % (14 MB)
59 20:14:20.143912 progress 35 % (17 MB)
60 20:14:20.157587 progress 40 % (19 MB)
61 20:14:20.171540 progress 45 % (22 MB)
62 20:14:20.185072 progress 50 % (24 MB)
63 20:14:20.198749 progress 55 % (27 MB)
64 20:14:20.212110 progress 60 % (29 MB)
65 20:14:20.225707 progress 65 % (32 MB)
66 20:14:20.239386 progress 70 % (34 MB)
67 20:14:20.252850 progress 75 % (36 MB)
68 20:14:20.266425 progress 80 % (39 MB)
69 20:14:20.280062 progress 85 % (41 MB)
70 20:14:20.293868 progress 90 % (44 MB)
71 20:14:20.307134 progress 95 % (46 MB)
72 20:14:20.320201 progress 100 % (49 MB)
73 20:14:20.320425 49 MB downloaded in 0.27 s (179.14 MB/s)
74 20:14:20.320575 end: 1.2.1 http-download (duration 00:00:00) [common]
76 20:14:20.320855 end: 1.2 download-retry (duration 00:00:00) [common]
77 20:14:20.320958 start: 1.3 download-retry (timeout 00:10:00) [common]
78 20:14:20.321044 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 20:14:20.321186 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 20:14:20.321269 saving as /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/dtb/mt8192-asurada-spherion-r0.dtb
81 20:14:20.321349 total size: 47278 (0 MB)
82 20:14:20.321441 No compression specified
83 20:14:20.322637 progress 69 % (0 MB)
84 20:14:20.322936 progress 100 % (0 MB)
85 20:14:20.323122 0 MB downloaded in 0.00 s (25.46 MB/s)
86 20:14:20.323262 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:14:20.323541 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:14:20.323655 start: 1.4 download-retry (timeout 00:10:00) [common]
90 20:14:20.323767 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 20:14:20.323913 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.78-cip15-547-gb5450675e67c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 20:14:20.323982 saving as /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/modules/modules.tar
93 20:14:20.324043 total size: 8632284 (8 MB)
94 20:14:20.324105 Using unxz to decompress xz
95 20:14:20.328442 progress 0 % (0 MB)
96 20:14:20.349673 progress 5 % (0 MB)
97 20:14:20.374158 progress 10 % (0 MB)
98 20:14:20.398835 progress 15 % (1 MB)
99 20:14:20.421690 progress 20 % (1 MB)
100 20:14:20.446257 progress 25 % (2 MB)
101 20:14:20.472693 progress 30 % (2 MB)
102 20:14:20.499296 progress 35 % (2 MB)
103 20:14:20.524987 progress 40 % (3 MB)
104 20:14:20.549690 progress 45 % (3 MB)
105 20:14:20.575073 progress 50 % (4 MB)
106 20:14:20.600006 progress 55 % (4 MB)
107 20:14:20.625392 progress 60 % (4 MB)
108 20:14:20.650550 progress 65 % (5 MB)
109 20:14:20.676189 progress 70 % (5 MB)
110 20:14:20.701407 progress 75 % (6 MB)
111 20:14:20.727922 progress 80 % (6 MB)
112 20:14:20.753261 progress 85 % (7 MB)
113 20:14:20.779795 progress 90 % (7 MB)
114 20:14:20.808521 progress 95 % (7 MB)
115 20:14:20.836966 progress 100 % (8 MB)
116 20:14:20.842343 8 MB downloaded in 0.52 s (15.88 MB/s)
117 20:14:20.842740 end: 1.4.1 http-download (duration 00:00:01) [common]
119 20:14:20.843210 end: 1.4 download-retry (duration 00:00:01) [common]
120 20:14:20.843368 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 20:14:20.843530 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 20:14:20.843673 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:14:20.843830 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 20:14:20.844172 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb
125 20:14:20.844392 makedir: /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin
126 20:14:20.844563 makedir: /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/tests
127 20:14:20.844731 makedir: /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/results
128 20:14:20.844915 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-add-keys
129 20:14:20.845157 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-add-sources
130 20:14:20.845369 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-background-process-start
131 20:14:20.845586 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-background-process-stop
132 20:14:20.845797 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-common-functions
133 20:14:20.846005 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-echo-ipv4
134 20:14:20.846213 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-install-packages
135 20:14:20.846460 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-installed-packages
136 20:14:20.846670 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-os-build
137 20:14:20.846880 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-probe-channel
138 20:14:20.847092 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-probe-ip
139 20:14:20.847304 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-target-ip
140 20:14:20.847512 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-target-mac
141 20:14:20.847718 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-target-storage
142 20:14:20.847931 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-case
143 20:14:20.848142 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-event
144 20:14:20.848352 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-feedback
145 20:14:20.848561 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-raise
146 20:14:20.848769 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-reference
147 20:14:20.848979 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-runner
148 20:14:20.849192 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-set
149 20:14:20.849404 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-test-shell
150 20:14:20.849618 Updating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-install-packages (oe)
151 20:14:20.849862 Updating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/bin/lava-installed-packages (oe)
152 20:14:20.850065 Creating /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/environment
153 20:14:20.850230 LAVA metadata
154 20:14:20.850362 - LAVA_JOB_ID=12928151
155 20:14:20.850522 - LAVA_DISPATCHER_IP=192.168.201.1
156 20:14:20.850700 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 20:14:20.850820 skipped lava-vland-overlay
158 20:14:20.850956 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 20:14:20.851115 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 20:14:20.851233 skipped lava-multinode-overlay
161 20:14:20.851364 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 20:14:20.851511 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 20:14:20.851642 Loading test definitions
164 20:14:20.851812 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 20:14:20.851952 Using /lava-12928151 at stage 0
166 20:14:20.852474 uuid=12928151_1.5.2.3.1 testdef=None
167 20:14:20.852619 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 20:14:20.852765 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 20:14:20.853684 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 20:14:20.854080 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 20:14:20.855160 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 20:14:20.855569 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 20:14:20.856596 runner path: /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/0/tests/0_v4l2-compliance-uvc test_uuid 12928151_1.5.2.3.1
176 20:14:20.856844 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 20:14:20.857217 Creating lava-test-runner.conf files
179 20:14:20.857327 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12928151/lava-overlay-360aj5cb/lava-12928151/0 for stage 0
180 20:14:20.857479 - 0_v4l2-compliance-uvc
181 20:14:20.857635 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 20:14:20.857817 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 20:14:20.869172 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 20:14:20.869347 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 20:14:20.869490 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 20:14:20.869636 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 20:14:20.869784 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 20:14:21.618870 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 20:14:21.619419 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 20:14:21.619598 extracting modules file /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12928151/extract-overlay-ramdisk-cf3ggffo/ramdisk
191 20:14:21.886636 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 20:14:21.886809 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 20:14:21.886904 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928151/compress-overlay-xkglloe5/overlay-1.5.2.4.tar.gz to ramdisk
194 20:14:21.886981 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12928151/compress-overlay-xkglloe5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12928151/extract-overlay-ramdisk-cf3ggffo/ramdisk
195 20:14:21.893667 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 20:14:21.893782 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 20:14:21.893875 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 20:14:21.893966 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 20:14:21.894045 Building ramdisk /var/lib/lava/dispatcher/tmp/12928151/extract-overlay-ramdisk-cf3ggffo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12928151/extract-overlay-ramdisk-cf3ggffo/ramdisk
200 20:14:22.543741 >> 228484 blocks
201 20:14:26.499953 rename /var/lib/lava/dispatcher/tmp/12928151/extract-overlay-ramdisk-cf3ggffo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/ramdisk/ramdisk.cpio.gz
202 20:14:26.500412 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 20:14:26.500535 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 20:14:26.500674 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 20:14:26.500798 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/kernel/Image'
206 20:14:40.067296 Returned 0 in 13 seconds
207 20:14:40.167936 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/kernel/image.itb
208 20:14:40.854957 output: FIT description: Kernel Image image with one or more FDT blobs
209 20:14:40.855473 output: Created: Sun Mar 3 20:14:40 2024
210 20:14:40.855610 output: Image 0 (kernel-1)
211 20:14:40.855731 output: Description:
212 20:14:40.855849 output: Created: Sun Mar 3 20:14:40 2024
213 20:14:40.855970 output: Type: Kernel Image
214 20:14:40.856088 output: Compression: lzma compressed
215 20:14:40.856198 output: Data Size: 12060038 Bytes = 11777.38 KiB = 11.50 MiB
216 20:14:40.856312 output: Architecture: AArch64
217 20:14:40.856420 output: OS: Linux
218 20:14:40.856523 output: Load Address: 0x00000000
219 20:14:40.856630 output: Entry Point: 0x00000000
220 20:14:40.856735 output: Hash algo: crc32
221 20:14:40.856838 output: Hash value: 91cb1a17
222 20:14:40.856943 output: Image 1 (fdt-1)
223 20:14:40.857052 output: Description: mt8192-asurada-spherion-r0
224 20:14:40.857159 output: Created: Sun Mar 3 20:14:40 2024
225 20:14:40.857263 output: Type: Flat Device Tree
226 20:14:40.857365 output: Compression: uncompressed
227 20:14:40.857471 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 20:14:40.857577 output: Architecture: AArch64
229 20:14:40.857679 output: Hash algo: crc32
230 20:14:40.857786 output: Hash value: cc4352de
231 20:14:40.857888 output: Image 2 (ramdisk-1)
232 20:14:40.857992 output: Description: unavailable
233 20:14:40.858096 output: Created: Sun Mar 3 20:14:40 2024
234 20:14:40.858198 output: Type: RAMDisk Image
235 20:14:40.858304 output: Compression: Unknown Compression
236 20:14:40.858429 output: Data Size: 39379936 Bytes = 38456.97 KiB = 37.56 MiB
237 20:14:40.858550 output: Architecture: AArch64
238 20:14:40.858651 output: OS: Linux
239 20:14:40.858754 output: Load Address: unavailable
240 20:14:40.858855 output: Entry Point: unavailable
241 20:14:40.858959 output: Hash algo: crc32
242 20:14:40.859061 output: Hash value: df77e006
243 20:14:40.859165 output: Default Configuration: 'conf-1'
244 20:14:40.859268 output: Configuration 0 (conf-1)
245 20:14:40.859372 output: Description: mt8192-asurada-spherion-r0
246 20:14:40.859479 output: Kernel: kernel-1
247 20:14:40.859580 output: Init Ramdisk: ramdisk-1
248 20:14:40.859709 output: FDT: fdt-1
249 20:14:40.859811 output: Loadables: kernel-1
250 20:14:40.859914 output:
251 20:14:40.860210 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 20:14:40.860381 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 20:14:40.860555 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 20:14:40.860711 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 20:14:40.860844 No LXC device requested
256 20:14:40.860987 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 20:14:40.861135 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 20:14:40.861274 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 20:14:40.861399 Checking files for TFTP limit of 4294967296 bytes.
260 20:14:40.862214 end: 1 tftp-deploy (duration 00:00:21) [common]
261 20:14:40.862406 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 20:14:40.862572 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 20:14:40.862778 substitutions:
264 20:14:40.862895 - {DTB}: 12928151/tftp-deploy-nv35dnge/dtb/mt8192-asurada-spherion-r0.dtb
265 20:14:40.863012 - {INITRD}: 12928151/tftp-deploy-nv35dnge/ramdisk/ramdisk.cpio.gz
266 20:14:40.863120 - {KERNEL}: 12928151/tftp-deploy-nv35dnge/kernel/Image
267 20:14:40.863229 - {LAVA_MAC}: None
268 20:14:40.863337 - {PRESEED_CONFIG}: None
269 20:14:40.863442 - {PRESEED_LOCAL}: None
270 20:14:40.863551 - {RAMDISK}: 12928151/tftp-deploy-nv35dnge/ramdisk/ramdisk.cpio.gz
271 20:14:40.863658 - {ROOT_PART}: None
272 20:14:40.863759 - {ROOT}: None
273 20:14:40.863862 - {SERVER_IP}: 192.168.201.1
274 20:14:40.863964 - {TEE}: None
275 20:14:40.864068 Parsed boot commands:
276 20:14:40.864171 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 20:14:40.864456 Parsed boot commands: tftpboot 192.168.201.1 12928151/tftp-deploy-nv35dnge/kernel/image.itb 12928151/tftp-deploy-nv35dnge/kernel/cmdline
278 20:14:40.864606 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 20:14:40.864751 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 20:14:40.864908 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 20:14:40.865060 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 20:14:40.865181 Not connected, no need to disconnect.
283 20:14:40.865312 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 20:14:40.865453 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 20:14:40.865571 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 20:14:40.870654 Setting prompt string to ['lava-test: # ']
287 20:14:40.871144 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 20:14:40.871332 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 20:14:40.871553 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 20:14:40.871769 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 20:14:40.872168 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 20:14:46.006096 >> Command sent successfully.
293 20:14:46.008884 Returned 0 in 5 seconds
294 20:14:46.109298 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 20:14:46.109624 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 20:14:46.109723 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 20:14:46.109808 Setting prompt string to 'Starting depthcharge on Spherion...'
299 20:14:46.109878 Changing prompt to 'Starting depthcharge on Spherion...'
300 20:14:46.109957 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 20:14:46.110223 [Enter `^Ec?' for help]
302 20:14:46.284690
303 20:14:46.284841
304 20:14:46.284908 F0: 102B 0000
305 20:14:46.284972
306 20:14:46.285036 F3: 1001 0000 [0200]
307 20:14:46.285094
308 20:14:46.288471 F3: 1001 0000
309 20:14:46.288554
310 20:14:46.288620 F7: 102D 0000
311 20:14:46.288680
312 20:14:46.288739 F1: 0000 0000
313 20:14:46.292211
314 20:14:46.292295 V0: 0000 0000 [0001]
315 20:14:46.292363
316 20:14:46.292424 00: 0007 8000
317 20:14:46.292487
318 20:14:46.296257 01: 0000 0000
319 20:14:46.296341
320 20:14:46.296408 BP: 0C00 0209 [0000]
321 20:14:46.296469
322 20:14:46.300009 G0: 1182 0000
323 20:14:46.300121
324 20:14:46.300187 EC: 0000 0021 [4000]
325 20:14:46.300246
326 20:14:46.303338 S7: 0000 0000 [0000]
327 20:14:46.303420
328 20:14:46.303484 CC: 0000 0000 [0001]
329 20:14:46.303545
330 20:14:46.307133 T0: 0000 0040 [010F]
331 20:14:46.307216
332 20:14:46.307281 Jump to BL
333 20:14:46.307341
334 20:14:46.331465
335 20:14:46.331548
336 20:14:46.331613
337 20:14:46.339130 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 20:14:46.342640 ARM64: Exception handlers installed.
339 20:14:46.346690 ARM64: Testing exception
340 20:14:46.350082 ARM64: Done test exception
341 20:14:46.357504 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 20:14:46.364537 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 20:14:46.371329 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 20:14:46.382068 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 20:14:46.388880 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 20:14:46.399447 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 20:14:46.409880 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 20:14:46.416576 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 20:14:46.434930 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 20:14:46.437770 WDT: Last reset was cold boot
351 20:14:46.441508 SPI1(PAD0) initialized at 2873684 Hz
352 20:14:46.444307 SPI5(PAD0) initialized at 992727 Hz
353 20:14:46.447986 VBOOT: Loading verstage.
354 20:14:46.455134 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 20:14:46.457741 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 20:14:46.461646 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 20:14:46.464606 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 20:14:46.472224 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 20:14:46.478974 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 20:14:46.489290 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 20:14:46.489373
362 20:14:46.489438
363 20:14:46.499358 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 20:14:46.503017 ARM64: Exception handlers installed.
365 20:14:46.506252 ARM64: Testing exception
366 20:14:46.506359 ARM64: Done test exception
367 20:14:46.512517 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 20:14:46.515780 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 20:14:46.531332 Probing TPM: . done!
370 20:14:46.531416 TPM ready after 0 ms
371 20:14:46.539129 Connected to device vid:did:rid of 1ae0:0028:00
372 20:14:46.545318 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 20:14:46.601614 Initialized TPM device CR50 revision 0
374 20:14:46.613100 tlcl_send_startup: Startup return code is 0
375 20:14:46.613243 TPM: setup succeeded
376 20:14:46.624918 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 20:14:46.633517 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 20:14:46.645077 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 20:14:46.654680 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 20:14:46.657602 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 20:14:46.666026 in-header: 03 07 00 00 08 00 00 00
382 20:14:46.669298 in-data: aa e4 47 04 13 02 00 00
383 20:14:46.673004 Chrome EC: UHEPI supported
384 20:14:46.680863 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 20:14:46.685368 in-header: 03 ad 00 00 08 00 00 00
386 20:14:46.685452 in-data: 00 20 20 08 00 00 00 00
387 20:14:46.687788 Phase 1
388 20:14:46.691609 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 20:14:46.695118 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 20:14:46.703333 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 20:14:46.706640 Recovery requested (1009000e)
392 20:14:46.715444 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 20:14:46.719428 tlcl_extend: response is 0
394 20:14:46.729658 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 20:14:46.734490 tlcl_extend: response is 0
396 20:14:46.741930 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 20:14:46.761170 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 20:14:46.767796 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 20:14:46.767879
400 20:14:46.767944
401 20:14:46.778191 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 20:14:46.782067 ARM64: Exception handlers installed.
403 20:14:46.782175 ARM64: Testing exception
404 20:14:46.785801 ARM64: Done test exception
405 20:14:46.806381 pmic_efuse_setting: Set efuses in 11 msecs
406 20:14:46.810284 pmwrap_interface_init: Select PMIF_VLD_RDY
407 20:14:46.817268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 20:14:46.819975 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 20:14:46.827324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 20:14:46.831043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 20:14:46.834136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 20:14:46.841307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 20:14:46.845290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 20:14:46.849336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 20:14:46.852556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 20:14:46.859989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 20:14:46.863556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 20:14:46.867341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 20:14:46.870598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 20:14:46.879023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 20:14:46.886309 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 20:14:46.890086 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 20:14:46.897460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 20:14:46.901304 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 20:14:46.908401 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 20:14:46.912630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 20:14:46.920146 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 20:14:46.923916 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 20:14:46.930584 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 20:14:46.934530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 20:14:46.941626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 20:14:46.945660 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 20:14:46.953230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 20:14:46.956875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 20:14:46.960207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 20:14:46.963626 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 20:14:46.971509 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 20:14:46.975015 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 20:14:46.982169 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 20:14:46.985870 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 20:14:46.989646 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 20:14:46.997205 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 20:14:47.000788 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 20:14:47.004239 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 20:14:47.011467 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 20:14:47.015570 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 20:14:47.019730 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 20:14:47.022589 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 20:14:47.025954 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 20:14:47.033828 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 20:14:47.037330 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 20:14:47.041459 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 20:14:47.045711 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 20:14:47.048967 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 20:14:47.052550 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 20:14:47.056157 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 20:14:47.063778 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 20:14:47.070927 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 20:14:47.077775 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 20:14:47.081326 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 20:14:47.092226 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 20:14:47.100079 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 20:14:47.103156 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 20:14:47.106752 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 20:14:47.114156 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 20:14:47.121722 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
467 20:14:47.125683 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 20:14:47.128992 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 20:14:47.133317 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 20:14:47.144703 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 20:14:47.153112 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 20:14:47.163324 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 20:14:47.172303 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 20:14:47.182187 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 20:14:47.191746 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 20:14:47.202471 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 20:14:47.206612 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 20:14:47.210098 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 20:14:47.213539 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 20:14:47.217202 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 20:14:47.224723 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 20:14:47.228094 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 20:14:47.228223 ADC[4]: Raw value=901328 ID=7
484 20:14:47.232351 ADC[3]: Raw value=213336 ID=1
485 20:14:47.236158 RAM Code: 0x71
486 20:14:47.239809 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 20:14:47.243028 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 20:14:47.250870 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 20:14:47.258555 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 20:14:47.262785 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 20:14:47.266673 in-header: 03 07 00 00 08 00 00 00
492 20:14:47.269921 in-data: aa e4 47 04 13 02 00 00
493 20:14:47.270047 Chrome EC: UHEPI supported
494 20:14:47.276469 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 20:14:47.280650 in-header: 03 ed 00 00 08 00 00 00
496 20:14:47.284513 in-data: 80 20 60 08 00 00 00 00
497 20:14:47.287783 MRC: failed to locate region type 0.
498 20:14:47.295013 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 20:14:47.299953 DRAM-K: Running full calibration
500 20:14:47.302909 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 20:14:47.306291 header.status = 0x0
502 20:14:47.310204 header.version = 0x6 (expected: 0x6)
503 20:14:47.313905 header.size = 0xd00 (expected: 0xd00)
504 20:14:47.314025 header.flags = 0x0
505 20:14:47.320786 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 20:14:47.338756 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 20:14:47.345719 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 20:14:47.349438 dram_init: ddr_geometry: 2
509 20:14:47.349538 [EMI] MDL number = 2
510 20:14:47.354021 [EMI] Get MDL freq = 0
511 20:14:47.354156 dram_init: ddr_type: 0
512 20:14:47.356793 is_discrete_lpddr4: 1
513 20:14:47.360877 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 20:14:47.361005
515 20:14:47.361148
516 20:14:47.361294 [Bian_co] ETT version 0.0.0.1
517 20:14:47.368623 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 20:14:47.368709
519 20:14:47.371720 dramc_set_vcore_voltage set vcore to 650000
520 20:14:47.371849 Read voltage for 800, 4
521 20:14:47.371964 Vio18 = 0
522 20:14:47.375996 Vcore = 650000
523 20:14:47.376121 Vdram = 0
524 20:14:47.376287 Vddq = 0
525 20:14:47.379859 Vmddr = 0
526 20:14:47.379982 dram_init: config_dvfs: 1
527 20:14:47.386241 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 20:14:47.389662 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 20:14:47.395580 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 20:14:47.399394 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 20:14:47.402519 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 20:14:47.405678 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 20:14:47.409351 MEM_TYPE=3, freq_sel=18
534 20:14:47.413639 sv_algorithm_assistance_LP4_1600
535 20:14:47.416006 ============ PULL DRAM RESETB DOWN ============
536 20:14:47.419546 ========== PULL DRAM RESETB DOWN end =========
537 20:14:47.422776 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 20:14:47.426631 ===================================
539 20:14:47.428949 LPDDR4 DRAM CONFIGURATION
540 20:14:47.432829 ===================================
541 20:14:47.435919 EX_ROW_EN[0] = 0x0
542 20:14:47.436046 EX_ROW_EN[1] = 0x0
543 20:14:47.439070 LP4Y_EN = 0x0
544 20:14:47.439197 WORK_FSP = 0x0
545 20:14:47.442708 WL = 0x2
546 20:14:47.442791 RL = 0x2
547 20:14:47.445970 BL = 0x2
548 20:14:47.446081 RPST = 0x0
549 20:14:47.449453 RD_PRE = 0x0
550 20:14:47.449538 WR_PRE = 0x1
551 20:14:47.452574 WR_PST = 0x0
552 20:14:47.452664 DBI_WR = 0x0
553 20:14:47.455723 DBI_RD = 0x0
554 20:14:47.455808 OTF = 0x1
555 20:14:47.459289 ===================================
556 20:14:47.462482 ===================================
557 20:14:47.466221 ANA top config
558 20:14:47.469263 ===================================
559 20:14:47.472810 DLL_ASYNC_EN = 0
560 20:14:47.472897 ALL_SLAVE_EN = 1
561 20:14:47.476089 NEW_RANK_MODE = 1
562 20:14:47.479161 DLL_IDLE_MODE = 1
563 20:14:47.483170 LP45_APHY_COMB_EN = 1
564 20:14:47.483255 TX_ODT_DIS = 1
565 20:14:47.487275 NEW_8X_MODE = 1
566 20:14:47.489496 ===================================
567 20:14:47.493261 ===================================
568 20:14:47.496360 data_rate = 1600
569 20:14:47.499639 CKR = 1
570 20:14:47.503171 DQ_P2S_RATIO = 8
571 20:14:47.506715 ===================================
572 20:14:47.506798 CA_P2S_RATIO = 8
573 20:14:47.509994 DQ_CA_OPEN = 0
574 20:14:47.513286 DQ_SEMI_OPEN = 0
575 20:14:47.516374 CA_SEMI_OPEN = 0
576 20:14:47.519470 CA_FULL_RATE = 0
577 20:14:47.523437 DQ_CKDIV4_EN = 1
578 20:14:47.523544 CA_CKDIV4_EN = 1
579 20:14:47.526766 CA_PREDIV_EN = 0
580 20:14:47.530127 PH8_DLY = 0
581 20:14:47.533151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 20:14:47.536458 DQ_AAMCK_DIV = 4
583 20:14:47.539974 CA_AAMCK_DIV = 4
584 20:14:47.540060 CA_ADMCK_DIV = 4
585 20:14:47.543268 DQ_TRACK_CA_EN = 0
586 20:14:47.546569 CA_PICK = 800
587 20:14:47.549836 CA_MCKIO = 800
588 20:14:47.553214 MCKIO_SEMI = 0
589 20:14:47.556773 PLL_FREQ = 3068
590 20:14:47.556856 DQ_UI_PI_RATIO = 32
591 20:14:47.560458 CA_UI_PI_RATIO = 0
592 20:14:47.564327 ===================================
593 20:14:47.568417 ===================================
594 20:14:47.568546 memory_type:LPDDR4
595 20:14:47.572091 GP_NUM : 10
596 20:14:47.572175 SRAM_EN : 1
597 20:14:47.576066 MD32_EN : 0
598 20:14:47.579898 ===================================
599 20:14:47.584041 [ANA_INIT] >>>>>>>>>>>>>>
600 20:14:47.584128 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 20:14:47.587700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 20:14:47.591305 ===================================
603 20:14:47.594654 data_rate = 1600,PCW = 0X7600
604 20:14:47.598156 ===================================
605 20:14:47.601834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 20:14:47.605076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 20:14:47.611260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 20:14:47.614958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 20:14:47.621389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 20:14:47.625154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 20:14:47.625236 [ANA_INIT] flow start
612 20:14:47.628635 [ANA_INIT] PLL >>>>>>>>
613 20:14:47.628718 [ANA_INIT] PLL <<<<<<<<
614 20:14:47.631662 [ANA_INIT] MIDPI >>>>>>>>
615 20:14:47.634825 [ANA_INIT] MIDPI <<<<<<<<
616 20:14:47.638711 [ANA_INIT] DLL >>>>>>>>
617 20:14:47.638792 [ANA_INIT] flow end
618 20:14:47.642320 ============ LP4 DIFF to SE enter ============
619 20:14:47.648315 ============ LP4 DIFF to SE exit ============
620 20:14:47.648398 [ANA_INIT] <<<<<<<<<<<<<
621 20:14:47.652732 [Flow] Enable top DCM control >>>>>
622 20:14:47.655227 [Flow] Enable top DCM control <<<<<
623 20:14:47.658266 Enable DLL master slave shuffle
624 20:14:47.665298 ==============================================================
625 20:14:47.665380 Gating Mode config
626 20:14:47.672528 ==============================================================
627 20:14:47.675330 Config description:
628 20:14:47.682184 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 20:14:47.688609 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 20:14:47.695265 SELPH_MODE 0: By rank 1: By Phase
631 20:14:47.698969 ==============================================================
632 20:14:47.702557 GAT_TRACK_EN = 1
633 20:14:47.705647 RX_GATING_MODE = 2
634 20:14:47.708914 RX_GATING_TRACK_MODE = 2
635 20:14:47.712064 SELPH_MODE = 1
636 20:14:47.715393 PICG_EARLY_EN = 1
637 20:14:47.718875 VALID_LAT_VALUE = 1
638 20:14:47.725402 ==============================================================
639 20:14:47.728821 Enter into Gating configuration >>>>
640 20:14:47.728922 Exit from Gating configuration <<<<
641 20:14:47.732336 Enter into DVFS_PRE_config >>>>>
642 20:14:47.746317 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 20:14:47.749098 Exit from DVFS_PRE_config <<<<<
644 20:14:47.752833 Enter into PICG configuration >>>>
645 20:14:47.752915 Exit from PICG configuration <<<<
646 20:14:47.755415 [RX_INPUT] configuration >>>>>
647 20:14:47.759821 [RX_INPUT] configuration <<<<<
648 20:14:47.766213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 20:14:47.768850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 20:14:47.776348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 20:14:47.783089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 20:14:47.789684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 20:14:47.796669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 20:14:47.800250 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 20:14:47.803688 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 20:14:47.807347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 20:14:47.810779 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 20:14:47.817164 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 20:14:47.820206 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 20:14:47.823883 ===================================
661 20:14:47.827388 LPDDR4 DRAM CONFIGURATION
662 20:14:47.830451 ===================================
663 20:14:47.830574 EX_ROW_EN[0] = 0x0
664 20:14:47.833593 EX_ROW_EN[1] = 0x0
665 20:14:47.833715 LP4Y_EN = 0x0
666 20:14:47.837141 WORK_FSP = 0x0
667 20:14:47.837262 WL = 0x2
668 20:14:47.840196 RL = 0x2
669 20:14:47.840320 BL = 0x2
670 20:14:47.843991 RPST = 0x0
671 20:14:47.844094 RD_PRE = 0x0
672 20:14:47.847055 WR_PRE = 0x1
673 20:14:47.847154 WR_PST = 0x0
674 20:14:47.850170 DBI_WR = 0x0
675 20:14:47.850266 DBI_RD = 0x0
676 20:14:47.854330 OTF = 0x1
677 20:14:47.856984 ===================================
678 20:14:47.861220 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 20:14:47.863790 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 20:14:47.870378 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 20:14:47.873495 ===================================
682 20:14:47.873568 LPDDR4 DRAM CONFIGURATION
683 20:14:47.877391 ===================================
684 20:14:47.880260 EX_ROW_EN[0] = 0x10
685 20:14:47.884313 EX_ROW_EN[1] = 0x0
686 20:14:47.884396 LP4Y_EN = 0x0
687 20:14:47.887837 WORK_FSP = 0x0
688 20:14:47.887921 WL = 0x2
689 20:14:47.890832 RL = 0x2
690 20:14:47.890915 BL = 0x2
691 20:14:47.893572 RPST = 0x0
692 20:14:47.893655 RD_PRE = 0x0
693 20:14:47.896788 WR_PRE = 0x1
694 20:14:47.896871 WR_PST = 0x0
695 20:14:47.900500 DBI_WR = 0x0
696 20:14:47.900583 DBI_RD = 0x0
697 20:14:47.903785 OTF = 0x1
698 20:14:47.907431 ===================================
699 20:14:47.913845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 20:14:47.917128 nWR fixed to 40
701 20:14:47.917212 [ModeRegInit_LP4] CH0 RK0
702 20:14:47.920647 [ModeRegInit_LP4] CH0 RK1
703 20:14:47.923936 [ModeRegInit_LP4] CH1 RK0
704 20:14:47.924018 [ModeRegInit_LP4] CH1 RK1
705 20:14:47.926921 match AC timing 13
706 20:14:47.930310 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 20:14:47.933758 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 20:14:47.940278 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 20:14:47.943971 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 20:14:47.951412 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 20:14:47.951496 [EMI DOE] emi_dcm 0
712 20:14:47.954129 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 20:14:47.957451 ==
714 20:14:47.960787 Dram Type= 6, Freq= 0, CH_0, rank 0
715 20:14:47.963944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 20:14:47.964027 ==
717 20:14:47.967317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 20:14:47.974681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 20:14:47.983722 [CA 0] Center 37 (7~68) winsize 62
720 20:14:47.986836 [CA 1] Center 37 (6~68) winsize 63
721 20:14:47.990303 [CA 2] Center 35 (4~66) winsize 63
722 20:14:47.993721 [CA 3] Center 34 (4~65) winsize 62
723 20:14:47.996905 [CA 4] Center 34 (3~65) winsize 63
724 20:14:48.000409 [CA 5] Center 33 (3~64) winsize 62
725 20:14:48.000491
726 20:14:48.003965 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 20:14:48.004048
728 20:14:48.007692 [CATrainingPosCal] consider 1 rank data
729 20:14:48.011279 u2DelayCellTimex100 = 270/100 ps
730 20:14:48.013884 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 20:14:48.017050 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 20:14:48.025074 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
733 20:14:48.027457 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 20:14:48.030729 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 20:14:48.034126 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 20:14:48.034251
737 20:14:48.037283 CA PerBit enable=1, Macro0, CA PI delay=33
738 20:14:48.037405
739 20:14:48.040714 [CBTSetCACLKResult] CA Dly = 33
740 20:14:48.040834 CS Dly: 5 (0~36)
741 20:14:48.040949 ==
742 20:14:48.043831 Dram Type= 6, Freq= 0, CH_0, rank 1
743 20:14:48.050914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 20:14:48.050999 ==
745 20:14:48.054499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 20:14:48.061380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 20:14:48.069862 [CA 0] Center 37 (6~68) winsize 63
748 20:14:48.074266 [CA 1] Center 37 (7~68) winsize 62
749 20:14:48.077089 [CA 2] Center 35 (5~66) winsize 62
750 20:14:48.080423 [CA 3] Center 35 (4~66) winsize 63
751 20:14:48.083126 [CA 4] Center 34 (3~65) winsize 63
752 20:14:48.086853 [CA 5] Center 33 (3~64) winsize 62
753 20:14:48.086936
754 20:14:48.090009 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 20:14:48.090092
756 20:14:48.093609 [CATrainingPosCal] consider 2 rank data
757 20:14:48.097024 u2DelayCellTimex100 = 270/100 ps
758 20:14:48.099895 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 20:14:48.103581 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 20:14:48.106899 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 20:14:48.113603 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 20:14:48.116893 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 20:14:48.120228 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 20:14:48.120353
765 20:14:48.123331 CA PerBit enable=1, Macro0, CA PI delay=33
766 20:14:48.123452
767 20:14:48.127134 [CBTSetCACLKResult] CA Dly = 33
768 20:14:48.127255 CS Dly: 6 (0~38)
769 20:14:48.127370
770 20:14:48.130301 ----->DramcWriteLeveling(PI) begin...
771 20:14:48.130465 ==
772 20:14:48.133670 Dram Type= 6, Freq= 0, CH_0, rank 0
773 20:14:48.141008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 20:14:48.141132 ==
775 20:14:48.141246 Write leveling (Byte 0): 29 => 29
776 20:14:48.144831 Write leveling (Byte 1): 32 => 32
777 20:14:48.148544 DramcWriteLeveling(PI) end<-----
778 20:14:48.148666
779 20:14:48.148777 ==
780 20:14:48.152480 Dram Type= 6, Freq= 0, CH_0, rank 0
781 20:14:48.155951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 20:14:48.156076 ==
783 20:14:48.159412 [Gating] SW mode calibration
784 20:14:48.166290 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 20:14:48.169962 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 20:14:48.176281 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 20:14:48.179704 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 20:14:48.184227 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 20:14:48.190187 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
790 20:14:48.193361 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 20:14:48.196594 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 20:14:48.204108 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 20:14:48.207562 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 20:14:48.209953 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 20:14:48.217263 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 20:14:48.220166 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 20:14:48.224315 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 20:14:48.227043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 20:14:48.233442 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 20:14:48.237321 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 20:14:48.240202 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 20:14:48.247194 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 20:14:48.250762 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 20:14:48.253825 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
805 20:14:48.260649 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 20:14:48.264149 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 20:14:48.267148 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 20:14:48.274224 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 20:14:48.277332 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 20:14:48.280471 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 20:14:48.283833 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 20:14:48.290754 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
813 20:14:48.294408 0 9 12 | B1->B0 | 2727 3131 | 1 0 | (1 1) (0 0)
814 20:14:48.297855 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 20:14:48.304363 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 20:14:48.307380 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 20:14:48.310576 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 20:14:48.317626 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 20:14:48.321129 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
820 20:14:48.323969 0 10 8 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (1 1)
821 20:14:48.330592 0 10 12 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
822 20:14:48.333959 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 20:14:48.337461 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 20:14:48.344203 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 20:14:48.347616 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 20:14:48.351277 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 20:14:48.357417 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 20:14:48.360889 0 11 8 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (1 1)
829 20:14:48.364322 0 11 12 | B1->B0 | 3939 4343 | 1 0 | (0 0) (0 0)
830 20:14:48.367575 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 20:14:48.374000 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 20:14:48.377572 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 20:14:48.380680 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 20:14:48.387853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 20:14:48.391149 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 20:14:48.394566 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 20:14:48.401459 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 20:14:48.404220 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 20:14:48.407682 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 20:14:48.414650 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 20:14:48.417673 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 20:14:48.421181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 20:14:48.427747 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 20:14:48.431117 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 20:14:48.434771 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 20:14:48.438214 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 20:14:48.444904 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 20:14:48.448031 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 20:14:48.451276 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 20:14:48.458392 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 20:14:48.461419 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 20:14:48.464609 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 20:14:48.471465 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 20:14:48.471548 Total UI for P1: 0, mck2ui 16
855 20:14:48.478333 best dqsien dly found for B0: ( 0, 14, 6)
856 20:14:48.478472 Total UI for P1: 0, mck2ui 16
857 20:14:48.481312 best dqsien dly found for B1: ( 0, 14, 10)
858 20:14:48.488318 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 20:14:48.491808 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 20:14:48.491890
861 20:14:48.494940 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 20:14:48.498201 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 20:14:48.501999 [Gating] SW calibration Done
864 20:14:48.502109 ==
865 20:14:48.505267 Dram Type= 6, Freq= 0, CH_0, rank 0
866 20:14:48.508307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 20:14:48.508391 ==
868 20:14:48.511529 RX Vref Scan: 0
869 20:14:48.511611
870 20:14:48.511676 RX Vref 0 -> 0, step: 1
871 20:14:48.511736
872 20:14:48.515122 RX Delay -130 -> 252, step: 16
873 20:14:48.518172 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 20:14:48.521844 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 20:14:48.529054 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 20:14:48.532286 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 20:14:48.535454 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 20:14:48.538545 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 20:14:48.542043 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 20:14:48.545428 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 20:14:48.552780 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 20:14:48.555742 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 20:14:48.558843 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 20:14:48.562312 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 20:14:48.565449 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 20:14:48.572573 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 20:14:48.576309 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 20:14:48.579128 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 20:14:48.579210 ==
890 20:14:48.582391 Dram Type= 6, Freq= 0, CH_0, rank 0
891 20:14:48.585990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 20:14:48.586115 ==
893 20:14:48.589122 DQS Delay:
894 20:14:48.589247 DQS0 = 0, DQS1 = 0
895 20:14:48.592832 DQM Delay:
896 20:14:48.592956 DQM0 = 84, DQM1 = 79
897 20:14:48.593071 DQ Delay:
898 20:14:48.595512 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 20:14:48.598981 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 20:14:48.602256 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
901 20:14:48.605706 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 20:14:48.605789
903 20:14:48.605854
904 20:14:48.609648 ==
905 20:14:48.609730 Dram Type= 6, Freq= 0, CH_0, rank 0
906 20:14:48.615813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 20:14:48.615896 ==
908 20:14:48.615962
909 20:14:48.616023
910 20:14:48.616081 TX Vref Scan disable
911 20:14:48.619658 == TX Byte 0 ==
912 20:14:48.623067 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 20:14:48.626373 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 20:14:48.630051 == TX Byte 1 ==
915 20:14:48.633279 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
916 20:14:48.636346 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
917 20:14:48.640266 ==
918 20:14:48.643616 Dram Type= 6, Freq= 0, CH_0, rank 0
919 20:14:48.646589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 20:14:48.646698 ==
921 20:14:48.658855 TX Vref=22, minBit 3, minWin=27, winSum=442
922 20:14:48.662143 TX Vref=24, minBit 5, minWin=27, winSum=445
923 20:14:48.665661 TX Vref=26, minBit 9, minWin=27, winSum=449
924 20:14:48.668810 TX Vref=28, minBit 12, minWin=27, winSum=452
925 20:14:48.672395 TX Vref=30, minBit 2, minWin=28, winSum=454
926 20:14:48.675727 TX Vref=32, minBit 0, minWin=28, winSum=453
927 20:14:48.682329 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
928 20:14:48.682472
929 20:14:48.686646 Final TX Range 1 Vref 30
930 20:14:48.686729
931 20:14:48.686802 ==
932 20:14:48.689412 Dram Type= 6, Freq= 0, CH_0, rank 0
933 20:14:48.692568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 20:14:48.692650 ==
935 20:14:48.692715
936 20:14:48.692777
937 20:14:48.695900 TX Vref Scan disable
938 20:14:48.699532 == TX Byte 0 ==
939 20:14:48.702366 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 20:14:48.705657 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 20:14:48.709053 == TX Byte 1 ==
942 20:14:48.712971 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 20:14:48.716471 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 20:14:48.716554
945 20:14:48.719133 [DATLAT]
946 20:14:48.719214 Freq=800, CH0 RK0
947 20:14:48.719279
948 20:14:48.722609 DATLAT Default: 0xa
949 20:14:48.722691 0, 0xFFFF, sum = 0
950 20:14:48.725941 1, 0xFFFF, sum = 0
951 20:14:48.726024 2, 0xFFFF, sum = 0
952 20:14:48.729227 3, 0xFFFF, sum = 0
953 20:14:48.729310 4, 0xFFFF, sum = 0
954 20:14:48.732886 5, 0xFFFF, sum = 0
955 20:14:48.733015 6, 0xFFFF, sum = 0
956 20:14:48.735999 7, 0xFFFF, sum = 0
957 20:14:48.736124 8, 0xFFFF, sum = 0
958 20:14:48.739534 9, 0x0, sum = 1
959 20:14:48.739658 10, 0x0, sum = 2
960 20:14:48.743077 11, 0x0, sum = 3
961 20:14:48.743199 12, 0x0, sum = 4
962 20:14:48.746106 best_step = 10
963 20:14:48.746226
964 20:14:48.746341 ==
965 20:14:48.749483 Dram Type= 6, Freq= 0, CH_0, rank 0
966 20:14:48.753154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 20:14:48.753275 ==
968 20:14:48.753390 RX Vref Scan: 1
969 20:14:48.756161
970 20:14:48.756284 Set Vref Range= 32 -> 127
971 20:14:48.756394
972 20:14:48.759886 RX Vref 32 -> 127, step: 1
973 20:14:48.760009
974 20:14:48.763492 RX Delay -95 -> 252, step: 8
975 20:14:48.763615
976 20:14:48.766493 Set Vref, RX VrefLevel [Byte0]: 32
977 20:14:48.769754 [Byte1]: 32
978 20:14:48.769877
979 20:14:48.773082 Set Vref, RX VrefLevel [Byte0]: 33
980 20:14:48.776898 [Byte1]: 33
981 20:14:48.777019
982 20:14:48.779975 Set Vref, RX VrefLevel [Byte0]: 34
983 20:14:48.783353 [Byte1]: 34
984 20:14:48.786723
985 20:14:48.786804 Set Vref, RX VrefLevel [Byte0]: 35
986 20:14:48.789921 [Byte1]: 35
987 20:14:48.794557
988 20:14:48.794638 Set Vref, RX VrefLevel [Byte0]: 36
989 20:14:48.797938 [Byte1]: 36
990 20:14:48.803068
991 20:14:48.803150 Set Vref, RX VrefLevel [Byte0]: 37
992 20:14:48.805706 [Byte1]: 37
993 20:14:48.810740
994 20:14:48.810822 Set Vref, RX VrefLevel [Byte0]: 38
995 20:14:48.813321 [Byte1]: 38
996 20:14:48.817729
997 20:14:48.817810 Set Vref, RX VrefLevel [Byte0]: 39
998 20:14:48.821646 [Byte1]: 39
999 20:14:48.825850
1000 20:14:48.825932 Set Vref, RX VrefLevel [Byte0]: 40
1001 20:14:48.828916 [Byte1]: 40
1002 20:14:48.833224
1003 20:14:48.833305 Set Vref, RX VrefLevel [Byte0]: 41
1004 20:14:48.836440 [Byte1]: 41
1005 20:14:48.840180
1006 20:14:48.840262 Set Vref, RX VrefLevel [Byte0]: 42
1007 20:14:48.843540 [Byte1]: 42
1008 20:14:48.847614
1009 20:14:48.847695 Set Vref, RX VrefLevel [Byte0]: 43
1010 20:14:48.851925 [Byte1]: 43
1011 20:14:48.855526
1012 20:14:48.855608 Set Vref, RX VrefLevel [Byte0]: 44
1013 20:14:48.858708 [Byte1]: 44
1014 20:14:48.863066
1015 20:14:48.863147 Set Vref, RX VrefLevel [Byte0]: 45
1016 20:14:48.865897 [Byte1]: 45
1017 20:14:48.870214
1018 20:14:48.870297 Set Vref, RX VrefLevel [Byte0]: 46
1019 20:14:48.874599 [Byte1]: 46
1020 20:14:48.878068
1021 20:14:48.878150 Set Vref, RX VrefLevel [Byte0]: 47
1022 20:14:48.881440 [Byte1]: 47
1023 20:14:48.885481
1024 20:14:48.885562 Set Vref, RX VrefLevel [Byte0]: 48
1025 20:14:48.889350 [Byte1]: 48
1026 20:14:48.893322
1027 20:14:48.896645 Set Vref, RX VrefLevel [Byte0]: 49
1028 20:14:48.896726 [Byte1]: 49
1029 20:14:48.900723
1030 20:14:48.900803 Set Vref, RX VrefLevel [Byte0]: 50
1031 20:14:48.904090 [Byte1]: 50
1032 20:14:48.908247
1033 20:14:48.908330 Set Vref, RX VrefLevel [Byte0]: 51
1034 20:14:48.911406 [Byte1]: 51
1035 20:14:48.916404
1036 20:14:48.916484 Set Vref, RX VrefLevel [Byte0]: 52
1037 20:14:48.919358 [Byte1]: 52
1038 20:14:48.924136
1039 20:14:48.924215 Set Vref, RX VrefLevel [Byte0]: 53
1040 20:14:48.927229 [Byte1]: 53
1041 20:14:48.930939
1042 20:14:48.931019 Set Vref, RX VrefLevel [Byte0]: 54
1043 20:14:48.935410 [Byte1]: 54
1044 20:14:48.938562
1045 20:14:48.938642 Set Vref, RX VrefLevel [Byte0]: 55
1046 20:14:48.941971 [Byte1]: 55
1047 20:14:48.946075
1048 20:14:48.946155 Set Vref, RX VrefLevel [Byte0]: 56
1049 20:14:48.949380 [Byte1]: 56
1050 20:14:48.954173
1051 20:14:48.954253 Set Vref, RX VrefLevel [Byte0]: 57
1052 20:14:48.957179 [Byte1]: 57
1053 20:14:48.961672
1054 20:14:48.961752 Set Vref, RX VrefLevel [Byte0]: 58
1055 20:14:48.964843 [Byte1]: 58
1056 20:14:48.969265
1057 20:14:48.969345 Set Vref, RX VrefLevel [Byte0]: 59
1058 20:14:48.972230 [Byte1]: 59
1059 20:14:48.976419
1060 20:14:48.976499 Set Vref, RX VrefLevel [Byte0]: 60
1061 20:14:48.980615 [Byte1]: 60
1062 20:14:48.984005
1063 20:14:48.984084 Set Vref, RX VrefLevel [Byte0]: 61
1064 20:14:48.987864 [Byte1]: 61
1065 20:14:48.991817
1066 20:14:48.991897 Set Vref, RX VrefLevel [Byte0]: 62
1067 20:14:48.995056 [Byte1]: 62
1068 20:14:49.000063
1069 20:14:49.000142 Set Vref, RX VrefLevel [Byte0]: 63
1070 20:14:49.002576 [Byte1]: 63
1071 20:14:49.007192
1072 20:14:49.007273 Set Vref, RX VrefLevel [Byte0]: 64
1073 20:14:49.011390 [Byte1]: 64
1074 20:14:49.015383
1075 20:14:49.015464 Set Vref, RX VrefLevel [Byte0]: 65
1076 20:14:49.017912 [Byte1]: 65
1077 20:14:49.022594
1078 20:14:49.022674 Set Vref, RX VrefLevel [Byte0]: 66
1079 20:14:49.025410 [Byte1]: 66
1080 20:14:49.030149
1081 20:14:49.030229 Set Vref, RX VrefLevel [Byte0]: 67
1082 20:14:49.033038 [Byte1]: 67
1083 20:14:49.037810
1084 20:14:49.037889 Set Vref, RX VrefLevel [Byte0]: 68
1085 20:14:49.040770 [Byte1]: 68
1086 20:14:49.045067
1087 20:14:49.045147 Set Vref, RX VrefLevel [Byte0]: 69
1088 20:14:49.048575 [Byte1]: 69
1089 20:14:49.052950
1090 20:14:49.053030 Set Vref, RX VrefLevel [Byte0]: 70
1091 20:14:49.056024 [Byte1]: 70
1092 20:14:49.060072
1093 20:14:49.060152 Set Vref, RX VrefLevel [Byte0]: 71
1094 20:14:49.063270 [Byte1]: 71
1095 20:14:49.067896
1096 20:14:49.067976 Set Vref, RX VrefLevel [Byte0]: 72
1097 20:14:49.071554 [Byte1]: 72
1098 20:14:49.075580
1099 20:14:49.075660 Set Vref, RX VrefLevel [Byte0]: 73
1100 20:14:49.079070 [Byte1]: 73
1101 20:14:49.083165
1102 20:14:49.083245 Set Vref, RX VrefLevel [Byte0]: 74
1103 20:14:49.086598 [Byte1]: 74
1104 20:14:49.090684
1105 20:14:49.090764 Set Vref, RX VrefLevel [Byte0]: 75
1106 20:14:49.093935 [Byte1]: 75
1107 20:14:49.098196
1108 20:14:49.098276 Set Vref, RX VrefLevel [Byte0]: 76
1109 20:14:49.101557 [Byte1]: 76
1110 20:14:49.106036
1111 20:14:49.106116 Set Vref, RX VrefLevel [Byte0]: 77
1112 20:14:49.109119 [Byte1]: 77
1113 20:14:49.113133
1114 20:14:49.113213 Final RX Vref Byte 0 = 62 to rank0
1115 20:14:49.116581 Final RX Vref Byte 1 = 58 to rank0
1116 20:14:49.120130 Final RX Vref Byte 0 = 62 to rank1
1117 20:14:49.123933 Final RX Vref Byte 1 = 58 to rank1==
1118 20:14:49.126947 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 20:14:49.130867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 20:14:49.133323 ==
1121 20:14:49.133403 DQS Delay:
1122 20:14:49.133477 DQS0 = 0, DQS1 = 0
1123 20:14:49.136809 DQM Delay:
1124 20:14:49.136889 DQM0 = 87, DQM1 = 78
1125 20:14:49.140145 DQ Delay:
1126 20:14:49.140226 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1127 20:14:49.144119 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1128 20:14:49.147285 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =76
1129 20:14:49.150119 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1130 20:14:49.150199
1131 20:14:49.154059
1132 20:14:49.160991 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1133 20:14:49.163458 CH0 RK0: MR19=606, MR18=270E
1134 20:14:49.170267 CH0_RK0: MR19=0x606, MR18=0x270E, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 20:14:49.170348
1136 20:14:49.173772 ----->DramcWriteLeveling(PI) begin...
1137 20:14:49.173854 ==
1138 20:14:49.177181 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 20:14:49.181159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 20:14:49.181266 ==
1141 20:14:49.183851 Write leveling (Byte 0): 32 => 32
1142 20:14:49.187058 Write leveling (Byte 1): 31 => 31
1143 20:14:49.190435 DramcWriteLeveling(PI) end<-----
1144 20:14:49.190530
1145 20:14:49.190594 ==
1146 20:14:49.193707 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 20:14:49.197345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 20:14:49.197426 ==
1149 20:14:49.200466 [Gating] SW mode calibration
1150 20:14:49.207319 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 20:14:49.213770 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 20:14:49.258811 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 20:14:49.259431 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 20:14:49.259554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 20:14:49.259858 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 20:14:49.259975 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 20:14:49.260103 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 20:14:49.261193 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 20:14:49.261313 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 20:14:49.261632 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 20:14:49.261959 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 20:14:49.302074 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 20:14:49.302202 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 20:14:49.302516 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 20:14:49.302883 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 20:14:49.303219 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 20:14:49.303355 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 20:14:49.303470 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 20:14:49.303638 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1170 20:14:49.303783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1171 20:14:49.303903 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 20:14:49.321165 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 20:14:49.321289 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 20:14:49.321602 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 20:14:49.321716 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 20:14:49.324939 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 20:14:49.328323 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 20:14:49.331474 0 9 8 | B1->B0 | 2322 3232 | 1 0 | (0 0) (0 0)
1179 20:14:49.334594 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1180 20:14:49.338404 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 20:14:49.344821 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 20:14:49.348679 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 20:14:49.351552 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 20:14:49.358434 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 20:14:49.361884 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1186 20:14:49.364863 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
1187 20:14:49.371985 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1188 20:14:49.375095 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 20:14:49.378929 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 20:14:49.385418 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 20:14:49.388811 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 20:14:49.393019 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 20:14:49.396197 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1194 20:14:49.399878 0 11 8 | B1->B0 | 2e2e 4444 | 0 1 | (0 0) (0 0)
1195 20:14:49.406918 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1196 20:14:49.410923 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 20:14:49.413683 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 20:14:49.418169 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 20:14:49.424162 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 20:14:49.427375 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 20:14:49.431072 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 20:14:49.437761 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 20:14:49.441121 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 20:14:49.444456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 20:14:49.450880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 20:14:49.454129 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 20:14:49.457462 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 20:14:49.464202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 20:14:49.467471 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 20:14:49.470703 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 20:14:49.477897 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 20:14:49.481337 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 20:14:49.484481 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 20:14:49.487549 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 20:14:49.494549 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 20:14:49.498130 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 20:14:49.500890 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 20:14:49.507871 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 20:14:49.507952 Total UI for P1: 0, mck2ui 16
1220 20:14:49.514895 best dqsien dly found for B0: ( 0, 14, 6)
1221 20:14:49.518176 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 20:14:49.521460 Total UI for P1: 0, mck2ui 16
1223 20:14:49.524895 best dqsien dly found for B1: ( 0, 14, 8)
1224 20:14:49.528017 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 20:14:49.531103 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 20:14:49.531184
1227 20:14:49.535048 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 20:14:49.538265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 20:14:49.541710 [Gating] SW calibration Done
1230 20:14:49.541791 ==
1231 20:14:49.544727 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 20:14:49.548231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 20:14:49.548312 ==
1234 20:14:49.551266 RX Vref Scan: 0
1235 20:14:49.551349
1236 20:14:49.551414 RX Vref 0 -> 0, step: 1
1237 20:14:49.555698
1238 20:14:49.555778 RX Delay -130 -> 252, step: 16
1239 20:14:49.561426 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1240 20:14:49.564781 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 20:14:49.568068 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1242 20:14:49.571353 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1243 20:14:49.575124 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1244 20:14:49.581504 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1245 20:14:49.585139 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1246 20:14:49.588291 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1247 20:14:49.591681 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1248 20:14:49.594888 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1249 20:14:49.598342 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 20:14:49.605385 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1251 20:14:49.608232 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1252 20:14:49.611780 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1253 20:14:49.615002 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1254 20:14:49.618228 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1255 20:14:49.621864 ==
1256 20:14:49.625248 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 20:14:49.628570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 20:14:49.628651 ==
1259 20:14:49.628715 DQS Delay:
1260 20:14:49.631811 DQS0 = 0, DQS1 = 0
1261 20:14:49.631920 DQM Delay:
1262 20:14:49.634917 DQM0 = 85, DQM1 = 76
1263 20:14:49.634998 DQ Delay:
1264 20:14:49.638345 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1265 20:14:49.642169 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1266 20:14:49.645251 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1267 20:14:49.648615 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1268 20:14:49.648696
1269 20:14:49.648760
1270 20:14:49.648820 ==
1271 20:14:49.652372 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 20:14:49.655743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 20:14:49.655824 ==
1274 20:14:49.655888
1275 20:14:49.655948
1276 20:14:49.658924 TX Vref Scan disable
1277 20:14:49.662460 == TX Byte 0 ==
1278 20:14:49.665311 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 20:14:49.668718 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 20:14:49.668800 == TX Byte 1 ==
1281 20:14:49.675268 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1282 20:14:49.679142 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1283 20:14:49.679225 ==
1284 20:14:49.682279 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 20:14:49.685897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 20:14:49.686023 ==
1287 20:14:49.700168 TX Vref=22, minBit 3, minWin=27, winSum=445
1288 20:14:49.703372 TX Vref=24, minBit 9, minWin=27, winSum=447
1289 20:14:49.706631 TX Vref=26, minBit 9, minWin=27, winSum=449
1290 20:14:49.709610 TX Vref=28, minBit 12, minWin=27, winSum=452
1291 20:14:49.713299 TX Vref=30, minBit 2, minWin=28, winSum=454
1292 20:14:49.716351 TX Vref=32, minBit 2, minWin=28, winSum=454
1293 20:14:49.723498 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
1294 20:14:49.723579
1295 20:14:49.726728 Final TX Range 1 Vref 30
1296 20:14:49.726808
1297 20:14:49.726870 ==
1298 20:14:49.729851 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 20:14:49.733382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 20:14:49.733462 ==
1301 20:14:49.733525
1302 20:14:49.733583
1303 20:14:49.736600 TX Vref Scan disable
1304 20:14:49.739722 == TX Byte 0 ==
1305 20:14:49.743515 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1306 20:14:49.746431 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1307 20:14:49.750132 == TX Byte 1 ==
1308 20:14:49.752939 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1309 20:14:49.756744 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1310 20:14:49.759978
1311 20:14:49.760056 [DATLAT]
1312 20:14:49.760119 Freq=800, CH0 RK1
1313 20:14:49.760178
1314 20:14:49.763101 DATLAT Default: 0xa
1315 20:14:49.763180 0, 0xFFFF, sum = 0
1316 20:14:49.766162 1, 0xFFFF, sum = 0
1317 20:14:49.766242 2, 0xFFFF, sum = 0
1318 20:14:49.769586 3, 0xFFFF, sum = 0
1319 20:14:49.769666 4, 0xFFFF, sum = 0
1320 20:14:49.772873 5, 0xFFFF, sum = 0
1321 20:14:49.772961 6, 0xFFFF, sum = 0
1322 20:14:49.776371 7, 0xFFFF, sum = 0
1323 20:14:49.776451 8, 0xFFFF, sum = 0
1324 20:14:49.779876 9, 0x0, sum = 1
1325 20:14:49.779956 10, 0x0, sum = 2
1326 20:14:49.782861 11, 0x0, sum = 3
1327 20:14:49.782941 12, 0x0, sum = 4
1328 20:14:49.786269 best_step = 10
1329 20:14:49.786373
1330 20:14:49.786485 ==
1331 20:14:49.789687 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 20:14:49.793096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 20:14:49.793176 ==
1334 20:14:49.796384 RX Vref Scan: 0
1335 20:14:49.796463
1336 20:14:49.796526 RX Vref 0 -> 0, step: 1
1337 20:14:49.796586
1338 20:14:49.800366 RX Delay -95 -> 252, step: 8
1339 20:14:49.806695 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 20:14:49.809908 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1341 20:14:49.813637 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1342 20:14:49.817424 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1343 20:14:49.820173 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1344 20:14:49.826637 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1345 20:14:49.829896 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1346 20:14:49.833694 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1347 20:14:49.837007 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1348 20:14:49.839989 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1349 20:14:49.843264 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1350 20:14:49.850109 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1351 20:14:49.853458 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1352 20:14:49.857388 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1353 20:14:49.860228 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1354 20:14:49.863804 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 20:14:49.866895 ==
1356 20:14:49.870102 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 20:14:49.873467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 20:14:49.873550 ==
1359 20:14:49.873633 DQS Delay:
1360 20:14:49.876651 DQS0 = 0, DQS1 = 0
1361 20:14:49.876733 DQM Delay:
1362 20:14:49.880358 DQM0 = 87, DQM1 = 78
1363 20:14:49.880440 DQ Delay:
1364 20:14:49.883955 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1365 20:14:49.887194 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1366 20:14:49.891329 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1367 20:14:49.893656 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1368 20:14:49.893738
1369 20:14:49.893837
1370 20:14:49.900592 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1371 20:14:49.904433 CH0 RK1: MR19=606, MR18=2E17
1372 20:14:49.910521 CH0_RK1: MR19=0x606, MR18=0x2E17, DQSOSC=398, MR23=63, INC=93, DEC=62
1373 20:14:49.913908 [RxdqsGatingPostProcess] freq 800
1374 20:14:49.917639 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 20:14:49.920291 Pre-setting of DQS Precalculation
1376 20:14:49.927714 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 20:14:49.927796 ==
1378 20:14:49.930499 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 20:14:49.934315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 20:14:49.934428 ==
1381 20:14:49.940962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 20:14:49.944179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 20:14:49.954535 [CA 0] Center 36 (6~66) winsize 61
1384 20:14:49.957661 [CA 1] Center 36 (6~66) winsize 61
1385 20:14:49.961636 [CA 2] Center 34 (5~64) winsize 60
1386 20:14:49.964917 [CA 3] Center 33 (3~64) winsize 62
1387 20:14:49.968315 [CA 4] Center 34 (4~65) winsize 62
1388 20:14:49.971312 [CA 5] Center 33 (3~64) winsize 62
1389 20:14:49.971394
1390 20:14:49.974983 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 20:14:49.975065
1392 20:14:49.978137 [CATrainingPosCal] consider 1 rank data
1393 20:14:49.981124 u2DelayCellTimex100 = 270/100 ps
1394 20:14:49.984736 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1395 20:14:49.988223 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 20:14:49.994514 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1397 20:14:49.997865 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 20:14:50.001246 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 20:14:50.004808 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 20:14:50.004888
1401 20:14:50.008213 CA PerBit enable=1, Macro0, CA PI delay=33
1402 20:14:50.008294
1403 20:14:50.011149 [CBTSetCACLKResult] CA Dly = 33
1404 20:14:50.011230 CS Dly: 5 (0~36)
1405 20:14:50.011294 ==
1406 20:14:50.014917 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 20:14:50.021117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 20:14:50.021223 ==
1409 20:14:50.024940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 20:14:50.031616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 20:14:50.040933 [CA 0] Center 36 (6~67) winsize 62
1412 20:14:50.044140 [CA 1] Center 36 (6~66) winsize 61
1413 20:14:50.047888 [CA 2] Center 34 (4~65) winsize 62
1414 20:14:50.051482 [CA 3] Center 33 (3~64) winsize 62
1415 20:14:50.054782 [CA 4] Center 34 (3~65) winsize 63
1416 20:14:50.058337 [CA 5] Center 33 (3~64) winsize 62
1417 20:14:50.058442
1418 20:14:50.062130 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 20:14:50.062210
1420 20:14:50.064935 [CATrainingPosCal] consider 2 rank data
1421 20:14:50.068626 u2DelayCellTimex100 = 270/100 ps
1422 20:14:50.072544 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1423 20:14:50.077197 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 20:14:50.079873 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1425 20:14:50.083984 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 20:14:50.087634 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1427 20:14:50.091234 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 20:14:50.091314
1429 20:14:50.094515 CA PerBit enable=1, Macro0, CA PI delay=33
1430 20:14:50.094595
1431 20:14:50.097925 [CBTSetCACLKResult] CA Dly = 33
1432 20:14:50.098005 CS Dly: 5 (0~37)
1433 20:14:50.098069
1434 20:14:50.100984 ----->DramcWriteLeveling(PI) begin...
1435 20:14:50.101090 ==
1436 20:14:50.104340 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 20:14:50.111295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 20:14:50.111402 ==
1439 20:14:50.114558 Write leveling (Byte 0): 27 => 27
1440 20:14:50.114639 Write leveling (Byte 1): 30 => 30
1441 20:14:50.117608 DramcWriteLeveling(PI) end<-----
1442 20:14:50.117688
1443 20:14:50.121161 ==
1444 20:14:50.121240 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 20:14:50.127792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 20:14:50.127872 ==
1447 20:14:50.131075 [Gating] SW mode calibration
1448 20:14:50.138558 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 20:14:50.141057 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 20:14:50.147818 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 20:14:50.150886 0 6 4 | B1->B0 | 2423 2323 | 1 0 | (1 1) (1 1)
1452 20:14:50.154319 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 20:14:50.160984 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 20:14:50.164390 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 20:14:50.168032 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 20:14:50.171263 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 20:14:50.178041 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 20:14:50.181046 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1459 20:14:50.184402 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 20:14:50.191025 0 7 8 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1461 20:14:50.195039 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 20:14:50.198591 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1463 20:14:50.204739 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 20:14:50.208084 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 20:14:50.211268 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 20:14:50.218633 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 20:14:50.221715 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1468 20:14:50.224803 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 20:14:50.231333 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 20:14:50.235221 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 20:14:50.238686 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 20:14:50.241343 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 20:14:50.248087 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 20:14:50.252014 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 20:14:50.255254 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 20:14:50.261715 0 9 8 | B1->B0 | 2323 2424 | 1 0 | (1 1) (0 0)
1477 20:14:50.264563 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 20:14:50.268678 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 20:14:50.274838 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 20:14:50.278184 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1481 20:14:50.281853 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 20:14:50.288278 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 20:14:50.292278 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1484 20:14:50.294846 0 10 8 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (0 0)
1485 20:14:50.298802 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 20:14:50.305343 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 20:14:50.308732 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 20:14:50.311987 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 20:14:50.318367 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 20:14:50.321839 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 20:14:50.325086 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 20:14:50.332121 0 11 8 | B1->B0 | 3333 3232 | 0 1 | (1 1) (0 0)
1493 20:14:50.335492 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1494 20:14:50.338449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 20:14:50.345840 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 20:14:50.349072 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 20:14:50.352225 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 20:14:50.358386 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 20:14:50.361923 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 20:14:50.366340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 20:14:50.372323 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 20:14:50.376144 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 20:14:50.378662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 20:14:50.382152 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 20:14:50.388893 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 20:14:50.392410 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 20:14:50.395478 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 20:14:50.402277 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 20:14:50.405643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 20:14:50.409112 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 20:14:50.415801 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 20:14:50.418879 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 20:14:50.422685 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 20:14:50.429163 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 20:14:50.432292 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1516 20:14:50.436521 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 20:14:50.439451 Total UI for P1: 0, mck2ui 16
1518 20:14:50.442646 best dqsien dly found for B0: ( 0, 14, 6)
1519 20:14:50.446160 Total UI for P1: 0, mck2ui 16
1520 20:14:50.449426 best dqsien dly found for B1: ( 0, 14, 4)
1521 20:14:50.452763 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 20:14:50.456001 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 20:14:50.456081
1524 20:14:50.459422 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 20:14:50.462754 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 20:14:50.466328 [Gating] SW calibration Done
1527 20:14:50.466436 ==
1528 20:14:50.469561 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 20:14:50.472538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 20:14:50.476078 ==
1531 20:14:50.476158 RX Vref Scan: 0
1532 20:14:50.476222
1533 20:14:50.479925 RX Vref 0 -> 0, step: 1
1534 20:14:50.480006
1535 20:14:50.483314 RX Delay -130 -> 252, step: 16
1536 20:14:50.486090 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1537 20:14:50.489245 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1538 20:14:50.493347 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1539 20:14:50.496405 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1540 20:14:50.499481 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1541 20:14:50.506255 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1542 20:14:50.509485 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1543 20:14:50.512932 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1544 20:14:50.516383 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1545 20:14:50.519814 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1546 20:14:50.526043 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1547 20:14:50.529227 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1548 20:14:50.533298 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1549 20:14:50.537245 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1550 20:14:50.540535 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1551 20:14:50.546150 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1552 20:14:50.546231 ==
1553 20:14:50.550420 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 20:14:50.553239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 20:14:50.553320 ==
1556 20:14:50.553384 DQS Delay:
1557 20:14:50.556284 DQS0 = 0, DQS1 = 0
1558 20:14:50.556364 DQM Delay:
1559 20:14:50.559643 DQM0 = 82, DQM1 = 74
1560 20:14:50.559723 DQ Delay:
1561 20:14:50.563177 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1562 20:14:50.566199 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1563 20:14:50.569513 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1564 20:14:50.573412 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1565 20:14:50.573493
1566 20:14:50.573556
1567 20:14:50.573615 ==
1568 20:14:50.576610 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 20:14:50.579394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 20:14:50.579502 ==
1571 20:14:50.579594
1572 20:14:50.582763
1573 20:14:50.582844 TX Vref Scan disable
1574 20:14:50.586840 == TX Byte 0 ==
1575 20:14:50.590022 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1576 20:14:50.593269 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1577 20:14:50.596384 == TX Byte 1 ==
1578 20:14:50.599846 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1579 20:14:50.603065 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1580 20:14:50.603185 ==
1581 20:14:50.606660 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 20:14:50.613084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 20:14:50.613166 ==
1584 20:14:50.625009 TX Vref=22, minBit 11, minWin=26, winSum=439
1585 20:14:50.628507 TX Vref=24, minBit 0, minWin=27, winSum=444
1586 20:14:50.631539 TX Vref=26, minBit 8, minWin=27, winSum=448
1587 20:14:50.635482 TX Vref=28, minBit 1, minWin=28, winSum=454
1588 20:14:50.638641 TX Vref=30, minBit 1, minWin=28, winSum=456
1589 20:14:50.642595 TX Vref=32, minBit 0, minWin=28, winSum=457
1590 20:14:50.649684 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 32
1591 20:14:50.649766
1592 20:14:50.652608 Final TX Range 1 Vref 32
1593 20:14:50.652689
1594 20:14:50.652752 ==
1595 20:14:50.656052 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 20:14:50.659793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 20:14:50.659874 ==
1598 20:14:50.659938
1599 20:14:50.659997
1600 20:14:50.662959 TX Vref Scan disable
1601 20:14:50.666030 == TX Byte 0 ==
1602 20:14:50.669182 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 20:14:50.673431 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 20:14:50.676301 == TX Byte 1 ==
1605 20:14:50.679238 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 20:14:50.682377 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 20:14:50.682502
1608 20:14:50.682596 [DATLAT]
1609 20:14:50.686703 Freq=800, CH1 RK0
1610 20:14:50.686784
1611 20:14:50.689806 DATLAT Default: 0xa
1612 20:14:50.689887 0, 0xFFFF, sum = 0
1613 20:14:50.693059 1, 0xFFFF, sum = 0
1614 20:14:50.693166 2, 0xFFFF, sum = 0
1615 20:14:50.696479 3, 0xFFFF, sum = 0
1616 20:14:50.696561 4, 0xFFFF, sum = 0
1617 20:14:50.699890 5, 0xFFFF, sum = 0
1618 20:14:50.699972 6, 0xFFFF, sum = 0
1619 20:14:50.702828 7, 0xFFFF, sum = 0
1620 20:14:50.702909 8, 0xFFFF, sum = 0
1621 20:14:50.706752 9, 0x0, sum = 1
1622 20:14:50.706834 10, 0x0, sum = 2
1623 20:14:50.709706 11, 0x0, sum = 3
1624 20:14:50.709787 12, 0x0, sum = 4
1625 20:14:50.709852 best_step = 10
1626 20:14:50.709913
1627 20:14:50.713057 ==
1628 20:14:50.713138 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 20:14:50.719977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 20:14:50.720058 ==
1631 20:14:50.720122 RX Vref Scan: 1
1632 20:14:50.720182
1633 20:14:50.722857 Set Vref Range= 32 -> 127
1634 20:14:50.722937
1635 20:14:50.726386 RX Vref 32 -> 127, step: 1
1636 20:14:50.726535
1637 20:14:50.730276 RX Delay -111 -> 252, step: 8
1638 20:14:50.730356
1639 20:14:50.733040 Set Vref, RX VrefLevel [Byte0]: 32
1640 20:14:50.736651 [Byte1]: 32
1641 20:14:50.736773
1642 20:14:50.739781 Set Vref, RX VrefLevel [Byte0]: 33
1643 20:14:50.743364 [Byte1]: 33
1644 20:14:50.743444
1645 20:14:50.746968 Set Vref, RX VrefLevel [Byte0]: 34
1646 20:14:50.750023 [Byte1]: 34
1647 20:14:50.753476
1648 20:14:50.753556 Set Vref, RX VrefLevel [Byte0]: 35
1649 20:14:50.756318 [Byte1]: 35
1650 20:14:50.760992
1651 20:14:50.761114 Set Vref, RX VrefLevel [Byte0]: 36
1652 20:14:50.764606 [Byte1]: 36
1653 20:14:50.768940
1654 20:14:50.769058 Set Vref, RX VrefLevel [Byte0]: 37
1655 20:14:50.772083 [Byte1]: 37
1656 20:14:50.775693
1657 20:14:50.775814 Set Vref, RX VrefLevel [Byte0]: 38
1658 20:14:50.779231 [Byte1]: 38
1659 20:14:50.783694
1660 20:14:50.783773 Set Vref, RX VrefLevel [Byte0]: 39
1661 20:14:50.786914 [Byte1]: 39
1662 20:14:50.791141
1663 20:14:50.791227 Set Vref, RX VrefLevel [Byte0]: 40
1664 20:14:50.794533 [Byte1]: 40
1665 20:14:50.798788
1666 20:14:50.798868 Set Vref, RX VrefLevel [Byte0]: 41
1667 20:14:50.802094 [Byte1]: 41
1668 20:14:50.806700
1669 20:14:50.806779 Set Vref, RX VrefLevel [Byte0]: 42
1670 20:14:50.809762 [Byte1]: 42
1671 20:14:50.814513
1672 20:14:50.814593 Set Vref, RX VrefLevel [Byte0]: 43
1673 20:14:50.817528 [Byte1]: 43
1674 20:14:50.822325
1675 20:14:50.822441 Set Vref, RX VrefLevel [Byte0]: 44
1676 20:14:50.825146 [Byte1]: 44
1677 20:14:50.829632
1678 20:14:50.829714 Set Vref, RX VrefLevel [Byte0]: 45
1679 20:14:50.832665 [Byte1]: 45
1680 20:14:50.837152
1681 20:14:50.837232 Set Vref, RX VrefLevel [Byte0]: 46
1682 20:14:50.840606 [Byte1]: 46
1683 20:14:50.844801
1684 20:14:50.844880 Set Vref, RX VrefLevel [Byte0]: 47
1685 20:14:50.848006 [Byte1]: 47
1686 20:14:50.853301
1687 20:14:50.853380 Set Vref, RX VrefLevel [Byte0]: 48
1688 20:14:50.855585 [Byte1]: 48
1689 20:14:50.860005
1690 20:14:50.860085 Set Vref, RX VrefLevel [Byte0]: 49
1691 20:14:50.863526 [Byte1]: 49
1692 20:14:50.868435
1693 20:14:50.868515 Set Vref, RX VrefLevel [Byte0]: 50
1694 20:14:50.871509 [Byte1]: 50
1695 20:14:50.875632
1696 20:14:50.875711 Set Vref, RX VrefLevel [Byte0]: 51
1697 20:14:50.879101 [Byte1]: 51
1698 20:14:50.883006
1699 20:14:50.883086 Set Vref, RX VrefLevel [Byte0]: 52
1700 20:14:50.886599 [Byte1]: 52
1701 20:14:50.890656
1702 20:14:50.890736 Set Vref, RX VrefLevel [Byte0]: 53
1703 20:14:50.894101 [Byte1]: 53
1704 20:14:50.898293
1705 20:14:50.898421 Set Vref, RX VrefLevel [Byte0]: 54
1706 20:14:50.901866 [Byte1]: 54
1707 20:14:50.905952
1708 20:14:50.906033 Set Vref, RX VrefLevel [Byte0]: 55
1709 20:14:50.909038 [Byte1]: 55
1710 20:14:50.914047
1711 20:14:50.914127 Set Vref, RX VrefLevel [Byte0]: 56
1712 20:14:50.916851 [Byte1]: 56
1713 20:14:50.921322
1714 20:14:50.921406 Set Vref, RX VrefLevel [Byte0]: 57
1715 20:14:50.924963 [Byte1]: 57
1716 20:14:50.929407
1717 20:14:50.929487 Set Vref, RX VrefLevel [Byte0]: 58
1718 20:14:50.931999 [Byte1]: 58
1719 20:14:50.936318
1720 20:14:50.936398 Set Vref, RX VrefLevel [Byte0]: 59
1721 20:14:50.939851 [Byte1]: 59
1722 20:14:50.944610
1723 20:14:50.944690 Set Vref, RX VrefLevel [Byte0]: 60
1724 20:14:50.947554 [Byte1]: 60
1725 20:14:50.952056
1726 20:14:50.952183 Set Vref, RX VrefLevel [Byte0]: 61
1727 20:14:50.955360 [Byte1]: 61
1728 20:14:50.959893
1729 20:14:50.959973 Set Vref, RX VrefLevel [Byte0]: 62
1730 20:14:50.963609 [Byte1]: 62
1731 20:14:50.967352
1732 20:14:50.967432 Set Vref, RX VrefLevel [Byte0]: 63
1733 20:14:50.970344 [Byte1]: 63
1734 20:14:50.975199
1735 20:14:50.975280 Set Vref, RX VrefLevel [Byte0]: 64
1736 20:14:50.980973 [Byte1]: 64
1737 20:14:50.981054
1738 20:14:50.984330 Set Vref, RX VrefLevel [Byte0]: 65
1739 20:14:50.988263 [Byte1]: 65
1740 20:14:50.988343
1741 20:14:50.991644 Set Vref, RX VrefLevel [Byte0]: 66
1742 20:14:50.994794 [Byte1]: 66
1743 20:14:50.994874
1744 20:14:50.998287 Set Vref, RX VrefLevel [Byte0]: 67
1745 20:14:51.001583 [Byte1]: 67
1746 20:14:51.005358
1747 20:14:51.005438 Set Vref, RX VrefLevel [Byte0]: 68
1748 20:14:51.008400 [Byte1]: 68
1749 20:14:51.012752
1750 20:14:51.012832 Set Vref, RX VrefLevel [Byte0]: 69
1751 20:14:51.016145 [Byte1]: 69
1752 20:14:51.020892
1753 20:14:51.020972 Set Vref, RX VrefLevel [Byte0]: 70
1754 20:14:51.024126 [Byte1]: 70
1755 20:14:51.028224
1756 20:14:51.028303 Set Vref, RX VrefLevel [Byte0]: 71
1757 20:14:51.031947 [Byte1]: 71
1758 20:14:51.035751
1759 20:14:51.035831 Set Vref, RX VrefLevel [Byte0]: 72
1760 20:14:51.039318 [Byte1]: 72
1761 20:14:51.044124
1762 20:14:51.044205 Set Vref, RX VrefLevel [Byte0]: 73
1763 20:14:51.046760 [Byte1]: 73
1764 20:14:51.051341
1765 20:14:51.051421 Set Vref, RX VrefLevel [Byte0]: 74
1766 20:14:51.054335 [Byte1]: 74
1767 20:14:51.059025
1768 20:14:51.059131 Set Vref, RX VrefLevel [Byte0]: 75
1769 20:14:51.062174 [Byte1]: 75
1770 20:14:51.066910
1771 20:14:51.066990 Set Vref, RX VrefLevel [Byte0]: 76
1772 20:14:51.069818 [Byte1]: 76
1773 20:14:51.075327
1774 20:14:51.075435 Set Vref, RX VrefLevel [Byte0]: 77
1775 20:14:51.077236 [Byte1]: 77
1776 20:14:51.082017
1777 20:14:51.082097 Final RX Vref Byte 0 = 58 to rank0
1778 20:14:51.084914 Final RX Vref Byte 1 = 58 to rank0
1779 20:14:51.089233 Final RX Vref Byte 0 = 58 to rank1
1780 20:14:51.092143 Final RX Vref Byte 1 = 58 to rank1==
1781 20:14:51.095278 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 20:14:51.098535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 20:14:51.101938 ==
1784 20:14:51.102020 DQS Delay:
1785 20:14:51.102084 DQS0 = 0, DQS1 = 0
1786 20:14:51.105213 DQM Delay:
1787 20:14:51.105318 DQM0 = 83, DQM1 = 74
1788 20:14:51.108332 DQ Delay:
1789 20:14:51.108409 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1790 20:14:51.112070 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =76
1791 20:14:51.115235 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =72
1792 20:14:51.118821 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1793 20:14:51.118901
1794 20:14:51.121929
1795 20:14:51.128778 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1796 20:14:51.132109 CH1 RK0: MR19=605, MR18=27FB
1797 20:14:51.138726 CH1_RK0: MR19=0x605, MR18=0x27FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1798 20:14:51.138808
1799 20:14:51.141957 ----->DramcWriteLeveling(PI) begin...
1800 20:14:51.142039 ==
1801 20:14:51.145770 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 20:14:51.148960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 20:14:51.149041 ==
1804 20:14:51.152177 Write leveling (Byte 0): 27 => 27
1805 20:14:51.155713 Write leveling (Byte 1): 31 => 31
1806 20:14:51.158854 DramcWriteLeveling(PI) end<-----
1807 20:14:51.158934
1808 20:14:51.158999 ==
1809 20:14:51.162153 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 20:14:51.165762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 20:14:51.165843 ==
1812 20:14:51.169195 [Gating] SW mode calibration
1813 20:14:51.176147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 20:14:51.184006 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 20:14:51.185914 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 20:14:51.188969 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 20:14:51.192573 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1818 20:14:51.199423 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 20:14:51.202808 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 20:14:51.206231 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 20:14:51.212500 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 20:14:51.216380 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 20:14:51.219168 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1824 20:14:51.226020 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 20:14:51.229527 0 7 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1826 20:14:51.233190 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 20:14:51.239498 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1828 20:14:51.242669 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 20:14:51.245898 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1830 20:14:51.249706 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 20:14:51.256586 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1832 20:14:51.259404 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 20:14:51.262781 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1834 20:14:51.270029 0 8 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1835 20:14:51.273034 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1836 20:14:51.276930 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 20:14:51.282827 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 20:14:51.286455 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 20:14:51.289852 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 20:14:51.296374 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1841 20:14:51.299743 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1842 20:14:51.303144 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1843 20:14:51.309561 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1844 20:14:51.312934 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 20:14:51.316918 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 20:14:51.319991 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 20:14:51.326675 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1848 20:14:51.330116 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (1 1)
1849 20:14:51.333112 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1850 20:14:51.340088 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 20:14:51.343220 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 20:14:51.347226 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 20:14:51.353327 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 20:14:51.356579 0 10 28 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1855 20:14:51.360102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 20:14:51.366929 0 11 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (1 1)
1857 20:14:51.370074 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1858 20:14:51.373601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 20:14:51.380849 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 20:14:51.383500 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 20:14:51.386786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 20:14:51.390273 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 20:14:51.397045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 20:14:51.401035 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1865 20:14:51.403596 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1866 20:14:51.410358 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 20:14:51.414173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 20:14:51.417554 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 20:14:51.424131 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 20:14:51.427894 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 20:14:51.430563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 20:14:51.437162 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 20:14:51.441140 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 20:14:51.444431 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 20:14:51.447564 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 20:14:51.454098 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 20:14:51.458373 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 20:14:51.460577 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 20:14:51.467522 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 20:14:51.471077 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1881 20:14:51.474155 Total UI for P1: 0, mck2ui 16
1882 20:14:51.478052 best dqsien dly found for B0: ( 0, 14, 2)
1883 20:14:51.480681 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 20:14:51.484073 Total UI for P1: 0, mck2ui 16
1885 20:14:51.487383 best dqsien dly found for B1: ( 0, 14, 4)
1886 20:14:51.491643 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1887 20:14:51.494253 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1888 20:14:51.494333
1889 20:14:51.497618 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1890 20:14:51.504270 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 20:14:51.504381 [Gating] SW calibration Done
1892 20:14:51.504452 ==
1893 20:14:51.507458 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 20:14:51.514705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 20:14:51.514786 ==
1896 20:14:51.514850 RX Vref Scan: 0
1897 20:14:51.514910
1898 20:14:51.518016 RX Vref 0 -> 0, step: 1
1899 20:14:51.518096
1900 20:14:51.520757 RX Delay -130 -> 252, step: 16
1901 20:14:51.524406 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1902 20:14:51.527629 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1903 20:14:51.531754 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1904 20:14:51.534576 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1905 20:14:51.541110 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1906 20:14:51.544609 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1907 20:14:51.548013 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1908 20:14:51.551274 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1909 20:14:51.554879 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1910 20:14:51.561623 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1911 20:14:51.564633 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1912 20:14:51.568685 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1913 20:14:51.571436 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1914 20:14:51.575130 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1915 20:14:51.581437 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1916 20:14:51.584572 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1917 20:14:51.584678 ==
1918 20:14:51.588070 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 20:14:51.592054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 20:14:51.592176 ==
1921 20:14:51.594615 DQS Delay:
1922 20:14:51.594712 DQS0 = 0, DQS1 = 0
1923 20:14:51.594800 DQM Delay:
1924 20:14:51.597904 DQM0 = 78, DQM1 = 77
1925 20:14:51.597984 DQ Delay:
1926 20:14:51.601823 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1927 20:14:51.604826 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1928 20:14:51.608444 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1929 20:14:51.611153 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1930 20:14:51.611258
1931 20:14:51.611349
1932 20:14:51.611445 ==
1933 20:14:51.614635 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 20:14:51.618113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 20:14:51.621506 ==
1936 20:14:51.621580
1937 20:14:51.621642
1938 20:14:51.621717 TX Vref Scan disable
1939 20:14:51.625117 == TX Byte 0 ==
1940 20:14:51.628191 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 20:14:51.631423 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 20:14:51.635744 == TX Byte 1 ==
1943 20:14:51.638532 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1944 20:14:51.641438 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1945 20:14:51.645198 ==
1946 20:14:51.645279 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 20:14:51.652809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 20:14:51.652891 ==
1949 20:14:51.663696 TX Vref=22, minBit 7, minWin=27, winSum=443
1950 20:14:51.667137 TX Vref=24, minBit 1, minWin=27, winSum=444
1951 20:14:51.670435 TX Vref=26, minBit 9, minWin=27, winSum=447
1952 20:14:51.673969 TX Vref=28, minBit 0, minWin=28, winSum=454
1953 20:14:51.677524 TX Vref=30, minBit 0, minWin=28, winSum=453
1954 20:14:51.680665 TX Vref=32, minBit 0, minWin=28, winSum=454
1955 20:14:51.687529 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
1956 20:14:51.687610
1957 20:14:51.690385 Final TX Range 1 Vref 28
1958 20:14:51.690549
1959 20:14:51.690648 ==
1960 20:14:51.695079 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 20:14:51.697502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 20:14:51.697583 ==
1963 20:14:51.697648
1964 20:14:51.697706
1965 20:14:51.700800 TX Vref Scan disable
1966 20:14:51.704390 == TX Byte 0 ==
1967 20:14:51.707766 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1968 20:14:51.711117 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1969 20:14:51.714390 == TX Byte 1 ==
1970 20:14:51.717537 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1971 20:14:51.720903 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1972 20:14:51.720984
1973 20:14:51.724181 [DATLAT]
1974 20:14:51.724261 Freq=800, CH1 RK1
1975 20:14:51.724324
1976 20:14:51.727782 DATLAT Default: 0xa
1977 20:14:51.727888 0, 0xFFFF, sum = 0
1978 20:14:51.730974 1, 0xFFFF, sum = 0
1979 20:14:51.731073 2, 0xFFFF, sum = 0
1980 20:14:51.734309 3, 0xFFFF, sum = 0
1981 20:14:51.734391 4, 0xFFFF, sum = 0
1982 20:14:51.737670 5, 0xFFFF, sum = 0
1983 20:14:51.737752 6, 0xFFFF, sum = 0
1984 20:14:51.741193 7, 0xFFFF, sum = 0
1985 20:14:51.741274 8, 0xFFFF, sum = 0
1986 20:14:51.744818 9, 0x0, sum = 1
1987 20:14:51.744900 10, 0x0, sum = 2
1988 20:14:51.747642 11, 0x0, sum = 3
1989 20:14:51.747724 12, 0x0, sum = 4
1990 20:14:51.750877 best_step = 10
1991 20:14:51.750956
1992 20:14:51.751020 ==
1993 20:14:51.754654 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 20:14:51.757931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 20:14:51.758013 ==
1996 20:14:51.761797 RX Vref Scan: 0
1997 20:14:51.761877
1998 20:14:51.761941 RX Vref 0 -> 0, step: 1
1999 20:14:51.761999
2000 20:14:51.764931 RX Delay -95 -> 252, step: 8
2001 20:14:51.768278 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2002 20:14:51.774783 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2003 20:14:51.777832 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2004 20:14:51.781490 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2005 20:14:51.785042 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2006 20:14:51.788478 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2007 20:14:51.794974 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2008 20:14:51.798013 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2009 20:14:51.801382 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2010 20:14:51.805280 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2011 20:14:51.808602 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2012 20:14:51.811478 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2013 20:14:51.818176 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2014 20:14:51.822329 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2015 20:14:51.824917 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2016 20:14:51.828342 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2017 20:14:51.828422 ==
2018 20:14:51.831547 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 20:14:51.838280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 20:14:51.838391 ==
2021 20:14:51.838497 DQS Delay:
2022 20:14:51.841539 DQS0 = 0, DQS1 = 0
2023 20:14:51.841618 DQM Delay:
2024 20:14:51.841681 DQM0 = 80, DQM1 = 74
2025 20:14:51.845000 DQ Delay:
2026 20:14:51.848619 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2027 20:14:51.851306 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2028 20:14:51.854988 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2029 20:14:51.858801 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =84
2030 20:14:51.858881
2031 20:14:51.858944
2032 20:14:51.865065 [DQSOSCAuto] RK1, (LSB)MR18= 0x212b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2033 20:14:51.868646 CH1 RK1: MR19=606, MR18=212B
2034 20:14:51.874849 CH1_RK1: MR19=0x606, MR18=0x212B, DQSOSC=398, MR23=63, INC=93, DEC=62
2035 20:14:51.878407 [RxdqsGatingPostProcess] freq 800
2036 20:14:51.882142 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 20:14:51.885334 Pre-setting of DQS Precalculation
2038 20:14:51.891486 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 20:14:51.898730 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 20:14:51.905197 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 20:14:51.905277
2042 20:14:51.905340
2043 20:14:51.908383 [Calibration Summary] 1600 Mbps
2044 20:14:51.908463 CH 0, Rank 0
2045 20:14:51.911737 SW Impedance : PASS
2046 20:14:51.915153 DUTY Scan : NO K
2047 20:14:51.915233 ZQ Calibration : PASS
2048 20:14:51.918370 Jitter Meter : NO K
2049 20:14:51.921895 CBT Training : PASS
2050 20:14:51.921975 Write leveling : PASS
2051 20:14:51.925742 RX DQS gating : PASS
2052 20:14:51.925822 RX DQ/DQS(RDDQC) : PASS
2053 20:14:51.928828 TX DQ/DQS : PASS
2054 20:14:51.932467 RX DATLAT : PASS
2055 20:14:51.932546 RX DQ/DQS(Engine): PASS
2056 20:14:51.935253 TX OE : NO K
2057 20:14:51.935333 All Pass.
2058 20:14:51.935397
2059 20:14:51.938346 CH 0, Rank 1
2060 20:14:51.938439 SW Impedance : PASS
2061 20:14:51.941775 DUTY Scan : NO K
2062 20:14:51.945574 ZQ Calibration : PASS
2063 20:14:51.945671 Jitter Meter : NO K
2064 20:14:51.948594 CBT Training : PASS
2065 20:14:51.951613 Write leveling : PASS
2066 20:14:51.951695 RX DQS gating : PASS
2067 20:14:51.955091 RX DQ/DQS(RDDQC) : PASS
2068 20:14:51.958961 TX DQ/DQS : PASS
2069 20:14:51.959041 RX DATLAT : PASS
2070 20:14:51.961926 RX DQ/DQS(Engine): PASS
2071 20:14:51.962005 TX OE : NO K
2072 20:14:51.966121 All Pass.
2073 20:14:51.966200
2074 20:14:51.966263 CH 1, Rank 0
2075 20:14:51.969091 SW Impedance : PASS
2076 20:14:51.969171 DUTY Scan : NO K
2077 20:14:51.972041 ZQ Calibration : PASS
2078 20:14:51.975730 Jitter Meter : NO K
2079 20:14:51.975809 CBT Training : PASS
2080 20:14:51.978389 Write leveling : PASS
2081 20:14:51.982084 RX DQS gating : PASS
2082 20:14:51.982165 RX DQ/DQS(RDDQC) : PASS
2083 20:14:51.985580 TX DQ/DQS : PASS
2084 20:14:51.988847 RX DATLAT : PASS
2085 20:14:51.988926 RX DQ/DQS(Engine): PASS
2086 20:14:51.991926 TX OE : NO K
2087 20:14:51.992005 All Pass.
2088 20:14:51.992068
2089 20:14:51.995286 CH 1, Rank 1
2090 20:14:51.995365 SW Impedance : PASS
2091 20:14:51.998708 DUTY Scan : NO K
2092 20:14:51.998787 ZQ Calibration : PASS
2093 20:14:52.002481 Jitter Meter : NO K
2094 20:14:52.005523 CBT Training : PASS
2095 20:14:52.005628 Write leveling : PASS
2096 20:14:52.009297 RX DQS gating : PASS
2097 20:14:52.011984 RX DQ/DQS(RDDQC) : PASS
2098 20:14:52.012063 TX DQ/DQS : PASS
2099 20:14:52.015346 RX DATLAT : PASS
2100 20:14:52.018828 RX DQ/DQS(Engine): PASS
2101 20:14:52.018908 TX OE : NO K
2102 20:14:52.022782 All Pass.
2103 20:14:52.022861
2104 20:14:52.022924 DramC Write-DBI off
2105 20:14:52.026062 PER_BANK_REFRESH: Hybrid Mode
2106 20:14:52.026186 TX_TRACKING: ON
2107 20:14:52.028832 [GetDramInforAfterCalByMRR] Vendor 6.
2108 20:14:52.032546 [GetDramInforAfterCalByMRR] Revision 606.
2109 20:14:52.039646 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 20:14:52.039768 MR0 0x3b3b
2111 20:14:52.039879 MR8 0x5151
2112 20:14:52.042299 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 20:14:52.042453
2114 20:14:52.045803 MR0 0x3b3b
2115 20:14:52.045904 MR8 0x5151
2116 20:14:52.048944 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 20:14:52.049024
2118 20:14:52.058905 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 20:14:52.062332 [FAST_K] Save calibration result to emmc
2120 20:14:52.066064 [FAST_K] Save calibration result to emmc
2121 20:14:52.069373 dram_init: config_dvfs: 1
2122 20:14:52.072546 dramc_set_vcore_voltage set vcore to 662500
2123 20:14:52.072620 Read voltage for 1200, 2
2124 20:14:52.076852 Vio18 = 0
2125 20:14:52.076944 Vcore = 662500
2126 20:14:52.077037 Vdram = 0
2127 20:14:52.079541 Vddq = 0
2128 20:14:52.079636 Vmddr = 0
2129 20:14:52.082471 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 20:14:52.089224 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 20:14:52.093158 MEM_TYPE=3, freq_sel=15
2132 20:14:52.096354 sv_algorithm_assistance_LP4_1600
2133 20:14:52.099292 ============ PULL DRAM RESETB DOWN ============
2134 20:14:52.102869 ========== PULL DRAM RESETB DOWN end =========
2135 20:14:52.105954 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 20:14:52.109862 ===================================
2137 20:14:52.113089 LPDDR4 DRAM CONFIGURATION
2138 20:14:52.116086 ===================================
2139 20:14:52.119487 EX_ROW_EN[0] = 0x0
2140 20:14:52.119585 EX_ROW_EN[1] = 0x0
2141 20:14:52.122896 LP4Y_EN = 0x0
2142 20:14:52.122977 WORK_FSP = 0x0
2143 20:14:52.126305 WL = 0x4
2144 20:14:52.126385 RL = 0x4
2145 20:14:52.129739 BL = 0x2
2146 20:14:52.129819 RPST = 0x0
2147 20:14:52.133174 RD_PRE = 0x0
2148 20:14:52.133254 WR_PRE = 0x1
2149 20:14:52.137691 WR_PST = 0x0
2150 20:14:52.137771 DBI_WR = 0x0
2151 20:14:52.139874 DBI_RD = 0x0
2152 20:14:52.139954 OTF = 0x1
2153 20:14:52.142935 ===================================
2154 20:14:52.146916 ===================================
2155 20:14:52.150366 ANA top config
2156 20:14:52.153447 ===================================
2157 20:14:52.157258 DLL_ASYNC_EN = 0
2158 20:14:52.157338 ALL_SLAVE_EN = 0
2159 20:14:52.159883 NEW_RANK_MODE = 1
2160 20:14:52.163251 DLL_IDLE_MODE = 1
2161 20:14:52.167027 LP45_APHY_COMB_EN = 1
2162 20:14:52.167107 TX_ODT_DIS = 1
2163 20:14:52.169872 NEW_8X_MODE = 1
2164 20:14:52.173236 ===================================
2165 20:14:52.176723 ===================================
2166 20:14:52.180034 data_rate = 2400
2167 20:14:52.183874 CKR = 1
2168 20:14:52.186758 DQ_P2S_RATIO = 8
2169 20:14:52.190286 ===================================
2170 20:14:52.190369 CA_P2S_RATIO = 8
2171 20:14:52.193323 DQ_CA_OPEN = 0
2172 20:14:52.196935 DQ_SEMI_OPEN = 0
2173 20:14:52.200210 CA_SEMI_OPEN = 0
2174 20:14:52.203474 CA_FULL_RATE = 0
2175 20:14:52.206930 DQ_CKDIV4_EN = 0
2176 20:14:52.207013 CA_CKDIV4_EN = 0
2177 20:14:52.210521 CA_PREDIV_EN = 0
2178 20:14:52.213727 PH8_DLY = 17
2179 20:14:52.217172 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 20:14:52.220457 DQ_AAMCK_DIV = 4
2181 20:14:52.220556 CA_AAMCK_DIV = 4
2182 20:14:52.223996 CA_ADMCK_DIV = 4
2183 20:14:52.227420 DQ_TRACK_CA_EN = 0
2184 20:14:52.230917 CA_PICK = 1200
2185 20:14:52.233947 CA_MCKIO = 1200
2186 20:14:52.237920 MCKIO_SEMI = 0
2187 20:14:52.240912 PLL_FREQ = 2366
2188 20:14:52.241010 DQ_UI_PI_RATIO = 32
2189 20:14:52.244434 CA_UI_PI_RATIO = 0
2190 20:14:52.247380 ===================================
2191 20:14:52.250779 ===================================
2192 20:14:52.254357 memory_type:LPDDR4
2193 20:14:52.257534 GP_NUM : 10
2194 20:14:52.257631 SRAM_EN : 1
2195 20:14:52.260542 MD32_EN : 0
2196 20:14:52.263924 ===================================
2197 20:14:52.267209 [ANA_INIT] >>>>>>>>>>>>>>
2198 20:14:52.267289 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 20:14:52.270715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 20:14:52.274254 ===================================
2201 20:14:52.277222 data_rate = 2400,PCW = 0X5b00
2202 20:14:52.280958 ===================================
2203 20:14:52.284716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 20:14:52.291058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 20:14:52.294490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 20:14:52.301148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 20:14:52.304395 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 20:14:52.307395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 20:14:52.311459 [ANA_INIT] flow start
2210 20:14:52.311531 [ANA_INIT] PLL >>>>>>>>
2211 20:14:52.314594 [ANA_INIT] PLL <<<<<<<<
2212 20:14:52.318037 [ANA_INIT] MIDPI >>>>>>>>
2213 20:14:52.318143 [ANA_INIT] MIDPI <<<<<<<<
2214 20:14:52.320895 [ANA_INIT] DLL >>>>>>>>
2215 20:14:52.324608 [ANA_INIT] DLL <<<<<<<<
2216 20:14:52.324705 [ANA_INIT] flow end
2217 20:14:52.327394 ============ LP4 DIFF to SE enter ============
2218 20:14:52.334295 ============ LP4 DIFF to SE exit ============
2219 20:14:52.334372 [ANA_INIT] <<<<<<<<<<<<<
2220 20:14:52.337799 [Flow] Enable top DCM control >>>>>
2221 20:14:52.341248 [Flow] Enable top DCM control <<<<<
2222 20:14:52.344267 Enable DLL master slave shuffle
2223 20:14:52.351135 ==============================================================
2224 20:14:52.351216 Gating Mode config
2225 20:14:52.358080 ==============================================================
2226 20:14:52.361509 Config description:
2227 20:14:52.371432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 20:14:52.374238 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 20:14:52.382128 SELPH_MODE 0: By rank 1: By Phase
2230 20:14:52.387738 ==============================================================
2231 20:14:52.387819 GAT_TRACK_EN = 1
2232 20:14:52.390901 RX_GATING_MODE = 2
2233 20:14:52.394749 RX_GATING_TRACK_MODE = 2
2234 20:14:52.398210 SELPH_MODE = 1
2235 20:14:52.401451 PICG_EARLY_EN = 1
2236 20:14:52.405013 VALID_LAT_VALUE = 1
2237 20:14:52.411273 ==============================================================
2238 20:14:52.414517 Enter into Gating configuration >>>>
2239 20:14:52.418167 Exit from Gating configuration <<<<
2240 20:14:52.421296 Enter into DVFS_PRE_config >>>>>
2241 20:14:52.431329 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 20:14:52.434430 Exit from DVFS_PRE_config <<<<<
2243 20:14:52.437691 Enter into PICG configuration >>>>
2244 20:14:52.441105 Exit from PICG configuration <<<<
2245 20:14:52.444519 [RX_INPUT] configuration >>>>>
2246 20:14:52.444592 [RX_INPUT] configuration <<<<<
2247 20:14:52.451243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 20:14:52.457869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 20:14:52.461132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 20:14:52.467894 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 20:14:52.475128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 20:14:52.481296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 20:14:52.484954 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 20:14:52.487901 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 20:14:52.495688 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 20:14:52.498205 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 20:14:52.501548 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 20:14:52.504851 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 20:14:52.508124 ===================================
2260 20:14:52.511307 LPDDR4 DRAM CONFIGURATION
2261 20:14:52.515347 ===================================
2262 20:14:52.518331 EX_ROW_EN[0] = 0x0
2263 20:14:52.518456 EX_ROW_EN[1] = 0x0
2264 20:14:52.521519 LP4Y_EN = 0x0
2265 20:14:52.521600 WORK_FSP = 0x0
2266 20:14:52.525173 WL = 0x4
2267 20:14:52.525254 RL = 0x4
2268 20:14:52.529065 BL = 0x2
2269 20:14:52.529146 RPST = 0x0
2270 20:14:52.531563 RD_PRE = 0x0
2271 20:14:52.531644 WR_PRE = 0x1
2272 20:14:52.534870 WR_PST = 0x0
2273 20:14:52.534950 DBI_WR = 0x0
2274 20:14:52.538368 DBI_RD = 0x0
2275 20:14:52.538487 OTF = 0x1
2276 20:14:52.541810 ===================================
2277 20:14:52.548911 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 20:14:52.551973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 20:14:52.556042 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 20:14:52.558637 ===================================
2281 20:14:52.561752 LPDDR4 DRAM CONFIGURATION
2282 20:14:52.565057 ===================================
2283 20:14:52.565138 EX_ROW_EN[0] = 0x10
2284 20:14:52.568386 EX_ROW_EN[1] = 0x0
2285 20:14:52.572380 LP4Y_EN = 0x0
2286 20:14:52.572465 WORK_FSP = 0x0
2287 20:14:52.575299 WL = 0x4
2288 20:14:52.575379 RL = 0x4
2289 20:14:52.578372 BL = 0x2
2290 20:14:52.578488 RPST = 0x0
2291 20:14:52.582039 RD_PRE = 0x0
2292 20:14:52.582120 WR_PRE = 0x1
2293 20:14:52.585441 WR_PST = 0x0
2294 20:14:52.585522 DBI_WR = 0x0
2295 20:14:52.588282 DBI_RD = 0x0
2296 20:14:52.588362 OTF = 0x1
2297 20:14:52.591709 ===================================
2298 20:14:52.598327 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 20:14:52.598419 ==
2300 20:14:52.601826 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 20:14:52.605333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 20:14:52.605438 ==
2303 20:14:52.608376 [Duty_Offset_Calibration]
2304 20:14:52.611774 B0:2 B1:-1 CA:1
2305 20:14:52.611874
2306 20:14:52.615263 [DutyScan_Calibration_Flow] k_type=0
2307 20:14:52.623018
2308 20:14:52.623098 ==CLK 0==
2309 20:14:52.625878 Final CLK duty delay cell = -4
2310 20:14:52.628867 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2311 20:14:52.632499 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2312 20:14:52.636681 [-4] AVG Duty = 4953%(X100)
2313 20:14:52.636763
2314 20:14:52.639327 CH0 CLK Duty spec in!! Max-Min= 156%
2315 20:14:52.643267 [DutyScan_Calibration_Flow] ====Done====
2316 20:14:52.643349
2317 20:14:52.646027 [DutyScan_Calibration_Flow] k_type=1
2318 20:14:52.660366
2319 20:14:52.660440 ==DQS 0 ==
2320 20:14:52.664055 Final DQS duty delay cell = -4
2321 20:14:52.667679 [-4] MAX Duty = 5031%(X100), DQS PI = 54
2322 20:14:52.670563 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2323 20:14:52.673893 [-4] AVG Duty = 4953%(X100)
2324 20:14:52.674009
2325 20:14:52.674101 ==DQS 1 ==
2326 20:14:52.678641 Final DQS duty delay cell = -4
2327 20:14:52.681019 [-4] MAX Duty = 5124%(X100), DQS PI = 16
2328 20:14:52.684150 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2329 20:14:52.687289 [-4] AVG Duty = 5062%(X100)
2330 20:14:52.687368
2331 20:14:52.691078 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2332 20:14:52.691184
2333 20:14:52.694591 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2334 20:14:52.697816 [DutyScan_Calibration_Flow] ====Done====
2335 20:14:52.697928
2336 20:14:52.700615 [DutyScan_Calibration_Flow] k_type=3
2337 20:14:52.717990
2338 20:14:52.718073 ==DQM 0 ==
2339 20:14:52.720848 Final DQM duty delay cell = 0
2340 20:14:52.724548 [0] MAX Duty = 5000%(X100), DQS PI = 46
2341 20:14:52.727663 [0] MIN Duty = 4907%(X100), DQS PI = 2
2342 20:14:52.727743 [0] AVG Duty = 4953%(X100)
2343 20:14:52.731426
2344 20:14:52.731524 ==DQM 1 ==
2345 20:14:52.734558 Final DQM duty delay cell = 0
2346 20:14:52.739088 [0] MAX Duty = 5156%(X100), DQS PI = 62
2347 20:14:52.740960 [0] MIN Duty = 4969%(X100), DQS PI = 10
2348 20:14:52.741060 [0] AVG Duty = 5062%(X100)
2349 20:14:52.741149
2350 20:14:52.744671 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2351 20:14:52.748045
2352 20:14:52.751390 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2353 20:14:52.754722 [DutyScan_Calibration_Flow] ====Done====
2354 20:14:52.754802
2355 20:14:52.757948 [DutyScan_Calibration_Flow] k_type=2
2356 20:14:52.773453
2357 20:14:52.773535 ==DQ 0 ==
2358 20:14:52.777056 Final DQ duty delay cell = -4
2359 20:14:52.780200 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2360 20:14:52.783179 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2361 20:14:52.786667 [-4] AVG Duty = 4953%(X100)
2362 20:14:52.786748
2363 20:14:52.786811 ==DQ 1 ==
2364 20:14:52.790452 Final DQ duty delay cell = 0
2365 20:14:52.793393 [0] MAX Duty = 5031%(X100), DQS PI = 18
2366 20:14:52.796880 [0] MIN Duty = 4907%(X100), DQS PI = 46
2367 20:14:52.796972 [0] AVG Duty = 4969%(X100)
2368 20:14:52.800092
2369 20:14:52.803722 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2370 20:14:52.803830
2371 20:14:52.807338 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2372 20:14:52.810047 [DutyScan_Calibration_Flow] ====Done====
2373 20:14:52.810150 ==
2374 20:14:52.813511 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 20:14:52.817040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 20:14:52.817148 ==
2377 20:14:52.821002 [Duty_Offset_Calibration]
2378 20:14:52.821099 B0:1 B1:1 CA:2
2379 20:14:52.821191
2380 20:14:52.823542 [DutyScan_Calibration_Flow] k_type=0
2381 20:14:52.834301
2382 20:14:52.834415 ==CLK 0==
2383 20:14:52.836953 Final CLK duty delay cell = 0
2384 20:14:52.840104 [0] MAX Duty = 5156%(X100), DQS PI = 24
2385 20:14:52.843977 [0] MIN Duty = 4969%(X100), DQS PI = 38
2386 20:14:52.844074 [0] AVG Duty = 5062%(X100)
2387 20:14:52.847145
2388 20:14:52.850137 CH1 CLK Duty spec in!! Max-Min= 187%
2389 20:14:52.853383 [DutyScan_Calibration_Flow] ====Done====
2390 20:14:52.853479
2391 20:14:52.856878 [DutyScan_Calibration_Flow] k_type=1
2392 20:14:52.873317
2393 20:14:52.873536 ==DQS 0 ==
2394 20:14:52.876715 Final DQS duty delay cell = 0
2395 20:14:52.880070 [0] MAX Duty = 5031%(X100), DQS PI = 20
2396 20:14:52.883508 [0] MIN Duty = 4813%(X100), DQS PI = 50
2397 20:14:52.883594 [0] AVG Duty = 4922%(X100)
2398 20:14:52.886641
2399 20:14:52.886721 ==DQS 1 ==
2400 20:14:52.890162 Final DQS duty delay cell = 0
2401 20:14:52.893536 [0] MAX Duty = 5062%(X100), DQS PI = 36
2402 20:14:52.896761 [0] MIN Duty = 4907%(X100), DQS PI = 8
2403 20:14:52.896863 [0] AVG Duty = 4984%(X100)
2404 20:14:52.896977
2405 20:14:52.903369 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2406 20:14:52.903510
2407 20:14:52.906230 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2408 20:14:52.909888 [DutyScan_Calibration_Flow] ====Done====
2409 20:14:52.910007
2410 20:14:52.912987 [DutyScan_Calibration_Flow] k_type=3
2411 20:14:52.929860
2412 20:14:52.929988 ==DQM 0 ==
2413 20:14:52.932616 Final DQM duty delay cell = 0
2414 20:14:52.936136 [0] MAX Duty = 5093%(X100), DQS PI = 18
2415 20:14:52.939220 [0] MIN Duty = 4907%(X100), DQS PI = 48
2416 20:14:52.939347 [0] AVG Duty = 5000%(X100)
2417 20:14:52.943381
2418 20:14:52.943498 ==DQM 1 ==
2419 20:14:52.945969 Final DQM duty delay cell = 0
2420 20:14:52.949426 [0] MAX Duty = 5156%(X100), DQS PI = 62
2421 20:14:52.952607 [0] MIN Duty = 4938%(X100), DQS PI = 22
2422 20:14:52.952726 [0] AVG Duty = 5047%(X100)
2423 20:14:52.956581
2424 20:14:52.959713 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2425 20:14:52.959833
2426 20:14:52.963052 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2427 20:14:52.966203 [DutyScan_Calibration_Flow] ====Done====
2428 20:14:52.966337
2429 20:14:52.969606 [DutyScan_Calibration_Flow] k_type=2
2430 20:14:52.986106
2431 20:14:52.986215 ==DQ 0 ==
2432 20:14:52.989233 Final DQ duty delay cell = 0
2433 20:14:52.993576 [0] MAX Duty = 5125%(X100), DQS PI = 18
2434 20:14:52.996691 [0] MIN Duty = 4907%(X100), DQS PI = 50
2435 20:14:52.996764 [0] AVG Duty = 5016%(X100)
2436 20:14:52.996825
2437 20:14:52.999573 ==DQ 1 ==
2438 20:14:52.999645 Final DQ duty delay cell = 0
2439 20:14:53.006520 [0] MAX Duty = 5093%(X100), DQS PI = 10
2440 20:14:53.009541 [0] MIN Duty = 5031%(X100), DQS PI = 2
2441 20:14:53.009613 [0] AVG Duty = 5062%(X100)
2442 20:14:53.009672
2443 20:14:53.013170 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2444 20:14:53.013267
2445 20:14:53.016552 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2446 20:14:53.019659 [DutyScan_Calibration_Flow] ====Done====
2447 20:14:53.025460 nWR fixed to 30
2448 20:14:53.028420 [ModeRegInit_LP4] CH0 RK0
2449 20:14:53.028503 [ModeRegInit_LP4] CH0 RK1
2450 20:14:53.031618 [ModeRegInit_LP4] CH1 RK0
2451 20:14:53.035302 [ModeRegInit_LP4] CH1 RK1
2452 20:14:53.035378 match AC timing 7
2453 20:14:53.041608 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 20:14:53.044972 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 20:14:53.048150 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 20:14:53.055368 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 20:14:53.058815 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 20:14:53.058930 ==
2459 20:14:53.062180 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 20:14:53.065563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 20:14:53.065682 ==
2462 20:14:53.072506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 20:14:53.078486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2464 20:14:53.085996 [CA 0] Center 40 (10~71) winsize 62
2465 20:14:53.089375 [CA 1] Center 39 (9~70) winsize 62
2466 20:14:53.092498 [CA 2] Center 36 (6~67) winsize 62
2467 20:14:53.096208 [CA 3] Center 36 (6~66) winsize 61
2468 20:14:53.099174 [CA 4] Center 34 (4~65) winsize 62
2469 20:14:53.102564 [CA 5] Center 34 (4~64) winsize 61
2470 20:14:53.102682
2471 20:14:53.105981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2472 20:14:53.106099
2473 20:14:53.109377 [CATrainingPosCal] consider 1 rank data
2474 20:14:53.113211 u2DelayCellTimex100 = 270/100 ps
2475 20:14:53.115929 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2476 20:14:53.120105 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2477 20:14:53.125902 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2478 20:14:53.129298 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2479 20:14:53.133351 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2480 20:14:53.136203 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2481 20:14:53.136276
2482 20:14:53.139783 CA PerBit enable=1, Macro0, CA PI delay=34
2483 20:14:53.139858
2484 20:14:53.142511 [CBTSetCACLKResult] CA Dly = 34
2485 20:14:53.142607 CS Dly: 7 (0~38)
2486 20:14:53.142703 ==
2487 20:14:53.146355 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 20:14:53.153069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 20:14:53.153142 ==
2490 20:14:53.156070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 20:14:53.162690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 20:14:53.171930 [CA 0] Center 39 (9~70) winsize 62
2493 20:14:53.175652 [CA 1] Center 39 (9~70) winsize 62
2494 20:14:53.178295 [CA 2] Center 36 (6~67) winsize 62
2495 20:14:53.182018 [CA 3] Center 35 (5~66) winsize 62
2496 20:14:53.185034 [CA 4] Center 34 (4~65) winsize 62
2497 20:14:53.188720 [CA 5] Center 34 (4~64) winsize 61
2498 20:14:53.188839
2499 20:14:53.191654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 20:14:53.191770
2501 20:14:53.195172 [CATrainingPosCal] consider 2 rank data
2502 20:14:53.198764 u2DelayCellTimex100 = 270/100 ps
2503 20:14:53.201768 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2504 20:14:53.205582 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2505 20:14:53.211928 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2506 20:14:53.215873 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2507 20:14:53.219276 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2508 20:14:53.222153 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2509 20:14:53.222270
2510 20:14:53.225409 CA PerBit enable=1, Macro0, CA PI delay=34
2511 20:14:53.225522
2512 20:14:53.228652 [CBTSetCACLKResult] CA Dly = 34
2513 20:14:53.228769 CS Dly: 8 (0~41)
2514 20:14:53.228875
2515 20:14:53.232178 ----->DramcWriteLeveling(PI) begin...
2516 20:14:53.235326 ==
2517 20:14:53.235445 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 20:14:53.242684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 20:14:53.242804 ==
2520 20:14:53.245060 Write leveling (Byte 0): 31 => 31
2521 20:14:53.248730 Write leveling (Byte 1): 29 => 29
2522 20:14:53.248831 DramcWriteLeveling(PI) end<-----
2523 20:14:53.252119
2524 20:14:53.252214 ==
2525 20:14:53.255145 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 20:14:53.258915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 20:14:53.258996 ==
2528 20:14:53.262186 [Gating] SW mode calibration
2529 20:14:53.268724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 20:14:53.272851 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 20:14:53.278779 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 20:14:53.282133 0 15 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2533 20:14:53.285302 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 20:14:53.292762 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 20:14:53.295545 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 20:14:53.298901 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 20:14:53.305828 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 20:14:53.309307 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 20:14:53.312093 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2540 20:14:53.316038 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2541 20:14:53.323660 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 20:14:53.325536 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 20:14:53.328909 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 20:14:53.336322 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 20:14:53.339128 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 20:14:53.343827 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 20:14:53.349281 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2548 20:14:53.352569 1 1 4 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
2549 20:14:53.356081 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 20:14:53.362792 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 20:14:53.366150 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 20:14:53.369942 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 20:14:53.376164 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 20:14:53.379549 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 20:14:53.382733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2556 20:14:53.385961 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 20:14:53.393773 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 20:14:53.396007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 20:14:53.399733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 20:14:53.406078 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 20:14:53.409630 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 20:14:53.413496 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 20:14:53.419817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 20:14:53.423288 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 20:14:53.426488 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 20:14:53.432925 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 20:14:53.436785 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 20:14:53.439652 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 20:14:53.446541 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 20:14:53.450536 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 20:14:53.453290 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2572 20:14:53.456930 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 20:14:53.459837 Total UI for P1: 0, mck2ui 16
2574 20:14:53.463456 best dqsien dly found for B0: ( 1, 4, 0)
2575 20:14:53.466848 Total UI for P1: 0, mck2ui 16
2576 20:14:53.469751 best dqsien dly found for B1: ( 1, 4, 0)
2577 20:14:53.473099 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2578 20:14:53.476659 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2579 20:14:53.476778
2580 20:14:53.479946 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 20:14:53.486866 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2582 20:14:53.486988 [Gating] SW calibration Done
2583 20:14:53.487100 ==
2584 20:14:53.490076 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 20:14:53.496916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 20:14:53.497018 ==
2587 20:14:53.497109 RX Vref Scan: 0
2588 20:14:53.497195
2589 20:14:53.500486 RX Vref 0 -> 0, step: 1
2590 20:14:53.500579
2591 20:14:53.503949 RX Delay -40 -> 252, step: 8
2592 20:14:53.507050 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2593 20:14:53.510378 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2594 20:14:53.513572 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2595 20:14:53.517132 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2596 20:14:53.523454 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2597 20:14:53.527726 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2598 20:14:53.530361 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2599 20:14:53.533502 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2600 20:14:53.537407 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2601 20:14:53.543544 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2602 20:14:53.547463 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2603 20:14:53.550898 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2604 20:14:53.553820 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2605 20:14:53.557223 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2606 20:14:53.564119 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2607 20:14:53.568127 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2608 20:14:53.568223 ==
2609 20:14:53.570643 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 20:14:53.573786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 20:14:53.573888 ==
2612 20:14:53.573976 DQS Delay:
2613 20:14:53.577309 DQS0 = 0, DQS1 = 0
2614 20:14:53.577385 DQM Delay:
2615 20:14:53.580601 DQM0 = 116, DQM1 = 107
2616 20:14:53.580674 DQ Delay:
2617 20:14:53.584112 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2618 20:14:53.587184 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2619 20:14:53.590668 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2620 20:14:53.594066 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2621 20:14:53.594170
2622 20:14:53.594260
2623 20:14:53.597147 ==
2624 20:14:53.600849 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 20:14:53.604014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 20:14:53.604094 ==
2627 20:14:53.604176
2628 20:14:53.604236
2629 20:14:53.607366 TX Vref Scan disable
2630 20:14:53.607445 == TX Byte 0 ==
2631 20:14:53.610926 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2632 20:14:53.617597 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2633 20:14:53.617673 == TX Byte 1 ==
2634 20:14:53.620830 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2635 20:14:53.627478 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2636 20:14:53.627552 ==
2637 20:14:53.631065 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 20:14:53.633891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 20:14:53.633994 ==
2640 20:14:53.646337 TX Vref=22, minBit 7, minWin=24, winSum=419
2641 20:14:53.649509 TX Vref=24, minBit 1, minWin=25, winSum=421
2642 20:14:53.652984 TX Vref=26, minBit 5, minWin=25, winSum=425
2643 20:14:53.656096 TX Vref=28, minBit 0, minWin=26, winSum=432
2644 20:14:53.659974 TX Vref=30, minBit 1, minWin=26, winSum=435
2645 20:14:53.662898 TX Vref=32, minBit 0, minWin=26, winSum=430
2646 20:14:53.669224 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 30
2647 20:14:53.669323
2648 20:14:53.672566 Final TX Range 1 Vref 30
2649 20:14:53.672661
2650 20:14:53.672755 ==
2651 20:14:53.676547 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 20:14:53.679789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 20:14:53.679895 ==
2654 20:14:53.679983
2655 20:14:53.680068
2656 20:14:53.683233 TX Vref Scan disable
2657 20:14:53.686788 == TX Byte 0 ==
2658 20:14:53.690037 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2659 20:14:53.693183 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2660 20:14:53.696813 == TX Byte 1 ==
2661 20:14:53.700100 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2662 20:14:53.703003 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2663 20:14:53.703088
2664 20:14:53.706389 [DATLAT]
2665 20:14:53.706487 Freq=1200, CH0 RK0
2666 20:14:53.706582
2667 20:14:53.709973 DATLAT Default: 0xd
2668 20:14:53.710070 0, 0xFFFF, sum = 0
2669 20:14:53.713079 1, 0xFFFF, sum = 0
2670 20:14:53.713185 2, 0xFFFF, sum = 0
2671 20:14:53.717277 3, 0xFFFF, sum = 0
2672 20:14:53.717352 4, 0xFFFF, sum = 0
2673 20:14:53.719822 5, 0xFFFF, sum = 0
2674 20:14:53.719895 6, 0xFFFF, sum = 0
2675 20:14:53.723341 7, 0xFFFF, sum = 0
2676 20:14:53.723424 8, 0xFFFF, sum = 0
2677 20:14:53.726351 9, 0xFFFF, sum = 0
2678 20:14:53.726474 10, 0xFFFF, sum = 0
2679 20:14:53.729888 11, 0xFFFF, sum = 0
2680 20:14:53.729995 12, 0x0, sum = 1
2681 20:14:53.734039 13, 0x0, sum = 2
2682 20:14:53.734154 14, 0x0, sum = 3
2683 20:14:53.737605 15, 0x0, sum = 4
2684 20:14:53.737704 best_step = 13
2685 20:14:53.737799
2686 20:14:53.737885 ==
2687 20:14:53.740059 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 20:14:53.743272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 20:14:53.746671 ==
2690 20:14:53.746769 RX Vref Scan: 1
2691 20:14:53.746855
2692 20:14:53.750271 Set Vref Range= 32 -> 127
2693 20:14:53.750343
2694 20:14:53.753695 RX Vref 32 -> 127, step: 1
2695 20:14:53.753764
2696 20:14:53.753840 RX Delay -21 -> 252, step: 4
2697 20:14:53.753898
2698 20:14:53.756700 Set Vref, RX VrefLevel [Byte0]: 32
2699 20:14:53.760607 [Byte1]: 32
2700 20:14:53.764167
2701 20:14:53.764237 Set Vref, RX VrefLevel [Byte0]: 33
2702 20:14:53.767867 [Byte1]: 33
2703 20:14:53.771996
2704 20:14:53.772097 Set Vref, RX VrefLevel [Byte0]: 34
2705 20:14:53.775557 [Byte1]: 34
2706 20:14:53.780115
2707 20:14:53.780190 Set Vref, RX VrefLevel [Byte0]: 35
2708 20:14:53.783584 [Byte1]: 35
2709 20:14:53.788306
2710 20:14:53.788412 Set Vref, RX VrefLevel [Byte0]: 36
2711 20:14:53.792419 [Byte1]: 36
2712 20:14:53.796281
2713 20:14:53.796354 Set Vref, RX VrefLevel [Byte0]: 37
2714 20:14:53.799758 [Byte1]: 37
2715 20:14:53.804609
2716 20:14:53.804722 Set Vref, RX VrefLevel [Byte0]: 38
2717 20:14:53.807048 [Byte1]: 38
2718 20:14:53.812258
2719 20:14:53.812333 Set Vref, RX VrefLevel [Byte0]: 39
2720 20:14:53.815282 [Byte1]: 39
2721 20:14:53.819625
2722 20:14:53.819704 Set Vref, RX VrefLevel [Byte0]: 40
2723 20:14:53.822868 [Byte1]: 40
2724 20:14:53.827820
2725 20:14:53.827979 Set Vref, RX VrefLevel [Byte0]: 41
2726 20:14:53.831128 [Byte1]: 41
2727 20:14:53.835623
2728 20:14:53.835696 Set Vref, RX VrefLevel [Byte0]: 42
2729 20:14:53.838836 [Byte1]: 42
2730 20:14:53.844379
2731 20:14:53.844451 Set Vref, RX VrefLevel [Byte0]: 43
2732 20:14:53.847194 [Byte1]: 43
2733 20:14:53.851327
2734 20:14:53.851408 Set Vref, RX VrefLevel [Byte0]: 44
2735 20:14:53.854496 [Byte1]: 44
2736 20:14:53.859284
2737 20:14:53.859364 Set Vref, RX VrefLevel [Byte0]: 45
2738 20:14:53.862840 [Byte1]: 45
2739 20:14:53.867263
2740 20:14:53.867359 Set Vref, RX VrefLevel [Byte0]: 46
2741 20:14:53.870954 [Byte1]: 46
2742 20:14:53.875277
2743 20:14:53.875357 Set Vref, RX VrefLevel [Byte0]: 47
2744 20:14:53.878474 [Byte1]: 47
2745 20:14:53.883054
2746 20:14:53.883150 Set Vref, RX VrefLevel [Byte0]: 48
2747 20:14:53.886619 [Byte1]: 48
2748 20:14:53.890862
2749 20:14:53.890942 Set Vref, RX VrefLevel [Byte0]: 49
2750 20:14:53.894688 [Byte1]: 49
2751 20:14:53.899717
2752 20:14:53.899797 Set Vref, RX VrefLevel [Byte0]: 50
2753 20:14:53.902716 [Byte1]: 50
2754 20:14:53.906829
2755 20:14:53.906909 Set Vref, RX VrefLevel [Byte0]: 51
2756 20:14:53.910414 [Byte1]: 51
2757 20:14:53.914803
2758 20:14:53.914883 Set Vref, RX VrefLevel [Byte0]: 52
2759 20:14:53.918528 [Byte1]: 52
2760 20:14:53.922829
2761 20:14:53.922951 Set Vref, RX VrefLevel [Byte0]: 53
2762 20:14:53.926338 [Byte1]: 53
2763 20:14:53.930406
2764 20:14:53.930511 Set Vref, RX VrefLevel [Byte0]: 54
2765 20:14:53.934235 [Byte1]: 54
2766 20:14:53.939246
2767 20:14:53.939325 Set Vref, RX VrefLevel [Byte0]: 55
2768 20:14:53.942237 [Byte1]: 55
2769 20:14:53.946409
2770 20:14:53.946499 Set Vref, RX VrefLevel [Byte0]: 56
2771 20:14:53.949676 [Byte1]: 56
2772 20:14:53.954661
2773 20:14:53.954737 Set Vref, RX VrefLevel [Byte0]: 57
2774 20:14:53.957941 [Byte1]: 57
2775 20:14:53.962552
2776 20:14:53.962659 Set Vref, RX VrefLevel [Byte0]: 58
2777 20:14:53.965695 [Byte1]: 58
2778 20:14:53.970236
2779 20:14:53.970316 Set Vref, RX VrefLevel [Byte0]: 59
2780 20:14:53.973814 [Byte1]: 59
2781 20:14:53.978167
2782 20:14:53.978248 Set Vref, RX VrefLevel [Byte0]: 60
2783 20:14:53.981319 [Byte1]: 60
2784 20:14:53.985958
2785 20:14:53.986042 Set Vref, RX VrefLevel [Byte0]: 61
2786 20:14:53.992797 [Byte1]: 61
2787 20:14:53.992877
2788 20:14:53.996010 Set Vref, RX VrefLevel [Byte0]: 62
2789 20:14:53.999679 [Byte1]: 62
2790 20:14:53.999759
2791 20:14:54.002918 Set Vref, RX VrefLevel [Byte0]: 63
2792 20:14:54.006537 [Byte1]: 63
2793 20:14:54.010188
2794 20:14:54.010300 Set Vref, RX VrefLevel [Byte0]: 64
2795 20:14:54.013624 [Byte1]: 64
2796 20:14:54.018385
2797 20:14:54.018503 Set Vref, RX VrefLevel [Byte0]: 65
2798 20:14:54.021142 [Byte1]: 65
2799 20:14:54.026029
2800 20:14:54.026109 Set Vref, RX VrefLevel [Byte0]: 66
2801 20:14:54.029540 [Byte1]: 66
2802 20:14:54.033845
2803 20:14:54.033924 Set Vref, RX VrefLevel [Byte0]: 67
2804 20:14:54.037433 [Byte1]: 67
2805 20:14:54.041637
2806 20:14:54.041717 Set Vref, RX VrefLevel [Byte0]: 68
2807 20:14:54.045522 [Byte1]: 68
2808 20:14:54.049498
2809 20:14:54.049577 Final RX Vref Byte 0 = 54 to rank0
2810 20:14:54.053253 Final RX Vref Byte 1 = 52 to rank0
2811 20:14:54.056278 Final RX Vref Byte 0 = 54 to rank1
2812 20:14:54.059394 Final RX Vref Byte 1 = 52 to rank1==
2813 20:14:54.063416 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 20:14:54.066260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 20:14:54.070517 ==
2816 20:14:54.070599 DQS Delay:
2817 20:14:54.070663 DQS0 = 0, DQS1 = 0
2818 20:14:54.072900 DQM Delay:
2819 20:14:54.072980 DQM0 = 115, DQM1 = 105
2820 20:14:54.076356 DQ Delay:
2821 20:14:54.079538 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2822 20:14:54.083334 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2823 20:14:54.086432 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2824 20:14:54.089779 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2825 20:14:54.089860
2826 20:14:54.089924
2827 20:14:54.096340 [DQSOSCAuto] RK0, (LSB)MR18= 0xfded, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
2828 20:14:54.100628 CH0 RK0: MR19=303, MR18=FDED
2829 20:14:54.106241 CH0_RK0: MR19=0x303, MR18=0xFDED, DQSOSC=411, MR23=63, INC=38, DEC=25
2830 20:14:54.106366
2831 20:14:54.110415 ----->DramcWriteLeveling(PI) begin...
2832 20:14:54.110531 ==
2833 20:14:54.114084 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 20:14:54.116780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 20:14:54.116890 ==
2836 20:14:54.119633 Write leveling (Byte 0): 31 => 31
2837 20:14:54.123031 Write leveling (Byte 1): 30 => 30
2838 20:14:54.126560 DramcWriteLeveling(PI) end<-----
2839 20:14:54.126641
2840 20:14:54.126705 ==
2841 20:14:54.129446 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 20:14:54.133522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 20:14:54.136483 ==
2844 20:14:54.136595 [Gating] SW mode calibration
2845 20:14:54.143045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 20:14:54.150908 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 20:14:54.153118 0 15 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
2848 20:14:54.160144 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2849 20:14:54.164077 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 20:14:54.166439 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 20:14:54.173573 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 20:14:54.176682 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 20:14:54.180584 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 20:14:54.183428 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
2855 20:14:54.190045 1 0 0 | B1->B0 | 2e2e 2727 | 1 0 | (1 0) (0 0)
2856 20:14:54.193331 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 20:14:54.196875 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 20:14:54.203311 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 20:14:54.207515 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 20:14:54.210380 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 20:14:54.217048 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2862 20:14:54.220385 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2863 20:14:54.223857 1 1 0 | B1->B0 | 2b2b 3e3e | 0 0 | (0 0) (0 0)
2864 20:14:54.230651 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2865 20:14:54.233960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 20:14:54.237453 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 20:14:54.240508 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 20:14:54.247088 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 20:14:54.251146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 20:14:54.253424 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2871 20:14:54.260406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2872 20:14:54.263967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2873 20:14:54.267334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 20:14:54.273907 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 20:14:54.277295 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 20:14:54.280339 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 20:14:54.287254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 20:14:54.290329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 20:14:54.294178 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 20:14:54.300253 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 20:14:54.303838 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 20:14:54.306942 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 20:14:54.315056 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 20:14:54.317168 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 20:14:54.320005 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2886 20:14:54.326988 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2887 20:14:54.330539 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2888 20:14:54.333669 Total UI for P1: 0, mck2ui 16
2889 20:14:54.337185 best dqsien dly found for B0: ( 1, 3, 26)
2890 20:14:54.340257 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 20:14:54.343710 Total UI for P1: 0, mck2ui 16
2892 20:14:54.347363 best dqsien dly found for B1: ( 1, 3, 30)
2893 20:14:54.350280 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2894 20:14:54.353787 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2895 20:14:54.353868
2896 20:14:54.357963 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2897 20:14:54.360942 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2898 20:14:54.364276 [Gating] SW calibration Done
2899 20:14:54.364357 ==
2900 20:14:54.367756 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 20:14:54.373912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 20:14:54.373994 ==
2903 20:14:54.374058 RX Vref Scan: 0
2904 20:14:54.374118
2905 20:14:54.377592 RX Vref 0 -> 0, step: 1
2906 20:14:54.377673
2907 20:14:54.380993 RX Delay -40 -> 252, step: 8
2908 20:14:54.383948 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2909 20:14:54.387526 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2910 20:14:54.390928 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2911 20:14:54.395055 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2912 20:14:54.400877 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2913 20:14:54.404035 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2914 20:14:54.407478 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2915 20:14:54.410859 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2916 20:14:54.414385 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2917 20:14:54.418253 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2918 20:14:54.424285 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2919 20:14:54.427676 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2920 20:14:54.430921 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2921 20:14:54.434283 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2922 20:14:54.437753 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2923 20:14:54.444807 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2924 20:14:54.444889 ==
2925 20:14:54.448642 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 20:14:54.451342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 20:14:54.451424 ==
2928 20:14:54.451488 DQS Delay:
2929 20:14:54.454703 DQS0 = 0, DQS1 = 0
2930 20:14:54.454783 DQM Delay:
2931 20:14:54.457590 DQM0 = 115, DQM1 = 106
2932 20:14:54.457670 DQ Delay:
2933 20:14:54.461207 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2934 20:14:54.465143 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2935 20:14:54.468342 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2936 20:14:54.471403 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2937 20:14:54.471484
2938 20:14:54.471582
2939 20:14:54.474553 ==
2940 20:14:54.474634 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 20:14:54.480841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 20:14:54.480947 ==
2943 20:14:54.481039
2944 20:14:54.481133
2945 20:14:54.484577 TX Vref Scan disable
2946 20:14:54.484651 == TX Byte 0 ==
2947 20:14:54.487708 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2948 20:14:54.494554 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2949 20:14:54.494634 == TX Byte 1 ==
2950 20:14:54.498058 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2951 20:14:54.504674 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2952 20:14:54.504779 ==
2953 20:14:54.508253 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 20:14:54.511301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 20:14:54.511376 ==
2956 20:14:54.522937 TX Vref=22, minBit 1, minWin=25, winSum=417
2957 20:14:54.526306 TX Vref=24, minBit 1, minWin=26, winSum=430
2958 20:14:54.529818 TX Vref=26, minBit 5, minWin=26, winSum=434
2959 20:14:54.532702 TX Vref=28, minBit 0, minWin=27, winSum=437
2960 20:14:54.536385 TX Vref=30, minBit 5, minWin=26, winSum=436
2961 20:14:54.539985 TX Vref=32, minBit 5, minWin=26, winSum=434
2962 20:14:54.546156 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 28
2963 20:14:54.546280
2964 20:14:54.549899 Final TX Range 1 Vref 28
2965 20:14:54.550017
2966 20:14:54.550124 ==
2967 20:14:54.553294 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 20:14:54.556483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 20:14:54.556566 ==
2970 20:14:54.556630
2971 20:14:54.556689
2972 20:14:54.560222 TX Vref Scan disable
2973 20:14:54.563825 == TX Byte 0 ==
2974 20:14:54.566352 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2975 20:14:54.570306 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2976 20:14:54.573818 == TX Byte 1 ==
2977 20:14:54.576585 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2978 20:14:54.580570 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2979 20:14:54.580652
2980 20:14:54.583614 [DATLAT]
2981 20:14:54.583695 Freq=1200, CH0 RK1
2982 20:14:54.583798
2983 20:14:54.586852 DATLAT Default: 0xd
2984 20:14:54.586933 0, 0xFFFF, sum = 0
2985 20:14:54.590636 1, 0xFFFF, sum = 0
2986 20:14:54.590736 2, 0xFFFF, sum = 0
2987 20:14:54.593523 3, 0xFFFF, sum = 0
2988 20:14:54.593606 4, 0xFFFF, sum = 0
2989 20:14:54.597771 5, 0xFFFF, sum = 0
2990 20:14:54.597880 6, 0xFFFF, sum = 0
2991 20:14:54.600666 7, 0xFFFF, sum = 0
2992 20:14:54.600748 8, 0xFFFF, sum = 0
2993 20:14:54.603584 9, 0xFFFF, sum = 0
2994 20:14:54.603667 10, 0xFFFF, sum = 0
2995 20:14:54.606831 11, 0xFFFF, sum = 0
2996 20:14:54.606914 12, 0x0, sum = 1
2997 20:14:54.610330 13, 0x0, sum = 2
2998 20:14:54.610463 14, 0x0, sum = 3
2999 20:14:54.613414 15, 0x0, sum = 4
3000 20:14:54.613512 best_step = 13
3001 20:14:54.613599
3002 20:14:54.613686 ==
3003 20:14:54.617271 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 20:14:54.621022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 20:14:54.623608 ==
3006 20:14:54.623689 RX Vref Scan: 0
3007 20:14:54.623752
3008 20:14:54.627104 RX Vref 0 -> 0, step: 1
3009 20:14:54.627185
3010 20:14:54.630874 RX Delay -21 -> 252, step: 4
3011 20:14:54.633714 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3012 20:14:54.636901 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3013 20:14:54.641158 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3014 20:14:54.647604 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3015 20:14:54.651069 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3016 20:14:54.654155 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3017 20:14:54.657519 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3018 20:14:54.661177 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3019 20:14:54.663809 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3020 20:14:54.670796 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3021 20:14:54.674308 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3022 20:14:54.677246 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3023 20:14:54.680627 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3024 20:14:54.684057 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3025 20:14:54.690504 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3026 20:14:54.694552 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3027 20:14:54.694630 ==
3028 20:14:54.697383 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 20:14:54.701165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 20:14:54.701265 ==
3031 20:14:54.704080 DQS Delay:
3032 20:14:54.704176 DQS0 = 0, DQS1 = 0
3033 20:14:54.704264 DQM Delay:
3034 20:14:54.708087 DQM0 = 113, DQM1 = 104
3035 20:14:54.708190 DQ Delay:
3036 20:14:54.710781 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3037 20:14:54.714239 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122
3038 20:14:54.717497 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =94
3039 20:14:54.721013 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3040 20:14:54.724153
3041 20:14:54.724250
3042 20:14:54.730787 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3043 20:14:54.734171 CH0 RK1: MR19=303, MR18=FFF1
3044 20:14:54.740729 CH0_RK1: MR19=0x303, MR18=0xFFF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3045 20:14:54.744449 [RxdqsGatingPostProcess] freq 1200
3046 20:14:54.747506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3047 20:14:54.750816 best DQS0 dly(2T, 0.5T) = (0, 12)
3048 20:14:54.754306 best DQS1 dly(2T, 0.5T) = (0, 12)
3049 20:14:54.757623 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3050 20:14:54.760521 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3051 20:14:54.763933 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 20:14:54.767663 best DQS1 dly(2T, 0.5T) = (0, 11)
3053 20:14:54.770552 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 20:14:54.774180 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3055 20:14:54.777699 Pre-setting of DQS Precalculation
3056 20:14:54.780967 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3057 20:14:54.781049 ==
3058 20:14:54.784339 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 20:14:54.787955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 20:14:54.788036 ==
3061 20:14:54.794653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3062 20:14:54.801029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3063 20:14:54.808469 [CA 0] Center 38 (9~68) winsize 60
3064 20:14:54.812512 [CA 1] Center 38 (8~68) winsize 61
3065 20:14:54.815254 [CA 2] Center 35 (6~65) winsize 60
3066 20:14:54.818740 [CA 3] Center 34 (4~65) winsize 62
3067 20:14:54.822318 [CA 4] Center 34 (4~65) winsize 62
3068 20:14:54.825477 [CA 5] Center 34 (4~64) winsize 61
3069 20:14:54.825558
3070 20:14:54.829203 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3071 20:14:54.829283
3072 20:14:54.832422 [CATrainingPosCal] consider 1 rank data
3073 20:14:54.835581 u2DelayCellTimex100 = 270/100 ps
3074 20:14:54.838818 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3075 20:14:54.842312 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3076 20:14:54.845360 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3077 20:14:54.852202 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3078 20:14:54.855535 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3079 20:14:54.859049 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3080 20:14:54.859131
3081 20:14:54.862463 CA PerBit enable=1, Macro0, CA PI delay=34
3082 20:14:54.862545
3083 20:14:54.865426 [CBTSetCACLKResult] CA Dly = 34
3084 20:14:54.865507 CS Dly: 6 (0~37)
3085 20:14:54.865571 ==
3086 20:14:54.868882 Dram Type= 6, Freq= 0, CH_1, rank 1
3087 20:14:54.875553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 20:14:54.875636 ==
3089 20:14:54.879174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 20:14:54.886228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 20:14:54.894815 [CA 0] Center 38 (8~68) winsize 61
3092 20:14:54.897504 [CA 1] Center 38 (8~68) winsize 61
3093 20:14:54.900715 [CA 2] Center 34 (4~65) winsize 62
3094 20:14:54.904294 [CA 3] Center 34 (4~65) winsize 62
3095 20:14:54.907964 [CA 4] Center 35 (5~65) winsize 61
3096 20:14:54.910992 [CA 5] Center 33 (3~64) winsize 62
3097 20:14:54.911074
3098 20:14:54.914869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 20:14:54.914975
3100 20:14:54.918057 [CATrainingPosCal] consider 2 rank data
3101 20:14:54.921447 u2DelayCellTimex100 = 270/100 ps
3102 20:14:54.924932 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3103 20:14:54.927575 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3104 20:14:54.934418 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3105 20:14:54.937871 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3106 20:14:54.941417 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3107 20:14:54.944448 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3108 20:14:54.944530
3109 20:14:54.948273 CA PerBit enable=1, Macro0, CA PI delay=34
3110 20:14:54.948354
3111 20:14:54.951153 [CBTSetCACLKResult] CA Dly = 34
3112 20:14:54.951234 CS Dly: 7 (0~40)
3113 20:14:54.951297
3114 20:14:54.956133 ----->DramcWriteLeveling(PI) begin...
3115 20:14:54.956215 ==
3116 20:14:54.957884 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 20:14:54.964394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 20:14:54.964476 ==
3119 20:14:54.967998 Write leveling (Byte 0): 28 => 28
3120 20:14:54.971461 Write leveling (Byte 1): 29 => 29
3121 20:14:54.971542 DramcWriteLeveling(PI) end<-----
3122 20:14:54.971607
3123 20:14:54.975095 ==
3124 20:14:54.978293 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 20:14:54.981599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 20:14:54.981681 ==
3127 20:14:54.984832 [Gating] SW mode calibration
3128 20:14:54.991239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3129 20:14:54.994592 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3130 20:14:55.002410 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3131 20:14:55.005026 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3132 20:14:55.008032 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 20:14:55.014915 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 20:14:55.018137 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 20:14:55.021369 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 20:14:55.024752 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3137 20:14:55.031732 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3138 20:14:55.034940 1 0 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3139 20:14:55.038619 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 20:14:55.045121 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 20:14:55.048742 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 20:14:55.052217 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 20:14:55.058705 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 20:14:55.061909 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 20:14:55.065211 1 0 28 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
3146 20:14:55.072743 1 1 0 | B1->B0 | 4242 3232 | 0 1 | (0 0) (0 0)
3147 20:14:55.075494 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 20:14:55.078499 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 20:14:55.085240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 20:14:55.088938 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 20:14:55.092575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 20:14:55.095546 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 20:14:55.102282 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3154 20:14:55.105311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3155 20:14:55.108847 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 20:14:55.115505 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 20:14:55.118596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 20:14:55.121946 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 20:14:55.128849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 20:14:55.132962 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 20:14:55.135166 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 20:14:55.141920 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 20:14:55.145958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 20:14:55.148954 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 20:14:55.156181 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 20:14:55.158810 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 20:14:55.162195 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 20:14:55.166119 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 20:14:55.172961 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3170 20:14:55.176002 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 20:14:55.179646 Total UI for P1: 0, mck2ui 16
3172 20:14:55.182440 best dqsien dly found for B0: ( 1, 3, 28)
3173 20:14:55.185957 Total UI for P1: 0, mck2ui 16
3174 20:14:55.189179 best dqsien dly found for B1: ( 1, 3, 30)
3175 20:14:55.193051 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3176 20:14:55.196176 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3177 20:14:55.196257
3178 20:14:55.199173 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3179 20:14:55.202620 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3180 20:14:55.206038 [Gating] SW calibration Done
3181 20:14:55.206119 ==
3182 20:14:55.209074 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 20:14:55.212471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 20:14:55.215969 ==
3185 20:14:55.216046 RX Vref Scan: 0
3186 20:14:55.216109
3187 20:14:55.219238 RX Vref 0 -> 0, step: 1
3188 20:14:55.219345
3189 20:14:55.219479 RX Delay -40 -> 252, step: 8
3190 20:14:55.226932 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3191 20:14:55.229608 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3192 20:14:55.232929 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3193 20:14:55.237694 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3194 20:14:55.239337 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3195 20:14:55.246319 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3196 20:14:55.249316 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3197 20:14:55.252932 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3198 20:14:55.256533 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3199 20:14:55.259898 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3200 20:14:55.263271 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3201 20:14:55.269429 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3202 20:14:55.273435 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3203 20:14:55.276267 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3204 20:14:55.279593 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3205 20:14:55.283658 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3206 20:14:55.286581 ==
3207 20:14:55.289639 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 20:14:55.293784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 20:14:55.293866 ==
3210 20:14:55.293930 DQS Delay:
3211 20:14:55.296559 DQS0 = 0, DQS1 = 0
3212 20:14:55.296640 DQM Delay:
3213 20:14:55.300503 DQM0 = 116, DQM1 = 109
3214 20:14:55.300584 DQ Delay:
3215 20:14:55.303347 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3216 20:14:55.307028 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3217 20:14:55.309976 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3218 20:14:55.313873 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3219 20:14:55.313955
3220 20:14:55.314018
3221 20:14:55.314077 ==
3222 20:14:55.316984 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 20:14:55.323486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 20:14:55.323568 ==
3225 20:14:55.323662
3226 20:14:55.323720
3227 20:14:55.323791 TX Vref Scan disable
3228 20:14:55.327608 == TX Byte 0 ==
3229 20:14:55.330137 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3230 20:14:55.333395 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3231 20:14:55.336868 == TX Byte 1 ==
3232 20:14:55.340176 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3233 20:14:55.343509 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3234 20:14:55.343590 ==
3235 20:14:55.347541 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 20:14:55.354012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 20:14:55.354093 ==
3238 20:14:55.364953 TX Vref=22, minBit 15, minWin=25, winSum=417
3239 20:14:55.367810 TX Vref=24, minBit 2, minWin=25, winSum=423
3240 20:14:55.371288 TX Vref=26, minBit 2, minWin=25, winSum=423
3241 20:14:55.374118 TX Vref=28, minBit 2, minWin=26, winSum=427
3242 20:14:55.378187 TX Vref=30, minBit 13, minWin=26, winSum=435
3243 20:14:55.384678 TX Vref=32, minBit 3, minWin=25, winSum=428
3244 20:14:55.387728 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 30
3245 20:14:55.387809
3246 20:14:55.391514 Final TX Range 1 Vref 30
3247 20:14:55.391594
3248 20:14:55.391658 ==
3249 20:14:55.394602 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 20:14:55.398232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 20:14:55.398313 ==
3252 20:14:55.398377
3253 20:14:55.401619
3254 20:14:55.401699 TX Vref Scan disable
3255 20:14:55.404484 == TX Byte 0 ==
3256 20:14:55.407785 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3257 20:14:55.411604 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3258 20:14:55.414804 == TX Byte 1 ==
3259 20:14:55.418070 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3260 20:14:55.421113 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3261 20:14:55.421209
3262 20:14:55.424906 [DATLAT]
3263 20:14:55.425002 Freq=1200, CH1 RK0
3264 20:14:55.425097
3265 20:14:55.428335 DATLAT Default: 0xd
3266 20:14:55.428414 0, 0xFFFF, sum = 0
3267 20:14:55.431199 1, 0xFFFF, sum = 0
3268 20:14:55.431281 2, 0xFFFF, sum = 0
3269 20:14:55.434599 3, 0xFFFF, sum = 0
3270 20:14:55.434696 4, 0xFFFF, sum = 0
3271 20:14:55.437988 5, 0xFFFF, sum = 0
3272 20:14:55.438070 6, 0xFFFF, sum = 0
3273 20:14:55.441096 7, 0xFFFF, sum = 0
3274 20:14:55.441178 8, 0xFFFF, sum = 0
3275 20:14:55.444688 9, 0xFFFF, sum = 0
3276 20:14:55.447992 10, 0xFFFF, sum = 0
3277 20:14:55.448074 11, 0xFFFF, sum = 0
3278 20:14:55.451296 12, 0x0, sum = 1
3279 20:14:55.451377 13, 0x0, sum = 2
3280 20:14:55.451442 14, 0x0, sum = 3
3281 20:14:55.455426 15, 0x0, sum = 4
3282 20:14:55.455508 best_step = 13
3283 20:14:55.455573
3284 20:14:55.455654 ==
3285 20:14:55.457959 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 20:14:55.464899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 20:14:55.465002 ==
3288 20:14:55.465099 RX Vref Scan: 1
3289 20:14:55.465184
3290 20:14:55.468351 Set Vref Range= 32 -> 127
3291 20:14:55.468425
3292 20:14:55.471443 RX Vref 32 -> 127, step: 1
3293 20:14:55.471530
3294 20:14:55.474713 RX Delay -21 -> 252, step: 4
3295 20:14:55.474808
3296 20:14:55.478230 Set Vref, RX VrefLevel [Byte0]: 32
3297 20:14:55.478324 [Byte1]: 32
3298 20:14:55.482896
3299 20:14:55.482975 Set Vref, RX VrefLevel [Byte0]: 33
3300 20:14:55.485952 [Byte1]: 33
3301 20:14:55.491912
3302 20:14:55.491991 Set Vref, RX VrefLevel [Byte0]: 34
3303 20:14:55.493887 [Byte1]: 34
3304 20:14:55.498793
3305 20:14:55.498883 Set Vref, RX VrefLevel [Byte0]: 35
3306 20:14:55.501834 [Byte1]: 35
3307 20:14:55.506667
3308 20:14:55.506745 Set Vref, RX VrefLevel [Byte0]: 36
3309 20:14:55.509693 [Byte1]: 36
3310 20:14:55.514790
3311 20:14:55.514868 Set Vref, RX VrefLevel [Byte0]: 37
3312 20:14:55.518392 [Byte1]: 37
3313 20:14:55.523162
3314 20:14:55.523241 Set Vref, RX VrefLevel [Byte0]: 38
3315 20:14:55.525741 [Byte1]: 38
3316 20:14:55.530122
3317 20:14:55.530205 Set Vref, RX VrefLevel [Byte0]: 39
3318 20:14:55.533948 [Byte1]: 39
3319 20:14:55.538278
3320 20:14:55.538359 Set Vref, RX VrefLevel [Byte0]: 40
3321 20:14:55.541784 [Byte1]: 40
3322 20:14:55.547225
3323 20:14:55.547304 Set Vref, RX VrefLevel [Byte0]: 41
3324 20:14:55.550274 [Byte1]: 41
3325 20:14:55.554204
3326 20:14:55.554327 Set Vref, RX VrefLevel [Byte0]: 42
3327 20:14:55.557132 [Byte1]: 42
3328 20:14:55.562525
3329 20:14:55.562605 Set Vref, RX VrefLevel [Byte0]: 43
3330 20:14:55.565556 [Byte1]: 43
3331 20:14:55.569570
3332 20:14:55.569652 Set Vref, RX VrefLevel [Byte0]: 44
3333 20:14:55.573128 [Byte1]: 44
3334 20:14:55.577454
3335 20:14:55.577572 Set Vref, RX VrefLevel [Byte0]: 45
3336 20:14:55.580791 [Byte1]: 45
3337 20:14:55.586145
3338 20:14:55.586246 Set Vref, RX VrefLevel [Byte0]: 46
3339 20:14:55.589049 [Byte1]: 46
3340 20:14:55.593790
3341 20:14:55.593887 Set Vref, RX VrefLevel [Byte0]: 47
3342 20:14:55.596921 [Byte1]: 47
3343 20:14:55.601328
3344 20:14:55.601441 Set Vref, RX VrefLevel [Byte0]: 48
3345 20:14:55.605366 [Byte1]: 48
3346 20:14:55.609168
3347 20:14:55.609275 Set Vref, RX VrefLevel [Byte0]: 49
3348 20:14:55.612869 [Byte1]: 49
3349 20:14:55.617334
3350 20:14:55.617465 Set Vref, RX VrefLevel [Byte0]: 50
3351 20:14:55.620632 [Byte1]: 50
3352 20:14:55.625291
3353 20:14:55.625378 Set Vref, RX VrefLevel [Byte0]: 51
3354 20:14:55.628886 [Byte1]: 51
3355 20:14:55.633285
3356 20:14:55.633404 Set Vref, RX VrefLevel [Byte0]: 52
3357 20:14:55.636450 [Byte1]: 52
3358 20:14:55.641179
3359 20:14:55.641296 Set Vref, RX VrefLevel [Byte0]: 53
3360 20:14:55.644567 [Byte1]: 53
3361 20:14:55.648963
3362 20:14:55.649082 Set Vref, RX VrefLevel [Byte0]: 54
3363 20:14:55.652491 [Byte1]: 54
3364 20:14:55.658187
3365 20:14:55.658303 Set Vref, RX VrefLevel [Byte0]: 55
3366 20:14:55.660455 [Byte1]: 55
3367 20:14:55.664748
3368 20:14:55.664868 Set Vref, RX VrefLevel [Byte0]: 56
3369 20:14:55.668136 [Byte1]: 56
3370 20:14:55.672641
3371 20:14:55.672757 Set Vref, RX VrefLevel [Byte0]: 57
3372 20:14:55.676109 [Byte1]: 57
3373 20:14:55.680824
3374 20:14:55.680950 Set Vref, RX VrefLevel [Byte0]: 58
3375 20:14:55.683842 [Byte1]: 58
3376 20:14:55.689003
3377 20:14:55.689079 Set Vref, RX VrefLevel [Byte0]: 59
3378 20:14:55.691846 [Byte1]: 59
3379 20:14:55.696564
3380 20:14:55.696645 Set Vref, RX VrefLevel [Byte0]: 60
3381 20:14:55.699860 [Byte1]: 60
3382 20:14:55.705130
3383 20:14:55.705251 Set Vref, RX VrefLevel [Byte0]: 61
3384 20:14:55.708098 [Byte1]: 61
3385 20:14:55.712291
3386 20:14:55.712409 Set Vref, RX VrefLevel [Byte0]: 62
3387 20:14:55.715979 [Byte1]: 62
3388 20:14:55.720032
3389 20:14:55.720157 Set Vref, RX VrefLevel [Byte0]: 63
3390 20:14:55.724777 [Byte1]: 63
3391 20:14:55.728007
3392 20:14:55.728125 Set Vref, RX VrefLevel [Byte0]: 64
3393 20:14:55.731837 [Byte1]: 64
3394 20:14:55.736001
3395 20:14:55.736121 Set Vref, RX VrefLevel [Byte0]: 65
3396 20:14:55.739497 [Byte1]: 65
3397 20:14:55.743782
3398 20:14:55.743901 Set Vref, RX VrefLevel [Byte0]: 66
3399 20:14:55.747233 [Byte1]: 66
3400 20:14:55.752212
3401 20:14:55.752332 Set Vref, RX VrefLevel [Byte0]: 67
3402 20:14:55.755098 [Byte1]: 67
3403 20:14:55.759966
3404 20:14:55.760085 Set Vref, RX VrefLevel [Byte0]: 68
3405 20:14:55.763012 [Byte1]: 68
3406 20:14:55.768305
3407 20:14:55.768424 Set Vref, RX VrefLevel [Byte0]: 69
3408 20:14:55.771196 [Byte1]: 69
3409 20:14:55.776096
3410 20:14:55.776216 Set Vref, RX VrefLevel [Byte0]: 70
3411 20:14:55.779276 [Byte1]: 70
3412 20:14:55.783969
3413 20:14:55.784089 Set Vref, RX VrefLevel [Byte0]: 71
3414 20:14:55.786760 [Byte1]: 71
3415 20:14:55.791838
3416 20:14:55.791958 Final RX Vref Byte 0 = 58 to rank0
3417 20:14:55.795674 Final RX Vref Byte 1 = 50 to rank0
3418 20:14:55.798667 Final RX Vref Byte 0 = 58 to rank1
3419 20:14:55.802126 Final RX Vref Byte 1 = 50 to rank1==
3420 20:14:55.805805 Dram Type= 6, Freq= 0, CH_1, rank 0
3421 20:14:55.808790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 20:14:55.811660 ==
3423 20:14:55.811780 DQS Delay:
3424 20:14:55.811892 DQS0 = 0, DQS1 = 0
3425 20:14:55.814901 DQM Delay:
3426 20:14:55.815021 DQM0 = 116, DQM1 = 108
3427 20:14:55.818289 DQ Delay:
3428 20:14:55.822339 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3429 20:14:55.825076 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3430 20:14:55.828850 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =104
3431 20:14:55.832000 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3432 20:14:55.832119
3433 20:14:55.832230
3434 20:14:55.838603 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3435 20:14:55.841924 CH1 RK0: MR19=303, MR18=FFE3
3436 20:14:55.848786 CH1_RK0: MR19=0x303, MR18=0xFFE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3437 20:14:55.848906
3438 20:14:55.852075 ----->DramcWriteLeveling(PI) begin...
3439 20:14:55.852195 ==
3440 20:14:55.855448 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 20:14:55.859582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 20:14:55.859664 ==
3443 20:14:55.862689 Write leveling (Byte 0): 26 => 26
3444 20:14:55.865339 Write leveling (Byte 1): 28 => 28
3445 20:14:55.868752 DramcWriteLeveling(PI) end<-----
3446 20:14:55.868871
3447 20:14:55.868980 ==
3448 20:14:55.872278 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 20:14:55.875232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 20:14:55.878617 ==
3451 20:14:55.878737 [Gating] SW mode calibration
3452 20:14:55.885292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3453 20:14:55.892176 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3454 20:14:55.895323 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 20:14:55.902519 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 20:14:55.906167 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3457 20:14:55.908956 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 20:14:55.912157 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 20:14:55.919114 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 20:14:55.922319 0 15 24 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (1 0)
3461 20:14:55.925589 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3462 20:14:55.932441 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 20:14:55.935942 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 20:14:55.939489 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 20:14:55.945790 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 20:14:55.949180 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 20:14:55.952492 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 20:14:55.959641 1 0 24 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
3469 20:14:55.962244 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3470 20:14:55.966095 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 20:14:55.972753 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 20:14:55.975595 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 20:14:55.979519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 20:14:55.986031 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 20:14:55.988976 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 20:14:55.993038 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3477 20:14:55.999434 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3478 20:14:56.002421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 20:14:56.005596 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 20:14:56.009218 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 20:14:56.015421 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 20:14:56.019513 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 20:14:56.022255 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 20:14:56.029106 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 20:14:56.032551 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 20:14:56.036041 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 20:14:56.042220 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 20:14:56.045611 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 20:14:56.050063 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 20:14:56.056074 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 20:14:56.059419 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 20:14:56.062482 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3493 20:14:56.069101 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3494 20:14:56.069208 Total UI for P1: 0, mck2ui 16
3495 20:14:56.072994 best dqsien dly found for B0: ( 1, 3, 24)
3496 20:14:56.079886 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 20:14:56.082394 Total UI for P1: 0, mck2ui 16
3498 20:14:56.085702 best dqsien dly found for B1: ( 1, 3, 28)
3499 20:14:56.089497 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3500 20:14:56.092841 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3501 20:14:56.092922
3502 20:14:56.096006 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3503 20:14:56.099253 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3504 20:14:56.102976 [Gating] SW calibration Done
3505 20:14:56.103057 ==
3506 20:14:56.106086 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 20:14:56.109232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 20:14:56.109313 ==
3509 20:14:56.113450 RX Vref Scan: 0
3510 20:14:56.113531
3511 20:14:56.113594 RX Vref 0 -> 0, step: 1
3512 20:14:56.116028
3513 20:14:56.116133 RX Delay -40 -> 252, step: 8
3514 20:14:56.122784 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3515 20:14:56.125859 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3516 20:14:56.129463 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3517 20:14:56.132910 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3518 20:14:56.136163 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3519 20:14:56.139759 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3520 20:14:56.145946 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3521 20:14:56.149557 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3522 20:14:56.152755 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3523 20:14:56.156358 iDelay=192, Bit 9, Center 99 (32 ~ 167) 136
3524 20:14:56.159326 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3525 20:14:56.165871 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3526 20:14:56.169496 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3527 20:14:56.172822 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3528 20:14:56.176219 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3529 20:14:56.179870 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3530 20:14:56.182691 ==
3531 20:14:56.187002 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 20:14:56.189487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 20:14:56.189593 ==
3534 20:14:56.189684 DQS Delay:
3535 20:14:56.192964 DQS0 = 0, DQS1 = 0
3536 20:14:56.193069 DQM Delay:
3537 20:14:56.196782 DQM0 = 113, DQM1 = 111
3538 20:14:56.196862 DQ Delay:
3539 20:14:56.199537 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3540 20:14:56.203330 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3541 20:14:56.206546 DQ8 =103, DQ9 =99, DQ10 =111, DQ11 =103
3542 20:14:56.209871 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3543 20:14:56.209951
3544 20:14:56.210015
3545 20:14:56.210073 ==
3546 20:14:56.212620 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 20:14:56.219584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 20:14:56.219665 ==
3549 20:14:56.219728
3550 20:14:56.219787
3551 20:14:56.219843 TX Vref Scan disable
3552 20:14:56.222789 == TX Byte 0 ==
3553 20:14:56.226671 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3554 20:14:56.229359 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3555 20:14:56.232898 == TX Byte 1 ==
3556 20:14:56.235947 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3557 20:14:56.239602 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3558 20:14:56.242712 ==
3559 20:14:56.246451 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 20:14:56.249223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 20:14:56.249352 ==
3562 20:14:56.261201 TX Vref=22, minBit 1, minWin=25, winSum=421
3563 20:14:56.264136 TX Vref=24, minBit 3, minWin=25, winSum=422
3564 20:14:56.267496 TX Vref=26, minBit 4, minWin=25, winSum=426
3565 20:14:56.270870 TX Vref=28, minBit 2, minWin=26, winSum=433
3566 20:14:56.273987 TX Vref=30, minBit 3, minWin=26, winSum=431
3567 20:14:56.277877 TX Vref=32, minBit 2, minWin=26, winSum=434
3568 20:14:56.284277 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3569 20:14:56.284359
3570 20:14:56.287362 Final TX Range 1 Vref 32
3571 20:14:56.287475
3572 20:14:56.287553 ==
3573 20:14:56.291164 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 20:14:56.293918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 20:14:56.293999 ==
3576 20:14:56.294062
3577 20:14:56.297502
3578 20:14:56.297582 TX Vref Scan disable
3579 20:14:56.301117 == TX Byte 0 ==
3580 20:14:56.304543 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3581 20:14:56.307510 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3582 20:14:56.310776 == TX Byte 1 ==
3583 20:14:56.314171 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 20:14:56.317503 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 20:14:56.317583
3586 20:14:56.320651 [DATLAT]
3587 20:14:56.320747 Freq=1200, CH1 RK1
3588 20:14:56.320844
3589 20:14:56.324835 DATLAT Default: 0xd
3590 20:14:56.324954 0, 0xFFFF, sum = 0
3591 20:14:56.327226 1, 0xFFFF, sum = 0
3592 20:14:56.327308 2, 0xFFFF, sum = 0
3593 20:14:56.330403 3, 0xFFFF, sum = 0
3594 20:14:56.330499 4, 0xFFFF, sum = 0
3595 20:14:56.333936 5, 0xFFFF, sum = 0
3596 20:14:56.334018 6, 0xFFFF, sum = 0
3597 20:14:56.337301 7, 0xFFFF, sum = 0
3598 20:14:56.337383 8, 0xFFFF, sum = 0
3599 20:14:56.341248 9, 0xFFFF, sum = 0
3600 20:14:56.344138 10, 0xFFFF, sum = 0
3601 20:14:56.344219 11, 0xFFFF, sum = 0
3602 20:14:56.347374 12, 0x0, sum = 1
3603 20:14:56.347455 13, 0x0, sum = 2
3604 20:14:56.347519 14, 0x0, sum = 3
3605 20:14:56.350787 15, 0x0, sum = 4
3606 20:14:56.350869 best_step = 13
3607 20:14:56.350931
3608 20:14:56.354298 ==
3609 20:14:56.354380 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 20:14:56.360743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 20:14:56.360825 ==
3612 20:14:56.360889 RX Vref Scan: 0
3613 20:14:56.360948
3614 20:14:56.364063 RX Vref 0 -> 0, step: 1
3615 20:14:56.364143
3616 20:14:56.367686 RX Delay -13 -> 252, step: 4
3617 20:14:56.370808 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3618 20:14:56.373835 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3619 20:14:56.380922 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3620 20:14:56.383887 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3621 20:14:56.387667 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3622 20:14:56.390900 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3623 20:14:56.393910 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3624 20:14:56.400935 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3625 20:14:56.404168 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3626 20:14:56.407634 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3627 20:14:56.411311 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3628 20:14:56.413812 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3629 20:14:56.421236 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3630 20:14:56.424592 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3631 20:14:56.428329 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3632 20:14:56.431314 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3633 20:14:56.431444 ==
3634 20:14:56.433892 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 20:14:56.437441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 20:14:56.441200 ==
3637 20:14:56.441322 DQS Delay:
3638 20:14:56.441431 DQS0 = 0, DQS1 = 0
3639 20:14:56.444382 DQM Delay:
3640 20:14:56.444501 DQM0 = 113, DQM1 = 109
3641 20:14:56.447702 DQ Delay:
3642 20:14:56.451123 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3643 20:14:56.454789 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3644 20:14:56.457694 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3645 20:14:56.461017 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3646 20:14:56.461126
3647 20:14:56.461190
3648 20:14:56.467818 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 414 ps
3649 20:14:56.470710 CH1 RK1: MR19=303, MR18=F6FE
3650 20:14:56.477302 CH1_RK1: MR19=0x303, MR18=0xF6FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3651 20:14:56.481104 [RxdqsGatingPostProcess] freq 1200
3652 20:14:56.487903 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3653 20:14:56.491017 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 20:14:56.491115 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 20:14:56.494169 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 20:14:56.497059 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 20:14:56.500769 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 20:14:56.504043 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 20:14:56.507670 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 20:14:56.510792 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 20:14:56.514124 Pre-setting of DQS Precalculation
3662 20:14:56.520938 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3663 20:14:56.527632 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3664 20:14:56.534086 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3665 20:14:56.534211
3666 20:14:56.534324
3667 20:14:56.537346 [Calibration Summary] 2400 Mbps
3668 20:14:56.537468 CH 0, Rank 0
3669 20:14:56.540598 SW Impedance : PASS
3670 20:14:56.544322 DUTY Scan : NO K
3671 20:14:56.544443 ZQ Calibration : PASS
3672 20:14:56.547064 Jitter Meter : NO K
3673 20:14:56.550372 CBT Training : PASS
3674 20:14:56.550517 Write leveling : PASS
3675 20:14:56.553683 RX DQS gating : PASS
3676 20:14:56.553803 RX DQ/DQS(RDDQC) : PASS
3677 20:14:56.557451 TX DQ/DQS : PASS
3678 20:14:56.560894 RX DATLAT : PASS
3679 20:14:56.561013 RX DQ/DQS(Engine): PASS
3680 20:14:56.563719 TX OE : NO K
3681 20:14:56.563842 All Pass.
3682 20:14:56.563953
3683 20:14:56.566868 CH 0, Rank 1
3684 20:14:56.566987 SW Impedance : PASS
3685 20:14:56.570547 DUTY Scan : NO K
3686 20:14:56.574130 ZQ Calibration : PASS
3687 20:14:56.574249 Jitter Meter : NO K
3688 20:14:56.577018 CBT Training : PASS
3689 20:14:56.580753 Write leveling : PASS
3690 20:14:56.580874 RX DQS gating : PASS
3691 20:14:56.584506 RX DQ/DQS(RDDQC) : PASS
3692 20:14:56.587469 TX DQ/DQS : PASS
3693 20:14:56.587592 RX DATLAT : PASS
3694 20:14:56.590594 RX DQ/DQS(Engine): PASS
3695 20:14:56.594206 TX OE : NO K
3696 20:14:56.594326 All Pass.
3697 20:14:56.594447
3698 20:14:56.594557 CH 1, Rank 0
3699 20:14:56.597289 SW Impedance : PASS
3700 20:14:56.600449 DUTY Scan : NO K
3701 20:14:56.600529 ZQ Calibration : PASS
3702 20:14:56.603762 Jitter Meter : NO K
3703 20:14:56.603842 CBT Training : PASS
3704 20:14:56.607829 Write leveling : PASS
3705 20:14:56.610454 RX DQS gating : PASS
3706 20:14:56.610535 RX DQ/DQS(RDDQC) : PASS
3707 20:14:56.613946 TX DQ/DQS : PASS
3708 20:14:56.617066 RX DATLAT : PASS
3709 20:14:56.617150 RX DQ/DQS(Engine): PASS
3710 20:14:56.620773 TX OE : NO K
3711 20:14:56.620853 All Pass.
3712 20:14:56.620934
3713 20:14:56.623782 CH 1, Rank 1
3714 20:14:56.623879 SW Impedance : PASS
3715 20:14:56.627817 DUTY Scan : NO K
3716 20:14:56.630405 ZQ Calibration : PASS
3717 20:14:56.630518 Jitter Meter : NO K
3718 20:14:56.634137 CBT Training : PASS
3719 20:14:56.637237 Write leveling : PASS
3720 20:14:56.637317 RX DQS gating : PASS
3721 20:14:56.640767 RX DQ/DQS(RDDQC) : PASS
3722 20:14:56.640847 TX DQ/DQS : PASS
3723 20:14:56.643651 RX DATLAT : PASS
3724 20:14:56.647235 RX DQ/DQS(Engine): PASS
3725 20:14:56.647315 TX OE : NO K
3726 20:14:56.650647 All Pass.
3727 20:14:56.650727
3728 20:14:56.650790 DramC Write-DBI off
3729 20:14:56.653772 PER_BANK_REFRESH: Hybrid Mode
3730 20:14:56.657029 TX_TRACKING: ON
3731 20:14:56.663756 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3732 20:14:56.667590 [FAST_K] Save calibration result to emmc
3733 20:14:56.670832 dramc_set_vcore_voltage set vcore to 650000
3734 20:14:56.674244 Read voltage for 600, 5
3735 20:14:56.674323 Vio18 = 0
3736 20:14:56.677325 Vcore = 650000
3737 20:14:56.677418 Vdram = 0
3738 20:14:56.677482 Vddq = 0
3739 20:14:56.681211 Vmddr = 0
3740 20:14:56.683770 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3741 20:14:56.690674 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3742 20:14:56.690755 MEM_TYPE=3, freq_sel=19
3743 20:14:56.694097 sv_algorithm_assistance_LP4_1600
3744 20:14:56.700794 ============ PULL DRAM RESETB DOWN ============
3745 20:14:56.703896 ========== PULL DRAM RESETB DOWN end =========
3746 20:14:56.706865 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 20:14:56.710305 ===================================
3748 20:14:56.713715 LPDDR4 DRAM CONFIGURATION
3749 20:14:56.717226 ===================================
3750 20:14:56.717306 EX_ROW_EN[0] = 0x0
3751 20:14:56.720426 EX_ROW_EN[1] = 0x0
3752 20:14:56.723891 LP4Y_EN = 0x0
3753 20:14:56.723986 WORK_FSP = 0x0
3754 20:14:56.726937 WL = 0x2
3755 20:14:56.727042 RL = 0x2
3756 20:14:56.730300 BL = 0x2
3757 20:14:56.730407 RPST = 0x0
3758 20:14:56.734304 RD_PRE = 0x0
3759 20:14:56.734386 WR_PRE = 0x1
3760 20:14:56.737109 WR_PST = 0x0
3761 20:14:56.737189 DBI_WR = 0x0
3762 20:14:56.740242 DBI_RD = 0x0
3763 20:14:56.740321 OTF = 0x1
3764 20:14:56.743595 ===================================
3765 20:14:56.747329 ===================================
3766 20:14:56.750767 ANA top config
3767 20:14:56.753865 ===================================
3768 20:14:56.753945 DLL_ASYNC_EN = 0
3769 20:14:56.757347 ALL_SLAVE_EN = 1
3770 20:14:56.760475 NEW_RANK_MODE = 1
3771 20:14:56.763935 DLL_IDLE_MODE = 1
3772 20:14:56.766992 LP45_APHY_COMB_EN = 1
3773 20:14:56.767072 TX_ODT_DIS = 1
3774 20:14:56.770792 NEW_8X_MODE = 1
3775 20:14:56.773641 ===================================
3776 20:14:56.776880 ===================================
3777 20:14:56.780617 data_rate = 1200
3778 20:14:56.784070 CKR = 1
3779 20:14:56.787131 DQ_P2S_RATIO = 8
3780 20:14:56.790483 ===================================
3781 20:14:56.790580 CA_P2S_RATIO = 8
3782 20:14:56.793544 DQ_CA_OPEN = 0
3783 20:14:56.797718 DQ_SEMI_OPEN = 0
3784 20:14:56.800522 CA_SEMI_OPEN = 0
3785 20:14:56.804398 CA_FULL_RATE = 0
3786 20:14:56.806993 DQ_CKDIV4_EN = 1
3787 20:14:56.807073 CA_CKDIV4_EN = 1
3788 20:14:56.810586 CA_PREDIV_EN = 0
3789 20:14:56.813824 PH8_DLY = 0
3790 20:14:56.817254 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3791 20:14:56.820525 DQ_AAMCK_DIV = 4
3792 20:14:56.820623 CA_AAMCK_DIV = 4
3793 20:14:56.823915 CA_ADMCK_DIV = 4
3794 20:14:56.826969 DQ_TRACK_CA_EN = 0
3795 20:14:56.830372 CA_PICK = 600
3796 20:14:56.834201 CA_MCKIO = 600
3797 20:14:56.837065 MCKIO_SEMI = 0
3798 20:14:56.840631 PLL_FREQ = 2288
3799 20:14:56.840712 DQ_UI_PI_RATIO = 32
3800 20:14:56.843754 CA_UI_PI_RATIO = 0
3801 20:14:56.847480 ===================================
3802 20:14:56.850692 ===================================
3803 20:14:56.853819 memory_type:LPDDR4
3804 20:14:56.857654 GP_NUM : 10
3805 20:14:56.857779 SRAM_EN : 1
3806 20:14:56.860431 MD32_EN : 0
3807 20:14:56.864295 ===================================
3808 20:14:56.867564 [ANA_INIT] >>>>>>>>>>>>>>
3809 20:14:56.867686 <<<<<< [CONFIGURE PHASE]: ANA_TX
3810 20:14:56.870616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3811 20:14:56.873935 ===================================
3812 20:14:56.877426 data_rate = 1200,PCW = 0X5800
3813 20:14:56.880541 ===================================
3814 20:14:56.883942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3815 20:14:56.891015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 20:14:56.897069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 20:14:56.900612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3818 20:14:56.904749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3819 20:14:56.907212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3820 20:14:56.910557 [ANA_INIT] flow start
3821 20:14:56.910679 [ANA_INIT] PLL >>>>>>>>
3822 20:14:56.914347 [ANA_INIT] PLL <<<<<<<<
3823 20:14:56.917211 [ANA_INIT] MIDPI >>>>>>>>
3824 20:14:56.917333 [ANA_INIT] MIDPI <<<<<<<<
3825 20:14:56.920696 [ANA_INIT] DLL >>>>>>>>
3826 20:14:56.923733 [ANA_INIT] flow end
3827 20:14:56.927062 ============ LP4 DIFF to SE enter ============
3828 20:14:56.930376 ============ LP4 DIFF to SE exit ============
3829 20:14:56.933736 [ANA_INIT] <<<<<<<<<<<<<
3830 20:14:56.937212 [Flow] Enable top DCM control >>>>>
3831 20:14:56.940532 [Flow] Enable top DCM control <<<<<
3832 20:14:56.943827 Enable DLL master slave shuffle
3833 20:14:56.947232 ==============================================================
3834 20:14:56.950545 Gating Mode config
3835 20:14:56.957260 ==============================================================
3836 20:14:56.957384 Config description:
3837 20:14:56.967351 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3838 20:14:56.973979 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3839 20:14:56.977378 SELPH_MODE 0: By rank 1: By Phase
3840 20:14:56.984038 ==============================================================
3841 20:14:56.987405 GAT_TRACK_EN = 1
3842 20:14:56.991574 RX_GATING_MODE = 2
3843 20:14:56.993973 RX_GATING_TRACK_MODE = 2
3844 20:14:56.997805 SELPH_MODE = 1
3845 20:14:57.000697 PICG_EARLY_EN = 1
3846 20:14:57.000768 VALID_LAT_VALUE = 1
3847 20:14:57.007091 ==============================================================
3848 20:14:57.011001 Enter into Gating configuration >>>>
3849 20:14:57.013935 Exit from Gating configuration <<<<
3850 20:14:57.018261 Enter into DVFS_PRE_config >>>>>
3851 20:14:57.026988 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3852 20:14:57.030902 Exit from DVFS_PRE_config <<<<<
3853 20:14:57.033911 Enter into PICG configuration >>>>
3854 20:14:57.037594 Exit from PICG configuration <<<<
3855 20:14:57.040666 [RX_INPUT] configuration >>>>>
3856 20:14:57.044048 [RX_INPUT] configuration <<<<<
3857 20:14:57.046983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3858 20:14:57.054099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3859 20:14:57.060671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 20:14:57.067625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 20:14:57.074436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 20:14:57.077113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 20:14:57.084022 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3864 20:14:57.087124 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3865 20:14:57.090383 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3866 20:14:57.094143 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3867 20:14:57.100359 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3868 20:14:57.104001 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 20:14:57.107748 ===================================
3870 20:14:57.110568 LPDDR4 DRAM CONFIGURATION
3871 20:14:57.114218 ===================================
3872 20:14:57.114338 EX_ROW_EN[0] = 0x0
3873 20:14:57.117726 EX_ROW_EN[1] = 0x0
3874 20:14:57.117843 LP4Y_EN = 0x0
3875 20:14:57.120483 WORK_FSP = 0x0
3876 20:14:57.120601 WL = 0x2
3877 20:14:57.124107 RL = 0x2
3878 20:14:57.124231 BL = 0x2
3879 20:14:57.127421 RPST = 0x0
3880 20:14:57.127541 RD_PRE = 0x0
3881 20:14:57.130829 WR_PRE = 0x1
3882 20:14:57.130972 WR_PST = 0x0
3883 20:14:57.133894 DBI_WR = 0x0
3884 20:14:57.134014 DBI_RD = 0x0
3885 20:14:57.137462 OTF = 0x1
3886 20:14:57.141132 ===================================
3887 20:14:57.144696 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3888 20:14:57.147500 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3889 20:14:57.154082 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 20:14:57.157962 ===================================
3891 20:14:57.158068 LPDDR4 DRAM CONFIGURATION
3892 20:14:57.160642 ===================================
3893 20:14:57.164306 EX_ROW_EN[0] = 0x10
3894 20:14:57.167755 EX_ROW_EN[1] = 0x0
3895 20:14:57.167835 LP4Y_EN = 0x0
3896 20:14:57.171752 WORK_FSP = 0x0
3897 20:14:57.171862 WL = 0x2
3898 20:14:57.173975 RL = 0x2
3899 20:14:57.174055 BL = 0x2
3900 20:14:57.177620 RPST = 0x0
3901 20:14:57.177700 RD_PRE = 0x0
3902 20:14:57.180841 WR_PRE = 0x1
3903 20:14:57.180921 WR_PST = 0x0
3904 20:14:57.184203 DBI_WR = 0x0
3905 20:14:57.184323 DBI_RD = 0x0
3906 20:14:57.187200 OTF = 0x1
3907 20:14:57.190970 ===================================
3908 20:14:57.197359 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3909 20:14:57.201300 nWR fixed to 30
3910 20:14:57.201427 [ModeRegInit_LP4] CH0 RK0
3911 20:14:57.204641 [ModeRegInit_LP4] CH0 RK1
3912 20:14:57.207781 [ModeRegInit_LP4] CH1 RK0
3913 20:14:57.210543 [ModeRegInit_LP4] CH1 RK1
3914 20:14:57.210667 match AC timing 17
3915 20:14:57.214360 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3916 20:14:57.221187 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3917 20:14:57.224074 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3918 20:14:57.227242 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3919 20:14:57.234366 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3920 20:14:57.234496 ==
3921 20:14:57.237543 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 20:14:57.240502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 20:14:57.240625 ==
3924 20:14:57.247288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 20:14:57.250859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 20:14:57.255319 [CA 0] Center 36 (6~67) winsize 62
3927 20:14:57.259283 [CA 1] Center 36 (6~66) winsize 61
3928 20:14:57.262726 [CA 2] Center 34 (4~64) winsize 61
3929 20:14:57.265375 [CA 3] Center 34 (4~64) winsize 61
3930 20:14:57.269158 [CA 4] Center 33 (3~64) winsize 62
3931 20:14:57.272005 [CA 5] Center 33 (3~64) winsize 62
3932 20:14:57.272087
3933 20:14:57.275599 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 20:14:57.275682
3935 20:14:57.278736 [CATrainingPosCal] consider 1 rank data
3936 20:14:57.282143 u2DelayCellTimex100 = 270/100 ps
3937 20:14:57.285684 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 20:14:57.289095 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3939 20:14:57.295177 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3940 20:14:57.299275 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3941 20:14:57.301940 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 20:14:57.305069 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 20:14:57.305150
3944 20:14:57.308800 CA PerBit enable=1, Macro0, CA PI delay=33
3945 20:14:57.308881
3946 20:14:57.312290 [CBTSetCACLKResult] CA Dly = 33
3947 20:14:57.312371 CS Dly: 5 (0~36)
3948 20:14:57.312435 ==
3949 20:14:57.315348 Dram Type= 6, Freq= 0, CH_0, rank 1
3950 20:14:57.322277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 20:14:57.322361 ==
3952 20:14:57.325478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 20:14:57.332586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3954 20:14:57.335722 [CA 0] Center 36 (6~66) winsize 61
3955 20:14:57.338620 [CA 1] Center 36 (6~66) winsize 61
3956 20:14:57.342313 [CA 2] Center 35 (5~65) winsize 61
3957 20:14:57.345499 [CA 3] Center 34 (4~65) winsize 62
3958 20:14:57.348604 [CA 4] Center 33 (3~64) winsize 62
3959 20:14:57.351987 [CA 5] Center 33 (3~64) winsize 62
3960 20:14:57.352137
3961 20:14:57.355403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3962 20:14:57.355484
3963 20:14:57.359571 [CATrainingPosCal] consider 2 rank data
3964 20:14:57.361934 u2DelayCellTimex100 = 270/100 ps
3965 20:14:57.365517 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3966 20:14:57.368936 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 20:14:57.375805 CA2 delay=34 (5~64),Diff = 1 PI (9 cell)
3968 20:14:57.378684 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3969 20:14:57.382849 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 20:14:57.385322 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 20:14:57.385403
3972 20:14:57.389321 CA PerBit enable=1, Macro0, CA PI delay=33
3973 20:14:57.389402
3974 20:14:57.392304 [CBTSetCACLKResult] CA Dly = 33
3975 20:14:57.392385 CS Dly: 5 (0~36)
3976 20:14:57.392449
3977 20:14:57.395607 ----->DramcWriteLeveling(PI) begin...
3978 20:14:57.399313 ==
3979 20:14:57.402317 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 20:14:57.405624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 20:14:57.405711 ==
3982 20:14:57.408497 Write leveling (Byte 0): 30 => 30
3983 20:14:57.411987 Write leveling (Byte 1): 28 => 28
3984 20:14:57.415562 DramcWriteLeveling(PI) end<-----
3985 20:14:57.415643
3986 20:14:57.415706 ==
3987 20:14:57.418859 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 20:14:57.422211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 20:14:57.422292 ==
3990 20:14:57.425458 [Gating] SW mode calibration
3991 20:14:57.432131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 20:14:57.435245 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3993 20:14:57.442388 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 20:14:57.445648 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 20:14:57.448807 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 20:14:57.455444 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 20:14:57.458900 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (1 0) (0 0)
3998 20:14:57.461817 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3999 20:14:57.468687 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 20:14:57.472048 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 20:14:57.475779 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 20:14:57.482227 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 20:14:57.485172 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 20:14:57.488917 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4005 20:14:57.495524 0 10 16 | B1->B0 | 2d2d 3d3d | 0 0 | (0 0) (0 0)
4006 20:14:57.499260 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4007 20:14:57.501859 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 20:14:57.509275 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 20:14:57.512461 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 20:14:57.515271 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 20:14:57.519119 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 20:14:57.525216 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 20:14:57.528941 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 20:14:57.532584 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 20:14:57.539402 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 20:14:57.542277 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 20:14:57.545829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 20:14:57.552367 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 20:14:57.555818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 20:14:57.558853 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 20:14:57.565731 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 20:14:57.568526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 20:14:57.571884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 20:14:57.579253 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 20:14:57.582120 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 20:14:57.585665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 20:14:57.592600 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 20:14:57.595227 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 20:14:57.598554 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4030 20:14:57.602127 Total UI for P1: 0, mck2ui 16
4031 20:14:57.605151 best dqsien dly found for B0: ( 0, 13, 14)
4032 20:14:57.609047 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4033 20:14:57.615936 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 20:14:57.618773 Total UI for P1: 0, mck2ui 16
4035 20:14:57.622172 best dqsien dly found for B1: ( 0, 13, 18)
4036 20:14:57.625184 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4037 20:14:57.628612 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4038 20:14:57.628693
4039 20:14:57.632258 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4040 20:14:57.635622 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4041 20:14:57.638744 [Gating] SW calibration Done
4042 20:14:57.638860 ==
4043 20:14:57.642236 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 20:14:57.645653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 20:14:57.645774 ==
4046 20:14:57.648778 RX Vref Scan: 0
4047 20:14:57.648897
4048 20:14:57.652204 RX Vref 0 -> 0, step: 1
4049 20:14:57.652323
4050 20:14:57.652427 RX Delay -230 -> 252, step: 16
4051 20:14:57.658771 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4052 20:14:57.662450 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4053 20:14:57.665435 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4054 20:14:57.669583 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4055 20:14:57.675511 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4056 20:14:57.679322 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4057 20:14:57.682362 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4058 20:14:57.685257 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4059 20:14:57.689013 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4060 20:14:57.695395 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4061 20:14:57.698922 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4062 20:14:57.702510 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4063 20:14:57.705065 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4064 20:14:57.712005 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4065 20:14:57.715318 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4066 20:14:57.718930 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4067 20:14:57.719051 ==
4068 20:14:57.721830 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 20:14:57.725341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 20:14:57.725462 ==
4071 20:14:57.729240 DQS Delay:
4072 20:14:57.729322 DQS0 = 0, DQS1 = 0
4073 20:14:57.731996 DQM Delay:
4074 20:14:57.732101 DQM0 = 40, DQM1 = 32
4075 20:14:57.732193 DQ Delay:
4076 20:14:57.735509 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4077 20:14:57.738742 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4078 20:14:57.742538 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4079 20:14:57.745286 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4080 20:14:57.745393
4081 20:14:57.745483
4082 20:14:57.749028 ==
4083 20:14:57.752068 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 20:14:57.755307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 20:14:57.755389 ==
4086 20:14:57.755454
4087 20:14:57.755513
4088 20:14:57.758324 TX Vref Scan disable
4089 20:14:57.758462 == TX Byte 0 ==
4090 20:14:57.765649 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4091 20:14:57.768366 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4092 20:14:57.768448 == TX Byte 1 ==
4093 20:14:57.775264 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4094 20:14:57.778593 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4095 20:14:57.778674 ==
4096 20:14:57.782113 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 20:14:57.785397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 20:14:57.785503 ==
4099 20:14:57.785582
4100 20:14:57.785641
4101 20:14:57.789657 TX Vref Scan disable
4102 20:14:57.792911 == TX Byte 0 ==
4103 20:14:57.795777 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4104 20:14:57.798405 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4105 20:14:57.801944 == TX Byte 1 ==
4106 20:14:57.804803 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4107 20:14:57.808275 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4108 20:14:57.808375
4109 20:14:57.811429 [DATLAT]
4110 20:14:57.811510 Freq=600, CH0 RK0
4111 20:14:57.811574
4112 20:14:57.814736 DATLAT Default: 0x9
4113 20:14:57.814855 0, 0xFFFF, sum = 0
4114 20:14:57.818239 1, 0xFFFF, sum = 0
4115 20:14:57.818346 2, 0xFFFF, sum = 0
4116 20:14:57.822721 3, 0xFFFF, sum = 0
4117 20:14:57.822828 4, 0xFFFF, sum = 0
4118 20:14:57.824637 5, 0xFFFF, sum = 0
4119 20:14:57.824717 6, 0xFFFF, sum = 0
4120 20:14:57.829072 7, 0xFFFF, sum = 0
4121 20:14:57.829153 8, 0x0, sum = 1
4122 20:14:57.832227 9, 0x0, sum = 2
4123 20:14:57.832313 10, 0x0, sum = 3
4124 20:14:57.835147 11, 0x0, sum = 4
4125 20:14:57.835254 best_step = 9
4126 20:14:57.835345
4127 20:14:57.835432 ==
4128 20:14:57.838439 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 20:14:57.842244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 20:14:57.845407 ==
4131 20:14:57.845487 RX Vref Scan: 1
4132 20:14:57.845552
4133 20:14:57.848412 RX Vref 0 -> 0, step: 1
4134 20:14:57.848494
4135 20:14:57.851565 RX Delay -195 -> 252, step: 8
4136 20:14:57.851646
4137 20:14:57.851710 Set Vref, RX VrefLevel [Byte0]: 54
4138 20:14:57.855392 [Byte1]: 52
4139 20:14:57.860227
4140 20:14:57.860308 Final RX Vref Byte 0 = 54 to rank0
4141 20:14:57.863526 Final RX Vref Byte 1 = 52 to rank0
4142 20:14:57.866601 Final RX Vref Byte 0 = 54 to rank1
4143 20:14:57.871158 Final RX Vref Byte 1 = 52 to rank1==
4144 20:14:57.873240 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 20:14:57.876702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 20:14:57.880916 ==
4147 20:14:57.880997 DQS Delay:
4148 20:14:57.881061 DQS0 = 0, DQS1 = 0
4149 20:14:57.883398 DQM Delay:
4150 20:14:57.883479 DQM0 = 42, DQM1 = 33
4151 20:14:57.886856 DQ Delay:
4152 20:14:57.889953 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4153 20:14:57.890034 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4154 20:14:57.897363 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4155 20:14:57.899569 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4156 20:14:57.899649
4157 20:14:57.899713
4158 20:14:57.906418 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4159 20:14:57.910299 CH0 RK0: MR19=808, MR18=3F1F
4160 20:14:57.916743 CH0_RK0: MR19=0x808, MR18=0x3F1F, DQSOSC=397, MR23=63, INC=166, DEC=110
4161 20:14:57.916825
4162 20:14:57.920010 ----->DramcWriteLeveling(PI) begin...
4163 20:14:57.920092 ==
4164 20:14:57.923472 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 20:14:57.926816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 20:14:57.926897 ==
4167 20:14:57.929802 Write leveling (Byte 0): 34 => 34
4168 20:14:57.932968 Write leveling (Byte 1): 29 => 29
4169 20:14:57.936775 DramcWriteLeveling(PI) end<-----
4170 20:14:57.936880
4171 20:14:57.936972 ==
4172 20:14:57.940110 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 20:14:57.944106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 20:14:57.944187 ==
4175 20:14:57.946796 [Gating] SW mode calibration
4176 20:14:57.953376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 20:14:57.960211 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 20:14:57.963003 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 20:14:57.966572 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 20:14:57.973032 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4181 20:14:57.976886 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
4182 20:14:57.979641 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4183 20:14:57.986323 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 20:14:57.989845 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 20:14:57.993551 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 20:14:58.000524 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 20:14:58.003444 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 20:14:58.006532 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 20:14:58.012959 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4190 20:14:58.016329 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4191 20:14:58.019889 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 20:14:58.026115 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 20:14:58.029846 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 20:14:58.032905 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 20:14:58.040132 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 20:14:58.043195 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 20:14:58.045970 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4198 20:14:58.052932 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4199 20:14:58.056175 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 20:14:58.059473 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 20:14:58.063324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 20:14:58.069727 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 20:14:58.073506 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 20:14:58.076637 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 20:14:58.083307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 20:14:58.086316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 20:14:58.089814 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 20:14:58.096541 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 20:14:58.100869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 20:14:58.103308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 20:14:58.109976 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 20:14:58.113313 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 20:14:58.116421 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4214 20:14:58.119950 Total UI for P1: 0, mck2ui 16
4215 20:14:58.123270 best dqsien dly found for B0: ( 0, 13, 10)
4216 20:14:58.130179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 20:14:58.130260 Total UI for P1: 0, mck2ui 16
4218 20:14:58.133341 best dqsien dly found for B1: ( 0, 13, 14)
4219 20:14:58.139623 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4220 20:14:58.142782 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4221 20:14:58.142863
4222 20:14:58.146133 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4223 20:14:58.149731 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4224 20:14:58.152880 [Gating] SW calibration Done
4225 20:14:58.152961 ==
4226 20:14:58.156530 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 20:14:58.159431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 20:14:58.159561 ==
4229 20:14:58.162879 RX Vref Scan: 0
4230 20:14:58.163013
4231 20:14:58.163143 RX Vref 0 -> 0, step: 1
4232 20:14:58.163236
4233 20:14:58.166590 RX Delay -230 -> 252, step: 16
4234 20:14:58.169997 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4235 20:14:58.176824 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4236 20:14:58.179611 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4237 20:14:58.183033 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4238 20:14:58.186815 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4239 20:14:58.192922 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4240 20:14:58.196239 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4241 20:14:58.199936 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4242 20:14:58.203087 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4243 20:14:58.206012 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4244 20:14:58.212816 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4245 20:14:58.216322 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4246 20:14:58.219750 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4247 20:14:58.222960 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4248 20:14:58.229472 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4249 20:14:58.232629 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4250 20:14:58.232712 ==
4251 20:14:58.237085 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 20:14:58.239701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 20:14:58.239783 ==
4254 20:14:58.242923 DQS Delay:
4255 20:14:58.243023 DQS0 = 0, DQS1 = 0
4256 20:14:58.243120 DQM Delay:
4257 20:14:58.246736 DQM0 = 40, DQM1 = 32
4258 20:14:58.246819 DQ Delay:
4259 20:14:58.249854 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4260 20:14:58.252894 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4261 20:14:58.257334 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4262 20:14:58.259746 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4263 20:14:58.259888
4264 20:14:58.259984
4265 20:14:58.260103 ==
4266 20:14:58.263162 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 20:14:58.266631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 20:14:58.269308 ==
4269 20:14:58.269403
4270 20:14:58.269495
4271 20:14:58.269582 TX Vref Scan disable
4272 20:14:58.273556 == TX Byte 0 ==
4273 20:14:58.276341 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4274 20:14:58.279495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4275 20:14:58.283185 == TX Byte 1 ==
4276 20:14:58.287140 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4277 20:14:58.290593 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4278 20:14:58.293005 ==
4279 20:14:58.296623 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 20:14:58.299770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 20:14:58.299899 ==
4282 20:14:58.300020
4283 20:14:58.300131
4284 20:14:58.303158 TX Vref Scan disable
4285 20:14:58.303288 == TX Byte 0 ==
4286 20:14:58.309947 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4287 20:14:58.312890 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4288 20:14:58.313016 == TX Byte 1 ==
4289 20:14:58.319856 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4290 20:14:58.323165 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4291 20:14:58.323292
4292 20:14:58.323409 [DATLAT]
4293 20:14:58.327695 Freq=600, CH0 RK1
4294 20:14:58.327822
4295 20:14:58.327937 DATLAT Default: 0x9
4296 20:14:58.329639 0, 0xFFFF, sum = 0
4297 20:14:58.329749 1, 0xFFFF, sum = 0
4298 20:14:58.332921 2, 0xFFFF, sum = 0
4299 20:14:58.333025 3, 0xFFFF, sum = 0
4300 20:14:58.336449 4, 0xFFFF, sum = 0
4301 20:14:58.339704 5, 0xFFFF, sum = 0
4302 20:14:58.339810 6, 0xFFFF, sum = 0
4303 20:14:58.343385 7, 0xFFFF, sum = 0
4304 20:14:58.343488 8, 0x0, sum = 1
4305 20:14:58.343586 9, 0x0, sum = 2
4306 20:14:58.346693 10, 0x0, sum = 3
4307 20:14:58.346768 11, 0x0, sum = 4
4308 20:14:58.349769 best_step = 9
4309 20:14:58.349868
4310 20:14:58.349959 ==
4311 20:14:58.353049 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 20:14:58.356864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 20:14:58.356970 ==
4314 20:14:58.359747 RX Vref Scan: 0
4315 20:14:58.359821
4316 20:14:58.359883 RX Vref 0 -> 0, step: 1
4317 20:14:58.359950
4318 20:14:58.363475 RX Delay -195 -> 252, step: 8
4319 20:14:58.370183 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4320 20:14:58.374470 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4321 20:14:58.377362 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4322 20:14:58.380723 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4323 20:14:58.386938 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4324 20:14:58.390337 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4325 20:14:58.393414 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4326 20:14:58.397136 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4327 20:14:58.400191 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4328 20:14:58.406750 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4329 20:14:58.410031 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4330 20:14:58.413691 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4331 20:14:58.416884 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4332 20:14:58.423808 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4333 20:14:58.426940 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4334 20:14:58.430295 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4335 20:14:58.430406 ==
4336 20:14:58.433737 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 20:14:58.437388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 20:14:58.437505 ==
4339 20:14:58.440382 DQS Delay:
4340 20:14:58.440485 DQS0 = 0, DQS1 = 0
4341 20:14:58.444031 DQM Delay:
4342 20:14:58.444135 DQM0 = 40, DQM1 = 33
4343 20:14:58.444228 DQ Delay:
4344 20:14:58.448206 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4345 20:14:58.451107 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4346 20:14:58.454036 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4347 20:14:58.457241 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4348 20:14:58.457339
4349 20:14:58.457432
4350 20:14:58.466838 [DQSOSCAuto] RK1, (LSB)MR18= 0x4526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4351 20:14:58.470854 CH0 RK1: MR19=808, MR18=4526
4352 20:14:58.477167 CH0_RK1: MR19=0x808, MR18=0x4526, DQSOSC=396, MR23=63, INC=167, DEC=111
4353 20:14:58.477271 [RxdqsGatingPostProcess] freq 600
4354 20:14:58.483917 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 20:14:58.487174 Pre-setting of DQS Precalculation
4356 20:14:58.490162 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 20:14:58.493511 ==
4358 20:14:58.493586 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 20:14:58.500927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 20:14:58.501028 ==
4361 20:14:58.503794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 20:14:58.510153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4363 20:14:58.514750 [CA 0] Center 35 (5~66) winsize 62
4364 20:14:58.517604 [CA 1] Center 35 (5~66) winsize 62
4365 20:14:58.520586 [CA 2] Center 34 (4~64) winsize 61
4366 20:14:58.524000 [CA 3] Center 33 (3~64) winsize 62
4367 20:14:58.527529 [CA 4] Center 34 (3~65) winsize 63
4368 20:14:58.531311 [CA 5] Center 33 (3~64) winsize 62
4369 20:14:58.531431
4370 20:14:58.533789 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4371 20:14:58.533907
4372 20:14:58.537183 [CATrainingPosCal] consider 1 rank data
4373 20:14:58.540899 u2DelayCellTimex100 = 270/100 ps
4374 20:14:58.544561 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 20:14:58.547534 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 20:14:58.551398 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4377 20:14:58.558101 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 20:14:58.560846 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4379 20:14:58.564112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4380 20:14:58.564236
4381 20:14:58.567384 CA PerBit enable=1, Macro0, CA PI delay=33
4382 20:14:58.567504
4383 20:14:58.570873 [CBTSetCACLKResult] CA Dly = 33
4384 20:14:58.570995 CS Dly: 5 (0~36)
4385 20:14:58.571104 ==
4386 20:14:58.574519 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 20:14:58.580935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 20:14:58.581057 ==
4389 20:14:58.583956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 20:14:58.591127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 20:14:58.594433 [CA 0] Center 35 (5~66) winsize 62
4392 20:14:58.597489 [CA 1] Center 35 (5~66) winsize 62
4393 20:14:58.602052 [CA 2] Center 34 (4~65) winsize 62
4394 20:14:58.604205 [CA 3] Center 34 (3~65) winsize 63
4395 20:14:58.607679 [CA 4] Center 34 (4~65) winsize 62
4396 20:14:58.610696 [CA 5] Center 33 (3~64) winsize 62
4397 20:14:58.610818
4398 20:14:58.614153 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 20:14:58.614277
4400 20:14:58.617994 [CATrainingPosCal] consider 2 rank data
4401 20:14:58.620610 u2DelayCellTimex100 = 270/100 ps
4402 20:14:58.624473 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 20:14:58.627587 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 20:14:58.630720 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4405 20:14:58.637743 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 20:14:58.640891 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 20:14:58.643864 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 20:14:58.643945
4409 20:14:58.647824 CA PerBit enable=1, Macro0, CA PI delay=33
4410 20:14:58.647904
4411 20:14:58.650592 [CBTSetCACLKResult] CA Dly = 33
4412 20:14:58.650672 CS Dly: 5 (0~37)
4413 20:14:58.650736
4414 20:14:58.654035 ----->DramcWriteLeveling(PI) begin...
4415 20:14:58.656974 ==
4416 20:14:58.660693 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 20:14:58.664266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 20:14:58.664350 ==
4419 20:14:58.667094 Write leveling (Byte 0): 30 => 30
4420 20:14:58.670845 Write leveling (Byte 1): 31 => 31
4421 20:14:58.673714 DramcWriteLeveling(PI) end<-----
4422 20:14:58.673854
4423 20:14:58.673946 ==
4424 20:14:58.677495 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 20:14:58.680760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 20:14:58.680866 ==
4427 20:14:58.684207 [Gating] SW mode calibration
4428 20:14:58.690573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 20:14:58.693740 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 20:14:58.700569 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 20:14:58.704033 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4432 20:14:58.707153 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 20:14:58.713582 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4434 20:14:58.717484 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (1 1)
4435 20:14:58.720459 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 20:14:58.726927 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 20:14:58.730307 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 20:14:58.734167 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4439 20:14:58.740577 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 20:14:58.744542 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 20:14:58.747350 0 10 12 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
4442 20:14:58.753865 0 10 16 | B1->B0 | 4040 4040 | 0 0 | (0 0) (0 0)
4443 20:14:58.756940 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 20:14:58.760619 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 20:14:58.767106 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 20:14:58.770104 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 20:14:58.773952 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 20:14:58.780805 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 20:14:58.784341 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 20:14:58.787198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4451 20:14:58.790426 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 20:14:58.797424 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 20:14:58.800884 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 20:14:58.803778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 20:14:58.810524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 20:14:58.814157 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 20:14:58.816924 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 20:14:58.823837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 20:14:58.827455 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 20:14:58.830496 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 20:14:58.836917 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 20:14:58.841138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 20:14:58.843986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 20:14:58.850930 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 20:14:58.853920 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4466 20:14:58.857169 Total UI for P1: 0, mck2ui 16
4467 20:14:58.860926 best dqsien dly found for B1: ( 0, 13, 10)
4468 20:14:58.863590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 20:14:58.867188 Total UI for P1: 0, mck2ui 16
4470 20:14:58.870742 best dqsien dly found for B0: ( 0, 13, 12)
4471 20:14:58.873911 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4472 20:14:58.877758 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4473 20:14:58.877858
4474 20:14:58.881004 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 20:14:58.887669 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4476 20:14:58.887749 [Gating] SW calibration Done
4477 20:14:58.887819 ==
4478 20:14:58.890880 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 20:14:58.897771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 20:14:58.897850 ==
4481 20:14:58.897921 RX Vref Scan: 0
4482 20:14:58.897985
4483 20:14:58.900561 RX Vref 0 -> 0, step: 1
4484 20:14:58.900639
4485 20:14:58.903786 RX Delay -230 -> 252, step: 16
4486 20:14:58.907779 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4487 20:14:58.910539 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4488 20:14:58.913974 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4489 20:14:58.920706 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4490 20:14:58.923556 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4491 20:14:58.927896 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4492 20:14:58.930290 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4493 20:14:58.937065 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4494 20:14:58.940388 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4495 20:14:58.943442 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4496 20:14:58.946839 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4497 20:14:58.953774 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4498 20:14:58.956871 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4499 20:14:58.961156 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4500 20:14:58.963862 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4501 20:14:58.967093 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4502 20:14:58.970428 ==
4503 20:14:58.974300 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 20:14:58.977216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 20:14:58.977301 ==
4506 20:14:58.977394 DQS Delay:
4507 20:14:58.980349 DQS0 = 0, DQS1 = 0
4508 20:14:58.980427 DQM Delay:
4509 20:14:58.983620 DQM0 = 45, DQM1 = 34
4510 20:14:58.983718 DQ Delay:
4511 20:14:58.986825 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4512 20:14:58.990533 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4513 20:14:58.993673 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4514 20:14:58.996970 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4515 20:14:58.997068
4516 20:14:58.997156
4517 20:14:58.997247 ==
4518 20:14:59.000455 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 20:14:59.003815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 20:14:59.003911 ==
4521 20:14:59.004000
4522 20:14:59.004085
4523 20:14:59.007233 TX Vref Scan disable
4524 20:14:59.010160 == TX Byte 0 ==
4525 20:14:59.013572 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 20:14:59.016771 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 20:14:59.020212 == TX Byte 1 ==
4528 20:14:59.023802 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4529 20:14:59.027145 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4530 20:14:59.027249 ==
4531 20:14:59.030452 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 20:14:59.033386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 20:14:59.036888 ==
4534 20:14:59.036987
4535 20:14:59.037080
4536 20:14:59.037168 TX Vref Scan disable
4537 20:14:59.040750 == TX Byte 0 ==
4538 20:14:59.044270 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 20:14:59.047449 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 20:14:59.050929 == TX Byte 1 ==
4541 20:14:59.054541 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4542 20:14:59.057293 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4543 20:14:59.060727
4544 20:14:59.060808 [DATLAT]
4545 20:14:59.060873 Freq=600, CH1 RK0
4546 20:14:59.060932
4547 20:14:59.065150 DATLAT Default: 0x9
4548 20:14:59.065223 0, 0xFFFF, sum = 0
4549 20:14:59.067608 1, 0xFFFF, sum = 0
4550 20:14:59.067685 2, 0xFFFF, sum = 0
4551 20:14:59.071192 3, 0xFFFF, sum = 0
4552 20:14:59.071271 4, 0xFFFF, sum = 0
4553 20:14:59.074525 5, 0xFFFF, sum = 0
4554 20:14:59.074600 6, 0xFFFF, sum = 0
4555 20:14:59.077462 7, 0xFFFF, sum = 0
4556 20:14:59.077549 8, 0x0, sum = 1
4557 20:14:59.081114 9, 0x0, sum = 2
4558 20:14:59.081191 10, 0x0, sum = 3
4559 20:14:59.084651 11, 0x0, sum = 4
4560 20:14:59.084728 best_step = 9
4561 20:14:59.084791
4562 20:14:59.084857 ==
4563 20:14:59.087512 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 20:14:59.094136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 20:14:59.094214 ==
4566 20:14:59.094285 RX Vref Scan: 1
4567 20:14:59.094345
4568 20:14:59.098360 RX Vref 0 -> 0, step: 1
4569 20:14:59.098493
4570 20:14:59.101153 RX Delay -195 -> 252, step: 8
4571 20:14:59.101232
4572 20:14:59.104230 Set Vref, RX VrefLevel [Byte0]: 58
4573 20:14:59.107717 [Byte1]: 50
4574 20:14:59.107791
4575 20:14:59.111026 Final RX Vref Byte 0 = 58 to rank0
4576 20:14:59.114274 Final RX Vref Byte 1 = 50 to rank0
4577 20:14:59.117956 Final RX Vref Byte 0 = 58 to rank1
4578 20:14:59.120511 Final RX Vref Byte 1 = 50 to rank1==
4579 20:14:59.124182 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 20:14:59.127615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 20:14:59.127697 ==
4582 20:14:59.130657 DQS Delay:
4583 20:14:59.130815 DQS0 = 0, DQS1 = 0
4584 20:14:59.130920 DQM Delay:
4585 20:14:59.134305 DQM0 = 40, DQM1 = 32
4586 20:14:59.134423 DQ Delay:
4587 20:14:59.137527 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4588 20:14:59.140765 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4589 20:14:59.144117 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4590 20:14:59.147333 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4591 20:14:59.147428
4592 20:14:59.147517
4593 20:14:59.157865 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4594 20:14:59.157942 CH1 RK0: MR19=808, MR18=3E04
4595 20:14:59.164130 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4596 20:14:59.164228
4597 20:14:59.167825 ----->DramcWriteLeveling(PI) begin...
4598 20:14:59.167921 ==
4599 20:14:59.170914 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 20:14:59.177601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 20:14:59.177700 ==
4602 20:14:59.180748 Write leveling (Byte 0): 29 => 29
4603 20:14:59.184694 Write leveling (Byte 1): 29 => 29
4604 20:14:59.184788 DramcWriteLeveling(PI) end<-----
4605 20:14:59.187721
4606 20:14:59.187815 ==
4607 20:14:59.190723 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 20:14:59.194123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 20:14:59.194236 ==
4610 20:14:59.197497 [Gating] SW mode calibration
4611 20:14:59.205042 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 20:14:59.207751 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 20:14:59.214993 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4614 20:14:59.217479 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 20:14:59.220701 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4616 20:14:59.227543 0 9 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4617 20:14:59.230726 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4618 20:14:59.234146 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4619 20:14:59.241101 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 20:14:59.243804 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4621 20:14:59.247848 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 20:14:59.254501 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 20:14:59.257909 0 10 8 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4624 20:14:59.260671 0 10 12 | B1->B0 | 3131 3a3a | 0 1 | (0 0) (0 0)
4625 20:14:59.267820 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4626 20:14:59.271107 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 20:14:59.274196 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 20:14:59.277518 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 20:14:59.284268 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 20:14:59.288673 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 20:14:59.291207 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 20:14:59.297464 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4633 20:14:59.300746 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 20:14:59.304289 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 20:14:59.311345 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 20:14:59.314647 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 20:14:59.318511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 20:14:59.324222 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 20:14:59.327542 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 20:14:59.331574 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 20:14:59.337721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 20:14:59.341068 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 20:14:59.343953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 20:14:59.350821 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 20:14:59.355068 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 20:14:59.357231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 20:14:59.363829 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4648 20:14:59.368234 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4649 20:14:59.371029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 20:14:59.374591 Total UI for P1: 0, mck2ui 16
4651 20:14:59.377932 best dqsien dly found for B0: ( 0, 13, 10)
4652 20:14:59.381296 Total UI for P1: 0, mck2ui 16
4653 20:14:59.384329 best dqsien dly found for B1: ( 0, 13, 14)
4654 20:14:59.387328 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4655 20:14:59.390880 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4656 20:14:59.390948
4657 20:14:59.393992 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4658 20:14:59.400723 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4659 20:14:59.400845 [Gating] SW calibration Done
4660 20:14:59.400958 ==
4661 20:14:59.404087 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 20:14:59.411459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 20:14:59.411583 ==
4664 20:14:59.411699 RX Vref Scan: 0
4665 20:14:59.411804
4666 20:14:59.414789 RX Vref 0 -> 0, step: 1
4667 20:14:59.414912
4668 20:14:59.418010 RX Delay -230 -> 252, step: 16
4669 20:14:59.421031 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4670 20:14:59.424656 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4671 20:14:59.428138 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4672 20:14:59.434262 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4673 20:14:59.437479 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4674 20:14:59.441025 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4675 20:14:59.444108 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4676 20:14:59.447888 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4677 20:14:59.454142 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4678 20:14:59.457350 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4679 20:14:59.461620 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4680 20:14:59.464374 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4681 20:14:59.470685 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4682 20:14:59.474379 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4683 20:14:59.477642 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4684 20:14:59.481191 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4685 20:14:59.481315 ==
4686 20:14:59.484693 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 20:14:59.490811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 20:14:59.490936 ==
4689 20:14:59.491048 DQS Delay:
4690 20:14:59.494530 DQS0 = 0, DQS1 = 0
4691 20:14:59.494651 DQM Delay:
4692 20:14:59.494760 DQM0 = 39, DQM1 = 34
4693 20:14:59.497559 DQ Delay:
4694 20:14:59.501142 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4695 20:14:59.504190 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4696 20:14:59.507722 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4697 20:14:59.511259 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4698 20:14:59.511378
4699 20:14:59.511485
4700 20:14:59.511594 ==
4701 20:14:59.514274 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 20:14:59.517864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 20:14:59.517985 ==
4704 20:14:59.518091
4705 20:14:59.518197
4706 20:14:59.520526 TX Vref Scan disable
4707 20:14:59.524080 == TX Byte 0 ==
4708 20:14:59.527739 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4709 20:14:59.531187 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4710 20:14:59.534249 == TX Byte 1 ==
4711 20:14:59.537592 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4712 20:14:59.540664 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4713 20:14:59.540784 ==
4714 20:14:59.543962 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 20:14:59.547532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 20:14:59.550271 ==
4717 20:14:59.550385
4718 20:14:59.550538
4719 20:14:59.550647 TX Vref Scan disable
4720 20:14:59.553965 == TX Byte 0 ==
4721 20:14:59.557739 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4722 20:14:59.560786 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4723 20:14:59.564138 == TX Byte 1 ==
4724 20:14:59.567587 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4725 20:14:59.570778 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4726 20:14:59.574617
4727 20:14:59.574737 [DATLAT]
4728 20:14:59.574846 Freq=600, CH1 RK1
4729 20:14:59.574958
4730 20:14:59.577720 DATLAT Default: 0x9
4731 20:14:59.577836 0, 0xFFFF, sum = 0
4732 20:14:59.581025 1, 0xFFFF, sum = 0
4733 20:14:59.581148 2, 0xFFFF, sum = 0
4734 20:14:59.584214 3, 0xFFFF, sum = 0
4735 20:14:59.584335 4, 0xFFFF, sum = 0
4736 20:14:59.587945 5, 0xFFFF, sum = 0
4737 20:14:59.588067 6, 0xFFFF, sum = 0
4738 20:14:59.590814 7, 0xFFFF, sum = 0
4739 20:14:59.590937 8, 0x0, sum = 1
4740 20:14:59.594012 9, 0x0, sum = 2
4741 20:14:59.594116 10, 0x0, sum = 3
4742 20:14:59.597428 11, 0x0, sum = 4
4743 20:14:59.597502 best_step = 9
4744 20:14:59.597563
4745 20:14:59.597653 ==
4746 20:14:59.601351 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 20:14:59.607682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 20:14:59.607782 ==
4749 20:14:59.607875 RX Vref Scan: 0
4750 20:14:59.607963
4751 20:14:59.610975 RX Vref 0 -> 0, step: 1
4752 20:14:59.611075
4753 20:14:59.614688 RX Delay -195 -> 252, step: 8
4754 20:14:59.618113 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4755 20:14:59.624487 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4756 20:14:59.627503 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4757 20:14:59.631193 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4758 20:14:59.634930 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4759 20:14:59.637815 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4760 20:14:59.644304 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4761 20:14:59.647548 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4762 20:14:59.651430 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4763 20:14:59.654447 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4764 20:14:59.657814 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4765 20:14:59.664741 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4766 20:14:59.668021 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4767 20:14:59.671082 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4768 20:14:59.674519 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4769 20:14:59.680936 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4770 20:14:59.681059 ==
4771 20:14:59.684413 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 20:14:59.687797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 20:14:59.687916 ==
4774 20:14:59.688031 DQS Delay:
4775 20:14:59.691420 DQS0 = 0, DQS1 = 0
4776 20:14:59.691524 DQM Delay:
4777 20:14:59.695157 DQM0 = 38, DQM1 = 33
4778 20:14:59.695256 DQ Delay:
4779 20:14:59.697527 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4780 20:14:59.701213 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4781 20:14:59.704961 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4782 20:14:59.707749 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4783 20:14:59.707844
4784 20:14:59.707933
4785 20:14:59.714596 [DQSOSCAuto] RK1, (LSB)MR18= 0x313f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4786 20:14:59.717725 CH1 RK1: MR19=808, MR18=313F
4787 20:14:59.724616 CH1_RK1: MR19=0x808, MR18=0x313F, DQSOSC=397, MR23=63, INC=166, DEC=110
4788 20:14:59.728215 [RxdqsGatingPostProcess] freq 600
4789 20:14:59.734557 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4790 20:14:59.738560 Pre-setting of DQS Precalculation
4791 20:14:59.741811 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4792 20:14:59.748156 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4793 20:14:59.754745 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4794 20:14:59.754820
4795 20:14:59.754904
4796 20:14:59.758296 [Calibration Summary] 1200 Mbps
4797 20:14:59.760889 CH 0, Rank 0
4798 20:14:59.760988 SW Impedance : PASS
4799 20:14:59.764203 DUTY Scan : NO K
4800 20:14:59.767784 ZQ Calibration : PASS
4801 20:14:59.767858 Jitter Meter : NO K
4802 20:14:59.770964 CBT Training : PASS
4803 20:14:59.771035 Write leveling : PASS
4804 20:14:59.774872 RX DQS gating : PASS
4805 20:14:59.777519 RX DQ/DQS(RDDQC) : PASS
4806 20:14:59.777624 TX DQ/DQS : PASS
4807 20:14:59.781298 RX DATLAT : PASS
4808 20:14:59.784456 RX DQ/DQS(Engine): PASS
4809 20:14:59.784557 TX OE : NO K
4810 20:14:59.787844 All Pass.
4811 20:14:59.787942
4812 20:14:59.788043 CH 0, Rank 1
4813 20:14:59.791316 SW Impedance : PASS
4814 20:14:59.791433 DUTY Scan : NO K
4815 20:14:59.794465 ZQ Calibration : PASS
4816 20:14:59.797561 Jitter Meter : NO K
4817 20:14:59.797681 CBT Training : PASS
4818 20:14:59.801274 Write leveling : PASS
4819 20:14:59.804400 RX DQS gating : PASS
4820 20:14:59.804521 RX DQ/DQS(RDDQC) : PASS
4821 20:14:59.807860 TX DQ/DQS : PASS
4822 20:14:59.811102 RX DATLAT : PASS
4823 20:14:59.811221 RX DQ/DQS(Engine): PASS
4824 20:14:59.814798 TX OE : NO K
4825 20:14:59.814919 All Pass.
4826 20:14:59.815031
4827 20:14:59.817981 CH 1, Rank 0
4828 20:14:59.818098 SW Impedance : PASS
4829 20:14:59.821191 DUTY Scan : NO K
4830 20:14:59.821294 ZQ Calibration : PASS
4831 20:14:59.824587 Jitter Meter : NO K
4832 20:14:59.827936 CBT Training : PASS
4833 20:14:59.828037 Write leveling : PASS
4834 20:14:59.831244 RX DQS gating : PASS
4835 20:14:59.834164 RX DQ/DQS(RDDQC) : PASS
4836 20:14:59.834266 TX DQ/DQS : PASS
4837 20:14:59.837521 RX DATLAT : PASS
4838 20:14:59.841892 RX DQ/DQS(Engine): PASS
4839 20:14:59.841991 TX OE : NO K
4840 20:14:59.844698 All Pass.
4841 20:14:59.844797
4842 20:14:59.844886 CH 1, Rank 1
4843 20:14:59.848260 SW Impedance : PASS
4844 20:14:59.848361 DUTY Scan : NO K
4845 20:14:59.851513 ZQ Calibration : PASS
4846 20:14:59.854386 Jitter Meter : NO K
4847 20:14:59.854526 CBT Training : PASS
4848 20:14:59.857647 Write leveling : PASS
4849 20:14:59.857722 RX DQS gating : PASS
4850 20:14:59.860975 RX DQ/DQS(RDDQC) : PASS
4851 20:14:59.864333 TX DQ/DQS : PASS
4852 20:14:59.864432 RX DATLAT : PASS
4853 20:14:59.868402 RX DQ/DQS(Engine): PASS
4854 20:14:59.871346 TX OE : NO K
4855 20:14:59.871428 All Pass.
4856 20:14:59.871491
4857 20:14:59.874282 DramC Write-DBI off
4858 20:14:59.874364 PER_BANK_REFRESH: Hybrid Mode
4859 20:14:59.877804 TX_TRACKING: ON
4860 20:14:59.884137 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4861 20:14:59.891249 [FAST_K] Save calibration result to emmc
4862 20:14:59.894328 dramc_set_vcore_voltage set vcore to 662500
4863 20:14:59.894452 Read voltage for 933, 3
4864 20:14:59.897702 Vio18 = 0
4865 20:14:59.897782 Vcore = 662500
4866 20:14:59.897881 Vdram = 0
4867 20:14:59.901478 Vddq = 0
4868 20:14:59.901557 Vmddr = 0
4869 20:14:59.904803 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4870 20:14:59.910751 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4871 20:14:59.914726 MEM_TYPE=3, freq_sel=17
4872 20:14:59.917750 sv_algorithm_assistance_LP4_1600
4873 20:14:59.921028 ============ PULL DRAM RESETB DOWN ============
4874 20:14:59.924461 ========== PULL DRAM RESETB DOWN end =========
4875 20:14:59.931004 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 20:14:59.934783 ===================================
4877 20:14:59.934865 LPDDR4 DRAM CONFIGURATION
4878 20:14:59.937417 ===================================
4879 20:14:59.940635 EX_ROW_EN[0] = 0x0
4880 20:14:59.940714 EX_ROW_EN[1] = 0x0
4881 20:14:59.944065 LP4Y_EN = 0x0
4882 20:14:59.944172 WORK_FSP = 0x0
4883 20:14:59.947648 WL = 0x3
4884 20:14:59.947750 RL = 0x3
4885 20:14:59.950680 BL = 0x2
4886 20:14:59.950782 RPST = 0x0
4887 20:14:59.955216 RD_PRE = 0x0
4888 20:14:59.957904 WR_PRE = 0x1
4889 20:14:59.958000 WR_PST = 0x0
4890 20:14:59.960995 DBI_WR = 0x0
4891 20:14:59.961094 DBI_RD = 0x0
4892 20:14:59.964389 OTF = 0x1
4893 20:14:59.967355 ===================================
4894 20:14:59.970890 ===================================
4895 20:14:59.970989 ANA top config
4896 20:14:59.974842 ===================================
4897 20:14:59.977372 DLL_ASYNC_EN = 0
4898 20:14:59.980743 ALL_SLAVE_EN = 1
4899 20:14:59.980824 NEW_RANK_MODE = 1
4900 20:14:59.984949 DLL_IDLE_MODE = 1
4901 20:14:59.987599 LP45_APHY_COMB_EN = 1
4902 20:14:59.990875 TX_ODT_DIS = 1
4903 20:14:59.990955 NEW_8X_MODE = 1
4904 20:14:59.994177 ===================================
4905 20:14:59.997340 ===================================
4906 20:15:00.001280 data_rate = 1866
4907 20:15:00.004412 CKR = 1
4908 20:15:00.007934 DQ_P2S_RATIO = 8
4909 20:15:00.011397 ===================================
4910 20:15:00.014911 CA_P2S_RATIO = 8
4911 20:15:00.017656 DQ_CA_OPEN = 0
4912 20:15:00.017738 DQ_SEMI_OPEN = 0
4913 20:15:00.021241 CA_SEMI_OPEN = 0
4914 20:15:00.024154 CA_FULL_RATE = 0
4915 20:15:00.027801 DQ_CKDIV4_EN = 1
4916 20:15:00.031292 CA_CKDIV4_EN = 1
4917 20:15:00.031373 CA_PREDIV_EN = 0
4918 20:15:00.034588 PH8_DLY = 0
4919 20:15:00.037682 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4920 20:15:00.041207 DQ_AAMCK_DIV = 4
4921 20:15:00.044855 CA_AAMCK_DIV = 4
4922 20:15:00.047540 CA_ADMCK_DIV = 4
4923 20:15:00.047624 DQ_TRACK_CA_EN = 0
4924 20:15:00.050751 CA_PICK = 933
4925 20:15:00.054148 CA_MCKIO = 933
4926 20:15:00.057484 MCKIO_SEMI = 0
4927 20:15:00.062098 PLL_FREQ = 3732
4928 20:15:00.064806 DQ_UI_PI_RATIO = 32
4929 20:15:00.068461 CA_UI_PI_RATIO = 0
4930 20:15:00.070825 ===================================
4931 20:15:00.074197 ===================================
4932 20:15:00.074273 memory_type:LPDDR4
4933 20:15:00.077680 GP_NUM : 10
4934 20:15:00.080746 SRAM_EN : 1
4935 20:15:00.080845 MD32_EN : 0
4936 20:15:00.084454 ===================================
4937 20:15:00.087938 [ANA_INIT] >>>>>>>>>>>>>>
4938 20:15:00.090784 <<<<<< [CONFIGURE PHASE]: ANA_TX
4939 20:15:00.094388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4940 20:15:00.097870 ===================================
4941 20:15:00.101431 data_rate = 1866,PCW = 0X8f00
4942 20:15:00.104375 ===================================
4943 20:15:00.107567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4944 20:15:00.111231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 20:15:00.117781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 20:15:00.121137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4947 20:15:00.124299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4948 20:15:00.128028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4949 20:15:00.130662 [ANA_INIT] flow start
4950 20:15:00.134327 [ANA_INIT] PLL >>>>>>>>
4951 20:15:00.134433 [ANA_INIT] PLL <<<<<<<<
4952 20:15:00.137758 [ANA_INIT] MIDPI >>>>>>>>
4953 20:15:00.141222 [ANA_INIT] MIDPI <<<<<<<<
4954 20:15:00.141304 [ANA_INIT] DLL >>>>>>>>
4955 20:15:00.144936 [ANA_INIT] flow end
4956 20:15:00.147876 ============ LP4 DIFF to SE enter ============
4957 20:15:00.150700 ============ LP4 DIFF to SE exit ============
4958 20:15:00.154307 [ANA_INIT] <<<<<<<<<<<<<
4959 20:15:00.157361 [Flow] Enable top DCM control >>>>>
4960 20:15:00.160756 [Flow] Enable top DCM control <<<<<
4961 20:15:00.164133 Enable DLL master slave shuffle
4962 20:15:00.171304 ==============================================================
4963 20:15:00.171387 Gating Mode config
4964 20:15:00.177975 ==============================================================
4965 20:15:00.178056 Config description:
4966 20:15:00.187688 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4967 20:15:00.194291 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4968 20:15:00.201678 SELPH_MODE 0: By rank 1: By Phase
4969 20:15:00.204572 ==============================================================
4970 20:15:00.207687 GAT_TRACK_EN = 1
4971 20:15:00.211184 RX_GATING_MODE = 2
4972 20:15:00.214204 RX_GATING_TRACK_MODE = 2
4973 20:15:00.217513 SELPH_MODE = 1
4974 20:15:00.221625 PICG_EARLY_EN = 1
4975 20:15:00.224290 VALID_LAT_VALUE = 1
4976 20:15:00.228064 ==============================================================
4977 20:15:00.231401 Enter into Gating configuration >>>>
4978 20:15:00.234789 Exit from Gating configuration <<<<
4979 20:15:00.237834 Enter into DVFS_PRE_config >>>>>
4980 20:15:00.251050 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4981 20:15:00.254253 Exit from DVFS_PRE_config <<<<<
4982 20:15:00.257850 Enter into PICG configuration >>>>
4983 20:15:00.257949 Exit from PICG configuration <<<<
4984 20:15:00.261222 [RX_INPUT] configuration >>>>>
4985 20:15:00.264652 [RX_INPUT] configuration <<<<<
4986 20:15:00.271009 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4987 20:15:00.274707 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4988 20:15:00.281564 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 20:15:00.288337 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 20:15:00.294915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 20:15:00.301730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 20:15:00.305040 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4993 20:15:00.308111 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4994 20:15:00.311770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4995 20:15:00.318620 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4996 20:15:00.321630 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4997 20:15:00.324707 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 20:15:00.328130 ===================================
4999 20:15:00.331563 LPDDR4 DRAM CONFIGURATION
5000 20:15:00.334777 ===================================
5001 20:15:00.334860 EX_ROW_EN[0] = 0x0
5002 20:15:00.337974 EX_ROW_EN[1] = 0x0
5003 20:15:00.341290 LP4Y_EN = 0x0
5004 20:15:00.341373 WORK_FSP = 0x0
5005 20:15:00.344821 WL = 0x3
5006 20:15:00.344904 RL = 0x3
5007 20:15:00.348300 BL = 0x2
5008 20:15:00.348383 RPST = 0x0
5009 20:15:00.351917 RD_PRE = 0x0
5010 20:15:00.352000 WR_PRE = 0x1
5011 20:15:00.354860 WR_PST = 0x0
5012 20:15:00.354967 DBI_WR = 0x0
5013 20:15:00.358102 DBI_RD = 0x0
5014 20:15:00.358185 OTF = 0x1
5015 20:15:00.361266 ===================================
5016 20:15:00.364700 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5017 20:15:00.371485 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5018 20:15:00.375136 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 20:15:00.378105 ===================================
5020 20:15:00.381286 LPDDR4 DRAM CONFIGURATION
5021 20:15:00.384945 ===================================
5022 20:15:00.385040 EX_ROW_EN[0] = 0x10
5023 20:15:00.388087 EX_ROW_EN[1] = 0x0
5024 20:15:00.388159 LP4Y_EN = 0x0
5025 20:15:00.391811 WORK_FSP = 0x0
5026 20:15:00.391924 WL = 0x3
5027 20:15:00.395220 RL = 0x3
5028 20:15:00.395340 BL = 0x2
5029 20:15:00.398252 RPST = 0x0
5030 20:15:00.398367 RD_PRE = 0x0
5031 20:15:00.401555 WR_PRE = 0x1
5032 20:15:00.401713 WR_PST = 0x0
5033 20:15:00.405031 DBI_WR = 0x0
5034 20:15:00.405133 DBI_RD = 0x0
5035 20:15:00.408690 OTF = 0x1
5036 20:15:00.411814 ===================================
5037 20:15:00.418308 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5038 20:15:00.421900 nWR fixed to 30
5039 20:15:00.424817 [ModeRegInit_LP4] CH0 RK0
5040 20:15:00.424902 [ModeRegInit_LP4] CH0 RK1
5041 20:15:00.428294 [ModeRegInit_LP4] CH1 RK0
5042 20:15:00.432009 [ModeRegInit_LP4] CH1 RK1
5043 20:15:00.432093 match AC timing 9
5044 20:15:00.438242 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5045 20:15:00.441586 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5046 20:15:00.445215 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5047 20:15:00.452257 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5048 20:15:00.455232 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5049 20:15:00.455311 ==
5050 20:15:00.458681 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 20:15:00.461975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 20:15:00.462055 ==
5053 20:15:00.468818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 20:15:00.475255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5055 20:15:00.478219 [CA 0] Center 38 (7~69) winsize 63
5056 20:15:00.481676 [CA 1] Center 38 (7~69) winsize 63
5057 20:15:00.485261 [CA 2] Center 35 (5~66) winsize 62
5058 20:15:00.488200 [CA 3] Center 35 (5~66) winsize 62
5059 20:15:00.492061 [CA 4] Center 34 (4~64) winsize 61
5060 20:15:00.495294 [CA 5] Center 33 (3~64) winsize 62
5061 20:15:00.495375
5062 20:15:00.498355 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5063 20:15:00.498484
5064 20:15:00.501695 [CATrainingPosCal] consider 1 rank data
5065 20:15:00.505154 u2DelayCellTimex100 = 270/100 ps
5066 20:15:00.508579 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5067 20:15:00.511827 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5068 20:15:00.515205 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5069 20:15:00.519199 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5070 20:15:00.521651 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5071 20:15:00.525187 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5072 20:15:00.525270
5073 20:15:00.531640 CA PerBit enable=1, Macro0, CA PI delay=33
5074 20:15:00.531747
5075 20:15:00.531846 [CBTSetCACLKResult] CA Dly = 33
5076 20:15:00.535312 CS Dly: 6 (0~37)
5077 20:15:00.535394 ==
5078 20:15:00.538466 Dram Type= 6, Freq= 0, CH_0, rank 1
5079 20:15:00.542005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 20:15:00.542088 ==
5081 20:15:00.548504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 20:15:00.555264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 20:15:00.558665 [CA 0] Center 38 (8~69) winsize 62
5084 20:15:00.562148 [CA 1] Center 38 (8~69) winsize 62
5085 20:15:00.565200 [CA 2] Center 35 (5~66) winsize 62
5086 20:15:00.568170 [CA 3] Center 35 (4~66) winsize 63
5087 20:15:00.572168 [CA 4] Center 34 (3~65) winsize 63
5088 20:15:00.575161 [CA 5] Center 33 (3~64) winsize 62
5089 20:15:00.575244
5090 20:15:00.578681 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 20:15:00.578764
5092 20:15:00.581571 [CATrainingPosCal] consider 2 rank data
5093 20:15:00.585513 u2DelayCellTimex100 = 270/100 ps
5094 20:15:00.588282 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5095 20:15:00.591680 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5096 20:15:00.594828 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5097 20:15:00.598591 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5098 20:15:00.601902 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5099 20:15:00.605224 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5100 20:15:00.605303
5101 20:15:00.611741 CA PerBit enable=1, Macro0, CA PI delay=33
5102 20:15:00.611821
5103 20:15:00.611883 [CBTSetCACLKResult] CA Dly = 33
5104 20:15:00.615431 CS Dly: 7 (0~39)
5105 20:15:00.615510
5106 20:15:00.619305 ----->DramcWriteLeveling(PI) begin...
5107 20:15:00.619391 ==
5108 20:15:00.622046 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 20:15:00.625154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 20:15:00.625234 ==
5111 20:15:00.628336 Write leveling (Byte 0): 32 => 32
5112 20:15:00.631591 Write leveling (Byte 1): 25 => 25
5113 20:15:00.635244 DramcWriteLeveling(PI) end<-----
5114 20:15:00.635323
5115 20:15:00.635387 ==
5116 20:15:00.638780 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 20:15:00.642078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 20:15:00.645471 ==
5119 20:15:00.645550 [Gating] SW mode calibration
5120 20:15:00.652153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5121 20:15:00.658407 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5122 20:15:00.662858 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5123 20:15:00.669163 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5124 20:15:00.672367 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 20:15:00.675096 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 20:15:00.682262 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 20:15:00.684958 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 20:15:00.688238 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5129 20:15:00.695860 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5130 20:15:00.698361 0 15 0 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
5131 20:15:00.701637 0 15 4 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
5132 20:15:00.708831 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 20:15:00.711871 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 20:15:00.715150 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 20:15:00.721851 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 20:15:00.725110 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 20:15:00.728597 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5138 20:15:00.731911 1 0 0 | B1->B0 | 2e2e 3c3c | 1 0 | (0 0) (0 0)
5139 20:15:00.738177 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 20:15:00.742149 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 20:15:00.745142 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 20:15:00.751950 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 20:15:00.755130 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 20:15:00.758246 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 20:15:00.764816 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 20:15:00.768450 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5147 20:15:00.771883 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5148 20:15:00.778763 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 20:15:00.781747 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 20:15:00.785409 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 20:15:00.791823 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 20:15:00.795473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 20:15:00.798192 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 20:15:00.805674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 20:15:00.808822 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 20:15:00.811927 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 20:15:00.815611 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 20:15:00.821981 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 20:15:00.825037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 20:15:00.828988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 20:15:00.835492 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 20:15:00.838369 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5163 20:15:00.842349 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5164 20:15:00.845202 Total UI for P1: 0, mck2ui 16
5165 20:15:00.848720 best dqsien dly found for B0: ( 1, 3, 0)
5166 20:15:00.855179 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 20:15:00.855260 Total UI for P1: 0, mck2ui 16
5168 20:15:00.861825 best dqsien dly found for B1: ( 1, 3, 2)
5169 20:15:00.865289 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5170 20:15:00.869126 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5171 20:15:00.869206
5172 20:15:00.871813 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5173 20:15:00.875334 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5174 20:15:00.879024 [Gating] SW calibration Done
5175 20:15:00.879106 ==
5176 20:15:00.882127 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 20:15:00.885106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 20:15:00.885187 ==
5179 20:15:00.889438 RX Vref Scan: 0
5180 20:15:00.889520
5181 20:15:00.889585 RX Vref 0 -> 0, step: 1
5182 20:15:00.889644
5183 20:15:00.891742 RX Delay -80 -> 252, step: 8
5184 20:15:00.895432 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5185 20:15:00.898409 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5186 20:15:00.905052 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5187 20:15:00.908706 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5188 20:15:00.911869 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5189 20:15:00.915623 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5190 20:15:00.918654 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5191 20:15:00.921699 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5192 20:15:00.928529 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5193 20:15:00.932203 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5194 20:15:00.936233 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5195 20:15:00.939306 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5196 20:15:00.942343 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5197 20:15:00.948724 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5198 20:15:00.951804 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5199 20:15:00.955769 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5200 20:15:00.955849 ==
5201 20:15:00.958419 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 20:15:00.961591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 20:15:00.961672 ==
5204 20:15:00.965059 DQS Delay:
5205 20:15:00.965139 DQS0 = 0, DQS1 = 0
5206 20:15:00.965203 DQM Delay:
5207 20:15:00.969776 DQM0 = 99, DQM1 = 86
5208 20:15:00.969857 DQ Delay:
5209 20:15:00.972043 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5210 20:15:00.975050 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5211 20:15:00.978348 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5212 20:15:00.981618 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5213 20:15:00.981699
5214 20:15:00.981798
5215 20:15:00.981894 ==
5216 20:15:00.985347 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 20:15:00.991952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 20:15:00.992060 ==
5219 20:15:00.992147
5220 20:15:00.992231
5221 20:15:00.992325 TX Vref Scan disable
5222 20:15:00.995338 == TX Byte 0 ==
5223 20:15:00.999031 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5224 20:15:01.002577 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5225 20:15:01.005402 == TX Byte 1 ==
5226 20:15:01.008589 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5227 20:15:01.012138 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5228 20:15:01.015309 ==
5229 20:15:01.018765 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 20:15:01.022356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 20:15:01.022504 ==
5232 20:15:01.022604
5233 20:15:01.022701
5234 20:15:01.025728 TX Vref Scan disable
5235 20:15:01.025832 == TX Byte 0 ==
5236 20:15:01.032206 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5237 20:15:01.035602 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5238 20:15:01.035685 == TX Byte 1 ==
5239 20:15:01.042230 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5240 20:15:01.045682 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5241 20:15:01.045764
5242 20:15:01.045848 [DATLAT]
5243 20:15:01.049042 Freq=933, CH0 RK0
5244 20:15:01.049128
5245 20:15:01.049211 DATLAT Default: 0xd
5246 20:15:01.052201 0, 0xFFFF, sum = 0
5247 20:15:01.052315 1, 0xFFFF, sum = 0
5248 20:15:01.055717 2, 0xFFFF, sum = 0
5249 20:15:01.055800 3, 0xFFFF, sum = 0
5250 20:15:01.059548 4, 0xFFFF, sum = 0
5251 20:15:01.059632 5, 0xFFFF, sum = 0
5252 20:15:01.062143 6, 0xFFFF, sum = 0
5253 20:15:01.062227 7, 0xFFFF, sum = 0
5254 20:15:01.065890 8, 0xFFFF, sum = 0
5255 20:15:01.065974 9, 0xFFFF, sum = 0
5256 20:15:01.069049 10, 0x0, sum = 1
5257 20:15:01.069175 11, 0x0, sum = 2
5258 20:15:01.072128 12, 0x0, sum = 3
5259 20:15:01.072232 13, 0x0, sum = 4
5260 20:15:01.075185 best_step = 11
5261 20:15:01.075281
5262 20:15:01.075368 ==
5263 20:15:01.079246 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 20:15:01.082344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 20:15:01.082476 ==
5266 20:15:01.085690 RX Vref Scan: 1
5267 20:15:01.085769
5268 20:15:01.085832 RX Vref 0 -> 0, step: 1
5269 20:15:01.085892
5270 20:15:01.089095 RX Delay -69 -> 252, step: 4
5271 20:15:01.089175
5272 20:15:01.092462 Set Vref, RX VrefLevel [Byte0]: 54
5273 20:15:01.095559 [Byte1]: 52
5274 20:15:01.099290
5275 20:15:01.099412 Final RX Vref Byte 0 = 54 to rank0
5276 20:15:01.103157 Final RX Vref Byte 1 = 52 to rank0
5277 20:15:01.105925 Final RX Vref Byte 0 = 54 to rank1
5278 20:15:01.109835 Final RX Vref Byte 1 = 52 to rank1==
5279 20:15:01.113253 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 20:15:01.119470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 20:15:01.119553 ==
5282 20:15:01.119637 DQS Delay:
5283 20:15:01.119716 DQS0 = 0, DQS1 = 0
5284 20:15:01.122709 DQM Delay:
5285 20:15:01.122828 DQM0 = 97, DQM1 = 88
5286 20:15:01.126169 DQ Delay:
5287 20:15:01.129851 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5288 20:15:01.132887 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5289 20:15:01.133009 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =80
5290 20:15:01.139935 DQ12 =96, DQ13 =90, DQ14 =102, DQ15 =98
5291 20:15:01.140056
5292 20:15:01.140165
5293 20:15:01.147309 [DQSOSCAuto] RK0, (LSB)MR18= 0x1702, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5294 20:15:01.150158 CH0 RK0: MR19=505, MR18=1702
5295 20:15:01.156700 CH0_RK0: MR19=0x505, MR18=0x1702, DQSOSC=414, MR23=63, INC=63, DEC=42
5296 20:15:01.156811
5297 20:15:01.160416 ----->DramcWriteLeveling(PI) begin...
5298 20:15:01.160496 ==
5299 20:15:01.163225 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 20:15:01.166292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 20:15:01.166419 ==
5302 20:15:01.169883 Write leveling (Byte 0): 30 => 30
5303 20:15:01.172972 Write leveling (Byte 1): 27 => 27
5304 20:15:01.176331 DramcWriteLeveling(PI) end<-----
5305 20:15:01.176436
5306 20:15:01.176525 ==
5307 20:15:01.180139 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 20:15:01.182985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 20:15:01.183064 ==
5310 20:15:01.186373 [Gating] SW mode calibration
5311 20:15:01.193175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5312 20:15:01.199933 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5313 20:15:01.203221 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5314 20:15:01.206257 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5315 20:15:01.213456 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 20:15:01.216575 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 20:15:01.219755 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 20:15:01.226661 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 20:15:01.230173 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 20:15:01.233114 0 14 28 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
5321 20:15:01.240045 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5322 20:15:01.243066 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 20:15:01.246646 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 20:15:01.253073 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 20:15:01.256211 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 20:15:01.260384 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 20:15:01.266968 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 20:15:01.269762 0 15 28 | B1->B0 | 2626 3838 | 0 0 | (1 1) (0 0)
5329 20:15:01.273426 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5330 20:15:01.276388 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 20:15:01.283072 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 20:15:01.286269 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 20:15:01.289965 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 20:15:01.296690 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5335 20:15:01.300113 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 20:15:01.303057 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5337 20:15:01.309689 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5338 20:15:01.312711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 20:15:01.317260 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 20:15:01.322908 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 20:15:01.326147 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 20:15:01.329684 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 20:15:01.336608 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 20:15:01.340287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 20:15:01.342855 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 20:15:01.350151 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 20:15:01.353537 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 20:15:01.356540 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 20:15:01.360092 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 20:15:01.366410 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 20:15:01.369727 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5352 20:15:01.376359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5353 20:15:01.379688 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5354 20:15:01.383075 Total UI for P1: 0, mck2ui 16
5355 20:15:01.386156 best dqsien dly found for B0: ( 1, 2, 26)
5356 20:15:01.389592 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 20:15:01.393095 Total UI for P1: 0, mck2ui 16
5358 20:15:01.396261 best dqsien dly found for B1: ( 1, 2, 30)
5359 20:15:01.400486 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5360 20:15:01.403261 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5361 20:15:01.403342
5362 20:15:01.406075 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5363 20:15:01.409372 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5364 20:15:01.413450 [Gating] SW calibration Done
5365 20:15:01.413529 ==
5366 20:15:01.416471 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 20:15:01.423174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 20:15:01.423257 ==
5369 20:15:01.423334 RX Vref Scan: 0
5370 20:15:01.423406
5371 20:15:01.426647 RX Vref 0 -> 0, step: 1
5372 20:15:01.426727
5373 20:15:01.429771 RX Delay -80 -> 252, step: 8
5374 20:15:01.432581 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5375 20:15:01.436292 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5376 20:15:01.439088 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5377 20:15:01.442984 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5378 20:15:01.445801 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5379 20:15:01.452713 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5380 20:15:01.455935 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5381 20:15:01.460127 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5382 20:15:01.462765 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5383 20:15:01.465950 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5384 20:15:01.472653 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5385 20:15:01.476239 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5386 20:15:01.479320 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5387 20:15:01.483463 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5388 20:15:01.486019 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5389 20:15:01.489655 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5390 20:15:01.492969 ==
5391 20:15:01.493054 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 20:15:01.499697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 20:15:01.499780 ==
5394 20:15:01.499863 DQS Delay:
5395 20:15:01.502902 DQS0 = 0, DQS1 = 0
5396 20:15:01.502983 DQM Delay:
5397 20:15:01.506165 DQM0 = 97, DQM1 = 86
5398 20:15:01.506262 DQ Delay:
5399 20:15:01.509233 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5400 20:15:01.512440 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5401 20:15:01.516029 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5402 20:15:01.519148 DQ12 =87, DQ13 =91, DQ14 =99, DQ15 =95
5403 20:15:01.519228
5404 20:15:01.519291
5405 20:15:01.519350 ==
5406 20:15:01.522554 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 20:15:01.525827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 20:15:01.525907 ==
5409 20:15:01.525971
5410 20:15:01.526045
5411 20:15:01.529083 TX Vref Scan disable
5412 20:15:01.532500 == TX Byte 0 ==
5413 20:15:01.536367 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5414 20:15:01.539562 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5415 20:15:01.542552 == TX Byte 1 ==
5416 20:15:01.546133 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5417 20:15:01.549367 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5418 20:15:01.549475 ==
5419 20:15:01.552468 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 20:15:01.555923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 20:15:01.559242 ==
5422 20:15:01.559356
5423 20:15:01.559457
5424 20:15:01.559554 TX Vref Scan disable
5425 20:15:01.562800 == TX Byte 0 ==
5426 20:15:01.566680 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5427 20:15:01.569752 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5428 20:15:01.572903 == TX Byte 1 ==
5429 20:15:01.576276 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5430 20:15:01.579808 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5431 20:15:01.583112
5432 20:15:01.583194 [DATLAT]
5433 20:15:01.583278 Freq=933, CH0 RK1
5434 20:15:01.583358
5435 20:15:01.586317 DATLAT Default: 0xb
5436 20:15:01.586461 0, 0xFFFF, sum = 0
5437 20:15:01.590245 1, 0xFFFF, sum = 0
5438 20:15:01.590355 2, 0xFFFF, sum = 0
5439 20:15:01.593051 3, 0xFFFF, sum = 0
5440 20:15:01.593135 4, 0xFFFF, sum = 0
5441 20:15:01.596271 5, 0xFFFF, sum = 0
5442 20:15:01.599814 6, 0xFFFF, sum = 0
5443 20:15:01.599898 7, 0xFFFF, sum = 0
5444 20:15:01.603182 8, 0xFFFF, sum = 0
5445 20:15:01.603266 9, 0xFFFF, sum = 0
5446 20:15:01.603350 10, 0x0, sum = 1
5447 20:15:01.606323 11, 0x0, sum = 2
5448 20:15:01.606453 12, 0x0, sum = 3
5449 20:15:01.609877 13, 0x0, sum = 4
5450 20:15:01.609961 best_step = 11
5451 20:15:01.610059
5452 20:15:01.610138 ==
5453 20:15:01.613028 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 20:15:01.619746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 20:15:01.619830 ==
5456 20:15:01.619914 RX Vref Scan: 0
5457 20:15:01.619996
5458 20:15:01.623333 RX Vref 0 -> 0, step: 1
5459 20:15:01.623417
5460 20:15:01.626753 RX Delay -69 -> 252, step: 4
5461 20:15:01.630385 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5462 20:15:01.634307 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5463 20:15:01.639808 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5464 20:15:01.643791 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5465 20:15:01.646359 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5466 20:15:01.650975 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5467 20:15:01.653293 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5468 20:15:01.656986 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5469 20:15:01.663729 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5470 20:15:01.666722 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5471 20:15:01.669883 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5472 20:15:01.673104 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5473 20:15:01.676521 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5474 20:15:01.682922 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5475 20:15:01.686528 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5476 20:15:01.690031 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5477 20:15:01.690137 ==
5478 20:15:01.693245 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 20:15:01.696711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 20:15:01.696793 ==
5481 20:15:01.699929 DQS Delay:
5482 20:15:01.700013 DQS0 = 0, DQS1 = 0
5483 20:15:01.700095 DQM Delay:
5484 20:15:01.703294 DQM0 = 95, DQM1 = 87
5485 20:15:01.703376 DQ Delay:
5486 20:15:01.706903 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5487 20:15:01.710141 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102
5488 20:15:01.713351 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5489 20:15:01.716731 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5490 20:15:01.716814
5491 20:15:01.716897
5492 20:15:01.726321 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
5493 20:15:01.726502 CH0 RK1: MR19=505, MR18=1C09
5494 20:15:01.732828 CH0_RK1: MR19=0x505, MR18=0x1C09, DQSOSC=412, MR23=63, INC=63, DEC=42
5495 20:15:01.736210 [RxdqsGatingPostProcess] freq 933
5496 20:15:01.743115 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5497 20:15:01.746878 best DQS0 dly(2T, 0.5T) = (0, 11)
5498 20:15:01.750202 best DQS1 dly(2T, 0.5T) = (0, 11)
5499 20:15:01.753707 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5500 20:15:01.756486 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5501 20:15:01.759649 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 20:15:01.759755 best DQS1 dly(2T, 0.5T) = (0, 10)
5503 20:15:01.763558 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 20:15:01.767224 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5505 20:15:01.770003 Pre-setting of DQS Precalculation
5506 20:15:01.776432 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5507 20:15:01.776513 ==
5508 20:15:01.780550 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 20:15:01.783197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 20:15:01.783277 ==
5511 20:15:01.790552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5512 20:15:01.796326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5513 20:15:01.799884 [CA 0] Center 36 (6~67) winsize 62
5514 20:15:01.803279 [CA 1] Center 36 (6~67) winsize 62
5515 20:15:01.806752 [CA 2] Center 34 (4~64) winsize 61
5516 20:15:01.809738 [CA 3] Center 33 (2~64) winsize 63
5517 20:15:01.813458 [CA 4] Center 33 (3~64) winsize 62
5518 20:15:01.816318 [CA 5] Center 33 (3~64) winsize 62
5519 20:15:01.816398
5520 20:15:01.820679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5521 20:15:01.820758
5522 20:15:01.822892 [CATrainingPosCal] consider 1 rank data
5523 20:15:01.827192 u2DelayCellTimex100 = 270/100 ps
5524 20:15:01.829239 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5525 20:15:01.832733 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5526 20:15:01.837107 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5527 20:15:01.839667 CA3 delay=33 (2~64),Diff = 0 PI (0 cell)
5528 20:15:01.843133 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5529 20:15:01.846927 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5530 20:15:01.847009
5531 20:15:01.849681 CA PerBit enable=1, Macro0, CA PI delay=33
5532 20:15:01.853308
5533 20:15:01.853389 [CBTSetCACLKResult] CA Dly = 33
5534 20:15:01.856152 CS Dly: 5 (0~36)
5535 20:15:01.856233 ==
5536 20:15:01.859686 Dram Type= 6, Freq= 0, CH_1, rank 1
5537 20:15:01.862948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 20:15:01.863029 ==
5539 20:15:01.869680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 20:15:01.876297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5541 20:15:01.879226 [CA 0] Center 36 (6~67) winsize 62
5542 20:15:01.883146 [CA 1] Center 36 (6~67) winsize 62
5543 20:15:01.886270 [CA 2] Center 33 (3~64) winsize 62
5544 20:15:01.889305 [CA 3] Center 33 (3~64) winsize 62
5545 20:15:01.892884 [CA 4] Center 34 (4~64) winsize 61
5546 20:15:01.896270 [CA 5] Center 32 (2~63) winsize 62
5547 20:15:01.896350
5548 20:15:01.899521 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5549 20:15:01.899601
5550 20:15:01.903661 [CATrainingPosCal] consider 2 rank data
5551 20:15:01.905791 u2DelayCellTimex100 = 270/100 ps
5552 20:15:01.909593 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5553 20:15:01.912476 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 20:15:01.916470 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 20:15:01.919064 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5556 20:15:01.922807 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5557 20:15:01.925967 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5558 20:15:01.926050
5559 20:15:01.933349 CA PerBit enable=1, Macro0, CA PI delay=33
5560 20:15:01.933431
5561 20:15:01.933514 [CBTSetCACLKResult] CA Dly = 33
5562 20:15:01.935740 CS Dly: 6 (0~38)
5563 20:15:01.935824
5564 20:15:01.939186 ----->DramcWriteLeveling(PI) begin...
5565 20:15:01.939267 ==
5566 20:15:01.942626 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 20:15:01.945855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 20:15:01.945935 ==
5569 20:15:01.949072 Write leveling (Byte 0): 26 => 26
5570 20:15:01.952726 Write leveling (Byte 1): 31 => 31
5571 20:15:01.955778 DramcWriteLeveling(PI) end<-----
5572 20:15:01.955858
5573 20:15:01.955921 ==
5574 20:15:01.959208 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 20:15:01.962547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 20:15:01.965842 ==
5577 20:15:01.965922 [Gating] SW mode calibration
5578 20:15:01.973133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5579 20:15:01.979702 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5580 20:15:01.982711 0 14 0 | B1->B0 | 3131 3232 | 0 1 | (0 0) (1 1)
5581 20:15:01.989665 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 20:15:01.993425 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5583 20:15:01.995821 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 20:15:02.002604 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 20:15:02.006969 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 20:15:02.009339 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 20:15:02.016068 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (1 0) (0 0)
5588 20:15:02.019429 0 15 0 | B1->B0 | 2828 2c2c | 0 0 | (1 1) (1 1)
5589 20:15:02.023000 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 20:15:02.026760 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 20:15:02.032502 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5592 20:15:02.036034 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 20:15:02.039200 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 20:15:02.045840 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 20:15:02.049860 0 15 28 | B1->B0 | 3636 2f2f | 0 0 | (1 1) (0 0)
5596 20:15:02.053134 1 0 0 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
5597 20:15:02.059036 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 20:15:02.062464 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 20:15:02.065815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 20:15:02.072614 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 20:15:02.076209 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 20:15:02.078935 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 20:15:02.085796 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5604 20:15:02.089110 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 20:15:02.092421 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 20:15:02.099426 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 20:15:02.102612 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 20:15:02.105790 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 20:15:02.112398 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 20:15:02.116406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 20:15:02.119087 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 20:15:02.122485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 20:15:02.130077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 20:15:02.132458 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 20:15:02.136049 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 20:15:02.142491 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 20:15:02.145992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 20:15:02.148990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 20:15:02.155609 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5620 20:15:02.159085 Total UI for P1: 0, mck2ui 16
5621 20:15:02.162581 best dqsien dly found for B1: ( 1, 2, 26)
5622 20:15:02.165720 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 20:15:02.169244 Total UI for P1: 0, mck2ui 16
5624 20:15:02.172603 best dqsien dly found for B0: ( 1, 2, 28)
5625 20:15:02.176109 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5626 20:15:02.179158 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5627 20:15:02.179238
5628 20:15:02.182887 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5629 20:15:02.185828 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5630 20:15:02.189181 [Gating] SW calibration Done
5631 20:15:02.189261 ==
5632 20:15:02.192499 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 20:15:02.196354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 20:15:02.199343 ==
5635 20:15:02.199423 RX Vref Scan: 0
5636 20:15:02.199486
5637 20:15:02.202750 RX Vref 0 -> 0, step: 1
5638 20:15:02.202830
5639 20:15:02.202893 RX Delay -80 -> 252, step: 8
5640 20:15:02.209316 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5641 20:15:02.212669 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5642 20:15:02.216179 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5643 20:15:02.219650 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5644 20:15:02.222964 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5645 20:15:02.226446 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5646 20:15:02.233134 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5647 20:15:02.236598 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5648 20:15:02.239675 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5649 20:15:02.242856 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5650 20:15:02.246873 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5651 20:15:02.252757 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5652 20:15:02.256055 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5653 20:15:02.259391 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5654 20:15:02.262746 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5655 20:15:02.265874 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5656 20:15:02.265954 ==
5657 20:15:02.270841 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 20:15:02.272500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 20:15:02.275928 ==
5660 20:15:02.276007 DQS Delay:
5661 20:15:02.276070 DQS0 = 0, DQS1 = 0
5662 20:15:02.279322 DQM Delay:
5663 20:15:02.279400 DQM0 = 96, DQM1 = 89
5664 20:15:02.283349 DQ Delay:
5665 20:15:02.286087 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5666 20:15:02.286166 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5667 20:15:02.289848 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5668 20:15:02.295863 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5669 20:15:02.295942
5670 20:15:02.296004
5671 20:15:02.296063 ==
5672 20:15:02.299444 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 20:15:02.302592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 20:15:02.302674 ==
5675 20:15:02.302738
5676 20:15:02.302798
5677 20:15:02.306091 TX Vref Scan disable
5678 20:15:02.306219 == TX Byte 0 ==
5679 20:15:02.312452 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5680 20:15:02.316614 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5681 20:15:02.316711 == TX Byte 1 ==
5682 20:15:02.322574 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5683 20:15:02.325569 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5684 20:15:02.325649 ==
5685 20:15:02.328947 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 20:15:02.332477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 20:15:02.332559 ==
5688 20:15:02.332622
5689 20:15:02.332681
5690 20:15:02.335895 TX Vref Scan disable
5691 20:15:02.339372 == TX Byte 0 ==
5692 20:15:02.342772 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5693 20:15:02.345742 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5694 20:15:02.349820 == TX Byte 1 ==
5695 20:15:02.352682 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5696 20:15:02.356279 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5697 20:15:02.356365
5698 20:15:02.359201 [DATLAT]
5699 20:15:02.359307 Freq=933, CH1 RK0
5700 20:15:02.359407
5701 20:15:02.362305 DATLAT Default: 0xd
5702 20:15:02.362434 0, 0xFFFF, sum = 0
5703 20:15:02.365677 1, 0xFFFF, sum = 0
5704 20:15:02.365785 2, 0xFFFF, sum = 0
5705 20:15:02.368848 3, 0xFFFF, sum = 0
5706 20:15:02.368929 4, 0xFFFF, sum = 0
5707 20:15:02.372329 5, 0xFFFF, sum = 0
5708 20:15:02.372411 6, 0xFFFF, sum = 0
5709 20:15:02.375456 7, 0xFFFF, sum = 0
5710 20:15:02.375537 8, 0xFFFF, sum = 0
5711 20:15:02.378987 9, 0xFFFF, sum = 0
5712 20:15:02.379069 10, 0x0, sum = 1
5713 20:15:02.381991 11, 0x0, sum = 2
5714 20:15:02.382073 12, 0x0, sum = 3
5715 20:15:02.385789 13, 0x0, sum = 4
5716 20:15:02.385870 best_step = 11
5717 20:15:02.385934
5718 20:15:02.385993 ==
5719 20:15:02.389344 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 20:15:02.395302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 20:15:02.395399 ==
5722 20:15:02.395478 RX Vref Scan: 1
5723 20:15:02.395537
5724 20:15:02.399108 RX Vref 0 -> 0, step: 1
5725 20:15:02.399188
5726 20:15:02.401980 RX Delay -61 -> 252, step: 4
5727 20:15:02.402060
5728 20:15:02.405464 Set Vref, RX VrefLevel [Byte0]: 58
5729 20:15:02.408805 [Byte1]: 50
5730 20:15:02.408886
5731 20:15:02.412105 Final RX Vref Byte 0 = 58 to rank0
5732 20:15:02.415739 Final RX Vref Byte 1 = 50 to rank0
5733 20:15:02.418667 Final RX Vref Byte 0 = 58 to rank1
5734 20:15:02.422201 Final RX Vref Byte 1 = 50 to rank1==
5735 20:15:02.425670 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 20:15:02.428730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 20:15:02.428804 ==
5738 20:15:02.431917 DQS Delay:
5739 20:15:02.431997 DQS0 = 0, DQS1 = 0
5740 20:15:02.435313 DQM Delay:
5741 20:15:02.435419 DQM0 = 97, DQM1 = 90
5742 20:15:02.435520 DQ Delay:
5743 20:15:02.438529 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5744 20:15:02.441903 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5745 20:15:02.445246 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =86
5746 20:15:02.448737 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5747 20:15:02.448817
5748 20:15:02.448880
5749 20:15:02.458902 [DQSOSCAuto] RK0, (LSB)MR18= 0x10ed, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5750 20:15:02.462391 CH1 RK0: MR19=504, MR18=10ED
5751 20:15:02.466522 CH1_RK0: MR19=0x504, MR18=0x10ED, DQSOSC=416, MR23=63, INC=62, DEC=41
5752 20:15:02.468695
5753 20:15:02.472160 ----->DramcWriteLeveling(PI) begin...
5754 20:15:02.472241 ==
5755 20:15:02.475111 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 20:15:02.479670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 20:15:02.479781 ==
5758 20:15:02.482064 Write leveling (Byte 0): 25 => 25
5759 20:15:02.486011 Write leveling (Byte 1): 27 => 27
5760 20:15:02.488434 DramcWriteLeveling(PI) end<-----
5761 20:15:02.488518
5762 20:15:02.488582 ==
5763 20:15:02.491878 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 20:15:02.495300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 20:15:02.495381 ==
5766 20:15:02.498640 [Gating] SW mode calibration
5767 20:15:02.505526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5768 20:15:02.512729 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5769 20:15:02.515704 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 20:15:02.518728 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 20:15:02.522391 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 20:15:02.529106 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 20:15:02.532491 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 20:15:02.535760 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
5775 20:15:02.542744 0 14 24 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (1 1)
5776 20:15:02.546054 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5777 20:15:02.548666 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 20:15:02.555378 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 20:15:02.559065 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 20:15:02.563015 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5781 20:15:02.568954 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 20:15:02.572320 0 15 20 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5783 20:15:02.575273 0 15 24 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5784 20:15:02.582332 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5785 20:15:02.586429 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 20:15:02.589388 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 20:15:02.595902 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 20:15:02.598948 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 20:15:02.601900 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 20:15:02.608611 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 20:15:02.612224 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5792 20:15:02.615640 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 20:15:02.622636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 20:15:02.625807 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 20:15:02.628898 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 20:15:02.632401 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 20:15:02.638986 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 20:15:02.642917 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 20:15:02.645750 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 20:15:02.652725 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 20:15:02.655966 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 20:15:02.658817 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 20:15:02.665474 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 20:15:02.668657 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 20:15:02.672045 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 20:15:02.679075 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 20:15:02.682206 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5808 20:15:02.685442 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5809 20:15:02.688834 Total UI for P1: 0, mck2ui 16
5810 20:15:02.692714 best dqsien dly found for B0: ( 1, 2, 24)
5811 20:15:02.699057 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 20:15:02.699139 Total UI for P1: 0, mck2ui 16
5813 20:15:02.701962 best dqsien dly found for B1: ( 1, 2, 26)
5814 20:15:02.708646 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5815 20:15:02.712290 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5816 20:15:02.712369
5817 20:15:02.715250 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5818 20:15:02.718528 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5819 20:15:02.722330 [Gating] SW calibration Done
5820 20:15:02.722469 ==
5821 20:15:02.725331 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 20:15:02.728540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 20:15:02.728620 ==
5824 20:15:02.731910 RX Vref Scan: 0
5825 20:15:02.731989
5826 20:15:02.732052 RX Vref 0 -> 0, step: 1
5827 20:15:02.732110
5828 20:15:02.735322 RX Delay -80 -> 252, step: 8
5829 20:15:02.738719 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5830 20:15:02.741758 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5831 20:15:02.748762 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5832 20:15:02.752367 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5833 20:15:02.755718 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5834 20:15:02.758993 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5835 20:15:02.761983 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5836 20:15:02.765404 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5837 20:15:02.772181 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5838 20:15:02.775723 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5839 20:15:02.778872 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5840 20:15:02.783132 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5841 20:15:02.785551 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5842 20:15:02.789111 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5843 20:15:02.795713 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5844 20:15:02.798931 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5845 20:15:02.799010 ==
5846 20:15:02.802203 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 20:15:02.805613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 20:15:02.805692 ==
5849 20:15:02.805755 DQS Delay:
5850 20:15:02.809266 DQS0 = 0, DQS1 = 0
5851 20:15:02.809345 DQM Delay:
5852 20:15:02.812429 DQM0 = 95, DQM1 = 89
5853 20:15:02.812509 DQ Delay:
5854 20:15:02.815761 DQ0 =95, DQ1 =95, DQ2 =87, DQ3 =95
5855 20:15:02.818865 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5856 20:15:02.822370 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5857 20:15:02.825588 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5858 20:15:02.825668
5859 20:15:02.825730
5860 20:15:02.825788 ==
5861 20:15:02.828893 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 20:15:02.832327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 20:15:02.835622 ==
5864 20:15:02.835701
5865 20:15:02.835776
5866 20:15:02.835879 TX Vref Scan disable
5867 20:15:02.838917 == TX Byte 0 ==
5868 20:15:02.842375 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5869 20:15:02.845369 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5870 20:15:02.849213 == TX Byte 1 ==
5871 20:15:02.852056 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5872 20:15:02.855250 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5873 20:15:02.859517 ==
5874 20:15:02.859597 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 20:15:02.865425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 20:15:02.865505 ==
5877 20:15:02.865567
5878 20:15:02.865625
5879 20:15:02.868328 TX Vref Scan disable
5880 20:15:02.868407 == TX Byte 0 ==
5881 20:15:02.875061 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5882 20:15:02.878671 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5883 20:15:02.878751 == TX Byte 1 ==
5884 20:15:02.885256 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5885 20:15:02.888994 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5886 20:15:02.889103
5887 20:15:02.889194 [DATLAT]
5888 20:15:02.891753 Freq=933, CH1 RK1
5889 20:15:02.891833
5890 20:15:02.891896 DATLAT Default: 0xb
5891 20:15:02.895502 0, 0xFFFF, sum = 0
5892 20:15:02.895583 1, 0xFFFF, sum = 0
5893 20:15:02.898228 2, 0xFFFF, sum = 0
5894 20:15:02.898309 3, 0xFFFF, sum = 0
5895 20:15:02.902131 4, 0xFFFF, sum = 0
5896 20:15:02.902212 5, 0xFFFF, sum = 0
5897 20:15:02.904895 6, 0xFFFF, sum = 0
5898 20:15:02.904975 7, 0xFFFF, sum = 0
5899 20:15:02.908916 8, 0xFFFF, sum = 0
5900 20:15:02.908997 9, 0xFFFF, sum = 0
5901 20:15:02.912030 10, 0x0, sum = 1
5902 20:15:02.912119 11, 0x0, sum = 2
5903 20:15:02.915679 12, 0x0, sum = 3
5904 20:15:02.915759 13, 0x0, sum = 4
5905 20:15:02.919000 best_step = 11
5906 20:15:02.919079
5907 20:15:02.919141 ==
5908 20:15:02.921886 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 20:15:02.925255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 20:15:02.925335 ==
5911 20:15:02.928339 RX Vref Scan: 0
5912 20:15:02.928419
5913 20:15:02.928481 RX Vref 0 -> 0, step: 1
5914 20:15:02.928539
5915 20:15:02.931819 RX Delay -61 -> 252, step: 4
5916 20:15:02.939202 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5917 20:15:02.942374 iDelay=195, Bit 1, Center 88 (-5 ~ 182) 188
5918 20:15:02.945196 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5919 20:15:02.949047 iDelay=195, Bit 3, Center 92 (-1 ~ 186) 188
5920 20:15:02.952574 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5921 20:15:02.955729 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5922 20:15:02.962369 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5923 20:15:02.965317 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5924 20:15:02.969474 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5925 20:15:02.971987 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5926 20:15:02.975318 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
5927 20:15:02.979766 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5928 20:15:02.985714 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5929 20:15:02.988647 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5930 20:15:02.992724 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5931 20:15:02.995996 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5932 20:15:02.996075 ==
5933 20:15:02.999158 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 20:15:03.002340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 20:15:03.006171 ==
5936 20:15:03.006250 DQS Delay:
5937 20:15:03.006312 DQS0 = 0, DQS1 = 0
5938 20:15:03.009373 DQM Delay:
5939 20:15:03.009452 DQM0 = 94, DQM1 = 90
5940 20:15:03.012175 DQ Delay:
5941 20:15:03.012254 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
5942 20:15:03.015640 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
5943 20:15:03.019031 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =82
5944 20:15:03.022945 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5945 20:15:03.023024
5946 20:15:03.025427
5947 20:15:03.032307 [DQSOSCAuto] RK1, (LSB)MR18= 0xa13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5948 20:15:03.035378 CH1 RK1: MR19=505, MR18=A13
5949 20:15:03.042173 CH1_RK1: MR19=0x505, MR18=0xA13, DQSOSC=415, MR23=63, INC=62, DEC=41
5950 20:15:03.042280 [RxdqsGatingPostProcess] freq 933
5951 20:15:03.049237 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 20:15:03.052101 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 20:15:03.055557 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 20:15:03.058935 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 20:15:03.062014 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 20:15:03.065462 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 20:15:03.068942 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 20:15:03.072095 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 20:15:03.075414 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 20:15:03.078825 Pre-setting of DQS Precalculation
5961 20:15:03.083478 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 20:15:03.088705 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 20:15:03.095813 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 20:15:03.095895
5965 20:15:03.095959
5966 20:15:03.099488 [Calibration Summary] 1866 Mbps
5967 20:15:03.102181 CH 0, Rank 0
5968 20:15:03.102262 SW Impedance : PASS
5969 20:15:03.105595 DUTY Scan : NO K
5970 20:15:03.108812 ZQ Calibration : PASS
5971 20:15:03.108893 Jitter Meter : NO K
5972 20:15:03.112557 CBT Training : PASS
5973 20:15:03.115705 Write leveling : PASS
5974 20:15:03.115786 RX DQS gating : PASS
5975 20:15:03.119012 RX DQ/DQS(RDDQC) : PASS
5976 20:15:03.122312 TX DQ/DQS : PASS
5977 20:15:03.122393 RX DATLAT : PASS
5978 20:15:03.125503 RX DQ/DQS(Engine): PASS
5979 20:15:03.125583 TX OE : NO K
5980 20:15:03.128733 All Pass.
5981 20:15:03.128813
5982 20:15:03.128877 CH 0, Rank 1
5983 20:15:03.132287 SW Impedance : PASS
5984 20:15:03.132368 DUTY Scan : NO K
5985 20:15:03.135908 ZQ Calibration : PASS
5986 20:15:03.139005 Jitter Meter : NO K
5987 20:15:03.139086 CBT Training : PASS
5988 20:15:03.142589 Write leveling : PASS
5989 20:15:03.145287 RX DQS gating : PASS
5990 20:15:03.145367 RX DQ/DQS(RDDQC) : PASS
5991 20:15:03.148977 TX DQ/DQS : PASS
5992 20:15:03.152269 RX DATLAT : PASS
5993 20:15:03.152350 RX DQ/DQS(Engine): PASS
5994 20:15:03.155727 TX OE : NO K
5995 20:15:03.155807 All Pass.
5996 20:15:03.155871
5997 20:15:03.158959 CH 1, Rank 0
5998 20:15:03.159040 SW Impedance : PASS
5999 20:15:03.162372 DUTY Scan : NO K
6000 20:15:03.166175 ZQ Calibration : PASS
6001 20:15:03.166269 Jitter Meter : NO K
6002 20:15:03.169341 CBT Training : PASS
6003 20:15:03.169421 Write leveling : PASS
6004 20:15:03.172089 RX DQS gating : PASS
6005 20:15:03.175392 RX DQ/DQS(RDDQC) : PASS
6006 20:15:03.175473 TX DQ/DQS : PASS
6007 20:15:03.179058 RX DATLAT : PASS
6008 20:15:03.182373 RX DQ/DQS(Engine): PASS
6009 20:15:03.182480 TX OE : NO K
6010 20:15:03.185322 All Pass.
6011 20:15:03.185403
6012 20:15:03.185466 CH 1, Rank 1
6013 20:15:03.188961 SW Impedance : PASS
6014 20:15:03.189042 DUTY Scan : NO K
6015 20:15:03.192281 ZQ Calibration : PASS
6016 20:15:03.195598 Jitter Meter : NO K
6017 20:15:03.195674 CBT Training : PASS
6018 20:15:03.199288 Write leveling : PASS
6019 20:15:03.201937 RX DQS gating : PASS
6020 20:15:03.202018 RX DQ/DQS(RDDQC) : PASS
6021 20:15:03.205491 TX DQ/DQS : PASS
6022 20:15:03.205573 RX DATLAT : PASS
6023 20:15:03.208787 RX DQ/DQS(Engine): PASS
6024 20:15:03.211982 TX OE : NO K
6025 20:15:03.212061 All Pass.
6026 20:15:03.212145
6027 20:15:03.216043 DramC Write-DBI off
6028 20:15:03.216128 PER_BANK_REFRESH: Hybrid Mode
6029 20:15:03.219087 TX_TRACKING: ON
6030 20:15:03.229041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 20:15:03.231911 [FAST_K] Save calibration result to emmc
6032 20:15:03.235238 dramc_set_vcore_voltage set vcore to 650000
6033 20:15:03.235319 Read voltage for 400, 6
6034 20:15:03.238691 Vio18 = 0
6035 20:15:03.238771 Vcore = 650000
6036 20:15:03.238835 Vdram = 0
6037 20:15:03.242615 Vddq = 0
6038 20:15:03.242705 Vmddr = 0
6039 20:15:03.248808 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 20:15:03.252067 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 20:15:03.255333 MEM_TYPE=3, freq_sel=20
6042 20:15:03.258987 sv_algorithm_assistance_LP4_800
6043 20:15:03.261908 ============ PULL DRAM RESETB DOWN ============
6044 20:15:03.265946 ========== PULL DRAM RESETB DOWN end =========
6045 20:15:03.272188 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 20:15:03.275740 ===================================
6047 20:15:03.275825 LPDDR4 DRAM CONFIGURATION
6048 20:15:03.278581 ===================================
6049 20:15:03.283198 EX_ROW_EN[0] = 0x0
6050 20:15:03.283268 EX_ROW_EN[1] = 0x0
6051 20:15:03.285517 LP4Y_EN = 0x0
6052 20:15:03.285614 WORK_FSP = 0x0
6053 20:15:03.289228 WL = 0x2
6054 20:15:03.289302 RL = 0x2
6055 20:15:03.292402 BL = 0x2
6056 20:15:03.296112 RPST = 0x0
6057 20:15:03.296194 RD_PRE = 0x0
6058 20:15:03.298632 WR_PRE = 0x1
6059 20:15:03.298733 WR_PST = 0x0
6060 20:15:03.302259 DBI_WR = 0x0
6061 20:15:03.302358 DBI_RD = 0x0
6062 20:15:03.305149 OTF = 0x1
6063 20:15:03.308478 ===================================
6064 20:15:03.312270 ===================================
6065 20:15:03.312369 ANA top config
6066 20:15:03.315537 ===================================
6067 20:15:03.319161 DLL_ASYNC_EN = 0
6068 20:15:03.321836 ALL_SLAVE_EN = 1
6069 20:15:03.321906 NEW_RANK_MODE = 1
6070 20:15:03.326172 DLL_IDLE_MODE = 1
6071 20:15:03.328784 LP45_APHY_COMB_EN = 1
6072 20:15:03.331916 TX_ODT_DIS = 1
6073 20:15:03.331989 NEW_8X_MODE = 1
6074 20:15:03.335489 ===================================
6075 20:15:03.338587 ===================================
6076 20:15:03.341696 data_rate = 800
6077 20:15:03.346342 CKR = 1
6078 20:15:03.348828 DQ_P2S_RATIO = 4
6079 20:15:03.351796 ===================================
6080 20:15:03.355415 CA_P2S_RATIO = 4
6081 20:15:03.358460 DQ_CA_OPEN = 0
6082 20:15:03.358541 DQ_SEMI_OPEN = 1
6083 20:15:03.362223 CA_SEMI_OPEN = 1
6084 20:15:03.365346 CA_FULL_RATE = 0
6085 20:15:03.368647 DQ_CKDIV4_EN = 0
6086 20:15:03.372475 CA_CKDIV4_EN = 1
6087 20:15:03.375270 CA_PREDIV_EN = 0
6088 20:15:03.375352 PH8_DLY = 0
6089 20:15:03.378912 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 20:15:03.381777 DQ_AAMCK_DIV = 0
6091 20:15:03.385170 CA_AAMCK_DIV = 0
6092 20:15:03.388659 CA_ADMCK_DIV = 4
6093 20:15:03.392166 DQ_TRACK_CA_EN = 0
6094 20:15:03.392248 CA_PICK = 800
6095 20:15:03.395631 CA_MCKIO = 400
6096 20:15:03.399143 MCKIO_SEMI = 400
6097 20:15:03.401862 PLL_FREQ = 3016
6098 20:15:03.405207 DQ_UI_PI_RATIO = 32
6099 20:15:03.408980 CA_UI_PI_RATIO = 32
6100 20:15:03.411879 ===================================
6101 20:15:03.415461 ===================================
6102 20:15:03.418791 memory_type:LPDDR4
6103 20:15:03.418890 GP_NUM : 10
6104 20:15:03.421866 SRAM_EN : 1
6105 20:15:03.421961 MD32_EN : 0
6106 20:15:03.425670 ===================================
6107 20:15:03.429276 [ANA_INIT] >>>>>>>>>>>>>>
6108 20:15:03.432001 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 20:15:03.435306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 20:15:03.438690 ===================================
6111 20:15:03.442264 data_rate = 800,PCW = 0X7400
6112 20:15:03.445313 ===================================
6113 20:15:03.448893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 20:15:03.451929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 20:15:03.465592 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 20:15:03.468679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 20:15:03.472512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 20:15:03.475235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 20:15:03.478593 [ANA_INIT] flow start
6120 20:15:03.482041 [ANA_INIT] PLL >>>>>>>>
6121 20:15:03.482113 [ANA_INIT] PLL <<<<<<<<
6122 20:15:03.485368 [ANA_INIT] MIDPI >>>>>>>>
6123 20:15:03.489002 [ANA_INIT] MIDPI <<<<<<<<
6124 20:15:03.489075 [ANA_INIT] DLL >>>>>>>>
6125 20:15:03.491893 [ANA_INIT] flow end
6126 20:15:03.495708 ============ LP4 DIFF to SE enter ============
6127 20:15:03.498954 ============ LP4 DIFF to SE exit ============
6128 20:15:03.501975 [ANA_INIT] <<<<<<<<<<<<<
6129 20:15:03.505121 [Flow] Enable top DCM control >>>>>
6130 20:15:03.508662 [Flow] Enable top DCM control <<<<<
6131 20:15:03.511854 Enable DLL master slave shuffle
6132 20:15:03.518334 ==============================================================
6133 20:15:03.518468 Gating Mode config
6134 20:15:03.525546 ==============================================================
6135 20:15:03.525648 Config description:
6136 20:15:03.536094 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 20:15:03.542084 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 20:15:03.548693 SELPH_MODE 0: By rank 1: By Phase
6139 20:15:03.551970 ==============================================================
6140 20:15:03.555647 GAT_TRACK_EN = 0
6141 20:15:03.558700 RX_GATING_MODE = 2
6142 20:15:03.562249 RX_GATING_TRACK_MODE = 2
6143 20:15:03.565209 SELPH_MODE = 1
6144 20:15:03.568699 PICG_EARLY_EN = 1
6145 20:15:03.572171 VALID_LAT_VALUE = 1
6146 20:15:03.575282 ==============================================================
6147 20:15:03.578655 Enter into Gating configuration >>>>
6148 20:15:03.581859 Exit from Gating configuration <<<<
6149 20:15:03.585374 Enter into DVFS_PRE_config >>>>>
6150 20:15:03.599266 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 20:15:03.602318 Exit from DVFS_PRE_config <<<<<
6152 20:15:03.602459 Enter into PICG configuration >>>>
6153 20:15:03.605884 Exit from PICG configuration <<<<
6154 20:15:03.608962 [RX_INPUT] configuration >>>>>
6155 20:15:03.612178 [RX_INPUT] configuration <<<<<
6156 20:15:03.619267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 20:15:03.622127 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 20:15:03.628471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 20:15:03.635230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 20:15:03.642036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 20:15:03.649016 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 20:15:03.652286 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 20:15:03.655414 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 20:15:03.658954 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 20:15:03.665409 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 20:15:03.669060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 20:15:03.672097 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 20:15:03.675467 ===================================
6169 20:15:03.679071 LPDDR4 DRAM CONFIGURATION
6170 20:15:03.682453 ===================================
6171 20:15:03.682534 EX_ROW_EN[0] = 0x0
6172 20:15:03.686179 EX_ROW_EN[1] = 0x0
6173 20:15:03.686309 LP4Y_EN = 0x0
6174 20:15:03.689063 WORK_FSP = 0x0
6175 20:15:03.689144 WL = 0x2
6176 20:15:03.692292 RL = 0x2
6177 20:15:03.695897 BL = 0x2
6178 20:15:03.695979 RPST = 0x0
6179 20:15:03.698992 RD_PRE = 0x0
6180 20:15:03.699073 WR_PRE = 0x1
6181 20:15:03.702032 WR_PST = 0x0
6182 20:15:03.702112 DBI_WR = 0x0
6183 20:15:03.706061 DBI_RD = 0x0
6184 20:15:03.706143 OTF = 0x1
6185 20:15:03.709335 ===================================
6186 20:15:03.712126 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 20:15:03.718795 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 20:15:03.722804 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 20:15:03.725530 ===================================
6190 20:15:03.729033 LPDDR4 DRAM CONFIGURATION
6191 20:15:03.732303 ===================================
6192 20:15:03.732384 EX_ROW_EN[0] = 0x10
6193 20:15:03.735388 EX_ROW_EN[1] = 0x0
6194 20:15:03.735469 LP4Y_EN = 0x0
6195 20:15:03.739296 WORK_FSP = 0x0
6196 20:15:03.739377 WL = 0x2
6197 20:15:03.742705 RL = 0x2
6198 20:15:03.742815 BL = 0x2
6199 20:15:03.745355 RPST = 0x0
6200 20:15:03.745458 RD_PRE = 0x0
6201 20:15:03.749481 WR_PRE = 0x1
6202 20:15:03.752357 WR_PST = 0x0
6203 20:15:03.752438 DBI_WR = 0x0
6204 20:15:03.755479 DBI_RD = 0x0
6205 20:15:03.755560 OTF = 0x1
6206 20:15:03.759150 ===================================
6207 20:15:03.765441 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 20:15:03.769013 nWR fixed to 30
6209 20:15:03.772331 [ModeRegInit_LP4] CH0 RK0
6210 20:15:03.772412 [ModeRegInit_LP4] CH0 RK1
6211 20:15:03.775991 [ModeRegInit_LP4] CH1 RK0
6212 20:15:03.778956 [ModeRegInit_LP4] CH1 RK1
6213 20:15:03.779053 match AC timing 19
6214 20:15:03.785872 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 20:15:03.789045 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 20:15:03.792321 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 20:15:03.798752 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 20:15:03.802077 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 20:15:03.802159 ==
6220 20:15:03.805547 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 20:15:03.809057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 20:15:03.809139 ==
6223 20:15:03.815594 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 20:15:03.822285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6225 20:15:03.825368 [CA 0] Center 36 (8~64) winsize 57
6226 20:15:03.829150 [CA 1] Center 36 (8~64) winsize 57
6227 20:15:03.829231 [CA 2] Center 36 (8~64) winsize 57
6228 20:15:03.832656 [CA 3] Center 36 (8~64) winsize 57
6229 20:15:03.835979 [CA 4] Center 36 (8~64) winsize 57
6230 20:15:03.839486 [CA 5] Center 36 (8~64) winsize 57
6231 20:15:03.839583
6232 20:15:03.842322 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6233 20:15:03.842413
6234 20:15:03.849129 [CATrainingPosCal] consider 1 rank data
6235 20:15:03.849211 u2DelayCellTimex100 = 270/100 ps
6236 20:15:03.855522 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 20:15:03.859109 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 20:15:03.862623 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 20:15:03.865379 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 20:15:03.869097 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 20:15:03.872572 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 20:15:03.872669
6243 20:15:03.875445 CA PerBit enable=1, Macro0, CA PI delay=36
6244 20:15:03.875523
6245 20:15:03.878750 [CBTSetCACLKResult] CA Dly = 36
6246 20:15:03.882500 CS Dly: 1 (0~32)
6247 20:15:03.882571 ==
6248 20:15:03.885905 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 20:15:03.888930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 20:15:03.889027 ==
6251 20:15:03.892502 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 20:15:03.899937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 20:15:03.902553 [CA 0] Center 36 (8~64) winsize 57
6254 20:15:03.907227 [CA 1] Center 36 (8~64) winsize 57
6255 20:15:03.908960 [CA 2] Center 36 (8~64) winsize 57
6256 20:15:03.912025 [CA 3] Center 36 (8~64) winsize 57
6257 20:15:03.915954 [CA 4] Center 36 (8~64) winsize 57
6258 20:15:03.918702 [CA 5] Center 36 (8~64) winsize 57
6259 20:15:03.918799
6260 20:15:03.922139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 20:15:03.922239
6262 20:15:03.926252 [CATrainingPosCal] consider 2 rank data
6263 20:15:03.928706 u2DelayCellTimex100 = 270/100 ps
6264 20:15:03.932276 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 20:15:03.935318 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 20:15:03.938757 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 20:15:03.943313 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 20:15:03.948677 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 20:15:03.952172 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 20:15:03.952270
6271 20:15:03.956054 CA PerBit enable=1, Macro0, CA PI delay=36
6272 20:15:03.956148
6273 20:15:03.958955 [CBTSetCACLKResult] CA Dly = 36
6274 20:15:03.959029 CS Dly: 1 (0~32)
6275 20:15:03.959117
6276 20:15:03.962167 ----->DramcWriteLeveling(PI) begin...
6277 20:15:03.962270 ==
6278 20:15:03.965503 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 20:15:03.971793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 20:15:03.971897 ==
6281 20:15:03.975290 Write leveling (Byte 0): 40 => 8
6282 20:15:03.975400 Write leveling (Byte 1): 32 => 0
6283 20:15:03.978969 DramcWriteLeveling(PI) end<-----
6284 20:15:03.979052
6285 20:15:03.979125 ==
6286 20:15:03.982036 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 20:15:03.988717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 20:15:03.988816 ==
6289 20:15:03.991820 [Gating] SW mode calibration
6290 20:15:03.998650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 20:15:04.002671 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 20:15:04.008711 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 20:15:04.011938 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 20:15:04.015575 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 20:15:04.021729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 20:15:04.025479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 20:15:04.028306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 20:15:04.032314 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 20:15:04.038265 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 20:15:04.041622 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 20:15:04.045225 Total UI for P1: 0, mck2ui 16
6302 20:15:04.048435 best dqsien dly found for B0: ( 0, 14, 24)
6303 20:15:04.052119 Total UI for P1: 0, mck2ui 16
6304 20:15:04.055134 best dqsien dly found for B1: ( 0, 14, 24)
6305 20:15:04.058514 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 20:15:04.062234 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 20:15:04.062343
6308 20:15:04.065064 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 20:15:04.068676 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 20:15:04.072136 [Gating] SW calibration Done
6311 20:15:04.072233 ==
6312 20:15:04.075446 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 20:15:04.082076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 20:15:04.082175 ==
6315 20:15:04.082267 RX Vref Scan: 0
6316 20:15:04.082357
6317 20:15:04.085205 RX Vref 0 -> 0, step: 1
6318 20:15:04.085302
6319 20:15:04.089042 RX Delay -410 -> 252, step: 16
6320 20:15:04.092045 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6321 20:15:04.095369 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6322 20:15:04.098735 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6323 20:15:04.105457 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6324 20:15:04.108693 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6325 20:15:04.112165 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6326 20:15:04.116287 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6327 20:15:04.122041 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6328 20:15:04.125556 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6329 20:15:04.128952 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6330 20:15:04.133087 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6331 20:15:04.138671 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6332 20:15:04.142255 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6333 20:15:04.145777 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6334 20:15:04.148740 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6335 20:15:04.155664 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6336 20:15:04.155749 ==
6337 20:15:04.158768 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 20:15:04.162256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 20:15:04.162362 ==
6340 20:15:04.162496 DQS Delay:
6341 20:15:04.165606 DQS0 = 35, DQS1 = 51
6342 20:15:04.165687 DQM Delay:
6343 20:15:04.168937 DQM0 = 6, DQM1 = 10
6344 20:15:04.169047 DQ Delay:
6345 20:15:04.172446 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6346 20:15:04.175731 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6347 20:15:04.178659 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6348 20:15:04.182104 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 20:15:04.182203
6350 20:15:04.182268
6351 20:15:04.182330 ==
6352 20:15:04.185400 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 20:15:04.188626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 20:15:04.188708 ==
6355 20:15:04.188773
6356 20:15:04.188832
6357 20:15:04.191902 TX Vref Scan disable
6358 20:15:04.195718 == TX Byte 0 ==
6359 20:15:04.198649 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 20:15:04.202127 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 20:15:04.202210 == TX Byte 1 ==
6362 20:15:04.208930 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6363 20:15:04.211842 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6364 20:15:04.211960 ==
6365 20:15:04.215296 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 20:15:04.218708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 20:15:04.218790 ==
6368 20:15:04.218855
6369 20:15:04.218914
6370 20:15:04.222296 TX Vref Scan disable
6371 20:15:04.225919 == TX Byte 0 ==
6372 20:15:04.228806 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 20:15:04.231931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 20:15:04.236388 == TX Byte 1 ==
6375 20:15:04.238789 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6376 20:15:04.242076 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6377 20:15:04.242157
6378 20:15:04.242221 [DATLAT]
6379 20:15:04.245969 Freq=400, CH0 RK0
6380 20:15:04.246050
6381 20:15:04.246113 DATLAT Default: 0xf
6382 20:15:04.248931 0, 0xFFFF, sum = 0
6383 20:15:04.249027 1, 0xFFFF, sum = 0
6384 20:15:04.253030 2, 0xFFFF, sum = 0
6385 20:15:04.255374 3, 0xFFFF, sum = 0
6386 20:15:04.255457 4, 0xFFFF, sum = 0
6387 20:15:04.258764 5, 0xFFFF, sum = 0
6388 20:15:04.258848 6, 0xFFFF, sum = 0
6389 20:15:04.262636 7, 0xFFFF, sum = 0
6390 20:15:04.262748 8, 0xFFFF, sum = 0
6391 20:15:04.265510 9, 0xFFFF, sum = 0
6392 20:15:04.265592 10, 0xFFFF, sum = 0
6393 20:15:04.269056 11, 0xFFFF, sum = 0
6394 20:15:04.269170 12, 0xFFFF, sum = 0
6395 20:15:04.272060 13, 0x0, sum = 1
6396 20:15:04.272142 14, 0x0, sum = 2
6397 20:15:04.275505 15, 0x0, sum = 3
6398 20:15:04.275587 16, 0x0, sum = 4
6399 20:15:04.279075 best_step = 14
6400 20:15:04.279156
6401 20:15:04.279220 ==
6402 20:15:04.283018 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 20:15:04.285657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 20:15:04.285738 ==
6405 20:15:04.285802 RX Vref Scan: 1
6406 20:15:04.285863
6407 20:15:04.288831 RX Vref 0 -> 0, step: 1
6408 20:15:04.288912
6409 20:15:04.292119 RX Delay -343 -> 252, step: 8
6410 20:15:04.292200
6411 20:15:04.295822 Set Vref, RX VrefLevel [Byte0]: 54
6412 20:15:04.298782 [Byte1]: 52
6413 20:15:04.302992
6414 20:15:04.303120 Final RX Vref Byte 0 = 54 to rank0
6415 20:15:04.305784 Final RX Vref Byte 1 = 52 to rank0
6416 20:15:04.309425 Final RX Vref Byte 0 = 54 to rank1
6417 20:15:04.313040 Final RX Vref Byte 1 = 52 to rank1==
6418 20:15:04.316287 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 20:15:04.322937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 20:15:04.323059 ==
6421 20:15:04.323174 DQS Delay:
6422 20:15:04.325946 DQS0 = 44, DQS1 = 60
6423 20:15:04.326101 DQM Delay:
6424 20:15:04.326209 DQM0 = 10, DQM1 = 15
6425 20:15:04.329271 DQ Delay:
6426 20:15:04.332975 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6427 20:15:04.333099 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6428 20:15:04.335906 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6429 20:15:04.339467 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =28
6430 20:15:04.339570
6431 20:15:04.342184
6432 20:15:04.349090 [DQSOSCAuto] RK0, (LSB)MR18= 0x814f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6433 20:15:04.352631 CH0 RK0: MR19=C0C, MR18=814F
6434 20:15:04.359493 CH0_RK0: MR19=0xC0C, MR18=0x814F, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 20:15:04.359620 ==
6436 20:15:04.362596 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 20:15:04.366777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 20:15:04.366902 ==
6439 20:15:04.369522 [Gating] SW mode calibration
6440 20:15:04.376189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 20:15:04.382643 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 20:15:04.385714 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 20:15:04.388994 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 20:15:04.393011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 20:15:04.399510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 20:15:04.402652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 20:15:04.405888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 20:15:04.412639 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 20:15:04.416078 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 20:15:04.419000 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 20:15:04.422595 Total UI for P1: 0, mck2ui 16
6452 20:15:04.425765 best dqsien dly found for B0: ( 0, 14, 24)
6453 20:15:04.429427 Total UI for P1: 0, mck2ui 16
6454 20:15:04.432416 best dqsien dly found for B1: ( 0, 14, 24)
6455 20:15:04.436170 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 20:15:04.439229 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 20:15:04.439350
6458 20:15:04.446835 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 20:15:04.449694 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 20:15:04.449815 [Gating] SW calibration Done
6461 20:15:04.453586 ==
6462 20:15:04.456456 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 20:15:04.459601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 20:15:04.459722 ==
6465 20:15:04.459833 RX Vref Scan: 0
6466 20:15:04.459941
6467 20:15:04.462871 RX Vref 0 -> 0, step: 1
6468 20:15:04.462990
6469 20:15:04.466115 RX Delay -410 -> 252, step: 16
6470 20:15:04.470158 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6471 20:15:04.472951 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6472 20:15:04.479411 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6473 20:15:04.482813 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6474 20:15:04.486105 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6475 20:15:04.489304 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6476 20:15:04.495933 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6477 20:15:04.499582 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6478 20:15:04.502772 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6479 20:15:04.505867 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6480 20:15:04.512855 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6481 20:15:04.515580 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 20:15:04.519116 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 20:15:04.525532 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 20:15:04.529690 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6485 20:15:04.532415 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6486 20:15:04.532535 ==
6487 20:15:04.535838 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 20:15:04.539337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 20:15:04.542237 ==
6490 20:15:04.542356 DQS Delay:
6491 20:15:04.542503 DQS0 = 43, DQS1 = 51
6492 20:15:04.546187 DQM Delay:
6493 20:15:04.546324 DQM0 = 11, DQM1 = 10
6494 20:15:04.549160 DQ Delay:
6495 20:15:04.549276 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6496 20:15:04.552690 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6497 20:15:04.556014 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 20:15:04.558898 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 20:15:04.559020
6500 20:15:04.559130
6501 20:15:04.559235 ==
6502 20:15:04.562148 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 20:15:04.569302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 20:15:04.569425 ==
6505 20:15:04.569536
6506 20:15:04.569643
6507 20:15:04.569752 TX Vref Scan disable
6508 20:15:04.572568 == TX Byte 0 ==
6509 20:15:04.575460 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 20:15:04.579196 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 20:15:04.582694 == TX Byte 1 ==
6512 20:15:04.585570 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6513 20:15:04.589407 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6514 20:15:04.589525 ==
6515 20:15:04.592354 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 20:15:04.598648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 20:15:04.598772 ==
6518 20:15:04.598933
6519 20:15:04.599044
6520 20:15:04.599165 TX Vref Scan disable
6521 20:15:04.602210 == TX Byte 0 ==
6522 20:15:04.605445 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 20:15:04.608704 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 20:15:04.612029 == TX Byte 1 ==
6525 20:15:04.615509 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6526 20:15:04.619430 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6527 20:15:04.619548
6528 20:15:04.622319 [DATLAT]
6529 20:15:04.622475 Freq=400, CH0 RK1
6530 20:15:04.622584
6531 20:15:04.625705 DATLAT Default: 0xe
6532 20:15:04.625824 0, 0xFFFF, sum = 0
6533 20:15:04.629018 1, 0xFFFF, sum = 0
6534 20:15:04.629142 2, 0xFFFF, sum = 0
6535 20:15:04.632838 3, 0xFFFF, sum = 0
6536 20:15:04.632964 4, 0xFFFF, sum = 0
6537 20:15:04.636468 5, 0xFFFF, sum = 0
6538 20:15:04.636578 6, 0xFFFF, sum = 0
6539 20:15:04.638665 7, 0xFFFF, sum = 0
6540 20:15:04.638767 8, 0xFFFF, sum = 0
6541 20:15:04.641817 9, 0xFFFF, sum = 0
6542 20:15:04.641916 10, 0xFFFF, sum = 0
6543 20:15:04.645437 11, 0xFFFF, sum = 0
6544 20:15:04.648713 12, 0xFFFF, sum = 0
6545 20:15:04.648810 13, 0x0, sum = 1
6546 20:15:04.652123 14, 0x0, sum = 2
6547 20:15:04.652221 15, 0x0, sum = 3
6548 20:15:04.652311 16, 0x0, sum = 4
6549 20:15:04.655578 best_step = 14
6550 20:15:04.655654
6551 20:15:04.655717 ==
6552 20:15:04.658845 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 20:15:04.661937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 20:15:04.662036 ==
6555 20:15:04.666040 RX Vref Scan: 0
6556 20:15:04.666139
6557 20:15:04.666229 RX Vref 0 -> 0, step: 1
6558 20:15:04.668463
6559 20:15:04.668555 RX Delay -343 -> 252, step: 8
6560 20:15:04.676992 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6561 20:15:04.680292 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6562 20:15:04.683513 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6563 20:15:04.686723 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6564 20:15:04.693871 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6565 20:15:04.697092 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6566 20:15:04.700319 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6567 20:15:04.704017 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6568 20:15:04.710210 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6569 20:15:04.713695 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6570 20:15:04.716590 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6571 20:15:04.720583 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6572 20:15:04.726927 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6573 20:15:04.729869 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6574 20:15:04.733365 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6575 20:15:04.740362 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6576 20:15:04.740468 ==
6577 20:15:04.743746 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 20:15:04.746621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 20:15:04.746754 ==
6580 20:15:04.746856 DQS Delay:
6581 20:15:04.750727 DQS0 = 48, DQS1 = 60
6582 20:15:04.750834 DQM Delay:
6583 20:15:04.753626 DQM0 = 13, DQM1 = 14
6584 20:15:04.753712 DQ Delay:
6585 20:15:04.757356 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6586 20:15:04.760714 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6587 20:15:04.763924 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6588 20:15:04.767347 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6589 20:15:04.767453
6590 20:15:04.767542
6591 20:15:04.774177 [DQSOSCAuto] RK1, (LSB)MR18= 0x976b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6592 20:15:04.776633 CH0 RK1: MR19=C0C, MR18=976B
6593 20:15:04.785009 CH0_RK1: MR19=0xC0C, MR18=0x976B, DQSOSC=390, MR23=63, INC=388, DEC=258
6594 20:15:04.786714 [RxdqsGatingPostProcess] freq 400
6595 20:15:04.793428 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 20:15:04.793551 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 20:15:04.796596 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 20:15:04.799902 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 20:15:04.803502 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 20:15:04.807092 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 20:15:04.810001 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 20:15:04.813424 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 20:15:04.816720 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 20:15:04.819927 Pre-setting of DQS Precalculation
6605 20:15:04.823751 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 20:15:04.826739 ==
6607 20:15:04.830342 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 20:15:04.833706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 20:15:04.833828 ==
6610 20:15:04.836975 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 20:15:04.843521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 20:15:04.846753 [CA 0] Center 36 (8~64) winsize 57
6613 20:15:04.849990 [CA 1] Center 36 (8~64) winsize 57
6614 20:15:04.853645 [CA 2] Center 36 (8~64) winsize 57
6615 20:15:04.856540 [CA 3] Center 36 (8~64) winsize 57
6616 20:15:04.860628 [CA 4] Center 36 (8~64) winsize 57
6617 20:15:04.863852 [CA 5] Center 36 (8~64) winsize 57
6618 20:15:04.863975
6619 20:15:04.866617 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 20:15:04.866739
6621 20:15:04.870390 [CATrainingPosCal] consider 1 rank data
6622 20:15:04.874119 u2DelayCellTimex100 = 270/100 ps
6623 20:15:04.876445 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 20:15:04.880444 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 20:15:04.883537 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 20:15:04.887039 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 20:15:04.889979 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 20:15:04.896896 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 20:15:04.897019
6630 20:15:04.900263 CA PerBit enable=1, Macro0, CA PI delay=36
6631 20:15:04.900386
6632 20:15:04.903790 [CBTSetCACLKResult] CA Dly = 36
6633 20:15:04.903913 CS Dly: 1 (0~32)
6634 20:15:04.904025 ==
6635 20:15:04.906796 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 20:15:04.910321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 20:15:04.910481 ==
6638 20:15:04.917455 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 20:15:04.924317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 20:15:04.926561 [CA 0] Center 36 (8~64) winsize 57
6641 20:15:04.929739 [CA 1] Center 36 (8~64) winsize 57
6642 20:15:04.933536 [CA 2] Center 36 (8~64) winsize 57
6643 20:15:04.936773 [CA 3] Center 36 (8~64) winsize 57
6644 20:15:04.940171 [CA 4] Center 36 (8~64) winsize 57
6645 20:15:04.940308 [CA 5] Center 36 (8~64) winsize 57
6646 20:15:04.943132
6647 20:15:04.947051 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 20:15:04.947170
6649 20:15:04.950052 [CATrainingPosCal] consider 2 rank data
6650 20:15:04.953871 u2DelayCellTimex100 = 270/100 ps
6651 20:15:04.957721 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 20:15:04.960688 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 20:15:04.963975 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 20:15:04.967116 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 20:15:04.971084 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 20:15:04.974006 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 20:15:04.974127
6658 20:15:04.976688 CA PerBit enable=1, Macro0, CA PI delay=36
6659 20:15:04.976809
6660 20:15:04.979986 [CBTSetCACLKResult] CA Dly = 36
6661 20:15:04.983839 CS Dly: 1 (0~32)
6662 20:15:04.983956
6663 20:15:04.987433 ----->DramcWriteLeveling(PI) begin...
6664 20:15:04.987555 ==
6665 20:15:04.990085 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 20:15:04.993606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 20:15:04.993731 ==
6668 20:15:04.996727 Write leveling (Byte 0): 40 => 8
6669 20:15:05.000366 Write leveling (Byte 1): 40 => 8
6670 20:15:05.003366 DramcWriteLeveling(PI) end<-----
6671 20:15:05.003488
6672 20:15:05.003598 ==
6673 20:15:05.007112 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 20:15:05.010065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 20:15:05.010188 ==
6676 20:15:05.013446 [Gating] SW mode calibration
6677 20:15:05.020788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 20:15:05.026971 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 20:15:05.030491 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 20:15:05.033959 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 20:15:05.040199 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 20:15:05.043884 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 20:15:05.046962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 20:15:05.054127 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 20:15:05.056796 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 20:15:05.060199 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 20:15:05.066737 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 20:15:05.066818 Total UI for P1: 0, mck2ui 16
6689 20:15:05.073751 best dqsien dly found for B0: ( 0, 14, 24)
6690 20:15:05.073831 Total UI for P1: 0, mck2ui 16
6691 20:15:05.076920 best dqsien dly found for B1: ( 0, 14, 24)
6692 20:15:05.083453 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 20:15:05.087523 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 20:15:05.087603
6695 20:15:05.090617 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 20:15:05.093534 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 20:15:05.096945 [Gating] SW calibration Done
6698 20:15:05.097041 ==
6699 20:15:05.100515 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 20:15:05.103781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 20:15:05.103878 ==
6702 20:15:05.107733 RX Vref Scan: 0
6703 20:15:05.107813
6704 20:15:05.107876 RX Vref 0 -> 0, step: 1
6705 20:15:05.107935
6706 20:15:05.110643 RX Delay -410 -> 252, step: 16
6707 20:15:05.114631 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6708 20:15:05.120415 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6709 20:15:05.124188 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6710 20:15:05.127370 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6711 20:15:05.130172 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6712 20:15:05.137233 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6713 20:15:05.140696 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6714 20:15:05.143776 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6715 20:15:05.147336 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6716 20:15:05.153899 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6717 20:15:05.157189 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6718 20:15:05.160077 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6719 20:15:05.163682 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6720 20:15:05.170326 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6721 20:15:05.173603 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6722 20:15:05.177116 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6723 20:15:05.177196 ==
6724 20:15:05.180145 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 20:15:05.183924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 20:15:05.187167 ==
6727 20:15:05.187267 DQS Delay:
6728 20:15:05.187357 DQS0 = 51, DQS1 = 59
6729 20:15:05.190250 DQM Delay:
6730 20:15:05.190343 DQM0 = 19, DQM1 = 17
6731 20:15:05.193412 DQ Delay:
6732 20:15:05.197074 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6733 20:15:05.197154 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6734 20:15:05.200317 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6735 20:15:05.203728 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6736 20:15:05.203807
6737 20:15:05.207206
6738 20:15:05.207292 ==
6739 20:15:05.210534 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 20:15:05.213976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 20:15:05.214056 ==
6742 20:15:05.214120
6743 20:15:05.214178
6744 20:15:05.216826 TX Vref Scan disable
6745 20:15:05.216905 == TX Byte 0 ==
6746 20:15:05.220294 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 20:15:05.227252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 20:15:05.227343 == TX Byte 1 ==
6749 20:15:05.230137 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 20:15:05.236661 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 20:15:05.236741 ==
6752 20:15:05.240359 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 20:15:05.243452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 20:15:05.243532 ==
6755 20:15:05.243595
6756 20:15:05.243653
6757 20:15:05.246953 TX Vref Scan disable
6758 20:15:05.247035 == TX Byte 0 ==
6759 20:15:05.250300 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 20:15:05.256803 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 20:15:05.256883 == TX Byte 1 ==
6762 20:15:05.261041 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 20:15:05.267230 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 20:15:05.267311
6765 20:15:05.267373 [DATLAT]
6766 20:15:05.267432 Freq=400, CH1 RK0
6767 20:15:05.267489
6768 20:15:05.270484 DATLAT Default: 0xf
6769 20:15:05.274273 0, 0xFFFF, sum = 0
6770 20:15:05.274354 1, 0xFFFF, sum = 0
6771 20:15:05.276966 2, 0xFFFF, sum = 0
6772 20:15:05.277096 3, 0xFFFF, sum = 0
6773 20:15:05.280651 4, 0xFFFF, sum = 0
6774 20:15:05.280732 5, 0xFFFF, sum = 0
6775 20:15:05.283599 6, 0xFFFF, sum = 0
6776 20:15:05.283680 7, 0xFFFF, sum = 0
6777 20:15:05.287132 8, 0xFFFF, sum = 0
6778 20:15:05.287239 9, 0xFFFF, sum = 0
6779 20:15:05.290094 10, 0xFFFF, sum = 0
6780 20:15:05.290192 11, 0xFFFF, sum = 0
6781 20:15:05.293498 12, 0xFFFF, sum = 0
6782 20:15:05.293594 13, 0x0, sum = 1
6783 20:15:05.297399 14, 0x0, sum = 2
6784 20:15:05.297480 15, 0x0, sum = 3
6785 20:15:05.299997 16, 0x0, sum = 4
6786 20:15:05.300132 best_step = 14
6787 20:15:05.300198
6788 20:15:05.300256 ==
6789 20:15:05.303869 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 20:15:05.306785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 20:15:05.310502 ==
6792 20:15:05.310582 RX Vref Scan: 1
6793 20:15:05.310644
6794 20:15:05.314372 RX Vref 0 -> 0, step: 1
6795 20:15:05.314501
6796 20:15:05.317015 RX Delay -359 -> 252, step: 8
6797 20:15:05.317094
6798 20:15:05.320823 Set Vref, RX VrefLevel [Byte0]: 58
6799 20:15:05.320903 [Byte1]: 50
6800 20:15:05.326244
6801 20:15:05.326324 Final RX Vref Byte 0 = 58 to rank0
6802 20:15:05.329720 Final RX Vref Byte 1 = 50 to rank0
6803 20:15:05.332796 Final RX Vref Byte 0 = 58 to rank1
6804 20:15:05.335985 Final RX Vref Byte 1 = 50 to rank1==
6805 20:15:05.339606 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 20:15:05.346365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 20:15:05.346468 ==
6808 20:15:05.346532 DQS Delay:
6809 20:15:05.346591 DQS0 = 48, DQS1 = 60
6810 20:15:05.349993 DQM Delay:
6811 20:15:05.350072 DQM0 = 12, DQM1 = 12
6812 20:15:05.352676 DQ Delay:
6813 20:15:05.355955 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6814 20:15:05.356034 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6815 20:15:05.359933 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6816 20:15:05.362883 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6817 20:15:05.362965
6818 20:15:05.363032
6819 20:15:05.372499 [DQSOSCAuto] RK0, (LSB)MR18= 0x8128, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6820 20:15:05.375921 CH1 RK0: MR19=C0C, MR18=8128
6821 20:15:05.382739 CH1_RK0: MR19=0xC0C, MR18=0x8128, DQSOSC=393, MR23=63, INC=382, DEC=254
6822 20:15:05.382846 ==
6823 20:15:05.385837 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 20:15:05.389130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 20:15:05.389216 ==
6826 20:15:05.393095 [Gating] SW mode calibration
6827 20:15:05.399151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 20:15:05.402801 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 20:15:05.409389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 20:15:05.412503 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 20:15:05.415813 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 20:15:05.422803 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 20:15:05.426426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 20:15:05.429268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 20:15:05.435724 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 20:15:05.439345 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 20:15:05.442491 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 20:15:05.445731 Total UI for P1: 0, mck2ui 16
6839 20:15:05.449223 best dqsien dly found for B0: ( 0, 14, 24)
6840 20:15:05.452488 Total UI for P1: 0, mck2ui 16
6841 20:15:05.455821 best dqsien dly found for B1: ( 0, 14, 24)
6842 20:15:05.459159 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 20:15:05.462361 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 20:15:05.462465
6845 20:15:05.469445 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 20:15:05.472376 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 20:15:05.472457 [Gating] SW calibration Done
6848 20:15:05.475710 ==
6849 20:15:05.479493 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 20:15:05.482914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 20:15:05.482995 ==
6852 20:15:05.483059 RX Vref Scan: 0
6853 20:15:05.483119
6854 20:15:05.485834 RX Vref 0 -> 0, step: 1
6855 20:15:05.485913
6856 20:15:05.489453 RX Delay -410 -> 252, step: 16
6857 20:15:05.492728 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6858 20:15:05.496139 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 20:15:05.502601 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6860 20:15:05.506322 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6861 20:15:05.509326 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6862 20:15:05.512588 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6863 20:15:05.519817 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6864 20:15:05.522519 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6865 20:15:05.526184 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 20:15:05.529514 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6867 20:15:05.536268 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 20:15:05.539147 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6869 20:15:05.542785 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6870 20:15:05.545775 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6871 20:15:05.552763 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6872 20:15:05.556133 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6873 20:15:05.556208 ==
6874 20:15:05.559260 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 20:15:05.563012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 20:15:05.563098 ==
6877 20:15:05.565781 DQS Delay:
6878 20:15:05.565866 DQS0 = 43, DQS1 = 59
6879 20:15:05.569280 DQM Delay:
6880 20:15:05.569358 DQM0 = 9, DQM1 = 17
6881 20:15:05.569441 DQ Delay:
6882 20:15:05.573003 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6883 20:15:05.576026 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6884 20:15:05.579923 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6885 20:15:05.583750 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6886 20:15:05.583831
6887 20:15:05.583913
6888 20:15:05.583998 ==
6889 20:15:05.585778 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 20:15:05.589245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 20:15:05.592629 ==
6892 20:15:05.592710
6893 20:15:05.592773
6894 20:15:05.592833 TX Vref Scan disable
6895 20:15:05.595855 == TX Byte 0 ==
6896 20:15:05.599840 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 20:15:05.602858 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 20:15:05.606022 == TX Byte 1 ==
6899 20:15:05.609684 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6900 20:15:05.613286 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6901 20:15:05.613365 ==
6902 20:15:05.615868 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 20:15:05.619547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 20:15:05.623056 ==
6905 20:15:05.623150
6906 20:15:05.623232
6907 20:15:05.623316 TX Vref Scan disable
6908 20:15:05.626194 == TX Byte 0 ==
6909 20:15:05.629565 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 20:15:05.633068 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 20:15:05.635932 == TX Byte 1 ==
6912 20:15:05.639467 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6913 20:15:05.642968 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6914 20:15:05.643052
6915 20:15:05.643133 [DATLAT]
6916 20:15:05.646174 Freq=400, CH1 RK1
6917 20:15:05.646251
6918 20:15:05.649154 DATLAT Default: 0xe
6919 20:15:05.649233 0, 0xFFFF, sum = 0
6920 20:15:05.653206 1, 0xFFFF, sum = 0
6921 20:15:05.653290 2, 0xFFFF, sum = 0
6922 20:15:05.655907 3, 0xFFFF, sum = 0
6923 20:15:05.655990 4, 0xFFFF, sum = 0
6924 20:15:05.659619 5, 0xFFFF, sum = 0
6925 20:15:05.659695 6, 0xFFFF, sum = 0
6926 20:15:05.662830 7, 0xFFFF, sum = 0
6927 20:15:05.662914 8, 0xFFFF, sum = 0
6928 20:15:05.666167 9, 0xFFFF, sum = 0
6929 20:15:05.666242 10, 0xFFFF, sum = 0
6930 20:15:05.669363 11, 0xFFFF, sum = 0
6931 20:15:05.669438 12, 0xFFFF, sum = 0
6932 20:15:05.672749 13, 0x0, sum = 1
6933 20:15:05.672833 14, 0x0, sum = 2
6934 20:15:05.675931 15, 0x0, sum = 3
6935 20:15:05.676008 16, 0x0, sum = 4
6936 20:15:05.679763 best_step = 14
6937 20:15:05.679845
6938 20:15:05.679927 ==
6939 20:15:05.683059 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 20:15:05.686217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 20:15:05.686293 ==
6942 20:15:05.686406 RX Vref Scan: 0
6943 20:15:05.690075
6944 20:15:05.690159 RX Vref 0 -> 0, step: 1
6945 20:15:05.690240
6946 20:15:05.692553 RX Delay -359 -> 252, step: 8
6947 20:15:05.700447 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6948 20:15:05.703554 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6949 20:15:05.707074 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6950 20:15:05.710038 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6951 20:15:05.716568 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6952 20:15:05.720571 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6953 20:15:05.723324 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6954 20:15:05.726996 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6955 20:15:05.733846 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6956 20:15:05.736665 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6957 20:15:05.739971 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6958 20:15:05.746376 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6959 20:15:05.750100 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6960 20:15:05.753055 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6961 20:15:05.756399 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6962 20:15:05.763378 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6963 20:15:05.763459 ==
6964 20:15:05.766373 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 20:15:05.770911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 20:15:05.770995 ==
6967 20:15:05.771062 DQS Delay:
6968 20:15:05.773491 DQS0 = 52, DQS1 = 60
6969 20:15:05.773566 DQM Delay:
6970 20:15:05.776752 DQM0 = 13, DQM1 = 13
6971 20:15:05.776823 DQ Delay:
6972 20:15:05.779849 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6973 20:15:05.783561 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6974 20:15:05.786654 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6975 20:15:05.789763 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6976 20:15:05.789842
6977 20:15:05.789905
6978 20:15:05.796645 [DQSOSCAuto] RK1, (LSB)MR18= 0x7289, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6979 20:15:05.800576 CH1 RK1: MR19=C0C, MR18=7289
6980 20:15:05.806235 CH1_RK1: MR19=0xC0C, MR18=0x7289, DQSOSC=392, MR23=63, INC=384, DEC=256
6981 20:15:05.809862 [RxdqsGatingPostProcess] freq 400
6982 20:15:05.816452 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 20:15:05.816537 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 20:15:05.820802 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 20:15:05.823553 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 20:15:05.826413 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 20:15:05.830334 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 20:15:05.833112 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 20:15:05.836495 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 20:15:05.839673 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 20:15:05.843370 Pre-setting of DQS Precalculation
6992 20:15:05.849502 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 20:15:05.856523 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 20:15:05.863058 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 20:15:05.863139
6996 20:15:05.863203
6997 20:15:05.866263 [Calibration Summary] 800 Mbps
6998 20:15:05.866343 CH 0, Rank 0
6999 20:15:05.869558 SW Impedance : PASS
7000 20:15:05.869639 DUTY Scan : NO K
7001 20:15:05.872704 ZQ Calibration : PASS
7002 20:15:05.876472 Jitter Meter : NO K
7003 20:15:05.876553 CBT Training : PASS
7004 20:15:05.879550 Write leveling : PASS
7005 20:15:05.882969 RX DQS gating : PASS
7006 20:15:05.883049 RX DQ/DQS(RDDQC) : PASS
7007 20:15:05.886905 TX DQ/DQS : PASS
7008 20:15:05.889580 RX DATLAT : PASS
7009 20:15:05.889660 RX DQ/DQS(Engine): PASS
7010 20:15:05.892626 TX OE : NO K
7011 20:15:05.892706 All Pass.
7012 20:15:05.892770
7013 20:15:05.896486 CH 0, Rank 1
7014 20:15:05.896566 SW Impedance : PASS
7015 20:15:05.899795 DUTY Scan : NO K
7016 20:15:05.902798 ZQ Calibration : PASS
7017 20:15:05.902879 Jitter Meter : NO K
7018 20:15:05.906485 CBT Training : PASS
7019 20:15:05.910879 Write leveling : NO K
7020 20:15:05.910960 RX DQS gating : PASS
7021 20:15:05.914140 RX DQ/DQS(RDDQC) : PASS
7022 20:15:05.914220 TX DQ/DQS : PASS
7023 20:15:05.916943 RX DATLAT : PASS
7024 20:15:05.919438 RX DQ/DQS(Engine): PASS
7025 20:15:05.919517 TX OE : NO K
7026 20:15:05.922846 All Pass.
7027 20:15:05.922926
7028 20:15:05.922990 CH 1, Rank 0
7029 20:15:05.926323 SW Impedance : PASS
7030 20:15:05.926436 DUTY Scan : NO K
7031 20:15:05.929527 ZQ Calibration : PASS
7032 20:15:05.932691 Jitter Meter : NO K
7033 20:15:05.932771 CBT Training : PASS
7034 20:15:05.936041 Write leveling : PASS
7035 20:15:05.940107 RX DQS gating : PASS
7036 20:15:05.940231 RX DQ/DQS(RDDQC) : PASS
7037 20:15:05.942825 TX DQ/DQS : PASS
7038 20:15:05.946099 RX DATLAT : PASS
7039 20:15:05.946216 RX DQ/DQS(Engine): PASS
7040 20:15:05.949740 TX OE : NO K
7041 20:15:05.949842 All Pass.
7042 20:15:05.949933
7043 20:15:05.952764 CH 1, Rank 1
7044 20:15:05.952881 SW Impedance : PASS
7045 20:15:05.956392 DUTY Scan : NO K
7046 20:15:05.956511 ZQ Calibration : PASS
7047 20:15:05.959753 Jitter Meter : NO K
7048 20:15:05.963645 CBT Training : PASS
7049 20:15:05.963765 Write leveling : NO K
7050 20:15:05.966511 RX DQS gating : PASS
7051 20:15:05.969407 RX DQ/DQS(RDDQC) : PASS
7052 20:15:05.969524 TX DQ/DQS : PASS
7053 20:15:05.973069 RX DATLAT : PASS
7054 20:15:05.976656 RX DQ/DQS(Engine): PASS
7055 20:15:05.976774 TX OE : NO K
7056 20:15:05.979978 All Pass.
7057 20:15:05.980098
7058 20:15:05.980207 DramC Write-DBI off
7059 20:15:05.983454 PER_BANK_REFRESH: Hybrid Mode
7060 20:15:05.983576 TX_TRACKING: ON
7061 20:15:05.992605 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 20:15:05.996206 [FAST_K] Save calibration result to emmc
7063 20:15:05.999467 dramc_set_vcore_voltage set vcore to 725000
7064 20:15:06.002649 Read voltage for 1600, 0
7065 20:15:06.002729 Vio18 = 0
7066 20:15:06.006335 Vcore = 725000
7067 20:15:06.006456 Vdram = 0
7068 20:15:06.006550 Vddq = 0
7069 20:15:06.009661 Vmddr = 0
7070 20:15:06.012771 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 20:15:06.019374 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 20:15:06.019500 MEM_TYPE=3, freq_sel=13
7073 20:15:06.022884 sv_algorithm_assistance_LP4_3733
7074 20:15:06.026083 ============ PULL DRAM RESETB DOWN ============
7075 20:15:06.033001 ========== PULL DRAM RESETB DOWN end =========
7076 20:15:06.036317 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 20:15:06.039514 ===================================
7078 20:15:06.042940 LPDDR4 DRAM CONFIGURATION
7079 20:15:06.046719 ===================================
7080 20:15:06.046852 EX_ROW_EN[0] = 0x0
7081 20:15:06.049435 EX_ROW_EN[1] = 0x0
7082 20:15:06.049558 LP4Y_EN = 0x0
7083 20:15:06.053228 WORK_FSP = 0x1
7084 20:15:06.056229 WL = 0x5
7085 20:15:06.056353 RL = 0x5
7086 20:15:06.059879 BL = 0x2
7087 20:15:06.060008 RPST = 0x0
7088 20:15:06.062908 RD_PRE = 0x0
7089 20:15:06.063037 WR_PRE = 0x1
7090 20:15:06.067262 WR_PST = 0x1
7091 20:15:06.067384 DBI_WR = 0x0
7092 20:15:06.069716 DBI_RD = 0x0
7093 20:15:06.069848 OTF = 0x1
7094 20:15:06.072850 ===================================
7095 20:15:06.076338 ===================================
7096 20:15:06.079797 ANA top config
7097 20:15:06.082901 ===================================
7098 20:15:06.083026 DLL_ASYNC_EN = 0
7099 20:15:06.086221 ALL_SLAVE_EN = 0
7100 20:15:06.089377 NEW_RANK_MODE = 1
7101 20:15:06.093146 DLL_IDLE_MODE = 1
7102 20:15:06.093276 LP45_APHY_COMB_EN = 1
7103 20:15:06.096375 TX_ODT_DIS = 0
7104 20:15:06.099690 NEW_8X_MODE = 1
7105 20:15:06.102716 ===================================
7106 20:15:06.106381 ===================================
7107 20:15:06.109588 data_rate = 3200
7108 20:15:06.113061 CKR = 1
7109 20:15:06.113141 DQ_P2S_RATIO = 8
7110 20:15:06.116167 ===================================
7111 20:15:06.119495 CA_P2S_RATIO = 8
7112 20:15:06.122723 DQ_CA_OPEN = 0
7113 20:15:06.126545 DQ_SEMI_OPEN = 0
7114 20:15:06.129911 CA_SEMI_OPEN = 0
7115 20:15:06.132740 CA_FULL_RATE = 0
7116 20:15:06.132865 DQ_CKDIV4_EN = 0
7117 20:15:06.135933 CA_CKDIV4_EN = 0
7118 20:15:06.139675 CA_PREDIV_EN = 0
7119 20:15:06.142880 PH8_DLY = 12
7120 20:15:06.145917 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 20:15:06.149726 DQ_AAMCK_DIV = 4
7122 20:15:06.149819 CA_AAMCK_DIV = 4
7123 20:15:06.152740 CA_ADMCK_DIV = 4
7124 20:15:06.155913 DQ_TRACK_CA_EN = 0
7125 20:15:06.159333 CA_PICK = 1600
7126 20:15:06.162788 CA_MCKIO = 1600
7127 20:15:06.166456 MCKIO_SEMI = 0
7128 20:15:06.169649 PLL_FREQ = 3068
7129 20:15:06.169768 DQ_UI_PI_RATIO = 32
7130 20:15:06.172882 CA_UI_PI_RATIO = 0
7131 20:15:06.176158 ===================================
7132 20:15:06.179879 ===================================
7133 20:15:06.182768 memory_type:LPDDR4
7134 20:15:06.186009 GP_NUM : 10
7135 20:15:06.186128 SRAM_EN : 1
7136 20:15:06.190223 MD32_EN : 0
7137 20:15:06.192964 ===================================
7138 20:15:06.195929 [ANA_INIT] >>>>>>>>>>>>>>
7139 20:15:06.196050 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 20:15:06.199275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 20:15:06.202654 ===================================
7142 20:15:06.207406 data_rate = 3200,PCW = 0X7600
7143 20:15:06.209514 ===================================
7144 20:15:06.212962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 20:15:06.219969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 20:15:06.226033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 20:15:06.229378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 20:15:06.233029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 20:15:06.235991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 20:15:06.239756 [ANA_INIT] flow start
7151 20:15:06.239836 [ANA_INIT] PLL >>>>>>>>
7152 20:15:06.242261 [ANA_INIT] PLL <<<<<<<<
7153 20:15:06.245848 [ANA_INIT] MIDPI >>>>>>>>
7154 20:15:06.245927 [ANA_INIT] MIDPI <<<<<<<<
7155 20:15:06.249201 [ANA_INIT] DLL >>>>>>>>
7156 20:15:06.252919 [ANA_INIT] DLL <<<<<<<<
7157 20:15:06.252998 [ANA_INIT] flow end
7158 20:15:06.259161 ============ LP4 DIFF to SE enter ============
7159 20:15:06.262513 ============ LP4 DIFF to SE exit ============
7160 20:15:06.266054 [ANA_INIT] <<<<<<<<<<<<<
7161 20:15:06.269186 [Flow] Enable top DCM control >>>>>
7162 20:15:06.272516 [Flow] Enable top DCM control <<<<<
7163 20:15:06.272596 Enable DLL master slave shuffle
7164 20:15:06.279596 ==============================================================
7165 20:15:06.282403 Gating Mode config
7166 20:15:06.286163 ==============================================================
7167 20:15:06.289253 Config description:
7168 20:15:06.299340 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 20:15:06.305941 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 20:15:06.309742 SELPH_MODE 0: By rank 1: By Phase
7171 20:15:06.316302 ==============================================================
7172 20:15:06.319651 GAT_TRACK_EN = 1
7173 20:15:06.322714 RX_GATING_MODE = 2
7174 20:15:06.322793 RX_GATING_TRACK_MODE = 2
7175 20:15:06.325935 SELPH_MODE = 1
7176 20:15:06.329333 PICG_EARLY_EN = 1
7177 20:15:06.333234 VALID_LAT_VALUE = 1
7178 20:15:06.339135 ==============================================================
7179 20:15:06.342538 Enter into Gating configuration >>>>
7180 20:15:06.345740 Exit from Gating configuration <<<<
7181 20:15:06.350133 Enter into DVFS_PRE_config >>>>>
7182 20:15:06.359394 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 20:15:06.363177 Exit from DVFS_PRE_config <<<<<
7184 20:15:06.365852 Enter into PICG configuration >>>>
7185 20:15:06.369121 Exit from PICG configuration <<<<
7186 20:15:06.372870 [RX_INPUT] configuration >>>>>
7187 20:15:06.375741 [RX_INPUT] configuration <<<<<
7188 20:15:06.380037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 20:15:06.386275 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 20:15:06.392914 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 20:15:06.399758 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 20:15:06.402791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 20:15:06.409693 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 20:15:06.412494 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 20:15:06.419894 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 20:15:06.423465 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 20:15:06.425868 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 20:15:06.429209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 20:15:06.436448 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 20:15:06.439317 ===================================
7201 20:15:06.439438 LPDDR4 DRAM CONFIGURATION
7202 20:15:06.442983 ===================================
7203 20:15:06.446245 EX_ROW_EN[0] = 0x0
7204 20:15:06.449837 EX_ROW_EN[1] = 0x0
7205 20:15:06.449958 LP4Y_EN = 0x0
7206 20:15:06.452764 WORK_FSP = 0x1
7207 20:15:06.452883 WL = 0x5
7208 20:15:06.455958 RL = 0x5
7209 20:15:06.456079 BL = 0x2
7210 20:15:06.459149 RPST = 0x0
7211 20:15:06.459269 RD_PRE = 0x0
7212 20:15:06.462574 WR_PRE = 0x1
7213 20:15:06.462696 WR_PST = 0x1
7214 20:15:06.465815 DBI_WR = 0x0
7215 20:15:06.465935 DBI_RD = 0x0
7216 20:15:06.469542 OTF = 0x1
7217 20:15:06.472436 ===================================
7218 20:15:06.475810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 20:15:06.480292 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 20:15:06.486036 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 20:15:06.489544 ===================================
7222 20:15:06.489664 LPDDR4 DRAM CONFIGURATION
7223 20:15:06.492530 ===================================
7224 20:15:06.496339 EX_ROW_EN[0] = 0x10
7225 20:15:06.496460 EX_ROW_EN[1] = 0x0
7226 20:15:06.499291 LP4Y_EN = 0x0
7227 20:15:06.499408 WORK_FSP = 0x1
7228 20:15:06.502606 WL = 0x5
7229 20:15:06.502727 RL = 0x5
7230 20:15:06.506043 BL = 0x2
7231 20:15:06.509855 RPST = 0x0
7232 20:15:06.509971 RD_PRE = 0x0
7233 20:15:06.512801 WR_PRE = 0x1
7234 20:15:06.512919 WR_PST = 0x1
7235 20:15:06.516188 DBI_WR = 0x0
7236 20:15:06.516306 DBI_RD = 0x0
7237 20:15:06.519561 OTF = 0x1
7238 20:15:06.522643 ===================================
7239 20:15:06.525860 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 20:15:06.530100 ==
7241 20:15:06.530220 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 20:15:06.536425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 20:15:06.536547 ==
7244 20:15:06.539322 [Duty_Offset_Calibration]
7245 20:15:06.539439 B0:2 B1:-1 CA:1
7246 20:15:06.539551
7247 20:15:06.543159 [DutyScan_Calibration_Flow] k_type=0
7248 20:15:06.552418
7249 20:15:06.552538 ==CLK 0==
7250 20:15:06.555109 Final CLK duty delay cell = -4
7251 20:15:06.558322 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7252 20:15:06.561865 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7253 20:15:06.565406 [-4] AVG Duty = 4937%(X100)
7254 20:15:06.565525
7255 20:15:06.568086 CH0 CLK Duty spec in!! Max-Min= 187%
7256 20:15:06.572249 [DutyScan_Calibration_Flow] ====Done====
7257 20:15:06.572366
7258 20:15:06.574873 [DutyScan_Calibration_Flow] k_type=1
7259 20:15:06.591188
7260 20:15:06.591307 ==DQS 0 ==
7261 20:15:06.594504 Final DQS duty delay cell = 0
7262 20:15:06.597972 [0] MAX Duty = 5125%(X100), DQS PI = 56
7263 20:15:06.601053 [0] MIN Duty = 5000%(X100), DQS PI = 16
7264 20:15:06.604703 [0] AVG Duty = 5062%(X100)
7265 20:15:06.604823
7266 20:15:06.604933 ==DQS 1 ==
7267 20:15:06.607554 Final DQS duty delay cell = -4
7268 20:15:06.611181 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7269 20:15:06.614617 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7270 20:15:06.617714 [-4] AVG Duty = 5046%(X100)
7271 20:15:06.617833
7272 20:15:06.622712 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7273 20:15:06.622831
7274 20:15:06.625188 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7275 20:15:06.628603 [DutyScan_Calibration_Flow] ====Done====
7276 20:15:06.628720
7277 20:15:06.631515 [DutyScan_Calibration_Flow] k_type=3
7278 20:15:06.648635
7279 20:15:06.648754 ==DQM 0 ==
7280 20:15:06.652271 Final DQM duty delay cell = 0
7281 20:15:06.655693 [0] MAX Duty = 5000%(X100), DQS PI = 20
7282 20:15:06.658706 [0] MIN Duty = 4875%(X100), DQS PI = 4
7283 20:15:06.658825 [0] AVG Duty = 4937%(X100)
7284 20:15:06.661926
7285 20:15:06.662042 ==DQM 1 ==
7286 20:15:06.665594 Final DQM duty delay cell = 0
7287 20:15:06.668642 [0] MAX Duty = 5187%(X100), DQS PI = 58
7288 20:15:06.671999 [0] MIN Duty = 4969%(X100), DQS PI = 20
7289 20:15:06.672122 [0] AVG Duty = 5078%(X100)
7290 20:15:06.675230
7291 20:15:06.678839 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7292 20:15:06.678958
7293 20:15:06.681914 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7294 20:15:06.685488 [DutyScan_Calibration_Flow] ====Done====
7295 20:15:06.685608
7296 20:15:06.688359 [DutyScan_Calibration_Flow] k_type=2
7297 20:15:06.704776
7298 20:15:06.704897 ==DQ 0 ==
7299 20:15:06.708137 Final DQ duty delay cell = -4
7300 20:15:06.711490 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7301 20:15:06.714994 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7302 20:15:06.718226 [-4] AVG Duty = 4922%(X100)
7303 20:15:06.718355
7304 20:15:06.718486 ==DQ 1 ==
7305 20:15:06.722056 Final DQ duty delay cell = 0
7306 20:15:06.725020 [0] MAX Duty = 5031%(X100), DQS PI = 38
7307 20:15:06.728401 [0] MIN Duty = 4907%(X100), DQS PI = 18
7308 20:15:06.728521 [0] AVG Duty = 4969%(X100)
7309 20:15:06.731566
7310 20:15:06.734931 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7311 20:15:06.735054
7312 20:15:06.738454 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7313 20:15:06.741806 [DutyScan_Calibration_Flow] ====Done====
7314 20:15:06.741928 ==
7315 20:15:06.745273 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 20:15:06.748239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 20:15:06.748365 ==
7318 20:15:06.751756 [Duty_Offset_Calibration]
7319 20:15:06.751876 B0:1 B1:1 CA:2
7320 20:15:06.751989
7321 20:15:06.755263 [DutyScan_Calibration_Flow] k_type=0
7322 20:15:06.765256
7323 20:15:06.765377 ==CLK 0==
7324 20:15:06.768932 Final CLK duty delay cell = 0
7325 20:15:06.772522 [0] MAX Duty = 5187%(X100), DQS PI = 24
7326 20:15:06.775472 [0] MIN Duty = 4938%(X100), DQS PI = 48
7327 20:15:06.775594 [0] AVG Duty = 5062%(X100)
7328 20:15:06.775707
7329 20:15:06.778698 CH1 CLK Duty spec in!! Max-Min= 249%
7330 20:15:06.785589 [DutyScan_Calibration_Flow] ====Done====
7331 20:15:06.785710
7332 20:15:06.788987 [DutyScan_Calibration_Flow] k_type=1
7333 20:15:06.805112
7334 20:15:06.805235 ==DQS 0 ==
7335 20:15:06.808567 Final DQS duty delay cell = 0
7336 20:15:06.811962 [0] MAX Duty = 5062%(X100), DQS PI = 22
7337 20:15:06.815636 [0] MIN Duty = 4813%(X100), DQS PI = 52
7338 20:15:06.818279 [0] AVG Duty = 4937%(X100)
7339 20:15:06.818406
7340 20:15:06.818552 ==DQS 1 ==
7341 20:15:06.821705 Final DQS duty delay cell = 0
7342 20:15:06.825680 [0] MAX Duty = 5062%(X100), DQS PI = 58
7343 20:15:06.828748 [0] MIN Duty = 4938%(X100), DQS PI = 12
7344 20:15:06.828869 [0] AVG Duty = 5000%(X100)
7345 20:15:06.832184
7346 20:15:06.835310 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7347 20:15:06.835431
7348 20:15:06.838897 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7349 20:15:06.841895 [DutyScan_Calibration_Flow] ====Done====
7350 20:15:06.842017
7351 20:15:06.845195 [DutyScan_Calibration_Flow] k_type=3
7352 20:15:06.862496
7353 20:15:06.862617 ==DQM 0 ==
7354 20:15:06.865614 Final DQM duty delay cell = 0
7355 20:15:06.868934 [0] MAX Duty = 5156%(X100), DQS PI = 20
7356 20:15:06.872067 [0] MIN Duty = 4813%(X100), DQS PI = 50
7357 20:15:06.872186 [0] AVG Duty = 4984%(X100)
7358 20:15:06.875364
7359 20:15:06.875483 ==DQM 1 ==
7360 20:15:06.879331 Final DQM duty delay cell = 0
7361 20:15:06.882296 [0] MAX Duty = 5125%(X100), DQS PI = 8
7362 20:15:06.886156 [0] MIN Duty = 4907%(X100), DQS PI = 20
7363 20:15:06.886276 [0] AVG Duty = 5016%(X100)
7364 20:15:06.888796
7365 20:15:06.892498 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7366 20:15:06.892618
7367 20:15:06.896230 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7368 20:15:06.898944 [DutyScan_Calibration_Flow] ====Done====
7369 20:15:06.899064
7370 20:15:06.901981 [DutyScan_Calibration_Flow] k_type=2
7371 20:15:06.918820
7372 20:15:06.918942 ==DQ 0 ==
7373 20:15:06.922731 Final DQ duty delay cell = 0
7374 20:15:06.925441 [0] MAX Duty = 5124%(X100), DQS PI = 20
7375 20:15:06.929133 [0] MIN Duty = 4907%(X100), DQS PI = 52
7376 20:15:06.929254 [0] AVG Duty = 5015%(X100)
7377 20:15:06.929363
7378 20:15:06.932256 ==DQ 1 ==
7379 20:15:06.935664 Final DQ duty delay cell = 0
7380 20:15:06.939221 [0] MAX Duty = 5124%(X100), DQS PI = 42
7381 20:15:06.942719 [0] MIN Duty = 5031%(X100), DQS PI = 0
7382 20:15:06.942840 [0] AVG Duty = 5077%(X100)
7383 20:15:06.942951
7384 20:15:06.946241 CH1 DQ 0 Duty spec in!! Max-Min= 217%
7385 20:15:06.946359
7386 20:15:06.949375 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7387 20:15:06.955666 [DutyScan_Calibration_Flow] ====Done====
7388 20:15:06.959659 nWR fixed to 30
7389 20:15:06.959780 [ModeRegInit_LP4] CH0 RK0
7390 20:15:06.962493 [ModeRegInit_LP4] CH0 RK1
7391 20:15:06.965769 [ModeRegInit_LP4] CH1 RK0
7392 20:15:06.965888 [ModeRegInit_LP4] CH1 RK1
7393 20:15:06.968830 match AC timing 5
7394 20:15:06.972929 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 20:15:06.976310 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 20:15:06.982296 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 20:15:06.985665 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 20:15:06.992801 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 20:15:06.992924 [MiockJmeterHQA]
7400 20:15:06.993035
7401 20:15:06.995535 [DramcMiockJmeter] u1RxGatingPI = 0
7402 20:15:06.998813 0 : 4257, 4031
7403 20:15:06.998936 4 : 4365, 4137
7404 20:15:06.999051 8 : 4253, 4027
7405 20:15:07.002768 12 : 4253, 4027
7406 20:15:07.002886 16 : 4252, 4027
7407 20:15:07.005823 20 : 4252, 4027
7408 20:15:07.005944 24 : 4255, 4029
7409 20:15:07.008982 28 : 4253, 4026
7410 20:15:07.009103 32 : 4252, 4027
7411 20:15:07.009215 36 : 4365, 4140
7412 20:15:07.012532 40 : 4252, 4027
7413 20:15:07.012652 44 : 4255, 4029
7414 20:15:07.016167 48 : 4252, 4027
7415 20:15:07.016289 52 : 4363, 4140
7416 20:15:07.019416 56 : 4252, 4027
7417 20:15:07.019537 60 : 4360, 4138
7418 20:15:07.019649 64 : 4249, 4027
7419 20:15:07.023088 68 : 4250, 4027
7420 20:15:07.023210 72 : 4253, 4029
7421 20:15:07.026147 76 : 4252, 4029
7422 20:15:07.026269 80 : 4360, 4138
7423 20:15:07.029044 84 : 4249, 4027
7424 20:15:07.029164 88 : 4361, 4137
7425 20:15:07.029276 92 : 4250, 4027
7426 20:15:07.032344 96 : 4250, 3244
7427 20:15:07.032466 100 : 4250, 0
7428 20:15:07.035922 104 : 4253, 0
7429 20:15:07.036046 108 : 4360, 0
7430 20:15:07.036161 112 : 4250, 0
7431 20:15:07.039581 116 : 4250, 0
7432 20:15:07.039704 120 : 4249, 0
7433 20:15:07.042606 124 : 4361, 0
7434 20:15:07.042729 128 : 4360, 0
7435 20:15:07.042842 132 : 4250, 0
7436 20:15:07.045983 136 : 4250, 0
7437 20:15:07.046104 140 : 4363, 0
7438 20:15:07.049213 144 : 4250, 0
7439 20:15:07.049335 148 : 4250, 0
7440 20:15:07.049449 152 : 4250, 0
7441 20:15:07.052578 156 : 4253, 0
7442 20:15:07.052699 160 : 4250, 0
7443 20:15:07.057320 164 : 4250, 0
7444 20:15:07.057442 168 : 4253, 0
7445 20:15:07.057553 172 : 4249, 0
7446 20:15:07.059350 176 : 4361, 0
7447 20:15:07.059471 180 : 4250, 0
7448 20:15:07.059584 184 : 4250, 0
7449 20:15:07.062579 188 : 4360, 0
7450 20:15:07.062701 192 : 4250, 0
7451 20:15:07.065926 196 : 4250, 0
7452 20:15:07.066048 200 : 4250, 0
7453 20:15:07.066162 204 : 4250, 0
7454 20:15:07.069066 208 : 4253, 0
7455 20:15:07.069187 212 : 4360, 95
7456 20:15:07.072598 216 : 4250, 3723
7457 20:15:07.072720 220 : 4361, 4137
7458 20:15:07.076422 224 : 4360, 4138
7459 20:15:07.076543 228 : 4247, 4024
7460 20:15:07.079029 232 : 4363, 4140
7461 20:15:07.079152 236 : 4250, 4026
7462 20:15:07.079263 240 : 4250, 4027
7463 20:15:07.082814 244 : 4249, 4027
7464 20:15:07.082937 248 : 4252, 4029
7465 20:15:07.086363 252 : 4250, 4026
7466 20:15:07.086530 256 : 4250, 4027
7467 20:15:07.089442 260 : 4252, 4027
7468 20:15:07.089564 264 : 4252, 4029
7469 20:15:07.092330 268 : 4250, 4026
7470 20:15:07.092451 272 : 4361, 4137
7471 20:15:07.096080 276 : 4360, 4138
7472 20:15:07.096201 280 : 4250, 4027
7473 20:15:07.098993 284 : 4363, 4140
7474 20:15:07.099115 288 : 4250, 4026
7475 20:15:07.102290 292 : 4250, 4027
7476 20:15:07.102434 296 : 4250, 4027
7477 20:15:07.102563 300 : 4252, 4029
7478 20:15:07.106065 304 : 4250, 4026
7479 20:15:07.106190 308 : 4250, 4027
7480 20:15:07.109300 312 : 4251, 4027
7481 20:15:07.109421 316 : 4252, 4029
7482 20:15:07.112198 320 : 4250, 4026
7483 20:15:07.112318 324 : 4361, 4137
7484 20:15:07.115660 328 : 4361, 4138
7485 20:15:07.115781 332 : 4250, 2938
7486 20:15:07.119066 336 : 4363, 61
7487 20:15:07.119186
7488 20:15:07.119297 MIOCK jitter meter ch=0
7489 20:15:07.119404
7490 20:15:07.122526 1T = (336-100) = 236 dly cells
7491 20:15:07.129257 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7492 20:15:07.129382 ==
7493 20:15:07.132510 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 20:15:07.135612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 20:15:07.135733 ==
7496 20:15:07.142633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 20:15:07.145878 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 20:15:07.148825 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 20:15:07.155354 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 20:15:07.165874 [CA 0] Center 44 (14~75) winsize 62
7501 20:15:07.169252 [CA 1] Center 44 (13~75) winsize 63
7502 20:15:07.172307 [CA 2] Center 40 (11~69) winsize 59
7503 20:15:07.175438 [CA 3] Center 39 (10~69) winsize 60
7504 20:15:07.179381 [CA 4] Center 38 (8~68) winsize 61
7505 20:15:07.182241 [CA 5] Center 37 (7~67) winsize 61
7506 20:15:07.182360
7507 20:15:07.187846 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 20:15:07.187966
7509 20:15:07.188907 [CATrainingPosCal] consider 1 rank data
7510 20:15:07.192713 u2DelayCellTimex100 = 275/100 ps
7511 20:15:07.196691 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7512 20:15:07.203122 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7513 20:15:07.205603 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7514 20:15:07.209445 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7515 20:15:07.212384 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7516 20:15:07.216103 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 20:15:07.216223
7518 20:15:07.218770 CA PerBit enable=1, Macro0, CA PI delay=37
7519 20:15:07.218891
7520 20:15:07.222697 [CBTSetCACLKResult] CA Dly = 37
7521 20:15:07.226250 CS Dly: 10 (0~41)
7522 20:15:07.228962 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 20:15:07.232656 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 20:15:07.232776 ==
7525 20:15:07.235475 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 20:15:07.239492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 20:15:07.242220 ==
7528 20:15:07.246100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 20:15:07.249203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 20:15:07.256125 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 20:15:07.258937 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 20:15:07.269141 [CA 0] Center 43 (13~74) winsize 62
7533 20:15:07.272603 [CA 1] Center 43 (13~74) winsize 62
7534 20:15:07.276624 [CA 2] Center 39 (10~69) winsize 60
7535 20:15:07.279344 [CA 3] Center 38 (9~68) winsize 60
7536 20:15:07.282469 [CA 4] Center 37 (7~67) winsize 61
7537 20:15:07.286424 [CA 5] Center 37 (7~67) winsize 61
7538 20:15:07.286557
7539 20:15:07.290684 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 20:15:07.290803
7541 20:15:07.292421 [CATrainingPosCal] consider 2 rank data
7542 20:15:07.296197 u2DelayCellTimex100 = 275/100 ps
7543 20:15:07.299333 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7544 20:15:07.307748 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7545 20:15:07.309648 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7546 20:15:07.312563 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7547 20:15:07.315763 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7548 20:15:07.320074 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7549 20:15:07.320194
7550 20:15:07.322757 CA PerBit enable=1, Macro0, CA PI delay=37
7551 20:15:07.322876
7552 20:15:07.326109 [CBTSetCACLKResult] CA Dly = 37
7553 20:15:07.329700 CS Dly: 11 (0~43)
7554 20:15:07.332710 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 20:15:07.336555 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 20:15:07.336676
7557 20:15:07.339110 ----->DramcWriteLeveling(PI) begin...
7558 20:15:07.339232 ==
7559 20:15:07.342423 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 20:15:07.349153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 20:15:07.349274 ==
7562 20:15:07.352435 Write leveling (Byte 0): 30 => 30
7563 20:15:07.352559 Write leveling (Byte 1): 27 => 27
7564 20:15:07.355801 DramcWriteLeveling(PI) end<-----
7565 20:15:07.355922
7566 20:15:07.356031 ==
7567 20:15:07.360108 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 20:15:07.366243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 20:15:07.366366 ==
7570 20:15:07.369501 [Gating] SW mode calibration
7571 20:15:07.375963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 20:15:07.379654 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 20:15:07.386890 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 20:15:07.389519 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 20:15:07.392758 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 20:15:07.396386 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 20:15:07.402655 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 20:15:07.406295 1 4 20 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
7579 20:15:07.409689 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
7580 20:15:07.415889 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 20:15:07.419437 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 20:15:07.422693 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 20:15:07.429955 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 20:15:07.432823 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 20:15:07.436673 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7586 20:15:07.442589 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (0 1) (0 0)
7587 20:15:07.446167 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7588 20:15:07.450076 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 20:15:07.456035 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 20:15:07.459303 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 20:15:07.462739 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 20:15:07.469448 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 20:15:07.472528 1 6 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7594 20:15:07.476111 1 6 20 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
7595 20:15:07.482860 1 6 24 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
7596 20:15:07.486090 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 20:15:07.489110 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 20:15:07.496094 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 20:15:07.499389 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 20:15:07.502309 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 20:15:07.509148 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 20:15:07.512260 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7603 20:15:07.515866 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 20:15:07.523010 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 20:15:07.525595 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 20:15:07.528887 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 20:15:07.532559 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 20:15:07.539144 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 20:15:07.542530 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 20:15:07.545635 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 20:15:07.552209 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 20:15:07.555753 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 20:15:07.559161 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 20:15:07.565890 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 20:15:07.568738 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 20:15:07.572709 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 20:15:07.579077 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 20:15:07.582208 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7619 20:15:07.585281 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7620 20:15:07.588717 Total UI for P1: 0, mck2ui 16
7621 20:15:07.592494 best dqsien dly found for B0: ( 1, 9, 18)
7622 20:15:07.598969 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 20:15:07.599090 Total UI for P1: 0, mck2ui 16
7624 20:15:07.602218 best dqsien dly found for B1: ( 1, 9, 22)
7625 20:15:07.609563 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7626 20:15:07.612069 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7627 20:15:07.612189
7628 20:15:07.616030 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7629 20:15:07.619435 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7630 20:15:07.622932 [Gating] SW calibration Done
7631 20:15:07.623055 ==
7632 20:15:07.625619 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 20:15:07.629379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 20:15:07.629502 ==
7635 20:15:07.632460 RX Vref Scan: 0
7636 20:15:07.632580
7637 20:15:07.632687 RX Vref 0 -> 0, step: 1
7638 20:15:07.632797
7639 20:15:07.635653 RX Delay 0 -> 252, step: 8
7640 20:15:07.638799 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7641 20:15:07.642318 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7642 20:15:07.648967 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7643 20:15:07.652357 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7644 20:15:07.655550 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7645 20:15:07.659914 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7646 20:15:07.662425 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7647 20:15:07.669065 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7648 20:15:07.673232 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7649 20:15:07.675777 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7650 20:15:07.678955 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7651 20:15:07.682098 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7652 20:15:07.689161 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7653 20:15:07.692834 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7654 20:15:07.695773 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7655 20:15:07.699012 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7656 20:15:07.699133 ==
7657 20:15:07.702134 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 20:15:07.708754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 20:15:07.708877 ==
7660 20:15:07.708988 DQS Delay:
7661 20:15:07.712108 DQS0 = 0, DQS1 = 0
7662 20:15:07.712228 DQM Delay:
7663 20:15:07.712338 DQM0 = 132, DQM1 = 123
7664 20:15:07.715234 DQ Delay:
7665 20:15:07.718839 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7666 20:15:07.722335 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7667 20:15:07.725551 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7668 20:15:07.729062 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7669 20:15:07.729185
7670 20:15:07.729295
7671 20:15:07.729402 ==
7672 20:15:07.731935 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 20:15:07.735472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 20:15:07.739449 ==
7675 20:15:07.739569
7676 20:15:07.739679
7677 20:15:07.739788 TX Vref Scan disable
7678 20:15:07.742319 == TX Byte 0 ==
7679 20:15:07.745520 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7680 20:15:07.749390 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7681 20:15:07.752172 == TX Byte 1 ==
7682 20:15:07.755412 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7683 20:15:07.759058 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7684 20:15:07.759179 ==
7685 20:15:07.761953 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 20:15:07.768484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 20:15:07.768608 ==
7688 20:15:07.780794
7689 20:15:07.784560 TX Vref early break, caculate TX vref
7690 20:15:07.787752 TX Vref=16, minBit 1, minWin=20, winSum=356
7691 20:15:07.791595 TX Vref=18, minBit 7, minWin=21, winSum=364
7692 20:15:07.794073 TX Vref=20, minBit 1, minWin=21, winSum=370
7693 20:15:07.797681 TX Vref=22, minBit 6, minWin=22, winSum=383
7694 20:15:07.800967 TX Vref=24, minBit 1, minWin=23, winSum=395
7695 20:15:07.808412 TX Vref=26, minBit 1, minWin=24, winSum=407
7696 20:15:07.810780 TX Vref=28, minBit 7, minWin=24, winSum=410
7697 20:15:07.814549 TX Vref=30, minBit 1, minWin=25, winSum=417
7698 20:15:07.818026 TX Vref=32, minBit 0, minWin=24, winSum=407
7699 20:15:07.820959 TX Vref=34, minBit 0, minWin=24, winSum=395
7700 20:15:07.827634 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 30
7701 20:15:07.827749
7702 20:15:07.830882 Final TX Range 0 Vref 30
7703 20:15:07.831002
7704 20:15:07.831110 ==
7705 20:15:07.834268 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 20:15:07.837645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 20:15:07.837767 ==
7708 20:15:07.837879
7709 20:15:07.837985
7710 20:15:07.840955 TX Vref Scan disable
7711 20:15:07.848323 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7712 20:15:07.848445 == TX Byte 0 ==
7713 20:15:07.851035 u2DelayCellOfst[0]=14 cells (4 PI)
7714 20:15:07.854355 u2DelayCellOfst[1]=21 cells (6 PI)
7715 20:15:07.858102 u2DelayCellOfst[2]=10 cells (3 PI)
7716 20:15:07.860789 u2DelayCellOfst[3]=14 cells (4 PI)
7717 20:15:07.864323 u2DelayCellOfst[4]=10 cells (3 PI)
7718 20:15:07.868263 u2DelayCellOfst[5]=0 cells (0 PI)
7719 20:15:07.868382 u2DelayCellOfst[6]=21 cells (6 PI)
7720 20:15:07.870924 u2DelayCellOfst[7]=17 cells (5 PI)
7721 20:15:07.877534 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7722 20:15:07.880961 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7723 20:15:07.881084 == TX Byte 1 ==
7724 20:15:07.884552 u2DelayCellOfst[8]=0 cells (0 PI)
7725 20:15:07.887676 u2DelayCellOfst[9]=3 cells (1 PI)
7726 20:15:07.891464 u2DelayCellOfst[10]=7 cells (2 PI)
7727 20:15:07.894828 u2DelayCellOfst[11]=0 cells (0 PI)
7728 20:15:07.898155 u2DelayCellOfst[12]=14 cells (4 PI)
7729 20:15:07.900791 u2DelayCellOfst[13]=10 cells (3 PI)
7730 20:15:07.904597 u2DelayCellOfst[14]=17 cells (5 PI)
7731 20:15:07.907889 u2DelayCellOfst[15]=10 cells (3 PI)
7732 20:15:07.911073 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7733 20:15:07.914208 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7734 20:15:07.917591 DramC Write-DBI on
7735 20:15:07.917711 ==
7736 20:15:07.920832 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 20:15:07.924655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 20:15:07.924777 ==
7739 20:15:07.924887
7740 20:15:07.924994
7741 20:15:07.927953 TX Vref Scan disable
7742 20:15:07.930963 == TX Byte 0 ==
7743 20:15:07.934016 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
7744 20:15:07.937415 == TX Byte 1 ==
7745 20:15:07.940701 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7746 20:15:07.940821 DramC Write-DBI off
7747 20:15:07.940930
7748 20:15:07.944520 [DATLAT]
7749 20:15:07.944639 Freq=1600, CH0 RK0
7750 20:15:07.944750
7751 20:15:07.947458 DATLAT Default: 0xf
7752 20:15:07.947576 0, 0xFFFF, sum = 0
7753 20:15:07.951580 1, 0xFFFF, sum = 0
7754 20:15:07.951704 2, 0xFFFF, sum = 0
7755 20:15:07.954594 3, 0xFFFF, sum = 0
7756 20:15:07.954715 4, 0xFFFF, sum = 0
7757 20:15:07.957417 5, 0xFFFF, sum = 0
7758 20:15:07.957542 6, 0xFFFF, sum = 0
7759 20:15:07.961237 7, 0xFFFF, sum = 0
7760 20:15:07.961362 8, 0xFFFF, sum = 0
7761 20:15:07.964923 9, 0xFFFF, sum = 0
7762 20:15:07.967710 10, 0xFFFF, sum = 0
7763 20:15:07.967831 11, 0xFFFF, sum = 0
7764 20:15:07.971066 12, 0xFFFF, sum = 0
7765 20:15:07.971188 13, 0xFFFF, sum = 0
7766 20:15:07.974916 14, 0x0, sum = 1
7767 20:15:07.975039 15, 0x0, sum = 2
7768 20:15:07.977697 16, 0x0, sum = 3
7769 20:15:07.977818 17, 0x0, sum = 4
7770 20:15:07.977932 best_step = 15
7771 20:15:07.978040
7772 20:15:07.980909 ==
7773 20:15:07.984470 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 20:15:07.987878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 20:15:07.987999 ==
7776 20:15:07.988110 RX Vref Scan: 1
7777 20:15:07.988216
7778 20:15:07.990824 Set Vref Range= 24 -> 127
7779 20:15:07.990942
7780 20:15:07.994417 RX Vref 24 -> 127, step: 1
7781 20:15:07.994534
7782 20:15:07.997528 RX Delay 11 -> 252, step: 4
7783 20:15:07.997646
7784 20:15:08.000850 Set Vref, RX VrefLevel [Byte0]: 24
7785 20:15:08.004267 [Byte1]: 24
7786 20:15:08.004390
7787 20:15:08.007753 Set Vref, RX VrefLevel [Byte0]: 25
7788 20:15:08.011249 [Byte1]: 25
7789 20:15:08.011369
7790 20:15:08.014156 Set Vref, RX VrefLevel [Byte0]: 26
7791 20:15:08.017611 [Byte1]: 26
7792 20:15:08.020706
7793 20:15:08.020823 Set Vref, RX VrefLevel [Byte0]: 27
7794 20:15:08.024639 [Byte1]: 27
7795 20:15:08.028716
7796 20:15:08.028838 Set Vref, RX VrefLevel [Byte0]: 28
7797 20:15:08.031758 [Byte1]: 28
7798 20:15:08.036007
7799 20:15:08.036127 Set Vref, RX VrefLevel [Byte0]: 29
7800 20:15:08.039488 [Byte1]: 29
7801 20:15:08.043827
7802 20:15:08.043948 Set Vref, RX VrefLevel [Byte0]: 30
7803 20:15:08.046866 [Byte1]: 30
7804 20:15:08.051364
7805 20:15:08.051478 Set Vref, RX VrefLevel [Byte0]: 31
7806 20:15:08.054557 [Byte1]: 31
7807 20:15:08.058935
7808 20:15:08.059052 Set Vref, RX VrefLevel [Byte0]: 32
7809 20:15:08.062200 [Byte1]: 32
7810 20:15:08.066780
7811 20:15:08.066894 Set Vref, RX VrefLevel [Byte0]: 33
7812 20:15:08.069866 [Byte1]: 33
7813 20:15:08.074548
7814 20:15:08.074669 Set Vref, RX VrefLevel [Byte0]: 34
7815 20:15:08.078266 [Byte1]: 34
7816 20:15:08.081481
7817 20:15:08.081574 Set Vref, RX VrefLevel [Byte0]: 35
7818 20:15:08.085032 [Byte1]: 35
7819 20:15:08.089423
7820 20:15:08.089544 Set Vref, RX VrefLevel [Byte0]: 36
7821 20:15:08.092388 [Byte1]: 36
7822 20:15:08.096935
7823 20:15:08.097053 Set Vref, RX VrefLevel [Byte0]: 37
7824 20:15:08.100190 [Byte1]: 37
7825 20:15:08.104957
7826 20:15:08.105079 Set Vref, RX VrefLevel [Byte0]: 38
7827 20:15:08.108152 [Byte1]: 38
7828 20:15:08.112018
7829 20:15:08.112137 Set Vref, RX VrefLevel [Byte0]: 39
7830 20:15:08.115695 [Byte1]: 39
7831 20:15:08.120163
7832 20:15:08.120280 Set Vref, RX VrefLevel [Byte0]: 40
7833 20:15:08.123275 [Byte1]: 40
7834 20:15:08.127707
7835 20:15:08.127828 Set Vref, RX VrefLevel [Byte0]: 41
7836 20:15:08.130736 [Byte1]: 41
7837 20:15:08.135315
7838 20:15:08.135434 Set Vref, RX VrefLevel [Byte0]: 42
7839 20:15:08.138495 [Byte1]: 42
7840 20:15:08.142618
7841 20:15:08.142738 Set Vref, RX VrefLevel [Byte0]: 43
7842 20:15:08.146267 [Byte1]: 43
7843 20:15:08.150343
7844 20:15:08.150504 Set Vref, RX VrefLevel [Byte0]: 44
7845 20:15:08.153346 [Byte1]: 44
7846 20:15:08.157861
7847 20:15:08.157979 Set Vref, RX VrefLevel [Byte0]: 45
7848 20:15:08.161113 [Byte1]: 45
7849 20:15:08.166266
7850 20:15:08.166380 Set Vref, RX VrefLevel [Byte0]: 46
7851 20:15:08.168961 [Byte1]: 46
7852 20:15:08.173391
7853 20:15:08.173509 Set Vref, RX VrefLevel [Byte0]: 47
7854 20:15:08.176631 [Byte1]: 47
7855 20:15:08.180948
7856 20:15:08.181065 Set Vref, RX VrefLevel [Byte0]: 48
7857 20:15:08.184431 [Byte1]: 48
7858 20:15:08.188205
7859 20:15:08.188320 Set Vref, RX VrefLevel [Byte0]: 49
7860 20:15:08.191657 [Byte1]: 49
7861 20:15:08.195975
7862 20:15:08.196095 Set Vref, RX VrefLevel [Byte0]: 50
7863 20:15:08.199396 [Byte1]: 50
7864 20:15:08.203644
7865 20:15:08.203763 Set Vref, RX VrefLevel [Byte0]: 51
7866 20:15:08.207131 [Byte1]: 51
7867 20:15:08.211997
7868 20:15:08.212116 Set Vref, RX VrefLevel [Byte0]: 52
7869 20:15:08.214326 [Byte1]: 52
7870 20:15:08.218866
7871 20:15:08.218984 Set Vref, RX VrefLevel [Byte0]: 53
7872 20:15:08.221998 [Byte1]: 53
7873 20:15:08.226282
7874 20:15:08.226422 Set Vref, RX VrefLevel [Byte0]: 54
7875 20:15:08.229755 [Byte1]: 54
7876 20:15:08.233795
7877 20:15:08.233913 Set Vref, RX VrefLevel [Byte0]: 55
7878 20:15:08.238313 [Byte1]: 55
7879 20:15:08.242582
7880 20:15:08.242697 Set Vref, RX VrefLevel [Byte0]: 56
7881 20:15:08.244776 [Byte1]: 56
7882 20:15:08.249950
7883 20:15:08.250074 Set Vref, RX VrefLevel [Byte0]: 57
7884 20:15:08.253579 [Byte1]: 57
7885 20:15:08.256929
7886 20:15:08.257049 Set Vref, RX VrefLevel [Byte0]: 58
7887 20:15:08.259979 [Byte1]: 58
7888 20:15:08.265333
7889 20:15:08.265452 Set Vref, RX VrefLevel [Byte0]: 59
7890 20:15:08.267675 [Byte1]: 59
7891 20:15:08.271975
7892 20:15:08.272093 Set Vref, RX VrefLevel [Byte0]: 60
7893 20:15:08.275522 [Byte1]: 60
7894 20:15:08.279608
7895 20:15:08.279728 Set Vref, RX VrefLevel [Byte0]: 61
7896 20:15:08.283192 [Byte1]: 61
7897 20:15:08.287012
7898 20:15:08.287129 Set Vref, RX VrefLevel [Byte0]: 62
7899 20:15:08.290952 [Byte1]: 62
7900 20:15:08.295370
7901 20:15:08.295490 Set Vref, RX VrefLevel [Byte0]: 63
7902 20:15:08.298219 [Byte1]: 63
7903 20:15:08.302694
7904 20:15:08.302813 Set Vref, RX VrefLevel [Byte0]: 64
7905 20:15:08.305939 [Byte1]: 64
7906 20:15:08.310131
7907 20:15:08.310212 Set Vref, RX VrefLevel [Byte0]: 65
7908 20:15:08.313435 [Byte1]: 65
7909 20:15:08.317874
7910 20:15:08.317953 Set Vref, RX VrefLevel [Byte0]: 66
7911 20:15:08.321335 [Byte1]: 66
7912 20:15:08.325888
7913 20:15:08.325967 Set Vref, RX VrefLevel [Byte0]: 67
7914 20:15:08.329611 [Byte1]: 67
7915 20:15:08.332820
7916 20:15:08.332898 Set Vref, RX VrefLevel [Byte0]: 68
7917 20:15:08.336216 [Byte1]: 68
7918 20:15:08.340891
7919 20:15:08.341012 Set Vref, RX VrefLevel [Byte0]: 69
7920 20:15:08.343670 [Byte1]: 69
7921 20:15:08.347987
7922 20:15:08.348107 Set Vref, RX VrefLevel [Byte0]: 70
7923 20:15:08.351435 [Byte1]: 70
7924 20:15:08.355713
7925 20:15:08.355825 Set Vref, RX VrefLevel [Byte0]: 71
7926 20:15:08.359387 [Byte1]: 71
7927 20:15:08.363573
7928 20:15:08.363692 Set Vref, RX VrefLevel [Byte0]: 72
7929 20:15:08.366804 [Byte1]: 72
7930 20:15:08.371151
7931 20:15:08.371270 Set Vref, RX VrefLevel [Byte0]: 73
7932 20:15:08.374576 [Byte1]: 73
7933 20:15:08.378657
7934 20:15:08.381916 Set Vref, RX VrefLevel [Byte0]: 74
7935 20:15:08.382034 [Byte1]: 74
7936 20:15:08.387079
7937 20:15:08.387199 Set Vref, RX VrefLevel [Byte0]: 75
7938 20:15:08.390329 [Byte1]: 75
7939 20:15:08.393871
7940 20:15:08.393989 Set Vref, RX VrefLevel [Byte0]: 76
7941 20:15:08.397034 [Byte1]: 76
7942 20:15:08.401404
7943 20:15:08.401524 Set Vref, RX VrefLevel [Byte0]: 77
7944 20:15:08.404691 [Byte1]: 77
7945 20:15:08.409074
7946 20:15:08.409195 Final RX Vref Byte 0 = 58 to rank0
7947 20:15:08.413022 Final RX Vref Byte 1 = 62 to rank0
7948 20:15:08.415955 Final RX Vref Byte 0 = 58 to rank1
7949 20:15:08.418998 Final RX Vref Byte 1 = 62 to rank1==
7950 20:15:08.422590 Dram Type= 6, Freq= 0, CH_0, rank 0
7951 20:15:08.429139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 20:15:08.429259 ==
7953 20:15:08.429372 DQS Delay:
7954 20:15:08.429482 DQS0 = 0, DQS1 = 0
7955 20:15:08.432665 DQM Delay:
7956 20:15:08.432783 DQM0 = 130, DQM1 = 121
7957 20:15:08.436015 DQ Delay:
7958 20:15:08.438988 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7959 20:15:08.443145 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7960 20:15:08.445722 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7961 20:15:08.448968 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7962 20:15:08.449087
7963 20:15:08.449197
7964 20:15:08.449301
7965 20:15:08.452476 [DramC_TX_OE_Calibration] TA2
7966 20:15:08.455510 Original DQ_B0 (3 6) =30, OEN = 27
7967 20:15:08.458633 Original DQ_B1 (3 6) =30, OEN = 27
7968 20:15:08.461970 24, 0x0, End_B0=24 End_B1=24
7969 20:15:08.462093 25, 0x0, End_B0=25 End_B1=25
7970 20:15:08.465838 26, 0x0, End_B0=26 End_B1=26
7971 20:15:08.468780 27, 0x0, End_B0=27 End_B1=27
7972 20:15:08.472185 28, 0x0, End_B0=28 End_B1=28
7973 20:15:08.475553 29, 0x0, End_B0=29 End_B1=29
7974 20:15:08.475674 30, 0x0, End_B0=30 End_B1=30
7975 20:15:08.478735 31, 0x4141, End_B0=30 End_B1=30
7976 20:15:08.482127 Byte0 end_step=30 best_step=27
7977 20:15:08.485740 Byte1 end_step=30 best_step=27
7978 20:15:08.488646 Byte0 TX OE(2T, 0.5T) = (3, 3)
7979 20:15:08.488766 Byte1 TX OE(2T, 0.5T) = (3, 3)
7980 20:15:08.492433
7981 20:15:08.492602
7982 20:15:08.498716 [DQSOSCAuto] RK0, (LSB)MR18= 0x1105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
7983 20:15:08.502675 CH0 RK0: MR19=303, MR18=1105
7984 20:15:08.508781 CH0_RK0: MR19=0x303, MR18=0x1105, DQSOSC=401, MR23=63, INC=22, DEC=15
7985 20:15:08.508901
7986 20:15:08.512162 ----->DramcWriteLeveling(PI) begin...
7987 20:15:08.512281 ==
7988 20:15:08.515512 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 20:15:08.519212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 20:15:08.519331 ==
7991 20:15:08.522276 Write leveling (Byte 0): 32 => 32
7992 20:15:08.525813 Write leveling (Byte 1): 29 => 29
7993 20:15:08.528996 DramcWriteLeveling(PI) end<-----
7994 20:15:08.529118
7995 20:15:08.529228 ==
7996 20:15:08.532034 Dram Type= 6, Freq= 0, CH_0, rank 1
7997 20:15:08.536246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 20:15:08.536370 ==
7999 20:15:08.539257 [Gating] SW mode calibration
8000 20:15:08.545707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8001 20:15:08.552081 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8002 20:15:08.555652 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 20:15:08.558834 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 20:15:08.565054 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8005 20:15:08.569256 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8006 20:15:08.571774 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8007 20:15:08.578937 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8008 20:15:08.581785 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 20:15:08.585225 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 20:15:08.591901 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 20:15:08.595161 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 20:15:08.599340 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8013 20:15:08.605499 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8014 20:15:08.608445 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8015 20:15:08.611840 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
8016 20:15:08.619124 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8017 20:15:08.622101 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 20:15:08.625729 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 20:15:08.629014 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 20:15:08.635581 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8021 20:15:08.638852 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8022 20:15:08.642390 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8023 20:15:08.648984 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8024 20:15:08.652438 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 20:15:08.655405 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 20:15:08.662666 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 20:15:08.665460 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 20:15:08.669219 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 20:15:08.675793 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8030 20:15:08.678671 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 20:15:08.682575 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8032 20:15:08.688906 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 20:15:08.692052 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 20:15:08.695432 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 20:15:08.702306 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 20:15:08.706094 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 20:15:08.709064 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 20:15:08.712285 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 20:15:08.718711 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 20:15:08.722184 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 20:15:08.725794 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 20:15:08.732610 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 20:15:08.735982 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 20:15:08.738946 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 20:15:08.745850 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 20:15:08.749095 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 20:15:08.752485 Total UI for P1: 0, mck2ui 16
8048 20:15:08.755828 best dqsien dly found for B0: ( 1, 9, 10)
8049 20:15:08.758896 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 20:15:08.766266 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 20:15:08.766346 Total UI for P1: 0, mck2ui 16
8052 20:15:08.772449 best dqsien dly found for B1: ( 1, 9, 18)
8053 20:15:08.776024 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8054 20:15:08.779573 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8055 20:15:08.779673
8056 20:15:08.782433 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8057 20:15:08.786613 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8058 20:15:08.788921 [Gating] SW calibration Done
8059 20:15:08.789001 ==
8060 20:15:08.792601 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 20:15:08.795411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 20:15:08.795491 ==
8063 20:15:08.798900 RX Vref Scan: 0
8064 20:15:08.798979
8065 20:15:08.799042 RX Vref 0 -> 0, step: 1
8066 20:15:08.799102
8067 20:15:08.802311 RX Delay 0 -> 252, step: 8
8068 20:15:08.806713 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8069 20:15:08.814115 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8070 20:15:08.816000 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8071 20:15:08.819092 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8072 20:15:08.822266 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8073 20:15:08.825536 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8074 20:15:08.828881 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8075 20:15:08.835975 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8076 20:15:08.838909 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8077 20:15:08.842134 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8078 20:15:08.845485 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8079 20:15:08.848937 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8080 20:15:08.855514 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8081 20:15:08.859378 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8082 20:15:08.862874 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8083 20:15:08.866263 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8084 20:15:08.866344 ==
8085 20:15:08.868965 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 20:15:08.875589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 20:15:08.875671 ==
8088 20:15:08.875734 DQS Delay:
8089 20:15:08.879043 DQS0 = 0, DQS1 = 0
8090 20:15:08.879122 DQM Delay:
8091 20:15:08.879186 DQM0 = 131, DQM1 = 123
8092 20:15:08.882226 DQ Delay:
8093 20:15:08.885515 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8094 20:15:08.888687 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8095 20:15:08.892255 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8096 20:15:08.895298 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8097 20:15:08.895378
8098 20:15:08.895442
8099 20:15:08.895500 ==
8100 20:15:08.899629 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 20:15:08.905578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 20:15:08.905660 ==
8103 20:15:08.905724
8104 20:15:08.905782
8105 20:15:08.905839 TX Vref Scan disable
8106 20:15:08.908542 == TX Byte 0 ==
8107 20:15:08.912144 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8108 20:15:08.915233 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8109 20:15:08.918526 == TX Byte 1 ==
8110 20:15:08.922500 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8111 20:15:08.925641 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8112 20:15:08.929233 ==
8113 20:15:08.931779 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 20:15:08.935435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 20:15:08.935515 ==
8116 20:15:08.948986
8117 20:15:08.952271 TX Vref early break, caculate TX vref
8118 20:15:08.955734 TX Vref=16, minBit 1, minWin=22, winSum=377
8119 20:15:08.958779 TX Vref=18, minBit 0, minWin=23, winSum=387
8120 20:15:08.962020 TX Vref=20, minBit 1, minWin=23, winSum=394
8121 20:15:08.965543 TX Vref=22, minBit 0, minWin=24, winSum=403
8122 20:15:08.969193 TX Vref=24, minBit 4, minWin=24, winSum=415
8123 20:15:08.976237 TX Vref=26, minBit 0, minWin=25, winSum=414
8124 20:15:08.978790 TX Vref=28, minBit 0, minWin=25, winSum=422
8125 20:15:08.982157 TX Vref=30, minBit 0, minWin=25, winSum=420
8126 20:15:08.985673 TX Vref=32, minBit 4, minWin=24, winSum=416
8127 20:15:08.989037 TX Vref=34, minBit 0, minWin=24, winSum=403
8128 20:15:08.992349 TX Vref=36, minBit 0, minWin=24, winSum=398
8129 20:15:08.999382 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
8130 20:15:08.999463
8131 20:15:09.002348 Final TX Range 0 Vref 28
8132 20:15:09.002467
8133 20:15:09.002530 ==
8134 20:15:09.005605 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 20:15:09.009135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 20:15:09.009215 ==
8137 20:15:09.009279
8138 20:15:09.009338
8139 20:15:09.012285 TX Vref Scan disable
8140 20:15:09.018890 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8141 20:15:09.018971 == TX Byte 0 ==
8142 20:15:09.022560 u2DelayCellOfst[0]=14 cells (4 PI)
8143 20:15:09.025391 u2DelayCellOfst[1]=17 cells (5 PI)
8144 20:15:09.029099 u2DelayCellOfst[2]=10 cells (3 PI)
8145 20:15:09.032480 u2DelayCellOfst[3]=10 cells (3 PI)
8146 20:15:09.035764 u2DelayCellOfst[4]=10 cells (3 PI)
8147 20:15:09.039136 u2DelayCellOfst[5]=0 cells (0 PI)
8148 20:15:09.042566 u2DelayCellOfst[6]=17 cells (5 PI)
8149 20:15:09.045405 u2DelayCellOfst[7]=21 cells (6 PI)
8150 20:15:09.049062 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8151 20:15:09.052503 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8152 20:15:09.055651 == TX Byte 1 ==
8153 20:15:09.055731 u2DelayCellOfst[8]=0 cells (0 PI)
8154 20:15:09.059466 u2DelayCellOfst[9]=3 cells (1 PI)
8155 20:15:09.062639 u2DelayCellOfst[10]=7 cells (2 PI)
8156 20:15:09.065450 u2DelayCellOfst[11]=3 cells (1 PI)
8157 20:15:09.068908 u2DelayCellOfst[12]=14 cells (4 PI)
8158 20:15:09.072375 u2DelayCellOfst[13]=14 cells (4 PI)
8159 20:15:09.075739 u2DelayCellOfst[14]=14 cells (4 PI)
8160 20:15:09.079112 u2DelayCellOfst[15]=10 cells (3 PI)
8161 20:15:09.082377 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8162 20:15:09.088777 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8163 20:15:09.088858 DramC Write-DBI on
8164 20:15:09.088922 ==
8165 20:15:09.092320 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 20:15:09.095766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 20:15:09.095846 ==
8168 20:15:09.099167
8169 20:15:09.099246
8170 20:15:09.099310 TX Vref Scan disable
8171 20:15:09.102716 == TX Byte 0 ==
8172 20:15:09.105622 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8173 20:15:09.109174 == TX Byte 1 ==
8174 20:15:09.112517 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8175 20:15:09.112597 DramC Write-DBI off
8176 20:15:09.112660
8177 20:15:09.115553 [DATLAT]
8178 20:15:09.115659 Freq=1600, CH0 RK1
8179 20:15:09.115810
8180 20:15:09.119322 DATLAT Default: 0xf
8181 20:15:09.119451 0, 0xFFFF, sum = 0
8182 20:15:09.122114 1, 0xFFFF, sum = 0
8183 20:15:09.122222 2, 0xFFFF, sum = 0
8184 20:15:09.125939 3, 0xFFFF, sum = 0
8185 20:15:09.126020 4, 0xFFFF, sum = 0
8186 20:15:09.129364 5, 0xFFFF, sum = 0
8187 20:15:09.129445 6, 0xFFFF, sum = 0
8188 20:15:09.132738 7, 0xFFFF, sum = 0
8189 20:15:09.132827 8, 0xFFFF, sum = 0
8190 20:15:09.135835 9, 0xFFFF, sum = 0
8191 20:15:09.138692 10, 0xFFFF, sum = 0
8192 20:15:09.138790 11, 0xFFFF, sum = 0
8193 20:15:09.142371 12, 0xFFFF, sum = 0
8194 20:15:09.142480 13, 0xFFFF, sum = 0
8195 20:15:09.145432 14, 0x0, sum = 1
8196 20:15:09.145516 15, 0x0, sum = 2
8197 20:15:09.149002 16, 0x0, sum = 3
8198 20:15:09.149087 17, 0x0, sum = 4
8199 20:15:09.152432 best_step = 15
8200 20:15:09.152514
8201 20:15:09.152598 ==
8202 20:15:09.155938 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 20:15:09.159225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 20:15:09.159309 ==
8205 20:15:09.159393 RX Vref Scan: 0
8206 20:15:09.159473
8207 20:15:09.162292 RX Vref 0 -> 0, step: 1
8208 20:15:09.162375
8209 20:15:09.166312 RX Delay 11 -> 252, step: 4
8210 20:15:09.168849 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8211 20:15:09.176069 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8212 20:15:09.178630 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8213 20:15:09.182839 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8214 20:15:09.185824 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8215 20:15:09.189564 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8216 20:15:09.195467 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8217 20:15:09.198878 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8218 20:15:09.202288 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8219 20:15:09.205641 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8220 20:15:09.208998 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8221 20:15:09.215047 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8222 20:15:09.219147 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8223 20:15:09.222325 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8224 20:15:09.225251 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8225 20:15:09.228423 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8226 20:15:09.231693 ==
8227 20:15:09.236364 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 20:15:09.238330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 20:15:09.238434 ==
8230 20:15:09.238513 DQS Delay:
8231 20:15:09.242068 DQS0 = 0, DQS1 = 0
8232 20:15:09.242147 DQM Delay:
8233 20:15:09.244807 DQM0 = 126, DQM1 = 122
8234 20:15:09.244886 DQ Delay:
8235 20:15:09.248589 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8236 20:15:09.251610 DQ4 =124, DQ5 =116, DQ6 =134, DQ7 =136
8237 20:15:09.255403 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8238 20:15:09.258589 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8239 20:15:09.258686
8240 20:15:09.258774
8241 20:15:09.258859
8242 20:15:09.261540 [DramC_TX_OE_Calibration] TA2
8243 20:15:09.265052 Original DQ_B0 (3 6) =30, OEN = 27
8244 20:15:09.269004 Original DQ_B1 (3 6) =30, OEN = 27
8245 20:15:09.271301 24, 0x0, End_B0=24 End_B1=24
8246 20:15:09.275181 25, 0x0, End_B0=25 End_B1=25
8247 20:15:09.275261 26, 0x0, End_B0=26 End_B1=26
8248 20:15:09.278231 27, 0x0, End_B0=27 End_B1=27
8249 20:15:09.281283 28, 0x0, End_B0=28 End_B1=28
8250 20:15:09.284952 29, 0x0, End_B0=29 End_B1=29
8251 20:15:09.288381 30, 0x0, End_B0=30 End_B1=30
8252 20:15:09.288462 31, 0x4545, End_B0=30 End_B1=30
8253 20:15:09.292225 Byte0 end_step=30 best_step=27
8254 20:15:09.294930 Byte1 end_step=30 best_step=27
8255 20:15:09.298369 Byte0 TX OE(2T, 0.5T) = (3, 3)
8256 20:15:09.302155 Byte1 TX OE(2T, 0.5T) = (3, 3)
8257 20:15:09.302235
8258 20:15:09.302314
8259 20:15:09.308443 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8260 20:15:09.312016 CH0 RK1: MR19=303, MR18=150A
8261 20:15:09.318683 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8262 20:15:09.321741 [RxdqsGatingPostProcess] freq 1600
8263 20:15:09.324984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8264 20:15:09.328236 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 20:15:09.331623 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 20:15:09.334836 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 20:15:09.337994 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 20:15:09.342030 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 20:15:09.344735 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 20:15:09.348164 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 20:15:09.351496 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 20:15:09.354455 Pre-setting of DQS Precalculation
8273 20:15:09.357996 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8274 20:15:09.358079 ==
8275 20:15:09.361399 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 20:15:09.368277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 20:15:09.368362 ==
8278 20:15:09.372229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8279 20:15:09.378183 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8280 20:15:09.381126 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8281 20:15:09.387886 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8282 20:15:09.395066 [CA 0] Center 42 (14~71) winsize 58
8283 20:15:09.398778 [CA 1] Center 42 (13~71) winsize 59
8284 20:15:09.402337 [CA 2] Center 37 (9~66) winsize 58
8285 20:15:09.405587 [CA 3] Center 36 (7~66) winsize 60
8286 20:15:09.408948 [CA 4] Center 36 (7~66) winsize 60
8287 20:15:09.411757 [CA 5] Center 36 (6~66) winsize 61
8288 20:15:09.411841
8289 20:15:09.415087 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8290 20:15:09.415170
8291 20:15:09.418594 [CATrainingPosCal] consider 1 rank data
8292 20:15:09.421765 u2DelayCellTimex100 = 275/100 ps
8293 20:15:09.425103 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8294 20:15:09.431806 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8295 20:15:09.435038 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8296 20:15:09.438340 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8297 20:15:09.442025 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8298 20:15:09.445338 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8299 20:15:09.445450
8300 20:15:09.448402 CA PerBit enable=1, Macro0, CA PI delay=36
8301 20:15:09.448482
8302 20:15:09.451622 [CBTSetCACLKResult] CA Dly = 36
8303 20:15:09.455493 CS Dly: 8 (0~39)
8304 20:15:09.458094 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8305 20:15:09.462000 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8306 20:15:09.462080 ==
8307 20:15:09.465466 Dram Type= 6, Freq= 0, CH_1, rank 1
8308 20:15:09.468241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 20:15:09.468321 ==
8310 20:15:09.474762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 20:15:09.478739 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 20:15:09.485137 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 20:15:09.488273 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 20:15:09.498170 [CA 0] Center 42 (13~72) winsize 60
8315 20:15:09.501588 [CA 1] Center 43 (14~72) winsize 59
8316 20:15:09.504982 [CA 2] Center 37 (9~66) winsize 58
8317 20:15:09.508369 [CA 3] Center 36 (7~66) winsize 60
8318 20:15:09.511654 [CA 4] Center 37 (8~67) winsize 60
8319 20:15:09.515030 [CA 5] Center 36 (7~66) winsize 60
8320 20:15:09.515111
8321 20:15:09.518291 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8322 20:15:09.518371
8323 20:15:09.521382 [CATrainingPosCal] consider 2 rank data
8324 20:15:09.524676 u2DelayCellTimex100 = 275/100 ps
8325 20:15:09.528263 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8326 20:15:09.534779 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8327 20:15:09.537996 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8328 20:15:09.541484 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8329 20:15:09.544979 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8330 20:15:09.548322 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8331 20:15:09.548404
8332 20:15:09.551950 CA PerBit enable=1, Macro0, CA PI delay=36
8333 20:15:09.552030
8334 20:15:09.554845 [CBTSetCACLKResult] CA Dly = 36
8335 20:15:09.558313 CS Dly: 11 (0~45)
8336 20:15:09.561447 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 20:15:09.564723 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 20:15:09.564803
8339 20:15:09.568169 ----->DramcWriteLeveling(PI) begin...
8340 20:15:09.568250 ==
8341 20:15:09.571535 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 20:15:09.575039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 20:15:09.578560 ==
8344 20:15:09.578639 Write leveling (Byte 0): 25 => 25
8345 20:15:09.581885 Write leveling (Byte 1): 31 => 31
8346 20:15:09.584961 DramcWriteLeveling(PI) end<-----
8347 20:15:09.585040
8348 20:15:09.585103 ==
8349 20:15:09.588005 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 20:15:09.595586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 20:15:09.595667 ==
8352 20:15:09.595730 [Gating] SW mode calibration
8353 20:15:09.604769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8354 20:15:09.608986 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8355 20:15:09.611894 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 20:15:09.618096 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 20:15:09.621819 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 20:15:09.625121 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 20:15:09.631367 1 4 16 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
8360 20:15:09.635465 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8361 20:15:09.638714 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 20:15:09.645285 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 20:15:09.648034 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 20:15:09.652195 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 20:15:09.658844 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 20:15:09.661401 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 20:15:09.664893 1 5 16 | B1->B0 | 2e2e 3333 | 0 0 | (0 1) (0 1)
8368 20:15:09.671982 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 20:15:09.675660 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 20:15:09.678537 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 20:15:09.682016 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 20:15:09.688351 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 20:15:09.691593 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 20:15:09.695057 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8375 20:15:09.701908 1 6 16 | B1->B0 | 4242 3c3c | 0 0 | (0 0) (0 0)
8376 20:15:09.705169 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 20:15:09.708370 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 20:15:09.715176 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 20:15:09.718189 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 20:15:09.722053 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 20:15:09.728882 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 20:15:09.731490 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8383 20:15:09.734892 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8384 20:15:09.741721 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8385 20:15:09.744807 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 20:15:09.748189 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 20:15:09.755421 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 20:15:09.758373 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 20:15:09.762108 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 20:15:09.768571 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 20:15:09.771756 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 20:15:09.775167 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 20:15:09.782231 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 20:15:09.784777 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 20:15:09.788296 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 20:15:09.791630 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 20:15:09.798550 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 20:15:09.801577 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 20:15:09.804862 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8400 20:15:09.811897 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 20:15:09.814907 Total UI for P1: 0, mck2ui 16
8402 20:15:09.818605 best dqsien dly found for B0: ( 1, 9, 16)
8403 20:15:09.818714 Total UI for P1: 0, mck2ui 16
8404 20:15:09.825544 best dqsien dly found for B1: ( 1, 9, 16)
8405 20:15:09.828220 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8406 20:15:09.831827 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8407 20:15:09.831910
8408 20:15:09.835125 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8409 20:15:09.838325 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8410 20:15:09.842043 [Gating] SW calibration Done
8411 20:15:09.842125 ==
8412 20:15:09.845153 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 20:15:09.848243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 20:15:09.848327 ==
8415 20:15:09.852000 RX Vref Scan: 0
8416 20:15:09.852083
8417 20:15:09.852166 RX Vref 0 -> 0, step: 1
8418 20:15:09.852246
8419 20:15:09.855669 RX Delay 0 -> 252, step: 8
8420 20:15:09.858250 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8421 20:15:09.865301 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8422 20:15:09.868686 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8423 20:15:09.871835 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8424 20:15:09.875203 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8425 20:15:09.878963 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8426 20:15:09.885018 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8427 20:15:09.888380 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8428 20:15:09.891626 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8429 20:15:09.895185 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8430 20:15:09.898825 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8431 20:15:09.902058 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8432 20:15:09.908690 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8433 20:15:09.912153 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8434 20:15:09.915436 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8435 20:15:09.918735 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8436 20:15:09.918841 ==
8437 20:15:09.922180 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 20:15:09.929447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 20:15:09.929528 ==
8440 20:15:09.929595 DQS Delay:
8441 20:15:09.931974 DQS0 = 0, DQS1 = 0
8442 20:15:09.932072 DQM Delay:
8443 20:15:09.935089 DQM0 = 135, DQM1 = 126
8444 20:15:09.935170 DQ Delay:
8445 20:15:09.938463 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8446 20:15:09.941886 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8447 20:15:09.945175 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8448 20:15:09.948677 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8449 20:15:09.948761
8450 20:15:09.948825
8451 20:15:09.948885 ==
8452 20:15:09.951958 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 20:15:09.958286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 20:15:09.958385 ==
8455 20:15:09.958475
8456 20:15:09.958536
8457 20:15:09.958593 TX Vref Scan disable
8458 20:15:09.962202 == TX Byte 0 ==
8459 20:15:09.965118 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8460 20:15:09.968757 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8461 20:15:09.971920 == TX Byte 1 ==
8462 20:15:09.975402 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8463 20:15:09.978823 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8464 20:15:09.981792 ==
8465 20:15:09.985127 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 20:15:09.988553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 20:15:09.988635 ==
8468 20:15:10.002020
8469 20:15:10.005783 TX Vref early break, caculate TX vref
8470 20:15:10.009321 TX Vref=16, minBit 8, minWin=21, winSum=361
8471 20:15:10.012435 TX Vref=18, minBit 5, minWin=22, winSum=373
8472 20:15:10.015557 TX Vref=20, minBit 8, minWin=22, winSum=381
8473 20:15:10.019196 TX Vref=22, minBit 8, minWin=23, winSum=393
8474 20:15:10.022280 TX Vref=24, minBit 5, minWin=23, winSum=403
8475 20:15:10.028846 TX Vref=26, minBit 8, minWin=25, winSum=415
8476 20:15:10.032505 TX Vref=28, minBit 8, minWin=25, winSum=421
8477 20:15:10.036234 TX Vref=30, minBit 0, minWin=25, winSum=418
8478 20:15:10.038873 TX Vref=32, minBit 3, minWin=24, winSum=405
8479 20:15:10.042941 TX Vref=34, minBit 3, minWin=24, winSum=399
8480 20:15:10.045719 TX Vref=36, minBit 9, minWin=23, winSum=392
8481 20:15:10.052476 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8482 20:15:10.052560
8483 20:15:10.055356 Final TX Range 0 Vref 28
8484 20:15:10.055438
8485 20:15:10.055502 ==
8486 20:15:10.058783 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 20:15:10.062340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 20:15:10.062456 ==
8489 20:15:10.062550
8490 20:15:10.062644
8491 20:15:10.066014 TX Vref Scan disable
8492 20:15:10.072067 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8493 20:15:10.072149 == TX Byte 0 ==
8494 20:15:10.075380 u2DelayCellOfst[0]=17 cells (5 PI)
8495 20:15:10.079065 u2DelayCellOfst[1]=14 cells (4 PI)
8496 20:15:10.082335 u2DelayCellOfst[2]=0 cells (0 PI)
8497 20:15:10.086043 u2DelayCellOfst[3]=7 cells (2 PI)
8498 20:15:10.088865 u2DelayCellOfst[4]=7 cells (2 PI)
8499 20:15:10.092687 u2DelayCellOfst[5]=17 cells (5 PI)
8500 20:15:10.095800 u2DelayCellOfst[6]=17 cells (5 PI)
8501 20:15:10.098840 u2DelayCellOfst[7]=7 cells (2 PI)
8502 20:15:10.102525 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8503 20:15:10.105647 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8504 20:15:10.109200 == TX Byte 1 ==
8505 20:15:10.109307 u2DelayCellOfst[8]=0 cells (0 PI)
8506 20:15:10.112028 u2DelayCellOfst[9]=3 cells (1 PI)
8507 20:15:10.115290 u2DelayCellOfst[10]=7 cells (2 PI)
8508 20:15:10.118907 u2DelayCellOfst[11]=7 cells (2 PI)
8509 20:15:10.122108 u2DelayCellOfst[12]=14 cells (4 PI)
8510 20:15:10.125379 u2DelayCellOfst[13]=17 cells (5 PI)
8511 20:15:10.129061 u2DelayCellOfst[14]=17 cells (5 PI)
8512 20:15:10.132046 u2DelayCellOfst[15]=17 cells (5 PI)
8513 20:15:10.135318 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8514 20:15:10.142722 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8515 20:15:10.142803 DramC Write-DBI on
8516 20:15:10.142868 ==
8517 20:15:10.145492 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 20:15:10.150615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 20:15:10.150698 ==
8520 20:15:10.153081
8521 20:15:10.153163
8522 20:15:10.153248 TX Vref Scan disable
8523 20:15:10.155340 == TX Byte 0 ==
8524 20:15:10.158722 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8525 20:15:10.162282 == TX Byte 1 ==
8526 20:15:10.165427 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
8527 20:15:10.165510 DramC Write-DBI off
8528 20:15:10.169092
8529 20:15:10.169173 [DATLAT]
8530 20:15:10.169257 Freq=1600, CH1 RK0
8531 20:15:10.169337
8532 20:15:10.172304 DATLAT Default: 0xf
8533 20:15:10.172386 0, 0xFFFF, sum = 0
8534 20:15:10.175235 1, 0xFFFF, sum = 0
8535 20:15:10.175322 2, 0xFFFF, sum = 0
8536 20:15:10.179114 3, 0xFFFF, sum = 0
8537 20:15:10.179199 4, 0xFFFF, sum = 0
8538 20:15:10.182112 5, 0xFFFF, sum = 0
8539 20:15:10.185500 6, 0xFFFF, sum = 0
8540 20:15:10.185585 7, 0xFFFF, sum = 0
8541 20:15:10.188853 8, 0xFFFF, sum = 0
8542 20:15:10.188939 9, 0xFFFF, sum = 0
8543 20:15:10.191883 10, 0xFFFF, sum = 0
8544 20:15:10.191958 11, 0xFFFF, sum = 0
8545 20:15:10.195435 12, 0xFFFF, sum = 0
8546 20:15:10.195519 13, 0xFFFF, sum = 0
8547 20:15:10.198939 14, 0x0, sum = 1
8548 20:15:10.199021 15, 0x0, sum = 2
8549 20:15:10.202220 16, 0x0, sum = 3
8550 20:15:10.202342 17, 0x0, sum = 4
8551 20:15:10.205568 best_step = 15
8552 20:15:10.205743
8553 20:15:10.205880 ==
8554 20:15:10.208484 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 20:15:10.211888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 20:15:10.211969 ==
8557 20:15:10.212032 RX Vref Scan: 1
8558 20:15:10.212091
8559 20:15:10.216116 Set Vref Range= 24 -> 127
8560 20:15:10.216212
8561 20:15:10.218989 RX Vref 24 -> 127, step: 1
8562 20:15:10.219068
8563 20:15:10.221980 RX Delay 11 -> 252, step: 4
8564 20:15:10.222077
8565 20:15:10.225057 Set Vref, RX VrefLevel [Byte0]: 24
8566 20:15:10.229098 [Byte1]: 24
8567 20:15:10.229203
8568 20:15:10.232338 Set Vref, RX VrefLevel [Byte0]: 25
8569 20:15:10.235533 [Byte1]: 25
8570 20:15:10.235663
8571 20:15:10.239430 Set Vref, RX VrefLevel [Byte0]: 26
8572 20:15:10.241969 [Byte1]: 26
8573 20:15:10.245900
8574 20:15:10.246014 Set Vref, RX VrefLevel [Byte0]: 27
8575 20:15:10.248886 [Byte1]: 27
8576 20:15:10.253234
8577 20:15:10.253353 Set Vref, RX VrefLevel [Byte0]: 28
8578 20:15:10.256449 [Byte1]: 28
8579 20:15:10.261144
8580 20:15:10.261225 Set Vref, RX VrefLevel [Byte0]: 29
8581 20:15:10.264230 [Byte1]: 29
8582 20:15:10.268977
8583 20:15:10.269056 Set Vref, RX VrefLevel [Byte0]: 30
8584 20:15:10.272132 [Byte1]: 30
8585 20:15:10.276432
8586 20:15:10.276511 Set Vref, RX VrefLevel [Byte0]: 31
8587 20:15:10.279721 [Byte1]: 31
8588 20:15:10.283841
8589 20:15:10.283921 Set Vref, RX VrefLevel [Byte0]: 32
8590 20:15:10.286990 [Byte1]: 32
8591 20:15:10.292572
8592 20:15:10.292652 Set Vref, RX VrefLevel [Byte0]: 33
8593 20:15:10.294722 [Byte1]: 33
8594 20:15:10.299325
8595 20:15:10.299427 Set Vref, RX VrefLevel [Byte0]: 34
8596 20:15:10.302133 [Byte1]: 34
8597 20:15:10.306634
8598 20:15:10.306713 Set Vref, RX VrefLevel [Byte0]: 35
8599 20:15:10.310126 [Byte1]: 35
8600 20:15:10.314271
8601 20:15:10.314350 Set Vref, RX VrefLevel [Byte0]: 36
8602 20:15:10.317878 [Byte1]: 36
8603 20:15:10.321868
8604 20:15:10.321964 Set Vref, RX VrefLevel [Byte0]: 37
8605 20:15:10.324952 [Byte1]: 37
8606 20:15:10.329655
8607 20:15:10.329734 Set Vref, RX VrefLevel [Byte0]: 38
8608 20:15:10.333084 [Byte1]: 38
8609 20:15:10.337151
8610 20:15:10.337231 Set Vref, RX VrefLevel [Byte0]: 39
8611 20:15:10.340375 [Byte1]: 39
8612 20:15:10.345854
8613 20:15:10.345937 Set Vref, RX VrefLevel [Byte0]: 40
8614 20:15:10.348196 [Byte1]: 40
8615 20:15:10.353051
8616 20:15:10.353130 Set Vref, RX VrefLevel [Byte0]: 41
8617 20:15:10.356348 [Byte1]: 41
8618 20:15:10.360351
8619 20:15:10.360429 Set Vref, RX VrefLevel [Byte0]: 42
8620 20:15:10.366754 [Byte1]: 42
8621 20:15:10.366834
8622 20:15:10.369679 Set Vref, RX VrefLevel [Byte0]: 43
8623 20:15:10.372927 [Byte1]: 43
8624 20:15:10.373008
8625 20:15:10.376712 Set Vref, RX VrefLevel [Byte0]: 44
8626 20:15:10.379817 [Byte1]: 44
8627 20:15:10.379897
8628 20:15:10.383324 Set Vref, RX VrefLevel [Byte0]: 45
8629 20:15:10.386523 [Byte1]: 45
8630 20:15:10.390331
8631 20:15:10.390434 Set Vref, RX VrefLevel [Byte0]: 46
8632 20:15:10.393674 [Byte1]: 46
8633 20:15:10.398298
8634 20:15:10.398378 Set Vref, RX VrefLevel [Byte0]: 47
8635 20:15:10.401544 [Byte1]: 47
8636 20:15:10.405924
8637 20:15:10.406003 Set Vref, RX VrefLevel [Byte0]: 48
8638 20:15:10.408881 [Byte1]: 48
8639 20:15:10.413212
8640 20:15:10.413291 Set Vref, RX VrefLevel [Byte0]: 49
8641 20:15:10.416471 [Byte1]: 49
8642 20:15:10.421036
8643 20:15:10.421114 Set Vref, RX VrefLevel [Byte0]: 50
8644 20:15:10.424228 [Byte1]: 50
8645 20:15:10.428403
8646 20:15:10.428498 Set Vref, RX VrefLevel [Byte0]: 51
8647 20:15:10.431961 [Byte1]: 51
8648 20:15:10.436802
8649 20:15:10.436882 Set Vref, RX VrefLevel [Byte0]: 52
8650 20:15:10.439508 [Byte1]: 52
8651 20:15:10.443960
8652 20:15:10.444039 Set Vref, RX VrefLevel [Byte0]: 53
8653 20:15:10.447249 [Byte1]: 53
8654 20:15:10.452015
8655 20:15:10.452093 Set Vref, RX VrefLevel [Byte0]: 54
8656 20:15:10.454927 [Byte1]: 54
8657 20:15:10.458903
8658 20:15:10.458983 Set Vref, RX VrefLevel [Byte0]: 55
8659 20:15:10.462351 [Byte1]: 55
8660 20:15:10.466778
8661 20:15:10.466858 Set Vref, RX VrefLevel [Byte0]: 56
8662 20:15:10.469934 [Byte1]: 56
8663 20:15:10.474340
8664 20:15:10.474473 Set Vref, RX VrefLevel [Byte0]: 57
8665 20:15:10.477464 [Byte1]: 57
8666 20:15:10.481786
8667 20:15:10.481865 Set Vref, RX VrefLevel [Byte0]: 58
8668 20:15:10.486031 [Byte1]: 58
8669 20:15:10.489810
8670 20:15:10.489890 Set Vref, RX VrefLevel [Byte0]: 59
8671 20:15:10.492599 [Byte1]: 59
8672 20:15:10.497371
8673 20:15:10.497450 Set Vref, RX VrefLevel [Byte0]: 60
8674 20:15:10.500338 [Byte1]: 60
8675 20:15:10.504674
8676 20:15:10.504753 Set Vref, RX VrefLevel [Byte0]: 61
8677 20:15:10.508183 [Byte1]: 61
8678 20:15:10.512601
8679 20:15:10.512685 Set Vref, RX VrefLevel [Byte0]: 62
8680 20:15:10.515496 [Byte1]: 62
8681 20:15:10.519843
8682 20:15:10.519923 Set Vref, RX VrefLevel [Byte0]: 63
8683 20:15:10.523598 [Byte1]: 63
8684 20:15:10.527412
8685 20:15:10.527490 Set Vref, RX VrefLevel [Byte0]: 64
8686 20:15:10.530733 [Byte1]: 64
8687 20:15:10.534776
8688 20:15:10.534855 Set Vref, RX VrefLevel [Byte0]: 65
8689 20:15:10.538264 [Byte1]: 65
8690 20:15:10.542650
8691 20:15:10.542729 Set Vref, RX VrefLevel [Byte0]: 66
8692 20:15:10.546216 [Byte1]: 66
8693 20:15:10.550391
8694 20:15:10.550477 Set Vref, RX VrefLevel [Byte0]: 67
8695 20:15:10.553433 [Byte1]: 67
8696 20:15:10.557897
8697 20:15:10.557976 Set Vref, RX VrefLevel [Byte0]: 68
8698 20:15:10.561234 [Byte1]: 68
8699 20:15:10.565256
8700 20:15:10.565335 Set Vref, RX VrefLevel [Byte0]: 69
8701 20:15:10.569609 [Byte1]: 69
8702 20:15:10.573506
8703 20:15:10.573585 Set Vref, RX VrefLevel [Byte0]: 70
8704 20:15:10.576242 [Byte1]: 70
8705 20:15:10.581404
8706 20:15:10.581483 Set Vref, RX VrefLevel [Byte0]: 71
8707 20:15:10.583769 [Byte1]: 71
8708 20:15:10.588557
8709 20:15:10.588636 Set Vref, RX VrefLevel [Byte0]: 72
8710 20:15:10.592109 [Byte1]: 72
8711 20:15:10.596038
8712 20:15:10.596117 Set Vref, RX VrefLevel [Byte0]: 73
8713 20:15:10.599277 [Byte1]: 73
8714 20:15:10.603834
8715 20:15:10.603913 Set Vref, RX VrefLevel [Byte0]: 74
8716 20:15:10.607219 [Byte1]: 74
8717 20:15:10.611253
8718 20:15:10.611333 Set Vref, RX VrefLevel [Byte0]: 75
8719 20:15:10.614957 [Byte1]: 75
8720 20:15:10.619099
8721 20:15:10.619179 Final RX Vref Byte 0 = 55 to rank0
8722 20:15:10.621974 Final RX Vref Byte 1 = 58 to rank0
8723 20:15:10.625575 Final RX Vref Byte 0 = 55 to rank1
8724 20:15:10.628899 Final RX Vref Byte 1 = 58 to rank1==
8725 20:15:10.632129 Dram Type= 6, Freq= 0, CH_1, rank 0
8726 20:15:10.638418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 20:15:10.638499 ==
8728 20:15:10.638563 DQS Delay:
8729 20:15:10.638623 DQS0 = 0, DQS1 = 0
8730 20:15:10.642231 DQM Delay:
8731 20:15:10.642311 DQM0 = 130, DQM1 = 124
8732 20:15:10.645216 DQ Delay:
8733 20:15:10.648740 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8734 20:15:10.652253 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8735 20:15:10.655413 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
8736 20:15:10.658832 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8737 20:15:10.658975
8738 20:15:10.659052
8739 20:15:10.659111
8740 20:15:10.662232 [DramC_TX_OE_Calibration] TA2
8741 20:15:10.665620 Original DQ_B0 (3 6) =30, OEN = 27
8742 20:15:10.668994 Original DQ_B1 (3 6) =30, OEN = 27
8743 20:15:10.672383 24, 0x0, End_B0=24 End_B1=24
8744 20:15:10.672464 25, 0x0, End_B0=25 End_B1=25
8745 20:15:10.675308 26, 0x0, End_B0=26 End_B1=26
8746 20:15:10.678605 27, 0x0, End_B0=27 End_B1=27
8747 20:15:10.682043 28, 0x0, End_B0=28 End_B1=28
8748 20:15:10.682124 29, 0x0, End_B0=29 End_B1=29
8749 20:15:10.685238 30, 0x0, End_B0=30 End_B1=30
8750 20:15:10.688812 31, 0x4141, End_B0=30 End_B1=30
8751 20:15:10.692545 Byte0 end_step=30 best_step=27
8752 20:15:10.695113 Byte1 end_step=30 best_step=27
8753 20:15:10.698621 Byte0 TX OE(2T, 0.5T) = (3, 3)
8754 20:15:10.698701 Byte1 TX OE(2T, 0.5T) = (3, 3)
8755 20:15:10.701941
8756 20:15:10.702020
8757 20:15:10.709006 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8758 20:15:10.712293 CH1 RK0: MR19=303, MR18=1600
8759 20:15:10.719353 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8760 20:15:10.719433
8761 20:15:10.722087 ----->DramcWriteLeveling(PI) begin...
8762 20:15:10.722169 ==
8763 20:15:10.725385 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 20:15:10.728832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 20:15:10.728912 ==
8766 20:15:10.731802 Write leveling (Byte 0): 25 => 25
8767 20:15:10.736088 Write leveling (Byte 1): 25 => 25
8768 20:15:10.738393 DramcWriteLeveling(PI) end<-----
8769 20:15:10.738514
8770 20:15:10.738577 ==
8771 20:15:10.741902 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 20:15:10.745827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 20:15:10.745907 ==
8774 20:15:10.748332 [Gating] SW mode calibration
8775 20:15:10.755821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8776 20:15:10.762130 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8777 20:15:10.765278 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 20:15:10.768702 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 20:15:10.775674 1 4 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8780 20:15:10.778746 1 4 12 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
8781 20:15:10.781973 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 20:15:10.788478 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 20:15:10.792116 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 20:15:10.795545 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 20:15:10.801947 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 20:15:10.805730 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 20:15:10.808852 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8788 20:15:10.812466 1 5 12 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
8789 20:15:10.818764 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8790 20:15:10.822252 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 20:15:10.825381 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 20:15:10.832003 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 20:15:10.835094 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 20:15:10.838844 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 20:15:10.845409 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
8796 20:15:10.849319 1 6 12 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
8797 20:15:10.852546 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 20:15:10.859190 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 20:15:10.863381 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 20:15:10.865391 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 20:15:10.872061 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 20:15:10.875855 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 20:15:10.879265 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8804 20:15:10.882332 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8805 20:15:10.889360 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8806 20:15:10.892186 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 20:15:10.895868 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 20:15:10.902337 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 20:15:10.906120 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 20:15:10.909815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 20:15:10.915947 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 20:15:10.918822 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 20:15:10.922211 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 20:15:10.929590 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 20:15:10.932120 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 20:15:10.935554 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 20:15:10.942631 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 20:15:10.945599 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8819 20:15:10.948940 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8820 20:15:10.955541 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8821 20:15:10.955660 Total UI for P1: 0, mck2ui 16
8822 20:15:10.962909 best dqsien dly found for B0: ( 1, 9, 6)
8823 20:15:10.965646 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 20:15:10.968721 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 20:15:10.972168 Total UI for P1: 0, mck2ui 16
8826 20:15:10.975569 best dqsien dly found for B1: ( 1, 9, 14)
8827 20:15:10.978930 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8828 20:15:10.982389 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8829 20:15:10.982537
8830 20:15:10.985671 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8831 20:15:10.992239 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8832 20:15:10.992360 [Gating] SW calibration Done
8833 20:15:10.992472 ==
8834 20:15:10.995482 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 20:15:11.002720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 20:15:11.002839 ==
8837 20:15:11.002950 RX Vref Scan: 0
8838 20:15:11.003055
8839 20:15:11.005893 RX Vref 0 -> 0, step: 1
8840 20:15:11.006011
8841 20:15:11.008637 RX Delay 0 -> 252, step: 8
8842 20:15:11.012432 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8843 20:15:11.015872 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8844 20:15:11.018819 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8845 20:15:11.022472 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8846 20:15:11.029182 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8847 20:15:11.032453 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8848 20:15:11.035904 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8849 20:15:11.039550 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8850 20:15:11.042666 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8851 20:15:11.049457 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8852 20:15:11.052107 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8853 20:15:11.055561 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8854 20:15:11.058746 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8855 20:15:11.062240 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8856 20:15:11.068813 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8857 20:15:11.072298 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8858 20:15:11.072422 ==
8859 20:15:11.075800 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 20:15:11.078877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 20:15:11.078997 ==
8862 20:15:11.082329 DQS Delay:
8863 20:15:11.082474 DQS0 = 0, DQS1 = 0
8864 20:15:11.082583 DQM Delay:
8865 20:15:11.085904 DQM0 = 132, DQM1 = 129
8866 20:15:11.086022 DQ Delay:
8867 20:15:11.089663 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8868 20:15:11.092327 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8869 20:15:11.095698 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8870 20:15:11.102209 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8871 20:15:11.102330
8872 20:15:11.102481
8873 20:15:11.102588 ==
8874 20:15:11.106009 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 20:15:11.109096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 20:15:11.109213 ==
8877 20:15:11.109318
8878 20:15:11.109428
8879 20:15:11.112536 TX Vref Scan disable
8880 20:15:11.112656 == TX Byte 0 ==
8881 20:15:11.120100 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8882 20:15:11.122943 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8883 20:15:11.123063 == TX Byte 1 ==
8884 20:15:11.129740 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 20:15:11.132708 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8886 20:15:11.132825 ==
8887 20:15:11.135961 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 20:15:11.138998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 20:15:11.139118 ==
8890 20:15:11.153966
8891 20:15:11.157027 TX Vref early break, caculate TX vref
8892 20:15:11.160482 TX Vref=16, minBit 6, minWin=23, winSum=385
8893 20:15:11.163734 TX Vref=18, minBit 0, minWin=24, winSum=395
8894 20:15:11.167023 TX Vref=20, minBit 5, minWin=24, winSum=405
8895 20:15:11.169806 TX Vref=22, minBit 8, minWin=23, winSum=410
8896 20:15:11.174104 TX Vref=24, minBit 1, minWin=25, winSum=417
8897 20:15:11.179786 TX Vref=26, minBit 5, minWin=25, winSum=422
8898 20:15:11.184007 TX Vref=28, minBit 0, minWin=26, winSum=427
8899 20:15:11.186974 TX Vref=30, minBit 0, minWin=25, winSum=427
8900 20:15:11.190033 TX Vref=32, minBit 0, minWin=25, winSum=425
8901 20:15:11.193233 TX Vref=34, minBit 0, minWin=25, winSum=410
8902 20:15:11.196926 TX Vref=36, minBit 0, minWin=23, winSum=399
8903 20:15:11.203266 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8904 20:15:11.203347
8905 20:15:11.207035 Final TX Range 0 Vref 28
8906 20:15:11.207116
8907 20:15:11.207179 ==
8908 20:15:11.209900 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 20:15:11.213258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 20:15:11.213339 ==
8911 20:15:11.213403
8912 20:15:11.213462
8913 20:15:11.216725 TX Vref Scan disable
8914 20:15:11.223283 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8915 20:15:11.223364 == TX Byte 0 ==
8916 20:15:11.226984 u2DelayCellOfst[0]=17 cells (5 PI)
8917 20:15:11.229652 u2DelayCellOfst[1]=10 cells (3 PI)
8918 20:15:11.233153 u2DelayCellOfst[2]=0 cells (0 PI)
8919 20:15:11.236794 u2DelayCellOfst[3]=7 cells (2 PI)
8920 20:15:11.239692 u2DelayCellOfst[4]=7 cells (2 PI)
8921 20:15:11.243549 u2DelayCellOfst[5]=17 cells (5 PI)
8922 20:15:11.247135 u2DelayCellOfst[6]=17 cells (5 PI)
8923 20:15:11.250335 u2DelayCellOfst[7]=7 cells (2 PI)
8924 20:15:11.253154 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8925 20:15:11.257570 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8926 20:15:11.260558 == TX Byte 1 ==
8927 20:15:11.260638 u2DelayCellOfst[8]=0 cells (0 PI)
8928 20:15:11.263396 u2DelayCellOfst[9]=7 cells (2 PI)
8929 20:15:11.267334 u2DelayCellOfst[10]=10 cells (3 PI)
8930 20:15:11.270877 u2DelayCellOfst[11]=3 cells (1 PI)
8931 20:15:11.273745 u2DelayCellOfst[12]=14 cells (4 PI)
8932 20:15:11.277030 u2DelayCellOfst[13]=17 cells (5 PI)
8933 20:15:11.280435 u2DelayCellOfst[14]=17 cells (5 PI)
8934 20:15:11.284068 u2DelayCellOfst[15]=14 cells (4 PI)
8935 20:15:11.287119 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8936 20:15:11.293439 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8937 20:15:11.293520 DramC Write-DBI on
8938 20:15:11.293585 ==
8939 20:15:11.297617 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 20:15:11.300083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 20:15:11.303542 ==
8942 20:15:11.303622
8943 20:15:11.303685
8944 20:15:11.303744 TX Vref Scan disable
8945 20:15:11.306540 == TX Byte 0 ==
8946 20:15:11.309669 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8947 20:15:11.314169 == TX Byte 1 ==
8948 20:15:11.316980 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8949 20:15:11.317063 DramC Write-DBI off
8950 20:15:11.320129
8951 20:15:11.320209 [DATLAT]
8952 20:15:11.320272 Freq=1600, CH1 RK1
8953 20:15:11.320332
8954 20:15:11.324213 DATLAT Default: 0xf
8955 20:15:11.324293 0, 0xFFFF, sum = 0
8956 20:15:11.326861 1, 0xFFFF, sum = 0
8957 20:15:11.326943 2, 0xFFFF, sum = 0
8958 20:15:11.329921 3, 0xFFFF, sum = 0
8959 20:15:11.333323 4, 0xFFFF, sum = 0
8960 20:15:11.333412 5, 0xFFFF, sum = 0
8961 20:15:11.337099 6, 0xFFFF, sum = 0
8962 20:15:11.337181 7, 0xFFFF, sum = 0
8963 20:15:11.340970 8, 0xFFFF, sum = 0
8964 20:15:11.341078 9, 0xFFFF, sum = 0
8965 20:15:11.343595 10, 0xFFFF, sum = 0
8966 20:15:11.343677 11, 0xFFFF, sum = 0
8967 20:15:11.347253 12, 0xFFFF, sum = 0
8968 20:15:11.347335 13, 0xFFFF, sum = 0
8969 20:15:11.350092 14, 0x0, sum = 1
8970 20:15:11.350201 15, 0x0, sum = 2
8971 20:15:11.353046 16, 0x0, sum = 3
8972 20:15:11.353128 17, 0x0, sum = 4
8973 20:15:11.356548 best_step = 15
8974 20:15:11.356628
8975 20:15:11.356691 ==
8976 20:15:11.359828 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 20:15:11.363364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 20:15:11.363445 ==
8979 20:15:11.363509 RX Vref Scan: 0
8980 20:15:11.363568
8981 20:15:11.366702 RX Vref 0 -> 0, step: 1
8982 20:15:11.366782
8983 20:15:11.370019 RX Delay 11 -> 252, step: 4
8984 20:15:11.373597 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8985 20:15:11.379942 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8986 20:15:11.383401 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8987 20:15:11.386681 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8988 20:15:11.390278 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8989 20:15:11.393731 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8990 20:15:11.396833 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8991 20:15:11.403345 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8992 20:15:11.406353 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8993 20:15:11.409683 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8994 20:15:11.413297 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8995 20:15:11.416706 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8996 20:15:11.423410 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8997 20:15:11.426408 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8998 20:15:11.430650 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8999 20:15:11.433723 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9000 20:15:11.433803 ==
9001 20:15:11.436715 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 20:15:11.444060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 20:15:11.444162 ==
9004 20:15:11.444228 DQS Delay:
9005 20:15:11.446328 DQS0 = 0, DQS1 = 0
9006 20:15:11.446482 DQM Delay:
9007 20:15:11.446579 DQM0 = 129, DQM1 = 126
9008 20:15:11.450641 DQ Delay:
9009 20:15:11.453441 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9010 20:15:11.456500 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9011 20:15:11.460444 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
9012 20:15:11.463313 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9013 20:15:11.463394
9014 20:15:11.463457
9015 20:15:11.463515
9016 20:15:11.466347 [DramC_TX_OE_Calibration] TA2
9017 20:15:11.470111 Original DQ_B0 (3 6) =30, OEN = 27
9018 20:15:11.473649 Original DQ_B1 (3 6) =30, OEN = 27
9019 20:15:11.476905 24, 0x0, End_B0=24 End_B1=24
9020 20:15:11.476986 25, 0x0, End_B0=25 End_B1=25
9021 20:15:11.480270 26, 0x0, End_B0=26 End_B1=26
9022 20:15:11.483273 27, 0x0, End_B0=27 End_B1=27
9023 20:15:11.486495 28, 0x0, End_B0=28 End_B1=28
9024 20:15:11.489719 29, 0x0, End_B0=29 End_B1=29
9025 20:15:11.489820 30, 0x0, End_B0=30 End_B1=30
9026 20:15:11.493391 31, 0x4545, End_B0=30 End_B1=30
9027 20:15:11.496993 Byte0 end_step=30 best_step=27
9028 20:15:11.500659 Byte1 end_step=30 best_step=27
9029 20:15:11.503035 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 20:15:11.506377 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 20:15:11.506527
9032 20:15:11.506624
9033 20:15:11.513510 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9034 20:15:11.516374 CH1 RK1: MR19=303, MR18=1117
9035 20:15:11.523414 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9036 20:15:11.526728 [RxdqsGatingPostProcess] freq 1600
9037 20:15:11.529897 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 20:15:11.533291 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 20:15:11.536387 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 20:15:11.539648 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 20:15:11.543331 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 20:15:11.546499 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 20:15:11.550180 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 20:15:11.553160 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 20:15:11.556336 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 20:15:11.560037 Pre-setting of DQS Precalculation
9047 20:15:11.563113 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 20:15:11.569601 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 20:15:11.577387 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 20:15:11.577468
9051 20:15:11.577532
9052 20:15:11.580018 [Calibration Summary] 3200 Mbps
9053 20:15:11.583290 CH 0, Rank 0
9054 20:15:11.583369 SW Impedance : PASS
9055 20:15:11.586598 DUTY Scan : NO K
9056 20:15:11.589896 ZQ Calibration : PASS
9057 20:15:11.589975 Jitter Meter : NO K
9058 20:15:11.593112 CBT Training : PASS
9059 20:15:11.596595 Write leveling : PASS
9060 20:15:11.596675 RX DQS gating : PASS
9061 20:15:11.600121 RX DQ/DQS(RDDQC) : PASS
9062 20:15:11.600201 TX DQ/DQS : PASS
9063 20:15:11.603859 RX DATLAT : PASS
9064 20:15:11.606740 RX DQ/DQS(Engine): PASS
9065 20:15:11.606858 TX OE : PASS
9066 20:15:11.610368 All Pass.
9067 20:15:11.610508
9068 20:15:11.610618 CH 0, Rank 1
9069 20:15:11.613063 SW Impedance : PASS
9070 20:15:11.613145 DUTY Scan : NO K
9071 20:15:11.616472 ZQ Calibration : PASS
9072 20:15:11.619798 Jitter Meter : NO K
9073 20:15:11.619879 CBT Training : PASS
9074 20:15:11.623790 Write leveling : PASS
9075 20:15:11.626766 RX DQS gating : PASS
9076 20:15:11.626846 RX DQ/DQS(RDDQC) : PASS
9077 20:15:11.629911 TX DQ/DQS : PASS
9078 20:15:11.633425 RX DATLAT : PASS
9079 20:15:11.633506 RX DQ/DQS(Engine): PASS
9080 20:15:11.636743 TX OE : PASS
9081 20:15:11.636823 All Pass.
9082 20:15:11.636887
9083 20:15:11.639705 CH 1, Rank 0
9084 20:15:11.639785 SW Impedance : PASS
9085 20:15:11.642917 DUTY Scan : NO K
9086 20:15:11.646658 ZQ Calibration : PASS
9087 20:15:11.646739 Jitter Meter : NO K
9088 20:15:11.650835 CBT Training : PASS
9089 20:15:11.653520 Write leveling : PASS
9090 20:15:11.653600 RX DQS gating : PASS
9091 20:15:11.656197 RX DQ/DQS(RDDQC) : PASS
9092 20:15:11.659464 TX DQ/DQS : PASS
9093 20:15:11.659544 RX DATLAT : PASS
9094 20:15:11.662834 RX DQ/DQS(Engine): PASS
9095 20:15:11.662914 TX OE : PASS
9096 20:15:11.667083 All Pass.
9097 20:15:11.667163
9098 20:15:11.667227 CH 1, Rank 1
9099 20:15:11.669590 SW Impedance : PASS
9100 20:15:11.669670 DUTY Scan : NO K
9101 20:15:11.673339 ZQ Calibration : PASS
9102 20:15:11.676296 Jitter Meter : NO K
9103 20:15:11.676376 CBT Training : PASS
9104 20:15:11.679746 Write leveling : PASS
9105 20:15:11.682814 RX DQS gating : PASS
9106 20:15:11.682894 RX DQ/DQS(RDDQC) : PASS
9107 20:15:11.686361 TX DQ/DQS : PASS
9108 20:15:11.690141 RX DATLAT : PASS
9109 20:15:11.690221 RX DQ/DQS(Engine): PASS
9110 20:15:11.693716 TX OE : PASS
9111 20:15:11.693797 All Pass.
9112 20:15:11.693861
9113 20:15:11.696314 DramC Write-DBI on
9114 20:15:11.699936 PER_BANK_REFRESH: Hybrid Mode
9115 20:15:11.700017 TX_TRACKING: ON
9116 20:15:11.709607 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 20:15:11.716532 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 20:15:11.723177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 20:15:11.726381 [FAST_K] Save calibration result to emmc
9120 20:15:11.729962 sync common calibartion params.
9121 20:15:11.732920 sync cbt_mode0:1, 1:1
9122 20:15:11.733000 dram_init: ddr_geometry: 2
9123 20:15:11.736452 dram_init: ddr_geometry: 2
9124 20:15:11.740245 dram_init: ddr_geometry: 2
9125 20:15:11.742925 0:dram_rank_size:100000000
9126 20:15:11.743006 1:dram_rank_size:100000000
9127 20:15:11.749917 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 20:15:11.752823 DFS_SHUFFLE_HW_MODE: ON
9129 20:15:11.756506 dramc_set_vcore_voltage set vcore to 725000
9130 20:15:11.760428 Read voltage for 1600, 0
9131 20:15:11.760509 Vio18 = 0
9132 20:15:11.760572 Vcore = 725000
9133 20:15:11.760632 Vdram = 0
9134 20:15:11.762956 Vddq = 0
9135 20:15:11.763036 Vmddr = 0
9136 20:15:11.766244 switch to 3200 Mbps bootup
9137 20:15:11.766324 [DramcRunTimeConfig]
9138 20:15:11.769658 PHYPLL
9139 20:15:11.769738 DPM_CONTROL_AFTERK: ON
9140 20:15:11.773614 PER_BANK_REFRESH: ON
9141 20:15:11.776292 REFRESH_OVERHEAD_REDUCTION: ON
9142 20:15:11.776373 CMD_PICG_NEW_MODE: OFF
9143 20:15:11.780001 XRTWTW_NEW_MODE: ON
9144 20:15:11.780085 XRTRTR_NEW_MODE: ON
9145 20:15:11.783463 TX_TRACKING: ON
9146 20:15:11.783546 RDSEL_TRACKING: OFF
9147 20:15:11.786631 DQS Precalculation for DVFS: ON
9148 20:15:11.789880 RX_TRACKING: OFF
9149 20:15:11.789963 HW_GATING DBG: ON
9150 20:15:11.793378 ZQCS_ENABLE_LP4: ON
9151 20:15:11.793461 RX_PICG_NEW_MODE: ON
9152 20:15:11.797038 TX_PICG_NEW_MODE: ON
9153 20:15:11.797121 ENABLE_RX_DCM_DPHY: ON
9154 20:15:11.799678 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 20:15:11.803002 DUMMY_READ_FOR_TRACKING: OFF
9156 20:15:11.806496 !!! SPM_CONTROL_AFTERK: OFF
9157 20:15:11.809615 !!! SPM could not control APHY
9158 20:15:11.809740 IMPEDANCE_TRACKING: ON
9159 20:15:11.813223 TEMP_SENSOR: ON
9160 20:15:11.813345 HW_SAVE_FOR_SR: OFF
9161 20:15:11.816384 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 20:15:11.819479 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 20:15:11.823426 Read ODT Tracking: ON
9164 20:15:11.826560 Refresh Rate DeBounce: ON
9165 20:15:11.826680 DFS_NO_QUEUE_FLUSH: ON
9166 20:15:11.829704 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 20:15:11.832646 ENABLE_DFS_RUNTIME_MRW: OFF
9168 20:15:11.836353 DDR_RESERVE_NEW_MODE: ON
9169 20:15:11.836474 MR_CBT_SWITCH_FREQ: ON
9170 20:15:11.839247 =========================
9171 20:15:11.858072 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 20:15:11.861711 dram_init: ddr_geometry: 2
9173 20:15:11.879993 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 20:15:11.882937 dram_init: dram init end (result: 0)
9175 20:15:11.889740 DRAM-K: Full calibration passed in 24580 msecs
9176 20:15:11.894013 MRC: failed to locate region type 0.
9177 20:15:11.894135 DRAM rank0 size:0x100000000,
9178 20:15:11.896438 DRAM rank1 size=0x100000000
9179 20:15:11.906606 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 20:15:11.913966 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 20:15:11.920045 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 20:15:11.926357 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 20:15:11.929931 DRAM rank0 size:0x100000000,
9184 20:15:11.932880 DRAM rank1 size=0x100000000
9185 20:15:11.932959 CBMEM:
9186 20:15:11.936682 IMD: root @ 0xfffff000 254 entries.
9187 20:15:11.939629 IMD: root @ 0xffffec00 62 entries.
9188 20:15:11.943609 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 20:15:11.946607 WARNING: RO_VPD is uninitialized or empty.
9190 20:15:11.953452 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 20:15:11.959548 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 20:15:11.972217 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9193 20:15:11.984315 BS: romstage times (exec / console): total (unknown) / 24082 ms
9194 20:15:11.984442
9195 20:15:11.984552
9196 20:15:11.994110 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 20:15:11.996991 ARM64: Exception handlers installed.
9198 20:15:12.000523 ARM64: Testing exception
9199 20:15:12.003955 ARM64: Done test exception
9200 20:15:12.004076 Enumerating buses...
9201 20:15:12.007260 Show all devs... Before device enumeration.
9202 20:15:12.010575 Root Device: enabled 1
9203 20:15:12.014126 CPU_CLUSTER: 0: enabled 1
9204 20:15:12.014248 CPU: 00: enabled 1
9205 20:15:12.017086 Compare with tree...
9206 20:15:12.017207 Root Device: enabled 1
9207 20:15:12.021235 CPU_CLUSTER: 0: enabled 1
9208 20:15:12.024005 CPU: 00: enabled 1
9209 20:15:12.024122 Root Device scanning...
9210 20:15:12.026985 scan_static_bus for Root Device
9211 20:15:12.030931 CPU_CLUSTER: 0 enabled
9212 20:15:12.034412 scan_static_bus for Root Device done
9213 20:15:12.036902 scan_bus: bus Root Device finished in 8 msecs
9214 20:15:12.036998 done
9215 20:15:12.043514 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 20:15:12.047232 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 20:15:12.054040 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 20:15:12.057203 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 20:15:12.060424 Allocating resources...
9220 20:15:12.060504 Reading resources...
9221 20:15:12.067187 Root Device read_resources bus 0 link: 0
9222 20:15:12.067269 DRAM rank0 size:0x100000000,
9223 20:15:12.070433 DRAM rank1 size=0x100000000
9224 20:15:12.073436 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 20:15:12.076755 CPU: 00 missing read_resources
9226 20:15:12.080318 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 20:15:12.086783 Root Device read_resources bus 0 link: 0 done
9228 20:15:12.086864 Done reading resources.
9229 20:15:12.093835 Show resources in subtree (Root Device)...After reading.
9230 20:15:12.097365 Root Device child on link 0 CPU_CLUSTER: 0
9231 20:15:12.100342 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 20:15:12.110866 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 20:15:12.110993 CPU: 00
9234 20:15:12.114362 Root Device assign_resources, bus 0 link: 0
9235 20:15:12.116971 CPU_CLUSTER: 0 missing set_resources
9236 20:15:12.120408 Root Device assign_resources, bus 0 link: 0 done
9237 20:15:12.124312 Done setting resources.
9238 20:15:12.130351 Show resources in subtree (Root Device)...After assigning values.
9239 20:15:12.133847 Root Device child on link 0 CPU_CLUSTER: 0
9240 20:15:12.137043 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 20:15:12.147016 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 20:15:12.147142 CPU: 00
9243 20:15:12.150522 Done allocating resources.
9244 20:15:12.154208 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 20:15:12.157324 Enabling resources...
9246 20:15:12.157440 done.
9247 20:15:12.160676 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 20:15:12.163755 Initializing devices...
9249 20:15:12.163874 Root Device init
9250 20:15:12.167277 init hardware done!
9251 20:15:12.170421 0x00000018: ctrlr->caps
9252 20:15:12.170560 52.000 MHz: ctrlr->f_max
9253 20:15:12.173932 0.400 MHz: ctrlr->f_min
9254 20:15:12.177720 0x40ff8080: ctrlr->voltages
9255 20:15:12.177843 sclk: 390625
9256 20:15:12.180798 Bus Width = 1
9257 20:15:12.180918 sclk: 390625
9258 20:15:12.181030 Bus Width = 1
9259 20:15:12.184132 Early init status = 3
9260 20:15:12.187122 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 20:15:12.191353 in-header: 03 fc 00 00 01 00 00 00
9262 20:15:12.195067 in-data: 00
9263 20:15:12.197775 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 20:15:12.202781 in-header: 03 fd 00 00 00 00 00 00
9265 20:15:12.206274 in-data:
9266 20:15:12.209397 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 20:15:12.213244 in-header: 03 fc 00 00 01 00 00 00
9268 20:15:12.216581 in-data: 00
9269 20:15:12.220234 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 20:15:12.225789 in-header: 03 fd 00 00 00 00 00 00
9271 20:15:12.228985 in-data:
9272 20:15:12.232584 [SSUSB] Setting up USB HOST controller...
9273 20:15:12.235358 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 20:15:12.239075 [SSUSB] phy power-on done.
9275 20:15:12.241876 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 20:15:12.249254 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 20:15:12.252166 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 20:15:12.259068 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 20:15:12.265387 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 20:15:12.272059 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 20:15:12.278565 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 20:15:12.285591 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9283 20:15:12.289574 SPM: binary array size = 0x9dc
9284 20:15:12.292375 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 20:15:12.299001 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 20:15:12.305609 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 20:15:12.309029 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 20:15:12.312191 configure_display: Starting display init
9289 20:15:12.348794 anx7625_power_on_init: Init interface.
9290 20:15:12.352790 anx7625_disable_pd_protocol: Disabled PD feature.
9291 20:15:12.355360 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 20:15:12.383593 anx7625_start_dp_work: Secure OCM version=00
9293 20:15:12.386727 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 20:15:12.401177 sp_tx_get_edid_block: EDID Block = 1
9295 20:15:12.504287 Extracted contents:
9296 20:15:12.507648 header: 00 ff ff ff ff ff ff 00
9297 20:15:12.510561 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 20:15:12.513870 version: 01 04
9299 20:15:12.517408 basic params: 95 1f 11 78 0a
9300 20:15:12.520440 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 20:15:12.523765 established: 00 00 00
9302 20:15:12.531003 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 20:15:12.533709 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 20:15:12.540992 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 20:15:12.547347 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 20:15:12.553703 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 20:15:12.556901 extensions: 00
9308 20:15:12.557020 checksum: fb
9309 20:15:12.557130
9310 20:15:12.560385 Manufacturer: IVO Model 57d Serial Number 0
9311 20:15:12.563832 Made week 0 of 2020
9312 20:15:12.563950 EDID version: 1.4
9313 20:15:12.567116 Digital display
9314 20:15:12.570172 6 bits per primary color channel
9315 20:15:12.570291 DisplayPort interface
9316 20:15:12.574490 Maximum image size: 31 cm x 17 cm
9317 20:15:12.577632 Gamma: 220%
9318 20:15:12.577750 Check DPMS levels
9319 20:15:12.580733 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 20:15:12.583520 First detailed timing is preferred timing
9321 20:15:12.587455 Established timings supported:
9322 20:15:12.590302 Standard timings supported:
9323 20:15:12.590427 Detailed timings
9324 20:15:12.598075 Hex of detail: 383680a07038204018303c0035ae10000019
9325 20:15:12.600611 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 20:15:12.604213 0780 0798 07c8 0820 hborder 0
9327 20:15:12.610599 0438 043b 0447 0458 vborder 0
9328 20:15:12.610719 -hsync -vsync
9329 20:15:12.613896 Did detailed timing
9330 20:15:12.617321 Hex of detail: 000000000000000000000000000000000000
9331 20:15:12.620600 Manufacturer-specified data, tag 0
9332 20:15:12.626887 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 20:15:12.627008 ASCII string: InfoVision
9334 20:15:12.633609 Hex of detail: 000000fe00523134304e574635205248200a
9335 20:15:12.633693 ASCII string: R140NWF5 RH
9336 20:15:12.638346 Checksum
9337 20:15:12.638504 Checksum: 0xfb (valid)
9338 20:15:12.643789 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 20:15:12.643910 DSI data_rate: 832800000 bps
9340 20:15:12.651329 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 20:15:12.655361 anx7625_parse_edid: pixelclock(138800).
9342 20:15:12.658164 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 20:15:12.661504 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 20:15:12.664676 anx7625_dsi_config: config dsi.
9345 20:15:12.671899 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 20:15:12.685754 anx7625_dsi_config: success to config DSI
9347 20:15:12.689497 anx7625_dp_start: MIPI phy setup OK.
9348 20:15:12.692458 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 20:15:12.695879 mtk_ddp_mode_set invalid vrefresh 60
9350 20:15:12.699327 main_disp_path_setup
9351 20:15:12.699408 ovl_layer_smi_id_en
9352 20:15:12.702315 ovl_layer_smi_id_en
9353 20:15:12.702480 ccorr_config
9354 20:15:12.702589 aal_config
9355 20:15:12.706064 gamma_config
9356 20:15:12.706181 postmask_config
9357 20:15:12.709368 dither_config
9358 20:15:12.712570 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 20:15:12.719137 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 20:15:12.722313 Root Device init finished in 553 msecs
9361 20:15:12.722463 CPU_CLUSTER: 0 init
9362 20:15:12.732792 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 20:15:12.735901 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 20:15:12.739541 APU_MBOX 0x190000b0 = 0x10001
9365 20:15:12.742876 APU_MBOX 0x190001b0 = 0x10001
9366 20:15:12.746330 APU_MBOX 0x190005b0 = 0x10001
9367 20:15:12.749340 APU_MBOX 0x190006b0 = 0x10001
9368 20:15:12.752783 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 20:15:12.765524 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9370 20:15:12.777433 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 20:15:12.784032 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 20:15:12.795869 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9373 20:15:12.805101 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 20:15:12.808131 CPU_CLUSTER: 0 init finished in 81 msecs
9375 20:15:12.811809 Devices initialized
9376 20:15:12.815342 Show all devs... After init.
9377 20:15:12.815465 Root Device: enabled 1
9378 20:15:12.818603 CPU_CLUSTER: 0: enabled 1
9379 20:15:12.821388 CPU: 00: enabled 1
9380 20:15:12.825242 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9381 20:15:12.828504 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 20:15:12.831348 ELOG: NV offset 0x57f000 size 0x1000
9383 20:15:12.838358 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9384 20:15:12.844916 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 20:15:12.848062 ELOG: Event(17) added with size 13 at 2024-03-03 20:15:12 UTC
9386 20:15:12.851819 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 20:15:12.855819 in-header: 03 d5 00 00 2c 00 00 00
9388 20:15:12.868906 in-data: 8a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9389 20:15:12.876297 ELOG: Event(A1) added with size 10 at 2024-03-03 20:15:12 UTC
9390 20:15:12.882741 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9391 20:15:12.889127 ELOG: Event(A0) added with size 9 at 2024-03-03 20:15:12 UTC
9392 20:15:12.892093 elog_add_boot_reason: Logged dev mode boot
9393 20:15:12.895652 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9394 20:15:12.898943 Finalize devices...
9395 20:15:12.899062 Devices finalized
9396 20:15:12.905790 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 20:15:12.908915 Writing coreboot table at 0xffe64000
9398 20:15:12.912382 0. 000000000010a000-0000000000113fff: RAMSTAGE
9399 20:15:12.915937 1. 0000000040000000-00000000400fffff: RAM
9400 20:15:12.919561 2. 0000000040100000-000000004032afff: RAMSTAGE
9401 20:15:12.925981 3. 000000004032b000-00000000545fffff: RAM
9402 20:15:12.929271 4. 0000000054600000-000000005465ffff: BL31
9403 20:15:12.932514 5. 0000000054660000-00000000ffe63fff: RAM
9404 20:15:12.936151 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9405 20:15:12.942505 7. 0000000100000000-000000023fffffff: RAM
9406 20:15:12.942626 Passing 5 GPIOs to payload:
9407 20:15:12.949013 NAME | PORT | POLARITY | VALUE
9408 20:15:12.952686 EC in RW | 0x000000aa | low | undefined
9409 20:15:12.959646 EC interrupt | 0x00000005 | low | undefined
9410 20:15:12.962278 TPM interrupt | 0x000000ab | high | undefined
9411 20:15:12.966218 SD card detect | 0x00000011 | high | undefined
9412 20:15:12.972644 speaker enable | 0x00000093 | high | undefined
9413 20:15:12.975719 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9414 20:15:12.979151 in-header: 03 f9 00 00 02 00 00 00
9415 20:15:12.979274 in-data: 02 00
9416 20:15:12.982313 ADC[4]: Raw value=900221 ID=7
9417 20:15:12.985799 ADC[3]: Raw value=213336 ID=1
9418 20:15:12.985917 RAM Code: 0x71
9419 20:15:12.988851 ADC[6]: Raw value=74926 ID=0
9420 20:15:12.992607 ADC[5]: Raw value=212229 ID=1
9421 20:15:12.992726 SKU Code: 0x1
9422 20:15:12.999129 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum eb57
9423 20:15:13.002434 coreboot table: 964 bytes.
9424 20:15:13.005384 IMD ROOT 0. 0xfffff000 0x00001000
9425 20:15:13.009053 IMD SMALL 1. 0xffffe000 0x00001000
9426 20:15:13.012031 RO MCACHE 2. 0xffffc000 0x00001104
9427 20:15:13.015316 CONSOLE 3. 0xfff7c000 0x00080000
9428 20:15:13.018991 FMAP 4. 0xfff7b000 0x00000452
9429 20:15:13.022598 TIME STAMP 5. 0xfff7a000 0x00000910
9430 20:15:13.025522 VBOOT WORK 6. 0xfff66000 0x00014000
9431 20:15:13.029629 RAMOOPS 7. 0xffe66000 0x00100000
9432 20:15:13.032238 COREBOOT 8. 0xffe64000 0x00002000
9433 20:15:13.032359 IMD small region:
9434 20:15:13.035433 IMD ROOT 0. 0xffffec00 0x00000400
9435 20:15:13.039075 VPD 1. 0xffffeb80 0x0000006c
9436 20:15:13.042820 MMC STATUS 2. 0xffffeb60 0x00000004
9437 20:15:13.049288 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9438 20:15:13.049409 Probing TPM: done!
9439 20:15:13.055976 Connected to device vid:did:rid of 1ae0:0028:00
9440 20:15:13.062431 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9441 20:15:13.066453 Initialized TPM device CR50 revision 0
9442 20:15:13.069873 Checking cr50 for pending updates
9443 20:15:13.075228 Reading cr50 TPM mode
9444 20:15:13.084036 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9445 20:15:13.091004 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9446 20:15:13.130403 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9447 20:15:13.133838 Checking segment from ROM address 0x40100000
9448 20:15:13.137659 Checking segment from ROM address 0x4010001c
9449 20:15:13.144003 Loading segment from ROM address 0x40100000
9450 20:15:13.144123 code (compression=0)
9451 20:15:13.150849 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9452 20:15:13.160955 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9453 20:15:13.161076 it's not compressed!
9454 20:15:13.168092 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9455 20:15:13.170760 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9456 20:15:13.191085 Loading segment from ROM address 0x4010001c
9457 20:15:13.191207 Entry Point 0x80000000
9458 20:15:13.194564 Loaded segments
9459 20:15:13.198282 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9460 20:15:13.204835 Jumping to boot code at 0x80000000(0xffe64000)
9461 20:15:13.211759 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9462 20:15:13.218055 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9463 20:15:13.225901 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9464 20:15:13.228837 Checking segment from ROM address 0x40100000
9465 20:15:13.232165 Checking segment from ROM address 0x4010001c
9466 20:15:13.239438 Loading segment from ROM address 0x40100000
9467 20:15:13.239559 code (compression=1)
9468 20:15:13.245485 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9469 20:15:13.255672 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9470 20:15:13.255797 using LZMA
9471 20:15:13.263805 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9472 20:15:13.270795 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9473 20:15:13.274739 Loading segment from ROM address 0x4010001c
9474 20:15:13.274856 Entry Point 0x54601000
9475 20:15:13.277321 Loaded segments
9476 20:15:13.280827 NOTICE: MT8192 bl31_setup
9477 20:15:13.288010 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9478 20:15:13.291630 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9479 20:15:13.294550 WARNING: region 0:
9480 20:15:13.298198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 20:15:13.298317 WARNING: region 1:
9482 20:15:13.304325 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9483 20:15:13.307354 WARNING: region 2:
9484 20:15:13.311193 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9485 20:15:13.314270 WARNING: region 3:
9486 20:15:13.317770 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 20:15:13.321127 WARNING: region 4:
9488 20:15:13.324859 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 20:15:13.328034 WARNING: region 5:
9490 20:15:13.331748 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 20:15:13.334405 WARNING: region 6:
9492 20:15:13.338166 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 20:15:13.338287 WARNING: region 7:
9494 20:15:13.344612 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 20:15:13.351512 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9496 20:15:13.354473 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9497 20:15:13.358544 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9498 20:15:13.361562 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9499 20:15:13.367792 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9500 20:15:13.371967 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9501 20:15:13.378311 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9502 20:15:13.381513 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9503 20:15:13.384723 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9504 20:15:13.391665 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9505 20:15:13.394709 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9506 20:15:13.397966 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9507 20:15:13.405807 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9508 20:15:13.408443 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9509 20:15:13.415358 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9510 20:15:13.418311 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9511 20:15:13.421551 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9512 20:15:13.428339 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9513 20:15:13.432093 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9514 20:15:13.435411 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9515 20:15:13.441857 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9516 20:15:13.445685 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9517 20:15:13.448499 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9518 20:15:13.455274 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9519 20:15:13.458704 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9520 20:15:13.465075 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9521 20:15:13.468625 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9522 20:15:13.472243 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9523 20:15:13.478723 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9524 20:15:13.482513 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9525 20:15:13.488743 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9526 20:15:13.492054 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9527 20:15:13.495342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9528 20:15:13.499303 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9529 20:15:13.505804 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9530 20:15:13.508909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9531 20:15:13.512371 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9532 20:15:13.516207 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9533 20:15:13.522509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9534 20:15:13.526340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9535 20:15:13.529183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9536 20:15:13.532489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9537 20:15:13.535722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9538 20:15:13.542687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9539 20:15:13.545704 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9540 20:15:13.549180 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9541 20:15:13.556034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9542 20:15:13.559362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9543 20:15:13.562637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9544 20:15:13.569483 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9545 20:15:13.572820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9546 20:15:13.576118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9547 20:15:13.582733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9548 20:15:13.586052 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9549 20:15:13.592910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9550 20:15:13.596375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9551 20:15:13.602909 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9552 20:15:13.606269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9553 20:15:13.609466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9554 20:15:13.616479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9555 20:15:13.619573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9556 20:15:13.626195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9557 20:15:13.629389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9558 20:15:13.636553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9559 20:15:13.639752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9560 20:15:13.643259 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9561 20:15:13.649878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9562 20:15:13.653409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9563 20:15:13.659719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9564 20:15:13.663275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9565 20:15:13.666741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9566 20:15:13.673237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9567 20:15:13.676627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9568 20:15:13.683052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9569 20:15:13.686879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9570 20:15:13.693071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9571 20:15:13.697318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9572 20:15:13.699822 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9573 20:15:13.706863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9574 20:15:13.710115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9575 20:15:13.716802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9576 20:15:13.719817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9577 20:15:13.727317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9578 20:15:13.730663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9579 20:15:13.733745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9580 20:15:13.740499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9581 20:15:13.743935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9582 20:15:13.750288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9583 20:15:13.753389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9584 20:15:13.757737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9585 20:15:13.764070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9586 20:15:13.767087 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9587 20:15:13.773591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9588 20:15:13.777148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9589 20:15:13.784195 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9590 20:15:13.788008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9591 20:15:13.790595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9592 20:15:13.797438 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9593 20:15:13.800575 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9594 20:15:13.803793 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9595 20:15:13.807315 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9596 20:15:13.813664 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9597 20:15:13.817141 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9598 20:15:13.824041 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9599 20:15:13.827371 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9600 20:15:13.830828 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9601 20:15:13.837502 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9602 20:15:13.841114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9603 20:15:13.844262 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9604 20:15:13.851200 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9605 20:15:13.854456 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9606 20:15:13.861071 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9607 20:15:13.864398 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9608 20:15:13.867825 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9609 20:15:13.874654 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9610 20:15:13.878531 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9611 20:15:13.881148 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9612 20:15:13.888021 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9613 20:15:13.891409 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9614 20:15:13.894370 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9615 20:15:13.897938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9616 20:15:13.904945 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9617 20:15:13.907949 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9618 20:15:13.910956 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9619 20:15:13.917751 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9620 20:15:13.921553 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9621 20:15:13.924537 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9622 20:15:13.930982 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9623 20:15:13.935252 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9624 20:15:13.937933 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9625 20:15:13.944657 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9626 20:15:13.948174 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9627 20:15:13.955045 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9628 20:15:13.957834 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9629 20:15:13.961706 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9630 20:15:13.968055 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9631 20:15:13.971444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9632 20:15:13.974887 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9633 20:15:13.981411 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9634 20:15:13.985721 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9635 20:15:13.991745 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9636 20:15:13.995289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9637 20:15:13.998068 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9638 20:15:14.005150 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9639 20:15:14.008303 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9640 20:15:14.011662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9641 20:15:14.018246 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9642 20:15:14.021746 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9643 20:15:14.028677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9644 20:15:14.031475 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9645 20:15:14.038010 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9646 20:15:14.041717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9647 20:15:14.044922 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9648 20:15:14.052279 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9649 20:15:14.054916 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9650 20:15:14.057968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9651 20:15:14.064901 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9652 20:15:14.068476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9653 20:15:14.071568 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9654 20:15:14.078195 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9655 20:15:14.081931 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9656 20:15:14.089077 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9657 20:15:14.092086 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9658 20:15:14.095432 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9659 20:15:14.101434 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9660 20:15:14.104897 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9661 20:15:14.112102 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9662 20:15:14.115299 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9663 20:15:14.118318 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9664 20:15:14.125138 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9665 20:15:14.128112 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9666 20:15:14.134840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9667 20:15:14.138572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9668 20:15:14.141672 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9669 20:15:14.148224 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9670 20:15:14.152241 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9671 20:15:14.154999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9672 20:15:14.161616 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9673 20:15:14.164763 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9674 20:15:14.172450 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9675 20:15:14.174638 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9676 20:15:14.178113 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9677 20:15:14.184941 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9678 20:15:14.188413 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9679 20:15:14.194952 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9680 20:15:14.198568 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9681 20:15:14.201782 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9682 20:15:14.208130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9683 20:15:14.211518 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9684 20:15:14.218112 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9685 20:15:14.221991 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9686 20:15:14.224744 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9687 20:15:14.231869 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9688 20:15:14.236167 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9689 20:15:14.242136 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9690 20:15:14.245350 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9691 20:15:14.248395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9692 20:15:14.255015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9693 20:15:14.258242 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9694 20:15:14.264905 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9695 20:15:14.268526 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9696 20:15:14.271774 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9697 20:15:14.278350 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9698 20:15:14.282351 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9699 20:15:14.288746 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9700 20:15:14.291557 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9701 20:15:14.298538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9702 20:15:14.301629 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9703 20:15:14.304954 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9704 20:15:14.312304 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9705 20:15:14.314988 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9706 20:15:14.321733 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9707 20:15:14.324742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9708 20:15:14.328213 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9709 20:15:14.335008 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9710 20:15:14.338277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9711 20:15:14.344881 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9712 20:15:14.348064 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9713 20:15:14.351670 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9714 20:15:14.358778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9715 20:15:14.361841 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9716 20:15:14.368311 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9717 20:15:14.371418 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9718 20:15:14.374889 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9719 20:15:14.381607 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9720 20:15:14.385343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9721 20:15:14.391741 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9722 20:15:14.394949 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9723 20:15:14.402050 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9724 20:15:14.405225 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9725 20:15:14.408272 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9726 20:15:14.412088 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9727 20:15:14.414897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9728 20:15:14.421950 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9729 20:15:14.425147 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9730 20:15:14.428371 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9731 20:15:14.435403 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9732 20:15:14.438200 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9733 20:15:14.441897 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9734 20:15:14.448381 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9735 20:15:14.451533 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9736 20:15:14.458292 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9737 20:15:14.461518 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9738 20:15:14.464764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9739 20:15:14.471820 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9740 20:15:14.474970 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9741 20:15:14.478063 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9742 20:15:14.484945 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9743 20:15:14.488079 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9744 20:15:14.491559 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9745 20:15:14.498928 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9746 20:15:14.501683 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9747 20:15:14.507835 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9748 20:15:14.511164 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9749 20:15:14.515210 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9750 20:15:14.521794 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9751 20:15:14.524509 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9752 20:15:14.527857 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9753 20:15:14.534662 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9754 20:15:14.538130 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9755 20:15:14.541063 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9756 20:15:14.548916 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9757 20:15:14.551015 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9758 20:15:14.554299 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9759 20:15:14.561662 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9760 20:15:14.564477 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9761 20:15:14.570904 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9762 20:15:14.574290 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9763 20:15:14.577791 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9764 20:15:14.584315 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9765 20:15:14.587764 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9766 20:15:14.591226 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9767 20:15:14.594320 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9768 20:15:14.597699 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9769 20:15:14.604491 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9770 20:15:14.607677 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9771 20:15:14.611155 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9772 20:15:14.614920 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9773 20:15:14.621789 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9774 20:15:14.624886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9775 20:15:14.628107 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9776 20:15:14.630854 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9777 20:15:14.637961 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9778 20:15:14.641095 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9779 20:15:14.647757 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9780 20:15:14.651859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9781 20:15:14.657592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9782 20:15:14.661543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9783 20:15:14.664555 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9784 20:15:14.671517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9785 20:15:14.674581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9786 20:15:14.681542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9787 20:15:14.684773 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9788 20:15:14.687892 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9789 20:15:14.694514 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9790 20:15:14.697725 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9791 20:15:14.704408 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9792 20:15:14.707670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9793 20:15:14.711313 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9794 20:15:14.717688 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9795 20:15:14.721462 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9796 20:15:14.727725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9797 20:15:14.731378 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9798 20:15:14.734217 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9799 20:15:14.741171 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9800 20:15:14.744301 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9801 20:15:14.750806 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9802 20:15:14.754352 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9803 20:15:14.758373 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9804 20:15:14.765034 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9805 20:15:14.767899 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9806 20:15:14.774353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9807 20:15:14.777736 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9808 20:15:14.780940 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9809 20:15:14.787881 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9810 20:15:14.790655 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9811 20:15:14.797525 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9812 20:15:14.800659 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9813 20:15:14.807507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9814 20:15:14.811008 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9815 20:15:14.814220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9816 20:15:14.820847 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9817 20:15:14.823969 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9818 20:15:14.827806 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9819 20:15:14.834228 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9820 20:15:14.837524 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9821 20:15:14.843995 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9822 20:15:14.848110 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9823 20:15:14.854591 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9824 20:15:14.857942 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9825 20:15:14.861622 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9826 20:15:14.867393 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9827 20:15:14.870943 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9828 20:15:14.877564 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9829 20:15:14.880802 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9830 20:15:14.884152 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9831 20:15:14.890971 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9832 20:15:14.894308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9833 20:15:14.898273 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9834 20:15:14.904148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9835 20:15:14.907813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9836 20:15:14.914257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9837 20:15:14.917699 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9838 20:15:14.924907 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9839 20:15:14.927575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9840 20:15:14.931219 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9841 20:15:14.938019 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9842 20:15:14.941394 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9843 20:15:14.944509 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9844 20:15:14.951353 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9845 20:15:14.954321 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9846 20:15:14.960876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9847 20:15:14.964445 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9848 20:15:14.968190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9849 20:15:14.974346 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9850 20:15:14.977990 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9851 20:15:14.984595 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9852 20:15:14.987883 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9853 20:15:14.995445 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9854 20:15:14.998420 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9855 20:15:15.004369 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9856 20:15:15.008055 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9857 20:15:15.011576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9858 20:15:15.017944 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9859 20:15:15.021962 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9860 20:15:15.028232 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9861 20:15:15.031114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9862 20:15:15.037684 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9863 20:15:15.041392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9864 20:15:15.044308 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9865 20:15:15.050935 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9866 20:15:15.054232 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9867 20:15:15.062370 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9868 20:15:15.064540 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9869 20:15:15.070837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9870 20:15:15.074804 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9871 20:15:15.077455 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9872 20:15:15.084571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9873 20:15:15.088315 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9874 20:15:15.094102 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9875 20:15:15.097715 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9876 20:15:15.104124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9877 20:15:15.107880 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9878 20:15:15.114473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9879 20:15:15.117254 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9880 20:15:15.120473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9881 20:15:15.127724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9882 20:15:15.130434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9883 20:15:15.136994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9884 20:15:15.140249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9885 20:15:15.147210 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9886 20:15:15.150538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9887 20:15:15.154303 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9888 20:15:15.160442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9889 20:15:15.164150 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9890 20:15:15.170427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9891 20:15:15.173957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9892 20:15:15.180752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9893 20:15:15.184983 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9894 20:15:15.186990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9895 20:15:15.193299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9896 20:15:15.197104 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9897 20:15:15.204047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9898 20:15:15.207182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9899 20:15:15.210717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9900 20:15:15.216837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9901 20:15:15.220878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9902 20:15:15.226727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9903 20:15:15.230663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9904 20:15:15.237146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9905 20:15:15.240111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9906 20:15:15.247244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9907 20:15:15.250200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9908 20:15:15.256747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9909 20:15:15.259995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9910 20:15:15.267151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9911 20:15:15.270204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9912 20:15:15.276794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9913 20:15:15.280477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9914 20:15:15.286728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9915 20:15:15.290139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9916 20:15:15.296906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9917 20:15:15.300555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9918 20:15:15.306796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9919 20:15:15.310089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9920 20:15:15.316539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9921 20:15:15.320124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9922 20:15:15.326602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9923 20:15:15.329949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9924 20:15:15.337068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9925 20:15:15.340966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9926 20:15:15.347250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9927 20:15:15.350103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9928 20:15:15.356895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9929 20:15:15.360364 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9930 20:15:15.360445 INFO: [APUAPC] vio 0
9931 20:15:15.367433 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9932 20:15:15.371080 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9933 20:15:15.373738 INFO: [APUAPC] D0_APC_0: 0x400510
9934 20:15:15.377200 INFO: [APUAPC] D0_APC_1: 0x0
9935 20:15:15.380477 INFO: [APUAPC] D0_APC_2: 0x1540
9936 20:15:15.384099 INFO: [APUAPC] D0_APC_3: 0x0
9937 20:15:15.387373 INFO: [APUAPC] D1_APC_0: 0xffffffff
9938 20:15:15.390921 INFO: [APUAPC] D1_APC_1: 0xffffffff
9939 20:15:15.394683 INFO: [APUAPC] D1_APC_2: 0x3fffff
9940 20:15:15.397664 INFO: [APUAPC] D1_APC_3: 0x0
9941 20:15:15.400906 INFO: [APUAPC] D2_APC_0: 0xffffffff
9942 20:15:15.404264 INFO: [APUAPC] D2_APC_1: 0xffffffff
9943 20:15:15.407314 INFO: [APUAPC] D2_APC_2: 0x3fffff
9944 20:15:15.410804 INFO: [APUAPC] D2_APC_3: 0x0
9945 20:15:15.414044 INFO: [APUAPC] D3_APC_0: 0xffffffff
9946 20:15:15.417693 INFO: [APUAPC] D3_APC_1: 0xffffffff
9947 20:15:15.420277 INFO: [APUAPC] D3_APC_2: 0x3fffff
9948 20:15:15.420358 INFO: [APUAPC] D3_APC_3: 0x0
9949 20:15:15.423800 INFO: [APUAPC] D4_APC_0: 0xffffffff
9950 20:15:15.430922 INFO: [APUAPC] D4_APC_1: 0xffffffff
9951 20:15:15.431003 INFO: [APUAPC] D4_APC_2: 0x3fffff
9952 20:15:15.433757 INFO: [APUAPC] D4_APC_3: 0x0
9953 20:15:15.437455 INFO: [APUAPC] D5_APC_0: 0xffffffff
9954 20:15:15.440752 INFO: [APUAPC] D5_APC_1: 0xffffffff
9955 20:15:15.444448 INFO: [APUAPC] D5_APC_2: 0x3fffff
9956 20:15:15.447369 INFO: [APUAPC] D5_APC_3: 0x0
9957 20:15:15.450776 INFO: [APUAPC] D6_APC_0: 0xffffffff
9958 20:15:15.453987 INFO: [APUAPC] D6_APC_1: 0xffffffff
9959 20:15:15.457142 INFO: [APUAPC] D6_APC_2: 0x3fffff
9960 20:15:15.460557 INFO: [APUAPC] D6_APC_3: 0x0
9961 20:15:15.464042 INFO: [APUAPC] D7_APC_0: 0xffffffff
9962 20:15:15.467408 INFO: [APUAPC] D7_APC_1: 0xffffffff
9963 20:15:15.470599 INFO: [APUAPC] D7_APC_2: 0x3fffff
9964 20:15:15.474119 INFO: [APUAPC] D7_APC_3: 0x0
9965 20:15:15.477324 INFO: [APUAPC] D8_APC_0: 0xffffffff
9966 20:15:15.480875 INFO: [APUAPC] D8_APC_1: 0xffffffff
9967 20:15:15.484017 INFO: [APUAPC] D8_APC_2: 0x3fffff
9968 20:15:15.487410 INFO: [APUAPC] D8_APC_3: 0x0
9969 20:15:15.490335 INFO: [APUAPC] D9_APC_0: 0xffffffff
9970 20:15:15.494146 INFO: [APUAPC] D9_APC_1: 0xffffffff
9971 20:15:15.497732 INFO: [APUAPC] D9_APC_2: 0x3fffff
9972 20:15:15.500807 INFO: [APUAPC] D9_APC_3: 0x0
9973 20:15:15.503938 INFO: [APUAPC] D10_APC_0: 0xffffffff
9974 20:15:15.507297 INFO: [APUAPC] D10_APC_1: 0xffffffff
9975 20:15:15.510740 INFO: [APUAPC] D10_APC_2: 0x3fffff
9976 20:15:15.514193 INFO: [APUAPC] D10_APC_3: 0x0
9977 20:15:15.517547 INFO: [APUAPC] D11_APC_0: 0xffffffff
9978 20:15:15.521342 INFO: [APUAPC] D11_APC_1: 0xffffffff
9979 20:15:15.524335 INFO: [APUAPC] D11_APC_2: 0x3fffff
9980 20:15:15.527737 INFO: [APUAPC] D11_APC_3: 0x0
9981 20:15:15.531009 INFO: [APUAPC] D12_APC_0: 0xffffffff
9982 20:15:15.534188 INFO: [APUAPC] D12_APC_1: 0xffffffff
9983 20:15:15.537397 INFO: [APUAPC] D12_APC_2: 0x3fffff
9984 20:15:15.540956 INFO: [APUAPC] D12_APC_3: 0x0
9985 20:15:15.544330 INFO: [APUAPC] D13_APC_0: 0xffffffff
9986 20:15:15.547094 INFO: [APUAPC] D13_APC_1: 0xffffffff
9987 20:15:15.550635 INFO: [APUAPC] D13_APC_2: 0x3fffff
9988 20:15:15.554231 INFO: [APUAPC] D13_APC_3: 0x0
9989 20:15:15.557447 INFO: [APUAPC] D14_APC_0: 0xffffffff
9990 20:15:15.561402 INFO: [APUAPC] D14_APC_1: 0xffffffff
9991 20:15:15.564409 INFO: [APUAPC] D14_APC_2: 0x3fffff
9992 20:15:15.567633 INFO: [APUAPC] D14_APC_3: 0x0
9993 20:15:15.570948 INFO: [APUAPC] D15_APC_0: 0xffffffff
9994 20:15:15.574240 INFO: [APUAPC] D15_APC_1: 0xffffffff
9995 20:15:15.577929 INFO: [APUAPC] D15_APC_2: 0x3fffff
9996 20:15:15.580747 INFO: [APUAPC] D15_APC_3: 0x0
9997 20:15:15.583954 INFO: [APUAPC] APC_CON: 0x4
9998 20:15:15.587254 INFO: [NOCDAPC] D0_APC_0: 0x0
9999 20:15:15.587334 INFO: [NOCDAPC] D0_APC_1: 0x0
10000 20:15:15.591310 INFO: [NOCDAPC] D1_APC_0: 0x0
10001 20:15:15.595404 INFO: [NOCDAPC] D1_APC_1: 0xfff
10002 20:15:15.597537 INFO: [NOCDAPC] D2_APC_0: 0x0
10003 20:15:15.600860 INFO: [NOCDAPC] D2_APC_1: 0xfff
10004 20:15:15.604018 INFO: [NOCDAPC] D3_APC_0: 0x0
10005 20:15:15.607785 INFO: [NOCDAPC] D3_APC_1: 0xfff
10006 20:15:15.610625 INFO: [NOCDAPC] D4_APC_0: 0x0
10007 20:15:15.613923 INFO: [NOCDAPC] D4_APC_1: 0xfff
10008 20:15:15.617520 INFO: [NOCDAPC] D5_APC_0: 0x0
10009 20:15:15.620403 INFO: [NOCDAPC] D5_APC_1: 0xfff
10010 20:15:15.620483 INFO: [NOCDAPC] D6_APC_0: 0x0
10011 20:15:15.624044 INFO: [NOCDAPC] D6_APC_1: 0xfff
10012 20:15:15.627282 INFO: [NOCDAPC] D7_APC_0: 0x0
10013 20:15:15.630871 INFO: [NOCDAPC] D7_APC_1: 0xfff
10014 20:15:15.634370 INFO: [NOCDAPC] D8_APC_0: 0x0
10015 20:15:15.637715 INFO: [NOCDAPC] D8_APC_1: 0xfff
10016 20:15:15.641298 INFO: [NOCDAPC] D9_APC_0: 0x0
10017 20:15:15.643904 INFO: [NOCDAPC] D9_APC_1: 0xfff
10018 20:15:15.647534 INFO: [NOCDAPC] D10_APC_0: 0x0
10019 20:15:15.650287 INFO: [NOCDAPC] D10_APC_1: 0xfff
10020 20:15:15.654224 INFO: [NOCDAPC] D11_APC_0: 0x0
10021 20:15:15.657298 INFO: [NOCDAPC] D11_APC_1: 0xfff
10022 20:15:15.657405 INFO: [NOCDAPC] D12_APC_0: 0x0
10023 20:15:15.661074 INFO: [NOCDAPC] D12_APC_1: 0xfff
10024 20:15:15.663962 INFO: [NOCDAPC] D13_APC_0: 0x0
10025 20:15:15.667153 INFO: [NOCDAPC] D13_APC_1: 0xfff
10026 20:15:15.670696 INFO: [NOCDAPC] D14_APC_0: 0x0
10027 20:15:15.673469 INFO: [NOCDAPC] D14_APC_1: 0xfff
10028 20:15:15.677659 INFO: [NOCDAPC] D15_APC_0: 0x0
10029 20:15:15.680718 INFO: [NOCDAPC] D15_APC_1: 0xfff
10030 20:15:15.683681 INFO: [NOCDAPC] APC_CON: 0x4
10031 20:15:15.687491 INFO: [APUAPC] set_apusys_apc done
10032 20:15:15.690342 INFO: [DEVAPC] devapc_init done
10033 20:15:15.693990 INFO: GICv3 without legacy support detected.
10034 20:15:15.697107 INFO: ARM GICv3 driver initialized in EL3
10035 20:15:15.700806 INFO: Maximum SPI INTID supported: 639
10036 20:15:15.707659 INFO: BL31: Initializing runtime services
10037 20:15:15.711196 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10038 20:15:15.714729 INFO: SPM: enable CPC mode
10039 20:15:15.720308 INFO: mcdi ready for mcusys-off-idle and system suspend
10040 20:15:15.723880 INFO: BL31: Preparing for EL3 exit to normal world
10041 20:15:15.727232 INFO: Entry point address = 0x80000000
10042 20:15:15.730437 INFO: SPSR = 0x8
10043 20:15:15.736253
10044 20:15:15.736333
10045 20:15:15.736396
10046 20:15:15.739051 Starting depthcharge on Spherion...
10047 20:15:15.739131
10048 20:15:15.739194 Wipe memory regions:
10049 20:15:15.739253
10050 20:15:15.739955 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10051 20:15:15.740063 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10052 20:15:15.740148 Setting prompt string to ['asurada:']
10053 20:15:15.740226 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10054 20:15:15.742261 [0x00000040000000, 0x00000054600000)
10055 20:15:15.864561
10056 20:15:15.864663 [0x00000054660000, 0x00000080000000)
10057 20:15:16.124719
10058 20:15:16.124845 [0x000000821a7280, 0x000000ffe64000)
10059 20:15:16.869435
10060 20:15:16.869591 [0x00000100000000, 0x00000240000000)
10061 20:15:18.759004
10062 20:15:18.761861 Initializing XHCI USB controller at 0x11200000.
10063 20:15:19.800547
10064 20:15:19.803262 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10065 20:15:19.803368
10066 20:15:19.803458
10067 20:15:19.803545
10068 20:15:19.803854 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 20:15:19.904234 asurada: tftpboot 192.168.201.1 12928151/tftp-deploy-nv35dnge/kernel/image.itb 12928151/tftp-deploy-nv35dnge/kernel/cmdline
10071 20:15:19.904374 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 20:15:19.904549 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10073 20:15:19.909175 tftpboot 192.168.201.1 12928151/tftp-deploy-nv35dnge/kernel/image.ittp-deploy-nv35dnge/kernel/cmdline
10074 20:15:19.909280
10075 20:15:19.909371 Waiting for link
10076 20:15:20.069205
10077 20:15:20.069385 R8152: Initializing
10078 20:15:20.069453
10079 20:15:20.072893 Version 6 (ocp_data = 5c30)
10080 20:15:20.072975
10081 20:15:20.075838 R8152: Done initializing
10082 20:15:20.075918
10083 20:15:20.075982 Adding net device
10084 20:15:21.978201
10085 20:15:21.978358 done.
10086 20:15:21.978453
10087 20:15:21.978546 MAC: 00:24:32:30:78:52
10088 20:15:21.978648
10089 20:15:21.981712 Sending DHCP discover... done.
10090 20:15:21.981794
10091 20:15:21.984771 Waiting for reply... done.
10092 20:15:21.984867
10093 20:15:21.987790 Sending DHCP request... done.
10094 20:15:21.987871
10095 20:15:21.993480 Waiting for reply... done.
10096 20:15:21.993560
10097 20:15:21.993625 My ip is 192.168.201.14
10098 20:15:21.993685
10099 20:15:21.997055 The DHCP server ip is 192.168.201.1
10100 20:15:21.997135
10101 20:15:22.003288 TFTP server IP predefined by user: 192.168.201.1
10102 20:15:22.003369
10103 20:15:22.009955 Bootfile predefined by user: 12928151/tftp-deploy-nv35dnge/kernel/image.itb
10104 20:15:22.010036
10105 20:15:22.010100 Sending tftp read request... done.
10106 20:15:22.012872
10107 20:15:22.016824 Waiting for the transfer...
10108 20:15:22.016906
10109 20:15:22.552589 00000000 ################################################################
10110 20:15:22.552743
10111 20:15:23.112857 00080000 ################################################################
10112 20:15:23.112995
10113 20:15:23.657616 00100000 ################################################################
10114 20:15:23.657752
10115 20:15:24.219794 00180000 ################################################################
10116 20:15:24.219935
10117 20:15:24.782300 00200000 ################################################################
10118 20:15:24.782510
10119 20:15:25.353035 00280000 ################################################################
10120 20:15:25.353194
10121 20:15:25.899916 00300000 ################################################################
10122 20:15:25.900068
10123 20:15:26.446701 00380000 ################################################################
10124 20:15:26.446843
10125 20:15:26.987582 00400000 ################################################################
10126 20:15:26.987730
10127 20:15:27.516743 00480000 ################################################################
10128 20:15:27.516905
10129 20:15:28.057977 00500000 ################################################################
10130 20:15:28.058113
10131 20:15:28.594182 00580000 ################################################################
10132 20:15:28.594319
10133 20:15:29.126253 00600000 ################################################################
10134 20:15:29.126434
10135 20:15:29.660942 00680000 ################################################################
10136 20:15:29.661090
10137 20:15:30.204974 00700000 ################################################################
10138 20:15:30.205178
10139 20:15:30.748869 00780000 ################################################################
10140 20:15:30.749002
10141 20:15:31.312222 00800000 ################################################################
10142 20:15:31.312363
10143 20:15:31.881094 00880000 ################################################################
10144 20:15:31.881239
10145 20:15:32.440189 00900000 ################################################################
10146 20:15:32.440348
10147 20:15:32.971180 00980000 ################################################################
10148 20:15:32.971314
10149 20:15:33.518040 00a00000 ################################################################
10150 20:15:33.518223
10151 20:15:34.074194 00a80000 ################################################################
10152 20:15:34.074348
10153 20:15:34.643010 00b00000 ################################################################
10154 20:15:34.643169
10155 20:15:35.207572 00b80000 ################################################################
10156 20:15:35.207768
10157 20:15:35.768459 00c00000 ################################################################
10158 20:15:35.768662
10159 20:15:36.310801 00c80000 ################################################################
10160 20:15:36.310945
10161 20:15:36.847349 00d00000 ################################################################
10162 20:15:36.847556
10163 20:15:37.394526 00d80000 ################################################################
10164 20:15:37.394723
10165 20:15:37.923133 00e00000 ################################################################
10166 20:15:37.923291
10167 20:15:38.472408 00e80000 ################################################################
10168 20:15:38.472561
10169 20:15:39.011135 00f00000 ################################################################
10170 20:15:39.011293
10171 20:15:39.534875 00f80000 ################################################################
10172 20:15:39.535024
10173 20:15:40.079490 01000000 ################################################################
10174 20:15:40.079643
10175 20:15:40.612542 01080000 ################################################################
10176 20:15:40.612689
10177 20:15:41.146876 01100000 ################################################################
10178 20:15:41.147043
10179 20:15:41.705517 01180000 ################################################################
10180 20:15:41.705666
10181 20:15:42.238815 01200000 ################################################################
10182 20:15:42.238981
10183 20:15:42.787943 01280000 ################################################################
10184 20:15:42.788088
10185 20:15:43.334678 01300000 ################################################################
10186 20:15:43.334827
10187 20:15:43.904384 01380000 ################################################################
10188 20:15:43.904586
10189 20:15:44.480186 01400000 ################################################################
10190 20:15:44.480331
10191 20:15:45.014177 01480000 ################################################################
10192 20:15:45.014326
10193 20:15:45.579489 01500000 ################################################################
10194 20:15:45.579637
10195 20:15:46.157205 01580000 ################################################################
10196 20:15:46.157415
10197 20:15:46.696670 01600000 ################################################################
10198 20:15:46.696820
10199 20:15:47.265765 01680000 ################################################################
10200 20:15:47.265915
10201 20:15:47.839853 01700000 ################################################################
10202 20:15:47.840005
10203 20:15:48.401427 01780000 ################################################################
10204 20:15:48.401575
10205 20:15:48.937716 01800000 ################################################################
10206 20:15:48.937870
10207 20:15:49.477923 01880000 ################################################################
10208 20:15:49.478070
10209 20:15:50.023179 01900000 ################################################################
10210 20:15:50.023329
10211 20:15:50.544425 01980000 ################################################################
10212 20:15:50.544577
10213 20:15:51.102347 01a00000 ################################################################
10214 20:15:51.102543
10215 20:15:51.655234 01a80000 ################################################################
10216 20:15:51.655378
10217 20:15:52.198603 01b00000 ################################################################
10218 20:15:52.198748
10219 20:15:52.742021 01b80000 ################################################################
10220 20:15:52.742165
10221 20:15:53.292856 01c00000 ################################################################
10222 20:15:53.292998
10223 20:15:53.823280 01c80000 ################################################################
10224 20:15:53.823425
10225 20:15:54.362300 01d00000 ################################################################
10226 20:15:54.362487
10227 20:15:54.900376 01d80000 ################################################################
10228 20:15:54.900513
10229 20:15:55.451903 01e00000 ################################################################
10230 20:15:55.452045
10231 20:15:55.997949 01e80000 ################################################################
10232 20:15:55.998092
10233 20:15:56.523152 01f00000 ################################################################
10234 20:15:56.523295
10235 20:15:57.068906 01f80000 ################################################################
10236 20:15:57.069048
10237 20:15:57.612744 02000000 ################################################################
10238 20:15:57.612891
10239 20:15:58.163824 02080000 ################################################################
10240 20:15:58.163967
10241 20:15:58.734340 02100000 ################################################################
10242 20:15:58.734557
10243 20:15:59.283493 02180000 ################################################################
10244 20:15:59.283658
10245 20:15:59.820531 02200000 ################################################################
10246 20:15:59.820678
10247 20:16:00.362932 02280000 ################################################################
10248 20:16:00.363079
10249 20:16:00.920324 02300000 ################################################################
10250 20:16:00.920476
10251 20:16:01.470612 02380000 ################################################################
10252 20:16:01.470758
10253 20:16:02.034160 02400000 ################################################################
10254 20:16:02.034371
10255 20:16:02.592251 02480000 ################################################################
10256 20:16:02.592454
10257 20:16:03.163831 02500000 ################################################################
10258 20:16:03.163981
10259 20:16:03.723066 02580000 ################################################################
10260 20:16:03.723210
10261 20:16:04.276620 02600000 ################################################################
10262 20:16:04.276772
10263 20:16:04.806815 02680000 ################################################################
10264 20:16:04.806962
10265 20:16:05.330597 02700000 ################################################################
10266 20:16:05.330742
10267 20:16:05.865866 02780000 ################################################################
10268 20:16:05.866077
10269 20:16:06.414320 02800000 ################################################################
10270 20:16:06.414577
10271 20:16:06.936079 02880000 ################################################################
10272 20:16:06.936222
10273 20:16:07.493017 02900000 ################################################################
10274 20:16:07.493163
10275 20:16:08.050676 02980000 ################################################################
10276 20:16:08.050824
10277 20:16:08.588520 02a00000 ################################################################
10278 20:16:08.588731
10279 20:16:09.122677 02a80000 ################################################################
10280 20:16:09.122822
10281 20:16:09.668042 02b00000 ################################################################
10282 20:16:09.668190
10283 20:16:10.199486 02b80000 ################################################################
10284 20:16:10.199637
10285 20:16:10.728701 02c00000 ################################################################
10286 20:16:10.728847
10287 20:16:11.288332 02c80000 ################################################################
10288 20:16:11.288480
10289 20:16:11.849059 02d00000 ################################################################
10290 20:16:11.849209
10291 20:16:12.407328 02d80000 ################################################################
10292 20:16:12.407473
10293 20:16:12.970125 02e00000 ################################################################
10294 20:16:12.970274
10295 20:16:13.516686 02e80000 ################################################################
10296 20:16:13.516838
10297 20:16:14.080755 02f00000 ################################################################
10298 20:16:14.080963
10299 20:16:14.654233 02f80000 ################################################################
10300 20:16:14.654407
10301 20:16:15.211730 03000000 ################################################################
10302 20:16:15.211942
10303 20:16:15.733209 03080000 ################################################################
10304 20:16:15.733357
10305 20:16:15.844752 03100000 ############## done.
10306 20:16:15.844941
10307 20:16:15.848149 The bootfile was 51489286 bytes long.
10308 20:16:15.848233
10309 20:16:15.851584 Sending tftp read request... done.
10310 20:16:15.851669
10311 20:16:15.855574 Waiting for the transfer...
10312 20:16:15.855658
10313 20:16:15.858684 00000000 # done.
10314 20:16:15.858795
10315 20:16:15.865263 Command line loaded dynamically from TFTP file: 12928151/tftp-deploy-nv35dnge/kernel/cmdline
10316 20:16:15.865347
10317 20:16:15.878499 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10318 20:16:15.878609
10319 20:16:15.878709 Loading FIT.
10320 20:16:15.881886
10321 20:16:15.881959 Image ramdisk-1 has 39379936 bytes.
10322 20:16:15.882021
10323 20:16:15.885006 Image fdt-1 has 47278 bytes.
10324 20:16:15.885086
10325 20:16:15.888066 Image kernel-1 has 12060038 bytes.
10326 20:16:15.888147
10327 20:16:15.898556 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10328 20:16:15.898662
10329 20:16:15.914677 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10330 20:16:15.914763
10331 20:16:15.921869 Choosing best match conf-1 for compat google,spherion-rev2.
10332 20:16:15.921950
10333 20:16:15.929411 Connected to device vid:did:rid of 1ae0:0028:00
10334 20:16:15.937868
10335 20:16:15.940968 tpm_get_response: command 0x17b, return code 0x0
10336 20:16:15.941076
10337 20:16:15.947650 ec_init: CrosEC protocol v3 supported (256, 248)
10338 20:16:15.947732
10339 20:16:15.951051 tpm_cleanup: add release locality here.
10340 20:16:15.951131
10341 20:16:15.953945 Shutting down all USB controllers.
10342 20:16:15.954026
10343 20:16:15.957661 Removing current net device
10344 20:16:15.957741
10345 20:16:15.961030 Exiting depthcharge with code 4 at timestamp: 89628318
10346 20:16:15.961161
10347 20:16:15.964539 LZMA decompressing kernel-1 to 0x821a6718
10348 20:16:15.967705
10349 20:16:15.971094 LZMA decompressing kernel-1 to 0x40000000
10350 20:16:17.468991
10351 20:16:17.469145 jumping to kernel
10352 20:16:17.469686 end: 2.2.4 bootloader-commands (duration 00:01:02) [common]
10353 20:16:17.469793 start: 2.2.5 auto-login-action (timeout 00:03:23) [common]
10354 20:16:17.469878 Setting prompt string to ['Linux version [0-9]']
10355 20:16:17.469960 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10356 20:16:17.470042 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10357 20:16:17.551004
10358 20:16:17.554484 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10359 20:16:17.557834 start: 2.2.5.1 login-action (timeout 00:03:23) [common]
10360 20:16:17.557956 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10361 20:16:17.558039 Setting prompt string to []
10362 20:16:17.558157 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10363 20:16:17.558269 Using line separator: #'\n'#
10364 20:16:17.558361 No login prompt set.
10365 20:16:17.558471 Parsing kernel messages
10366 20:16:17.558563 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10367 20:16:17.558741 [login-action] Waiting for messages, (timeout 00:03:23)
10368 20:16:17.558843 Waiting using forced prompt support (timeout 00:01:42)
10369 20:16:17.577357 [ 0.000000] Linux version 6.1.80-cip16-rt9 (KernelCI@build-j129309-arm64-gcc-10-defconfig-arm64-chromebook-czjxn) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024
10370 20:16:17.580575 [ 0.000000] random: crng init done
10371 20:16:17.587517 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10372 20:16:17.590770 [ 0.000000] efi: UEFI not found.
10373 20:16:17.597579 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10374 20:16:17.607611 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10375 20:16:17.614472 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10376 20:16:17.624455 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10377 20:16:17.630997 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10378 20:16:17.636954 [ 0.000000] printk: bootconsole [mtk8250] enabled
10379 20:16:17.644357 [ 0.000000] NUMA: No NUMA configuration found
10380 20:16:17.650047 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10381 20:16:17.653460 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10382 20:16:17.656748 [ 0.000000] Zone ranges:
10383 20:16:17.663431 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10384 20:16:17.668093 [ 0.000000] DMA32 empty
10385 20:16:17.674547 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10386 20:16:17.676959 [ 0.000000] Movable zone start for each node
10387 20:16:17.680686 [ 0.000000] Early memory node ranges
10388 20:16:17.687986 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10389 20:16:17.693331 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10390 20:16:17.700498 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10391 20:16:17.706721 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10392 20:16:17.713677 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10393 20:16:17.720161 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10394 20:16:17.775784 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10395 20:16:17.782799 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10396 20:16:17.789634 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10397 20:16:17.792834 [ 0.000000] psci: probing for conduit method from DT.
10398 20:16:17.799730 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10399 20:16:17.802330 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10400 20:16:17.809371 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10401 20:16:17.812460 [ 0.000000] psci: SMC Calling Convention v1.2
10402 20:16:17.819358 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10403 20:16:17.822578 [ 0.000000] Detected VIPT I-cache on CPU0
10404 20:16:17.828824 [ 0.000000] CPU features: detected: GIC system register CPU interface
10405 20:16:17.835796 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10406 20:16:17.842046 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10407 20:16:17.849288 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10408 20:16:17.855212 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10409 20:16:17.862264 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10410 20:16:17.869286 [ 0.000000] alternatives: applying boot alternatives
10411 20:16:17.872059 [ 0.000000] Fallback order for Node 0: 0
10412 20:16:17.882213 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10413 20:16:17.885156 [ 0.000000] Policy zone: Normal
10414 20:16:17.898520 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10415 20:16:17.908895 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10416 20:16:17.920251 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10417 20:16:17.930326 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10418 20:16:17.936886 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10419 20:16:17.940589 <6>[ 0.000000] software IO TLB: area num 8.
10420 20:16:17.997006 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10421 20:16:18.147262 <6>[ 0.000000] Memory: 7928740K/8385536K available (18048K kernel code, 4120K rwdata, 19616K rodata, 8448K init, 616K bss, 424028K reserved, 32768K cma-reserved)
10422 20:16:18.153823 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10423 20:16:18.160913 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10424 20:16:18.164171 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10425 20:16:18.170161 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10426 20:16:18.176509 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10427 20:16:18.180209 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10428 20:16:18.190061 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10429 20:16:18.196619 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10430 20:16:18.199760 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10431 20:16:18.208096 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10432 20:16:18.211191 <6>[ 0.000000] GICv3: 608 SPIs implemented
10433 20:16:18.217522 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10434 20:16:18.220969 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10435 20:16:18.224329 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10436 20:16:18.234385 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10437 20:16:18.244352 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10438 20:16:18.258362 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10439 20:16:18.264305 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10440 20:16:18.273797 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10441 20:16:18.286665 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10442 20:16:18.293059 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10443 20:16:18.300436 <6>[ 0.009232] Console: colour dummy device 80x25
10444 20:16:18.309569 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10445 20:16:18.314113 <6>[ 0.024392] pid_max: default: 32768 minimum: 301
10446 20:16:18.319649 <6>[ 0.029265] LSM: Security Framework initializing
10447 20:16:18.326497 <6>[ 0.034202] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 20:16:18.336191 <6>[ 0.042066] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10449 20:16:18.343054 <6>[ 0.051476] cblist_init_generic: Setting adjustable number of callback queues.
10450 20:16:18.349751 <6>[ 0.058965] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 20:16:18.359808 <6>[ 0.065343] cblist_init_generic: Setting adjustable number of callback queues.
10452 20:16:18.363431 <6>[ 0.072771] cblist_init_generic: Setting shift to 3 and lim to 1.
10453 20:16:18.370242 <6>[ 0.079213] rcu: Hierarchical SRCU implementation.
10454 20:16:18.376779 <6>[ 0.079215] rcu: Max phase no-delay instances is 1000.
10455 20:16:18.382810 <6>[ 0.079239] printk: bootconsole [mtk8250] printing thread started
10456 20:16:18.389448 <6>[ 0.097564] EFI services will not be available.
10457 20:16:18.393259 <6>[ 0.097757] smp: Bringing up secondary CPUs ...
10458 20:16:18.396476 <6>[ 0.098037] Detected VIPT I-cache on CPU1
10459 20:16:18.403068 <6>[ 0.098092] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10460 20:16:18.409630 <6>[ 0.098116] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10461 20:16:18.421438 <6>[ 0.125967] Detected VIPT I-cache on CPU2
10462 20:16:18.427963 <6>[ 0.126013] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10463 20:16:18.438230 <6>[ 0.126027] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10464 20:16:18.441384 <6>[ 0.126284] Detected VIPT I-cache on CPU3
10465 20:16:18.448076 <6>[ 0.126330] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10466 20:16:18.454300 <6>[ 0.126343] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10467 20:16:18.458075 <6>[ 0.126657] CPU features: detected: Spectre-v4
10468 20:16:18.464116 <6>[ 0.126663] CPU features: detected: Spectre-BHB
10469 20:16:18.467748 <6>[ 0.126669] Detected PIPT I-cache on CPU4
10470 20:16:18.474119 <6>[ 0.126727] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10471 20:16:18.480673 <6>[ 0.126744] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10472 20:16:18.488004 <6>[ 0.127039] Detected PIPT I-cache on CPU5
10473 20:16:18.494409 <6>[ 0.127100] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10474 20:16:18.500973 <6>[ 0.127115] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10475 20:16:18.504452 <6>[ 0.127391] Detected PIPT I-cache on CPU6
10476 20:16:18.513835 <6>[ 0.127454] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10477 20:16:18.520708 <6>[ 0.127469] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10478 20:16:18.524140 <6>[ 0.127766] Detected PIPT I-cache on CPU7
10479 20:16:18.531059 <6>[ 0.127830] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10480 20:16:18.537671 <6>[ 0.127846] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10481 20:16:18.540867 <6>[ 0.127893] smp: Brought up 1 node, 8 CPUs
10482 20:16:18.547631 <6>[ 0.127897] SMP: Total of 8 processors activated.
10483 20:16:18.550551 <6>[ 0.127900] CPU features: detected: 32-bit EL0 Support
10484 20:16:18.561262 <6>[ 0.127902] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10485 20:16:18.567643 <6>[ 0.127905] CPU features: detected: Common not Private translations
10486 20:16:18.574312 <6>[ 0.127907] CPU features: detected: CRC32 instructions
10487 20:16:18.577868 <6>[ 0.127910] CPU features: detected: RCpc load-acquire (LDAPR)
10488 20:16:18.583775 <6>[ 0.127911] CPU features: detected: LSE atomic instructions
10489 20:16:18.590484 <6>[ 0.127913] CPU features: detected: Privileged Access Never
10490 20:16:18.597712 <6>[ 0.127914] CPU features: detected: RAS Extension Support
10491 20:16:18.603684 <6>[ 0.127917] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10492 20:16:18.607758 <6>[ 0.127987] CPU: All CPU(s) started at EL2
10493 20:16:18.614045 <6>[ 0.127989] alternatives: applying system-wide alternatives
10494 20:16:18.617411 <6>[ 0.141193] devtmpfs: initialized
10495 20:16:18.627061 <6>[ 0.147395] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10496 20:16:18.656546 �@I����ѕɕ���}%9Q��ɽѽ����2�����5R�<6>[ <0.364792] printk: console [ttyS0] printing thread started
10497 20:16:18.662226 6<6>[ 0.364822] printk: console [ttyS0] enabled
10498 20:16:18.668303 >[ 0.228789] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10499 20:16:18.675569 <6>[ 0.364826] printk: bootconsole [mtk8250] disabled
10500 20:16:18.682348 <6>[ 0.382912] printk: bootconsole [mtk8250] printing thread stopped
10501 20:16:18.685527 <6>[ 0.384133] SuperH (H)SCI(F) driver initialized
10502 20:16:18.692327 <6>[ 0.384620] msm_serial: driver initialized
10503 20:16:18.698998 <6>[ 0.389170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10504 20:16:18.709413 <6>[ 0.389200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10505 20:16:18.716272 <6>[ 0.389229] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10506 20:16:18.725243 <6>[ 0.389258] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10507 20:16:18.744093 <6>[ 0.389280] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10508 20:16:18.744427 <6>[ 0.389308] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10509 20:16:18.760475 <6>[ 0.389335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10510 20:16:18.760958 <6>[ 0.389476] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10511 20:16:18.770335 <6>[ 0.389506] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10512 20:16:18.774964 <6>[ 0.400285] loop: module loaded
10513 20:16:18.779279 <6>[ 0.402882] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10514 20:16:18.785880 <4>[ 0.419603] mtk-pmic-keys: Failed to locate of_node [id: -1]
10515 20:16:18.789265 <6>[ 0.420535] megasas: 07.719.03.00-rc1
10516 20:16:18.795691 <6>[ 0.432821] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10517 20:16:18.799138 <6>[ 0.432967] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10518 20:16:18.806345 <6>[ 0.444794] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10519 20:16:18.816143 <6>[ 0.498661] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10520 20:16:20.119526 <6>[ 1.825928] Freeing initrd memory: 38452K
10521 20:16:20.126723 <6>[ 1.832236] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10522 20:16:20.129701 <6>[ 1.836951] tun: Universal TUN/TAP device driver, 1.6
10523 20:16:20.133537 <6>[ 1.837729] thunder_xcv, ver 1.0
10524 20:16:20.136571 <6>[ 1.837748] thunder_bgx, ver 1.0
10525 20:16:20.140649 <6>[ 1.837766] nicpf, ver 1.0
10526 20:16:20.146627 <6>[ 1.838813] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10527 20:16:20.152755 <6>[ 1.838816] hns3: Copyright (c) 2017 Huawei Corporation.
10528 20:16:20.156163 <6>[ 1.838842] hclge is initializing
10529 20:16:20.163126 <6>[ 1.838858] e1000: Intel(R) PRO/1000 Network Driver
10530 20:16:20.169560 <6>[ 1.838860] e1000: Copyright (c) 1999-2006 Intel Corporation.
10531 20:16:20.173090 <6>[ 1.838879] e1000e: Intel(R) PRO/1000 Network Driver
10532 20:16:20.179888 <6>[ 1.838881] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10533 20:16:20.183895 <6>[ 1.838899] igb: Intel(R) Gigabit Ethernet Network Driver
10534 20:16:20.190684 <6>[ 1.838901] igb: Copyright (c) 2007-2014 Intel Corporation.
10535 20:16:20.197687 <6>[ 1.838916] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10536 20:16:20.204187 <6>[ 1.838919] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10537 20:16:20.208045 <6>[ 1.839216] sky2: driver version 1.30
10538 20:16:20.214538 <6>[ 1.840283] VFIO - User Level meta-driver version: 0.3
10539 20:16:20.218044 <6>[ 1.843134] usbcore: registered new interface driver usb-storage
10540 20:16:20.224544 <6>[ 1.843317] usbcore: registered new device driver onboard-usb-hub
10541 20:16:20.231716 <6>[ 1.846129] mt6397-rtc mt6359-rtc: registered as rtc0
10542 20:16:20.241012 <6>[ 1.846280] mt6397-rtc mt6359-rtc: setting system clock to 2024-03-03T20:16:20 UTC (1709496980)
10543 20:16:20.244614 <6>[ 1.846893] i2c_dev: i2c /dev entries driver
10544 20:16:20.251797 <6>[ 1.854119] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10545 20:16:20.258194 <6>[ 1.870117] cpu cpu0: EM: created perf domain
10546 20:16:20.260902 <6>[ 1.870460] cpu cpu4: EM: created perf domain
10547 20:16:20.267789 <6>[ 1.871938] sdhci: Secure Digital Host Controller Interface driver
10548 20:16:20.270999 <6>[ 1.871939] sdhci: Copyright(c) Pierre Ossman
10549 20:16:20.277865 <6>[ 1.872298] Synopsys Designware Multimedia Card Interface Driver
10550 20:16:20.284657 <6>[ 1.872662] sdhci-pltfm: SDHCI platform and OF driver helper
10551 20:16:20.287572 <6>[ 1.877233] mmc0: CQHCI version 5.10
10552 20:16:20.294089 <6>[ 1.883000] ledtrig-cpu: registered to indicate activity on CPUs
10553 20:16:20.300757 <6>[ 1.883832] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10554 20:16:20.307639 <6>[ 1.884103] usbcore: registered new interface driver usbhid
10555 20:16:20.310522 <6>[ 1.884105] usbhid: USB HID core driver
10556 20:16:20.317606 <6>[ 1.884228] spi_master spi0: will run message pump with realtime priority
10557 20:16:20.330782 <6>[ 1.915031] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10558 20:16:20.344415 <6>[ 1.916896] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10559 20:16:20.350716 <6>[ 1.918906] cros-ec-spi spi0.0: Chrome EC device registered
10560 20:16:20.360956 <6>[ 1.931153] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10561 20:16:20.364142 <6>[ 1.932143] NET: Registered PF_PACKET protocol family
10562 20:16:20.370183 <6>[ 1.932220] 9pnet: Installing 9P2000 support
10563 20:16:20.374008 <5>[ 1.932255] Key type dns_resolver registered
10564 20:16:20.377402 <6>[ 1.932646] registered taskstats version 1
10565 20:16:20.384153 <5>[ 1.932665] Loading compiled-in X.509 certificates
10566 20:16:20.393292 <4>[ 1.949689] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 20:16:20.403707 <4>[ 1.949990] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 20:16:20.410353 <3>[ 1.950019] debugfs: File 'uA_load' in directory '/' already present!
10569 20:16:20.416741 <3>[ 1.950030] debugfs: File 'min_uV' in directory '/' already present!
10570 20:16:20.423941 <3>[ 1.950037] debugfs: File 'max_uV' in directory '/' already present!
10571 20:16:20.433657 <3>[ 1.950044] debugfs: File 'constraint_flags' in directory '/' already present!
10572 20:16:20.440099 <3>[ 1.953583] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10573 20:16:20.446777 <6>[ 1.962080] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10574 20:16:20.453622 <6>[ 1.962674] xhci-mtk 11200000.usb: xHCI Host Controller
10575 20:16:20.460060 <6>[ 1.962690] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10576 20:16:20.469950 <6>[ 1.962897] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10577 20:16:20.476799 <6>[ 1.962944] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10578 20:16:20.480117 <6>[ 1.963035] xhci-mtk 11200000.usb: xHCI Host Controller
10579 20:16:20.489347 <6>[ 1.963042] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10580 20:16:20.496207 <6>[ 1.963049] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10581 20:16:20.499465 <6>[ 1.963485] hub 1-0:1.0: USB hub found
10582 20:16:20.502960 <6>[ 1.963502] hub 1-0:1.0: 1 port detected
10583 20:16:20.512901 <6>[ 1.963676] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10584 20:16:20.516045 <6>[ 1.964068] hub 2-0:1.0: USB hub found
10585 20:16:20.519197 <6>[ 1.964084] hub 2-0:1.0: 1 port detected
10586 20:16:20.526350 <6>[ 1.967131] mtk-msdc 11f70000.mmc: Got CD GPIO
10587 20:16:20.529101 <6>[ 1.976376] mmc0: Command Queue Engine enabled
10588 20:16:20.535581 <6>[ 1.976389] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10589 20:16:20.539437 <6>[ 1.977004] mmcblk0: mmc0:0001 DA4128 116 GiB
10590 20:16:20.546190 <6>[ 1.980445] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10591 20:16:20.555984 <6>[ 1.981624] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10592 20:16:20.562489 <6>[ 1.981632] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10593 20:16:20.568605 <6>[ 1.981762] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10594 20:16:20.576058 <4>[ 1.981812] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10595 20:16:20.582002 <6>[ 1.982367] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10596 20:16:20.588533 <6>[ 1.982449] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10597 20:16:20.598456 <6>[ 1.982452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10598 20:16:20.605429 <6>[ 1.982595] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10599 20:16:20.611928 <6>[ 1.982607] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10600 20:16:20.621808 <6>[ 1.982612] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10601 20:16:20.631813 <6>[ 1.982619] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10602 20:16:20.638439 <6>[ 1.982933] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10603 20:16:20.644957 <6>[ 1.984801] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10604 20:16:20.655040 <6>[ 1.984818] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10605 20:16:20.661740 <6>[ 1.984824] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10606 20:16:20.671454 <6>[ 1.984829] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10607 20:16:20.677990 <6>[ 1.984834] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10608 20:16:20.688251 <6>[ 1.984840] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10609 20:16:20.694612 <6>[ 1.984845] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10610 20:16:20.704772 <6>[ 1.984850] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10611 20:16:20.711578 <6>[ 1.984855] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10612 20:16:20.721168 <6>[ 1.984860] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10613 20:16:20.728036 <6>[ 1.984866] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10614 20:16:20.737958 <6>[ 1.984871] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10615 20:16:20.744559 <6>[ 1.984877] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10616 20:16:20.754497 <6>[ 1.984886] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10617 20:16:20.761112 <6>[ 1.984891] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10618 20:16:20.767405 <6>[ 1.985496] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10619 20:16:20.774460 <6>[ 1.986571] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10620 20:16:20.781071 <6>[ 1.987128] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10621 20:16:20.787792 <6>[ 1.987742] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10622 20:16:20.794754 <6>[ 1.988384] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10623 20:16:20.803889 <6>[ 1.988563] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10624 20:16:20.814257 <6>[ 1.988578] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10625 20:16:20.824300 <6>[ 1.988584] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10626 20:16:20.830978 <6>[ 1.988590] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10627 20:16:20.840463 <6>[ 1.988596] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10628 20:16:20.851151 <6>[ 1.988602] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10629 20:16:20.860996 <6>[ 1.988607] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10630 20:16:20.870375 <6>[ 1.988613] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10631 20:16:20.876602 <6>[ 1.988618] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10632 20:16:20.890156 <6>[ 1.988625] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10633 20:16:20.900262 <6>[ 1.988630] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10634 20:16:20.906286 <6>[ 1.989174] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10635 20:16:20.913722 <6>[ 2.381555] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10636 20:16:20.916280 <6>[ 2.541639] hub 1-1:1.0: USB hub found
10637 20:16:20.923375 <6>[ 2.542028] hub 1-1:1.0: 4 ports detected
10638 20:16:20.926189 <6>[ 2.545114] hub 1-1:1.0: USB hub found
10639 20:16:20.929956 <6>[ 2.545430] hub 1-1:1.0: 4 ports detected
10640 20:16:20.962806 <6>[ 2.665705] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10641 20:16:20.983868 <6>[ 2.690622] hub 2-1:1.0: USB hub found
10642 20:16:20.986911 <6>[ 2.691029] hub 2-1:1.0: 3 ports detected
10643 20:16:20.990837 <6>[ 2.693887] hub 2-1:1.0: USB hub found
10644 20:16:20.993833 <6>[ 2.694251] hub 2-1:1.0: 3 ports detected
10645 20:16:21.155489 <6>[ 2.857768] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10646 20:16:21.275391 <6>[ 2.985345] hub 1-1.4:1.0: USB hub found
10647 20:16:21.278826 <6>[ 2.985799] hub 1-1.4:1.0: 2 ports detected
10648 20:16:21.282378 <6>[ 2.988709] hub 1-1.4:1.0: USB hub found
10649 20:16:21.289121 <6>[ 2.988993] hub 1-1.4:1.0: 2 ports detected
10650 20:16:21.363649 <6>[ 3.065795] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10651 20:16:21.574745 <6>[ 3.277698] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10652 20:16:21.759057 <6>[ 3.461705] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10653 20:16:32.563242 <6>[ 14.274748] ALSA device list:
10654 20:16:32.569760 <6>[ 14.274770] No soundcards found.
10655 20:16:32.573151 <6>[ 14.279207] Freeing unused kernel memory: 8448K
10656 20:16:32.576070 <6>[ 14.279375] Run /init as init process
10657 20:16:32.594466 <6>[ 14.302678] NET: Registered PF_INET6 protocol family
10658 20:16:32.597922 <6>[ 14.303699] Segment Routing with IPv6
10659 20:16:32.604793 <6>[ 14.303710] In-situ OAM (IOAM) with IPv6
10660 20:16:32.604874
10661 20:16:32.630917 Welcome to [1mDebian GNU/Linu<30>[ 14.319102] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10662 20:16:32.634314 <30>[ 14.319530] systemd[1]: Detected architecture arm64.
10663 20:16:32.637786 x 11 (bullseye)[0m!
10664 20:16:32.637866
10665 20:16:32.658468 <30>[ 14.365754] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10666 20:16:32.781916 <30>[ 14.488395] systemd[1]: Queued start job for default target Graphical Interface.
10667 20:16:32.816121 [[0;32m OK [0m] Created slic<30>[ 14.522727] systemd[1]: Created slice system-getty.slice.
10668 20:16:32.818547 e [0;1;39msystem-getty.slice[0m.
10669 20:16:32.843528 [[0;32m OK [0m] Created slic<30>[ 14.551316] systemd[1]: Created slice system-modprobe.slice.
10670 20:16:32.848355 e [0;1;39msystem-modprobe.slice[0m.
10671 20:16:32.869720 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.574052] systemd[1]: Created slice system-serial\x2dgetty.slice.
10672 20:16:32.872637 m-serial\x2dgetty.slice[0m.
10673 20:16:32.890894 [[0;32m OK [0m] Created slic<30>[ 14.598886] systemd[1]: Created slice User and Session Slice.
10674 20:16:32.894166 e [0;1;39mUser and Session Slice[0m.
10675 20:16:32.918346 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.622353] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10676 20:16:32.920960 ssword …ts to Console Directory Watch[0m.
10677 20:16:32.946141 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.650331] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10678 20:16:32.948982 sword R…uests to Wall Directory Watch[0m.
10679 20:16:32.977184 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.678136] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10680 20:16:32.986953 l Encrypted Volu<30>[ 14.678375] systemd[1]: Reached target Local Encrypted Volumes.
10681 20:16:32.987038 mes[0m.
10682 20:16:33.006686 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.714165] systemd[1]: Reached target Paths.
10683 20:16:33.006769 s[0m.
10684 20:16:33.028937 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.733666] systemd[1]: Reached target Remote File Systems.
10685 20:16:33.029021 te File Systems[0m.
10686 20:16:33.046052 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.753622] systemd[1]: Reached target Slices.
10687 20:16:33.046136 es[0m.
10688 20:16:33.065689 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.773668] systemd[1]: Reached target Swap.
10689 20:16:33.065772 [0m.
10690 20:16:33.089732 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.794131] systemd[1]: Listening on initctl Compatibility Named Pipe.
10691 20:16:33.092585 l Compatibility Named Pipe[0m.
10692 20:16:33.112136 [[0;32m OK [0m] Listening on<30>[ 14.819031] systemd[1]: Listening on Journal Audit Socket.
10693 20:16:33.115229 [0;1;39mJournal Audit Socket[0m.
10694 20:16:33.135189 [[0;32m OK [0m] Listening on<30>[ 14.842791] systemd[1]: Listening on Journal Socket (/dev/log).
10695 20:16:33.138301 [0;1;39mJournal Socket (/dev/log)[0m.
10696 20:16:33.159201 [[0;32m OK [0m] Listening on<30>[ 14.866799] systemd[1]: Listening on Journal Socket.
10697 20:16:33.162167 [0;1;39mJournal Socket[0m.
10698 20:16:33.181820 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.886302] systemd[1]: Listening on Network Service Netlink Socket.
10699 20:16:33.185258 k Service Netlink Socket[0m.
10700 20:16:33.203413 [[0;32m OK [0m] Listening on<30>[ 14.910851] systemd[1]: Listening on udev Control Socket.
10701 20:16:33.206219 [0;1;39mudev Control Socket[0m.
10702 20:16:33.227103 [[0;32m OK [0m] Listening on<30>[ 14.934679] systemd[1]: Listening on udev Kernel Socket.
10703 20:16:33.230366 [0;1;39mudev Kernel Socket[0m.
10704 20:16:33.289702 Mounting [0;1;39mHuge Pages File Syste<30>[ 14.993884] systemd[1]: Mounting Huge Pages File System...
10705 20:16:33.289793 m[0m...
10706 20:16:33.308026 Mounting [0;1;39mPOSIX<30>[ 15.015809] systemd[1]: Mounting POSIX Message Queue File System...
10707 20:16:33.311565 Message Queue File System[0m...
10708 20:16:33.332866 Mountin<30>[ 15.040251] systemd[1]: Mounting Kernel Debug File System...
10709 20:16:33.335935 g [0;1;39mKernel Debug File System[0m...
10710 20:16:33.360917 Startin<30>[ 15.061965] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10711 20:16:33.370908 g [0;1;39mCreat<30>[ 15.064912] systemd[1]: Starting Create list of static device nodes for the current kernel...
10712 20:16:33.373734 e list of st…odes for the current kernel[0m...
10713 20:16:33.401611 Starting [0;1;39mLoad Kernel Module co<30>[ 15.106047] systemd[1]: Starting Load Kernel Module configfs...
10714 20:16:33.401695 nfigfs[0m...
10715 20:16:33.418582 <30>[ 15.129383] systemd[1]: Starting Load Kernel Module drm...
10716 20:16:33.424823 Starting [0;1;39mLoad Kernel Module drm[0m...
10717 20:16:33.445266 <30>[ 15.150085] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10718 20:16:33.459413 Starting [0;1;39mJourn<30>[ 15.166831] systemd[1]: Starting Journal Service...
10719 20:16:33.459496 al Service[0m...
10720 20:16:33.482378 Starting [0;1;39mLoad Kernel Modules[<30>[ 15.190200] systemd[1]: Starting Load Kernel Modules...
10721 20:16:33.485481 0m...
10722 20:16:33.504466 Startin<30>[ 15.212442] systemd[1]: Starting Remount Root and Kernel File Systems...
10723 20:16:33.511011 g [0;1;39mRemount Root and Kernel File Systems[0m...
10724 20:16:33.526207 <30>[ 15.237030] systemd[1]: Starting Coldplug All udev Devices...
10725 20:16:33.533087 Starting [0;1;39mColdplug All udev Devices[0m...
10726 20:16:33.549553 [[0;32m OK [<30>[ 15.260749] systemd[1]: Started Journal Service.
10727 20:16:33.556744 0m] Started [0;1;39mJournal Service[0m.
10728 20:16:33.573647 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10729 20:16:33.591644 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10730 20:16:33.608471 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10731 20:16:33.627764 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10732 20:16:33.644326 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10733 20:16:33.659404 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10734 20:16:33.675046 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10735 20:16:33.697386 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10736 20:16:33.710031 See 'systemctl status systemd-remount-fs.service' for details.
10737 20:16:33.755484 Mounting [0;1;39mKernel Configuration File System[0m...
10738 20:16:33.773291 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10739 20:16:33.789302 <46>[ 15.494677] systemd-journald[193]: Received client request to flush runtime journal.
10740 20:16:33.798708 Starting [0;1;39mLoad/Save Random Seed[0m...
10741 20:16:33.818407 Starting [0;1;39mApply Kernel Variables[0m...
10742 20:16:33.840336 Starting [0;1;39mCreate System Users[0m...
10743 20:16:33.863959 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10744 20:16:33.879531 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10745 20:16:33.899790 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10746 20:16:33.912549 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10747 20:16:33.928458 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10748 20:16:33.944058 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10749 20:16:33.983235 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10750 20:16:34.010714 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10751 20:16:34.026788 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10752 20:16:34.042580 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10753 20:16:34.075916 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10754 20:16:34.099962 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10755 20:16:34.120760 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10756 20:16:34.142079 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10757 20:16:34.200592 Starting [0;1;39mNetwork Service[0m...
10758 20:16:34.233616 Starting [0;1;39mNetwork Time Synchronization[0m...
10759 20:16:34.255936 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10760 20:16:34.284151 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10761 20:16:34.305875 <6>[ 16.012970] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10762 20:16:34.315093 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10763 20:16:34.330406 <6>[ 16.040763] remoteproc remoteproc0: scp is available
10764 20:16:34.336767 <6>[ 16.040905] remoteproc remoteproc0: powering up scp
10765 20:16:34.343616 <6>[ 16.040917] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10766 20:16:34.350075 [[0;32m OK [<6>[ 16.040952] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10767 20:16:34.360258 0m] Found device<6>[ 16.062038] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10768 20:16:34.370050 <6>[ 16.062111] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10769 20:16:34.380307 [0;1;39m/dev/t<6>[ 16.062124] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10770 20:16:34.386494 <4>[ 16.071273] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10771 20:16:34.393168 <4>[ 16.081491] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10772 20:16:34.393250 tyS0[0m.
10773 20:16:34.409340 <3>[ 16.116865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 20:16:34.415753 <3>[ 16.116886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 20:16:34.425842 <3>[ 16.116894] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 20:16:34.432494 <3>[ 16.124092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 20:16:34.443018 <3>[ 16.124111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 20:16:34.449830 <3>[ 16.124115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 20:16:34.462472 [[0;32m OK [0m] Created slice [0;1;39msyste<3>[ 16.124120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 20:16:34.472365 m-systemd\x2dbac<3>[ 16.124124] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 20:16:34.480119 <3>[ 16.146172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 20:16:34.485939 <3>[ 16.158451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 20:16:34.495997 klight.slice[0m<3>[ 16.158471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 20:16:34.505673 <3>[ 16.158479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 20:16:34.512729 <6>[ 16.162046] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10786 20:16:34.522358 <6>[ 16.162056] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10787 20:16:34.526532 <6>[ 16.162065] remoteproc remoteproc0: remote processor scp is now up
10788 20:16:34.536240 <3>[ 16.165350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 20:16:34.536323 .
10790 20:16:34.543637 <3>[ 16.165375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 20:16:34.553234 <3>[ 16.165383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 20:16:34.559695 <3>[ 16.165398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 20:16:34.566349 <3>[ 16.165511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 20:16:34.577406 <3>[ 16.179472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 20:16:34.583230 [[0;32m OK [<6>[ 16.182433] mc: Linux media interface: v0.10
10796 20:16:34.590000 0m] Reached targ<6>[ 16.186940] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10797 20:16:34.596832 <6>[ 16.186952] pci_bus 0000:00: root bus resource [bus 00-ff]
10798 20:16:34.603440 <6>[ 16.186958] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10799 20:16:34.613161 <6>[ 16.186962] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10800 20:16:34.620003 et [0;1;39mSyst<6>[ 16.186994] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10801 20:16:34.626750 <6>[ 16.187020] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10802 20:16:34.633798 <6>[ 16.187176] pci 0000:00:00.0: supports D1 D2
10803 20:16:34.639548 <6>[ 16.187189] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10804 20:16:34.646084 <6>[ 16.188186] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10805 20:16:34.656525 em Time Set[0m.<6>[ 16.220320] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10806 20:16:34.666241 <4>[ 16.223957] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10807 20:16:34.672910 <4>[ 16.223957] Fallback method does not support PEC.
10808 20:16:34.679863 <6>[ 16.224175] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10809 20:16:34.685918 <6>[ 16.229079] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10810 20:16:34.686001
10811 20:16:34.692758 <6>[ 16.229139] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10812 20:16:34.699892 <6>[ 16.229184] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10813 20:16:34.709892 <6>[ 16.229213] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10814 20:16:34.713196 <6>[ 16.229495] pci 0000:01:00.0: supports D1 D2
10815 20:16:34.719870 <6>[ 16.229512] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10816 20:16:34.729649 <3>[ 16.248043] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10817 20:16:34.733348 <6>[ 16.260626] videodev: Linux video capture interface: v2.00
10818 20:16:34.743519 <6>[ 16.265926] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10819 20:16:34.753499 <6>[ 16.266285] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10820 20:16:34.763491 [[0;32m OK [<6>[ 16.276945] usbcore: registered new device driver r8152-cfgselector
10821 20:16:34.769686 <3>[ 16.292624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 20:16:34.776263 <6>[ 16.309545] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10823 20:16:34.783783 <6>[ 16.309632] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10824 20:16:34.793878 <6>[ 16.309639] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10825 20:16:34.800401 <6>[ 16.309654] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10826 20:16:34.809992 0m] Reached targ<6>[ 16.309671] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10827 20:16:34.819888 <6>[ 16.309688] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10828 20:16:34.823364 <6>[ 16.309707] pci 0000:00:00.0: PCI bridge to [bus 01]
10829 20:16:34.829828 <6>[ 16.309718] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10830 20:16:34.840489 et [0;1;39mSyst<6>[ 16.313333] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10831 20:16:34.843424 <6>[ 16.355949] Bluetooth: Core ver 2.22
10832 20:16:34.850683 em Time Synchron<6>[ 16.356021] NET: Registered PF_BLUETOOTH protocol family
10833 20:16:34.858736 <6>[ 16.356023] Bluetooth: HCI device and connection manager initialized
10834 20:16:34.861750 <6>[ 16.356038] Bluetooth: HCI socket layer initialized
10835 20:16:34.861832 ized[0m.
10836 20:16:34.868413 <6>[ 16.356041] Bluetooth: L2CAP socket layer initialized
10837 20:16:34.872303 <6>[ 16.356048] Bluetooth: SCO socket layer initialized
10838 20:16:34.879092 <6>[ 16.400848] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10839 20:16:34.888534 <3>[ 16.415361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 20:16:34.902261 <6>[ 16.450008] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10841 20:16:34.909372 <6>[ 16.471655] usbcore: registered new interface driver uvcvideo
10842 20:16:34.912713 <6>[ 16.472080] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10843 20:16:34.918693 <6>[ 16.479369] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10844 20:16:34.925106 <6>[ 16.479812] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10845 20:16:34.931926 <6>[ 16.479869] usbcore: registered new interface driver btusb
10846 20:16:34.942623 <4>[ 16.480949] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10847 20:16:34.949913 <3>[ 16.480982] Bluetooth: hci0: Failed to load firmware file (-2)
10848 20:16:34.953488 <3>[ 16.480990] Bluetooth: hci0: Failed to set up firmware (-2)
10849 20:16:34.963011 <4>[ 16.480997] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10850 20:16:34.973551 <3>[ 16.497366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 20:16:34.980465 <6>[ 16.509134] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10852 20:16:34.990727 <6>[ 16.526715] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10853 20:16:34.997482 <6>[ 16.533994] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10854 20:16:35.008182 <4>[ 16.536281] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10855 20:16:35.015168 <4>[ 16.536298] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10856 20:16:35.025463 <5>[ 16.537820] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10857 20:16:35.029018 <5>[ 16.547494] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10858 20:16:35.039053 <5>[ 16.547735] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10859 20:16:35.045339 <4>[ 16.547801] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10860 20:16:35.052756 <6>[ 16.547808] cfg80211: failed to load regulatory.db
10861 20:16:35.059717 <3>[ 16.581518] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10862 20:16:35.066549 <6>[ 16.589995] r8152 2-1.3:1.0 eth0: v1.12.13
10863 20:16:35.070169 <6>[ 16.590202] usbcore: registered new interface driver r8152
10864 20:16:35.077017 <6>[ 16.624585] usbcore: registered new interface driver cdc_ether
10865 20:16:35.090550 Starting [0;1;39mLoad/Save Screen …o<3>[ 16.624826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 20:16:35.097787 f leds:white:kbd<6>[ 16.637028] usbcore: registered new interface driver r8153_ecm
10867 20:16:35.108462 _backlight[0m..<6>[ 16.652734] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10868 20:16:35.108544 .
10869 20:16:35.115216 <6>[ 16.652841] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10870 20:16:35.118274 <6>[ 16.658018] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10871 20:16:35.128027 <3>[ 16.662469] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 20:16:35.135050 <3>[ 16.663367] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
10873 20:16:35.141450 <6>[ 16.669583] mt7921e 0000:01:00.0: ASIC revision: 79610010
10874 20:16:35.152224 <3>[ 16.703534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 20:16:35.161151 Starting [0;1;39mNetwo<3>[ 16.704315] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10876 20:16:35.171315 <6>[ 16.764413] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10877 20:16:35.171398 <6>[ 16.764413]
10878 20:16:35.174443 rk Name Resolution[0m...
10879 20:16:35.194583 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10880 20:16:35.214709 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10881 20:16:35.253809 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10882 20:16:35.317267 <6>[ 17.023296] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10883 20:16:35.366761 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10884 20:16:35.382583 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10885 20:16:35.401938 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10886 20:16:35.414643 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10887 20:16:35.431104 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10888 20:16:35.449699 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10889 20:16:35.462596 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10890 20:16:35.482132 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10891 20:16:35.494594 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10892 20:16:35.510323 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10893 20:16:35.530227 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10894 20:16:35.562406 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10895 20:16:35.590849 Starting [0;1;39mUser Login Management[0m...
10896 20:16:35.610386 Starting [0;1;39mPermit User Sessions[0m...
10897 20:16:35.630294 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10898 20:16:35.651923 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10899 20:16:35.670768 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10900 20:16:35.686542 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10901 20:16:35.706248 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10902 20:16:35.723206 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10903 20:16:35.738789 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10904 20:16:35.756077 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10905 20:16:35.775217 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10906 20:16:35.835266 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10907 20:16:35.866035 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10908 20:16:35.903147
10909 20:16:35.903233
10910 20:16:35.906360 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10911 20:16:35.906492
10912 20:16:35.910083 debian-bullseye-arm64 login: root (automatic login)
10913 20:16:35.910189
10914 20:16:35.910280
10915 20:16:35.927009 Linux debian-bullseye-arm64 6.1.80-cip16-rt9 #1 SMP PREEMPT Sun Mar 3 20:03:35 UTC 2024 aarch64
10916 20:16:35.927092
10917 20:16:35.934285 The programs included with the Debian GNU/Linux system are free software;
10918 20:16:35.940775 the exact distribution terms for each program are described in the
10919 20:16:35.944193 individual files in /usr/share/doc/*/copyright.
10920 20:16:35.944319
10921 20:16:35.950681 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10922 20:16:35.953816 permitted by applicable law.
10923 20:16:35.954316 Matched prompt #10: / #
10925 20:16:35.954709 Setting prompt string to ['/ #']
10926 20:16:35.954861 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10928 20:16:35.955214 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10929 20:16:35.955354 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
10930 20:16:35.955476 Setting prompt string to ['/ #']
10931 20:16:35.955583 Forcing a shell prompt, looking for ['/ #']
10933 20:16:36.005897 / #
10934 20:16:36.005995 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10935 20:16:36.006065 Waiting using forced prompt support (timeout 00:02:30)
10936 20:16:36.011177
10937 20:16:36.011445 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10938 20:16:36.011534 start: 2.2.7 export-device-env (timeout 00:03:05) [common]
10939 20:16:36.011625 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10940 20:16:36.011710 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
10941 20:16:36.011796 end: 2 depthcharge-action (duration 00:01:55) [common]
10942 20:16:36.011884 start: 3 lava-test-retry (timeout 00:07:44) [common]
10943 20:16:36.011965 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
10944 20:16:36.012036 Using namespace: common
10946 20:16:36.112357 / # #
10947 20:16:36.112473 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10948 20:16:36.117601 #
10949 20:16:36.117865 Using /lava-12928151
10951 20:16:36.218158 / # export SHELL=/bin/sh
10952 20:16:36.218316 <6>[ 17.869343] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10953 20:16:36.222961 export SHELL=/bin/sh
10955 20:16:36.323477 / # . /lava-12928151/environment
10956 20:16:36.328755 . /lava-12928151/environment
10958 20:16:36.429281 / # /lava-12928151/bin/lava-test-runner /lava-12928151/0
10959 20:16:36.429398 Test shell timeout: 10s (minimum of the action and connection timeout)
10960 20:16:36.434611 /lava-12928151/bin/lava-test-runner /lava-12928151/0
10961 20:16:36.456344 + export TESTRUN_ID=0_v4l2-compliance-uvc
10962 20:16:36.459640 + cd /lava-12928151/0/tests/0_v4l2-compliance-uvc
10963 20:16:36.459723 + cat uuid
10964 20:16:36.463198 + UUID=12928151_1.5.2.3.1
10965 20:16:36.463280 + set +x
10966 20:16:36.469705 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12928151_1.5.2.3.1>
10967 20:16:36.469963 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12928151_1.5.2.3.1
10968 20:16:36.470035 Starting test lava.0_v4l2-compliance-uvc (12928151_1.5.2.3.1)
10969 20:16:36.470119 Skipping test definition patterns.
10970 20:16:36.473317 + /usr/bin/v4l2-parser.sh -d uvcvideo
10971 20:16:36.479289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10972 20:16:36.479371 device: /dev/video0
10973 20:16:36.479606 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10975 20:16:36.500974 <6>[ 18.206007] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
10976 20:16:36.504563 <6>[ 18.208274] r8152 2-1.3:1.0 enx002432307852: carrier on
10977 20:16:42.962000 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10978 20:16:42.972091 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10979 20:16:42.979691
10980 20:16:42.995028 Compliance test for uvcvideo device /dev/video0:
10981 20:16:43.002989
10982 20:16:43.014364 Driver Info:
10983 20:16:43.023826 Driver name : uvcvideo
10984 20:16:43.041236 Card type : HD User Facing: HD User Facing
10985 20:16:43.052568 Bus info : usb-11200000.usb-1.4.1
10986 20:16:43.059714 Driver version : 6.1.80
10987 20:16:43.076143 Capabilities : 0x84a00001
10988 20:16:43.093332 Metadata Capture
10989 20:16:43.104314 Streaming
10990 20:16:43.115481 Extended Pix Format
10991 20:16:43.132324 Device Capabilities
10992 20:16:43.144084 Device Caps : 0x04200001
10993 20:16:43.159619 Streaming
10994 20:16:43.171689 Extended Pix Format
10995 20:16:43.188883 Media Driver Info:
10996 20:16:43.198670 Driver name : uvcvideo
10997 20:16:43.216442 Model : HD User Facing: HD User Facing
10998 20:16:43.224602 Serial : 200901010001
10999 20:16:43.243704 Bus info : usb-11200000.usb-1.4.1
11000 20:16:43.250668 Media version : 6.1.80
11001 20:16:43.265337 Hardware revision: 0x00009758 (38744)
11002 20:16:43.273197 Driver version : 6.1.80
11003 20:16:43.285156 Interface Info:
11004 20:16:43.301134 <LAVA_SIGNAL_TESTSET START Interface-Info>
11005 20:16:43.301217 ID : 0x03000002
11006 20:16:43.301459 Received signal: <TESTSET> START Interface-Info
11007 20:16:43.301531 Starting test_set Interface-Info
11008 20:16:43.311541 Type : V4L Video
11009 20:16:43.325854 Entity Info:
11010 20:16:43.333077 <LAVA_SIGNAL_TESTSET STOP>
11011 20:16:43.333328 Received signal: <TESTSET> STOP
11012 20:16:43.333397 Closing test_set Interface-Info
11013 20:16:43.345060 <LAVA_SIGNAL_TESTSET START Entity-Info>
11014 20:16:43.345312 Received signal: <TESTSET> START Entity-Info
11015 20:16:43.345380 Starting test_set Entity-Info
11016 20:16:43.348481 ID : 0x00000001 (1)
11017 20:16:43.359652 Name : HD User Facing: HD User Facing
11018 20:16:43.370031 Function : V4L2 I/O
11019 20:16:43.382746 Flags : default
11020 20:16:43.397074 Pad 0x01000007 : 0: Sink
11021 20:16:43.417577 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11022 20:16:43.417660
11023 20:16:43.433144 Required ioctls:
11024 20:16:43.440634 <LAVA_SIGNAL_TESTSET STOP>
11025 20:16:43.440888 Received signal: <TESTSET> STOP
11026 20:16:43.440955 Closing test_set Entity-Info
11027 20:16:43.450144 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11028 20:16:43.450419 Received signal: <TESTSET> START Required-ioctls
11029 20:16:43.450503 Starting test_set Required-ioctls
11030 20:16:43.453551 test MC information (see 'Media Driver Info' above): OK
11031 20:16:43.480836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11032 20:16:43.481091 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11034 20:16:43.484260 test VIDIOC_QUERYCAP: OK
11035 20:16:43.504277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11036 20:16:43.504531 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11038 20:16:43.507465 test invalid ioctls: OK
11039 20:16:43.530675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11040 20:16:43.530756
11041 20:16:43.530989 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11043 20:16:43.541511 Allow for multiple opens:
11044 20:16:43.548176 <LAVA_SIGNAL_TESTSET STOP>
11045 20:16:43.548436 Received signal: <TESTSET> STOP
11046 20:16:43.548507 Closing test_set Required-ioctls
11047 20:16:43.557470 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11048 20:16:43.557722 Received signal: <TESTSET> START Allow-for-multiple-opens
11049 20:16:43.557791 Starting test_set Allow-for-multiple-opens
11050 20:16:43.560804 test second /dev/video0 open: OK
11051 20:16:43.583406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11052 20:16:43.583658 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11054 20:16:43.586593 test VIDIOC_QUERYCAP: OK
11055 20:16:43.610264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11056 20:16:43.610541 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11058 20:16:43.614045 test VIDIOC_G/S_PRIORITY: OK
11059 20:16:43.635422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11060 20:16:43.635673 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11062 20:16:43.638228 test for unlimited opens: OK
11063 20:16:43.659616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11064 20:16:43.659697
11065 20:16:43.659931 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11067 20:16:43.673738 Debug ioctls:
11068 20:16:43.680848 <LAVA_SIGNAL_TESTSET STOP>
11069 20:16:43.681099 Received signal: <TESTSET> STOP
11070 20:16:43.681166 Closing test_set Allow-for-multiple-opens
11071 20:16:43.690741 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11072 20:16:43.690993 Received signal: <TESTSET> START Debug-ioctls
11073 20:16:43.691061 Starting test_set Debug-ioctls
11074 20:16:43.693536 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11075 20:16:43.715307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11076 20:16:43.715559 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11078 20:16:43.721967 test VIDIOC_LOG_STATUS: OK (Not Supported)
11079 20:16:43.740953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11080 20:16:43.741034
11081 20:16:43.741268 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11083 20:16:43.755919 Input ioctls:
11084 20:16:43.763382 <LAVA_SIGNAL_TESTSET STOP>
11085 20:16:43.763631 Received signal: <TESTSET> STOP
11086 20:16:43.763698 Closing test_set Debug-ioctls
11087 20:16:43.772360 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11088 20:16:43.772610 Received signal: <TESTSET> START Input-ioctls
11089 20:16:43.772678 Starting test_set Input-ioctls
11090 20:16:43.775788 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11091 20:16:43.801946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11092 20:16:43.802228 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11094 20:16:43.805437 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11095 20:16:43.824637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11096 20:16:43.824888 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11098 20:16:43.831637 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11099 20:16:43.853066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11100 20:16:43.853317 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11102 20:16:43.856323 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11103 20:16:43.882918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11104 20:16:43.883170 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11106 20:16:43.886371 test VIDIOC_G/S/ENUMINPUT: OK
11107 20:16:43.906196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11108 20:16:43.906473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11110 20:16:43.909791 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11111 20:16:43.932259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11112 20:16:43.932510 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11114 20:16:43.934675 Inputs: 1 Audio Inputs: 0 Tuners: 0
11115 20:16:43.942247
11116 20:16:43.958312 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11117 20:16:43.980262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11118 20:16:43.980514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11120 20:16:43.986584 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11121 20:16:44.010182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11122 20:16:44.010419 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11124 20:16:44.016744 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11125 20:16:44.035222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11126 20:16:44.035473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11128 20:16:44.038629 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11129 20:16:44.065800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11130 20:16:44.066053 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11132 20:16:44.072071 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11133 20:16:44.090899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11134 20:16:44.090980
11135 20:16:44.091214 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11137 20:16:44.111599 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11138 20:16:44.132185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11139 20:16:44.132436 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11141 20:16:44.139612 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11142 20:16:44.161375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11143 20:16:44.161626 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11145 20:16:44.164102 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11146 20:16:44.183765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11147 20:16:44.184015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11149 20:16:44.186988 test VIDIOC_G/S_EDID: OK (Not Supported)
11150 20:16:44.213638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11151 20:16:44.213720
11152 20:16:44.213952 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11154 20:16:44.225538 Control ioctls (Input 0):
11155 20:16:44.235381 <LAVA_SIGNAL_TESTSET STOP>
11156 20:16:44.235629 Received signal: <TESTSET> STOP
11157 20:16:44.235699 Closing test_set Input-ioctls
11158 20:16:44.246841 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11159 20:16:44.247091 Received signal: <TESTSET> START Control-ioctls-Input-0
11160 20:16:44.247159 Starting test_set Control-ioctls-Input-0
11161 20:16:44.250299 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11162 20:16:44.276288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11163 20:16:44.276369 test VIDIOC_QUERYCTRL: OK
11164 20:16:44.276602 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11166 20:16:44.296853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11167 20:16:44.297107 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11169 20:16:44.299824 test VIDIOC_G/S_CTRL: OK
11170 20:16:44.324298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11171 20:16:44.324549 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11173 20:16:44.327294 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11174 20:16:44.350354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11175 20:16:44.350693 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11177 20:16:44.357602 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11178 20:16:44.378375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11179 20:16:44.378685 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11181 20:16:44.382288 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11182 20:16:44.401516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11183 20:16:44.401818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11185 20:16:44.404454 Standard Controls: 16 Private Controls: 0
11186 20:16:44.411801
11187 20:16:44.422241 Format ioctls (Input 0):
11188 20:16:44.430850 <LAVA_SIGNAL_TESTSET STOP>
11189 20:16:44.431148 Received signal: <TESTSET> STOP
11190 20:16:44.431261 Closing test_set Control-ioctls-Input-0
11191 20:16:44.442524 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11192 20:16:44.442822 Received signal: <TESTSET> START Format-ioctls-Input-0
11193 20:16:44.442935 Starting test_set Format-ioctls-Input-0
11194 20:16:44.446579 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11195 20:16:44.471431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11196 20:16:44.471732 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11198 20:16:44.474853 test VIDIOC_G/S_PARM: OK
11199 20:16:44.495580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11200 20:16:44.495881 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11202 20:16:44.498079 test VIDIOC_G_FBUF: OK (Not Supported)
11203 20:16:44.520502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11204 20:16:44.520802 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11206 20:16:44.523724 test VIDIOC_G_FMT: OK
11207 20:16:44.545965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11208 20:16:44.546265 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11210 20:16:44.549890 test VIDIOC_TRY_FMT: OK
11211 20:16:44.573406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11212 20:16:44.573709 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11214 20:16:44.579722 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11215 20:16:44.583461 test VIDIOC_S_FMT: OK
11216 20:16:44.610215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11217 20:16:44.610516 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11219 20:16:44.613554 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11220 20:16:44.636332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11221 20:16:44.636581 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11223 20:16:44.639730 test Cropping: OK (Not Supported)
11224 20:16:44.664466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11225 20:16:44.664773 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11227 20:16:44.668168 test Composing: OK (Not Supported)
11228 20:16:44.689992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11229 20:16:44.690295 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11231 20:16:44.693501 test Scaling: OK (Not Supported)
11232 20:16:44.717257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11233 20:16:44.717384
11234 20:16:44.717670 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11236 20:16:44.732243 Codec ioctls (Input 0):
11237 20:16:44.738080 <LAVA_SIGNAL_TESTSET STOP>
11238 20:16:44.738379 Received signal: <TESTSET> STOP
11239 20:16:44.738502 Closing test_set Format-ioctls-Input-0
11240 20:16:44.748453 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11241 20:16:44.748753 Received signal: <TESTSET> START Codec-ioctls-Input-0
11242 20:16:44.748864 Starting test_set Codec-ioctls-Input-0
11243 20:16:44.751238 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11244 20:16:44.773494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11245 20:16:44.773795 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11247 20:16:44.780241 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11248 20:16:44.803912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11249 20:16:44.804215 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11251 20:16:44.809130 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11252 20:16:44.830058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11253 20:16:44.830180
11254 20:16:44.830426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11256 20:16:44.840649 Buffer ioctls (Input 0):
11257 20:16:44.848371 <LAVA_SIGNAL_TESTSET STOP>
11258 20:16:44.848667 Received signal: <TESTSET> STOP
11259 20:16:44.848778 Closing test_set Codec-ioctls-Input-0
11260 20:16:44.859981 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11261 20:16:44.860280 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11262 20:16:44.860394 Starting test_set Buffer-ioctls-Input-0
11263 20:16:44.863367 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11264 20:16:44.888870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11265 20:16:44.888995 test VIDIOC_EXPBUF: OK
11266 20:16:44.889274 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11268 20:16:44.912146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11269 20:16:44.912402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11271 20:16:44.915729 test Requests: OK (Not Supported)
11272 20:16:44.945198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11273 20:16:44.945283
11274 20:16:44.945538 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11276 20:16:44.956266 Test input 0:
11277 20:16:44.966011
11278 20:16:44.977863 Streaming ioctls:
11279 20:16:44.984558 <LAVA_SIGNAL_TESTSET STOP>
11280 20:16:44.984813 Received signal: <TESTSET> STOP
11281 20:16:44.984885 Closing test_set Buffer-ioctls-Input-0
11282 20:16:44.993428 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11283 20:16:44.993733 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11284 20:16:44.993850 Starting test_set Streaming-ioctls_Test-input-0
11285 20:16:44.996809 test read/write: OK (Not Supported)
11286 20:16:45.019256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11287 20:16:45.019514 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11289 20:16:45.022758 test blocking wait: OK
11290 20:16:45.044094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11291 20:16:45.044350 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11293 20:16:45.053950 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11294 20:16:45.054035 test MMAP (no poll): FAIL
11295 20:16:45.082825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11296 20:16:45.083081 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11298 20:16:45.092206 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11299 20:16:45.095051 test MMAP (select): FAIL
11300 20:16:45.123899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11301 20:16:45.124154 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11303 20:16:45.134051 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11304 20:16:45.137723 test MMAP (epoll): FAIL
11305 20:16:45.167438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11306 20:16:45.167523
11307 20:16:45.167779 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11309 20:16:45.184578
11310 20:16:45.375267
11311 20:16:45.383422 test USERPTR (no poll): OK
11312 20:16:45.411539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11313 20:16:45.411626
11314 20:16:45.411883 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11316 20:16:45.424683
11317 20:16:45.611925
11318 20:16:45.622818 test USERPTR (select): OK
11319 20:16:45.648159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11320 20:16:45.648421 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11322 20:16:45.654861 test DMABUF: Cannot test, specify --expbuf-device
11323 20:16:45.660947
11324 20:16:45.684102 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11325 20:16:45.692164 <LAVA_TEST_RUNNER EXIT>
11326 20:16:45.692427 ok: lava_test_shell seems to have completed
11327 20:16:45.692509 Marking unfinished test run as failed
11329 20:16:45.693631 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11330 20:16:45.693767 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11331 20:16:45.693866 end: 3 lava-test-retry (duration 00:00:10) [common]
11332 20:16:45.693970 start: 4 finalize (timeout 00:07:34) [common]
11333 20:16:45.694076 start: 4.1 power-off (timeout 00:00:30) [common]
11334 20:16:45.694335 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11335 20:16:45.769484 >> Command sent successfully.
11336 20:16:45.772180 Returned 0 in 0 seconds
11337 20:16:45.872585 end: 4.1 power-off (duration 00:00:00) [common]
11339 20:16:45.872897 start: 4.2 read-feedback (timeout 00:07:34) [common]
11340 20:16:45.873170 Listened to connection for namespace 'common' for up to 1s
11341 20:16:46.874126 Finalising connection for namespace 'common'
11342 20:16:46.874315 Disconnecting from shell: Finalise
11343 20:16:46.874391 / #
11344 20:16:46.974727 end: 4.2 read-feedback (duration 00:00:01) [common]
11345 20:16:46.974887 end: 4 finalize (duration 00:00:01) [common]
11346 20:16:46.975001 Cleaning after the job
11347 20:16:46.975103 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/ramdisk
11348 20:16:46.980700 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/kernel
11349 20:16:46.989603 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/dtb
11350 20:16:46.989767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12928151/tftp-deploy-nv35dnge/modules
11351 20:16:46.997166 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12928151
11352 20:16:47.065404 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12928151
11353 20:16:47.065587 Job finished correctly