Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:49:44.064109 lava-dispatcher, installed at version: 2024.03
2 23:49:44.064290 start: 0 validate
3 23:49:44.064414 Start time: 2024-05-29 23:49:44.064406+00:00 (UTC)
4 23:49:44.064534 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:49:44.064724 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:49:44.324994 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:49:44.325814 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:49:44.597464 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:49:44.598233 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:50:04.986936 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:50:04.987871 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:50:05.511314 validate duration: 21.45
14 23:50:05.511626 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:50:05.511755 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:50:05.511865 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:50:05.512008 Not decompressing ramdisk as can be used compressed.
18 23:50:05.512106 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:50:05.512195 saving as /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/ramdisk/rootfs.cpio.gz
20 23:50:05.512277 total size: 8181887 (7 MB)
21 23:50:08.081361 progress 0 % (0 MB)
22 23:50:08.087215 progress 5 % (0 MB)
23 23:50:08.089410 progress 10 % (0 MB)
24 23:50:08.091581 progress 15 % (1 MB)
25 23:50:08.093676 progress 20 % (1 MB)
26 23:50:08.095822 progress 25 % (1 MB)
27 23:50:08.097905 progress 30 % (2 MB)
28 23:50:08.100065 progress 35 % (2 MB)
29 23:50:08.102135 progress 40 % (3 MB)
30 23:50:08.104277 progress 45 % (3 MB)
31 23:50:08.106373 progress 50 % (3 MB)
32 23:50:08.108500 progress 55 % (4 MB)
33 23:50:08.110518 progress 60 % (4 MB)
34 23:50:08.112634 progress 65 % (5 MB)
35 23:50:08.114582 progress 70 % (5 MB)
36 23:50:08.116690 progress 75 % (5 MB)
37 23:50:08.118639 progress 80 % (6 MB)
38 23:50:08.120742 progress 85 % (6 MB)
39 23:50:08.122701 progress 90 % (7 MB)
40 23:50:08.124814 progress 95 % (7 MB)
41 23:50:08.126780 progress 100 % (7 MB)
42 23:50:08.126974 7 MB downloaded in 2.61 s (2.98 MB/s)
43 23:50:08.127121 end: 1.1.1 http-download (duration 00:00:03) [common]
45 23:50:08.127358 end: 1.1 download-retry (duration 00:00:03) [common]
46 23:50:08.127445 start: 1.2 download-retry (timeout 00:09:57) [common]
47 23:50:08.127530 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 23:50:08.127663 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:50:08.127733 saving as /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/kernel/Image
50 23:50:08.127797 total size: 54682112 (52 MB)
51 23:50:08.127860 No compression specified
52 23:50:08.129003 progress 0 % (0 MB)
53 23:50:08.142568 progress 5 % (2 MB)
54 23:50:08.156049 progress 10 % (5 MB)
55 23:50:08.169468 progress 15 % (7 MB)
56 23:50:08.182923 progress 20 % (10 MB)
57 23:50:08.196806 progress 25 % (13 MB)
58 23:50:08.210459 progress 30 % (15 MB)
59 23:50:08.224145 progress 35 % (18 MB)
60 23:50:08.237422 progress 40 % (20 MB)
61 23:50:08.250705 progress 45 % (23 MB)
62 23:50:08.264261 progress 50 % (26 MB)
63 23:50:08.277617 progress 55 % (28 MB)
64 23:50:08.291454 progress 60 % (31 MB)
65 23:50:08.305077 progress 65 % (33 MB)
66 23:50:08.318777 progress 70 % (36 MB)
67 23:50:08.332093 progress 75 % (39 MB)
68 23:50:08.345460 progress 80 % (41 MB)
69 23:50:08.358808 progress 85 % (44 MB)
70 23:50:08.371981 progress 90 % (46 MB)
71 23:50:08.385379 progress 95 % (49 MB)
72 23:50:08.398749 progress 100 % (52 MB)
73 23:50:08.398972 52 MB downloaded in 0.27 s (192.31 MB/s)
74 23:50:08.399125 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:50:08.399361 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:50:08.399450 start: 1.3 download-retry (timeout 00:09:57) [common]
78 23:50:08.399536 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 23:50:08.399669 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:50:08.399741 saving as /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/dtb/mt8192-asurada-spherion-r0.dtb
81 23:50:08.399804 total size: 47258 (0 MB)
82 23:50:08.399867 No compression specified
83 23:50:08.401063 progress 69 % (0 MB)
84 23:50:08.401334 progress 100 % (0 MB)
85 23:50:08.401487 0 MB downloaded in 0.00 s (26.80 MB/s)
86 23:50:08.401612 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:50:08.401835 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:50:08.401922 start: 1.4 download-retry (timeout 00:09:57) [common]
90 23:50:08.402005 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 23:50:08.402113 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:50:08.402182 saving as /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/modules/modules.tar
93 23:50:08.402242 total size: 8601444 (8 MB)
94 23:50:08.402304 Using unxz to decompress xz
95 23:50:08.405802 progress 0 % (0 MB)
96 23:50:08.425549 progress 5 % (0 MB)
97 23:50:08.449317 progress 10 % (0 MB)
98 23:50:08.474027 progress 15 % (1 MB)
99 23:50:08.498231 progress 20 % (1 MB)
100 23:50:08.523608 progress 25 % (2 MB)
101 23:50:08.547651 progress 30 % (2 MB)
102 23:50:08.570315 progress 35 % (2 MB)
103 23:50:08.593924 progress 40 % (3 MB)
104 23:50:08.620334 progress 45 % (3 MB)
105 23:50:08.643980 progress 50 % (4 MB)
106 23:50:08.667967 progress 55 % (4 MB)
107 23:50:08.691553 progress 60 % (4 MB)
108 23:50:08.714709 progress 65 % (5 MB)
109 23:50:08.742715 progress 70 % (5 MB)
110 23:50:08.768249 progress 75 % (6 MB)
111 23:50:08.791628 progress 80 % (6 MB)
112 23:50:08.817129 progress 85 % (7 MB)
113 23:50:08.841649 progress 90 % (7 MB)
114 23:50:08.870922 progress 95 % (7 MB)
115 23:50:08.898632 progress 100 % (8 MB)
116 23:50:08.904053 8 MB downloaded in 0.50 s (16.35 MB/s)
117 23:50:08.904285 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:50:08.904552 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:50:08.904686 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 23:50:08.904783 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 23:50:08.904869 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:50:08.904953 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 23:50:08.905178 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly
125 23:50:08.905310 makedir: /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin
126 23:50:08.905412 makedir: /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/tests
127 23:50:08.905510 makedir: /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/results
128 23:50:08.905626 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-add-keys
129 23:50:08.905768 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-add-sources
130 23:50:08.905896 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-background-process-start
131 23:50:08.906023 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-background-process-stop
132 23:50:08.906147 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-common-functions
133 23:50:08.906269 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-echo-ipv4
134 23:50:08.906392 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-install-packages
135 23:50:08.906513 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-installed-packages
136 23:50:08.906634 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-os-build
137 23:50:08.906756 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-probe-channel
138 23:50:08.906877 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-probe-ip
139 23:50:08.906998 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-target-ip
140 23:50:08.907119 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-target-mac
141 23:50:08.907241 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-target-storage
142 23:50:08.907366 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-case
143 23:50:08.907488 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-event
144 23:50:08.907610 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-feedback
145 23:50:08.907731 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-raise
146 23:50:08.907853 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-reference
147 23:50:08.907974 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-runner
148 23:50:08.908099 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-set
149 23:50:08.908221 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-test-shell
150 23:50:08.908347 Updating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-install-packages (oe)
151 23:50:08.908498 Updating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/bin/lava-installed-packages (oe)
152 23:50:08.908672 Creating /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/environment
153 23:50:08.908777 LAVA metadata
154 23:50:08.908853 - LAVA_JOB_ID=14084338
155 23:50:08.908920 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:50:08.909024 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:57) [common]
157 23:50:08.909097 skipped lava-vland-overlay
158 23:50:08.909173 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:50:08.909258 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:57) [common]
160 23:50:08.909332 skipped lava-multinode-overlay
161 23:50:08.909408 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:50:08.909495 start: 1.5.2.3 test-definition (timeout 00:09:57) [common]
163 23:50:08.909571 Loading test definitions
164 23:50:08.909666 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:57) [common]
165 23:50:08.909741 Using /lava-14084338 at stage 0
166 23:50:08.910057 uuid=14084338_1.5.2.3.1 testdef=None
167 23:50:08.910148 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:50:08.910237 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
169 23:50:08.910754 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:50:08.910986 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
172 23:50:08.911628 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:50:08.911864 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
175 23:50:08.912478 runner path: /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/0/tests/0_dmesg test_uuid 14084338_1.5.2.3.1
176 23:50:08.912674 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:50:08.912889 Creating lava-test-runner.conf files
179 23:50:08.912956 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084338/lava-overlay-tkyyv4ly/lava-14084338/0 for stage 0
180 23:50:08.913044 - 0_dmesg
181 23:50:08.913143 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:50:08.913231 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
183 23:50:08.920193 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:50:08.920301 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
185 23:50:08.920390 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:50:08.920478 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:50:08.920595 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
188 23:50:09.150387 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 23:50:09.150749 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
190 23:50:09.150865 extracting modules file /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084338/extract-overlay-ramdisk-b7hsvjya/ramdisk
191 23:50:09.349420 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:50:09.349592 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 23:50:09.349693 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084338/compress-overlay-ispy_eav/overlay-1.5.2.4.tar.gz to ramdisk
194 23:50:09.349765 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084338/compress-overlay-ispy_eav/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084338/extract-overlay-ramdisk-b7hsvjya/ramdisk
195 23:50:09.356165 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:50:09.356277 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 23:50:09.356370 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:50:09.356460 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 23:50:09.356540 Building ramdisk /var/lib/lava/dispatcher/tmp/14084338/extract-overlay-ramdisk-b7hsvjya/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084338/extract-overlay-ramdisk-b7hsvjya/ramdisk
200 23:50:09.720827 >> 145117 blocks
201 23:50:11.973870 rename /var/lib/lava/dispatcher/tmp/14084338/extract-overlay-ramdisk-b7hsvjya/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/ramdisk/ramdisk.cpio.gz
202 23:50:11.974307 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 23:50:11.974435 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 23:50:11.974537 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 23:50:11.974646 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/kernel/Image']
206 23:50:25.285302 Returned 0 in 13 seconds
207 23:50:25.386025 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/kernel/image.itb
208 23:50:25.776971 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:50:25.777331 output: Created: Thu May 30 00:50:25 2024
210 23:50:25.777410 output: Image 0 (kernel-1)
211 23:50:25.777480 output: Description:
212 23:50:25.777545 output: Created: Thu May 30 00:50:25 2024
213 23:50:25.777606 output: Type: Kernel Image
214 23:50:25.777666 output: Compression: lzma compressed
215 23:50:25.777722 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
216 23:50:25.777781 output: Architecture: AArch64
217 23:50:25.777840 output: OS: Linux
218 23:50:25.777898 output: Load Address: 0x00000000
219 23:50:25.777957 output: Entry Point: 0x00000000
220 23:50:25.778016 output: Hash algo: crc32
221 23:50:25.778077 output: Hash value: 907bf91d
222 23:50:25.778137 output: Image 1 (fdt-1)
223 23:50:25.778197 output: Description: mt8192-asurada-spherion-r0
224 23:50:25.778259 output: Created: Thu May 30 00:50:25 2024
225 23:50:25.778319 output: Type: Flat Device Tree
226 23:50:25.778375 output: Compression: uncompressed
227 23:50:25.778430 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:50:25.778486 output: Architecture: AArch64
229 23:50:25.778541 output: Hash algo: crc32
230 23:50:25.778597 output: Hash value: 0f8e4d2e
231 23:50:25.778651 output: Image 2 (ramdisk-1)
232 23:50:25.778706 output: Description: unavailable
233 23:50:25.778761 output: Created: Thu May 30 00:50:25 2024
234 23:50:25.778816 output: Type: RAMDisk Image
235 23:50:25.778871 output: Compression: Unknown Compression
236 23:50:25.778929 output: Data Size: 21363643 Bytes = 20862.93 KiB = 20.37 MiB
237 23:50:25.779031 output: Architecture: AArch64
238 23:50:25.779094 output: OS: Linux
239 23:50:25.779151 output: Load Address: unavailable
240 23:50:25.779207 output: Entry Point: unavailable
241 23:50:25.779263 output: Hash algo: crc32
242 23:50:25.779318 output: Hash value: 1e0aa306
243 23:50:25.779374 output: Default Configuration: 'conf-1'
244 23:50:25.779430 output: Configuration 0 (conf-1)
245 23:50:25.779485 output: Description: mt8192-asurada-spherion-r0
246 23:50:25.779540 output: Kernel: kernel-1
247 23:50:25.779595 output: Init Ramdisk: ramdisk-1
248 23:50:25.779650 output: FDT: fdt-1
249 23:50:25.779705 output: Loadables: kernel-1
250 23:50:25.779760 output:
251 23:50:25.779960 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:50:25.780055 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:50:25.780159 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 23:50:25.780252 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 23:50:25.780333 No LXC device requested
256 23:50:25.780414 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:50:25.780501 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 23:50:25.780591 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:50:25.780664 Checking files for TFTP limit of 4294967296 bytes.
260 23:50:25.781154 end: 1 tftp-deploy (duration 00:00:20) [common]
261 23:50:25.781260 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:50:25.781356 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:50:25.781483 substitutions:
264 23:50:25.781552 - {DTB}: 14084338/tftp-deploy-kfz9ggpj/dtb/mt8192-asurada-spherion-r0.dtb
265 23:50:25.781618 - {INITRD}: 14084338/tftp-deploy-kfz9ggpj/ramdisk/ramdisk.cpio.gz
266 23:50:25.781680 - {KERNEL}: 14084338/tftp-deploy-kfz9ggpj/kernel/Image
267 23:50:25.781741 - {LAVA_MAC}: None
268 23:50:25.781801 - {PRESEED_CONFIG}: None
269 23:50:25.781859 - {PRESEED_LOCAL}: None
270 23:50:25.781916 - {RAMDISK}: 14084338/tftp-deploy-kfz9ggpj/ramdisk/ramdisk.cpio.gz
271 23:50:25.781973 - {ROOT_PART}: None
272 23:50:25.782029 - {ROOT}: None
273 23:50:25.782085 - {SERVER_IP}: 192.168.201.1
274 23:50:25.782141 - {TEE}: None
275 23:50:25.782198 Parsed boot commands:
276 23:50:25.782253 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:50:25.782430 Parsed boot commands: tftpboot 192.168.201.1 14084338/tftp-deploy-kfz9ggpj/kernel/image.itb 14084338/tftp-deploy-kfz9ggpj/kernel/cmdline
278 23:50:25.782523 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:50:25.782611 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:50:25.782704 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:50:25.782792 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:50:25.782868 Not connected, no need to disconnect.
283 23:50:25.782944 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:50:25.783027 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:50:25.783098 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 23:50:25.786149 Setting prompt string to ['lava-test: # ']
287 23:50:25.786495 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:50:25.786604 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:50:25.786707 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:50:25.786826 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:50:25.787005 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
292 23:50:39.276984 Returned 0 in 13 seconds
293 23:50:39.378146 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 23:50:39.379683 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 23:50:39.380246 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 23:50:39.380761 Setting prompt string to 'Starting depthcharge on Spherion...'
298 23:50:39.381154 Changing prompt to 'Starting depthcharge on Spherion...'
299 23:50:39.381563 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 23:50:39.384266 [Enter `^Ec?' for help]
301 23:50:39.385052
302 23:50:39.385688
303 23:50:39.386227 F0: 102B 0000
304 23:50:39.386759
305 23:50:39.387275 F3: 1001 0000 [0200]
306 23:50:39.387787
307 23:50:39.388289 F3: 1001 0000
308 23:50:39.388816
309 23:50:39.389289 F7: 102D 0000
310 23:50:39.389626
311 23:50:39.389948 F1: 0000 0000
312 23:50:39.390268
313 23:50:39.390585 V0: 0000 0000 [0001]
314 23:50:39.390902
315 23:50:39.391220 00: 0007 8000
316 23:50:39.391574
317 23:50:39.391893 01: 0000 0000
318 23:50:39.392219
319 23:50:39.392652 BP: 0C00 0209 [0000]
320 23:50:39.392985
321 23:50:39.393298 G0: 1182 0000
322 23:50:39.393615
323 23:50:39.393927 EC: 0000 0021 [4000]
324 23:50:39.394244
325 23:50:39.394556 S7: 0000 0000 [0000]
326 23:50:39.394870
327 23:50:39.395181 CC: 0000 0000 [0001]
328 23:50:39.395498
329 23:50:39.395992 T0: 0000 0040 [010F]
330 23:50:39.396477
331 23:50:39.396980 Jump to BL
332 23:50:39.397306
333 23:50:39.397623
334 23:50:39.397936
335 23:50:39.398252 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 23:50:39.398587 ARM64: Exception handlers installed.
337 23:50:39.398904 ARM64: Testing exception
338 23:50:39.399255 ARM64: Done test exception
339 23:50:39.399576 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 23:50:39.399892 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 23:50:39.400211 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 23:50:39.400526 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 23:50:39.400883 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 23:50:39.401204 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 23:50:39.401527 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 23:50:39.401847 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 23:50:39.402159 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 23:50:39.402497 WDT: Last reset was cold boot
349 23:50:39.402818 SPI1(PAD0) initialized at 2873684 Hz
350 23:50:39.403133 SPI5(PAD0) initialized at 992727 Hz
351 23:50:39.403443 VBOOT: Loading verstage.
352 23:50:39.403757 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 23:50:39.404073 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 23:50:39.404387 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 23:50:39.404753 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 23:50:39.405045 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 23:50:39.405334 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 23:50:39.405652 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 23:50:39.405872
360 23:50:39.406082
361 23:50:39.406288 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 23:50:39.406494 ARM64: Exception handlers installed.
363 23:50:39.406701 ARM64: Testing exception
364 23:50:39.406906 ARM64: Done test exception
365 23:50:39.407110 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 23:50:39.407315 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 23:50:39.407523 Probing TPM: . done!
368 23:50:39.407727 TPM ready after 0 ms
369 23:50:39.407931 Connected to device vid:did:rid of 1ae0:0028:00
370 23:50:39.408135 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 23:50:39.408342 Initialized TPM device CR50 revision 0
372 23:50:39.408663 tlcl_send_startup: Startup return code is 0
373 23:50:39.408907 TPM: setup succeeded
374 23:50:39.409122 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 23:50:39.409332 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 23:50:39.409540 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 23:50:39.409746 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:50:39.409951 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 23:50:39.410158 in-header: 03 07 00 00 08 00 00 00
380 23:50:39.410361 in-data: aa e4 47 04 13 02 00 00
381 23:50:39.410566 Chrome EC: UHEPI supported
382 23:50:39.410745 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 23:50:39.410900 in-header: 03 a9 00 00 08 00 00 00
384 23:50:39.411053 in-data: 84 60 60 08 00 00 00 00
385 23:50:39.411207 Phase 1
386 23:50:39.411359 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 23:50:39.411514 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 23:50:39.411668 VB2:vb2_check_recovery() Recovery was requested manually
389 23:50:39.411823 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 23:50:39.411976 Recovery requested (1009000e)
391 23:50:39.412131 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:50:39.412285 tlcl_extend: response is 0
393 23:50:39.412441 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:50:39.412630 tlcl_extend: response is 0
395 23:50:39.412788 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:50:39.412945 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 23:50:39.413103 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:50:39.413258
399 23:50:39.413411
400 23:50:39.413564 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:50:39.413722 ARM64: Exception handlers installed.
402 23:50:39.413877 ARM64: Testing exception
403 23:50:39.414030 ARM64: Done test exception
404 23:50:39.414183 pmic_efuse_setting: Set efuses in 11 msecs
405 23:50:39.414339 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:50:39.414494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:50:39.414648 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:50:39.415059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:50:39.415376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:50:39.415693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:50:39.415896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:50:39.416091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:50:39.416284 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:50:39.416475 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:50:39.416686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:50:39.416880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:50:39.417071 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:50:39.417261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:50:39.417453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:50:39.417645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:50:39.417836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:50:39.418026 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:50:39.418217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:50:39.418407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:50:39.418597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:50:39.418787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:50:39.418977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:50:39.419167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:50:39.419356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:50:39.419546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:50:39.419736 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:50:39.419926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:50:39.420115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:50:39.420304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:50:39.420495 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:50:39.420714 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:50:39.420874 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:50:39.421033 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:50:39.421191 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:50:39.421350 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:50:39.421509 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:50:39.421668 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:50:39.421826 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:50:39.421985 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:50:39.422143 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:50:39.422301 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:50:39.422459 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:50:39.422617 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:50:39.422775 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:50:39.422933 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:50:39.423091 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:50:39.423249 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:50:39.423407 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:50:39.423565 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:50:39.423723 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:50:39.423880 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:50:39.424041 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 23:50:39.424202 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:50:39.424362 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:50:39.424522 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:50:39.424657 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:50:39.424764 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:50:39.424869 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:50:39.424974 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:50:39.425079 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
466 23:50:39.425183 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:50:39.425288 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 23:50:39.425391 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:50:39.425494 [RTC]rtc_get_frequency_meter,154: input=15, output=773
470 23:50:39.425598 [RTC]rtc_get_frequency_meter,154: input=23, output=958
471 23:50:39.425706 [RTC]rtc_get_frequency_meter,154: input=19, output=864
472 23:50:39.425795 [RTC]rtc_get_frequency_meter,154: input=17, output=819
473 23:50:39.425884 [RTC]rtc_get_frequency_meter,154: input=16, output=795
474 23:50:39.425972 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
475 23:50:39.426062 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
476 23:50:39.426152 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
477 23:50:39.426242 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
478 23:50:39.426541 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
479 23:50:39.426648 ADC[4]: Raw value=902876 ID=7
480 23:50:39.426741 ADC[3]: Raw value=213179 ID=1
481 23:50:39.426830 RAM Code: 0x71
482 23:50:39.426919 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
483 23:50:39.427010 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
484 23:50:39.427106 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
485 23:50:39.427198 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
486 23:50:39.427290 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
487 23:50:39.427380 in-header: 03 07 00 00 08 00 00 00
488 23:50:39.427469 in-data: aa e4 47 04 13 02 00 00
489 23:50:39.427558 Chrome EC: UHEPI supported
490 23:50:39.427647 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
491 23:50:39.427737 in-header: 03 a9 00 00 08 00 00 00
492 23:50:39.427825 in-data: 84 60 60 08 00 00 00 00
493 23:50:39.427913 MRC: failed to locate region type 0.
494 23:50:39.428003 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
495 23:50:39.428092 DRAM-K: Running full calibration
496 23:50:39.428180 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
497 23:50:39.428270 header.status = 0x0
498 23:50:39.428358 header.version = 0x6 (expected: 0x6)
499 23:50:39.428447 header.size = 0xd00 (expected: 0xd00)
500 23:50:39.428535 header.flags = 0x0
501 23:50:39.428645 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
502 23:50:39.428736 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
503 23:50:39.428826 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
504 23:50:39.428915 dram_init: ddr_geometry: 2
505 23:50:39.429004 [EMI] MDL number = 2
506 23:50:39.429093 [EMI] Get MDL freq = 0
507 23:50:39.429181 dram_init: ddr_type: 0
508 23:50:39.429268 is_discrete_lpddr4: 1
509 23:50:39.429357 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
510 23:50:39.429445
511 23:50:39.429533
512 23:50:39.429621 [Bian_co] ETT version 0.0.0.1
513 23:50:39.429711 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
514 23:50:39.429799
515 23:50:39.429888 dramc_set_vcore_voltage set vcore to 650000
516 23:50:39.429977 Read voltage for 800, 4
517 23:50:39.430066 Vio18 = 0
518 23:50:39.430154 Vcore = 650000
519 23:50:39.430242 Vdram = 0
520 23:50:39.430330 Vddq = 0
521 23:50:39.430417 Vmddr = 0
522 23:50:39.430504 dram_init: config_dvfs: 1
523 23:50:39.430593 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
524 23:50:39.430686 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
525 23:50:39.430765 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
526 23:50:39.430843 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
527 23:50:39.430923 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
528 23:50:39.431001 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
529 23:50:39.431078 MEM_TYPE=3, freq_sel=18
530 23:50:39.431156 sv_algorithm_assistance_LP4_1600
531 23:50:39.431233 ============ PULL DRAM RESETB DOWN ============
532 23:50:39.431314 ========== PULL DRAM RESETB DOWN end =========
533 23:50:39.431392 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
534 23:50:39.431488 ===================================
535 23:50:39.431572 LPDDR4 DRAM CONFIGURATION
536 23:50:39.431651 ===================================
537 23:50:39.431730 EX_ROW_EN[0] = 0x0
538 23:50:39.431809 EX_ROW_EN[1] = 0x0
539 23:50:39.431887 LP4Y_EN = 0x0
540 23:50:39.431964 WORK_FSP = 0x0
541 23:50:39.432041 WL = 0x2
542 23:50:39.432118 RL = 0x2
543 23:50:39.432195 BL = 0x2
544 23:50:39.432272 RPST = 0x0
545 23:50:39.432349 RD_PRE = 0x0
546 23:50:39.432426 WR_PRE = 0x1
547 23:50:39.432503 WR_PST = 0x0
548 23:50:39.432594 DBI_WR = 0x0
549 23:50:39.432672 DBI_RD = 0x0
550 23:50:39.432749 OTF = 0x1
551 23:50:39.432826 ===================================
552 23:50:39.432905 ===================================
553 23:50:39.432983 ANA top config
554 23:50:39.433060 ===================================
555 23:50:39.433137 DLL_ASYNC_EN = 0
556 23:50:39.433215 ALL_SLAVE_EN = 1
557 23:50:39.433292 NEW_RANK_MODE = 1
558 23:50:39.433369 DLL_IDLE_MODE = 1
559 23:50:39.433446 LP45_APHY_COMB_EN = 1
560 23:50:39.433523 TX_ODT_DIS = 1
561 23:50:39.433601 NEW_8X_MODE = 1
562 23:50:39.433678 ===================================
563 23:50:39.433756 ===================================
564 23:50:39.433833 data_rate = 1600
565 23:50:39.433911 CKR = 1
566 23:50:39.433988 DQ_P2S_RATIO = 8
567 23:50:39.434066 ===================================
568 23:50:39.434144 CA_P2S_RATIO = 8
569 23:50:39.434221 DQ_CA_OPEN = 0
570 23:50:39.434298 DQ_SEMI_OPEN = 0
571 23:50:39.434376 CA_SEMI_OPEN = 0
572 23:50:39.434453 CA_FULL_RATE = 0
573 23:50:39.434531 DQ_CKDIV4_EN = 1
574 23:50:39.434609 CA_CKDIV4_EN = 1
575 23:50:39.434687 CA_PREDIV_EN = 0
576 23:50:39.434764 PH8_DLY = 0
577 23:50:39.434841 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
578 23:50:39.434918 DQ_AAMCK_DIV = 4
579 23:50:39.434996 CA_AAMCK_DIV = 4
580 23:50:39.435073 CA_ADMCK_DIV = 4
581 23:50:39.435150 DQ_TRACK_CA_EN = 0
582 23:50:39.435227 CA_PICK = 800
583 23:50:39.435304 CA_MCKIO = 800
584 23:50:39.435381 MCKIO_SEMI = 0
585 23:50:39.435458 PLL_FREQ = 3068
586 23:50:39.435536 DQ_UI_PI_RATIO = 32
587 23:50:39.435614 CA_UI_PI_RATIO = 0
588 23:50:39.435698 ===================================
589 23:50:39.435767 ===================================
590 23:50:39.435836 memory_type:LPDDR4
591 23:50:39.435905 GP_NUM : 10
592 23:50:39.435974 SRAM_EN : 1
593 23:50:39.436043 MD32_EN : 0
594 23:50:39.436112 ===================================
595 23:50:39.436181 [ANA_INIT] >>>>>>>>>>>>>>
596 23:50:39.436250 <<<<<< [CONFIGURE PHASE]: ANA_TX
597 23:50:39.436322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
598 23:50:39.436391 ===================================
599 23:50:39.436670 data_rate = 1600,PCW = 0X7600
600 23:50:39.436747 ===================================
601 23:50:39.436819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:50:39.436889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
603 23:50:39.436960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 23:50:39.437030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
605 23:50:39.437101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
606 23:50:39.437171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
607 23:50:39.437241 [ANA_INIT] flow start
608 23:50:39.437310 [ANA_INIT] PLL >>>>>>>>
609 23:50:39.437379 [ANA_INIT] PLL <<<<<<<<
610 23:50:39.437448 [ANA_INIT] MIDPI >>>>>>>>
611 23:50:39.437518 [ANA_INIT] MIDPI <<<<<<<<
612 23:50:39.437586 [ANA_INIT] DLL >>>>>>>>
613 23:50:39.437655 [ANA_INIT] flow end
614 23:50:39.437724 ============ LP4 DIFF to SE enter ============
615 23:50:39.437793 ============ LP4 DIFF to SE exit ============
616 23:50:39.437863 [ANA_INIT] <<<<<<<<<<<<<
617 23:50:39.437932 [Flow] Enable top DCM control >>>>>
618 23:50:39.438001 [Flow] Enable top DCM control <<<<<
619 23:50:39.438070 Enable DLL master slave shuffle
620 23:50:39.438139 ==============================================================
621 23:50:39.438209 Gating Mode config
622 23:50:39.438278 ==============================================================
623 23:50:39.438347 Config description:
624 23:50:39.438416 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
625 23:50:39.438487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
626 23:50:39.438556 SELPH_MODE 0: By rank 1: By Phase
627 23:50:39.438626 ==============================================================
628 23:50:39.438695 GAT_TRACK_EN = 1
629 23:50:39.438765 RX_GATING_MODE = 2
630 23:50:39.438834 RX_GATING_TRACK_MODE = 2
631 23:50:39.438903 SELPH_MODE = 1
632 23:50:39.438972 PICG_EARLY_EN = 1
633 23:50:39.439041 VALID_LAT_VALUE = 1
634 23:50:39.439109 ==============================================================
635 23:50:39.439179 Enter into Gating configuration >>>>
636 23:50:39.439248 Exit from Gating configuration <<<<
637 23:50:39.439317 Enter into DVFS_PRE_config >>>>>
638 23:50:39.439385 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
639 23:50:39.439458 Exit from DVFS_PRE_config <<<<<
640 23:50:39.439527 Enter into PICG configuration >>>>
641 23:50:39.439596 Exit from PICG configuration <<<<
642 23:50:39.439664 [RX_INPUT] configuration >>>>>
643 23:50:39.439733 [RX_INPUT] configuration <<<<<
644 23:50:39.439802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
645 23:50:39.439872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
646 23:50:39.439941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
647 23:50:39.440011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
648 23:50:39.440080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
649 23:50:39.440150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
650 23:50:39.440219 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
651 23:50:39.440289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
652 23:50:39.440358 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
653 23:50:39.440428 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
654 23:50:39.440497 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
655 23:50:39.440576 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
656 23:50:39.440656 ===================================
657 23:50:39.440719 LPDDR4 DRAM CONFIGURATION
658 23:50:39.440781 ===================================
659 23:50:39.440843 EX_ROW_EN[0] = 0x0
660 23:50:39.440906 EX_ROW_EN[1] = 0x0
661 23:50:39.440966 LP4Y_EN = 0x0
662 23:50:39.441028 WORK_FSP = 0x0
663 23:50:39.441088 WL = 0x2
664 23:50:39.441149 RL = 0x2
665 23:50:39.441209 BL = 0x2
666 23:50:39.441271 RPST = 0x0
667 23:50:39.441334 RD_PRE = 0x0
668 23:50:39.441396 WR_PRE = 0x1
669 23:50:39.441457 WR_PST = 0x0
670 23:50:39.441519 DBI_WR = 0x0
671 23:50:39.441579 DBI_RD = 0x0
672 23:50:39.441641 OTF = 0x1
673 23:50:39.441703 ===================================
674 23:50:39.441766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
675 23:50:39.441828 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
676 23:50:39.441891 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
677 23:50:39.441953 ===================================
678 23:50:39.442016 LPDDR4 DRAM CONFIGURATION
679 23:50:39.442078 ===================================
680 23:50:39.442140 EX_ROW_EN[0] = 0x10
681 23:50:39.442203 EX_ROW_EN[1] = 0x0
682 23:50:39.442265 LP4Y_EN = 0x0
683 23:50:39.442327 WORK_FSP = 0x0
684 23:50:39.442388 WL = 0x2
685 23:50:39.442450 RL = 0x2
686 23:50:39.442512 BL = 0x2
687 23:50:39.442573 RPST = 0x0
688 23:50:39.442634 RD_PRE = 0x0
689 23:50:39.442696 WR_PRE = 0x1
690 23:50:39.442757 WR_PST = 0x0
691 23:50:39.442819 DBI_WR = 0x0
692 23:50:39.442881 DBI_RD = 0x0
693 23:50:39.442943 OTF = 0x1
694 23:50:39.443005 ===================================
695 23:50:39.443068 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
696 23:50:39.443131 nWR fixed to 40
697 23:50:39.443194 [ModeRegInit_LP4] CH0 RK0
698 23:50:39.443256 [ModeRegInit_LP4] CH0 RK1
699 23:50:39.443319 [ModeRegInit_LP4] CH1 RK0
700 23:50:39.443381 [ModeRegInit_LP4] CH1 RK1
701 23:50:39.443443 match AC timing 13
702 23:50:39.443504 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
703 23:50:39.443567 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
704 23:50:39.443629 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
705 23:50:39.443692 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
706 23:50:39.443951 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
707 23:50:39.444021 [EMI DOE] emi_dcm 0
708 23:50:39.444085 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
709 23:50:39.444148 ==
710 23:50:39.444212 Dram Type= 6, Freq= 0, CH_0, rank 0
711 23:50:39.444275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
712 23:50:39.444339 ==
713 23:50:39.444402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
714 23:50:39.444465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
715 23:50:39.444529 [CA 0] Center 38 (7~69) winsize 63
716 23:50:39.444601 [CA 1] Center 38 (7~69) winsize 63
717 23:50:39.444665 [CA 2] Center 35 (5~66) winsize 62
718 23:50:39.444727 [CA 3] Center 35 (5~66) winsize 62
719 23:50:39.444789 [CA 4] Center 34 (4~65) winsize 62
720 23:50:39.444852 [CA 5] Center 33 (3~64) winsize 62
721 23:50:39.444914
722 23:50:39.444976 [CmdBusTrainingLP45] Vref(ca) range 1: 32
723 23:50:39.445039
724 23:50:39.445102 [CATrainingPosCal] consider 1 rank data
725 23:50:39.445165 u2DelayCellTimex100 = 270/100 ps
726 23:50:39.445227 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
727 23:50:39.445290 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
728 23:50:39.445352 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
729 23:50:39.445415 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
730 23:50:39.445477 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
731 23:50:39.445539 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
732 23:50:39.445602
733 23:50:39.445674 CA PerBit enable=1, Macro0, CA PI delay=33
734 23:50:39.445731
735 23:50:39.445788 [CBTSetCACLKResult] CA Dly = 33
736 23:50:39.445845 CS Dly: 5 (0~36)
737 23:50:39.445901 ==
738 23:50:39.445957 Dram Type= 6, Freq= 0, CH_0, rank 1
739 23:50:39.446015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
740 23:50:39.446071 ==
741 23:50:39.446129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
742 23:50:39.446185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
743 23:50:39.446243 [CA 0] Center 38 (7~69) winsize 63
744 23:50:39.446300 [CA 1] Center 38 (7~69) winsize 63
745 23:50:39.446357 [CA 2] Center 36 (6~67) winsize 62
746 23:50:39.446414 [CA 3] Center 36 (5~67) winsize 63
747 23:50:39.446470 [CA 4] Center 35 (4~66) winsize 63
748 23:50:39.446527 [CA 5] Center 34 (4~65) winsize 62
749 23:50:39.446584
750 23:50:39.446640 [CmdBusTrainingLP45] Vref(ca) range 1: 32
751 23:50:39.446697
752 23:50:39.446754 [CATrainingPosCal] consider 2 rank data
753 23:50:39.446810 u2DelayCellTimex100 = 270/100 ps
754 23:50:39.446867 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
755 23:50:39.446924 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
756 23:50:39.446981 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
757 23:50:39.447038 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
758 23:50:39.447094 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
759 23:50:39.447151 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
760 23:50:39.447207
761 23:50:39.447264 CA PerBit enable=1, Macro0, CA PI delay=34
762 23:50:39.447321
763 23:50:39.447378 [CBTSetCACLKResult] CA Dly = 34
764 23:50:39.447435 CS Dly: 6 (0~38)
765 23:50:39.447491
766 23:50:39.447549 ----->DramcWriteLeveling(PI) begin...
767 23:50:39.447607 ==
768 23:50:39.447665 Dram Type= 6, Freq= 0, CH_0, rank 0
769 23:50:39.447722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
770 23:50:39.447779 ==
771 23:50:39.447836 Write leveling (Byte 0): 31 => 31
772 23:50:39.447894 Write leveling (Byte 1): 29 => 29
773 23:50:39.447951 DramcWriteLeveling(PI) end<-----
774 23:50:39.448008
775 23:50:39.448065 ==
776 23:50:39.448123 Dram Type= 6, Freq= 0, CH_0, rank 0
777 23:50:39.448180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 23:50:39.448237 ==
779 23:50:39.448294 [Gating] SW mode calibration
780 23:50:39.448352 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
781 23:50:39.448410 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
782 23:50:39.448466 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
783 23:50:39.448524 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 23:50:39.448588 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
785 23:50:39.448646 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 23:50:39.448704 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 23:50:39.448761 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 23:50:39.448818 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:50:39.448875 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:50:39.448933 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:50:39.448990 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:50:39.449046 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:50:39.449103 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:50:39.449160 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:50:39.449217 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:50:39.449273 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:50:39.449331 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:50:39.449387 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:50:39.449443 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
800 23:50:39.449500 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
801 23:50:39.449557 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:50:39.449614 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:50:39.449670 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:50:39.449727 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:50:39.449784 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:50:39.449841 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:50:39.449897 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:50:39.449954 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
809 23:50:39.450011 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
810 23:50:39.450068 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 23:50:39.450124 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 23:50:39.450181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 23:50:39.450237 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:50:39.450497 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
815 23:50:39.450561 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
816 23:50:39.450621 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
817 23:50:39.450693 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:50:39.450748 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 23:50:39.450804 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 23:50:39.450876 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 23:50:39.450946 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:50:39.451002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:50:39.451058 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
824 23:50:39.451113 0 11 8 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
825 23:50:39.451169 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
826 23:50:39.451225 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 23:50:39.451281 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 23:50:39.451337 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 23:50:39.451392 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 23:50:39.451448 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:50:39.451503 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:50:39.451559 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
833 23:50:39.451614 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 23:50:39.451670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 23:50:39.451726 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 23:50:39.451782 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 23:50:39.451838 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:50:39.451893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:50:39.451949 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:50:39.452004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:50:39.452059 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:50:39.452115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:50:39.452171 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:50:39.452227 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:50:39.452283 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:50:39.452339 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:50:39.452394 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
848 23:50:39.452450 Total UI for P1: 0, mck2ui 16
849 23:50:39.452506 best dqsien dly found for B0: ( 0, 14, 2)
850 23:50:39.452608 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
851 23:50:39.452666 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 23:50:39.452722 Total UI for P1: 0, mck2ui 16
853 23:50:39.452778 best dqsien dly found for B1: ( 0, 14, 6)
854 23:50:39.452834 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 23:50:39.452890 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
856 23:50:39.452946
857 23:50:39.453002 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 23:50:39.453058 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 23:50:39.453114 [Gating] SW calibration Done
860 23:50:39.453169 ==
861 23:50:39.453226 Dram Type= 6, Freq= 0, CH_0, rank 0
862 23:50:39.453282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 23:50:39.453338 ==
864 23:50:39.453394 RX Vref Scan: 0
865 23:50:39.453449
866 23:50:39.453505 RX Vref 0 -> 0, step: 1
867 23:50:39.453560
868 23:50:39.453615 RX Delay -130 -> 252, step: 16
869 23:50:39.453672 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 23:50:39.453728 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
871 23:50:39.453784 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 23:50:39.453840 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 23:50:39.453896 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 23:50:39.453951 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 23:50:39.454007 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
876 23:50:39.454063 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 23:50:39.454118 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 23:50:39.454173 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
879 23:50:39.454229 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 23:50:39.454285 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 23:50:39.454341 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 23:50:39.454395 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 23:50:39.454451 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 23:50:39.454507 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 23:50:39.454562 ==
886 23:50:39.454618 Dram Type= 6, Freq= 0, CH_0, rank 0
887 23:50:39.454674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 23:50:39.454730 ==
889 23:50:39.454786 DQS Delay:
890 23:50:39.454841 DQS0 = 0, DQS1 = 0
891 23:50:39.454897 DQM Delay:
892 23:50:39.454953 DQM0 = 90, DQM1 = 80
893 23:50:39.455009 DQ Delay:
894 23:50:39.455065 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
895 23:50:39.455121 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
896 23:50:39.455177 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
897 23:50:39.455232 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
898 23:50:39.455288
899 23:50:39.455344
900 23:50:39.455399 ==
901 23:50:39.455455 Dram Type= 6, Freq= 0, CH_0, rank 0
902 23:50:39.455511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 23:50:39.455567 ==
904 23:50:39.455623
905 23:50:39.455677
906 23:50:39.455732 TX Vref Scan disable
907 23:50:39.455788 == TX Byte 0 ==
908 23:50:39.455844 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
909 23:50:39.455899 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
910 23:50:39.455955 == TX Byte 1 ==
911 23:50:39.456011 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
912 23:50:39.456067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
913 23:50:39.456122 ==
914 23:50:39.456177 Dram Type= 6, Freq= 0, CH_0, rank 0
915 23:50:39.456234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 23:50:39.456290 ==
917 23:50:39.456346 TX Vref=22, minBit 6, minWin=27, winSum=443
918 23:50:39.456402 TX Vref=24, minBit 8, minWin=27, winSum=444
919 23:50:39.456458 TX Vref=26, minBit 9, minWin=27, winSum=450
920 23:50:39.456514 TX Vref=28, minBit 8, minWin=27, winSum=453
921 23:50:39.456603 TX Vref=30, minBit 5, minWin=28, winSum=458
922 23:50:39.456867 TX Vref=32, minBit 5, minWin=28, winSum=456
923 23:50:39.456933 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
924 23:50:39.456991
925 23:50:39.457049 Final TX Range 1 Vref 30
926 23:50:39.457106
927 23:50:39.457162 ==
928 23:50:39.457217 Dram Type= 6, Freq= 0, CH_0, rank 0
929 23:50:39.457274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 23:50:39.457331 ==
931 23:50:39.457387
932 23:50:39.457442
933 23:50:39.457497 TX Vref Scan disable
934 23:50:39.457553 == TX Byte 0 ==
935 23:50:39.457609 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 23:50:39.457665 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 23:50:39.457721 == TX Byte 1 ==
938 23:50:39.457776 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
939 23:50:39.457832 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
940 23:50:39.457887
941 23:50:39.457943 [DATLAT]
942 23:50:39.457999 Freq=800, CH0 RK0
943 23:50:39.458059
944 23:50:39.458115 DATLAT Default: 0xa
945 23:50:39.458171 0, 0xFFFF, sum = 0
946 23:50:39.458228 1, 0xFFFF, sum = 0
947 23:50:39.458285 2, 0xFFFF, sum = 0
948 23:50:39.458342 3, 0xFFFF, sum = 0
949 23:50:39.458399 4, 0xFFFF, sum = 0
950 23:50:39.458456 5, 0xFFFF, sum = 0
951 23:50:39.458512 6, 0xFFFF, sum = 0
952 23:50:39.458569 7, 0xFFFF, sum = 0
953 23:50:39.458625 8, 0xFFFF, sum = 0
954 23:50:39.458681 9, 0x0, sum = 1
955 23:50:39.458737 10, 0x0, sum = 2
956 23:50:39.458794 11, 0x0, sum = 3
957 23:50:39.458866 12, 0x0, sum = 4
958 23:50:39.458936 best_step = 10
959 23:50:39.458992
960 23:50:39.459047 ==
961 23:50:39.459103 Dram Type= 6, Freq= 0, CH_0, rank 0
962 23:50:39.459160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 23:50:39.459216 ==
964 23:50:39.459272 RX Vref Scan: 1
965 23:50:39.459327
966 23:50:39.459383 Set Vref Range= 32 -> 127
967 23:50:39.459438
968 23:50:39.459493 RX Vref 32 -> 127, step: 1
969 23:50:39.459549
970 23:50:39.459604 RX Delay -79 -> 252, step: 8
971 23:50:39.459660
972 23:50:39.459715 Set Vref, RX VrefLevel [Byte0]: 32
973 23:50:39.459771 [Byte1]: 32
974 23:50:39.459826
975 23:50:39.459882 Set Vref, RX VrefLevel [Byte0]: 33
976 23:50:39.459938 [Byte1]: 33
977 23:50:39.459994
978 23:50:39.460049 Set Vref, RX VrefLevel [Byte0]: 34
979 23:50:39.460105 [Byte1]: 34
980 23:50:39.460161
981 23:50:39.460217 Set Vref, RX VrefLevel [Byte0]: 35
982 23:50:39.460272 [Byte1]: 35
983 23:50:39.460328
984 23:50:39.460383 Set Vref, RX VrefLevel [Byte0]: 36
985 23:50:39.460439 [Byte1]: 36
986 23:50:39.460494
987 23:50:39.460577 Set Vref, RX VrefLevel [Byte0]: 37
988 23:50:39.460656 [Byte1]: 37
989 23:50:39.460712
990 23:50:39.460768 Set Vref, RX VrefLevel [Byte0]: 38
991 23:50:39.460824 [Byte1]: 38
992 23:50:39.460879
993 23:50:39.460935 Set Vref, RX VrefLevel [Byte0]: 39
994 23:50:39.460990 [Byte1]: 39
995 23:50:39.461045
996 23:50:39.461101 Set Vref, RX VrefLevel [Byte0]: 40
997 23:50:39.461156 [Byte1]: 40
998 23:50:39.461211
999 23:50:39.461266 Set Vref, RX VrefLevel [Byte0]: 41
1000 23:50:39.461321 [Byte1]: 41
1001 23:50:39.461376
1002 23:50:39.461431 Set Vref, RX VrefLevel [Byte0]: 42
1003 23:50:39.461486 [Byte1]: 42
1004 23:50:39.461541
1005 23:50:39.461597 Set Vref, RX VrefLevel [Byte0]: 43
1006 23:50:39.461652 [Byte1]: 43
1007 23:50:39.461707
1008 23:50:39.461763 Set Vref, RX VrefLevel [Byte0]: 44
1009 23:50:39.461818 [Byte1]: 44
1010 23:50:39.461873
1011 23:50:39.461928 Set Vref, RX VrefLevel [Byte0]: 45
1012 23:50:39.462045 [Byte1]: 45
1013 23:50:39.462100
1014 23:50:39.462155 Set Vref, RX VrefLevel [Byte0]: 46
1015 23:50:39.462211 [Byte1]: 46
1016 23:50:39.462266
1017 23:50:39.462322 Set Vref, RX VrefLevel [Byte0]: 47
1018 23:50:39.462378 [Byte1]: 47
1019 23:50:39.462434
1020 23:50:39.462490 Set Vref, RX VrefLevel [Byte0]: 48
1021 23:50:39.462547 [Byte1]: 48
1022 23:50:39.462602
1023 23:50:39.462657 Set Vref, RX VrefLevel [Byte0]: 49
1024 23:50:39.462714 [Byte1]: 49
1025 23:50:39.462777
1026 23:50:39.462835 Set Vref, RX VrefLevel [Byte0]: 50
1027 23:50:39.462891 [Byte1]: 50
1028 23:50:39.462947
1029 23:50:39.463003 Set Vref, RX VrefLevel [Byte0]: 51
1030 23:50:39.463058 [Byte1]: 51
1031 23:50:39.463113
1032 23:50:39.463168 Set Vref, RX VrefLevel [Byte0]: 52
1033 23:50:39.463223 [Byte1]: 52
1034 23:50:39.463278
1035 23:50:39.463332 Set Vref, RX VrefLevel [Byte0]: 53
1036 23:50:39.463387 [Byte1]: 53
1037 23:50:39.463442
1038 23:50:39.463496 Set Vref, RX VrefLevel [Byte0]: 54
1039 23:50:39.463551 [Byte1]: 54
1040 23:50:39.463606
1041 23:50:39.463660 Set Vref, RX VrefLevel [Byte0]: 55
1042 23:50:39.463715 [Byte1]: 55
1043 23:50:39.463770
1044 23:50:39.463824 Set Vref, RX VrefLevel [Byte0]: 56
1045 23:50:39.463879 [Byte1]: 56
1046 23:50:39.463934
1047 23:50:39.463989 Set Vref, RX VrefLevel [Byte0]: 57
1048 23:50:39.464044 [Byte1]: 57
1049 23:50:39.464099
1050 23:50:39.464154 Set Vref, RX VrefLevel [Byte0]: 58
1051 23:50:39.464209 [Byte1]: 58
1052 23:50:39.464263
1053 23:50:39.464318 Set Vref, RX VrefLevel [Byte0]: 59
1054 23:50:39.464373 [Byte1]: 59
1055 23:50:39.464428
1056 23:50:39.464481 Set Vref, RX VrefLevel [Byte0]: 60
1057 23:50:39.464536 [Byte1]: 60
1058 23:50:39.464648
1059 23:50:39.464703 Set Vref, RX VrefLevel [Byte0]: 61
1060 23:50:39.464756 [Byte1]: 61
1061 23:50:39.464813
1062 23:50:39.464868 Set Vref, RX VrefLevel [Byte0]: 62
1063 23:50:39.464924 [Byte1]: 62
1064 23:50:39.464978
1065 23:50:39.465033 Set Vref, RX VrefLevel [Byte0]: 63
1066 23:50:39.465088 [Byte1]: 63
1067 23:50:39.465142
1068 23:50:39.465197 Set Vref, RX VrefLevel [Byte0]: 64
1069 23:50:39.465252 [Byte1]: 64
1070 23:50:39.465306
1071 23:50:39.465361 Set Vref, RX VrefLevel [Byte0]: 65
1072 23:50:39.465416 [Byte1]: 65
1073 23:50:39.465471
1074 23:50:39.465525 Set Vref, RX VrefLevel [Byte0]: 66
1075 23:50:39.465580 [Byte1]: 66
1076 23:50:39.465635
1077 23:50:39.465689 Set Vref, RX VrefLevel [Byte0]: 67
1078 23:50:39.465744 [Byte1]: 67
1079 23:50:39.465799
1080 23:50:39.465854 Set Vref, RX VrefLevel [Byte0]: 68
1081 23:50:39.465908 [Byte1]: 68
1082 23:50:39.465962
1083 23:50:39.466017 Set Vref, RX VrefLevel [Byte0]: 69
1084 23:50:39.466072 [Byte1]: 69
1085 23:50:39.466126
1086 23:50:39.466180 Set Vref, RX VrefLevel [Byte0]: 70
1087 23:50:39.466235 [Byte1]: 70
1088 23:50:39.466290
1089 23:50:39.466344 Set Vref, RX VrefLevel [Byte0]: 71
1090 23:50:39.466399 [Byte1]: 71
1091 23:50:39.466454
1092 23:50:39.466508 Set Vref, RX VrefLevel [Byte0]: 72
1093 23:50:39.466752 [Byte1]: 72
1094 23:50:39.466814
1095 23:50:39.466871 Set Vref, RX VrefLevel [Byte0]: 73
1096 23:50:39.466927 [Byte1]: 73
1097 23:50:39.466983
1098 23:50:39.467067 Set Vref, RX VrefLevel [Byte0]: 74
1099 23:50:39.467122 [Byte1]: 74
1100 23:50:39.467178
1101 23:50:39.467233 Set Vref, RX VrefLevel [Byte0]: 75
1102 23:50:39.467288 [Byte1]: 75
1103 23:50:39.467343
1104 23:50:39.467397 Set Vref, RX VrefLevel [Byte0]: 76
1105 23:50:39.467452 [Byte1]: 76
1106 23:50:39.467507
1107 23:50:39.467561 Final RX Vref Byte 0 = 61 to rank0
1108 23:50:39.467618 Final RX Vref Byte 1 = 53 to rank0
1109 23:50:39.467673 Final RX Vref Byte 0 = 61 to rank1
1110 23:50:39.467729 Final RX Vref Byte 1 = 53 to rank1==
1111 23:50:39.467784 Dram Type= 6, Freq= 0, CH_0, rank 0
1112 23:50:39.467839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1113 23:50:39.467894 ==
1114 23:50:39.467950 DQS Delay:
1115 23:50:39.468004 DQS0 = 0, DQS1 = 0
1116 23:50:39.468058 DQM Delay:
1117 23:50:39.468113 DQM0 = 93, DQM1 = 81
1118 23:50:39.468167 DQ Delay:
1119 23:50:39.468223 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1120 23:50:39.468277 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1121 23:50:39.468332 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1122 23:50:39.468387 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1123 23:50:39.468441
1124 23:50:39.468495
1125 23:50:39.468560 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1126 23:50:39.468655 CH0 RK0: MR19=606, MR18=3C38
1127 23:50:39.468711 CH0_RK0: MR19=0x606, MR18=0x3C38, DQSOSC=394, MR23=63, INC=95, DEC=63
1128 23:50:39.468766
1129 23:50:39.468821 ----->DramcWriteLeveling(PI) begin...
1130 23:50:39.468878 ==
1131 23:50:39.468933 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 23:50:39.469018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 23:50:39.469074 ==
1134 23:50:39.469128 Write leveling (Byte 0): 35 => 35
1135 23:50:39.469184 Write leveling (Byte 1): 29 => 29
1136 23:50:39.469238 DramcWriteLeveling(PI) end<-----
1137 23:50:39.469293
1138 23:50:39.469348 ==
1139 23:50:39.469402 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 23:50:39.469457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 23:50:39.469511 ==
1142 23:50:39.469566 [Gating] SW mode calibration
1143 23:50:39.469621 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1144 23:50:39.469676 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1145 23:50:39.469730 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1146 23:50:39.469785 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1147 23:50:39.469840 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 23:50:39.469895 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 23:50:39.469949 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 23:50:39.470004 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 23:50:39.470059 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 23:50:39.470114 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 23:50:39.470168 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:50:39.470222 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:50:39.470277 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:50:39.470331 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:50:39.470386 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:50:39.470441 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:50:39.470496 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:50:39.470551 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:50:39.470605 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1162 23:50:39.470660 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1163 23:50:39.470715 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1164 23:50:39.470770 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:50:39.470825 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:50:39.470880 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:50:39.470935 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:50:39.470990 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:50:39.471044 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:50:39.471100 0 9 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
1171 23:50:39.471155 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1172 23:50:39.471239 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 23:50:39.471294 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 23:50:39.471349 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 23:50:39.471404 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 23:50:39.471459 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 23:50:39.471514 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:50:39.471569 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 1)
1179 23:50:39.471624 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1180 23:50:39.471679 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:50:39.471734 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:50:39.471789 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:50:39.471844 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:50:39.471899 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:50:39.471953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:50:39.472008 0 11 4 | B1->B0 | 2828 3636 | 0 0 | (0 0) (0 0)
1187 23:50:39.472062 0 11 8 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
1188 23:50:39.472124 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 23:50:39.472187 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 23:50:39.472242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 23:50:39.472298 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 23:50:39.472353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:50:39.472407 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1194 23:50:39.472462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1195 23:50:39.472517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1196 23:50:39.472804 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 23:50:39.472866 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 23:50:39.472922 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 23:50:39.472978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:50:39.473033 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:50:39.473089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:50:39.473143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:50:39.473229 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:50:39.473284 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:50:39.473339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:50:39.473394 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:50:39.473449 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:50:39.473504 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:50:39.473559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:50:39.473614 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:50:39.473669 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 23:50:39.473724 Total UI for P1: 0, mck2ui 16
1213 23:50:39.473780 best dqsien dly found for B0: ( 0, 14, 6)
1214 23:50:39.473835 Total UI for P1: 0, mck2ui 16
1215 23:50:39.473890 best dqsien dly found for B1: ( 0, 14, 6)
1216 23:50:39.473945 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1217 23:50:39.473999 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1218 23:50:39.474055
1219 23:50:39.474110 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1220 23:50:39.474165 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1221 23:50:39.474219 [Gating] SW calibration Done
1222 23:50:39.474274 ==
1223 23:50:39.474329 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 23:50:39.474385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 23:50:39.474440 ==
1226 23:50:39.474506 RX Vref Scan: 0
1227 23:50:39.474563
1228 23:50:39.474618 RX Vref 0 -> 0, step: 1
1229 23:50:39.474672
1230 23:50:39.474727 RX Delay -130 -> 252, step: 16
1231 23:50:39.474782 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1232 23:50:39.474838 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1233 23:50:39.474893 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1234 23:50:39.474948 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1235 23:50:39.475003 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1236 23:50:39.475059 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1237 23:50:39.475113 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1238 23:50:39.475168 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1239 23:50:39.475223 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1240 23:50:39.475302 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1241 23:50:39.475370 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1242 23:50:39.475425 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1243 23:50:39.475480 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1244 23:50:39.475535 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1245 23:50:39.475590 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1246 23:50:39.475644 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1247 23:50:39.475699 ==
1248 23:50:39.475754 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 23:50:39.475810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 23:50:39.475864 ==
1251 23:50:39.475949 DQS Delay:
1252 23:50:39.476003 DQS0 = 0, DQS1 = 0
1253 23:50:39.476058 DQM Delay:
1254 23:50:39.476112 DQM0 = 92, DQM1 = 80
1255 23:50:39.476166 DQ Delay:
1256 23:50:39.476220 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1257 23:50:39.476276 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =93
1258 23:50:39.476331 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1259 23:50:39.476386 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1260 23:50:39.476441
1261 23:50:39.476495
1262 23:50:39.476558 ==
1263 23:50:39.476682 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 23:50:39.476767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 23:50:39.476858 ==
1266 23:50:39.476950
1267 23:50:39.477010
1268 23:50:39.477066 TX Vref Scan disable
1269 23:50:39.477121 == TX Byte 0 ==
1270 23:50:39.477176 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1271 23:50:39.477231 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1272 23:50:39.477285 == TX Byte 1 ==
1273 23:50:39.477341 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1274 23:50:39.477394 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1275 23:50:39.477449 ==
1276 23:50:39.477504 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 23:50:39.477559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 23:50:39.477615 ==
1279 23:50:39.477670 TX Vref=22, minBit 1, minWin=27, winSum=440
1280 23:50:39.477726 TX Vref=24, minBit 8, minWin=27, winSum=448
1281 23:50:39.477782 TX Vref=26, minBit 8, minWin=27, winSum=452
1282 23:50:39.477853 TX Vref=28, minBit 10, minWin=27, winSum=454
1283 23:50:39.477922 TX Vref=30, minBit 10, minWin=27, winSum=454
1284 23:50:39.477977 TX Vref=32, minBit 4, minWin=28, winSum=455
1285 23:50:39.478033 [TxChooseVref] Worse bit 4, Min win 28, Win sum 455, Final Vref 32
1286 23:50:39.478087
1287 23:50:39.478141 Final TX Range 1 Vref 32
1288 23:50:39.478196
1289 23:50:39.478251 ==
1290 23:50:39.478305 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 23:50:39.478360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 23:50:39.478416 ==
1293 23:50:39.478471
1294 23:50:39.478524
1295 23:50:39.478577 TX Vref Scan disable
1296 23:50:39.478630 == TX Byte 0 ==
1297 23:50:39.478683 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1298 23:50:39.478736 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1299 23:50:39.478789 == TX Byte 1 ==
1300 23:50:39.478842 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1301 23:50:39.478896 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1302 23:50:39.478949
1303 23:50:39.479001 [DATLAT]
1304 23:50:39.479053 Freq=800, CH0 RK1
1305 23:50:39.479106
1306 23:50:39.479158 DATLAT Default: 0xa
1307 23:50:39.479211 0, 0xFFFF, sum = 0
1308 23:50:39.479266 1, 0xFFFF, sum = 0
1309 23:50:39.479320 2, 0xFFFF, sum = 0
1310 23:50:39.479373 3, 0xFFFF, sum = 0
1311 23:50:39.479427 4, 0xFFFF, sum = 0
1312 23:50:39.479479 5, 0xFFFF, sum = 0
1313 23:50:39.479533 6, 0xFFFF, sum = 0
1314 23:50:39.479586 7, 0xFFFF, sum = 0
1315 23:50:39.479639 8, 0xFFFF, sum = 0
1316 23:50:39.479692 9, 0x0, sum = 1
1317 23:50:39.479746 10, 0x0, sum = 2
1318 23:50:39.479800 11, 0x0, sum = 3
1319 23:50:39.479853 12, 0x0, sum = 4
1320 23:50:39.479907 best_step = 10
1321 23:50:39.479959
1322 23:50:39.480027 ==
1323 23:50:39.480093 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 23:50:39.480147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 23:50:39.480200 ==
1326 23:50:39.480252 RX Vref Scan: 0
1327 23:50:39.480305
1328 23:50:39.480357 RX Vref 0 -> 0, step: 1
1329 23:50:39.480410
1330 23:50:39.480462 RX Delay -95 -> 252, step: 8
1331 23:50:39.480708 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1332 23:50:39.480770 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1333 23:50:39.480826 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1334 23:50:39.480880 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1335 23:50:39.480933 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1336 23:50:39.480987 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1337 23:50:39.481041 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1338 23:50:39.481094 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1339 23:50:39.481147 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1340 23:50:39.481200 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1341 23:50:39.481253 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1342 23:50:39.481305 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1343 23:50:39.481357 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1344 23:50:39.481410 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1345 23:50:39.481462 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1346 23:50:39.481514 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1347 23:50:39.481567 ==
1348 23:50:39.481619 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 23:50:39.481672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 23:50:39.481726 ==
1351 23:50:39.481778 DQS Delay:
1352 23:50:39.481830 DQS0 = 0, DQS1 = 0
1353 23:50:39.481883 DQM Delay:
1354 23:50:39.481936 DQM0 = 90, DQM1 = 82
1355 23:50:39.481988 DQ Delay:
1356 23:50:39.482040 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1357 23:50:39.482092 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1358 23:50:39.482146 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1359 23:50:39.482231 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1360 23:50:39.482284
1361 23:50:39.482336
1362 23:50:39.482388 [DQSOSCAuto] RK1, (LSB)MR18= 0x431d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1363 23:50:39.482442 CH0 RK1: MR19=606, MR18=431D
1364 23:50:39.482495 CH0_RK1: MR19=0x606, MR18=0x431D, DQSOSC=393, MR23=63, INC=95, DEC=63
1365 23:50:39.482548 [RxdqsGatingPostProcess] freq 800
1366 23:50:39.482601 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1367 23:50:39.482655 Pre-setting of DQS Precalculation
1368 23:50:39.482708 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1369 23:50:39.482761 ==
1370 23:50:39.482814 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 23:50:39.482866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 23:50:39.482919 ==
1373 23:50:39.482972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1374 23:50:39.483025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1375 23:50:39.483079 [CA 0] Center 36 (6~67) winsize 62
1376 23:50:39.483132 [CA 1] Center 37 (6~68) winsize 63
1377 23:50:39.483184 [CA 2] Center 34 (4~65) winsize 62
1378 23:50:39.483237 [CA 3] Center 34 (3~65) winsize 63
1379 23:50:39.483290 [CA 4] Center 34 (4~65) winsize 62
1380 23:50:39.483343 [CA 5] Center 33 (3~64) winsize 62
1381 23:50:39.483396
1382 23:50:39.483448 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1383 23:50:39.483501
1384 23:50:39.483553 [CATrainingPosCal] consider 1 rank data
1385 23:50:39.483606 u2DelayCellTimex100 = 270/100 ps
1386 23:50:39.483658 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1387 23:50:39.483711 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1388 23:50:39.483763 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 23:50:39.483816 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1390 23:50:39.483868 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 23:50:39.483921 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1392 23:50:39.483973
1393 23:50:39.484025 CA PerBit enable=1, Macro0, CA PI delay=33
1394 23:50:39.484077
1395 23:50:39.484129 [CBTSetCACLKResult] CA Dly = 33
1396 23:50:39.484183 CS Dly: 5 (0~36)
1397 23:50:39.484235 ==
1398 23:50:39.484304 Dram Type= 6, Freq= 0, CH_1, rank 1
1399 23:50:39.484371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 23:50:39.484424 ==
1401 23:50:39.484478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 23:50:39.484531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 23:50:39.484634 [CA 0] Center 37 (7~67) winsize 61
1404 23:50:39.484688 [CA 1] Center 37 (6~68) winsize 63
1405 23:50:39.484741 [CA 2] Center 35 (4~66) winsize 63
1406 23:50:39.484794 [CA 3] Center 34 (4~65) winsize 62
1407 23:50:39.484847 [CA 4] Center 34 (4~65) winsize 62
1408 23:50:39.484900 [CA 5] Center 34 (4~65) winsize 62
1409 23:50:39.484953
1410 23:50:39.485005 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1411 23:50:39.485058
1412 23:50:39.485110 [CATrainingPosCal] consider 2 rank data
1413 23:50:39.485163 u2DelayCellTimex100 = 270/100 ps
1414 23:50:39.485217 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1415 23:50:39.485270 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1416 23:50:39.485323 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 23:50:39.485376 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 23:50:39.485429 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 23:50:39.485483 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1420 23:50:39.485535
1421 23:50:39.485588 CA PerBit enable=1, Macro0, CA PI delay=34
1422 23:50:39.485641
1423 23:50:39.485693 [CBTSetCACLKResult] CA Dly = 34
1424 23:50:39.485746 CS Dly: 6 (0~38)
1425 23:50:39.485799
1426 23:50:39.485851 ----->DramcWriteLeveling(PI) begin...
1427 23:50:39.485905 ==
1428 23:50:39.485958 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 23:50:39.486011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 23:50:39.486065 ==
1431 23:50:39.486118 Write leveling (Byte 0): 26 => 26
1432 23:50:39.486171 Write leveling (Byte 1): 30 => 30
1433 23:50:39.486223 DramcWriteLeveling(PI) end<-----
1434 23:50:39.486276
1435 23:50:39.486329 ==
1436 23:50:39.486381 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 23:50:39.486433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 23:50:39.486486 ==
1439 23:50:39.486539 [Gating] SW mode calibration
1440 23:50:39.486592 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1441 23:50:39.486676 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1442 23:50:39.486729 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1443 23:50:39.486782 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1444 23:50:39.486835 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 23:50:39.486888 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 23:50:39.486941 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 23:50:39.486994 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 23:50:39.487238 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 23:50:39.487299 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 23:50:39.487353 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:50:39.487407 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:50:39.487461 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:50:39.487514 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:50:39.487567 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:50:39.487620 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:50:39.487673 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:50:39.487726 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:50:39.487779 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:50:39.487831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1460 23:50:39.487884 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:50:39.487937 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:50:39.487990 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:50:39.488042 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:50:39.488095 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:50:39.488148 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:50:39.488200 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:50:39.488253 0 9 4 | B1->B0 | 2424 2727 | 0 1 | (0 0) (0 0)
1468 23:50:39.488306 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 23:50:39.488359 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 23:50:39.488411 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 23:50:39.488464 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 23:50:39.488517 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 23:50:39.488605 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 23:50:39.488674 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1475 23:50:39.488727 0 10 4 | B1->B0 | 2d2d 2b2b | 1 1 | (1 0) (1 0)
1476 23:50:39.488797 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1477 23:50:39.488864 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:50:39.488917 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:50:39.488970 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:50:39.489023 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:50:39.489075 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:50:39.489128 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1483 23:50:39.489180 0 11 4 | B1->B0 | 2f2f 3838 | 1 0 | (0 0) (1 1)
1484 23:50:39.489233 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 23:50:39.489287 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 23:50:39.489339 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 23:50:39.489392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 23:50:39.489445 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 23:50:39.489498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 23:50:39.489551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:50:39.489604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1492 23:50:39.489657 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 23:50:39.489710 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 23:50:39.489762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 23:50:39.489815 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 23:50:39.489868 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 23:50:39.489920 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 23:50:39.489972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:50:39.490025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:50:39.490078 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:50:39.490131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:50:39.490183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:50:39.490236 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:50:39.490288 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:50:39.490341 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:50:39.490393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1507 23:50:39.490446 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1508 23:50:39.490498 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1509 23:50:39.490551 Total UI for P1: 0, mck2ui 16
1510 23:50:39.490603 best dqsien dly found for B0: ( 0, 14, 2)
1511 23:50:39.490657 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 23:50:39.490709 Total UI for P1: 0, mck2ui 16
1513 23:50:39.490762 best dqsien dly found for B1: ( 0, 14, 8)
1514 23:50:39.490815 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1515 23:50:39.490868 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1516 23:50:39.490920
1517 23:50:39.490973 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1518 23:50:39.491025 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1519 23:50:39.491103 [Gating] SW calibration Done
1520 23:50:39.491171 ==
1521 23:50:39.491224 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 23:50:39.491277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 23:50:39.491331 ==
1524 23:50:39.491383 RX Vref Scan: 0
1525 23:50:39.491436
1526 23:50:39.491488 RX Vref 0 -> 0, step: 1
1527 23:50:39.491540
1528 23:50:39.491593 RX Delay -130 -> 252, step: 16
1529 23:50:39.491646 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1530 23:50:39.491699 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1531 23:50:39.491752 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1532 23:50:39.491804 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1533 23:50:39.491856 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1534 23:50:39.491909 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1535 23:50:39.491962 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1536 23:50:39.492015 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1537 23:50:39.492067 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1538 23:50:39.492312 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1539 23:50:39.492374 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1540 23:50:39.492429 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1541 23:50:39.492483 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1542 23:50:39.492536 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1543 23:50:39.492631 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1544 23:50:39.492685 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1545 23:50:39.492738 ==
1546 23:50:39.492791 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 23:50:39.492844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 23:50:39.492897 ==
1549 23:50:39.492950 DQS Delay:
1550 23:50:39.493003 DQS0 = 0, DQS1 = 0
1551 23:50:39.493056 DQM Delay:
1552 23:50:39.493108 DQM0 = 86, DQM1 = 80
1553 23:50:39.493192 DQ Delay:
1554 23:50:39.493245 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1555 23:50:39.493298 DQ4 =77, DQ5 =93, DQ6 =101, DQ7 =85
1556 23:50:39.493351 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1557 23:50:39.493403 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1558 23:50:39.493456
1559 23:50:39.493508
1560 23:50:39.493561 ==
1561 23:50:39.493613 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 23:50:39.493666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 23:50:39.493720 ==
1564 23:50:39.493771
1565 23:50:39.493823
1566 23:50:39.493875 TX Vref Scan disable
1567 23:50:39.493928 == TX Byte 0 ==
1568 23:50:39.493980 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1569 23:50:39.494033 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1570 23:50:39.494086 == TX Byte 1 ==
1571 23:50:39.494138 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1572 23:50:39.494191 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1573 23:50:39.494244 ==
1574 23:50:39.494296 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 23:50:39.494350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 23:50:39.494404 ==
1577 23:50:39.494456 TX Vref=22, minBit 8, minWin=27, winSum=451
1578 23:50:39.494509 TX Vref=24, minBit 15, minWin=27, winSum=454
1579 23:50:39.494563 TX Vref=26, minBit 15, minWin=27, winSum=454
1580 23:50:39.494616 TX Vref=28, minBit 15, minWin=27, winSum=457
1581 23:50:39.494669 TX Vref=30, minBit 15, minWin=27, winSum=460
1582 23:50:39.494722 TX Vref=32, minBit 9, minWin=27, winSum=457
1583 23:50:39.494776 [TxChooseVref] Worse bit 15, Min win 27, Win sum 460, Final Vref 30
1584 23:50:39.494829
1585 23:50:39.494882 Final TX Range 1 Vref 30
1586 23:50:39.494935
1587 23:50:39.494987 ==
1588 23:50:39.495040 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 23:50:39.495111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 23:50:39.495178 ==
1591 23:50:39.495231
1592 23:50:39.495283
1593 23:50:39.495335 TX Vref Scan disable
1594 23:50:39.495387 == TX Byte 0 ==
1595 23:50:39.495439 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1596 23:50:39.495492 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1597 23:50:39.495545 == TX Byte 1 ==
1598 23:50:39.495597 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1599 23:50:39.495650 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1600 23:50:39.495703
1601 23:50:39.495756 [DATLAT]
1602 23:50:39.495809 Freq=800, CH1 RK0
1603 23:50:39.495861
1604 23:50:39.495914 DATLAT Default: 0xa
1605 23:50:39.495967 0, 0xFFFF, sum = 0
1606 23:50:39.496021 1, 0xFFFF, sum = 0
1607 23:50:39.496074 2, 0xFFFF, sum = 0
1608 23:50:39.496128 3, 0xFFFF, sum = 0
1609 23:50:39.496181 4, 0xFFFF, sum = 0
1610 23:50:39.496235 5, 0xFFFF, sum = 0
1611 23:50:39.496288 6, 0xFFFF, sum = 0
1612 23:50:39.496341 7, 0xFFFF, sum = 0
1613 23:50:39.496394 8, 0xFFFF, sum = 0
1614 23:50:39.496448 9, 0x0, sum = 1
1615 23:50:39.496502 10, 0x0, sum = 2
1616 23:50:39.496565 11, 0x0, sum = 3
1617 23:50:39.496658 12, 0x0, sum = 4
1618 23:50:39.496712 best_step = 10
1619 23:50:39.496765
1620 23:50:39.496817 ==
1621 23:50:39.496870 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 23:50:39.496923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 23:50:39.496976 ==
1624 23:50:39.497029 RX Vref Scan: 1
1625 23:50:39.497082
1626 23:50:39.497134 Set Vref Range= 32 -> 127
1627 23:50:39.497186
1628 23:50:39.497238 RX Vref 32 -> 127, step: 1
1629 23:50:39.497292
1630 23:50:39.497344 RX Delay -95 -> 252, step: 8
1631 23:50:39.497398
1632 23:50:39.497450 Set Vref, RX VrefLevel [Byte0]: 32
1633 23:50:39.497503 [Byte1]: 32
1634 23:50:39.497555
1635 23:50:39.497608 Set Vref, RX VrefLevel [Byte0]: 33
1636 23:50:39.497660 [Byte1]: 33
1637 23:50:39.497713
1638 23:50:39.497766 Set Vref, RX VrefLevel [Byte0]: 34
1639 23:50:39.497819 [Byte1]: 34
1640 23:50:39.497872
1641 23:50:39.497924 Set Vref, RX VrefLevel [Byte0]: 35
1642 23:50:39.497977 [Byte1]: 35
1643 23:50:39.498030
1644 23:50:39.498083 Set Vref, RX VrefLevel [Byte0]: 36
1645 23:50:39.498135 [Byte1]: 36
1646 23:50:39.498189
1647 23:50:39.498241 Set Vref, RX VrefLevel [Byte0]: 37
1648 23:50:39.498294 [Byte1]: 37
1649 23:50:39.498346
1650 23:50:39.498399 Set Vref, RX VrefLevel [Byte0]: 38
1651 23:50:39.498452 [Byte1]: 38
1652 23:50:39.498504
1653 23:50:39.498557 Set Vref, RX VrefLevel [Byte0]: 39
1654 23:50:39.498610 [Byte1]: 39
1655 23:50:39.498662
1656 23:50:39.498714 Set Vref, RX VrefLevel [Byte0]: 40
1657 23:50:39.498766 [Byte1]: 40
1658 23:50:39.498819
1659 23:50:39.498871 Set Vref, RX VrefLevel [Byte0]: 41
1660 23:50:39.498924 [Byte1]: 41
1661 23:50:39.498976
1662 23:50:39.499028 Set Vref, RX VrefLevel [Byte0]: 42
1663 23:50:39.499081 [Byte1]: 42
1664 23:50:39.499134
1665 23:50:39.499186 Set Vref, RX VrefLevel [Byte0]: 43
1666 23:50:39.499240 [Byte1]: 43
1667 23:50:39.499292
1668 23:50:39.499345 Set Vref, RX VrefLevel [Byte0]: 44
1669 23:50:39.499397 [Byte1]: 44
1670 23:50:39.499450
1671 23:50:39.499502 Set Vref, RX VrefLevel [Byte0]: 45
1672 23:50:39.499554 [Byte1]: 45
1673 23:50:39.499607
1674 23:50:39.499658 Set Vref, RX VrefLevel [Byte0]: 46
1675 23:50:39.499711 [Byte1]: 46
1676 23:50:39.499763
1677 23:50:39.499815 Set Vref, RX VrefLevel [Byte0]: 47
1678 23:50:39.499867 [Byte1]: 47
1679 23:50:39.499920
1680 23:50:39.499972 Set Vref, RX VrefLevel [Byte0]: 48
1681 23:50:39.500024 [Byte1]: 48
1682 23:50:39.500077
1683 23:50:39.500129 Set Vref, RX VrefLevel [Byte0]: 49
1684 23:50:39.500181 [Byte1]: 49
1685 23:50:39.500234
1686 23:50:39.500286 Set Vref, RX VrefLevel [Byte0]: 50
1687 23:50:39.500339 [Byte1]: 50
1688 23:50:39.500393
1689 23:50:39.500446 Set Vref, RX VrefLevel [Byte0]: 51
1690 23:50:39.500498 [Byte1]: 51
1691 23:50:39.500561
1692 23:50:39.500648 Set Vref, RX VrefLevel [Byte0]: 52
1693 23:50:39.500700 [Byte1]: 52
1694 23:50:39.500753
1695 23:50:39.500805 Set Vref, RX VrefLevel [Byte0]: 53
1696 23:50:39.500858 [Byte1]: 53
1697 23:50:39.500910
1698 23:50:39.500963 Set Vref, RX VrefLevel [Byte0]: 54
1699 23:50:39.501016 [Byte1]: 54
1700 23:50:39.501069
1701 23:50:39.501312 Set Vref, RX VrefLevel [Byte0]: 55
1702 23:50:39.501371 [Byte1]: 55
1703 23:50:39.501425
1704 23:50:39.501479 Set Vref, RX VrefLevel [Byte0]: 56
1705 23:50:39.501532 [Byte1]: 56
1706 23:50:39.501584
1707 23:50:39.501637 Set Vref, RX VrefLevel [Byte0]: 57
1708 23:50:39.501690 [Byte1]: 57
1709 23:50:39.501744
1710 23:50:39.501796 Set Vref, RX VrefLevel [Byte0]: 58
1711 23:50:39.501849 [Byte1]: 58
1712 23:50:39.501902
1713 23:50:39.501954 Set Vref, RX VrefLevel [Byte0]: 59
1714 23:50:39.502007 [Byte1]: 59
1715 23:50:39.502059
1716 23:50:39.502111 Set Vref, RX VrefLevel [Byte0]: 60
1717 23:50:39.502164 [Byte1]: 60
1718 23:50:39.502216
1719 23:50:39.502269 Set Vref, RX VrefLevel [Byte0]: 61
1720 23:50:39.502322 [Byte1]: 61
1721 23:50:39.502375
1722 23:50:39.502427 Set Vref, RX VrefLevel [Byte0]: 62
1723 23:50:39.502480 [Byte1]: 62
1724 23:50:39.502532
1725 23:50:39.502585 Set Vref, RX VrefLevel [Byte0]: 63
1726 23:50:39.502638 [Byte1]: 63
1727 23:50:39.502690
1728 23:50:39.502743 Set Vref, RX VrefLevel [Byte0]: 64
1729 23:50:39.502796 [Byte1]: 64
1730 23:50:39.502849
1731 23:50:39.502902 Set Vref, RX VrefLevel [Byte0]: 65
1732 23:50:39.502954 [Byte1]: 65
1733 23:50:39.503006
1734 23:50:39.503058 Set Vref, RX VrefLevel [Byte0]: 66
1735 23:50:39.503111 [Byte1]: 66
1736 23:50:39.503163
1737 23:50:39.503215 Set Vref, RX VrefLevel [Byte0]: 67
1738 23:50:39.503267 [Byte1]: 67
1739 23:50:39.503320
1740 23:50:39.503372 Set Vref, RX VrefLevel [Byte0]: 68
1741 23:50:39.503424 [Byte1]: 68
1742 23:50:39.503477
1743 23:50:39.503529 Set Vref, RX VrefLevel [Byte0]: 69
1744 23:50:39.503581 [Byte1]: 69
1745 23:50:39.503634
1746 23:50:39.503686 Set Vref, RX VrefLevel [Byte0]: 70
1747 23:50:39.503738 [Byte1]: 70
1748 23:50:39.503790
1749 23:50:39.503842 Set Vref, RX VrefLevel [Byte0]: 71
1750 23:50:39.503895 [Byte1]: 71
1751 23:50:39.503947
1752 23:50:39.503999 Set Vref, RX VrefLevel [Byte0]: 72
1753 23:50:39.504051 [Byte1]: 72
1754 23:50:39.504103
1755 23:50:39.504156 Set Vref, RX VrefLevel [Byte0]: 73
1756 23:50:39.504208 [Byte1]: 73
1757 23:50:39.504261
1758 23:50:39.504313 Set Vref, RX VrefLevel [Byte0]: 74
1759 23:50:39.504366 [Byte1]: 74
1760 23:50:39.504418
1761 23:50:39.504470 Set Vref, RX VrefLevel [Byte0]: 75
1762 23:50:39.504537 [Byte1]: 75
1763 23:50:39.504617
1764 23:50:39.504671 Set Vref, RX VrefLevel [Byte0]: 76
1765 23:50:39.504724 [Byte1]: 76
1766 23:50:39.504776
1767 23:50:39.504829 Set Vref, RX VrefLevel [Byte0]: 77
1768 23:50:39.504882 [Byte1]: 77
1769 23:50:39.504935
1770 23:50:39.504987 Set Vref, RX VrefLevel [Byte0]: 78
1771 23:50:39.505040 [Byte1]: 78
1772 23:50:39.505093
1773 23:50:39.505145 Set Vref, RX VrefLevel [Byte0]: 79
1774 23:50:39.505198 [Byte1]: 79
1775 23:50:39.505250
1776 23:50:39.505302 Final RX Vref Byte 0 = 53 to rank0
1777 23:50:39.505355 Final RX Vref Byte 1 = 61 to rank0
1778 23:50:39.505409 Final RX Vref Byte 0 = 53 to rank1
1779 23:50:39.505462 Final RX Vref Byte 1 = 61 to rank1==
1780 23:50:39.505515 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 23:50:39.505569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 23:50:39.505621 ==
1783 23:50:39.505675 DQS Delay:
1784 23:50:39.505727 DQS0 = 0, DQS1 = 0
1785 23:50:39.505780 DQM Delay:
1786 23:50:39.505832 DQM0 = 90, DQM1 = 81
1787 23:50:39.505885 DQ Delay:
1788 23:50:39.505937 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =84
1789 23:50:39.505990 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =88
1790 23:50:39.506043 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1791 23:50:39.506097 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =84
1792 23:50:39.506149
1793 23:50:39.506201
1794 23:50:39.506254 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1795 23:50:39.506307 CH1 RK0: MR19=606, MR18=2F4D
1796 23:50:39.506361 CH1_RK0: MR19=0x606, MR18=0x2F4D, DQSOSC=390, MR23=63, INC=97, DEC=64
1797 23:50:39.506414
1798 23:50:39.506466 ----->DramcWriteLeveling(PI) begin...
1799 23:50:39.506520 ==
1800 23:50:39.506573 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 23:50:39.506625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 23:50:39.506679 ==
1803 23:50:39.506731 Write leveling (Byte 0): 27 => 27
1804 23:50:39.506784 Write leveling (Byte 1): 32 => 32
1805 23:50:39.506836 DramcWriteLeveling(PI) end<-----
1806 23:50:39.506889
1807 23:50:39.506941 ==
1808 23:50:39.506994 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 23:50:39.507047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 23:50:39.507100 ==
1811 23:50:39.507152 [Gating] SW mode calibration
1812 23:50:39.507205 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 23:50:39.507259 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 23:50:39.507312 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 23:50:39.507366 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1816 23:50:39.507418 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:50:39.507471 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:50:39.507524 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:50:39.507578 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:50:39.507630 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:50:39.507683 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:50:39.507736 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:50:39.507788 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:50:39.507841 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:50:39.507893 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:50:39.507946 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:50:39.507998 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:50:39.508051 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:50:39.508104 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:50:39.508156 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:50:39.508209 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1832 23:50:39.508261 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:50:39.508314 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:50:39.508582 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:50:39.508689 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:50:39.508770 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:50:39.508826 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:50:39.508881 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:50:39.508935 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1840 23:50:39.508989 0 9 8 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
1841 23:50:39.509043 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 23:50:39.509096 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 23:50:39.509149 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 23:50:39.509202 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:50:39.509255 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 23:50:39.509308 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1847 23:50:39.509361 0 10 4 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (1 0)
1848 23:50:39.509415 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:50:39.509467 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:50:39.509520 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:50:39.509573 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:50:39.509626 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:50:39.509678 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:50:39.509731 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:50:39.509785 0 11 4 | B1->B0 | 3535 3030 | 0 0 | (0 0) (1 1)
1856 23:50:39.509837 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 23:50:39.509889 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 23:50:39.509942 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 23:50:39.509995 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:50:39.510048 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:50:39.510099 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:50:39.510152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 23:50:39.510205 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1864 23:50:39.510258 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1865 23:50:39.510311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:50:39.510364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:50:39.510417 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:50:39.510471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:50:39.510524 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:50:39.510578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:50:39.510631 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:50:39.510684 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:50:39.510737 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:50:39.510790 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:50:39.510843 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:50:39.510895 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:50:39.510948 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:50:39.511001 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1879 23:50:39.511055 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1880 23:50:39.511108 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 23:50:39.511161 Total UI for P1: 0, mck2ui 16
1882 23:50:39.511214 best dqsien dly found for B0: ( 0, 14, 6)
1883 23:50:39.511268 Total UI for P1: 0, mck2ui 16
1884 23:50:39.511322 best dqsien dly found for B1: ( 0, 14, 2)
1885 23:50:39.511375 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1886 23:50:39.511428 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1887 23:50:39.511481
1888 23:50:39.511534 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 23:50:39.511587 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1890 23:50:39.511640 [Gating] SW calibration Done
1891 23:50:39.511693 ==
1892 23:50:39.511746 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 23:50:39.511799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 23:50:39.511853 ==
1895 23:50:39.511905 RX Vref Scan: 0
1896 23:50:39.511958
1897 23:50:39.512011 RX Vref 0 -> 0, step: 1
1898 23:50:39.512065
1899 23:50:39.512117 RX Delay -130 -> 252, step: 16
1900 23:50:39.512170 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1901 23:50:39.512222 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1902 23:50:39.512275 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1903 23:50:39.512327 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1904 23:50:39.512380 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1905 23:50:39.512433 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1906 23:50:39.512486 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1907 23:50:39.512538 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1908 23:50:39.512623 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1909 23:50:39.512692 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1910 23:50:39.512744 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1911 23:50:39.512798 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1912 23:50:39.512850 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1913 23:50:39.512904 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1914 23:50:39.512956 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1915 23:50:39.513009 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1916 23:50:39.513061 ==
1917 23:50:39.707562 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 23:50:39.708094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 23:50:39.708465 ==
1920 23:50:39.709067 DQS Delay:
1921 23:50:39.709463 DQS0 = 0, DQS1 = 0
1922 23:50:39.709799 DQM Delay:
1923 23:50:39.710124 DQM0 = 88, DQM1 = 81
1924 23:50:39.710440 DQ Delay:
1925 23:50:39.710751 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1926 23:50:39.711060 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1927 23:50:39.711366 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1928 23:50:39.711673 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1929 23:50:39.711976
1930 23:50:39.712272
1931 23:50:39.712612 ==
1932 23:50:39.712934 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 23:50:39.713241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 23:50:39.713544 ==
1935 23:50:39.713844
1936 23:50:39.714141
1937 23:50:39.714436 TX Vref Scan disable
1938 23:50:39.715146 == TX Byte 0 ==
1939 23:50:39.715537 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1940 23:50:39.716146 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1941 23:50:39.716786 == TX Byte 1 ==
1942 23:50:39.717410 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1943 23:50:39.717963 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1944 23:50:39.718436 ==
1945 23:50:39.718950 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 23:50:39.719432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 23:50:39.719902 ==
1948 23:50:39.720375 TX Vref=22, minBit 8, minWin=27, winSum=451
1949 23:50:39.720893 TX Vref=24, minBit 13, minWin=27, winSum=454
1950 23:50:39.721370 TX Vref=26, minBit 13, minWin=27, winSum=456
1951 23:50:39.721844 TX Vref=28, minBit 13, minWin=27, winSum=458
1952 23:50:39.722314 TX Vref=30, minBit 8, minWin=27, winSum=460
1953 23:50:39.722784 TX Vref=32, minBit 15, minWin=27, winSum=456
1954 23:50:39.723161 [TxChooseVref] Worse bit 8, Min win 27, Win sum 460, Final Vref 30
1955 23:50:39.723474
1956 23:50:39.723773 Final TX Range 1 Vref 30
1957 23:50:39.724078
1958 23:50:39.724376 ==
1959 23:50:39.724752 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 23:50:39.725064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 23:50:39.725370 ==
1962 23:50:39.725682
1963 23:50:39.726003
1964 23:50:39.726300 TX Vref Scan disable
1965 23:50:39.726601 == TX Byte 0 ==
1966 23:50:39.726901 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1967 23:50:39.727203 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1968 23:50:39.727503 == TX Byte 1 ==
1969 23:50:39.727826 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1970 23:50:39.728127 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1971 23:50:39.728424
1972 23:50:39.728766 [DATLAT]
1973 23:50:39.729105 Freq=800, CH1 RK1
1974 23:50:39.729411
1975 23:50:39.729709 DATLAT Default: 0xa
1976 23:50:39.730010 0, 0xFFFF, sum = 0
1977 23:50:39.730314 1, 0xFFFF, sum = 0
1978 23:50:39.730634 2, 0xFFFF, sum = 0
1979 23:50:39.730850 3, 0xFFFF, sum = 0
1980 23:50:39.731065 4, 0xFFFF, sum = 0
1981 23:50:39.731279 5, 0xFFFF, sum = 0
1982 23:50:39.731493 6, 0xFFFF, sum = 0
1983 23:50:39.731706 7, 0xFFFF, sum = 0
1984 23:50:39.731945 8, 0xFFFF, sum = 0
1985 23:50:39.732251 9, 0x0, sum = 1
1986 23:50:39.732476 10, 0x0, sum = 2
1987 23:50:39.732726 11, 0x0, sum = 3
1988 23:50:39.732945 12, 0x0, sum = 4
1989 23:50:39.733164 best_step = 10
1990 23:50:39.733373
1991 23:50:39.733586 ==
1992 23:50:39.733796 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:50:39.734009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:50:39.734224 ==
1995 23:50:39.734437 RX Vref Scan: 0
1996 23:50:39.734648
1997 23:50:39.734856 RX Vref 0 -> 0, step: 1
1998 23:50:39.735069
1999 23:50:39.735278 RX Delay -95 -> 252, step: 8
2000 23:50:39.735490 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2001 23:50:39.735697 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2002 23:50:39.735854 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2003 23:50:39.736011 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
2004 23:50:39.736168 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2005 23:50:39.736324 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2006 23:50:39.736480 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
2007 23:50:39.736659 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2008 23:50:39.736819 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2009 23:50:39.736975 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2010 23:50:39.737137 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2011 23:50:39.737301 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2012 23:50:39.737464 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2013 23:50:39.737626 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2014 23:50:39.737788 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2015 23:50:39.737981 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2016 23:50:39.738145 ==
2017 23:50:39.738307 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 23:50:39.738472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 23:50:39.738637 ==
2020 23:50:39.738800 DQS Delay:
2021 23:50:39.738961 DQS0 = 0, DQS1 = 0
2022 23:50:39.739121 DQM Delay:
2023 23:50:39.739303 DQM0 = 93, DQM1 = 83
2024 23:50:39.739469 DQ Delay:
2025 23:50:39.739631 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =92
2026 23:50:39.739794 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
2027 23:50:39.739958 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2028 23:50:39.740122 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2029 23:50:39.740286
2030 23:50:39.740447
2031 23:50:39.740641 [DQSOSCAuto] RK1, (LSB)MR18= 0x3910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
2032 23:50:39.740774 CH1 RK1: MR19=606, MR18=3910
2033 23:50:39.740904 CH1_RK1: MR19=0x606, MR18=0x3910, DQSOSC=395, MR23=63, INC=94, DEC=63
2034 23:50:39.741053 [RxdqsGatingPostProcess] freq 800
2035 23:50:39.741183 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 23:50:39.741312 Pre-setting of DQS Precalculation
2037 23:50:39.741441 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 23:50:39.741570 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 23:50:39.741700 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 23:50:39.741829
2041 23:50:39.741957
2042 23:50:39.742082 [Calibration Summary] 1600 Mbps
2043 23:50:39.742219 CH 0, Rank 0
2044 23:50:39.742360 SW Impedance : PASS
2045 23:50:39.742490 DUTY Scan : NO K
2046 23:50:39.742618 ZQ Calibration : PASS
2047 23:50:39.742747 Jitter Meter : NO K
2048 23:50:39.742876 CBT Training : PASS
2049 23:50:39.743004 Write leveling : PASS
2050 23:50:39.743130 RX DQS gating : PASS
2051 23:50:39.743259 RX DQ/DQS(RDDQC) : PASS
2052 23:50:39.743386 TX DQ/DQS : PASS
2053 23:50:39.743514 RX DATLAT : PASS
2054 23:50:39.743642 RX DQ/DQS(Engine): PASS
2055 23:50:39.743769 TX OE : NO K
2056 23:50:39.743898 All Pass.
2057 23:50:39.744024
2058 23:50:39.744152 CH 0, Rank 1
2059 23:50:39.744294 SW Impedance : PASS
2060 23:50:39.744424 DUTY Scan : NO K
2061 23:50:39.744567 ZQ Calibration : PASS
2062 23:50:39.744715 Jitter Meter : NO K
2063 23:50:39.744848 CBT Training : PASS
2064 23:50:39.744977 Write leveling : PASS
2065 23:50:39.745107 RX DQS gating : PASS
2066 23:50:39.745235 RX DQ/DQS(RDDQC) : PASS
2067 23:50:39.745378 TX DQ/DQS : PASS
2068 23:50:39.745510 RX DATLAT : PASS
2069 23:50:39.745646 RX DQ/DQS(Engine): PASS
2070 23:50:39.745752 TX OE : NO K
2071 23:50:39.745858 All Pass.
2072 23:50:39.745961
2073 23:50:39.746066 CH 1, Rank 0
2074 23:50:39.746171 SW Impedance : PASS
2075 23:50:39.746277 DUTY Scan : NO K
2076 23:50:39.746383 ZQ Calibration : PASS
2077 23:50:39.746502 Jitter Meter : NO K
2078 23:50:39.746612 CBT Training : PASS
2079 23:50:39.746719 Write leveling : PASS
2080 23:50:39.746825 RX DQS gating : PASS
2081 23:50:39.746930 RX DQ/DQS(RDDQC) : PASS
2082 23:50:39.747036 TX DQ/DQS : PASS
2083 23:50:39.747376 RX DATLAT : PASS
2084 23:50:39.747511 RX DQ/DQS(Engine): PASS
2085 23:50:39.747621 TX OE : NO K
2086 23:50:39.747729 All Pass.
2087 23:50:39.747835
2088 23:50:39.747940 CH 1, Rank 1
2089 23:50:39.748047 SW Impedance : PASS
2090 23:50:39.748153 DUTY Scan : NO K
2091 23:50:39.748260 ZQ Calibration : PASS
2092 23:50:39.748367 Jitter Meter : NO K
2093 23:50:39.748472 CBT Training : PASS
2094 23:50:39.748604 Write leveling : PASS
2095 23:50:39.748715 RX DQS gating : PASS
2096 23:50:39.748840 RX DQ/DQS(RDDQC) : PASS
2097 23:50:39.748948 TX DQ/DQS : PASS
2098 23:50:39.749056 RX DATLAT : PASS
2099 23:50:39.749162 RX DQ/DQS(Engine): PASS
2100 23:50:39.749269 TX OE : NO K
2101 23:50:39.749374 All Pass.
2102 23:50:39.749479
2103 23:50:39.749585 DramC Write-DBI off
2104 23:50:39.749692 PER_BANK_REFRESH: Hybrid Mode
2105 23:50:39.749815 TX_TRACKING: ON
2106 23:50:39.749923 [GetDramInforAfterCalByMRR] Vendor 6.
2107 23:50:39.750031 [GetDramInforAfterCalByMRR] Revision 606.
2108 23:50:39.750138 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 23:50:39.750244 MR0 0x3b3b
2110 23:50:39.750350 MR8 0x5151
2111 23:50:39.750456 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 23:50:39.750562
2113 23:50:39.750679 MR0 0x3b3b
2114 23:50:39.750772 MR8 0x5151
2115 23:50:39.750862 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 23:50:39.750952
2117 23:50:39.751043 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 23:50:39.751135 [FAST_K] Save calibration result to emmc
2119 23:50:39.751226 [FAST_K] Save calibration result to emmc
2120 23:50:39.751317 dram_init: config_dvfs: 1
2121 23:50:39.751408 dramc_set_vcore_voltage set vcore to 662500
2122 23:50:39.751498 Read voltage for 1200, 2
2123 23:50:39.751588 Vio18 = 0
2124 23:50:39.751678 Vcore = 662500
2125 23:50:39.751768 Vdram = 0
2126 23:50:39.751858 Vddq = 0
2127 23:50:39.751947 Vmddr = 0
2128 23:50:39.752038 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 23:50:39.752129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 23:50:39.752219 MEM_TYPE=3, freq_sel=15
2131 23:50:39.752309 sv_algorithm_assistance_LP4_1600
2132 23:50:39.752400 ============ PULL DRAM RESETB DOWN ============
2133 23:50:39.752492 ========== PULL DRAM RESETB DOWN end =========
2134 23:50:39.752606 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 23:50:39.752700 ===================================
2136 23:50:39.752792 LPDDR4 DRAM CONFIGURATION
2137 23:50:39.752882 ===================================
2138 23:50:39.752974 EX_ROW_EN[0] = 0x0
2139 23:50:39.753065 EX_ROW_EN[1] = 0x0
2140 23:50:39.753154 LP4Y_EN = 0x0
2141 23:50:39.753245 WORK_FSP = 0x0
2142 23:50:39.753335 WL = 0x4
2143 23:50:39.753425 RL = 0x4
2144 23:50:39.753515 BL = 0x2
2145 23:50:39.753605 RPST = 0x0
2146 23:50:39.753696 RD_PRE = 0x0
2147 23:50:39.753802 WR_PRE = 0x1
2148 23:50:39.753893 WR_PST = 0x0
2149 23:50:39.753984 DBI_WR = 0x0
2150 23:50:39.754074 DBI_RD = 0x0
2151 23:50:39.754164 OTF = 0x1
2152 23:50:39.754254 ===================================
2153 23:50:39.754346 ===================================
2154 23:50:39.754437 ANA top config
2155 23:50:39.754534 ===================================
2156 23:50:39.754629 DLL_ASYNC_EN = 0
2157 23:50:39.754719 ALL_SLAVE_EN = 0
2158 23:50:39.754809 NEW_RANK_MODE = 1
2159 23:50:39.754901 DLL_IDLE_MODE = 1
2160 23:50:39.754991 LP45_APHY_COMB_EN = 1
2161 23:50:39.755082 TX_ODT_DIS = 1
2162 23:50:39.755172 NEW_8X_MODE = 1
2163 23:50:39.755264 ===================================
2164 23:50:39.755356 ===================================
2165 23:50:39.755458 data_rate = 2400
2166 23:50:39.755550 CKR = 1
2167 23:50:39.755654 DQ_P2S_RATIO = 8
2168 23:50:39.755733 ===================================
2169 23:50:39.755813 CA_P2S_RATIO = 8
2170 23:50:39.755892 DQ_CA_OPEN = 0
2171 23:50:39.755971 DQ_SEMI_OPEN = 0
2172 23:50:39.756049 CA_SEMI_OPEN = 0
2173 23:50:39.756132 CA_FULL_RATE = 0
2174 23:50:39.756218 DQ_CKDIV4_EN = 0
2175 23:50:39.756297 CA_CKDIV4_EN = 0
2176 23:50:39.756376 CA_PREDIV_EN = 0
2177 23:50:39.756454 PH8_DLY = 17
2178 23:50:39.756533 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 23:50:39.756669 DQ_AAMCK_DIV = 4
2180 23:50:39.756790 CA_AAMCK_DIV = 4
2181 23:50:39.756912 CA_ADMCK_DIV = 4
2182 23:50:39.757033 DQ_TRACK_CA_EN = 0
2183 23:50:39.757154 CA_PICK = 1200
2184 23:50:39.757259 CA_MCKIO = 1200
2185 23:50:39.757340 MCKIO_SEMI = 0
2186 23:50:39.757419 PLL_FREQ = 2366
2187 23:50:39.757498 DQ_UI_PI_RATIO = 32
2188 23:50:39.757577 CA_UI_PI_RATIO = 0
2189 23:50:39.757656 ===================================
2190 23:50:39.757735 ===================================
2191 23:50:39.757815 memory_type:LPDDR4
2192 23:50:39.757894 GP_NUM : 10
2193 23:50:39.757973 SRAM_EN : 1
2194 23:50:39.758052 MD32_EN : 0
2195 23:50:39.758130 ===================================
2196 23:50:39.758210 [ANA_INIT] >>>>>>>>>>>>>>
2197 23:50:39.758303 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 23:50:39.758385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 23:50:39.758465 ===================================
2200 23:50:39.758545 data_rate = 2400,PCW = 0X5b00
2201 23:50:39.758623 ===================================
2202 23:50:39.758703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 23:50:39.758783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 23:50:39.758862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 23:50:39.758942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 23:50:39.759021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 23:50:39.759100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 23:50:39.759180 [ANA_INIT] flow start
2209 23:50:39.759259 [ANA_INIT] PLL >>>>>>>>
2210 23:50:39.759347 [ANA_INIT] PLL <<<<<<<<
2211 23:50:39.759428 [ANA_INIT] MIDPI >>>>>>>>
2212 23:50:39.759507 [ANA_INIT] MIDPI <<<<<<<<
2213 23:50:39.759586 [ANA_INIT] DLL >>>>>>>>
2214 23:50:39.759664 [ANA_INIT] DLL <<<<<<<<
2215 23:50:39.759744 [ANA_INIT] flow end
2216 23:50:39.759823 ============ LP4 DIFF to SE enter ============
2217 23:50:39.759902 ============ LP4 DIFF to SE exit ============
2218 23:50:39.759981 [ANA_INIT] <<<<<<<<<<<<<
2219 23:50:39.760061 [Flow] Enable top DCM control >>>>>
2220 23:50:39.760350 [Flow] Enable top DCM control <<<<<
2221 23:50:39.760480 Enable DLL master slave shuffle
2222 23:50:39.760636 ==============================================================
2223 23:50:39.760747 Gating Mode config
2224 23:50:39.760856 ==============================================================
2225 23:50:39.760964 Config description:
2226 23:50:39.761074 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 23:50:39.761185 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 23:50:39.761294 SELPH_MODE 0: By rank 1: By Phase
2229 23:50:39.761403 ==============================================================
2230 23:50:39.761498 GAT_TRACK_EN = 1
2231 23:50:39.761572 RX_GATING_MODE = 2
2232 23:50:39.761643 RX_GATING_TRACK_MODE = 2
2233 23:50:39.761713 SELPH_MODE = 1
2234 23:50:39.761784 PICG_EARLY_EN = 1
2235 23:50:39.761855 VALID_LAT_VALUE = 1
2236 23:50:39.761925 ==============================================================
2237 23:50:39.761997 Enter into Gating configuration >>>>
2238 23:50:39.762068 Exit from Gating configuration <<<<
2239 23:50:39.762138 Enter into DVFS_PRE_config >>>>>
2240 23:50:39.762210 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 23:50:39.762283 Exit from DVFS_PRE_config <<<<<
2242 23:50:39.762353 Enter into PICG configuration >>>>
2243 23:50:39.762424 Exit from PICG configuration <<<<
2244 23:50:39.762495 [RX_INPUT] configuration >>>>>
2245 23:50:39.762574 [RX_INPUT] configuration <<<<<
2246 23:50:39.762646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 23:50:39.762716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 23:50:39.762787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 23:50:39.762859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 23:50:39.762930 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 23:50:39.763001 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 23:50:39.763071 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 23:50:39.763142 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 23:50:39.763212 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 23:50:39.763282 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 23:50:39.763353 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 23:50:39.763423 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 23:50:39.763493 ===================================
2259 23:50:39.763570 LPDDR4 DRAM CONFIGURATION
2260 23:50:39.763643 ===================================
2261 23:50:39.763715 EX_ROW_EN[0] = 0x0
2262 23:50:39.763785 EX_ROW_EN[1] = 0x0
2263 23:50:39.763855 LP4Y_EN = 0x0
2264 23:50:39.763924 WORK_FSP = 0x0
2265 23:50:39.763995 WL = 0x4
2266 23:50:39.764065 RL = 0x4
2267 23:50:39.764135 BL = 0x2
2268 23:50:39.764204 RPST = 0x0
2269 23:50:39.764274 RD_PRE = 0x0
2270 23:50:39.764344 WR_PRE = 0x1
2271 23:50:39.764415 WR_PST = 0x0
2272 23:50:39.764484 DBI_WR = 0x0
2273 23:50:39.764565 DBI_RD = 0x0
2274 23:50:39.764669 OTF = 0x1
2275 23:50:39.764742 ===================================
2276 23:50:39.764813 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 23:50:39.764884 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 23:50:39.764956 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 23:50:39.765028 ===================================
2280 23:50:39.765098 LPDDR4 DRAM CONFIGURATION
2281 23:50:39.765168 ===================================
2282 23:50:39.765238 EX_ROW_EN[0] = 0x10
2283 23:50:39.765309 EX_ROW_EN[1] = 0x0
2284 23:50:39.765379 LP4Y_EN = 0x0
2285 23:50:39.765448 WORK_FSP = 0x0
2286 23:50:39.765518 WL = 0x4
2287 23:50:39.765588 RL = 0x4
2288 23:50:39.765669 BL = 0x2
2289 23:50:39.765749 RPST = 0x0
2290 23:50:39.765813 RD_PRE = 0x0
2291 23:50:39.765876 WR_PRE = 0x1
2292 23:50:39.765939 WR_PST = 0x0
2293 23:50:39.766002 DBI_WR = 0x0
2294 23:50:39.766064 DBI_RD = 0x0
2295 23:50:39.766125 OTF = 0x1
2296 23:50:39.766186 ===================================
2297 23:50:39.766247 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 23:50:39.766309 ==
2299 23:50:39.766370 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 23:50:39.766432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 23:50:39.766494 ==
2302 23:50:39.766554 [Duty_Offset_Calibration]
2303 23:50:39.766615 B0:2 B1:0 CA:1
2304 23:50:39.766676
2305 23:50:39.766737 [DutyScan_Calibration_Flow] k_type=0
2306 23:50:39.766808
2307 23:50:39.766869 ==CLK 0==
2308 23:50:39.766930 Final CLK duty delay cell = -4
2309 23:50:39.766991 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2310 23:50:39.767052 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2311 23:50:39.767113 [-4] AVG Duty = 4953%(X100)
2312 23:50:39.767173
2313 23:50:39.767234 CH0 CLK Duty spec in!! Max-Min= 156%
2314 23:50:39.767295 [DutyScan_Calibration_Flow] ====Done====
2315 23:50:39.767356
2316 23:50:39.767417 [DutyScan_Calibration_Flow] k_type=1
2317 23:50:39.767477
2318 23:50:39.767538 ==DQS 0 ==
2319 23:50:39.767599 Final DQS duty delay cell = 0
2320 23:50:39.767660 [0] MAX Duty = 5187%(X100), DQS PI = 30
2321 23:50:39.767721 [0] MIN Duty = 4938%(X100), DQS PI = 0
2322 23:50:39.767782 [0] AVG Duty = 5062%(X100)
2323 23:50:39.767854
2324 23:50:39.767916 ==DQS 1 ==
2325 23:50:39.767977 Final DQS duty delay cell = -4
2326 23:50:39.768038 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2327 23:50:39.768100 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2328 23:50:39.768161 [-4] AVG Duty = 5015%(X100)
2329 23:50:39.768222
2330 23:50:39.768283 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2331 23:50:39.768344
2332 23:50:39.768403 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2333 23:50:39.768464 [DutyScan_Calibration_Flow] ====Done====
2334 23:50:39.768524
2335 23:50:39.768617 [DutyScan_Calibration_Flow] k_type=3
2336 23:50:39.768714
2337 23:50:39.768808 ==DQM 0 ==
2338 23:50:39.768903 Final DQM duty delay cell = 0
2339 23:50:39.768969 [0] MAX Duty = 5062%(X100), DQS PI = 24
2340 23:50:39.769031 [0] MIN Duty = 4813%(X100), DQS PI = 0
2341 23:50:39.769300 [0] AVG Duty = 4937%(X100)
2342 23:50:39.769374
2343 23:50:39.769436 ==DQM 1 ==
2344 23:50:39.769498 Final DQM duty delay cell = 0
2345 23:50:39.769560 [0] MAX Duty = 5187%(X100), DQS PI = 48
2346 23:50:39.769621 [0] MIN Duty = 5000%(X100), DQS PI = 14
2347 23:50:39.769683 [0] AVG Duty = 5093%(X100)
2348 23:50:39.769743
2349 23:50:39.769805 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2350 23:50:39.769866
2351 23:50:39.769928 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2352 23:50:39.769997 [DutyScan_Calibration_Flow] ====Done====
2353 23:50:39.770059
2354 23:50:39.770120 [DutyScan_Calibration_Flow] k_type=2
2355 23:50:39.770182
2356 23:50:39.770242 ==DQ 0 ==
2357 23:50:39.770303 Final DQ duty delay cell = -4
2358 23:50:39.770364 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2359 23:50:39.770425 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2360 23:50:39.770486 [-4] AVG Duty = 4953%(X100)
2361 23:50:39.770547
2362 23:50:39.770607 ==DQ 1 ==
2363 23:50:39.770676 Final DQ duty delay cell = 4
2364 23:50:39.770732 [4] MAX Duty = 5093%(X100), DQS PI = 4
2365 23:50:39.770787 [4] MIN Duty = 5000%(X100), DQS PI = 18
2366 23:50:39.770842 [4] AVG Duty = 5046%(X100)
2367 23:50:39.770896
2368 23:50:39.770951 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2369 23:50:39.771014
2370 23:50:39.771070 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2371 23:50:39.771126 [DutyScan_Calibration_Flow] ====Done====
2372 23:50:39.771181 ==
2373 23:50:39.771237 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 23:50:39.771293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 23:50:39.771349 ==
2376 23:50:39.771404 [Duty_Offset_Calibration]
2377 23:50:39.771459 B0:0 B1:-1 CA:2
2378 23:50:39.771514
2379 23:50:39.771570 [DutyScan_Calibration_Flow] k_type=0
2380 23:50:39.771625
2381 23:50:39.771680 ==CLK 0==
2382 23:50:39.771735 Final CLK duty delay cell = 0
2383 23:50:39.771790 [0] MAX Duty = 5156%(X100), DQS PI = 14
2384 23:50:39.771846 [0] MIN Duty = 4938%(X100), DQS PI = 44
2385 23:50:39.771901 [0] AVG Duty = 5047%(X100)
2386 23:50:39.771956
2387 23:50:39.772010 CH1 CLK Duty spec in!! Max-Min= 218%
2388 23:50:39.772073 [DutyScan_Calibration_Flow] ====Done====
2389 23:50:39.772131
2390 23:50:39.772187 [DutyScan_Calibration_Flow] k_type=1
2391 23:50:39.772242
2392 23:50:39.772296 ==DQS 0 ==
2393 23:50:39.772352 Final DQS duty delay cell = 0
2394 23:50:39.772407 [0] MAX Duty = 5062%(X100), DQS PI = 22
2395 23:50:39.772462 [0] MIN Duty = 4969%(X100), DQS PI = 0
2396 23:50:39.772518 [0] AVG Duty = 5015%(X100)
2397 23:50:39.772596
2398 23:50:39.772683 ==DQS 1 ==
2399 23:50:39.772775 Final DQS duty delay cell = 0
2400 23:50:39.772864 [0] MAX Duty = 5156%(X100), DQS PI = 0
2401 23:50:39.772951 [0] MIN Duty = 4844%(X100), DQS PI = 36
2402 23:50:39.773037 [0] AVG Duty = 5000%(X100)
2403 23:50:39.773127
2404 23:50:39.773216 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2405 23:50:39.773285
2406 23:50:39.773342 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2407 23:50:39.773397 [DutyScan_Calibration_Flow] ====Done====
2408 23:50:39.773453
2409 23:50:39.773510 [DutyScan_Calibration_Flow] k_type=3
2410 23:50:39.773565
2411 23:50:39.773620 ==DQM 0 ==
2412 23:50:39.773675 Final DQM duty delay cell = 4
2413 23:50:39.773735 [4] MAX Duty = 5093%(X100), DQS PI = 20
2414 23:50:39.773791 [4] MIN Duty = 4938%(X100), DQS PI = 44
2415 23:50:39.773846 [4] AVG Duty = 5015%(X100)
2416 23:50:39.773901
2417 23:50:39.773956 ==DQM 1 ==
2418 23:50:39.774012 Final DQM duty delay cell = 0
2419 23:50:39.774068 [0] MAX Duty = 5249%(X100), DQS PI = 60
2420 23:50:39.774123 [0] MIN Duty = 4875%(X100), DQS PI = 36
2421 23:50:39.774186 [0] AVG Duty = 5062%(X100)
2422 23:50:39.774245
2423 23:50:39.774300 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2424 23:50:39.774356
2425 23:50:39.774410 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2426 23:50:39.774466 [DutyScan_Calibration_Flow] ====Done====
2427 23:50:39.774521
2428 23:50:39.774577 [DutyScan_Calibration_Flow] k_type=2
2429 23:50:39.774633
2430 23:50:39.774687 ==DQ 0 ==
2431 23:50:39.774743 Final DQ duty delay cell = 0
2432 23:50:39.774798 [0] MAX Duty = 5062%(X100), DQS PI = 20
2433 23:50:39.774854 [0] MIN Duty = 4938%(X100), DQS PI = 0
2434 23:50:39.774910 [0] AVG Duty = 5000%(X100)
2435 23:50:39.774968
2436 23:50:39.775057 ==DQ 1 ==
2437 23:50:39.775144 Final DQ duty delay cell = 0
2438 23:50:39.775232 [0] MAX Duty = 5031%(X100), DQS PI = 2
2439 23:50:39.775301 [0] MIN Duty = 4813%(X100), DQS PI = 34
2440 23:50:39.775357 [0] AVG Duty = 4922%(X100)
2441 23:50:39.775413
2442 23:50:39.775468 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2443 23:50:39.775524
2444 23:50:39.775579 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2445 23:50:39.775646 [DutyScan_Calibration_Flow] ====Done====
2446 23:50:39.775699 nWR fixed to 30
2447 23:50:39.775752 [ModeRegInit_LP4] CH0 RK0
2448 23:50:39.775805 [ModeRegInit_LP4] CH0 RK1
2449 23:50:39.775860 [ModeRegInit_LP4] CH1 RK0
2450 23:50:39.775917 [ModeRegInit_LP4] CH1 RK1
2451 23:50:39.775970 match AC timing 7
2452 23:50:39.776023 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 23:50:39.776076 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 23:50:39.776129 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 23:50:39.776182 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 23:50:39.776236 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 23:50:39.776288 ==
2458 23:50:39.776347 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 23:50:39.776402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 23:50:39.776455 ==
2461 23:50:39.776508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 23:50:39.776602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2463 23:50:39.776659 [CA 0] Center 38 (8~69) winsize 62
2464 23:50:39.776713 [CA 1] Center 38 (8~69) winsize 62
2465 23:50:39.776765 [CA 2] Center 35 (5~66) winsize 62
2466 23:50:39.776819 [CA 3] Center 35 (4~66) winsize 63
2467 23:50:39.776871 [CA 4] Center 34 (4~65) winsize 62
2468 23:50:39.776931 [CA 5] Center 33 (3~63) winsize 61
2469 23:50:39.776985
2470 23:50:39.777038 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2471 23:50:39.777091
2472 23:50:39.777144 [CATrainingPosCal] consider 1 rank data
2473 23:50:39.777198 u2DelayCellTimex100 = 270/100 ps
2474 23:50:39.777251 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 23:50:39.777304 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2476 23:50:39.777357 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 23:50:39.777416 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2478 23:50:39.777470 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 23:50:39.777523 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 23:50:39.777576
2481 23:50:39.777629 CA PerBit enable=1, Macro0, CA PI delay=33
2482 23:50:39.777682
2483 23:50:39.777735 [CBTSetCACLKResult] CA Dly = 33
2484 23:50:39.777788 CS Dly: 6 (0~37)
2485 23:50:39.777841 ==
2486 23:50:39.777893 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 23:50:39.777964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 23:50:39.778054 ==
2489 23:50:39.778139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 23:50:39.778391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2491 23:50:39.778496 [CA 0] Center 39 (8~70) winsize 63
2492 23:50:39.778554 [CA 1] Center 38 (8~69) winsize 62
2493 23:50:39.778609 [CA 2] Center 35 (5~66) winsize 62
2494 23:50:39.778662 [CA 3] Center 35 (5~66) winsize 62
2495 23:50:39.778716 [CA 4] Center 34 (4~65) winsize 62
2496 23:50:39.778769 [CA 5] Center 34 (4~64) winsize 61
2497 23:50:39.778821
2498 23:50:39.778874 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2499 23:50:39.778928
2500 23:50:39.778981 [CATrainingPosCal] consider 2 rank data
2501 23:50:39.779036 u2DelayCellTimex100 = 270/100 ps
2502 23:50:39.779095 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 23:50:39.779148 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2504 23:50:39.779202 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 23:50:39.779254 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 23:50:39.779307 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 23:50:39.779360 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 23:50:39.779413
2509 23:50:39.779465 CA PerBit enable=1, Macro0, CA PI delay=33
2510 23:50:39.779522
2511 23:50:39.779617 [CBTSetCACLKResult] CA Dly = 33
2512 23:50:39.779670 CS Dly: 7 (0~39)
2513 23:50:39.779726
2514 23:50:39.779779 ----->DramcWriteLeveling(PI) begin...
2515 23:50:39.779834 ==
2516 23:50:39.779887 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 23:50:39.779940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 23:50:39.780001 ==
2519 23:50:39.780056 Write leveling (Byte 0): 36 => 36
2520 23:50:39.780109 Write leveling (Byte 1): 30 => 30
2521 23:50:39.780162 DramcWriteLeveling(PI) end<-----
2522 23:50:39.780214
2523 23:50:39.780267 ==
2524 23:50:39.780319 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 23:50:39.780372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 23:50:39.780425 ==
2527 23:50:39.780477 [Gating] SW mode calibration
2528 23:50:39.780540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 23:50:39.780642 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 23:50:39.780695 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2531 23:50:39.780749 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2532 23:50:39.780803 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 23:50:39.780856 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 23:50:39.780908 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 23:50:39.780961 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 23:50:39.781014 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2537 23:50:39.781072 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2538 23:50:39.781126 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2539 23:50:39.781180 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 23:50:39.781233 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 23:50:39.781287 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 23:50:39.781339 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:50:39.781392 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 23:50:39.781449 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2545 23:50:39.781503 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2546 23:50:39.781560 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
2547 23:50:39.781615 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 23:50:39.781667 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 23:50:39.781720 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 23:50:39.781773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:50:39.781826 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 23:50:39.781879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 23:50:39.781931 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 23:50:39.781984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 23:50:39.782037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:50:39.782089 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:50:39.782142 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:50:39.782199 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:50:39.782254 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:50:39.782307 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:50:39.782360 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:50:39.782413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:50:39.782466 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:50:39.782519 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:50:39.782572 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:50:39.782624 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:50:39.782677 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:50:39.782737 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 23:50:39.782791 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2570 23:50:39.782844 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 23:50:39.782897 Total UI for P1: 0, mck2ui 16
2572 23:50:39.782950 best dqsien dly found for B0: ( 1, 3, 26)
2573 23:50:39.783003 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 23:50:39.783057 Total UI for P1: 0, mck2ui 16
2575 23:50:39.783110 best dqsien dly found for B1: ( 1, 3, 30)
2576 23:50:39.783163 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2577 23:50:39.783216 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2578 23:50:39.783276
2579 23:50:39.783330 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2580 23:50:39.783383 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2581 23:50:39.783435 [Gating] SW calibration Done
2582 23:50:39.783489 ==
2583 23:50:39.783542 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 23:50:39.783595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 23:50:39.783649 ==
2586 23:50:39.783701 RX Vref Scan: 0
2587 23:50:39.783762
2588 23:50:39.783820 RX Vref 0 -> 0, step: 1
2589 23:50:39.783873
2590 23:50:39.783926 RX Delay -40 -> 252, step: 8
2591 23:50:39.783979 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2592 23:50:39.784031 iDelay=208, Bit 1, Center 123 (48 ~ 199) 152
2593 23:50:39.784084 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2594 23:50:39.784137 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2595 23:50:39.784388 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2596 23:50:39.784494 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2597 23:50:39.784636 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2598 23:50:39.784741 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2599 23:50:39.784844 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2600 23:50:39.784947 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2601 23:50:39.785051 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2602 23:50:39.785153 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2603 23:50:39.785256 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2604 23:50:39.785359 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2605 23:50:39.785437 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2606 23:50:39.785492 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2607 23:50:39.785546 ==
2608 23:50:39.785600 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 23:50:39.785653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 23:50:39.785707 ==
2611 23:50:39.785760 DQS Delay:
2612 23:50:39.785812 DQS0 = 0, DQS1 = 0
2613 23:50:39.785866 DQM Delay:
2614 23:50:39.785918 DQM0 = 123, DQM1 = 110
2615 23:50:39.785971 DQ Delay:
2616 23:50:39.786024 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2617 23:50:39.786077 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2618 23:50:39.786130 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2619 23:50:39.786183 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2620 23:50:39.786235
2621 23:50:39.786287
2622 23:50:39.786339 ==
2623 23:50:39.786391 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 23:50:39.786444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 23:50:39.786497 ==
2626 23:50:39.786549
2627 23:50:39.786601
2628 23:50:39.786653 TX Vref Scan disable
2629 23:50:39.786706 == TX Byte 0 ==
2630 23:50:39.786759 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2631 23:50:39.786812 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2632 23:50:39.786865 == TX Byte 1 ==
2633 23:50:39.786918 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2634 23:50:39.786971 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2635 23:50:39.787024 ==
2636 23:50:39.787076 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 23:50:39.787129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 23:50:39.787183 ==
2639 23:50:39.787236 TX Vref=22, minBit 3, minWin=24, winSum=409
2640 23:50:39.787290 TX Vref=24, minBit 4, minWin=25, winSum=419
2641 23:50:39.787343 TX Vref=26, minBit 1, minWin=24, winSum=425
2642 23:50:39.787396 TX Vref=28, minBit 2, minWin=26, winSum=428
2643 23:50:39.787449 TX Vref=30, minBit 7, minWin=25, winSum=427
2644 23:50:39.787502 TX Vref=32, minBit 3, minWin=25, winSum=425
2645 23:50:39.787555 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 28
2646 23:50:39.787608
2647 23:50:39.787661 Final TX Range 1 Vref 28
2648 23:50:39.787714
2649 23:50:39.787766 ==
2650 23:50:39.787819 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 23:50:39.787872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 23:50:39.787925 ==
2653 23:50:39.787977
2654 23:50:39.788030
2655 23:50:39.788089 TX Vref Scan disable
2656 23:50:39.788172 == TX Byte 0 ==
2657 23:50:39.788255 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2658 23:50:39.788338 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2659 23:50:39.788419 == TX Byte 1 ==
2660 23:50:39.788501 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2661 23:50:39.788599 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2662 23:50:39.788668
2663 23:50:39.788722 [DATLAT]
2664 23:50:39.788782 Freq=1200, CH0 RK0
2665 23:50:39.788835
2666 23:50:39.788888 DATLAT Default: 0xd
2667 23:50:39.788941 0, 0xFFFF, sum = 0
2668 23:50:39.788996 1, 0xFFFF, sum = 0
2669 23:50:39.789050 2, 0xFFFF, sum = 0
2670 23:50:39.789103 3, 0xFFFF, sum = 0
2671 23:50:39.789157 4, 0xFFFF, sum = 0
2672 23:50:39.789211 5, 0xFFFF, sum = 0
2673 23:50:39.789264 6, 0xFFFF, sum = 0
2674 23:50:39.789324 7, 0xFFFF, sum = 0
2675 23:50:39.789379 8, 0xFFFF, sum = 0
2676 23:50:39.789433 9, 0xFFFF, sum = 0
2677 23:50:39.789486 10, 0xFFFF, sum = 0
2678 23:50:39.789541 11, 0xFFFF, sum = 0
2679 23:50:39.789595 12, 0x0, sum = 1
2680 23:50:39.789648 13, 0x0, sum = 2
2681 23:50:39.789702 14, 0x0, sum = 3
2682 23:50:39.789756 15, 0x0, sum = 4
2683 23:50:39.789814 best_step = 13
2684 23:50:39.789869
2685 23:50:39.789921 ==
2686 23:50:39.789974 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 23:50:39.790027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 23:50:39.790080 ==
2689 23:50:39.790133 RX Vref Scan: 1
2690 23:50:39.790186
2691 23:50:39.790238 Set Vref Range= 32 -> 127
2692 23:50:39.790291
2693 23:50:39.790351 RX Vref 32 -> 127, step: 1
2694 23:50:39.790405
2695 23:50:39.790457 RX Delay -13 -> 252, step: 4
2696 23:50:39.790510
2697 23:50:39.790562 Set Vref, RX VrefLevel [Byte0]: 32
2698 23:50:39.790615 [Byte1]: 32
2699 23:50:39.790669
2700 23:50:39.790722 Set Vref, RX VrefLevel [Byte0]: 33
2701 23:50:39.790775 [Byte1]: 33
2702 23:50:39.790832
2703 23:50:39.790886 Set Vref, RX VrefLevel [Byte0]: 34
2704 23:50:39.790940 [Byte1]: 34
2705 23:50:39.790992
2706 23:50:39.791045 Set Vref, RX VrefLevel [Byte0]: 35
2707 23:50:39.791097 [Byte1]: 35
2708 23:50:39.791150
2709 23:50:39.791203 Set Vref, RX VrefLevel [Byte0]: 36
2710 23:50:39.791256 [Byte1]: 36
2711 23:50:39.791309
2712 23:50:39.791367 Set Vref, RX VrefLevel [Byte0]: 37
2713 23:50:39.791422 [Byte1]: 37
2714 23:50:39.791474
2715 23:50:39.791527 Set Vref, RX VrefLevel [Byte0]: 38
2716 23:50:39.791586 [Byte1]: 38
2717 23:50:39.791640
2718 23:50:39.791693 Set Vref, RX VrefLevel [Byte0]: 39
2719 23:50:39.791747 [Byte1]: 39
2720 23:50:39.791800
2721 23:50:39.791852 Set Vref, RX VrefLevel [Byte0]: 40
2722 23:50:39.791935 [Byte1]: 40
2723 23:50:39.792017
2724 23:50:39.792099 Set Vref, RX VrefLevel [Byte0]: 41
2725 23:50:39.792182 [Byte1]: 41
2726 23:50:39.792263
2727 23:50:39.792345 Set Vref, RX VrefLevel [Byte0]: 42
2728 23:50:39.792430 [Byte1]: 42
2729 23:50:39.792513
2730 23:50:39.792616 Set Vref, RX VrefLevel [Byte0]: 43
2731 23:50:39.792671 [Byte1]: 43
2732 23:50:39.792725
2733 23:50:39.792778 Set Vref, RX VrefLevel [Byte0]: 44
2734 23:50:39.792831 [Byte1]: 44
2735 23:50:39.792884
2736 23:50:39.792945 Set Vref, RX VrefLevel [Byte0]: 45
2737 23:50:39.792999 [Byte1]: 45
2738 23:50:39.793052
2739 23:50:39.793105 Set Vref, RX VrefLevel [Byte0]: 46
2740 23:50:39.793158 [Byte1]: 46
2741 23:50:39.793211
2742 23:50:39.793264 Set Vref, RX VrefLevel [Byte0]: 47
2743 23:50:39.793318 [Byte1]: 47
2744 23:50:39.793371
2745 23:50:39.793432 Set Vref, RX VrefLevel [Byte0]: 48
2746 23:50:39.793486 [Byte1]: 48
2747 23:50:39.793539
2748 23:50:39.793592 Set Vref, RX VrefLevel [Byte0]: 49
2749 23:50:39.793645 [Byte1]: 49
2750 23:50:39.793698
2751 23:50:39.793750 Set Vref, RX VrefLevel [Byte0]: 50
2752 23:50:39.793803 [Byte1]: 50
2753 23:50:39.793855
2754 23:50:39.794103 Set Vref, RX VrefLevel [Byte0]: 51
2755 23:50:39.794189 [Byte1]: 51
2756 23:50:39.794292
2757 23:50:39.794394 Set Vref, RX VrefLevel [Byte0]: 52
2758 23:50:39.794497 [Byte1]: 52
2759 23:50:39.794591
2760 23:50:39.794679 Set Vref, RX VrefLevel [Byte0]: 53
2761 23:50:39.794762 [Byte1]: 53
2762 23:50:39.794845
2763 23:50:39.794927 Set Vref, RX VrefLevel [Byte0]: 54
2764 23:50:39.795009 [Byte1]: 54
2765 23:50:39.795091
2766 23:50:39.795165 Set Vref, RX VrefLevel [Byte0]: 55
2767 23:50:39.795219 [Byte1]: 55
2768 23:50:39.795273
2769 23:50:39.795325 Set Vref, RX VrefLevel [Byte0]: 56
2770 23:50:39.795378 [Byte1]: 56
2771 23:50:39.795431
2772 23:50:39.795483 Set Vref, RX VrefLevel [Byte0]: 57
2773 23:50:39.795536 [Byte1]: 57
2774 23:50:39.795590
2775 23:50:39.795642 Set Vref, RX VrefLevel [Byte0]: 58
2776 23:50:39.795703 [Byte1]: 58
2777 23:50:39.795756
2778 23:50:39.795809 Set Vref, RX VrefLevel [Byte0]: 59
2779 23:50:39.795863 [Byte1]: 59
2780 23:50:39.795916
2781 23:50:39.795968 Set Vref, RX VrefLevel [Byte0]: 60
2782 23:50:39.796021 [Byte1]: 60
2783 23:50:39.796074
2784 23:50:39.796127 Set Vref, RX VrefLevel [Byte0]: 61
2785 23:50:39.796183 [Byte1]: 61
2786 23:50:39.796267
2787 23:50:39.796349 Set Vref, RX VrefLevel [Byte0]: 62
2788 23:50:39.796432 [Byte1]: 62
2789 23:50:39.796513
2790 23:50:39.796616 Set Vref, RX VrefLevel [Byte0]: 63
2791 23:50:39.796687 [Byte1]: 63
2792 23:50:39.796745
2793 23:50:39.796798 Set Vref, RX VrefLevel [Byte0]: 64
2794 23:50:39.796851 [Byte1]: 64
2795 23:50:39.796904
2796 23:50:39.796957 Set Vref, RX VrefLevel [Byte0]: 65
2797 23:50:39.797009 [Byte1]: 65
2798 23:50:39.797062
2799 23:50:39.797115 Set Vref, RX VrefLevel [Byte0]: 66
2800 23:50:39.797168 [Byte1]: 66
2801 23:50:39.797221
2802 23:50:39.797280 Set Vref, RX VrefLevel [Byte0]: 67
2803 23:50:39.797334 [Byte1]: 67
2804 23:50:39.797387
2805 23:50:39.797440 Set Vref, RX VrefLevel [Byte0]: 68
2806 23:50:39.797493 [Byte1]: 68
2807 23:50:39.797545
2808 23:50:39.797598 Set Vref, RX VrefLevel [Byte0]: 69
2809 23:50:39.797651 [Byte1]: 69
2810 23:50:39.797703
2811 23:50:39.797758 Set Vref, RX VrefLevel [Byte0]: 70
2812 23:50:39.797814 [Byte1]: 70
2813 23:50:39.797868
2814 23:50:39.797920 Set Vref, RX VrefLevel [Byte0]: 71
2815 23:50:39.797973 [Byte1]: 71
2816 23:50:39.798025
2817 23:50:39.798077 Final RX Vref Byte 0 = 58 to rank0
2818 23:50:39.798131 Final RX Vref Byte 1 = 50 to rank0
2819 23:50:39.798190 Final RX Vref Byte 0 = 58 to rank1
2820 23:50:39.798244 Final RX Vref Byte 1 = 50 to rank1==
2821 23:50:39.798297 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 23:50:39.798356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 23:50:39.798410 ==
2824 23:50:39.798463 DQS Delay:
2825 23:50:39.798516 DQS0 = 0, DQS1 = 0
2826 23:50:39.798569 DQM Delay:
2827 23:50:39.798622 DQM0 = 122, DQM1 = 109
2828 23:50:39.798675 DQ Delay:
2829 23:50:39.798728 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2830 23:50:39.798781 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2831 23:50:39.798839 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108
2832 23:50:39.798893 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2833 23:50:39.798946
2834 23:50:39.798998
2835 23:50:39.799051 [DQSOSCAuto] RK0, (LSB)MR18= 0x100c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2836 23:50:39.799109 CH0 RK0: MR19=404, MR18=100C
2837 23:50:39.799163 CH0_RK0: MR19=0x404, MR18=0x100C, DQSOSC=403, MR23=63, INC=40, DEC=26
2838 23:50:39.799216
2839 23:50:39.799269 ----->DramcWriteLeveling(PI) begin...
2840 23:50:39.799323 ==
2841 23:50:39.799385 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 23:50:39.799469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 23:50:39.799552 ==
2844 23:50:39.799634 Write leveling (Byte 0): 36 => 36
2845 23:50:39.799716 Write leveling (Byte 1): 29 => 29
2846 23:50:39.799798 DramcWriteLeveling(PI) end<-----
2847 23:50:39.799881
2848 23:50:39.799938 ==
2849 23:50:39.799992 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 23:50:39.800045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 23:50:39.800098 ==
2852 23:50:39.800151 [Gating] SW mode calibration
2853 23:50:39.800205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 23:50:39.800258 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 23:50:39.800311 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2856 23:50:39.800365 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 23:50:39.800431 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 23:50:39.800515 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 23:50:39.800618 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 23:50:39.800673 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 23:50:39.800727 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 23:50:39.800780 0 15 28 | B1->B0 | 3030 3030 | 0 0 | (1 0) (1 0)
2863 23:50:39.800833 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2864 23:50:39.800887 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 23:50:39.800947 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 23:50:39.801001 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 23:50:39.801054 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 23:50:39.801107 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 23:50:39.801161 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2870 23:50:39.801214 1 0 28 | B1->B0 | 3c3c 4342 | 1 1 | (0 0) (0 0)
2871 23:50:39.801267 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 23:50:39.801320 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 23:50:39.801379 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 23:50:39.801436 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 23:50:39.801489 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 23:50:39.801543 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 23:50:39.801596 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 23:50:39.801649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2879 23:50:39.801703 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2880 23:50:39.801952 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:50:39.802033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:50:39.802137 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:50:39.802240 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:50:39.802343 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:50:39.802438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:50:39.802525 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:50:39.802608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:50:39.802691 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:50:39.802774 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:50:39.802857 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:50:39.802939 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:50:39.803022 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:50:39.803094 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:50:39.803148 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2895 23:50:39.803202 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2896 23:50:39.803255 Total UI for P1: 0, mck2ui 16
2897 23:50:39.803309 best dqsien dly found for B1: ( 1, 3, 28)
2898 23:50:39.803363 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 23:50:39.803417 Total UI for P1: 0, mck2ui 16
2900 23:50:39.803472 best dqsien dly found for B0: ( 1, 3, 30)
2901 23:50:39.803525 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2902 23:50:39.803578 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2903 23:50:39.803639
2904 23:50:39.803692 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2905 23:50:39.803746 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2906 23:50:39.803798 [Gating] SW calibration Done
2907 23:50:39.803851 ==
2908 23:50:39.803904 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 23:50:39.803958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 23:50:39.804011 ==
2911 23:50:39.804064 RX Vref Scan: 0
2912 23:50:39.804117
2913 23:50:39.804175 RX Vref 0 -> 0, step: 1
2914 23:50:39.804229
2915 23:50:39.804283 RX Delay -40 -> 252, step: 8
2916 23:50:39.804336 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2917 23:50:39.804389 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2918 23:50:39.804442 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2919 23:50:39.804496 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2920 23:50:39.804555 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2921 23:50:39.804650 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2922 23:50:39.804706 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2923 23:50:39.804759 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2924 23:50:39.804812 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2925 23:50:39.804865 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 23:50:39.804918 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2927 23:50:39.804971 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2928 23:50:39.805024 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2929 23:50:39.805077 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2930 23:50:39.805130 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 23:50:39.805191 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2932 23:50:39.805244 ==
2933 23:50:39.805297 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 23:50:39.805350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 23:50:39.805404 ==
2936 23:50:39.805457 DQS Delay:
2937 23:50:39.805510 DQS0 = 0, DQS1 = 0
2938 23:50:40.051117 DQM Delay:
2939 23:50:40.051653 DQM0 = 120, DQM1 = 108
2940 23:50:40.052019 DQ Delay:
2941 23:50:40.052353 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2942 23:50:40.052712 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2943 23:50:40.053033 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2944 23:50:40.053345 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =111
2945 23:50:40.053654
2946 23:50:40.053954
2947 23:50:40.054305 ==
2948 23:50:40.054621 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 23:50:40.054928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 23:50:40.055230 ==
2951 23:50:40.055527
2952 23:50:40.055822
2953 23:50:40.056115 TX Vref Scan disable
2954 23:50:40.056415 == TX Byte 0 ==
2955 23:50:40.056733 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2956 23:50:40.057033 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2957 23:50:40.057331 == TX Byte 1 ==
2958 23:50:40.057629 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2959 23:50:40.057994 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2960 23:50:40.058299 ==
2961 23:50:40.058597 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 23:50:40.058892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 23:50:40.059190 ==
2964 23:50:40.059482 TX Vref=22, minBit 0, minWin=24, winSum=412
2965 23:50:40.059787 TX Vref=24, minBit 1, minWin=26, winSum=424
2966 23:50:40.060084 TX Vref=26, minBit 5, minWin=25, winSum=427
2967 23:50:40.060379 TX Vref=28, minBit 3, minWin=25, winSum=430
2968 23:50:40.060697 TX Vref=30, minBit 3, minWin=25, winSum=430
2969 23:50:40.061041 TX Vref=32, minBit 0, minWin=26, winSum=433
2970 23:50:40.061345 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 32
2971 23:50:40.061647
2972 23:50:40.061941 Final TX Range 1 Vref 32
2973 23:50:40.062239
2974 23:50:40.062532 ==
2975 23:50:40.062824 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 23:50:40.063117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 23:50:40.063411 ==
2978 23:50:40.063706
2979 23:50:40.064000
2980 23:50:40.064293 TX Vref Scan disable
2981 23:50:40.064655 == TX Byte 0 ==
2982 23:50:40.064956 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2983 23:50:40.065254 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2984 23:50:40.065549 == TX Byte 1 ==
2985 23:50:40.065843 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2986 23:50:40.066139 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2987 23:50:40.066432
2988 23:50:40.066726 [DATLAT]
2989 23:50:40.067020 Freq=1200, CH0 RK1
2990 23:50:40.067318
2991 23:50:40.067638 DATLAT Default: 0xd
2992 23:50:40.067968 0, 0xFFFF, sum = 0
2993 23:50:40.068287 1, 0xFFFF, sum = 0
2994 23:50:40.068609 2, 0xFFFF, sum = 0
2995 23:50:40.068915 3, 0xFFFF, sum = 0
2996 23:50:40.069216 4, 0xFFFF, sum = 0
2997 23:50:40.069513 5, 0xFFFF, sum = 0
2998 23:50:40.069813 6, 0xFFFF, sum = 0
2999 23:50:40.070210 7, 0xFFFF, sum = 0
3000 23:50:40.070544 8, 0xFFFF, sum = 0
3001 23:50:40.070878 9, 0xFFFF, sum = 0
3002 23:50:40.071332 10, 0xFFFF, sum = 0
3003 23:50:40.071943 11, 0xFFFF, sum = 0
3004 23:50:40.072588 12, 0x0, sum = 1
3005 23:50:40.073159 13, 0x0, sum = 2
3006 23:50:40.073659 14, 0x0, sum = 3
3007 23:50:40.074151 15, 0x0, sum = 4
3008 23:50:40.074479 best_step = 13
3009 23:50:40.074780
3010 23:50:40.075075 ==
3011 23:50:40.075375 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 23:50:40.075672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 23:50:40.075883 ==
3014 23:50:40.076091 RX Vref Scan: 0
3015 23:50:40.076303
3016 23:50:40.076860 RX Vref 0 -> 0, step: 1
3017 23:50:40.077106
3018 23:50:40.077361 RX Delay -21 -> 252, step: 4
3019 23:50:40.077582 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3020 23:50:40.077796 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3021 23:50:40.078009 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3022 23:50:40.078220 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3023 23:50:40.078430 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3024 23:50:40.078639 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3025 23:50:40.078850 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3026 23:50:40.079059 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3027 23:50:40.079269 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3028 23:50:40.079483 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3029 23:50:40.079695 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3030 23:50:40.079905 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3031 23:50:40.080115 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3032 23:50:40.080326 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3033 23:50:40.080535 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3034 23:50:40.080773 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3035 23:50:40.080936 ==
3036 23:50:40.081092 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 23:50:40.081248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 23:50:40.081417 ==
3039 23:50:40.081577 DQS Delay:
3040 23:50:40.081733 DQS0 = 0, DQS1 = 0
3041 23:50:40.081887 DQM Delay:
3042 23:50:40.082042 DQM0 = 119, DQM1 = 107
3043 23:50:40.082196 DQ Delay:
3044 23:50:40.082348 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3045 23:50:40.082502 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3046 23:50:40.082656 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3047 23:50:40.082810 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3048 23:50:40.082965
3049 23:50:40.083119
3050 23:50:40.083271 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3051 23:50:40.083428 CH0 RK1: MR19=403, MR18=10F7
3052 23:50:40.083581 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3053 23:50:40.083736 [RxdqsGatingPostProcess] freq 1200
3054 23:50:40.083890 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 23:50:40.084069 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 23:50:40.084226 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 23:50:40.084380 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 23:50:40.084534 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 23:50:40.084712 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 23:50:40.084868 best DQS1 dly(2T, 0.5T) = (0, 11)
3061 23:50:40.085028 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 23:50:40.085187 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3063 23:50:40.085347 Pre-setting of DQS Precalculation
3064 23:50:40.085506 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 23:50:40.085664 ==
3066 23:50:40.085789 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 23:50:40.085916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 23:50:40.086044 ==
3069 23:50:40.086172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 23:50:40.086300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3071 23:50:40.086427 [CA 0] Center 38 (8~68) winsize 61
3072 23:50:40.086554 [CA 1] Center 37 (7~68) winsize 62
3073 23:50:40.086680 [CA 2] Center 35 (5~65) winsize 61
3074 23:50:40.086806 [CA 3] Center 34 (4~65) winsize 62
3075 23:50:40.086931 [CA 4] Center 34 (4~65) winsize 62
3076 23:50:40.087057 [CA 5] Center 33 (3~64) winsize 62
3077 23:50:40.087181
3078 23:50:40.087307 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3079 23:50:40.087433
3080 23:50:40.087575 [CATrainingPosCal] consider 1 rank data
3081 23:50:40.087705 u2DelayCellTimex100 = 270/100 ps
3082 23:50:40.087831 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3083 23:50:40.087956 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 23:50:40.088082 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3085 23:50:40.088209 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3086 23:50:40.088335 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3087 23:50:40.088459 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 23:50:40.088603
3089 23:50:40.088733 CA PerBit enable=1, Macro0, CA PI delay=33
3090 23:50:40.088860
3091 23:50:40.088984 [CBTSetCACLKResult] CA Dly = 33
3092 23:50:40.089108 CS Dly: 5 (0~36)
3093 23:50:40.089235 ==
3094 23:50:40.089361 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 23:50:40.089489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 23:50:40.089616 ==
3097 23:50:40.089742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 23:50:40.089869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3099 23:50:40.089997 [CA 0] Center 38 (8~68) winsize 61
3100 23:50:40.090123 [CA 1] Center 38 (7~69) winsize 63
3101 23:50:40.090249 [CA 2] Center 35 (5~66) winsize 62
3102 23:50:40.090375 [CA 3] Center 35 (5~65) winsize 61
3103 23:50:40.090500 [CA 4] Center 35 (5~65) winsize 61
3104 23:50:40.090640 [CA 5] Center 34 (4~64) winsize 61
3105 23:50:40.090751
3106 23:50:40.090855 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 23:50:40.090959
3108 23:50:40.091062 [CATrainingPosCal] consider 2 rank data
3109 23:50:40.091167 u2DelayCellTimex100 = 270/100 ps
3110 23:50:40.091271 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3111 23:50:40.091376 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3112 23:50:40.091480 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3113 23:50:40.091584 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3114 23:50:40.091689 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 23:50:40.091792 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3116 23:50:40.091896
3117 23:50:40.091998 CA PerBit enable=1, Macro0, CA PI delay=34
3118 23:50:40.092103
3119 23:50:40.092207 [CBTSetCACLKResult] CA Dly = 34
3120 23:50:40.092311 CS Dly: 6 (0~39)
3121 23:50:40.092415
3122 23:50:40.092518 ----->DramcWriteLeveling(PI) begin...
3123 23:50:40.092641 ==
3124 23:50:40.092746 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 23:50:40.092876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 23:50:40.092984 ==
3127 23:50:40.093090 Write leveling (Byte 0): 24 => 24
3128 23:50:40.093195 Write leveling (Byte 1): 28 => 28
3129 23:50:40.093302 DramcWriteLeveling(PI) end<-----
3130 23:50:40.093407
3131 23:50:40.093510 ==
3132 23:50:40.093615 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 23:50:40.093720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 23:50:40.093829 ==
3135 23:50:40.093941 [Gating] SW mode calibration
3136 23:50:40.094284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 23:50:40.094403 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 23:50:40.094513 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 23:50:40.094621 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 23:50:40.094730 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 23:50:40.094857 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 23:50:40.094966 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 23:50:40.095072 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3144 23:50:40.095177 0 15 24 | B1->B0 | 2727 2525 | 1 0 | (1 0) (0 0)
3145 23:50:40.095281 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3146 23:50:40.095386 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 23:50:40.095489 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 23:50:40.095594 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 23:50:40.095700 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 23:50:40.095790 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 23:50:40.095880 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3152 23:50:40.095969 1 0 24 | B1->B0 | 4141 4444 | 0 0 | (0 0) (1 1)
3153 23:50:40.096058 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 23:50:40.096146 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 23:50:40.096237 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 23:50:40.096326 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 23:50:40.096415 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 23:50:40.096504 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 23:50:40.096613 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3160 23:50:40.096704 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3161 23:50:40.096793 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3162 23:50:40.096881 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:50:40.096971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:50:40.097060 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:50:40.097149 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:50:40.097238 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:50:40.097341 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:50:40.097432 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:50:40.097522 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:50:40.097611 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:50:40.097700 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:50:40.097789 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:50:40.097878 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:50:40.097967 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:50:40.098056 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3176 23:50:40.098145 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 23:50:40.098234 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 23:50:40.098324 Total UI for P1: 0, mck2ui 16
3179 23:50:40.098415 best dqsien dly found for B0: ( 1, 3, 22)
3180 23:50:40.098505 Total UI for P1: 0, mck2ui 16
3181 23:50:40.098595 best dqsien dly found for B1: ( 1, 3, 24)
3182 23:50:40.098685 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3183 23:50:40.098775 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3184 23:50:40.098864
3185 23:50:40.098952 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3186 23:50:40.099041 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3187 23:50:40.099131 [Gating] SW calibration Done
3188 23:50:40.099220 ==
3189 23:50:40.099310 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 23:50:40.099399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 23:50:40.099490 ==
3192 23:50:40.099594 RX Vref Scan: 0
3193 23:50:40.099684
3194 23:50:40.099771 RX Vref 0 -> 0, step: 1
3195 23:50:40.099860
3196 23:50:40.099949 RX Delay -40 -> 252, step: 8
3197 23:50:40.100039 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3198 23:50:40.100129 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3199 23:50:40.100219 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3200 23:50:40.100309 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3201 23:50:40.100399 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3202 23:50:40.100517 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3203 23:50:40.100632 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3204 23:50:40.100725 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3205 23:50:40.100803 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3206 23:50:40.100881 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3207 23:50:40.100959 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3208 23:50:40.101036 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3209 23:50:40.101114 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3210 23:50:40.101192 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3211 23:50:40.101270 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3212 23:50:40.101347 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3213 23:50:40.101425 ==
3214 23:50:40.101504 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 23:50:40.101581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 23:50:40.101660 ==
3217 23:50:40.101738 DQS Delay:
3218 23:50:40.101816 DQS0 = 0, DQS1 = 0
3219 23:50:40.101895 DQM Delay:
3220 23:50:40.101972 DQM0 = 119, DQM1 = 112
3221 23:50:40.102050 DQ Delay:
3222 23:50:40.102128 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3223 23:50:40.102206 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3224 23:50:40.102284 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3225 23:50:40.102362 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3226 23:50:40.102440
3227 23:50:40.102516
3228 23:50:40.102593 ==
3229 23:50:40.102671 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 23:50:40.102749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 23:50:40.102827 ==
3232 23:50:40.102905
3233 23:50:40.102982
3234 23:50:40.103058 TX Vref Scan disable
3235 23:50:40.103135 == TX Byte 0 ==
3236 23:50:40.103212 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3237 23:50:40.103290 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3238 23:50:40.103368 == TX Byte 1 ==
3239 23:50:40.103445 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3240 23:50:40.103523 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3241 23:50:40.103600 ==
3242 23:50:40.103888 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 23:50:40.103975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 23:50:40.104082 ==
3245 23:50:40.104179 TX Vref=22, minBit 1, minWin=24, winSum=404
3246 23:50:40.104260 TX Vref=24, minBit 10, minWin=24, winSum=410
3247 23:50:40.104340 TX Vref=26, minBit 10, minWin=24, winSum=413
3248 23:50:40.104419 TX Vref=28, minBit 8, minWin=25, winSum=418
3249 23:50:40.104498 TX Vref=30, minBit 10, minWin=25, winSum=424
3250 23:50:40.104588 TX Vref=32, minBit 11, minWin=25, winSum=422
3251 23:50:40.104670 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 30
3252 23:50:40.104748
3253 23:50:40.104827 Final TX Range 1 Vref 30
3254 23:50:40.104904
3255 23:50:40.104981 ==
3256 23:50:40.105058 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 23:50:40.105135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 23:50:40.105214 ==
3259 23:50:40.105292
3260 23:50:40.105369
3261 23:50:40.105446 TX Vref Scan disable
3262 23:50:40.105523 == TX Byte 0 ==
3263 23:50:40.105601 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3264 23:50:40.105686 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3265 23:50:40.105754 == TX Byte 1 ==
3266 23:50:40.105822 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 23:50:40.105892 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 23:50:40.105961
3269 23:50:40.106030 [DATLAT]
3270 23:50:40.106098 Freq=1200, CH1 RK0
3271 23:50:40.106167
3272 23:50:40.106236 DATLAT Default: 0xd
3273 23:50:40.106305 0, 0xFFFF, sum = 0
3274 23:50:40.106375 1, 0xFFFF, sum = 0
3275 23:50:40.106446 2, 0xFFFF, sum = 0
3276 23:50:40.106516 3, 0xFFFF, sum = 0
3277 23:50:40.106586 4, 0xFFFF, sum = 0
3278 23:50:40.106656 5, 0xFFFF, sum = 0
3279 23:50:40.106727 6, 0xFFFF, sum = 0
3280 23:50:40.106797 7, 0xFFFF, sum = 0
3281 23:50:40.106866 8, 0xFFFF, sum = 0
3282 23:50:40.106936 9, 0xFFFF, sum = 0
3283 23:50:40.107005 10, 0xFFFF, sum = 0
3284 23:50:40.107076 11, 0xFFFF, sum = 0
3285 23:50:40.107145 12, 0x0, sum = 1
3286 23:50:40.107215 13, 0x0, sum = 2
3287 23:50:40.107285 14, 0x0, sum = 3
3288 23:50:40.107355 15, 0x0, sum = 4
3289 23:50:40.107425 best_step = 13
3290 23:50:40.107494
3291 23:50:40.107562 ==
3292 23:50:40.107635 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 23:50:40.107709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 23:50:40.107778 ==
3295 23:50:40.107845 RX Vref Scan: 1
3296 23:50:40.107912
3297 23:50:40.107977 Set Vref Range= 32 -> 127
3298 23:50:40.108044
3299 23:50:40.108110 RX Vref 32 -> 127, step: 1
3300 23:50:40.108177
3301 23:50:40.108243 RX Delay -13 -> 252, step: 4
3302 23:50:40.108309
3303 23:50:40.108375 Set Vref, RX VrefLevel [Byte0]: 32
3304 23:50:40.108442 [Byte1]: 32
3305 23:50:40.108509
3306 23:50:40.108586 Set Vref, RX VrefLevel [Byte0]: 33
3307 23:50:40.108653 [Byte1]: 33
3308 23:50:40.108720
3309 23:50:40.108786 Set Vref, RX VrefLevel [Byte0]: 34
3310 23:50:40.108852 [Byte1]: 34
3311 23:50:40.108919
3312 23:50:40.108985 Set Vref, RX VrefLevel [Byte0]: 35
3313 23:50:40.109052 [Byte1]: 35
3314 23:50:40.109118
3315 23:50:40.109184 Set Vref, RX VrefLevel [Byte0]: 36
3316 23:50:40.109251 [Byte1]: 36
3317 23:50:40.109317
3318 23:50:40.109383 Set Vref, RX VrefLevel [Byte0]: 37
3319 23:50:40.109450 [Byte1]: 37
3320 23:50:40.109516
3321 23:50:40.109582 Set Vref, RX VrefLevel [Byte0]: 38
3322 23:50:40.109648 [Byte1]: 38
3323 23:50:40.109714
3324 23:50:40.109780 Set Vref, RX VrefLevel [Byte0]: 39
3325 23:50:40.109854 [Byte1]: 39
3326 23:50:40.109944
3327 23:50:40.110014 Set Vref, RX VrefLevel [Byte0]: 40
3328 23:50:40.110081 [Byte1]: 40
3329 23:50:40.110148
3330 23:50:40.110214 Set Vref, RX VrefLevel [Byte0]: 41
3331 23:50:40.110282 [Byte1]: 41
3332 23:50:40.110348
3333 23:50:40.110414 Set Vref, RX VrefLevel [Byte0]: 42
3334 23:50:40.110480 [Byte1]: 42
3335 23:50:40.110547
3336 23:50:40.110612 Set Vref, RX VrefLevel [Byte0]: 43
3337 23:50:40.110689 [Byte1]: 43
3338 23:50:40.110750
3339 23:50:40.110817 Set Vref, RX VrefLevel [Byte0]: 44
3340 23:50:40.110877 [Byte1]: 44
3341 23:50:40.110937
3342 23:50:40.110997 Set Vref, RX VrefLevel [Byte0]: 45
3343 23:50:40.111057 [Byte1]: 45
3344 23:50:40.111117
3345 23:50:40.111176 Set Vref, RX VrefLevel [Byte0]: 46
3346 23:50:40.111235 [Byte1]: 46
3347 23:50:40.111295
3348 23:50:40.111355 Set Vref, RX VrefLevel [Byte0]: 47
3349 23:50:40.111415 [Byte1]: 47
3350 23:50:40.111474
3351 23:50:40.111534 Set Vref, RX VrefLevel [Byte0]: 48
3352 23:50:40.111594 [Byte1]: 48
3353 23:50:40.111654
3354 23:50:40.111713 Set Vref, RX VrefLevel [Byte0]: 49
3355 23:50:40.111772 [Byte1]: 49
3356 23:50:40.111832
3357 23:50:40.111891 Set Vref, RX VrefLevel [Byte0]: 50
3358 23:50:40.111951 [Byte1]: 50
3359 23:50:40.112011
3360 23:50:40.112069 Set Vref, RX VrefLevel [Byte0]: 51
3361 23:50:40.112130 [Byte1]: 51
3362 23:50:40.112189
3363 23:50:40.112247 Set Vref, RX VrefLevel [Byte0]: 52
3364 23:50:40.112306 [Byte1]: 52
3365 23:50:40.112366
3366 23:50:40.112425 Set Vref, RX VrefLevel [Byte0]: 53
3367 23:50:40.112484 [Byte1]: 53
3368 23:50:40.112544
3369 23:50:40.112613 Set Vref, RX VrefLevel [Byte0]: 54
3370 23:50:40.112673 [Byte1]: 54
3371 23:50:40.112732
3372 23:50:40.112792 Set Vref, RX VrefLevel [Byte0]: 55
3373 23:50:40.112852 [Byte1]: 55
3374 23:50:40.112912
3375 23:50:40.112972 Set Vref, RX VrefLevel [Byte0]: 56
3376 23:50:40.113031 [Byte1]: 56
3377 23:50:40.113091
3378 23:50:40.113150 Set Vref, RX VrefLevel [Byte0]: 57
3379 23:50:40.113211 [Byte1]: 57
3380 23:50:40.113271
3381 23:50:40.113330 Set Vref, RX VrefLevel [Byte0]: 58
3382 23:50:40.113390 [Byte1]: 58
3383 23:50:40.113450
3384 23:50:40.113509 Set Vref, RX VrefLevel [Byte0]: 59
3385 23:50:40.113569 [Byte1]: 59
3386 23:50:40.113628
3387 23:50:40.113686 Set Vref, RX VrefLevel [Byte0]: 60
3388 23:50:40.113745 [Byte1]: 60
3389 23:50:40.113804
3390 23:50:40.113863 Set Vref, RX VrefLevel [Byte0]: 61
3391 23:50:40.113923 [Byte1]: 61
3392 23:50:40.113992
3393 23:50:40.114053 Set Vref, RX VrefLevel [Byte0]: 62
3394 23:50:40.114113 [Byte1]: 62
3395 23:50:40.114172
3396 23:50:40.114232 Set Vref, RX VrefLevel [Byte0]: 63
3397 23:50:40.114291 [Byte1]: 63
3398 23:50:40.114351
3399 23:50:40.114411 Set Vref, RX VrefLevel [Byte0]: 64
3400 23:50:40.114471 [Byte1]: 64
3401 23:50:40.114531
3402 23:50:40.114589 Set Vref, RX VrefLevel [Byte0]: 65
3403 23:50:40.114649 [Byte1]: 65
3404 23:50:40.114710
3405 23:50:40.114768 Set Vref, RX VrefLevel [Byte0]: 66
3406 23:50:40.114828 [Byte1]: 66
3407 23:50:40.114887
3408 23:50:40.114947 Set Vref, RX VrefLevel [Byte0]: 67
3409 23:50:40.115208 [Byte1]: 67
3410 23:50:40.115278
3411 23:50:40.115339 Set Vref, RX VrefLevel [Byte0]: 68
3412 23:50:40.115399 [Byte1]: 68
3413 23:50:40.115459
3414 23:50:40.115518 Final RX Vref Byte 0 = 51 to rank0
3415 23:50:40.115579 Final RX Vref Byte 1 = 57 to rank0
3416 23:50:40.115650 Final RX Vref Byte 0 = 51 to rank1
3417 23:50:40.115705 Final RX Vref Byte 1 = 57 to rank1==
3418 23:50:40.115760 Dram Type= 6, Freq= 0, CH_1, rank 0
3419 23:50:40.115815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 23:50:40.115870 ==
3421 23:50:40.115925 DQS Delay:
3422 23:50:40.115980 DQS0 = 0, DQS1 = 0
3423 23:50:40.116034 DQM Delay:
3424 23:50:40.116089 DQM0 = 119, DQM1 = 113
3425 23:50:40.116143 DQ Delay:
3426 23:50:40.116198 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3427 23:50:40.116252 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3428 23:50:40.116306 DQ8 =102, DQ9 =100, DQ10 =116, DQ11 =108
3429 23:50:40.116361 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =120
3430 23:50:40.116415
3431 23:50:40.116469
3432 23:50:40.116523 [DQSOSCAuto] RK0, (LSB)MR18= 0x71a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3433 23:50:40.116594 CH1 RK0: MR19=404, MR18=71A
3434 23:50:40.116651 CH1_RK0: MR19=0x404, MR18=0x71A, DQSOSC=400, MR23=63, INC=40, DEC=27
3435 23:50:40.116706
3436 23:50:40.116761 ----->DramcWriteLeveling(PI) begin...
3437 23:50:40.116816 ==
3438 23:50:40.116871 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 23:50:40.116926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 23:50:40.116981 ==
3441 23:50:40.117036 Write leveling (Byte 0): 25 => 25
3442 23:50:40.117090 Write leveling (Byte 1): 28 => 28
3443 23:50:40.117145 DramcWriteLeveling(PI) end<-----
3444 23:50:40.117199
3445 23:50:40.117252 ==
3446 23:50:40.117306 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 23:50:40.117361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 23:50:40.117415 ==
3449 23:50:40.117469 [Gating] SW mode calibration
3450 23:50:40.117524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3451 23:50:40.117585 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3452 23:50:40.117641 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 23:50:40.117696 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 23:50:40.117750 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 23:50:40.117805 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 23:50:40.117860 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 23:50:40.117915 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 23:50:40.117969 0 15 24 | B1->B0 | 2a2a 3434 | 1 1 | (1 0) (1 0)
3459 23:50:40.118024 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3460 23:50:40.118080 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 23:50:40.118135 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 23:50:40.118189 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 23:50:40.118244 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 23:50:40.118298 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 23:50:40.118352 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 23:50:40.118407 1 0 24 | B1->B0 | 3c3c 2e2e | 1 0 | (0 0) (1 1)
3467 23:50:40.118462 1 0 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
3468 23:50:40.118516 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 23:50:40.118570 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 23:50:40.118625 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 23:50:40.118679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 23:50:40.118733 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 23:50:40.118787 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 23:50:40.118842 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3475 23:50:40.118896 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3476 23:50:40.118950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 23:50:40.119004 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 23:50:40.119058 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 23:50:40.119113 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 23:50:40.119167 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 23:50:40.119222 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 23:50:40.119276 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 23:50:40.119331 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 23:50:40.119386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:50:40.119440 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:50:40.119495 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:50:40.119549 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:50:40.119604 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:50:40.119658 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:50:40.119713 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 23:50:40.119768 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3492 23:50:40.119822 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 23:50:40.119877 Total UI for P1: 0, mck2ui 16
3494 23:50:40.119932 best dqsien dly found for B0: ( 1, 3, 26)
3495 23:50:40.119987 Total UI for P1: 0, mck2ui 16
3496 23:50:40.120041 best dqsien dly found for B1: ( 1, 3, 26)
3497 23:50:40.120095 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3498 23:50:40.120149 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3499 23:50:40.120204
3500 23:50:40.120257 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3501 23:50:40.120312 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3502 23:50:40.120366 [Gating] SW calibration Done
3503 23:50:40.120421 ==
3504 23:50:40.120475 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 23:50:40.120530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 23:50:40.120593 ==
3507 23:50:40.120684 RX Vref Scan: 0
3508 23:50:40.120737
3509 23:50:40.120789 RX Vref 0 -> 0, step: 1
3510 23:50:40.120841
3511 23:50:40.120893 RX Delay -40 -> 252, step: 8
3512 23:50:40.120944 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3513 23:50:40.120997 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3514 23:50:40.121049 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3515 23:50:40.121100 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3516 23:50:40.121343 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3517 23:50:40.121401 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3518 23:50:40.121454 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3519 23:50:40.121507 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3520 23:50:40.121559 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3521 23:50:40.121612 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3522 23:50:40.121664 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3523 23:50:40.121717 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3524 23:50:40.121769 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3525 23:50:40.121821 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3526 23:50:40.121873 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3527 23:50:40.121926 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3528 23:50:40.121978 ==
3529 23:50:40.122030 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 23:50:40.122083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 23:50:40.122136 ==
3532 23:50:40.122187 DQS Delay:
3533 23:50:40.122239 DQS0 = 0, DQS1 = 0
3534 23:50:40.122291 DQM Delay:
3535 23:50:40.122342 DQM0 = 119, DQM1 = 112
3536 23:50:40.122394 DQ Delay:
3537 23:50:40.122446 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3538 23:50:40.122498 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3539 23:50:40.122551 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3540 23:50:40.122603 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3541 23:50:40.122655
3542 23:50:40.122706
3543 23:50:40.122757 ==
3544 23:50:40.122808 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 23:50:40.122860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 23:50:40.122913 ==
3547 23:50:40.122965
3548 23:50:40.123016
3549 23:50:40.123068 TX Vref Scan disable
3550 23:50:40.123119 == TX Byte 0 ==
3551 23:50:40.123171 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3552 23:50:40.123224 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3553 23:50:40.123276 == TX Byte 1 ==
3554 23:50:40.123327 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3555 23:50:40.123379 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3556 23:50:40.123431 ==
3557 23:50:40.123483 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 23:50:40.123535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 23:50:40.123587 ==
3560 23:50:40.123639 TX Vref=22, minBit 3, minWin=25, winSum=416
3561 23:50:40.123692 TX Vref=24, minBit 8, minWin=25, winSum=420
3562 23:50:40.123745 TX Vref=26, minBit 9, minWin=25, winSum=423
3563 23:50:40.123802 TX Vref=28, minBit 3, minWin=25, winSum=428
3564 23:50:40.123864 TX Vref=30, minBit 7, minWin=26, winSum=429
3565 23:50:40.123926 TX Vref=32, minBit 0, minWin=26, winSum=426
3566 23:50:40.124011 [TxChooseVref] Worse bit 7, Min win 26, Win sum 429, Final Vref 30
3567 23:50:40.124064
3568 23:50:40.124117 Final TX Range 1 Vref 30
3569 23:50:40.124169
3570 23:50:40.124221 ==
3571 23:50:40.124273 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 23:50:40.124324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 23:50:40.124377 ==
3574 23:50:40.124429
3575 23:50:40.124480
3576 23:50:40.124531 TX Vref Scan disable
3577 23:50:40.124631 == TX Byte 0 ==
3578 23:50:40.124684 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3579 23:50:40.124737 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3580 23:50:40.124789 == TX Byte 1 ==
3581 23:50:40.124841 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3582 23:50:40.124893 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3583 23:50:40.124944
3584 23:50:40.124996 [DATLAT]
3585 23:50:40.125047 Freq=1200, CH1 RK1
3586 23:50:40.125100
3587 23:50:40.125151 DATLAT Default: 0xd
3588 23:50:40.125202 0, 0xFFFF, sum = 0
3589 23:50:40.125256 1, 0xFFFF, sum = 0
3590 23:50:40.125309 2, 0xFFFF, sum = 0
3591 23:50:40.125362 3, 0xFFFF, sum = 0
3592 23:50:40.125415 4, 0xFFFF, sum = 0
3593 23:50:40.125467 5, 0xFFFF, sum = 0
3594 23:50:40.125519 6, 0xFFFF, sum = 0
3595 23:50:40.125571 7, 0xFFFF, sum = 0
3596 23:50:40.125623 8, 0xFFFF, sum = 0
3597 23:50:40.125675 9, 0xFFFF, sum = 0
3598 23:50:40.125728 10, 0xFFFF, sum = 0
3599 23:50:40.125787 11, 0xFFFF, sum = 0
3600 23:50:40.125872 12, 0x0, sum = 1
3601 23:50:40.125925 13, 0x0, sum = 2
3602 23:50:40.125977 14, 0x0, sum = 3
3603 23:50:40.126029 15, 0x0, sum = 4
3604 23:50:40.126082 best_step = 13
3605 23:50:40.126133
3606 23:50:40.126184 ==
3607 23:50:40.126236 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 23:50:40.126288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 23:50:40.126341 ==
3610 23:50:40.126393 RX Vref Scan: 0
3611 23:50:40.126445
3612 23:50:40.126496 RX Vref 0 -> 0, step: 1
3613 23:50:40.126548
3614 23:50:40.126600 RX Delay -13 -> 252, step: 4
3615 23:50:40.126651 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3616 23:50:40.126703 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3617 23:50:40.126756 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3618 23:50:40.126808 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3619 23:50:40.126861 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3620 23:50:40.126913 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3621 23:50:40.126965 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3622 23:50:40.127017 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3623 23:50:40.127069 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3624 23:50:40.127126 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3625 23:50:40.127180 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3626 23:50:40.127232 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3627 23:50:40.127283 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3628 23:50:40.127335 iDelay=195, Bit 13, Center 120 (55 ~ 186) 132
3629 23:50:40.127386 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3630 23:50:40.127438 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3631 23:50:40.127489 ==
3632 23:50:40.127545 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 23:50:40.127598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 23:50:40.127650 ==
3635 23:50:40.127702 DQS Delay:
3636 23:50:40.127753 DQS0 = 0, DQS1 = 0
3637 23:50:40.127812 DQM Delay:
3638 23:50:40.127871 DQM0 = 119, DQM1 = 113
3639 23:50:40.127924 DQ Delay:
3640 23:50:40.127976 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3641 23:50:40.128027 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3642 23:50:40.128080 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3643 23:50:40.128131 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =124
3644 23:50:40.128183
3645 23:50:40.128234
3646 23:50:40.128285 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3647 23:50:40.128338 CH1 RK1: MR19=403, MR18=BF0
3648 23:50:40.128391 CH1_RK1: MR19=0x403, MR18=0xBF0, DQSOSC=405, MR23=63, INC=39, DEC=26
3649 23:50:40.128443 [RxdqsGatingPostProcess] freq 1200
3650 23:50:40.128494 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3651 23:50:40.128554 best DQS0 dly(2T, 0.5T) = (0, 11)
3652 23:50:40.128645 best DQS1 dly(2T, 0.5T) = (0, 11)
3653 23:50:40.128697 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3654 23:50:40.128940 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3655 23:50:40.128999 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 23:50:40.129052 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 23:50:40.129104 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 23:50:40.129156 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 23:50:40.129208 Pre-setting of DQS Precalculation
3660 23:50:40.129260 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3661 23:50:40.129313 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3662 23:50:40.129366 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3663 23:50:40.129419
3664 23:50:40.129470
3665 23:50:40.129521 [Calibration Summary] 2400 Mbps
3666 23:50:40.129573 CH 0, Rank 0
3667 23:50:40.129625 SW Impedance : PASS
3668 23:50:40.129677 DUTY Scan : NO K
3669 23:50:40.129729 ZQ Calibration : PASS
3670 23:50:40.129784 Jitter Meter : NO K
3671 23:50:40.129848 CBT Training : PASS
3672 23:50:40.129902 Write leveling : PASS
3673 23:50:40.129954 RX DQS gating : PASS
3674 23:50:40.130007 RX DQ/DQS(RDDQC) : PASS
3675 23:50:40.130058 TX DQ/DQS : PASS
3676 23:50:40.130110 RX DATLAT : PASS
3677 23:50:40.130162 RX DQ/DQS(Engine): PASS
3678 23:50:40.130214 TX OE : NO K
3679 23:50:40.130266 All Pass.
3680 23:50:40.130318
3681 23:50:40.130370 CH 0, Rank 1
3682 23:50:40.130421 SW Impedance : PASS
3683 23:50:40.130478 DUTY Scan : NO K
3684 23:50:40.130532 ZQ Calibration : PASS
3685 23:50:40.130617 Jitter Meter : NO K
3686 23:50:40.130669 CBT Training : PASS
3687 23:50:40.130720 Write leveling : PASS
3688 23:50:40.130772 RX DQS gating : PASS
3689 23:50:40.130824 RX DQ/DQS(RDDQC) : PASS
3690 23:50:40.130876 TX DQ/DQS : PASS
3691 23:50:40.130927 RX DATLAT : PASS
3692 23:50:40.130978 RX DQ/DQS(Engine): PASS
3693 23:50:40.131030 TX OE : NO K
3694 23:50:40.131083 All Pass.
3695 23:50:40.131135
3696 23:50:40.131186 CH 1, Rank 0
3697 23:50:40.131238 SW Impedance : PASS
3698 23:50:40.131290 DUTY Scan : NO K
3699 23:50:40.131342 ZQ Calibration : PASS
3700 23:50:40.131393 Jitter Meter : NO K
3701 23:50:40.131445 CBT Training : PASS
3702 23:50:40.131496 Write leveling : PASS
3703 23:50:40.131548 RX DQS gating : PASS
3704 23:50:40.131600 RX DQ/DQS(RDDQC) : PASS
3705 23:50:40.131651 TX DQ/DQS : PASS
3706 23:50:40.131704 RX DATLAT : PASS
3707 23:50:40.131779 RX DQ/DQS(Engine): PASS
3708 23:50:40.131837 TX OE : NO K
3709 23:50:40.131890 All Pass.
3710 23:50:40.131942
3711 23:50:40.131994 CH 1, Rank 1
3712 23:50:40.132045 SW Impedance : PASS
3713 23:50:40.132097 DUTY Scan : NO K
3714 23:50:40.132148 ZQ Calibration : PASS
3715 23:50:40.132200 Jitter Meter : NO K
3716 23:50:40.132251 CBT Training : PASS
3717 23:50:40.132302 Write leveling : PASS
3718 23:50:40.132354 RX DQS gating : PASS
3719 23:50:40.132406 RX DQ/DQS(RDDQC) : PASS
3720 23:50:40.132458 TX DQ/DQS : PASS
3721 23:50:40.132510 RX DATLAT : PASS
3722 23:50:40.132602 RX DQ/DQS(Engine): PASS
3723 23:50:40.132702 TX OE : NO K
3724 23:50:40.132754 All Pass.
3725 23:50:40.132806
3726 23:50:40.132857 DramC Write-DBI off
3727 23:50:40.132908 PER_BANK_REFRESH: Hybrid Mode
3728 23:50:40.132960 TX_TRACKING: ON
3729 23:50:40.133012 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3730 23:50:40.133066 [FAST_K] Save calibration result to emmc
3731 23:50:40.133118 dramc_set_vcore_voltage set vcore to 650000
3732 23:50:40.133169 Read voltage for 600, 5
3733 23:50:40.133221 Vio18 = 0
3734 23:50:40.133273 Vcore = 650000
3735 23:50:40.133325 Vdram = 0
3736 23:50:40.133376 Vddq = 0
3737 23:50:40.133427 Vmddr = 0
3738 23:50:40.133479 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3739 23:50:40.133533 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3740 23:50:40.133586 MEM_TYPE=3, freq_sel=19
3741 23:50:40.133638 sv_algorithm_assistance_LP4_1600
3742 23:50:40.133690 ============ PULL DRAM RESETB DOWN ============
3743 23:50:40.133742 ========== PULL DRAM RESETB DOWN end =========
3744 23:50:40.133814 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3745 23:50:40.133870 ===================================
3746 23:50:40.133923 LPDDR4 DRAM CONFIGURATION
3747 23:50:40.133982 ===================================
3748 23:50:40.134035 EX_ROW_EN[0] = 0x0
3749 23:50:40.134088 EX_ROW_EN[1] = 0x0
3750 23:50:40.134140 LP4Y_EN = 0x0
3751 23:50:40.134191 WORK_FSP = 0x0
3752 23:50:40.134243 WL = 0x2
3753 23:50:40.134295 RL = 0x2
3754 23:50:40.134347 BL = 0x2
3755 23:50:40.134399 RPST = 0x0
3756 23:50:40.134450 RD_PRE = 0x0
3757 23:50:40.134502 WR_PRE = 0x1
3758 23:50:40.134553 WR_PST = 0x0
3759 23:50:40.134605 DBI_WR = 0x0
3760 23:50:40.134656 DBI_RD = 0x0
3761 23:50:40.134707 OTF = 0x1
3762 23:50:40.134758 ===================================
3763 23:50:40.134811 ===================================
3764 23:50:40.134863 ANA top config
3765 23:50:40.134914 ===================================
3766 23:50:40.134966 DLL_ASYNC_EN = 0
3767 23:50:40.135018 ALL_SLAVE_EN = 1
3768 23:50:40.135070 NEW_RANK_MODE = 1
3769 23:50:40.135123 DLL_IDLE_MODE = 1
3770 23:50:40.135175 LP45_APHY_COMB_EN = 1
3771 23:50:40.135227 TX_ODT_DIS = 1
3772 23:50:40.135279 NEW_8X_MODE = 1
3773 23:50:40.135331 ===================================
3774 23:50:40.135383 ===================================
3775 23:50:40.135434 data_rate = 1200
3776 23:50:40.135486 CKR = 1
3777 23:50:40.135537 DQ_P2S_RATIO = 8
3778 23:50:40.135589 ===================================
3779 23:50:40.135642 CA_P2S_RATIO = 8
3780 23:50:40.135694 DQ_CA_OPEN = 0
3781 23:50:40.135745 DQ_SEMI_OPEN = 0
3782 23:50:40.135802 CA_SEMI_OPEN = 0
3783 23:50:40.135868 CA_FULL_RATE = 0
3784 23:50:40.135921 DQ_CKDIV4_EN = 1
3785 23:50:40.135973 CA_CKDIV4_EN = 1
3786 23:50:40.136025 CA_PREDIV_EN = 0
3787 23:50:40.136077 PH8_DLY = 0
3788 23:50:40.136128 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3789 23:50:40.136181 DQ_AAMCK_DIV = 4
3790 23:50:40.136233 CA_AAMCK_DIV = 4
3791 23:50:40.136285 CA_ADMCK_DIV = 4
3792 23:50:40.136336 DQ_TRACK_CA_EN = 0
3793 23:50:40.136388 CA_PICK = 600
3794 23:50:40.136440 CA_MCKIO = 600
3795 23:50:40.136492 MCKIO_SEMI = 0
3796 23:50:40.136544 PLL_FREQ = 2288
3797 23:50:40.136632 DQ_UI_PI_RATIO = 32
3798 23:50:40.136684 CA_UI_PI_RATIO = 0
3799 23:50:40.136737 ===================================
3800 23:50:40.136980 ===================================
3801 23:50:40.137041 memory_type:LPDDR4
3802 23:50:40.137099 GP_NUM : 10
3803 23:50:40.137152 SRAM_EN : 1
3804 23:50:40.137203 MD32_EN : 0
3805 23:50:40.137255 ===================================
3806 23:50:40.137307 [ANA_INIT] >>>>>>>>>>>>>>
3807 23:50:40.137358 <<<<<< [CONFIGURE PHASE]: ANA_TX
3808 23:50:40.137411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3809 23:50:40.137463 ===================================
3810 23:50:40.137515 data_rate = 1200,PCW = 0X5800
3811 23:50:40.137567 ===================================
3812 23:50:40.137619 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3813 23:50:40.137671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 23:50:40.137723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 23:50:40.137778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3816 23:50:40.137846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3817 23:50:40.137935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3818 23:50:40.137994 [ANA_INIT] flow start
3819 23:50:40.138047 [ANA_INIT] PLL >>>>>>>>
3820 23:50:40.138099 [ANA_INIT] PLL <<<<<<<<
3821 23:50:40.138150 [ANA_INIT] MIDPI >>>>>>>>
3822 23:50:40.138202 [ANA_INIT] MIDPI <<<<<<<<
3823 23:50:40.138254 [ANA_INIT] DLL >>>>>>>>
3824 23:50:40.138306 [ANA_INIT] flow end
3825 23:50:40.138357 ============ LP4 DIFF to SE enter ============
3826 23:50:40.138409 ============ LP4 DIFF to SE exit ============
3827 23:50:40.138461 [ANA_INIT] <<<<<<<<<<<<<
3828 23:50:40.138513 [Flow] Enable top DCM control >>>>>
3829 23:50:40.138565 [Flow] Enable top DCM control <<<<<
3830 23:50:40.138616 Enable DLL master slave shuffle
3831 23:50:40.138668 ==============================================================
3832 23:50:40.138721 Gating Mode config
3833 23:50:40.138773 ==============================================================
3834 23:50:40.138825 Config description:
3835 23:50:40.138876 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3836 23:50:40.138929 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3837 23:50:40.138982 SELPH_MODE 0: By rank 1: By Phase
3838 23:50:40.139034 ==============================================================
3839 23:50:40.139086 GAT_TRACK_EN = 1
3840 23:50:40.139138 RX_GATING_MODE = 2
3841 23:50:40.139189 RX_GATING_TRACK_MODE = 2
3842 23:50:40.139240 SELPH_MODE = 1
3843 23:50:40.139292 PICG_EARLY_EN = 1
3844 23:50:40.139343 VALID_LAT_VALUE = 1
3845 23:50:40.139395 ==============================================================
3846 23:50:40.139447 Enter into Gating configuration >>>>
3847 23:50:40.139499 Exit from Gating configuration <<<<
3848 23:50:40.139550 Enter into DVFS_PRE_config >>>>>
3849 23:50:40.139602 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3850 23:50:40.139655 Exit from DVFS_PRE_config <<<<<
3851 23:50:40.139707 Enter into PICG configuration >>>>
3852 23:50:40.139759 Exit from PICG configuration <<<<
3853 23:50:40.139811 [RX_INPUT] configuration >>>>>
3854 23:50:40.139863 [RX_INPUT] configuration <<<<<
3855 23:50:40.139921 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3856 23:50:40.139980 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3857 23:50:40.140032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 23:50:40.140084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 23:50:40.140136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 23:50:40.140188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 23:50:40.140240 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3862 23:50:40.140292 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3863 23:50:40.140344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3864 23:50:40.140396 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3865 23:50:40.140468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3866 23:50:40.140556 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 23:50:40.140645 ===================================
3868 23:50:40.140698 LPDDR4 DRAM CONFIGURATION
3869 23:50:40.140750 ===================================
3870 23:50:40.140802 EX_ROW_EN[0] = 0x0
3871 23:50:40.140854 EX_ROW_EN[1] = 0x0
3872 23:50:40.140906 LP4Y_EN = 0x0
3873 23:50:40.140958 WORK_FSP = 0x0
3874 23:50:40.141010 WL = 0x2
3875 23:50:40.141061 RL = 0x2
3876 23:50:40.141112 BL = 0x2
3877 23:50:40.141163 RPST = 0x0
3878 23:50:40.141215 RD_PRE = 0x0
3879 23:50:40.141266 WR_PRE = 0x1
3880 23:50:40.141318 WR_PST = 0x0
3881 23:50:40.141369 DBI_WR = 0x0
3882 23:50:40.141421 DBI_RD = 0x0
3883 23:50:40.141485 OTF = 0x1
3884 23:50:40.141540 ===================================
3885 23:50:40.143861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3886 23:50:40.147313 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3887 23:50:40.150639 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 23:50:40.153824 ===================================
3889 23:50:40.157174 LPDDR4 DRAM CONFIGURATION
3890 23:50:40.160524 ===================================
3891 23:50:40.163680 EX_ROW_EN[0] = 0x10
3892 23:50:40.163761 EX_ROW_EN[1] = 0x0
3893 23:50:40.167356 LP4Y_EN = 0x0
3894 23:50:40.167438 WORK_FSP = 0x0
3895 23:50:40.170727 WL = 0x2
3896 23:50:40.170810 RL = 0x2
3897 23:50:40.173894 BL = 0x2
3898 23:50:40.173982 RPST = 0x0
3899 23:50:40.177001 RD_PRE = 0x0
3900 23:50:40.177110 WR_PRE = 0x1
3901 23:50:40.180482 WR_PST = 0x0
3902 23:50:40.183655 DBI_WR = 0x0
3903 23:50:40.183738 DBI_RD = 0x0
3904 23:50:40.187296 OTF = 0x1
3905 23:50:40.190237 ===================================
3906 23:50:40.193988 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3907 23:50:40.199259 nWR fixed to 30
3908 23:50:40.202354 [ModeRegInit_LP4] CH0 RK0
3909 23:50:40.202466 [ModeRegInit_LP4] CH0 RK1
3910 23:50:40.205648 [ModeRegInit_LP4] CH1 RK0
3911 23:50:40.209139 [ModeRegInit_LP4] CH1 RK1
3912 23:50:40.209303 match AC timing 17
3913 23:50:40.215939 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3914 23:50:40.219201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3915 23:50:40.222614 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3916 23:50:40.229371 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3917 23:50:40.232594 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3918 23:50:40.232886 ==
3919 23:50:40.236271 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 23:50:40.239449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 23:50:40.239769 ==
3922 23:50:40.246092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 23:50:40.252539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3924 23:50:40.255898 [CA 0] Center 36 (5~67) winsize 63
3925 23:50:40.259231 [CA 1] Center 36 (6~67) winsize 62
3926 23:50:40.262630 [CA 2] Center 34 (4~65) winsize 62
3927 23:50:40.265782 [CA 3] Center 34 (4~65) winsize 62
3928 23:50:40.269269 [CA 4] Center 34 (3~65) winsize 63
3929 23:50:40.272788 [CA 5] Center 33 (2~64) winsize 63
3930 23:50:40.273207
3931 23:50:40.275987 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3932 23:50:40.276405
3933 23:50:40.279047 [CATrainingPosCal] consider 1 rank data
3934 23:50:40.282811 u2DelayCellTimex100 = 270/100 ps
3935 23:50:40.286248 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3936 23:50:40.289262 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 23:50:40.292697 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3938 23:50:40.296119 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 23:50:40.299644 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3940 23:50:40.302598 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3941 23:50:40.305893
3942 23:50:40.309213 CA PerBit enable=1, Macro0, CA PI delay=33
3943 23:50:40.309678
3944 23:50:40.312419 [CBTSetCACLKResult] CA Dly = 33
3945 23:50:40.312895 CS Dly: 4 (0~35)
3946 23:50:40.313321 ==
3947 23:50:40.315538 Dram Type= 6, Freq= 0, CH_0, rank 1
3948 23:50:40.319051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 23:50:40.319508 ==
3950 23:50:40.325599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 23:50:40.332422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3952 23:50:40.335509 [CA 0] Center 36 (6~67) winsize 62
3953 23:50:40.339066 [CA 1] Center 36 (6~67) winsize 62
3954 23:50:40.342389 [CA 2] Center 34 (4~65) winsize 62
3955 23:50:40.345424 [CA 3] Center 34 (4~65) winsize 62
3956 23:50:40.348753 [CA 4] Center 34 (3~65) winsize 63
3957 23:50:40.352228 [CA 5] Center 33 (3~64) winsize 62
3958 23:50:40.352817
3959 23:50:40.355370 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3960 23:50:40.355801
3961 23:50:40.358644 [CATrainingPosCal] consider 2 rank data
3962 23:50:40.361993 u2DelayCellTimex100 = 270/100 ps
3963 23:50:40.365471 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 23:50:40.368661 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3965 23:50:40.372212 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 23:50:40.375405 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 23:50:40.381876 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3968 23:50:40.385298 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 23:50:40.385830
3970 23:50:40.388683 CA PerBit enable=1, Macro0, CA PI delay=33
3971 23:50:40.389117
3972 23:50:40.392088 [CBTSetCACLKResult] CA Dly = 33
3973 23:50:40.392661 CS Dly: 4 (0~36)
3974 23:50:40.393016
3975 23:50:40.395634 ----->DramcWriteLeveling(PI) begin...
3976 23:50:40.396160 ==
3977 23:50:40.398828 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 23:50:40.405332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 23:50:40.405863 ==
3980 23:50:40.408635 Write leveling (Byte 0): 33 => 33
3981 23:50:40.411934 Write leveling (Byte 1): 33 => 33
3982 23:50:40.412458 DramcWriteLeveling(PI) end<-----
3983 23:50:40.412870
3984 23:50:40.415589 ==
3985 23:50:40.416112 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 23:50:40.422162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 23:50:40.422702 ==
3988 23:50:40.425437 [Gating] SW mode calibration
3989 23:50:40.432175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3990 23:50:40.435252 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3991 23:50:40.442483 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 23:50:40.445450 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 23:50:40.448747 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 23:50:40.455095 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
3995 23:50:40.458910 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3996 23:50:40.461841 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 23:50:40.465126 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 23:50:40.472038 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 23:50:40.475178 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 23:50:40.478464 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 23:50:40.485413 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4002 23:50:40.488904 0 10 12 | B1->B0 | 2525 4040 | 1 1 | (0 0) (0 0)
4003 23:50:40.491935 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4004 23:50:40.498687 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 23:50:40.502237 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 23:50:40.505200 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 23:50:40.511866 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 23:50:40.515395 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 23:50:40.518541 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4010 23:50:40.525253 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4011 23:50:40.528699 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4012 23:50:40.531906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 23:50:40.538666 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 23:50:40.542138 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:50:40.545326 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:50:40.552253 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 23:50:40.555179 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 23:50:40.558539 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 23:50:40.565099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:50:40.568514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:50:40.571763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:50:40.578436 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:50:40.581724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:50:40.584888 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:50:40.588598 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:50:40.595028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4027 23:50:40.598474 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4028 23:50:40.601909 Total UI for P1: 0, mck2ui 16
4029 23:50:40.605026 best dqsien dly found for B0: ( 0, 13, 12)
4030 23:50:40.608800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 23:50:40.611558 Total UI for P1: 0, mck2ui 16
4032 23:50:40.615269 best dqsien dly found for B1: ( 0, 13, 14)
4033 23:50:40.618561 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4034 23:50:40.622076 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4035 23:50:40.625210
4036 23:50:40.628809 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4037 23:50:40.631968 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4038 23:50:40.635425 [Gating] SW calibration Done
4039 23:50:40.636004 ==
4040 23:50:40.638624 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 23:50:40.641942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 23:50:40.642517 ==
4043 23:50:40.643007 RX Vref Scan: 0
4044 23:50:40.643460
4045 23:50:40.644992 RX Vref 0 -> 0, step: 1
4046 23:50:40.645471
4047 23:50:40.648912 RX Delay -230 -> 252, step: 16
4048 23:50:40.651954 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4049 23:50:40.654867 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4050 23:50:40.661770 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4051 23:50:40.665421 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4052 23:50:40.668578 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4053 23:50:40.671753 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4054 23:50:40.678626 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4055 23:50:40.681793 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4056 23:50:40.684831 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4057 23:50:40.688209 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4058 23:50:40.691704 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4059 23:50:40.698543 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4060 23:50:40.701866 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4061 23:50:40.704670 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4062 23:50:40.708660 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4063 23:50:40.714861 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4064 23:50:40.715439 ==
4065 23:50:40.718363 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 23:50:40.721648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 23:50:40.722224 ==
4068 23:50:40.722714 DQS Delay:
4069 23:50:40.724992 DQS0 = 0, DQS1 = 0
4070 23:50:40.725562 DQM Delay:
4071 23:50:40.728234 DQM0 = 52, DQM1 = 38
4072 23:50:40.728843 DQ Delay:
4073 23:50:40.731651 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4074 23:50:40.734686 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4075 23:50:40.738223 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4076 23:50:40.741702 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4077 23:50:40.742182
4078 23:50:40.742659
4079 23:50:40.743110 ==
4080 23:50:40.744729 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 23:50:40.748288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 23:50:40.748918 ==
4083 23:50:40.751775
4084 23:50:40.752347
4085 23:50:40.752863 TX Vref Scan disable
4086 23:50:40.754679 == TX Byte 0 ==
4087 23:50:40.758475 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4088 23:50:40.761480 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4089 23:50:40.764615 == TX Byte 1 ==
4090 23:50:40.767960 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4091 23:50:40.771402 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4092 23:50:40.771888 ==
4093 23:50:40.774358 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 23:50:40.781547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 23:50:40.782264 ==
4096 23:50:40.782755
4097 23:50:40.783203
4098 23:50:40.783643 TX Vref Scan disable
4099 23:50:40.785590 == TX Byte 0 ==
4100 23:50:40.789142 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4101 23:50:40.795935 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4102 23:50:40.796525 == TX Byte 1 ==
4103 23:50:40.799197 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4104 23:50:40.805871 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4105 23:50:40.806435
4106 23:50:40.806922 [DATLAT]
4107 23:50:40.807375 Freq=600, CH0 RK0
4108 23:50:40.807818
4109 23:50:40.809045 DATLAT Default: 0x9
4110 23:50:40.809527 0, 0xFFFF, sum = 0
4111 23:50:40.812094 1, 0xFFFF, sum = 0
4112 23:50:40.812608 2, 0xFFFF, sum = 0
4113 23:50:40.816003 3, 0xFFFF, sum = 0
4114 23:50:40.819217 4, 0xFFFF, sum = 0
4115 23:50:40.819793 5, 0xFFFF, sum = 0
4116 23:50:40.822657 6, 0xFFFF, sum = 0
4117 23:50:40.823231 7, 0xFFFF, sum = 0
4118 23:50:40.825682 8, 0x0, sum = 1
4119 23:50:40.826279 9, 0x0, sum = 2
4120 23:50:40.826773 10, 0x0, sum = 3
4121 23:50:40.829172 11, 0x0, sum = 4
4122 23:50:40.829659 best_step = 9
4123 23:50:40.830137
4124 23:50:40.830584 ==
4125 23:50:40.832245 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 23:50:40.839188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 23:50:40.839756 ==
4128 23:50:40.840249 RX Vref Scan: 1
4129 23:50:40.840819
4130 23:50:40.842554 RX Vref 0 -> 0, step: 1
4131 23:50:40.843119
4132 23:50:40.845857 RX Delay -179 -> 252, step: 8
4133 23:50:40.846425
4134 23:50:40.849413 Set Vref, RX VrefLevel [Byte0]: 58
4135 23:50:40.852437 [Byte1]: 50
4136 23:50:40.853051
4137 23:50:40.855781 Final RX Vref Byte 0 = 58 to rank0
4138 23:50:40.858879 Final RX Vref Byte 1 = 50 to rank0
4139 23:50:40.862513 Final RX Vref Byte 0 = 58 to rank1
4140 23:50:40.865957 Final RX Vref Byte 1 = 50 to rank1==
4141 23:50:40.869203 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 23:50:40.872472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 23:50:40.873081 ==
4144 23:50:40.875812 DQS Delay:
4145 23:50:40.876291 DQS0 = 0, DQS1 = 0
4146 23:50:40.876843 DQM Delay:
4147 23:50:40.879048 DQM0 = 50, DQM1 = 36
4148 23:50:40.879609 DQ Delay:
4149 23:50:40.882151 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =48
4150 23:50:40.885385 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4151 23:50:40.889034 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4152 23:50:40.892646 DQ12 =40, DQ13 =36, DQ14 =48, DQ15 =44
4153 23:50:40.893229
4154 23:50:40.893713
4155 23:50:40.902511 [DQSOSCAuto] RK0, (LSB)MR18= 0x605a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4156 23:50:40.903100 CH0 RK0: MR19=808, MR18=605A
4157 23:50:40.909377 CH0_RK0: MR19=0x808, MR18=0x605A, DQSOSC=391, MR23=63, INC=171, DEC=114
4158 23:50:40.909950
4159 23:50:40.912482 ----->DramcWriteLeveling(PI) begin...
4160 23:50:40.913016 ==
4161 23:50:40.915632 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 23:50:40.922671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 23:50:40.923248 ==
4164 23:50:40.925725 Write leveling (Byte 0): 34 => 34
4165 23:50:40.929183 Write leveling (Byte 1): 31 => 31
4166 23:50:40.932523 DramcWriteLeveling(PI) end<-----
4167 23:50:40.933153
4168 23:50:40.933640 ==
4169 23:50:40.935779 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 23:50:40.939027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 23:50:40.939593 ==
4172 23:50:40.942119 [Gating] SW mode calibration
4173 23:50:40.949224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4174 23:50:40.955550 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4175 23:50:40.958817 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 23:50:40.962433 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 23:50:40.965360 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 23:50:40.971962 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 1) (1 1)
4179 23:50:40.975029 0 9 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (1 0)
4180 23:50:40.978790 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 23:50:40.985525 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 23:50:40.988586 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 23:50:40.992224 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 23:50:40.998999 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 23:50:41.002080 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 23:50:41.005407 0 10 12 | B1->B0 | 3131 3030 | 0 1 | (0 0) (0 0)
4187 23:50:41.011780 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4188 23:50:41.015330 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 23:50:41.018433 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 23:50:41.025383 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 23:50:41.028493 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 23:50:41.031738 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 23:50:41.038698 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 23:50:41.041742 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4195 23:50:41.045384 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 23:50:41.051957 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 23:50:41.054967 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 23:50:41.058541 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 23:50:41.065226 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 23:50:41.068499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 23:50:41.071678 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 23:50:41.074759 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:50:41.081298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:50:41.084728 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:50:41.088257 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:50:41.094873 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:50:41.098437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:50:41.101977 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:50:41.108752 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:50:41.111561 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4211 23:50:41.115096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 23:50:41.118250 Total UI for P1: 0, mck2ui 16
4213 23:50:41.121665 best dqsien dly found for B0: ( 0, 13, 12)
4214 23:50:41.125113 Total UI for P1: 0, mck2ui 16
4215 23:50:41.128734 best dqsien dly found for B1: ( 0, 13, 14)
4216 23:50:41.131921 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4217 23:50:41.135022 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4218 23:50:41.138577
4219 23:50:41.141480 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4220 23:50:41.145006 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4221 23:50:41.148327 [Gating] SW calibration Done
4222 23:50:41.148922 ==
4223 23:50:41.151833 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 23:50:41.154971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 23:50:41.155540 ==
4226 23:50:41.155916 RX Vref Scan: 0
4227 23:50:41.156262
4228 23:50:41.158467 RX Vref 0 -> 0, step: 1
4229 23:50:41.159027
4230 23:50:41.161308 RX Delay -230 -> 252, step: 16
4231 23:50:41.165264 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4232 23:50:41.171792 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4233 23:50:41.174994 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4234 23:50:41.178330 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4235 23:50:41.181496 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4236 23:50:41.184774 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4237 23:50:41.191534 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4238 23:50:41.194894 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4239 23:50:41.198400 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4240 23:50:41.201481 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4241 23:50:41.204900 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4242 23:50:41.211419 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4243 23:50:41.214582 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4244 23:50:41.218426 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4245 23:50:41.221356 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4246 23:50:41.228390 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4247 23:50:41.228994 ==
4248 23:50:41.231331 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 23:50:41.234731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 23:50:41.235241 ==
4251 23:50:41.235614 DQS Delay:
4252 23:50:41.238015 DQS0 = 0, DQS1 = 0
4253 23:50:41.238572 DQM Delay:
4254 23:50:41.241441 DQM0 = 49, DQM1 = 41
4255 23:50:41.242003 DQ Delay:
4256 23:50:41.245100 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4257 23:50:41.248021 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4258 23:50:41.251582 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4259 23:50:41.255116 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4260 23:50:41.255672
4261 23:50:41.256045
4262 23:50:41.256387 ==
4263 23:50:41.258068 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 23:50:41.261732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 23:50:41.262293 ==
4266 23:50:41.262665
4267 23:50:41.264923
4268 23:50:41.265475 TX Vref Scan disable
4269 23:50:41.268582 == TX Byte 0 ==
4270 23:50:41.271644 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4271 23:50:41.274776 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4272 23:50:41.278127 == TX Byte 1 ==
4273 23:50:41.281835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4274 23:50:41.284913 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4275 23:50:41.285509 ==
4276 23:50:41.288073 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 23:50:41.295026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 23:50:41.295740 ==
4279 23:50:41.296133
4280 23:50:41.296483
4281 23:50:41.296861 TX Vref Scan disable
4282 23:50:41.299524 == TX Byte 0 ==
4283 23:50:41.302583 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4284 23:50:41.309169 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4285 23:50:41.309734 == TX Byte 1 ==
4286 23:50:41.312650 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4287 23:50:41.319210 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4288 23:50:41.319778
4289 23:50:41.320151 [DATLAT]
4290 23:50:41.320497 Freq=600, CH0 RK1
4291 23:50:41.320931
4292 23:50:41.322497 DATLAT Default: 0x9
4293 23:50:41.323064 0, 0xFFFF, sum = 0
4294 23:50:41.325692 1, 0xFFFF, sum = 0
4295 23:50:41.329051 2, 0xFFFF, sum = 0
4296 23:50:41.329550 3, 0xFFFF, sum = 0
4297 23:50:41.332401 4, 0xFFFF, sum = 0
4298 23:50:41.332902 5, 0xFFFF, sum = 0
4299 23:50:41.335612 6, 0xFFFF, sum = 0
4300 23:50:41.336069 7, 0xFFFF, sum = 0
4301 23:50:41.338820 8, 0x0, sum = 1
4302 23:50:41.339275 9, 0x0, sum = 2
4303 23:50:41.339635 10, 0x0, sum = 3
4304 23:50:41.342472 11, 0x0, sum = 4
4305 23:50:41.342932 best_step = 9
4306 23:50:41.343290
4307 23:50:41.343618 ==
4308 23:50:41.345616 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 23:50:41.352585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 23:50:41.353143 ==
4311 23:50:41.353511 RX Vref Scan: 0
4312 23:50:41.353846
4313 23:50:41.355988 RX Vref 0 -> 0, step: 1
4314 23:50:41.356533
4315 23:50:41.358938 RX Delay -179 -> 252, step: 8
4316 23:50:41.362628 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4317 23:50:41.368845 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4318 23:50:41.372236 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4319 23:50:41.375273 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4320 23:50:41.378803 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4321 23:50:41.381990 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4322 23:50:41.388652 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4323 23:50:41.392200 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4324 23:50:41.395235 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4325 23:50:41.398559 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4326 23:50:41.405311 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4327 23:50:41.408765 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4328 23:50:41.411734 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4329 23:50:41.415440 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4330 23:50:41.418347 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4331 23:50:41.425299 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4332 23:50:41.425761 ==
4333 23:50:41.428479 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 23:50:41.431927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 23:50:41.432392 ==
4336 23:50:41.432806 DQS Delay:
4337 23:50:41.435076 DQS0 = 0, DQS1 = 0
4338 23:50:41.435660 DQM Delay:
4339 23:50:41.438387 DQM0 = 48, DQM1 = 41
4340 23:50:41.438836 DQ Delay:
4341 23:50:41.441738 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4342 23:50:41.445280 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4343 23:50:41.448537 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4344 23:50:41.451603 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52
4345 23:50:41.452058
4346 23:50:41.452411
4347 23:50:41.458321 [DQSOSCAuto] RK1, (LSB)MR18= 0x6431, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4348 23:50:41.461934 CH0 RK1: MR19=808, MR18=6431
4349 23:50:41.468226 CH0_RK1: MR19=0x808, MR18=0x6431, DQSOSC=391, MR23=63, INC=171, DEC=114
4350 23:50:41.471819 [RxdqsGatingPostProcess] freq 600
4351 23:50:41.478103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 23:50:41.481574 Pre-setting of DQS Precalculation
4353 23:50:41.485093 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 23:50:41.485506 ==
4355 23:50:41.488156 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 23:50:41.491677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 23:50:41.492093 ==
4358 23:50:41.498213 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 23:50:41.504574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4360 23:50:41.508068 [CA 0] Center 35 (5~66) winsize 62
4361 23:50:41.511685 [CA 1] Center 35 (5~66) winsize 62
4362 23:50:41.514665 [CA 2] Center 34 (3~65) winsize 63
4363 23:50:41.518006 [CA 3] Center 34 (3~65) winsize 63
4364 23:50:41.521392 [CA 4] Center 34 (3~65) winsize 63
4365 23:50:41.524754 [CA 5] Center 33 (3~64) winsize 62
4366 23:50:41.525046
4367 23:50:41.528045 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4368 23:50:41.528345
4369 23:50:41.531336 [CATrainingPosCal] consider 1 rank data
4370 23:50:41.534704 u2DelayCellTimex100 = 270/100 ps
4371 23:50:41.537778 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 23:50:41.541536 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 23:50:41.544861 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4374 23:50:41.548326 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4375 23:50:41.551712 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4376 23:50:41.558037 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4377 23:50:41.558503
4378 23:50:41.561239 CA PerBit enable=1, Macro0, CA PI delay=33
4379 23:50:41.561711
4380 23:50:41.564538 [CBTSetCACLKResult] CA Dly = 33
4381 23:50:41.565036 CS Dly: 4 (0~35)
4382 23:50:41.565410 ==
4383 23:50:41.568279 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 23:50:41.571302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 23:50:41.574445 ==
4386 23:50:41.577884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 23:50:41.584615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4388 23:50:41.587731 [CA 0] Center 35 (5~66) winsize 62
4389 23:50:41.591400 [CA 1] Center 35 (5~66) winsize 62
4390 23:50:41.594614 [CA 2] Center 34 (4~65) winsize 62
4391 23:50:41.597965 [CA 3] Center 34 (4~65) winsize 62
4392 23:50:41.601071 [CA 4] Center 34 (4~64) winsize 61
4393 23:50:41.604515 [CA 5] Center 33 (3~64) winsize 62
4394 23:50:41.604975
4395 23:50:41.607851 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4396 23:50:41.608270
4397 23:50:41.611243 [CATrainingPosCal] consider 2 rank data
4398 23:50:41.614429 u2DelayCellTimex100 = 270/100 ps
4399 23:50:41.617732 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 23:50:41.621161 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 23:50:41.624128 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 23:50:41.627389 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 23:50:41.634158 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4404 23:50:41.637499 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 23:50:41.637683
4406 23:50:41.640726 CA PerBit enable=1, Macro0, CA PI delay=33
4407 23:50:41.640908
4408 23:50:41.644135 [CBTSetCACLKResult] CA Dly = 33
4409 23:50:41.644319 CS Dly: 5 (0~37)
4410 23:50:41.644466
4411 23:50:41.647373 ----->DramcWriteLeveling(PI) begin...
4412 23:50:41.647558 ==
4413 23:50:41.650683 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 23:50:41.657933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 23:50:41.658527 ==
4416 23:50:41.660887 Write leveling (Byte 0): 29 => 29
4417 23:50:41.664496 Write leveling (Byte 1): 29 => 29
4418 23:50:41.665004 DramcWriteLeveling(PI) end<-----
4419 23:50:41.665383
4420 23:50:41.668045 ==
4421 23:50:41.670901 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 23:50:41.674382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 23:50:41.674684 ==
4424 23:50:41.677624 [Gating] SW mode calibration
4425 23:50:41.684163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 23:50:41.687389 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 23:50:41.694070 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 23:50:41.697369 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 23:50:41.700973 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
4430 23:50:41.707783 0 9 12 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (1 0)
4431 23:50:41.710792 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 23:50:41.713935 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 23:50:41.720997 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 23:50:41.724219 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 23:50:41.727671 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 23:50:41.733972 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 23:50:41.737745 0 10 8 | B1->B0 | 2626 2c2c | 0 1 | (0 0) (0 0)
4438 23:50:41.740843 0 10 12 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)
4439 23:50:41.744010 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 23:50:41.750671 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 23:50:41.754177 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 23:50:41.757539 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 23:50:41.764106 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 23:50:41.767185 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 23:50:41.770824 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4446 23:50:41.777041 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 23:50:41.780721 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 23:50:41.783916 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 23:50:41.790449 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 23:50:41.794064 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 23:50:41.797156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 23:50:41.804361 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 23:50:41.807201 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 23:50:41.810707 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 23:50:41.817196 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:50:41.820569 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 23:50:41.824202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:50:41.830473 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:50:41.833892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:50:41.837296 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:50:41.840556 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4462 23:50:41.847448 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 23:50:41.850432 Total UI for P1: 0, mck2ui 16
4464 23:50:41.853822 best dqsien dly found for B0: ( 0, 13, 8)
4465 23:50:41.857058 Total UI for P1: 0, mck2ui 16
4466 23:50:41.860205 best dqsien dly found for B1: ( 0, 13, 8)
4467 23:50:41.863533 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4468 23:50:41.866845 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4469 23:50:41.866964
4470 23:50:41.870560 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4471 23:50:41.873785 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4472 23:50:41.877062 [Gating] SW calibration Done
4473 23:50:41.877191 ==
4474 23:50:41.880118 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 23:50:41.883855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 23:50:41.884083 ==
4477 23:50:41.887186 RX Vref Scan: 0
4478 23:50:41.887443
4479 23:50:41.887601 RX Vref 0 -> 0, step: 1
4480 23:50:41.890637
4481 23:50:41.890903 RX Delay -230 -> 252, step: 16
4482 23:50:41.897213 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4483 23:50:41.900733 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4484 23:50:41.903811 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4485 23:50:41.907561 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4486 23:50:41.914434 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4487 23:50:41.917281 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4488 23:50:41.920930 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4489 23:50:41.924111 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4490 23:50:41.927628 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4491 23:50:41.933965 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4492 23:50:41.937425 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4493 23:50:41.940782 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4494 23:50:41.944078 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4495 23:50:41.947350 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4496 23:50:41.953824 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4497 23:50:41.957545 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4498 23:50:41.958115 ==
4499 23:50:41.960680 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 23:50:41.963808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 23:50:41.964291 ==
4502 23:50:41.967261 DQS Delay:
4503 23:50:41.967831 DQS0 = 0, DQS1 = 0
4504 23:50:41.970996 DQM Delay:
4505 23:50:41.971558 DQM0 = 51, DQM1 = 45
4506 23:50:41.971933 DQ Delay:
4507 23:50:41.973926 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4508 23:50:41.977524 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4509 23:50:41.980664 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4510 23:50:41.984128 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4511 23:50:41.984792
4512 23:50:41.985193
4513 23:50:41.987053 ==
4514 23:50:41.987523 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 23:50:41.993969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 23:50:41.994529 ==
4517 23:50:41.994905
4518 23:50:41.995252
4519 23:50:41.996871 TX Vref Scan disable
4520 23:50:41.997337 == TX Byte 0 ==
4521 23:50:42.000700 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 23:50:42.007279 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 23:50:42.007850 == TX Byte 1 ==
4524 23:50:42.010487 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4525 23:50:42.017106 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4526 23:50:42.017674 ==
4527 23:50:42.020818 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 23:50:42.023986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 23:50:42.024613 ==
4530 23:50:42.025008
4531 23:50:42.025362
4532 23:50:42.027248 TX Vref Scan disable
4533 23:50:42.030523 == TX Byte 0 ==
4534 23:50:42.033951 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4535 23:50:42.037181 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4536 23:50:42.040356 == TX Byte 1 ==
4537 23:50:42.043761 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4538 23:50:42.046803 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4539 23:50:42.047278
4540 23:50:42.050498 [DATLAT]
4541 23:50:42.051081 Freq=600, CH1 RK0
4542 23:50:42.051464
4543 23:50:42.053537 DATLAT Default: 0x9
4544 23:50:42.054011 0, 0xFFFF, sum = 0
4545 23:50:42.056757 1, 0xFFFF, sum = 0
4546 23:50:42.057236 2, 0xFFFF, sum = 0
4547 23:50:42.060160 3, 0xFFFF, sum = 0
4548 23:50:42.060682 4, 0xFFFF, sum = 0
4549 23:50:42.063705 5, 0xFFFF, sum = 0
4550 23:50:42.064288 6, 0xFFFF, sum = 0
4551 23:50:42.067134 7, 0xFFFF, sum = 0
4552 23:50:42.067711 8, 0x0, sum = 1
4553 23:50:42.070194 9, 0x0, sum = 2
4554 23:50:42.070700 10, 0x0, sum = 3
4555 23:50:42.073470 11, 0x0, sum = 4
4556 23:50:42.073952 best_step = 9
4557 23:50:42.074328
4558 23:50:42.074710 ==
4559 23:50:42.076845 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 23:50:42.080300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 23:50:42.080922 ==
4562 23:50:42.083696 RX Vref Scan: 1
4563 23:50:42.084276
4564 23:50:42.087117 RX Vref 0 -> 0, step: 1
4565 23:50:42.087683
4566 23:50:42.088069 RX Delay -179 -> 252, step: 8
4567 23:50:42.088423
4568 23:50:42.089976 Set Vref, RX VrefLevel [Byte0]: 51
4569 23:50:42.093793 [Byte1]: 57
4570 23:50:42.098234
4571 23:50:42.098797 Final RX Vref Byte 0 = 51 to rank0
4572 23:50:42.101765 Final RX Vref Byte 1 = 57 to rank0
4573 23:50:42.104902 Final RX Vref Byte 0 = 51 to rank1
4574 23:50:42.108400 Final RX Vref Byte 1 = 57 to rank1==
4575 23:50:42.111589 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 23:50:42.118329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 23:50:42.118910 ==
4578 23:50:42.119293 DQS Delay:
4579 23:50:42.119646 DQS0 = 0, DQS1 = 0
4580 23:50:42.121855 DQM Delay:
4581 23:50:42.122430 DQM0 = 49, DQM1 = 41
4582 23:50:42.124938 DQ Delay:
4583 23:50:42.128011 DQ0 =56, DQ1 =48, DQ2 =36, DQ3 =44
4584 23:50:42.131687 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4585 23:50:42.132285 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4586 23:50:42.135003 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4587 23:50:42.138267
4588 23:50:42.138741
4589 23:50:42.144955 [DQSOSCAuto] RK0, (LSB)MR18= 0x5178, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4590 23:50:42.148597 CH1 RK0: MR19=808, MR18=5178
4591 23:50:42.154893 CH1_RK0: MR19=0x808, MR18=0x5178, DQSOSC=387, MR23=63, INC=175, DEC=116
4592 23:50:42.155369
4593 23:50:42.158377 ----->DramcWriteLeveling(PI) begin...
4594 23:50:42.158954 ==
4595 23:50:42.161538 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 23:50:42.165361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 23:50:42.165934 ==
4598 23:50:42.168259 Write leveling (Byte 0): 30 => 30
4599 23:50:42.171788 Write leveling (Byte 1): 30 => 30
4600 23:50:42.175369 DramcWriteLeveling(PI) end<-----
4601 23:50:42.175934
4602 23:50:42.176314 ==
4603 23:50:42.178083 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 23:50:42.182054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 23:50:42.182673 ==
4606 23:50:42.184866 [Gating] SW mode calibration
4607 23:50:42.191795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 23:50:42.198454 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 23:50:42.201863 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 23:50:42.205004 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 23:50:42.211676 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 23:50:42.215443 0 9 12 | B1->B0 | 2f2f 3030 | 0 1 | (0 1) (1 0)
4613 23:50:42.218479 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 23:50:42.225143 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 23:50:42.228750 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 23:50:42.231814 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 23:50:42.238380 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 23:50:42.241947 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 23:50:42.245115 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 23:50:42.248674 0 10 12 | B1->B0 | 3e3e 3333 | 0 0 | (0 0) (0 0)
4621 23:50:42.254889 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 23:50:42.258677 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 23:50:42.261994 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 23:50:42.268482 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 23:50:42.271990 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 23:50:42.275494 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 23:50:42.281531 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4628 23:50:42.284883 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4629 23:50:42.288135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 23:50:42.295321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 23:50:42.298512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 23:50:42.301777 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 23:50:42.308364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 23:50:42.311801 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 23:50:42.315028 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 23:50:42.321576 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 23:50:42.325132 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:50:42.328544 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:50:42.335323 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 23:50:42.338440 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:50:42.341669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:50:42.347935 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:50:42.351887 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:50:42.354487 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4645 23:50:42.361337 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 23:50:42.361948 Total UI for P1: 0, mck2ui 16
4647 23:50:42.364961 best dqsien dly found for B0: ( 0, 13, 12)
4648 23:50:42.367933 Total UI for P1: 0, mck2ui 16
4649 23:50:42.371630 best dqsien dly found for B1: ( 0, 13, 12)
4650 23:50:42.374671 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4651 23:50:42.381487 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4652 23:50:42.381977
4653 23:50:42.384740 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 23:50:42.388062 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4655 23:50:42.391436 [Gating] SW calibration Done
4656 23:50:42.392153 ==
4657 23:50:42.394826 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 23:50:42.398274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 23:50:42.398748 ==
4660 23:50:42.401431 RX Vref Scan: 0
4661 23:50:42.401928
4662 23:50:42.402302 RX Vref 0 -> 0, step: 1
4663 23:50:42.402676
4664 23:50:42.404713 RX Delay -230 -> 252, step: 16
4665 23:50:42.407951 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4666 23:50:42.414752 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4667 23:50:42.417690 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4668 23:50:42.421214 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4669 23:50:42.424484 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4670 23:50:42.427840 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4671 23:50:42.434519 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4672 23:50:42.437996 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4673 23:50:42.441151 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4674 23:50:42.444454 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4675 23:50:42.451317 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4676 23:50:42.454189 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4677 23:50:42.457845 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4678 23:50:42.460952 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4679 23:50:42.467387 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4680 23:50:42.470801 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4681 23:50:42.471035 ==
4682 23:50:42.474238 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 23:50:42.477692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 23:50:42.478131 ==
4685 23:50:42.480953 DQS Delay:
4686 23:50:42.481380 DQS0 = 0, DQS1 = 0
4687 23:50:42.481724 DQM Delay:
4688 23:50:42.484332 DQM0 = 51, DQM1 = 46
4689 23:50:42.484792 DQ Delay:
4690 23:50:42.487812 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4691 23:50:42.490817 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4692 23:50:42.494455 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4693 23:50:42.497711 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4694 23:50:42.498250
4695 23:50:42.498596
4696 23:50:42.498914 ==
4697 23:50:42.501073 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 23:50:42.504682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 23:50:42.507776 ==
4700 23:50:42.508208
4701 23:50:42.508576
4702 23:50:42.508916 TX Vref Scan disable
4703 23:50:42.510796 == TX Byte 0 ==
4704 23:50:42.514295 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 23:50:42.521033 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 23:50:42.521462 == TX Byte 1 ==
4707 23:50:42.524365 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4708 23:50:42.531160 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4709 23:50:42.531716 ==
4710 23:50:42.534210 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 23:50:42.537881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 23:50:42.538417 ==
4713 23:50:42.538766
4714 23:50:42.539087
4715 23:50:42.541087 TX Vref Scan disable
4716 23:50:42.541616 == TX Byte 0 ==
4717 23:50:42.547934 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4718 23:50:42.550757 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4719 23:50:42.554266 == TX Byte 1 ==
4720 23:50:42.557792 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4721 23:50:42.561202 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4722 23:50:42.561867
4723 23:50:42.562227 [DATLAT]
4724 23:50:42.564264 Freq=600, CH1 RK1
4725 23:50:42.564757
4726 23:50:42.565197 DATLAT Default: 0x9
4727 23:50:42.567275 0, 0xFFFF, sum = 0
4728 23:50:42.567711 1, 0xFFFF, sum = 0
4729 23:50:42.570953 2, 0xFFFF, sum = 0
4730 23:50:42.571386 3, 0xFFFF, sum = 0
4731 23:50:42.574533 4, 0xFFFF, sum = 0
4732 23:50:42.574965 5, 0xFFFF, sum = 0
4733 23:50:42.577459 6, 0xFFFF, sum = 0
4734 23:50:42.580796 7, 0xFFFF, sum = 0
4735 23:50:42.581248 8, 0x0, sum = 1
4736 23:50:42.581595 9, 0x0, sum = 2
4737 23:50:42.584520 10, 0x0, sum = 3
4738 23:50:42.585117 11, 0x0, sum = 4
4739 23:50:42.587521 best_step = 9
4740 23:50:42.587997
4741 23:50:42.588370 ==
4742 23:50:42.590812 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 23:50:42.594606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 23:50:42.595176 ==
4745 23:50:42.597995 RX Vref Scan: 0
4746 23:50:42.598557
4747 23:50:42.598931 RX Vref 0 -> 0, step: 1
4748 23:50:42.599283
4749 23:50:42.600614 RX Delay -179 -> 252, step: 8
4750 23:50:42.607976 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4751 23:50:42.611602 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4752 23:50:42.614651 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4753 23:50:42.618098 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4754 23:50:42.625007 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4755 23:50:42.628183 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4756 23:50:42.631322 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4757 23:50:42.634442 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4758 23:50:42.638213 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4759 23:50:42.641465 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4760 23:50:42.648252 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4761 23:50:42.651359 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4762 23:50:42.654410 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4763 23:50:42.657973 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4764 23:50:42.664387 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4765 23:50:42.667809 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4766 23:50:42.668380 ==
4767 23:50:42.671141 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 23:50:42.674344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 23:50:42.674819 ==
4770 23:50:42.677863 DQS Delay:
4771 23:50:42.678493 DQS0 = 0, DQS1 = 0
4772 23:50:42.678881 DQM Delay:
4773 23:50:42.680858 DQM0 = 48, DQM1 = 43
4774 23:50:42.681328 DQ Delay:
4775 23:50:42.684444 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4776 23:50:42.687837 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4777 23:50:42.691315 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =40
4778 23:50:42.694132 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4779 23:50:42.694606
4780 23:50:42.694979
4781 23:50:42.704751 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
4782 23:50:42.705351 CH1 RK1: MR19=808, MR18=5D25
4783 23:50:42.711343 CH1_RK1: MR19=0x808, MR18=0x5D25, DQSOSC=392, MR23=63, INC=170, DEC=113
4784 23:50:42.714873 [RxdqsGatingPostProcess] freq 600
4785 23:50:42.721487 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4786 23:50:42.724625 Pre-setting of DQS Precalculation
4787 23:50:42.727770 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4788 23:50:42.734437 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4789 23:50:42.744288 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4790 23:50:42.744915
4791 23:50:42.745409
4792 23:50:42.747778 [Calibration Summary] 1200 Mbps
4793 23:50:42.748359 CH 0, Rank 0
4794 23:50:42.750929 SW Impedance : PASS
4795 23:50:42.751507 DUTY Scan : NO K
4796 23:50:42.754533 ZQ Calibration : PASS
4797 23:50:42.755111 Jitter Meter : NO K
4798 23:50:42.757414 CBT Training : PASS
4799 23:50:42.760698 Write leveling : PASS
4800 23:50:42.761269 RX DQS gating : PASS
4801 23:50:42.764495 RX DQ/DQS(RDDQC) : PASS
4802 23:50:42.767463 TX DQ/DQS : PASS
4803 23:50:42.768042 RX DATLAT : PASS
4804 23:50:42.770828 RX DQ/DQS(Engine): PASS
4805 23:50:42.774220 TX OE : NO K
4806 23:50:42.774695 All Pass.
4807 23:50:42.775069
4808 23:50:42.775420 CH 0, Rank 1
4809 23:50:42.777481 SW Impedance : PASS
4810 23:50:42.780959 DUTY Scan : NO K
4811 23:50:42.781429 ZQ Calibration : PASS
4812 23:50:42.784278 Jitter Meter : NO K
4813 23:50:42.787809 CBT Training : PASS
4814 23:50:42.788276 Write leveling : PASS
4815 23:50:42.790674 RX DQS gating : PASS
4816 23:50:42.794061 RX DQ/DQS(RDDQC) : PASS
4817 23:50:42.794531 TX DQ/DQS : PASS
4818 23:50:42.797799 RX DATLAT : PASS
4819 23:50:42.798358 RX DQ/DQS(Engine): PASS
4820 23:50:42.800942 TX OE : NO K
4821 23:50:42.801413 All Pass.
4822 23:50:42.801788
4823 23:50:42.804277 CH 1, Rank 0
4824 23:50:42.804768 SW Impedance : PASS
4825 23:50:42.807871 DUTY Scan : NO K
4826 23:50:42.811151 ZQ Calibration : PASS
4827 23:50:42.811715 Jitter Meter : NO K
4828 23:50:42.814314 CBT Training : PASS
4829 23:50:42.817428 Write leveling : PASS
4830 23:50:42.817973 RX DQS gating : PASS
4831 23:50:42.821143 RX DQ/DQS(RDDQC) : PASS
4832 23:50:42.824225 TX DQ/DQS : PASS
4833 23:50:42.824836 RX DATLAT : PASS
4834 23:50:42.827827 RX DQ/DQS(Engine): PASS
4835 23:50:42.830992 TX OE : NO K
4836 23:50:42.831556 All Pass.
4837 23:50:42.831931
4838 23:50:42.832279 CH 1, Rank 1
4839 23:50:42.834278 SW Impedance : PASS
4840 23:50:42.837434 DUTY Scan : NO K
4841 23:50:42.837905 ZQ Calibration : PASS
4842 23:50:42.840620 Jitter Meter : NO K
4843 23:50:42.841088 CBT Training : PASS
4844 23:50:42.844502 Write leveling : PASS
4845 23:50:42.847351 RX DQS gating : PASS
4846 23:50:42.847907 RX DQ/DQS(RDDQC) : PASS
4847 23:50:42.850897 TX DQ/DQS : PASS
4848 23:50:42.854190 RX DATLAT : PASS
4849 23:50:42.854755 RX DQ/DQS(Engine): PASS
4850 23:50:42.857428 TX OE : NO K
4851 23:50:42.857994 All Pass.
4852 23:50:42.858373
4853 23:50:42.860898 DramC Write-DBI off
4854 23:50:42.864507 PER_BANK_REFRESH: Hybrid Mode
4855 23:50:42.865131 TX_TRACKING: ON
4856 23:50:42.874192 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4857 23:50:42.877296 [FAST_K] Save calibration result to emmc
4858 23:50:42.880625 dramc_set_vcore_voltage set vcore to 662500
4859 23:50:42.883921 Read voltage for 933, 3
4860 23:50:42.884393 Vio18 = 0
4861 23:50:42.884854 Vcore = 662500
4862 23:50:42.887393 Vdram = 0
4863 23:50:42.888006 Vddq = 0
4864 23:50:42.888388 Vmddr = 0
4865 23:50:42.893690 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4866 23:50:42.897366 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4867 23:50:42.900697 MEM_TYPE=3, freq_sel=17
4868 23:50:42.903920 sv_algorithm_assistance_LP4_1600
4869 23:50:42.907238 ============ PULL DRAM RESETB DOWN ============
4870 23:50:42.913924 ========== PULL DRAM RESETB DOWN end =========
4871 23:50:42.917135 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4872 23:50:42.920737 ===================================
4873 23:50:42.923825 LPDDR4 DRAM CONFIGURATION
4874 23:50:42.927453 ===================================
4875 23:50:42.928017 EX_ROW_EN[0] = 0x0
4876 23:50:42.930571 EX_ROW_EN[1] = 0x0
4877 23:50:42.931135 LP4Y_EN = 0x0
4878 23:50:42.933549 WORK_FSP = 0x0
4879 23:50:42.934015 WL = 0x3
4880 23:50:42.937469 RL = 0x3
4881 23:50:42.938035 BL = 0x2
4882 23:50:42.940382 RPST = 0x0
4883 23:50:42.940864 RD_PRE = 0x0
4884 23:50:42.944166 WR_PRE = 0x1
4885 23:50:42.944769 WR_PST = 0x0
4886 23:50:42.947034 DBI_WR = 0x0
4887 23:50:42.947499 DBI_RD = 0x0
4888 23:50:42.950813 OTF = 0x1
4889 23:50:42.953976 ===================================
4890 23:50:42.957379 ===================================
4891 23:50:42.957947 ANA top config
4892 23:50:42.960505 ===================================
4893 23:50:42.963992 DLL_ASYNC_EN = 0
4894 23:50:42.967078 ALL_SLAVE_EN = 1
4895 23:50:42.970214 NEW_RANK_MODE = 1
4896 23:50:42.970782 DLL_IDLE_MODE = 1
4897 23:50:42.973753 LP45_APHY_COMB_EN = 1
4898 23:50:42.977027 TX_ODT_DIS = 1
4899 23:50:42.980467 NEW_8X_MODE = 1
4900 23:50:42.983820 ===================================
4901 23:50:42.986902 ===================================
4902 23:50:42.990255 data_rate = 1866
4903 23:50:42.993561 CKR = 1
4904 23:50:42.994091 DQ_P2S_RATIO = 8
4905 23:50:42.996627 ===================================
4906 23:50:43.000331 CA_P2S_RATIO = 8
4907 23:50:43.003859 DQ_CA_OPEN = 0
4908 23:50:43.006706 DQ_SEMI_OPEN = 0
4909 23:50:43.010081 CA_SEMI_OPEN = 0
4910 23:50:43.010553 CA_FULL_RATE = 0
4911 23:50:43.013188 DQ_CKDIV4_EN = 1
4912 23:50:43.016772 CA_CKDIV4_EN = 1
4913 23:50:43.020150 CA_PREDIV_EN = 0
4914 23:50:43.023661 PH8_DLY = 0
4915 23:50:43.027120 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4916 23:50:43.027709 DQ_AAMCK_DIV = 4
4917 23:50:43.030510 CA_AAMCK_DIV = 4
4918 23:50:43.033631 CA_ADMCK_DIV = 4
4919 23:50:43.037146 DQ_TRACK_CA_EN = 0
4920 23:50:43.040208 CA_PICK = 933
4921 23:50:43.043784 CA_MCKIO = 933
4922 23:50:43.044359 MCKIO_SEMI = 0
4923 23:50:43.047109 PLL_FREQ = 3732
4924 23:50:43.050505 DQ_UI_PI_RATIO = 32
4925 23:50:43.053795 CA_UI_PI_RATIO = 0
4926 23:50:43.056724 ===================================
4927 23:50:43.060332 ===================================
4928 23:50:43.063522 memory_type:LPDDR4
4929 23:50:43.064097 GP_NUM : 10
4930 23:50:43.066623 SRAM_EN : 1
4931 23:50:43.070070 MD32_EN : 0
4932 23:50:43.073434 ===================================
4933 23:50:43.073916 [ANA_INIT] >>>>>>>>>>>>>>
4934 23:50:43.076483 <<<<<< [CONFIGURE PHASE]: ANA_TX
4935 23:50:43.079566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4936 23:50:43.083603 ===================================
4937 23:50:43.086739 data_rate = 1866,PCW = 0X8f00
4938 23:50:43.089668 ===================================
4939 23:50:43.093211 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4940 23:50:43.099999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 23:50:43.103320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 23:50:43.109922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4943 23:50:43.112726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4944 23:50:43.116381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4945 23:50:43.119447 [ANA_INIT] flow start
4946 23:50:43.119936 [ANA_INIT] PLL >>>>>>>>
4947 23:50:43.123017 [ANA_INIT] PLL <<<<<<<<
4948 23:50:43.126439 [ANA_INIT] MIDPI >>>>>>>>
4949 23:50:43.127019 [ANA_INIT] MIDPI <<<<<<<<
4950 23:50:43.129368 [ANA_INIT] DLL >>>>>>>>
4951 23:50:43.132902 [ANA_INIT] flow end
4952 23:50:43.136293 ============ LP4 DIFF to SE enter ============
4953 23:50:43.139276 ============ LP4 DIFF to SE exit ============
4954 23:50:43.143114 [ANA_INIT] <<<<<<<<<<<<<
4955 23:50:43.146275 [Flow] Enable top DCM control >>>>>
4956 23:50:43.149552 [Flow] Enable top DCM control <<<<<
4957 23:50:43.152913 Enable DLL master slave shuffle
4958 23:50:43.156262 ==============================================================
4959 23:50:43.159959 Gating Mode config
4960 23:50:43.166653 ==============================================================
4961 23:50:43.167232 Config description:
4962 23:50:43.176288 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4963 23:50:43.182795 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4964 23:50:43.186678 SELPH_MODE 0: By rank 1: By Phase
4965 23:50:43.192954 ==============================================================
4966 23:50:43.196080 GAT_TRACK_EN = 1
4967 23:50:43.200004 RX_GATING_MODE = 2
4968 23:50:43.202725 RX_GATING_TRACK_MODE = 2
4969 23:50:43.205859 SELPH_MODE = 1
4970 23:50:43.209518 PICG_EARLY_EN = 1
4971 23:50:43.213173 VALID_LAT_VALUE = 1
4972 23:50:43.216323 ==============================================================
4973 23:50:43.219217 Enter into Gating configuration >>>>
4974 23:50:43.222975 Exit from Gating configuration <<<<
4975 23:50:43.226268 Enter into DVFS_PRE_config >>>>>
4976 23:50:43.236249 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4977 23:50:43.239287 Exit from DVFS_PRE_config <<<<<
4978 23:50:43.243164 Enter into PICG configuration >>>>
4979 23:50:43.246191 Exit from PICG configuration <<<<
4980 23:50:43.249710 [RX_INPUT] configuration >>>>>
4981 23:50:43.252809 [RX_INPUT] configuration <<<<<
4982 23:50:43.256674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4983 23:50:43.262887 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4984 23:50:43.269454 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 23:50:43.276178 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 23:50:43.282942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 23:50:43.289356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 23:50:43.292297 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4989 23:50:43.296079 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4990 23:50:43.299224 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4991 23:50:43.305674 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4992 23:50:43.309256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4993 23:50:43.312574 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 23:50:43.315804 ===================================
4995 23:50:43.318845 LPDDR4 DRAM CONFIGURATION
4996 23:50:43.322757 ===================================
4997 23:50:43.323326 EX_ROW_EN[0] = 0x0
4998 23:50:43.325702 EX_ROW_EN[1] = 0x0
4999 23:50:43.326270 LP4Y_EN = 0x0
5000 23:50:43.329142 WORK_FSP = 0x0
5001 23:50:43.329717 WL = 0x3
5002 23:50:43.332477 RL = 0x3
5003 23:50:43.335969 BL = 0x2
5004 23:50:43.336532 RPST = 0x0
5005 23:50:43.338774 RD_PRE = 0x0
5006 23:50:43.339361 WR_PRE = 0x1
5007 23:50:43.342688 WR_PST = 0x0
5008 23:50:43.343315 DBI_WR = 0x0
5009 23:50:43.345600 DBI_RD = 0x0
5010 23:50:43.346164 OTF = 0x1
5011 23:50:43.349073 ===================================
5012 23:50:43.352472 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5013 23:50:43.359303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5014 23:50:43.362582 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 23:50:43.365548 ===================================
5016 23:50:43.369179 LPDDR4 DRAM CONFIGURATION
5017 23:50:43.372301 ===================================
5018 23:50:43.372905 EX_ROW_EN[0] = 0x10
5019 23:50:43.375783 EX_ROW_EN[1] = 0x0
5020 23:50:43.376346 LP4Y_EN = 0x0
5021 23:50:43.379374 WORK_FSP = 0x0
5022 23:50:43.379937 WL = 0x3
5023 23:50:43.382185 RL = 0x3
5024 23:50:43.382858 BL = 0x2
5025 23:50:43.385444 RPST = 0x0
5026 23:50:43.386135 RD_PRE = 0x0
5027 23:50:43.389052 WR_PRE = 0x1
5028 23:50:43.389712 WR_PST = 0x0
5029 23:50:43.392031 DBI_WR = 0x0
5030 23:50:43.392664 DBI_RD = 0x0
5031 23:50:43.395487 OTF = 0x1
5032 23:50:43.398954 ===================================
5033 23:50:43.405371 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5034 23:50:43.409088 nWR fixed to 30
5035 23:50:43.412319 [ModeRegInit_LP4] CH0 RK0
5036 23:50:43.412955 [ModeRegInit_LP4] CH0 RK1
5037 23:50:43.415668 [ModeRegInit_LP4] CH1 RK0
5038 23:50:43.419033 [ModeRegInit_LP4] CH1 RK1
5039 23:50:43.419503 match AC timing 9
5040 23:50:43.425767 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5041 23:50:43.429246 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5042 23:50:43.432504 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5043 23:50:43.438955 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5044 23:50:43.442401 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5045 23:50:43.442983 ==
5046 23:50:43.445810 Dram Type= 6, Freq= 0, CH_0, rank 0
5047 23:50:43.449004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5048 23:50:43.449485 ==
5049 23:50:43.455984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5050 23:50:43.462434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5051 23:50:43.466065 [CA 0] Center 38 (7~69) winsize 63
5052 23:50:43.469149 [CA 1] Center 38 (8~69) winsize 62
5053 23:50:43.472727 [CA 2] Center 35 (5~66) winsize 62
5054 23:50:43.476269 [CA 3] Center 34 (4~65) winsize 62
5055 23:50:43.479549 [CA 4] Center 34 (4~65) winsize 62
5056 23:50:43.482234 [CA 5] Center 33 (3~64) winsize 62
5057 23:50:43.482716
5058 23:50:43.486003 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5059 23:50:43.486580
5060 23:50:43.488839 [CATrainingPosCal] consider 1 rank data
5061 23:50:43.492322 u2DelayCellTimex100 = 270/100 ps
5062 23:50:43.495671 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5063 23:50:43.499063 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5064 23:50:43.502233 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5065 23:50:43.505953 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5066 23:50:43.508977 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5067 23:50:43.512443 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5068 23:50:43.512953
5069 23:50:43.515699 CA PerBit enable=1, Macro0, CA PI delay=33
5070 23:50:43.519167
5071 23:50:43.519688 [CBTSetCACLKResult] CA Dly = 33
5072 23:50:43.522608 CS Dly: 7 (0~38)
5073 23:50:43.523322 ==
5074 23:50:43.525663 Dram Type= 6, Freq= 0, CH_0, rank 1
5075 23:50:43.529068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 23:50:43.529551 ==
5077 23:50:43.535452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 23:50:43.542299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5079 23:50:43.545826 [CA 0] Center 38 (8~69) winsize 62
5080 23:50:43.548867 [CA 1] Center 38 (8~69) winsize 62
5081 23:50:43.552440 [CA 2] Center 36 (6~66) winsize 61
5082 23:50:43.556261 [CA 3] Center 35 (5~66) winsize 62
5083 23:50:43.559205 [CA 4] Center 34 (4~65) winsize 62
5084 23:50:43.562739 [CA 5] Center 34 (4~64) winsize 61
5085 23:50:43.563300
5086 23:50:43.565973 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5087 23:50:43.566545
5088 23:50:43.569214 [CATrainingPosCal] consider 2 rank data
5089 23:50:43.572645 u2DelayCellTimex100 = 270/100 ps
5090 23:50:43.576006 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5091 23:50:43.579110 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5092 23:50:43.582450 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5093 23:50:43.585882 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5094 23:50:43.588721 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5095 23:50:43.592490 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5096 23:50:43.593092
5097 23:50:43.598983 CA PerBit enable=1, Macro0, CA PI delay=34
5098 23:50:43.599449
5099 23:50:43.599818 [CBTSetCACLKResult] CA Dly = 34
5100 23:50:43.602524 CS Dly: 7 (0~39)
5101 23:50:43.603084
5102 23:50:43.605520 ----->DramcWriteLeveling(PI) begin...
5103 23:50:43.605992 ==
5104 23:50:43.608610 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 23:50:43.612260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 23:50:43.612892 ==
5107 23:50:43.615289 Write leveling (Byte 0): 34 => 34
5108 23:50:43.618632 Write leveling (Byte 1): 28 => 28
5109 23:50:43.622538 DramcWriteLeveling(PI) end<-----
5110 23:50:43.623161
5111 23:50:43.623551 ==
5112 23:50:43.625604 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 23:50:43.628857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 23:50:43.632459 ==
5115 23:50:43.633072 [Gating] SW mode calibration
5116 23:50:43.642160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5117 23:50:43.645504 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5118 23:50:43.648863 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5119 23:50:43.655371 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 23:50:43.658856 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 23:50:43.662348 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 23:50:43.669140 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 23:50:43.672588 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 23:50:43.675560 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5125 23:50:43.682285 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
5126 23:50:43.685450 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5127 23:50:43.689033 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 23:50:43.695734 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 23:50:43.698563 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 23:50:43.701965 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 23:50:43.708801 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 23:50:43.712309 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5133 23:50:43.715391 0 15 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
5134 23:50:43.722273 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5135 23:50:43.725371 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 23:50:43.728771 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 23:50:43.732299 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 23:50:43.738573 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 23:50:43.741715 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 23:50:43.745433 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 23:50:43.752020 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 23:50:43.755598 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 23:50:43.758725 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 23:50:43.765510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 23:50:43.768637 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 23:50:43.771891 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 23:50:43.778921 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 23:50:43.781759 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 23:50:43.785192 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 23:50:43.791854 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 23:50:43.795305 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 23:50:43.798245 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 23:50:43.805247 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 23:50:43.808320 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:50:43.811823 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:50:43.818613 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5157 23:50:43.821933 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 23:50:43.825044 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5159 23:50:43.828583 Total UI for P1: 0, mck2ui 16
5160 23:50:43.831957 best dqsien dly found for B0: ( 1, 2, 26)
5161 23:50:43.838450 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 23:50:43.839024 Total UI for P1: 0, mck2ui 16
5163 23:50:43.841557 best dqsien dly found for B1: ( 1, 3, 0)
5164 23:50:43.848504 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5165 23:50:43.851601 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5166 23:50:43.852177
5167 23:50:43.854867 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5168 23:50:43.858139 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5169 23:50:43.861626 [Gating] SW calibration Done
5170 23:50:43.862192 ==
5171 23:50:43.865067 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 23:50:43.868510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 23:50:43.869101 ==
5174 23:50:43.871711 RX Vref Scan: 0
5175 23:50:43.872269
5176 23:50:43.872679 RX Vref 0 -> 0, step: 1
5177 23:50:43.873031
5178 23:50:43.875123 RX Delay -80 -> 252, step: 8
5179 23:50:43.878271 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5180 23:50:43.884844 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5181 23:50:43.888210 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5182 23:50:43.891533 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5183 23:50:43.895139 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5184 23:50:43.897900 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5185 23:50:43.901104 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5186 23:50:43.907940 iDelay=208, Bit 7, Center 119 (32 ~ 207) 176
5187 23:50:43.911668 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5188 23:50:43.914636 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5189 23:50:43.918458 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5190 23:50:43.921310 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5191 23:50:43.924626 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5192 23:50:43.928368 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5193 23:50:43.934759 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5194 23:50:43.937934 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5195 23:50:43.938404 ==
5196 23:50:43.941280 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 23:50:43.944731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 23:50:43.945318 ==
5199 23:50:43.948004 DQS Delay:
5200 23:50:43.948606 DQS0 = 0, DQS1 = 0
5201 23:50:43.948995 DQM Delay:
5202 23:50:43.951173 DQM0 = 106, DQM1 = 90
5203 23:50:43.951701 DQ Delay:
5204 23:50:43.954842 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5205 23:50:43.957920 DQ4 =107, DQ5 =95, DQ6 =119, DQ7 =119
5206 23:50:43.961375 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5207 23:50:43.964702 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5208 23:50:43.965264
5209 23:50:43.965643
5210 23:50:43.965991 ==
5211 23:50:43.968236 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 23:50:43.974635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 23:50:43.975199 ==
5214 23:50:43.975578
5215 23:50:43.975926
5216 23:50:43.976257 TX Vref Scan disable
5217 23:50:43.978637 == TX Byte 0 ==
5218 23:50:43.981589 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5219 23:50:43.988656 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5220 23:50:43.989222 == TX Byte 1 ==
5221 23:50:43.991687 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5222 23:50:43.998213 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5223 23:50:43.998767 ==
5224 23:50:44.001198 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 23:50:44.005171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 23:50:44.005739 ==
5227 23:50:44.006112
5228 23:50:44.006454
5229 23:50:44.007957 TX Vref Scan disable
5230 23:50:44.008420 == TX Byte 0 ==
5231 23:50:44.014923 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5232 23:50:44.017944 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5233 23:50:44.018411 == TX Byte 1 ==
5234 23:50:44.024983 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5235 23:50:44.028289 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5236 23:50:44.028910
5237 23:50:44.029292 [DATLAT]
5238 23:50:44.031378 Freq=933, CH0 RK0
5239 23:50:44.031938
5240 23:50:44.032308 DATLAT Default: 0xd
5241 23:50:44.034469 0, 0xFFFF, sum = 0
5242 23:50:44.034941 1, 0xFFFF, sum = 0
5243 23:50:44.037737 2, 0xFFFF, sum = 0
5244 23:50:44.040969 3, 0xFFFF, sum = 0
5245 23:50:44.041437 4, 0xFFFF, sum = 0
5246 23:50:44.044451 5, 0xFFFF, sum = 0
5247 23:50:44.045076 6, 0xFFFF, sum = 0
5248 23:50:44.048201 7, 0xFFFF, sum = 0
5249 23:50:44.048814 8, 0xFFFF, sum = 0
5250 23:50:44.050954 9, 0xFFFF, sum = 0
5251 23:50:44.051423 10, 0x0, sum = 1
5252 23:50:44.054582 11, 0x0, sum = 2
5253 23:50:44.055167 12, 0x0, sum = 3
5254 23:50:44.055552 13, 0x0, sum = 4
5255 23:50:44.057824 best_step = 11
5256 23:50:44.058282
5257 23:50:44.058649 ==
5258 23:50:44.061283 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 23:50:44.064727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 23:50:44.065288 ==
5261 23:50:44.068231 RX Vref Scan: 1
5262 23:50:44.068834
5263 23:50:44.071077 RX Vref 0 -> 0, step: 1
5264 23:50:44.071716
5265 23:50:44.072094 RX Delay -53 -> 252, step: 4
5266 23:50:44.072443
5267 23:50:44.074114 Set Vref, RX VrefLevel [Byte0]: 58
5268 23:50:44.077484 [Byte1]: 50
5269 23:50:44.082282
5270 23:50:44.082846 Final RX Vref Byte 0 = 58 to rank0
5271 23:50:44.085794 Final RX Vref Byte 1 = 50 to rank0
5272 23:50:44.088769 Final RX Vref Byte 0 = 58 to rank1
5273 23:50:44.092636 Final RX Vref Byte 1 = 50 to rank1==
5274 23:50:44.095723 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 23:50:44.102486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 23:50:44.103069 ==
5277 23:50:44.103453 DQS Delay:
5278 23:50:44.103810 DQS0 = 0, DQS1 = 0
5279 23:50:44.105244 DQM Delay:
5280 23:50:44.105720 DQM0 = 108, DQM1 = 92
5281 23:50:44.108771 DQ Delay:
5282 23:50:44.112525 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5283 23:50:44.115432 DQ4 =108, DQ5 =98, DQ6 =120, DQ7 =114
5284 23:50:44.119155 DQ8 =86, DQ9 =78, DQ10 =90, DQ11 =90
5285 23:50:44.122217 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5286 23:50:44.122793
5287 23:50:44.123170
5288 23:50:44.128796 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5289 23:50:44.132070 CH0 RK0: MR19=505, MR18=2723
5290 23:50:44.138847 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5291 23:50:44.139324
5292 23:50:44.142078 ----->DramcWriteLeveling(PI) begin...
5293 23:50:44.142561 ==
5294 23:50:44.145401 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 23:50:44.148862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 23:50:44.149326 ==
5297 23:50:44.151896 Write leveling (Byte 0): 31 => 31
5298 23:50:44.155001 Write leveling (Byte 1): 30 => 30
5299 23:50:44.158463 DramcWriteLeveling(PI) end<-----
5300 23:50:44.158923
5301 23:50:44.159288 ==
5302 23:50:44.161790 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 23:50:44.165293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 23:50:44.168798 ==
5305 23:50:44.169355 [Gating] SW mode calibration
5306 23:50:44.178911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 23:50:44.182089 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 23:50:44.185337 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 23:50:44.192053 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 23:50:44.195258 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 23:50:44.198680 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 23:50:44.205006 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 23:50:44.208571 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 23:50:44.211657 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5315 23:50:44.218474 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (1 0)
5316 23:50:44.222217 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 23:50:44.225197 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 23:50:44.231840 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 23:50:44.235182 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 23:50:44.238523 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 23:50:44.245421 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 23:50:44.248696 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5323 23:50:44.251733 0 15 28 | B1->B0 | 3b3b 4242 | 1 0 | (0 0) (0 0)
5324 23:50:44.258467 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 23:50:44.262028 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 23:50:44.265281 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 23:50:44.268847 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 23:50:44.275422 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 23:50:44.278801 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 23:50:44.281820 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 23:50:44.288923 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5332 23:50:44.292127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 23:50:44.295713 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 23:50:44.301857 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 23:50:44.304999 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 23:50:44.308621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 23:50:44.315496 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 23:50:44.318941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 23:50:44.322032 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 23:50:44.328803 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 23:50:44.332058 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 23:50:44.335687 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 23:50:44.342045 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 23:50:44.345332 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:50:44.348441 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:50:44.354973 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5347 23:50:44.358625 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5348 23:50:44.361621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 23:50:44.365355 Total UI for P1: 0, mck2ui 16
5350 23:50:44.368654 best dqsien dly found for B0: ( 1, 2, 26)
5351 23:50:44.372142 Total UI for P1: 0, mck2ui 16
5352 23:50:44.375174 best dqsien dly found for B1: ( 1, 2, 26)
5353 23:50:44.378466 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5354 23:50:44.381628 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5355 23:50:44.382187
5356 23:50:44.385142 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5357 23:50:44.391425 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5358 23:50:44.391967 [Gating] SW calibration Done
5359 23:50:44.392331 ==
5360 23:50:44.395068 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 23:50:44.401643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 23:50:44.402196 ==
5363 23:50:44.402561 RX Vref Scan: 0
5364 23:50:44.402897
5365 23:50:44.404754 RX Vref 0 -> 0, step: 1
5366 23:50:44.405216
5367 23:50:44.408680 RX Delay -80 -> 252, step: 8
5368 23:50:44.411722 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5369 23:50:44.414767 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5370 23:50:44.418475 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5371 23:50:44.421335 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5372 23:50:44.428599 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5373 23:50:44.431709 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5374 23:50:44.435011 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5375 23:50:44.438160 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5376 23:50:44.441411 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5377 23:50:44.444690 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5378 23:50:44.451139 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5379 23:50:44.454810 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5380 23:50:44.458312 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5381 23:50:44.461328 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5382 23:50:44.464824 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5383 23:50:44.471424 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5384 23:50:44.471991 ==
5385 23:50:44.474405 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 23:50:44.478199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 23:50:44.478775 ==
5388 23:50:44.479158 DQS Delay:
5389 23:50:44.481468 DQS0 = 0, DQS1 = 0
5390 23:50:44.481936 DQM Delay:
5391 23:50:44.484188 DQM0 = 104, DQM1 = 90
5392 23:50:44.484734 DQ Delay:
5393 23:50:44.487881 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5394 23:50:44.491179 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5395 23:50:44.494836 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =83
5396 23:50:44.498020 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5397 23:50:44.498583
5398 23:50:44.498963
5399 23:50:44.499311 ==
5400 23:50:44.500965 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 23:50:44.504579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 23:50:44.507940 ==
5403 23:50:44.508526
5404 23:50:44.508994
5405 23:50:44.509349 TX Vref Scan disable
5406 23:50:44.511417 == TX Byte 0 ==
5407 23:50:44.514561 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5408 23:50:44.517974 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5409 23:50:44.521218 == TX Byte 1 ==
5410 23:50:44.524838 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5411 23:50:44.527882 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5412 23:50:44.528450 ==
5413 23:50:44.531423 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 23:50:44.537673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 23:50:44.538242 ==
5416 23:50:44.538626
5417 23:50:44.538972
5418 23:50:44.539304 TX Vref Scan disable
5419 23:50:44.542147 == TX Byte 0 ==
5420 23:50:44.545247 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5421 23:50:44.548625 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5422 23:50:44.551690 == TX Byte 1 ==
5423 23:50:44.555035 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5424 23:50:44.561733 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5425 23:50:44.562272
5426 23:50:44.562643 [DATLAT]
5427 23:50:44.563231 Freq=933, CH0 RK1
5428 23:50:44.563580
5429 23:50:44.564998 DATLAT Default: 0xb
5430 23:50:44.565462 0, 0xFFFF, sum = 0
5431 23:50:44.568482 1, 0xFFFF, sum = 0
5432 23:50:44.568986 2, 0xFFFF, sum = 0
5433 23:50:44.571796 3, 0xFFFF, sum = 0
5434 23:50:44.572266 4, 0xFFFF, sum = 0
5435 23:50:44.575521 5, 0xFFFF, sum = 0
5436 23:50:44.576050 6, 0xFFFF, sum = 0
5437 23:50:44.578534 7, 0xFFFF, sum = 0
5438 23:50:44.581835 8, 0xFFFF, sum = 0
5439 23:50:44.582332 9, 0xFFFF, sum = 0
5440 23:50:44.585193 10, 0x0, sum = 1
5441 23:50:44.585692 11, 0x0, sum = 2
5442 23:50:44.586364 12, 0x0, sum = 3
5443 23:50:44.588353 13, 0x0, sum = 4
5444 23:50:44.588775 best_step = 11
5445 23:50:44.589122
5446 23:50:44.589451 ==
5447 23:50:44.592127 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 23:50:44.598627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 23:50:44.599195 ==
5450 23:50:44.599573 RX Vref Scan: 0
5451 23:50:44.599919
5452 23:50:44.602146 RX Vref 0 -> 0, step: 1
5453 23:50:44.602645
5454 23:50:44.605143 RX Delay -53 -> 252, step: 4
5455 23:50:44.608877 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5456 23:50:44.615322 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5457 23:50:44.618582 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5458 23:50:44.621698 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5459 23:50:44.625257 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5460 23:50:44.628661 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5461 23:50:44.632073 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5462 23:50:44.638681 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5463 23:50:44.641923 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5464 23:50:44.645626 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5465 23:50:44.648324 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5466 23:50:44.651981 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5467 23:50:44.658572 iDelay=199, Bit 12, Center 100 (15 ~ 186) 172
5468 23:50:44.661678 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5469 23:50:44.665228 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5470 23:50:44.668685 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5471 23:50:44.669248 ==
5472 23:50:44.671838 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 23:50:44.675266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 23:50:44.678931 ==
5475 23:50:44.679508 DQS Delay:
5476 23:50:44.679886 DQS0 = 0, DQS1 = 0
5477 23:50:44.681915 DQM Delay:
5478 23:50:44.682386 DQM0 = 104, DQM1 = 92
5479 23:50:44.685200 DQ Delay:
5480 23:50:44.688758 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5481 23:50:44.691960 DQ4 =104, DQ5 =100, DQ6 =112, DQ7 =112
5482 23:50:44.695029 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =92
5483 23:50:44.698640 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =98
5484 23:50:44.699208
5485 23:50:44.699581
5486 23:50:44.705267 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5487 23:50:44.708269 CH0 RK1: MR19=505, MR18=2C0C
5488 23:50:44.715234 CH0_RK1: MR19=0x505, MR18=0x2C0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5489 23:50:44.718667 [RxdqsGatingPostProcess] freq 933
5490 23:50:44.725455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 23:50:44.726018 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 23:50:44.728296 best DQS1 dly(2T, 0.5T) = (0, 11)
5493 23:50:44.731839 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 23:50:44.735112 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5495 23:50:44.738651 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 23:50:44.741441 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 23:50:44.745414 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 23:50:44.748238 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 23:50:44.751733 Pre-setting of DQS Precalculation
5500 23:50:44.755190 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 23:50:44.758164 ==
5502 23:50:44.761605 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 23:50:44.764934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 23:50:44.765498 ==
5505 23:50:44.768384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 23:50:44.775094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5507 23:50:44.778781 [CA 0] Center 37 (7~68) winsize 62
5508 23:50:44.781675 [CA 1] Center 37 (7~68) winsize 62
5509 23:50:44.785464 [CA 2] Center 36 (6~66) winsize 61
5510 23:50:44.788438 [CA 3] Center 34 (4~65) winsize 62
5511 23:50:44.791780 [CA 4] Center 34 (4~65) winsize 62
5512 23:50:44.795380 [CA 5] Center 34 (4~65) winsize 62
5513 23:50:44.795973
5514 23:50:44.798768 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5515 23:50:44.799352
5516 23:50:44.801808 [CATrainingPosCal] consider 1 rank data
5517 23:50:44.804955 u2DelayCellTimex100 = 270/100 ps
5518 23:50:44.808503 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5519 23:50:44.811907 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5520 23:50:44.818607 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5521 23:50:44.821581 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5522 23:50:44.825348 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5523 23:50:44.828463 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5524 23:50:44.829073
5525 23:50:44.831639 CA PerBit enable=1, Macro0, CA PI delay=34
5526 23:50:44.832223
5527 23:50:44.835118 [CBTSetCACLKResult] CA Dly = 34
5528 23:50:44.835690 CS Dly: 7 (0~38)
5529 23:50:44.838599 ==
5530 23:50:44.841496 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 23:50:44.844947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 23:50:44.845524 ==
5533 23:50:44.848440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 23:50:44.855262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 23:50:44.858936 [CA 0] Center 38 (8~69) winsize 62
5536 23:50:44.861760 [CA 1] Center 38 (8~69) winsize 62
5537 23:50:44.865262 [CA 2] Center 35 (5~66) winsize 62
5538 23:50:44.868180 [CA 3] Center 35 (5~65) winsize 61
5539 23:50:44.871941 [CA 4] Center 35 (5~65) winsize 61
5540 23:50:44.875083 [CA 5] Center 35 (5~65) winsize 61
5541 23:50:44.875665
5542 23:50:44.878170 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 23:50:44.878644
5544 23:50:44.881805 [CATrainingPosCal] consider 2 rank data
5545 23:50:44.885013 u2DelayCellTimex100 = 270/100 ps
5546 23:50:44.888341 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5547 23:50:44.895260 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5548 23:50:44.898575 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5549 23:50:44.901591 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5550 23:50:44.904873 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5551 23:50:44.908513 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5552 23:50:44.909110
5553 23:50:44.911906 CA PerBit enable=1, Macro0, CA PI delay=35
5554 23:50:44.912474
5555 23:50:44.915283 [CBTSetCACLKResult] CA Dly = 35
5556 23:50:44.915845 CS Dly: 7 (0~39)
5557 23:50:44.918145
5558 23:50:44.921442 ----->DramcWriteLeveling(PI) begin...
5559 23:50:44.922044 ==
5560 23:50:44.924994 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 23:50:44.928329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 23:50:44.928946 ==
5563 23:50:44.931644 Write leveling (Byte 0): 28 => 28
5564 23:50:44.934759 Write leveling (Byte 1): 30 => 30
5565 23:50:44.938202 DramcWriteLeveling(PI) end<-----
5566 23:50:44.938672
5567 23:50:44.939043 ==
5568 23:50:44.941248 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 23:50:44.944880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 23:50:44.945349 ==
5571 23:50:44.948671 [Gating] SW mode calibration
5572 23:50:44.954886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 23:50:44.961469 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 23:50:44.964946 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 23:50:44.968377 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 23:50:44.974997 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 23:50:44.978279 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 23:50:44.981257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 23:50:44.988159 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5580 23:50:44.991290 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
5581 23:50:44.994884 0 14 28 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
5582 23:50:44.998311 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 23:50:45.004586 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 23:50:45.008132 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 23:50:45.011576 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 23:50:45.018165 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 23:50:45.021419 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 23:50:45.024755 0 15 24 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)
5589 23:50:45.031394 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5590 23:50:45.035016 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 23:50:45.038216 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 23:50:45.045158 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 23:50:45.048180 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 23:50:45.051341 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 23:50:45.058140 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5596 23:50:45.061492 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5597 23:50:45.065062 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 23:50:45.071350 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 23:50:45.074648 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 23:50:45.078167 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 23:50:45.084617 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 23:50:45.087761 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 23:50:45.091293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 23:50:45.097830 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 23:50:45.101158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 23:50:45.104619 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 23:50:45.111255 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 23:50:45.114410 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 23:50:45.117424 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 23:50:45.124461 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:50:45.127841 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:50:45.130860 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5613 23:50:45.137531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 23:50:45.138157 Total UI for P1: 0, mck2ui 16
5615 23:50:45.140803 best dqsien dly found for B0: ( 1, 2, 24)
5616 23:50:45.144342 Total UI for P1: 0, mck2ui 16
5617 23:50:45.147978 best dqsien dly found for B1: ( 1, 2, 26)
5618 23:50:45.150985 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5619 23:50:45.154630 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5620 23:50:45.157553
5621 23:50:45.161169 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5622 23:50:45.164498 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5623 23:50:45.167517 [Gating] SW calibration Done
5624 23:50:45.168080 ==
5625 23:50:45.171248 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 23:50:45.174286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 23:50:45.174857 ==
5628 23:50:45.175235 RX Vref Scan: 0
5629 23:50:45.175587
5630 23:50:45.177636 RX Vref 0 -> 0, step: 1
5631 23:50:45.178193
5632 23:50:45.181126 RX Delay -80 -> 252, step: 8
5633 23:50:45.184385 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5634 23:50:45.187374 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5635 23:50:45.194302 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5636 23:50:45.197516 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5637 23:50:45.200679 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5638 23:50:45.204064 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5639 23:50:45.207548 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5640 23:50:45.210927 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5641 23:50:45.213987 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5642 23:50:45.220996 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5643 23:50:45.223850 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5644 23:50:45.227320 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5645 23:50:45.230895 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5646 23:50:45.234437 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5647 23:50:45.241080 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5648 23:50:45.243732 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5649 23:50:45.244198 ==
5650 23:50:45.247535 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 23:50:45.250683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 23:50:45.251249 ==
5653 23:50:45.251628 DQS Delay:
5654 23:50:45.253964 DQS0 = 0, DQS1 = 0
5655 23:50:45.254449 DQM Delay:
5656 23:50:45.257376 DQM0 = 101, DQM1 = 95
5657 23:50:45.257940 DQ Delay:
5658 23:50:45.260832 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5659 23:50:45.264531 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5660 23:50:45.267581 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5661 23:50:45.271142 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5662 23:50:45.271711
5663 23:50:45.272084
5664 23:50:45.272424 ==
5665 23:50:45.274315 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 23:50:45.280653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 23:50:45.281223 ==
5668 23:50:45.281598
5669 23:50:45.281942
5670 23:50:45.282273 TX Vref Scan disable
5671 23:50:45.283827 == TX Byte 0 ==
5672 23:50:45.287224 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5673 23:50:45.293837 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5674 23:50:45.294314 == TX Byte 1 ==
5675 23:50:45.297130 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5676 23:50:45.303559 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5677 23:50:45.304109 ==
5678 23:50:45.306892 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 23:50:45.310200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 23:50:45.310669 ==
5681 23:50:45.311042
5682 23:50:45.311387
5683 23:50:45.314016 TX Vref Scan disable
5684 23:50:45.314483 == TX Byte 0 ==
5685 23:50:45.320210 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5686 23:50:45.323602 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5687 23:50:45.324071 == TX Byte 1 ==
5688 23:50:45.330621 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5689 23:50:45.333820 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5690 23:50:45.334406
5691 23:50:45.334785 [DATLAT]
5692 23:50:45.337027 Freq=933, CH1 RK0
5693 23:50:45.337592
5694 23:50:45.337964 DATLAT Default: 0xd
5695 23:50:45.340371 0, 0xFFFF, sum = 0
5696 23:50:45.340969 1, 0xFFFF, sum = 0
5697 23:50:45.343622 2, 0xFFFF, sum = 0
5698 23:50:45.344096 3, 0xFFFF, sum = 0
5699 23:50:45.347073 4, 0xFFFF, sum = 0
5700 23:50:45.350722 5, 0xFFFF, sum = 0
5701 23:50:45.351293 6, 0xFFFF, sum = 0
5702 23:50:45.353833 7, 0xFFFF, sum = 0
5703 23:50:45.354412 8, 0xFFFF, sum = 0
5704 23:50:45.358620 9, 0xFFFF, sum = 0
5705 23:50:45.359091 10, 0x0, sum = 1
5706 23:50:45.360302 11, 0x0, sum = 2
5707 23:50:45.360806 12, 0x0, sum = 3
5708 23:50:45.361190 13, 0x0, sum = 4
5709 23:50:45.363764 best_step = 11
5710 23:50:45.364327
5711 23:50:45.364738 ==
5712 23:50:45.366747 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 23:50:45.370549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 23:50:45.371120 ==
5715 23:50:45.373414 RX Vref Scan: 1
5716 23:50:45.373884
5717 23:50:45.374254 RX Vref 0 -> 0, step: 1
5718 23:50:45.376763
5719 23:50:45.377322 RX Delay -53 -> 252, step: 4
5720 23:50:45.377695
5721 23:50:45.380369 Set Vref, RX VrefLevel [Byte0]: 51
5722 23:50:45.383463 [Byte1]: 57
5723 23:50:45.387843
5724 23:50:45.388412 Final RX Vref Byte 0 = 51 to rank0
5725 23:50:45.391038 Final RX Vref Byte 1 = 57 to rank0
5726 23:50:45.394370 Final RX Vref Byte 0 = 51 to rank1
5727 23:50:45.397984 Final RX Vref Byte 1 = 57 to rank1==
5728 23:50:45.401266 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 23:50:45.407466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 23:50:45.408019 ==
5731 23:50:45.408388 DQS Delay:
5732 23:50:45.408786 DQS0 = 0, DQS1 = 0
5733 23:50:45.411324 DQM Delay:
5734 23:50:45.411890 DQM0 = 104, DQM1 = 97
5735 23:50:45.414666 DQ Delay:
5736 23:50:45.418042 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5737 23:50:45.420813 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =104
5738 23:50:45.424367 DQ8 =90, DQ9 =84, DQ10 =98, DQ11 =94
5739 23:50:45.427831 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5740 23:50:45.428412
5741 23:50:45.428845
5742 23:50:45.434538 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5743 23:50:45.437803 CH1 RK0: MR19=505, MR18=1C35
5744 23:50:45.444197 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5745 23:50:45.444777
5746 23:50:45.447614 ----->DramcWriteLeveling(PI) begin...
5747 23:50:45.448187 ==
5748 23:50:45.450923 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 23:50:45.454116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 23:50:45.454586 ==
5751 23:50:45.457252 Write leveling (Byte 0): 26 => 26
5752 23:50:45.461169 Write leveling (Byte 1): 30 => 30
5753 23:50:45.464400 DramcWriteLeveling(PI) end<-----
5754 23:50:45.464992
5755 23:50:45.465365 ==
5756 23:50:45.467486 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 23:50:45.471065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 23:50:45.474136 ==
5759 23:50:45.474702 [Gating] SW mode calibration
5760 23:50:45.484221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5761 23:50:45.487854 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5762 23:50:45.490764 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5763 23:50:45.497719 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 23:50:45.500926 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 23:50:45.504239 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 23:50:45.510813 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 23:50:45.514536 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 23:50:45.517443 0 14 24 | B1->B0 | 3030 3333 | 1 1 | (1 0) (1 1)
5769 23:50:45.523713 0 14 28 | B1->B0 | 2525 2929 | 0 0 | (0 0) (1 1)
5770 23:50:45.527500 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5771 23:50:45.530665 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 23:50:45.537501 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 23:50:45.540993 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 23:50:45.543942 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 23:50:45.550742 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 23:50:45.554270 0 15 24 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (0 0)
5777 23:50:45.557170 0 15 28 | B1->B0 | 4343 3636 | 0 1 | (0 0) (0 0)
5778 23:50:45.564077 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 23:50:45.567605 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 23:50:45.571190 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 23:50:45.574311 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 23:50:45.580985 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 23:50:45.584141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 23:50:45.587773 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5785 23:50:45.593806 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5786 23:50:45.597564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 23:50:45.600473 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 23:50:45.607117 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 23:50:45.610377 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 23:50:45.613779 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 23:50:45.620360 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 23:50:45.623815 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 23:50:45.626917 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 23:50:45.633449 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 23:50:45.636779 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 23:50:45.640195 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 23:50:45.646758 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 23:50:45.649847 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 23:50:45.652972 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:50:45.659998 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5801 23:50:45.663641 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 23:50:45.666934 Total UI for P1: 0, mck2ui 16
5803 23:50:45.670410 best dqsien dly found for B0: ( 1, 2, 24)
5804 23:50:45.673362 Total UI for P1: 0, mck2ui 16
5805 23:50:45.677148 best dqsien dly found for B1: ( 1, 2, 26)
5806 23:50:45.680276 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5807 23:50:45.683484 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5808 23:50:45.684071
5809 23:50:45.687003 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5810 23:50:45.690111 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 23:50:45.693509 [Gating] SW calibration Done
5812 23:50:45.694080 ==
5813 23:50:45.696908 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 23:50:45.700029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 23:50:45.703296 ==
5816 23:50:45.703861 RX Vref Scan: 0
5817 23:50:45.704243
5818 23:50:45.706558 RX Vref 0 -> 0, step: 1
5819 23:50:45.707029
5820 23:50:45.709454 RX Delay -80 -> 252, step: 8
5821 23:50:45.712934 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5822 23:50:45.716395 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5823 23:50:45.719766 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5824 23:50:45.723006 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5825 23:50:45.726435 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5826 23:50:45.732807 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5827 23:50:45.736296 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5828 23:50:45.739750 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5829 23:50:45.742951 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5830 23:50:45.745997 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5831 23:50:45.749691 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5832 23:50:45.756629 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5833 23:50:45.759293 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5834 23:50:45.763174 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5835 23:50:45.766248 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5836 23:50:45.769412 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5837 23:50:45.772948 ==
5838 23:50:45.776014 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 23:50:45.779638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 23:50:45.780207 ==
5841 23:50:45.780612 DQS Delay:
5842 23:50:45.782381 DQS0 = 0, DQS1 = 0
5843 23:50:45.782844 DQM Delay:
5844 23:50:45.785773 DQM0 = 102, DQM1 = 95
5845 23:50:45.786259 DQ Delay:
5846 23:50:45.789017 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5847 23:50:45.792485 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =99
5848 23:50:45.796072 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5849 23:50:45.799399 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5850 23:50:45.799965
5851 23:50:45.800341
5852 23:50:45.800740 ==
5853 23:50:45.802636 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 23:50:45.805934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 23:50:45.806405 ==
5856 23:50:45.809417
5857 23:50:45.809912
5858 23:50:45.810284 TX Vref Scan disable
5859 23:50:45.812404 == TX Byte 0 ==
5860 23:50:45.816008 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5861 23:50:45.818977 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5862 23:50:45.822476 == TX Byte 1 ==
5863 23:50:45.826224 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5864 23:50:45.829021 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5865 23:50:45.829490 ==
5866 23:50:45.832508 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 23:50:45.839267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 23:50:45.839858 ==
5869 23:50:45.840240
5870 23:50:45.840611
5871 23:50:45.840950 TX Vref Scan disable
5872 23:50:45.843324 == TX Byte 0 ==
5873 23:50:45.846844 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5874 23:50:45.853633 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5875 23:50:45.854198 == TX Byte 1 ==
5876 23:50:45.856952 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5877 23:50:45.863445 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5878 23:50:45.864013
5879 23:50:45.864388 [DATLAT]
5880 23:50:45.864775 Freq=933, CH1 RK1
5881 23:50:45.865116
5882 23:50:45.866864 DATLAT Default: 0xb
5883 23:50:45.867425 0, 0xFFFF, sum = 0
5884 23:50:45.870035 1, 0xFFFF, sum = 0
5885 23:50:45.870609 2, 0xFFFF, sum = 0
5886 23:50:45.873609 3, 0xFFFF, sum = 0
5887 23:50:45.876810 4, 0xFFFF, sum = 0
5888 23:50:45.877380 5, 0xFFFF, sum = 0
5889 23:50:45.880428 6, 0xFFFF, sum = 0
5890 23:50:45.881018 7, 0xFFFF, sum = 0
5891 23:50:45.883553 8, 0xFFFF, sum = 0
5892 23:50:45.884120 9, 0xFFFF, sum = 0
5893 23:50:45.886361 10, 0x0, sum = 1
5894 23:50:45.886833 11, 0x0, sum = 2
5895 23:50:45.890116 12, 0x0, sum = 3
5896 23:50:45.890689 13, 0x0, sum = 4
5897 23:50:45.891070 best_step = 11
5898 23:50:45.891417
5899 23:50:45.893177 ==
5900 23:50:45.893710 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 23:50:45.899993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 23:50:45.900600 ==
5903 23:50:45.900983 RX Vref Scan: 0
5904 23:50:45.901331
5905 23:50:45.903452 RX Vref 0 -> 0, step: 1
5906 23:50:45.904013
5907 23:50:45.906880 RX Delay -53 -> 252, step: 4
5908 23:50:45.910044 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5909 23:50:45.916683 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5910 23:50:45.919776 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5911 23:50:45.923103 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5912 23:50:45.927163 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5913 23:50:45.929909 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5914 23:50:45.933742 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5915 23:50:45.940311 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5916 23:50:45.943320 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5917 23:50:45.947084 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5918 23:50:45.950102 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5919 23:50:45.953350 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5920 23:50:45.960240 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5921 23:50:45.963468 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5922 23:50:45.966868 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5923 23:50:45.970037 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5924 23:50:45.970605 ==
5925 23:50:45.973274 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 23:50:45.980301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 23:50:45.980910 ==
5928 23:50:45.981290 DQS Delay:
5929 23:50:45.981637 DQS0 = 0, DQS1 = 0
5930 23:50:45.983413 DQM Delay:
5931 23:50:45.983980 DQM0 = 104, DQM1 = 97
5932 23:50:45.986909 DQ Delay:
5933 23:50:45.990045 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5934 23:50:45.993385 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =100
5935 23:50:45.996903 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =94
5936 23:50:45.999876 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =104
5937 23:50:46.000441
5938 23:50:46.000861
5939 23:50:46.006182 [DQSOSCAuto] RK1, (LSB)MR18= 0x2501, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5940 23:50:46.009753 CH1 RK1: MR19=505, MR18=2501
5941 23:50:46.016516 CH1_RK1: MR19=0x505, MR18=0x2501, DQSOSC=410, MR23=63, INC=64, DEC=42
5942 23:50:46.019589 [RxdqsGatingPostProcess] freq 933
5943 23:50:46.026181 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5944 23:50:46.026735 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 23:50:46.029721 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 23:50:46.032874 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 23:50:46.036164 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 23:50:46.039649 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 23:50:46.043191 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 23:50:46.046057 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 23:50:46.049747 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 23:50:46.052924 Pre-setting of DQS Precalculation
5953 23:50:46.059756 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5954 23:50:46.066525 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5955 23:50:46.072752 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5956 23:50:46.073298
5957 23:50:46.073674
5958 23:50:46.075873 [Calibration Summary] 1866 Mbps
5959 23:50:46.076339 CH 0, Rank 0
5960 23:50:46.079577 SW Impedance : PASS
5961 23:50:46.082767 DUTY Scan : NO K
5962 23:50:46.083333 ZQ Calibration : PASS
5963 23:50:46.086003 Jitter Meter : NO K
5964 23:50:46.086469 CBT Training : PASS
5965 23:50:46.089621 Write leveling : PASS
5966 23:50:46.092669 RX DQS gating : PASS
5967 23:50:46.093132 RX DQ/DQS(RDDQC) : PASS
5968 23:50:46.096479 TX DQ/DQS : PASS
5969 23:50:46.099822 RX DATLAT : PASS
5970 23:50:46.100389 RX DQ/DQS(Engine): PASS
5971 23:50:46.103155 TX OE : NO K
5972 23:50:46.103725 All Pass.
5973 23:50:46.104102
5974 23:50:46.106112 CH 0, Rank 1
5975 23:50:46.106575 SW Impedance : PASS
5976 23:50:46.109607 DUTY Scan : NO K
5977 23:50:46.112614 ZQ Calibration : PASS
5978 23:50:46.113083 Jitter Meter : NO K
5979 23:50:46.116224 CBT Training : PASS
5980 23:50:46.119595 Write leveling : PASS
5981 23:50:46.120160 RX DQS gating : PASS
5982 23:50:46.123073 RX DQ/DQS(RDDQC) : PASS
5983 23:50:46.123535 TX DQ/DQS : PASS
5984 23:50:46.126059 RX DATLAT : PASS
5985 23:50:46.129450 RX DQ/DQS(Engine): PASS
5986 23:50:46.129992 TX OE : NO K
5987 23:50:46.132742 All Pass.
5988 23:50:46.133209
5989 23:50:46.133578 CH 1, Rank 0
5990 23:50:46.136097 SW Impedance : PASS
5991 23:50:46.136594 DUTY Scan : NO K
5992 23:50:46.139549 ZQ Calibration : PASS
5993 23:50:46.142913 Jitter Meter : NO K
5994 23:50:46.143475 CBT Training : PASS
5995 23:50:46.145883 Write leveling : PASS
5996 23:50:46.149517 RX DQS gating : PASS
5997 23:50:46.150256 RX DQ/DQS(RDDQC) : PASS
5998 23:50:46.152666 TX DQ/DQS : PASS
5999 23:50:46.156135 RX DATLAT : PASS
6000 23:50:46.156755 RX DQ/DQS(Engine): PASS
6001 23:50:46.159591 TX OE : NO K
6002 23:50:46.160159 All Pass.
6003 23:50:46.160620
6004 23:50:46.162581 CH 1, Rank 1
6005 23:50:46.163146 SW Impedance : PASS
6006 23:50:46.165596 DUTY Scan : NO K
6007 23:50:46.169456 ZQ Calibration : PASS
6008 23:50:46.170022 Jitter Meter : NO K
6009 23:50:46.172447 CBT Training : PASS
6010 23:50:46.176029 Write leveling : PASS
6011 23:50:46.176624 RX DQS gating : PASS
6012 23:50:46.179174 RX DQ/DQS(RDDQC) : PASS
6013 23:50:46.182302 TX DQ/DQS : PASS
6014 23:50:46.182781 RX DATLAT : PASS
6015 23:50:46.185991 RX DQ/DQS(Engine): PASS
6016 23:50:46.186558 TX OE : NO K
6017 23:50:46.188971 All Pass.
6018 23:50:46.189440
6019 23:50:46.189818 DramC Write-DBI off
6020 23:50:46.192317 PER_BANK_REFRESH: Hybrid Mode
6021 23:50:46.195863 TX_TRACKING: ON
6022 23:50:46.202582 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6023 23:50:46.205562 [FAST_K] Save calibration result to emmc
6024 23:50:46.212436 dramc_set_vcore_voltage set vcore to 650000
6025 23:50:46.213024 Read voltage for 400, 6
6026 23:50:46.213407 Vio18 = 0
6027 23:50:46.215817 Vcore = 650000
6028 23:50:46.216379 Vdram = 0
6029 23:50:46.216813 Vddq = 0
6030 23:50:46.219157 Vmddr = 0
6031 23:50:46.222544 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6032 23:50:46.228845 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6033 23:50:46.229414 MEM_TYPE=3, freq_sel=20
6034 23:50:46.232391 sv_algorithm_assistance_LP4_800
6035 23:50:46.239150 ============ PULL DRAM RESETB DOWN ============
6036 23:50:46.242246 ========== PULL DRAM RESETB DOWN end =========
6037 23:50:46.245560 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6038 23:50:46.249266 ===================================
6039 23:50:46.252714 LPDDR4 DRAM CONFIGURATION
6040 23:50:46.255736 ===================================
6041 23:50:46.258942 EX_ROW_EN[0] = 0x0
6042 23:50:46.259509 EX_ROW_EN[1] = 0x0
6043 23:50:46.262566 LP4Y_EN = 0x0
6044 23:50:46.263155 WORK_FSP = 0x0
6045 23:50:46.265312 WL = 0x2
6046 23:50:46.265985 RL = 0x2
6047 23:50:46.269150 BL = 0x2
6048 23:50:46.269713 RPST = 0x0
6049 23:50:46.272331 RD_PRE = 0x0
6050 23:50:46.272926 WR_PRE = 0x1
6051 23:50:46.275957 WR_PST = 0x0
6052 23:50:46.276524 DBI_WR = 0x0
6053 23:50:46.278973 DBI_RD = 0x0
6054 23:50:46.279538 OTF = 0x1
6055 23:50:46.282336 ===================================
6056 23:50:46.285581 ===================================
6057 23:50:46.289245 ANA top config
6058 23:50:46.292615 ===================================
6059 23:50:46.293180 DLL_ASYNC_EN = 0
6060 23:50:46.295434 ALL_SLAVE_EN = 1
6061 23:50:46.299257 NEW_RANK_MODE = 1
6062 23:50:46.302279 DLL_IDLE_MODE = 1
6063 23:50:46.305897 LP45_APHY_COMB_EN = 1
6064 23:50:46.306466 TX_ODT_DIS = 1
6065 23:50:46.309056 NEW_8X_MODE = 1
6066 23:50:46.312326 ===================================
6067 23:50:46.315642 ===================================
6068 23:50:46.319117 data_rate = 800
6069 23:50:46.322578 CKR = 1
6070 23:50:46.325711 DQ_P2S_RATIO = 4
6071 23:50:46.329125 ===================================
6072 23:50:46.329696 CA_P2S_RATIO = 4
6073 23:50:46.332313 DQ_CA_OPEN = 0
6074 23:50:46.335616 DQ_SEMI_OPEN = 1
6075 23:50:46.339188 CA_SEMI_OPEN = 1
6076 23:50:46.342072 CA_FULL_RATE = 0
6077 23:50:46.345402 DQ_CKDIV4_EN = 0
6078 23:50:46.345881 CA_CKDIV4_EN = 1
6079 23:50:46.348987 CA_PREDIV_EN = 0
6080 23:50:46.352176 PH8_DLY = 0
6081 23:50:46.355628 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6082 23:50:46.359156 DQ_AAMCK_DIV = 0
6083 23:50:46.362487 CA_AAMCK_DIV = 0
6084 23:50:46.363054 CA_ADMCK_DIV = 4
6085 23:50:46.365598 DQ_TRACK_CA_EN = 0
6086 23:50:46.369031 CA_PICK = 800
6087 23:50:46.372494 CA_MCKIO = 400
6088 23:50:46.375580 MCKIO_SEMI = 400
6089 23:50:46.379162 PLL_FREQ = 3016
6090 23:50:46.382199 DQ_UI_PI_RATIO = 32
6091 23:50:46.382763 CA_UI_PI_RATIO = 32
6092 23:50:46.385702 ===================================
6093 23:50:46.388769 ===================================
6094 23:50:46.392226 memory_type:LPDDR4
6095 23:50:46.395344 GP_NUM : 10
6096 23:50:46.395820 SRAM_EN : 1
6097 23:50:46.398769 MD32_EN : 0
6098 23:50:46.402313 ===================================
6099 23:50:46.405512 [ANA_INIT] >>>>>>>>>>>>>>
6100 23:50:46.408727 <<<<<< [CONFIGURE PHASE]: ANA_TX
6101 23:50:46.411930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6102 23:50:46.415632 ===================================
6103 23:50:46.416196 data_rate = 800,PCW = 0X7400
6104 23:50:46.418748 ===================================
6105 23:50:46.422269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6106 23:50:46.428949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 23:50:46.441829 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 23:50:46.445444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6109 23:50:46.448711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6110 23:50:46.451974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6111 23:50:46.455349 [ANA_INIT] flow start
6112 23:50:46.455821 [ANA_INIT] PLL >>>>>>>>
6113 23:50:46.458784 [ANA_INIT] PLL <<<<<<<<
6114 23:50:46.462108 [ANA_INIT] MIDPI >>>>>>>>
6115 23:50:46.462676 [ANA_INIT] MIDPI <<<<<<<<
6116 23:50:46.465303 [ANA_INIT] DLL >>>>>>>>
6117 23:50:46.469073 [ANA_INIT] flow end
6118 23:50:46.472023 ============ LP4 DIFF to SE enter ============
6119 23:50:46.475518 ============ LP4 DIFF to SE exit ============
6120 23:50:46.479134 [ANA_INIT] <<<<<<<<<<<<<
6121 23:50:46.482051 [Flow] Enable top DCM control >>>>>
6122 23:50:46.485680 [Flow] Enable top DCM control <<<<<
6123 23:50:46.488886 Enable DLL master slave shuffle
6124 23:50:46.492415 ==============================================================
6125 23:50:46.495472 Gating Mode config
6126 23:50:46.502034 ==============================================================
6127 23:50:46.502599 Config description:
6128 23:50:46.512118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6129 23:50:46.519117 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6130 23:50:46.522273 SELPH_MODE 0: By rank 1: By Phase
6131 23:50:46.529059 ==============================================================
6132 23:50:46.532095 GAT_TRACK_EN = 0
6133 23:50:46.535122 RX_GATING_MODE = 2
6134 23:50:46.538677 RX_GATING_TRACK_MODE = 2
6135 23:50:46.542137 SELPH_MODE = 1
6136 23:50:46.545129 PICG_EARLY_EN = 1
6137 23:50:46.545742 VALID_LAT_VALUE = 1
6138 23:50:46.551824 ==============================================================
6139 23:50:46.555079 Enter into Gating configuration >>>>
6140 23:50:46.559185 Exit from Gating configuration <<<<
6141 23:50:46.562061 Enter into DVFS_PRE_config >>>>>
6142 23:50:46.571890 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6143 23:50:46.575483 Exit from DVFS_PRE_config <<<<<
6144 23:50:46.578580 Enter into PICG configuration >>>>
6145 23:50:46.581893 Exit from PICG configuration <<<<
6146 23:50:46.585443 [RX_INPUT] configuration >>>>>
6147 23:50:46.588627 [RX_INPUT] configuration <<<<<
6148 23:50:46.592228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6149 23:50:46.599037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6150 23:50:46.605328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 23:50:46.611837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 23:50:46.618132 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 23:50:46.624972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 23:50:46.628125 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6155 23:50:46.632041 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6156 23:50:46.634728 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6157 23:50:46.641596 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6158 23:50:46.645039 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6159 23:50:46.647935 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 23:50:46.651736 ===================================
6161 23:50:46.655161 LPDDR4 DRAM CONFIGURATION
6162 23:50:46.658066 ===================================
6163 23:50:46.658538 EX_ROW_EN[0] = 0x0
6164 23:50:46.661338 EX_ROW_EN[1] = 0x0
6165 23:50:46.661980 LP4Y_EN = 0x0
6166 23:50:46.664663 WORK_FSP = 0x0
6167 23:50:46.668026 WL = 0x2
6168 23:50:46.668596 RL = 0x2
6169 23:50:46.671564 BL = 0x2
6170 23:50:46.672025 RPST = 0x0
6171 23:50:46.674710 RD_PRE = 0x0
6172 23:50:46.675173 WR_PRE = 0x1
6173 23:50:46.677991 WR_PST = 0x0
6174 23:50:46.678456 DBI_WR = 0x0
6175 23:50:46.681180 DBI_RD = 0x0
6176 23:50:46.681837 OTF = 0x1
6177 23:50:46.684512 ===================================
6178 23:50:46.687959 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6179 23:50:46.694581 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6180 23:50:46.697677 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 23:50:46.701269 ===================================
6182 23:50:46.704349 LPDDR4 DRAM CONFIGURATION
6183 23:50:46.707551 ===================================
6184 23:50:46.708017 EX_ROW_EN[0] = 0x10
6185 23:50:46.711112 EX_ROW_EN[1] = 0x0
6186 23:50:46.711576 LP4Y_EN = 0x0
6187 23:50:46.714298 WORK_FSP = 0x0
6188 23:50:46.714763 WL = 0x2
6189 23:50:46.718026 RL = 0x2
6190 23:50:46.721300 BL = 0x2
6191 23:50:46.721764 RPST = 0x0
6192 23:50:46.724405 RD_PRE = 0x0
6193 23:50:46.724898 WR_PRE = 0x1
6194 23:50:46.727412 WR_PST = 0x0
6195 23:50:46.727872 DBI_WR = 0x0
6196 23:50:46.731383 DBI_RD = 0x0
6197 23:50:46.731944 OTF = 0x1
6198 23:50:46.734542 ===================================
6199 23:50:46.741224 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6200 23:50:46.745297 nWR fixed to 30
6201 23:50:46.748223 [ModeRegInit_LP4] CH0 RK0
6202 23:50:46.748789 [ModeRegInit_LP4] CH0 RK1
6203 23:50:46.751880 [ModeRegInit_LP4] CH1 RK0
6204 23:50:46.755176 [ModeRegInit_LP4] CH1 RK1
6205 23:50:46.755742 match AC timing 19
6206 23:50:46.761366 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6207 23:50:46.765394 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6208 23:50:46.768317 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6209 23:50:46.774599 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6210 23:50:46.778358 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6211 23:50:46.778944 ==
6212 23:50:46.781510 Dram Type= 6, Freq= 0, CH_0, rank 0
6213 23:50:46.785278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 23:50:46.785914 ==
6215 23:50:46.791702 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 23:50:46.798716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6217 23:50:46.801760 [CA 0] Center 36 (8~64) winsize 57
6218 23:50:46.805066 [CA 1] Center 36 (8~64) winsize 57
6219 23:50:46.805639 [CA 2] Center 36 (8~64) winsize 57
6220 23:50:46.808345 [CA 3] Center 36 (8~64) winsize 57
6221 23:50:46.811756 [CA 4] Center 36 (8~64) winsize 57
6222 23:50:46.814677 [CA 5] Center 36 (8~64) winsize 57
6223 23:50:46.815153
6224 23:50:46.818103 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6225 23:50:46.818577
6226 23:50:46.824759 [CATrainingPosCal] consider 1 rank data
6227 23:50:46.825231 u2DelayCellTimex100 = 270/100 ps
6228 23:50:46.831654 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 23:50:46.835221 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 23:50:46.838352 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 23:50:46.841672 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 23:50:46.844941 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 23:50:46.848394 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 23:50:46.849008
6235 23:50:46.851578 CA PerBit enable=1, Macro0, CA PI delay=36
6236 23:50:46.852051
6237 23:50:46.855187 [CBTSetCACLKResult] CA Dly = 36
6238 23:50:46.855762 CS Dly: 1 (0~32)
6239 23:50:46.858635 ==
6240 23:50:46.861355 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 23:50:46.865186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 23:50:46.865767 ==
6243 23:50:46.868318 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 23:50:46.874779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6245 23:50:46.878116 [CA 0] Center 36 (8~64) winsize 57
6246 23:50:46.881489 [CA 1] Center 36 (8~64) winsize 57
6247 23:50:46.884839 [CA 2] Center 36 (8~64) winsize 57
6248 23:50:46.888475 [CA 3] Center 36 (8~64) winsize 57
6249 23:50:46.891719 [CA 4] Center 36 (8~64) winsize 57
6250 23:50:46.895113 [CA 5] Center 36 (8~64) winsize 57
6251 23:50:46.895740
6252 23:50:46.898463 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6253 23:50:46.899028
6254 23:50:46.901230 [CATrainingPosCal] consider 2 rank data
6255 23:50:46.905187 u2DelayCellTimex100 = 270/100 ps
6256 23:50:46.908362 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 23:50:46.911495 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 23:50:46.914835 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 23:50:46.918169 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 23:50:46.924802 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 23:50:46.928005 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 23:50:46.928479
6263 23:50:46.931590 CA PerBit enable=1, Macro0, CA PI delay=36
6264 23:50:46.932158
6265 23:50:46.934706 [CBTSetCACLKResult] CA Dly = 36
6266 23:50:46.935270 CS Dly: 1 (0~32)
6267 23:50:46.935651
6268 23:50:46.938243 ----->DramcWriteLeveling(PI) begin...
6269 23:50:46.938814 ==
6270 23:50:46.941128 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 23:50:46.947882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 23:50:46.948359 ==
6273 23:50:46.951525 Write leveling (Byte 0): 40 => 8
6274 23:50:46.952088 Write leveling (Byte 1): 32 => 0
6275 23:50:46.954881 DramcWriteLeveling(PI) end<-----
6276 23:50:46.955441
6277 23:50:46.955822 ==
6278 23:50:46.958252 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 23:50:46.964754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 23:50:46.965319 ==
6281 23:50:46.965702 [Gating] SW mode calibration
6282 23:50:46.975237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6283 23:50:46.978409 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6284 23:50:46.981423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 23:50:46.988118 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 23:50:46.991237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 23:50:46.994901 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 23:50:47.001411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 23:50:47.005075 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 23:50:47.008206 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 23:50:47.014591 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 23:50:47.017991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 23:50:47.021198 Total UI for P1: 0, mck2ui 16
6294 23:50:47.024395 best dqsien dly found for B0: ( 0, 14, 24)
6295 23:50:47.027911 Total UI for P1: 0, mck2ui 16
6296 23:50:47.031413 best dqsien dly found for B1: ( 0, 14, 24)
6297 23:50:47.034494 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6298 23:50:47.037938 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6299 23:50:47.038394
6300 23:50:47.041131 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 23:50:47.044258 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 23:50:47.047918 [Gating] SW calibration Done
6303 23:50:47.048383 ==
6304 23:50:47.051027 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 23:50:47.057800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 23:50:47.058258 ==
6307 23:50:47.058619 RX Vref Scan: 0
6308 23:50:47.058955
6309 23:50:47.061155 RX Vref 0 -> 0, step: 1
6310 23:50:47.061610
6311 23:50:47.064533 RX Delay -410 -> 252, step: 16
6312 23:50:47.067928 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6313 23:50:47.071300 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6314 23:50:47.074258 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6315 23:50:47.081433 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6316 23:50:47.084429 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6317 23:50:47.087282 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6318 23:50:47.090567 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6319 23:50:47.097487 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6320 23:50:47.100854 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6321 23:50:47.104199 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6322 23:50:47.107336 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6323 23:50:47.113816 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6324 23:50:47.117379 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6325 23:50:47.120730 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6326 23:50:47.127066 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6327 23:50:47.130304 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6328 23:50:47.130496 ==
6329 23:50:47.133847 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 23:50:47.136817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 23:50:47.136952 ==
6332 23:50:47.140066 DQS Delay:
6333 23:50:47.140200 DQS0 = 27, DQS1 = 43
6334 23:50:47.140306 DQM Delay:
6335 23:50:47.143940 DQM0 = 12, DQM1 = 11
6336 23:50:47.144074 DQ Delay:
6337 23:50:47.146915 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6338 23:50:47.150257 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6339 23:50:47.153788 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6340 23:50:47.156778 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6341 23:50:47.156912
6342 23:50:47.157017
6343 23:50:47.157114 ==
6344 23:50:47.160244 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 23:50:47.163598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 23:50:47.166863 ==
6347 23:50:47.166997
6348 23:50:47.167103
6349 23:50:47.167200 TX Vref Scan disable
6350 23:50:47.169954 == TX Byte 0 ==
6351 23:50:47.173370 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 23:50:47.177031 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 23:50:47.180291 == TX Byte 1 ==
6354 23:50:47.183731 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6355 23:50:47.187037 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6356 23:50:47.187345 ==
6357 23:50:47.190020 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 23:50:47.196604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 23:50:47.196805 ==
6360 23:50:47.196954
6361 23:50:47.197092
6362 23:50:47.197224 TX Vref Scan disable
6363 23:50:47.200038 == TX Byte 0 ==
6364 23:50:47.203346 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 23:50:47.206564 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 23:50:47.209915 == TX Byte 1 ==
6367 23:50:47.213509 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6368 23:50:47.216530 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6369 23:50:47.216677
6370 23:50:47.219785 [DATLAT]
6371 23:50:47.219916 Freq=400, CH0 RK0
6372 23:50:47.220022
6373 23:50:47.222936 DATLAT Default: 0xf
6374 23:50:47.223069 0, 0xFFFF, sum = 0
6375 23:50:47.226499 1, 0xFFFF, sum = 0
6376 23:50:47.226634 2, 0xFFFF, sum = 0
6377 23:50:47.229980 3, 0xFFFF, sum = 0
6378 23:50:47.230114 4, 0xFFFF, sum = 0
6379 23:50:47.233118 5, 0xFFFF, sum = 0
6380 23:50:47.233254 6, 0xFFFF, sum = 0
6381 23:50:47.236255 7, 0xFFFF, sum = 0
6382 23:50:47.236389 8, 0xFFFF, sum = 0
6383 23:50:47.239793 9, 0xFFFF, sum = 0
6384 23:50:47.243226 10, 0xFFFF, sum = 0
6385 23:50:47.243360 11, 0xFFFF, sum = 0
6386 23:50:47.246412 12, 0xFFFF, sum = 0
6387 23:50:47.246547 13, 0x0, sum = 1
6388 23:50:47.249776 14, 0x0, sum = 2
6389 23:50:47.249910 15, 0x0, sum = 3
6390 23:50:47.252866 16, 0x0, sum = 4
6391 23:50:47.253017 best_step = 14
6392 23:50:47.253135
6393 23:50:47.253246 ==
6394 23:50:47.256445 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 23:50:47.259906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 23:50:47.260075 ==
6397 23:50:47.263074 RX Vref Scan: 1
6398 23:50:47.263267
6399 23:50:47.266416 RX Vref 0 -> 0, step: 1
6400 23:50:47.266635
6401 23:50:47.266817 RX Delay -327 -> 252, step: 8
6402 23:50:47.266987
6403 23:50:47.269961 Set Vref, RX VrefLevel [Byte0]: 58
6404 23:50:47.272847 [Byte1]: 50
6405 23:50:47.278461
6406 23:50:47.278910 Final RX Vref Byte 0 = 58 to rank0
6407 23:50:47.281756 Final RX Vref Byte 1 = 50 to rank0
6408 23:50:47.285009 Final RX Vref Byte 0 = 58 to rank1
6409 23:50:47.288280 Final RX Vref Byte 1 = 50 to rank1==
6410 23:50:47.291580 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 23:50:47.298493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 23:50:47.298865 ==
6413 23:50:47.299154 DQS Delay:
6414 23:50:47.301451 DQS0 = 28, DQS1 = 48
6415 23:50:47.301752 DQM Delay:
6416 23:50:47.301961 DQM0 = 12, DQM1 = 14
6417 23:50:47.304789 DQ Delay:
6418 23:50:47.308102 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6419 23:50:47.311182 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6420 23:50:47.311387 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6421 23:50:47.314512 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6422 23:50:47.318112
6423 23:50:47.318316
6424 23:50:47.324709 [DQSOSCAuto] RK0, (LSB)MR18= 0xb8b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 386 ps
6425 23:50:47.327702 CH0 RK0: MR19=C0C, MR18=B8B0
6426 23:50:47.334377 CH0_RK0: MR19=0xC0C, MR18=0xB8B0, DQSOSC=386, MR23=63, INC=396, DEC=264
6427 23:50:47.334583 ==
6428 23:50:47.337950 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 23:50:47.341075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 23:50:47.341245 ==
6431 23:50:47.344528 [Gating] SW mode calibration
6432 23:50:47.351523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 23:50:47.357773 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6434 23:50:47.361244 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 23:50:47.364376 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 23:50:47.371331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 23:50:47.374329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 23:50:47.377893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 23:50:47.384259 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 23:50:47.387913 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 23:50:47.391057 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 23:50:47.394520 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 23:50:47.397779 Total UI for P1: 0, mck2ui 16
6444 23:50:47.401180 best dqsien dly found for B0: ( 0, 14, 24)
6445 23:50:47.404301 Total UI for P1: 0, mck2ui 16
6446 23:50:47.408033 best dqsien dly found for B1: ( 0, 14, 24)
6447 23:50:47.411004 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6448 23:50:47.414469 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6449 23:50:47.417677
6450 23:50:47.421088 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 23:50:47.424310 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 23:50:47.427660 [Gating] SW calibration Done
6453 23:50:47.427869 ==
6454 23:50:47.430944 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 23:50:47.434225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 23:50:47.434370 ==
6457 23:50:47.437607 RX Vref Scan: 0
6458 23:50:47.437751
6459 23:50:47.437864 RX Vref 0 -> 0, step: 1
6460 23:50:47.437970
6461 23:50:47.440770 RX Delay -410 -> 252, step: 16
6462 23:50:47.444454 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6463 23:50:47.450662 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6464 23:50:47.454176 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6465 23:50:47.457350 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6466 23:50:47.460686 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6467 23:50:47.467316 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6468 23:50:47.470632 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6469 23:50:47.474428 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6470 23:50:47.478019 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6471 23:50:47.484118 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6472 23:50:47.487679 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6473 23:50:47.490648 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6474 23:50:47.494449 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6475 23:50:47.500792 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6476 23:50:47.504473 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6477 23:50:47.507886 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6478 23:50:47.508408 ==
6479 23:50:47.510874 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 23:50:47.517683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 23:50:47.518278 ==
6482 23:50:47.518657 DQS Delay:
6483 23:50:47.520664 DQS0 = 27, DQS1 = 43
6484 23:50:47.521145 DQM Delay:
6485 23:50:47.521644 DQM0 = 9, DQM1 = 15
6486 23:50:47.524156 DQ Delay:
6487 23:50:47.527748 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6488 23:50:47.528312 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6489 23:50:47.530941 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6490 23:50:47.534224 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6491 23:50:47.534806
6492 23:50:47.535294
6493 23:50:47.537829 ==
6494 23:50:47.540848 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 23:50:47.544407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 23:50:47.545041 ==
6497 23:50:47.545534
6498 23:50:47.545983
6499 23:50:47.547306 TX Vref Scan disable
6500 23:50:47.547777 == TX Byte 0 ==
6501 23:50:47.550744 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6502 23:50:47.557479 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6503 23:50:47.558046 == TX Byte 1 ==
6504 23:50:47.560633 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6505 23:50:47.567413 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6506 23:50:47.567984 ==
6507 23:50:47.571042 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 23:50:47.573798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 23:50:47.574272 ==
6510 23:50:47.574648
6511 23:50:47.574993
6512 23:50:47.577670 TX Vref Scan disable
6513 23:50:47.578231 == TX Byte 0 ==
6514 23:50:47.580955 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6515 23:50:47.587545 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6516 23:50:47.588239 == TX Byte 1 ==
6517 23:50:47.590619 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6518 23:50:47.597142 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6519 23:50:47.597774
6520 23:50:47.598152 [DATLAT]
6521 23:50:47.598504 Freq=400, CH0 RK1
6522 23:50:47.598843
6523 23:50:47.600321 DATLAT Default: 0xe
6524 23:50:47.604257 0, 0xFFFF, sum = 0
6525 23:50:47.604862 1, 0xFFFF, sum = 0
6526 23:50:47.607585 2, 0xFFFF, sum = 0
6527 23:50:47.608155 3, 0xFFFF, sum = 0
6528 23:50:47.610454 4, 0xFFFF, sum = 0
6529 23:50:47.610935 5, 0xFFFF, sum = 0
6530 23:50:47.613740 6, 0xFFFF, sum = 0
6531 23:50:47.614214 7, 0xFFFF, sum = 0
6532 23:50:47.617120 8, 0xFFFF, sum = 0
6533 23:50:47.617604 9, 0xFFFF, sum = 0
6534 23:50:47.620540 10, 0xFFFF, sum = 0
6535 23:50:47.621051 11, 0xFFFF, sum = 0
6536 23:50:47.623897 12, 0xFFFF, sum = 0
6537 23:50:47.624370 13, 0x0, sum = 1
6538 23:50:47.626946 14, 0x0, sum = 2
6539 23:50:47.627422 15, 0x0, sum = 3
6540 23:50:47.630583 16, 0x0, sum = 4
6541 23:50:47.631162 best_step = 14
6542 23:50:47.631540
6543 23:50:47.631885 ==
6544 23:50:47.633725 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 23:50:47.637166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 23:50:47.640741 ==
6547 23:50:47.641296 RX Vref Scan: 0
6548 23:50:47.641676
6549 23:50:47.643783 RX Vref 0 -> 0, step: 1
6550 23:50:47.644343
6551 23:50:47.647173 RX Delay -327 -> 252, step: 8
6552 23:50:47.650656 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6553 23:50:47.657299 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6554 23:50:47.660862 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6555 23:50:47.663769 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6556 23:50:47.667396 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6557 23:50:47.673911 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6558 23:50:47.677505 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6559 23:50:47.680266 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6560 23:50:47.684227 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6561 23:50:47.690650 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6562 23:50:47.694009 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6563 23:50:47.697154 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6564 23:50:47.700525 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6565 23:50:47.706818 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6566 23:50:47.710231 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6567 23:50:47.713445 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6568 23:50:47.714008 ==
6569 23:50:47.716679 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 23:50:47.723499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 23:50:47.724003 ==
6572 23:50:47.724642 DQS Delay:
6573 23:50:47.726816 DQS0 = 28, DQS1 = 44
6574 23:50:47.727525 DQM Delay:
6575 23:50:47.728215 DQM0 = 9, DQM1 = 15
6576 23:50:47.730222 DQ Delay:
6577 23:50:47.733677 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6578 23:50:47.734322 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6579 23:50:47.736617 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6580 23:50:47.740165 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6581 23:50:47.740669
6582 23:50:47.741050
6583 23:50:47.750402 [DQSOSCAuto] RK1, (LSB)MR18= 0xc678, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6584 23:50:47.753472 CH0 RK1: MR19=C0C, MR18=C678
6585 23:50:47.760177 CH0_RK1: MR19=0xC0C, MR18=0xC678, DQSOSC=385, MR23=63, INC=398, DEC=265
6586 23:50:47.760775 [RxdqsGatingPostProcess] freq 400
6587 23:50:47.767192 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6588 23:50:47.770617 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 23:50:47.773587 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 23:50:47.777081 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 23:50:47.780352 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 23:50:47.783909 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 23:50:47.787022 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 23:50:47.790313 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 23:50:47.793655 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 23:50:47.796630 Pre-setting of DQS Precalculation
6597 23:50:47.800123 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6598 23:50:47.800619 ==
6599 23:50:47.803799 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 23:50:47.807220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 23:50:47.807801 ==
6602 23:50:47.813797 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 23:50:47.820462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6604 23:50:47.823505 [CA 0] Center 36 (8~64) winsize 57
6605 23:50:47.826847 [CA 1] Center 36 (8~64) winsize 57
6606 23:50:47.830275 [CA 2] Center 36 (8~64) winsize 57
6607 23:50:47.833392 [CA 3] Center 36 (8~64) winsize 57
6608 23:50:47.836922 [CA 4] Center 36 (8~64) winsize 57
6609 23:50:47.840039 [CA 5] Center 36 (8~64) winsize 57
6610 23:50:47.840645
6611 23:50:47.843630 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6612 23:50:47.844188
6613 23:50:47.846782 [CATrainingPosCal] consider 1 rank data
6614 23:50:47.850466 u2DelayCellTimex100 = 270/100 ps
6615 23:50:47.853385 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 23:50:47.856994 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 23:50:47.860110 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 23:50:47.863819 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 23:50:47.866842 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 23:50:47.870361 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 23:50:47.870922
6622 23:50:47.873447 CA PerBit enable=1, Macro0, CA PI delay=36
6623 23:50:47.874004
6624 23:50:47.876350 [CBTSetCACLKResult] CA Dly = 36
6625 23:50:47.879995 CS Dly: 1 (0~32)
6626 23:50:47.880592 ==
6627 23:50:47.883478 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 23:50:47.886649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 23:50:47.887209 ==
6630 23:50:47.893664 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 23:50:47.899940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6632 23:50:47.903564 [CA 0] Center 36 (8~64) winsize 57
6633 23:50:47.904122 [CA 1] Center 36 (8~64) winsize 57
6634 23:50:47.906631 [CA 2] Center 36 (8~64) winsize 57
6635 23:50:47.910073 [CA 3] Center 36 (8~64) winsize 57
6636 23:50:47.913298 [CA 4] Center 36 (8~64) winsize 57
6637 23:50:47.916593 [CA 5] Center 36 (8~64) winsize 57
6638 23:50:47.917096
6639 23:50:47.919927 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6640 23:50:47.920421
6641 23:50:47.923360 [CATrainingPosCal] consider 2 rank data
6642 23:50:47.926835 u2DelayCellTimex100 = 270/100 ps
6643 23:50:47.929949 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 23:50:47.936521 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 23:50:47.940055 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 23:50:47.943167 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 23:50:47.946518 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 23:50:47.950151 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 23:50:47.950750
6650 23:50:47.953122 CA PerBit enable=1, Macro0, CA PI delay=36
6651 23:50:47.953596
6652 23:50:47.956229 [CBTSetCACLKResult] CA Dly = 36
6653 23:50:47.956778 CS Dly: 1 (0~32)
6654 23:50:47.959792
6655 23:50:47.963018 ----->DramcWriteLeveling(PI) begin...
6656 23:50:47.963594 ==
6657 23:50:47.966338 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 23:50:47.969914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 23:50:47.970488 ==
6660 23:50:47.972993 Write leveling (Byte 0): 40 => 8
6661 23:50:47.976190 Write leveling (Byte 1): 32 => 0
6662 23:50:47.979880 DramcWriteLeveling(PI) end<-----
6663 23:50:47.980443
6664 23:50:47.980877 ==
6665 23:50:47.983092 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 23:50:47.986312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 23:50:47.986879 ==
6668 23:50:47.989325 [Gating] SW mode calibration
6669 23:50:47.996645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6670 23:50:48.003147 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6671 23:50:48.005858 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 23:50:48.009539 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 23:50:48.015907 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 23:50:48.019117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 23:50:48.022283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 23:50:48.028942 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 23:50:48.032327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 23:50:48.035819 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 23:50:48.042691 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 23:50:48.043170 Total UI for P1: 0, mck2ui 16
6681 23:50:48.045627 best dqsien dly found for B0: ( 0, 14, 24)
6682 23:50:48.048985 Total UI for P1: 0, mck2ui 16
6683 23:50:48.052247 best dqsien dly found for B1: ( 0, 14, 24)
6684 23:50:48.058917 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6685 23:50:48.062755 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6686 23:50:48.063332
6687 23:50:48.065862 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 23:50:48.069513 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 23:50:48.072333 [Gating] SW calibration Done
6690 23:50:48.072845 ==
6691 23:50:48.075451 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 23:50:48.078997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 23:50:48.079473 ==
6694 23:50:48.082100 RX Vref Scan: 0
6695 23:50:48.082709
6696 23:50:48.083291 RX Vref 0 -> 0, step: 1
6697 23:50:48.083665
6698 23:50:48.085556 RX Delay -410 -> 252, step: 16
6699 23:50:48.088857 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6700 23:50:48.095702 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6701 23:50:48.098874 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6702 23:50:48.102533 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6703 23:50:48.105674 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6704 23:50:48.112102 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6705 23:50:48.115655 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6706 23:50:48.118843 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6707 23:50:48.121930 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6708 23:50:48.128767 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6709 23:50:48.132162 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6710 23:50:48.135384 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6711 23:50:48.138868 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6712 23:50:48.145296 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6713 23:50:48.148662 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6714 23:50:48.152137 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6715 23:50:48.152748 ==
6716 23:50:48.155716 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 23:50:48.162201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 23:50:48.162749 ==
6719 23:50:48.163126 DQS Delay:
6720 23:50:48.165210 DQS0 = 27, DQS1 = 43
6721 23:50:48.165681 DQM Delay:
6722 23:50:48.166056 DQM0 = 9, DQM1 = 17
6723 23:50:48.168393 DQ Delay:
6724 23:50:48.172391 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6725 23:50:48.172995 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6726 23:50:48.175405 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6727 23:50:48.179143 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6728 23:50:48.179713
6729 23:50:48.180090
6730 23:50:48.182096 ==
6731 23:50:48.185428 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 23:50:48.188460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 23:50:48.188967 ==
6734 23:50:48.189411
6735 23:50:48.189765
6736 23:50:48.192478 TX Vref Scan disable
6737 23:50:48.192984 == TX Byte 0 ==
6738 23:50:48.195566 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 23:50:48.202225 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 23:50:48.202792 == TX Byte 1 ==
6741 23:50:48.206042 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6742 23:50:48.212330 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6743 23:50:48.212934 ==
6744 23:50:48.215854 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 23:50:48.218619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 23:50:48.219182 ==
6747 23:50:48.219557
6748 23:50:48.220171
6749 23:50:48.221916 TX Vref Scan disable
6750 23:50:48.222469 == TX Byte 0 ==
6751 23:50:48.225277 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 23:50:48.231809 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 23:50:48.232626 == TX Byte 1 ==
6754 23:50:48.235180 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6755 23:50:48.241623 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6756 23:50:48.242101
6757 23:50:48.242476 [DATLAT]
6758 23:50:48.245379 Freq=400, CH1 RK0
6759 23:50:48.245911
6760 23:50:48.246346 DATLAT Default: 0xf
6761 23:50:48.248494 0, 0xFFFF, sum = 0
6762 23:50:48.249067 1, 0xFFFF, sum = 0
6763 23:50:48.252031 2, 0xFFFF, sum = 0
6764 23:50:48.252477 3, 0xFFFF, sum = 0
6765 23:50:48.255082 4, 0xFFFF, sum = 0
6766 23:50:48.255562 5, 0xFFFF, sum = 0
6767 23:50:48.258474 6, 0xFFFF, sum = 0
6768 23:50:48.258954 7, 0xFFFF, sum = 0
6769 23:50:48.261936 8, 0xFFFF, sum = 0
6770 23:50:48.262420 9, 0xFFFF, sum = 0
6771 23:50:48.265109 10, 0xFFFF, sum = 0
6772 23:50:48.265589 11, 0xFFFF, sum = 0
6773 23:50:48.268319 12, 0xFFFF, sum = 0
6774 23:50:48.268874 13, 0x0, sum = 1
6775 23:50:48.271882 14, 0x0, sum = 2
6776 23:50:48.272361 15, 0x0, sum = 3
6777 23:50:48.275104 16, 0x0, sum = 4
6778 23:50:48.275714 best_step = 14
6779 23:50:48.276096
6780 23:50:48.276450 ==
6781 23:50:48.278500 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 23:50:48.284999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 23:50:48.285478 ==
6784 23:50:48.285857 RX Vref Scan: 1
6785 23:50:48.286208
6786 23:50:48.288182 RX Vref 0 -> 0, step: 1
6787 23:50:48.288723
6788 23:50:48.292022 RX Delay -327 -> 252, step: 8
6789 23:50:48.292620
6790 23:50:48.295129 Set Vref, RX VrefLevel [Byte0]: 51
6791 23:50:48.298845 [Byte1]: 57
6792 23:50:48.299420
6793 23:50:48.301755 Final RX Vref Byte 0 = 51 to rank0
6794 23:50:48.305287 Final RX Vref Byte 1 = 57 to rank0
6795 23:50:48.308704 Final RX Vref Byte 0 = 51 to rank1
6796 23:50:48.311760 Final RX Vref Byte 1 = 57 to rank1==
6797 23:50:48.314984 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 23:50:48.318221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 23:50:48.321736 ==
6800 23:50:48.322208 DQS Delay:
6801 23:50:48.322585 DQS0 = 32, DQS1 = 40
6802 23:50:48.324765 DQM Delay:
6803 23:50:48.325236 DQM0 = 10, DQM1 = 11
6804 23:50:48.328709 DQ Delay:
6805 23:50:48.329266 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6806 23:50:48.331580 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6807 23:50:48.334985 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6808 23:50:48.338115 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6809 23:50:48.338579
6810 23:50:48.338950
6811 23:50:48.347950 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6812 23:50:48.351297 CH1 RK0: MR19=C0C, MR18=9AD5
6813 23:50:48.354757 CH1_RK0: MR19=0xC0C, MR18=0x9AD5, DQSOSC=383, MR23=63, INC=402, DEC=268
6814 23:50:48.358152 ==
6815 23:50:48.361345 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 23:50:48.365021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 23:50:48.365588 ==
6818 23:50:48.368073 [Gating] SW mode calibration
6819 23:50:48.374844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6820 23:50:48.378268 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6821 23:50:48.384981 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 23:50:48.388480 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 23:50:48.391584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 23:50:48.398159 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 23:50:48.401691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 23:50:48.404507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 23:50:48.411519 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 23:50:48.414930 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 23:50:48.418095 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 23:50:48.421061 Total UI for P1: 0, mck2ui 16
6831 23:50:48.424228 best dqsien dly found for B0: ( 0, 14, 24)
6832 23:50:48.427991 Total UI for P1: 0, mck2ui 16
6833 23:50:48.430857 best dqsien dly found for B1: ( 0, 14, 24)
6834 23:50:48.434098 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6835 23:50:48.437473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6836 23:50:48.437950
6837 23:50:48.444165 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 23:50:48.447517 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 23:50:48.447998 [Gating] SW calibration Done
6840 23:50:48.450808 ==
6841 23:50:48.454159 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 23:50:48.457727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 23:50:48.458203 ==
6844 23:50:48.458581 RX Vref Scan: 0
6845 23:50:48.458930
6846 23:50:48.461053 RX Vref 0 -> 0, step: 1
6847 23:50:48.461521
6848 23:50:48.464127 RX Delay -410 -> 252, step: 16
6849 23:50:48.468100 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6850 23:50:48.471090 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6851 23:50:48.477982 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6852 23:50:48.480876 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6853 23:50:48.484086 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6854 23:50:48.487586 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6855 23:50:48.494149 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6856 23:50:48.497197 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6857 23:50:48.500664 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6858 23:50:48.504076 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6859 23:50:48.510619 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6860 23:50:48.514092 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6861 23:50:48.517622 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6862 23:50:48.520760 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6863 23:50:48.527465 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6864 23:50:48.530795 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6865 23:50:48.531273 ==
6866 23:50:48.534083 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 23:50:48.537287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 23:50:48.537769 ==
6869 23:50:48.540990 DQS Delay:
6870 23:50:48.541461 DQS0 = 35, DQS1 = 43
6871 23:50:48.544121 DQM Delay:
6872 23:50:48.544613 DQM0 = 18, DQM1 = 18
6873 23:50:48.544999 DQ Delay:
6874 23:50:48.547339 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6875 23:50:48.550982 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6876 23:50:48.554543 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6877 23:50:48.557638 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6878 23:50:48.558112
6879 23:50:48.558490
6880 23:50:48.558843 ==
6881 23:50:48.560748 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 23:50:48.567811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 23:50:48.568375 ==
6884 23:50:48.568818
6885 23:50:48.569172
6886 23:50:48.569508 TX Vref Scan disable
6887 23:50:48.570881 == TX Byte 0 ==
6888 23:50:48.574198 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6889 23:50:48.577740 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6890 23:50:48.580662 == TX Byte 1 ==
6891 23:50:48.584508 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6892 23:50:48.587671 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6893 23:50:48.588235 ==
6894 23:50:48.590806 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 23:50:48.597288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 23:50:48.597802 ==
6897 23:50:48.598208
6898 23:50:48.598571
6899 23:50:48.598954 TX Vref Scan disable
6900 23:50:48.600417 == TX Byte 0 ==
6901 23:50:48.603958 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6902 23:50:48.607428 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6903 23:50:48.610503 == TX Byte 1 ==
6904 23:50:48.614359 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6905 23:50:48.617171 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6906 23:50:48.617838
6907 23:50:48.620757 [DATLAT]
6908 23:50:48.621403 Freq=400, CH1 RK1
6909 23:50:48.621833
6910 23:50:48.623772 DATLAT Default: 0xe
6911 23:50:48.624265 0, 0xFFFF, sum = 0
6912 23:50:48.627484 1, 0xFFFF, sum = 0
6913 23:50:48.628040 2, 0xFFFF, sum = 0
6914 23:50:48.630475 3, 0xFFFF, sum = 0
6915 23:50:48.630973 4, 0xFFFF, sum = 0
6916 23:50:48.633936 5, 0xFFFF, sum = 0
6917 23:50:48.634538 6, 0xFFFF, sum = 0
6918 23:50:48.637175 7, 0xFFFF, sum = 0
6919 23:50:48.637607 8, 0xFFFF, sum = 0
6920 23:50:48.640592 9, 0xFFFF, sum = 0
6921 23:50:48.643844 10, 0xFFFF, sum = 0
6922 23:50:48.644298 11, 0xFFFF, sum = 0
6923 23:50:48.647214 12, 0xFFFF, sum = 0
6924 23:50:48.647743 13, 0x0, sum = 1
6925 23:50:48.650635 14, 0x0, sum = 2
6926 23:50:48.651070 15, 0x0, sum = 3
6927 23:50:48.651419 16, 0x0, sum = 4
6928 23:50:48.653916 best_step = 14
6929 23:50:48.654346
6930 23:50:48.654694 ==
6931 23:50:48.657182 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 23:50:48.660703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 23:50:48.661228 ==
6934 23:50:48.663951 RX Vref Scan: 0
6935 23:50:48.664376
6936 23:50:48.664776 RX Vref 0 -> 0, step: 1
6937 23:50:48.667365
6938 23:50:48.667882 RX Delay -327 -> 252, step: 8
6939 23:50:48.675746 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6940 23:50:48.679273 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6941 23:50:48.682271 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6942 23:50:48.685853 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6943 23:50:48.692150 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6944 23:50:48.695509 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6945 23:50:48.698663 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6946 23:50:48.702071 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6947 23:50:48.708982 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6948 23:50:48.712066 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6949 23:50:48.715408 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6950 23:50:48.718840 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6951 23:50:48.725512 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6952 23:50:48.728604 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6953 23:50:48.731916 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6954 23:50:48.739130 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6955 23:50:48.739715 ==
6956 23:50:48.742532 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 23:50:48.745609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 23:50:48.746078 ==
6959 23:50:48.746452 DQS Delay:
6960 23:50:48.749108 DQS0 = 28, DQS1 = 40
6961 23:50:48.749636 DQM Delay:
6962 23:50:48.752256 DQM0 = 9, DQM1 = 14
6963 23:50:48.752747 DQ Delay:
6964 23:50:48.755533 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6965 23:50:48.758730 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6966 23:50:48.762214 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
6967 23:50:48.765752 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6968 23:50:48.766364
6969 23:50:48.766894
6970 23:50:48.772255 [DQSOSCAuto] RK1, (LSB)MR18= 0xb35e, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 387 ps
6971 23:50:48.775629 CH1 RK1: MR19=C0C, MR18=B35E
6972 23:50:48.782034 CH1_RK1: MR19=0xC0C, MR18=0xB35E, DQSOSC=387, MR23=63, INC=394, DEC=262
6973 23:50:48.785256 [RxdqsGatingPostProcess] freq 400
6974 23:50:48.788672 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6975 23:50:48.791938 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 23:50:48.795503 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 23:50:48.798620 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 23:50:48.802231 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 23:50:48.805375 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 23:50:48.808390 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 23:50:48.811986 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 23:50:48.815428 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 23:50:48.818917 Pre-setting of DQS Precalculation
6984 23:50:48.821574 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6985 23:50:48.831645 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6986 23:50:48.838215 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6987 23:50:48.838721
6988 23:50:48.839171
6989 23:50:48.841629 [Calibration Summary] 800 Mbps
6990 23:50:48.842180 CH 0, Rank 0
6991 23:50:48.844628 SW Impedance : PASS
6992 23:50:48.845096 DUTY Scan : NO K
6993 23:50:48.847955 ZQ Calibration : PASS
6994 23:50:48.851583 Jitter Meter : NO K
6995 23:50:48.852116 CBT Training : PASS
6996 23:50:48.854914 Write leveling : PASS
6997 23:50:48.858347 RX DQS gating : PASS
6998 23:50:48.858824 RX DQ/DQS(RDDQC) : PASS
6999 23:50:48.861312 TX DQ/DQS : PASS
7000 23:50:48.864892 RX DATLAT : PASS
7001 23:50:48.865311 RX DQ/DQS(Engine): PASS
7002 23:50:48.868069 TX OE : NO K
7003 23:50:48.868492 All Pass.
7004 23:50:48.868858
7005 23:50:48.871357 CH 0, Rank 1
7006 23:50:48.871772 SW Impedance : PASS
7007 23:50:48.874328 DUTY Scan : NO K
7008 23:50:48.877715 ZQ Calibration : PASS
7009 23:50:48.878137 Jitter Meter : NO K
7010 23:50:48.881235 CBT Training : PASS
7011 23:50:48.884399 Write leveling : NO K
7012 23:50:48.884904 RX DQS gating : PASS
7013 23:50:48.887589 RX DQ/DQS(RDDQC) : PASS
7014 23:50:48.890723 TX DQ/DQS : PASS
7015 23:50:48.891184 RX DATLAT : PASS
7016 23:50:48.894523 RX DQ/DQS(Engine): PASS
7017 23:50:48.894975 TX OE : NO K
7018 23:50:48.897881 All Pass.
7019 23:50:48.898345
7020 23:50:48.898759 CH 1, Rank 0
7021 23:50:48.900975 SW Impedance : PASS
7022 23:50:48.901447 DUTY Scan : NO K
7023 23:50:48.904249 ZQ Calibration : PASS
7024 23:50:48.907374 Jitter Meter : NO K
7025 23:50:48.907803 CBT Training : PASS
7026 23:50:48.910985 Write leveling : PASS
7027 23:50:48.914247 RX DQS gating : PASS
7028 23:50:48.914678 RX DQ/DQS(RDDQC) : PASS
7029 23:50:48.917479 TX DQ/DQS : PASS
7030 23:50:48.920649 RX DATLAT : PASS
7031 23:50:48.921076 RX DQ/DQS(Engine): PASS
7032 23:50:48.924175 TX OE : NO K
7033 23:50:48.924643 All Pass.
7034 23:50:48.925173
7035 23:50:48.927226 CH 1, Rank 1
7036 23:50:48.927650 SW Impedance : PASS
7037 23:50:48.930923 DUTY Scan : NO K
7038 23:50:48.933988 ZQ Calibration : PASS
7039 23:50:48.934407 Jitter Meter : NO K
7040 23:50:48.937295 CBT Training : PASS
7041 23:50:48.940424 Write leveling : NO K
7042 23:50:48.940905 RX DQS gating : PASS
7043 23:50:48.943785 RX DQ/DQS(RDDQC) : PASS
7044 23:50:48.947194 TX DQ/DQS : PASS
7045 23:50:48.947760 RX DATLAT : PASS
7046 23:50:48.950833 RX DQ/DQS(Engine): PASS
7047 23:50:48.953918 TX OE : NO K
7048 23:50:48.954395 All Pass.
7049 23:50:48.954780
7050 23:50:48.955270 DramC Write-DBI off
7051 23:50:48.957242 PER_BANK_REFRESH: Hybrid Mode
7052 23:50:48.960544 TX_TRACKING: ON
7053 23:50:48.966935 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7054 23:50:48.970289 [FAST_K] Save calibration result to emmc
7055 23:50:48.977142 dramc_set_vcore_voltage set vcore to 725000
7056 23:50:48.977646 Read voltage for 1600, 0
7057 23:50:48.980656 Vio18 = 0
7058 23:50:48.981077 Vcore = 725000
7059 23:50:48.981415 Vdram = 0
7060 23:50:48.981726 Vddq = 0
7061 23:50:48.983567 Vmddr = 0
7062 23:50:48.986989 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7063 23:50:48.993740 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7064 23:50:48.997148 MEM_TYPE=3, freq_sel=13
7065 23:50:48.997567 sv_algorithm_assistance_LP4_3733
7066 23:50:49.004080 ============ PULL DRAM RESETB DOWN ============
7067 23:50:49.007167 ========== PULL DRAM RESETB DOWN end =========
7068 23:50:49.009950 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7069 23:50:49.013585 ===================================
7070 23:50:49.016787 LPDDR4 DRAM CONFIGURATION
7071 23:50:49.019952 ===================================
7072 23:50:49.023737 EX_ROW_EN[0] = 0x0
7073 23:50:49.023819 EX_ROW_EN[1] = 0x0
7074 23:50:49.026859 LP4Y_EN = 0x0
7075 23:50:49.026941 WORK_FSP = 0x1
7076 23:50:49.030385 WL = 0x5
7077 23:50:49.030495 RL = 0x5
7078 23:50:49.034084 BL = 0x2
7079 23:50:49.034245 RPST = 0x0
7080 23:50:49.037217 RD_PRE = 0x0
7081 23:50:49.037383 WR_PRE = 0x1
7082 23:50:49.040392 WR_PST = 0x1
7083 23:50:49.040567 DBI_WR = 0x0
7084 23:50:49.043610 DBI_RD = 0x0
7085 23:50:49.043780 OTF = 0x1
7086 23:50:49.046863 ===================================
7087 23:50:49.050087 ===================================
7088 23:50:49.053434 ANA top config
7089 23:50:49.056992 ===================================
7090 23:50:49.060258 DLL_ASYNC_EN = 0
7091 23:50:49.060420 ALL_SLAVE_EN = 0
7092 23:50:49.063693 NEW_RANK_MODE = 1
7093 23:50:49.067092 DLL_IDLE_MODE = 1
7094 23:50:49.070336 LP45_APHY_COMB_EN = 1
7095 23:50:49.070509 TX_ODT_DIS = 0
7096 23:50:49.073776 NEW_8X_MODE = 1
7097 23:50:49.077114 ===================================
7098 23:50:49.080628 ===================================
7099 23:50:49.083671 data_rate = 3200
7100 23:50:49.087279 CKR = 1
7101 23:50:49.090712 DQ_P2S_RATIO = 8
7102 23:50:49.093651 ===================================
7103 23:50:49.097207 CA_P2S_RATIO = 8
7104 23:50:49.097672 DQ_CA_OPEN = 0
7105 23:50:49.100700 DQ_SEMI_OPEN = 0
7106 23:50:49.104312 CA_SEMI_OPEN = 0
7107 23:50:49.107437 CA_FULL_RATE = 0
7108 23:50:49.110995 DQ_CKDIV4_EN = 0
7109 23:50:49.113995 CA_CKDIV4_EN = 0
7110 23:50:49.114462 CA_PREDIV_EN = 0
7111 23:50:49.117456 PH8_DLY = 12
7112 23:50:49.120748 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7113 23:50:49.124269 DQ_AAMCK_DIV = 4
7114 23:50:49.127107 CA_AAMCK_DIV = 4
7115 23:50:49.127734 CA_ADMCK_DIV = 4
7116 23:50:49.130853 DQ_TRACK_CA_EN = 0
7117 23:50:49.134208 CA_PICK = 1600
7118 23:50:49.137159 CA_MCKIO = 1600
7119 23:50:49.140991 MCKIO_SEMI = 0
7120 23:50:49.144004 PLL_FREQ = 3068
7121 23:50:49.147823 DQ_UI_PI_RATIO = 32
7122 23:50:49.150307 CA_UI_PI_RATIO = 0
7123 23:50:49.153920 ===================================
7124 23:50:49.157451 ===================================
7125 23:50:49.158034 memory_type:LPDDR4
7126 23:50:49.160508 GP_NUM : 10
7127 23:50:49.163540 SRAM_EN : 1
7128 23:50:49.164078 MD32_EN : 0
7129 23:50:49.166913 ===================================
7130 23:50:49.170602 [ANA_INIT] >>>>>>>>>>>>>>
7131 23:50:49.173551 <<<<<< [CONFIGURE PHASE]: ANA_TX
7132 23:50:49.177004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7133 23:50:49.180194 ===================================
7134 23:50:49.183521 data_rate = 3200,PCW = 0X7600
7135 23:50:49.186405 ===================================
7136 23:50:49.190131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7137 23:50:49.193504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 23:50:49.200049 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 23:50:49.203296 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7140 23:50:49.207285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7141 23:50:49.210061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7142 23:50:49.213326 [ANA_INIT] flow start
7143 23:50:49.216976 [ANA_INIT] PLL >>>>>>>>
7144 23:50:49.217446 [ANA_INIT] PLL <<<<<<<<
7145 23:50:49.220252 [ANA_INIT] MIDPI >>>>>>>>
7146 23:50:49.223806 [ANA_INIT] MIDPI <<<<<<<<
7147 23:50:49.224381 [ANA_INIT] DLL >>>>>>>>
7148 23:50:49.227139 [ANA_INIT] DLL <<<<<<<<
7149 23:50:49.230338 [ANA_INIT] flow end
7150 23:50:49.233220 ============ LP4 DIFF to SE enter ============
7151 23:50:49.236639 ============ LP4 DIFF to SE exit ============
7152 23:50:49.239917 [ANA_INIT] <<<<<<<<<<<<<
7153 23:50:49.243624 [Flow] Enable top DCM control >>>>>
7154 23:50:49.247011 [Flow] Enable top DCM control <<<<<
7155 23:50:49.250253 Enable DLL master slave shuffle
7156 23:50:49.254083 ==============================================================
7157 23:50:49.257064 Gating Mode config
7158 23:50:49.263393 ==============================================================
7159 23:50:49.263868 Config description:
7160 23:50:49.273683 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7161 23:50:49.280127 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7162 23:50:49.283557 SELPH_MODE 0: By rank 1: By Phase
7163 23:50:49.289822 ==============================================================
7164 23:50:49.293544 GAT_TRACK_EN = 1
7165 23:50:49.296461 RX_GATING_MODE = 2
7166 23:50:49.299773 RX_GATING_TRACK_MODE = 2
7167 23:50:49.303072 SELPH_MODE = 1
7168 23:50:49.306369 PICG_EARLY_EN = 1
7169 23:50:49.309954 VALID_LAT_VALUE = 1
7170 23:50:49.313078 ==============================================================
7171 23:50:49.316366 Enter into Gating configuration >>>>
7172 23:50:49.319887 Exit from Gating configuration <<<<
7173 23:50:49.323082 Enter into DVFS_PRE_config >>>>>
7174 23:50:49.336448 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7175 23:50:49.336928 Exit from DVFS_PRE_config <<<<<
7176 23:50:49.339702 Enter into PICG configuration >>>>
7177 23:50:49.342867 Exit from PICG configuration <<<<
7178 23:50:49.346153 [RX_INPUT] configuration >>>>>
7179 23:50:49.349546 [RX_INPUT] configuration <<<<<
7180 23:50:49.355902 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7181 23:50:49.359411 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7182 23:50:49.366753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 23:50:49.373190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 23:50:49.379857 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 23:50:49.386079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 23:50:49.389269 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7187 23:50:49.392815 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7188 23:50:49.396318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7189 23:50:49.402649 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7190 23:50:49.406256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7191 23:50:49.409621 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 23:50:49.413135 ===================================
7193 23:50:49.416106 LPDDR4 DRAM CONFIGURATION
7194 23:50:49.419402 ===================================
7195 23:50:49.419600 EX_ROW_EN[0] = 0x0
7196 23:50:49.422603 EX_ROW_EN[1] = 0x0
7197 23:50:49.425869 LP4Y_EN = 0x0
7198 23:50:49.425995 WORK_FSP = 0x1
7199 23:50:49.429339 WL = 0x5
7200 23:50:49.429476 RL = 0x5
7201 23:50:49.432245 BL = 0x2
7202 23:50:49.432427 RPST = 0x0
7203 23:50:49.435971 RD_PRE = 0x0
7204 23:50:49.436126 WR_PRE = 0x1
7205 23:50:49.439022 WR_PST = 0x1
7206 23:50:49.439200 DBI_WR = 0x0
7207 23:50:49.442439 DBI_RD = 0x0
7208 23:50:49.442914 OTF = 0x1
7209 23:50:49.446063 ===================================
7210 23:50:49.449512 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7211 23:50:49.455644 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7212 23:50:49.459398 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 23:50:49.462446 ===================================
7214 23:50:49.466168 LPDDR4 DRAM CONFIGURATION
7215 23:50:49.469081 ===================================
7216 23:50:49.469556 EX_ROW_EN[0] = 0x10
7217 23:50:49.472544 EX_ROW_EN[1] = 0x0
7218 23:50:49.475556 LP4Y_EN = 0x0
7219 23:50:49.475985 WORK_FSP = 0x1
7220 23:50:49.479101 WL = 0x5
7221 23:50:49.479528 RL = 0x5
7222 23:50:49.482341 BL = 0x2
7223 23:50:49.482762 RPST = 0x0
7224 23:50:49.485519 RD_PRE = 0x0
7225 23:50:49.485948 WR_PRE = 0x1
7226 23:50:49.488524 WR_PST = 0x1
7227 23:50:49.488632 DBI_WR = 0x0
7228 23:50:49.491842 DBI_RD = 0x0
7229 23:50:49.491926 OTF = 0x1
7230 23:50:49.495347 ===================================
7231 23:50:49.502106 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7232 23:50:49.502240 ==
7233 23:50:49.505409 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 23:50:49.508449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7235 23:50:49.511693 ==
7236 23:50:49.511829 [Duty_Offset_Calibration]
7237 23:50:49.515102 B0:2 B1:0 CA:1
7238 23:50:49.515233
7239 23:50:49.518392 [DutyScan_Calibration_Flow] k_type=0
7240 23:50:49.527277
7241 23:50:49.527439 ==CLK 0==
7242 23:50:49.530648 Final CLK duty delay cell = 0
7243 23:50:49.533940 [0] MAX Duty = 5187%(X100), DQS PI = 20
7244 23:50:49.537095 [0] MIN Duty = 5031%(X100), DQS PI = 0
7245 23:50:49.537300 [0] AVG Duty = 5109%(X100)
7246 23:50:49.540315
7247 23:50:49.543680 CH0 CLK Duty spec in!! Max-Min= 156%
7248 23:50:49.547061 [DutyScan_Calibration_Flow] ====Done====
7249 23:50:49.547365
7250 23:50:49.550378 [DutyScan_Calibration_Flow] k_type=1
7251 23:50:49.566567
7252 23:50:49.566991 ==DQS 0 ==
7253 23:50:49.569926 Final DQS duty delay cell = 0
7254 23:50:49.573015 [0] MAX Duty = 5218%(X100), DQS PI = 30
7255 23:50:49.576517 [0] MIN Duty = 4938%(X100), DQS PI = 62
7256 23:50:49.579712 [0] AVG Duty = 5078%(X100)
7257 23:50:49.580142
7258 23:50:49.580508 ==DQS 1 ==
7259 23:50:49.583041 Final DQS duty delay cell = -4
7260 23:50:49.586544 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7261 23:50:49.589820 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7262 23:50:49.592870 [-4] AVG Duty = 4984%(X100)
7263 23:50:49.593300
7264 23:50:49.596423 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7265 23:50:49.596949
7266 23:50:49.600099 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7267 23:50:49.602766 [DutyScan_Calibration_Flow] ====Done====
7268 23:50:49.603193
7269 23:50:49.605746 [DutyScan_Calibration_Flow] k_type=3
7270 23:50:49.623903
7271 23:50:49.624000 ==DQM 0 ==
7272 23:50:49.627133 Final DQM duty delay cell = 0
7273 23:50:49.630795 [0] MAX Duty = 5062%(X100), DQS PI = 24
7274 23:50:49.633776 [0] MIN Duty = 4813%(X100), DQS PI = 50
7275 23:50:49.633948 [0] AVG Duty = 4937%(X100)
7276 23:50:49.637491
7277 23:50:49.637694 ==DQM 1 ==
7278 23:50:49.640636 Final DQM duty delay cell = 0
7279 23:50:49.644142 [0] MAX Duty = 5249%(X100), DQS PI = 30
7280 23:50:49.647611 [0] MIN Duty = 5000%(X100), DQS PI = 18
7281 23:50:49.647850 [0] AVG Duty = 5124%(X100)
7282 23:50:49.650614
7283 23:50:49.654207 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7284 23:50:49.654435
7285 23:50:49.657403 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7286 23:50:49.660917 [DutyScan_Calibration_Flow] ====Done====
7287 23:50:49.661211
7288 23:50:49.664049 [DutyScan_Calibration_Flow] k_type=2
7289 23:50:49.681950
7290 23:50:49.682526 ==DQ 0 ==
7291 23:50:49.684788 Final DQ duty delay cell = 0
7292 23:50:49.688094 [0] MAX Duty = 5124%(X100), DQS PI = 36
7293 23:50:49.691191 [0] MIN Duty = 5000%(X100), DQS PI = 0
7294 23:50:49.691730 [0] AVG Duty = 5062%(X100)
7295 23:50:49.694513
7296 23:50:49.694970 ==DQ 1 ==
7297 23:50:49.697922 Final DQ duty delay cell = 0
7298 23:50:49.701242 [0] MAX Duty = 4969%(X100), DQS PI = 44
7299 23:50:49.704582 [0] MIN Duty = 4875%(X100), DQS PI = 12
7300 23:50:49.705045 [0] AVG Duty = 4922%(X100)
7301 23:50:49.705410
7302 23:50:49.707916 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7303 23:50:49.708372
7304 23:50:49.711616 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7305 23:50:49.718065 [DutyScan_Calibration_Flow] ====Done====
7306 23:50:49.718632 ==
7307 23:50:49.721411 Dram Type= 6, Freq= 0, CH_1, rank 0
7308 23:50:49.724901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 23:50:49.725471 ==
7310 23:50:49.728773 [Duty_Offset_Calibration]
7311 23:50:49.729564 B0:0 B1:-1 CA:2
7312 23:50:49.729950
7313 23:50:49.731382 [DutyScan_Calibration_Flow] k_type=0
7314 23:50:49.741807
7315 23:50:49.742360 ==CLK 0==
7316 23:50:49.744701 Final CLK duty delay cell = 0
7317 23:50:49.748303 [0] MAX Duty = 5156%(X100), DQS PI = 12
7318 23:50:49.751520 [0] MIN Duty = 4906%(X100), DQS PI = 46
7319 23:50:49.751979 [0] AVG Duty = 5031%(X100)
7320 23:50:49.754935
7321 23:50:49.758252 CH1 CLK Duty spec in!! Max-Min= 250%
7322 23:50:49.761456 [DutyScan_Calibration_Flow] ====Done====
7323 23:50:49.762021
7324 23:50:49.764824 [DutyScan_Calibration_Flow] k_type=1
7325 23:50:49.781454
7326 23:50:49.782011 ==DQS 0 ==
7327 23:50:49.784714 Final DQS duty delay cell = 0
7328 23:50:49.788143 [0] MAX Duty = 5093%(X100), DQS PI = 38
7329 23:50:49.791142 [0] MIN Duty = 4969%(X100), DQS PI = 2
7330 23:50:49.791604 [0] AVG Duty = 5031%(X100)
7331 23:50:49.794564
7332 23:50:49.795081 ==DQS 1 ==
7333 23:50:49.797748 Final DQS duty delay cell = 0
7334 23:50:49.801248 [0] MAX Duty = 5187%(X100), DQS PI = 0
7335 23:50:49.804442 [0] MIN Duty = 4844%(X100), DQS PI = 34
7336 23:50:49.807601 [0] AVG Duty = 5015%(X100)
7337 23:50:49.808068
7338 23:50:49.811072 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7339 23:50:49.811645
7340 23:50:49.814522 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7341 23:50:49.817547 [DutyScan_Calibration_Flow] ====Done====
7342 23:50:49.818008
7343 23:50:49.820740 [DutyScan_Calibration_Flow] k_type=3
7344 23:50:49.838605
7345 23:50:49.839071 ==DQM 0 ==
7346 23:50:49.842185 Final DQM duty delay cell = 4
7347 23:50:49.845261 [4] MAX Duty = 5125%(X100), DQS PI = 22
7348 23:50:49.848947 [4] MIN Duty = 4969%(X100), DQS PI = 32
7349 23:50:49.852004 [4] AVG Duty = 5047%(X100)
7350 23:50:49.852468
7351 23:50:49.852867 ==DQM 1 ==
7352 23:50:49.855594 Final DQM duty delay cell = 0
7353 23:50:49.858723 [0] MAX Duty = 5281%(X100), DQS PI = 58
7354 23:50:49.861891 [0] MIN Duty = 4876%(X100), DQS PI = 34
7355 23:50:49.865345 [0] AVG Duty = 5078%(X100)
7356 23:50:49.865805
7357 23:50:49.868728 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7358 23:50:49.869190
7359 23:50:49.871862 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7360 23:50:49.875388 [DutyScan_Calibration_Flow] ====Done====
7361 23:50:49.875961
7362 23:50:49.878537 [DutyScan_Calibration_Flow] k_type=2
7363 23:50:49.895923
7364 23:50:49.896351 ==DQ 0 ==
7365 23:50:49.899225 Final DQ duty delay cell = 0
7366 23:50:49.902399 [0] MAX Duty = 5062%(X100), DQS PI = 20
7367 23:50:49.905653 [0] MIN Duty = 4969%(X100), DQS PI = 2
7368 23:50:49.906085 [0] AVG Duty = 5015%(X100)
7369 23:50:49.906516
7370 23:50:49.909467 ==DQ 1 ==
7371 23:50:49.912504 Final DQ duty delay cell = 0
7372 23:50:49.916212 [0] MAX Duty = 5031%(X100), DQS PI = 0
7373 23:50:49.919144 [0] MIN Duty = 4813%(X100), DQS PI = 34
7374 23:50:49.919673 [0] AVG Duty = 4922%(X100)
7375 23:50:49.920109
7376 23:50:49.922603 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7377 23:50:49.923139
7378 23:50:49.925594 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7379 23:50:49.932115 [DutyScan_Calibration_Flow] ====Done====
7380 23:50:49.935609 nWR fixed to 30
7381 23:50:49.936043 [ModeRegInit_LP4] CH0 RK0
7382 23:50:49.939539 [ModeRegInit_LP4] CH0 RK1
7383 23:50:49.942345 [ModeRegInit_LP4] CH1 RK0
7384 23:50:49.942780 [ModeRegInit_LP4] CH1 RK1
7385 23:50:49.945758 match AC timing 5
7386 23:50:49.949299 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7387 23:50:49.952396 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7388 23:50:49.959342 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7389 23:50:49.962235 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7390 23:50:49.968894 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7391 23:50:49.969374 [MiockJmeterHQA]
7392 23:50:49.969746
7393 23:50:49.972403 [DramcMiockJmeter] u1RxGatingPI = 0
7394 23:50:49.975597 0 : 4252, 4027
7395 23:50:49.976076 4 : 4253, 4026
7396 23:50:49.976455 8 : 4363, 4137
7397 23:50:49.978861 12 : 4252, 4027
7398 23:50:49.979337 16 : 4253, 4027
7399 23:50:49.982038 20 : 4363, 4138
7400 23:50:49.982509 24 : 4363, 4137
7401 23:50:49.985580 28 : 4252, 4027
7402 23:50:49.986055 32 : 4253, 4027
7403 23:50:49.986432 36 : 4253, 4026
7404 23:50:49.988713 40 : 4252, 4027
7405 23:50:49.989186 44 : 4254, 4029
7406 23:50:49.992370 48 : 4363, 4137
7407 23:50:49.992948 52 : 4252, 4027
7408 23:50:49.995720 56 : 4252, 4027
7409 23:50:49.995803 60 : 4252, 4027
7410 23:50:49.995870 64 : 4255, 4029
7411 23:50:49.998805 68 : 4250, 4027
7412 23:50:49.998889 72 : 4252, 4029
7413 23:50:50.002130 76 : 4363, 4139
7414 23:50:50.002213 80 : 4253, 4029
7415 23:50:50.005200 84 : 4252, 4029
7416 23:50:50.005284 88 : 4250, 3769
7417 23:50:50.005350 92 : 4250, 3
7418 23:50:50.008515 96 : 4250, 0
7419 23:50:50.008645 100 : 4250, 0
7420 23:50:50.012139 104 : 4250, 0
7421 23:50:50.012227 108 : 4250, 0
7422 23:50:50.012299 112 : 4361, 0
7423 23:50:50.015146 116 : 4360, 0
7424 23:50:50.015236 120 : 4250, 0
7425 23:50:50.018411 124 : 4250, 0
7426 23:50:50.018507 128 : 4250, 0
7427 23:50:50.018584 132 : 4250, 0
7428 23:50:50.021796 136 : 4250, 0
7429 23:50:50.021900 140 : 4250, 0
7430 23:50:50.025325 144 : 4250, 0
7431 23:50:50.025428 148 : 4250, 0
7432 23:50:50.025511 152 : 4250, 0
7433 23:50:50.028610 156 : 4252, 0
7434 23:50:50.028723 160 : 4360, 0
7435 23:50:50.028813 164 : 4250, 0
7436 23:50:50.031765 168 : 4360, 0
7437 23:50:50.031889 172 : 4250, 0
7438 23:50:50.035268 176 : 4250, 0
7439 23:50:50.035394 180 : 4250, 0
7440 23:50:50.035495 184 : 4250, 0
7441 23:50:50.038610 188 : 4250, 0
7442 23:50:50.038748 192 : 4250, 0
7443 23:50:50.041991 196 : 4250, 0
7444 23:50:50.042145 200 : 4250, 1
7445 23:50:50.042269 204 : 4250, 1974
7446 23:50:50.045386 208 : 4250, 4027
7447 23:50:50.045541 212 : 4252, 4029
7448 23:50:50.048669 216 : 4251, 4027
7449 23:50:50.048845 220 : 4250, 4026
7450 23:50:50.052013 224 : 4250, 4027
7451 23:50:50.052217 228 : 4360, 4138
7452 23:50:50.055619 232 : 4249, 4027
7453 23:50:50.055823 236 : 4250, 4026
7454 23:50:50.058588 240 : 4361, 4137
7455 23:50:50.058830 244 : 4250, 4027
7456 23:50:50.062004 248 : 4250, 4027
7457 23:50:50.062306 252 : 4363, 4140
7458 23:50:50.062547 256 : 4250, 4026
7459 23:50:50.065068 260 : 4250, 4027
7460 23:50:50.065372 264 : 4250, 4027
7461 23:50:50.068775 268 : 4253, 4029
7462 23:50:50.069165 272 : 4250, 4026
7463 23:50:50.072062 276 : 4250, 4027
7464 23:50:50.072487 280 : 4360, 4138
7465 23:50:50.075488 284 : 4249, 4027
7466 23:50:50.075921 288 : 4250, 4026
7467 23:50:50.078838 292 : 4361, 4137
7468 23:50:50.079267 296 : 4250, 4027
7469 23:50:50.082076 300 : 4250, 4027
7470 23:50:50.082504 304 : 4363, 4140
7471 23:50:50.085302 308 : 4250, 4026
7472 23:50:50.085729 312 : 4250, 4025
7473 23:50:50.086069 316 : 4250, 2251
7474 23:50:50.089022 320 : 4252, 15
7475 23:50:50.089449
7476 23:50:50.091700 MIOCK jitter meter ch=0
7477 23:50:50.092120
7478 23:50:50.092454 1T = (320-92) = 228 dly cells
7479 23:50:50.098490 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7480 23:50:50.098917 ==
7481 23:50:50.101902 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 23:50:50.105231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7483 23:50:50.108478 ==
7484 23:50:50.112014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7485 23:50:50.115343 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7486 23:50:50.122100 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7487 23:50:50.128307 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7488 23:50:50.135738 [CA 0] Center 43 (13~73) winsize 61
7489 23:50:50.138820 [CA 1] Center 43 (13~73) winsize 61
7490 23:50:50.142486 [CA 2] Center 38 (8~68) winsize 61
7491 23:50:50.145780 [CA 3] Center 37 (8~67) winsize 60
7492 23:50:50.148913 [CA 4] Center 37 (7~67) winsize 61
7493 23:50:50.152634 [CA 5] Center 35 (5~66) winsize 62
7494 23:50:50.153059
7495 23:50:50.155727 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7496 23:50:50.156152
7497 23:50:50.159152 [CATrainingPosCal] consider 1 rank data
7498 23:50:50.162257 u2DelayCellTimex100 = 285/100 ps
7499 23:50:50.165601 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7500 23:50:50.172383 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7501 23:50:50.176000 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7502 23:50:50.178910 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7503 23:50:50.182377 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7504 23:50:50.185451 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7505 23:50:50.185875
7506 23:50:50.189372 CA PerBit enable=1, Macro0, CA PI delay=35
7507 23:50:50.189795
7508 23:50:50.192131 [CBTSetCACLKResult] CA Dly = 35
7509 23:50:50.195494 CS Dly: 9 (0~40)
7510 23:50:50.199161 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7511 23:50:50.202426 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7512 23:50:50.203088 ==
7513 23:50:50.205347 Dram Type= 6, Freq= 0, CH_0, rank 1
7514 23:50:50.208745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7515 23:50:50.209254 ==
7516 23:50:50.215631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7517 23:50:50.218809 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7518 23:50:50.225469 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7519 23:50:50.228660 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7520 23:50:50.238961 [CA 0] Center 44 (14~74) winsize 61
7521 23:50:50.242391 [CA 1] Center 43 (14~73) winsize 60
7522 23:50:50.245570 [CA 2] Center 38 (9~68) winsize 60
7523 23:50:50.248826 [CA 3] Center 38 (9~68) winsize 60
7524 23:50:50.252508 [CA 4] Center 37 (7~67) winsize 61
7525 23:50:50.255871 [CA 5] Center 36 (6~66) winsize 61
7526 23:50:50.256442
7527 23:50:50.259012 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7528 23:50:50.259534
7529 23:50:50.262261 [CATrainingPosCal] consider 2 rank data
7530 23:50:50.265513 u2DelayCellTimex100 = 285/100 ps
7531 23:50:50.268815 CA0 delay=43 (14~73),Diff = 7 PI (23 cell)
7532 23:50:50.275553 CA1 delay=43 (14~73),Diff = 7 PI (23 cell)
7533 23:50:50.278970 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7534 23:50:50.282466 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7535 23:50:50.285355 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7536 23:50:50.288841 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7537 23:50:50.289300
7538 23:50:50.291957 CA PerBit enable=1, Macro0, CA PI delay=36
7539 23:50:50.292416
7540 23:50:50.295594 [CBTSetCACLKResult] CA Dly = 36
7541 23:50:50.298883 CS Dly: 11 (0~44)
7542 23:50:50.302275 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7543 23:50:50.305431 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7544 23:50:50.305912
7545 23:50:50.308852 ----->DramcWriteLeveling(PI) begin...
7546 23:50:50.309434 ==
7547 23:50:50.312453 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 23:50:50.315549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 23:50:50.318755 ==
7550 23:50:50.319176 Write leveling (Byte 0): 35 => 35
7551 23:50:50.322288 Write leveling (Byte 1): 29 => 29
7552 23:50:50.325657 DramcWriteLeveling(PI) end<-----
7553 23:50:50.326085
7554 23:50:50.326426 ==
7555 23:50:50.328666 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 23:50:50.335579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 23:50:50.336010 ==
7558 23:50:50.338968 [Gating] SW mode calibration
7559 23:50:50.345588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7560 23:50:50.348460 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7561 23:50:50.355303 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 23:50:50.358815 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 23:50:50.362100 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7564 23:50:50.368423 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7565 23:50:50.371803 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7566 23:50:50.375288 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7567 23:50:50.378648 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 23:50:50.385083 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 23:50:50.388364 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 23:50:50.391626 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 23:50:50.398479 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7572 23:50:50.402112 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7573 23:50:50.405628 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7574 23:50:50.412140 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7575 23:50:50.415294 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 23:50:50.418619 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 23:50:50.425499 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 23:50:50.428490 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7579 23:50:50.431969 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
7580 23:50:50.438781 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7581 23:50:50.442064 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7582 23:50:50.445057 1 6 20 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7583 23:50:50.452179 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 23:50:50.455482 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 23:50:50.458831 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 23:50:50.465076 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 23:50:50.468836 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 23:50:50.472322 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7589 23:50:50.475428 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 23:50:50.482283 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 23:50:50.485477 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 23:50:50.488832 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 23:50:50.495431 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 23:50:50.498799 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 23:50:50.502152 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 23:50:50.508702 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 23:50:50.512060 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 23:50:50.515596 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 23:50:50.521919 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 23:50:50.525255 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 23:50:50.528706 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 23:50:50.535462 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 23:50:50.538825 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 23:50:50.542101 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7605 23:50:50.549071 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7606 23:50:50.549634 Total UI for P1: 0, mck2ui 16
7607 23:50:50.555405 best dqsien dly found for B0: ( 1, 9, 10)
7608 23:50:50.558923 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7609 23:50:50.562391 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 23:50:50.565162 Total UI for P1: 0, mck2ui 16
7611 23:50:50.568941 best dqsien dly found for B1: ( 1, 9, 18)
7612 23:50:50.572178 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7613 23:50:50.575660 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7614 23:50:50.576225
7615 23:50:50.578453 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7616 23:50:50.585460 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7617 23:50:50.586027 [Gating] SW calibration Done
7618 23:50:50.588505 ==
7619 23:50:50.589100 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 23:50:50.595678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 23:50:50.596243 ==
7622 23:50:50.596657 RX Vref Scan: 0
7623 23:50:50.597011
7624 23:50:50.598391 RX Vref 0 -> 0, step: 1
7625 23:50:50.598899
7626 23:50:50.602022 RX Delay 0 -> 252, step: 8
7627 23:50:50.605120 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7628 23:50:50.608900 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7629 23:50:50.611919 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7630 23:50:50.618531 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7631 23:50:50.621792 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7632 23:50:50.625234 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7633 23:50:50.628248 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7634 23:50:50.631643 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7635 23:50:50.634898 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
7636 23:50:50.642103 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7637 23:50:50.645109 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7638 23:50:50.648518 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7639 23:50:50.652180 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7640 23:50:50.654988 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7641 23:50:50.661756 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7642 23:50:50.665033 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7643 23:50:50.665595 ==
7644 23:50:50.668871 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 23:50:50.671909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 23:50:50.672480 ==
7647 23:50:50.675064 DQS Delay:
7648 23:50:50.675626 DQS0 = 0, DQS1 = 0
7649 23:50:50.676005 DQM Delay:
7650 23:50:50.678658 DQM0 = 138, DQM1 = 128
7651 23:50:50.679222 DQ Delay:
7652 23:50:50.681667 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7653 23:50:50.685425 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7654 23:50:50.691588 DQ8 =123, DQ9 =115, DQ10 =127, DQ11 =127
7655 23:50:50.695096 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7656 23:50:50.695657
7657 23:50:50.696034
7658 23:50:50.696386 ==
7659 23:50:50.698110 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 23:50:50.701712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 23:50:50.702287 ==
7662 23:50:50.702669
7663 23:50:50.703017
7664 23:50:50.704805 TX Vref Scan disable
7665 23:50:50.705275 == TX Byte 0 ==
7666 23:50:50.711321 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7667 23:50:50.714940 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7668 23:50:50.718499 == TX Byte 1 ==
7669 23:50:50.721785 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7670 23:50:50.724958 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7671 23:50:50.725526 ==
7672 23:50:50.727817 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 23:50:50.731259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 23:50:50.731731 ==
7675 23:50:50.746287
7676 23:50:50.749035 TX Vref early break, caculate TX vref
7677 23:50:50.752514 TX Vref=16, minBit 12, minWin=22, winSum=380
7678 23:50:50.755977 TX Vref=18, minBit 6, minWin=23, winSum=387
7679 23:50:50.759365 TX Vref=20, minBit 7, minWin=23, winSum=395
7680 23:50:50.762526 TX Vref=22, minBit 7, minWin=24, winSum=408
7681 23:50:50.766115 TX Vref=24, minBit 1, minWin=25, winSum=413
7682 23:50:50.772500 TX Vref=26, minBit 7, minWin=25, winSum=425
7683 23:50:50.775964 TX Vref=28, minBit 0, minWin=25, winSum=431
7684 23:50:50.779099 TX Vref=30, minBit 2, minWin=25, winSum=423
7685 23:50:50.782400 TX Vref=32, minBit 0, minWin=25, winSum=414
7686 23:50:50.785968 TX Vref=34, minBit 0, minWin=24, winSum=401
7687 23:50:50.792224 [TxChooseVref] Worse bit 0, Min win 25, Win sum 431, Final Vref 28
7688 23:50:50.792869
7689 23:50:50.795968 Final TX Range 0 Vref 28
7690 23:50:50.796529
7691 23:50:50.796958 ==
7692 23:50:50.799405 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 23:50:50.802579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 23:50:50.803148 ==
7695 23:50:50.803526
7696 23:50:50.803873
7697 23:50:50.805495 TX Vref Scan disable
7698 23:50:50.812208 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7699 23:50:50.812797 == TX Byte 0 ==
7700 23:50:50.815909 u2DelayCellOfst[0]=13 cells (4 PI)
7701 23:50:50.819120 u2DelayCellOfst[1]=20 cells (6 PI)
7702 23:50:50.822312 u2DelayCellOfst[2]=13 cells (4 PI)
7703 23:50:50.825657 u2DelayCellOfst[3]=13 cells (4 PI)
7704 23:50:50.829372 u2DelayCellOfst[4]=13 cells (4 PI)
7705 23:50:50.832316 u2DelayCellOfst[5]=0 cells (0 PI)
7706 23:50:50.835735 u2DelayCellOfst[6]=20 cells (6 PI)
7707 23:50:50.836205 u2DelayCellOfst[7]=20 cells (6 PI)
7708 23:50:50.842343 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7709 23:50:50.845749 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7710 23:50:50.849154 == TX Byte 1 ==
7711 23:50:50.849627 u2DelayCellOfst[8]=0 cells (0 PI)
7712 23:50:50.852303 u2DelayCellOfst[9]=0 cells (0 PI)
7713 23:50:50.855845 u2DelayCellOfst[10]=6 cells (2 PI)
7714 23:50:50.859126 u2DelayCellOfst[11]=3 cells (1 PI)
7715 23:50:50.862885 u2DelayCellOfst[12]=10 cells (3 PI)
7716 23:50:50.865672 u2DelayCellOfst[13]=10 cells (3 PI)
7717 23:50:50.869058 u2DelayCellOfst[14]=13 cells (4 PI)
7718 23:50:50.872432 u2DelayCellOfst[15]=10 cells (3 PI)
7719 23:50:50.876002 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7720 23:50:50.882612 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7721 23:50:50.883180 DramC Write-DBI on
7722 23:50:50.883560 ==
7723 23:50:50.885387 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 23:50:50.889264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 23:50:50.889833 ==
7726 23:50:50.892404
7727 23:50:50.893001
7728 23:50:50.893376 TX Vref Scan disable
7729 23:50:50.895991 == TX Byte 0 ==
7730 23:50:50.898896 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7731 23:50:50.902507 == TX Byte 1 ==
7732 23:50:50.905549 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7733 23:50:50.908723 DramC Write-DBI off
7734 23:50:50.909494
7735 23:50:50.909884 [DATLAT]
7736 23:50:50.910317 Freq=1600, CH0 RK0
7737 23:50:50.910670
7738 23:50:50.912033 DATLAT Default: 0xf
7739 23:50:50.912501 0, 0xFFFF, sum = 0
7740 23:50:50.915257 1, 0xFFFF, sum = 0
7741 23:50:50.915739 2, 0xFFFF, sum = 0
7742 23:50:50.918765 3, 0xFFFF, sum = 0
7743 23:50:50.919514 4, 0xFFFF, sum = 0
7744 23:50:50.922213 5, 0xFFFF, sum = 0
7745 23:50:50.925594 6, 0xFFFF, sum = 0
7746 23:50:50.926075 7, 0xFFFF, sum = 0
7747 23:50:50.928864 8, 0xFFFF, sum = 0
7748 23:50:50.929665 9, 0xFFFF, sum = 0
7749 23:50:50.932203 10, 0xFFFF, sum = 0
7750 23:50:50.932980 11, 0xFFFF, sum = 0
7751 23:50:50.935551 12, 0xFFFF, sum = 0
7752 23:50:50.936283 13, 0xFFFF, sum = 0
7753 23:50:50.938952 14, 0x0, sum = 1
7754 23:50:50.939755 15, 0x0, sum = 2
7755 23:50:50.942200 16, 0x0, sum = 3
7756 23:50:50.942862 17, 0x0, sum = 4
7757 23:50:50.945456 best_step = 15
7758 23:50:50.945919
7759 23:50:50.946288 ==
7760 23:50:50.948863 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 23:50:50.952162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 23:50:50.952772 ==
7763 23:50:50.953154 RX Vref Scan: 1
7764 23:50:50.953587
7765 23:50:50.955340 Set Vref Range= 24 -> 127
7766 23:50:50.955911
7767 23:50:50.958800 RX Vref 24 -> 127, step: 1
7768 23:50:50.959372
7769 23:50:50.962216 RX Delay 19 -> 252, step: 4
7770 23:50:50.962764
7771 23:50:50.965215 Set Vref, RX VrefLevel [Byte0]: 24
7772 23:50:50.968663 [Byte1]: 24
7773 23:50:50.969149
7774 23:50:50.972061 Set Vref, RX VrefLevel [Byte0]: 25
7775 23:50:50.975663 [Byte1]: 25
7776 23:50:50.976130
7777 23:50:50.979018 Set Vref, RX VrefLevel [Byte0]: 26
7778 23:50:50.982222 [Byte1]: 26
7779 23:50:50.985658
7780 23:50:50.986215 Set Vref, RX VrefLevel [Byte0]: 27
7781 23:50:50.989426 [Byte1]: 27
7782 23:50:50.993747
7783 23:50:50.994318 Set Vref, RX VrefLevel [Byte0]: 28
7784 23:50:50.997001 [Byte1]: 28
7785 23:50:51.000789
7786 23:50:51.001256 Set Vref, RX VrefLevel [Byte0]: 29
7787 23:50:51.004661 [Byte1]: 29
7788 23:50:51.008963
7789 23:50:51.009523 Set Vref, RX VrefLevel [Byte0]: 30
7790 23:50:51.012013 [Byte1]: 30
7791 23:50:51.016375
7792 23:50:51.016979 Set Vref, RX VrefLevel [Byte0]: 31
7793 23:50:51.019093 [Byte1]: 31
7794 23:50:51.023853
7795 23:50:51.024410 Set Vref, RX VrefLevel [Byte0]: 32
7796 23:50:51.026930 [Byte1]: 32
7797 23:50:51.031442
7798 23:50:51.032003 Set Vref, RX VrefLevel [Byte0]: 33
7799 23:50:51.034448 [Byte1]: 33
7800 23:50:51.038871
7801 23:50:51.039431 Set Vref, RX VrefLevel [Byte0]: 34
7802 23:50:51.042258 [Byte1]: 34
7803 23:50:51.046586
7804 23:50:51.047171 Set Vref, RX VrefLevel [Byte0]: 35
7805 23:50:51.049632 [Byte1]: 35
7806 23:50:51.053959
7807 23:50:51.054535 Set Vref, RX VrefLevel [Byte0]: 36
7808 23:50:51.057125 [Byte1]: 36
7809 23:50:51.061419
7810 23:50:51.061981 Set Vref, RX VrefLevel [Byte0]: 37
7811 23:50:51.064661 [Byte1]: 37
7812 23:50:51.068963
7813 23:50:51.069527 Set Vref, RX VrefLevel [Byte0]: 38
7814 23:50:51.072422 [Byte1]: 38
7815 23:50:51.076488
7816 23:50:51.076984 Set Vref, RX VrefLevel [Byte0]: 39
7817 23:50:51.080198 [Byte1]: 39
7818 23:50:51.083968
7819 23:50:51.087499 Set Vref, RX VrefLevel [Byte0]: 40
7820 23:50:51.088069 [Byte1]: 40
7821 23:50:51.092065
7822 23:50:51.092664 Set Vref, RX VrefLevel [Byte0]: 41
7823 23:50:51.095139 [Byte1]: 41
7824 23:50:51.099710
7825 23:50:51.100276 Set Vref, RX VrefLevel [Byte0]: 42
7826 23:50:51.102721 [Byte1]: 42
7827 23:50:51.107204
7828 23:50:51.107764 Set Vref, RX VrefLevel [Byte0]: 43
7829 23:50:51.110411 [Byte1]: 43
7830 23:50:51.114440
7831 23:50:51.115002 Set Vref, RX VrefLevel [Byte0]: 44
7832 23:50:51.117832 [Byte1]: 44
7833 23:50:51.121988
7834 23:50:51.122553 Set Vref, RX VrefLevel [Byte0]: 45
7835 23:50:51.125569 [Byte1]: 45
7836 23:50:51.129655
7837 23:50:51.130220 Set Vref, RX VrefLevel [Byte0]: 46
7838 23:50:51.133314 [Byte1]: 46
7839 23:50:51.137222
7840 23:50:51.137692 Set Vref, RX VrefLevel [Byte0]: 47
7841 23:50:51.140483 [Byte1]: 47
7842 23:50:51.144678
7843 23:50:51.145243 Set Vref, RX VrefLevel [Byte0]: 48
7844 23:50:51.148210 [Byte1]: 48
7845 23:50:51.152329
7846 23:50:51.152948 Set Vref, RX VrefLevel [Byte0]: 49
7847 23:50:51.155716 [Byte1]: 49
7848 23:50:51.160078
7849 23:50:51.160679 Set Vref, RX VrefLevel [Byte0]: 50
7850 23:50:51.163144 [Byte1]: 50
7851 23:50:51.167517
7852 23:50:51.168082 Set Vref, RX VrefLevel [Byte0]: 51
7853 23:50:51.170722 [Byte1]: 51
7854 23:50:51.175289
7855 23:50:51.175851 Set Vref, RX VrefLevel [Byte0]: 52
7856 23:50:51.178405 [Byte1]: 52
7857 23:50:51.182964
7858 23:50:51.183528 Set Vref, RX VrefLevel [Byte0]: 53
7859 23:50:51.186015 [Byte1]: 53
7860 23:50:51.190561
7861 23:50:51.191121 Set Vref, RX VrefLevel [Byte0]: 54
7862 23:50:51.193713 [Byte1]: 54
7863 23:50:51.197680
7864 23:50:51.198238 Set Vref, RX VrefLevel [Byte0]: 55
7865 23:50:51.201244 [Byte1]: 55
7866 23:50:51.205235
7867 23:50:51.205800 Set Vref, RX VrefLevel [Byte0]: 56
7868 23:50:51.208979 [Byte1]: 56
7869 23:50:51.212977
7870 23:50:51.213539 Set Vref, RX VrefLevel [Byte0]: 57
7871 23:50:51.216594 [Byte1]: 57
7872 23:50:51.220676
7873 23:50:51.221241 Set Vref, RX VrefLevel [Byte0]: 58
7874 23:50:51.224213 [Byte1]: 58
7875 23:50:51.228101
7876 23:50:51.228704 Set Vref, RX VrefLevel [Byte0]: 59
7877 23:50:51.231566 [Byte1]: 59
7878 23:50:51.235682
7879 23:50:51.236339 Set Vref, RX VrefLevel [Byte0]: 60
7880 23:50:51.239049 [Byte1]: 60
7881 23:50:51.243035
7882 23:50:51.243499 Set Vref, RX VrefLevel [Byte0]: 61
7883 23:50:51.246707 [Byte1]: 61
7884 23:50:51.250663
7885 23:50:51.251127 Set Vref, RX VrefLevel [Byte0]: 62
7886 23:50:51.253939 [Byte1]: 62
7887 23:50:51.258456
7888 23:50:51.259040 Set Vref, RX VrefLevel [Byte0]: 63
7889 23:50:51.261515 [Byte1]: 63
7890 23:50:51.266003
7891 23:50:51.266464 Set Vref, RX VrefLevel [Byte0]: 64
7892 23:50:51.269202 [Byte1]: 64
7893 23:50:51.273635
7894 23:50:51.274096 Set Vref, RX VrefLevel [Byte0]: 65
7895 23:50:51.277057 [Byte1]: 65
7896 23:50:51.280853
7897 23:50:51.281316 Set Vref, RX VrefLevel [Byte0]: 66
7898 23:50:51.284507 [Byte1]: 66
7899 23:50:51.288439
7900 23:50:51.288947 Set Vref, RX VrefLevel [Byte0]: 67
7901 23:50:51.292231 [Byte1]: 67
7902 23:50:51.296445
7903 23:50:51.297047 Set Vref, RX VrefLevel [Byte0]: 68
7904 23:50:51.299575 [Byte1]: 68
7905 23:50:51.304217
7906 23:50:51.304817 Set Vref, RX VrefLevel [Byte0]: 69
7907 23:50:51.307029 [Byte1]: 69
7908 23:50:51.311669
7909 23:50:51.312240 Set Vref, RX VrefLevel [Byte0]: 70
7910 23:50:51.314718 [Byte1]: 70
7911 23:50:51.319198
7912 23:50:51.319765 Set Vref, RX VrefLevel [Byte0]: 71
7913 23:50:51.322169 [Byte1]: 71
7914 23:50:51.326926
7915 23:50:51.327484 Set Vref, RX VrefLevel [Byte0]: 72
7916 23:50:51.329875 [Byte1]: 72
7917 23:50:51.334371
7918 23:50:51.334933 Set Vref, RX VrefLevel [Byte0]: 73
7919 23:50:51.337199 [Byte1]: 73
7920 23:50:51.341960
7921 23:50:51.342522 Set Vref, RX VrefLevel [Byte0]: 74
7922 23:50:51.344855 [Byte1]: 74
7923 23:50:51.349510
7924 23:50:51.350071 Set Vref, RX VrefLevel [Byte0]: 75
7925 23:50:51.352726 [Byte1]: 75
7926 23:50:51.356931
7927 23:50:51.357394 Set Vref, RX VrefLevel [Byte0]: 76
7928 23:50:51.360254 [Byte1]: 76
7929 23:50:51.364649
7930 23:50:51.365222 Set Vref, RX VrefLevel [Byte0]: 77
7931 23:50:51.368060 [Byte1]: 77
7932 23:50:51.372126
7933 23:50:51.372791 Set Vref, RX VrefLevel [Byte0]: 78
7934 23:50:51.375174 [Byte1]: 78
7935 23:50:51.379335
7936 23:50:51.379860 Set Vref, RX VrefLevel [Byte0]: 79
7937 23:50:51.382898 [Byte1]: 79
7938 23:50:51.387303
7939 23:50:51.387874 Final RX Vref Byte 0 = 63 to rank0
7940 23:50:51.390629 Final RX Vref Byte 1 = 63 to rank0
7941 23:50:51.393899 Final RX Vref Byte 0 = 63 to rank1
7942 23:50:51.397438 Final RX Vref Byte 1 = 63 to rank1==
7943 23:50:51.400385 Dram Type= 6, Freq= 0, CH_0, rank 0
7944 23:50:51.407022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7945 23:50:51.407596 ==
7946 23:50:51.407975 DQS Delay:
7947 23:50:51.408322 DQS0 = 0, DQS1 = 0
7948 23:50:51.410773 DQM Delay:
7949 23:50:51.411345 DQM0 = 134, DQM1 = 126
7950 23:50:51.413697 DQ Delay:
7951 23:50:51.417400 DQ0 =132, DQ1 =134, DQ2 =130, DQ3 =134
7952 23:50:51.420530 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
7953 23:50:51.423994 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
7954 23:50:51.427208 DQ12 =132, DQ13 =130, DQ14 =138, DQ15 =134
7955 23:50:51.427779
7956 23:50:51.428154
7957 23:50:51.428502
7958 23:50:51.430034 [DramC_TX_OE_Calibration] TA2
7959 23:50:51.433656 Original DQ_B0 (3 6) =30, OEN = 27
7960 23:50:51.437025 Original DQ_B1 (3 6) =30, OEN = 27
7961 23:50:51.440408 24, 0x0, End_B0=24 End_B1=24
7962 23:50:51.440928 25, 0x0, End_B0=25 End_B1=25
7963 23:50:51.443767 26, 0x0, End_B0=26 End_B1=26
7964 23:50:51.447423 27, 0x0, End_B0=27 End_B1=27
7965 23:50:51.450309 28, 0x0, End_B0=28 End_B1=28
7966 23:50:51.450789 29, 0x0, End_B0=29 End_B1=29
7967 23:50:51.453534 30, 0x0, End_B0=30 End_B1=30
7968 23:50:51.457183 31, 0x4141, End_B0=30 End_B1=30
7969 23:50:51.460375 Byte0 end_step=30 best_step=27
7970 23:50:51.463849 Byte1 end_step=30 best_step=27
7971 23:50:51.467163 Byte0 TX OE(2T, 0.5T) = (3, 3)
7972 23:50:51.467639 Byte1 TX OE(2T, 0.5T) = (3, 3)
7973 23:50:51.470630
7974 23:50:51.471201
7975 23:50:51.477134 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7976 23:50:51.480233 CH0 RK0: MR19=303, MR18=1D1B
7977 23:50:51.486775 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7978 23:50:51.487352
7979 23:50:51.490125 ----->DramcWriteLeveling(PI) begin...
7980 23:50:51.490731 ==
7981 23:50:51.493320 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 23:50:51.496869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 23:50:51.497446 ==
7984 23:50:51.500021 Write leveling (Byte 0): 37 => 37
7985 23:50:51.503353 Write leveling (Byte 1): 28 => 28
7986 23:50:51.506641 DramcWriteLeveling(PI) end<-----
7987 23:50:51.507109
7988 23:50:51.507481 ==
7989 23:50:51.510513 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 23:50:51.513432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 23:50:51.514001 ==
7992 23:50:51.516711 [Gating] SW mode calibration
7993 23:50:51.523402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7994 23:50:51.530208 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7995 23:50:51.533452 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 23:50:51.536602 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 23:50:51.543251 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 23:50:51.546646 1 4 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
7999 23:50:51.549487 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 23:50:51.556328 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 23:50:51.559984 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 23:50:51.563016 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 23:50:51.569593 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 23:50:51.573283 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 23:50:51.576369 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8006 23:50:51.583175 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (1 0)
8007 23:50:51.586280 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
8008 23:50:51.589996 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 23:50:51.596385 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 23:50:51.599916 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 23:50:51.602714 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 23:50:51.609688 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 23:50:51.612913 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8014 23:50:51.616450 1 6 12 | B1->B0 | 2b2a 4444 | 1 0 | (0 0) (0 0)
8015 23:50:51.623092 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8016 23:50:51.626246 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 23:50:51.629809 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 23:50:51.636395 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 23:50:51.639292 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 23:50:51.642800 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 23:50:51.646365 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8022 23:50:51.653026 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8023 23:50:51.655899 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8024 23:50:51.659652 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 23:50:51.666254 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 23:50:51.669438 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 23:50:51.672948 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 23:50:51.679574 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 23:50:51.682608 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 23:50:51.686139 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 23:50:51.692726 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 23:50:51.695942 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 23:50:51.699215 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 23:50:51.706001 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:50:51.709459 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:50:51.712811 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:50:51.719735 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8038 23:50:51.722739 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8039 23:50:51.725924 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8040 23:50:51.729440 Total UI for P1: 0, mck2ui 16
8041 23:50:51.732683 best dqsien dly found for B0: ( 1, 9, 10)
8042 23:50:51.739202 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 23:50:51.739780 Total UI for P1: 0, mck2ui 16
8044 23:50:51.745872 best dqsien dly found for B1: ( 1, 9, 14)
8045 23:50:51.749489 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8046 23:50:51.752496 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8047 23:50:51.753093
8048 23:50:51.755840 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8049 23:50:51.759296 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8050 23:50:51.762145 [Gating] SW calibration Done
8051 23:50:51.762609 ==
8052 23:50:51.765727 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 23:50:51.769176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 23:50:51.769745 ==
8055 23:50:51.772403 RX Vref Scan: 0
8056 23:50:51.773006
8057 23:50:51.773386 RX Vref 0 -> 0, step: 1
8058 23:50:51.773792
8059 23:50:51.775858 RX Delay 0 -> 252, step: 8
8060 23:50:51.778986 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8061 23:50:51.785777 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8062 23:50:51.789048 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8063 23:50:51.792390 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8064 23:50:51.795875 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8065 23:50:51.799354 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8066 23:50:51.805567 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8067 23:50:51.809054 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8068 23:50:51.812285 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8069 23:50:51.815575 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8070 23:50:51.819026 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8071 23:50:51.825607 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8072 23:50:51.828743 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8073 23:50:51.832386 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8074 23:50:51.835606 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8075 23:50:51.838916 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8076 23:50:51.839527 ==
8077 23:50:51.842297 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 23:50:51.848966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 23:50:51.849534 ==
8080 23:50:51.849908 DQS Delay:
8081 23:50:51.852139 DQS0 = 0, DQS1 = 0
8082 23:50:51.852745 DQM Delay:
8083 23:50:51.855388 DQM0 = 136, DQM1 = 127
8084 23:50:51.855864 DQ Delay:
8085 23:50:51.858813 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8086 23:50:51.862240 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8087 23:50:51.865758 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8088 23:50:51.869163 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8089 23:50:51.869730
8090 23:50:51.870102
8091 23:50:51.870444 ==
8092 23:50:51.872172 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 23:50:51.878509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 23:50:51.879181 ==
8095 23:50:51.879568
8096 23:50:51.879916
8097 23:50:51.880250 TX Vref Scan disable
8098 23:50:51.882080 == TX Byte 0 ==
8099 23:50:51.885626 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8100 23:50:51.892156 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8101 23:50:51.892726 == TX Byte 1 ==
8102 23:50:51.895519 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8103 23:50:51.902045 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8104 23:50:51.902634 ==
8105 23:50:51.905433 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 23:50:51.908735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 23:50:51.909199 ==
8108 23:50:51.923546
8109 23:50:51.926564 TX Vref early break, caculate TX vref
8110 23:50:51.930173 TX Vref=16, minBit 8, minWin=22, winSum=390
8111 23:50:51.933269 TX Vref=18, minBit 0, minWin=24, winSum=400
8112 23:50:51.936912 TX Vref=20, minBit 8, minWin=24, winSum=405
8113 23:50:51.939617 TX Vref=22, minBit 8, minWin=24, winSum=413
8114 23:50:51.943464 TX Vref=24, minBit 0, minWin=25, winSum=423
8115 23:50:51.949392 TX Vref=26, minBit 0, minWin=26, winSum=426
8116 23:50:51.952934 TX Vref=28, minBit 0, minWin=26, winSum=428
8117 23:50:51.956245 TX Vref=30, minBit 0, minWin=26, winSum=425
8118 23:50:51.959830 TX Vref=32, minBit 8, minWin=25, winSum=418
8119 23:50:51.962967 TX Vref=34, minBit 2, minWin=24, winSum=408
8120 23:50:51.966491 TX Vref=36, minBit 2, minWin=24, winSum=402
8121 23:50:51.973230 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8122 23:50:51.973696
8123 23:50:51.976509 Final TX Range 0 Vref 28
8124 23:50:51.977257
8125 23:50:51.977964 ==
8126 23:50:51.979816 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 23:50:51.982939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 23:50:51.983721 ==
8129 23:50:51.984324
8130 23:50:51.984884
8131 23:50:51.986043 TX Vref Scan disable
8132 23:50:51.992859 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8133 23:50:51.993365 == TX Byte 0 ==
8134 23:50:51.996071 u2DelayCellOfst[0]=13 cells (4 PI)
8135 23:50:51.999426 u2DelayCellOfst[1]=20 cells (6 PI)
8136 23:50:52.002928 u2DelayCellOfst[2]=13 cells (4 PI)
8137 23:50:52.006523 u2DelayCellOfst[3]=13 cells (4 PI)
8138 23:50:52.009616 u2DelayCellOfst[4]=10 cells (3 PI)
8139 23:50:52.012759 u2DelayCellOfst[5]=0 cells (0 PI)
8140 23:50:52.016147 u2DelayCellOfst[6]=20 cells (6 PI)
8141 23:50:52.019542 u2DelayCellOfst[7]=20 cells (6 PI)
8142 23:50:52.023109 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8143 23:50:52.026257 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8144 23:50:52.029391 == TX Byte 1 ==
8145 23:50:52.033209 u2DelayCellOfst[8]=0 cells (0 PI)
8146 23:50:52.036227 u2DelayCellOfst[9]=0 cells (0 PI)
8147 23:50:52.036834 u2DelayCellOfst[10]=6 cells (2 PI)
8148 23:50:52.039445 u2DelayCellOfst[11]=3 cells (1 PI)
8149 23:50:52.043022 u2DelayCellOfst[12]=13 cells (4 PI)
8150 23:50:52.046343 u2DelayCellOfst[13]=10 cells (3 PI)
8151 23:50:52.049331 u2DelayCellOfst[14]=13 cells (4 PI)
8152 23:50:52.053074 u2DelayCellOfst[15]=10 cells (3 PI)
8153 23:50:52.056258 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8154 23:50:52.062640 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8155 23:50:52.063356 DramC Write-DBI on
8156 23:50:52.063940 ==
8157 23:50:52.066035 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 23:50:52.073040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 23:50:52.073776 ==
8160 23:50:52.074428
8161 23:50:52.075046
8162 23:50:52.075612 TX Vref Scan disable
8163 23:50:52.076539 == TX Byte 0 ==
8164 23:50:52.079974 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8165 23:50:52.083355 == TX Byte 1 ==
8166 23:50:52.086655 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8167 23:50:52.089995 DramC Write-DBI off
8168 23:50:52.090463
8169 23:50:52.090832 [DATLAT]
8170 23:50:52.091175 Freq=1600, CH0 RK1
8171 23:50:52.091524
8172 23:50:52.093382 DATLAT Default: 0xf
8173 23:50:52.093706 0, 0xFFFF, sum = 0
8174 23:50:52.096163 1, 0xFFFF, sum = 0
8175 23:50:52.099520 2, 0xFFFF, sum = 0
8176 23:50:52.099764 3, 0xFFFF, sum = 0
8177 23:50:52.102748 4, 0xFFFF, sum = 0
8178 23:50:52.102941 5, 0xFFFF, sum = 0
8179 23:50:52.106289 6, 0xFFFF, sum = 0
8180 23:50:52.106591 7, 0xFFFF, sum = 0
8181 23:50:52.109603 8, 0xFFFF, sum = 0
8182 23:50:52.109804 9, 0xFFFF, sum = 0
8183 23:50:52.112853 10, 0xFFFF, sum = 0
8184 23:50:52.113047 11, 0xFFFF, sum = 0
8185 23:50:52.116396 12, 0xFFFF, sum = 0
8186 23:50:52.116697 13, 0xFFFF, sum = 0
8187 23:50:52.119323 14, 0x0, sum = 1
8188 23:50:52.119619 15, 0x0, sum = 2
8189 23:50:52.122726 16, 0x0, sum = 3
8190 23:50:52.122921 17, 0x0, sum = 4
8191 23:50:52.126064 best_step = 15
8192 23:50:52.126254
8193 23:50:52.126404 ==
8194 23:50:52.129746 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 23:50:52.132969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 23:50:52.133186 ==
8197 23:50:52.133341 RX Vref Scan: 0
8198 23:50:52.136128
8199 23:50:52.136318 RX Vref 0 -> 0, step: 1
8200 23:50:52.136470
8201 23:50:52.139510 RX Delay 19 -> 252, step: 4
8202 23:50:52.143152 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8203 23:50:52.150200 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8204 23:50:52.153113 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8205 23:50:52.156736 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8206 23:50:52.160456 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8207 23:50:52.163546 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8208 23:50:52.167012 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8209 23:50:52.173418 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8210 23:50:52.176932 iDelay=191, Bit 8, Center 118 (71 ~ 166) 96
8211 23:50:52.179860 iDelay=191, Bit 9, Center 114 (67 ~ 162) 96
8212 23:50:52.183477 iDelay=191, Bit 10, Center 126 (83 ~ 170) 88
8213 23:50:52.186447 iDelay=191, Bit 11, Center 122 (75 ~ 170) 96
8214 23:50:52.193023 iDelay=191, Bit 12, Center 130 (83 ~ 178) 96
8215 23:50:52.196435 iDelay=191, Bit 13, Center 130 (83 ~ 178) 96
8216 23:50:52.199635 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8217 23:50:52.202805 iDelay=191, Bit 15, Center 132 (83 ~ 182) 100
8218 23:50:52.203275 ==
8219 23:50:52.206175 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 23:50:52.213191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 23:50:52.213822 ==
8222 23:50:52.214209 DQS Delay:
8223 23:50:52.214560 DQS0 = 0, DQS1 = 0
8224 23:50:52.216258 DQM Delay:
8225 23:50:52.216858 DQM0 = 132, DQM1 = 125
8226 23:50:52.219857 DQ Delay:
8227 23:50:52.223181 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =130
8228 23:50:52.226435 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =138
8229 23:50:52.229450 DQ8 =118, DQ9 =114, DQ10 =126, DQ11 =122
8230 23:50:52.233166 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
8231 23:50:52.233728
8232 23:50:52.234107
8233 23:50:52.234457
8234 23:50:52.236155 [DramC_TX_OE_Calibration] TA2
8235 23:50:52.239728 Original DQ_B0 (3 6) =30, OEN = 27
8236 23:50:52.242903 Original DQ_B1 (3 6) =30, OEN = 27
8237 23:50:52.246365 24, 0x0, End_B0=24 End_B1=24
8238 23:50:52.246934 25, 0x0, End_B0=25 End_B1=25
8239 23:50:52.249781 26, 0x0, End_B0=26 End_B1=26
8240 23:50:52.253243 27, 0x0, End_B0=27 End_B1=27
8241 23:50:52.256619 28, 0x0, End_B0=28 End_B1=28
8242 23:50:52.257192 29, 0x0, End_B0=29 End_B1=29
8243 23:50:52.259776 30, 0x0, End_B0=30 End_B1=30
8244 23:50:52.263122 31, 0x4545, End_B0=30 End_B1=30
8245 23:50:52.266248 Byte0 end_step=30 best_step=27
8246 23:50:52.269845 Byte1 end_step=30 best_step=27
8247 23:50:52.272816 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 23:50:52.276327 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 23:50:52.276924
8250 23:50:52.277305
8251 23:50:52.283219 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8252 23:50:52.286179 CH0 RK1: MR19=303, MR18=210D
8253 23:50:52.293008 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8254 23:50:52.296353 [RxdqsGatingPostProcess] freq 1600
8255 23:50:52.299626 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 23:50:52.302645 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 23:50:52.306045 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 23:50:52.309227 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 23:50:52.312915 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 23:50:52.316399 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 23:50:52.319619 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 23:50:52.322761 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 23:50:52.326159 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 23:50:52.329384 Pre-setting of DQS Precalculation
8265 23:50:52.332872 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 23:50:52.333471 ==
8267 23:50:52.336323 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 23:50:52.339075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 23:50:52.339554 ==
8270 23:50:52.345821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 23:50:52.349491 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 23:50:52.356109 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 23:50:52.359061 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 23:50:52.369169 [CA 0] Center 40 (11~70) winsize 60
8275 23:50:52.372732 [CA 1] Center 41 (11~71) winsize 61
8276 23:50:52.375667 [CA 2] Center 37 (7~67) winsize 61
8277 23:50:52.379115 [CA 3] Center 36 (6~66) winsize 61
8278 23:50:52.382850 [CA 4] Center 37 (7~67) winsize 61
8279 23:50:52.385793 [CA 5] Center 36 (6~66) winsize 61
8280 23:50:52.386490
8281 23:50:52.389203 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8282 23:50:52.389764
8283 23:50:52.392628 [CATrainingPosCal] consider 1 rank data
8284 23:50:52.395808 u2DelayCellTimex100 = 285/100 ps
8285 23:50:52.399195 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8286 23:50:52.405932 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8287 23:50:52.409079 CA2 delay=37 (7~67),Diff = 1 PI (3 cell)
8288 23:50:52.412335 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8289 23:50:52.415692 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8290 23:50:52.419038 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8291 23:50:52.419603
8292 23:50:52.422393 CA PerBit enable=1, Macro0, CA PI delay=36
8293 23:50:52.422956
8294 23:50:52.425517 [CBTSetCACLKResult] CA Dly = 36
8295 23:50:52.428843 CS Dly: 8 (0~39)
8296 23:50:52.432253 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 23:50:52.435770 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 23:50:52.436226 ==
8299 23:50:52.438719 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 23:50:52.442173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 23:50:52.442706 ==
8302 23:50:52.448660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 23:50:52.452453 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 23:50:52.459019 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 23:50:52.462026 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 23:50:52.472384 [CA 0] Center 41 (12~71) winsize 60
8307 23:50:52.475890 [CA 1] Center 41 (12~71) winsize 60
8308 23:50:52.478970 [CA 2] Center 38 (8~68) winsize 61
8309 23:50:52.482654 [CA 3] Center 37 (8~67) winsize 60
8310 23:50:52.485508 [CA 4] Center 37 (8~67) winsize 60
8311 23:50:52.489075 [CA 5] Center 37 (7~67) winsize 61
8312 23:50:52.489627
8313 23:50:52.492177 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8314 23:50:52.492750
8315 23:50:52.496005 [CATrainingPosCal] consider 2 rank data
8316 23:50:52.499106 u2DelayCellTimex100 = 285/100 ps
8317 23:50:52.502004 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8318 23:50:52.509127 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8319 23:50:52.512031 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8320 23:50:52.515394 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8321 23:50:52.518720 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8322 23:50:52.521815 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 23:50:52.522275
8324 23:50:52.525099 CA PerBit enable=1, Macro0, CA PI delay=36
8325 23:50:52.525654
8326 23:50:52.528601 [CBTSetCACLKResult] CA Dly = 36
8327 23:50:52.531857 CS Dly: 9 (0~42)
8328 23:50:52.535210 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 23:50:52.538313 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 23:50:52.538772
8331 23:50:52.541682 ----->DramcWriteLeveling(PI) begin...
8332 23:50:52.542147 ==
8333 23:50:52.545156 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 23:50:52.551766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 23:50:52.552316 ==
8336 23:50:52.555324 Write leveling (Byte 0): 24 => 24
8337 23:50:52.555872 Write leveling (Byte 1): 31 => 31
8338 23:50:52.558112 DramcWriteLeveling(PI) end<-----
8339 23:50:52.558568
8340 23:50:52.558929 ==
8341 23:50:52.561969 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 23:50:52.568655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 23:50:52.569212 ==
8344 23:50:52.571819 [Gating] SW mode calibration
8345 23:50:52.578643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 23:50:52.581529 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 23:50:52.588594 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 23:50:52.591668 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 23:50:52.594696 1 4 8 | B1->B0 | 2f2f 3131 | 1 1 | (0 0) (1 1)
8350 23:50:52.601887 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 23:50:52.604930 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 23:50:52.608488 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 23:50:52.615168 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 23:50:52.618388 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 23:50:52.621366 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 23:50:52.625276 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 23:50:52.631718 1 5 8 | B1->B0 | 2f2f 2929 | 1 1 | (1 0) (1 0)
8358 23:50:52.634630 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8359 23:50:52.638228 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 23:50:52.644897 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 23:50:52.648213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:50:52.651875 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 23:50:52.657987 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 23:50:52.661623 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8365 23:50:52.665292 1 6 8 | B1->B0 | 3939 4242 | 1 0 | (1 1) (0 0)
8366 23:50:52.671473 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 23:50:52.674974 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 23:50:52.678580 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 23:50:52.684897 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 23:50:52.688446 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 23:50:52.691438 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 23:50:52.697967 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8373 23:50:52.701761 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8374 23:50:52.704831 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8375 23:50:52.711720 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8376 23:50:52.714591 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 23:50:52.718316 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 23:50:52.724734 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 23:50:52.728111 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 23:50:52.731314 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 23:50:52.737904 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 23:50:52.741096 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 23:50:52.744407 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 23:50:52.748108 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 23:50:52.754598 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:50:52.757802 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:50:52.760827 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:50:52.768058 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8389 23:50:52.771161 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8390 23:50:52.774760 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 23:50:52.781405 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 23:50:52.784342 Total UI for P1: 0, mck2ui 16
8393 23:50:52.787922 best dqsien dly found for B0: ( 1, 9, 8)
8394 23:50:52.791094 Total UI for P1: 0, mck2ui 16
8395 23:50:52.794611 best dqsien dly found for B1: ( 1, 9, 10)
8396 23:50:52.797614 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8397 23:50:52.801139 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8398 23:50:52.801702
8399 23:50:52.804339 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8400 23:50:52.807781 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8401 23:50:52.811007 [Gating] SW calibration Done
8402 23:50:52.811573 ==
8403 23:50:52.814479 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 23:50:52.817302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 23:50:52.817775 ==
8406 23:50:52.820887 RX Vref Scan: 0
8407 23:50:52.821462
8408 23:50:52.821838 RX Vref 0 -> 0, step: 1
8409 23:50:52.824327
8410 23:50:52.824838 RX Delay 0 -> 252, step: 8
8411 23:50:52.827586 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8412 23:50:52.834153 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8413 23:50:52.837188 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8414 23:50:52.840853 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8415 23:50:52.844168 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8416 23:50:52.847679 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8417 23:50:52.854482 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8418 23:50:52.857323 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8419 23:50:52.860939 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8420 23:50:52.864135 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8421 23:50:52.867348 iDelay=200, Bit 10, Center 135 (88 ~ 183) 96
8422 23:50:52.874235 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8423 23:50:52.877391 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8424 23:50:52.880627 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8425 23:50:52.884113 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8426 23:50:52.887589 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8427 23:50:52.890727 ==
8428 23:50:52.894128 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 23:50:52.897404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 23:50:52.897969 ==
8431 23:50:52.898348 DQS Delay:
8432 23:50:52.900426 DQS0 = 0, DQS1 = 0
8433 23:50:52.901024 DQM Delay:
8434 23:50:52.903746 DQM0 = 137, DQM1 = 131
8435 23:50:52.904310 DQ Delay:
8436 23:50:52.907237 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8437 23:50:52.910457 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8438 23:50:52.913799 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =123
8439 23:50:52.917124 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8440 23:50:52.917598
8441 23:50:52.917969
8442 23:50:52.918316 ==
8443 23:50:52.920530 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 23:50:52.927580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 23:50:52.928161 ==
8446 23:50:52.928541
8447 23:50:52.928921
8448 23:50:52.929251 TX Vref Scan disable
8449 23:50:52.930584 == TX Byte 0 ==
8450 23:50:52.934228 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8451 23:50:52.937227 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8452 23:50:52.940710 == TX Byte 1 ==
8453 23:50:52.944285 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8454 23:50:52.947096 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8455 23:50:52.950684 ==
8456 23:50:52.953808 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 23:50:52.957168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 23:50:52.957638 ==
8459 23:50:52.970185
8460 23:50:52.973407 TX Vref early break, caculate TX vref
8461 23:50:52.976932 TX Vref=16, minBit 8, minWin=21, winSum=366
8462 23:50:52.980115 TX Vref=18, minBit 8, minWin=22, winSum=375
8463 23:50:52.983331 TX Vref=20, minBit 8, minWin=23, winSum=388
8464 23:50:52.986230 TX Vref=22, minBit 8, minWin=23, winSum=393
8465 23:50:52.990034 TX Vref=24, minBit 10, minWin=24, winSum=405
8466 23:50:52.996733 TX Vref=26, minBit 8, minWin=25, winSum=416
8467 23:50:53.000290 TX Vref=28, minBit 8, minWin=25, winSum=418
8468 23:50:53.003394 TX Vref=30, minBit 8, minWin=24, winSum=415
8469 23:50:53.006665 TX Vref=32, minBit 8, minWin=24, winSum=403
8470 23:50:53.009777 TX Vref=34, minBit 8, minWin=22, winSum=394
8471 23:50:53.016537 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8472 23:50:53.017142
8473 23:50:53.019637 Final TX Range 0 Vref 28
8474 23:50:53.020244
8475 23:50:53.020712 ==
8476 23:50:53.022943 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 23:50:53.026362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 23:50:53.026833 ==
8479 23:50:53.027207
8480 23:50:53.027597
8481 23:50:53.029574 TX Vref Scan disable
8482 23:50:53.036379 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8483 23:50:53.037438 == TX Byte 0 ==
8484 23:50:53.039861 u2DelayCellOfst[0]=17 cells (5 PI)
8485 23:50:53.043071 u2DelayCellOfst[1]=10 cells (3 PI)
8486 23:50:53.046252 u2DelayCellOfst[2]=0 cells (0 PI)
8487 23:50:53.049427 u2DelayCellOfst[3]=6 cells (2 PI)
8488 23:50:53.053295 u2DelayCellOfst[4]=6 cells (2 PI)
8489 23:50:53.056111 u2DelayCellOfst[5]=17 cells (5 PI)
8490 23:50:53.059364 u2DelayCellOfst[6]=17 cells (5 PI)
8491 23:50:53.059829 u2DelayCellOfst[7]=3 cells (1 PI)
8492 23:50:53.066530 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8493 23:50:53.069339 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8494 23:50:53.072674 == TX Byte 1 ==
8495 23:50:53.073343 u2DelayCellOfst[8]=0 cells (0 PI)
8496 23:50:53.076286 u2DelayCellOfst[9]=3 cells (1 PI)
8497 23:50:53.079400 u2DelayCellOfst[10]=10 cells (3 PI)
8498 23:50:53.082703 u2DelayCellOfst[11]=3 cells (1 PI)
8499 23:50:53.086360 u2DelayCellOfst[12]=13 cells (4 PI)
8500 23:50:53.089385 u2DelayCellOfst[13]=17 cells (5 PI)
8501 23:50:53.092813 u2DelayCellOfst[14]=20 cells (6 PI)
8502 23:50:53.096122 u2DelayCellOfst[15]=17 cells (5 PI)
8503 23:50:53.099114 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8504 23:50:53.105919 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8505 23:50:53.106485 DramC Write-DBI on
8506 23:50:53.106859 ==
8507 23:50:53.109464 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 23:50:53.112912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 23:50:53.116100 ==
8510 23:50:53.116714
8511 23:50:53.117092
8512 23:50:53.117436 TX Vref Scan disable
8513 23:50:53.119506 == TX Byte 0 ==
8514 23:50:53.122927 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8515 23:50:53.125902 == TX Byte 1 ==
8516 23:50:53.129785 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8517 23:50:53.130354 DramC Write-DBI off
8518 23:50:53.132936
8519 23:50:53.133496 [DATLAT]
8520 23:50:53.133871 Freq=1600, CH1 RK0
8521 23:50:53.134219
8522 23:50:53.135763 DATLAT Default: 0xf
8523 23:50:53.136225 0, 0xFFFF, sum = 0
8524 23:50:53.139341 1, 0xFFFF, sum = 0
8525 23:50:53.139912 2, 0xFFFF, sum = 0
8526 23:50:53.142479 3, 0xFFFF, sum = 0
8527 23:50:53.145679 4, 0xFFFF, sum = 0
8528 23:50:53.146153 5, 0xFFFF, sum = 0
8529 23:50:53.149116 6, 0xFFFF, sum = 0
8530 23:50:53.149587 7, 0xFFFF, sum = 0
8531 23:50:53.152749 8, 0xFFFF, sum = 0
8532 23:50:53.153316 9, 0xFFFF, sum = 0
8533 23:50:53.156295 10, 0xFFFF, sum = 0
8534 23:50:53.156803 11, 0xFFFF, sum = 0
8535 23:50:53.159305 12, 0xFFFF, sum = 0
8536 23:50:53.159776 13, 0xFFFF, sum = 0
8537 23:50:53.162594 14, 0x0, sum = 1
8538 23:50:53.163170 15, 0x0, sum = 2
8539 23:50:53.165863 16, 0x0, sum = 3
8540 23:50:53.166432 17, 0x0, sum = 4
8541 23:50:53.169178 best_step = 15
8542 23:50:53.169640
8543 23:50:53.170012 ==
8544 23:50:53.172384 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 23:50:53.175986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 23:50:53.176605 ==
8547 23:50:53.177121 RX Vref Scan: 1
8548 23:50:53.179293
8549 23:50:53.179755 Set Vref Range= 24 -> 127
8550 23:50:53.180130
8551 23:50:53.182654 RX Vref 24 -> 127, step: 1
8552 23:50:53.183229
8553 23:50:53.186174 RX Delay 19 -> 252, step: 4
8554 23:50:53.186744
8555 23:50:53.189439 Set Vref, RX VrefLevel [Byte0]: 24
8556 23:50:53.192995 [Byte1]: 24
8557 23:50:53.193569
8558 23:50:53.195854 Set Vref, RX VrefLevel [Byte0]: 25
8559 23:50:53.198996 [Byte1]: 25
8560 23:50:53.199463
8561 23:50:53.202192 Set Vref, RX VrefLevel [Byte0]: 26
8562 23:50:53.205811 [Byte1]: 26
8563 23:50:53.209452
8564 23:50:53.210021 Set Vref, RX VrefLevel [Byte0]: 27
8565 23:50:53.213066 [Byte1]: 27
8566 23:50:53.217462
8567 23:50:53.218034 Set Vref, RX VrefLevel [Byte0]: 28
8568 23:50:53.220213 [Byte1]: 28
8569 23:50:53.225063
8570 23:50:53.225637 Set Vref, RX VrefLevel [Byte0]: 29
8571 23:50:53.227836 [Byte1]: 29
8572 23:50:53.232230
8573 23:50:53.232740 Set Vref, RX VrefLevel [Byte0]: 30
8574 23:50:53.235503 [Byte1]: 30
8575 23:50:53.239984
8576 23:50:53.240585 Set Vref, RX VrefLevel [Byte0]: 31
8577 23:50:53.243312 [Byte1]: 31
8578 23:50:53.247268
8579 23:50:53.247977 Set Vref, RX VrefLevel [Byte0]: 32
8580 23:50:53.250635 [Byte1]: 32
8581 23:50:53.255078
8582 23:50:53.255649 Set Vref, RX VrefLevel [Byte0]: 33
8583 23:50:53.258429 [Byte1]: 33
8584 23:50:53.262529
8585 23:50:53.263089 Set Vref, RX VrefLevel [Byte0]: 34
8586 23:50:53.266060 [Byte1]: 34
8587 23:50:53.270121
8588 23:50:53.270679 Set Vref, RX VrefLevel [Byte0]: 35
8589 23:50:53.273551 [Byte1]: 35
8590 23:50:53.277789
8591 23:50:53.278348 Set Vref, RX VrefLevel [Byte0]: 36
8592 23:50:53.280892 [Byte1]: 36
8593 23:50:53.285481
8594 23:50:53.286040 Set Vref, RX VrefLevel [Byte0]: 37
8595 23:50:53.288666 [Byte1]: 37
8596 23:50:53.293119
8597 23:50:53.293678 Set Vref, RX VrefLevel [Byte0]: 38
8598 23:50:53.296191 [Byte1]: 38
8599 23:50:53.300644
8600 23:50:53.301203 Set Vref, RX VrefLevel [Byte0]: 39
8601 23:50:53.303807 [Byte1]: 39
8602 23:50:53.308342
8603 23:50:53.308945 Set Vref, RX VrefLevel [Byte0]: 40
8604 23:50:53.311309 [Byte1]: 40
8605 23:50:53.315429
8606 23:50:53.315989 Set Vref, RX VrefLevel [Byte0]: 41
8607 23:50:53.318956 [Byte1]: 41
8608 23:50:53.323231
8609 23:50:53.323791 Set Vref, RX VrefLevel [Byte0]: 42
8610 23:50:53.326496 [Byte1]: 42
8611 23:50:53.330792
8612 23:50:53.334234 Set Vref, RX VrefLevel [Byte0]: 43
8613 23:50:53.334802 [Byte1]: 43
8614 23:50:53.338559
8615 23:50:53.339124 Set Vref, RX VrefLevel [Byte0]: 44
8616 23:50:53.341621 [Byte1]: 44
8617 23:50:53.346104
8618 23:50:53.346862 Set Vref, RX VrefLevel [Byte0]: 45
8619 23:50:53.348922 [Byte1]: 45
8620 23:50:53.353196
8621 23:50:53.353670 Set Vref, RX VrefLevel [Byte0]: 46
8622 23:50:53.356532 [Byte1]: 46
8623 23:50:53.361212
8624 23:50:53.361674 Set Vref, RX VrefLevel [Byte0]: 47
8625 23:50:53.364190 [Byte1]: 47
8626 23:50:53.368747
8627 23:50:53.369308 Set Vref, RX VrefLevel [Byte0]: 48
8628 23:50:53.372035 [Byte1]: 48
8629 23:50:53.376521
8630 23:50:53.377124 Set Vref, RX VrefLevel [Byte0]: 49
8631 23:50:53.379280 [Byte1]: 49
8632 23:50:53.383973
8633 23:50:53.384606 Set Vref, RX VrefLevel [Byte0]: 50
8634 23:50:53.387120 [Byte1]: 50
8635 23:50:53.391122
8636 23:50:53.391587 Set Vref, RX VrefLevel [Byte0]: 51
8637 23:50:53.394827 [Byte1]: 51
8638 23:50:53.398878
8639 23:50:53.399447 Set Vref, RX VrefLevel [Byte0]: 52
8640 23:50:53.402167 [Byte1]: 52
8641 23:50:53.406464
8642 23:50:53.407034 Set Vref, RX VrefLevel [Byte0]: 53
8643 23:50:53.409954 [Byte1]: 53
8644 23:50:53.413987
8645 23:50:53.414554 Set Vref, RX VrefLevel [Byte0]: 54
8646 23:50:53.417558 [Byte1]: 54
8647 23:50:53.421364
8648 23:50:53.421828 Set Vref, RX VrefLevel [Byte0]: 55
8649 23:50:53.425254 [Byte1]: 55
8650 23:50:53.429334
8651 23:50:53.429888 Set Vref, RX VrefLevel [Byte0]: 56
8652 23:50:53.432151 [Byte1]: 56
8653 23:50:53.437001
8654 23:50:53.437637 Set Vref, RX VrefLevel [Byte0]: 57
8655 23:50:53.440372 [Byte1]: 57
8656 23:50:53.444168
8657 23:50:53.444782 Set Vref, RX VrefLevel [Byte0]: 58
8658 23:50:53.447446 [Byte1]: 58
8659 23:50:53.452096
8660 23:50:53.452694 Set Vref, RX VrefLevel [Byte0]: 59
8661 23:50:53.454923 [Byte1]: 59
8662 23:50:53.459426
8663 23:50:53.459888 Set Vref, RX VrefLevel [Byte0]: 60
8664 23:50:53.463026 [Byte1]: 60
8665 23:50:53.466938
8666 23:50:53.467511 Set Vref, RX VrefLevel [Byte0]: 61
8667 23:50:53.470248 [Byte1]: 61
8668 23:50:53.474425
8669 23:50:53.474930 Set Vref, RX VrefLevel [Byte0]: 62
8670 23:50:53.477784 [Byte1]: 62
8671 23:50:53.482268
8672 23:50:53.482842 Set Vref, RX VrefLevel [Byte0]: 63
8673 23:50:53.485416 [Byte1]: 63
8674 23:50:53.489831
8675 23:50:53.490393 Set Vref, RX VrefLevel [Byte0]: 64
8676 23:50:53.493418 [Byte1]: 64
8677 23:50:53.497414
8678 23:50:53.497984 Set Vref, RX VrefLevel [Byte0]: 65
8679 23:50:53.500445 [Byte1]: 65
8680 23:50:53.505026
8681 23:50:53.505594 Set Vref, RX VrefLevel [Byte0]: 66
8682 23:50:53.508054 [Byte1]: 66
8683 23:50:53.512586
8684 23:50:53.513174 Set Vref, RX VrefLevel [Byte0]: 67
8685 23:50:53.515771 [Byte1]: 67
8686 23:50:53.520208
8687 23:50:53.520815 Set Vref, RX VrefLevel [Byte0]: 68
8688 23:50:53.523703 [Byte1]: 68
8689 23:50:53.527616
8690 23:50:53.528189 Set Vref, RX VrefLevel [Byte0]: 69
8691 23:50:53.531159 [Byte1]: 69
8692 23:50:53.535328
8693 23:50:53.535893 Set Vref, RX VrefLevel [Byte0]: 70
8694 23:50:53.538654 [Byte1]: 70
8695 23:50:53.542989
8696 23:50:53.543552 Set Vref, RX VrefLevel [Byte0]: 71
8697 23:50:53.546007 [Byte1]: 71
8698 23:50:53.549980
8699 23:50:53.550448 Set Vref, RX VrefLevel [Byte0]: 72
8700 23:50:53.553508 [Byte1]: 72
8701 23:50:53.557746
8702 23:50:53.558211 Set Vref, RX VrefLevel [Byte0]: 73
8703 23:50:53.560932 [Byte1]: 73
8704 23:50:53.565678
8705 23:50:53.566242 Set Vref, RX VrefLevel [Byte0]: 74
8706 23:50:53.568709 [Byte1]: 74
8707 23:50:53.573129
8708 23:50:53.573711 Set Vref, RX VrefLevel [Byte0]: 75
8709 23:50:53.576540 [Byte1]: 75
8710 23:50:53.580542
8711 23:50:53.581140 Final RX Vref Byte 0 = 58 to rank0
8712 23:50:53.583965 Final RX Vref Byte 1 = 61 to rank0
8713 23:50:53.587441 Final RX Vref Byte 0 = 58 to rank1
8714 23:50:53.590601 Final RX Vref Byte 1 = 61 to rank1==
8715 23:50:53.594009 Dram Type= 6, Freq= 0, CH_1, rank 0
8716 23:50:53.600662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 23:50:53.601231 ==
8718 23:50:53.601610 DQS Delay:
8719 23:50:53.601955 DQS0 = 0, DQS1 = 0
8720 23:50:53.604235 DQM Delay:
8721 23:50:53.604836 DQM0 = 134, DQM1 = 129
8722 23:50:53.607431 DQ Delay:
8723 23:50:53.610926 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8724 23:50:53.614091 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8725 23:50:53.617379 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8726 23:50:53.620297 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8727 23:50:53.620792
8728 23:50:53.621160
8729 23:50:53.621504
8730 23:50:53.623804 [DramC_TX_OE_Calibration] TA2
8731 23:50:53.627353 Original DQ_B0 (3 6) =30, OEN = 27
8732 23:50:53.630822 Original DQ_B1 (3 6) =30, OEN = 27
8733 23:50:53.633760 24, 0x0, End_B0=24 End_B1=24
8734 23:50:53.634234 25, 0x0, End_B0=25 End_B1=25
8735 23:50:53.637346 26, 0x0, End_B0=26 End_B1=26
8736 23:50:53.640447 27, 0x0, End_B0=27 End_B1=27
8737 23:50:53.644277 28, 0x0, End_B0=28 End_B1=28
8738 23:50:53.644901 29, 0x0, End_B0=29 End_B1=29
8739 23:50:53.647240 30, 0x0, End_B0=30 End_B1=30
8740 23:50:53.651039 31, 0x4141, End_B0=30 End_B1=30
8741 23:50:53.654207 Byte0 end_step=30 best_step=27
8742 23:50:53.657215 Byte1 end_step=30 best_step=27
8743 23:50:53.660640 Byte0 TX OE(2T, 0.5T) = (3, 3)
8744 23:50:53.661108 Byte1 TX OE(2T, 0.5T) = (3, 3)
8745 23:50:53.661476
8746 23:50:53.664098
8747 23:50:53.670393 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8748 23:50:53.673845 CH1 RK0: MR19=303, MR18=1A28
8749 23:50:53.680459 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8750 23:50:53.680966
8751 23:50:53.683813 ----->DramcWriteLeveling(PI) begin...
8752 23:50:53.684284 ==
8753 23:50:53.686725 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 23:50:53.690558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 23:50:53.691023 ==
8756 23:50:53.693546 Write leveling (Byte 0): 24 => 24
8757 23:50:53.696939 Write leveling (Byte 1): 29 => 29
8758 23:50:53.700262 DramcWriteLeveling(PI) end<-----
8759 23:50:53.700777
8760 23:50:53.701161 ==
8761 23:50:53.703842 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 23:50:53.706903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 23:50:53.707378 ==
8764 23:50:53.710458 [Gating] SW mode calibration
8765 23:50:53.717140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8766 23:50:53.723264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8767 23:50:53.726772 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 23:50:53.729896 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 23:50:53.736538 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8770 23:50:53.739635 1 4 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (0 0)
8771 23:50:53.743124 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 23:50:53.749572 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 23:50:53.753045 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 23:50:53.756173 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 23:50:53.763464 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 23:50:53.766311 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 23:50:53.769441 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8778 23:50:53.776168 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8779 23:50:53.779792 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 23:50:53.783108 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 23:50:53.789485 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 23:50:53.792915 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 23:50:53.796331 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:50:53.803117 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:50:53.806585 1 6 8 | B1->B0 | 4444 2323 | 0 0 | (0 0) (0 0)
8786 23:50:53.809566 1 6 12 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
8787 23:50:53.816247 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 23:50:53.820030 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 23:50:53.823202 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 23:50:53.826046 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 23:50:53.833286 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 23:50:53.836811 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 23:50:53.839913 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 23:50:53.846705 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 23:50:53.849826 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 23:50:53.852992 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 23:50:53.859603 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 23:50:53.862872 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 23:50:53.866146 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 23:50:53.872964 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 23:50:53.876382 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 23:50:53.879588 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 23:50:53.886580 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 23:50:53.889553 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 23:50:53.892954 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 23:50:53.899168 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 23:50:53.902520 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:50:53.905833 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:50:53.912671 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8810 23:50:53.915759 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8811 23:50:53.919403 Total UI for P1: 0, mck2ui 16
8812 23:50:53.922783 best dqsien dly found for B1: ( 1, 9, 8)
8813 23:50:53.925688 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 23:50:53.929364 Total UI for P1: 0, mck2ui 16
8815 23:50:53.932576 best dqsien dly found for B0: ( 1, 9, 10)
8816 23:50:53.936149 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8817 23:50:53.939251 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8818 23:50:53.939424
8819 23:50:53.942832 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8820 23:50:53.949429 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8821 23:50:53.949618 [Gating] SW calibration Done
8822 23:50:53.949730 ==
8823 23:50:53.952415 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 23:50:53.959227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 23:50:53.959419 ==
8826 23:50:53.959547 RX Vref Scan: 0
8827 23:50:53.959663
8828 23:50:53.962877 RX Vref 0 -> 0, step: 1
8829 23:50:53.963079
8830 23:50:53.965964 RX Delay 0 -> 252, step: 8
8831 23:50:53.968931 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8832 23:50:53.972186 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8833 23:50:53.975894 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8834 23:50:53.982395 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8835 23:50:53.985843 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8836 23:50:53.989207 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8837 23:50:53.992655 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8838 23:50:53.995752 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8839 23:50:54.002584 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8840 23:50:54.006132 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8841 23:50:54.008880 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8842 23:50:54.012499 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8843 23:50:54.015933 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8844 23:50:54.022398 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8845 23:50:54.025666 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8846 23:50:54.028774 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8847 23:50:54.029240 ==
8848 23:50:54.032662 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 23:50:54.035813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 23:50:54.036383 ==
8851 23:50:54.039388 DQS Delay:
8852 23:50:54.039949 DQS0 = 0, DQS1 = 0
8853 23:50:54.042314 DQM Delay:
8854 23:50:54.042778 DQM0 = 136, DQM1 = 132
8855 23:50:54.043183 DQ Delay:
8856 23:50:54.049046 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8857 23:50:54.052189 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8858 23:50:54.055810 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8859 23:50:54.058792 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8860 23:50:54.059259
8861 23:50:54.059628
8862 23:50:54.060048 ==
8863 23:50:54.062367 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 23:50:54.065402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 23:50:54.065891 ==
8866 23:50:54.066300
8867 23:50:54.066645
8868 23:50:54.068795 TX Vref Scan disable
8869 23:50:54.072389 == TX Byte 0 ==
8870 23:50:54.075449 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8871 23:50:54.078812 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8872 23:50:54.082278 == TX Byte 1 ==
8873 23:50:54.085663 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8874 23:50:54.088857 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8875 23:50:54.089365 ==
8876 23:50:54.092045 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 23:50:54.095554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 23:50:54.098830 ==
8879 23:50:54.110506
8880 23:50:54.113590 TX Vref early break, caculate TX vref
8881 23:50:54.116983 TX Vref=16, minBit 11, minWin=22, winSum=379
8882 23:50:54.119965 TX Vref=18, minBit 9, minWin=22, winSum=393
8883 23:50:54.123704 TX Vref=20, minBit 9, minWin=23, winSum=398
8884 23:50:54.126857 TX Vref=22, minBit 9, minWin=23, winSum=406
8885 23:50:54.130532 TX Vref=24, minBit 9, minWin=24, winSum=413
8886 23:50:54.136601 TX Vref=26, minBit 11, minWin=24, winSum=418
8887 23:50:54.140123 TX Vref=28, minBit 9, minWin=25, winSum=420
8888 23:50:54.142954 TX Vref=30, minBit 9, minWin=24, winSum=412
8889 23:50:54.146775 TX Vref=32, minBit 0, minWin=24, winSum=405
8890 23:50:54.149887 TX Vref=34, minBit 9, minWin=23, winSum=395
8891 23:50:54.156462 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 28
8892 23:50:54.156977
8893 23:50:54.159482 Final TX Range 0 Vref 28
8894 23:50:54.160005
8895 23:50:54.160396 ==
8896 23:50:54.163105 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 23:50:54.166767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 23:50:54.167346 ==
8899 23:50:54.167729
8900 23:50:54.168078
8901 23:50:54.169830 TX Vref Scan disable
8902 23:50:54.176376 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8903 23:50:54.177013 == TX Byte 0 ==
8904 23:50:54.179464 u2DelayCellOfst[0]=13 cells (4 PI)
8905 23:50:54.183601 u2DelayCellOfst[1]=10 cells (3 PI)
8906 23:50:54.186643 u2DelayCellOfst[2]=0 cells (0 PI)
8907 23:50:54.189230 u2DelayCellOfst[3]=3 cells (1 PI)
8908 23:50:54.192661 u2DelayCellOfst[4]=6 cells (2 PI)
8909 23:50:54.195942 u2DelayCellOfst[5]=17 cells (5 PI)
8910 23:50:54.199506 u2DelayCellOfst[6]=17 cells (5 PI)
8911 23:50:54.203056 u2DelayCellOfst[7]=6 cells (2 PI)
8912 23:50:54.206103 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 23:50:54.209545 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 23:50:54.212778 == TX Byte 1 ==
8915 23:50:54.216404 u2DelayCellOfst[8]=0 cells (0 PI)
8916 23:50:54.217006 u2DelayCellOfst[9]=3 cells (1 PI)
8917 23:50:54.219347 u2DelayCellOfst[10]=6 cells (2 PI)
8918 23:50:54.222768 u2DelayCellOfst[11]=0 cells (0 PI)
8919 23:50:54.226158 u2DelayCellOfst[12]=10 cells (3 PI)
8920 23:50:54.229110 u2DelayCellOfst[13]=13 cells (4 PI)
8921 23:50:54.232971 u2DelayCellOfst[14]=17 cells (5 PI)
8922 23:50:54.236000 u2DelayCellOfst[15]=17 cells (5 PI)
8923 23:50:54.239649 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8924 23:50:54.245934 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 23:50:54.246501 DramC Write-DBI on
8926 23:50:54.246873 ==
8927 23:50:54.249429 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 23:50:54.252474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 23:50:54.255973 ==
8930 23:50:54.256439
8931 23:50:54.256868
8932 23:50:54.257220 TX Vref Scan disable
8933 23:50:54.259519 == TX Byte 0 ==
8934 23:50:54.262936 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8935 23:50:54.266335 == TX Byte 1 ==
8936 23:50:54.269837 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 23:50:54.270408 DramC Write-DBI off
8938 23:50:54.272713
8939 23:50:54.273177 [DATLAT]
8940 23:50:54.273550 Freq=1600, CH1 RK1
8941 23:50:54.273897
8942 23:50:54.276331 DATLAT Default: 0xf
8943 23:50:54.276818 0, 0xFFFF, sum = 0
8944 23:50:54.279893 1, 0xFFFF, sum = 0
8945 23:50:54.280462 2, 0xFFFF, sum = 0
8946 23:50:54.283239 3, 0xFFFF, sum = 0
8947 23:50:54.286069 4, 0xFFFF, sum = 0
8948 23:50:54.286541 5, 0xFFFF, sum = 0
8949 23:50:54.289405 6, 0xFFFF, sum = 0
8950 23:50:54.289974 7, 0xFFFF, sum = 0
8951 23:50:54.292629 8, 0xFFFF, sum = 0
8952 23:50:54.293102 9, 0xFFFF, sum = 0
8953 23:50:54.296404 10, 0xFFFF, sum = 0
8954 23:50:54.297075 11, 0xFFFF, sum = 0
8955 23:50:54.299450 12, 0xFFFF, sum = 0
8956 23:50:54.300024 13, 0xFFFF, sum = 0
8957 23:50:54.302828 14, 0x0, sum = 1
8958 23:50:54.303453 15, 0x0, sum = 2
8959 23:50:54.306415 16, 0x0, sum = 3
8960 23:50:54.306888 17, 0x0, sum = 4
8961 23:50:54.309566 best_step = 15
8962 23:50:54.310081
8963 23:50:54.310458 ==
8964 23:50:54.313056 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 23:50:54.316173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 23:50:54.316793 ==
8967 23:50:54.317178 RX Vref Scan: 0
8968 23:50:54.317589
8969 23:50:54.319878 RX Vref 0 -> 0, step: 1
8970 23:50:54.320544
8971 23:50:54.322885 RX Delay 19 -> 252, step: 4
8972 23:50:54.326277 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8973 23:50:54.329478 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8974 23:50:54.336129 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8975 23:50:54.339832 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8976 23:50:54.343017 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8977 23:50:54.346112 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8978 23:50:54.349473 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8979 23:50:54.356348 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8980 23:50:54.359523 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8981 23:50:54.362955 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8982 23:50:54.366171 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8983 23:50:54.369612 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8984 23:50:54.376098 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8985 23:50:54.379604 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8986 23:50:54.382716 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8987 23:50:54.386141 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8988 23:50:54.386619 ==
8989 23:50:54.389473 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 23:50:54.396262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 23:50:54.396872 ==
8992 23:50:54.397255 DQS Delay:
8993 23:50:54.397601 DQS0 = 0, DQS1 = 0
8994 23:50:54.399025 DQM Delay:
8995 23:50:54.399485 DQM0 = 133, DQM1 = 129
8996 23:50:54.402315 DQ Delay:
8997 23:50:54.405794 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8998 23:50:54.409185 DQ4 =134, DQ5 =144, DQ6 =140, DQ7 =130
8999 23:50:54.412836 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9000 23:50:54.416228 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
9001 23:50:54.416855
9002 23:50:54.417243
9003 23:50:54.417591
9004 23:50:54.419453 [DramC_TX_OE_Calibration] TA2
9005 23:50:54.422643 Original DQ_B0 (3 6) =30, OEN = 27
9006 23:50:54.426164 Original DQ_B1 (3 6) =30, OEN = 27
9007 23:50:54.429701 24, 0x0, End_B0=24 End_B1=24
9008 23:50:54.430285 25, 0x0, End_B0=25 End_B1=25
9009 23:50:54.432823 26, 0x0, End_B0=26 End_B1=26
9010 23:50:54.435835 27, 0x0, End_B0=27 End_B1=27
9011 23:50:54.439342 28, 0x0, End_B0=28 End_B1=28
9012 23:50:54.439926 29, 0x0, End_B0=29 End_B1=29
9013 23:50:54.442786 30, 0x0, End_B0=30 End_B1=30
9014 23:50:54.445822 31, 0x4141, End_B0=30 End_B1=30
9015 23:50:54.449455 Byte0 end_step=30 best_step=27
9016 23:50:54.452697 Byte1 end_step=30 best_step=27
9017 23:50:54.456073 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 23:50:54.456704 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 23:50:54.459155
9020 23:50:54.459727
9021 23:50:54.465879 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
9022 23:50:54.469134 CH1 RK1: MR19=303, MR18=1F0A
9023 23:50:54.476033 CH1_RK1: MR19=0x303, MR18=0x1F0A, DQSOSC=394, MR23=63, INC=23, DEC=15
9024 23:50:54.479229 [RxdqsGatingPostProcess] freq 1600
9025 23:50:54.482421 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 23:50:54.485812 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 23:50:54.489119 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 23:50:54.492432 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 23:50:54.495897 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 23:50:54.498795 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 23:50:54.502186 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 23:50:54.505588 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 23:50:54.508802 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 23:50:54.512675 Pre-setting of DQS Precalculation
9035 23:50:54.515560 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 23:50:54.522494 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 23:50:54.528898 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 23:50:54.529459
9039 23:50:54.529837
9040 23:50:54.532182 [Calibration Summary] 3200 Mbps
9041 23:50:54.535668 CH 0, Rank 0
9042 23:50:54.536233 SW Impedance : PASS
9043 23:50:54.539340 DUTY Scan : NO K
9044 23:50:54.542567 ZQ Calibration : PASS
9045 23:50:54.543143 Jitter Meter : NO K
9046 23:50:54.545933 CBT Training : PASS
9047 23:50:54.549049 Write leveling : PASS
9048 23:50:54.549627 RX DQS gating : PASS
9049 23:50:54.551960 RX DQ/DQS(RDDQC) : PASS
9050 23:50:54.555951 TX DQ/DQS : PASS
9051 23:50:54.556531 RX DATLAT : PASS
9052 23:50:54.558812 RX DQ/DQS(Engine): PASS
9053 23:50:54.559386 TX OE : PASS
9054 23:50:54.562104 All Pass.
9055 23:50:54.562574
9056 23:50:54.562948 CH 0, Rank 1
9057 23:50:54.565219 SW Impedance : PASS
9058 23:50:54.569006 DUTY Scan : NO K
9059 23:50:54.569579 ZQ Calibration : PASS
9060 23:50:54.572103 Jitter Meter : NO K
9061 23:50:54.572704 CBT Training : PASS
9062 23:50:54.575537 Write leveling : PASS
9063 23:50:54.578727 RX DQS gating : PASS
9064 23:50:54.579325 RX DQ/DQS(RDDQC) : PASS
9065 23:50:54.582213 TX DQ/DQS : PASS
9066 23:50:54.585436 RX DATLAT : PASS
9067 23:50:54.586008 RX DQ/DQS(Engine): PASS
9068 23:50:54.589004 TX OE : PASS
9069 23:50:54.589588 All Pass.
9070 23:50:54.589971
9071 23:50:54.592335 CH 1, Rank 0
9072 23:50:54.592937 SW Impedance : PASS
9073 23:50:54.595458 DUTY Scan : NO K
9074 23:50:54.598601 ZQ Calibration : PASS
9075 23:50:54.599077 Jitter Meter : NO K
9076 23:50:54.602233 CBT Training : PASS
9077 23:50:54.605567 Write leveling : PASS
9078 23:50:54.606044 RX DQS gating : PASS
9079 23:50:54.608813 RX DQ/DQS(RDDQC) : PASS
9080 23:50:54.609308 TX DQ/DQS : PASS
9081 23:50:54.612120 RX DATLAT : PASS
9082 23:50:54.615391 RX DQ/DQS(Engine): PASS
9083 23:50:54.615968 TX OE : PASS
9084 23:50:54.618838 All Pass.
9085 23:50:54.619310
9086 23:50:54.619685 CH 1, Rank 1
9087 23:50:54.622045 SW Impedance : PASS
9088 23:50:54.622516 DUTY Scan : NO K
9089 23:50:54.625404 ZQ Calibration : PASS
9090 23:50:54.628842 Jitter Meter : NO K
9091 23:50:54.629433 CBT Training : PASS
9092 23:50:54.632375 Write leveling : PASS
9093 23:50:54.635280 RX DQS gating : PASS
9094 23:50:54.635852 RX DQ/DQS(RDDQC) : PASS
9095 23:50:54.638353 TX DQ/DQS : PASS
9096 23:50:54.641934 RX DATLAT : PASS
9097 23:50:54.642552 RX DQ/DQS(Engine): PASS
9098 23:50:54.645178 TX OE : PASS
9099 23:50:54.645654 All Pass.
9100 23:50:54.646031
9101 23:50:54.648572 DramC Write-DBI on
9102 23:50:54.652132 PER_BANK_REFRESH: Hybrid Mode
9103 23:50:54.652757 TX_TRACKING: ON
9104 23:50:54.662200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 23:50:54.669168 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 23:50:54.675808 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 23:50:54.679113 [FAST_K] Save calibration result to emmc
9108 23:50:54.682343 sync common calibartion params.
9109 23:50:54.685658 sync cbt_mode0:1, 1:1
9110 23:50:54.686268 dram_init: ddr_geometry: 2
9111 23:50:54.688769 dram_init: ddr_geometry: 2
9112 23:50:54.692212 dram_init: ddr_geometry: 2
9113 23:50:54.695698 0:dram_rank_size:100000000
9114 23:50:54.696281 1:dram_rank_size:100000000
9115 23:50:54.702040 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 23:50:54.705472 DFS_SHUFFLE_HW_MODE: ON
9117 23:50:54.708767 dramc_set_vcore_voltage set vcore to 725000
9118 23:50:54.712058 Read voltage for 1600, 0
9119 23:50:54.712679 Vio18 = 0
9120 23:50:54.713087 Vcore = 725000
9121 23:50:54.715286 Vdram = 0
9122 23:50:54.715906 Vddq = 0
9123 23:50:54.716307 Vmddr = 0
9124 23:50:54.718854 switch to 3200 Mbps bootup
9125 23:50:54.719430 [DramcRunTimeConfig]
9126 23:50:54.721986 PHYPLL
9127 23:50:54.722457 DPM_CONTROL_AFTERK: ON
9128 23:50:54.725124 PER_BANK_REFRESH: ON
9129 23:50:54.728270 REFRESH_OVERHEAD_REDUCTION: ON
9130 23:50:54.728828 CMD_PICG_NEW_MODE: OFF
9131 23:50:54.731784 XRTWTW_NEW_MODE: ON
9132 23:50:54.732385 XRTRTR_NEW_MODE: ON
9133 23:50:54.735014 TX_TRACKING: ON
9134 23:50:54.735589 RDSEL_TRACKING: OFF
9135 23:50:54.738453 DQS Precalculation for DVFS: ON
9136 23:50:54.741720 RX_TRACKING: OFF
9137 23:50:54.742297 HW_GATING DBG: ON
9138 23:50:54.745269 ZQCS_ENABLE_LP4: ON
9139 23:50:54.745837 RX_PICG_NEW_MODE: ON
9140 23:50:54.748515 TX_PICG_NEW_MODE: ON
9141 23:50:54.749100 ENABLE_RX_DCM_DPHY: ON
9142 23:50:54.751507 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 23:50:54.755113 DUMMY_READ_FOR_TRACKING: OFF
9144 23:50:54.758633 !!! SPM_CONTROL_AFTERK: OFF
9145 23:50:54.761653 !!! SPM could not control APHY
9146 23:50:54.762123 IMPEDANCE_TRACKING: ON
9147 23:50:54.765408 TEMP_SENSOR: ON
9148 23:50:54.765975 HW_SAVE_FOR_SR: OFF
9149 23:50:54.768238 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 23:50:54.771810 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 23:50:54.774952 Read ODT Tracking: ON
9152 23:50:54.778417 Refresh Rate DeBounce: ON
9153 23:50:54.778981 DFS_NO_QUEUE_FLUSH: ON
9154 23:50:54.781897 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 23:50:54.785460 ENABLE_DFS_RUNTIME_MRW: OFF
9156 23:50:54.788723 DDR_RESERVE_NEW_MODE: ON
9157 23:50:54.789312 MR_CBT_SWITCH_FREQ: ON
9158 23:50:54.791576 =========================
9159 23:50:54.810671 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 23:50:54.813531 dram_init: ddr_geometry: 2
9161 23:50:54.831954 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 23:50:54.835497 dram_init: dram init end (result: 0)
9163 23:50:54.842061 DRAM-K: Full calibration passed in 24536 msecs
9164 23:50:54.845264 MRC: failed to locate region type 0.
9165 23:50:54.845785 DRAM rank0 size:0x100000000,
9166 23:50:54.848916 DRAM rank1 size=0x100000000
9167 23:50:54.859032 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 23:50:54.865210 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 23:50:54.872300 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 23:50:54.878632 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 23:50:54.881583 DRAM rank0 size:0x100000000,
9172 23:50:54.885185 DRAM rank1 size=0x100000000
9173 23:50:54.885653 CBMEM:
9174 23:50:54.888211 IMD: root @ 0xfffff000 254 entries.
9175 23:50:54.891987 IMD: root @ 0xffffec00 62 entries.
9176 23:50:54.895377 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 23:50:54.898454 WARNING: RO_VPD is uninitialized or empty.
9178 23:50:54.905123 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 23:50:54.912270 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 23:50:54.925190 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9181 23:50:54.936635 BS: romstage times (exec / console): total (unknown) / 24027 ms
9182 23:50:54.937210
9183 23:50:54.937585
9184 23:50:54.946324 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 23:50:54.949847 ARM64: Exception handlers installed.
9186 23:50:54.953268 ARM64: Testing exception
9187 23:50:54.956123 ARM64: Done test exception
9188 23:50:54.956628 Enumerating buses...
9189 23:50:54.959996 Show all devs... Before device enumeration.
9190 23:50:54.962967 Root Device: enabled 1
9191 23:50:54.966388 CPU_CLUSTER: 0: enabled 1
9192 23:50:54.966956 CPU: 00: enabled 1
9193 23:50:54.969823 Compare with tree...
9194 23:50:54.970389 Root Device: enabled 1
9195 23:50:54.972774 CPU_CLUSTER: 0: enabled 1
9196 23:50:54.976623 CPU: 00: enabled 1
9197 23:50:54.977188 Root Device scanning...
9198 23:50:54.979754 scan_static_bus for Root Device
9199 23:50:54.982971 CPU_CLUSTER: 0 enabled
9200 23:50:54.985977 scan_static_bus for Root Device done
9201 23:50:54.989296 scan_bus: bus Root Device finished in 8 msecs
9202 23:50:54.989765 done
9203 23:50:54.996468 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 23:50:54.999493 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 23:50:55.006105 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 23:50:55.009479 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 23:50:55.012381 Allocating resources...
9208 23:50:55.016093 Reading resources...
9209 23:50:55.019123 Root Device read_resources bus 0 link: 0
9210 23:50:55.019695 DRAM rank0 size:0x100000000,
9211 23:50:55.022812 DRAM rank1 size=0x100000000
9212 23:50:55.025851 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 23:50:55.029378 CPU: 00 missing read_resources
9214 23:50:55.035915 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 23:50:55.039349 Root Device read_resources bus 0 link: 0 done
9216 23:50:55.039916 Done reading resources.
9217 23:50:55.045782 Show resources in subtree (Root Device)...After reading.
9218 23:50:55.049260 Root Device child on link 0 CPU_CLUSTER: 0
9219 23:50:55.052672 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 23:50:55.062447 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 23:50:55.063005 CPU: 00
9222 23:50:55.065829 Root Device assign_resources, bus 0 link: 0
9223 23:50:55.069097 CPU_CLUSTER: 0 missing set_resources
9224 23:50:55.075421 Root Device assign_resources, bus 0 link: 0 done
9225 23:50:55.075895 Done setting resources.
9226 23:50:55.082359 Show resources in subtree (Root Device)...After assigning values.
9227 23:50:55.085988 Root Device child on link 0 CPU_CLUSTER: 0
9228 23:50:55.089151 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 23:50:55.098804 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 23:50:55.099338 CPU: 00
9231 23:50:55.102143 Done allocating resources.
9232 23:50:55.105706 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 23:50:55.108993 Enabling resources...
9234 23:50:55.109484 done.
9235 23:50:55.114968 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 23:50:55.115460 Initializing devices...
9237 23:50:55.118746 Root Device init
9238 23:50:55.119289 init hardware done!
9239 23:50:55.122186 0x00000018: ctrlr->caps
9240 23:50:55.125024 52.000 MHz: ctrlr->f_max
9241 23:50:55.125608 0.400 MHz: ctrlr->f_min
9242 23:50:55.128299 0x40ff8080: ctrlr->voltages
9243 23:50:55.128998 sclk: 390625
9244 23:50:55.131742 Bus Width = 1
9245 23:50:55.132318 sclk: 390625
9246 23:50:55.135186 Bus Width = 1
9247 23:50:55.135837 Early init status = 3
9248 23:50:55.141930 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 23:50:55.144976 in-header: 03 fc 00 00 01 00 00 00
9250 23:50:55.145473 in-data: 00
9251 23:50:55.151989 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 23:50:55.155239 in-header: 03 fd 00 00 00 00 00 00
9253 23:50:55.158486 in-data:
9254 23:50:55.161724 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 23:50:55.164929 in-header: 03 fc 00 00 01 00 00 00
9256 23:50:55.168669 in-data: 00
9257 23:50:55.171877 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 23:50:55.176542 in-header: 03 fd 00 00 00 00 00 00
9259 23:50:55.180203 in-data:
9260 23:50:55.183298 [SSUSB] Setting up USB HOST controller...
9261 23:50:55.186902 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 23:50:55.190060 [SSUSB] phy power-on done.
9263 23:50:55.193667 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 23:50:55.200077 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 23:50:55.203117 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 23:50:55.209997 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 23:50:55.216615 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9268 23:50:55.223573 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 23:50:55.230154 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 23:50:55.236670 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9271 23:50:55.237160 SPM: binary array size = 0x9dc
9272 23:50:55.243516 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 23:50:55.249711 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 23:50:55.256418 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 23:50:55.259876 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 23:50:55.263132 configure_display: Starting display init
9277 23:50:55.299955 anx7625_power_on_init: Init interface.
9278 23:50:55.303046 anx7625_disable_pd_protocol: Disabled PD feature.
9279 23:50:55.306533 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 23:50:55.334297 anx7625_start_dp_work: Secure OCM version=00
9281 23:50:55.337891 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 23:50:55.352538 sp_tx_get_edid_block: EDID Block = 1
9283 23:50:55.455009 Extracted contents:
9284 23:50:55.458486 header: 00 ff ff ff ff ff ff 00
9285 23:50:55.461504 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 23:50:55.464811 version: 01 04
9287 23:50:55.468133 basic params: 95 1f 11 78 0a
9288 23:50:55.471528 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 23:50:55.474793 established: 00 00 00
9290 23:50:55.481581 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 23:50:55.484623 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 23:50:55.491396 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 23:50:55.498195 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 23:50:55.504816 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 23:50:55.507997 extensions: 00
9296 23:50:55.508521 checksum: fb
9297 23:50:55.508922
9298 23:50:55.511488 Manufacturer: IVO Model 57d Serial Number 0
9299 23:50:55.514127 Made week 0 of 2020
9300 23:50:55.514208 EDID version: 1.4
9301 23:50:55.517791 Digital display
9302 23:50:55.520923 6 bits per primary color channel
9303 23:50:55.521005 DisplayPort interface
9304 23:50:55.524206 Maximum image size: 31 cm x 17 cm
9305 23:50:55.527659 Gamma: 220%
9306 23:50:55.527740 Check DPMS levels
9307 23:50:55.530777 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 23:50:55.534127 First detailed timing is preferred timing
9309 23:50:55.537533 Established timings supported:
9310 23:50:55.541036 Standard timings supported:
9311 23:50:55.544075 Detailed timings
9312 23:50:55.547646 Hex of detail: 383680a07038204018303c0035ae10000019
9313 23:50:55.550948 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 23:50:55.557690 0780 0798 07c8 0820 hborder 0
9315 23:50:55.561034 0438 043b 0447 0458 vborder 0
9316 23:50:55.564122 -hsync -vsync
9317 23:50:55.564233 Did detailed timing
9318 23:50:55.567603 Hex of detail: 000000000000000000000000000000000000
9319 23:50:55.570922 Manufacturer-specified data, tag 0
9320 23:50:55.577642 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 23:50:55.577722 ASCII string: InfoVision
9322 23:50:55.584035 Hex of detail: 000000fe00523134304e574635205248200a
9323 23:50:55.587626 ASCII string: R140NWF5 RH
9324 23:50:55.587707 Checksum
9325 23:50:55.587770 Checksum: 0xfb (valid)
9326 23:50:55.594332 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 23:50:55.597560 DSI data_rate: 832800000 bps
9328 23:50:55.600715 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 23:50:55.607531 anx7625_parse_edid: pixelclock(138800).
9330 23:50:55.611066 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 23:50:55.614264 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 23:50:55.617529 anx7625_dsi_config: config dsi.
9333 23:50:55.624068 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 23:50:55.636835 anx7625_dsi_config: success to config DSI
9335 23:50:55.639875 anx7625_dp_start: MIPI phy setup OK.
9336 23:50:55.643288 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 23:50:55.646699 mtk_ddp_mode_set invalid vrefresh 60
9338 23:50:55.650023 main_disp_path_setup
9339 23:50:55.650103 ovl_layer_smi_id_en
9340 23:50:55.653075 ovl_layer_smi_id_en
9341 23:50:55.653155 ccorr_config
9342 23:50:55.653219 aal_config
9343 23:50:55.656477 gamma_config
9344 23:50:55.656616 postmask_config
9345 23:50:55.659835 dither_config
9346 23:50:55.663156 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 23:50:55.670038 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 23:50:55.673413 Root Device init finished in 552 msecs
9349 23:50:55.676819 CPU_CLUSTER: 0 init
9350 23:50:55.683199 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 23:50:55.686477 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 23:50:55.689931 APU_MBOX 0x190000b0 = 0x10001
9353 23:50:55.693051 APU_MBOX 0x190001b0 = 0x10001
9354 23:50:55.696662 APU_MBOX 0x190005b0 = 0x10001
9355 23:50:55.699796 APU_MBOX 0x190006b0 = 0x10001
9356 23:50:55.702962 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 23:50:55.715799 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9358 23:50:55.728222 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 23:50:55.734705 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 23:50:55.746393 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9361 23:50:55.755519 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 23:50:55.758933 CPU_CLUSTER: 0 init finished in 81 msecs
9363 23:50:55.761973 Devices initialized
9364 23:50:55.765638 Show all devs... After init.
9365 23:50:55.765726 Root Device: enabled 1
9366 23:50:55.768919 CPU_CLUSTER: 0: enabled 1
9367 23:50:55.772119 CPU: 00: enabled 1
9368 23:50:55.775182 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9369 23:50:55.778498 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 23:50:55.781965 ELOG: NV offset 0x57f000 size 0x1000
9371 23:50:55.788877 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9372 23:50:55.795302 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 23:50:55.798886 ELOG: Event(17) added with size 13 at 2024-05-29 23:49:29 UTC
9374 23:50:55.802109 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 23:50:55.805694 in-header: 03 4c 00 00 2c 00 00 00
9376 23:50:55.819007 in-data: f3 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 23:50:55.825683 ELOG: Event(A1) added with size 10 at 2024-05-29 23:49:29 UTC
9378 23:50:55.832396 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9379 23:50:55.839201 ELOG: Event(A0) added with size 9 at 2024-05-29 23:49:29 UTC
9380 23:50:55.842325 elog_add_boot_reason: Logged dev mode boot
9381 23:50:55.846003 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9382 23:50:55.849466 Finalize devices...
9383 23:50:55.849548 Devices finalized
9384 23:50:55.855620 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9385 23:50:55.858784 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9386 23:50:55.862198 in-header: 03 07 00 00 08 00 00 00
9387 23:50:55.865591 in-data: aa e4 47 04 13 02 00 00
9388 23:50:55.868892 Chrome EC: UHEPI supported
9389 23:50:55.875202 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9390 23:50:55.878691 in-header: 03 a9 00 00 08 00 00 00
9391 23:50:55.881955 in-data: 84 60 60 08 00 00 00 00
9392 23:50:55.885341 ELOG: Event(91) added with size 10 at 2024-05-29 23:49:29 UTC
9393 23:50:55.892122 Chrome EC: clear events_b mask to 0x0000000020004000
9394 23:50:55.898530 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9395 23:50:55.902100 in-header: 03 fd 00 00 00 00 00 00
9396 23:50:55.902182 in-data:
9397 23:50:55.908805 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9398 23:50:55.912063 Writing coreboot table at 0xffe64000
9399 23:50:55.915656 0. 000000000010a000-0000000000113fff: RAMSTAGE
9400 23:50:55.918846 1. 0000000040000000-00000000400fffff: RAM
9401 23:50:55.922473 2. 0000000040100000-000000004032afff: RAMSTAGE
9402 23:50:55.925624 3. 000000004032b000-00000000545fffff: RAM
9403 23:50:55.932284 4. 0000000054600000-000000005465ffff: BL31
9404 23:50:55.935455 5. 0000000054660000-00000000ffe63fff: RAM
9405 23:50:55.938804 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9406 23:50:55.942103 7. 0000000100000000-000000023fffffff: RAM
9407 23:50:55.945717 Passing 5 GPIOs to payload:
9408 23:50:55.952198 NAME | PORT | POLARITY | VALUE
9409 23:50:55.955508 EC in RW | 0x000000aa | low | undefined
9410 23:50:55.958909 EC interrupt | 0x00000005 | low | undefined
9411 23:50:55.965618 TPM interrupt | 0x000000ab | high | undefined
9412 23:50:55.968636 SD card detect | 0x00000011 | high | undefined
9413 23:50:55.975449 speaker enable | 0x00000093 | high | undefined
9414 23:50:55.978853 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9415 23:50:55.981978 in-header: 03 f9 00 00 02 00 00 00
9416 23:50:55.982061 in-data: 02 00
9417 23:50:55.985313 ADC[4]: Raw value=900295 ID=7
9418 23:50:55.988692 ADC[3]: Raw value=212810 ID=1
9419 23:50:55.988774 RAM Code: 0x71
9420 23:50:55.992007 ADC[6]: Raw value=74502 ID=0
9421 23:50:55.995393 ADC[5]: Raw value=212072 ID=1
9422 23:50:55.995476 SKU Code: 0x1
9423 23:50:56.001915 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3c1a
9424 23:50:56.005585 coreboot table: 964 bytes.
9425 23:50:56.008852 IMD ROOT 0. 0xfffff000 0x00001000
9426 23:50:56.012026 IMD SMALL 1. 0xffffe000 0x00001000
9427 23:50:56.015683 RO MCACHE 2. 0xffffc000 0x00001104
9428 23:50:56.018838 CONSOLE 3. 0xfff7c000 0x00080000
9429 23:50:56.022045 FMAP 4. 0xfff7b000 0x00000452
9430 23:50:56.025193 TIME STAMP 5. 0xfff7a000 0x00000910
9431 23:50:56.028761 VBOOT WORK 6. 0xfff66000 0x00014000
9432 23:50:56.031824 RAMOOPS 7. 0xffe66000 0x00100000
9433 23:50:56.035378 COREBOOT 8. 0xffe64000 0x00002000
9434 23:50:56.035460 IMD small region:
9435 23:50:56.038661 IMD ROOT 0. 0xffffec00 0x00000400
9436 23:50:56.041950 VPD 1. 0xffffeb80 0x0000006c
9437 23:50:56.045285 MMC STATUS 2. 0xffffeb60 0x00000004
9438 23:50:56.052008 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9439 23:50:56.058232 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9440 23:50:56.097348 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9441 23:50:56.100805 Checking segment from ROM address 0x40100000
9442 23:50:56.103735 Checking segment from ROM address 0x4010001c
9443 23:50:56.110406 Loading segment from ROM address 0x40100000
9444 23:50:56.110490 code (compression=0)
9445 23:50:56.120655 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9446 23:50:56.127237 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9447 23:50:56.127320 it's not compressed!
9448 23:50:56.133904 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9449 23:50:56.137061 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9450 23:50:56.157466 Loading segment from ROM address 0x4010001c
9451 23:50:56.157550 Entry Point 0x80000000
9452 23:50:56.160932 Loaded segments
9453 23:50:56.164224 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9454 23:50:56.170899 Jumping to boot code at 0x80000000(0xffe64000)
9455 23:50:56.177727 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9456 23:50:56.184343 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9457 23:50:56.192086 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9458 23:50:56.195653 Checking segment from ROM address 0x40100000
9459 23:50:56.198980 Checking segment from ROM address 0x4010001c
9460 23:50:56.205300 Loading segment from ROM address 0x40100000
9461 23:50:56.205383 code (compression=1)
9462 23:50:56.211965 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9463 23:50:56.221800 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9464 23:50:56.221884 using LZMA
9465 23:50:56.230335 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9466 23:50:56.237008 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9467 23:50:56.240524 Loading segment from ROM address 0x4010001c
9468 23:50:56.240642 Entry Point 0x54601000
9469 23:50:56.243731 Loaded segments
9470 23:50:56.246947 NOTICE: MT8192 bl31_setup
9471 23:50:56.254113 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9472 23:50:56.257617 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9473 23:50:56.260624 WARNING: region 0:
9474 23:50:56.264209 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 23:50:56.264292 WARNING: region 1:
9476 23:50:56.270955 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9477 23:50:56.273957 WARNING: region 2:
9478 23:50:56.277368 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9479 23:50:56.280818 WARNING: region 3:
9480 23:50:56.284080 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 23:50:56.287428 WARNING: region 4:
9482 23:50:56.293866 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 23:50:56.293950 WARNING: region 5:
9484 23:50:56.297349 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 23:50:56.300938 WARNING: region 6:
9486 23:50:56.303883 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 23:50:56.307346 WARNING: region 7:
9488 23:50:56.310908 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 23:50:56.317291 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9490 23:50:56.320823 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9491 23:50:56.324030 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9492 23:50:56.330736 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9493 23:50:56.333941 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9494 23:50:56.337556 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9495 23:50:56.344271 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9496 23:50:56.347444 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9497 23:50:56.354162 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9498 23:50:56.357169 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9499 23:50:56.360923 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9500 23:50:56.367372 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9501 23:50:56.370797 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9502 23:50:56.374120 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9503 23:50:56.380573 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9504 23:50:56.384022 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9505 23:50:56.390450 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9506 23:50:56.394044 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9507 23:50:56.397076 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9508 23:50:56.403971 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9509 23:50:56.407340 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9510 23:50:56.410715 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9511 23:50:56.417377 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9512 23:50:56.420515 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9513 23:50:56.427382 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9514 23:50:56.430511 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9515 23:50:56.434033 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9516 23:50:56.440671 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9517 23:50:56.443792 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9518 23:50:56.450866 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9519 23:50:56.454033 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9520 23:50:56.457302 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9521 23:50:56.464148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9522 23:50:56.467337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9523 23:50:56.470527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9524 23:50:56.474302 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9525 23:50:56.480558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9526 23:50:56.483987 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9527 23:50:56.487432 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9528 23:50:56.490716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9529 23:50:56.493754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9530 23:50:56.500498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9531 23:50:56.503938 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9532 23:50:56.507402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9533 23:50:56.514101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9534 23:50:56.517609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9535 23:50:56.520541 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9536 23:50:56.524101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9537 23:50:56.531114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9538 23:50:56.534172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9539 23:50:56.540735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9540 23:50:56.544141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9541 23:50:56.547302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9542 23:50:56.554119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9543 23:50:56.557338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9544 23:50:56.563969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9545 23:50:56.567333 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9546 23:50:56.573885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9547 23:50:56.577432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9548 23:50:56.580678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9549 23:50:56.587526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9550 23:50:56.590789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9551 23:50:56.597102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9552 23:50:56.600837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9553 23:50:56.607421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9554 23:50:56.610776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9555 23:50:56.614004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9556 23:50:56.620486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9557 23:50:56.623836 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9558 23:50:56.630709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9559 23:50:56.633855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9560 23:50:56.640638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9561 23:50:56.643734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9562 23:50:56.650127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9563 23:50:56.653607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9564 23:50:56.656743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9565 23:50:56.663339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9566 23:50:56.666950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9567 23:50:56.673420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9568 23:50:56.676691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9569 23:50:56.683675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9570 23:50:56.686904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9571 23:50:56.693580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9572 23:50:56.696734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9573 23:50:56.700161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9574 23:50:56.706709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9575 23:50:56.709887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9576 23:50:56.716805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9577 23:50:56.720197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9578 23:50:56.726757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9579 23:50:56.729924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9580 23:50:56.733153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9581 23:50:56.739942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9582 23:50:56.743157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9583 23:50:56.749882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9584 23:50:56.753341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9585 23:50:56.759589 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9586 23:50:56.763270 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9587 23:50:56.766376 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9588 23:50:56.769431 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9589 23:50:56.776460 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9590 23:50:56.779823 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9591 23:50:56.782839 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9592 23:50:56.789684 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9593 23:50:56.793180 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9594 23:50:56.799444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9595 23:50:56.802892 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9596 23:50:56.806176 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9597 23:50:56.812655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9598 23:50:56.816088 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9599 23:50:56.822859 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9600 23:50:56.826105 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9601 23:50:56.829554 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9602 23:50:56.836123 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9603 23:50:56.839306 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9604 23:50:56.845966 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9605 23:50:56.849456 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9606 23:50:56.852635 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9607 23:50:56.856164 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9608 23:50:56.862840 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9609 23:50:56.865949 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9610 23:50:56.869671 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9611 23:50:56.872851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9612 23:50:56.879521 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9613 23:50:56.882626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9614 23:50:56.886027 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9615 23:50:56.892948 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9616 23:50:56.896022 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9617 23:50:56.902945 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9618 23:50:56.906105 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9619 23:50:56.909601 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9620 23:50:56.915931 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9621 23:50:56.919414 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9622 23:50:56.925933 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9623 23:50:56.929615 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9624 23:50:56.932988 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9625 23:50:56.939359 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9626 23:50:56.942724 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9627 23:50:56.946346 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9628 23:50:56.952870 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9629 23:50:56.956080 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9630 23:50:56.962664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9631 23:50:56.966211 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9632 23:50:56.969380 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9633 23:50:56.976300 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9634 23:50:56.979284 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9635 23:50:56.986007 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9636 23:50:56.989429 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9637 23:50:56.992785 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9638 23:50:56.999580 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9639 23:50:57.002852 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9640 23:50:57.005898 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9641 23:50:57.012433 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9642 23:50:57.016153 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9643 23:50:57.022759 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9644 23:50:57.026033 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9645 23:50:57.029132 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9646 23:50:57.036058 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9647 23:50:57.039451 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9648 23:50:57.046016 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9649 23:50:57.049399 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9650 23:50:57.052455 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9651 23:50:57.059244 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9652 23:50:57.062455 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9653 23:50:57.069209 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9654 23:50:57.072696 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9655 23:50:57.075904 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9656 23:50:57.082508 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9657 23:50:57.085677 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9658 23:50:57.089269 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9659 23:50:57.095920 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9660 23:50:57.099161 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9661 23:50:57.105902 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9662 23:50:57.109326 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9663 23:50:57.112449 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9664 23:50:57.119113 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9665 23:50:57.122510 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9666 23:50:57.128996 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9667 23:50:57.132402 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9668 23:50:57.135994 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9669 23:50:57.142458 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9670 23:50:57.145485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9671 23:50:57.152092 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9672 23:50:57.155712 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9673 23:50:57.158833 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9674 23:50:57.165701 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9675 23:50:57.168907 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9676 23:50:57.172457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9677 23:50:57.178663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9678 23:50:57.182236 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9679 23:50:57.189066 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9680 23:50:57.192261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9681 23:50:57.198907 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9682 23:50:57.202373 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9683 23:50:57.205738 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9684 23:50:57.212309 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9685 23:50:57.215718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9686 23:50:57.222468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9687 23:50:57.225599 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9688 23:50:57.228833 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9689 23:50:57.235605 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9690 23:50:57.238883 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9691 23:50:57.245435 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9692 23:50:57.248823 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9693 23:50:57.255673 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9694 23:50:57.258858 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9695 23:50:57.261954 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9696 23:50:57.268736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9697 23:50:57.272269 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9698 23:50:57.278858 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9699 23:50:57.281984 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9700 23:50:57.285523 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9701 23:50:57.292272 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9702 23:50:57.295482 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9703 23:50:57.301946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9704 23:50:57.305072 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9705 23:50:57.308710 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9706 23:50:57.315176 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9707 23:50:57.318675 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9708 23:50:57.325125 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9709 23:50:57.328424 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9710 23:50:57.335154 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9711 23:50:57.338307 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9712 23:50:57.342065 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9713 23:50:57.348482 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9714 23:50:57.351806 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9715 23:50:57.358550 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9716 23:50:57.361732 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9717 23:50:57.365388 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9718 23:50:57.372090 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9719 23:50:57.375321 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9720 23:50:57.378435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9721 23:50:57.381849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9722 23:50:57.385436 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9723 23:50:57.391665 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9724 23:50:57.395129 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9725 23:50:57.401860 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9726 23:50:57.405048 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9727 23:50:57.408567 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9728 23:50:57.414882 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9729 23:50:57.418323 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9730 23:50:57.424965 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9731 23:50:57.428790 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9732 23:50:57.431822 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9733 23:50:57.435145 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9734 23:50:57.441535 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9735 23:50:57.444989 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9736 23:50:57.451448 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9737 23:50:57.454986 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9738 23:50:57.458108 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9739 23:50:57.464920 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9740 23:50:57.468136 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9741 23:50:57.474882 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9742 23:50:57.478432 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9743 23:50:57.481531 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9744 23:50:57.488048 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9745 23:50:57.491676 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9746 23:50:57.494872 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9747 23:50:57.501762 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9748 23:50:57.504974 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9749 23:50:57.508271 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9750 23:50:57.514782 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9751 23:50:57.518405 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9752 23:50:57.521807 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9753 23:50:57.528046 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9754 23:50:57.531666 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9755 23:50:57.538202 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9756 23:50:57.541276 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9757 23:50:57.544819 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9758 23:50:57.548160 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9759 23:50:57.554645 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9760 23:50:57.557849 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9761 23:50:57.561106 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9762 23:50:57.564501 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9763 23:50:57.571248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9764 23:50:57.574727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9765 23:50:57.577846 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9766 23:50:57.581430 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9767 23:50:57.587689 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9768 23:50:57.591188 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9769 23:50:57.594317 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9770 23:50:57.597597 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9771 23:50:57.604345 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9772 23:50:57.607767 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9773 23:50:57.614397 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9774 23:50:57.617629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9775 23:50:57.624249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9776 23:50:57.627616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9777 23:50:57.630993 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9778 23:50:57.637682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9779 23:50:57.640782 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9780 23:50:57.647430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9781 23:50:57.651040 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9782 23:50:57.654252 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9783 23:50:57.660997 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9784 23:50:57.664194 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9785 23:50:57.671070 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9786 23:50:57.674244 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9787 23:50:57.677481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9788 23:50:57.684263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9789 23:50:57.687363 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9790 23:50:57.693970 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9791 23:50:57.697542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9792 23:50:57.700648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9793 23:50:57.707281 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9794 23:50:57.710860 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9795 23:50:57.717557 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9796 23:50:57.720692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9797 23:50:57.724236 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9798 23:50:57.730776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9799 23:50:57.734400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9800 23:50:57.741076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9801 23:50:57.744358 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9802 23:50:57.747524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9803 23:50:57.754325 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9804 23:50:57.757603 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9805 23:50:57.764092 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9806 23:50:57.767295 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9807 23:50:57.773937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9808 23:50:57.777551 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9809 23:50:57.780715 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9810 23:50:57.787625 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9811 23:50:57.790606 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9812 23:50:57.794208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9813 23:50:57.800878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9814 23:50:57.803951 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9815 23:50:57.810806 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9816 23:50:57.813910 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9817 23:50:57.820802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9818 23:50:57.823806 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9819 23:50:57.827370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9820 23:50:57.834004 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9821 23:50:57.837674 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9822 23:50:57.843936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9823 23:50:57.847429 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9824 23:50:57.850745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9825 23:50:57.857318 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9826 23:50:57.860839 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9827 23:50:57.867293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9828 23:50:57.870993 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9829 23:50:57.873904 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9830 23:50:57.880808 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9831 23:50:57.884032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9832 23:50:57.890661 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9833 23:50:57.893793 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9834 23:50:57.897319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9835 23:50:57.904024 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9836 23:50:57.907106 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9837 23:50:57.913879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9838 23:50:57.917407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9839 23:50:57.920515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9840 23:50:57.927240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9841 23:50:57.930432 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9842 23:50:57.937589 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9843 23:50:57.940427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9844 23:50:57.943825 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9845 23:50:57.950499 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9846 23:50:57.953918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9847 23:50:57.960459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9848 23:50:57.963624 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9849 23:50:57.970671 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9850 23:50:57.973872 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9851 23:50:57.977377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9852 23:50:57.983711 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9853 23:50:57.986968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9854 23:50:57.993843 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9855 23:50:57.997160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9856 23:50:58.003755 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9857 23:50:58.006931 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9858 23:50:58.010559 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9859 23:50:58.016896 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9860 23:50:58.020399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9861 23:50:58.027111 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9862 23:50:58.030249 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9863 23:50:58.037110 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9864 23:50:58.040352 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9865 23:50:58.047123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9866 23:50:58.050322 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9867 23:50:58.053511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9868 23:50:58.060412 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9869 23:50:58.063751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9870 23:50:58.070281 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9871 23:50:58.073788 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9872 23:50:58.080188 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9873 23:50:58.083365 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9874 23:50:58.086703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9875 23:50:58.093570 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9876 23:50:58.096703 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9877 23:50:58.103433 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9878 23:50:58.106756 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9879 23:50:58.113444 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9880 23:50:58.116997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9881 23:50:58.123697 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9882 23:50:58.126920 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9883 23:50:58.130097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9884 23:50:58.136715 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9885 23:50:58.140169 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9886 23:50:58.146471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9887 23:50:58.149788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9888 23:50:58.156495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9889 23:50:58.159972 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9890 23:50:58.163264 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9891 23:50:58.170158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9892 23:50:58.173231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9893 23:50:58.179915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9894 23:50:58.183214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9895 23:50:58.186588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9896 23:50:58.193410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9897 23:50:58.196494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9898 23:50:58.203432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9899 23:50:58.206695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9900 23:50:58.213149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9901 23:50:58.216765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9902 23:50:58.223490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9903 23:50:58.226716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9904 23:50:58.233224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9905 23:50:58.236709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9906 23:50:58.243424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9907 23:50:58.246677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9908 23:50:58.253485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9909 23:50:58.256751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9910 23:50:58.263298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9911 23:50:58.266808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9912 23:50:58.273368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9913 23:50:58.276455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9914 23:50:58.283363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9915 23:50:58.286497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9916 23:50:58.293180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9917 23:50:58.296481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9918 23:50:58.303339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9919 23:50:58.306707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9920 23:50:58.312953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9921 23:50:58.316752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9922 23:50:58.323028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9923 23:50:58.326654 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9924 23:50:58.326752 INFO: [APUAPC] vio 0
9925 23:50:58.333986 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9926 23:50:58.337295 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9927 23:50:58.340579 INFO: [APUAPC] D0_APC_0: 0x400510
9928 23:50:58.343913 INFO: [APUAPC] D0_APC_1: 0x0
9929 23:50:58.347019 INFO: [APUAPC] D0_APC_2: 0x1540
9930 23:50:58.350492 INFO: [APUAPC] D0_APC_3: 0x0
9931 23:50:58.353693 INFO: [APUAPC] D1_APC_0: 0xffffffff
9932 23:50:58.357036 INFO: [APUAPC] D1_APC_1: 0xffffffff
9933 23:50:58.360485 INFO: [APUAPC] D1_APC_2: 0x3fffff
9934 23:50:58.364097 INFO: [APUAPC] D1_APC_3: 0x0
9935 23:50:58.367092 INFO: [APUAPC] D2_APC_0: 0xffffffff
9936 23:50:58.370340 INFO: [APUAPC] D2_APC_1: 0xffffffff
9937 23:50:58.373622 INFO: [APUAPC] D2_APC_2: 0x3fffff
9938 23:50:58.377184 INFO: [APUAPC] D2_APC_3: 0x0
9939 23:50:58.380187 INFO: [APUAPC] D3_APC_0: 0xffffffff
9940 23:50:58.383557 INFO: [APUAPC] D3_APC_1: 0xffffffff
9941 23:50:58.387127 INFO: [APUAPC] D3_APC_2: 0x3fffff
9942 23:50:58.390705 INFO: [APUAPC] D3_APC_3: 0x0
9943 23:50:58.393790 INFO: [APUAPC] D4_APC_0: 0xffffffff
9944 23:50:58.396883 INFO: [APUAPC] D4_APC_1: 0xffffffff
9945 23:50:58.400198 INFO: [APUAPC] D4_APC_2: 0x3fffff
9946 23:50:58.400294 INFO: [APUAPC] D4_APC_3: 0x0
9947 23:50:58.403873 INFO: [APUAPC] D5_APC_0: 0xffffffff
9948 23:50:58.410179 INFO: [APUAPC] D5_APC_1: 0xffffffff
9949 23:50:58.410282 INFO: [APUAPC] D5_APC_2: 0x3fffff
9950 23:50:58.413512 INFO: [APUAPC] D5_APC_3: 0x0
9951 23:50:58.416903 INFO: [APUAPC] D6_APC_0: 0xffffffff
9952 23:50:58.420185 INFO: [APUAPC] D6_APC_1: 0xffffffff
9953 23:50:58.423383 INFO: [APUAPC] D6_APC_2: 0x3fffff
9954 23:50:58.426967 INFO: [APUAPC] D6_APC_3: 0x0
9955 23:50:58.430601 INFO: [APUAPC] D7_APC_0: 0xffffffff
9956 23:50:58.433717 INFO: [APUAPC] D7_APC_1: 0xffffffff
9957 23:50:58.437244 INFO: [APUAPC] D7_APC_2: 0x3fffff
9958 23:50:58.440426 INFO: [APUAPC] D7_APC_3: 0x0
9959 23:50:58.443750 INFO: [APUAPC] D8_APC_0: 0xffffffff
9960 23:50:58.446902 INFO: [APUAPC] D8_APC_1: 0xffffffff
9961 23:50:58.450037 INFO: [APUAPC] D8_APC_2: 0x3fffff
9962 23:50:58.453794 INFO: [APUAPC] D8_APC_3: 0x0
9963 23:50:58.456806 INFO: [APUAPC] D9_APC_0: 0xffffffff
9964 23:50:58.460048 INFO: [APUAPC] D9_APC_1: 0xffffffff
9965 23:50:58.463347 INFO: [APUAPC] D9_APC_2: 0x3fffff
9966 23:50:58.467073 INFO: [APUAPC] D9_APC_3: 0x0
9967 23:50:58.470453 INFO: [APUAPC] D10_APC_0: 0xffffffff
9968 23:50:58.473406 INFO: [APUAPC] D10_APC_1: 0xffffffff
9969 23:50:58.476688 INFO: [APUAPC] D10_APC_2: 0x3fffff
9970 23:50:58.480248 INFO: [APUAPC] D10_APC_3: 0x0
9971 23:50:58.483365 INFO: [APUAPC] D11_APC_0: 0xffffffff
9972 23:50:58.486757 INFO: [APUAPC] D11_APC_1: 0xffffffff
9973 23:50:58.489843 INFO: [APUAPC] D11_APC_2: 0x3fffff
9974 23:50:58.493453 INFO: [APUAPC] D11_APC_3: 0x0
9975 23:50:58.496639 INFO: [APUAPC] D12_APC_0: 0xffffffff
9976 23:50:58.500049 INFO: [APUAPC] D12_APC_1: 0xffffffff
9977 23:50:58.503135 INFO: [APUAPC] D12_APC_2: 0x3fffff
9978 23:50:58.506670 INFO: [APUAPC] D12_APC_3: 0x0
9979 23:50:58.509900 INFO: [APUAPC] D13_APC_0: 0xffffffff
9980 23:50:58.513077 INFO: [APUAPC] D13_APC_1: 0xffffffff
9981 23:50:58.516297 INFO: [APUAPC] D13_APC_2: 0x3fffff
9982 23:50:58.520019 INFO: [APUAPC] D13_APC_3: 0x0
9983 23:50:58.523183 INFO: [APUAPC] D14_APC_0: 0xffffffff
9984 23:50:58.526433 INFO: [APUAPC] D14_APC_1: 0xffffffff
9985 23:50:58.529689 INFO: [APUAPC] D14_APC_2: 0x3fffff
9986 23:50:58.533040 INFO: [APUAPC] D14_APC_3: 0x0
9987 23:50:58.536578 INFO: [APUAPC] D15_APC_0: 0xffffffff
9988 23:50:58.540060 INFO: [APUAPC] D15_APC_1: 0xffffffff
9989 23:50:58.543188 INFO: [APUAPC] D15_APC_2: 0x3fffff
9990 23:50:58.546467 INFO: [APUAPC] D15_APC_3: 0x0
9991 23:50:58.549880 INFO: [APUAPC] APC_CON: 0x4
9992 23:50:58.553349 INFO: [NOCDAPC] D0_APC_0: 0x0
9993 23:50:58.556430 INFO: [NOCDAPC] D0_APC_1: 0x0
9994 23:50:58.560054 INFO: [NOCDAPC] D1_APC_0: 0x0
9995 23:50:58.563147 INFO: [NOCDAPC] D1_APC_1: 0xfff
9996 23:50:58.563250 INFO: [NOCDAPC] D2_APC_0: 0x0
9997 23:50:58.566439 INFO: [NOCDAPC] D2_APC_1: 0xfff
9998 23:50:58.569720 INFO: [NOCDAPC] D3_APC_0: 0x0
9999 23:50:58.572924 INFO: [NOCDAPC] D3_APC_1: 0xfff
10000 23:50:58.576419 INFO: [NOCDAPC] D4_APC_0: 0x0
10001 23:50:58.579739 INFO: [NOCDAPC] D4_APC_1: 0xfff
10002 23:50:58.583268 INFO: [NOCDAPC] D5_APC_0: 0x0
10003 23:50:58.586334 INFO: [NOCDAPC] D5_APC_1: 0xfff
10004 23:50:58.589811 INFO: [NOCDAPC] D6_APC_0: 0x0
10005 23:50:58.593281 INFO: [NOCDAPC] D6_APC_1: 0xfff
10006 23:50:58.593352 INFO: [NOCDAPC] D7_APC_0: 0x0
10007 23:50:58.596245 INFO: [NOCDAPC] D7_APC_1: 0xfff
10008 23:50:58.600045 INFO: [NOCDAPC] D8_APC_0: 0x0
10009 23:50:58.602916 INFO: [NOCDAPC] D8_APC_1: 0xfff
10010 23:50:58.606568 INFO: [NOCDAPC] D9_APC_0: 0x0
10011 23:50:58.609575 INFO: [NOCDAPC] D9_APC_1: 0xfff
10012 23:50:58.613392 INFO: [NOCDAPC] D10_APC_0: 0x0
10013 23:50:58.616398 INFO: [NOCDAPC] D10_APC_1: 0xfff
10014 23:50:58.619719 INFO: [NOCDAPC] D11_APC_0: 0x0
10015 23:50:58.623021 INFO: [NOCDAPC] D11_APC_1: 0xfff
10016 23:50:58.626279 INFO: [NOCDAPC] D12_APC_0: 0x0
10017 23:50:58.629557 INFO: [NOCDAPC] D12_APC_1: 0xfff
10018 23:50:58.632886 INFO: [NOCDAPC] D13_APC_0: 0x0
10019 23:50:58.636418 INFO: [NOCDAPC] D13_APC_1: 0xfff
10020 23:50:58.636503 INFO: [NOCDAPC] D14_APC_0: 0x0
10021 23:50:58.639830 INFO: [NOCDAPC] D14_APC_1: 0xfff
10022 23:50:58.643241 INFO: [NOCDAPC] D15_APC_0: 0x0
10023 23:50:58.646241 INFO: [NOCDAPC] D15_APC_1: 0xfff
10024 23:50:58.649775 INFO: [NOCDAPC] APC_CON: 0x4
10025 23:50:58.653048 INFO: [APUAPC] set_apusys_apc done
10026 23:50:58.656242 INFO: [DEVAPC] devapc_init done
10027 23:50:58.659761 INFO: GICv3 without legacy support detected.
10028 23:50:58.662767 INFO: ARM GICv3 driver initialized in EL3
10029 23:50:58.669921 INFO: Maximum SPI INTID supported: 639
10030 23:50:58.673304 INFO: BL31: Initializing runtime services
10031 23:50:58.680021 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10032 23:50:58.680124 INFO: SPM: enable CPC mode
10033 23:50:58.686576 INFO: mcdi ready for mcusys-off-idle and system suspend
10034 23:50:58.689745 INFO: BL31: Preparing for EL3 exit to normal world
10035 23:50:58.693207 INFO: Entry point address = 0x80000000
10036 23:50:58.696514 INFO: SPSR = 0x8
10037 23:50:58.702042
10038 23:50:58.702118
10039 23:50:58.702203
10040 23:50:58.705195 Starting depthcharge on Spherion...
10041 23:50:58.705265
10042 23:50:58.705325 Wipe memory regions:
10043 23:50:58.705401
10044 23:50:58.705987 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10045 23:50:58.706086 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10046 23:50:58.706189 Setting prompt string to ['asurada:']
10047 23:50:58.706268 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10048 23:50:58.708837 [0x00000040000000, 0x00000054600000)
10049 23:50:58.830879
10050 23:50:58.831016 [0x00000054660000, 0x00000080000000)
10051 23:50:59.091369
10052 23:50:59.091495 [0x000000821a7280, 0x000000ffe64000)
10053 23:50:59.836554
10054 23:50:59.836714 [0x00000100000000, 0x00000240000000)
10055 23:51:01.726419
10056 23:51:01.729830 Initializing XHCI USB controller at 0x11200000.
10057 23:51:02.768303
10058 23:51:02.771796 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10059 23:51:02.772537
10060 23:51:02.773173
10061 23:51:02.774263 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 23:51:02.875937 asurada: tftpboot 192.168.201.1 14084338/tftp-deploy-kfz9ggpj/kernel/image.itb 14084338/tftp-deploy-kfz9ggpj/kernel/cmdline
10064 23:51:02.876631 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 23:51:02.877212 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10066 23:51:02.881985 tftpboot 192.168.201.1 14084338/tftp-deploy-kfz9ggpj/kernel/image.itp-deploy-kfz9ggpj/kernel/cmdline
10067 23:51:02.882513
10068 23:51:02.883124 Waiting for link
10069 23:51:03.039611
10070 23:51:03.040377 R8152: Initializing
10071 23:51:03.041029
10072 23:51:03.043033 Version 9 (ocp_data = 6010)
10073 23:51:03.043650
10074 23:51:03.046384 R8152: Done initializing
10075 23:51:03.046956
10076 23:51:03.047399 Adding net device
10077 23:51:04.989400
10078 23:51:04.989948 done.
10079 23:51:04.990332
10080 23:51:04.990683 MAC: 00:e0:4c:72:2d:d6
10081 23:51:04.991026
10082 23:51:04.992809 Sending DHCP discover... done.
10083 23:51:04.993282
10084 23:51:14.707396 Waiting for reply... R8152: Bulk read error 0xffffffbf
10085 23:51:14.708243
10086 23:51:14.710263 Receive failed.
10087 23:51:14.710783
10088 23:51:14.711489 done.
10089 23:51:14.711878
10090 23:51:14.713998 Sending DHCP request... done.
10091 23:51:14.714463
10092 23:51:14.720633 Waiting for reply... done.
10093 23:51:14.721100
10094 23:51:14.721472 My ip is 192.168.201.21
10095 23:51:14.721821
10096 23:51:14.723926 The DHCP server ip is 192.168.201.1
10097 23:51:14.724495
10098 23:51:14.730693 TFTP server IP predefined by user: 192.168.201.1
10099 23:51:14.731265
10100 23:51:14.737278 Bootfile predefined by user: 14084338/tftp-deploy-kfz9ggpj/kernel/image.itb
10101 23:51:14.737844
10102 23:51:14.738223 Sending tftp read request... done.
10103 23:51:14.740249
10104 23:51:14.744733 Waiting for the transfer...
10105 23:51:14.745351
10106 23:51:15.034276 00000000 ################################################################
10107 23:51:15.034405
10108 23:51:15.283281 00080000 ################################################################
10109 23:51:15.283419
10110 23:51:15.532318 00100000 ################################################################
10111 23:51:15.532447
10112 23:51:15.780926 00180000 ################################################################
10113 23:51:15.781059
10114 23:51:16.029797 00200000 ################################################################
10115 23:51:16.029923
10116 23:51:16.278213 00280000 ################################################################
10117 23:51:16.278349
10118 23:51:16.527535 00300000 ################################################################
10119 23:51:16.527660
10120 23:51:16.776490 00380000 ################################################################
10121 23:51:16.776690
10122 23:51:17.035568 00400000 ################################################################
10123 23:51:17.035723
10124 23:51:17.285998 00480000 ################################################################
10125 23:51:17.286124
10126 23:51:17.535682 00500000 ################################################################
10127 23:51:17.535806
10128 23:51:17.783354 00580000 ################################################################
10129 23:51:17.783485
10130 23:51:18.032823 00600000 ################################################################
10131 23:51:18.032951
10132 23:51:18.294751 00680000 ################################################################
10133 23:51:18.294885
10134 23:51:18.561002 00700000 ################################################################
10135 23:51:18.561132
10136 23:51:18.828291 00780000 ################################################################
10137 23:51:18.828459
10138 23:51:19.080665 00800000 ################################################################
10139 23:51:19.080793
10140 23:51:19.354320 00880000 ################################################################
10141 23:51:19.354450
10142 23:51:19.635510 00900000 ################################################################
10143 23:51:19.635656
10144 23:51:19.904306 00980000 ################################################################
10145 23:51:19.904477
10146 23:51:20.153764 00a00000 ################################################################
10147 23:51:20.153891
10148 23:51:20.424126 00a80000 ################################################################
10149 23:51:20.424257
10150 23:51:20.692200 00b00000 ################################################################
10151 23:51:20.692330
10152 23:51:20.995170 00b80000 ################################################################
10153 23:51:20.995665
10154 23:51:21.384189 00c00000 ################################################################
10155 23:51:21.384357
10156 23:51:21.680463 00c80000 ################################################################
10157 23:51:21.680616
10158 23:51:21.968821 00d00000 ################################################################
10159 23:51:21.968958
10160 23:51:22.256381 00d80000 ################################################################
10161 23:51:22.256532
10162 23:51:22.542455 00e00000 ################################################################
10163 23:51:22.542611
10164 23:51:22.843600 00e80000 ################################################################
10165 23:51:22.843760
10166 23:51:23.144325 00f00000 ################################################################
10167 23:51:23.144476
10168 23:51:23.430844 00f80000 ################################################################
10169 23:51:23.430999
10170 23:51:23.696809 01000000 ################################################################
10171 23:51:23.696940
10172 23:51:24.043188 01080000 ################################################################
10173 23:51:24.043327
10174 23:51:24.328970 01100000 ################################################################
10175 23:51:24.329106
10176 23:51:24.610356 01180000 ################################################################
10177 23:51:24.610487
10178 23:51:24.910323 01200000 ################################################################
10179 23:51:24.910456
10180 23:51:25.210085 01280000 ################################################################
10181 23:51:25.210225
10182 23:51:25.504250 01300000 ################################################################
10183 23:51:25.504383
10184 23:51:25.797994 01380000 ################################################################
10185 23:51:25.798152
10186 23:51:26.062167 01400000 ################################################################
10187 23:51:26.062331
10188 23:51:26.315116 01480000 ################################################################
10189 23:51:26.315272
10190 23:51:26.564609 01500000 ################################################################
10191 23:51:26.564766
10192 23:51:26.840693 01580000 ################################################################
10193 23:51:26.840832
10194 23:51:27.141942 01600000 ################################################################
10195 23:51:27.142109
10196 23:51:27.439234 01680000 ################################################################
10197 23:51:27.439400
10198 23:51:27.720425 01700000 ################################################################
10199 23:51:27.720649
10200 23:51:28.003918 01780000 ################################################################
10201 23:51:28.004063
10202 23:51:28.296831 01800000 ################################################################
10203 23:51:28.296959
10204 23:51:28.593494 01880000 ################################################################
10205 23:51:28.593691
10206 23:51:28.892511 01900000 ################################################################
10207 23:51:28.892676
10208 23:51:29.161027 01980000 ################################################################
10209 23:51:29.161252
10210 23:51:29.423702 01a00000 ################################################################
10211 23:51:29.423839
10212 23:51:29.672463 01a80000 ################################################################
10213 23:51:29.672638
10214 23:51:29.921216 01b00000 ################################################################
10215 23:51:29.921337
10216 23:51:30.194517 01b80000 ################################################################
10217 23:51:30.194645
10218 23:51:30.443851 01c00000 ################################################################
10219 23:51:30.443985
10220 23:51:30.691826 01c80000 ################################################################
10221 23:51:30.691967
10222 23:51:30.940993 01d00000 ################################################################
10223 23:51:30.941149
10224 23:51:31.190162 01d80000 ################################################################
10225 23:51:31.190313
10226 23:51:31.439246 01e00000 ################################################################
10227 23:51:31.439408
10228 23:51:31.688326 01e80000 ################################################################
10229 23:51:31.688448
10230 23:51:32.001302 01f00000 ################################################################
10231 23:51:32.001809
10232 23:51:32.377092 01f80000 ################################################################
10233 23:51:32.377639
10234 23:51:32.745815 02000000 ################################################################
10235 23:51:32.746396
10236 23:51:32.991388 02080000 ################################################# done.
10237 23:51:32.991534
10238 23:51:32.994518 The bootfile was 34476422 bytes long.
10239 23:51:32.994608
10240 23:51:32.998117 Sending tftp read request... done.
10241 23:51:32.998212
10242 23:51:33.001259 Waiting for the transfer...
10243 23:51:33.001353
10244 23:51:33.004786 00000000 # done.
10245 23:51:33.004970
10246 23:51:33.011164 Command line loaded dynamically from TFTP file: 14084338/tftp-deploy-kfz9ggpj/kernel/cmdline
10247 23:51:33.011353
10248 23:51:33.024354 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10249 23:51:33.024610
10250 23:51:33.024755 Loading FIT.
10251 23:51:33.027839
10252 23:51:33.028015 Image ramdisk-1 has 21363643 bytes.
10253 23:51:33.028154
10254 23:51:33.031204 Image fdt-1 has 47258 bytes.
10255 23:51:33.031466
10256 23:51:33.034312 Image kernel-1 has 13063488 bytes.
10257 23:51:33.034608
10258 23:51:33.044606 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10259 23:51:33.045003
10260 23:51:33.061283 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10261 23:51:33.061797
10262 23:51:33.067578 Choosing best match conf-1 for compat google,spherion-rev2.
10263 23:51:33.070994
10264 23:51:33.075747 Connected to device vid:did:rid of 1ae0:0028:00
10265 23:51:33.084344
10266 23:51:33.087495 tpm_get_response: command 0x17b, return code 0x0
10267 23:51:33.087993
10268 23:51:33.090536 ec_init: CrosEC protocol v3 supported (256, 248)
10269 23:51:33.094889
10270 23:51:33.098175 tpm_cleanup: add release locality here.
10271 23:51:33.098691
10272 23:51:33.099006 Shutting down all USB controllers.
10273 23:51:33.101139
10274 23:51:33.101522 Removing current net device
10275 23:51:33.101833
10276 23:51:33.108161 Exiting depthcharge with code 4 at timestamp: 63740805
10277 23:51:33.108690
10278 23:51:33.110991 LZMA decompressing kernel-1 to 0x821a6718
10279 23:51:33.111381
10280 23:51:33.114788 LZMA decompressing kernel-1 to 0x40000000
10281 23:51:34.725560
10282 23:51:34.726127 jumping to kernel
10283 23:51:34.728462 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10284 23:51:34.729038 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
10285 23:51:34.729466 Setting prompt string to ['Linux version [0-9]']
10286 23:51:34.729846 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10287 23:51:34.730229 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10288 23:51:34.808822
10289 23:51:34.812106 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10290 23:51:34.815801 start: 2.2.5.1 login-action (timeout 00:03:51) [common]
10291 23:51:34.816385 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10292 23:51:34.816826 Setting prompt string to []
10293 23:51:34.817251 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10294 23:51:34.817651 Using line separator: #'\n'#
10295 23:51:34.817989 No login prompt set.
10296 23:51:34.818322 Parsing kernel messages
10297 23:51:34.818637 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10298 23:51:34.819206 [login-action] Waiting for messages, (timeout 00:03:51)
10299 23:51:34.819578 Waiting using forced prompt support (timeout 00:01:55)
10300 23:51:34.834976 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10301 23:51:34.837926 [ 0.000000] random: crng init done
10302 23:51:34.845097 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10303 23:51:34.848129 [ 0.000000] efi: UEFI not found.
10304 23:51:34.854561 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10305 23:51:34.864650 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10306 23:51:34.871220 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10307 23:51:34.881197 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10308 23:51:34.887950 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10309 23:51:34.894436 [ 0.000000] printk: bootconsole [mtk8250] enabled
10310 23:51:34.901403 [ 0.000000] NUMA: No NUMA configuration found
10311 23:51:34.907841 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10312 23:51:34.914179 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10313 23:51:34.914732 [ 0.000000] Zone ranges:
10314 23:51:34.921180 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10315 23:51:34.924291 [ 0.000000] DMA32 empty
10316 23:51:34.930952 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10317 23:51:34.933931 [ 0.000000] Movable zone start for each node
10318 23:51:34.937182 [ 0.000000] Early memory node ranges
10319 23:51:34.943862 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10320 23:51:34.950651 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10321 23:51:34.957185 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10322 23:51:34.963529 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10323 23:51:34.970217 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10324 23:51:34.976637 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10325 23:51:35.033473 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10326 23:51:35.039815 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10327 23:51:35.046538 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10328 23:51:35.050067 [ 0.000000] psci: probing for conduit method from DT.
10329 23:51:35.056722 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10330 23:51:35.059844 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10331 23:51:35.066535 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10332 23:51:35.069980 [ 0.000000] psci: SMC Calling Convention v1.2
10333 23:51:35.076346 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10334 23:51:35.079597 [ 0.000000] Detected VIPT I-cache on CPU0
10335 23:51:35.086194 [ 0.000000] CPU features: detected: GIC system register CPU interface
10336 23:51:35.092939 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10337 23:51:35.099543 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10338 23:51:35.105835 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10339 23:51:35.115811 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10340 23:51:35.122905 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10341 23:51:35.126023 [ 0.000000] alternatives: applying boot alternatives
10342 23:51:35.132638 [ 0.000000] Fallback order for Node 0: 0
10343 23:51:35.139100 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10344 23:51:35.142770 [ 0.000000] Policy zone: Normal
10345 23:51:35.155915 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10346 23:51:35.165495 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10347 23:51:35.178096 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10348 23:51:35.187965 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10349 23:51:35.194187 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10350 23:51:35.197418 <6>[ 0.000000] software IO TLB: area num 8.
10351 23:51:35.254629 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10352 23:51:35.404167 <6>[ 0.000000] Memory: 7943328K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 409440K reserved, 32768K cma-reserved)
10353 23:51:35.410858 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10354 23:51:35.416993 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10355 23:51:35.420509 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10356 23:51:35.427152 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10357 23:51:35.433531 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10358 23:51:35.437015 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10359 23:51:35.447021 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10360 23:51:35.453294 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10361 23:51:35.460293 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10362 23:51:35.466477 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10363 23:51:35.469887 <6>[ 0.000000] GICv3: 608 SPIs implemented
10364 23:51:35.473111 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10365 23:51:35.479863 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10366 23:51:35.483110 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10367 23:51:35.489670 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10368 23:51:35.503240 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10369 23:51:35.515890 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10370 23:51:35.522769 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10371 23:51:35.530334 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10372 23:51:35.543768 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10373 23:51:35.550427 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10374 23:51:35.557352 <6>[ 0.009233] Console: colour dummy device 80x25
10375 23:51:35.567270 <6>[ 0.013989] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10376 23:51:35.573826 <6>[ 0.024431] pid_max: default: 32768 minimum: 301
10377 23:51:35.576770 <6>[ 0.029332] LSM: Security Framework initializing
10378 23:51:35.583656 <6>[ 0.034269] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10379 23:51:35.593624 <6>[ 0.042130] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 23:51:35.603470 <6>[ 0.051552] cblist_init_generic: Setting adjustable number of callback queues.
10381 23:51:35.606726 <6>[ 0.059042] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 23:51:35.616681 <6>[ 0.065380] cblist_init_generic: Setting adjustable number of callback queues.
10383 23:51:35.623366 <6>[ 0.072807] cblist_init_generic: Setting shift to 3 and lim to 1.
10384 23:51:35.626898 <6>[ 0.079208] rcu: Hierarchical SRCU implementation.
10385 23:51:35.633000 <6>[ 0.084223] rcu: Max phase no-delay instances is 1000.
10386 23:51:35.639639 <6>[ 0.091247] EFI services will not be available.
10387 23:51:35.642692 <6>[ 0.096205] smp: Bringing up secondary CPUs ...
10388 23:51:35.651619 <6>[ 0.101254] Detected VIPT I-cache on CPU1
10389 23:51:35.658248 <6>[ 0.101327] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10390 23:51:35.664657 <6>[ 0.101358] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10391 23:51:35.667883 <6>[ 0.101700] Detected VIPT I-cache on CPU2
10392 23:51:35.677785 <6>[ 0.101752] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10393 23:51:35.684215 <6>[ 0.101770] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10394 23:51:35.687780 <6>[ 0.102029] Detected VIPT I-cache on CPU3
10395 23:51:35.694440 <6>[ 0.102075] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10396 23:51:35.701170 <6>[ 0.102089] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10397 23:51:35.707243 <6>[ 0.102393] CPU features: detected: Spectre-v4
10398 23:51:35.710900 <6>[ 0.102400] CPU features: detected: Spectre-BHB
10399 23:51:35.713835 <6>[ 0.102404] Detected PIPT I-cache on CPU4
10400 23:51:35.720787 <6>[ 0.102462] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10401 23:51:35.730438 <6>[ 0.102479] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10402 23:51:35.733854 <6>[ 0.102771] Detected PIPT I-cache on CPU5
10403 23:51:35.740404 <6>[ 0.102832] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10404 23:51:35.746770 <6>[ 0.102847] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10405 23:51:35.750201 <6>[ 0.103127] Detected PIPT I-cache on CPU6
10406 23:51:35.757141 <6>[ 0.103193] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10407 23:51:35.766971 <6>[ 0.103209] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10408 23:51:35.770053 <6>[ 0.103505] Detected PIPT I-cache on CPU7
10409 23:51:35.776772 <6>[ 0.103569] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10410 23:51:35.783393 <6>[ 0.103584] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10411 23:51:35.786917 <6>[ 0.103630] smp: Brought up 1 node, 8 CPUs
10412 23:51:35.793504 <6>[ 0.245108] SMP: Total of 8 processors activated.
10413 23:51:35.796650 <6>[ 0.250029] CPU features: detected: 32-bit EL0 Support
10414 23:51:35.806432 <6>[ 0.255392] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10415 23:51:35.813279 <6>[ 0.264192] CPU features: detected: Common not Private translations
10416 23:51:35.819505 <6>[ 0.270669] CPU features: detected: CRC32 instructions
10417 23:51:35.826535 <6>[ 0.276053] CPU features: detected: RCpc load-acquire (LDAPR)
10418 23:51:35.829514 <6>[ 0.282013] CPU features: detected: LSE atomic instructions
10419 23:51:35.836259 <6>[ 0.287795] CPU features: detected: Privileged Access Never
10420 23:51:35.842864 <6>[ 0.293574] CPU features: detected: RAS Extension Support
10421 23:51:35.849642 <6>[ 0.299218] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10422 23:51:35.852583 <6>[ 0.306448] CPU: All CPU(s) started at EL2
10423 23:51:35.859621 <6>[ 0.310765] alternatives: applying system-wide alternatives
10424 23:51:35.869102 <6>[ 0.321580] devtmpfs: initialized
10425 23:51:35.881505 <6>[ 0.330377] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10426 23:51:35.891262 <6>[ 0.340341] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10427 23:51:35.897817 <6>[ 0.348362] pinctrl core: initialized pinctrl subsystem
10428 23:51:35.901421 <6>[ 0.354999] DMI not present or invalid.
10429 23:51:35.907892 <6>[ 0.359404] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10430 23:51:35.917542 <6>[ 0.366261] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10431 23:51:35.924438 <6>[ 0.373844] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10432 23:51:35.934393 <6>[ 0.382061] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10433 23:51:35.937428 <6>[ 0.390304] audit: initializing netlink subsys (disabled)
10434 23:51:35.947180 <5>[ 0.395995] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10435 23:51:35.953758 <6>[ 0.396689] thermal_sys: Registered thermal governor 'step_wise'
10436 23:51:35.960256 <6>[ 0.403957] thermal_sys: Registered thermal governor 'power_allocator'
10437 23:51:35.963787 <6>[ 0.410214] cpuidle: using governor menu
10438 23:51:35.970491 <6>[ 0.421175] NET: Registered PF_QIPCRTR protocol family
10439 23:51:35.977034 <6>[ 0.426652] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10440 23:51:35.983486 <6>[ 0.433751] ASID allocator initialised with 32768 entries
10441 23:51:35.986570 <6>[ 0.440316] Serial: AMBA PL011 UART driver
10442 23:51:35.996587 <4>[ 0.449041] Trying to register duplicate clock ID: 134
10443 23:51:36.054489 <6>[ 0.510143] KASLR enabled
10444 23:51:36.069130 <6>[ 0.517819] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10445 23:51:36.075557 <6>[ 0.524830] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10446 23:51:36.082124 <6>[ 0.531315] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10447 23:51:36.088725 <6>[ 0.538317] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10448 23:51:36.095504 <6>[ 0.544800] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10449 23:51:36.102320 <6>[ 0.551802] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10450 23:51:36.108781 <6>[ 0.558287] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10451 23:51:36.115562 <6>[ 0.565294] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10452 23:51:36.118600 <6>[ 0.572740] ACPI: Interpreter disabled.
10453 23:51:36.127297 <6>[ 0.579181] iommu: Default domain type: Translated
10454 23:51:36.133437 <6>[ 0.584296] iommu: DMA domain TLB invalidation policy: strict mode
10455 23:51:36.137268 <5>[ 0.590959] SCSI subsystem initialized
10456 23:51:36.143509 <6>[ 0.595208] usbcore: registered new interface driver usbfs
10457 23:51:36.149823 <6>[ 0.600939] usbcore: registered new interface driver hub
10458 23:51:36.153483 <6>[ 0.606491] usbcore: registered new device driver usb
10459 23:51:36.160298 <6>[ 0.612602] pps_core: LinuxPPS API ver. 1 registered
10460 23:51:36.170426 <6>[ 0.617794] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10461 23:51:36.173450 <6>[ 0.627139] PTP clock support registered
10462 23:51:36.176851 <6>[ 0.631381] EDAC MC: Ver: 3.0.0
10463 23:51:36.184287 <6>[ 0.636551] FPGA manager framework
10464 23:51:36.190569 <6>[ 0.640223] Advanced Linux Sound Architecture Driver Initialized.
10465 23:51:36.194085 <6>[ 0.646991] vgaarb: loaded
10466 23:51:36.200629 <6>[ 0.650152] clocksource: Switched to clocksource arch_sys_counter
10467 23:51:36.204218 <5>[ 0.656597] VFS: Disk quotas dquot_6.6.0
10468 23:51:36.210733 <6>[ 0.660784] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10469 23:51:36.213881 <6>[ 0.667973] pnp: PnP ACPI: disabled
10470 23:51:36.222718 <6>[ 0.674573] NET: Registered PF_INET protocol family
10471 23:51:36.232380 <6>[ 0.680162] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10472 23:51:36.243632 <6>[ 0.692483] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10473 23:51:36.253465 <6>[ 0.701297] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10474 23:51:36.260030 <6>[ 0.709268] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10475 23:51:36.270167 <6>[ 0.717970] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10476 23:51:36.276611 <6>[ 0.727727] TCP: Hash tables configured (established 65536 bind 65536)
10477 23:51:36.283418 <6>[ 0.734592] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10478 23:51:36.293104 <6>[ 0.741787] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 23:51:36.299578 <6>[ 0.749494] NET: Registered PF_UNIX/PF_LOCAL protocol family
10480 23:51:36.303184 <6>[ 0.755649] RPC: Registered named UNIX socket transport module.
10481 23:51:36.309189 <6>[ 0.761804] RPC: Registered udp transport module.
10482 23:51:36.313157 <6>[ 0.766736] RPC: Registered tcp transport module.
10483 23:51:36.323021 <6>[ 0.771670] RPC: Registered tcp NFSv4.1 backchannel transport module.
10484 23:51:36.326251 <6>[ 0.778337] PCI: CLS 0 bytes, default 64
10485 23:51:36.329221 <6>[ 0.782678] Unpacking initramfs...
10486 23:51:36.353297 <6>[ 0.802274] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10487 23:51:36.363539 <6>[ 0.810920] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10488 23:51:36.366525 <6>[ 0.819755] kvm [1]: IPA Size Limit: 40 bits
10489 23:51:36.373236 <6>[ 0.824271] kvm [1]: GICv3: no GICV resource entry
10490 23:51:36.376461 <6>[ 0.829289] kvm [1]: disabling GICv2 emulation
10491 23:51:36.383388 <6>[ 0.833976] kvm [1]: GIC system register CPU interface enabled
10492 23:51:36.386489 <6>[ 0.840130] kvm [1]: vgic interrupt IRQ18
10493 23:51:36.393164 <6>[ 0.844485] kvm [1]: VHE mode initialized successfully
10494 23:51:36.399619 <5>[ 0.850959] Initialise system trusted keyrings
10495 23:51:36.406354 <6>[ 0.855768] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10496 23:51:36.413604 <6>[ 0.865779] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10497 23:51:36.419908 <5>[ 0.872167] NFS: Registering the id_resolver key type
10498 23:51:36.423517 <5>[ 0.877467] Key type id_resolver registered
10499 23:51:36.430254 <5>[ 0.881878] Key type id_legacy registered
10500 23:51:36.437128 <6>[ 0.886161] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10501 23:51:36.443688 <6>[ 0.893086] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10502 23:51:36.449909 <6>[ 0.900805] 9p: Installing v9fs 9p2000 file system support
10503 23:51:36.486064 <5>[ 0.938219] Key type asymmetric registered
10504 23:51:36.489602 <5>[ 0.942550] Asymmetric key parser 'x509' registered
10505 23:51:36.499238 <6>[ 0.947693] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10506 23:51:36.502522 <6>[ 0.955308] io scheduler mq-deadline registered
10507 23:51:36.505786 <6>[ 0.960068] io scheduler kyber registered
10508 23:51:36.524766 <6>[ 0.977156] EINJ: ACPI disabled.
10509 23:51:36.557231 <4>[ 1.003123] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10510 23:51:36.567727 <4>[ 1.013752] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 23:51:36.582150 <6>[ 1.034667] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10512 23:51:36.590199 <6>[ 1.042688] printk: console [ttyS0] disabled
10513 23:51:36.618421 <6>[ 1.067320] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10514 23:51:36.625295 <6>[ 1.076795] printk: console [ttyS0] enabled
10515 23:51:36.628362 <6>[ 1.076795] printk: console [ttyS0] enabled
10516 23:51:36.634764 <6>[ 1.085692] printk: bootconsole [mtk8250] disabled
10517 23:51:36.638537 <6>[ 1.085692] printk: bootconsole [mtk8250] disabled
10518 23:51:36.644730 <6>[ 1.096966] SuperH (H)SCI(F) driver initialized
10519 23:51:36.648223 <6>[ 1.102288] msm_serial: driver initialized
10520 23:51:36.662603 <6>[ 1.111212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10521 23:51:36.672483 <6>[ 1.119760] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10522 23:51:36.679025 <6>[ 1.128300] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10523 23:51:36.688806 <6>[ 1.136928] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10524 23:51:36.699193 <6>[ 1.145634] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10525 23:51:36.705310 <6>[ 1.154354] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10526 23:51:36.715326 <6>[ 1.162894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10527 23:51:36.721792 <6>[ 1.171701] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10528 23:51:36.731913 <6>[ 1.180243] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10529 23:51:36.743255 <6>[ 1.195332] loop: module loaded
10530 23:51:36.749467 <6>[ 1.201374] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10531 23:51:36.772497 <4>[ 1.224660] mtk-pmic-keys: Failed to locate of_node [id: -1]
10532 23:51:36.779227 <6>[ 1.231484] megasas: 07.719.03.00-rc1
10533 23:51:36.788939 <6>[ 1.241235] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10534 23:51:36.801347 <6>[ 1.253541] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10535 23:51:36.818285 <6>[ 1.270345] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10536 23:51:36.874698 <6>[ 1.320402] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10537 23:51:37.250959 <6>[ 1.703729] Freeing initrd memory: 20856K
10538 23:51:37.266391 <6>[ 1.719334] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10539 23:51:37.277441 <6>[ 1.730264] tun: Universal TUN/TAP device driver, 1.6
10540 23:51:37.280903 <6>[ 1.736327] thunder_xcv, ver 1.0
10541 23:51:37.284103 <6>[ 1.739835] thunder_bgx, ver 1.0
10542 23:51:37.287223 <6>[ 1.743329] nicpf, ver 1.0
10543 23:51:37.298167 <6>[ 1.747340] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10544 23:51:37.301206 <6>[ 1.754815] hns3: Copyright (c) 2017 Huawei Corporation.
10545 23:51:37.304899 <6>[ 1.760407] hclge is initializing
10546 23:51:37.311227 <6>[ 1.763989] e1000: Intel(R) PRO/1000 Network Driver
10547 23:51:37.317842 <6>[ 1.769119] e1000: Copyright (c) 1999-2006 Intel Corporation.
10548 23:51:37.321316 <6>[ 1.775130] e1000e: Intel(R) PRO/1000 Network Driver
10549 23:51:37.328007 <6>[ 1.780345] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10550 23:51:37.334714 <6>[ 1.786532] igb: Intel(R) Gigabit Ethernet Network Driver
10551 23:51:37.341616 <6>[ 1.792181] igb: Copyright (c) 2007-2014 Intel Corporation.
10552 23:51:37.348470 <6>[ 1.798019] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10553 23:51:37.351604 <6>[ 1.804538] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10554 23:51:37.358557 <6>[ 1.810997] sky2: driver version 1.30
10555 23:51:37.365435 <6>[ 1.815917] usbcore: registered new device driver r8152-cfgselector
10556 23:51:37.371859 <6>[ 1.822450] usbcore: registered new interface driver r8152
10557 23:51:37.375365 <6>[ 1.828264] VFIO - User Level meta-driver version: 0.3
10558 23:51:37.383979 <6>[ 1.836520] usbcore: registered new interface driver usb-storage
10559 23:51:37.390840 <6>[ 1.842963] usbcore: registered new device driver onboard-usb-hub
10560 23:51:37.399894 <6>[ 1.852113] mt6397-rtc mt6359-rtc: registered as rtc0
10561 23:51:37.409409 <6>[ 1.857573] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:50:10 UTC (1717026610)
10562 23:51:37.413047 <6>[ 1.867138] i2c_dev: i2c /dev entries driver
10563 23:51:37.429913 <6>[ 1.878953] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10564 23:51:37.436831 <4>[ 1.887672] cpu cpu0: supply cpu not found, using dummy regulator
10565 23:51:37.443278 <4>[ 1.894107] cpu cpu1: supply cpu not found, using dummy regulator
10566 23:51:37.449937 <4>[ 1.900513] cpu cpu2: supply cpu not found, using dummy regulator
10567 23:51:37.456312 <4>[ 1.906913] cpu cpu3: supply cpu not found, using dummy regulator
10568 23:51:37.463718 <4>[ 1.913303] cpu cpu4: supply cpu not found, using dummy regulator
10569 23:51:37.470018 <4>[ 1.919702] cpu cpu5: supply cpu not found, using dummy regulator
10570 23:51:37.476379 <4>[ 1.926111] cpu cpu6: supply cpu not found, using dummy regulator
10571 23:51:37.479877 <4>[ 1.932510] cpu cpu7: supply cpu not found, using dummy regulator
10572 23:51:37.501839 <6>[ 1.954135] cpu cpu0: EM: created perf domain
10573 23:51:37.505166 <6>[ 1.959064] cpu cpu4: EM: created perf domain
10574 23:51:37.511723 <6>[ 1.964350] sdhci: Secure Digital Host Controller Interface driver
10575 23:51:37.518369 <6>[ 1.970783] sdhci: Copyright(c) Pierre Ossman
10576 23:51:37.525200 <6>[ 1.975733] Synopsys Designware Multimedia Card Interface Driver
10577 23:51:37.531795 <6>[ 1.982378] sdhci-pltfm: SDHCI platform and OF driver helper
10578 23:51:37.535119 <6>[ 1.982491] mmc0: CQHCI version 5.10
10579 23:51:37.541868 <6>[ 1.992350] ledtrig-cpu: registered to indicate activity on CPUs
10580 23:51:37.548428 <6>[ 1.999388] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10581 23:51:37.554779 <6>[ 2.006441] usbcore: registered new interface driver usbhid
10582 23:51:37.558671 <6>[ 2.012263] usbhid: USB HID core driver
10583 23:51:37.564946 <6>[ 2.016462] spi_master spi0: will run message pump with realtime priority
10584 23:51:37.613110 <6>[ 2.058900] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10585 23:51:37.629468 <6>[ 2.075191] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10586 23:51:37.636904 <6>[ 2.088811] mmc0: Command Queue Engine enabled
10587 23:51:37.643879 <6>[ 2.093572] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10588 23:51:37.650694 <6>[ 2.100698] cros-ec-spi spi0.0: Chrome EC device registered
10589 23:51:37.653391 <6>[ 2.100948] mmcblk0: mmc0:0001 DA4128 116 GiB
10590 23:51:37.664066 <6>[ 2.116603] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10591 23:51:37.671916 <6>[ 2.124137] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10592 23:51:37.678626 <6>[ 2.130027] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10593 23:51:37.685162 <6>[ 2.136061] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10594 23:51:37.695371 <6>[ 2.142861] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10595 23:51:37.702324 <6>[ 2.153488] NET: Registered PF_PACKET protocol family
10596 23:51:37.705251 <6>[ 2.158908] 9pnet: Installing 9P2000 support
10597 23:51:37.711795 <5>[ 2.163473] Key type dns_resolver registered
10598 23:51:37.715456 <6>[ 2.168592] registered taskstats version 1
10599 23:51:37.721748 <5>[ 2.173004] Loading compiled-in X.509 certificates
10600 23:51:37.750328 <4>[ 2.196048] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 23:51:37.760458 <4>[ 2.206778] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 23:51:37.776072 <6>[ 2.228165] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10603 23:51:37.782707 <6>[ 2.235066] xhci-mtk 11200000.usb: xHCI Host Controller
10604 23:51:37.789408 <6>[ 2.240592] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10605 23:51:37.799318 <6>[ 2.248436] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10606 23:51:37.805921 <6>[ 2.257863] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10607 23:51:37.812834 <6>[ 2.263940] xhci-mtk 11200000.usb: xHCI Host Controller
10608 23:51:37.819097 <6>[ 2.269418] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10609 23:51:37.825929 <6>[ 2.277068] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10610 23:51:37.832839 <6>[ 2.284703] hub 1-0:1.0: USB hub found
10611 23:51:37.835835 <6>[ 2.288721] hub 1-0:1.0: 1 port detected
10612 23:51:37.842954 <6>[ 2.292992] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10613 23:51:37.849158 <6>[ 2.301543] hub 2-0:1.0: USB hub found
10614 23:51:37.852750 <6>[ 2.305548] hub 2-0:1.0: 1 port detected
10615 23:51:37.860148 <6>[ 2.312747] mtk-msdc 11f70000.mmc: Got CD GPIO
10616 23:51:37.872766 <6>[ 2.322024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10617 23:51:37.879293 <6>[ 2.330048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10618 23:51:37.889507 <4>[ 2.337987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10619 23:51:37.899847 <6>[ 2.347518] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10620 23:51:37.906000 <6>[ 2.355596] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10621 23:51:37.912781 <6>[ 2.363611] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10622 23:51:37.922626 <6>[ 2.371531] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10623 23:51:37.929393 <6>[ 2.379349] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10624 23:51:37.939565 <6>[ 2.387166] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10625 23:51:37.949470 <6>[ 2.397554] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10626 23:51:37.955960 <6>[ 2.405912] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10627 23:51:37.965832 <6>[ 2.414261] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10628 23:51:37.972005 <6>[ 2.422603] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10629 23:51:37.982624 <6>[ 2.430941] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10630 23:51:37.989116 <6>[ 2.439280] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10631 23:51:37.998771 <6>[ 2.447618] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10632 23:51:38.005348 <6>[ 2.455955] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10633 23:51:38.015403 <6>[ 2.464293] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10634 23:51:38.021953 <6>[ 2.472631] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10635 23:51:38.031692 <6>[ 2.480968] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10636 23:51:38.038744 <6>[ 2.489307] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10637 23:51:38.048784 <6>[ 2.497645] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10638 23:51:38.058421 <6>[ 2.505991] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10639 23:51:38.065099 <6>[ 2.514330] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10640 23:51:38.071464 <6>[ 2.523058] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10641 23:51:38.078398 <6>[ 2.530218] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10642 23:51:38.084942 <6>[ 2.536994] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10643 23:51:38.091545 <6>[ 2.543754] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10644 23:51:38.101594 <6>[ 2.550678] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10645 23:51:38.108295 <6>[ 2.557524] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10646 23:51:38.117850 <6>[ 2.566667] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10647 23:51:38.127997 <6>[ 2.575787] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10648 23:51:38.137717 <6>[ 2.585080] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10649 23:51:38.147416 <6>[ 2.594547] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10650 23:51:38.154218 <6>[ 2.604016] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10651 23:51:38.164481 <6>[ 2.613135] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10652 23:51:38.174303 <6>[ 2.622602] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10653 23:51:38.183966 <6>[ 2.631721] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10654 23:51:38.194021 <6>[ 2.641016] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10655 23:51:38.204026 <6>[ 2.651175] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10656 23:51:38.213365 <6>[ 2.662701] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10657 23:51:38.261533 <6>[ 2.710427] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10658 23:51:38.416284 <6>[ 2.868551] hub 1-1:1.0: USB hub found
10659 23:51:38.419437 <6>[ 2.873068] hub 1-1:1.0: 4 ports detected
10660 23:51:38.429323 <6>[ 2.881610] hub 1-1:1.0: USB hub found
10661 23:51:38.432093 <6>[ 2.885952] hub 1-1:1.0: 4 ports detected
10662 23:51:38.541603 <6>[ 2.990771] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10663 23:51:38.568188 <6>[ 3.020316] hub 2-1:1.0: USB hub found
10664 23:51:38.570966 <6>[ 3.024815] hub 2-1:1.0: 3 ports detected
10665 23:51:38.580373 <6>[ 3.032878] hub 2-1:1.0: USB hub found
10666 23:51:38.583726 <6>[ 3.037329] hub 2-1:1.0: 3 ports detected
10667 23:51:38.757076 <6>[ 3.206453] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10668 23:51:38.889452 <6>[ 3.342037] hub 1-1.4:1.0: USB hub found
10669 23:51:38.892934 <6>[ 3.346624] hub 1-1.4:1.0: 2 ports detected
10670 23:51:38.901618 <6>[ 3.354007] hub 1-1.4:1.0: USB hub found
10671 23:51:38.904496 <6>[ 3.358612] hub 1-1.4:1.0: 2 ports detected
10672 23:51:38.969356 <6>[ 3.418677] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10673 23:51:39.077527 <6>[ 3.527109] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10674 23:51:39.113430 <4>[ 3.562656] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10675 23:51:39.123191 <4>[ 3.571805] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10676 23:51:39.163484 <6>[ 3.615982] r8152 2-1.3:1.0 eth0: v1.12.13
10677 23:51:39.201199 <6>[ 3.650475] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10678 23:51:39.392241 <6>[ 3.842257] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10679 23:51:40.780145 <6>[ 5.233015] r8152 2-1.3:1.0 eth0: carrier on
10680 23:51:40.821288 <5>[ 5.258245] Sending DHCP requests ., OK
10681 23:51:40.828001 <6>[ 5.278412] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10682 23:51:40.831490 <6>[ 5.286697] IP-Config: Complete:
10683 23:51:40.844824 <6>[ 5.290196] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10684 23:51:40.851449 <6>[ 5.300912] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10685 23:51:40.858244 <6>[ 5.309530] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10686 23:51:40.865029 <6>[ 5.309539] nameserver0=192.168.201.1
10687 23:51:40.868233 <6>[ 5.321676] clk: Disabling unused clocks
10688 23:51:40.870997 <6>[ 5.327078] ALSA device list:
10689 23:51:40.874667 <6>[ 5.330337] No soundcards found.
10690 23:51:40.885240 <6>[ 5.337727] Freeing unused kernel memory: 8512K
10691 23:51:40.888126 <6>[ 5.342756] Run /init as init process
10692 23:51:40.913429 Starting syslogd: OK
10693 23:51:40.918154 Starting klogd: OK
10694 23:51:40.926449 Running sysctl: OK
10695 23:51:40.936755 Populating /dev using udev: <30>[ 5.388146] udevd[199]: starting version 3.2.9
10696 23:51:40.943529 <27>[ 5.395976] udevd[199]: specified user 'tss' unknown
10697 23:51:40.950166 <27>[ 5.401402] udevd[199]: specified group 'tss' unknown
10698 23:51:40.953440 <30>[ 5.407745] udevd[200]: starting eudev-3.2.9
10699 23:51:40.973622 <27>[ 5.426291] udevd[200]: specified user 'tss' unknown
10700 23:51:40.980129 <27>[ 5.431666] udevd[200]: specified group 'tss' unknown
10701 23:51:41.079772 <6>[ 5.529351] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10702 23:51:41.096159 <6>[ 5.545678] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10703 23:51:41.106058 <6>[ 5.554851] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10704 23:51:41.112946 <6>[ 5.564916] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10705 23:51:41.133962 <6>[ 5.586339] remoteproc remoteproc0: scp is available
10706 23:51:41.140917 <6>[ 5.592008] remoteproc remoteproc0: powering up scp
10707 23:51:41.143989 <6>[ 5.592558] mc: Linux media interface: v0.10
10708 23:51:41.153498 <3>[ 5.593245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 23:51:41.160789 <3>[ 5.593265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 23:51:41.167058 <3>[ 5.593268] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 23:51:41.176919 <3>[ 5.593454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 23:51:41.183433 <3>[ 5.593463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 23:51:41.193401 <3>[ 5.593470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:51:41.200076 <3>[ 5.593483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 23:51:41.209993 <3>[ 5.593486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 23:51:41.216541 <3>[ 5.593700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 23:51:41.226610 <3>[ 5.593764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 23:51:41.233007 <3>[ 5.593767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 23:51:41.240065 <3>[ 5.593771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 23:51:41.250090 <3>[ 5.593813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 23:51:41.256475 <3>[ 5.593816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 23:51:41.266132 <3>[ 5.593819] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 23:51:41.272706 <3>[ 5.593823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 23:51:41.282669 <3>[ 5.593825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 23:51:41.289249 <3>[ 5.593860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 23:51:41.299243 <6>[ 5.597316] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10727 23:51:41.305804 <6>[ 5.635445] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10728 23:51:41.312787 <4>[ 5.635474] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10729 23:51:41.319062 <4>[ 5.635591] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10730 23:51:41.325538 <6>[ 5.642272] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10731 23:51:41.332604 <6>[ 5.675339] videodev: Linux video capture interface: v2.00
10732 23:51:41.339088 <4>[ 5.683566] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10733 23:51:41.345796 <4>[ 5.683566] Fallback method does not support PEC.
10734 23:51:41.352486 <6>[ 5.687570] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10735 23:51:41.358914 <6>[ 5.687576] pci_bus 0000:00: root bus resource [bus 00-ff]
10736 23:51:41.365634 <6>[ 5.687580] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10737 23:51:41.376076 <6>[ 5.687582] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10738 23:51:41.383484 <6>[ 5.687640] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10739 23:51:41.389628 <6>[ 5.687704] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10740 23:51:41.392812 <6>[ 5.687977] pci 0000:00:00.0: supports D1 D2
10741 23:51:41.399848 <6>[ 5.687979] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10742 23:51:41.409342 <6>[ 5.689194] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10743 23:51:41.416000 <6>[ 5.689435] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10744 23:51:41.422578 <6>[ 5.689510] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10745 23:51:41.429366 <6>[ 5.689557] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10746 23:51:41.436232 <6>[ 5.689604] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10747 23:51:41.442612 <6>[ 5.689878] pci 0000:01:00.0: supports D1 D2
10748 23:51:41.449378 <6>[ 5.689880] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 23:51:41.455958 <6>[ 5.706236] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10750 23:51:41.465978 <6>[ 5.711083] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10751 23:51:41.472478 <6>[ 5.715423] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10752 23:51:41.482374 <6>[ 5.724039] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10753 23:51:41.492960 <6>[ 5.731684] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10754 23:51:41.499530 <6>[ 5.744307] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10755 23:51:41.509507 <6>[ 5.747981] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10756 23:51:41.512857 <6>[ 5.784903] Bluetooth: Core ver 2.22
10757 23:51:41.519529 <6>[ 5.789820] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10758 23:51:41.525924 <6>[ 5.803552] NET: Registered PF_BLUETOOTH protocol family
10759 23:51:41.532467 <6>[ 5.808636] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10760 23:51:41.542265 <6>[ 5.808654] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10761 23:51:41.548953 <6>[ 5.808663] remoteproc remoteproc0: remote processor scp is now up
10762 23:51:41.555620 <6>[ 5.810319] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10763 23:51:41.561994 <6>[ 5.810337] pci 0000:00:00.0: PCI bridge to [bus 01]
10764 23:51:41.569301 <6>[ 5.810348] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10765 23:51:41.575535 <6>[ 5.810907] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10766 23:51:41.582299 <6>[ 5.816107] Bluetooth: HCI device and connection manager initialized
10767 23:51:41.588729 <6>[ 5.824907] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10768 23:51:41.595284 <6>[ 5.824977] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10769 23:51:41.601851 <6>[ 5.826086] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10770 23:51:41.608530 <6>[ 5.826112] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10771 23:51:41.618146 <6>[ 5.830640] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10772 23:51:41.621827 <6>[ 5.833213] Bluetooth: HCI socket layer initialized
10773 23:51:41.628014 <6>[ 5.841249] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10774 23:51:41.637876 <5>[ 5.841342] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10775 23:51:41.647933 <6>[ 5.841380] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10776 23:51:41.654856 <6>[ 5.841543] usbcore: registered new interface driver uvcvideo
10777 23:51:41.661178 <6>[ 5.847046] Bluetooth: L2CAP socket layer initialized
10778 23:51:41.668051 <3>[ 5.853519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 23:51:41.674303 <6>[ 5.858428] Bluetooth: SCO socket layer initialized
10780 23:51:41.681537 <5>[ 5.868485] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10781 23:51:41.687948 <6>[ 5.924258] usbcore: registered new interface driver btusb
10782 23:51:41.697894 <4>[ 5.925225] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10783 23:51:41.704323 <3>[ 5.925233] Bluetooth: hci0: Failed to load firmware file (-2)
10784 23:51:41.711060 <3>[ 5.925235] Bluetooth: hci0: Failed to set up firmware (-2)
10785 23:51:41.721319 <4>[ 5.925238] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10786 23:51:41.727750 <5>[ 5.932288] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10787 23:51:41.737392 <3>[ 5.951310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10788 23:51:41.747601 <4>[ 5.958308] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10789 23:51:41.753936 <6>[ 6.059917] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10790 23:51:41.757045 <6>[ 6.061061] cfg80211: failed to load regulatory.db
10791 23:51:41.763619 <6>[ 6.067063] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10792 23:51:41.789391 <6>[ 6.242382] mt7921e 0000:01:00.0: ASIC revision: 79610010
10793 23:51:41.893134 <6>[ 6.342508] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10794 23:51:41.896358 <6>[ 6.342508]
10795 23:51:41.896958 done
10796 23:51:41.907201 Saving random seed: OK
10797 23:51:41.917770 Starting network: ip: RTNETLINK answers: File exists
10798 23:51:41.920951 FAIL
10799 23:51:41.953870 Starting dropbear sshd: <6>[ 6.406875] NET: Registered PF_INET6 protocol family
10800 23:51:41.960840 <6>[ 6.413418] Segment Routing with IPv6
10801 23:51:41.963827 <6>[ 6.417396] In-situ OAM (IOAM) with IPv6
10802 23:51:41.967562 OK
10803 23:51:41.981277 /bin/sh: can't access tty; job control turned off
10804 23:51:41.982694 Matched prompt #10: / #
10806 23:51:41.983830 Setting prompt string to ['/ #']
10807 23:51:41.984309 end: 2.2.5.1 login-action (duration 00:00:07) [common]
10809 23:51:41.985427 end: 2.2.5 auto-login-action (duration 00:00:07) [common]
10810 23:51:41.985917 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
10811 23:51:41.986316 Setting prompt string to ['/ #']
10812 23:51:41.986661 Forcing a shell prompt, looking for ['/ #']
10814 23:51:42.037688 / #
10815 23:51:42.038350 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10816 23:51:42.038897 Waiting using forced prompt support (timeout 00:02:30)
10817 23:51:42.044661
10818 23:51:42.045596 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10819 23:51:42.046125 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
10820 23:51:42.046630 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10821 23:51:42.047105 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
10822 23:51:42.047570 end: 2 depthcharge-action (duration 00:01:16) [common]
10823 23:51:42.048056 start: 3 lava-test-retry (timeout 00:01:00) [common]
10824 23:51:42.048533 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10825 23:51:42.048983 Using namespace: common
10827 23:51:42.150381 / # #
10828 23:51:42.151050 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10829 23:51:42.161780 #<6>[ 6.611320] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10830 23:51:42.162358
10831 23:51:42.163040 Using /lava-14084338
10833 23:51:42.264316 / # export SHELL=/bin/sh
10834 23:51:42.270992 export SHELL=/bin/sh
10836 23:51:42.372684 / # . /lava-14084338/environment
10837 23:51:42.379539 . /lava-14084338/environment
10839 23:51:42.481453 / # /lava-14084338/bin/lava-test-runner /lava-14084338/0
10840 23:51:42.482088 Test shell timeout: 10s (minimum of the action and connection timeout)
10841 23:51:42.488440 /lava-14084338/bin/lava-test-runner /lava-14084338/0
10842 23:51:42.508530 + export 'TESTRUN_ID=0_dmesg'
10843 23:51:42.514925 +<8>[ 6.966952] <LAVA_SIGNAL_STARTRUN 0_dmesg 14084338_1.5.2.3.1>
10844 23:51:42.515786 Received signal: <STARTRUN> 0_dmesg 14084338_1.5.2.3.1
10845 23:51:42.516212 Starting test lava.0_dmesg (14084338_1.5.2.3.1)
10846 23:51:42.516709 Skipping test definition patterns.
10847 23:51:42.518219 cd /lava-14084338/0/tests/0_dmesg
10848 23:51:42.518919 + cat uuid
10849 23:51:42.521498 + UUID=14084338_1.5.2.3.1
10850 23:51:42.521992 + set +x
10851 23:51:42.528296 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10852 23:51:42.537924 <8>[ 6.987478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10853 23:51:42.538658 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10855 23:51:42.558691 <8>[ 7.008203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10856 23:51:42.559535 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10858 23:51:42.578884 <8>[ 7.028515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10859 23:51:42.579716 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10861 23:51:42.581939 + set +x
10862 23:51:42.585607 <8>[ 7.037928] <LAVA_SIGNAL_ENDRUN 0_dmesg 14084338_1.5.2.3.1>
10863 23:51:42.586438 Received signal: <ENDRUN> 0_dmesg 14084338_1.5.2.3.1
10864 23:51:42.586893 Ending use of test pattern.
10865 23:51:42.587250 Ending test lava.0_dmesg (14084338_1.5.2.3.1), duration 0.07
10867 23:51:42.589209 <LAVA_TEST_RUNNER EXIT>
10868 23:51:42.589923 ok: lava_test_shell seems to have completed
10869 23:51:42.590504 alert: pass
crit: pass
emerg: pass
10870 23:51:42.590958 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10871 23:51:42.591416 end: 3 lava-test-retry (duration 00:00:01) [common]
10872 23:51:42.591894 start: 4 finalize (timeout 00:08:23) [common]
10873 23:51:42.592382 start: 4.1 power-off (timeout 00:00:30) [common]
10874 23:51:42.593221 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
10875 23:51:42.856218 >> Command sent successfully.
10876 23:51:42.867090 Returned 0 in 0 seconds
10877 23:51:42.968438 end: 4.1 power-off (duration 00:00:00) [common]
10879 23:51:42.970059 start: 4.2 read-feedback (timeout 00:08:23) [common]
10880 23:51:42.971414 Listened to connection for namespace 'common' for up to 1s
10881 23:51:43.972124 Finalising connection for namespace 'common'
10882 23:51:43.972848 Disconnecting from shell: Finalise
10883 23:51:43.973281 / #
10884 23:51:44.074386 end: 4.2 read-feedback (duration 00:00:01) [common]
10885 23:51:44.075145 end: 4 finalize (duration 00:00:01) [common]
10886 23:51:44.075760 Cleaning after the job
10887 23:51:44.076289 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/ramdisk
10888 23:51:44.081680 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/kernel
10889 23:51:44.088741 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/dtb
10890 23:51:44.088890 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084338/tftp-deploy-kfz9ggpj/modules
10891 23:51:44.094196 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084338
10892 23:51:44.129317 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084338
10893 23:51:44.129483 Job finished correctly