Boot log: mt8192-asurada-spherion-r0

    1 23:52:56.104186  lava-dispatcher, installed at version: 2024.03
    2 23:52:56.104448  start: 0 validate
    3 23:52:56.104602  Start time: 2024-05-29 23:52:56.104594+00:00 (UTC)
    4 23:52:56.104731  Using caching service: 'http://localhost/cache/?uri=%s'
    5 23:52:56.104860  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
    6 23:52:56.363563  Using caching service: 'http://localhost/cache/?uri=%s'
    7 23:52:56.363823  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 23:53:11.622575  Using caching service: 'http://localhost/cache/?uri=%s'
    9 23:53:11.622740  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 23:53:11.887779  Using caching service: 'http://localhost/cache/?uri=%s'
   11 23:53:11.887932  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 23:53:12.416540  Using caching service: 'http://localhost/cache/?uri=%s'
   13 23:53:12.416710  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 23:53:14.919494  validate duration: 18.81
   16 23:53:14.919758  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 23:53:14.919857  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 23:53:14.919944  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 23:53:14.920065  Not decompressing ramdisk as can be used compressed.
   20 23:53:14.920150  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
   21 23:53:14.920213  saving as /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/ramdisk/initrd.cpio.gz
   22 23:53:14.920275  total size: 5628182 (5 MB)
   23 23:53:15.177969  progress   0 % (0 MB)
   24 23:53:15.180175  progress   5 % (0 MB)
   25 23:53:15.182492  progress  10 % (0 MB)
   26 23:53:15.184619  progress  15 % (0 MB)
   27 23:53:15.187060  progress  20 % (1 MB)
   28 23:53:15.189256  progress  25 % (1 MB)
   29 23:53:15.191629  progress  30 % (1 MB)
   30 23:53:15.194005  progress  35 % (1 MB)
   31 23:53:15.196120  progress  40 % (2 MB)
   32 23:53:15.198504  progress  45 % (2 MB)
   33 23:53:15.200661  progress  50 % (2 MB)
   34 23:53:15.203058  progress  55 % (2 MB)
   35 23:53:15.205423  progress  60 % (3 MB)
   36 23:53:15.207493  progress  65 % (3 MB)
   37 23:53:15.209192  progress  70 % (3 MB)
   38 23:53:15.210668  progress  75 % (4 MB)
   39 23:53:15.212297  progress  80 % (4 MB)
   40 23:53:15.213818  progress  85 % (4 MB)
   41 23:53:15.215423  progress  90 % (4 MB)
   42 23:53:15.217128  progress  95 % (5 MB)
   43 23:53:15.218591  progress 100 % (5 MB)
   44 23:53:15.218798  5 MB downloaded in 0.30 s (17.98 MB/s)
   45 23:53:15.218951  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 23:53:15.219179  end: 1.1 download-retry (duration 00:00:00) [common]
   48 23:53:15.219266  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 23:53:15.219352  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 23:53:15.219485  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 23:53:15.219554  saving as /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/kernel/Image
   52 23:53:15.219614  total size: 54682112 (52 MB)
   53 23:53:15.219675  No compression specified
   54 23:53:15.220822  progress   0 % (0 MB)
   55 23:53:15.235746  progress   5 % (2 MB)
   56 23:53:15.257010  progress  10 % (5 MB)
   57 23:53:15.275516  progress  15 % (7 MB)
   58 23:53:15.289679  progress  20 % (10 MB)
   59 23:53:15.306772  progress  25 % (13 MB)
   60 23:53:15.327881  progress  30 % (15 MB)
   61 23:53:15.348276  progress  35 % (18 MB)
   62 23:53:15.365504  progress  40 % (20 MB)
   63 23:53:15.380780  progress  45 % (23 MB)
   64 23:53:15.395005  progress  50 % (26 MB)
   65 23:53:15.409078  progress  55 % (28 MB)
   66 23:53:15.423130  progress  60 % (31 MB)
   67 23:53:15.437216  progress  65 % (33 MB)
   68 23:53:15.451443  progress  70 % (36 MB)
   69 23:53:15.465542  progress  75 % (39 MB)
   70 23:53:15.479905  progress  80 % (41 MB)
   71 23:53:15.494031  progress  85 % (44 MB)
   72 23:53:15.508115  progress  90 % (46 MB)
   73 23:53:15.522201  progress  95 % (49 MB)
   74 23:53:15.535990  progress 100 % (52 MB)
   75 23:53:15.536251  52 MB downloaded in 0.32 s (164.70 MB/s)
   76 23:53:15.536415  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 23:53:15.536655  end: 1.2 download-retry (duration 00:00:00) [common]
   79 23:53:15.536742  start: 1.3 download-retry (timeout 00:09:59) [common]
   80 23:53:15.536827  start: 1.3.1 http-download (timeout 00:09:59) [common]
   81 23:53:15.536962  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 23:53:15.537034  saving as /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/dtb/mt8192-asurada-spherion-r0.dtb
   83 23:53:15.537095  total size: 47258 (0 MB)
   84 23:53:15.537155  No compression specified
   85 23:53:15.538256  progress  69 % (0 MB)
   86 23:53:15.538550  progress 100 % (0 MB)
   87 23:53:15.538707  0 MB downloaded in 0.00 s (27.99 MB/s)
   88 23:53:15.538830  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 23:53:15.539051  end: 1.3 download-retry (duration 00:00:00) [common]
   91 23:53:15.539136  start: 1.4 download-retry (timeout 00:09:59) [common]
   92 23:53:15.539219  start: 1.4.1 http-download (timeout 00:09:59) [common]
   93 23:53:15.539335  downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
   94 23:53:15.539403  saving as /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/nfsrootfs/full.rootfs.tar
   95 23:53:15.539463  total size: 107552908 (102 MB)
   96 23:53:15.539524  Using unxz to decompress xz
   97 23:53:15.543635  progress   0 % (0 MB)
   98 23:53:15.869054  progress   5 % (5 MB)
   99 23:53:16.200364  progress  10 % (10 MB)
  100 23:53:16.533266  progress  15 % (15 MB)
  101 23:53:16.888714  progress  20 % (20 MB)
  102 23:53:17.195551  progress  25 % (25 MB)
  103 23:53:17.504077  progress  30 % (30 MB)
  104 23:53:17.874024  progress  35 % (35 MB)
  105 23:53:18.058142  progress  40 % (41 MB)
  106 23:53:18.260049  progress  45 % (46 MB)
  107 23:53:18.585835  progress  50 % (51 MB)
  108 23:53:18.899805  progress  55 % (56 MB)
  109 23:53:19.286391  progress  60 % (61 MB)
  110 23:53:19.633016  progress  65 % (66 MB)
  111 23:53:20.001420  progress  70 % (71 MB)
  112 23:53:20.361432  progress  75 % (76 MB)
  113 23:53:20.678913  progress  80 % (82 MB)
  114 23:53:21.000237  progress  85 % (87 MB)
  115 23:53:21.324396  progress  90 % (92 MB)
  116 23:53:21.674254  progress  95 % (97 MB)
  117 23:53:22.031083  progress 100 % (102 MB)
  118 23:53:22.036463  102 MB downloaded in 6.50 s (15.79 MB/s)
  119 23:53:22.036764  end: 1.4.1 http-download (duration 00:00:06) [common]
  121 23:53:22.037045  end: 1.4 download-retry (duration 00:00:06) [common]
  122 23:53:22.037140  start: 1.5 download-retry (timeout 00:09:53) [common]
  123 23:53:22.037231  start: 1.5.1 http-download (timeout 00:09:53) [common]
  124 23:53:22.037387  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 23:53:22.037458  saving as /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/modules/modules.tar
  126 23:53:22.037519  total size: 8601444 (8 MB)
  127 23:53:22.037582  Using unxz to decompress xz
  128 23:53:22.296993  progress   0 % (0 MB)
  129 23:53:22.318091  progress   5 % (0 MB)
  130 23:53:22.344428  progress  10 % (0 MB)
  131 23:53:22.372503  progress  15 % (1 MB)
  132 23:53:22.400402  progress  20 % (1 MB)
  133 23:53:22.428067  progress  25 % (2 MB)
  134 23:53:22.455977  progress  30 % (2 MB)
  135 23:53:22.480907  progress  35 % (2 MB)
  136 23:53:22.507063  progress  40 % (3 MB)
  137 23:53:22.535707  progress  45 % (3 MB)
  138 23:53:22.561736  progress  50 % (4 MB)
  139 23:53:22.588907  progress  55 % (4 MB)
  140 23:53:22.615067  progress  60 % (4 MB)
  141 23:53:22.640281  progress  65 % (5 MB)
  142 23:53:22.674120  progress  70 % (5 MB)
  143 23:53:22.710274  progress  75 % (6 MB)
  144 23:53:22.737095  progress  80 % (6 MB)
  145 23:53:22.765703  progress  85 % (7 MB)
  146 23:53:22.791133  progress  90 % (7 MB)
  147 23:53:22.822167  progress  95 % (7 MB)
  148 23:53:22.851760  progress 100 % (8 MB)
  149 23:53:22.857437  8 MB downloaded in 0.82 s (10.00 MB/s)
  150 23:53:22.857735  end: 1.5.1 http-download (duration 00:00:01) [common]
  152 23:53:22.858033  end: 1.5 download-retry (duration 00:00:01) [common]
  153 23:53:22.858132  start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
  154 23:53:22.858232  start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
  155 23:53:25.289530  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub
  156 23:53:25.289747  end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
  157 23:53:25.289851  start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
  158 23:53:25.290032  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o
  159 23:53:25.290163  makedir: /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin
  160 23:53:25.290270  makedir: /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/tests
  161 23:53:25.290369  makedir: /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/results
  162 23:53:25.290474  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-add-keys
  163 23:53:25.290619  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-add-sources
  164 23:53:25.290751  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-background-process-start
  165 23:53:25.290880  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-background-process-stop
  166 23:53:25.291008  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-common-functions
  167 23:53:25.291135  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-echo-ipv4
  168 23:53:25.291262  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-install-packages
  169 23:53:25.291388  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-installed-packages
  170 23:53:25.291517  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-os-build
  171 23:53:25.291644  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-probe-channel
  172 23:53:25.291769  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-probe-ip
  173 23:53:25.291896  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-target-ip
  174 23:53:25.292020  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-target-mac
  175 23:53:25.292145  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-target-storage
  176 23:53:25.292274  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-case
  177 23:53:25.292411  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-event
  178 23:53:25.292536  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-feedback
  179 23:53:25.292661  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-raise
  180 23:53:25.292785  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-reference
  181 23:53:25.292909  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-runner
  182 23:53:25.293032  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-set
  183 23:53:25.293158  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-test-shell
  184 23:53:25.293285  Updating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-install-packages (oe)
  185 23:53:25.293441  Updating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/bin/lava-installed-packages (oe)
  186 23:53:25.293565  Creating /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/environment
  187 23:53:25.293663  LAVA metadata
  188 23:53:25.293730  - LAVA_JOB_ID=14084317
  189 23:53:25.293792  - LAVA_DISPATCHER_IP=192.168.201.1
  190 23:53:25.293904  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
  191 23:53:25.293970  skipped lava-vland-overlay
  192 23:53:25.294047  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  193 23:53:25.294127  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
  194 23:53:25.294188  skipped lava-multinode-overlay
  195 23:53:25.294259  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  196 23:53:25.294336  start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
  197 23:53:25.294412  Loading test definitions
  198 23:53:25.294501  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
  199 23:53:25.294574  Using /lava-14084317 at stage 0
  200 23:53:25.294880  uuid=14084317_1.6.2.3.1 testdef=None
  201 23:53:25.294972  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  202 23:53:25.295057  start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
  203 23:53:25.295567  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  205 23:53:25.295791  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
  206 23:53:25.296509  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  208 23:53:25.296737  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
  209 23:53:25.297516  runner path: /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/0/tests/0_dmesg test_uuid 14084317_1.6.2.3.1
  210 23:53:25.297674  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  212 23:53:25.297878  Creating lava-test-runner.conf files
  213 23:53:25.297940  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084317/lava-overlay-jp_y5k0o/lava-14084317/0 for stage 0
  214 23:53:25.298029  - 0_dmesg
  215 23:53:25.298126  end: 1.6.2.3 test-definition (duration 00:00:00) [common]
  216 23:53:25.298210  start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
  217 23:53:25.304429  end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
  218 23:53:25.304583  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
  219 23:53:25.304676  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  220 23:53:25.304765  end: 1.6.2 lava-overlay (duration 00:00:00) [common]
  221 23:53:25.304851  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
  222 23:53:25.473744  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  223 23:53:25.474128  start: 1.6.4 extract-modules (timeout 00:09:49) [common]
  224 23:53:25.474243  extracting modules file /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub
  225 23:53:25.701642  extracting modules file /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084317/extract-overlay-ramdisk-814k_a8u/ramdisk
  226 23:53:25.931283  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  227 23:53:25.931482  start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
  228 23:53:25.931573  [common] Applying overlay to NFS
  229 23:53:25.931676  [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084317/compress-overlay-6mh3vled/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub
  230 23:53:25.938435  end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
  231 23:53:25.938603  start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
  232 23:53:25.938701  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  233 23:53:25.938802  start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
  234 23:53:25.938888  Building ramdisk /var/lib/lava/dispatcher/tmp/14084317/extract-overlay-ramdisk-814k_a8u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084317/extract-overlay-ramdisk-814k_a8u/ramdisk
  235 23:53:26.262166  >> 130335 blocks

  236 23:53:28.468257  rename /var/lib/lava/dispatcher/tmp/14084317/extract-overlay-ramdisk-814k_a8u/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/ramdisk/ramdisk.cpio.gz
  237 23:53:28.468818  end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
  238 23:53:28.469002  start: 1.6.8 prepare-kernel (timeout 00:09:46) [common]
  239 23:53:28.469138  start: 1.6.8.1 prepare-fit (timeout 00:09:46) [common]
  240 23:53:28.469286  Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/kernel/Image']
  241 23:53:43.243886  Returned 0 in 14 seconds
  242 23:53:43.344534  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/kernel/image.itb
  243 23:53:43.727861  output: FIT description: Kernel Image image with one or more FDT blobs
  244 23:53:43.728358  output: Created:         Thu May 30 00:53:43 2024
  245 23:53:43.728491  output:  Image 0 (kernel-1)
  246 23:53:43.728608  output:   Description:  
  247 23:53:43.728721  output:   Created:      Thu May 30 00:53:43 2024
  248 23:53:43.728833  output:   Type:         Kernel Image
  249 23:53:43.728946  output:   Compression:  lzma compressed
  250 23:53:43.729062  output:   Data Size:    13063488 Bytes = 12757.31 KiB = 12.46 MiB
  251 23:53:43.729181  output:   Architecture: AArch64
  252 23:53:43.729293  output:   OS:           Linux
  253 23:53:43.729408  output:   Load Address: 0x00000000
  254 23:53:43.729520  output:   Entry Point:  0x00000000
  255 23:53:43.729626  output:   Hash algo:    crc32
  256 23:53:43.729740  output:   Hash value:   907bf91d
  257 23:53:43.729851  output:  Image 1 (fdt-1)
  258 23:53:43.729962  output:   Description:  mt8192-asurada-spherion-r0
  259 23:53:43.730070  output:   Created:      Thu May 30 00:53:43 2024
  260 23:53:43.730183  output:   Type:         Flat Device Tree
  261 23:53:43.730293  output:   Compression:  uncompressed
  262 23:53:43.730402  output:   Data Size:    47258 Bytes = 46.15 KiB = 0.05 MiB
  263 23:53:43.730511  output:   Architecture: AArch64
  264 23:53:43.730619  output:   Hash algo:    crc32
  265 23:53:43.730726  output:   Hash value:   0f8e4d2e
  266 23:53:43.730836  output:  Image 2 (ramdisk-1)
  267 23:53:43.730939  output:   Description:  unavailable
  268 23:53:43.731048  output:   Created:      Thu May 30 00:53:43 2024
  269 23:53:43.731156  output:   Type:         RAMDisk Image
  270 23:53:43.731263  output:   Compression:  Unknown Compression
  271 23:53:43.731369  output:   Data Size:    18730692 Bytes = 18291.69 KiB = 17.86 MiB
  272 23:53:43.731475  output:   Architecture: AArch64
  273 23:53:43.731583  output:   OS:           Linux
  274 23:53:43.731690  output:   Load Address: unavailable
  275 23:53:43.731796  output:   Entry Point:  unavailable
  276 23:53:43.731902  output:   Hash algo:    crc32
  277 23:53:43.732004  output:   Hash value:   3d6a0da7
  278 23:53:43.732113  output:  Default Configuration: 'conf-1'
  279 23:53:43.732219  output:  Configuration 0 (conf-1)
  280 23:53:43.732325  output:   Description:  mt8192-asurada-spherion-r0
  281 23:53:43.732438  output:   Kernel:       kernel-1
  282 23:53:43.732543  output:   Init Ramdisk: ramdisk-1
  283 23:53:43.732651  output:   FDT:          fdt-1
  284 23:53:43.732755  output:   Loadables:    kernel-1
  285 23:53:43.732864  output: 
  286 23:53:43.733170  end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
  287 23:53:43.733339  end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
  288 23:53:43.733515  end: 1.6 prepare-tftp-overlay (duration 00:00:21) [common]
  289 23:53:43.733678  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
  290 23:53:43.733815  No LXC device requested
  291 23:53:43.733963  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  292 23:53:43.734116  start: 1.8 deploy-device-env (timeout 00:09:31) [common]
  293 23:53:43.734262  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  294 23:53:43.734386  Checking files for TFTP limit of 4294967296 bytes.
  295 23:53:43.735226  end: 1 tftp-deploy (duration 00:00:29) [common]
  296 23:53:43.735392  start: 2 depthcharge-action (timeout 00:05:00) [common]
  297 23:53:43.735549  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  298 23:53:43.735757  substitutions:
  299 23:53:43.735878  - {DTB}: 14084317/tftp-deploy-krm2ljnt/dtb/mt8192-asurada-spherion-r0.dtb
  300 23:53:43.735995  - {INITRD}: 14084317/tftp-deploy-krm2ljnt/ramdisk/ramdisk.cpio.gz
  301 23:53:43.736106  - {KERNEL}: 14084317/tftp-deploy-krm2ljnt/kernel/Image
  302 23:53:43.736219  - {LAVA_MAC}: None
  303 23:53:43.736329  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub
  304 23:53:43.736443  - {NFS_SERVER_IP}: 192.168.201.1
  305 23:53:43.736554  - {PRESEED_CONFIG}: None
  306 23:53:43.736664  - {PRESEED_LOCAL}: None
  307 23:53:43.736771  - {RAMDISK}: 14084317/tftp-deploy-krm2ljnt/ramdisk/ramdisk.cpio.gz
  308 23:53:43.736883  - {ROOT_PART}: None
  309 23:53:43.736994  - {ROOT}: None
  310 23:53:43.737100  - {SERVER_IP}: 192.168.201.1
  311 23:53:43.737209  - {TEE}: None
  312 23:53:43.737318  Parsed boot commands:
  313 23:53:43.737422  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  314 23:53:43.737726  Parsed boot commands: tftpboot 192.168.201.1 14084317/tftp-deploy-krm2ljnt/kernel/image.itb 14084317/tftp-deploy-krm2ljnt/kernel/cmdline 
  315 23:53:43.737880  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  316 23:53:43.738031  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  317 23:53:43.738194  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  318 23:53:43.738345  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  319 23:53:43.738478  Not connected, no need to disconnect.
  320 23:53:43.738617  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  321 23:53:43.738760  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  322 23:53:43.738885  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
  323 23:53:43.743436  Setting prompt string to ['lava-test: # ']
  324 23:53:43.743970  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  325 23:53:43.744150  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  326 23:53:43.744316  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  327 23:53:43.744493  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  328 23:53:43.744845  Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
  329 23:53:48.874133  >> Command sent successfully.

  330 23:53:48.877175  Returned 0 in 5 seconds
  331 23:53:48.977641  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  333 23:53:48.977967  end: 2.2.2 reset-device (duration 00:00:05) [common]
  334 23:53:48.978066  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  335 23:53:48.978156  Setting prompt string to 'Starting depthcharge on Spherion...'
  336 23:53:48.978224  Changing prompt to 'Starting depthcharge on Spherion...'
  337 23:53:48.978289  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  338 23:53:48.978692  [Enter `^Ec?' for help]

  339 23:53:49.149613  

  340 23:53:49.149805  

  341 23:53:49.149940  F0: 102B 0000

  342 23:53:49.150050  

  343 23:53:49.150143  F3: 1001 0000 [0200]

  344 23:53:49.150235  

  345 23:53:49.153357  F3: 1001 0000

  346 23:53:49.153480  

  347 23:53:49.153576  F7: 102D 0000

  348 23:53:49.153648  

  349 23:53:49.153708  F1: 0000 0000

  350 23:53:49.157134  

  351 23:53:49.157219  V0: 0000 0000 [0001]

  352 23:53:49.157284  

  353 23:53:49.157344  00: 0007 8000

  354 23:53:49.157407  

  355 23:53:49.161302  01: 0000 0000

  356 23:53:49.161389  

  357 23:53:49.161486  BP: 0C00 0209 [0000]

  358 23:53:49.161547  

  359 23:53:49.164319  G0: 1182 0000

  360 23:53:49.164432  

  361 23:53:49.164556  EC: 0000 0021 [4000]

  362 23:53:49.164675  

  363 23:53:49.168262  S7: 0000 0000 [0000]

  364 23:53:49.168391  

  365 23:53:49.168458  CC: 0000 0000 [0001]

  366 23:53:49.168520  

  367 23:53:49.171301  T0: 0000 0040 [010F]

  368 23:53:49.171383  

  369 23:53:49.171469  Jump to BL

  370 23:53:49.171560  

  371 23:53:49.196739  


  372 23:53:49.196870  

  373 23:53:49.203880  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  374 23:53:49.207425  ARM64: Exception handlers installed.

  375 23:53:49.211290  ARM64: Testing exception

  376 23:53:49.214991  ARM64: Done test exception

  377 23:53:49.222576  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  378 23:53:49.229627  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  379 23:53:49.239309  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  380 23:53:49.249654  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  381 23:53:49.256483  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  382 23:53:49.262816  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  383 23:53:49.273693  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  384 23:53:49.280643  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  385 23:53:49.299692  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  386 23:53:49.302906  WDT: Last reset was cold boot

  387 23:53:49.305827  SPI1(PAD0) initialized at 2873684 Hz

  388 23:53:49.309541  SPI5(PAD0) initialized at 992727 Hz

  389 23:53:49.313134  VBOOT: Loading verstage.

  390 23:53:49.319279  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  391 23:53:49.323665  FMAP: Found "FLASH" version 1.1 at 0x20000.

  392 23:53:49.326883  FMAP: base = 0x0 size = 0x800000 #areas = 25

  393 23:53:49.329998  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  394 23:53:49.336934  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  395 23:53:49.343603  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  396 23:53:49.354364  read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps

  397 23:53:49.354548  

  398 23:53:49.354646  

  399 23:53:49.364780  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  400 23:53:49.368573  ARM64: Exception handlers installed.

  401 23:53:49.371647  ARM64: Testing exception

  402 23:53:49.371764  ARM64: Done test exception

  403 23:53:49.375551  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  404 23:53:49.381644  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  405 23:53:49.395324  Probing TPM: . done!

  406 23:53:49.395467  TPM ready after 0 ms

  407 23:53:49.402168  Connected to device vid:did:rid of 1ae0:0028:00

  408 23:53:49.409312  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  409 23:53:49.468885  Initialized TPM device CR50 revision 0

  410 23:53:49.480202  tlcl_send_startup: Startup return code is 0

  411 23:53:49.480323  TPM: setup succeeded

  412 23:53:49.491520  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  413 23:53:49.500383  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  414 23:53:49.512917  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  415 23:53:49.523002  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  416 23:53:49.526597  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  417 23:53:49.530287  in-header: 03 07 00 00 08 00 00 00 

  418 23:53:49.534418  in-data: aa e4 47 04 13 02 00 00 

  419 23:53:49.534505  Chrome EC: UHEPI supported

  420 23:53:49.541057  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  421 23:53:49.546010  in-header: 03 95 00 00 08 00 00 00 

  422 23:53:49.549836  in-data: 18 20 20 08 00 00 00 00 

  423 23:53:49.549922  Phase 1

  424 23:53:49.556728  FMAP: area GBB found @ 3f5000 (12032 bytes)

  425 23:53:49.560384  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  426 23:53:49.567938  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  427 23:53:49.568058  Recovery requested (1009000e)

  428 23:53:49.579406  TPM: Extending digest for VBOOT: boot mode into PCR 0

  429 23:53:49.584500  tlcl_extend: response is 0

  430 23:53:49.595664  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  431 23:53:49.599257  tlcl_extend: response is 0

  432 23:53:49.606012  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  433 23:53:49.626213  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  434 23:53:49.633023  BS: bootblock times (exec / console): total (unknown) / 149 ms

  435 23:53:49.633177  

  436 23:53:49.633295  

  437 23:53:49.642687  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  438 23:53:49.646237  ARM64: Exception handlers installed.

  439 23:53:49.649256  ARM64: Testing exception

  440 23:53:49.649386  ARM64: Done test exception

  441 23:53:49.671648  pmic_efuse_setting: Set efuses in 11 msecs

  442 23:53:49.674897  pmwrap_interface_init: Select PMIF_VLD_RDY

  443 23:53:49.682013  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  444 23:53:49.685016  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  445 23:53:49.692761  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  446 23:53:49.696413  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  447 23:53:49.700161  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  448 23:53:49.703405  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  449 23:53:49.711111  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  450 23:53:49.714860  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  451 23:53:49.718567  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  452 23:53:49.722504  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  453 23:53:49.730311  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  454 23:53:49.733987  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  455 23:53:49.737904  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  456 23:53:49.745465  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  457 23:53:49.749853  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  458 23:53:49.756434  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  459 23:53:49.760525  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  460 23:53:49.767921  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  461 23:53:49.771517  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  462 23:53:49.779247  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  463 23:53:49.783229  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  464 23:53:49.790718  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  465 23:53:49.794057  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  466 23:53:49.801458  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  467 23:53:49.805482  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  468 23:53:49.813002  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  469 23:53:49.816752  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  470 23:53:49.820139  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  471 23:53:49.827370  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  472 23:53:49.830831  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  473 23:53:49.834675  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  474 23:53:49.842501  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  475 23:53:49.846140  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  476 23:53:49.850080  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  477 23:53:49.857130  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  478 23:53:49.860951  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  479 23:53:49.864541  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  480 23:53:49.872113  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  481 23:53:49.875586  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  482 23:53:49.879432  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  483 23:53:49.883087  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  484 23:53:49.886821  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  485 23:53:49.894000  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  486 23:53:49.898171  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  487 23:53:49.901358  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  488 23:53:49.905236  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  489 23:53:49.909015  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  490 23:53:49.912951  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  491 23:53:49.920109  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  492 23:53:49.924007  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  493 23:53:49.927249  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  494 23:53:49.934964  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  495 23:53:49.942175  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  496 23:53:49.949961  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  497 23:53:49.956686  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  498 23:53:49.964220  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  499 23:53:49.967999  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  500 23:53:49.972379  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  501 23:53:49.979115  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  502 23:53:49.987076  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0

  503 23:53:49.990465  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  504 23:53:49.994027  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  505 23:53:49.997905  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  506 23:53:50.009273  [RTC]rtc_get_frequency_meter,154: input=15, output=758

  507 23:53:50.018928  [RTC]rtc_get_frequency_meter,154: input=23, output=943

  508 23:53:50.028291  [RTC]rtc_get_frequency_meter,154: input=19, output=848

  509 23:53:50.037739  [RTC]rtc_get_frequency_meter,154: input=17, output=805

  510 23:53:50.047001  [RTC]rtc_get_frequency_meter,154: input=16, output=783

  511 23:53:50.057099  [RTC]rtc_get_frequency_meter,154: input=16, output=781

  512 23:53:50.067097  [RTC]rtc_get_frequency_meter,154: input=17, output=806

  513 23:53:50.071434  [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17

  514 23:53:50.074828  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  515 23:53:50.078759  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  516 23:53:50.082266  [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486

  517 23:53:50.090343  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  518 23:53:50.093409  [RTC]rtc_bbpu_power_on,300: done BBPU=0x1

  519 23:53:50.093549  ADC[4]: Raw value=905834 ID=7

  520 23:53:50.096778  ADC[3]: Raw value=213441 ID=1

  521 23:53:50.101030  RAM Code: 0x71

  522 23:53:50.105191  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  523 23:53:50.108506  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  524 23:53:50.115551  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  525 23:53:50.123098  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  526 23:53:50.126585  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  527 23:53:50.130548  in-header: 03 07 00 00 08 00 00 00 

  528 23:53:50.134609  in-data: aa e4 47 04 13 02 00 00 

  529 23:53:50.138246  Chrome EC: UHEPI supported

  530 23:53:50.146062  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  531 23:53:50.149525  in-header: 03 95 00 00 08 00 00 00 

  532 23:53:50.149618  in-data: 18 20 20 08 00 00 00 00 

  533 23:53:50.153018  MRC: failed to locate region type 0.

  534 23:53:50.160161  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  535 23:53:50.164493  DRAM-K: Running full calibration

  536 23:53:50.171860  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  537 23:53:50.171963  header.status = 0x0

  538 23:53:50.175208  header.version = 0x6 (expected: 0x6)

  539 23:53:50.179591  header.size = 0xd00 (expected: 0xd00)

  540 23:53:50.179691  header.flags = 0x0

  541 23:53:50.186536  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  542 23:53:50.204932  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  543 23:53:50.212319  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  544 23:53:50.212449  dram_init: ddr_geometry: 2

  545 23:53:50.216181  [EMI] MDL number = 2

  546 23:53:50.220031  [EMI] Get MDL freq = 0

  547 23:53:50.220115  dram_init: ddr_type: 0

  548 23:53:50.223410  is_discrete_lpddr4: 1

  549 23:53:50.227139  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  550 23:53:50.227225  

  551 23:53:50.227289  

  552 23:53:50.227349  [Bian_co] ETT version 0.0.0.1

  553 23:53:50.231917   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  554 23:53:50.232011  

  555 23:53:50.235611  dramc_set_vcore_voltage set vcore to 650000

  556 23:53:50.238910  Read voltage for 800, 4

  557 23:53:50.238997  Vio18 = 0

  558 23:53:50.243185  Vcore = 650000

  559 23:53:50.243273  Vdram = 0

  560 23:53:50.243339  Vddq = 0

  561 23:53:50.243400  Vmddr = 0

  562 23:53:50.246416  dram_init: config_dvfs: 1

  563 23:53:50.250245  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  564 23:53:50.257758  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  565 23:53:50.261572  [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9

  566 23:53:50.265490  freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9

  567 23:53:50.268469  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  568 23:53:50.272346  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  569 23:53:50.275106  MEM_TYPE=3, freq_sel=18

  570 23:53:50.278655  sv_algorithm_assistance_LP4_1600 

  571 23:53:50.282012  ============ PULL DRAM RESETB DOWN ============

  572 23:53:50.285546  ========== PULL DRAM RESETB DOWN end =========

  573 23:53:50.289204  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  574 23:53:50.293286  =================================== 

  575 23:53:50.296687  LPDDR4 DRAM CONFIGURATION

  576 23:53:50.299853  =================================== 

  577 23:53:50.299979  EX_ROW_EN[0]    = 0x0

  578 23:53:50.303666  EX_ROW_EN[1]    = 0x0

  579 23:53:50.303785  LP4Y_EN      = 0x0

  580 23:53:50.307257  WORK_FSP     = 0x0

  581 23:53:50.307386  WL           = 0x2

  582 23:53:50.310944  RL           = 0x2

  583 23:53:50.311067  BL           = 0x2

  584 23:53:50.313844  RPST         = 0x0

  585 23:53:50.313967  RD_PRE       = 0x0

  586 23:53:50.317624  WR_PRE       = 0x1

  587 23:53:50.317746  WR_PST       = 0x0

  588 23:53:50.321085  DBI_WR       = 0x0

  589 23:53:50.321209  DBI_RD       = 0x0

  590 23:53:50.324055  OTF          = 0x1

  591 23:53:50.327468  =================================== 

  592 23:53:50.331527  =================================== 

  593 23:53:50.331668  ANA top config

  594 23:53:50.335374  =================================== 

  595 23:53:50.338554  DLL_ASYNC_EN            =  0

  596 23:53:50.338639  ALL_SLAVE_EN            =  1

  597 23:53:50.341719  NEW_RANK_MODE           =  1

  598 23:53:50.345607  DLL_IDLE_MODE           =  1

  599 23:53:50.348435  LP45_APHY_COMB_EN       =  1

  600 23:53:50.351944  TX_ODT_DIS              =  1

  601 23:53:50.352029  NEW_8X_MODE             =  1

  602 23:53:50.355607  =================================== 

  603 23:53:50.359494  =================================== 

  604 23:53:50.362624  data_rate                  = 1600

  605 23:53:50.366094  CKR                        = 1

  606 23:53:50.369612  DQ_P2S_RATIO               = 8

  607 23:53:50.372990  =================================== 

  608 23:53:50.373117  CA_P2S_RATIO               = 8

  609 23:53:50.376469  DQ_CA_OPEN                 = 0

  610 23:53:50.379626  DQ_SEMI_OPEN               = 0

  611 23:53:50.382767  CA_SEMI_OPEN               = 0

  612 23:53:50.385995  CA_FULL_RATE               = 0

  613 23:53:50.389905  DQ_CKDIV4_EN               = 1

  614 23:53:50.390032  CA_CKDIV4_EN               = 1

  615 23:53:50.392663  CA_PREDIV_EN               = 0

  616 23:53:50.396223  PH8_DLY                    = 0

  617 23:53:50.399591  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  618 23:53:50.402861  DQ_AAMCK_DIV               = 4

  619 23:53:50.402985  CA_AAMCK_DIV               = 4

  620 23:53:50.406461  CA_ADMCK_DIV               = 4

  621 23:53:50.409773  DQ_TRACK_CA_EN             = 0

  622 23:53:50.412877  CA_PICK                    = 800

  623 23:53:50.416775  CA_MCKIO                   = 800

  624 23:53:50.420663  MCKIO_SEMI                 = 0

  625 23:53:50.420775  PLL_FREQ                   = 3068

  626 23:53:50.424073  DQ_UI_PI_RATIO             = 32

  627 23:53:50.427766  CA_UI_PI_RATIO             = 0

  628 23:53:50.431766  =================================== 

  629 23:53:50.434799  =================================== 

  630 23:53:50.434885  memory_type:LPDDR4         

  631 23:53:50.438248  GP_NUM     : 10       

  632 23:53:50.442188  SRAM_EN    : 1       

  633 23:53:50.442326  MD32_EN    : 0       

  634 23:53:50.445923  =================================== 

  635 23:53:50.449690  [ANA_INIT] >>>>>>>>>>>>>> 

  636 23:53:50.449777  <<<<<< [CONFIGURE PHASE]: ANA_TX

  637 23:53:50.453549  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  638 23:53:50.456810  =================================== 

  639 23:53:50.460268  data_rate = 1600,PCW = 0X7600

  640 23:53:50.463464  =================================== 

  641 23:53:50.466828  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  642 23:53:50.473585  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  643 23:53:50.476970  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  644 23:53:50.483669  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  645 23:53:50.487131  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  646 23:53:50.490072  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  647 23:53:50.490161  [ANA_INIT] flow start 

  648 23:53:50.493814  [ANA_INIT] PLL >>>>>>>> 

  649 23:53:50.496935  [ANA_INIT] PLL <<<<<<<< 

  650 23:53:50.500118  [ANA_INIT] MIDPI >>>>>>>> 

  651 23:53:50.500204  [ANA_INIT] MIDPI <<<<<<<< 

  652 23:53:50.503858  [ANA_INIT] DLL >>>>>>>> 

  653 23:53:50.503943  [ANA_INIT] flow end 

  654 23:53:50.510202  ============ LP4 DIFF to SE enter ============

  655 23:53:50.513911  ============ LP4 DIFF to SE exit  ============

  656 23:53:50.516874  [ANA_INIT] <<<<<<<<<<<<< 

  657 23:53:50.520351  [Flow] Enable top DCM control >>>>> 

  658 23:53:50.523815  [Flow] Enable top DCM control <<<<< 

  659 23:53:50.523901  Enable DLL master slave shuffle 

  660 23:53:50.530623  ============================================================== 

  661 23:53:50.533554  Gating Mode config

  662 23:53:50.536802  ============================================================== 

  663 23:53:50.540359  Config description: 

  664 23:53:50.550527  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  665 23:53:50.557144  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  666 23:53:50.560276  SELPH_MODE            0: By rank         1: By Phase 

  667 23:53:50.566667  ============================================================== 

  668 23:53:50.570070  GAT_TRACK_EN                 =  1

  669 23:53:50.573443  RX_GATING_MODE               =  2

  670 23:53:50.577341  RX_GATING_TRACK_MODE         =  2

  671 23:53:50.577429  SELPH_MODE                   =  1

  672 23:53:50.580419  PICG_EARLY_EN                =  1

  673 23:53:50.583452  VALID_LAT_VALUE              =  1

  674 23:53:50.590423  ============================================================== 

  675 23:53:50.593645  Enter into Gating configuration >>>> 

  676 23:53:50.596881  Exit from Gating configuration <<<< 

  677 23:53:50.600775  Enter into  DVFS_PRE_config >>>>> 

  678 23:53:50.610645  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  679 23:53:50.613835  Exit from  DVFS_PRE_config <<<<< 

  680 23:53:50.617018  Enter into PICG configuration >>>> 

  681 23:53:50.620781  Exit from PICG configuration <<<< 

  682 23:53:50.623634  [RX_INPUT] configuration >>>>> 

  683 23:53:50.626889  [RX_INPUT] configuration <<<<< 

  684 23:53:50.630770  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  685 23:53:50.637118  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  686 23:53:50.643772  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  687 23:53:50.650566  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  688 23:53:50.653572  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  689 23:53:50.660796  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  690 23:53:50.663901  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  691 23:53:50.670891  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  692 23:53:50.673979  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  693 23:53:50.677283  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  694 23:53:50.680687  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  695 23:53:50.687057  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  696 23:53:50.690808  =================================== 

  697 23:53:50.690962  LPDDR4 DRAM CONFIGURATION

  698 23:53:50.693599  =================================== 

  699 23:53:50.697518  EX_ROW_EN[0]    = 0x0

  700 23:53:50.700547  EX_ROW_EN[1]    = 0x0

  701 23:53:50.700657  LP4Y_EN      = 0x0

  702 23:53:50.703695  WORK_FSP     = 0x0

  703 23:53:50.703796  WL           = 0x2

  704 23:53:50.706914  RL           = 0x2

  705 23:53:50.707012  BL           = 0x2

  706 23:53:50.710752  RPST         = 0x0

  707 23:53:50.710838  RD_PRE       = 0x0

  708 23:53:50.714007  WR_PRE       = 0x1

  709 23:53:50.714093  WR_PST       = 0x0

  710 23:53:50.717234  DBI_WR       = 0x0

  711 23:53:50.717327  DBI_RD       = 0x0

  712 23:53:50.720383  OTF          = 0x1

  713 23:53:50.724107  =================================== 

  714 23:53:50.727228  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  715 23:53:50.731136  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  716 23:53:50.734249  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  717 23:53:50.737269  =================================== 

  718 23:53:50.740525  LPDDR4 DRAM CONFIGURATION

  719 23:53:50.744212  =================================== 

  720 23:53:50.747753  EX_ROW_EN[0]    = 0x10

  721 23:53:50.747841  EX_ROW_EN[1]    = 0x0

  722 23:53:50.751034  LP4Y_EN      = 0x0

  723 23:53:50.751121  WORK_FSP     = 0x0

  724 23:53:50.754562  WL           = 0x2

  725 23:53:50.754648  RL           = 0x2

  726 23:53:50.757896  BL           = 0x2

  727 23:53:50.757981  RPST         = 0x0

  728 23:53:50.760551  RD_PRE       = 0x0

  729 23:53:50.760637  WR_PRE       = 0x1

  730 23:53:50.764290  WR_PST       = 0x0

  731 23:53:50.764415  DBI_WR       = 0x0

  732 23:53:50.767373  DBI_RD       = 0x0

  733 23:53:50.771076  OTF          = 0x1

  734 23:53:50.774485  =================================== 

  735 23:53:50.777211  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  736 23:53:50.782654  nWR fixed to 40

  737 23:53:50.786392  [ModeRegInit_LP4] CH0 RK0

  738 23:53:50.786485  [ModeRegInit_LP4] CH0 RK1

  739 23:53:50.789093  [ModeRegInit_LP4] CH1 RK0

  740 23:53:50.792552  [ModeRegInit_LP4] CH1 RK1

  741 23:53:50.792638  match AC timing 13

  742 23:53:50.799603  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  743 23:53:50.802894  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  744 23:53:50.806291  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  745 23:53:50.812496  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  746 23:53:50.816489  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  747 23:53:50.816591  [EMI DOE] emi_dcm 0

  748 23:53:50.823182  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  749 23:53:50.823269  ==

  750 23:53:50.826487  Dram Type= 6, Freq= 0, CH_0, rank 0

  751 23:53:50.829604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  752 23:53:50.829690  ==

  753 23:53:50.835937  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  754 23:53:50.839156  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  755 23:53:50.849724  [CA 0] Center 36 (6~67) winsize 62

  756 23:53:50.853367  [CA 1] Center 36 (6~67) winsize 62

  757 23:53:50.856368  [CA 2] Center 34 (4~65) winsize 62

  758 23:53:50.860381  [CA 3] Center 33 (3~64) winsize 62

  759 23:53:50.863328  [CA 4] Center 33 (3~64) winsize 62

  760 23:53:50.866325  [CA 5] Center 32 (3~62) winsize 60

  761 23:53:50.866451  

  762 23:53:50.870075  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  763 23:53:50.870201  

  764 23:53:50.873379  [CATrainingPosCal] consider 1 rank data

  765 23:53:50.876845  u2DelayCellTimex100 = 270/100 ps

  766 23:53:50.880233  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  767 23:53:50.883383  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  768 23:53:50.890056  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  769 23:53:50.893631  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  770 23:53:50.897004  CA4 delay=33 (3~64),Diff = 1 PI (7 cell)

  771 23:53:50.899899  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  772 23:53:50.900008  

  773 23:53:50.903726  CA PerBit enable=1, Macro0, CA PI delay=32

  774 23:53:50.903811  

  775 23:53:50.906990  [CBTSetCACLKResult] CA Dly = 32

  776 23:53:50.907074  CS Dly: 5 (0~36)

  777 23:53:50.907141  ==

  778 23:53:50.910553  Dram Type= 6, Freq= 0, CH_0, rank 1

  779 23:53:50.916993  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  780 23:53:50.917079  ==

  781 23:53:50.920473  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  782 23:53:50.926835  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  783 23:53:50.936287  [CA 0] Center 36 (6~67) winsize 62

  784 23:53:50.939562  [CA 1] Center 36 (6~67) winsize 62

  785 23:53:50.942811  [CA 2] Center 34 (4~64) winsize 61

  786 23:53:50.946479  [CA 3] Center 33 (3~64) winsize 62

  787 23:53:50.949622  [CA 4] Center 32 (2~63) winsize 62

  788 23:53:50.952619  [CA 5] Center 32 (2~63) winsize 62

  789 23:53:50.952704  

  790 23:53:50.956697  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  791 23:53:50.956782  

  792 23:53:50.959544  [CATrainingPosCal] consider 2 rank data

  793 23:53:50.963069  u2DelayCellTimex100 = 270/100 ps

  794 23:53:50.966268  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  795 23:53:50.969552  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  796 23:53:50.976646  CA2 delay=34 (4~64),Diff = 2 PI (14 cell)

  797 23:53:50.979772  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  798 23:53:50.983469  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  799 23:53:50.986368  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  800 23:53:50.986457  

  801 23:53:50.990004  CA PerBit enable=1, Macro0, CA PI delay=32

  802 23:53:50.990090  

  803 23:53:50.993198  [CBTSetCACLKResult] CA Dly = 32

  804 23:53:50.993283  CS Dly: 5 (0~37)

  805 23:53:50.993349  

  806 23:53:50.997033  ----->DramcWriteLeveling(PI) begin...

  807 23:53:50.997120  ==

  808 23:53:51.000572  Dram Type= 6, Freq= 0, CH_0, rank 0

  809 23:53:51.004183  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  810 23:53:51.004315  ==

  811 23:53:51.007647  Write leveling (Byte 0): 33 => 33

  812 23:53:51.012091  Write leveling (Byte 1): 30 => 30

  813 23:53:51.015318  DramcWriteLeveling(PI) end<-----

  814 23:53:51.015407  

  815 23:53:51.015473  ==

  816 23:53:51.018376  Dram Type= 6, Freq= 0, CH_0, rank 0

  817 23:53:51.022151  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  818 23:53:51.022239  ==

  819 23:53:51.025858  [Gating] SW mode calibration

  820 23:53:51.032563  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  821 23:53:51.036477  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  822 23:53:51.042903   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  823 23:53:51.046045   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  824 23:53:51.049787   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  825 23:53:51.055945   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 23:53:51.059605   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 23:53:51.062836   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  828 23:53:51.069473   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  829 23:53:51.072765   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  830 23:53:51.075618   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  831 23:53:51.082941   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  832 23:53:51.086016   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  833 23:53:51.089400   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  834 23:53:51.095940   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  835 23:53:51.099759   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  836 23:53:51.103172   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  837 23:53:51.109197   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  838 23:53:51.112907   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  839 23:53:51.115789   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

  840 23:53:51.119608   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

  841 23:53:51.125986   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  842 23:53:51.129325   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  843 23:53:51.132942   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  844 23:53:51.139174   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  845 23:53:51.142345   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  846 23:53:51.146270   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  847 23:53:51.152915   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  848 23:53:51.156235   0  9  8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)

  849 23:53:51.159652   0  9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

  850 23:53:51.165984   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  851 23:53:51.169430   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  852 23:53:51.173028   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  853 23:53:51.179199   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  854 23:53:51.182996   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  855 23:53:51.185956   0 10  4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)

  856 23:53:51.193194   0 10  8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)

  857 23:53:51.196030   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  858 23:53:51.199431   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  859 23:53:51.206120   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 23:53:51.209734   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 23:53:51.212929   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  862 23:53:51.216683   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  863 23:53:51.223530   0 11  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

  864 23:53:51.226354   0 11  8 | B1->B0 | 2c2c 3b3b | 0 0 | (0 0) (1 1)

  865 23:53:51.229478   0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)

  866 23:53:51.236328   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  867 23:53:51.239792   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  868 23:53:51.242978   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  869 23:53:51.249949   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  870 23:53:51.253091   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  871 23:53:51.256277   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  872 23:53:51.263201   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  873 23:53:51.266198   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  874 23:53:51.269600   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  875 23:53:51.276215   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  876 23:53:51.279561   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  877 23:53:51.282946   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  878 23:53:51.289889   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  879 23:53:51.293110   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  880 23:53:51.296238   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  881 23:53:51.300035   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  882 23:53:51.306527   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  883 23:53:51.309701   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  884 23:53:51.313191   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  885 23:53:51.320199   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  886 23:53:51.323091   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  887 23:53:51.326994   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  888 23:53:51.333421   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  889 23:53:51.333541  Total UI for P1: 0, mck2ui 16

  890 23:53:51.340308  best dqsien dly found for B0: ( 0, 14,  4)

  891 23:53:51.343358   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  892 23:53:51.346406  Total UI for P1: 0, mck2ui 16

  893 23:53:51.350142  best dqsien dly found for B1: ( 0, 14,  8)

  894 23:53:51.353290  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

  895 23:53:51.356976  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  896 23:53:51.357064  

  897 23:53:51.360922  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

  898 23:53:51.363937  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  899 23:53:51.367153  [Gating] SW calibration Done

  900 23:53:51.367239  ==

  901 23:53:51.370795  Dram Type= 6, Freq= 0, CH_0, rank 0

  902 23:53:51.373846  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  903 23:53:51.373932  ==

  904 23:53:51.376856  RX Vref Scan: 0

  905 23:53:51.376940  

  906 23:53:51.377006  RX Vref 0 -> 0, step: 1

  907 23:53:51.377068  

  908 23:53:51.380827  RX Delay -130 -> 252, step: 16

  909 23:53:51.384051  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

  910 23:53:51.390334  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  911 23:53:51.394468  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  912 23:53:51.397186  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  913 23:53:51.400741  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

  914 23:53:51.404256  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  915 23:53:51.410803  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

  916 23:53:51.413874  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  917 23:53:51.417623  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

  918 23:53:51.420556  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

  919 23:53:51.424302  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

  920 23:53:51.431200  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  921 23:53:51.434334  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

  922 23:53:51.437383  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

  923 23:53:51.441101  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

  924 23:53:51.444248  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

  925 23:53:51.444358  ==

  926 23:53:51.447893  Dram Type= 6, Freq= 0, CH_0, rank 0

  927 23:53:51.454113  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  928 23:53:51.454208  ==

  929 23:53:51.454275  DQS Delay:

  930 23:53:51.457348  DQS0 = 0, DQS1 = 0

  931 23:53:51.457478  DQM Delay:

  932 23:53:51.457593  DQM0 = 91, DQM1 = 85

  933 23:53:51.460781  DQ Delay:

  934 23:53:51.464362  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

  935 23:53:51.467658  DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101

  936 23:53:51.471325  DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77

  937 23:53:51.474439  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

  938 23:53:51.474571  

  939 23:53:51.474688  

  940 23:53:51.474797  ==

  941 23:53:51.478072  Dram Type= 6, Freq= 0, CH_0, rank 0

  942 23:53:51.481307  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  943 23:53:51.481433  ==

  944 23:53:51.481548  

  945 23:53:51.481660  

  946 23:53:51.484330  	TX Vref Scan disable

  947 23:53:51.484491   == TX Byte 0 ==

  948 23:53:51.491218  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  949 23:53:51.494333  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  950 23:53:51.494457   == TX Byte 1 ==

  951 23:53:51.501350  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  952 23:53:51.504559  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  953 23:53:51.504685  ==

  954 23:53:51.507891  Dram Type= 6, Freq= 0, CH_0, rank 0

  955 23:53:51.511247  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  956 23:53:51.511375  ==

  957 23:53:51.525582  TX Vref=22, minBit 8, minWin=27, winSum=442

  958 23:53:51.528840  TX Vref=24, minBit 8, minWin=27, winSum=452

  959 23:53:51.532107  TX Vref=26, minBit 8, minWin=27, winSum=457

  960 23:53:51.535304  TX Vref=28, minBit 0, minWin=28, winSum=457

  961 23:53:51.538989  TX Vref=30, minBit 5, minWin=28, winSum=456

  962 23:53:51.545206  TX Vref=32, minBit 5, minWin=28, winSum=456

  963 23:53:51.548826  [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28

  964 23:53:51.548959  

  965 23:53:51.551724  Final TX Range 1 Vref 28

  966 23:53:51.551848  

  967 23:53:51.551959  ==

  968 23:53:51.555475  Dram Type= 6, Freq= 0, CH_0, rank 0

  969 23:53:51.558684  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  970 23:53:51.558811  ==

  971 23:53:51.558926  

  972 23:53:51.561832  

  973 23:53:51.561958  	TX Vref Scan disable

  974 23:53:51.565783   == TX Byte 0 ==

  975 23:53:51.568910  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

  976 23:53:51.571952  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

  977 23:53:51.575354   == TX Byte 1 ==

  978 23:53:51.578974  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  979 23:53:51.582088  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  980 23:53:51.585766  

  981 23:53:51.585876  [DATLAT]

  982 23:53:51.585972  Freq=800, CH0 RK0

  983 23:53:51.586065  

  984 23:53:51.589024  DATLAT Default: 0xa

  985 23:53:51.589131  0, 0xFFFF, sum = 0

  986 23:53:51.592008  1, 0xFFFF, sum = 0

  987 23:53:51.592120  2, 0xFFFF, sum = 0

  988 23:53:51.595655  3, 0xFFFF, sum = 0

  989 23:53:51.595765  4, 0xFFFF, sum = 0

  990 23:53:51.598728  5, 0xFFFF, sum = 0

  991 23:53:51.598837  6, 0xFFFF, sum = 0

  992 23:53:51.602383  7, 0xFFFF, sum = 0

  993 23:53:51.605630  8, 0xFFFF, sum = 0

  994 23:53:51.605741  9, 0x0, sum = 1

  995 23:53:51.605836  10, 0x0, sum = 2

  996 23:53:51.608779  11, 0x0, sum = 3

  997 23:53:51.608887  12, 0x0, sum = 4

  998 23:53:51.612031  best_step = 10

  999 23:53:51.612137  

 1000 23:53:51.612231  ==

 1001 23:53:51.615706  Dram Type= 6, Freq= 0, CH_0, rank 0

 1002 23:53:51.618629  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1003 23:53:51.618738  ==

 1004 23:53:51.621938  RX Vref Scan: 1

 1005 23:53:51.622051  

 1006 23:53:51.622146  Set Vref Range= 32 -> 127

 1007 23:53:51.622282  

 1008 23:53:51.625302  RX Vref 32 -> 127, step: 1

 1009 23:53:51.625410  

 1010 23:53:51.628646  RX Delay -95 -> 252, step: 8

 1011 23:53:51.628755  

 1012 23:53:51.632170  Set Vref, RX VrefLevel [Byte0]: 32

 1013 23:53:51.635577                           [Byte1]: 32

 1014 23:53:51.635687  

 1015 23:53:51.639012  Set Vref, RX VrefLevel [Byte0]: 33

 1016 23:53:51.642063                           [Byte1]: 33

 1017 23:53:51.645652  

 1018 23:53:51.645779  Set Vref, RX VrefLevel [Byte0]: 34

 1019 23:53:51.649200                           [Byte1]: 34

 1020 23:53:51.653125  

 1021 23:53:51.653246  Set Vref, RX VrefLevel [Byte0]: 35

 1022 23:53:51.656748                           [Byte1]: 35

 1023 23:53:51.661044  

 1024 23:53:51.661171  Set Vref, RX VrefLevel [Byte0]: 36

 1025 23:53:51.664591                           [Byte1]: 36

 1026 23:53:51.668953  

 1027 23:53:51.669078  Set Vref, RX VrefLevel [Byte0]: 37

 1028 23:53:51.672150                           [Byte1]: 37

 1029 23:53:51.676769  

 1030 23:53:51.676861  Set Vref, RX VrefLevel [Byte0]: 38

 1031 23:53:51.679760                           [Byte1]: 38

 1032 23:53:51.684078  

 1033 23:53:51.684191  Set Vref, RX VrefLevel [Byte0]: 39

 1034 23:53:51.687307                           [Byte1]: 39

 1035 23:53:51.691707  

 1036 23:53:51.691794  Set Vref, RX VrefLevel [Byte0]: 40

 1037 23:53:51.694900                           [Byte1]: 40

 1038 23:53:51.699142  

 1039 23:53:51.699234  Set Vref, RX VrefLevel [Byte0]: 41

 1040 23:53:51.702486                           [Byte1]: 41

 1041 23:53:51.706831  

 1042 23:53:51.706917  Set Vref, RX VrefLevel [Byte0]: 42

 1043 23:53:51.710051                           [Byte1]: 42

 1044 23:53:51.714410  

 1045 23:53:51.714493  Set Vref, RX VrefLevel [Byte0]: 43

 1046 23:53:51.717449                           [Byte1]: 43

 1047 23:53:51.721445  

 1048 23:53:51.721528  Set Vref, RX VrefLevel [Byte0]: 44

 1049 23:53:51.725166                           [Byte1]: 44

 1050 23:53:51.729297  

 1051 23:53:51.729389  Set Vref, RX VrefLevel [Byte0]: 45

 1052 23:53:51.733059                           [Byte1]: 45

 1053 23:53:51.736679  

 1054 23:53:51.736761  Set Vref, RX VrefLevel [Byte0]: 46

 1055 23:53:51.740647                           [Byte1]: 46

 1056 23:53:51.744691  

 1057 23:53:51.744773  Set Vref, RX VrefLevel [Byte0]: 47

 1058 23:53:51.747778                           [Byte1]: 47

 1059 23:53:51.752463  

 1060 23:53:51.752570  Set Vref, RX VrefLevel [Byte0]: 48

 1061 23:53:51.755402                           [Byte1]: 48

 1062 23:53:51.759710  

 1063 23:53:51.759793  Set Vref, RX VrefLevel [Byte0]: 49

 1064 23:53:51.762983                           [Byte1]: 49

 1065 23:53:51.767378  

 1066 23:53:51.767460  Set Vref, RX VrefLevel [Byte0]: 50

 1067 23:53:51.770465                           [Byte1]: 50

 1068 23:53:51.774906  

 1069 23:53:51.774993  Set Vref, RX VrefLevel [Byte0]: 51

 1070 23:53:51.778407                           [Byte1]: 51

 1071 23:53:51.782505  

 1072 23:53:51.782590  Set Vref, RX VrefLevel [Byte0]: 52

 1073 23:53:51.785661                           [Byte1]: 52

 1074 23:53:51.789986  

 1075 23:53:51.790069  Set Vref, RX VrefLevel [Byte0]: 53

 1076 23:53:51.793196                           [Byte1]: 53

 1077 23:53:51.797442  

 1078 23:53:51.797526  Set Vref, RX VrefLevel [Byte0]: 54

 1079 23:53:51.801074                           [Byte1]: 54

 1080 23:53:51.805275  

 1081 23:53:51.805359  Set Vref, RX VrefLevel [Byte0]: 55

 1082 23:53:51.808355                           [Byte1]: 55

 1083 23:53:51.812816  

 1084 23:53:51.812898  Set Vref, RX VrefLevel [Byte0]: 56

 1085 23:53:51.816168                           [Byte1]: 56

 1086 23:53:51.820488  

 1087 23:53:51.820570  Set Vref, RX VrefLevel [Byte0]: 57

 1088 23:53:51.823607                           [Byte1]: 57

 1089 23:53:51.828040  

 1090 23:53:51.828122  Set Vref, RX VrefLevel [Byte0]: 58

 1091 23:53:51.831633                           [Byte1]: 58

 1092 23:53:51.835672  

 1093 23:53:51.835755  Set Vref, RX VrefLevel [Byte0]: 59

 1094 23:53:51.838791                           [Byte1]: 59

 1095 23:53:51.843237  

 1096 23:53:51.843321  Set Vref, RX VrefLevel [Byte0]: 60

 1097 23:53:51.846452                           [Byte1]: 60

 1098 23:53:51.850696  

 1099 23:53:51.850795  Set Vref, RX VrefLevel [Byte0]: 61

 1100 23:53:51.854210                           [Byte1]: 61

 1101 23:53:51.858417  

 1102 23:53:51.858502  Set Vref, RX VrefLevel [Byte0]: 62

 1103 23:53:51.861743                           [Byte1]: 62

 1104 23:53:51.865845  

 1105 23:53:51.865930  Set Vref, RX VrefLevel [Byte0]: 63

 1106 23:53:51.869642                           [Byte1]: 63

 1107 23:53:51.873557  

 1108 23:53:51.873642  Set Vref, RX VrefLevel [Byte0]: 64

 1109 23:53:51.877263                           [Byte1]: 64

 1110 23:53:51.881505  

 1111 23:53:51.881594  Set Vref, RX VrefLevel [Byte0]: 65

 1112 23:53:51.884938                           [Byte1]: 65

 1113 23:53:51.889260  

 1114 23:53:51.889342  Set Vref, RX VrefLevel [Byte0]: 66

 1115 23:53:51.892084                           [Byte1]: 66

 1116 23:53:51.896278  

 1117 23:53:51.896424  Set Vref, RX VrefLevel [Byte0]: 67

 1118 23:53:51.899969                           [Byte1]: 67

 1119 23:53:51.904271  

 1120 23:53:51.904404  Set Vref, RX VrefLevel [Byte0]: 68

 1121 23:53:51.907451                           [Byte1]: 68

 1122 23:53:51.912156  

 1123 23:53:51.912278  Set Vref, RX VrefLevel [Byte0]: 69

 1124 23:53:51.915097                           [Byte1]: 69

 1125 23:53:51.919135  

 1126 23:53:51.919258  Set Vref, RX VrefLevel [Byte0]: 70

 1127 23:53:51.922667                           [Byte1]: 70

 1128 23:53:51.927054  

 1129 23:53:51.927174  Set Vref, RX VrefLevel [Byte0]: 71

 1130 23:53:51.930443                           [Byte1]: 71

 1131 23:53:51.934780  

 1132 23:53:51.934904  Set Vref, RX VrefLevel [Byte0]: 72

 1133 23:53:51.937908                           [Byte1]: 72

 1134 23:53:51.942036  

 1135 23:53:51.942161  Set Vref, RX VrefLevel [Byte0]: 73

 1136 23:53:51.945545                           [Byte1]: 73

 1137 23:53:51.949789  

 1138 23:53:51.949910  Set Vref, RX VrefLevel [Byte0]: 74

 1139 23:53:51.952931                           [Byte1]: 74

 1140 23:53:51.957141  

 1141 23:53:51.957267  Set Vref, RX VrefLevel [Byte0]: 75

 1142 23:53:51.960765                           [Byte1]: 75

 1143 23:53:51.964827  

 1144 23:53:51.964950  Set Vref, RX VrefLevel [Byte0]: 76

 1145 23:53:51.968113                           [Byte1]: 76

 1146 23:53:51.972280  

 1147 23:53:51.972408  Set Vref, RX VrefLevel [Byte0]: 77

 1148 23:53:51.976272                           [Byte1]: 77

 1149 23:53:51.979938  

 1150 23:53:51.980056  Final RX Vref Byte 0 = 58 to rank0

 1151 23:53:51.983406  Final RX Vref Byte 1 = 55 to rank0

 1152 23:53:51.986931  Final RX Vref Byte 0 = 58 to rank1

 1153 23:53:51.990170  Final RX Vref Byte 1 = 55 to rank1==

 1154 23:53:51.993382  Dram Type= 6, Freq= 0, CH_0, rank 0

 1155 23:53:51.997184  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1156 23:53:52.000157  ==

 1157 23:53:52.000276  DQS Delay:

 1158 23:53:52.000403  DQS0 = 0, DQS1 = 0

 1159 23:53:52.003595  DQM Delay:

 1160 23:53:52.003720  DQM0 = 92, DQM1 = 84

 1161 23:53:52.006817  DQ Delay:

 1162 23:53:52.010302  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88

 1163 23:53:52.010426  DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100

 1164 23:53:52.013524  DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =80

 1165 23:53:52.020012  DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92

 1166 23:53:52.020141  

 1167 23:53:52.020252  

 1168 23:53:52.026578  [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 1169 23:53:52.030044  CH0 RK0: MR19=606, MR18=4B42

 1170 23:53:52.036459  CH0_RK0: MR19=0x606, MR18=0x4B42, DQSOSC=391, MR23=63, INC=96, DEC=64

 1171 23:53:52.036582  

 1172 23:53:52.040347  ----->DramcWriteLeveling(PI) begin...

 1173 23:53:52.040438  ==

 1174 23:53:52.043485  Dram Type= 6, Freq= 0, CH_0, rank 1

 1175 23:53:52.046838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1176 23:53:52.046941  ==

 1177 23:53:52.049741  Write leveling (Byte 0): 33 => 33

 1178 23:53:52.053146  Write leveling (Byte 1): 31 => 31

 1179 23:53:52.056821  DramcWriteLeveling(PI) end<-----

 1180 23:53:52.056928  

 1181 23:53:52.056995  ==

 1182 23:53:52.059972  Dram Type= 6, Freq= 0, CH_0, rank 1

 1183 23:53:52.063189  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1184 23:53:52.063298  ==

 1185 23:53:52.066828  [Gating] SW mode calibration

 1186 23:53:52.113839  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1187 23:53:52.114255  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1188 23:53:52.114352   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1189 23:53:52.114430   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1190 23:53:52.114521   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1191 23:53:52.114889   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1192 23:53:52.115198   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1193 23:53:52.115484   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1194 23:53:52.115569   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1195 23:53:52.115661   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1196 23:53:52.132226   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1197 23:53:52.132616   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1198 23:53:52.132695   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1199 23:53:52.132760   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1200 23:53:52.135632   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1201 23:53:52.142379   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1202 23:53:52.145586   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1203 23:53:52.148821   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1204 23:53:52.152526   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1205 23:53:52.159254   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1206 23:53:52.162478   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1207 23:53:52.165656   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1208 23:53:52.172416   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1209 23:53:52.175557   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1210 23:53:52.179186   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1211 23:53:52.185673   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1212 23:53:52.188833   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1213 23:53:52.192604   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1214 23:53:52.199425   0  9  8 | B1->B0 | 2c2c 2929 | 0 1 | (0 0) (1 1)

 1215 23:53:52.202316   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1216 23:53:52.205532   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1217 23:53:52.212441   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1218 23:53:52.215923   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1219 23:53:52.218967   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1220 23:53:52.225931   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1221 23:53:52.229160   0 10  4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 1222 23:53:52.232444   0 10  8 | B1->B0 | 2828 2828 | 1 0 | (1 1) (1 0)

 1223 23:53:52.236359   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1224 23:53:52.243101   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1225 23:53:52.246269   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1226 23:53:52.250297   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1227 23:53:52.254432   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1228 23:53:52.258299   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1229 23:53:52.264818   0 11  4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 1230 23:53:52.268148   0 11  8 | B1->B0 | 3939 3737 | 1 1 | (0 0) (0 0)

 1231 23:53:52.271586   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1232 23:53:52.275543   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1233 23:53:52.282565   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1234 23:53:52.285733   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1235 23:53:52.289010   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1236 23:53:52.295616   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1237 23:53:52.299070   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1238 23:53:52.302195   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1239 23:53:52.309202   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1240 23:53:52.312209   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1241 23:53:52.316218   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1242 23:53:52.322236   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1243 23:53:52.325919   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1244 23:53:52.328955   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1245 23:53:52.336098   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1246 23:53:52.338964   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1247 23:53:52.342660   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1248 23:53:52.345914   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1249 23:53:52.352531   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1250 23:53:52.355726   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1251 23:53:52.358772   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1252 23:53:52.365928   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1253 23:53:52.368928   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1254 23:53:52.372613   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1255 23:53:52.375600  Total UI for P1: 0, mck2ui 16

 1256 23:53:52.378978  best dqsien dly found for B1: ( 0, 14,  6)

 1257 23:53:52.385730   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1258 23:53:52.385869  Total UI for P1: 0, mck2ui 16

 1259 23:53:52.392090  best dqsien dly found for B0: ( 0, 14,  8)

 1260 23:53:52.395727  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1261 23:53:52.399147  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1262 23:53:52.399236  

 1263 23:53:52.402746  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1264 23:53:52.405604  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1265 23:53:52.409332  [Gating] SW calibration Done

 1266 23:53:52.409416  ==

 1267 23:53:52.412489  Dram Type= 6, Freq= 0, CH_0, rank 1

 1268 23:53:52.415607  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1269 23:53:52.415696  ==

 1270 23:53:52.419370  RX Vref Scan: 0

 1271 23:53:52.419455  

 1272 23:53:52.419518  RX Vref 0 -> 0, step: 1

 1273 23:53:52.419578  

 1274 23:53:52.422692  RX Delay -130 -> 252, step: 16

 1275 23:53:52.425633  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1276 23:53:52.432281  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1277 23:53:52.436051  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1278 23:53:52.439242  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1279 23:53:52.442360  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1280 23:53:52.445567  iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240

 1281 23:53:52.449310  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1282 23:53:52.455594  iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224

 1283 23:53:52.459391  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1284 23:53:52.462655  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1285 23:53:52.465852  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

 1286 23:53:52.472491  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1287 23:53:52.475630  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1288 23:53:52.479396  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1289 23:53:52.482152  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1290 23:53:52.485709  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1291 23:53:52.488638  ==

 1292 23:53:52.488722  Dram Type= 6, Freq= 0, CH_0, rank 1

 1293 23:53:52.495703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1294 23:53:52.495793  ==

 1295 23:53:52.495859  DQS Delay:

 1296 23:53:52.499130  DQS0 = 0, DQS1 = 0

 1297 23:53:52.499224  DQM Delay:

 1298 23:53:52.499323  DQM0 = 93, DQM1 = 80

 1299 23:53:52.502585  DQ Delay:

 1300 23:53:52.505577  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

 1301 23:53:52.509202  DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109

 1302 23:53:52.512306  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77

 1303 23:53:52.516085  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85

 1304 23:53:52.516170  

 1305 23:53:52.516234  

 1306 23:53:52.516293  ==

 1307 23:53:52.519030  Dram Type= 6, Freq= 0, CH_0, rank 1

 1308 23:53:52.522476  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1309 23:53:52.522559  ==

 1310 23:53:52.522624  

 1311 23:53:52.522682  

 1312 23:53:52.525673  	TX Vref Scan disable

 1313 23:53:52.525756   == TX Byte 0 ==

 1314 23:53:52.533159  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1315 23:53:52.535886  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1316 23:53:52.535970   == TX Byte 1 ==

 1317 23:53:52.542622  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1318 23:53:52.546190  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1319 23:53:52.546275  ==

 1320 23:53:52.549330  Dram Type= 6, Freq= 0, CH_0, rank 1

 1321 23:53:52.552479  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1322 23:53:52.552562  ==

 1323 23:53:52.567090  TX Vref=22, minBit 8, minWin=27, winSum=448

 1324 23:53:52.570316  TX Vref=24, minBit 10, minWin=27, winSum=452

 1325 23:53:52.573417  TX Vref=26, minBit 12, minWin=27, winSum=455

 1326 23:53:52.576636  TX Vref=28, minBit 1, minWin=28, winSum=454

 1327 23:53:52.580584  TX Vref=30, minBit 1, minWin=28, winSum=456

 1328 23:53:52.586705  TX Vref=32, minBit 0, minWin=28, winSum=454

 1329 23:53:52.589943  [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 30

 1330 23:53:52.590031  

 1331 23:53:52.593791  Final TX Range 1 Vref 30

 1332 23:53:52.593880  

 1333 23:53:52.593944  ==

 1334 23:53:52.597396  Dram Type= 6, Freq= 0, CH_0, rank 1

 1335 23:53:52.600657  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1336 23:53:52.600756  ==

 1337 23:53:52.600820  

 1338 23:53:52.600878  

 1339 23:53:52.603639  	TX Vref Scan disable

 1340 23:53:52.607119   == TX Byte 0 ==

 1341 23:53:52.610821  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1342 23:53:52.613960  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1343 23:53:52.617110   == TX Byte 1 ==

 1344 23:53:52.620869  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1345 23:53:52.624094  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1346 23:53:52.624177  

 1347 23:53:52.627019  [DATLAT]

 1348 23:53:52.627100  Freq=800, CH0 RK1

 1349 23:53:52.627164  

 1350 23:53:52.630322  DATLAT Default: 0xa

 1351 23:53:52.630403  0, 0xFFFF, sum = 0

 1352 23:53:52.634237  1, 0xFFFF, sum = 0

 1353 23:53:52.634350  2, 0xFFFF, sum = 0

 1354 23:53:52.637398  3, 0xFFFF, sum = 0

 1355 23:53:52.637481  4, 0xFFFF, sum = 0

 1356 23:53:52.640785  5, 0xFFFF, sum = 0

 1357 23:53:52.640868  6, 0xFFFF, sum = 0

 1358 23:53:52.644194  7, 0xFFFF, sum = 0

 1359 23:53:52.644305  8, 0xFFFF, sum = 0

 1360 23:53:52.647345  9, 0x0, sum = 1

 1361 23:53:52.647419  10, 0x0, sum = 2

 1362 23:53:52.650475  11, 0x0, sum = 3

 1363 23:53:52.650560  12, 0x0, sum = 4

 1364 23:53:52.654034  best_step = 10

 1365 23:53:52.654115  

 1366 23:53:52.654178  ==

 1367 23:53:52.657461  Dram Type= 6, Freq= 0, CH_0, rank 1

 1368 23:53:52.660883  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1369 23:53:52.660966  ==

 1370 23:53:52.663839  RX Vref Scan: 0

 1371 23:53:52.663923  

 1372 23:53:52.663986  RX Vref 0 -> 0, step: 1

 1373 23:53:52.664046  

 1374 23:53:52.667507  RX Delay -95 -> 252, step: 8

 1375 23:53:52.673725  iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216

 1376 23:53:52.677491  iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208

 1377 23:53:52.680833  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1378 23:53:52.683966  iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224

 1379 23:53:52.687127  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 1380 23:53:52.690508  iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224

 1381 23:53:52.697260  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1382 23:53:52.700937  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1383 23:53:52.703872  iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216

 1384 23:53:52.707077  iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216

 1385 23:53:52.710895  iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216

 1386 23:53:52.717424  iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216

 1387 23:53:52.720360  iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208

 1388 23:53:52.724040  iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208

 1389 23:53:52.727784  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1390 23:53:52.730923  iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216

 1391 23:53:52.733939  ==

 1392 23:53:52.737762  Dram Type= 6, Freq= 0, CH_0, rank 1

 1393 23:53:52.740948  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1394 23:53:52.741029  ==

 1395 23:53:52.741092  DQS Delay:

 1396 23:53:52.744053  DQS0 = 0, DQS1 = 0

 1397 23:53:52.744159  DQM Delay:

 1398 23:53:52.747179  DQM0 = 93, DQM1 = 84

 1399 23:53:52.747260  DQ Delay:

 1400 23:53:52.751049  DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88

 1401 23:53:52.754197  DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100

 1402 23:53:52.757474  DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76

 1403 23:53:52.761044  DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92

 1404 23:53:52.761125  

 1405 23:53:52.761188  

 1406 23:53:52.767805  [DQSOSCAuto] RK1, (LSB)MR18= 0x4718, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps

 1407 23:53:52.770777  CH0 RK1: MR19=606, MR18=4718

 1408 23:53:52.777429  CH0_RK1: MR19=0x606, MR18=0x4718, DQSOSC=392, MR23=63, INC=96, DEC=64

 1409 23:53:52.780827  [RxdqsGatingPostProcess] freq 800

 1410 23:53:52.784317  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1411 23:53:52.787411  Pre-setting of DQS Precalculation

 1412 23:53:52.794205  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1413 23:53:52.794289  ==

 1414 23:53:52.797500  Dram Type= 6, Freq= 0, CH_1, rank 0

 1415 23:53:52.801178  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1416 23:53:52.801259  ==

 1417 23:53:52.807403  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1418 23:53:52.814001  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1419 23:53:52.821931  [CA 0] Center 36 (6~67) winsize 62

 1420 23:53:52.825340  [CA 1] Center 36 (6~67) winsize 62

 1421 23:53:52.829091  [CA 2] Center 34 (4~65) winsize 62

 1422 23:53:52.831989  [CA 3] Center 34 (4~65) winsize 62

 1423 23:53:52.835682  [CA 4] Center 34 (4~65) winsize 62

 1424 23:53:52.838663  [CA 5] Center 34 (4~65) winsize 62

 1425 23:53:52.838785  

 1426 23:53:52.842120  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1427 23:53:52.842242  

 1428 23:53:52.845041  [CATrainingPosCal] consider 1 rank data

 1429 23:53:52.849120  u2DelayCellTimex100 = 270/100 ps

 1430 23:53:52.852148  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1431 23:53:52.855314  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1432 23:53:52.862243  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 1433 23:53:52.865474  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1434 23:53:52.868629  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1435 23:53:52.871849  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 1436 23:53:52.871971  

 1437 23:53:52.875057  CA PerBit enable=1, Macro0, CA PI delay=34

 1438 23:53:52.875177  

 1439 23:53:52.879051  [CBTSetCACLKResult] CA Dly = 34

 1440 23:53:52.879189  CS Dly: 5 (0~36)

 1441 23:53:52.879330  ==

 1442 23:53:52.882042  Dram Type= 6, Freq= 0, CH_1, rank 1

 1443 23:53:52.889123  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1444 23:53:52.889246  ==

 1445 23:53:52.892150  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1446 23:53:52.898926  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1447 23:53:52.908554  [CA 0] Center 36 (6~67) winsize 62

 1448 23:53:52.912695  [CA 1] Center 37 (6~68) winsize 63

 1449 23:53:52.916263  [CA 2] Center 35 (5~66) winsize 62

 1450 23:53:52.919952  [CA 3] Center 34 (4~65) winsize 62

 1451 23:53:52.924091  [CA 4] Center 35 (5~66) winsize 62

 1452 23:53:52.924269  [CA 5] Center 34 (4~65) winsize 62

 1453 23:53:52.924387  

 1454 23:53:52.928077  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1455 23:53:52.928239  

 1456 23:53:52.932042  [CATrainingPosCal] consider 2 rank data

 1457 23:53:52.935411  u2DelayCellTimex100 = 270/100 ps

 1458 23:53:52.939034  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1459 23:53:52.943082  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1460 23:53:52.946201  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1461 23:53:52.949705  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1462 23:53:52.952790  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1463 23:53:52.956534  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 1464 23:53:52.956619  

 1465 23:53:52.959883  CA PerBit enable=1, Macro0, CA PI delay=34

 1466 23:53:52.962895  

 1467 23:53:52.962975  [CBTSetCACLKResult] CA Dly = 34

 1468 23:53:52.966085  CS Dly: 6 (0~38)

 1469 23:53:52.966169  

 1470 23:53:52.969983  ----->DramcWriteLeveling(PI) begin...

 1471 23:53:52.970069  ==

 1472 23:53:52.972979  Dram Type= 6, Freq= 0, CH_1, rank 0

 1473 23:53:52.976150  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1474 23:53:52.976236  ==

 1475 23:53:52.980013  Write leveling (Byte 0): 26 => 26

 1476 23:53:52.983157  Write leveling (Byte 1): 29 => 29

 1477 23:53:52.986294  DramcWriteLeveling(PI) end<-----

 1478 23:53:52.986378  

 1479 23:53:52.986461  ==

 1480 23:53:52.990102  Dram Type= 6, Freq= 0, CH_1, rank 0

 1481 23:53:52.993283  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1482 23:53:52.993368  ==

 1483 23:53:52.996249  [Gating] SW mode calibration

 1484 23:53:53.003366  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1485 23:53:53.009620  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1486 23:53:53.013330   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1487 23:53:53.016549   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1488 23:53:53.023243   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1489 23:53:53.026303   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1490 23:53:53.029997   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1491 23:53:53.036433   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1492 23:53:53.040031   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1493 23:53:53.043400   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1494 23:53:53.049852   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1495 23:53:53.053495   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1496 23:53:53.056627   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1497 23:53:53.062970   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1498 23:53:53.066686   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1499 23:53:53.069876   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1500 23:53:53.076568   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1501 23:53:53.080033   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1502 23:53:53.083581   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1503 23:53:53.090185   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

 1504 23:53:53.093178   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1505 23:53:53.096984   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1506 23:53:53.100473   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1507 23:53:53.106645   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1508 23:53:53.110297   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1509 23:53:53.113490   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1510 23:53:53.120176   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1511 23:53:53.123371   0  9  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1512 23:53:53.126540   0  9  8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)

 1513 23:53:53.133660   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1514 23:53:53.137198   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1515 23:53:53.140337   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1516 23:53:53.146850   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1517 23:53:53.149996   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1518 23:53:53.153359   0 10  0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 1519 23:53:53.159968   0 10  4 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (0 0)

 1520 23:53:53.163850   0 10  8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (1 0)

 1521 23:53:53.166890   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1522 23:53:53.173595   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1523 23:53:53.176574   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1524 23:53:53.179982   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1525 23:53:53.183462   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1526 23:53:53.190330   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1527 23:53:53.193497   0 11  4 | B1->B0 | 2c2c 3535 | 0 0 | (0 0) (0 0)

 1528 23:53:53.196705   0 11  8 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)

 1529 23:53:53.203706   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1530 23:53:53.206810   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1531 23:53:53.210129   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1532 23:53:53.217137   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1533 23:53:53.220574   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1534 23:53:53.224000   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1535 23:53:53.230440   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1536 23:53:53.234222   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1537 23:53:53.237338   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1538 23:53:53.244292   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1539 23:53:53.247173   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1540 23:53:53.250986   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1541 23:53:53.253856   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1542 23:53:53.260773   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1543 23:53:53.264061   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1544 23:53:53.267268   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1545 23:53:53.273846   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1546 23:53:53.277008   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1547 23:53:53.280636   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1548 23:53:53.287524   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1549 23:53:53.290756   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1550 23:53:53.293678   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1551 23:53:53.300382   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1552 23:53:53.304117   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1553 23:53:53.307125  Total UI for P1: 0, mck2ui 16

 1554 23:53:53.310611  best dqsien dly found for B0: ( 0, 14,  4)

 1555 23:53:53.314287  Total UI for P1: 0, mck2ui 16

 1556 23:53:53.317479  best dqsien dly found for B1: ( 0, 14,  4)

 1557 23:53:53.321054  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1558 23:53:53.323865  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1559 23:53:53.323949  

 1560 23:53:53.327376  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1561 23:53:53.330688  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1562 23:53:53.334009  [Gating] SW calibration Done

 1563 23:53:53.334093  ==

 1564 23:53:53.337494  Dram Type= 6, Freq= 0, CH_1, rank 0

 1565 23:53:53.340525  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1566 23:53:53.340610  ==

 1567 23:53:53.343775  RX Vref Scan: 0

 1568 23:53:53.343859  

 1569 23:53:53.347480  RX Vref 0 -> 0, step: 1

 1570 23:53:53.347565  

 1571 23:53:53.347648  RX Delay -130 -> 252, step: 16

 1572 23:53:53.354055  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1573 23:53:53.357781  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1574 23:53:53.360632  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1575 23:53:53.364538  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1576 23:53:53.367497  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1577 23:53:53.373869  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1578 23:53:53.377478  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1579 23:53:53.380497  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1580 23:53:53.384257  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1581 23:53:53.387380  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1582 23:53:53.394196  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1583 23:53:53.397370  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1584 23:53:53.400802  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1585 23:53:53.403808  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1586 23:53:53.407596  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1587 23:53:53.413874  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1588 23:53:53.413958  ==

 1589 23:53:53.417493  Dram Type= 6, Freq= 0, CH_1, rank 0

 1590 23:53:53.420571  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1591 23:53:53.420694  ==

 1592 23:53:53.420759  DQS Delay:

 1593 23:53:53.424253  DQS0 = 0, DQS1 = 0

 1594 23:53:53.424398  DQM Delay:

 1595 23:53:53.427839  DQM0 = 93, DQM1 = 87

 1596 23:53:53.427920  DQ Delay:

 1597 23:53:53.430794  DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93

 1598 23:53:53.434446  DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93

 1599 23:53:53.437452  DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85

 1600 23:53:53.441185  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1601 23:53:53.441268  

 1602 23:53:53.441332  

 1603 23:53:53.441392  ==

 1604 23:53:53.444320  Dram Type= 6, Freq= 0, CH_1, rank 0

 1605 23:53:53.447725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1606 23:53:53.447809  ==

 1607 23:53:53.447874  

 1608 23:53:53.447933  

 1609 23:53:53.450918  	TX Vref Scan disable

 1610 23:53:53.454596   == TX Byte 0 ==

 1611 23:53:53.457633  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1612 23:53:53.460973  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1613 23:53:53.464324   == TX Byte 1 ==

 1614 23:53:53.467970  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1615 23:53:53.471185  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1616 23:53:53.471268  ==

 1617 23:53:53.474378  Dram Type= 6, Freq= 0, CH_1, rank 0

 1618 23:53:53.480980  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1619 23:53:53.481073  ==

 1620 23:53:53.493374  TX Vref=22, minBit 0, minWin=26, winSum=433

 1621 23:53:53.496707  TX Vref=24, minBit 1, minWin=26, winSum=439

 1622 23:53:53.499693  TX Vref=26, minBit 1, minWin=27, winSum=444

 1623 23:53:53.503470  TX Vref=28, minBit 3, minWin=26, winSum=443

 1624 23:53:53.506632  TX Vref=30, minBit 1, minWin=27, winSum=447

 1625 23:53:53.509522  TX Vref=32, minBit 2, minWin=26, winSum=445

 1626 23:53:53.516554  [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 30

 1627 23:53:53.516638  

 1628 23:53:53.519671  Final TX Range 1 Vref 30

 1629 23:53:53.519755  

 1630 23:53:53.519852  ==

 1631 23:53:53.523549  Dram Type= 6, Freq= 0, CH_1, rank 0

 1632 23:53:53.527099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1633 23:53:53.527197  ==

 1634 23:53:53.527261  

 1635 23:53:53.527321  

 1636 23:53:53.530054  	TX Vref Scan disable

 1637 23:53:53.533460   == TX Byte 0 ==

 1638 23:53:53.537041  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1639 23:53:53.539764  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1640 23:53:53.543647   == TX Byte 1 ==

 1641 23:53:53.546561  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1642 23:53:53.549964  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1643 23:53:53.550081  

 1644 23:53:53.553432  [DATLAT]

 1645 23:53:53.553513  Freq=800, CH1 RK0

 1646 23:53:53.553577  

 1647 23:53:53.557098  DATLAT Default: 0xa

 1648 23:53:53.557237  0, 0xFFFF, sum = 0

 1649 23:53:53.559863  1, 0xFFFF, sum = 0

 1650 23:53:53.559945  2, 0xFFFF, sum = 0

 1651 23:53:53.563351  3, 0xFFFF, sum = 0

 1652 23:53:53.563434  4, 0xFFFF, sum = 0

 1653 23:53:53.566773  5, 0xFFFF, sum = 0

 1654 23:53:53.566887  6, 0xFFFF, sum = 0

 1655 23:53:53.570132  7, 0xFFFF, sum = 0

 1656 23:53:53.570232  8, 0xFFFF, sum = 0

 1657 23:53:53.573136  9, 0x0, sum = 1

 1658 23:53:53.573278  10, 0x0, sum = 2

 1659 23:53:53.576951  11, 0x0, sum = 3

 1660 23:53:53.577034  12, 0x0, sum = 4

 1661 23:53:53.580002  best_step = 10

 1662 23:53:53.580121  

 1663 23:53:53.580212  ==

 1664 23:53:53.583310  Dram Type= 6, Freq= 0, CH_1, rank 0

 1665 23:53:53.587033  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1666 23:53:53.587116  ==

 1667 23:53:53.587179  RX Vref Scan: 1

 1668 23:53:53.587238  

 1669 23:53:53.590470  Set Vref Range= 32 -> 127

 1670 23:53:53.590552  

 1671 23:53:53.593942  RX Vref 32 -> 127, step: 1

 1672 23:53:53.594023  

 1673 23:53:53.596774  RX Delay -79 -> 252, step: 8

 1674 23:53:53.596860  

 1675 23:53:53.600105  Set Vref, RX VrefLevel [Byte0]: 32

 1676 23:53:53.603475                           [Byte1]: 32

 1677 23:53:53.603562  

 1678 23:53:53.606857  Set Vref, RX VrefLevel [Byte0]: 33

 1679 23:53:53.610350                           [Byte1]: 33

 1680 23:53:53.610433  

 1681 23:53:53.613449  Set Vref, RX VrefLevel [Byte0]: 34

 1682 23:53:53.617190                           [Byte1]: 34

 1683 23:53:53.620102  

 1684 23:53:53.620183  Set Vref, RX VrefLevel [Byte0]: 35

 1685 23:53:53.623927                           [Byte1]: 35

 1686 23:53:53.628067  

 1687 23:53:53.628147  Set Vref, RX VrefLevel [Byte0]: 36

 1688 23:53:53.631253                           [Byte1]: 36

 1689 23:53:53.635248  

 1690 23:53:53.635330  Set Vref, RX VrefLevel [Byte0]: 37

 1691 23:53:53.639086                           [Byte1]: 37

 1692 23:53:53.642892  

 1693 23:53:53.642979  Set Vref, RX VrefLevel [Byte0]: 38

 1694 23:53:53.646423                           [Byte1]: 38

 1695 23:53:53.650469  

 1696 23:53:53.650553  Set Vref, RX VrefLevel [Byte0]: 39

 1697 23:53:53.653574                           [Byte1]: 39

 1698 23:53:53.657957  

 1699 23:53:53.658070  Set Vref, RX VrefLevel [Byte0]: 40

 1700 23:53:53.661898                           [Byte1]: 40

 1701 23:53:53.666061  

 1702 23:53:53.666146  Set Vref, RX VrefLevel [Byte0]: 41

 1703 23:53:53.668837                           [Byte1]: 41

 1704 23:53:53.672934  

 1705 23:53:53.673018  Set Vref, RX VrefLevel [Byte0]: 42

 1706 23:53:53.676551                           [Byte1]: 42

 1707 23:53:53.680876  

 1708 23:53:53.680985  Set Vref, RX VrefLevel [Byte0]: 43

 1709 23:53:53.684094                           [Byte1]: 43

 1710 23:53:53.688473  

 1711 23:53:53.688558  Set Vref, RX VrefLevel [Byte0]: 44

 1712 23:53:53.691508                           [Byte1]: 44

 1713 23:53:53.695770  

 1714 23:53:53.695855  Set Vref, RX VrefLevel [Byte0]: 45

 1715 23:53:53.698946                           [Byte1]: 45

 1716 23:53:53.703410  

 1717 23:53:53.703495  Set Vref, RX VrefLevel [Byte0]: 46

 1718 23:53:53.706554                           [Byte1]: 46

 1719 23:53:53.710911  

 1720 23:53:53.710994  Set Vref, RX VrefLevel [Byte0]: 47

 1721 23:53:53.714210                           [Byte1]: 47

 1722 23:53:53.718516  

 1723 23:53:53.718598  Set Vref, RX VrefLevel [Byte0]: 48

 1724 23:53:53.721522                           [Byte1]: 48

 1725 23:53:53.725787  

 1726 23:53:53.725871  Set Vref, RX VrefLevel [Byte0]: 49

 1727 23:53:53.729559                           [Byte1]: 49

 1728 23:53:53.733307  

 1729 23:53:53.733404  Set Vref, RX VrefLevel [Byte0]: 50

 1730 23:53:53.737055                           [Byte1]: 50

 1731 23:53:53.740810  

 1732 23:53:53.740892  Set Vref, RX VrefLevel [Byte0]: 51

 1733 23:53:53.744636                           [Byte1]: 51

 1734 23:53:53.748321  

 1735 23:53:53.748418  Set Vref, RX VrefLevel [Byte0]: 52

 1736 23:53:53.752246                           [Byte1]: 52

 1737 23:53:53.756334  

 1738 23:53:53.756440  Set Vref, RX VrefLevel [Byte0]: 53

 1739 23:53:53.759381                           [Byte1]: 53

 1740 23:53:53.763514  

 1741 23:53:53.763597  Set Vref, RX VrefLevel [Byte0]: 54

 1742 23:53:53.767305                           [Byte1]: 54

 1743 23:53:53.771025  

 1744 23:53:53.771139  Set Vref, RX VrefLevel [Byte0]: 55

 1745 23:53:53.774684                           [Byte1]: 55

 1746 23:53:53.778776  

 1747 23:53:53.778858  Set Vref, RX VrefLevel [Byte0]: 56

 1748 23:53:53.782266                           [Byte1]: 56

 1749 23:53:53.786712  

 1750 23:53:53.786797  Set Vref, RX VrefLevel [Byte0]: 57

 1751 23:53:53.790078                           [Byte1]: 57

 1752 23:53:53.793960  

 1753 23:53:53.794059  Set Vref, RX VrefLevel [Byte0]: 58

 1754 23:53:53.797127                           [Byte1]: 58

 1755 23:53:53.801554  

 1756 23:53:53.801658  Set Vref, RX VrefLevel [Byte0]: 59

 1757 23:53:53.805240                           [Byte1]: 59

 1758 23:53:53.809076  

 1759 23:53:53.809159  Set Vref, RX VrefLevel [Byte0]: 60

 1760 23:53:53.812522                           [Byte1]: 60

 1761 23:53:53.816813  

 1762 23:53:53.816896  Set Vref, RX VrefLevel [Byte0]: 61

 1763 23:53:53.820042                           [Byte1]: 61

 1764 23:53:53.824676  

 1765 23:53:53.824773  Set Vref, RX VrefLevel [Byte0]: 62

 1766 23:53:53.827727                           [Byte1]: 62

 1767 23:53:53.831570  

 1768 23:53:53.831651  Set Vref, RX VrefLevel [Byte0]: 63

 1769 23:53:53.834789                           [Byte1]: 63

 1770 23:53:53.839247  

 1771 23:53:53.839329  Set Vref, RX VrefLevel [Byte0]: 64

 1772 23:53:53.842450                           [Byte1]: 64

 1773 23:53:53.846851  

 1774 23:53:53.846935  Set Vref, RX VrefLevel [Byte0]: 65

 1775 23:53:53.849972                           [Byte1]: 65

 1776 23:53:53.854311  

 1777 23:53:53.854394  Set Vref, RX VrefLevel [Byte0]: 66

 1778 23:53:53.857482                           [Byte1]: 66

 1779 23:53:53.861735  

 1780 23:53:53.861817  Set Vref, RX VrefLevel [Byte0]: 67

 1781 23:53:53.865325                           [Byte1]: 67

 1782 23:53:53.869436  

 1783 23:53:53.869525  Set Vref, RX VrefLevel [Byte0]: 68

 1784 23:53:53.872491                           [Byte1]: 68

 1785 23:53:53.876963  

 1786 23:53:53.877044  Set Vref, RX VrefLevel [Byte0]: 69

 1787 23:53:53.880647                           [Byte1]: 69

 1788 23:53:53.884667  

 1789 23:53:53.884749  Set Vref, RX VrefLevel [Byte0]: 70

 1790 23:53:53.887650                           [Byte1]: 70

 1791 23:53:53.892037  

 1792 23:53:53.892134  Final RX Vref Byte 0 = 58 to rank0

 1793 23:53:53.894978  Final RX Vref Byte 1 = 56 to rank0

 1794 23:53:53.898589  Final RX Vref Byte 0 = 58 to rank1

 1795 23:53:53.902076  Final RX Vref Byte 1 = 56 to rank1==

 1796 23:53:53.905478  Dram Type= 6, Freq= 0, CH_1, rank 0

 1797 23:53:53.911996  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1798 23:53:53.912085  ==

 1799 23:53:53.912150  DQS Delay:

 1800 23:53:53.912210  DQS0 = 0, DQS1 = 0

 1801 23:53:53.915598  DQM Delay:

 1802 23:53:53.915679  DQM0 = 95, DQM1 = 89

 1803 23:53:53.918864  DQ Delay:

 1804 23:53:53.921877  DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92

 1805 23:53:53.925609  DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92

 1806 23:53:53.928813  DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84

 1807 23:53:53.932070  DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96

 1808 23:53:53.932152  

 1809 23:53:53.932217  

 1810 23:53:53.939006  [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 1811 23:53:53.942418  CH1 RK0: MR19=606, MR18=2B48

 1812 23:53:53.949055  CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64

 1813 23:53:53.949169  

 1814 23:53:53.951924  ----->DramcWriteLeveling(PI) begin...

 1815 23:53:53.952034  ==

 1816 23:53:53.955593  Dram Type= 6, Freq= 0, CH_1, rank 1

 1817 23:53:53.958847  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1818 23:53:53.958933  ==

 1819 23:53:53.961995  Write leveling (Byte 0): 26 => 26

 1820 23:53:53.965521  Write leveling (Byte 1): 28 => 28

 1821 23:53:53.968530  DramcWriteLeveling(PI) end<-----

 1822 23:53:53.968613  

 1823 23:53:53.968676  ==

 1824 23:53:53.972209  Dram Type= 6, Freq= 0, CH_1, rank 1

 1825 23:53:53.975431  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1826 23:53:53.975514  ==

 1827 23:53:53.978804  [Gating] SW mode calibration

 1828 23:53:53.985492  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1829 23:53:53.991761  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1830 23:53:53.995741   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1831 23:53:53.998611   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1832 23:53:54.005623   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1833 23:53:54.008689   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1834 23:53:54.012069   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1835 23:53:54.018885   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1836 23:53:54.022144   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 23:53:54.025065   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1838 23:53:54.032033   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1839 23:53:54.035737   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1840 23:53:54.039108   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 23:53:54.045830   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 23:53:54.048706   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1843 23:53:54.052220   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1844 23:53:54.059151   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1845 23:53:54.062322   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1846 23:53:54.065670   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1847 23:53:54.068957   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)

 1848 23:53:54.075317   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1849 23:53:54.078971   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1850 23:53:54.082238   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1851 23:53:54.089374   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1852 23:53:54.092299   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1853 23:53:54.095567   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1854 23:53:54.102603   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1855 23:53:54.105693   0  9  4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)

 1856 23:53:54.108932   0  9  8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 1)

 1857 23:53:54.115684   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1858 23:53:54.119241   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1859 23:53:54.122387   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1860 23:53:54.126008   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1861 23:53:54.132678   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1862 23:53:54.135609   0 10  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1863 23:53:54.138978   0 10  4 | B1->B0 | 2727 3030 | 0 0 | (1 0) (1 0)

 1864 23:53:54.146001   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1865 23:53:54.149260   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1866 23:53:54.152333   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1867 23:53:54.159405   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1868 23:53:54.162471   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1869 23:53:54.165623   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1870 23:53:54.172756   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1871 23:53:54.175617   0 11  4 | B1->B0 | 3838 2a29 | 1 1 | (0 0) (0 0)

 1872 23:53:54.179326   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1873 23:53:54.186204   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1874 23:53:54.189352   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1875 23:53:54.192593   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1876 23:53:54.199515   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1877 23:53:54.202628   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1878 23:53:54.205740   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1879 23:53:54.212457   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1880 23:53:54.215942   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1881 23:53:54.219623   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1882 23:53:54.222973   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1883 23:53:54.229119   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1884 23:53:54.232661   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1885 23:53:54.236284   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1886 23:53:54.242722   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1887 23:53:54.245995   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1888 23:53:54.249437   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1889 23:53:54.256045   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1890 23:53:54.259147   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1891 23:53:54.262476   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1892 23:53:54.269644   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1893 23:53:54.273037   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1894 23:53:54.275851   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1895 23:53:54.282621   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1896 23:53:54.286024   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1897 23:53:54.289436  Total UI for P1: 0, mck2ui 16

 1898 23:53:54.293268  best dqsien dly found for B0: ( 0, 14,  4)

 1899 23:53:54.296456  Total UI for P1: 0, mck2ui 16

 1900 23:53:54.299621  best dqsien dly found for B1: ( 0, 14,  4)

 1901 23:53:54.302992  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1902 23:53:54.306206  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1903 23:53:54.306288  

 1904 23:53:54.309992  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1905 23:53:54.313327  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1906 23:53:54.316200  [Gating] SW calibration Done

 1907 23:53:54.316280  ==

 1908 23:53:54.319976  Dram Type= 6, Freq= 0, CH_1, rank 1

 1909 23:53:54.323224  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1910 23:53:54.323322  ==

 1911 23:53:54.326926  RX Vref Scan: 0

 1912 23:53:54.327023  

 1913 23:53:54.327117  RX Vref 0 -> 0, step: 1

 1914 23:53:54.327191  

 1915 23:53:54.329778  RX Delay -130 -> 252, step: 16

 1916 23:53:54.333037  iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208

 1917 23:53:54.340067  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1918 23:53:54.343333  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1919 23:53:54.346316  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1920 23:53:54.350048  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1921 23:53:54.352931  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1922 23:53:54.359769  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1923 23:53:54.363161  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1924 23:53:54.366690  iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208

 1925 23:53:54.370050  iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208

 1926 23:53:54.373358  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1927 23:53:54.380327  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1928 23:53:54.383444  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1929 23:53:54.386770  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1930 23:53:54.389845  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1931 23:53:54.393751  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1932 23:53:54.393851  ==

 1933 23:53:54.396639  Dram Type= 6, Freq= 0, CH_1, rank 1

 1934 23:53:54.403360  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1935 23:53:54.403447  ==

 1936 23:53:54.403511  DQS Delay:

 1937 23:53:54.406306  DQS0 = 0, DQS1 = 0

 1938 23:53:54.406388  DQM Delay:

 1939 23:53:54.410019  DQM0 = 93, DQM1 = 90

 1940 23:53:54.410101  DQ Delay:

 1941 23:53:54.413382  DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85

 1942 23:53:54.416469  DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93

 1943 23:53:54.419596  DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85

 1944 23:53:54.423355  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1945 23:53:54.423436  

 1946 23:53:54.423498  

 1947 23:53:54.423556  ==

 1948 23:53:54.426465  Dram Type= 6, Freq= 0, CH_1, rank 1

 1949 23:53:54.430127  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1950 23:53:54.430210  ==

 1951 23:53:54.430274  

 1952 23:53:54.430332  

 1953 23:53:54.433072  	TX Vref Scan disable

 1954 23:53:54.436976   == TX Byte 0 ==

 1955 23:53:54.439756  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1956 23:53:54.443608  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1957 23:53:54.446619   == TX Byte 1 ==

 1958 23:53:54.450218  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1959 23:53:54.453458  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1960 23:53:54.453541  ==

 1961 23:53:54.456691  Dram Type= 6, Freq= 0, CH_1, rank 1

 1962 23:53:54.460259  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1963 23:53:54.463098  ==

 1964 23:53:54.474162  TX Vref=22, minBit 1, minWin=26, winSum=442

 1965 23:53:54.477593  TX Vref=24, minBit 1, minWin=26, winSum=443

 1966 23:53:54.480904  TX Vref=26, minBit 0, minWin=27, winSum=450

 1967 23:53:54.484208  TX Vref=28, minBit 2, minWin=27, winSum=447

 1968 23:53:54.487799  TX Vref=30, minBit 0, minWin=27, winSum=452

 1969 23:53:54.490878  TX Vref=32, minBit 2, minWin=27, winSum=449

 1970 23:53:54.497970  [TxChooseVref] Worse bit 0, Min win 27, Win sum 452, Final Vref 30

 1971 23:53:54.498073  

 1972 23:53:54.501124  Final TX Range 1 Vref 30

 1973 23:53:54.501234  

 1974 23:53:54.501327  ==

 1975 23:53:54.504503  Dram Type= 6, Freq= 0, CH_1, rank 1

 1976 23:53:54.507595  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1977 23:53:54.507681  ==

 1978 23:53:54.507746  

 1979 23:53:54.507806  

 1980 23:53:54.510843  	TX Vref Scan disable

 1981 23:53:54.514623   == TX Byte 0 ==

 1982 23:53:54.517823  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1983 23:53:54.521472  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1984 23:53:54.524722   == TX Byte 1 ==

 1985 23:53:54.527742  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1986 23:53:54.531154  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1987 23:53:54.531235  

 1988 23:53:54.534628  [DATLAT]

 1989 23:53:54.534742  Freq=800, CH1 RK1

 1990 23:53:54.534806  

 1991 23:53:54.538429  DATLAT Default: 0xa

 1992 23:53:54.538510  0, 0xFFFF, sum = 0

 1993 23:53:54.541518  1, 0xFFFF, sum = 0

 1994 23:53:54.541601  2, 0xFFFF, sum = 0

 1995 23:53:54.544599  3, 0xFFFF, sum = 0

 1996 23:53:54.544681  4, 0xFFFF, sum = 0

 1997 23:53:54.548366  5, 0xFFFF, sum = 0

 1998 23:53:54.548465  6, 0xFFFF, sum = 0

 1999 23:53:54.551413  7, 0xFFFF, sum = 0

 2000 23:53:54.551511  8, 0xFFFF, sum = 0

 2001 23:53:54.555126  9, 0x0, sum = 1

 2002 23:53:54.555209  10, 0x0, sum = 2

 2003 23:53:54.557958  11, 0x0, sum = 3

 2004 23:53:54.558041  12, 0x0, sum = 4

 2005 23:53:54.561687  best_step = 10

 2006 23:53:54.561769  

 2007 23:53:54.561832  ==

 2008 23:53:54.564743  Dram Type= 6, Freq= 0, CH_1, rank 1

 2009 23:53:54.568259  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2010 23:53:54.568366  ==

 2011 23:53:54.568446  RX Vref Scan: 0

 2012 23:53:54.571593  

 2013 23:53:54.571673  RX Vref 0 -> 0, step: 1

 2014 23:53:54.571737  

 2015 23:53:54.574591  RX Delay -63 -> 252, step: 8

 2016 23:53:54.578473  iDelay=209, Bit 0, Center 104 (9 ~ 200) 192

 2017 23:53:54.584979  iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200

 2018 23:53:54.588244  iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200

 2019 23:53:54.591871  iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200

 2020 23:53:54.595347  iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200

 2021 23:53:54.598469  iDelay=209, Bit 5, Center 112 (17 ~ 208) 192

 2022 23:53:54.601590  iDelay=209, Bit 6, Center 108 (9 ~ 208) 200

 2023 23:53:54.608066  iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208

 2024 23:53:54.611451  iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208

 2025 23:53:54.614944  iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208

 2026 23:53:54.618601  iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208

 2027 23:53:54.621855  iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208

 2028 23:53:54.628107  iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216

 2029 23:53:54.631732  iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208

 2030 23:53:54.635400  iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208

 2031 23:53:54.638428  iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208

 2032 23:53:54.638556  ==

 2033 23:53:54.641627  Dram Type= 6, Freq= 0, CH_1, rank 1

 2034 23:53:54.644857  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2035 23:53:54.648599  ==

 2036 23:53:54.648733  DQS Delay:

 2037 23:53:54.648855  DQS0 = 0, DQS1 = 0

 2038 23:53:54.651868  DQM Delay:

 2039 23:53:54.651995  DQM0 = 97, DQM1 = 91

 2040 23:53:54.654919  DQ Delay:

 2041 23:53:54.658473  DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92

 2042 23:53:54.658558  DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96

 2043 23:53:54.661489  DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88

 2044 23:53:54.668334  DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96

 2045 23:53:54.668433  

 2046 23:53:54.668500  

 2047 23:53:54.674633  [DQSOSCAuto] RK1, (LSB)MR18= 0x4811, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps

 2048 23:53:54.678395  CH1 RK1: MR19=606, MR18=4811

 2049 23:53:54.685194  CH1_RK1: MR19=0x606, MR18=0x4811, DQSOSC=391, MR23=63, INC=96, DEC=64

 2050 23:53:54.688361  [RxdqsGatingPostProcess] freq 800

 2051 23:53:54.691676  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2052 23:53:54.694806  Pre-setting of DQS Precalculation

 2053 23:53:54.701454  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2054 23:53:54.708219  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2055 23:53:54.715559  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2056 23:53:54.715654  

 2057 23:53:54.715719  

 2058 23:53:54.718481  [Calibration Summary] 1600 Mbps

 2059 23:53:54.718566  CH 0, Rank 0

 2060 23:53:54.721483  SW Impedance     : PASS

 2061 23:53:54.724928  DUTY Scan        : NO K

 2062 23:53:54.725010  ZQ Calibration   : PASS

 2063 23:53:54.728750  Jitter Meter     : NO K

 2064 23:53:54.728836  CBT Training     : PASS

 2065 23:53:54.731953  Write leveling   : PASS

 2066 23:53:54.735025  RX DQS gating    : PASS

 2067 23:53:54.735131  RX DQ/DQS(RDDQC) : PASS

 2068 23:53:54.738588  TX DQ/DQS        : PASS

 2069 23:53:54.741619  RX DATLAT        : PASS

 2070 23:53:54.741709  RX DQ/DQS(Engine): PASS

 2071 23:53:54.745421  TX OE            : NO K

 2072 23:53:54.745508  All Pass.

 2073 23:53:54.745594  

 2074 23:53:54.748582  CH 0, Rank 1

 2075 23:53:54.748668  SW Impedance     : PASS

 2076 23:53:54.751778  DUTY Scan        : NO K

 2077 23:53:54.754934  ZQ Calibration   : PASS

 2078 23:53:54.755020  Jitter Meter     : NO K

 2079 23:53:54.758720  CBT Training     : PASS

 2080 23:53:54.761627  Write leveling   : PASS

 2081 23:53:54.761712  RX DQS gating    : PASS

 2082 23:53:54.765197  RX DQ/DQS(RDDQC) : PASS

 2083 23:53:54.765280  TX DQ/DQS        : PASS

 2084 23:53:54.768457  RX DATLAT        : PASS

 2085 23:53:54.772168  RX DQ/DQS(Engine): PASS

 2086 23:53:54.772276  TX OE            : NO K

 2087 23:53:54.775127  All Pass.

 2088 23:53:54.775207  

 2089 23:53:54.775298  CH 1, Rank 0

 2090 23:53:54.778261  SW Impedance     : PASS

 2091 23:53:54.778342  DUTY Scan        : NO K

 2092 23:53:54.782070  ZQ Calibration   : PASS

 2093 23:53:54.785206  Jitter Meter     : NO K

 2094 23:53:54.785317  CBT Training     : PASS

 2095 23:53:54.788844  Write leveling   : PASS

 2096 23:53:54.792016  RX DQS gating    : PASS

 2097 23:53:54.792101  RX DQ/DQS(RDDQC) : PASS

 2098 23:53:54.795093  TX DQ/DQS        : PASS

 2099 23:53:54.798897  RX DATLAT        : PASS

 2100 23:53:54.798983  RX DQ/DQS(Engine): PASS

 2101 23:53:54.801977  TX OE            : NO K

 2102 23:53:54.802050  All Pass.

 2103 23:53:54.802111  

 2104 23:53:54.804962  CH 1, Rank 1

 2105 23:53:54.805044  SW Impedance     : PASS

 2106 23:53:54.808500  DUTY Scan        : NO K

 2107 23:53:54.808599  ZQ Calibration   : PASS

 2108 23:53:54.812028  Jitter Meter     : NO K

 2109 23:53:54.815253  CBT Training     : PASS

 2110 23:53:54.815336  Write leveling   : PASS

 2111 23:53:54.818448  RX DQS gating    : PASS

 2112 23:53:54.822187  RX DQ/DQS(RDDQC) : PASS

 2113 23:53:54.822271  TX DQ/DQS        : PASS

 2114 23:53:54.825303  RX DATLAT        : PASS

 2115 23:53:54.828542  RX DQ/DQS(Engine): PASS

 2116 23:53:54.828625  TX OE            : NO K

 2117 23:53:54.831756  All Pass.

 2118 23:53:54.831836  

 2119 23:53:54.831899  DramC Write-DBI off

 2120 23:53:54.834705  	PER_BANK_REFRESH: Hybrid Mode

 2121 23:53:54.838478  TX_TRACKING: ON

 2122 23:53:54.841801  [GetDramInforAfterCalByMRR] Vendor 6.

 2123 23:53:54.844889  [GetDramInforAfterCalByMRR] Revision 606.

 2124 23:53:54.848455  [GetDramInforAfterCalByMRR] Revision 2 0.

 2125 23:53:54.848554  MR0 0x3b3b

 2126 23:53:54.848633  MR8 0x5151

 2127 23:53:54.851776  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2128 23:53:54.855225  

 2129 23:53:54.855309  MR0 0x3b3b

 2130 23:53:54.855375  MR8 0x5151

 2131 23:53:54.858374  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2132 23:53:54.858459  

 2133 23:53:54.868153  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2134 23:53:54.872050  [FAST_K] Save calibration result to emmc

 2135 23:53:54.874969  [FAST_K] Save calibration result to emmc

 2136 23:53:54.878045  dram_init: config_dvfs: 1

 2137 23:53:54.881859  dramc_set_vcore_voltage set vcore to 662500

 2138 23:53:54.884957  Read voltage for 1200, 2

 2139 23:53:54.885041  Vio18 = 0

 2140 23:53:54.885106  Vcore = 662500

 2141 23:53:54.888217  Vdram = 0

 2142 23:53:54.888327  Vddq = 0

 2143 23:53:54.888406  Vmddr = 0

 2144 23:53:54.895048  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2145 23:53:54.898144  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2146 23:53:54.901854  MEM_TYPE=3, freq_sel=15

 2147 23:53:54.905193  sv_algorithm_assistance_LP4_1600 

 2148 23:53:54.908220  ============ PULL DRAM RESETB DOWN ============

 2149 23:53:54.911925  ========== PULL DRAM RESETB DOWN end =========

 2150 23:53:54.918696  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2151 23:53:54.921900  =================================== 

 2152 23:53:54.921989  LPDDR4 DRAM CONFIGURATION

 2153 23:53:54.925017  =================================== 

 2154 23:53:54.928641  EX_ROW_EN[0]    = 0x0

 2155 23:53:54.932047  EX_ROW_EN[1]    = 0x0

 2156 23:53:54.932131  LP4Y_EN      = 0x0

 2157 23:53:54.935041  WORK_FSP     = 0x0

 2158 23:53:54.935152  WL           = 0x4

 2159 23:53:54.938637  RL           = 0x4

 2160 23:53:54.938721  BL           = 0x2

 2161 23:53:54.941860  RPST         = 0x0

 2162 23:53:54.941944  RD_PRE       = 0x0

 2163 23:53:54.944969  WR_PRE       = 0x1

 2164 23:53:54.945053  WR_PST       = 0x0

 2165 23:53:54.948299  DBI_WR       = 0x0

 2166 23:53:54.948400  DBI_RD       = 0x0

 2167 23:53:54.952044  OTF          = 0x1

 2168 23:53:54.955248  =================================== 

 2169 23:53:54.958647  =================================== 

 2170 23:53:54.958734  ANA top config

 2171 23:53:54.961705  =================================== 

 2172 23:53:54.965366  DLL_ASYNC_EN            =  0

 2173 23:53:54.968310  ALL_SLAVE_EN            =  0

 2174 23:53:54.968437  NEW_RANK_MODE           =  1

 2175 23:53:54.971986  DLL_IDLE_MODE           =  1

 2176 23:53:54.975089  LP45_APHY_COMB_EN       =  1

 2177 23:53:54.978507  TX_ODT_DIS              =  1

 2178 23:53:54.982340  NEW_8X_MODE             =  1

 2179 23:53:54.982429  =================================== 

 2180 23:53:54.985323  =================================== 

 2181 23:53:54.988933  data_rate                  = 2400

 2182 23:53:54.992038  CKR                        = 1

 2183 23:53:54.995200  DQ_P2S_RATIO               = 8

 2184 23:53:54.998910  =================================== 

 2185 23:53:55.002065  CA_P2S_RATIO               = 8

 2186 23:53:55.005149  DQ_CA_OPEN                 = 0

 2187 23:53:55.008801  DQ_SEMI_OPEN               = 0

 2188 23:53:55.008887  CA_SEMI_OPEN               = 0

 2189 23:53:55.012044  CA_FULL_RATE               = 0

 2190 23:53:55.014959  DQ_CKDIV4_EN               = 0

 2191 23:53:55.018628  CA_CKDIV4_EN               = 0

 2192 23:53:55.021786  CA_PREDIV_EN               = 0

 2193 23:53:55.021905  PH8_DLY                    = 17

 2194 23:53:55.025550  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2195 23:53:55.028539  DQ_AAMCK_DIV               = 4

 2196 23:53:55.032219  CA_AAMCK_DIV               = 4

 2197 23:53:55.035328  CA_ADMCK_DIV               = 4

 2198 23:53:55.038696  DQ_TRACK_CA_EN             = 0

 2199 23:53:55.042275  CA_PICK                    = 1200

 2200 23:53:55.042358  CA_MCKIO                   = 1200

 2201 23:53:55.045567  MCKIO_SEMI                 = 0

 2202 23:53:55.049101  PLL_FREQ                   = 2366

 2203 23:53:55.052032  DQ_UI_PI_RATIO             = 32

 2204 23:53:55.055232  CA_UI_PI_RATIO             = 0

 2205 23:53:55.058399  =================================== 

 2206 23:53:55.062023  =================================== 

 2207 23:53:55.065110  memory_type:LPDDR4         

 2208 23:53:55.065196  GP_NUM     : 10       

 2209 23:53:55.068922  SRAM_EN    : 1       

 2210 23:53:55.069056  MD32_EN    : 0       

 2211 23:53:55.071921  =================================== 

 2212 23:53:55.075615  [ANA_INIT] >>>>>>>>>>>>>> 

 2213 23:53:55.078826  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2214 23:53:55.082081  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2215 23:53:55.085470  =================================== 

 2216 23:53:55.088772  data_rate = 2400,PCW = 0X5b00

 2217 23:53:55.091860  =================================== 

 2218 23:53:55.095196  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2219 23:53:55.098715  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2220 23:53:55.105370  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2221 23:53:55.108470  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2222 23:53:55.112095  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2223 23:53:55.115295  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2224 23:53:55.118948  [ANA_INIT] flow start 

 2225 23:53:55.122056  [ANA_INIT] PLL >>>>>>>> 

 2226 23:53:55.122139  [ANA_INIT] PLL <<<<<<<< 

 2227 23:53:55.125586  [ANA_INIT] MIDPI >>>>>>>> 

 2228 23:53:55.128894  [ANA_INIT] MIDPI <<<<<<<< 

 2229 23:53:55.132031  [ANA_INIT] DLL >>>>>>>> 

 2230 23:53:55.132117  [ANA_INIT] DLL <<<<<<<< 

 2231 23:53:55.135249  [ANA_INIT] flow end 

 2232 23:53:55.139083  ============ LP4 DIFF to SE enter ============

 2233 23:53:55.142185  ============ LP4 DIFF to SE exit  ============

 2234 23:53:55.145263  [ANA_INIT] <<<<<<<<<<<<< 

 2235 23:53:55.148651  [Flow] Enable top DCM control >>>>> 

 2236 23:53:55.151939  [Flow] Enable top DCM control <<<<< 

 2237 23:53:55.155236  Enable DLL master slave shuffle 

 2238 23:53:55.162228  ============================================================== 

 2239 23:53:55.162309  Gating Mode config

 2240 23:53:55.169389  ============================================================== 

 2241 23:53:55.169523  Config description: 

 2242 23:53:55.178777  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2243 23:53:55.185509  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2244 23:53:55.192258  SELPH_MODE            0: By rank         1: By Phase 

 2245 23:53:55.195294  ============================================================== 

 2246 23:53:55.199171  GAT_TRACK_EN                 =  1

 2247 23:53:55.201907  RX_GATING_MODE               =  2

 2248 23:53:55.205364  RX_GATING_TRACK_MODE         =  2

 2249 23:53:55.208766  SELPH_MODE                   =  1

 2250 23:53:55.212020  PICG_EARLY_EN                =  1

 2251 23:53:55.215420  VALID_LAT_VALUE              =  1

 2252 23:53:55.218934  ============================================================== 

 2253 23:53:55.221977  Enter into Gating configuration >>>> 

 2254 23:53:55.225432  Exit from Gating configuration <<<< 

 2255 23:53:55.228829  Enter into  DVFS_PRE_config >>>>> 

 2256 23:53:55.242393  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2257 23:53:55.242489  Exit from  DVFS_PRE_config <<<<< 

 2258 23:53:55.245456  Enter into PICG configuration >>>> 

 2259 23:53:55.249119  Exit from PICG configuration <<<< 

 2260 23:53:55.252237  [RX_INPUT] configuration >>>>> 

 2261 23:53:55.255437  [RX_INPUT] configuration <<<<< 

 2262 23:53:55.262251  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2263 23:53:55.265294  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2264 23:53:55.272008  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2265 23:53:55.278892  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2266 23:53:55.285270  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2267 23:53:55.291941  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2268 23:53:55.295795  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2269 23:53:55.298980  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2270 23:53:55.302312  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2271 23:53:55.309124  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2272 23:53:55.312064  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2273 23:53:55.315744  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2274 23:53:55.319140  =================================== 

 2275 23:53:55.322077  LPDDR4 DRAM CONFIGURATION

 2276 23:53:55.325773  =================================== 

 2277 23:53:55.325899  EX_ROW_EN[0]    = 0x0

 2278 23:53:55.329046  EX_ROW_EN[1]    = 0x0

 2279 23:53:55.329169  LP4Y_EN      = 0x0

 2280 23:53:55.332098  WORK_FSP     = 0x0

 2281 23:53:55.332220  WL           = 0x4

 2282 23:53:55.335478  RL           = 0x4

 2283 23:53:55.335564  BL           = 0x2

 2284 23:53:55.339095  RPST         = 0x0

 2285 23:53:55.342368  RD_PRE       = 0x0

 2286 23:53:55.342451  WR_PRE       = 0x1

 2287 23:53:55.345753  WR_PST       = 0x0

 2288 23:53:55.345836  DBI_WR       = 0x0

 2289 23:53:55.348972  DBI_RD       = 0x0

 2290 23:53:55.349057  OTF          = 0x1

 2291 23:53:55.352151  =================================== 

 2292 23:53:55.356199  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2293 23:53:55.359078  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2294 23:53:55.365681  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2295 23:53:55.368825  =================================== 

 2296 23:53:55.372530  LPDDR4 DRAM CONFIGURATION

 2297 23:53:55.375690  =================================== 

 2298 23:53:55.375817  EX_ROW_EN[0]    = 0x10

 2299 23:53:55.378809  EX_ROW_EN[1]    = 0x0

 2300 23:53:55.378893  LP4Y_EN      = 0x0

 2301 23:53:55.382582  WORK_FSP     = 0x0

 2302 23:53:55.382665  WL           = 0x4

 2303 23:53:55.385995  RL           = 0x4

 2304 23:53:55.386078  BL           = 0x2

 2305 23:53:55.389017  RPST         = 0x0

 2306 23:53:55.389100  RD_PRE       = 0x0

 2307 23:53:55.392213  WR_PRE       = 0x1

 2308 23:53:55.392313  WR_PST       = 0x0

 2309 23:53:55.396168  DBI_WR       = 0x0

 2310 23:53:55.396251  DBI_RD       = 0x0

 2311 23:53:55.399020  OTF          = 0x1

 2312 23:53:55.402174  =================================== 

 2313 23:53:55.409046  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2314 23:53:55.409181  ==

 2315 23:53:55.412876  Dram Type= 6, Freq= 0, CH_0, rank 0

 2316 23:53:55.416192  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2317 23:53:55.416320  ==

 2318 23:53:55.419401  [Duty_Offset_Calibration]

 2319 23:53:55.419526  	B0:2	B1:1	CA:1

 2320 23:53:55.419638  

 2321 23:53:55.422595  [DutyScan_Calibration_Flow] k_type=0

 2322 23:53:55.432861  

 2323 23:53:55.432987  ==CLK 0==

 2324 23:53:55.436568  Final CLK duty delay cell = 0

 2325 23:53:55.439845  [0] MAX Duty = 5187%(X100), DQS PI = 24

 2326 23:53:55.442798  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2327 23:53:55.442923  [0] AVG Duty = 5031%(X100)

 2328 23:53:55.446093  

 2329 23:53:55.446215  CH0 CLK Duty spec in!! Max-Min= 312%

 2330 23:53:55.452770  [DutyScan_Calibration_Flow] ====Done====

 2331 23:53:55.452908  

 2332 23:53:55.456745  [DutyScan_Calibration_Flow] k_type=1

 2333 23:53:55.470537  

 2334 23:53:55.470684  ==DQS 0 ==

 2335 23:53:55.474177  Final DQS duty delay cell = -4

 2336 23:53:55.477190  [-4] MAX Duty = 5124%(X100), DQS PI = 22

 2337 23:53:55.480920  [-4] MIN Duty = 4751%(X100), DQS PI = 60

 2338 23:53:55.483853  [-4] AVG Duty = 4937%(X100)

 2339 23:53:55.483976  

 2340 23:53:55.484091  ==DQS 1 ==

 2341 23:53:55.487758  Final DQS duty delay cell = -4

 2342 23:53:55.490791  [-4] MAX Duty = 4969%(X100), DQS PI = 0

 2343 23:53:55.493964  [-4] MIN Duty = 4844%(X100), DQS PI = 32

 2344 23:53:55.497059  [-4] AVG Duty = 4906%(X100)

 2345 23:53:55.497183  

 2346 23:53:55.500214  CH0 DQS 0 Duty spec in!! Max-Min= 373%

 2347 23:53:55.500336  

 2348 23:53:55.503811  CH0 DQS 1 Duty spec in!! Max-Min= 125%

 2349 23:53:55.507305  [DutyScan_Calibration_Flow] ====Done====

 2350 23:53:55.507428  

 2351 23:53:55.510258  [DutyScan_Calibration_Flow] k_type=3

 2352 23:53:55.527926  

 2353 23:53:55.528074  ==DQM 0 ==

 2354 23:53:55.530991  Final DQM duty delay cell = 0

 2355 23:53:55.534737  [0] MAX Duty = 5156%(X100), DQS PI = 30

 2356 23:53:55.537818  [0] MIN Duty = 4906%(X100), DQS PI = 52

 2357 23:53:55.541063  [0] AVG Duty = 5031%(X100)

 2358 23:53:55.541186  

 2359 23:53:55.541299  ==DQM 1 ==

 2360 23:53:55.544610  Final DQM duty delay cell = 0

 2361 23:53:55.547781  [0] MAX Duty = 5125%(X100), DQS PI = 58

 2362 23:53:55.551504  [0] MIN Duty = 5031%(X100), DQS PI = 16

 2363 23:53:55.554342  [0] AVG Duty = 5078%(X100)

 2364 23:53:55.554464  

 2365 23:53:55.557415  CH0 DQM 0 Duty spec in!! Max-Min= 250%

 2366 23:53:55.557519  

 2367 23:53:55.561060  CH0 DQM 1 Duty spec in!! Max-Min= 94%

 2368 23:53:55.564416  [DutyScan_Calibration_Flow] ====Done====

 2369 23:53:55.564497  

 2370 23:53:55.567586  [DutyScan_Calibration_Flow] k_type=2

 2371 23:53:55.584248  

 2372 23:53:55.584415  ==DQ 0 ==

 2373 23:53:55.587666  Final DQ duty delay cell = 0

 2374 23:53:55.591331  [0] MAX Duty = 5062%(X100), DQS PI = 32

 2375 23:53:55.594316  [0] MIN Duty = 4906%(X100), DQS PI = 0

 2376 23:53:55.594439  [0] AVG Duty = 4984%(X100)

 2377 23:53:55.594548  

 2378 23:53:55.597345  ==DQ 1 ==

 2379 23:53:55.601433  Final DQ duty delay cell = 0

 2380 23:53:55.604532  [0] MAX Duty = 5093%(X100), DQS PI = 26

 2381 23:53:55.607757  [0] MIN Duty = 4969%(X100), DQS PI = 16

 2382 23:53:55.607880  [0] AVG Duty = 5031%(X100)

 2383 23:53:55.607990  

 2384 23:53:55.610807  CH0 DQ 0 Duty spec in!! Max-Min= 156%

 2385 23:53:55.610928  

 2386 23:53:55.614436  CH0 DQ 1 Duty spec in!! Max-Min= 124%

 2387 23:53:55.620753  [DutyScan_Calibration_Flow] ====Done====

 2388 23:53:55.620875  ==

 2389 23:53:55.624622  Dram Type= 6, Freq= 0, CH_1, rank 0

 2390 23:53:55.627620  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2391 23:53:55.627866  ==

 2392 23:53:55.631416  [Duty_Offset_Calibration]

 2393 23:53:55.631622  	B0:1	B1:0	CA:0

 2394 23:53:55.631748  

 2395 23:53:55.634593  [DutyScan_Calibration_Flow] k_type=0

 2396 23:53:55.643437  

 2397 23:53:55.643641  ==CLK 0==

 2398 23:53:55.647092  Final CLK duty delay cell = -4

 2399 23:53:55.650280  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2400 23:53:55.653263  [-4] MIN Duty = 4875%(X100), DQS PI = 52

 2401 23:53:55.657265  [-4] AVG Duty = 4953%(X100)

 2402 23:53:55.657353  

 2403 23:53:55.660086  CH1 CLK Duty spec in!! Max-Min= 156%

 2404 23:53:55.664001  [DutyScan_Calibration_Flow] ====Done====

 2405 23:53:55.664178  

 2406 23:53:55.666944  [DutyScan_Calibration_Flow] k_type=1

 2407 23:53:55.682886  

 2408 23:53:55.683072  ==DQS 0 ==

 2409 23:53:55.686562  Final DQS duty delay cell = 0

 2410 23:53:55.690027  [0] MAX Duty = 5062%(X100), DQS PI = 12

 2411 23:53:55.693279  [0] MIN Duty = 4844%(X100), DQS PI = 0

 2412 23:53:55.693409  [0] AVG Duty = 4953%(X100)

 2413 23:53:55.696247  

 2414 23:53:55.696376  ==DQS 1 ==

 2415 23:53:55.699817  Final DQS duty delay cell = 0

 2416 23:53:55.703016  [0] MAX Duty = 5187%(X100), DQS PI = 20

 2417 23:53:55.706364  [0] MIN Duty = 4969%(X100), DQS PI = 8

 2418 23:53:55.706493  [0] AVG Duty = 5078%(X100)

 2419 23:53:55.709808  

 2420 23:53:55.713059  CH1 DQS 0 Duty spec in!! Max-Min= 218%

 2421 23:53:55.713168  

 2422 23:53:55.717110  CH1 DQS 1 Duty spec in!! Max-Min= 218%

 2423 23:53:55.720014  [DutyScan_Calibration_Flow] ====Done====

 2424 23:53:55.720098  

 2425 23:53:55.723216  [DutyScan_Calibration_Flow] k_type=3

 2426 23:53:55.739898  

 2427 23:53:55.740052  ==DQM 0 ==

 2428 23:53:55.743392  Final DQM duty delay cell = 0

 2429 23:53:55.746367  [0] MAX Duty = 5187%(X100), DQS PI = 8

 2430 23:53:55.749543  [0] MIN Duty = 5031%(X100), DQS PI = 0

 2431 23:53:55.749675  [0] AVG Duty = 5109%(X100)

 2432 23:53:55.749787  

 2433 23:53:55.752686  ==DQM 1 ==

 2434 23:53:55.756482  Final DQM duty delay cell = 0

 2435 23:53:55.760025  [0] MAX Duty = 5062%(X100), DQS PI = 44

 2436 23:53:55.763052  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2437 23:53:55.763179  [0] AVG Duty = 4984%(X100)

 2438 23:53:55.766333  

 2439 23:53:55.769912  CH1 DQM 0 Duty spec in!! Max-Min= 156%

 2440 23:53:55.770039  

 2441 23:53:55.772899  CH1 DQM 1 Duty spec in!! Max-Min= 155%

 2442 23:53:55.776540  [DutyScan_Calibration_Flow] ====Done====

 2443 23:53:55.776663  

 2444 23:53:55.779851  [DutyScan_Calibration_Flow] k_type=2

 2445 23:53:55.795601  

 2446 23:53:55.795747  ==DQ 0 ==

 2447 23:53:55.798731  Final DQ duty delay cell = -4

 2448 23:53:55.802458  [-4] MAX Duty = 5094%(X100), DQS PI = 10

 2449 23:53:55.805522  [-4] MIN Duty = 4906%(X100), DQS PI = 46

 2450 23:53:55.808540  [-4] AVG Duty = 5000%(X100)

 2451 23:53:55.808625  

 2452 23:53:55.808691  ==DQ 1 ==

 2453 23:53:55.812389  Final DQ duty delay cell = 0

 2454 23:53:55.815362  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2455 23:53:55.818668  [0] MIN Duty = 4969%(X100), DQS PI = 12

 2456 23:53:55.818753  [0] AVG Duty = 5047%(X100)

 2457 23:53:55.822324  

 2458 23:53:55.825513  CH1 DQ 0 Duty spec in!! Max-Min= 188%

 2459 23:53:55.825598  

 2460 23:53:55.828646  CH1 DQ 1 Duty spec in!! Max-Min= 156%

 2461 23:53:55.832320  [DutyScan_Calibration_Flow] ====Done====

 2462 23:53:55.835552  nWR fixed to 30

 2463 23:53:55.835638  [ModeRegInit_LP4] CH0 RK0

 2464 23:53:55.838923  [ModeRegInit_LP4] CH0 RK1

 2465 23:53:55.841950  [ModeRegInit_LP4] CH1 RK0

 2466 23:53:55.846045  [ModeRegInit_LP4] CH1 RK1

 2467 23:53:55.846152  match AC timing 7

 2468 23:53:55.848934  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2469 23:53:55.856133  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2470 23:53:55.859035  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2471 23:53:55.865338  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2472 23:53:55.869078  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2473 23:53:55.869214  ==

 2474 23:53:55.872153  Dram Type= 6, Freq= 0, CH_0, rank 0

 2475 23:53:55.876067  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2476 23:53:55.876195  ==

 2477 23:53:55.882295  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2478 23:53:55.888461  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2479 23:53:55.895762  [CA 0] Center 39 (8~70) winsize 63

 2480 23:53:55.898867  [CA 1] Center 39 (8~70) winsize 63

 2481 23:53:55.902702  [CA 2] Center 35 (5~66) winsize 62

 2482 23:53:55.905886  [CA 3] Center 34 (4~65) winsize 62

 2483 23:53:55.908966  [CA 4] Center 33 (3~64) winsize 62

 2484 23:53:55.912212  [CA 5] Center 32 (3~62) winsize 60

 2485 23:53:55.912296  

 2486 23:53:55.916070  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2487 23:53:55.916154  

 2488 23:53:55.919095  [CATrainingPosCal] consider 1 rank data

 2489 23:53:55.922409  u2DelayCellTimex100 = 270/100 ps

 2490 23:53:55.925991  CA0 delay=39 (8~70),Diff = 7 PI (33 cell)

 2491 23:53:55.929229  CA1 delay=39 (8~70),Diff = 7 PI (33 cell)

 2492 23:53:55.936111  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2493 23:53:55.939016  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2494 23:53:55.942698  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2495 23:53:55.945925  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2496 23:53:55.946010  

 2497 23:53:55.949174  CA PerBit enable=1, Macro0, CA PI delay=32

 2498 23:53:55.949257  

 2499 23:53:55.952746  [CBTSetCACLKResult] CA Dly = 32

 2500 23:53:55.952836  CS Dly: 6 (0~37)

 2501 23:53:55.952904  ==

 2502 23:53:55.955911  Dram Type= 6, Freq= 0, CH_0, rank 1

 2503 23:53:55.962554  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2504 23:53:55.962665  ==

 2505 23:53:55.965553  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2506 23:53:55.972568  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2507 23:53:55.981441  [CA 0] Center 38 (8~69) winsize 62

 2508 23:53:55.985279  [CA 1] Center 38 (8~69) winsize 62

 2509 23:53:55.987768  [CA 2] Center 35 (5~66) winsize 62

 2510 23:53:55.991231  [CA 3] Center 34 (4~65) winsize 62

 2511 23:53:55.994853  [CA 4] Center 33 (3~64) winsize 62

 2512 23:53:55.997860  [CA 5] Center 32 (3~62) winsize 60

 2513 23:53:55.997991  

 2514 23:53:56.001680  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2515 23:53:56.001836  

 2516 23:53:56.004562  [CATrainingPosCal] consider 2 rank data

 2517 23:53:56.008213  u2DelayCellTimex100 = 270/100 ps

 2518 23:53:56.011728  CA0 delay=38 (8~69),Diff = 6 PI (28 cell)

 2519 23:53:56.014928  CA1 delay=38 (8~69),Diff = 6 PI (28 cell)

 2520 23:53:56.021443  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2521 23:53:56.024957  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2522 23:53:56.027989  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2523 23:53:56.031220  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2524 23:53:56.031333  

 2525 23:53:56.034975  CA PerBit enable=1, Macro0, CA PI delay=32

 2526 23:53:56.035059  

 2527 23:53:56.038128  [CBTSetCACLKResult] CA Dly = 32

 2528 23:53:56.038213  CS Dly: 6 (0~38)

 2529 23:53:56.038279  

 2530 23:53:56.041493  ----->DramcWriteLeveling(PI) begin...

 2531 23:53:56.044786  ==

 2532 23:53:56.048133  Dram Type= 6, Freq= 0, CH_0, rank 0

 2533 23:53:56.051536  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2534 23:53:56.051648  ==

 2535 23:53:56.054539  Write leveling (Byte 0): 32 => 32

 2536 23:53:56.058484  Write leveling (Byte 1): 30 => 30

 2537 23:53:56.061709  DramcWriteLeveling(PI) end<-----

 2538 23:53:56.061794  

 2539 23:53:56.061857  ==

 2540 23:53:56.065217  Dram Type= 6, Freq= 0, CH_0, rank 0

 2541 23:53:56.068439  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2542 23:53:56.068526  ==

 2543 23:53:56.071610  [Gating] SW mode calibration

 2544 23:53:56.078784  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2545 23:53:56.081785  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2546 23:53:56.088413   0 15  0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)

 2547 23:53:56.091305   0 15  4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)

 2548 23:53:56.095177   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2549 23:53:56.101280   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2550 23:53:56.104877   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2551 23:53:56.108444   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2552 23:53:56.114742   0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)

 2553 23:53:56.118335   0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)

 2554 23:53:56.121218   1  0  0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)

 2555 23:53:56.128386   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2556 23:53:56.131750   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2557 23:53:56.135356   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2558 23:53:56.141311   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2559 23:53:56.144597   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2560 23:53:56.148664   1  0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)

 2561 23:53:56.155120   1  0 28 | B1->B0 | 2727 4545 | 1 0 | (0 0) (0 0)

 2562 23:53:56.158505   1  1  0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)

 2563 23:53:56.161666   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2564 23:53:56.168180   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2565 23:53:56.171418   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2566 23:53:56.174747   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2567 23:53:56.178318   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2568 23:53:56.184999   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2569 23:53:56.188258   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2570 23:53:56.191783   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2571 23:53:56.198259   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2572 23:53:56.202114   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2573 23:53:56.205023   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2574 23:53:56.211638   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2575 23:53:56.214611   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2576 23:53:56.218348   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2577 23:53:56.224907   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2578 23:53:56.227950   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2579 23:53:56.231281   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2580 23:53:56.238484   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2581 23:53:56.241726   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2582 23:53:56.244915   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2583 23:53:56.251570   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2584 23:53:56.254821   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2585 23:53:56.259069   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2586 23:53:56.262042   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2587 23:53:56.265112  Total UI for P1: 0, mck2ui 16

 2588 23:53:56.268443  best dqsien dly found for B0: ( 1,  3, 26)

 2589 23:53:56.274925   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2590 23:53:56.278293  Total UI for P1: 0, mck2ui 16

 2591 23:53:56.281403  best dqsien dly found for B1: ( 1,  4,  0)

 2592 23:53:56.284778  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2593 23:53:56.288735  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2594 23:53:56.288816  

 2595 23:53:56.291735  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2596 23:53:56.294936  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2597 23:53:56.298833  [Gating] SW calibration Done

 2598 23:53:56.298942  ==

 2599 23:53:56.302442  Dram Type= 6, Freq= 0, CH_0, rank 0

 2600 23:53:56.305160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2601 23:53:56.305244  ==

 2602 23:53:56.308780  RX Vref Scan: 0

 2603 23:53:56.308864  

 2604 23:53:56.308928  RX Vref 0 -> 0, step: 1

 2605 23:53:56.308987  

 2606 23:53:56.311887  RX Delay -40 -> 252, step: 8

 2607 23:53:56.315114  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2608 23:53:56.321979  iDelay=200, Bit 1, Center 123 (48 ~ 199) 152

 2609 23:53:56.325301  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2610 23:53:56.328844  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2611 23:53:56.331887  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2612 23:53:56.335081  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2613 23:53:56.342317  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2614 23:53:56.345168  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2615 23:53:56.348240  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2616 23:53:56.352167  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 2617 23:53:56.355771  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2618 23:53:56.359054  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2619 23:53:56.365165  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2620 23:53:56.368721  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2621 23:53:56.371836  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2622 23:53:56.375037  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 2623 23:53:56.375109  ==

 2624 23:53:56.378925  Dram Type= 6, Freq= 0, CH_0, rank 0

 2625 23:53:56.385592  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2626 23:53:56.385680  ==

 2627 23:53:56.385742  DQS Delay:

 2628 23:53:56.388676  DQS0 = 0, DQS1 = 0

 2629 23:53:56.388746  DQM Delay:

 2630 23:53:56.388804  DQM0 = 121, DQM1 = 113

 2631 23:53:56.392147  DQ Delay:

 2632 23:53:56.395266  DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119

 2633 23:53:56.398853  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2634 23:53:56.402240  DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107

 2635 23:53:56.405271  DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119

 2636 23:53:56.405360  

 2637 23:53:56.405461  

 2638 23:53:56.405524  ==

 2639 23:53:56.408555  Dram Type= 6, Freq= 0, CH_0, rank 0

 2640 23:53:56.412631  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2641 23:53:56.415978  ==

 2642 23:53:56.416084  

 2643 23:53:56.416173  

 2644 23:53:56.416259  	TX Vref Scan disable

 2645 23:53:56.418453   == TX Byte 0 ==

 2646 23:53:56.422205  Update DQ  dly =850 (3 ,2, 18)  DQ  OEN =(2 ,7)

 2647 23:53:56.425168  Update DQM dly =850 (3 ,2, 18)  DQM OEN =(2 ,7)

 2648 23:53:56.428996   == TX Byte 1 ==

 2649 23:53:56.431867  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2650 23:53:56.435800  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2651 23:53:56.435925  ==

 2652 23:53:56.438647  Dram Type= 6, Freq= 0, CH_0, rank 0

 2653 23:53:56.445087  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2654 23:53:56.445210  ==

 2655 23:53:56.455914  TX Vref=22, minBit 0, minWin=25, winSum=410

 2656 23:53:56.459483  TX Vref=24, minBit 0, minWin=25, winSum=413

 2657 23:53:56.462642  TX Vref=26, minBit 1, minWin=25, winSum=420

 2658 23:53:56.466316  TX Vref=28, minBit 0, minWin=26, winSum=427

 2659 23:53:56.469485  TX Vref=30, minBit 0, minWin=26, winSum=428

 2660 23:53:56.472664  TX Vref=32, minBit 12, minWin=25, winSum=418

 2661 23:53:56.479531  [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30

 2662 23:53:56.479656  

 2663 23:53:56.483371  Final TX Range 1 Vref 30

 2664 23:53:56.483490  

 2665 23:53:56.483597  ==

 2666 23:53:56.486461  Dram Type= 6, Freq= 0, CH_0, rank 0

 2667 23:53:56.489660  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2668 23:53:56.489781  ==

 2669 23:53:56.489891  

 2670 23:53:56.490025  

 2671 23:53:56.492842  	TX Vref Scan disable

 2672 23:53:56.496076   == TX Byte 0 ==

 2673 23:53:56.499934  Update DQ  dly =850 (3 ,2, 18)  DQ  OEN =(2 ,7)

 2674 23:53:56.503234  Update DQM dly =850 (3 ,2, 18)  DQM OEN =(2 ,7)

 2675 23:53:56.506479   == TX Byte 1 ==

 2676 23:53:56.509768  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2677 23:53:56.513032  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2678 23:53:56.513154  

 2679 23:53:56.516665  [DATLAT]

 2680 23:53:56.516799  Freq=1200, CH0 RK0

 2681 23:53:56.516925  

 2682 23:53:56.519930  DATLAT Default: 0xd

 2683 23:53:56.520048  0, 0xFFFF, sum = 0

 2684 23:53:56.523222  1, 0xFFFF, sum = 0

 2685 23:53:56.523341  2, 0xFFFF, sum = 0

 2686 23:53:56.526480  3, 0xFFFF, sum = 0

 2687 23:53:56.526600  4, 0xFFFF, sum = 0

 2688 23:53:56.529757  5, 0xFFFF, sum = 0

 2689 23:53:56.529881  6, 0xFFFF, sum = 0

 2690 23:53:56.533085  7, 0xFFFF, sum = 0

 2691 23:53:56.533188  8, 0xFFFF, sum = 0

 2692 23:53:56.536544  9, 0xFFFF, sum = 0

 2693 23:53:56.536642  10, 0xFFFF, sum = 0

 2694 23:53:56.539853  11, 0xFFFF, sum = 0

 2695 23:53:56.539948  12, 0x0, sum = 1

 2696 23:53:56.543274  13, 0x0, sum = 2

 2697 23:53:56.543356  14, 0x0, sum = 3

 2698 23:53:56.546832  15, 0x0, sum = 4

 2699 23:53:56.546914  best_step = 13

 2700 23:53:56.546977  

 2701 23:53:56.547062  ==

 2702 23:53:56.550040  Dram Type= 6, Freq= 0, CH_0, rank 0

 2703 23:53:56.556595  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2704 23:53:56.556677  ==

 2705 23:53:56.556740  RX Vref Scan: 1

 2706 23:53:56.556798  

 2707 23:53:56.560023  Set Vref Range= 32 -> 127

 2708 23:53:56.560103  

 2709 23:53:56.563132  RX Vref 32 -> 127, step: 1

 2710 23:53:56.563212  

 2711 23:53:56.563275  RX Delay -13 -> 252, step: 4

 2712 23:53:56.566293  

 2713 23:53:56.566373  Set Vref, RX VrefLevel [Byte0]: 32

 2714 23:53:56.569961                           [Byte1]: 32

 2715 23:53:56.574450  

 2716 23:53:56.574531  Set Vref, RX VrefLevel [Byte0]: 33

 2717 23:53:56.577615                           [Byte1]: 33

 2718 23:53:56.582395  

 2719 23:53:56.582475  Set Vref, RX VrefLevel [Byte0]: 34

 2720 23:53:56.585441                           [Byte1]: 34

 2721 23:53:56.590265  

 2722 23:53:56.590346  Set Vref, RX VrefLevel [Byte0]: 35

 2723 23:53:56.593380                           [Byte1]: 35

 2724 23:53:56.598305  

 2725 23:53:56.598386  Set Vref, RX VrefLevel [Byte0]: 36

 2726 23:53:56.601540                           [Byte1]: 36

 2727 23:53:56.605631  

 2728 23:53:56.605737  Set Vref, RX VrefLevel [Byte0]: 37

 2729 23:53:56.609185                           [Byte1]: 37

 2730 23:53:56.614352  

 2731 23:53:56.614432  Set Vref, RX VrefLevel [Byte0]: 38

 2732 23:53:56.617317                           [Byte1]: 38

 2733 23:53:56.622067  

 2734 23:53:56.622147  Set Vref, RX VrefLevel [Byte0]: 39

 2735 23:53:56.625056                           [Byte1]: 39

 2736 23:53:56.629666  

 2737 23:53:56.629746  Set Vref, RX VrefLevel [Byte0]: 40

 2738 23:53:56.632910                           [Byte1]: 40

 2739 23:53:56.637577  

 2740 23:53:56.637684  Set Vref, RX VrefLevel [Byte0]: 41

 2741 23:53:56.640671                           [Byte1]: 41

 2742 23:53:56.645077  

 2743 23:53:56.645184  Set Vref, RX VrefLevel [Byte0]: 42

 2744 23:53:56.649339                           [Byte1]: 42

 2745 23:53:56.653546  

 2746 23:53:56.653642  Set Vref, RX VrefLevel [Byte0]: 43

 2747 23:53:56.656656                           [Byte1]: 43

 2748 23:53:56.661221  

 2749 23:53:56.661289  Set Vref, RX VrefLevel [Byte0]: 44

 2750 23:53:56.664083                           [Byte1]: 44

 2751 23:53:56.669254  

 2752 23:53:56.669333  Set Vref, RX VrefLevel [Byte0]: 45

 2753 23:53:56.672590                           [Byte1]: 45

 2754 23:53:56.677125  

 2755 23:53:56.677199  Set Vref, RX VrefLevel [Byte0]: 46

 2756 23:53:56.680257                           [Byte1]: 46

 2757 23:53:56.684752  

 2758 23:53:56.684848  Set Vref, RX VrefLevel [Byte0]: 47

 2759 23:53:56.687854                           [Byte1]: 47

 2760 23:53:56.692336  

 2761 23:53:56.692458  Set Vref, RX VrefLevel [Byte0]: 48

 2762 23:53:56.696405                           [Byte1]: 48

 2763 23:53:56.700524  

 2764 23:53:56.700596  Set Vref, RX VrefLevel [Byte0]: 49

 2765 23:53:56.704155                           [Byte1]: 49

 2766 23:53:56.708908  

 2767 23:53:56.709034  Set Vref, RX VrefLevel [Byte0]: 50

 2768 23:53:56.712244                           [Byte1]: 50

 2769 23:53:56.716070  

 2770 23:53:56.716176  Set Vref, RX VrefLevel [Byte0]: 51

 2771 23:53:56.719450                           [Byte1]: 51

 2772 23:53:56.724353  

 2773 23:53:56.724447  Set Vref, RX VrefLevel [Byte0]: 52

 2774 23:53:56.727615                           [Byte1]: 52

 2775 23:53:56.732168  

 2776 23:53:56.732248  Set Vref, RX VrefLevel [Byte0]: 53

 2777 23:53:56.735530                           [Byte1]: 53

 2778 23:53:56.740214  

 2779 23:53:56.740294  Set Vref, RX VrefLevel [Byte0]: 54

 2780 23:53:56.743571                           [Byte1]: 54

 2781 23:53:56.747945  

 2782 23:53:56.748038  Set Vref, RX VrefLevel [Byte0]: 55

 2783 23:53:56.751014                           [Byte1]: 55

 2784 23:53:56.755913  

 2785 23:53:56.755994  Set Vref, RX VrefLevel [Byte0]: 56

 2786 23:53:56.758894                           [Byte1]: 56

 2787 23:53:56.763479  

 2788 23:53:56.763559  Set Vref, RX VrefLevel [Byte0]: 57

 2789 23:53:56.766947                           [Byte1]: 57

 2790 23:53:56.771805  

 2791 23:53:56.771884  Set Vref, RX VrefLevel [Byte0]: 58

 2792 23:53:56.774819                           [Byte1]: 58

 2793 23:53:56.779323  

 2794 23:53:56.782628  Set Vref, RX VrefLevel [Byte0]: 59

 2795 23:53:56.786111                           [Byte1]: 59

 2796 23:53:56.786194  

 2797 23:53:56.789015  Set Vref, RX VrefLevel [Byte0]: 60

 2798 23:53:56.792786                           [Byte1]: 60

 2799 23:53:56.792895  

 2800 23:53:56.796101  Set Vref, RX VrefLevel [Byte0]: 61

 2801 23:53:56.799387                           [Byte1]: 61

 2802 23:53:56.803244  

 2803 23:53:56.803347  Set Vref, RX VrefLevel [Byte0]: 62

 2804 23:53:56.806511                           [Byte1]: 62

 2805 23:53:56.811063  

 2806 23:53:56.811181  Set Vref, RX VrefLevel [Byte0]: 63

 2807 23:53:56.814222                           [Byte1]: 63

 2808 23:53:56.819046  

 2809 23:53:56.819162  Set Vref, RX VrefLevel [Byte0]: 64

 2810 23:53:56.822630                           [Byte1]: 64

 2811 23:53:56.826974  

 2812 23:53:56.827045  Set Vref, RX VrefLevel [Byte0]: 65

 2813 23:53:56.830303                           [Byte1]: 65

 2814 23:53:56.835270  

 2815 23:53:56.835352  Set Vref, RX VrefLevel [Byte0]: 66

 2816 23:53:56.838069                           [Byte1]: 66

 2817 23:53:56.842615  

 2818 23:53:56.842697  Set Vref, RX VrefLevel [Byte0]: 67

 2819 23:53:56.845624                           [Byte1]: 67

 2820 23:53:56.850202  

 2821 23:53:56.850300  Set Vref, RX VrefLevel [Byte0]: 68

 2822 23:53:56.853683                           [Byte1]: 68

 2823 23:53:56.858630  

 2824 23:53:56.858705  Set Vref, RX VrefLevel [Byte0]: 69

 2825 23:53:56.861641                           [Byte1]: 69

 2826 23:53:56.866221  

 2827 23:53:56.866303  Final RX Vref Byte 0 = 54 to rank0

 2828 23:53:56.869639  Final RX Vref Byte 1 = 48 to rank0

 2829 23:53:56.872783  Final RX Vref Byte 0 = 54 to rank1

 2830 23:53:56.876048  Final RX Vref Byte 1 = 48 to rank1==

 2831 23:53:56.880061  Dram Type= 6, Freq= 0, CH_0, rank 0

 2832 23:53:56.883008  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2833 23:53:56.886069  ==

 2834 23:53:56.886151  DQS Delay:

 2835 23:53:56.886214  DQS0 = 0, DQS1 = 0

 2836 23:53:56.889359  DQM Delay:

 2837 23:53:56.889465  DQM0 = 120, DQM1 = 111

 2838 23:53:56.893271  DQ Delay:

 2839 23:53:56.896446  DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118

 2840 23:53:56.899608  DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128

 2841 23:53:56.902847  DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106

 2842 23:53:56.906038  DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120

 2843 23:53:56.906167  

 2844 23:53:56.906250  

 2845 23:53:56.913475  [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps

 2846 23:53:56.916488  CH0 RK0: MR19=404, MR18=1610

 2847 23:53:56.922946  CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27

 2848 23:53:56.923027  

 2849 23:53:56.926061  ----->DramcWriteLeveling(PI) begin...

 2850 23:53:56.926147  ==

 2851 23:53:56.929720  Dram Type= 6, Freq= 0, CH_0, rank 1

 2852 23:53:56.933359  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2853 23:53:56.936267  ==

 2854 23:53:56.936424  Write leveling (Byte 0): 32 => 32

 2855 23:53:56.939740  Write leveling (Byte 1): 28 => 28

 2856 23:53:56.942814  DramcWriteLeveling(PI) end<-----

 2857 23:53:56.942909  

 2858 23:53:56.942972  ==

 2859 23:53:56.946056  Dram Type= 6, Freq= 0, CH_0, rank 1

 2860 23:53:56.953198  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2861 23:53:56.953315  ==

 2862 23:53:56.953378  [Gating] SW mode calibration

 2863 23:53:56.962706  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2864 23:53:56.966296  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2865 23:53:56.969917   0 15  0 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (0 0)

 2866 23:53:56.976464   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2867 23:53:56.979436   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2868 23:53:56.983147   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2869 23:53:56.989757   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2870 23:53:56.993307   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2871 23:53:56.996620   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 2872 23:53:57.002850   0 15 28 | B1->B0 | 3131 2f2f | 0 0 | (1 0) (0 0)

 2873 23:53:57.006423   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2874 23:53:57.009937   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2875 23:53:57.016326   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2876 23:53:57.019879   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2877 23:53:57.023524   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2878 23:53:57.030259   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2879 23:53:57.033244   1  0 24 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)

 2880 23:53:57.036954   1  0 28 | B1->B0 | 3b3b 3b3b | 0 1 | (0 0) (0 0)

 2881 23:53:57.039970   1  1  0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)

 2882 23:53:57.046757   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2883 23:53:57.050160   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2884 23:53:57.053349   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2885 23:53:57.060095   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2886 23:53:57.063156   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2887 23:53:57.066438   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2888 23:53:57.073384   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2889 23:53:57.076854   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2890 23:53:57.079822   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2891 23:53:57.086562   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2892 23:53:57.089904   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2893 23:53:57.093122   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2894 23:53:57.100202   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2895 23:53:57.103379   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2896 23:53:57.106508   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2897 23:53:57.113282   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2898 23:53:57.116929   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2899 23:53:57.119713   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2900 23:53:57.127037   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2901 23:53:57.130189   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2902 23:53:57.133598   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2903 23:53:57.136990   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2904 23:53:57.143114   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2905 23:53:57.146801   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 2906 23:53:57.149781  Total UI for P1: 0, mck2ui 16

 2907 23:53:57.153370  best dqsien dly found for B1: ( 1,  3, 28)

 2908 23:53:57.156509   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2909 23:53:57.160025  Total UI for P1: 0, mck2ui 16

 2910 23:53:57.163050  best dqsien dly found for B0: ( 1,  3, 30)

 2911 23:53:57.166413  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2912 23:53:57.169660  best DQS1 dly(MCK, UI, PI) = (1, 3, 28)

 2913 23:53:57.169784  

 2914 23:53:57.176723  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2915 23:53:57.180111  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2916 23:53:57.183316  [Gating] SW calibration Done

 2917 23:53:57.183440  ==

 2918 23:53:57.186379  Dram Type= 6, Freq= 0, CH_0, rank 1

 2919 23:53:57.190015  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2920 23:53:57.190136  ==

 2921 23:53:57.190248  RX Vref Scan: 0

 2922 23:53:57.190354  

 2923 23:53:57.193100  RX Vref 0 -> 0, step: 1

 2924 23:53:57.193215  

 2925 23:53:57.196483  RX Delay -40 -> 252, step: 8

 2926 23:53:57.199557  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2927 23:53:57.203416  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2928 23:53:57.210016  iDelay=200, Bit 2, Center 123 (56 ~ 191) 136

 2929 23:53:57.213395  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2930 23:53:57.216299  iDelay=200, Bit 4, Center 127 (56 ~ 199) 144

 2931 23:53:57.219891  iDelay=200, Bit 5, Center 119 (48 ~ 191) 144

 2932 23:53:57.223524  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2933 23:53:57.226629  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2934 23:53:57.233437  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2935 23:53:57.237129  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 2936 23:53:57.239780  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2937 23:53:57.243039  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 2938 23:53:57.246500  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2939 23:53:57.252998  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 2940 23:53:57.256679  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2941 23:53:57.260096  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 2942 23:53:57.260219  ==

 2943 23:53:57.262994  Dram Type= 6, Freq= 0, CH_0, rank 1

 2944 23:53:57.266806  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2945 23:53:57.270314  ==

 2946 23:53:57.270433  DQS Delay:

 2947 23:53:57.270536  DQS0 = 0, DQS1 = 0

 2948 23:53:57.273273  DQM Delay:

 2949 23:53:57.273390  DQM0 = 122, DQM1 = 112

 2950 23:53:57.276576  DQ Delay:

 2951 23:53:57.280457  DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119

 2952 23:53:57.283795  DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127

 2953 23:53:57.286920  DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103

 2954 23:53:57.290180  DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123

 2955 23:53:57.290270  

 2956 23:53:57.290347  

 2957 23:53:57.290404  ==

 2958 23:53:57.293442  Dram Type= 6, Freq= 0, CH_0, rank 1

 2959 23:53:57.296813  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2960 23:53:57.296896  ==

 2961 23:53:57.296959  

 2962 23:53:57.297017  

 2963 23:53:57.300060  	TX Vref Scan disable

 2964 23:53:57.303391   == TX Byte 0 ==

 2965 23:53:57.306431  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2966 23:53:57.310420  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2967 23:53:57.313507   == TX Byte 1 ==

 2968 23:53:57.316744  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2969 23:53:57.319956  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2970 23:53:57.320024  ==

 2971 23:53:57.323485  Dram Type= 6, Freq= 0, CH_0, rank 1

 2972 23:53:57.326472  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2973 23:53:57.329798  ==

 2974 23:53:57.340789  TX Vref=22, minBit 1, minWin=25, winSum=421

 2975 23:53:57.344028  TX Vref=24, minBit 1, minWin=25, winSum=424

 2976 23:53:57.347264  TX Vref=26, minBit 0, minWin=26, winSum=426

 2977 23:53:57.350230  TX Vref=28, minBit 0, minWin=26, winSum=427

 2978 23:53:57.353934  TX Vref=30, minBit 1, minWin=26, winSum=435

 2979 23:53:57.356839  TX Vref=32, minBit 0, minWin=26, winSum=429

 2980 23:53:57.364050  [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 30

 2981 23:53:57.364165  

 2982 23:53:57.367121  Final TX Range 1 Vref 30

 2983 23:53:57.367225  

 2984 23:53:57.367320  ==

 2985 23:53:57.370527  Dram Type= 6, Freq= 0, CH_0, rank 1

 2986 23:53:57.374024  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2987 23:53:57.374126  ==

 2988 23:53:57.374201  

 2989 23:53:57.374292  

 2990 23:53:57.377264  	TX Vref Scan disable

 2991 23:53:57.380688   == TX Byte 0 ==

 2992 23:53:57.384049  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2993 23:53:57.387300  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2994 23:53:57.390464   == TX Byte 1 ==

 2995 23:53:57.394284  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 2996 23:53:57.397151  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 2997 23:53:57.397247  

 2998 23:53:57.400983  [DATLAT]

 2999 23:53:57.401125  Freq=1200, CH0 RK1

 3000 23:53:57.401251  

 3001 23:53:57.403853  DATLAT Default: 0xd

 3002 23:53:57.403985  0, 0xFFFF, sum = 0

 3003 23:53:57.407776  1, 0xFFFF, sum = 0

 3004 23:53:57.407873  2, 0xFFFF, sum = 0

 3005 23:53:57.411092  3, 0xFFFF, sum = 0

 3006 23:53:57.411261  4, 0xFFFF, sum = 0

 3007 23:53:57.414140  5, 0xFFFF, sum = 0

 3008 23:53:57.414259  6, 0xFFFF, sum = 0

 3009 23:53:57.417368  7, 0xFFFF, sum = 0

 3010 23:53:57.417456  8, 0xFFFF, sum = 0

 3011 23:53:57.420561  9, 0xFFFF, sum = 0

 3012 23:53:57.420639  10, 0xFFFF, sum = 0

 3013 23:53:57.424060  11, 0xFFFF, sum = 0

 3014 23:53:57.424158  12, 0x0, sum = 1

 3015 23:53:57.427184  13, 0x0, sum = 2

 3016 23:53:57.427282  14, 0x0, sum = 3

 3017 23:53:57.431104  15, 0x0, sum = 4

 3018 23:53:57.431203  best_step = 13

 3019 23:53:57.431288  

 3020 23:53:57.431372  ==

 3021 23:53:57.434412  Dram Type= 6, Freq= 0, CH_0, rank 1

 3022 23:53:57.441068  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3023 23:53:57.441170  ==

 3024 23:53:57.441259  RX Vref Scan: 0

 3025 23:53:57.441344  

 3026 23:53:57.444476  RX Vref 0 -> 0, step: 1

 3027 23:53:57.444550  

 3028 23:53:57.447305  RX Delay -13 -> 252, step: 4

 3029 23:53:57.451301  iDelay=195, Bit 0, Center 118 (51 ~ 186) 136

 3030 23:53:57.454352  iDelay=195, Bit 1, Center 120 (55 ~ 186) 132

 3031 23:53:57.461189  iDelay=195, Bit 2, Center 118 (51 ~ 186) 136

 3032 23:53:57.464134  iDelay=195, Bit 3, Center 118 (51 ~ 186) 136

 3033 23:53:57.467338  iDelay=195, Bit 4, Center 122 (55 ~ 190) 136

 3034 23:53:57.470499  iDelay=195, Bit 5, Center 116 (51 ~ 182) 132

 3035 23:53:57.474378  iDelay=195, Bit 6, Center 128 (63 ~ 194) 132

 3036 23:53:57.477315  iDelay=195, Bit 7, Center 128 (63 ~ 194) 132

 3037 23:53:57.484200  iDelay=195, Bit 8, Center 100 (35 ~ 166) 132

 3038 23:53:57.487394  iDelay=195, Bit 9, Center 96 (31 ~ 162) 132

 3039 23:53:57.490809  iDelay=195, Bit 10, Center 110 (47 ~ 174) 128

 3040 23:53:57.493873  iDelay=195, Bit 11, Center 102 (39 ~ 166) 128

 3041 23:53:57.497624  iDelay=195, Bit 12, Center 114 (51 ~ 178) 128

 3042 23:53:57.504401  iDelay=195, Bit 13, Center 114 (51 ~ 178) 128

 3043 23:53:57.507549  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3044 23:53:57.511332  iDelay=195, Bit 15, Center 120 (55 ~ 186) 132

 3045 23:53:57.511439  ==

 3046 23:53:57.514346  Dram Type= 6, Freq= 0, CH_0, rank 1

 3047 23:53:57.518293  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3048 23:53:57.518399  ==

 3049 23:53:57.521169  DQS Delay:

 3050 23:53:57.521245  DQS0 = 0, DQS1 = 0

 3051 23:53:57.524579  DQM Delay:

 3052 23:53:57.524653  DQM0 = 121, DQM1 = 109

 3053 23:53:57.524714  DQ Delay:

 3054 23:53:57.531077  DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118

 3055 23:53:57.534560  DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128

 3056 23:53:57.537761  DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102

 3057 23:53:57.540891  DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =120

 3058 23:53:57.540970  

 3059 23:53:57.541033  

 3060 23:53:57.548130  [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps

 3061 23:53:57.551283  CH0 RK1: MR19=403, MR18=DEE

 3062 23:53:57.557912  CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26

 3063 23:53:57.561389  [RxdqsGatingPostProcess] freq 1200

 3064 23:53:57.564445  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3065 23:53:57.567695  best DQS0 dly(2T, 0.5T) = (0, 11)

 3066 23:53:57.571540  best DQS1 dly(2T, 0.5T) = (0, 12)

 3067 23:53:57.574629  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3068 23:53:57.577987  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3069 23:53:57.581215  best DQS0 dly(2T, 0.5T) = (0, 11)

 3070 23:53:57.584466  best DQS1 dly(2T, 0.5T) = (0, 11)

 3071 23:53:57.588205  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3072 23:53:57.591376  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3073 23:53:57.594639  Pre-setting of DQS Precalculation

 3074 23:53:57.597927  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3075 23:53:57.598025  ==

 3076 23:53:57.601318  Dram Type= 6, Freq= 0, CH_1, rank 0

 3077 23:53:57.608161  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3078 23:53:57.608263  ==

 3079 23:53:57.611477  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3080 23:53:57.618097  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3081 23:53:57.626678  [CA 0] Center 37 (7~68) winsize 62

 3082 23:53:57.629849  [CA 1] Center 37 (7~68) winsize 62

 3083 23:53:57.633118  [CA 2] Center 35 (5~65) winsize 61

 3084 23:53:57.636298  [CA 3] Center 34 (4~64) winsize 61

 3085 23:53:57.639481  [CA 4] Center 34 (4~64) winsize 61

 3086 23:53:57.643014  [CA 5] Center 33 (3~63) winsize 61

 3087 23:53:57.643094  

 3088 23:53:57.646388  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3089 23:53:57.646470  

 3090 23:53:57.649592  [CATrainingPosCal] consider 1 rank data

 3091 23:53:57.652688  u2DelayCellTimex100 = 270/100 ps

 3092 23:53:57.656408  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3093 23:53:57.659762  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3094 23:53:57.666540  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3095 23:53:57.669336  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3096 23:53:57.673088  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3097 23:53:57.676119  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3098 23:53:57.676220  

 3099 23:53:57.679678  CA PerBit enable=1, Macro0, CA PI delay=33

 3100 23:53:57.679829  

 3101 23:53:57.683092  [CBTSetCACLKResult] CA Dly = 33

 3102 23:53:57.683184  CS Dly: 7 (0~38)

 3103 23:53:57.686135  ==

 3104 23:53:57.686216  Dram Type= 6, Freq= 0, CH_1, rank 1

 3105 23:53:57.693258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3106 23:53:57.693340  ==

 3107 23:53:57.696572  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3108 23:53:57.703148  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3109 23:53:57.712309  [CA 0] Center 37 (7~68) winsize 62

 3110 23:53:57.715574  [CA 1] Center 37 (7~68) winsize 62

 3111 23:53:57.718753  [CA 2] Center 35 (5~65) winsize 61

 3112 23:53:57.722017  [CA 3] Center 34 (4~65) winsize 62

 3113 23:53:57.725341  [CA 4] Center 34 (4~65) winsize 62

 3114 23:53:57.728528  [CA 5] Center 34 (4~64) winsize 61

 3115 23:53:57.728608  

 3116 23:53:57.731939  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3117 23:53:57.732037  

 3118 23:53:57.735141  [CATrainingPosCal] consider 2 rank data

 3119 23:53:57.738421  u2DelayCellTimex100 = 270/100 ps

 3120 23:53:57.741795  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3121 23:53:57.748331  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3122 23:53:57.751594  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3123 23:53:57.755159  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3124 23:53:57.758236  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3125 23:53:57.761947  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3126 23:53:57.762020  

 3127 23:53:57.765066  CA PerBit enable=1, Macro0, CA PI delay=33

 3128 23:53:57.765138  

 3129 23:53:57.768261  [CBTSetCACLKResult] CA Dly = 33

 3130 23:53:57.768366  CS Dly: 8 (0~41)

 3131 23:53:57.768430  

 3132 23:53:57.771974  ----->DramcWriteLeveling(PI) begin...

 3133 23:53:57.774987  ==

 3134 23:53:57.778711  Dram Type= 6, Freq= 0, CH_1, rank 0

 3135 23:53:57.781602  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3136 23:53:57.781686  ==

 3137 23:53:57.785146  Write leveling (Byte 0): 26 => 26

 3138 23:53:57.788368  Write leveling (Byte 1): 28 => 28

 3139 23:53:57.791984  DramcWriteLeveling(PI) end<-----

 3140 23:53:57.792066  

 3141 23:53:57.792129  ==

 3142 23:53:57.794830  Dram Type= 6, Freq= 0, CH_1, rank 0

 3143 23:53:57.798620  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3144 23:53:57.798704  ==

 3145 23:53:57.801810  [Gating] SW mode calibration

 3146 23:53:57.808316  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3147 23:53:57.812098  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3148 23:53:57.818587   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3149 23:53:57.822007   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3150 23:53:57.825072   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3151 23:53:57.832156   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3152 23:53:57.835498   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3153 23:53:57.839080   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3154 23:53:57.845235   0 15 24 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (0 0)

 3155 23:53:57.848738   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 3156 23:53:57.851827   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3157 23:53:57.858484   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3158 23:53:57.861810   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3159 23:53:57.865753   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3160 23:53:57.871905   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3161 23:53:57.875136   1  0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3162 23:53:57.878326   1  0 24 | B1->B0 | 3333 4040 | 0 0 | (1 1) (0 0)

 3163 23:53:57.885855   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3164 23:53:57.889139   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3165 23:53:57.892053   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3166 23:53:57.895398   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3167 23:53:57.902146   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3168 23:53:57.905754   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3169 23:53:57.908756   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3170 23:53:57.915219   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3171 23:53:57.918588   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3172 23:53:57.922195   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3173 23:53:57.928845   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3174 23:53:57.932074   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3175 23:53:57.935437   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3176 23:53:57.941782   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3177 23:53:57.945134   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3178 23:53:57.948710   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3179 23:53:57.955542   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3180 23:53:57.958503   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3181 23:53:57.962436   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3182 23:53:57.968722   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3183 23:53:57.971898   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3184 23:53:57.975596   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3185 23:53:57.981974   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3186 23:53:57.985241   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3187 23:53:57.988559   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3188 23:53:57.992134   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3189 23:53:57.995858  Total UI for P1: 0, mck2ui 16

 3190 23:53:57.998544  best dqsien dly found for B0: ( 1,  3, 24)

 3191 23:53:58.002573  Total UI for P1: 0, mck2ui 16

 3192 23:53:58.005703  best dqsien dly found for B1: ( 1,  3, 26)

 3193 23:53:58.008824  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3194 23:53:58.012154  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3195 23:53:58.012277  

 3196 23:53:58.019477  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3197 23:53:58.022555  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3198 23:53:58.025507  [Gating] SW calibration Done

 3199 23:53:58.025603  ==

 3200 23:53:58.029025  Dram Type= 6, Freq= 0, CH_1, rank 0

 3201 23:53:58.032296  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3202 23:53:58.032444  ==

 3203 23:53:58.032535  RX Vref Scan: 0

 3204 23:53:58.032622  

 3205 23:53:58.035544  RX Vref 0 -> 0, step: 1

 3206 23:53:58.035642  

 3207 23:53:58.039040  RX Delay -40 -> 252, step: 8

 3208 23:53:58.042073  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3209 23:53:58.045573  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3210 23:53:58.052170  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3211 23:53:58.055704  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3212 23:53:58.058447  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3213 23:53:58.061815  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3214 23:53:58.065820  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3215 23:53:58.068621  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3216 23:53:58.075333  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3217 23:53:58.078752  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3218 23:53:58.082222  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3219 23:53:58.085637  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3220 23:53:58.088761  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3221 23:53:58.095736  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3222 23:53:58.098640  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3223 23:53:58.101996  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3224 23:53:58.102121  ==

 3225 23:53:58.106295  Dram Type= 6, Freq= 0, CH_1, rank 0

 3226 23:53:58.108892  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3227 23:53:58.112690  ==

 3228 23:53:58.112772  DQS Delay:

 3229 23:53:58.112837  DQS0 = 0, DQS1 = 0

 3230 23:53:58.115572  DQM Delay:

 3231 23:53:58.115674  DQM0 = 120, DQM1 = 116

 3232 23:53:58.118865  DQ Delay:

 3233 23:53:58.122579  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3234 23:53:58.125823  DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123

 3235 23:53:58.129282  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111

 3236 23:53:58.132116  DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123

 3237 23:53:58.132242  

 3238 23:53:58.132366  

 3239 23:53:58.132479  ==

 3240 23:53:58.135819  Dram Type= 6, Freq= 0, CH_1, rank 0

 3241 23:53:58.139401  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3242 23:53:58.139530  ==

 3243 23:53:58.139647  

 3244 23:53:58.139753  

 3245 23:53:58.142390  	TX Vref Scan disable

 3246 23:53:58.145486   == TX Byte 0 ==

 3247 23:53:58.149035  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3248 23:53:58.152210  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3249 23:53:58.156060   == TX Byte 1 ==

 3250 23:53:58.159342  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3251 23:53:58.162340  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3252 23:53:58.162463  ==

 3253 23:53:58.166174  Dram Type= 6, Freq= 0, CH_1, rank 0

 3254 23:53:58.168949  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3255 23:53:58.172631  ==

 3256 23:53:58.182119  TX Vref=22, minBit 1, minWin=25, winSum=412

 3257 23:53:58.185712  TX Vref=24, minBit 9, minWin=24, winSum=420

 3258 23:53:58.189102  TX Vref=26, minBit 9, minWin=25, winSum=425

 3259 23:53:58.192826  TX Vref=28, minBit 9, minWin=25, winSum=427

 3260 23:53:58.195613  TX Vref=30, minBit 2, minWin=26, winSum=430

 3261 23:53:58.199272  TX Vref=32, minBit 9, minWin=26, winSum=431

 3262 23:53:58.205643  [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 32

 3263 23:53:58.205724  

 3264 23:53:58.208737  Final TX Range 1 Vref 32

 3265 23:53:58.208843  

 3266 23:53:58.208943  ==

 3267 23:53:58.212447  Dram Type= 6, Freq= 0, CH_1, rank 0

 3268 23:53:58.215702  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3269 23:53:58.215811  ==

 3270 23:53:58.215902  

 3271 23:53:58.215988  

 3272 23:53:58.218795  	TX Vref Scan disable

 3273 23:53:58.222727   == TX Byte 0 ==

 3274 23:53:58.225857  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3275 23:53:58.229147  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3276 23:53:58.232560   == TX Byte 1 ==

 3277 23:53:58.235806  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3278 23:53:58.239476  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3279 23:53:58.239578  

 3280 23:53:58.242687  [DATLAT]

 3281 23:53:58.242786  Freq=1200, CH1 RK0

 3282 23:53:58.242886  

 3283 23:53:58.245979  DATLAT Default: 0xd

 3284 23:53:58.246086  0, 0xFFFF, sum = 0

 3285 23:53:58.249019  1, 0xFFFF, sum = 0

 3286 23:53:58.249093  2, 0xFFFF, sum = 0

 3287 23:53:58.252975  3, 0xFFFF, sum = 0

 3288 23:53:58.253050  4, 0xFFFF, sum = 0

 3289 23:53:58.256165  5, 0xFFFF, sum = 0

 3290 23:53:58.256239  6, 0xFFFF, sum = 0

 3291 23:53:58.259410  7, 0xFFFF, sum = 0

 3292 23:53:58.259508  8, 0xFFFF, sum = 0

 3293 23:53:58.262743  9, 0xFFFF, sum = 0

 3294 23:53:58.262840  10, 0xFFFF, sum = 0

 3295 23:53:58.266024  11, 0xFFFF, sum = 0

 3296 23:53:58.266124  12, 0x0, sum = 1

 3297 23:53:58.269510  13, 0x0, sum = 2

 3298 23:53:58.269581  14, 0x0, sum = 3

 3299 23:53:58.272560  15, 0x0, sum = 4

 3300 23:53:58.272657  best_step = 13

 3301 23:53:58.272744  

 3302 23:53:58.272839  ==

 3303 23:53:58.275826  Dram Type= 6, Freq= 0, CH_1, rank 0

 3304 23:53:58.282675  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3305 23:53:58.282775  ==

 3306 23:53:58.282874  RX Vref Scan: 1

 3307 23:53:58.282960  

 3308 23:53:58.286142  Set Vref Range= 32 -> 127

 3309 23:53:58.286212  

 3310 23:53:58.289070  RX Vref 32 -> 127, step: 1

 3311 23:53:58.289166  

 3312 23:53:58.289264  RX Delay -5 -> 252, step: 4

 3313 23:53:58.292479  

 3314 23:53:58.292551  Set Vref, RX VrefLevel [Byte0]: 32

 3315 23:53:58.295655                           [Byte1]: 32

 3316 23:53:58.301056  

 3317 23:53:58.301153  Set Vref, RX VrefLevel [Byte0]: 33

 3318 23:53:58.303933                           [Byte1]: 33

 3319 23:53:58.307860  

 3320 23:53:58.307965  Set Vref, RX VrefLevel [Byte0]: 34

 3321 23:53:58.311889                           [Byte1]: 34

 3322 23:53:58.316247  

 3323 23:53:58.316353  Set Vref, RX VrefLevel [Byte0]: 35

 3324 23:53:58.319363                           [Byte1]: 35

 3325 23:53:58.323982  

 3326 23:53:58.324080  Set Vref, RX VrefLevel [Byte0]: 36

 3327 23:53:58.327222                           [Byte1]: 36

 3328 23:53:58.331960  

 3329 23:53:58.332068  Set Vref, RX VrefLevel [Byte0]: 37

 3330 23:53:58.334896                           [Byte1]: 37

 3331 23:53:58.339525  

 3332 23:53:58.339646  Set Vref, RX VrefLevel [Byte0]: 38

 3333 23:53:58.342685                           [Byte1]: 38

 3334 23:53:58.347385  

 3335 23:53:58.347505  Set Vref, RX VrefLevel [Byte0]: 39

 3336 23:53:58.351077                           [Byte1]: 39

 3337 23:53:58.355458  

 3338 23:53:58.355562  Set Vref, RX VrefLevel [Byte0]: 40

 3339 23:53:58.358668                           [Byte1]: 40

 3340 23:53:58.363202  

 3341 23:53:58.363317  Set Vref, RX VrefLevel [Byte0]: 41

 3342 23:53:58.366357                           [Byte1]: 41

 3343 23:53:58.371083  

 3344 23:53:58.371163  Set Vref, RX VrefLevel [Byte0]: 42

 3345 23:53:58.374679                           [Byte1]: 42

 3346 23:53:58.379223  

 3347 23:53:58.379302  Set Vref, RX VrefLevel [Byte0]: 43

 3348 23:53:58.382393                           [Byte1]: 43

 3349 23:53:58.386794  

 3350 23:53:58.386917  Set Vref, RX VrefLevel [Byte0]: 44

 3351 23:53:58.389833                           [Byte1]: 44

 3352 23:53:58.394331  

 3353 23:53:58.394450  Set Vref, RX VrefLevel [Byte0]: 45

 3354 23:53:58.398370                           [Byte1]: 45

 3355 23:53:58.402361  

 3356 23:53:58.402479  Set Vref, RX VrefLevel [Byte0]: 46

 3357 23:53:58.405596                           [Byte1]: 46

 3358 23:53:58.410083  

 3359 23:53:58.410205  Set Vref, RX VrefLevel [Byte0]: 47

 3360 23:53:58.413373                           [Byte1]: 47

 3361 23:53:58.418066  

 3362 23:53:58.418147  Set Vref, RX VrefLevel [Byte0]: 48

 3363 23:53:58.421396                           [Byte1]: 48

 3364 23:53:58.426022  

 3365 23:53:58.426102  Set Vref, RX VrefLevel [Byte0]: 49

 3366 23:53:58.429259                           [Byte1]: 49

 3367 23:53:58.433720  

 3368 23:53:58.433800  Set Vref, RX VrefLevel [Byte0]: 50

 3369 23:53:58.436842                           [Byte1]: 50

 3370 23:53:58.441739  

 3371 23:53:58.441845  Set Vref, RX VrefLevel [Byte0]: 51

 3372 23:53:58.444877                           [Byte1]: 51

 3373 23:53:58.449775  

 3374 23:53:58.449855  Set Vref, RX VrefLevel [Byte0]: 52

 3375 23:53:58.452903                           [Byte1]: 52

 3376 23:53:58.457284  

 3377 23:53:58.457366  Set Vref, RX VrefLevel [Byte0]: 53

 3378 23:53:58.463675                           [Byte1]: 53

 3379 23:53:58.463753  

 3380 23:53:58.467276  Set Vref, RX VrefLevel [Byte0]: 54

 3381 23:53:58.470721                           [Byte1]: 54

 3382 23:53:58.470850  

 3383 23:53:58.474310  Set Vref, RX VrefLevel [Byte0]: 55

 3384 23:53:58.476905                           [Byte1]: 55

 3385 23:53:58.481287  

 3386 23:53:58.481433  Set Vref, RX VrefLevel [Byte0]: 56

 3387 23:53:58.484095                           [Byte1]: 56

 3388 23:53:58.488532  

 3389 23:53:58.488681  Set Vref, RX VrefLevel [Byte0]: 57

 3390 23:53:58.492212                           [Byte1]: 57

 3391 23:53:58.496402  

 3392 23:53:58.496547  Set Vref, RX VrefLevel [Byte0]: 58

 3393 23:53:58.500046                           [Byte1]: 58

 3394 23:53:58.504474  

 3395 23:53:58.504583  Set Vref, RX VrefLevel [Byte0]: 59

 3396 23:53:58.507755                           [Byte1]: 59

 3397 23:53:58.512503  

 3398 23:53:58.512588  Set Vref, RX VrefLevel [Byte0]: 60

 3399 23:53:58.515890                           [Byte1]: 60

 3400 23:53:58.520285  

 3401 23:53:58.520376  Set Vref, RX VrefLevel [Byte0]: 61

 3402 23:53:58.523453                           [Byte1]: 61

 3403 23:53:58.528266  

 3404 23:53:58.528355  Set Vref, RX VrefLevel [Byte0]: 62

 3405 23:53:58.531690                           [Byte1]: 62

 3406 23:53:58.535983  

 3407 23:53:58.536111  Set Vref, RX VrefLevel [Byte0]: 63

 3408 23:53:58.539248                           [Byte1]: 63

 3409 23:53:58.543743  

 3410 23:53:58.543872  Set Vref, RX VrefLevel [Byte0]: 64

 3411 23:53:58.550119                           [Byte1]: 64

 3412 23:53:58.551633  

 3413 23:53:58.551718  Set Vref, RX VrefLevel [Byte0]: 65

 3414 23:53:58.554888                           [Byte1]: 65

 3415 23:53:58.559650  

 3416 23:53:58.559767  Set Vref, RX VrefLevel [Byte0]: 66

 3417 23:53:58.562638                           [Byte1]: 66

 3418 23:53:58.567344  

 3419 23:53:58.567485  Set Vref, RX VrefLevel [Byte0]: 67

 3420 23:53:58.570480                           [Byte1]: 67

 3421 23:53:58.574947  

 3422 23:53:58.575085  Set Vref, RX VrefLevel [Byte0]: 68

 3423 23:53:58.578645                           [Byte1]: 68

 3424 23:53:58.582789  

 3425 23:53:58.582978  Set Vref, RX VrefLevel [Byte0]: 69

 3426 23:53:58.586642                           [Byte1]: 69

 3427 23:53:58.591023  

 3428 23:53:58.591147  Final RX Vref Byte 0 = 54 to rank0

 3429 23:53:58.594384  Final RX Vref Byte 1 = 48 to rank0

 3430 23:53:58.597307  Final RX Vref Byte 0 = 54 to rank1

 3431 23:53:58.601115  Final RX Vref Byte 1 = 48 to rank1==

 3432 23:53:58.604197  Dram Type= 6, Freq= 0, CH_1, rank 0

 3433 23:53:58.610754  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3434 23:53:58.610955  ==

 3435 23:53:58.611116  DQS Delay:

 3436 23:53:58.611236  DQS0 = 0, DQS1 = 0

 3437 23:53:58.614064  DQM Delay:

 3438 23:53:58.614178  DQM0 = 120, DQM1 = 116

 3439 23:53:58.617883  DQ Delay:

 3440 23:53:58.621216  DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118

 3441 23:53:58.624263  DQ4 =120, DQ5 =130, DQ6 =128, DQ7 =120

 3442 23:53:58.627988  DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108

 3443 23:53:58.630796  DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126

 3444 23:53:58.630937  

 3445 23:53:58.631064  

 3446 23:53:58.637378  [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps

 3447 23:53:58.640569  CH1 RK0: MR19=304, MR18=FF12

 3448 23:53:58.647800  CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26

 3449 23:53:58.647963  

 3450 23:53:58.651125  ----->DramcWriteLeveling(PI) begin...

 3451 23:53:58.651253  ==

 3452 23:53:58.654376  Dram Type= 6, Freq= 0, CH_1, rank 1

 3453 23:53:58.657672  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3454 23:53:58.657779  ==

 3455 23:53:58.661043  Write leveling (Byte 0): 24 => 24

 3456 23:53:58.664472  Write leveling (Byte 1): 30 => 30

 3457 23:53:58.668085  DramcWriteLeveling(PI) end<-----

 3458 23:53:58.668198  

 3459 23:53:58.668299  ==

 3460 23:53:58.670955  Dram Type= 6, Freq= 0, CH_1, rank 1

 3461 23:53:58.677673  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3462 23:53:58.677810  ==

 3463 23:53:58.677920  [Gating] SW mode calibration

 3464 23:53:58.688042  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3465 23:53:58.691239  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3466 23:53:58.694422   0 15  0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 3467 23:53:58.701065   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3468 23:53:58.704317   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3469 23:53:58.707771   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3470 23:53:58.714509   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3471 23:53:58.717511   0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)

 3472 23:53:58.720985   0 15 24 | B1->B0 | 2b2b 3434 | 1 1 | (1 0) (1 1)

 3473 23:53:58.727844   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 3474 23:53:58.731004   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3475 23:53:58.734352   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3476 23:53:58.740967   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3477 23:53:58.744676   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3478 23:53:58.747900   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3479 23:53:58.754267   1  0 20 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)

 3480 23:53:58.757693   1  0 24 | B1->B0 | 4040 2828 | 0 1 | (0 0) (0 0)

 3481 23:53:58.761220   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3482 23:53:58.764892   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3483 23:53:58.771526   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3484 23:53:58.774618   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3485 23:53:58.777704   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3486 23:53:58.784688   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3487 23:53:58.787748   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3488 23:53:58.791040   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3489 23:53:58.797956   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3490 23:53:58.801054   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3491 23:53:58.804406   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3492 23:53:58.811371   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3493 23:53:58.814347   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3494 23:53:58.817932   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3495 23:53:58.824655   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3496 23:53:58.827538   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3497 23:53:58.831096   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3498 23:53:58.837906   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3499 23:53:58.841546   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3500 23:53:58.844267   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3501 23:53:58.850938   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3502 23:53:58.854877   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3503 23:53:58.857582   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3504 23:53:58.860859   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3505 23:53:58.867606   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3506 23:53:58.871330  Total UI for P1: 0, mck2ui 16

 3507 23:53:58.874744  best dqsien dly found for B1: ( 1,  3, 22)

 3508 23:53:58.877854   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3509 23:53:58.881079  Total UI for P1: 0, mck2ui 16

 3510 23:53:58.884249  best dqsien dly found for B0: ( 1,  3, 26)

 3511 23:53:58.887420  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3512 23:53:58.891455  best DQS1 dly(MCK, UI, PI) = (1, 3, 22)

 3513 23:53:58.891546  

 3514 23:53:58.894410  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3515 23:53:58.897970  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3516 23:53:58.901401  [Gating] SW calibration Done

 3517 23:53:58.901523  ==

 3518 23:53:58.904178  Dram Type= 6, Freq= 0, CH_1, rank 1

 3519 23:53:58.910989  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3520 23:53:58.911167  ==

 3521 23:53:58.911291  RX Vref Scan: 0

 3522 23:53:58.911408  

 3523 23:53:58.914631  RX Vref 0 -> 0, step: 1

 3524 23:53:58.914765  

 3525 23:53:58.917695  RX Delay -40 -> 252, step: 8

 3526 23:53:58.921087  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3527 23:53:58.924674  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3528 23:53:58.927538  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3529 23:53:58.930737  iDelay=200, Bit 3, Center 115 (48 ~ 183) 136

 3530 23:53:58.937563  iDelay=200, Bit 4, Center 115 (48 ~ 183) 136

 3531 23:53:58.940605  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3532 23:53:58.944263  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3533 23:53:58.947477  iDelay=200, Bit 7, Center 119 (48 ~ 191) 144

 3534 23:53:58.951075  iDelay=200, Bit 8, Center 107 (40 ~ 175) 136

 3535 23:53:58.957349  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3536 23:53:58.961025  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3537 23:53:58.964357  iDelay=200, Bit 11, Center 115 (48 ~ 183) 136

 3538 23:53:58.967499  iDelay=200, Bit 12, Center 127 (56 ~ 199) 144

 3539 23:53:58.970911  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3540 23:53:58.977409  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3541 23:53:58.980903  iDelay=200, Bit 15, Center 127 (64 ~ 191) 128

 3542 23:53:58.981009  ==

 3543 23:53:58.984081  Dram Type= 6, Freq= 0, CH_1, rank 1

 3544 23:53:58.987340  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3545 23:53:58.987456  ==

 3546 23:53:58.990692  DQS Delay:

 3547 23:53:58.990794  DQS0 = 0, DQS1 = 0

 3548 23:53:58.990896  DQM Delay:

 3549 23:53:58.993855  DQM0 = 119, DQM1 = 118

 3550 23:53:58.993957  DQ Delay:

 3551 23:53:58.998022  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115

 3552 23:53:59.000919  DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119

 3553 23:53:59.007303  DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115

 3554 23:53:59.010626  DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127

 3555 23:53:59.010750  

 3556 23:53:59.010818  

 3557 23:53:59.010879  ==

 3558 23:53:59.014340  Dram Type= 6, Freq= 0, CH_1, rank 1

 3559 23:53:59.017226  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3560 23:53:59.017339  ==

 3561 23:53:59.017406  

 3562 23:53:59.017467  

 3563 23:53:59.020829  	TX Vref Scan disable

 3564 23:53:59.023780   == TX Byte 0 ==

 3565 23:53:59.026838  Update DQ  dly =841 (3 ,1, 41)  DQ  OEN =(2 ,6)

 3566 23:53:59.030715  Update DQM dly =841 (3 ,1, 41)  DQM OEN =(2 ,6)

 3567 23:53:59.033770   == TX Byte 1 ==

 3568 23:53:59.036966  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3569 23:53:59.040664  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3570 23:53:59.040844  ==

 3571 23:53:59.043778  Dram Type= 6, Freq= 0, CH_1, rank 1

 3572 23:53:59.047308  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3573 23:53:59.050263  ==

 3574 23:53:59.060798  TX Vref=22, minBit 9, minWin=25, winSum=419

 3575 23:53:59.063861  TX Vref=24, minBit 1, minWin=26, winSum=425

 3576 23:53:59.067327  TX Vref=26, minBit 2, minWin=26, winSum=428

 3577 23:53:59.070590  TX Vref=28, minBit 9, minWin=26, winSum=437

 3578 23:53:59.073860  TX Vref=30, minBit 9, minWin=26, winSum=435

 3579 23:53:59.080309  TX Vref=32, minBit 0, minWin=27, winSum=438

 3580 23:53:59.083665  [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 32

 3581 23:53:59.083784  

 3582 23:53:59.086894  Final TX Range 1 Vref 32

 3583 23:53:59.086991  

 3584 23:53:59.087061  ==

 3585 23:53:59.090472  Dram Type= 6, Freq= 0, CH_1, rank 1

 3586 23:53:59.093461  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3587 23:53:59.093546  ==

 3588 23:53:59.096812  

 3589 23:53:59.096898  

 3590 23:53:59.096970  	TX Vref Scan disable

 3591 23:53:59.100011   == TX Byte 0 ==

 3592 23:53:59.103428  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3593 23:53:59.110575  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3594 23:53:59.110694   == TX Byte 1 ==

 3595 23:53:59.113901  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3596 23:53:59.116916  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3597 23:53:59.120444  

 3598 23:53:59.120536  [DATLAT]

 3599 23:53:59.120607  Freq=1200, CH1 RK1

 3600 23:53:59.120672  

 3601 23:53:59.123677  DATLAT Default: 0xd

 3602 23:53:59.123769  0, 0xFFFF, sum = 0

 3603 23:53:59.127424  1, 0xFFFF, sum = 0

 3604 23:53:59.127536  2, 0xFFFF, sum = 0

 3605 23:53:59.130180  3, 0xFFFF, sum = 0

 3606 23:53:59.130275  4, 0xFFFF, sum = 0

 3607 23:53:59.134012  5, 0xFFFF, sum = 0

 3608 23:53:59.137131  6, 0xFFFF, sum = 0

 3609 23:53:59.137234  7, 0xFFFF, sum = 0

 3610 23:53:59.140614  8, 0xFFFF, sum = 0

 3611 23:53:59.140719  9, 0xFFFF, sum = 0

 3612 23:53:59.143763  10, 0xFFFF, sum = 0

 3613 23:53:59.143859  11, 0xFFFF, sum = 0

 3614 23:53:59.146943  12, 0x0, sum = 1

 3615 23:53:59.147039  13, 0x0, sum = 2

 3616 23:53:59.150044  14, 0x0, sum = 3

 3617 23:53:59.150176  15, 0x0, sum = 4

 3618 23:53:59.150315  best_step = 13

 3619 23:53:59.153762  

 3620 23:53:59.153854  ==

 3621 23:53:59.157037  Dram Type= 6, Freq= 0, CH_1, rank 1

 3622 23:53:59.160229  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3623 23:53:59.160360  ==

 3624 23:53:59.160434  RX Vref Scan: 0

 3625 23:53:59.160495  

 3626 23:53:59.163737  RX Vref 0 -> 0, step: 1

 3627 23:53:59.163821  

 3628 23:53:59.166792  RX Delay -5 -> 252, step: 4

 3629 23:53:59.170654  iDelay=195, Bit 0, Center 122 (59 ~ 186) 128

 3630 23:53:59.176883  iDelay=195, Bit 1, Center 116 (55 ~ 178) 124

 3631 23:53:59.180160  iDelay=195, Bit 2, Center 110 (51 ~ 170) 120

 3632 23:53:59.183295  iDelay=195, Bit 3, Center 118 (59 ~ 178) 120

 3633 23:53:59.187099  iDelay=195, Bit 4, Center 116 (55 ~ 178) 124

 3634 23:53:59.190393  iDelay=195, Bit 5, Center 132 (71 ~ 194) 124

 3635 23:53:59.197057  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3636 23:53:59.200247  iDelay=195, Bit 7, Center 120 (59 ~ 182) 124

 3637 23:53:59.203505  iDelay=195, Bit 8, Center 106 (47 ~ 166) 120

 3638 23:53:59.206838  iDelay=195, Bit 9, Center 106 (47 ~ 166) 120

 3639 23:53:59.210106  iDelay=195, Bit 10, Center 116 (55 ~ 178) 124

 3640 23:53:59.216797  iDelay=195, Bit 11, Center 110 (51 ~ 170) 120

 3641 23:53:59.220319  iDelay=195, Bit 12, Center 126 (63 ~ 190) 128

 3642 23:53:59.223790  iDelay=195, Bit 13, Center 124 (67 ~ 182) 116

 3643 23:53:59.226873  iDelay=195, Bit 14, Center 122 (63 ~ 182) 120

 3644 23:53:59.229947  iDelay=195, Bit 15, Center 124 (63 ~ 186) 124

 3645 23:53:59.233108  ==

 3646 23:53:59.233223  Dram Type= 6, Freq= 0, CH_1, rank 1

 3647 23:53:59.240001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3648 23:53:59.240143  ==

 3649 23:53:59.240241  DQS Delay:

 3650 23:53:59.243595  DQS0 = 0, DQS1 = 0

 3651 23:53:59.243701  DQM Delay:

 3652 23:53:59.246604  DQM0 = 120, DQM1 = 116

 3653 23:53:59.246710  DQ Delay:

 3654 23:53:59.249963  DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118

 3655 23:53:59.253262  DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120

 3656 23:53:59.256761  DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110

 3657 23:53:59.259713  DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124

 3658 23:53:59.259788  

 3659 23:53:59.259850  

 3660 23:53:59.269963  [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps

 3661 23:53:59.273009  CH1 RK1: MR19=403, MR18=10ED

 3662 23:53:59.276549  CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26

 3663 23:53:59.279595  [RxdqsGatingPostProcess] freq 1200

 3664 23:53:59.286194  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3665 23:53:59.289742  best DQS0 dly(2T, 0.5T) = (0, 11)

 3666 23:53:59.292744  best DQS1 dly(2T, 0.5T) = (0, 11)

 3667 23:53:59.296242  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3668 23:53:59.299326  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3669 23:53:59.303352  best DQS0 dly(2T, 0.5T) = (0, 11)

 3670 23:53:59.306476  best DQS1 dly(2T, 0.5T) = (0, 11)

 3671 23:53:59.309853  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3672 23:53:59.313044  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3673 23:53:59.313164  Pre-setting of DQS Precalculation

 3674 23:53:59.320019  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3675 23:53:59.326435  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3676 23:53:59.333113  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3677 23:53:59.333267  

 3678 23:53:59.333362  

 3679 23:53:59.336044  [Calibration Summary] 2400 Mbps

 3680 23:53:59.339600  CH 0, Rank 0

 3681 23:53:59.339742  SW Impedance     : PASS

 3682 23:53:59.342805  DUTY Scan        : NO K

 3683 23:53:59.346045  ZQ Calibration   : PASS

 3684 23:53:59.346162  Jitter Meter     : NO K

 3685 23:53:59.349356  CBT Training     : PASS

 3686 23:53:59.352593  Write leveling   : PASS

 3687 23:53:59.352702  RX DQS gating    : PASS

 3688 23:53:59.356352  RX DQ/DQS(RDDQC) : PASS

 3689 23:53:59.356430  TX DQ/DQS        : PASS

 3690 23:53:59.359428  RX DATLAT        : PASS

 3691 23:53:59.362869  RX DQ/DQS(Engine): PASS

 3692 23:53:59.362947  TX OE            : NO K

 3693 23:53:59.365861  All Pass.

 3694 23:53:59.365934  

 3695 23:53:59.365993  CH 0, Rank 1

 3696 23:53:59.369420  SW Impedance     : PASS

 3697 23:53:59.369521  DUTY Scan        : NO K

 3698 23:53:59.372558  ZQ Calibration   : PASS

 3699 23:53:59.376080  Jitter Meter     : NO K

 3700 23:53:59.376189  CBT Training     : PASS

 3701 23:53:59.379332  Write leveling   : PASS

 3702 23:53:59.383028  RX DQS gating    : PASS

 3703 23:53:59.383100  RX DQ/DQS(RDDQC) : PASS

 3704 23:53:59.386221  TX DQ/DQS        : PASS

 3705 23:53:59.389321  RX DATLAT        : PASS

 3706 23:53:59.389405  RX DQ/DQS(Engine): PASS

 3707 23:53:59.392815  TX OE            : NO K

 3708 23:53:59.392901  All Pass.

 3709 23:53:59.392985  

 3710 23:53:59.396222  CH 1, Rank 0

 3711 23:53:59.396332  SW Impedance     : PASS

 3712 23:53:59.399412  DUTY Scan        : NO K

 3713 23:53:59.399496  ZQ Calibration   : PASS

 3714 23:53:59.403334  Jitter Meter     : NO K

 3715 23:53:59.406481  CBT Training     : PASS

 3716 23:53:59.406566  Write leveling   : PASS

 3717 23:53:59.409591  RX DQS gating    : PASS

 3718 23:53:59.412948  RX DQ/DQS(RDDQC) : PASS

 3719 23:53:59.413032  TX DQ/DQS        : PASS

 3720 23:53:59.416177  RX DATLAT        : PASS

 3721 23:53:59.419390  RX DQ/DQS(Engine): PASS

 3722 23:53:59.419477  TX OE            : NO K

 3723 23:53:59.422751  All Pass.

 3724 23:53:59.422856  

 3725 23:53:59.422947  CH 1, Rank 1

 3726 23:53:59.426029  SW Impedance     : PASS

 3727 23:53:59.426103  DUTY Scan        : NO K

 3728 23:53:59.429485  ZQ Calibration   : PASS

 3729 23:53:59.433349  Jitter Meter     : NO K

 3730 23:53:59.433427  CBT Training     : PASS

 3731 23:53:59.436179  Write leveling   : PASS

 3732 23:53:59.439327  RX DQS gating    : PASS

 3733 23:53:59.439430  RX DQ/DQS(RDDQC) : PASS

 3734 23:53:59.443233  TX DQ/DQS        : PASS

 3735 23:53:59.446429  RX DATLAT        : PASS

 3736 23:53:59.446507  RX DQ/DQS(Engine): PASS

 3737 23:53:59.449440  TX OE            : NO K

 3738 23:53:59.449514  All Pass.

 3739 23:53:59.449575  

 3740 23:53:59.452730  DramC Write-DBI off

 3741 23:53:59.456413  	PER_BANK_REFRESH: Hybrid Mode

 3742 23:53:59.456490  TX_TRACKING: ON

 3743 23:53:59.466210  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3744 23:53:59.469067  [FAST_K] Save calibration result to emmc

 3745 23:53:59.472691  dramc_set_vcore_voltage set vcore to 650000

 3746 23:53:59.475924  Read voltage for 600, 5

 3747 23:53:59.476039  Vio18 = 0

 3748 23:53:59.476128  Vcore = 650000

 3749 23:53:59.476227  Vdram = 0

 3750 23:53:59.479479  Vddq = 0

 3751 23:53:59.479590  Vmddr = 0

 3752 23:53:59.485719  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3753 23:53:59.489247  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3754 23:53:59.492149  MEM_TYPE=3, freq_sel=19

 3755 23:53:59.495850  sv_algorithm_assistance_LP4_1600 

 3756 23:53:59.499384  ============ PULL DRAM RESETB DOWN ============

 3757 23:53:59.502510  ========== PULL DRAM RESETB DOWN end =========

 3758 23:53:59.509136  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3759 23:53:59.512285  =================================== 

 3760 23:53:59.512420  LPDDR4 DRAM CONFIGURATION

 3761 23:53:59.515892  =================================== 

 3762 23:53:59.518960  EX_ROW_EN[0]    = 0x0

 3763 23:53:59.522550  EX_ROW_EN[1]    = 0x0

 3764 23:53:59.522633  LP4Y_EN      = 0x0

 3765 23:53:59.525620  WORK_FSP     = 0x0

 3766 23:53:59.525702  WL           = 0x2

 3767 23:53:59.529132  RL           = 0x2

 3768 23:53:59.529215  BL           = 0x2

 3769 23:53:59.532252  RPST         = 0x0

 3770 23:53:59.532381  RD_PRE       = 0x0

 3771 23:53:59.535507  WR_PRE       = 0x1

 3772 23:53:59.535629  WR_PST       = 0x0

 3773 23:53:59.539109  DBI_WR       = 0x0

 3774 23:53:59.539232  DBI_RD       = 0x0

 3775 23:53:59.542268  OTF          = 0x1

 3776 23:53:59.545294  =================================== 

 3777 23:53:59.548968  =================================== 

 3778 23:53:59.549104  ANA top config

 3779 23:53:59.552384  =================================== 

 3780 23:53:59.555452  DLL_ASYNC_EN            =  0

 3781 23:53:59.558740  ALL_SLAVE_EN            =  1

 3782 23:53:59.562069  NEW_RANK_MODE           =  1

 3783 23:53:59.562153  DLL_IDLE_MODE           =  1

 3784 23:53:59.565270  LP45_APHY_COMB_EN       =  1

 3785 23:53:59.568631  TX_ODT_DIS              =  1

 3786 23:53:59.571834  NEW_8X_MODE             =  1

 3787 23:53:59.575714  =================================== 

 3788 23:53:59.579036  =================================== 

 3789 23:53:59.582259  data_rate                  = 1200

 3790 23:53:59.582357  CKR                        = 1

 3791 23:53:59.585284  DQ_P2S_RATIO               = 8

 3792 23:53:59.588425  =================================== 

 3793 23:53:59.591897  CA_P2S_RATIO               = 8

 3794 23:53:59.594953  DQ_CA_OPEN                 = 0

 3795 23:53:59.598674  DQ_SEMI_OPEN               = 0

 3796 23:53:59.601906  CA_SEMI_OPEN               = 0

 3797 23:53:59.602018  CA_FULL_RATE               = 0

 3798 23:53:59.605114  DQ_CKDIV4_EN               = 1

 3799 23:53:59.608268  CA_CKDIV4_EN               = 1

 3800 23:53:59.612262  CA_PREDIV_EN               = 0

 3801 23:53:59.615211  PH8_DLY                    = 0

 3802 23:53:59.618588  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3803 23:53:59.618691  DQ_AAMCK_DIV               = 4

 3804 23:53:59.621894  CA_AAMCK_DIV               = 4

 3805 23:53:59.625118  CA_ADMCK_DIV               = 4

 3806 23:53:59.628601  DQ_TRACK_CA_EN             = 0

 3807 23:53:59.631792  CA_PICK                    = 600

 3808 23:53:59.635353  CA_MCKIO                   = 600

 3809 23:53:59.635436  MCKIO_SEMI                 = 0

 3810 23:53:59.638618  PLL_FREQ                   = 2288

 3811 23:53:59.641862  DQ_UI_PI_RATIO             = 32

 3812 23:53:59.645015  CA_UI_PI_RATIO             = 0

 3813 23:53:59.648290  =================================== 

 3814 23:53:59.652240  =================================== 

 3815 23:53:59.654885  memory_type:LPDDR4         

 3816 23:53:59.654966  GP_NUM     : 10       

 3817 23:53:59.657987  SRAM_EN    : 1       

 3818 23:53:59.661335  MD32_EN    : 0       

 3819 23:53:59.664611  =================================== 

 3820 23:53:59.664692  [ANA_INIT] >>>>>>>>>>>>>> 

 3821 23:53:59.668171  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3822 23:53:59.671898  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3823 23:53:59.675088  =================================== 

 3824 23:53:59.678631  data_rate = 1200,PCW = 0X5800

 3825 23:53:59.681751  =================================== 

 3826 23:53:59.684915  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3827 23:53:59.691497  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3828 23:53:59.694841  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3829 23:53:59.701684  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3830 23:53:59.704946  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3831 23:53:59.708084  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3832 23:53:59.708168  [ANA_INIT] flow start 

 3833 23:53:59.711467  [ANA_INIT] PLL >>>>>>>> 

 3834 23:53:59.714991  [ANA_INIT] PLL <<<<<<<< 

 3835 23:53:59.715096  [ANA_INIT] MIDPI >>>>>>>> 

 3836 23:53:59.718346  [ANA_INIT] MIDPI <<<<<<<< 

 3837 23:53:59.721423  [ANA_INIT] DLL >>>>>>>> 

 3838 23:53:59.721518  [ANA_INIT] flow end 

 3839 23:53:59.728014  ============ LP4 DIFF to SE enter ============

 3840 23:53:59.731681  ============ LP4 DIFF to SE exit  ============

 3841 23:53:59.735093  [ANA_INIT] <<<<<<<<<<<<< 

 3842 23:53:59.737804  [Flow] Enable top DCM control >>>>> 

 3843 23:53:59.741389  [Flow] Enable top DCM control <<<<< 

 3844 23:53:59.744806  Enable DLL master slave shuffle 

 3845 23:53:59.748078  ============================================================== 

 3846 23:53:59.751115  Gating Mode config

 3847 23:53:59.754810  ============================================================== 

 3848 23:53:59.757941  Config description: 

 3849 23:53:59.767503  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3850 23:53:59.774557  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3851 23:53:59.778119  SELPH_MODE            0: By rank         1: By Phase 

 3852 23:53:59.784166  ============================================================== 

 3853 23:53:59.788235  GAT_TRACK_EN                 =  1

 3854 23:53:59.791362  RX_GATING_MODE               =  2

 3855 23:53:59.794421  RX_GATING_TRACK_MODE         =  2

 3856 23:53:59.797652  SELPH_MODE                   =  1

 3857 23:53:59.797733  PICG_EARLY_EN                =  1

 3858 23:53:59.800892  VALID_LAT_VALUE              =  1

 3859 23:53:59.807532  ============================================================== 

 3860 23:53:59.811134  Enter into Gating configuration >>>> 

 3861 23:53:59.814060  Exit from Gating configuration <<<< 

 3862 23:53:59.817811  Enter into  DVFS_PRE_config >>>>> 

 3863 23:53:59.828012  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3864 23:53:59.830703  Exit from  DVFS_PRE_config <<<<< 

 3865 23:53:59.834718  Enter into PICG configuration >>>> 

 3866 23:53:59.838041  Exit from PICG configuration <<<< 

 3867 23:53:59.841072  [RX_INPUT] configuration >>>>> 

 3868 23:53:59.844166  [RX_INPUT] configuration <<<<< 

 3869 23:53:59.847764  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3870 23:53:59.854125  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3871 23:53:59.860958  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3872 23:53:59.867349  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3873 23:53:59.874056  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3874 23:53:59.877450  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3875 23:53:59.884395  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3876 23:53:59.887294  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3877 23:53:59.890374  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3878 23:53:59.894615  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3879 23:53:59.901166  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3880 23:53:59.904109  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3881 23:53:59.907543  =================================== 

 3882 23:53:59.911002  LPDDR4 DRAM CONFIGURATION

 3883 23:53:59.913756  =================================== 

 3884 23:53:59.913878  EX_ROW_EN[0]    = 0x0

 3885 23:53:59.917549  EX_ROW_EN[1]    = 0x0

 3886 23:53:59.917670  LP4Y_EN      = 0x0

 3887 23:53:59.920636  WORK_FSP     = 0x0

 3888 23:53:59.920755  WL           = 0x2

 3889 23:53:59.924057  RL           = 0x2

 3890 23:53:59.924176  BL           = 0x2

 3891 23:53:59.927250  RPST         = 0x0

 3892 23:53:59.927369  RD_PRE       = 0x0

 3893 23:53:59.930487  WR_PRE       = 0x1

 3894 23:53:59.933774  WR_PST       = 0x0

 3895 23:53:59.933849  DBI_WR       = 0x0

 3896 23:53:59.937001  DBI_RD       = 0x0

 3897 23:53:59.937125  OTF          = 0x1

 3898 23:53:59.940232  =================================== 

 3899 23:53:59.944335  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3900 23:53:59.947389  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3901 23:53:59.954082  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3902 23:53:59.957291  =================================== 

 3903 23:53:59.960222  LPDDR4 DRAM CONFIGURATION

 3904 23:53:59.963532  =================================== 

 3905 23:53:59.963615  EX_ROW_EN[0]    = 0x10

 3906 23:53:59.967211  EX_ROW_EN[1]    = 0x0

 3907 23:53:59.967294  LP4Y_EN      = 0x0

 3908 23:53:59.970254  WORK_FSP     = 0x0

 3909 23:53:59.970336  WL           = 0x2

 3910 23:53:59.973738  RL           = 0x2

 3911 23:53:59.973820  BL           = 0x2

 3912 23:53:59.976890  RPST         = 0x0

 3913 23:53:59.976972  RD_PRE       = 0x0

 3914 23:53:59.980173  WR_PRE       = 0x1

 3915 23:53:59.980285  WR_PST       = 0x0

 3916 23:53:59.983625  DBI_WR       = 0x0

 3917 23:53:59.983707  DBI_RD       = 0x0

 3918 23:53:59.987032  OTF          = 0x1

 3919 23:53:59.990274  =================================== 

 3920 23:53:59.996923  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3921 23:54:00.000156  nWR fixed to 30

 3922 23:54:00.003706  [ModeRegInit_LP4] CH0 RK0

 3923 23:54:00.003789  [ModeRegInit_LP4] CH0 RK1

 3924 23:54:00.007347  [ModeRegInit_LP4] CH1 RK0

 3925 23:54:00.010692  [ModeRegInit_LP4] CH1 RK1

 3926 23:54:00.010775  match AC timing 17

 3927 23:54:00.017094  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3928 23:54:00.020266  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3929 23:54:00.023845  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3930 23:54:00.029925  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3931 23:54:00.033624  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3932 23:54:00.033709  ==

 3933 23:54:00.036796  Dram Type= 6, Freq= 0, CH_0, rank 0

 3934 23:54:00.040917  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3935 23:54:00.041000  ==

 3936 23:54:00.047206  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3937 23:54:00.053497  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3938 23:54:00.056906  [CA 0] Center 35 (5~66) winsize 62

 3939 23:54:00.060018  [CA 1] Center 35 (5~66) winsize 62

 3940 23:54:00.063326  [CA 2] Center 33 (3~64) winsize 62

 3941 23:54:00.066575  [CA 3] Center 33 (2~64) winsize 63

 3942 23:54:00.070465  [CA 4] Center 33 (2~64) winsize 63

 3943 23:54:00.073776  [CA 5] Center 32 (2~63) winsize 62

 3944 23:54:00.073873  

 3945 23:54:00.076844  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3946 23:54:00.076956  

 3947 23:54:00.080097  [CATrainingPosCal] consider 1 rank data

 3948 23:54:00.083703  u2DelayCellTimex100 = 270/100 ps

 3949 23:54:00.086753  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3950 23:54:00.090199  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3951 23:54:00.093302  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3952 23:54:00.096555  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3953 23:54:00.099757  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3954 23:54:00.103477  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3955 23:54:00.107138  

 3956 23:54:00.110011  CA PerBit enable=1, Macro0, CA PI delay=32

 3957 23:54:00.110147  

 3958 23:54:00.113676  [CBTSetCACLKResult] CA Dly = 32

 3959 23:54:00.113790  CS Dly: 5 (0~36)

 3960 23:54:00.113884  ==

 3961 23:54:00.116697  Dram Type= 6, Freq= 0, CH_0, rank 1

 3962 23:54:00.119943  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3963 23:54:00.120067  ==

 3964 23:54:00.126452  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3965 23:54:00.133551  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3966 23:54:00.136539  [CA 0] Center 35 (5~66) winsize 62

 3967 23:54:00.140049  [CA 1] Center 35 (5~66) winsize 62

 3968 23:54:00.143229  [CA 2] Center 34 (3~65) winsize 63

 3969 23:54:00.146925  [CA 3] Center 33 (2~64) winsize 63

 3970 23:54:00.150138  [CA 4] Center 32 (2~63) winsize 62

 3971 23:54:00.153433  [CA 5] Center 32 (2~63) winsize 62

 3972 23:54:00.153515  

 3973 23:54:00.156808  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3974 23:54:00.156892  

 3975 23:54:00.160091  [CATrainingPosCal] consider 2 rank data

 3976 23:54:00.163465  u2DelayCellTimex100 = 270/100 ps

 3977 23:54:00.166564  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3978 23:54:00.169990  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3979 23:54:00.173289  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3980 23:54:00.176594  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3981 23:54:00.179697  CA4 delay=32 (2~63),Diff = 0 PI (0 cell)

 3982 23:54:00.183425  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3983 23:54:00.186824  

 3984 23:54:00.190028  CA PerBit enable=1, Macro0, CA PI delay=32

 3985 23:54:00.190111  

 3986 23:54:00.193067  [CBTSetCACLKResult] CA Dly = 32

 3987 23:54:00.193149  CS Dly: 4 (0~35)

 3988 23:54:00.193214  

 3989 23:54:00.196646  ----->DramcWriteLeveling(PI) begin...

 3990 23:54:00.196730  ==

 3991 23:54:00.199487  Dram Type= 6, Freq= 0, CH_0, rank 0

 3992 23:54:00.203260  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3993 23:54:00.206646  ==

 3994 23:54:00.206729  Write leveling (Byte 0): 35 => 35

 3995 23:54:00.209927  Write leveling (Byte 1): 32 => 32

 3996 23:54:00.213545  DramcWriteLeveling(PI) end<-----

 3997 23:54:00.213628  

 3998 23:54:00.213693  ==

 3999 23:54:00.216748  Dram Type= 6, Freq= 0, CH_0, rank 0

 4000 23:54:00.223503  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4001 23:54:00.223586  ==

 4002 23:54:00.223653  [Gating] SW mode calibration

 4003 23:54:00.233192  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4004 23:54:00.236398  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4005 23:54:00.243130   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4006 23:54:00.246541   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4007 23:54:00.249586   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4008 23:54:00.252856   0  9 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)

 4009 23:54:00.259768   0  9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)

 4010 23:54:00.262926   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4011 23:54:00.266480   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4012 23:54:00.272756   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4013 23:54:00.276028   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4014 23:54:00.279468   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4015 23:54:00.285906   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4016 23:54:00.289102   0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)

 4017 23:54:00.292272   0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)

 4018 23:54:00.299161   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4019 23:54:00.302865   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4020 23:54:00.305483   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4021 23:54:00.312556   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4022 23:54:00.316107   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4023 23:54:00.319255   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4024 23:54:00.325977   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4025 23:54:00.329160   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4026 23:54:00.332280   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4027 23:54:00.338969   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4028 23:54:00.342424   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4029 23:54:00.346024   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4030 23:54:00.352566   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4031 23:54:00.355545   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4032 23:54:00.358758   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4033 23:54:00.366205   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4034 23:54:00.369114   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4035 23:54:00.372124   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4036 23:54:00.379082   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4037 23:54:00.382180   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4038 23:54:00.385661   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4039 23:54:00.392594   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4040 23:54:00.395727   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4041 23:54:00.398972   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4042 23:54:00.402269  Total UI for P1: 0, mck2ui 16

 4043 23:54:00.405960  best dqsien dly found for B0: ( 0, 13, 12)

 4044 23:54:00.409167  Total UI for P1: 0, mck2ui 16

 4045 23:54:00.412862  best dqsien dly found for B1: ( 0, 13, 14)

 4046 23:54:00.415473  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4047 23:54:00.418968  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4048 23:54:00.419070  

 4049 23:54:00.422282  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4050 23:54:00.429164  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4051 23:54:00.429248  [Gating] SW calibration Done

 4052 23:54:00.429315  ==

 4053 23:54:00.432401  Dram Type= 6, Freq= 0, CH_0, rank 0

 4054 23:54:00.439209  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4055 23:54:00.439313  ==

 4056 23:54:00.439418  RX Vref Scan: 0

 4057 23:54:00.439510  

 4058 23:54:00.442402  RX Vref 0 -> 0, step: 1

 4059 23:54:00.442512  

 4060 23:54:00.445888  RX Delay -230 -> 252, step: 16

 4061 23:54:00.448801  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4062 23:54:00.452289  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4063 23:54:00.455877  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4064 23:54:00.462080  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4065 23:54:00.465469  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4066 23:54:00.468942  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4067 23:54:00.472155  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4068 23:54:00.479001  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4069 23:54:00.482001  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4070 23:54:00.485627  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4071 23:54:00.488602  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4072 23:54:00.492334  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4073 23:54:00.498859  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4074 23:54:00.502147  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4075 23:54:00.505283  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4076 23:54:00.508693  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4077 23:54:00.511717  ==

 4078 23:54:00.515611  Dram Type= 6, Freq= 0, CH_0, rank 0

 4079 23:54:00.518428  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4080 23:54:00.518533  ==

 4081 23:54:00.518643  DQS Delay:

 4082 23:54:00.521902  DQS0 = 0, DQS1 = 0

 4083 23:54:00.522011  DQM Delay:

 4084 23:54:00.525415  DQM0 = 51, DQM1 = 46

 4085 23:54:00.525523  DQ Delay:

 4086 23:54:00.528780  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49

 4087 23:54:00.532167  DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57

 4088 23:54:00.534974  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4089 23:54:00.538211  DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57

 4090 23:54:00.538330  

 4091 23:54:00.538427  

 4092 23:54:00.538534  ==

 4093 23:54:00.541448  Dram Type= 6, Freq= 0, CH_0, rank 0

 4094 23:54:00.544790  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4095 23:54:00.544897  ==

 4096 23:54:00.545008  

 4097 23:54:00.545100  

 4098 23:54:00.548497  	TX Vref Scan disable

 4099 23:54:00.551379   == TX Byte 0 ==

 4100 23:54:00.554668  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4101 23:54:00.558702  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4102 23:54:00.561425   == TX Byte 1 ==

 4103 23:54:00.564694  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4104 23:54:00.568661  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4105 23:54:00.568746  ==

 4106 23:54:00.571463  Dram Type= 6, Freq= 0, CH_0, rank 0

 4107 23:54:00.578081  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4108 23:54:00.578166  ==

 4109 23:54:00.578231  

 4110 23:54:00.578290  

 4111 23:54:00.578347  	TX Vref Scan disable

 4112 23:54:00.582800   == TX Byte 0 ==

 4113 23:54:00.585837  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4114 23:54:00.589055  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4115 23:54:00.592688   == TX Byte 1 ==

 4116 23:54:00.595837  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4117 23:54:00.602470  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4118 23:54:00.602599  

 4119 23:54:00.602712  [DATLAT]

 4120 23:54:00.602826  Freq=600, CH0 RK0

 4121 23:54:00.602935  

 4122 23:54:00.605861  DATLAT Default: 0x9

 4123 23:54:00.605986  0, 0xFFFF, sum = 0

 4124 23:54:00.609194  1, 0xFFFF, sum = 0

 4125 23:54:00.609320  2, 0xFFFF, sum = 0

 4126 23:54:00.612811  3, 0xFFFF, sum = 0

 4127 23:54:00.612919  4, 0xFFFF, sum = 0

 4128 23:54:00.616301  5, 0xFFFF, sum = 0

 4129 23:54:00.616409  6, 0xFFFF, sum = 0

 4130 23:54:00.619399  7, 0xFFFF, sum = 0

 4131 23:54:00.619497  8, 0x0, sum = 1

 4132 23:54:00.622533  9, 0x0, sum = 2

 4133 23:54:00.622631  10, 0x0, sum = 3

 4134 23:54:00.625907  11, 0x0, sum = 4

 4135 23:54:00.626004  best_step = 9

 4136 23:54:00.626089  

 4137 23:54:00.626173  ==

 4138 23:54:00.629516  Dram Type= 6, Freq= 0, CH_0, rank 0

 4139 23:54:00.635677  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4140 23:54:00.635779  ==

 4141 23:54:00.635845  RX Vref Scan: 1

 4142 23:54:00.635905  

 4143 23:54:00.639720  RX Vref 0 -> 0, step: 1

 4144 23:54:00.639803  

 4145 23:54:00.642638  RX Delay -163 -> 252, step: 8

 4146 23:54:00.642768  

 4147 23:54:00.645958  Set Vref, RX VrefLevel [Byte0]: 54

 4148 23:54:00.649354                           [Byte1]: 48

 4149 23:54:00.649476  

 4150 23:54:00.652419  Final RX Vref Byte 0 = 54 to rank0

 4151 23:54:00.655770  Final RX Vref Byte 1 = 48 to rank0

 4152 23:54:00.658970  Final RX Vref Byte 0 = 54 to rank1

 4153 23:54:00.662362  Final RX Vref Byte 1 = 48 to rank1==

 4154 23:54:00.665510  Dram Type= 6, Freq= 0, CH_0, rank 0

 4155 23:54:00.669591  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4156 23:54:00.669697  ==

 4157 23:54:00.672427  DQS Delay:

 4158 23:54:00.672510  DQS0 = 0, DQS1 = 0

 4159 23:54:00.672575  DQM Delay:

 4160 23:54:00.675982  DQM0 = 53, DQM1 = 46

 4161 23:54:00.676065  DQ Delay:

 4162 23:54:00.679313  DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48

 4163 23:54:00.682609  DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60

 4164 23:54:00.685817  DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40

 4165 23:54:00.689111  DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52

 4166 23:54:00.689195  

 4167 23:54:00.689259  

 4168 23:54:00.698887  [DQSOSCAuto] RK0, (LSB)MR18= 0x7266, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps

 4169 23:54:00.698998  CH0 RK0: MR19=808, MR18=7266

 4170 23:54:00.705396  CH0_RK0: MR19=0x808, MR18=0x7266, DQSOSC=388, MR23=63, INC=174, DEC=116

 4171 23:54:00.705530  

 4172 23:54:00.709238  ----->DramcWriteLeveling(PI) begin...

 4173 23:54:00.712123  ==

 4174 23:54:00.715795  Dram Type= 6, Freq= 0, CH_0, rank 1

 4175 23:54:00.719159  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4176 23:54:00.719246  ==

 4177 23:54:00.722371  Write leveling (Byte 0): 33 => 33

 4178 23:54:00.725775  Write leveling (Byte 1): 31 => 31

 4179 23:54:00.729132  DramcWriteLeveling(PI) end<-----

 4180 23:54:00.729261  

 4181 23:54:00.729375  ==

 4182 23:54:00.732213  Dram Type= 6, Freq= 0, CH_0, rank 1

 4183 23:54:00.735420  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4184 23:54:00.735504  ==

 4185 23:54:00.739312  [Gating] SW mode calibration

 4186 23:54:00.745601  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4187 23:54:00.749279  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4188 23:54:00.755939   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4189 23:54:00.758986   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4190 23:54:00.762338   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4191 23:54:00.768836   0  9 12 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 0)

 4192 23:54:00.772181   0  9 16 | B1->B0 | 2b2b 2525 | 0 0 | (1 1) (0 0)

 4193 23:54:00.775329   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4194 23:54:00.782037   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4195 23:54:00.785351   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4196 23:54:00.788982   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4197 23:54:00.795408   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4198 23:54:00.798618   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4199 23:54:00.802107   0 10 12 | B1->B0 | 2929 2828 | 0 1 | (0 0) (0 0)

 4200 23:54:00.808702   0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)

 4201 23:54:00.812222   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4202 23:54:00.815046   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4203 23:54:00.822071   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4204 23:54:00.825063   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4205 23:54:00.828854   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4206 23:54:00.835428   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4207 23:54:00.838695   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4208 23:54:00.841928   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4209 23:54:00.848292   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4210 23:54:00.852001   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4211 23:54:00.855066   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4212 23:54:00.861444   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4213 23:54:00.864772   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4214 23:54:00.868909   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4215 23:54:00.875267   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4216 23:54:00.878542   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4217 23:54:00.881818   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4218 23:54:00.885120   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4219 23:54:00.891611   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4220 23:54:00.894824   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4221 23:54:00.898377   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4222 23:54:00.905114   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4223 23:54:00.908238   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4224 23:54:00.911647   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4225 23:54:00.914693  Total UI for P1: 0, mck2ui 16

 4226 23:54:00.918463  best dqsien dly found for B0: ( 0, 13, 12)

 4227 23:54:00.921454  Total UI for P1: 0, mck2ui 16

 4228 23:54:00.925003  best dqsien dly found for B1: ( 0, 13, 12)

 4229 23:54:00.928268  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4230 23:54:00.931378  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4231 23:54:00.934687  

 4232 23:54:00.938203  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4233 23:54:00.941355  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4234 23:54:00.944847  [Gating] SW calibration Done

 4235 23:54:00.944930  ==

 4236 23:54:00.948037  Dram Type= 6, Freq= 0, CH_0, rank 1

 4237 23:54:00.951176  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4238 23:54:00.951261  ==

 4239 23:54:00.951326  RX Vref Scan: 0

 4240 23:54:00.954945  

 4241 23:54:00.955073  RX Vref 0 -> 0, step: 1

 4242 23:54:00.955188  

 4243 23:54:00.958206  RX Delay -230 -> 252, step: 16

 4244 23:54:00.961507  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4245 23:54:00.968507  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4246 23:54:00.971479  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4247 23:54:00.974812  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4248 23:54:00.978100  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4249 23:54:00.981339  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4250 23:54:00.987867  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4251 23:54:00.990967  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4252 23:54:00.994543  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4253 23:54:00.998080  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4254 23:54:01.004349  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4255 23:54:01.007556  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4256 23:54:01.011278  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4257 23:54:01.014814  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4258 23:54:01.020786  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4259 23:54:01.024321  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4260 23:54:01.024414  ==

 4261 23:54:01.027701  Dram Type= 6, Freq= 0, CH_0, rank 1

 4262 23:54:01.030916  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4263 23:54:01.030999  ==

 4264 23:54:01.034503  DQS Delay:

 4265 23:54:01.034585  DQS0 = 0, DQS1 = 0

 4266 23:54:01.034650  DQM Delay:

 4267 23:54:01.037847  DQM0 = 51, DQM1 = 43

 4268 23:54:01.037930  DQ Delay:

 4269 23:54:01.040684  DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49

 4270 23:54:01.044725  DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57

 4271 23:54:01.048041  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33

 4272 23:54:01.050988  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4273 23:54:01.051071  

 4274 23:54:01.051136  

 4275 23:54:01.051195  ==

 4276 23:54:01.054474  Dram Type= 6, Freq= 0, CH_0, rank 1

 4277 23:54:01.058065  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4278 23:54:01.061437  ==

 4279 23:54:01.061520  

 4280 23:54:01.061585  

 4281 23:54:01.061643  	TX Vref Scan disable

 4282 23:54:01.064206   == TX Byte 0 ==

 4283 23:54:01.067833  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4284 23:54:01.074011  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4285 23:54:01.074094   == TX Byte 1 ==

 4286 23:54:01.078154  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4287 23:54:01.084126  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4288 23:54:01.084249  ==

 4289 23:54:01.087888  Dram Type= 6, Freq= 0, CH_0, rank 1

 4290 23:54:01.091145  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4291 23:54:01.091232  ==

 4292 23:54:01.091297  

 4293 23:54:01.091356  

 4294 23:54:01.094352  	TX Vref Scan disable

 4295 23:54:01.097625   == TX Byte 0 ==

 4296 23:54:01.100885  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4297 23:54:01.103902  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4298 23:54:01.107974   == TX Byte 1 ==

 4299 23:54:01.110489  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4300 23:54:01.113990  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4301 23:54:01.114074  

 4302 23:54:01.114140  [DATLAT]

 4303 23:54:01.117585  Freq=600, CH0 RK1

 4304 23:54:01.117686  

 4305 23:54:01.117784  DATLAT Default: 0x9

 4306 23:54:01.120875  0, 0xFFFF, sum = 0

 4307 23:54:01.124134  1, 0xFFFF, sum = 0

 4308 23:54:01.124210  2, 0xFFFF, sum = 0

 4309 23:54:01.127288  3, 0xFFFF, sum = 0

 4310 23:54:01.127373  4, 0xFFFF, sum = 0

 4311 23:54:01.130446  5, 0xFFFF, sum = 0

 4312 23:54:01.130559  6, 0xFFFF, sum = 0

 4313 23:54:01.133730  7, 0xFFFF, sum = 0

 4314 23:54:01.133815  8, 0x0, sum = 1

 4315 23:54:01.137759  9, 0x0, sum = 2

 4316 23:54:01.137919  10, 0x0, sum = 3

 4317 23:54:01.138039  11, 0x0, sum = 4

 4318 23:54:01.140976  best_step = 9

 4319 23:54:01.141099  

 4320 23:54:01.141212  ==

 4321 23:54:01.144069  Dram Type= 6, Freq= 0, CH_0, rank 1

 4322 23:54:01.147360  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4323 23:54:01.147487  ==

 4324 23:54:01.150717  RX Vref Scan: 0

 4325 23:54:01.150840  

 4326 23:54:01.150952  RX Vref 0 -> 0, step: 1

 4327 23:54:01.151065  

 4328 23:54:01.154029  RX Delay -163 -> 252, step: 8

 4329 23:54:01.161126  iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288

 4330 23:54:01.164666  iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280

 4331 23:54:01.167976  iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288

 4332 23:54:01.171202  iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288

 4333 23:54:01.174349  iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280

 4334 23:54:01.181504  iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288

 4335 23:54:01.184405  iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280

 4336 23:54:01.188042  iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272

 4337 23:54:01.191064  iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288

 4338 23:54:01.194493  iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288

 4339 23:54:01.201032  iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280

 4340 23:54:01.204239  iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280

 4341 23:54:01.207367  iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272

 4342 23:54:01.211176  iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288

 4343 23:54:01.217803  iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280

 4344 23:54:01.220745  iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288

 4345 23:54:01.220851  ==

 4346 23:54:01.224305  Dram Type= 6, Freq= 0, CH_0, rank 1

 4347 23:54:01.227672  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4348 23:54:01.227770  ==

 4349 23:54:01.230893  DQS Delay:

 4350 23:54:01.230976  DQS0 = 0, DQS1 = 0

 4351 23:54:01.231040  DQM Delay:

 4352 23:54:01.234075  DQM0 = 53, DQM1 = 46

 4353 23:54:01.234157  DQ Delay:

 4354 23:54:01.237331  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4355 23:54:01.240641  DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60

 4356 23:54:01.243912  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4357 23:54:01.247196  DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52

 4358 23:54:01.247306  

 4359 23:54:01.247398  

 4360 23:54:01.257531  [DQSOSCAuto] RK1, (LSB)MR18= 0x6628, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps

 4361 23:54:01.257613  CH0 RK1: MR19=808, MR18=6628

 4362 23:54:01.264288  CH0_RK1: MR19=0x808, MR18=0x6628, DQSOSC=390, MR23=63, INC=172, DEC=114

 4363 23:54:01.267696  [RxdqsGatingPostProcess] freq 600

 4364 23:54:01.273967  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4365 23:54:01.277648  Pre-setting of DQS Precalculation

 4366 23:54:01.280701  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4367 23:54:01.280828  ==

 4368 23:54:01.284476  Dram Type= 6, Freq= 0, CH_1, rank 0

 4369 23:54:01.287608  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4370 23:54:01.290550  ==

 4371 23:54:01.294335  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4372 23:54:01.300947  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4373 23:54:01.304240  [CA 0] Center 36 (5~67) winsize 63

 4374 23:54:01.307755  [CA 1] Center 36 (5~67) winsize 63

 4375 23:54:01.310873  [CA 2] Center 34 (4~65) winsize 62

 4376 23:54:01.314084  [CA 3] Center 34 (4~65) winsize 62

 4377 23:54:01.317425  [CA 4] Center 34 (4~65) winsize 62

 4378 23:54:01.320652  [CA 5] Center 34 (3~65) winsize 63

 4379 23:54:01.320760  

 4380 23:54:01.324249  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4381 23:54:01.324355  

 4382 23:54:01.327497  [CATrainingPosCal] consider 1 rank data

 4383 23:54:01.330475  u2DelayCellTimex100 = 270/100 ps

 4384 23:54:01.334029  CA0 delay=36 (5~67),Diff = 2 PI (19 cell)

 4385 23:54:01.337043  CA1 delay=36 (5~67),Diff = 2 PI (19 cell)

 4386 23:54:01.340245  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4387 23:54:01.346932  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4388 23:54:01.350552  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4389 23:54:01.354112  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 4390 23:54:01.354223  

 4391 23:54:01.357434  CA PerBit enable=1, Macro0, CA PI delay=34

 4392 23:54:01.357510  

 4393 23:54:01.360824  [CBTSetCACLKResult] CA Dly = 34

 4394 23:54:01.360903  CS Dly: 5 (0~36)

 4395 23:54:01.360967  ==

 4396 23:54:01.363662  Dram Type= 6, Freq= 0, CH_1, rank 1

 4397 23:54:01.370699  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4398 23:54:01.370821  ==

 4399 23:54:01.373737  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4400 23:54:01.380515  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4401 23:54:01.383416  [CA 0] Center 36 (5~67) winsize 63

 4402 23:54:01.386893  [CA 1] Center 36 (5~67) winsize 63

 4403 23:54:01.390160  [CA 2] Center 34 (4~65) winsize 62

 4404 23:54:01.393840  [CA 3] Center 34 (4~65) winsize 62

 4405 23:54:01.397024  [CA 4] Center 35 (4~66) winsize 63

 4406 23:54:01.400253  [CA 5] Center 34 (3~65) winsize 63

 4407 23:54:01.400370  

 4408 23:54:01.403825  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4409 23:54:01.403935  

 4410 23:54:01.406744  [CATrainingPosCal] consider 2 rank data

 4411 23:54:01.410534  u2DelayCellTimex100 = 270/100 ps

 4412 23:54:01.413783  CA0 delay=36 (5~67),Diff = 2 PI (19 cell)

 4413 23:54:01.420070  CA1 delay=36 (5~67),Diff = 2 PI (19 cell)

 4414 23:54:01.423278  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4415 23:54:01.426522  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4416 23:54:01.430498  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4417 23:54:01.433795  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 4418 23:54:01.433902  

 4419 23:54:01.436930  CA PerBit enable=1, Macro0, CA PI delay=34

 4420 23:54:01.437006  

 4421 23:54:01.440235  [CBTSetCACLKResult] CA Dly = 34

 4422 23:54:01.440334  CS Dly: 6 (0~38)

 4423 23:54:01.443648  

 4424 23:54:01.446928  ----->DramcWriteLeveling(PI) begin...

 4425 23:54:01.447034  ==

 4426 23:54:01.450695  Dram Type= 6, Freq= 0, CH_1, rank 0

 4427 23:54:01.453728  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4428 23:54:01.453812  ==

 4429 23:54:01.456957  Write leveling (Byte 0): 30 => 30

 4430 23:54:01.460195  Write leveling (Byte 1): 30 => 30

 4431 23:54:01.463773  DramcWriteLeveling(PI) end<-----

 4432 23:54:01.463856  

 4433 23:54:01.463919  ==

 4434 23:54:01.466858  Dram Type= 6, Freq= 0, CH_1, rank 0

 4435 23:54:01.470110  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4436 23:54:01.470193  ==

 4437 23:54:01.473631  [Gating] SW mode calibration

 4438 23:54:01.479836  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4439 23:54:01.486931  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4440 23:54:01.489737   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4441 23:54:01.493938   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4442 23:54:01.500065   0  9  8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 4443 23:54:01.503263   0  9 12 | B1->B0 | 2f2f 2a2a | 1 1 | (1 1) (1 0)

 4444 23:54:01.506535   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 4445 23:54:01.510129   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4446 23:54:01.516594   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4447 23:54:01.519984   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4448 23:54:01.523063   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4449 23:54:01.529755   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4450 23:54:01.533506   0 10  8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)

 4451 23:54:01.536582   0 10 12 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)

 4452 23:54:01.543131   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4453 23:54:01.546785   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4454 23:54:01.549600   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4455 23:54:01.556220   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4456 23:54:01.559532   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4457 23:54:01.562746   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4458 23:54:01.569990   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4459 23:54:01.573471   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 4460 23:54:01.576600   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4461 23:54:01.583192   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4462 23:54:01.586492   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4463 23:54:01.589727   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4464 23:54:01.596028   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4465 23:54:01.599407   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4466 23:54:01.602718   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4467 23:54:01.609560   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4468 23:54:01.612697   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4469 23:54:01.616259   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4470 23:54:01.623165   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4471 23:54:01.625957   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4472 23:54:01.629349   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4473 23:54:01.636007   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4474 23:54:01.639251   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4475 23:54:01.642173   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4476 23:54:01.645948  Total UI for P1: 0, mck2ui 16

 4477 23:54:01.648970  best dqsien dly found for B0: ( 0, 13, 10)

 4478 23:54:01.655590   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4479 23:54:01.655675  Total UI for P1: 0, mck2ui 16

 4480 23:54:01.659112  best dqsien dly found for B1: ( 0, 13, 12)

 4481 23:54:01.665532  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4482 23:54:01.668762  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4483 23:54:01.668846  

 4484 23:54:01.672497  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4485 23:54:01.675962  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4486 23:54:01.678940  [Gating] SW calibration Done

 4487 23:54:01.679026  ==

 4488 23:54:01.682363  Dram Type= 6, Freq= 0, CH_1, rank 0

 4489 23:54:01.686040  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4490 23:54:01.686127  ==

 4491 23:54:01.688975  RX Vref Scan: 0

 4492 23:54:01.689049  

 4493 23:54:01.689112  RX Vref 0 -> 0, step: 1

 4494 23:54:01.689172  

 4495 23:54:01.692279  RX Delay -230 -> 252, step: 16

 4496 23:54:01.695617  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4497 23:54:01.702194  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4498 23:54:01.705343  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4499 23:54:01.709257  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4500 23:54:01.712442  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4501 23:54:01.719070  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4502 23:54:01.722383  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4503 23:54:01.725115  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4504 23:54:01.729069  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4505 23:54:01.732122  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4506 23:54:01.738965  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4507 23:54:01.742494  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4508 23:54:01.745598  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4509 23:54:01.749228  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4510 23:54:01.755729  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4511 23:54:01.758813  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4512 23:54:01.758904  ==

 4513 23:54:01.762062  Dram Type= 6, Freq= 0, CH_1, rank 0

 4514 23:54:01.765251  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4515 23:54:01.765333  ==

 4516 23:54:01.769007  DQS Delay:

 4517 23:54:01.769086  DQS0 = 0, DQS1 = 0

 4518 23:54:01.769164  DQM Delay:

 4519 23:54:01.772146  DQM0 = 50, DQM1 = 46

 4520 23:54:01.772221  DQ Delay:

 4521 23:54:01.775256  DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49

 4522 23:54:01.779003  DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49

 4523 23:54:01.781732  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4524 23:54:01.785318  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4525 23:54:01.785397  

 4526 23:54:01.785466  

 4527 23:54:01.785532  ==

 4528 23:54:01.788595  Dram Type= 6, Freq= 0, CH_1, rank 0

 4529 23:54:01.795180  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4530 23:54:01.795261  ==

 4531 23:54:01.795325  

 4532 23:54:01.795397  

 4533 23:54:01.795457  	TX Vref Scan disable

 4534 23:54:01.798847   == TX Byte 0 ==

 4535 23:54:01.802146  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4536 23:54:01.805419  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4537 23:54:01.808718   == TX Byte 1 ==

 4538 23:54:01.812544  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4539 23:54:01.816068  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4540 23:54:01.819195  ==

 4541 23:54:01.822449  Dram Type= 6, Freq= 0, CH_1, rank 0

 4542 23:54:01.825703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4543 23:54:01.825788  ==

 4544 23:54:01.825871  

 4545 23:54:01.825955  

 4546 23:54:01.829151  	TX Vref Scan disable

 4547 23:54:01.829234   == TX Byte 0 ==

 4548 23:54:01.835718  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4549 23:54:01.838677  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4550 23:54:01.838816   == TX Byte 1 ==

 4551 23:54:01.845620  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4552 23:54:01.849099  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4553 23:54:01.849181  

 4554 23:54:01.849246  [DATLAT]

 4555 23:54:01.852293  Freq=600, CH1 RK0

 4556 23:54:01.852382  

 4557 23:54:01.852460  DATLAT Default: 0x9

 4558 23:54:01.855358  0, 0xFFFF, sum = 0

 4559 23:54:01.855445  1, 0xFFFF, sum = 0

 4560 23:54:01.859218  2, 0xFFFF, sum = 0

 4561 23:54:01.859310  3, 0xFFFF, sum = 0

 4562 23:54:01.861921  4, 0xFFFF, sum = 0

 4563 23:54:01.865790  5, 0xFFFF, sum = 0

 4564 23:54:01.865876  6, 0xFFFF, sum = 0

 4565 23:54:01.869247  7, 0xFFFF, sum = 0

 4566 23:54:01.869366  8, 0x0, sum = 1

 4567 23:54:01.869469  9, 0x0, sum = 2

 4568 23:54:01.872439  10, 0x0, sum = 3

 4569 23:54:01.872516  11, 0x0, sum = 4

 4570 23:54:01.875636  best_step = 9

 4571 23:54:01.875713  

 4572 23:54:01.875789  ==

 4573 23:54:01.878619  Dram Type= 6, Freq= 0, CH_1, rank 0

 4574 23:54:01.882321  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4575 23:54:01.882409  ==

 4576 23:54:01.885551  RX Vref Scan: 1

 4577 23:54:01.885635  

 4578 23:54:01.885701  RX Vref 0 -> 0, step: 1

 4579 23:54:01.885762  

 4580 23:54:01.888751  RX Delay -163 -> 252, step: 8

 4581 23:54:01.888839  

 4582 23:54:01.892092  Set Vref, RX VrefLevel [Byte0]: 54

 4583 23:54:01.895342                           [Byte1]: 48

 4584 23:54:01.899493  

 4585 23:54:01.899575  Final RX Vref Byte 0 = 54 to rank0

 4586 23:54:01.903174  Final RX Vref Byte 1 = 48 to rank0

 4587 23:54:01.906156  Final RX Vref Byte 0 = 54 to rank1

 4588 23:54:01.909673  Final RX Vref Byte 1 = 48 to rank1==

 4589 23:54:01.913170  Dram Type= 6, Freq= 0, CH_1, rank 0

 4590 23:54:01.919431  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4591 23:54:01.919516  ==

 4592 23:54:01.919582  DQS Delay:

 4593 23:54:01.919642  DQS0 = 0, DQS1 = 0

 4594 23:54:01.922687  DQM Delay:

 4595 23:54:01.922770  DQM0 = 48, DQM1 = 44

 4596 23:54:01.926197  DQ Delay:

 4597 23:54:01.929529  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4598 23:54:01.929612  DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48

 4599 23:54:01.932832  DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36

 4600 23:54:01.939039  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52

 4601 23:54:01.939125  

 4602 23:54:01.939196  

 4603 23:54:01.945875  [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps

 4604 23:54:01.949317  CH1 RK0: MR19=808, MR18=486E

 4605 23:54:01.956335  CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115

 4606 23:54:01.956445  

 4607 23:54:01.959560  ----->DramcWriteLeveling(PI) begin...

 4608 23:54:01.959645  ==

 4609 23:54:01.962576  Dram Type= 6, Freq= 0, CH_1, rank 1

 4610 23:54:01.965707  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4611 23:54:01.965785  ==

 4612 23:54:01.969321  Write leveling (Byte 0): 31 => 31

 4613 23:54:01.972694  Write leveling (Byte 1): 31 => 31

 4614 23:54:01.975823  DramcWriteLeveling(PI) end<-----

 4615 23:54:01.975901  

 4616 23:54:01.975976  ==

 4617 23:54:01.978906  Dram Type= 6, Freq= 0, CH_1, rank 1

 4618 23:54:01.982699  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4619 23:54:01.982781  ==

 4620 23:54:01.985900  [Gating] SW mode calibration

 4621 23:54:01.991995  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4622 23:54:01.999044  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4623 23:54:02.002368   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4624 23:54:02.008870   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4625 23:54:02.012155   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4626 23:54:02.015291   0  9 12 | B1->B0 | 2e2e 3030 | 1 0 | (1 0) (0 1)

 4627 23:54:02.019044   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4628 23:54:02.025807   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4629 23:54:02.029098   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4630 23:54:02.032295   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4631 23:54:02.038951   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4632 23:54:02.042195   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4633 23:54:02.045259   0 10  8 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)

 4634 23:54:02.052382   0 10 12 | B1->B0 | 3838 3737 | 1 1 | (0 0) (0 0)

 4635 23:54:02.055420   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4636 23:54:02.058824   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4637 23:54:02.065261   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4638 23:54:02.068932   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4639 23:54:02.072073   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4640 23:54:02.078284   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4641 23:54:02.081926   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4642 23:54:02.084955   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4643 23:54:02.091523   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4644 23:54:02.095296   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4645 23:54:02.098279   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4646 23:54:02.104801   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4647 23:54:02.107921   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4648 23:54:02.111859   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4649 23:54:02.118393   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4650 23:54:02.121762   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4651 23:54:02.124834   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4652 23:54:02.131292   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4653 23:54:02.134896   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4654 23:54:02.138186   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4655 23:54:02.145058   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4656 23:54:02.148291   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4657 23:54:02.151680   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4658 23:54:02.158104   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4659 23:54:02.158188  Total UI for P1: 0, mck2ui 16

 4660 23:54:02.161825  best dqsien dly found for B0: ( 0, 13, 10)

 4661 23:54:02.165017  Total UI for P1: 0, mck2ui 16

 4662 23:54:02.168388  best dqsien dly found for B1: ( 0, 13, 10)

 4663 23:54:02.171394  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4664 23:54:02.177888  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4665 23:54:02.177973  

 4666 23:54:02.181217  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4667 23:54:02.184589  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4668 23:54:02.188118  [Gating] SW calibration Done

 4669 23:54:02.188231  ==

 4670 23:54:02.191731  Dram Type= 6, Freq= 0, CH_1, rank 1

 4671 23:54:02.194859  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4672 23:54:02.194982  ==

 4673 23:54:02.198244  RX Vref Scan: 0

 4674 23:54:02.198365  

 4675 23:54:02.198474  RX Vref 0 -> 0, step: 1

 4676 23:54:02.198580  

 4677 23:54:02.201412  RX Delay -230 -> 252, step: 16

 4678 23:54:02.205163  iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288

 4679 23:54:02.211329  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4680 23:54:02.215492  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4681 23:54:02.218080  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4682 23:54:02.221472  iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288

 4683 23:54:02.224752  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4684 23:54:02.231678  iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304

 4685 23:54:02.234583  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4686 23:54:02.237852  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4687 23:54:02.241495  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4688 23:54:02.248107  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4689 23:54:02.251280  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4690 23:54:02.254374  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4691 23:54:02.257579  iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304

 4692 23:54:02.261426  iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288

 4693 23:54:02.268078  iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304

 4694 23:54:02.268160  ==

 4695 23:54:02.271077  Dram Type= 6, Freq= 0, CH_1, rank 1

 4696 23:54:02.274331  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4697 23:54:02.274433  ==

 4698 23:54:02.274511  DQS Delay:

 4699 23:54:02.277689  DQS0 = 0, DQS1 = 0

 4700 23:54:02.277801  DQM Delay:

 4701 23:54:02.280831  DQM0 = 53, DQM1 = 50

 4702 23:54:02.280912  DQ Delay:

 4703 23:54:02.284776  DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49

 4704 23:54:02.287860  DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49

 4705 23:54:02.290793  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4706 23:54:02.294193  DQ12 =57, DQ13 =65, DQ14 =57, DQ15 =65

 4707 23:54:02.294274  

 4708 23:54:02.294337  

 4709 23:54:02.294395  ==

 4710 23:54:02.297810  Dram Type= 6, Freq= 0, CH_1, rank 1

 4711 23:54:02.300735  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4712 23:54:02.304184  ==

 4713 23:54:02.304264  

 4714 23:54:02.304327  

 4715 23:54:02.304409  	TX Vref Scan disable

 4716 23:54:02.307394   == TX Byte 0 ==

 4717 23:54:02.311346  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4718 23:54:02.314148  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4719 23:54:02.317690   == TX Byte 1 ==

 4720 23:54:02.320992  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4721 23:54:02.324189  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4722 23:54:02.327319  ==

 4723 23:54:02.327422  Dram Type= 6, Freq= 0, CH_1, rank 1

 4724 23:54:02.334089  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4725 23:54:02.334166  ==

 4726 23:54:02.334229  

 4727 23:54:02.334287  

 4728 23:54:02.337339  	TX Vref Scan disable

 4729 23:54:02.337421   == TX Byte 0 ==

 4730 23:54:02.344219  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4731 23:54:02.347326  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4732 23:54:02.347408   == TX Byte 1 ==

 4733 23:54:02.354297  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4734 23:54:02.357628  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4735 23:54:02.357710  

 4736 23:54:02.357792  [DATLAT]

 4737 23:54:02.361106  Freq=600, CH1 RK1

 4738 23:54:02.361190  

 4739 23:54:02.361254  DATLAT Default: 0x9

 4740 23:54:02.364463  0, 0xFFFF, sum = 0

 4741 23:54:02.364546  1, 0xFFFF, sum = 0

 4742 23:54:02.367629  2, 0xFFFF, sum = 0

 4743 23:54:02.367712  3, 0xFFFF, sum = 0

 4744 23:54:02.370646  4, 0xFFFF, sum = 0

 4745 23:54:02.370729  5, 0xFFFF, sum = 0

 4746 23:54:02.374199  6, 0xFFFF, sum = 0

 4747 23:54:02.374282  7, 0xFFFF, sum = 0

 4748 23:54:02.377209  8, 0x0, sum = 1

 4749 23:54:02.377291  9, 0x0, sum = 2

 4750 23:54:02.381096  10, 0x0, sum = 3

 4751 23:54:02.381179  11, 0x0, sum = 4

 4752 23:54:02.384331  best_step = 9

 4753 23:54:02.384455  

 4754 23:54:02.384519  ==

 4755 23:54:02.388085  Dram Type= 6, Freq= 0, CH_1, rank 1

 4756 23:54:02.391313  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4757 23:54:02.391397  ==

 4758 23:54:02.394796  RX Vref Scan: 0

 4759 23:54:02.394879  

 4760 23:54:02.394945  RX Vref 0 -> 0, step: 1

 4761 23:54:02.395023  

 4762 23:54:02.397523  RX Delay -163 -> 252, step: 8

 4763 23:54:02.403989  iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280

 4764 23:54:02.407777  iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288

 4765 23:54:02.410583  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4766 23:54:02.414140  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4767 23:54:02.417428  iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288

 4768 23:54:02.424324  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4769 23:54:02.427714  iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288

 4770 23:54:02.430703  iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296

 4771 23:54:02.434462  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4772 23:54:02.437390  iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296

 4773 23:54:02.444144  iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296

 4774 23:54:02.447549  iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296

 4775 23:54:02.450502  iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304

 4776 23:54:02.453776  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4777 23:54:02.460515  iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296

 4778 23:54:02.464383  iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288

 4779 23:54:02.464467  ==

 4780 23:54:02.467325  Dram Type= 6, Freq= 0, CH_1, rank 1

 4781 23:54:02.470550  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4782 23:54:02.470634  ==

 4783 23:54:02.473898  DQS Delay:

 4784 23:54:02.473981  DQS0 = 0, DQS1 = 0

 4785 23:54:02.474045  DQM Delay:

 4786 23:54:02.477153  DQM0 = 49, DQM1 = 44

 4787 23:54:02.477281  DQ Delay:

 4788 23:54:02.480461  DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44

 4789 23:54:02.483809  DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48

 4790 23:54:02.487050  DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40

 4791 23:54:02.490360  DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52

 4792 23:54:02.490443  

 4793 23:54:02.490508  

 4794 23:54:02.500200  [DQSOSCAuto] RK1, (LSB)MR18= 0x7025, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps

 4795 23:54:02.503984  CH1 RK1: MR19=808, MR18=7025

 4796 23:54:02.507542  CH1_RK1: MR19=0x808, MR18=0x7025, DQSOSC=388, MR23=63, INC=174, DEC=116

 4797 23:54:02.510534  [RxdqsGatingPostProcess] freq 600

 4798 23:54:02.516730  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4799 23:54:02.520348  Pre-setting of DQS Precalculation

 4800 23:54:02.523501  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4801 23:54:02.533161  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4802 23:54:02.539709  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4803 23:54:02.539821  

 4804 23:54:02.539916  

 4805 23:54:02.543612  [Calibration Summary] 1200 Mbps

 4806 23:54:02.543700  CH 0, Rank 0

 4807 23:54:02.546918  SW Impedance     : PASS

 4808 23:54:02.547001  DUTY Scan        : NO K

 4809 23:54:02.549815  ZQ Calibration   : PASS

 4810 23:54:02.553231  Jitter Meter     : NO K

 4811 23:54:02.553314  CBT Training     : PASS

 4812 23:54:02.556194  Write leveling   : PASS

 4813 23:54:02.560004  RX DQS gating    : PASS

 4814 23:54:02.560086  RX DQ/DQS(RDDQC) : PASS

 4815 23:54:02.563235  TX DQ/DQS        : PASS

 4816 23:54:02.566634  RX DATLAT        : PASS

 4817 23:54:02.566715  RX DQ/DQS(Engine): PASS

 4818 23:54:02.569607  TX OE            : NO K

 4819 23:54:02.569722  All Pass.

 4820 23:54:02.569802  

 4821 23:54:02.573038  CH 0, Rank 1

 4822 23:54:02.573119  SW Impedance     : PASS

 4823 23:54:02.576199  DUTY Scan        : NO K

 4824 23:54:02.579794  ZQ Calibration   : PASS

 4825 23:54:02.579876  Jitter Meter     : NO K

 4826 23:54:02.582784  CBT Training     : PASS

 4827 23:54:02.582866  Write leveling   : PASS

 4828 23:54:02.586778  RX DQS gating    : PASS

 4829 23:54:02.589664  RX DQ/DQS(RDDQC) : PASS

 4830 23:54:02.589792  TX DQ/DQS        : PASS

 4831 23:54:02.593034  RX DATLAT        : PASS

 4832 23:54:02.596432  RX DQ/DQS(Engine): PASS

 4833 23:54:02.596556  TX OE            : NO K

 4834 23:54:02.599708  All Pass.

 4835 23:54:02.599830  

 4836 23:54:02.599942  CH 1, Rank 0

 4837 23:54:02.603129  SW Impedance     : PASS

 4838 23:54:02.603250  DUTY Scan        : NO K

 4839 23:54:02.606282  ZQ Calibration   : PASS

 4840 23:54:02.609706  Jitter Meter     : NO K

 4841 23:54:02.609828  CBT Training     : PASS

 4842 23:54:02.613291  Write leveling   : PASS

 4843 23:54:02.616489  RX DQS gating    : PASS

 4844 23:54:02.616613  RX DQ/DQS(RDDQC) : PASS

 4845 23:54:02.619934  TX DQ/DQS        : PASS

 4846 23:54:02.622830  RX DATLAT        : PASS

 4847 23:54:02.622954  RX DQ/DQS(Engine): PASS

 4848 23:54:02.626322  TX OE            : NO K

 4849 23:54:02.626444  All Pass.

 4850 23:54:02.626559  

 4851 23:54:02.626664  CH 1, Rank 1

 4852 23:54:02.629835  SW Impedance     : PASS

 4853 23:54:02.632831  DUTY Scan        : NO K

 4854 23:54:02.632956  ZQ Calibration   : PASS

 4855 23:54:02.636485  Jitter Meter     : NO K

 4856 23:54:02.639857  CBT Training     : PASS

 4857 23:54:02.639985  Write leveling   : PASS

 4858 23:54:02.643323  RX DQS gating    : PASS

 4859 23:54:02.646291  RX DQ/DQS(RDDQC) : PASS

 4860 23:54:02.646376  TX DQ/DQS        : PASS

 4861 23:54:02.649453  RX DATLAT        : PASS

 4862 23:54:02.652958  RX DQ/DQS(Engine): PASS

 4863 23:54:02.653043  TX OE            : NO K

 4864 23:54:02.656330  All Pass.

 4865 23:54:02.656421  

 4866 23:54:02.656486  DramC Write-DBI off

 4867 23:54:02.659276  	PER_BANK_REFRESH: Hybrid Mode

 4868 23:54:02.659359  TX_TRACKING: ON

 4869 23:54:02.669501  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4870 23:54:02.672550  [FAST_K] Save calibration result to emmc

 4871 23:54:02.676149  dramc_set_vcore_voltage set vcore to 662500

 4872 23:54:02.679468  Read voltage for 933, 3

 4873 23:54:02.679551  Vio18 = 0

 4874 23:54:02.682688  Vcore = 662500

 4875 23:54:02.682800  Vdram = 0

 4876 23:54:02.682898  Vddq = 0

 4877 23:54:02.685726  Vmddr = 0

 4878 23:54:02.689472  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4879 23:54:02.695605  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4880 23:54:02.695690  MEM_TYPE=3, freq_sel=17

 4881 23:54:02.698955  sv_algorithm_assistance_LP4_1600 

 4882 23:54:02.705622  ============ PULL DRAM RESETB DOWN ============

 4883 23:54:02.709101  ========== PULL DRAM RESETB DOWN end =========

 4884 23:54:02.712560  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4885 23:54:02.715847  =================================== 

 4886 23:54:02.719266  LPDDR4 DRAM CONFIGURATION

 4887 23:54:02.722578  =================================== 

 4888 23:54:02.722662  EX_ROW_EN[0]    = 0x0

 4889 23:54:02.725678  EX_ROW_EN[1]    = 0x0

 4890 23:54:02.728875  LP4Y_EN      = 0x0

 4891 23:54:02.728958  WORK_FSP     = 0x0

 4892 23:54:02.732809  WL           = 0x3

 4893 23:54:02.732892  RL           = 0x3

 4894 23:54:02.735771  BL           = 0x2

 4895 23:54:02.735853  RPST         = 0x0

 4896 23:54:02.738827  RD_PRE       = 0x0

 4897 23:54:02.738910  WR_PRE       = 0x1

 4898 23:54:02.742501  WR_PST       = 0x0

 4899 23:54:02.742612  DBI_WR       = 0x0

 4900 23:54:02.745878  DBI_RD       = 0x0

 4901 23:54:02.745961  OTF          = 0x1

 4902 23:54:02.749469  =================================== 

 4903 23:54:02.752206  =================================== 

 4904 23:54:02.755492  ANA top config

 4905 23:54:02.758809  =================================== 

 4906 23:54:02.758893  DLL_ASYNC_EN            =  0

 4907 23:54:02.762119  ALL_SLAVE_EN            =  1

 4908 23:54:02.765779  NEW_RANK_MODE           =  1

 4909 23:54:02.769093  DLL_IDLE_MODE           =  1

 4910 23:54:02.772182  LP45_APHY_COMB_EN       =  1

 4911 23:54:02.772264  TX_ODT_DIS              =  1

 4912 23:54:02.775472  NEW_8X_MODE             =  1

 4913 23:54:02.779011  =================================== 

 4914 23:54:02.782166  =================================== 

 4915 23:54:02.785954  data_rate                  = 1866

 4916 23:54:02.788854  CKR                        = 1

 4917 23:54:02.791970  DQ_P2S_RATIO               = 8

 4918 23:54:02.795508  =================================== 

 4919 23:54:02.795591  CA_P2S_RATIO               = 8

 4920 23:54:02.798949  DQ_CA_OPEN                 = 0

 4921 23:54:02.801824  DQ_SEMI_OPEN               = 0

 4922 23:54:02.805293  CA_SEMI_OPEN               = 0

 4923 23:54:02.809164  CA_FULL_RATE               = 0

 4924 23:54:02.811967  DQ_CKDIV4_EN               = 1

 4925 23:54:02.812052  CA_CKDIV4_EN               = 1

 4926 23:54:02.815643  CA_PREDIV_EN               = 0

 4927 23:54:02.818852  PH8_DLY                    = 0

 4928 23:54:02.822080  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4929 23:54:02.825506  DQ_AAMCK_DIV               = 4

 4930 23:54:02.828587  CA_AAMCK_DIV               = 4

 4931 23:54:02.828713  CA_ADMCK_DIV               = 4

 4932 23:54:02.832214  DQ_TRACK_CA_EN             = 0

 4933 23:54:02.835656  CA_PICK                    = 933

 4934 23:54:02.838781  CA_MCKIO                   = 933

 4935 23:54:02.841883  MCKIO_SEMI                 = 0

 4936 23:54:02.845106  PLL_FREQ                   = 3732

 4937 23:54:02.848841  DQ_UI_PI_RATIO             = 32

 4938 23:54:02.848924  CA_UI_PI_RATIO             = 0

 4939 23:54:02.852046  =================================== 

 4940 23:54:02.855092  =================================== 

 4941 23:54:02.858994  memory_type:LPDDR4         

 4942 23:54:02.862276  GP_NUM     : 10       

 4943 23:54:02.862358  SRAM_EN    : 1       

 4944 23:54:02.865438  MD32_EN    : 0       

 4945 23:54:02.868655  =================================== 

 4946 23:54:02.872054  [ANA_INIT] >>>>>>>>>>>>>> 

 4947 23:54:02.875090  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4948 23:54:02.878588  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4949 23:54:02.881629  =================================== 

 4950 23:54:02.881711  data_rate = 1866,PCW = 0X8f00

 4951 23:54:02.885257  =================================== 

 4952 23:54:02.888203  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4953 23:54:02.894735  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4954 23:54:02.902014  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4955 23:54:02.905166  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4956 23:54:02.908287  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4957 23:54:02.911446  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4958 23:54:02.915095  [ANA_INIT] flow start 

 4959 23:54:02.918120  [ANA_INIT] PLL >>>>>>>> 

 4960 23:54:02.918227  [ANA_INIT] PLL <<<<<<<< 

 4961 23:54:02.921435  [ANA_INIT] MIDPI >>>>>>>> 

 4962 23:54:02.924479  [ANA_INIT] MIDPI <<<<<<<< 

 4963 23:54:02.924561  [ANA_INIT] DLL >>>>>>>> 

 4964 23:54:02.927831  [ANA_INIT] flow end 

 4965 23:54:02.931199  ============ LP4 DIFF to SE enter ============

 4966 23:54:02.934750  ============ LP4 DIFF to SE exit  ============

 4967 23:54:02.938337  [ANA_INIT] <<<<<<<<<<<<< 

 4968 23:54:02.941760  [Flow] Enable top DCM control >>>>> 

 4969 23:54:02.944962  [Flow] Enable top DCM control <<<<< 

 4970 23:54:02.948371  Enable DLL master slave shuffle 

 4971 23:54:02.954657  ============================================================== 

 4972 23:54:02.954759  Gating Mode config

 4973 23:54:02.961214  ============================================================== 

 4974 23:54:02.961328  Config description: 

 4975 23:54:02.971186  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4976 23:54:02.977828  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4977 23:54:02.984928  SELPH_MODE            0: By rank         1: By Phase 

 4978 23:54:02.988158  ============================================================== 

 4979 23:54:02.991361  GAT_TRACK_EN                 =  1

 4980 23:54:02.994684  RX_GATING_MODE               =  2

 4981 23:54:02.998064  RX_GATING_TRACK_MODE         =  2

 4982 23:54:03.001238  SELPH_MODE                   =  1

 4983 23:54:03.004794  PICG_EARLY_EN                =  1

 4984 23:54:03.007883  VALID_LAT_VALUE              =  1

 4985 23:54:03.014633  ============================================================== 

 4986 23:54:03.017660  Enter into Gating configuration >>>> 

 4987 23:54:03.020982  Exit from Gating configuration <<<< 

 4988 23:54:03.021105  Enter into  DVFS_PRE_config >>>>> 

 4989 23:54:03.034679  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4990 23:54:03.037528  Exit from  DVFS_PRE_config <<<<< 

 4991 23:54:03.040934  Enter into PICG configuration >>>> 

 4992 23:54:03.044181  Exit from PICG configuration <<<< 

 4993 23:54:03.044296  [RX_INPUT] configuration >>>>> 

 4994 23:54:03.047892  [RX_INPUT] configuration <<<<< 

 4995 23:54:03.054153  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4996 23:54:03.060960  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4997 23:54:03.064080  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4998 23:54:03.070528  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4999 23:54:03.077382  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5000 23:54:03.083701  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5001 23:54:03.087348  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5002 23:54:03.090661  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5003 23:54:03.097512  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5004 23:54:03.100717  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5005 23:54:03.103925  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5006 23:54:03.110485  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5007 23:54:03.113465  =================================== 

 5008 23:54:03.113550  LPDDR4 DRAM CONFIGURATION

 5009 23:54:03.117075  =================================== 

 5010 23:54:03.120296  EX_ROW_EN[0]    = 0x0

 5011 23:54:03.120403  EX_ROW_EN[1]    = 0x0

 5012 23:54:03.123740  LP4Y_EN      = 0x0

 5013 23:54:03.123846  WORK_FSP     = 0x0

 5014 23:54:03.126873  WL           = 0x3

 5015 23:54:03.130123  RL           = 0x3

 5016 23:54:03.130228  BL           = 0x2

 5017 23:54:03.133404  RPST         = 0x0

 5018 23:54:03.133490  RD_PRE       = 0x0

 5019 23:54:03.136725  WR_PRE       = 0x1

 5020 23:54:03.136803  WR_PST       = 0x0

 5021 23:54:03.139938  DBI_WR       = 0x0

 5022 23:54:03.140040  DBI_RD       = 0x0

 5023 23:54:03.143691  OTF          = 0x1

 5024 23:54:03.146840  =================================== 

 5025 23:54:03.150017  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5026 23:54:03.153145  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5027 23:54:03.157077  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5028 23:54:03.159751  =================================== 

 5029 23:54:03.163509  LPDDR4 DRAM CONFIGURATION

 5030 23:54:03.167003  =================================== 

 5031 23:54:03.170074  EX_ROW_EN[0]    = 0x10

 5032 23:54:03.170177  EX_ROW_EN[1]    = 0x0

 5033 23:54:03.173386  LP4Y_EN      = 0x0

 5034 23:54:03.173461  WORK_FSP     = 0x0

 5035 23:54:03.176300  WL           = 0x3

 5036 23:54:03.176410  RL           = 0x3

 5037 23:54:03.179989  BL           = 0x2

 5038 23:54:03.183106  RPST         = 0x0

 5039 23:54:03.183208  RD_PRE       = 0x0

 5040 23:54:03.186538  WR_PRE       = 0x1

 5041 23:54:03.186632  WR_PST       = 0x0

 5042 23:54:03.189960  DBI_WR       = 0x0

 5043 23:54:03.190068  DBI_RD       = 0x0

 5044 23:54:03.193054  OTF          = 0x1

 5045 23:54:03.196740  =================================== 

 5046 23:54:03.199690  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5047 23:54:03.205395  nWR fixed to 30

 5048 23:54:03.208787  [ModeRegInit_LP4] CH0 RK0

 5049 23:54:03.208893  [ModeRegInit_LP4] CH0 RK1

 5050 23:54:03.211966  [ModeRegInit_LP4] CH1 RK0

 5051 23:54:03.215100  [ModeRegInit_LP4] CH1 RK1

 5052 23:54:03.215223  match AC timing 9

 5053 23:54:03.222134  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5054 23:54:03.225236  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5055 23:54:03.228733  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5056 23:54:03.235282  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5057 23:54:03.238730  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5058 23:54:03.238818  ==

 5059 23:54:03.242354  Dram Type= 6, Freq= 0, CH_0, rank 0

 5060 23:54:03.245139  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5061 23:54:03.245281  ==

 5062 23:54:03.252087  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5063 23:54:03.258673  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5064 23:54:03.261773  [CA 0] Center 37 (6~68) winsize 63

 5065 23:54:03.264954  [CA 1] Center 37 (7~68) winsize 62

 5066 23:54:03.268837  [CA 2] Center 34 (4~65) winsize 62

 5067 23:54:03.272018  [CA 3] Center 34 (3~65) winsize 63

 5068 23:54:03.275590  [CA 4] Center 33 (3~64) winsize 62

 5069 23:54:03.278660  [CA 5] Center 32 (2~62) winsize 61

 5070 23:54:03.278786  

 5071 23:54:03.281904  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5072 23:54:03.282029  

 5073 23:54:03.285133  [CATrainingPosCal] consider 1 rank data

 5074 23:54:03.288235  u2DelayCellTimex100 = 270/100 ps

 5075 23:54:03.291899  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5076 23:54:03.294915  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5077 23:54:03.298411  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5078 23:54:03.301770  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5079 23:54:03.305588  CA4 delay=33 (3~64),Diff = 1 PI (6 cell)

 5080 23:54:03.308519  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5081 23:54:03.311547  

 5082 23:54:03.314954  CA PerBit enable=1, Macro0, CA PI delay=32

 5083 23:54:03.315078  

 5084 23:54:03.318327  [CBTSetCACLKResult] CA Dly = 32

 5085 23:54:03.318453  CS Dly: 5 (0~36)

 5086 23:54:03.318565  ==

 5087 23:54:03.321411  Dram Type= 6, Freq= 0, CH_0, rank 1

 5088 23:54:03.324996  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5089 23:54:03.325098  ==

 5090 23:54:03.331369  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5091 23:54:03.338330  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5092 23:54:03.341743  [CA 0] Center 37 (6~68) winsize 63

 5093 23:54:03.344937  [CA 1] Center 37 (7~68) winsize 62

 5094 23:54:03.348607  [CA 2] Center 34 (4~65) winsize 62

 5095 23:54:03.351305  [CA 3] Center 33 (3~64) winsize 62

 5096 23:54:03.354693  [CA 4] Center 33 (3~63) winsize 61

 5097 23:54:03.358091  [CA 5] Center 32 (2~63) winsize 62

 5098 23:54:03.358173  

 5099 23:54:03.361229  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5100 23:54:03.361311  

 5101 23:54:03.364598  [CATrainingPosCal] consider 2 rank data

 5102 23:54:03.368175  u2DelayCellTimex100 = 270/100 ps

 5103 23:54:03.371567  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5104 23:54:03.374584  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5105 23:54:03.378116  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5106 23:54:03.381083  CA3 delay=33 (3~64),Diff = 1 PI (6 cell)

 5107 23:54:03.384429  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5108 23:54:03.391624  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5109 23:54:03.391703  

 5110 23:54:03.394960  CA PerBit enable=1, Macro0, CA PI delay=32

 5111 23:54:03.395048  

 5112 23:54:03.398124  [CBTSetCACLKResult] CA Dly = 32

 5113 23:54:03.398205  CS Dly: 6 (0~38)

 5114 23:54:03.398268  

 5115 23:54:03.401490  ----->DramcWriteLeveling(PI) begin...

 5116 23:54:03.401620  ==

 5117 23:54:03.404848  Dram Type= 6, Freq= 0, CH_0, rank 0

 5118 23:54:03.411052  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5119 23:54:03.411134  ==

 5120 23:54:03.414691  Write leveling (Byte 0): 31 => 31

 5121 23:54:03.414814  Write leveling (Byte 1): 29 => 29

 5122 23:54:03.418206  DramcWriteLeveling(PI) end<-----

 5123 23:54:03.418287  

 5124 23:54:03.418366  ==

 5125 23:54:03.421447  Dram Type= 6, Freq= 0, CH_0, rank 0

 5126 23:54:03.427595  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5127 23:54:03.427679  ==

 5128 23:54:03.431394  [Gating] SW mode calibration

 5129 23:54:03.437573  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5130 23:54:03.441023  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5131 23:54:03.447392   0 14  0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)

 5132 23:54:03.450902   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5133 23:54:03.454526   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5134 23:54:03.461349   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5135 23:54:03.464059   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5136 23:54:03.467600   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5137 23:54:03.474349   0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)

 5138 23:54:03.477307   0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 1)

 5139 23:54:03.480644   0 15  0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)

 5140 23:54:03.487748   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5141 23:54:03.490617   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5142 23:54:03.494328   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5143 23:54:03.497667   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5144 23:54:03.504265   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5145 23:54:03.507448   0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 5146 23:54:03.510807   0 15 28 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)

 5147 23:54:03.517565   1  0  0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)

 5148 23:54:03.520698   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5149 23:54:03.524377   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5150 23:54:03.530598   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5151 23:54:03.533954   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5152 23:54:03.537858   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5153 23:54:03.544070   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5154 23:54:03.549103   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5155 23:54:03.551002   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5156 23:54:03.557224   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5157 23:54:03.560629   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5158 23:54:03.563858   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5159 23:54:03.570100   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5160 23:54:03.574258   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5161 23:54:03.577132   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5162 23:54:03.583567   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5163 23:54:03.586949   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5164 23:54:03.590155   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5165 23:54:03.596703   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5166 23:54:03.599936   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5167 23:54:03.603849   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5168 23:54:03.610519   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5169 23:54:03.613696   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5170 23:54:03.616877   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5171 23:54:03.623511   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5172 23:54:03.623636  Total UI for P1: 0, mck2ui 16

 5173 23:54:03.630095  best dqsien dly found for B0: ( 1,  2, 26)

 5174 23:54:03.630206  Total UI for P1: 0, mck2ui 16

 5175 23:54:03.633602  best dqsien dly found for B1: ( 1,  2, 30)

 5176 23:54:03.640098  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5177 23:54:03.643578  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5178 23:54:03.643698  

 5179 23:54:03.646730  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5180 23:54:03.649912  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5181 23:54:03.653660  [Gating] SW calibration Done

 5182 23:54:03.653781  ==

 5183 23:54:03.657195  Dram Type= 6, Freq= 0, CH_0, rank 0

 5184 23:54:03.660080  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5185 23:54:03.660203  ==

 5186 23:54:03.663371  RX Vref Scan: 0

 5187 23:54:03.663492  

 5188 23:54:03.663604  RX Vref 0 -> 0, step: 1

 5189 23:54:03.663710  

 5190 23:54:03.666876  RX Delay -80 -> 252, step: 8

 5191 23:54:03.670309  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5192 23:54:03.673327  iDelay=208, Bit 1, Center 103 (8 ~ 199) 192

 5193 23:54:03.680202  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5194 23:54:03.683543  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5195 23:54:03.686809  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5196 23:54:03.689963  iDelay=208, Bit 5, Center 95 (8 ~ 183) 176

 5197 23:54:03.693743  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5198 23:54:03.696452  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5199 23:54:03.703477  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5200 23:54:03.706973  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5201 23:54:03.709994  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5202 23:54:03.713265  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5203 23:54:03.716588  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5204 23:54:03.719791  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5205 23:54:03.726995  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5206 23:54:03.730287  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5207 23:54:03.730386  ==

 5208 23:54:03.733336  Dram Type= 6, Freq= 0, CH_0, rank 0

 5209 23:54:03.736287  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5210 23:54:03.736386  ==

 5211 23:54:03.739895  DQS Delay:

 5212 23:54:03.739989  DQS0 = 0, DQS1 = 0

 5213 23:54:03.740094  DQM Delay:

 5214 23:54:03.743126  DQM0 = 104, DQM1 = 95

 5215 23:54:03.743240  DQ Delay:

 5216 23:54:03.746809  DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99

 5217 23:54:03.749537  DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115

 5218 23:54:03.753320  DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91

 5219 23:54:03.756520  DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99

 5220 23:54:03.756648  

 5221 23:54:03.759316  

 5222 23:54:03.759440  ==

 5223 23:54:03.762972  Dram Type= 6, Freq= 0, CH_0, rank 0

 5224 23:54:03.766120  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5225 23:54:03.766233  ==

 5226 23:54:03.766331  

 5227 23:54:03.766426  

 5228 23:54:03.769593  	TX Vref Scan disable

 5229 23:54:03.769695   == TX Byte 0 ==

 5230 23:54:03.776084  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5231 23:54:03.779739  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5232 23:54:03.779833   == TX Byte 1 ==

 5233 23:54:03.786301  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5234 23:54:03.789313  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5235 23:54:03.789395  ==

 5236 23:54:03.792870  Dram Type= 6, Freq= 0, CH_0, rank 0

 5237 23:54:03.795907  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5238 23:54:03.795997  ==

 5239 23:54:03.796062  

 5240 23:54:03.796120  

 5241 23:54:03.799360  	TX Vref Scan disable

 5242 23:54:03.802854   == TX Byte 0 ==

 5243 23:54:03.805913  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5244 23:54:03.808895  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5245 23:54:03.813100   == TX Byte 1 ==

 5246 23:54:03.816208  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5247 23:54:03.819318  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5248 23:54:03.819436  

 5249 23:54:03.822564  [DATLAT]

 5250 23:54:03.822686  Freq=933, CH0 RK0

 5251 23:54:03.822800  

 5252 23:54:03.825756  DATLAT Default: 0xd

 5253 23:54:03.825860  0, 0xFFFF, sum = 0

 5254 23:54:03.829181  1, 0xFFFF, sum = 0

 5255 23:54:03.829264  2, 0xFFFF, sum = 0

 5256 23:54:03.832205  3, 0xFFFF, sum = 0

 5257 23:54:03.832315  4, 0xFFFF, sum = 0

 5258 23:54:03.835709  5, 0xFFFF, sum = 0

 5259 23:54:03.835786  6, 0xFFFF, sum = 0

 5260 23:54:03.839064  7, 0xFFFF, sum = 0

 5261 23:54:03.839167  8, 0xFFFF, sum = 0

 5262 23:54:03.842114  9, 0xFFFF, sum = 0

 5263 23:54:03.842224  10, 0x0, sum = 1

 5264 23:54:03.845424  11, 0x0, sum = 2

 5265 23:54:03.845538  12, 0x0, sum = 3

 5266 23:54:03.848689  13, 0x0, sum = 4

 5267 23:54:03.848765  best_step = 11

 5268 23:54:03.848826  

 5269 23:54:03.848883  ==

 5270 23:54:03.852548  Dram Type= 6, Freq= 0, CH_0, rank 0

 5271 23:54:03.858678  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5272 23:54:03.858800  ==

 5273 23:54:03.858916  RX Vref Scan: 1

 5274 23:54:03.859030  

 5275 23:54:03.862187  RX Vref 0 -> 0, step: 1

 5276 23:54:03.862305  

 5277 23:54:03.865587  RX Delay -45 -> 252, step: 4

 5278 23:54:03.865712  

 5279 23:54:03.869097  Set Vref, RX VrefLevel [Byte0]: 54

 5280 23:54:03.872039                           [Byte1]: 48

 5281 23:54:03.872160  

 5282 23:54:03.875189  Final RX Vref Byte 0 = 54 to rank0

 5283 23:54:03.878687  Final RX Vref Byte 1 = 48 to rank0

 5284 23:54:03.882035  Final RX Vref Byte 0 = 54 to rank1

 5285 23:54:03.885672  Final RX Vref Byte 1 = 48 to rank1==

 5286 23:54:03.888808  Dram Type= 6, Freq= 0, CH_0, rank 0

 5287 23:54:03.891942  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5288 23:54:03.892065  ==

 5289 23:54:03.895259  DQS Delay:

 5290 23:54:03.895382  DQS0 = 0, DQS1 = 0

 5291 23:54:03.895494  DQM Delay:

 5292 23:54:03.898651  DQM0 = 104, DQM1 = 95

 5293 23:54:03.898794  DQ Delay:

 5294 23:54:03.902332  DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102

 5295 23:54:03.905239  DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110

 5296 23:54:03.908966  DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =88

 5297 23:54:03.915228  DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102

 5298 23:54:03.915352  

 5299 23:54:03.915463  

 5300 23:54:03.921986  [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps

 5301 23:54:03.925532  CH0 RK0: MR19=505, MR18=322A

 5302 23:54:03.931917  CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43

 5303 23:54:03.932050  

 5304 23:54:03.935248  ----->DramcWriteLeveling(PI) begin...

 5305 23:54:03.935355  ==

 5306 23:54:03.938245  Dram Type= 6, Freq= 0, CH_0, rank 1

 5307 23:54:03.941730  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5308 23:54:03.941829  ==

 5309 23:54:03.945294  Write leveling (Byte 0): 34 => 34

 5310 23:54:03.948649  Write leveling (Byte 1): 29 => 29

 5311 23:54:03.951821  DramcWriteLeveling(PI) end<-----

 5312 23:54:03.951896  

 5313 23:54:03.951965  ==

 5314 23:54:03.955038  Dram Type= 6, Freq= 0, CH_0, rank 1

 5315 23:54:03.958397  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5316 23:54:03.958497  ==

 5317 23:54:03.961340  [Gating] SW mode calibration

 5318 23:54:03.968320  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5319 23:54:03.974996  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5320 23:54:03.978186   0 14  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 5321 23:54:03.985168   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5322 23:54:03.988463   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5323 23:54:03.991671   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5324 23:54:03.998124   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5325 23:54:04.001448   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5326 23:54:04.004784   0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)

 5327 23:54:04.011099   0 14 28 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 0)

 5328 23:54:04.014643   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5329 23:54:04.018299   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5330 23:54:04.024349   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5331 23:54:04.027489   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5332 23:54:04.031221   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5333 23:54:04.034727   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5334 23:54:04.041025   0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)

 5335 23:54:04.044586   0 15 28 | B1->B0 | 3d3d 3b3b | 1 1 | (1 1) (0 0)

 5336 23:54:04.047339   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5337 23:54:04.054354   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5338 23:54:04.057528   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5339 23:54:04.060743   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5340 23:54:04.068062   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5341 23:54:04.071023   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5342 23:54:04.074077   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5343 23:54:04.081129   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5344 23:54:04.084355   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5345 23:54:04.087495   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5346 23:54:04.093860   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5347 23:54:04.097409   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5348 23:54:04.100734   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5349 23:54:04.107322   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5350 23:54:04.110525   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5351 23:54:04.113964   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5352 23:54:04.120552   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5353 23:54:04.124203   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5354 23:54:04.127113   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5355 23:54:04.134036   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5356 23:54:04.137077   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5357 23:54:04.140849   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5358 23:54:04.147402   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5359 23:54:04.151070   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5360 23:54:04.154120   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5361 23:54:04.157514  Total UI for P1: 0, mck2ui 16

 5362 23:54:04.160836  best dqsien dly found for B0: ( 1,  2, 28)

 5363 23:54:04.164434  Total UI for P1: 0, mck2ui 16

 5364 23:54:04.167663  best dqsien dly found for B1: ( 1,  2, 28)

 5365 23:54:04.171070  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5366 23:54:04.174280  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5367 23:54:04.174417  

 5368 23:54:04.177665  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5369 23:54:04.184202  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5370 23:54:04.184330  [Gating] SW calibration Done

 5371 23:54:04.184493  ==

 5372 23:54:04.187413  Dram Type= 6, Freq= 0, CH_0, rank 1

 5373 23:54:04.193958  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5374 23:54:04.194094  ==

 5375 23:54:04.194202  RX Vref Scan: 0

 5376 23:54:04.194325  

 5377 23:54:04.197264  RX Vref 0 -> 0, step: 1

 5378 23:54:04.197390  

 5379 23:54:04.201147  RX Delay -80 -> 252, step: 8

 5380 23:54:04.203917  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5381 23:54:04.207143  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5382 23:54:04.210659  iDelay=208, Bit 2, Center 103 (8 ~ 199) 192

 5383 23:54:04.213589  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5384 23:54:04.221391  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5385 23:54:04.224021  iDelay=208, Bit 5, Center 99 (8 ~ 191) 184

 5386 23:54:04.227431  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5387 23:54:04.230568  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5388 23:54:04.234268  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5389 23:54:04.237249  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5390 23:54:04.244038  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5391 23:54:04.247623  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5392 23:54:04.250412  iDelay=208, Bit 12, Center 95 (8 ~ 183) 176

 5393 23:54:04.254251  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5394 23:54:04.257407  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5395 23:54:04.264001  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5396 23:54:04.264082  ==

 5397 23:54:04.266910  Dram Type= 6, Freq= 0, CH_0, rank 1

 5398 23:54:04.270675  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5399 23:54:04.270792  ==

 5400 23:54:04.270951  DQS Delay:

 5401 23:54:04.274002  DQS0 = 0, DQS1 = 0

 5402 23:54:04.274083  DQM Delay:

 5403 23:54:04.277357  DQM0 = 105, DQM1 = 93

 5404 23:54:04.277438  DQ Delay:

 5405 23:54:04.280369  DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99

 5406 23:54:04.284025  DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115

 5407 23:54:04.287334  DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87

 5408 23:54:04.290294  DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99

 5409 23:54:04.290374  

 5410 23:54:04.290436  

 5411 23:54:04.290493  ==

 5412 23:54:04.293500  Dram Type= 6, Freq= 0, CH_0, rank 1

 5413 23:54:04.296843  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5414 23:54:04.300302  ==

 5415 23:54:04.300457  

 5416 23:54:04.300568  

 5417 23:54:04.300673  	TX Vref Scan disable

 5418 23:54:04.303300   == TX Byte 0 ==

 5419 23:54:04.306706  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5420 23:54:04.310303  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5421 23:54:04.313669   == TX Byte 1 ==

 5422 23:54:04.316540  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5423 23:54:04.320055  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5424 23:54:04.323604  ==

 5425 23:54:04.326845  Dram Type= 6, Freq= 0, CH_0, rank 1

 5426 23:54:04.330193  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5427 23:54:04.330302  ==

 5428 23:54:04.330397  

 5429 23:54:04.330482  

 5430 23:54:04.333366  	TX Vref Scan disable

 5431 23:54:04.333450   == TX Byte 0 ==

 5432 23:54:04.339771  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5433 23:54:04.343040  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5434 23:54:04.343155   == TX Byte 1 ==

 5435 23:54:04.349569  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5436 23:54:04.352832  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5437 23:54:04.352929  

 5438 23:54:04.352996  [DATLAT]

 5439 23:54:04.356231  Freq=933, CH0 RK1

 5440 23:54:04.356322  

 5441 23:54:04.356403  DATLAT Default: 0xb

 5442 23:54:04.359613  0, 0xFFFF, sum = 0

 5443 23:54:04.363183  1, 0xFFFF, sum = 0

 5444 23:54:04.363280  2, 0xFFFF, sum = 0

 5445 23:54:04.366574  3, 0xFFFF, sum = 0

 5446 23:54:04.366667  4, 0xFFFF, sum = 0

 5447 23:54:04.369557  5, 0xFFFF, sum = 0

 5448 23:54:04.369638  6, 0xFFFF, sum = 0

 5449 23:54:04.373189  7, 0xFFFF, sum = 0

 5450 23:54:04.373278  8, 0xFFFF, sum = 0

 5451 23:54:04.376313  9, 0xFFFF, sum = 0

 5452 23:54:04.376400  10, 0x0, sum = 1

 5453 23:54:04.379452  11, 0x0, sum = 2

 5454 23:54:04.379540  12, 0x0, sum = 3

 5455 23:54:04.379608  13, 0x0, sum = 4

 5456 23:54:04.383155  best_step = 11

 5457 23:54:04.383238  

 5458 23:54:04.383308  ==

 5459 23:54:04.386455  Dram Type= 6, Freq= 0, CH_0, rank 1

 5460 23:54:04.389648  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5461 23:54:04.389772  ==

 5462 23:54:04.392814  RX Vref Scan: 0

 5463 23:54:04.392890  

 5464 23:54:04.396243  RX Vref 0 -> 0, step: 1

 5465 23:54:04.396349  

 5466 23:54:04.396457  RX Delay -53 -> 252, step: 4

 5467 23:54:04.403590  iDelay=199, Bit 0, Center 104 (15 ~ 194) 180

 5468 23:54:04.407315  iDelay=199, Bit 1, Center 108 (23 ~ 194) 172

 5469 23:54:04.410260  iDelay=199, Bit 2, Center 100 (11 ~ 190) 180

 5470 23:54:04.414064  iDelay=199, Bit 3, Center 102 (15 ~ 190) 176

 5471 23:54:04.416995  iDelay=199, Bit 4, Center 106 (19 ~ 194) 176

 5472 23:54:04.424085  iDelay=199, Bit 5, Center 96 (7 ~ 186) 180

 5473 23:54:04.427064  iDelay=199, Bit 6, Center 110 (27 ~ 194) 168

 5474 23:54:04.430521  iDelay=199, Bit 7, Center 112 (27 ~ 198) 172

 5475 23:54:04.433929  iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172

 5476 23:54:04.437394  iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168

 5477 23:54:04.440908  iDelay=199, Bit 10, Center 94 (11 ~ 178) 168

 5478 23:54:04.446819  iDelay=199, Bit 11, Center 88 (7 ~ 170) 164

 5479 23:54:04.450213  iDelay=199, Bit 12, Center 100 (19 ~ 182) 164

 5480 23:54:04.453713  iDelay=199, Bit 13, Center 98 (15 ~ 182) 168

 5481 23:54:04.457003  iDelay=199, Bit 14, Center 102 (19 ~ 186) 168

 5482 23:54:04.460448  iDelay=199, Bit 15, Center 102 (19 ~ 186) 168

 5483 23:54:04.464166  ==

 5484 23:54:04.467233  Dram Type= 6, Freq= 0, CH_0, rank 1

 5485 23:54:04.470537  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5486 23:54:04.470664  ==

 5487 23:54:04.470796  DQS Delay:

 5488 23:54:04.473720  DQS0 = 0, DQS1 = 0

 5489 23:54:04.473805  DQM Delay:

 5490 23:54:04.477003  DQM0 = 104, DQM1 = 93

 5491 23:54:04.477106  DQ Delay:

 5492 23:54:04.480330  DQ0 =104, DQ1 =108, DQ2 =100, DQ3 =102

 5493 23:54:04.483665  DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112

 5494 23:54:04.486989  DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88

 5495 23:54:04.490010  DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102

 5496 23:54:04.490121  

 5497 23:54:04.490214  

 5498 23:54:04.500180  [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps

 5499 23:54:04.500264  CH0 RK1: MR19=505, MR18=2801

 5500 23:54:04.506825  CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43

 5501 23:54:04.510051  [RxdqsGatingPostProcess] freq 933

 5502 23:54:04.516642  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5503 23:54:04.520257  best DQS0 dly(2T, 0.5T) = (0, 10)

 5504 23:54:04.523468  best DQS1 dly(2T, 0.5T) = (0, 10)

 5505 23:54:04.526877  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5506 23:54:04.530545  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5507 23:54:04.533418  best DQS0 dly(2T, 0.5T) = (0, 10)

 5508 23:54:04.533495  best DQS1 dly(2T, 0.5T) = (0, 10)

 5509 23:54:04.536516  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5510 23:54:04.540207  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5511 23:54:04.543461  Pre-setting of DQS Precalculation

 5512 23:54:04.550100  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5513 23:54:04.550177  ==

 5514 23:54:04.553314  Dram Type= 6, Freq= 0, CH_1, rank 0

 5515 23:54:04.556787  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5516 23:54:04.556863  ==

 5517 23:54:04.563862  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5518 23:54:04.570144  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5519 23:54:04.573624  [CA 0] Center 36 (6~67) winsize 62

 5520 23:54:04.576830  [CA 1] Center 36 (6~67) winsize 62

 5521 23:54:04.579886  [CA 2] Center 34 (4~65) winsize 62

 5522 23:54:04.583497  [CA 3] Center 34 (4~65) winsize 62

 5523 23:54:04.586507  [CA 4] Center 34 (4~65) winsize 62

 5524 23:54:04.590193  [CA 5] Center 33 (3~64) winsize 62

 5525 23:54:04.590265  

 5526 23:54:04.593509  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5527 23:54:04.593580  

 5528 23:54:04.596779  [CATrainingPosCal] consider 1 rank data

 5529 23:54:04.600092  u2DelayCellTimex100 = 270/100 ps

 5530 23:54:04.603475  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5531 23:54:04.606404  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5532 23:54:04.609951  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5533 23:54:04.613127  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5534 23:54:04.616223  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5535 23:54:04.619773  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5536 23:54:04.619848  

 5537 23:54:04.623460  CA PerBit enable=1, Macro0, CA PI delay=33

 5538 23:54:04.626358  

 5539 23:54:04.626436  [CBTSetCACLKResult] CA Dly = 33

 5540 23:54:04.629848  CS Dly: 6 (0~37)

 5541 23:54:04.629919  ==

 5542 23:54:04.633195  Dram Type= 6, Freq= 0, CH_1, rank 1

 5543 23:54:04.636497  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5544 23:54:04.636571  ==

 5545 23:54:04.643521  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5546 23:54:04.649800  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5547 23:54:04.652944  [CA 0] Center 36 (6~67) winsize 62

 5548 23:54:04.656383  [CA 1] Center 37 (6~68) winsize 63

 5549 23:54:04.659576  [CA 2] Center 35 (5~65) winsize 61

 5550 23:54:04.662996  [CA 3] Center 34 (4~65) winsize 62

 5551 23:54:04.666027  [CA 4] Center 34 (4~65) winsize 62

 5552 23:54:04.669305  [CA 5] Center 33 (3~64) winsize 62

 5553 23:54:04.669403  

 5554 23:54:04.672959  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5555 23:54:04.673032  

 5556 23:54:04.676130  [CATrainingPosCal] consider 2 rank data

 5557 23:54:04.679383  u2DelayCellTimex100 = 270/100 ps

 5558 23:54:04.682930  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5559 23:54:04.686096  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5560 23:54:04.689556  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5561 23:54:04.692535  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5562 23:54:04.696170  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5563 23:54:04.699042  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5564 23:54:04.702308  

 5565 23:54:04.706238  CA PerBit enable=1, Macro0, CA PI delay=33

 5566 23:54:04.706335  

 5567 23:54:04.709351  [CBTSetCACLKResult] CA Dly = 33

 5568 23:54:04.709530  CS Dly: 7 (0~40)

 5569 23:54:04.709654  

 5570 23:54:04.712702  ----->DramcWriteLeveling(PI) begin...

 5571 23:54:04.712785  ==

 5572 23:54:04.716047  Dram Type= 6, Freq= 0, CH_1, rank 0

 5573 23:54:04.719419  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5574 23:54:04.722474  ==

 5575 23:54:04.722554  Write leveling (Byte 0): 26 => 26

 5576 23:54:04.725660  Write leveling (Byte 1): 27 => 27

 5577 23:54:04.729112  DramcWriteLeveling(PI) end<-----

 5578 23:54:04.729194  

 5579 23:54:04.729305  ==

 5580 23:54:04.732313  Dram Type= 6, Freq= 0, CH_1, rank 0

 5581 23:54:04.739177  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5582 23:54:04.739301  ==

 5583 23:54:04.739415  [Gating] SW mode calibration

 5584 23:54:04.749134  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5585 23:54:04.752104  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5586 23:54:04.756109   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5587 23:54:04.762444   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5588 23:54:04.765560   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5589 23:54:04.768885   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5590 23:54:04.775291   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5591 23:54:04.779098   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5592 23:54:04.782223   0 14 24 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (1 1)

 5593 23:54:04.788704   0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)

 5594 23:54:04.792184   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5595 23:54:04.795992   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5596 23:54:04.802760   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5597 23:54:04.805817   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5598 23:54:04.809046   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5599 23:54:04.815577   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5600 23:54:04.818812   0 15 24 | B1->B0 | 2323 3636 | 1 0 | (0 0) (1 1)

 5601 23:54:04.822092   0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 5602 23:54:04.829093   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5603 23:54:04.832194   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5604 23:54:04.835232   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5605 23:54:04.842159   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5606 23:54:04.845364   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5607 23:54:04.848643   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5608 23:54:04.855089   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5609 23:54:04.858666   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5610 23:54:04.862114   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5611 23:54:04.868227   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5612 23:54:04.871578   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5613 23:54:04.875474   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5614 23:54:04.882004   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5615 23:54:04.885202   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5616 23:54:04.888567   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5617 23:54:04.891960   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5618 23:54:04.898737   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5619 23:54:04.902025   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5620 23:54:04.905311   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5621 23:54:04.912112   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5622 23:54:04.914959   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5623 23:54:04.918365   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5624 23:54:04.925465   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5625 23:54:04.928544   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5626 23:54:04.931797  Total UI for P1: 0, mck2ui 16

 5627 23:54:04.935410  best dqsien dly found for B0: ( 1,  2, 24)

 5628 23:54:04.938251  Total UI for P1: 0, mck2ui 16

 5629 23:54:04.941955  best dqsien dly found for B1: ( 1,  2, 24)

 5630 23:54:04.945103  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5631 23:54:04.948230  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5632 23:54:04.948369  

 5633 23:54:04.951519  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5634 23:54:04.954733  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5635 23:54:04.958944  [Gating] SW calibration Done

 5636 23:54:04.959054  ==

 5637 23:54:04.961723  Dram Type= 6, Freq= 0, CH_1, rank 0

 5638 23:54:04.965252  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5639 23:54:04.968250  ==

 5640 23:54:04.968377  RX Vref Scan: 0

 5641 23:54:04.968487  

 5642 23:54:04.971862  RX Vref 0 -> 0, step: 1

 5643 23:54:04.971981  

 5644 23:54:04.974794  RX Delay -80 -> 252, step: 8

 5645 23:54:04.978446  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5646 23:54:04.981923  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5647 23:54:04.985079  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5648 23:54:04.988350  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5649 23:54:04.991403  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5650 23:54:04.997918  iDelay=208, Bit 5, Center 119 (32 ~ 207) 176

 5651 23:54:05.002052  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5652 23:54:05.004899  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5653 23:54:05.007881  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5654 23:54:05.011686  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5655 23:54:05.014796  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5656 23:54:05.021704  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5657 23:54:05.024715  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5658 23:54:05.028067  iDelay=208, Bit 13, Center 107 (16 ~ 199) 184

 5659 23:54:05.031592  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5660 23:54:05.034800  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5661 23:54:05.038006  ==

 5662 23:54:05.041317  Dram Type= 6, Freq= 0, CH_1, rank 0

 5663 23:54:05.044883  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5664 23:54:05.044987  ==

 5665 23:54:05.045071  DQS Delay:

 5666 23:54:05.048165  DQS0 = 0, DQS1 = 0

 5667 23:54:05.048267  DQM Delay:

 5668 23:54:05.051031  DQM0 = 103, DQM1 = 98

 5669 23:54:05.051138  DQ Delay:

 5670 23:54:05.054863  DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99

 5671 23:54:05.058100  DQ4 =99, DQ5 =119, DQ6 =115, DQ7 =103

 5672 23:54:05.061597  DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91

 5673 23:54:05.064651  DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107

 5674 23:54:05.064729  

 5675 23:54:05.064807  

 5676 23:54:05.064866  ==

 5677 23:54:05.067863  Dram Type= 6, Freq= 0, CH_1, rank 0

 5678 23:54:05.071198  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5679 23:54:05.074711  ==

 5680 23:54:05.074792  

 5681 23:54:05.074854  

 5682 23:54:05.074912  	TX Vref Scan disable

 5683 23:54:05.078029   == TX Byte 0 ==

 5684 23:54:05.081098  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5685 23:54:05.084628  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5686 23:54:05.087814   == TX Byte 1 ==

 5687 23:54:05.091026  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5688 23:54:05.094630  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5689 23:54:05.097558  ==

 5690 23:54:05.101305  Dram Type= 6, Freq= 0, CH_1, rank 0

 5691 23:54:05.104133  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5692 23:54:05.104240  ==

 5693 23:54:05.104331  

 5694 23:54:05.104454  

 5695 23:54:05.107694  	TX Vref Scan disable

 5696 23:54:05.107799   == TX Byte 0 ==

 5697 23:54:05.114044  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5698 23:54:05.117376  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5699 23:54:05.117484   == TX Byte 1 ==

 5700 23:54:05.123888  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5701 23:54:05.127689  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5702 23:54:05.127791  

 5703 23:54:05.127886  [DATLAT]

 5704 23:54:05.130918  Freq=933, CH1 RK0

 5705 23:54:05.131021  

 5706 23:54:05.131156  DATLAT Default: 0xd

 5707 23:54:05.134056  0, 0xFFFF, sum = 0

 5708 23:54:05.134186  1, 0xFFFF, sum = 0

 5709 23:54:05.137260  2, 0xFFFF, sum = 0

 5710 23:54:05.137401  3, 0xFFFF, sum = 0

 5711 23:54:05.140675  4, 0xFFFF, sum = 0

 5712 23:54:05.143809  5, 0xFFFF, sum = 0

 5713 23:54:05.143938  6, 0xFFFF, sum = 0

 5714 23:54:05.147298  7, 0xFFFF, sum = 0

 5715 23:54:05.147425  8, 0xFFFF, sum = 0

 5716 23:54:05.150462  9, 0xFFFF, sum = 0

 5717 23:54:05.150567  10, 0x0, sum = 1

 5718 23:54:05.153624  11, 0x0, sum = 2

 5719 23:54:05.153725  12, 0x0, sum = 3

 5720 23:54:05.153824  13, 0x0, sum = 4

 5721 23:54:05.157221  best_step = 11

 5722 23:54:05.157310  

 5723 23:54:05.157403  ==

 5724 23:54:05.160070  Dram Type= 6, Freq= 0, CH_1, rank 0

 5725 23:54:05.163938  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5726 23:54:05.164025  ==

 5727 23:54:05.167275  RX Vref Scan: 1

 5728 23:54:05.167358  

 5729 23:54:05.170253  RX Vref 0 -> 0, step: 1

 5730 23:54:05.170337  

 5731 23:54:05.170401  RX Delay -45 -> 252, step: 4

 5732 23:54:05.170461  

 5733 23:54:05.173576  Set Vref, RX VrefLevel [Byte0]: 54

 5734 23:54:05.177085                           [Byte1]: 48

 5735 23:54:05.181410  

 5736 23:54:05.181493  Final RX Vref Byte 0 = 54 to rank0

 5737 23:54:05.184753  Final RX Vref Byte 1 = 48 to rank0

 5738 23:54:05.187850  Final RX Vref Byte 0 = 54 to rank1

 5739 23:54:05.190991  Final RX Vref Byte 1 = 48 to rank1==

 5740 23:54:05.194592  Dram Type= 6, Freq= 0, CH_1, rank 0

 5741 23:54:05.200834  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5742 23:54:05.200918  ==

 5743 23:54:05.200987  DQS Delay:

 5744 23:54:05.204366  DQS0 = 0, DQS1 = 0

 5745 23:54:05.204471  DQM Delay:

 5746 23:54:05.204555  DQM0 = 103, DQM1 = 98

 5747 23:54:05.207643  DQ Delay:

 5748 23:54:05.211010  DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102

 5749 23:54:05.215092  DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102

 5750 23:54:05.218047  DQ8 =86, DQ9 =90, DQ10 =100, DQ11 =92

 5751 23:54:05.221059  DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108

 5752 23:54:05.221164  

 5753 23:54:05.221258  

 5754 23:54:05.227877  [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps

 5755 23:54:05.230893  CH1 RK0: MR19=505, MR18=1B32

 5756 23:54:05.237469  CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43

 5757 23:54:05.237560  

 5758 23:54:05.241232  ----->DramcWriteLeveling(PI) begin...

 5759 23:54:05.241337  ==

 5760 23:54:05.244736  Dram Type= 6, Freq= 0, CH_1, rank 1

 5761 23:54:05.247309  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5762 23:54:05.250696  ==

 5763 23:54:05.250805  Write leveling (Byte 0): 28 => 28

 5764 23:54:05.254712  Write leveling (Byte 1): 27 => 27

 5765 23:54:05.257922  DramcWriteLeveling(PI) end<-----

 5766 23:54:05.258029  

 5767 23:54:05.258120  ==

 5768 23:54:05.261052  Dram Type= 6, Freq= 0, CH_1, rank 1

 5769 23:54:05.267904  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5770 23:54:05.268009  ==

 5771 23:54:05.268104  [Gating] SW mode calibration

 5772 23:54:05.277708  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5773 23:54:05.280953  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5774 23:54:05.287491   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5775 23:54:05.290734   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5776 23:54:05.293993   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5777 23:54:05.300540   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5778 23:54:05.303657   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5779 23:54:05.307322   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 5780 23:54:05.310795   0 14 24 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 1)

 5781 23:54:05.317330   0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 5782 23:54:05.320663   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5783 23:54:05.324056   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5784 23:54:05.330458   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5785 23:54:05.334082   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5786 23:54:05.336954   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5787 23:54:05.344008   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5788 23:54:05.347578   0 15 24 | B1->B0 | 3434 2727 | 1 0 | (0 0) (0 0)

 5789 23:54:05.350907   0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)

 5790 23:54:05.357136   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5791 23:54:05.360273   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5792 23:54:05.364204   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5793 23:54:05.370658   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5794 23:54:05.373706   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5795 23:54:05.376895   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5796 23:54:05.383584   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5797 23:54:05.386981   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5798 23:54:05.390566   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5799 23:54:05.397054   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5800 23:54:05.400167   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5801 23:54:05.403363   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5802 23:54:05.409986   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5803 23:54:05.413337   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5804 23:54:05.416648   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5805 23:54:05.423223   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5806 23:54:05.426840   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5807 23:54:05.430146   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5808 23:54:05.436468   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5809 23:54:05.440163   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5810 23:54:05.443664   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5811 23:54:05.450136   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 5812 23:54:05.453487   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 5813 23:54:05.456699   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5814 23:54:05.459636  Total UI for P1: 0, mck2ui 16

 5815 23:54:05.462815  best dqsien dly found for B0: ( 1,  2, 26)

 5816 23:54:05.466431  Total UI for P1: 0, mck2ui 16

 5817 23:54:05.470211  best dqsien dly found for B1: ( 1,  2, 22)

 5818 23:54:05.473166  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5819 23:54:05.476658  best DQS1 dly(MCK, UI, PI) = (1, 2, 22)

 5820 23:54:05.476762  

 5821 23:54:05.479632  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5822 23:54:05.486157  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5823 23:54:05.486266  [Gating] SW calibration Done

 5824 23:54:05.486360  ==

 5825 23:54:05.489427  Dram Type= 6, Freq= 0, CH_1, rank 1

 5826 23:54:05.496461  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5827 23:54:05.496563  ==

 5828 23:54:05.496667  RX Vref Scan: 0

 5829 23:54:05.496776  

 5830 23:54:05.499627  RX Vref 0 -> 0, step: 1

 5831 23:54:05.499737  

 5832 23:54:05.503148  RX Delay -80 -> 252, step: 8

 5833 23:54:05.506258  iDelay=208, Bit 0, Center 111 (24 ~ 199) 176

 5834 23:54:05.509540  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5835 23:54:05.512699  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5836 23:54:05.516165  iDelay=208, Bit 3, Center 95 (8 ~ 183) 176

 5837 23:54:05.523159  iDelay=208, Bit 4, Center 95 (8 ~ 183) 176

 5838 23:54:05.526300  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5839 23:54:05.529712  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5840 23:54:05.532765  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5841 23:54:05.536186  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5842 23:54:05.539216  iDelay=208, Bit 9, Center 91 (0 ~ 183) 184

 5843 23:54:05.546413  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5844 23:54:05.549073  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5845 23:54:05.552503  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5846 23:54:05.555971  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5847 23:54:05.559549  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5848 23:54:05.566321  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5849 23:54:05.566454  ==

 5850 23:54:05.569426  Dram Type= 6, Freq= 0, CH_1, rank 1

 5851 23:54:05.572558  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5852 23:54:05.572684  ==

 5853 23:54:05.572788  DQS Delay:

 5854 23:54:05.575994  DQS0 = 0, DQS1 = 0

 5855 23:54:05.576107  DQM Delay:

 5856 23:54:05.579045  DQM0 = 102, DQM1 = 98

 5857 23:54:05.579151  DQ Delay:

 5858 23:54:05.582317  DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =95

 5859 23:54:05.585638  DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99

 5860 23:54:05.589525  DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91

 5861 23:54:05.592741  DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107

 5862 23:54:05.592816  

 5863 23:54:05.592878  

 5864 23:54:05.592945  ==

 5865 23:54:05.595932  Dram Type= 6, Freq= 0, CH_1, rank 1

 5866 23:54:05.602435  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5867 23:54:05.602514  ==

 5868 23:54:05.602578  

 5869 23:54:05.602660  

 5870 23:54:05.602729  	TX Vref Scan disable

 5871 23:54:05.605881   == TX Byte 0 ==

 5872 23:54:05.608795  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5873 23:54:05.615441  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5874 23:54:05.615523   == TX Byte 1 ==

 5875 23:54:05.618879  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5876 23:54:05.625397  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5877 23:54:05.625475  ==

 5878 23:54:05.628804  Dram Type= 6, Freq= 0, CH_1, rank 1

 5879 23:54:05.631973  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5880 23:54:05.632085  ==

 5881 23:54:05.632188  

 5882 23:54:05.632278  

 5883 23:54:05.636009  	TX Vref Scan disable

 5884 23:54:05.636110   == TX Byte 0 ==

 5885 23:54:05.642321  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5886 23:54:05.645686  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5887 23:54:05.645769   == TX Byte 1 ==

 5888 23:54:05.651939  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5889 23:54:05.655615  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5890 23:54:05.655718  

 5891 23:54:05.655819  [DATLAT]

 5892 23:54:05.658590  Freq=933, CH1 RK1

 5893 23:54:05.658699  

 5894 23:54:05.658815  DATLAT Default: 0xb

 5895 23:54:05.662385  0, 0xFFFF, sum = 0

 5896 23:54:05.662506  1, 0xFFFF, sum = 0

 5897 23:54:05.665403  2, 0xFFFF, sum = 0

 5898 23:54:05.665515  3, 0xFFFF, sum = 0

 5899 23:54:05.668480  4, 0xFFFF, sum = 0

 5900 23:54:05.672188  5, 0xFFFF, sum = 0

 5901 23:54:05.672299  6, 0xFFFF, sum = 0

 5902 23:54:05.675560  7, 0xFFFF, sum = 0

 5903 23:54:05.675671  8, 0xFFFF, sum = 0

 5904 23:54:05.678738  9, 0xFFFF, sum = 0

 5905 23:54:05.678858  10, 0x0, sum = 1

 5906 23:54:05.678928  11, 0x0, sum = 2

 5907 23:54:05.682131  12, 0x0, sum = 3

 5908 23:54:05.682235  13, 0x0, sum = 4

 5909 23:54:05.685293  best_step = 11

 5910 23:54:05.685398  

 5911 23:54:05.685500  ==

 5912 23:54:05.688884  Dram Type= 6, Freq= 0, CH_1, rank 1

 5913 23:54:05.691975  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5914 23:54:05.692091  ==

 5915 23:54:05.695686  RX Vref Scan: 0

 5916 23:54:05.695789  

 5917 23:54:05.695890  RX Vref 0 -> 0, step: 1

 5918 23:54:05.695979  

 5919 23:54:05.698329  RX Delay -45 -> 252, step: 4

 5920 23:54:05.706075  iDelay=203, Bit 0, Center 110 (27 ~ 194) 168

 5921 23:54:05.709430  iDelay=203, Bit 1, Center 102 (19 ~ 186) 168

 5922 23:54:05.712582  iDelay=203, Bit 2, Center 94 (11 ~ 178) 168

 5923 23:54:05.715760  iDelay=203, Bit 3, Center 100 (19 ~ 182) 164

 5924 23:54:05.719637  iDelay=203, Bit 4, Center 100 (19 ~ 182) 164

 5925 23:54:05.726021  iDelay=203, Bit 5, Center 118 (35 ~ 202) 168

 5926 23:54:05.729346  iDelay=203, Bit 6, Center 114 (31 ~ 198) 168

 5927 23:54:05.732707  iDelay=203, Bit 7, Center 102 (19 ~ 186) 168

 5928 23:54:05.735931  iDelay=203, Bit 8, Center 86 (-1 ~ 174) 176

 5929 23:54:05.739306  iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176

 5930 23:54:05.743142  iDelay=203, Bit 10, Center 100 (15 ~ 186) 172

 5931 23:54:05.749568  iDelay=203, Bit 11, Center 94 (11 ~ 178) 168

 5932 23:54:05.753188  iDelay=203, Bit 12, Center 110 (23 ~ 198) 176

 5933 23:54:05.756171  iDelay=203, Bit 13, Center 106 (23 ~ 190) 168

 5934 23:54:05.759419  iDelay=203, Bit 14, Center 104 (23 ~ 186) 164

 5935 23:54:05.766128  iDelay=203, Bit 15, Center 108 (23 ~ 194) 172

 5936 23:54:05.766214  ==

 5937 23:54:05.769406  Dram Type= 6, Freq= 0, CH_1, rank 1

 5938 23:54:05.773332  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5939 23:54:05.773444  ==

 5940 23:54:05.773544  DQS Delay:

 5941 23:54:05.776228  DQS0 = 0, DQS1 = 0

 5942 23:54:05.776336  DQM Delay:

 5943 23:54:05.779478  DQM0 = 105, DQM1 = 99

 5944 23:54:05.779603  DQ Delay:

 5945 23:54:05.782982  DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100

 5946 23:54:05.786459  DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102

 5947 23:54:05.789435  DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =94

 5948 23:54:05.792755  DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108

 5949 23:54:05.792839  

 5950 23:54:05.792903  

 5951 23:54:05.803297  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps

 5952 23:54:05.803427  CH1 RK1: MR19=505, MR18=2D00

 5953 23:54:05.809738  CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43

 5954 23:54:05.813074  [RxdqsGatingPostProcess] freq 933

 5955 23:54:05.819380  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5956 23:54:05.822781  best DQS0 dly(2T, 0.5T) = (0, 10)

 5957 23:54:05.825996  best DQS1 dly(2T, 0.5T) = (0, 10)

 5958 23:54:05.829339  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5959 23:54:05.832725  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5960 23:54:05.835976  best DQS0 dly(2T, 0.5T) = (0, 10)

 5961 23:54:05.836062  best DQS1 dly(2T, 0.5T) = (0, 10)

 5962 23:54:05.839874  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5963 23:54:05.842596  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5964 23:54:05.846340  Pre-setting of DQS Precalculation

 5965 23:54:05.853162  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5966 23:54:05.859464  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5967 23:54:05.866080  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5968 23:54:05.866210  

 5969 23:54:05.866329  

 5970 23:54:05.869816  [Calibration Summary] 1866 Mbps

 5971 23:54:05.869942  CH 0, Rank 0

 5972 23:54:05.873107  SW Impedance     : PASS

 5973 23:54:05.876144  DUTY Scan        : NO K

 5974 23:54:05.876258  ZQ Calibration   : PASS

 5975 23:54:05.879159  Jitter Meter     : NO K

 5976 23:54:05.882714  CBT Training     : PASS

 5977 23:54:05.882798  Write leveling   : PASS

 5978 23:54:05.886504  RX DQS gating    : PASS

 5979 23:54:05.889489  RX DQ/DQS(RDDQC) : PASS

 5980 23:54:05.889570  TX DQ/DQS        : PASS

 5981 23:54:05.892954  RX DATLAT        : PASS

 5982 23:54:05.896432  RX DQ/DQS(Engine): PASS

 5983 23:54:05.896513  TX OE            : NO K

 5984 23:54:05.899999  All Pass.

 5985 23:54:05.900080  

 5986 23:54:05.900143  CH 0, Rank 1

 5987 23:54:05.903005  SW Impedance     : PASS

 5988 23:54:05.903088  DUTY Scan        : NO K

 5989 23:54:05.906162  ZQ Calibration   : PASS

 5990 23:54:05.909251  Jitter Meter     : NO K

 5991 23:54:05.909333  CBT Training     : PASS

 5992 23:54:05.913030  Write leveling   : PASS

 5993 23:54:05.913122  RX DQS gating    : PASS

 5994 23:54:05.916039  RX DQ/DQS(RDDQC) : PASS

 5995 23:54:05.919337  TX DQ/DQS        : PASS

 5996 23:54:05.919420  RX DATLAT        : PASS

 5997 23:54:05.922816  RX DQ/DQS(Engine): PASS

 5998 23:54:05.925730  TX OE            : NO K

 5999 23:54:05.925812  All Pass.

 6000 23:54:05.925875  

 6001 23:54:05.925934  CH 1, Rank 0

 6002 23:54:05.929724  SW Impedance     : PASS

 6003 23:54:05.932782  DUTY Scan        : NO K

 6004 23:54:05.932864  ZQ Calibration   : PASS

 6005 23:54:05.936079  Jitter Meter     : NO K

 6006 23:54:05.939330  CBT Training     : PASS

 6007 23:54:05.939412  Write leveling   : PASS

 6008 23:54:05.942610  RX DQS gating    : PASS

 6009 23:54:05.945811  RX DQ/DQS(RDDQC) : PASS

 6010 23:54:05.945894  TX DQ/DQS        : PASS

 6011 23:54:05.948993  RX DATLAT        : PASS

 6012 23:54:05.952891  RX DQ/DQS(Engine): PASS

 6013 23:54:05.952973  TX OE            : NO K

 6014 23:54:05.953039  All Pass.

 6015 23:54:05.956101  

 6016 23:54:05.956182  CH 1, Rank 1

 6017 23:54:05.959436  SW Impedance     : PASS

 6018 23:54:05.959518  DUTY Scan        : NO K

 6019 23:54:05.963051  ZQ Calibration   : PASS

 6020 23:54:05.963133  Jitter Meter     : NO K

 6021 23:54:05.965934  CBT Training     : PASS

 6022 23:54:05.969316  Write leveling   : PASS

 6023 23:54:05.969442  RX DQS gating    : PASS

 6024 23:54:05.972591  RX DQ/DQS(RDDQC) : PASS

 6025 23:54:05.975708  TX DQ/DQS        : PASS

 6026 23:54:05.975830  RX DATLAT        : PASS

 6027 23:54:05.979442  RX DQ/DQS(Engine): PASS

 6028 23:54:05.982218  TX OE            : NO K

 6029 23:54:05.982344  All Pass.

 6030 23:54:05.982452  

 6031 23:54:05.986003  DramC Write-DBI off

 6032 23:54:05.986088  	PER_BANK_REFRESH: Hybrid Mode

 6033 23:54:05.988938  TX_TRACKING: ON

 6034 23:54:05.996014  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6035 23:54:06.002427  [FAST_K] Save calibration result to emmc

 6036 23:54:06.006088  dramc_set_vcore_voltage set vcore to 650000

 6037 23:54:06.006207  Read voltage for 400, 6

 6038 23:54:06.009566  Vio18 = 0

 6039 23:54:06.009683  Vcore = 650000

 6040 23:54:06.009793  Vdram = 0

 6041 23:54:06.012387  Vddq = 0

 6042 23:54:06.012507  Vmddr = 0

 6043 23:54:06.015899  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6044 23:54:06.022434  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6045 23:54:06.025445  MEM_TYPE=3, freq_sel=20

 6046 23:54:06.028634  sv_algorithm_assistance_LP4_800 

 6047 23:54:06.032447  ============ PULL DRAM RESETB DOWN ============

 6048 23:54:06.035889  ========== PULL DRAM RESETB DOWN end =========

 6049 23:54:06.042517  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6050 23:54:06.045716  =================================== 

 6051 23:54:06.045810  LPDDR4 DRAM CONFIGURATION

 6052 23:54:06.048658  =================================== 

 6053 23:54:06.052155  EX_ROW_EN[0]    = 0x0

 6054 23:54:06.052239  EX_ROW_EN[1]    = 0x0

 6055 23:54:06.055474  LP4Y_EN      = 0x0

 6056 23:54:06.055581  WORK_FSP     = 0x0

 6057 23:54:06.058885  WL           = 0x2

 6058 23:54:06.058967  RL           = 0x2

 6059 23:54:06.062259  BL           = 0x2

 6060 23:54:06.062342  RPST         = 0x0

 6061 23:54:06.065588  RD_PRE       = 0x0

 6062 23:54:06.069222  WR_PRE       = 0x1

 6063 23:54:06.069304  WR_PST       = 0x0

 6064 23:54:06.072197  DBI_WR       = 0x0

 6065 23:54:06.072279  DBI_RD       = 0x0

 6066 23:54:06.075426  OTF          = 0x1

 6067 23:54:06.078689  =================================== 

 6068 23:54:06.082384  =================================== 

 6069 23:54:06.082467  ANA top config

 6070 23:54:06.085425  =================================== 

 6071 23:54:06.088596  DLL_ASYNC_EN            =  0

 6072 23:54:06.092090  ALL_SLAVE_EN            =  1

 6073 23:54:06.092172  NEW_RANK_MODE           =  1

 6074 23:54:06.095722  DLL_IDLE_MODE           =  1

 6075 23:54:06.098960  LP45_APHY_COMB_EN       =  1

 6076 23:54:06.101816  TX_ODT_DIS              =  1

 6077 23:54:06.101898  NEW_8X_MODE             =  1

 6078 23:54:06.105523  =================================== 

 6079 23:54:06.108882  =================================== 

 6080 23:54:06.112115  data_rate                  =  800

 6081 23:54:06.115376  CKR                        = 1

 6082 23:54:06.118572  DQ_P2S_RATIO               = 4

 6083 23:54:06.122072  =================================== 

 6084 23:54:06.125033  CA_P2S_RATIO               = 4

 6085 23:54:06.128486  DQ_CA_OPEN                 = 0

 6086 23:54:06.128569  DQ_SEMI_OPEN               = 1

 6087 23:54:06.132255  CA_SEMI_OPEN               = 1

 6088 23:54:06.135423  CA_FULL_RATE               = 0

 6089 23:54:06.138696  DQ_CKDIV4_EN               = 0

 6090 23:54:06.142095  CA_CKDIV4_EN               = 1

 6091 23:54:06.145174  CA_PREDIV_EN               = 0

 6092 23:54:06.145256  PH8_DLY                    = 0

 6093 23:54:06.148290  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6094 23:54:06.151975  DQ_AAMCK_DIV               = 0

 6095 23:54:06.155399  CA_AAMCK_DIV               = 0

 6096 23:54:06.158530  CA_ADMCK_DIV               = 4

 6097 23:54:06.161594  DQ_TRACK_CA_EN             = 0

 6098 23:54:06.161677  CA_PICK                    = 800

 6099 23:54:06.164996  CA_MCKIO                   = 400

 6100 23:54:06.168543  MCKIO_SEMI                 = 400

 6101 23:54:06.171954  PLL_FREQ                   = 3016

 6102 23:54:06.175143  DQ_UI_PI_RATIO             = 32

 6103 23:54:06.178575  CA_UI_PI_RATIO             = 32

 6104 23:54:06.181479  =================================== 

 6105 23:54:06.184768  =================================== 

 6106 23:54:06.188691  memory_type:LPDDR4         

 6107 23:54:06.188776  GP_NUM     : 10       

 6108 23:54:06.191719  SRAM_EN    : 1       

 6109 23:54:06.191795  MD32_EN    : 0       

 6110 23:54:06.194972  =================================== 

 6111 23:54:06.198085  [ANA_INIT] >>>>>>>>>>>>>> 

 6112 23:54:06.201982  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6113 23:54:06.205286  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6114 23:54:06.208520  =================================== 

 6115 23:54:06.211828  data_rate = 800,PCW = 0X7400

 6116 23:54:06.215359  =================================== 

 6117 23:54:06.218250  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6118 23:54:06.221495  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6119 23:54:06.235100  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6120 23:54:06.238388  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6121 23:54:06.241557  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6122 23:54:06.245046  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6123 23:54:06.248560  [ANA_INIT] flow start 

 6124 23:54:06.251852  [ANA_INIT] PLL >>>>>>>> 

 6125 23:54:06.251956  [ANA_INIT] PLL <<<<<<<< 

 6126 23:54:06.255056  [ANA_INIT] MIDPI >>>>>>>> 

 6127 23:54:06.258214  [ANA_INIT] MIDPI <<<<<<<< 

 6128 23:54:06.258295  [ANA_INIT] DLL >>>>>>>> 

 6129 23:54:06.261391  [ANA_INIT] flow end 

 6130 23:54:06.265338  ============ LP4 DIFF to SE enter ============

 6131 23:54:06.268563  ============ LP4 DIFF to SE exit  ============

 6132 23:54:06.271551  [ANA_INIT] <<<<<<<<<<<<< 

 6133 23:54:06.275140  [Flow] Enable top DCM control >>>>> 

 6134 23:54:06.278676  [Flow] Enable top DCM control <<<<< 

 6135 23:54:06.281754  Enable DLL master slave shuffle 

 6136 23:54:06.288659  ============================================================== 

 6137 23:54:06.288746  Gating Mode config

 6138 23:54:06.295292  ============================================================== 

 6139 23:54:06.295377  Config description: 

 6140 23:54:06.305087  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6141 23:54:06.311275  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6142 23:54:06.318829  SELPH_MODE            0: By rank         1: By Phase 

 6143 23:54:06.321942  ============================================================== 

 6144 23:54:06.324823  GAT_TRACK_EN                 =  0

 6145 23:54:06.328477  RX_GATING_MODE               =  2

 6146 23:54:06.331774  RX_GATING_TRACK_MODE         =  2

 6147 23:54:06.335094  SELPH_MODE                   =  1

 6148 23:54:06.338162  PICG_EARLY_EN                =  1

 6149 23:54:06.341531  VALID_LAT_VALUE              =  1

 6150 23:54:06.348060  ============================================================== 

 6151 23:54:06.351429  Enter into Gating configuration >>>> 

 6152 23:54:06.355296  Exit from Gating configuration <<<< 

 6153 23:54:06.355380  Enter into  DVFS_PRE_config >>>>> 

 6154 23:54:06.368472  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6155 23:54:06.371574  Exit from  DVFS_PRE_config <<<<< 

 6156 23:54:06.374875  Enter into PICG configuration >>>> 

 6157 23:54:06.378084  Exit from PICG configuration <<<< 

 6158 23:54:06.378169  [RX_INPUT] configuration >>>>> 

 6159 23:54:06.381322  [RX_INPUT] configuration <<<<< 

 6160 23:54:06.388041  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6161 23:54:06.391358  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6162 23:54:06.398060  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6163 23:54:06.404307  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6164 23:54:06.411199  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6165 23:54:06.417918  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6166 23:54:06.421178  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6167 23:54:06.424511  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6168 23:54:06.431331  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6169 23:54:06.434485  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6170 23:54:06.438385  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6171 23:54:06.441368  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6172 23:54:06.444753  =================================== 

 6173 23:54:06.447717  LPDDR4 DRAM CONFIGURATION

 6174 23:54:06.451226  =================================== 

 6175 23:54:06.454177  EX_ROW_EN[0]    = 0x0

 6176 23:54:06.454307  EX_ROW_EN[1]    = 0x0

 6177 23:54:06.457631  LP4Y_EN      = 0x0

 6178 23:54:06.457758  WORK_FSP     = 0x0

 6179 23:54:06.461082  WL           = 0x2

 6180 23:54:06.461209  RL           = 0x2

 6181 23:54:06.464312  BL           = 0x2

 6182 23:54:06.464446  RPST         = 0x0

 6183 23:54:06.467667  RD_PRE       = 0x0

 6184 23:54:06.467793  WR_PRE       = 0x1

 6185 23:54:06.470869  WR_PST       = 0x0

 6186 23:54:06.470977  DBI_WR       = 0x0

 6187 23:54:06.474135  DBI_RD       = 0x0

 6188 23:54:06.477945  OTF          = 0x1

 6189 23:54:06.481293  =================================== 

 6190 23:54:06.484154  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6191 23:54:06.487801  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6192 23:54:06.491100  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6193 23:54:06.494220  =================================== 

 6194 23:54:06.497448  LPDDR4 DRAM CONFIGURATION

 6195 23:54:06.501333  =================================== 

 6196 23:54:06.504650  EX_ROW_EN[0]    = 0x10

 6197 23:54:06.504776  EX_ROW_EN[1]    = 0x0

 6198 23:54:06.507517  LP4Y_EN      = 0x0

 6199 23:54:06.507642  WORK_FSP     = 0x0

 6200 23:54:06.510617  WL           = 0x2

 6201 23:54:06.510735  RL           = 0x2

 6202 23:54:06.514007  BL           = 0x2

 6203 23:54:06.514093  RPST         = 0x0

 6204 23:54:06.517633  RD_PRE       = 0x0

 6205 23:54:06.517717  WR_PRE       = 0x1

 6206 23:54:06.521004  WR_PST       = 0x0

 6207 23:54:06.521088  DBI_WR       = 0x0

 6208 23:54:06.524145  DBI_RD       = 0x0

 6209 23:54:06.524229  OTF          = 0x1

 6210 23:54:06.527415  =================================== 

 6211 23:54:06.533865  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6212 23:54:06.539090  nWR fixed to 30

 6213 23:54:06.542196  [ModeRegInit_LP4] CH0 RK0

 6214 23:54:06.542280  [ModeRegInit_LP4] CH0 RK1

 6215 23:54:06.545441  [ModeRegInit_LP4] CH1 RK0

 6216 23:54:06.548764  [ModeRegInit_LP4] CH1 RK1

 6217 23:54:06.548868  match AC timing 19

 6218 23:54:06.555339  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6219 23:54:06.558803  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6220 23:54:06.562268  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6221 23:54:06.568710  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6222 23:54:06.572484  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6223 23:54:06.572610  ==

 6224 23:54:06.575365  Dram Type= 6, Freq= 0, CH_0, rank 0

 6225 23:54:06.578402  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6226 23:54:06.578529  ==

 6227 23:54:06.585574  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6228 23:54:06.592048  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6229 23:54:06.595588  [CA 0] Center 36 (8~64) winsize 57

 6230 23:54:06.598527  [CA 1] Center 36 (8~64) winsize 57

 6231 23:54:06.601745  [CA 2] Center 36 (8~64) winsize 57

 6232 23:54:06.605040  [CA 3] Center 36 (8~64) winsize 57

 6233 23:54:06.605124  [CA 4] Center 36 (8~64) winsize 57

 6234 23:54:06.608728  [CA 5] Center 36 (8~64) winsize 57

 6235 23:54:06.608814  

 6236 23:54:06.615288  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6237 23:54:06.615375  

 6238 23:54:06.618526  [CATrainingPosCal] consider 1 rank data

 6239 23:54:06.621904  u2DelayCellTimex100 = 270/100 ps

 6240 23:54:06.625267  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6241 23:54:06.628575  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6242 23:54:06.631525  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6243 23:54:06.634714  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6244 23:54:06.638209  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6245 23:54:06.641884  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6246 23:54:06.641968  

 6247 23:54:06.645156  CA PerBit enable=1, Macro0, CA PI delay=36

 6248 23:54:06.645239  

 6249 23:54:06.648315  [CBTSetCACLKResult] CA Dly = 36

 6250 23:54:06.651560  CS Dly: 1 (0~32)

 6251 23:54:06.651641  ==

 6252 23:54:06.655125  Dram Type= 6, Freq= 0, CH_0, rank 1

 6253 23:54:06.658175  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6254 23:54:06.658259  ==

 6255 23:54:06.664708  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6256 23:54:06.671516  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6257 23:54:06.671647  [CA 0] Center 36 (8~64) winsize 57

 6258 23:54:06.675424  [CA 1] Center 36 (8~64) winsize 57

 6259 23:54:06.678198  [CA 2] Center 36 (8~64) winsize 57

 6260 23:54:06.681395  [CA 3] Center 36 (8~64) winsize 57

 6261 23:54:06.685147  [CA 4] Center 36 (8~64) winsize 57

 6262 23:54:06.688346  [CA 5] Center 36 (8~64) winsize 57

 6263 23:54:06.688432  

 6264 23:54:06.691541  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6265 23:54:06.691628  

 6266 23:54:06.694966  [CATrainingPosCal] consider 2 rank data

 6267 23:54:06.698636  u2DelayCellTimex100 = 270/100 ps

 6268 23:54:06.701808  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6269 23:54:06.704655  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6270 23:54:06.711336  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6271 23:54:06.715057  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6272 23:54:06.718243  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6273 23:54:06.721535  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6274 23:54:06.721616  

 6275 23:54:06.724825  CA PerBit enable=1, Macro0, CA PI delay=36

 6276 23:54:06.724928  

 6277 23:54:06.727909  [CBTSetCACLKResult] CA Dly = 36

 6278 23:54:06.727989  CS Dly: 1 (0~32)

 6279 23:54:06.728069  

 6280 23:54:06.731691  ----->DramcWriteLeveling(PI) begin...

 6281 23:54:06.734830  ==

 6282 23:54:06.737850  Dram Type= 6, Freq= 0, CH_0, rank 0

 6283 23:54:06.741770  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6284 23:54:06.741910  ==

 6285 23:54:06.744357  Write leveling (Byte 0): 40 => 8

 6286 23:54:06.747875  Write leveling (Byte 1): 40 => 8

 6287 23:54:06.751262  DramcWriteLeveling(PI) end<-----

 6288 23:54:06.751357  

 6289 23:54:06.751443  ==

 6290 23:54:06.754723  Dram Type= 6, Freq= 0, CH_0, rank 0

 6291 23:54:06.757716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6292 23:54:06.757801  ==

 6293 23:54:06.761160  [Gating] SW mode calibration

 6294 23:54:06.767485  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6295 23:54:06.774338  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6296 23:54:06.777540   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6297 23:54:06.780677   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6298 23:54:06.784447   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6299 23:54:06.790862   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6300 23:54:06.794336   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6301 23:54:06.797917   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6302 23:54:06.804580   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6303 23:54:06.807500   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6304 23:54:06.811136   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6305 23:54:06.814415  Total UI for P1: 0, mck2ui 16

 6306 23:54:06.817361  best dqsien dly found for B0: ( 0, 14, 24)

 6307 23:54:06.820480  Total UI for P1: 0, mck2ui 16

 6308 23:54:06.824359  best dqsien dly found for B1: ( 0, 14, 24)

 6309 23:54:06.827590  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6310 23:54:06.834063  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6311 23:54:06.834148  

 6312 23:54:06.837488  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6313 23:54:06.840375  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6314 23:54:06.844294  [Gating] SW calibration Done

 6315 23:54:06.844406  ==

 6316 23:54:06.847566  Dram Type= 6, Freq= 0, CH_0, rank 0

 6317 23:54:06.850516  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6318 23:54:06.850605  ==

 6319 23:54:06.850703  RX Vref Scan: 0

 6320 23:54:06.854291  

 6321 23:54:06.854389  RX Vref 0 -> 0, step: 1

 6322 23:54:06.854480  

 6323 23:54:06.857683  RX Delay -410 -> 252, step: 16

 6324 23:54:06.860829  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6325 23:54:06.867383  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6326 23:54:06.870559  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6327 23:54:06.873827  iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480

 6328 23:54:06.877535  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6329 23:54:06.883936  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6330 23:54:06.887103  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6331 23:54:06.890380  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6332 23:54:06.893781  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6333 23:54:06.900637  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6334 23:54:06.903912  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6335 23:54:06.907678  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6336 23:54:06.910497  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6337 23:54:06.917502  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6338 23:54:06.920719  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6339 23:54:06.923834  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6340 23:54:06.923915  ==

 6341 23:54:06.927018  Dram Type= 6, Freq= 0, CH_0, rank 0

 6342 23:54:06.930513  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6343 23:54:06.934275  ==

 6344 23:54:06.934379  DQS Delay:

 6345 23:54:06.934473  DQS0 = 27, DQS1 = 35

 6346 23:54:06.937368  DQM Delay:

 6347 23:54:06.937445  DQM0 = 9, DQM1 = 11

 6348 23:54:06.940637  DQ Delay:

 6349 23:54:06.940713  DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0

 6350 23:54:06.943721  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24

 6351 23:54:06.946959  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6352 23:54:06.950836  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6353 23:54:06.950918  

 6354 23:54:06.950985  

 6355 23:54:06.951046  ==

 6356 23:54:06.954006  Dram Type= 6, Freq= 0, CH_0, rank 0

 6357 23:54:06.960703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6358 23:54:06.960802  ==

 6359 23:54:06.960867  

 6360 23:54:06.960926  

 6361 23:54:06.960986  	TX Vref Scan disable

 6362 23:54:06.963560   == TX Byte 0 ==

 6363 23:54:06.967360  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6364 23:54:06.970532  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6365 23:54:06.973528   == TX Byte 1 ==

 6366 23:54:06.977232  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6367 23:54:06.980175  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6368 23:54:06.983732  ==

 6369 23:54:06.983808  Dram Type= 6, Freq= 0, CH_0, rank 0

 6370 23:54:06.990219  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6371 23:54:06.990304  ==

 6372 23:54:06.990370  

 6373 23:54:06.990433  

 6374 23:54:06.993952  	TX Vref Scan disable

 6375 23:54:06.994027   == TX Byte 0 ==

 6376 23:54:06.997203  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6377 23:54:07.003730  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6378 23:54:07.003848   == TX Byte 1 ==

 6379 23:54:07.007253  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6380 23:54:07.010171  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6381 23:54:07.013592  

 6382 23:54:07.013692  [DATLAT]

 6383 23:54:07.013756  Freq=400, CH0 RK0

 6384 23:54:07.013816  

 6385 23:54:07.016986  DATLAT Default: 0xf

 6386 23:54:07.017061  0, 0xFFFF, sum = 0

 6387 23:54:07.020038  1, 0xFFFF, sum = 0

 6388 23:54:07.020120  2, 0xFFFF, sum = 0

 6389 23:54:07.023872  3, 0xFFFF, sum = 0

 6390 23:54:07.023962  4, 0xFFFF, sum = 0

 6391 23:54:07.026700  5, 0xFFFF, sum = 0

 6392 23:54:07.026791  6, 0xFFFF, sum = 0

 6393 23:54:07.030478  7, 0xFFFF, sum = 0

 6394 23:54:07.033676  8, 0xFFFF, sum = 0

 6395 23:54:07.033783  9, 0xFFFF, sum = 0

 6396 23:54:07.037187  10, 0xFFFF, sum = 0

 6397 23:54:07.037268  11, 0xFFFF, sum = 0

 6398 23:54:07.040298  12, 0xFFFF, sum = 0

 6399 23:54:07.040382  13, 0x0, sum = 1

 6400 23:54:07.043466  14, 0x0, sum = 2

 6401 23:54:07.043542  15, 0x0, sum = 3

 6402 23:54:07.046735  16, 0x0, sum = 4

 6403 23:54:07.046811  best_step = 14

 6404 23:54:07.046876  

 6405 23:54:07.046935  ==

 6406 23:54:07.050061  Dram Type= 6, Freq= 0, CH_0, rank 0

 6407 23:54:07.053749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6408 23:54:07.053859  ==

 6409 23:54:07.057192  RX Vref Scan: 1

 6410 23:54:07.057266  

 6411 23:54:07.060243  RX Vref 0 -> 0, step: 1

 6412 23:54:07.060319  

 6413 23:54:07.060388  RX Delay -311 -> 252, step: 8

 6414 23:54:07.060451  

 6415 23:54:07.063523  Set Vref, RX VrefLevel [Byte0]: 54

 6416 23:54:07.066887                           [Byte1]: 48

 6417 23:54:07.072173  

 6418 23:54:07.072250  Final RX Vref Byte 0 = 54 to rank0

 6419 23:54:07.075371  Final RX Vref Byte 1 = 48 to rank0

 6420 23:54:07.078541  Final RX Vref Byte 0 = 54 to rank1

 6421 23:54:07.082209  Final RX Vref Byte 1 = 48 to rank1==

 6422 23:54:07.085700  Dram Type= 6, Freq= 0, CH_0, rank 0

 6423 23:54:07.091915  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6424 23:54:07.092041  ==

 6425 23:54:07.092157  DQS Delay:

 6426 23:54:07.095360  DQS0 = 28, DQS1 = 36

 6427 23:54:07.095480  DQM Delay:

 6428 23:54:07.095598  DQM0 = 10, DQM1 = 13

 6429 23:54:07.098354  DQ Delay:

 6430 23:54:07.101838  DQ0 =8, DQ1 =16, DQ2 =4, DQ3 =8

 6431 23:54:07.101969  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6432 23:54:07.105022  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8

 6433 23:54:07.108914  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6434 23:54:07.109026  

 6435 23:54:07.109126  

 6436 23:54:07.118571  [DQSOSCAuto] RK0, (LSB)MR18= 0xcebd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps

 6437 23:54:07.122173  CH0 RK0: MR19=C0C, MR18=CEBD

 6438 23:54:07.128693  CH0_RK0: MR19=0xC0C, MR18=0xCEBD, DQSOSC=384, MR23=63, INC=400, DEC=267

 6439 23:54:07.128825  ==

 6440 23:54:07.131745  Dram Type= 6, Freq= 0, CH_0, rank 1

 6441 23:54:07.135084  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6442 23:54:07.135213  ==

 6443 23:54:07.138360  [Gating] SW mode calibration

 6444 23:54:07.145346  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6445 23:54:07.151662  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6446 23:54:07.155211   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6447 23:54:07.158416   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6448 23:54:07.161975   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6449 23:54:07.168394   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6450 23:54:07.171654   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6451 23:54:07.175172   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6452 23:54:07.181733   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6453 23:54:07.185062   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6454 23:54:07.188984   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6455 23:54:07.191318  Total UI for P1: 0, mck2ui 16

 6456 23:54:07.195244  best dqsien dly found for B0: ( 0, 14, 24)

 6457 23:54:07.198640  Total UI for P1: 0, mck2ui 16

 6458 23:54:07.202010  best dqsien dly found for B1: ( 0, 14, 24)

 6459 23:54:07.204811  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6460 23:54:07.208224  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6461 23:54:07.211891  

 6462 23:54:07.214955  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6463 23:54:07.217964  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6464 23:54:07.221495  [Gating] SW calibration Done

 6465 23:54:07.221575  ==

 6466 23:54:07.224821  Dram Type= 6, Freq= 0, CH_0, rank 1

 6467 23:54:07.228570  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6468 23:54:07.228647  ==

 6469 23:54:07.228709  RX Vref Scan: 0

 6470 23:54:07.228773  

 6471 23:54:07.231830  RX Vref 0 -> 0, step: 1

 6472 23:54:07.231909  

 6473 23:54:07.235100  RX Delay -410 -> 252, step: 16

 6474 23:54:07.238262  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6475 23:54:07.244783  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6476 23:54:07.248157  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6477 23:54:07.251891  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6478 23:54:07.254546  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6479 23:54:07.261546  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6480 23:54:07.264726  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6481 23:54:07.267993  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6482 23:54:07.271328  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6483 23:54:07.277933  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6484 23:54:07.281284  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6485 23:54:07.284299  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6486 23:54:07.287942  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6487 23:54:07.294649  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6488 23:54:07.297923  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6489 23:54:07.301203  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6490 23:54:07.301316  ==

 6491 23:54:07.304696  Dram Type= 6, Freq= 0, CH_0, rank 1

 6492 23:54:07.308354  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6493 23:54:07.311043  ==

 6494 23:54:07.311163  DQS Delay:

 6495 23:54:07.311257  DQS0 = 27, DQS1 = 35

 6496 23:54:07.314407  DQM Delay:

 6497 23:54:07.314509  DQM0 = 12, DQM1 = 11

 6498 23:54:07.317663  DQ Delay:

 6499 23:54:07.317752  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6500 23:54:07.321417  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6501 23:54:07.324518  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6502 23:54:07.327848  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6503 23:54:07.327932  

 6504 23:54:07.327996  

 6505 23:54:07.331326  ==

 6506 23:54:07.331410  Dram Type= 6, Freq= 0, CH_0, rank 1

 6507 23:54:07.337671  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6508 23:54:07.337755  ==

 6509 23:54:07.337819  

 6510 23:54:07.337878  

 6511 23:54:07.340889  	TX Vref Scan disable

 6512 23:54:07.340972   == TX Byte 0 ==

 6513 23:54:07.344279  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6514 23:54:07.347808  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6515 23:54:07.351343   == TX Byte 1 ==

 6516 23:54:07.354332  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6517 23:54:07.357682  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6518 23:54:07.361294  ==

 6519 23:54:07.364465  Dram Type= 6, Freq= 0, CH_0, rank 1

 6520 23:54:07.367324  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6521 23:54:07.367406  ==

 6522 23:54:07.367471  

 6523 23:54:07.367530  

 6524 23:54:07.370952  	TX Vref Scan disable

 6525 23:54:07.371035   == TX Byte 0 ==

 6526 23:54:07.374109  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6527 23:54:07.380511  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6528 23:54:07.380615   == TX Byte 1 ==

 6529 23:54:07.384520  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6530 23:54:07.390579  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6531 23:54:07.390686  

 6532 23:54:07.390786  [DATLAT]

 6533 23:54:07.390863  Freq=400, CH0 RK1

 6534 23:54:07.390925  

 6535 23:54:07.394274  DATLAT Default: 0xe

 6536 23:54:07.394353  0, 0xFFFF, sum = 0

 6537 23:54:07.397290  1, 0xFFFF, sum = 0

 6538 23:54:07.401029  2, 0xFFFF, sum = 0

 6539 23:54:07.401135  3, 0xFFFF, sum = 0

 6540 23:54:07.404047  4, 0xFFFF, sum = 0

 6541 23:54:07.404150  5, 0xFFFF, sum = 0

 6542 23:54:07.407264  6, 0xFFFF, sum = 0

 6543 23:54:07.407373  7, 0xFFFF, sum = 0

 6544 23:54:07.410555  8, 0xFFFF, sum = 0

 6545 23:54:07.410641  9, 0xFFFF, sum = 0

 6546 23:54:07.414010  10, 0xFFFF, sum = 0

 6547 23:54:07.414094  11, 0xFFFF, sum = 0

 6548 23:54:07.416996  12, 0xFFFF, sum = 0

 6549 23:54:07.417101  13, 0x0, sum = 1

 6550 23:54:07.420239  14, 0x0, sum = 2

 6551 23:54:07.420349  15, 0x0, sum = 3

 6552 23:54:07.424088  16, 0x0, sum = 4

 6553 23:54:07.424172  best_step = 14

 6554 23:54:07.424268  

 6555 23:54:07.424367  ==

 6556 23:54:07.427253  Dram Type= 6, Freq= 0, CH_0, rank 1

 6557 23:54:07.430596  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6558 23:54:07.433709  ==

 6559 23:54:07.433795  RX Vref Scan: 0

 6560 23:54:07.433860  

 6561 23:54:07.437189  RX Vref 0 -> 0, step: 1

 6562 23:54:07.437272  

 6563 23:54:07.440283  RX Delay -311 -> 252, step: 8

 6564 23:54:07.443532  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6565 23:54:07.450036  iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448

 6566 23:54:07.453374  iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456

 6567 23:54:07.457251  iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448

 6568 23:54:07.460227  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6569 23:54:07.467101  iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448

 6570 23:54:07.470254  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6571 23:54:07.473573  iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448

 6572 23:54:07.477431  iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440

 6573 23:54:07.483581  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6574 23:54:07.486532  iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440

 6575 23:54:07.489785  iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440

 6576 23:54:07.496692  iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440

 6577 23:54:07.500251  iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440

 6578 23:54:07.503402  iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440

 6579 23:54:07.506776  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6580 23:54:07.506854  ==

 6581 23:54:07.509906  Dram Type= 6, Freq= 0, CH_0, rank 1

 6582 23:54:07.516317  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6583 23:54:07.516410  ==

 6584 23:54:07.516475  DQS Delay:

 6585 23:54:07.519693  DQS0 = 24, DQS1 = 32

 6586 23:54:07.519776  DQM Delay:

 6587 23:54:07.519841  DQM0 = 8, DQM1 = 10

 6588 23:54:07.523685  DQ Delay:

 6589 23:54:07.526889  DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8

 6590 23:54:07.526973  DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16

 6591 23:54:07.530339  DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4

 6592 23:54:07.533622  DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16

 6593 23:54:07.533744  

 6594 23:54:07.533842  

 6595 23:54:07.543234  [DQSOSCAuto] RK1, (LSB)MR18= 0xc363, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps

 6596 23:54:07.546921  CH0 RK1: MR19=C0C, MR18=C363

 6597 23:54:07.553432  CH0_RK1: MR19=0xC0C, MR18=0xC363, DQSOSC=385, MR23=63, INC=398, DEC=265

 6598 23:54:07.553538  [RxdqsGatingPostProcess] freq 400

 6599 23:54:07.559765  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6600 23:54:07.563057  best DQS0 dly(2T, 0.5T) = (0, 10)

 6601 23:54:07.566922  best DQS1 dly(2T, 0.5T) = (0, 10)

 6602 23:54:07.570024  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6603 23:54:07.573322  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6604 23:54:07.576554  best DQS0 dly(2T, 0.5T) = (0, 10)

 6605 23:54:07.579663  best DQS1 dly(2T, 0.5T) = (0, 10)

 6606 23:54:07.582897  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6607 23:54:07.586397  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6608 23:54:07.589917  Pre-setting of DQS Precalculation

 6609 23:54:07.593228  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6610 23:54:07.593337  ==

 6611 23:54:07.596345  Dram Type= 6, Freq= 0, CH_1, rank 0

 6612 23:54:07.599536  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6613 23:54:07.603280  ==

 6614 23:54:07.606324  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6615 23:54:07.613097  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6616 23:54:07.616164  [CA 0] Center 36 (8~64) winsize 57

 6617 23:54:07.619941  [CA 1] Center 36 (8~64) winsize 57

 6618 23:54:07.623426  [CA 2] Center 36 (8~64) winsize 57

 6619 23:54:07.626429  [CA 3] Center 36 (8~64) winsize 57

 6620 23:54:07.629604  [CA 4] Center 36 (8~64) winsize 57

 6621 23:54:07.633065  [CA 5] Center 36 (8~64) winsize 57

 6622 23:54:07.633172  

 6623 23:54:07.636664  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6624 23:54:07.636746  

 6625 23:54:07.639797  [CATrainingPosCal] consider 1 rank data

 6626 23:54:07.643027  u2DelayCellTimex100 = 270/100 ps

 6627 23:54:07.646812  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6628 23:54:07.650103  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6629 23:54:07.653475  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6630 23:54:07.656545  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6631 23:54:07.659603  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6632 23:54:07.662943  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6633 23:54:07.663051  

 6634 23:54:07.666256  CA PerBit enable=1, Macro0, CA PI delay=36

 6635 23:54:07.666358  

 6636 23:54:07.670067  [CBTSetCACLKResult] CA Dly = 36

 6637 23:54:07.673553  CS Dly: 1 (0~32)

 6638 23:54:07.673630  ==

 6639 23:54:07.676771  Dram Type= 6, Freq= 0, CH_1, rank 1

 6640 23:54:07.679432  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6641 23:54:07.679507  ==

 6642 23:54:07.686086  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6643 23:54:07.692802  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6644 23:54:07.696108  [CA 0] Center 36 (8~64) winsize 57

 6645 23:54:07.696216  [CA 1] Center 36 (8~64) winsize 57

 6646 23:54:07.699388  [CA 2] Center 36 (8~64) winsize 57

 6647 23:54:07.702889  [CA 3] Center 36 (8~64) winsize 57

 6648 23:54:07.706230  [CA 4] Center 36 (8~64) winsize 57

 6649 23:54:07.709708  [CA 5] Center 36 (8~64) winsize 57

 6650 23:54:07.709813  

 6651 23:54:07.713330  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6652 23:54:07.713451  

 6653 23:54:07.716623  [CATrainingPosCal] consider 2 rank data

 6654 23:54:07.719872  u2DelayCellTimex100 = 270/100 ps

 6655 23:54:07.723241  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6656 23:54:07.729540  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6657 23:54:07.733266  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6658 23:54:07.736158  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6659 23:54:07.739435  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6660 23:54:07.742736  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6661 23:54:07.742820  

 6662 23:54:07.746375  CA PerBit enable=1, Macro0, CA PI delay=36

 6663 23:54:07.746458  

 6664 23:54:07.749743  [CBTSetCACLKResult] CA Dly = 36

 6665 23:54:07.749826  CS Dly: 1 (0~32)

 6666 23:54:07.749891  

 6667 23:54:07.756595  ----->DramcWriteLeveling(PI) begin...

 6668 23:54:07.756708  ==

 6669 23:54:07.759739  Dram Type= 6, Freq= 0, CH_1, rank 0

 6670 23:54:07.762940  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6671 23:54:07.763049  ==

 6672 23:54:07.766108  Write leveling (Byte 0): 40 => 8

 6673 23:54:07.769450  Write leveling (Byte 1): 40 => 8

 6674 23:54:07.772780  DramcWriteLeveling(PI) end<-----

 6675 23:54:07.772890  

 6676 23:54:07.772983  ==

 6677 23:54:07.776098  Dram Type= 6, Freq= 0, CH_1, rank 0

 6678 23:54:07.779368  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6679 23:54:07.779451  ==

 6680 23:54:07.782743  [Gating] SW mode calibration

 6681 23:54:07.789152  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6682 23:54:07.795808  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6683 23:54:07.799502   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6684 23:54:07.802600   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6685 23:54:07.808967   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6686 23:54:07.812301   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6687 23:54:07.816274   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6688 23:54:07.819591   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6689 23:54:07.826202   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6690 23:54:07.829287   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6691 23:54:07.832648   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6692 23:54:07.835982  Total UI for P1: 0, mck2ui 16

 6693 23:54:07.839286  best dqsien dly found for B0: ( 0, 14, 24)

 6694 23:54:07.842648  Total UI for P1: 0, mck2ui 16

 6695 23:54:07.845765  best dqsien dly found for B1: ( 0, 14, 24)

 6696 23:54:07.849176  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6697 23:54:07.852357  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6698 23:54:07.856048  

 6699 23:54:07.859226  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6700 23:54:07.862882  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6701 23:54:07.865555  [Gating] SW calibration Done

 6702 23:54:07.865638  ==

 6703 23:54:07.869251  Dram Type= 6, Freq= 0, CH_1, rank 0

 6704 23:54:07.872218  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6705 23:54:07.872325  ==

 6706 23:54:07.872405  RX Vref Scan: 0

 6707 23:54:07.872466  

 6708 23:54:07.875858  RX Vref 0 -> 0, step: 1

 6709 23:54:07.875940  

 6710 23:54:07.879170  RX Delay -410 -> 252, step: 16

 6711 23:54:07.882836  iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480

 6712 23:54:07.889278  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6713 23:54:07.892524  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6714 23:54:07.896015  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6715 23:54:07.899209  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6716 23:54:07.905782  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6717 23:54:07.909364  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6718 23:54:07.912573  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6719 23:54:07.915782  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6720 23:54:07.922645  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6721 23:54:07.925838  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6722 23:54:07.928990  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6723 23:54:07.932169  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6724 23:54:07.939143  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6725 23:54:07.942403  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6726 23:54:07.945619  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6727 23:54:07.945749  ==

 6728 23:54:07.948862  Dram Type= 6, Freq= 0, CH_1, rank 0

 6729 23:54:07.952125  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6730 23:54:07.955486  ==

 6731 23:54:07.955610  DQS Delay:

 6732 23:54:07.955730  DQS0 = 35, DQS1 = 35

 6733 23:54:07.958853  DQM Delay:

 6734 23:54:07.958946  DQM0 = 18, DQM1 = 13

 6735 23:54:07.962150  DQ Delay:

 6736 23:54:07.962242  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6737 23:54:07.966134  DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16

 6738 23:54:07.969151  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6739 23:54:07.972532  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24

 6740 23:54:07.972616  

 6741 23:54:07.972687  

 6742 23:54:07.975907  ==

 6743 23:54:07.978944  Dram Type= 6, Freq= 0, CH_1, rank 0

 6744 23:54:07.982062  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6745 23:54:07.982173  ==

 6746 23:54:07.982269  

 6747 23:54:07.982362  

 6748 23:54:07.985447  	TX Vref Scan disable

 6749 23:54:07.985519   == TX Byte 0 ==

 6750 23:54:07.989006  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6751 23:54:07.995689  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6752 23:54:07.995802   == TX Byte 1 ==

 6753 23:54:07.999057  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6754 23:54:08.006163  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6755 23:54:08.006248  ==

 6756 23:54:08.009344  Dram Type= 6, Freq= 0, CH_1, rank 0

 6757 23:54:08.011799  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6758 23:54:08.011902  ==

 6759 23:54:08.011993  

 6760 23:54:08.012079  

 6761 23:54:08.015202  	TX Vref Scan disable

 6762 23:54:08.015285   == TX Byte 0 ==

 6763 23:54:08.018724  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6764 23:54:08.025202  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6765 23:54:08.025290   == TX Byte 1 ==

 6766 23:54:08.028394  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6767 23:54:08.035569  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6768 23:54:08.035683  

 6769 23:54:08.035750  [DATLAT]

 6770 23:54:08.035812  Freq=400, CH1 RK0

 6771 23:54:08.035870  

 6772 23:54:08.038894  DATLAT Default: 0xf

 6773 23:54:08.039003  0, 0xFFFF, sum = 0

 6774 23:54:08.042224  1, 0xFFFF, sum = 0

 6775 23:54:08.045286  2, 0xFFFF, sum = 0

 6776 23:54:08.045366  3, 0xFFFF, sum = 0

 6777 23:54:08.048502  4, 0xFFFF, sum = 0

 6778 23:54:08.048587  5, 0xFFFF, sum = 0

 6779 23:54:08.051665  6, 0xFFFF, sum = 0

 6780 23:54:08.051750  7, 0xFFFF, sum = 0

 6781 23:54:08.055192  8, 0xFFFF, sum = 0

 6782 23:54:08.055277  9, 0xFFFF, sum = 0

 6783 23:54:08.058679  10, 0xFFFF, sum = 0

 6784 23:54:08.058762  11, 0xFFFF, sum = 0

 6785 23:54:08.062111  12, 0xFFFF, sum = 0

 6786 23:54:08.062196  13, 0x0, sum = 1

 6787 23:54:08.065175  14, 0x0, sum = 2

 6788 23:54:08.065287  15, 0x0, sum = 3

 6789 23:54:08.068748  16, 0x0, sum = 4

 6790 23:54:08.068834  best_step = 14

 6791 23:54:08.068902  

 6792 23:54:08.068967  ==

 6793 23:54:08.071975  Dram Type= 6, Freq= 0, CH_1, rank 0

 6794 23:54:08.075378  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6795 23:54:08.079176  ==

 6796 23:54:08.079288  RX Vref Scan: 1

 6797 23:54:08.079381  

 6798 23:54:08.081575  RX Vref 0 -> 0, step: 1

 6799 23:54:08.081658  

 6800 23:54:08.085217  RX Delay -311 -> 252, step: 8

 6801 23:54:08.085299  

 6802 23:54:08.088306  Set Vref, RX VrefLevel [Byte0]: 54

 6803 23:54:08.091366                           [Byte1]: 48

 6804 23:54:08.091449  

 6805 23:54:08.095240  Final RX Vref Byte 0 = 54 to rank0

 6806 23:54:08.098149  Final RX Vref Byte 1 = 48 to rank0

 6807 23:54:08.101613  Final RX Vref Byte 0 = 54 to rank1

 6808 23:54:08.105117  Final RX Vref Byte 1 = 48 to rank1==

 6809 23:54:08.108158  Dram Type= 6, Freq= 0, CH_1, rank 0

 6810 23:54:08.111560  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6811 23:54:08.111644  ==

 6812 23:54:08.115065  DQS Delay:

 6813 23:54:08.115149  DQS0 = 28, DQS1 = 32

 6814 23:54:08.118252  DQM Delay:

 6815 23:54:08.118341  DQM0 = 10, DQM1 = 12

 6816 23:54:08.118407  DQ Delay:

 6817 23:54:08.122099  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8

 6818 23:54:08.125331  DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8

 6819 23:54:08.128310  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4

 6820 23:54:08.132213  DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24

 6821 23:54:08.132316  

 6822 23:54:08.132420  

 6823 23:54:08.142103  [DQSOSCAuto] RK0, (LSB)MR18= 0x96cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps

 6824 23:54:08.142213  CH1 RK0: MR19=C0C, MR18=96CF

 6825 23:54:08.148224  CH1_RK0: MR19=0xC0C, MR18=0x96CF, DQSOSC=384, MR23=63, INC=400, DEC=267

 6826 23:54:08.148305  ==

 6827 23:54:08.151930  Dram Type= 6, Freq= 0, CH_1, rank 1

 6828 23:54:08.158559  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6829 23:54:08.158640  ==

 6830 23:54:08.161620  [Gating] SW mode calibration

 6831 23:54:08.167993  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6832 23:54:08.171659  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6833 23:54:08.178065   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6834 23:54:08.181074   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6835 23:54:08.184708   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6836 23:54:08.191302   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6837 23:54:08.194471   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6838 23:54:08.197819   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6839 23:54:08.204285   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6840 23:54:08.207938   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6841 23:54:08.211228   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6842 23:54:08.214385  Total UI for P1: 0, mck2ui 16

 6843 23:54:08.217736  best dqsien dly found for B0: ( 0, 14, 24)

 6844 23:54:08.221213  Total UI for P1: 0, mck2ui 16

 6845 23:54:08.224239  best dqsien dly found for B1: ( 0, 14, 24)

 6846 23:54:08.227779  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6847 23:54:08.230696  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6848 23:54:08.230779  

 6849 23:54:08.237293  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6850 23:54:08.241083  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6851 23:54:08.241162  [Gating] SW calibration Done

 6852 23:54:08.244083  ==

 6853 23:54:08.244208  Dram Type= 6, Freq= 0, CH_1, rank 1

 6854 23:54:08.251127  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6855 23:54:08.251240  ==

 6856 23:54:08.251309  RX Vref Scan: 0

 6857 23:54:08.251373  

 6858 23:54:08.254443  RX Vref 0 -> 0, step: 1

 6859 23:54:08.254525  

 6860 23:54:08.257893  RX Delay -410 -> 252, step: 16

 6861 23:54:08.260951  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6862 23:54:08.264143  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6863 23:54:08.271295  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6864 23:54:08.274412  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6865 23:54:08.277847  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6866 23:54:08.281029  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6867 23:54:08.287723  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6868 23:54:08.291019  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6869 23:54:08.294366  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6870 23:54:08.297472  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6871 23:54:08.304286  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6872 23:54:08.307411  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6873 23:54:08.310668  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6874 23:54:08.314388  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6875 23:54:08.321153  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6876 23:54:08.324538  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6877 23:54:08.324653  ==

 6878 23:54:08.327510  Dram Type= 6, Freq= 0, CH_1, rank 1

 6879 23:54:08.330885  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6880 23:54:08.330962  ==

 6881 23:54:08.334611  DQS Delay:

 6882 23:54:08.334695  DQS0 = 35, DQS1 = 35

 6883 23:54:08.337487  DQM Delay:

 6884 23:54:08.337571  DQM0 = 18, DQM1 = 13

 6885 23:54:08.337652  DQ Delay:

 6886 23:54:08.340962  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16

 6887 23:54:08.343724  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6888 23:54:08.347357  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6889 23:54:08.350458  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24

 6890 23:54:08.350540  

 6891 23:54:08.350603  

 6892 23:54:08.350663  ==

 6893 23:54:08.354085  Dram Type= 6, Freq= 0, CH_1, rank 1

 6894 23:54:08.360598  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6895 23:54:08.360682  ==

 6896 23:54:08.360748  

 6897 23:54:08.360807  

 6898 23:54:08.360882  	TX Vref Scan disable

 6899 23:54:08.363961   == TX Byte 0 ==

 6900 23:54:08.367094  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6901 23:54:08.370640  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6902 23:54:08.373661   == TX Byte 1 ==

 6903 23:54:08.377159  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6904 23:54:08.380332  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6905 23:54:08.380464  ==

 6906 23:54:08.383802  Dram Type= 6, Freq= 0, CH_1, rank 1

 6907 23:54:08.390375  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6908 23:54:08.390500  ==

 6909 23:54:08.390611  

 6910 23:54:08.390721  

 6911 23:54:08.390831  	TX Vref Scan disable

 6912 23:54:08.393765   == TX Byte 0 ==

 6913 23:54:08.396914  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6914 23:54:08.400695  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6915 23:54:08.403658   == TX Byte 1 ==

 6916 23:54:08.406941  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6917 23:54:08.410466  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6918 23:54:08.410588  

 6919 23:54:08.413644  [DATLAT]

 6920 23:54:08.413765  Freq=400, CH1 RK1

 6921 23:54:08.413879  

 6922 23:54:08.416906  DATLAT Default: 0xe

 6923 23:54:08.417030  0, 0xFFFF, sum = 0

 6924 23:54:08.420405  1, 0xFFFF, sum = 0

 6925 23:54:08.420525  2, 0xFFFF, sum = 0

 6926 23:54:08.424065  3, 0xFFFF, sum = 0

 6927 23:54:08.424190  4, 0xFFFF, sum = 0

 6928 23:54:08.427100  5, 0xFFFF, sum = 0

 6929 23:54:08.427224  6, 0xFFFF, sum = 0

 6930 23:54:08.430390  7, 0xFFFF, sum = 0

 6931 23:54:08.430515  8, 0xFFFF, sum = 0

 6932 23:54:08.433675  9, 0xFFFF, sum = 0

 6933 23:54:08.433792  10, 0xFFFF, sum = 0

 6934 23:54:08.437052  11, 0xFFFF, sum = 0

 6935 23:54:08.440206  12, 0xFFFF, sum = 0

 6936 23:54:08.440328  13, 0x0, sum = 1

 6937 23:54:08.440444  14, 0x0, sum = 2

 6938 23:54:08.443757  15, 0x0, sum = 3

 6939 23:54:08.443881  16, 0x0, sum = 4

 6940 23:54:08.447444  best_step = 14

 6941 23:54:08.447565  

 6942 23:54:08.447679  ==

 6943 23:54:08.450656  Dram Type= 6, Freq= 0, CH_1, rank 1

 6944 23:54:08.453997  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6945 23:54:08.454121  ==

 6946 23:54:08.457318  RX Vref Scan: 0

 6947 23:54:08.457435  

 6948 23:54:08.457540  RX Vref 0 -> 0, step: 1

 6949 23:54:08.457649  

 6950 23:54:08.460679  RX Delay -311 -> 252, step: 8

 6951 23:54:08.468273  iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440

 6952 23:54:08.471778  iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440

 6953 23:54:08.475280  iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440

 6954 23:54:08.481187  iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440

 6955 23:54:08.485013  iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440

 6956 23:54:08.488020  iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440

 6957 23:54:08.491668  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6958 23:54:08.495035  iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448

 6959 23:54:08.501702  iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448

 6960 23:54:08.504751  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6961 23:54:08.507873  iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448

 6962 23:54:08.514340  iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448

 6963 23:54:08.517684  iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456

 6964 23:54:08.521559  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6965 23:54:08.524568  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6966 23:54:08.531524  iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456

 6967 23:54:08.531607  ==

 6968 23:54:08.534467  Dram Type= 6, Freq= 0, CH_1, rank 1

 6969 23:54:08.538138  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6970 23:54:08.538215  ==

 6971 23:54:08.538277  DQS Delay:

 6972 23:54:08.541411  DQS0 = 28, DQS1 = 32

 6973 23:54:08.541484  DQM Delay:

 6974 23:54:08.544355  DQM0 = 12, DQM1 = 12

 6975 23:54:08.544426  DQ Delay:

 6976 23:54:08.548087  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6977 23:54:08.551366  DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12

 6978 23:54:08.554745  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6979 23:54:08.557896  DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20

 6980 23:54:08.558018  

 6981 23:54:08.558130  

 6982 23:54:08.564555  [DQSOSCAuto] RK1, (LSB)MR18= 0xc656, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps

 6983 23:54:08.568188  CH1 RK1: MR19=C0C, MR18=C656

 6984 23:54:08.574949  CH1_RK1: MR19=0xC0C, MR18=0xC656, DQSOSC=385, MR23=63, INC=398, DEC=265

 6985 23:54:08.577958  [RxdqsGatingPostProcess] freq 400

 6986 23:54:08.584621  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6987 23:54:08.587614  best DQS0 dly(2T, 0.5T) = (0, 10)

 6988 23:54:08.587722  best DQS1 dly(2T, 0.5T) = (0, 10)

 6989 23:54:08.591043  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6990 23:54:08.594477  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6991 23:54:08.597427  best DQS0 dly(2T, 0.5T) = (0, 10)

 6992 23:54:08.600857  best DQS1 dly(2T, 0.5T) = (0, 10)

 6993 23:54:08.604177  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6994 23:54:08.607486  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6995 23:54:08.610840  Pre-setting of DQS Precalculation

 6996 23:54:08.617629  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6997 23:54:08.623816  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6998 23:54:08.630478  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6999 23:54:08.630589  

 7000 23:54:08.630682  

 7001 23:54:08.634484  [Calibration Summary] 800 Mbps

 7002 23:54:08.634568  CH 0, Rank 0

 7003 23:54:08.637752  SW Impedance     : PASS

 7004 23:54:08.640945  DUTY Scan        : NO K

 7005 23:54:08.641024  ZQ Calibration   : PASS

 7006 23:54:08.643891  Jitter Meter     : NO K

 7007 23:54:08.643966  CBT Training     : PASS

 7008 23:54:08.647693  Write leveling   : PASS

 7009 23:54:08.650541  RX DQS gating    : PASS

 7010 23:54:08.650614  RX DQ/DQS(RDDQC) : PASS

 7011 23:54:08.654043  TX DQ/DQS        : PASS

 7012 23:54:08.656917  RX DATLAT        : PASS

 7013 23:54:08.656991  RX DQ/DQS(Engine): PASS

 7014 23:54:08.660360  TX OE            : NO K

 7015 23:54:08.660470  All Pass.

 7016 23:54:08.660563  

 7017 23:54:08.664160  CH 0, Rank 1

 7018 23:54:08.664268  SW Impedance     : PASS

 7019 23:54:08.667130  DUTY Scan        : NO K

 7020 23:54:08.670286  ZQ Calibration   : PASS

 7021 23:54:08.670364  Jitter Meter     : NO K

 7022 23:54:08.673539  CBT Training     : PASS

 7023 23:54:08.676885  Write leveling   : NO K

 7024 23:54:08.676995  RX DQS gating    : PASS

 7025 23:54:08.680833  RX DQ/DQS(RDDQC) : PASS

 7026 23:54:08.683493  TX DQ/DQS        : PASS

 7027 23:54:08.683572  RX DATLAT        : PASS

 7028 23:54:08.687049  RX DQ/DQS(Engine): PASS

 7029 23:54:08.690500  TX OE            : NO K

 7030 23:54:08.690578  All Pass.

 7031 23:54:08.690640  

 7032 23:54:08.690698  CH 1, Rank 0

 7033 23:54:08.693741  SW Impedance     : PASS

 7034 23:54:08.697516  DUTY Scan        : NO K

 7035 23:54:08.697598  ZQ Calibration   : PASS

 7036 23:54:08.700469  Jitter Meter     : NO K

 7037 23:54:08.703825  CBT Training     : PASS

 7038 23:54:08.703938  Write leveling   : PASS

 7039 23:54:08.707190  RX DQS gating    : PASS

 7040 23:54:08.707266  RX DQ/DQS(RDDQC) : PASS

 7041 23:54:08.710130  TX DQ/DQS        : PASS

 7042 23:54:08.713281  RX DATLAT        : PASS

 7043 23:54:08.713382  RX DQ/DQS(Engine): PASS

 7044 23:54:08.717108  TX OE            : NO K

 7045 23:54:08.717195  All Pass.

 7046 23:54:08.717261  

 7047 23:54:08.720345  CH 1, Rank 1

 7048 23:54:08.720422  SW Impedance     : PASS

 7049 23:54:08.723710  DUTY Scan        : NO K

 7050 23:54:08.726906  ZQ Calibration   : PASS

 7051 23:54:08.727031  Jitter Meter     : NO K

 7052 23:54:08.730007  CBT Training     : PASS

 7053 23:54:08.733639  Write leveling   : NO K

 7054 23:54:08.733745  RX DQS gating    : PASS

 7055 23:54:08.736650  RX DQ/DQS(RDDQC) : PASS

 7056 23:54:08.740032  TX DQ/DQS        : PASS

 7057 23:54:08.740116  RX DATLAT        : PASS

 7058 23:54:08.743653  RX DQ/DQS(Engine): PASS

 7059 23:54:08.746759  TX OE            : NO K

 7060 23:54:08.746843  All Pass.

 7061 23:54:08.746912  

 7062 23:54:08.746987  DramC Write-DBI off

 7063 23:54:08.750466  	PER_BANK_REFRESH: Hybrid Mode

 7064 23:54:08.753292  TX_TRACKING: ON

 7065 23:54:08.760078  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7066 23:54:08.763291  [FAST_K] Save calibration result to emmc

 7067 23:54:08.769773  dramc_set_vcore_voltage set vcore to 725000

 7068 23:54:08.769880  Read voltage for 1600, 0

 7069 23:54:08.773155  Vio18 = 0

 7070 23:54:08.773236  Vcore = 725000

 7071 23:54:08.773298  Vdram = 0

 7072 23:54:08.776439  Vddq = 0

 7073 23:54:08.776514  Vmddr = 0

 7074 23:54:08.779902  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7075 23:54:08.786558  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7076 23:54:08.790011  MEM_TYPE=3, freq_sel=13

 7077 23:54:08.793161  sv_algorithm_assistance_LP4_3733 

 7078 23:54:08.796517  ============ PULL DRAM RESETB DOWN ============

 7079 23:54:08.799997  ========== PULL DRAM RESETB DOWN end =========

 7080 23:54:08.803128  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7081 23:54:08.806238  =================================== 

 7082 23:54:08.809586  LPDDR4 DRAM CONFIGURATION

 7083 23:54:08.813161  =================================== 

 7084 23:54:08.816232  EX_ROW_EN[0]    = 0x0

 7085 23:54:08.816334  EX_ROW_EN[1]    = 0x0

 7086 23:54:08.819882  LP4Y_EN      = 0x0

 7087 23:54:08.819959  WORK_FSP     = 0x1

 7088 23:54:08.822967  WL           = 0x5

 7089 23:54:08.823046  RL           = 0x5

 7090 23:54:08.826592  BL           = 0x2

 7091 23:54:08.826700  RPST         = 0x0

 7092 23:54:08.829978  RD_PRE       = 0x0

 7093 23:54:08.830062  WR_PRE       = 0x1

 7094 23:54:08.832914  WR_PST       = 0x1

 7095 23:54:08.833004  DBI_WR       = 0x0

 7096 23:54:08.836209  DBI_RD       = 0x0

 7097 23:54:08.839766  OTF          = 0x1

 7098 23:54:08.842910  =================================== 

 7099 23:54:08.842994  =================================== 

 7100 23:54:08.846175  ANA top config

 7101 23:54:08.849571  =================================== 

 7102 23:54:08.852998  DLL_ASYNC_EN            =  0

 7103 23:54:08.853102  ALL_SLAVE_EN            =  0

 7104 23:54:08.856372  NEW_RANK_MODE           =  1

 7105 23:54:08.859444  DLL_IDLE_MODE           =  1

 7106 23:54:08.862951  LP45_APHY_COMB_EN       =  1

 7107 23:54:08.866164  TX_ODT_DIS              =  0

 7108 23:54:08.866275  NEW_8X_MODE             =  1

 7109 23:54:08.869853  =================================== 

 7110 23:54:08.873541  =================================== 

 7111 23:54:08.876206  data_rate                  = 3200

 7112 23:54:08.879629  CKR                        = 1

 7113 23:54:08.882752  DQ_P2S_RATIO               = 8

 7114 23:54:08.886725  =================================== 

 7115 23:54:08.889687  CA_P2S_RATIO               = 8

 7116 23:54:08.889793  DQ_CA_OPEN                 = 0

 7117 23:54:08.892978  DQ_SEMI_OPEN               = 0

 7118 23:54:08.896384  CA_SEMI_OPEN               = 0

 7119 23:54:08.899697  CA_FULL_RATE               = 0

 7120 23:54:08.903066  DQ_CKDIV4_EN               = 0

 7121 23:54:08.906390  CA_CKDIV4_EN               = 0

 7122 23:54:08.906479  CA_PREDIV_EN               = 0

 7123 23:54:08.909443  PH8_DLY                    = 12

 7124 23:54:08.912533  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7125 23:54:08.916451  DQ_AAMCK_DIV               = 4

 7126 23:54:08.919718  CA_AAMCK_DIV               = 4

 7127 23:54:08.923009  CA_ADMCK_DIV               = 4

 7128 23:54:08.926288  DQ_TRACK_CA_EN             = 0

 7129 23:54:08.926371  CA_PICK                    = 1600

 7130 23:54:08.929622  CA_MCKIO                   = 1600

 7131 23:54:08.933031  MCKIO_SEMI                 = 0

 7132 23:54:08.935854  PLL_FREQ                   = 3068

 7133 23:54:08.939681  DQ_UI_PI_RATIO             = 32

 7134 23:54:08.942967  CA_UI_PI_RATIO             = 0

 7135 23:54:08.946232  =================================== 

 7136 23:54:08.949392  =================================== 

 7137 23:54:08.949469  memory_type:LPDDR4         

 7138 23:54:08.952936  GP_NUM     : 10       

 7139 23:54:08.956067  SRAM_EN    : 1       

 7140 23:54:08.956143  MD32_EN    : 0       

 7141 23:54:08.959205  =================================== 

 7142 23:54:08.962513  [ANA_INIT] >>>>>>>>>>>>>> 

 7143 23:54:08.966540  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7144 23:54:08.969446  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7145 23:54:08.972538  =================================== 

 7146 23:54:08.976312  data_rate = 3200,PCW = 0X7600

 7147 23:54:08.979585  =================================== 

 7148 23:54:08.982911  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7149 23:54:08.985913  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7150 23:54:08.992576  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7151 23:54:08.996206  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7152 23:54:08.999671  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7153 23:54:09.002527  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7154 23:54:09.005963  [ANA_INIT] flow start 

 7155 23:54:09.010241  [ANA_INIT] PLL >>>>>>>> 

 7156 23:54:09.010371  [ANA_INIT] PLL <<<<<<<< 

 7157 23:54:09.012669  [ANA_INIT] MIDPI >>>>>>>> 

 7158 23:54:09.016589  [ANA_INIT] MIDPI <<<<<<<< 

 7159 23:54:09.016674  [ANA_INIT] DLL >>>>>>>> 

 7160 23:54:09.019424  [ANA_INIT] DLL <<<<<<<< 

 7161 23:54:09.022629  [ANA_INIT] flow end 

 7162 23:54:09.025861  ============ LP4 DIFF to SE enter ============

 7163 23:54:09.029204  ============ LP4 DIFF to SE exit  ============

 7164 23:54:09.032659  [ANA_INIT] <<<<<<<<<<<<< 

 7165 23:54:09.036399  [Flow] Enable top DCM control >>>>> 

 7166 23:54:09.039647  [Flow] Enable top DCM control <<<<< 

 7167 23:54:09.042536  Enable DLL master slave shuffle 

 7168 23:54:09.046209  ============================================================== 

 7169 23:54:09.049236  Gating Mode config

 7170 23:54:09.056021  ============================================================== 

 7171 23:54:09.056140  Config description: 

 7172 23:54:09.065649  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7173 23:54:09.072467  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7174 23:54:09.079174  SELPH_MODE            0: By rank         1: By Phase 

 7175 23:54:09.082467  ============================================================== 

 7176 23:54:09.085745  GAT_TRACK_EN                 =  1

 7177 23:54:09.089000  RX_GATING_MODE               =  2

 7178 23:54:09.092284  RX_GATING_TRACK_MODE         =  2

 7179 23:54:09.095436  SELPH_MODE                   =  1

 7180 23:54:09.099403  PICG_EARLY_EN                =  1

 7181 23:54:09.102722  VALID_LAT_VALUE              =  1

 7182 23:54:09.105739  ============================================================== 

 7183 23:54:09.108964  Enter into Gating configuration >>>> 

 7184 23:54:09.112310  Exit from Gating configuration <<<< 

 7185 23:54:09.115565  Enter into  DVFS_PRE_config >>>>> 

 7186 23:54:09.129015  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7187 23:54:09.132285  Exit from  DVFS_PRE_config <<<<< 

 7188 23:54:09.135534  Enter into PICG configuration >>>> 

 7189 23:54:09.135656  Exit from PICG configuration <<<< 

 7190 23:54:09.138970  [RX_INPUT] configuration >>>>> 

 7191 23:54:09.142237  [RX_INPUT] configuration <<<<< 

 7192 23:54:09.148661  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7193 23:54:09.152035  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7194 23:54:09.158970  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7195 23:54:09.165538  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7196 23:54:09.171954  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7197 23:54:09.178528  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7198 23:54:09.181797  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7199 23:54:09.185483  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7200 23:54:09.188654  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7201 23:54:09.195064  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7202 23:54:09.198862  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7203 23:54:09.202089  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7204 23:54:09.205387  =================================== 

 7205 23:54:09.208866  LPDDR4 DRAM CONFIGURATION

 7206 23:54:09.211791  =================================== 

 7207 23:54:09.214972  EX_ROW_EN[0]    = 0x0

 7208 23:54:09.215080  EX_ROW_EN[1]    = 0x0

 7209 23:54:09.218241  LP4Y_EN      = 0x0

 7210 23:54:09.218323  WORK_FSP     = 0x1

 7211 23:54:09.222037  WL           = 0x5

 7212 23:54:09.222119  RL           = 0x5

 7213 23:54:09.225074  BL           = 0x2

 7214 23:54:09.225156  RPST         = 0x0

 7215 23:54:09.228612  RD_PRE       = 0x0

 7216 23:54:09.228694  WR_PRE       = 0x1

 7217 23:54:09.231730  WR_PST       = 0x1

 7218 23:54:09.231812  DBI_WR       = 0x0

 7219 23:54:09.235368  DBI_RD       = 0x0

 7220 23:54:09.235450  OTF          = 0x1

 7221 23:54:09.238477  =================================== 

 7222 23:54:09.245104  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7223 23:54:09.248382  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7224 23:54:09.251792  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7225 23:54:09.255423  =================================== 

 7226 23:54:09.258372  LPDDR4 DRAM CONFIGURATION

 7227 23:54:09.261672  =================================== 

 7228 23:54:09.264838  EX_ROW_EN[0]    = 0x10

 7229 23:54:09.264917  EX_ROW_EN[1]    = 0x0

 7230 23:54:09.268347  LP4Y_EN      = 0x0

 7231 23:54:09.268422  WORK_FSP     = 0x1

 7232 23:54:09.271629  WL           = 0x5

 7233 23:54:09.271726  RL           = 0x5

 7234 23:54:09.275132  BL           = 0x2

 7235 23:54:09.275204  RPST         = 0x0

 7236 23:54:09.278144  RD_PRE       = 0x0

 7237 23:54:09.278221  WR_PRE       = 0x1

 7238 23:54:09.281531  WR_PST       = 0x1

 7239 23:54:09.281603  DBI_WR       = 0x0

 7240 23:54:09.285213  DBI_RD       = 0x0

 7241 23:54:09.285316  OTF          = 0x1

 7242 23:54:09.288472  =================================== 

 7243 23:54:09.295064  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7244 23:54:09.295169  ==

 7245 23:54:09.298009  Dram Type= 6, Freq= 0, CH_0, rank 0

 7246 23:54:09.301266  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7247 23:54:09.305107  ==

 7248 23:54:09.305182  [Duty_Offset_Calibration]

 7249 23:54:09.308373  	B0:2	B1:1	CA:1

 7250 23:54:09.308446  

 7251 23:54:09.311599  [DutyScan_Calibration_Flow] k_type=0

 7252 23:54:09.320356  

 7253 23:54:09.320463  ==CLK 0==

 7254 23:54:09.324236  Final CLK duty delay cell = 0

 7255 23:54:09.326982  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7256 23:54:09.330712  [0] MIN Duty = 4876%(X100), DQS PI = 48

 7257 23:54:09.330816  [0] AVG Duty = 5016%(X100)

 7258 23:54:09.333971  

 7259 23:54:09.337171  CH0 CLK Duty spec in!! Max-Min= 280%

 7260 23:54:09.340141  [DutyScan_Calibration_Flow] ====Done====

 7261 23:54:09.340244  

 7262 23:54:09.343464  [DutyScan_Calibration_Flow] k_type=1

 7263 23:54:09.359517  

 7264 23:54:09.359601  ==DQS 0 ==

 7265 23:54:09.362660  Final DQS duty delay cell = -4

 7266 23:54:09.366280  [-4] MAX Duty = 5125%(X100), DQS PI = 26

 7267 23:54:09.369811  [-4] MIN Duty = 4657%(X100), DQS PI = 0

 7268 23:54:09.373076  [-4] AVG Duty = 4891%(X100)

 7269 23:54:09.373184  

 7270 23:54:09.373279  ==DQS 1 ==

 7271 23:54:09.376115  Final DQS duty delay cell = 0

 7272 23:54:09.379267  [0] MAX Duty = 5187%(X100), DQS PI = 4

 7273 23:54:09.382716  [0] MIN Duty = 5031%(X100), DQS PI = 52

 7274 23:54:09.386162  [0] AVG Duty = 5109%(X100)

 7275 23:54:09.386242  

 7276 23:54:09.389837  CH0 DQS 0 Duty spec in!! Max-Min= 468%

 7277 23:54:09.389923  

 7278 23:54:09.392703  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 7279 23:54:09.396315  [DutyScan_Calibration_Flow] ====Done====

 7280 23:54:09.396404  

 7281 23:54:09.399476  [DutyScan_Calibration_Flow] k_type=3

 7282 23:54:09.416357  

 7283 23:54:09.416443  ==DQM 0 ==

 7284 23:54:09.419618  Final DQM duty delay cell = 0

 7285 23:54:09.422810  [0] MAX Duty = 5218%(X100), DQS PI = 32

 7286 23:54:09.426147  [0] MIN Duty = 4907%(X100), DQS PI = 56

 7287 23:54:09.429368  [0] AVG Duty = 5062%(X100)

 7288 23:54:09.429443  

 7289 23:54:09.429505  ==DQM 1 ==

 7290 23:54:09.433142  Final DQM duty delay cell = -4

 7291 23:54:09.436689  [-4] MAX Duty = 4969%(X100), DQS PI = 22

 7292 23:54:09.439664  [-4] MIN Duty = 4813%(X100), DQS PI = 12

 7293 23:54:09.442636  [-4] AVG Duty = 4891%(X100)

 7294 23:54:09.442719  

 7295 23:54:09.446260  CH0 DQM 0 Duty spec in!! Max-Min= 311%

 7296 23:54:09.446349  

 7297 23:54:09.449600  CH0 DQM 1 Duty spec in!! Max-Min= 156%

 7298 23:54:09.452766  [DutyScan_Calibration_Flow] ====Done====

 7299 23:54:09.452851  

 7300 23:54:09.456013  [DutyScan_Calibration_Flow] k_type=2

 7301 23:54:09.473566  

 7302 23:54:09.473696  ==DQ 0 ==

 7303 23:54:09.477503  Final DQ duty delay cell = 0

 7304 23:54:09.480579  [0] MAX Duty = 5062%(X100), DQS PI = 26

 7305 23:54:09.483853  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7306 23:54:09.483936  [0] AVG Duty = 4984%(X100)

 7307 23:54:09.484000  

 7308 23:54:09.487032  ==DQ 1 ==

 7309 23:54:09.490129  Final DQ duty delay cell = 0

 7310 23:54:09.493588  [0] MAX Duty = 5094%(X100), DQS PI = 4

 7311 23:54:09.496940  [0] MIN Duty = 4938%(X100), DQS PI = 34

 7312 23:54:09.497056  [0] AVG Duty = 5016%(X100)

 7313 23:54:09.497150  

 7314 23:54:09.500536  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7315 23:54:09.503976  

 7316 23:54:09.506802  CH0 DQ 1 Duty spec in!! Max-Min= 156%

 7317 23:54:09.510623  [DutyScan_Calibration_Flow] ====Done====

 7318 23:54:09.510756  ==

 7319 23:54:09.513480  Dram Type= 6, Freq= 0, CH_1, rank 0

 7320 23:54:09.516748  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7321 23:54:09.516898  ==

 7322 23:54:09.520264  [Duty_Offset_Calibration]

 7323 23:54:09.520382  	B0:1	B1:0	CA:0

 7324 23:54:09.520477  

 7325 23:54:09.523651  [DutyScan_Calibration_Flow] k_type=0

 7326 23:54:09.532819  

 7327 23:54:09.532953  ==CLK 0==

 7328 23:54:09.536276  Final CLK duty delay cell = -4

 7329 23:54:09.539511  [-4] MAX Duty = 5000%(X100), DQS PI = 24

 7330 23:54:09.542882  [-4] MIN Duty = 4876%(X100), DQS PI = 0

 7331 23:54:09.546445  [-4] AVG Duty = 4938%(X100)

 7332 23:54:09.546578  

 7333 23:54:09.549675  CH1 CLK Duty spec in!! Max-Min= 124%

 7334 23:54:09.552662  [DutyScan_Calibration_Flow] ====Done====

 7335 23:54:09.552789  

 7336 23:54:09.555929  [DutyScan_Calibration_Flow] k_type=1

 7337 23:54:09.573380  

 7338 23:54:09.573553  ==DQS 0 ==

 7339 23:54:09.576650  Final DQS duty delay cell = 0

 7340 23:54:09.579831  [0] MAX Duty = 5125%(X100), DQS PI = 30

 7341 23:54:09.583252  [0] MIN Duty = 4844%(X100), DQS PI = 48

 7342 23:54:09.586190  [0] AVG Duty = 4984%(X100)

 7343 23:54:09.586299  

 7344 23:54:09.586396  ==DQS 1 ==

 7345 23:54:09.589524  Final DQS duty delay cell = 0

 7346 23:54:09.592873  [0] MAX Duty = 5249%(X100), DQS PI = 18

 7347 23:54:09.595989  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7348 23:54:09.599788  [0] AVG Duty = 5093%(X100)

 7349 23:54:09.599871  

 7350 23:54:09.603040  CH1 DQS 0 Duty spec in!! Max-Min= 281%

 7351 23:54:09.603122  

 7352 23:54:09.606056  CH1 DQS 1 Duty spec in!! Max-Min= 311%

 7353 23:54:09.609761  [DutyScan_Calibration_Flow] ====Done====

 7354 23:54:09.609886  

 7355 23:54:09.612742  [DutyScan_Calibration_Flow] k_type=3

 7356 23:54:09.630251  

 7357 23:54:09.630394  ==DQM 0 ==

 7358 23:54:09.633112  Final DQM duty delay cell = 0

 7359 23:54:09.636365  [0] MAX Duty = 5218%(X100), DQS PI = 18

 7360 23:54:09.639876  [0] MIN Duty = 4969%(X100), DQS PI = 48

 7361 23:54:09.643413  [0] AVG Duty = 5093%(X100)

 7362 23:54:09.643496  

 7363 23:54:09.643560  ==DQM 1 ==

 7364 23:54:09.646725  Final DQM duty delay cell = 0

 7365 23:54:09.650146  [0] MAX Duty = 5093%(X100), DQS PI = 16

 7366 23:54:09.652941  [0] MIN Duty = 4907%(X100), DQS PI = 50

 7367 23:54:09.656821  [0] AVG Duty = 5000%(X100)

 7368 23:54:09.656904  

 7369 23:54:09.660050  CH1 DQM 0 Duty spec in!! Max-Min= 249%

 7370 23:54:09.660190  

 7371 23:54:09.663056  CH1 DQM 1 Duty spec in!! Max-Min= 186%

 7372 23:54:09.666412  [DutyScan_Calibration_Flow] ====Done====

 7373 23:54:09.666539  

 7374 23:54:09.669934  [DutyScan_Calibration_Flow] k_type=2

 7375 23:54:09.686258  

 7376 23:54:09.686375  ==DQ 0 ==

 7377 23:54:09.689604  Final DQ duty delay cell = -4

 7378 23:54:09.693092  [-4] MAX Duty = 5062%(X100), DQS PI = 12

 7379 23:54:09.695975  [-4] MIN Duty = 4875%(X100), DQS PI = 46

 7380 23:54:09.699284  [-4] AVG Duty = 4968%(X100)

 7381 23:54:09.699395  

 7382 23:54:09.699488  ==DQ 1 ==

 7383 23:54:09.702391  Final DQ duty delay cell = 0

 7384 23:54:09.706210  [0] MAX Duty = 5124%(X100), DQS PI = 18

 7385 23:54:09.709545  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7386 23:54:09.713229  [0] AVG Duty = 5031%(X100)

 7387 23:54:09.713311  

 7388 23:54:09.715947  CH1 DQ 0 Duty spec in!! Max-Min= 187%

 7389 23:54:09.716076  

 7390 23:54:09.719188  CH1 DQ 1 Duty spec in!! Max-Min= 186%

 7391 23:54:09.722685  [DutyScan_Calibration_Flow] ====Done====

 7392 23:54:09.725663  nWR fixed to 30

 7393 23:54:09.725744  [ModeRegInit_LP4] CH0 RK0

 7394 23:54:09.728879  [ModeRegInit_LP4] CH0 RK1

 7395 23:54:09.732656  [ModeRegInit_LP4] CH1 RK0

 7396 23:54:09.735731  [ModeRegInit_LP4] CH1 RK1

 7397 23:54:09.735810  match AC timing 5

 7398 23:54:09.742539  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7399 23:54:09.745654  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7400 23:54:09.748769  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7401 23:54:09.755771  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7402 23:54:09.758772  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7403 23:54:09.758856  [MiockJmeterHQA]

 7404 23:54:09.758920  

 7405 23:54:09.762379  [DramcMiockJmeter] u1RxGatingPI = 0

 7406 23:54:09.765956  0 : 4255, 4029

 7407 23:54:09.766040  4 : 4252, 4027

 7408 23:54:09.768872  8 : 4255, 4029

 7409 23:54:09.768955  12 : 4255, 4029

 7410 23:54:09.769022  16 : 4252, 4027

 7411 23:54:09.772393  20 : 4363, 4137

 7412 23:54:09.772477  24 : 4363, 4138

 7413 23:54:09.775467  28 : 4363, 4137

 7414 23:54:09.775546  32 : 4253, 4027

 7415 23:54:09.779189  36 : 4254, 4029

 7416 23:54:09.779292  40 : 4250, 4027

 7417 23:54:09.782709  44 : 4252, 4027

 7418 23:54:09.782788  48 : 4361, 4137

 7419 23:54:09.782853  52 : 4250, 4027

 7420 23:54:09.785534  56 : 4250, 4026

 7421 23:54:09.785637  60 : 4250, 4027

 7422 23:54:09.788882  64 : 4252, 4027

 7423 23:54:09.788957  68 : 4252, 4029

 7424 23:54:09.792569  72 : 4361, 4137

 7425 23:54:09.792644  76 : 4361, 4137

 7426 23:54:09.792709  80 : 4363, 4140

 7427 23:54:09.795445  84 : 4255, 4028

 7428 23:54:09.795576  88 : 4252, 34

 7429 23:54:09.799035  92 : 4250, 0

 7430 23:54:09.799159  96 : 4360, 0

 7431 23:54:09.799274  100 : 4250, 0

 7432 23:54:09.802021  104 : 4250, 0

 7433 23:54:09.802147  108 : 4252, 0

 7434 23:54:09.805205  112 : 4250, 0

 7435 23:54:09.805331  116 : 4250, 0

 7436 23:54:09.805446  120 : 4252, 0

 7437 23:54:09.809291  124 : 4363, 0

 7438 23:54:09.809415  128 : 4250, 0

 7439 23:54:09.812370  132 : 4363, 0

 7440 23:54:09.812456  136 : 4252, 0

 7441 23:54:09.812537  140 : 4250, 0

 7442 23:54:09.815527  144 : 4360, 0

 7443 23:54:09.815622  148 : 4250, 0

 7444 23:54:09.815689  152 : 4252, 0

 7445 23:54:09.818820  156 : 4252, 0

 7446 23:54:09.818916  160 : 4250, 0

 7447 23:54:09.822323  164 : 4250, 0

 7448 23:54:09.822434  168 : 4250, 0

 7449 23:54:09.822529  172 : 4255, 0

 7450 23:54:09.825405  176 : 4360, 0

 7451 23:54:09.825511  180 : 4361, 0

 7452 23:54:09.828655  184 : 4363, 0

 7453 23:54:09.828732  188 : 4249, 0

 7454 23:54:09.828794  192 : 4363, 0

 7455 23:54:09.832275  196 : 4250, 0

 7456 23:54:09.832381  200 : 4255, 0

 7457 23:54:09.835558  204 : 4250, 1133

 7458 23:54:09.835662  208 : 4255, 3949

 7459 23:54:09.838480  212 : 4252, 4030

 7460 23:54:09.838583  216 : 4250, 4027

 7461 23:54:09.841871  220 : 4250, 4027

 7462 23:54:09.841951  224 : 4250, 4027

 7463 23:54:09.842028  228 : 4249, 4027

 7464 23:54:09.845149  232 : 4250, 4027

 7465 23:54:09.845224  236 : 4363, 4140

 7466 23:54:09.848545  240 : 4361, 4137

 7467 23:54:09.848646  244 : 4249, 4027

 7468 23:54:09.852318  248 : 4360, 4137

 7469 23:54:09.852426  252 : 4252, 4029

 7470 23:54:09.855616  256 : 4250, 4026

 7471 23:54:09.855691  260 : 4255, 4032

 7472 23:54:09.858794  264 : 4363, 4139

 7473 23:54:09.858873  268 : 4252, 4029

 7474 23:54:09.861814  272 : 4250, 4027

 7475 23:54:09.861891  276 : 4361, 4137

 7476 23:54:09.861966  280 : 4250, 4027

 7477 23:54:09.865100  284 : 4250, 4026

 7478 23:54:09.865177  288 : 4361, 4137

 7479 23:54:09.869146  292 : 4361, 4137

 7480 23:54:09.869230  296 : 4250, 4027

 7481 23:54:09.871986  300 : 4255, 4029

 7482 23:54:09.872076  304 : 4252, 4029

 7483 23:54:09.874981  308 : 4250, 3976

 7484 23:54:09.875059  312 : 4250, 1988

 7485 23:54:09.875122  

 7486 23:54:09.878458  	MIOCK jitter meter	ch=0

 7487 23:54:09.878561  

 7488 23:54:09.882311  1T = (312-88) = 224 dly cells

 7489 23:54:09.888690  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps

 7490 23:54:09.888776  ==

 7491 23:54:09.891910  Dram Type= 6, Freq= 0, CH_0, rank 0

 7492 23:54:09.895120  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7493 23:54:09.895199  ==

 7494 23:54:09.901990  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7495 23:54:09.905309  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7496 23:54:09.908766  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7497 23:54:09.915064  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7498 23:54:09.923442  [CA 0] Center 43 (12~74) winsize 63

 7499 23:54:09.926681  [CA 1] Center 43 (12~74) winsize 63

 7500 23:54:09.930535  [CA 2] Center 38 (9~68) winsize 60

 7501 23:54:09.933773  [CA 3] Center 38 (8~68) winsize 61

 7502 23:54:09.936958  [CA 4] Center 36 (7~66) winsize 60

 7503 23:54:09.940154  [CA 5] Center 36 (7~65) winsize 59

 7504 23:54:09.940237  

 7505 23:54:09.943420  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7506 23:54:09.943503  

 7507 23:54:09.946983  [CATrainingPosCal] consider 1 rank data

 7508 23:54:09.950250  u2DelayCellTimex100 = 290/100 ps

 7509 23:54:09.953664  CA0 delay=43 (12~74),Diff = 7 PI (23 cell)

 7510 23:54:09.959905  CA1 delay=43 (12~74),Diff = 7 PI (23 cell)

 7511 23:54:09.964075  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 7512 23:54:09.967231  CA3 delay=38 (8~68),Diff = 2 PI (6 cell)

 7513 23:54:09.970385  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 7514 23:54:09.973166  CA5 delay=36 (7~65),Diff = 0 PI (0 cell)

 7515 23:54:09.973249  

 7516 23:54:09.976784  CA PerBit enable=1, Macro0, CA PI delay=36

 7517 23:54:09.976866  

 7518 23:54:09.980419  [CBTSetCACLKResult] CA Dly = 36

 7519 23:54:09.983572  CS Dly: 9 (0~40)

 7520 23:54:09.986642  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7521 23:54:09.990283  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7522 23:54:09.990405  ==

 7523 23:54:09.993345  Dram Type= 6, Freq= 0, CH_0, rank 1

 7524 23:54:09.996631  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7525 23:54:09.996716  ==

 7526 23:54:10.003005  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7527 23:54:10.007157  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7528 23:54:10.013383  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7529 23:54:10.016534  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7530 23:54:10.026683  [CA 0] Center 42 (12~73) winsize 62

 7531 23:54:10.030127  [CA 1] Center 42 (12~73) winsize 62

 7532 23:54:10.033067  [CA 2] Center 38 (8~68) winsize 61

 7533 23:54:10.037315  [CA 3] Center 37 (8~67) winsize 60

 7534 23:54:10.040354  [CA 4] Center 36 (6~66) winsize 61

 7535 23:54:10.043658  [CA 5] Center 35 (5~65) winsize 61

 7536 23:54:10.043783  

 7537 23:54:10.046912  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7538 23:54:10.047034  

 7539 23:54:10.049944  [CATrainingPosCal] consider 2 rank data

 7540 23:54:10.053603  u2DelayCellTimex100 = 290/100 ps

 7541 23:54:10.057038  CA0 delay=42 (12~73),Diff = 6 PI (20 cell)

 7542 23:54:10.063489  CA1 delay=42 (12~73),Diff = 6 PI (20 cell)

 7543 23:54:10.066457  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 7544 23:54:10.070292  CA3 delay=37 (8~67),Diff = 1 PI (3 cell)

 7545 23:54:10.073465  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 7546 23:54:10.076846  CA5 delay=36 (7~65),Diff = 0 PI (0 cell)

 7547 23:54:10.076973  

 7548 23:54:10.079909  CA PerBit enable=1, Macro0, CA PI delay=36

 7549 23:54:10.080033  

 7550 23:54:10.083439  [CBTSetCACLKResult] CA Dly = 36

 7551 23:54:10.087047  CS Dly: 10 (0~42)

 7552 23:54:10.089813  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7553 23:54:10.093182  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7554 23:54:10.093308  

 7555 23:54:10.096412  ----->DramcWriteLeveling(PI) begin...

 7556 23:54:10.096539  ==

 7557 23:54:10.100183  Dram Type= 6, Freq= 0, CH_0, rank 0

 7558 23:54:10.103413  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7559 23:54:10.106440  ==

 7560 23:54:10.106550  Write leveling (Byte 0): 34 => 34

 7561 23:54:10.109545  Write leveling (Byte 1): 28 => 28

 7562 23:54:10.112955  DramcWriteLeveling(PI) end<-----

 7563 23:54:10.113043  

 7564 23:54:10.113108  ==

 7565 23:54:10.116851  Dram Type= 6, Freq= 0, CH_0, rank 0

 7566 23:54:10.123055  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7567 23:54:10.123171  ==

 7568 23:54:10.126693  [Gating] SW mode calibration

 7569 23:54:10.133053  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7570 23:54:10.136895  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7571 23:54:10.139990   1  4  0 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)

 7572 23:54:10.146463   1  4  4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)

 7573 23:54:10.149745   1  4  8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)

 7574 23:54:10.153097   1  4 12 | B1->B0 | 2323 3736 | 0 1 | (0 0) (1 1)

 7575 23:54:10.160123   1  4 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)

 7576 23:54:10.163222   1  4 20 | B1->B0 | 3434 3b3b | 1 0 | (1 1) (0 0)

 7577 23:54:10.166691   1  4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)

 7578 23:54:10.172973   1  4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)

 7579 23:54:10.176494   1  5  0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)

 7580 23:54:10.179880   1  5  4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)

 7581 23:54:10.186489   1  5  8 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (0 0)

 7582 23:54:10.189772   1  5 12 | B1->B0 | 3434 2d2c | 1 1 | (1 1) (0 0)

 7583 23:54:10.192995   1  5 16 | B1->B0 | 3434 2b2a | 0 1 | (0 1) (0 0)

 7584 23:54:10.199419   1  5 20 | B1->B0 | 2929 3131 | 0 1 | (0 0) (1 1)

 7585 23:54:10.203156   1  5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)

 7586 23:54:10.206351   1  5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 7587 23:54:10.212887   1  6  0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)

 7588 23:54:10.216461   1  6  4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)

 7589 23:54:10.219429   1  6  8 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)

 7590 23:54:10.226044   1  6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)

 7591 23:54:10.229678   1  6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)

 7592 23:54:10.233341   1  6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (0 0)

 7593 23:54:10.239856   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7594 23:54:10.242831   1  6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 7595 23:54:10.246490   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7596 23:54:10.253087   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7597 23:54:10.256842   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7598 23:54:10.259926   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7599 23:54:10.266333   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 7600 23:54:10.269375   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7601 23:54:10.272924   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7602 23:54:10.275860   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7603 23:54:10.282976   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7604 23:54:10.286267   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7605 23:54:10.289503   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7606 23:54:10.296005   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7607 23:54:10.299269   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7608 23:54:10.302776   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7609 23:54:10.309729   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7610 23:54:10.313150   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7611 23:54:10.316046   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7612 23:54:10.322844   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7613 23:54:10.326195   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7614 23:54:10.330099   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7615 23:54:10.336292   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7616 23:54:10.336399  Total UI for P1: 0, mck2ui 16

 7617 23:54:10.339922  best dqsien dly found for B0: ( 1,  9, 10)

 7618 23:54:10.346971   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7619 23:54:10.349667   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7620 23:54:10.352783  Total UI for P1: 0, mck2ui 16

 7621 23:54:10.356492  best dqsien dly found for B1: ( 1,  9, 18)

 7622 23:54:10.359722  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7623 23:54:10.363079  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 7624 23:54:10.363205  

 7625 23:54:10.366511  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7626 23:54:10.373029  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 7627 23:54:10.373113  [Gating] SW calibration Done

 7628 23:54:10.373178  ==

 7629 23:54:10.376283  Dram Type= 6, Freq= 0, CH_0, rank 0

 7630 23:54:10.382730  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7631 23:54:10.382814  ==

 7632 23:54:10.382883  RX Vref Scan: 0

 7633 23:54:10.382974  

 7634 23:54:10.386434  RX Vref 0 -> 0, step: 1

 7635 23:54:10.386515  

 7636 23:54:10.389081  RX Delay 0 -> 252, step: 8

 7637 23:54:10.392619  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 7638 23:54:10.395717  iDelay=200, Bit 1, Center 143 (88 ~ 199) 112

 7639 23:54:10.399530  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 7640 23:54:10.406501  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 7641 23:54:10.409729  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7642 23:54:10.412227  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7643 23:54:10.416033  iDelay=200, Bit 6, Center 143 (96 ~ 191) 96

 7644 23:54:10.419148  iDelay=200, Bit 7, Center 143 (96 ~ 191) 96

 7645 23:54:10.422281  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 7646 23:54:10.428908  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 7647 23:54:10.432169  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 7648 23:54:10.435966  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7649 23:54:10.439178  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 7650 23:54:10.445668  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 7651 23:54:10.449522  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7652 23:54:10.452488  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7653 23:54:10.452571  ==

 7654 23:54:10.455650  Dram Type= 6, Freq= 0, CH_0, rank 0

 7655 23:54:10.459396  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7656 23:54:10.459504  ==

 7657 23:54:10.462191  DQS Delay:

 7658 23:54:10.462293  DQS0 = 0, DQS1 = 0

 7659 23:54:10.465895  DQM Delay:

 7660 23:54:10.465977  DQM0 = 137, DQM1 = 130

 7661 23:54:10.466041  DQ Delay:

 7662 23:54:10.468858  DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135

 7663 23:54:10.475706  DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143

 7664 23:54:10.479355  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123

 7665 23:54:10.482306  DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135

 7666 23:54:10.482386  

 7667 23:54:10.482450  

 7668 23:54:10.482511  ==

 7669 23:54:10.485670  Dram Type= 6, Freq= 0, CH_0, rank 0

 7670 23:54:10.489021  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7671 23:54:10.489100  ==

 7672 23:54:10.489164  

 7673 23:54:10.489223  

 7674 23:54:10.492223  	TX Vref Scan disable

 7675 23:54:10.495270   == TX Byte 0 ==

 7676 23:54:10.498860  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 7677 23:54:10.502234  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7678 23:54:10.505592   == TX Byte 1 ==

 7679 23:54:10.508894  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7680 23:54:10.512256  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7681 23:54:10.512380  ==

 7682 23:54:10.515107  Dram Type= 6, Freq= 0, CH_0, rank 0

 7683 23:54:10.518997  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7684 23:54:10.522112  ==

 7685 23:54:10.533733  

 7686 23:54:10.538815  TX Vref early break, caculate TX vref

 7687 23:54:10.540237  TX Vref=16, minBit 0, minWin=23, winSum=387

 7688 23:54:10.543525  TX Vref=18, minBit 4, minWin=23, winSum=390

 7689 23:54:10.546780  TX Vref=20, minBit 7, minWin=23, winSum=397

 7690 23:54:10.550269  TX Vref=22, minBit 1, minWin=25, winSum=409

 7691 23:54:10.553284  TX Vref=24, minBit 6, minWin=25, winSum=417

 7692 23:54:10.559935  TX Vref=26, minBit 2, minWin=24, winSum=424

 7693 23:54:10.563291  TX Vref=28, minBit 1, minWin=25, winSum=425

 7694 23:54:10.566454  TX Vref=30, minBit 6, minWin=24, winSum=415

 7695 23:54:10.569699  TX Vref=32, minBit 6, minWin=24, winSum=407

 7696 23:54:10.573730  TX Vref=34, minBit 2, minWin=23, winSum=398

 7697 23:54:10.580021  [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28

 7698 23:54:10.580136  

 7699 23:54:10.583263  Final TX Range 0 Vref 28

 7700 23:54:10.583369  

 7701 23:54:10.583468  ==

 7702 23:54:10.586656  Dram Type= 6, Freq= 0, CH_0, rank 0

 7703 23:54:10.589996  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7704 23:54:10.590079  ==

 7705 23:54:10.590143  

 7706 23:54:10.590203  

 7707 23:54:10.593401  	TX Vref Scan disable

 7708 23:54:10.599806  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 7709 23:54:10.599915   == TX Byte 0 ==

 7710 23:54:10.602923  u2DelayCellOfst[0]=10 cells (3 PI)

 7711 23:54:10.606653  u2DelayCellOfst[1]=13 cells (4 PI)

 7712 23:54:10.609906  u2DelayCellOfst[2]=13 cells (4 PI)

 7713 23:54:10.613371  u2DelayCellOfst[3]=10 cells (3 PI)

 7714 23:54:10.616570  u2DelayCellOfst[4]=6 cells (2 PI)

 7715 23:54:10.619717  u2DelayCellOfst[5]=0 cells (0 PI)

 7716 23:54:10.622925  u2DelayCellOfst[6]=20 cells (6 PI)

 7717 23:54:10.626500  u2DelayCellOfst[7]=13 cells (4 PI)

 7718 23:54:10.629395  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 7719 23:54:10.632852  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7720 23:54:10.636241   == TX Byte 1 ==

 7721 23:54:10.636354  u2DelayCellOfst[8]=0 cells (0 PI)

 7722 23:54:10.639649  u2DelayCellOfst[9]=3 cells (1 PI)

 7723 23:54:10.643306  u2DelayCellOfst[10]=10 cells (3 PI)

 7724 23:54:10.646498  u2DelayCellOfst[11]=6 cells (2 PI)

 7725 23:54:10.649726  u2DelayCellOfst[12]=10 cells (3 PI)

 7726 23:54:10.653194  u2DelayCellOfst[13]=10 cells (3 PI)

 7727 23:54:10.656355  u2DelayCellOfst[14]=13 cells (4 PI)

 7728 23:54:10.659632  u2DelayCellOfst[15]=10 cells (3 PI)

 7729 23:54:10.662680  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 7730 23:54:10.669899  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7731 23:54:10.670013  DramC Write-DBI on

 7732 23:54:10.670108  ==

 7733 23:54:10.672821  Dram Type= 6, Freq= 0, CH_0, rank 0

 7734 23:54:10.676146  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7735 23:54:10.679830  ==

 7736 23:54:10.679915  

 7737 23:54:10.680008  

 7738 23:54:10.680124  	TX Vref Scan disable

 7739 23:54:10.683440   == TX Byte 0 ==

 7740 23:54:10.686789  Update DQM dly =734 (2 ,6, 30)  DQM OEN =(3 ,3)

 7741 23:54:10.689664   == TX Byte 1 ==

 7742 23:54:10.693272  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 7743 23:54:10.696330  DramC Write-DBI off

 7744 23:54:10.696418  

 7745 23:54:10.696482  [DATLAT]

 7746 23:54:10.696543  Freq=1600, CH0 RK0

 7747 23:54:10.696602  

 7748 23:54:10.699945  DATLAT Default: 0xf

 7749 23:54:10.700028  0, 0xFFFF, sum = 0

 7750 23:54:10.703294  1, 0xFFFF, sum = 0

 7751 23:54:10.703372  2, 0xFFFF, sum = 0

 7752 23:54:10.706351  3, 0xFFFF, sum = 0

 7753 23:54:10.709943  4, 0xFFFF, sum = 0

 7754 23:54:10.710023  5, 0xFFFF, sum = 0

 7755 23:54:10.713145  6, 0xFFFF, sum = 0

 7756 23:54:10.713249  7, 0xFFFF, sum = 0

 7757 23:54:10.716648  8, 0xFFFF, sum = 0

 7758 23:54:10.716724  9, 0xFFFF, sum = 0

 7759 23:54:10.719665  10, 0xFFFF, sum = 0

 7760 23:54:10.719768  11, 0xFFFF, sum = 0

 7761 23:54:10.722948  12, 0xFFFF, sum = 0

 7762 23:54:10.723033  13, 0xFFFF, sum = 0

 7763 23:54:10.726315  14, 0x0, sum = 1

 7764 23:54:10.726395  15, 0x0, sum = 2

 7765 23:54:10.729840  16, 0x0, sum = 3

 7766 23:54:10.729955  17, 0x0, sum = 4

 7767 23:54:10.732956  best_step = 15

 7768 23:54:10.733054  

 7769 23:54:10.733118  ==

 7770 23:54:10.736056  Dram Type= 6, Freq= 0, CH_0, rank 0

 7771 23:54:10.740100  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7772 23:54:10.740204  ==

 7773 23:54:10.743272  RX Vref Scan: 1

 7774 23:54:10.743375  

 7775 23:54:10.743478  Set Vref Range= 24 -> 127

 7776 23:54:10.743559  

 7777 23:54:10.746502  RX Vref 24 -> 127, step: 1

 7778 23:54:10.746579  

 7779 23:54:10.749297  RX Delay 27 -> 252, step: 4

 7780 23:54:10.749401  

 7781 23:54:10.753000  Set Vref, RX VrefLevel [Byte0]: 24

 7782 23:54:10.756111                           [Byte1]: 24

 7783 23:54:10.756194  

 7784 23:54:10.759527  Set Vref, RX VrefLevel [Byte0]: 25

 7785 23:54:10.762624                           [Byte1]: 25

 7786 23:54:10.762709  

 7787 23:54:10.765927  Set Vref, RX VrefLevel [Byte0]: 26

 7788 23:54:10.769045                           [Byte1]: 26

 7789 23:54:10.773629  

 7790 23:54:10.773708  Set Vref, RX VrefLevel [Byte0]: 27

 7791 23:54:10.776831                           [Byte1]: 27

 7792 23:54:10.781101  

 7793 23:54:10.781201  Set Vref, RX VrefLevel [Byte0]: 28

 7794 23:54:10.784307                           [Byte1]: 28

 7795 23:54:10.788673  

 7796 23:54:10.788785  Set Vref, RX VrefLevel [Byte0]: 29

 7797 23:54:10.792118                           [Byte1]: 29

 7798 23:54:10.796066  

 7799 23:54:10.796185  Set Vref, RX VrefLevel [Byte0]: 30

 7800 23:54:10.799242                           [Byte1]: 30

 7801 23:54:10.803459  

 7802 23:54:10.803549  Set Vref, RX VrefLevel [Byte0]: 31

 7803 23:54:10.806646                           [Byte1]: 31

 7804 23:54:10.811607  

 7805 23:54:10.811694  Set Vref, RX VrefLevel [Byte0]: 32

 7806 23:54:10.814030                           [Byte1]: 32

 7807 23:54:10.818406  

 7808 23:54:10.818511  Set Vref, RX VrefLevel [Byte0]: 33

 7809 23:54:10.821713                           [Byte1]: 33

 7810 23:54:10.826675  

 7811 23:54:10.826758  Set Vref, RX VrefLevel [Byte0]: 34

 7812 23:54:10.829627                           [Byte1]: 34

 7813 23:54:10.833588  

 7814 23:54:10.833677  Set Vref, RX VrefLevel [Byte0]: 35

 7815 23:54:10.837018                           [Byte1]: 35

 7816 23:54:10.841709  

 7817 23:54:10.841801  Set Vref, RX VrefLevel [Byte0]: 36

 7818 23:54:10.844943                           [Byte1]: 36

 7819 23:54:10.848615  

 7820 23:54:10.848697  Set Vref, RX VrefLevel [Byte0]: 37

 7821 23:54:10.851826                           [Byte1]: 37

 7822 23:54:10.856147  

 7823 23:54:10.856251  Set Vref, RX VrefLevel [Byte0]: 38

 7824 23:54:10.859322                           [Byte1]: 38

 7825 23:54:10.864236  

 7826 23:54:10.864357  Set Vref, RX VrefLevel [Byte0]: 39

 7827 23:54:10.867211                           [Byte1]: 39

 7828 23:54:10.871009  

 7829 23:54:10.871099  Set Vref, RX VrefLevel [Byte0]: 40

 7830 23:54:10.874546                           [Byte1]: 40

 7831 23:54:10.879255  

 7832 23:54:10.879335  Set Vref, RX VrefLevel [Byte0]: 41

 7833 23:54:10.882084                           [Byte1]: 41

 7834 23:54:10.886552  

 7835 23:54:10.886631  Set Vref, RX VrefLevel [Byte0]: 42

 7836 23:54:10.889657                           [Byte1]: 42

 7837 23:54:10.894161  

 7838 23:54:10.894233  Set Vref, RX VrefLevel [Byte0]: 43

 7839 23:54:10.897279                           [Byte1]: 43

 7840 23:54:10.901275  

 7841 23:54:10.901376  Set Vref, RX VrefLevel [Byte0]: 44

 7842 23:54:10.904936                           [Byte1]: 44

 7843 23:54:10.909030  

 7844 23:54:10.909104  Set Vref, RX VrefLevel [Byte0]: 45

 7845 23:54:10.912555                           [Byte1]: 45

 7846 23:54:10.916603  

 7847 23:54:10.916682  Set Vref, RX VrefLevel [Byte0]: 46

 7848 23:54:10.919976                           [Byte1]: 46

 7849 23:54:10.923788  

 7850 23:54:10.923902  Set Vref, RX VrefLevel [Byte0]: 47

 7851 23:54:10.927024                           [Byte1]: 47

 7852 23:54:10.931881  

 7853 23:54:10.931975  Set Vref, RX VrefLevel [Byte0]: 48

 7854 23:54:10.935135                           [Byte1]: 48

 7855 23:54:10.938933  

 7856 23:54:10.939058  Set Vref, RX VrefLevel [Byte0]: 49

 7857 23:54:10.942784                           [Byte1]: 49

 7858 23:54:10.946566  

 7859 23:54:10.946641  Set Vref, RX VrefLevel [Byte0]: 50

 7860 23:54:10.950024                           [Byte1]: 50

 7861 23:54:10.954542  

 7862 23:54:10.954662  Set Vref, RX VrefLevel [Byte0]: 51

 7863 23:54:10.957562                           [Byte1]: 51

 7864 23:54:10.961671  

 7865 23:54:10.961756  Set Vref, RX VrefLevel [Byte0]: 52

 7866 23:54:10.964785                           [Byte1]: 52

 7867 23:54:10.969162  

 7868 23:54:10.969246  Set Vref, RX VrefLevel [Byte0]: 53

 7869 23:54:10.972535                           [Byte1]: 53

 7870 23:54:10.976614  

 7871 23:54:10.976707  Set Vref, RX VrefLevel [Byte0]: 54

 7872 23:54:10.979786                           [Byte1]: 54

 7873 23:54:10.984668  

 7874 23:54:10.984749  Set Vref, RX VrefLevel [Byte0]: 55

 7875 23:54:10.987799                           [Byte1]: 55

 7876 23:54:10.992130  

 7877 23:54:10.992211  Set Vref, RX VrefLevel [Byte0]: 56

 7878 23:54:10.995335                           [Byte1]: 56

 7879 23:54:10.999527  

 7880 23:54:10.999618  Set Vref, RX VrefLevel [Byte0]: 57

 7881 23:54:11.002536                           [Byte1]: 57

 7882 23:54:11.006590  

 7883 23:54:11.006691  Set Vref, RX VrefLevel [Byte0]: 58

 7884 23:54:11.010207                           [Byte1]: 58

 7885 23:54:11.014519  

 7886 23:54:11.014616  Set Vref, RX VrefLevel [Byte0]: 59

 7887 23:54:11.017884                           [Byte1]: 59

 7888 23:54:11.021744  

 7889 23:54:11.021854  Set Vref, RX VrefLevel [Byte0]: 60

 7890 23:54:11.025293                           [Byte1]: 60

 7891 23:54:11.029621  

 7892 23:54:11.029707  Set Vref, RX VrefLevel [Byte0]: 61

 7893 23:54:11.032621                           [Byte1]: 61

 7894 23:54:11.036776  

 7895 23:54:11.036863  Set Vref, RX VrefLevel [Byte0]: 62

 7896 23:54:11.040070                           [Byte1]: 62

 7897 23:54:11.044649  

 7898 23:54:11.044734  Set Vref, RX VrefLevel [Byte0]: 63

 7899 23:54:11.047750                           [Byte1]: 63

 7900 23:54:11.052272  

 7901 23:54:11.052383  Set Vref, RX VrefLevel [Byte0]: 64

 7902 23:54:11.055521                           [Byte1]: 64

 7903 23:54:11.059482  

 7904 23:54:11.059571  Set Vref, RX VrefLevel [Byte0]: 65

 7905 23:54:11.062947                           [Byte1]: 65

 7906 23:54:11.067545  

 7907 23:54:11.067633  Set Vref, RX VrefLevel [Byte0]: 66

 7908 23:54:11.070471                           [Byte1]: 66

 7909 23:54:11.075065  

 7910 23:54:11.075156  Set Vref, RX VrefLevel [Byte0]: 67

 7911 23:54:11.078516                           [Byte1]: 67

 7912 23:54:11.082036  

 7913 23:54:11.082125  Set Vref, RX VrefLevel [Byte0]: 68

 7914 23:54:11.085273                           [Byte1]: 68

 7915 23:54:11.089814  

 7916 23:54:11.089899  Set Vref, RX VrefLevel [Byte0]: 69

 7917 23:54:11.093078                           [Byte1]: 69

 7918 23:54:11.097512  

 7919 23:54:11.097602  Set Vref, RX VrefLevel [Byte0]: 70

 7920 23:54:11.100813                           [Byte1]: 70

 7921 23:54:11.105310  

 7922 23:54:11.105444  Set Vref, RX VrefLevel [Byte0]: 71

 7923 23:54:11.108116                           [Byte1]: 71

 7924 23:54:11.112295  

 7925 23:54:11.112386  Set Vref, RX VrefLevel [Byte0]: 72

 7926 23:54:11.115590                           [Byte1]: 72

 7927 23:54:11.119891  

 7928 23:54:11.120026  Final RX Vref Byte 0 = 57 to rank0

 7929 23:54:11.123243  Final RX Vref Byte 1 = 62 to rank0

 7930 23:54:11.126632  Final RX Vref Byte 0 = 57 to rank1

 7931 23:54:11.130257  Final RX Vref Byte 1 = 62 to rank1==

 7932 23:54:11.133557  Dram Type= 6, Freq= 0, CH_0, rank 0

 7933 23:54:11.140157  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7934 23:54:11.140246  ==

 7935 23:54:11.140318  DQS Delay:

 7936 23:54:11.140393  DQS0 = 0, DQS1 = 0

 7937 23:54:11.143259  DQM Delay:

 7938 23:54:11.143345  DQM0 = 134, DQM1 = 127

 7939 23:54:11.146317  DQ Delay:

 7940 23:54:11.149759  DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132

 7941 23:54:11.152886  DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138

 7942 23:54:11.156758  DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120

 7943 23:54:11.160063  DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136

 7944 23:54:11.160201  

 7945 23:54:11.160328  

 7946 23:54:11.160456  

 7947 23:54:11.163234  [DramC_TX_OE_Calibration] TA2

 7948 23:54:11.166373  Original DQ_B0 (3 6) =30, OEN = 27

 7949 23:54:11.169664  Original DQ_B1 (3 6) =30, OEN = 27

 7950 23:54:11.172848  24, 0x0, End_B0=24 End_B1=24

 7951 23:54:11.172987  25, 0x0, End_B0=25 End_B1=25

 7952 23:54:11.176653  26, 0x0, End_B0=26 End_B1=26

 7953 23:54:11.179702  27, 0x0, End_B0=27 End_B1=27

 7954 23:54:11.182944  28, 0x0, End_B0=28 End_B1=28

 7955 23:54:11.183025  29, 0x0, End_B0=29 End_B1=29

 7956 23:54:11.186160  30, 0x0, End_B0=30 End_B1=30

 7957 23:54:11.189493  31, 0x4141, End_B0=30 End_B1=30

 7958 23:54:11.192867  Byte0 end_step=30  best_step=27

 7959 23:54:11.196258  Byte1 end_step=30  best_step=27

 7960 23:54:11.199664  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7961 23:54:11.202807  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7962 23:54:11.202895  

 7963 23:54:11.202960  

 7964 23:54:11.210284  [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 7965 23:54:11.212832  CH0 RK0: MR19=303, MR18=2520

 7966 23:54:11.219919  CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16

 7967 23:54:11.220035  

 7968 23:54:11.222730  ----->DramcWriteLeveling(PI) begin...

 7969 23:54:11.222839  ==

 7970 23:54:11.226283  Dram Type= 6, Freq= 0, CH_0, rank 1

 7971 23:54:11.229387  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7972 23:54:11.229488  ==

 7973 23:54:11.232973  Write leveling (Byte 0): 36 => 36

 7974 23:54:11.236277  Write leveling (Byte 1): 25 => 25

 7975 23:54:11.239883  DramcWriteLeveling(PI) end<-----

 7976 23:54:11.240010  

 7977 23:54:11.240123  ==

 7978 23:54:11.242836  Dram Type= 6, Freq= 0, CH_0, rank 1

 7979 23:54:11.246014  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7980 23:54:11.246118  ==

 7981 23:54:11.249645  [Gating] SW mode calibration

 7982 23:54:11.256345  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7983 23:54:11.262956  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7984 23:54:11.266610   1  4  0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)

 7985 23:54:11.269785   1  4  4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)

 7986 23:54:11.275881   1  4  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7987 23:54:11.279724   1  4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)

 7988 23:54:11.283083   1  4 16 | B1->B0 | 2a2a 3939 | 1 0 | (1 1) (1 1)

 7989 23:54:11.289461   1  4 20 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (1 1)

 7990 23:54:11.292636   1  4 24 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (1 1)

 7991 23:54:11.296465   1  4 28 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)

 7992 23:54:11.302539   1  5  0 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)

 7993 23:54:11.305851   1  5  4 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)

 7994 23:54:11.309211   1  5  8 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 0)

 7995 23:54:11.316365   1  5 12 | B1->B0 | 3434 3636 | 1 0 | (1 0) (1 0)

 7996 23:54:11.319948   1  5 16 | B1->B0 | 2d2d 3433 | 0 1 | (1 0) (0 1)

 7997 23:54:11.322948   1  5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 7998 23:54:11.329657   1  5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)

 7999 23:54:11.332595   1  5 28 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)

 8000 23:54:11.336073   1  6  0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)

 8001 23:54:11.342418   1  6  4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 8002 23:54:11.346290   1  6  8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)

 8003 23:54:11.349334   1  6 12 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)

 8004 23:54:11.353112   1  6 16 | B1->B0 | 4242 4545 | 0 1 | (0 0) (0 0)

 8005 23:54:11.359316   1  6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 8006 23:54:11.362628   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8007 23:54:11.366028   1  6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 8008 23:54:11.372641   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8009 23:54:11.375870   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8010 23:54:11.379234   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8011 23:54:11.385708   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8012 23:54:11.389665   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8013 23:54:11.392627   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8014 23:54:11.399093   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8015 23:54:11.402336   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8016 23:54:11.405663   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8017 23:54:11.412517   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8018 23:54:11.416106   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8019 23:54:11.418991   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8020 23:54:11.425718   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8021 23:54:11.429282   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8022 23:54:11.432183   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8023 23:54:11.438697   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8024 23:54:11.442067   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8025 23:54:11.445711   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8026 23:54:11.452653   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8027 23:54:11.455949   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8028 23:54:11.459222   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8029 23:54:11.465822   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8030 23:54:11.465911  Total UI for P1: 0, mck2ui 16

 8031 23:54:11.472054  best dqsien dly found for B0: ( 1,  9, 14)

 8032 23:54:11.472171  Total UI for P1: 0, mck2ui 16

 8033 23:54:11.475160  best dqsien dly found for B1: ( 1,  9, 14)

 8034 23:54:11.482026  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 8035 23:54:11.485236  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8036 23:54:11.485318  

 8037 23:54:11.489089  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8038 23:54:11.491953  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8039 23:54:11.495284  [Gating] SW calibration Done

 8040 23:54:11.495367  ==

 8041 23:54:11.498843  Dram Type= 6, Freq= 0, CH_0, rank 1

 8042 23:54:11.501797  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8043 23:54:11.501931  ==

 8044 23:54:11.505200  RX Vref Scan: 0

 8045 23:54:11.505278  

 8046 23:54:11.505342  RX Vref 0 -> 0, step: 1

 8047 23:54:11.505406  

 8048 23:54:11.508898  RX Delay 0 -> 252, step: 8

 8049 23:54:11.512029  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8050 23:54:11.518496  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8051 23:54:11.521888  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8052 23:54:11.525616  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8053 23:54:11.528663  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8054 23:54:11.531608  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8055 23:54:11.535511  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8056 23:54:11.542196  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8057 23:54:11.545317  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8058 23:54:11.548442  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8059 23:54:11.552077  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 8060 23:54:11.555145  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8061 23:54:11.562509  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8062 23:54:11.565520  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8063 23:54:11.568680  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8064 23:54:11.571868  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8065 23:54:11.571943  ==

 8066 23:54:11.574957  Dram Type= 6, Freq= 0, CH_0, rank 1

 8067 23:54:11.581531  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8068 23:54:11.581617  ==

 8069 23:54:11.581682  DQS Delay:

 8070 23:54:11.584748  DQS0 = 0, DQS1 = 0

 8071 23:54:11.584824  DQM Delay:

 8072 23:54:11.588505  DQM0 = 137, DQM1 = 129

 8073 23:54:11.588579  DQ Delay:

 8074 23:54:11.591815  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 8075 23:54:11.595491  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8076 23:54:11.598905  DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123

 8077 23:54:11.601908  DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139

 8078 23:54:11.602018  

 8079 23:54:11.602121  

 8080 23:54:11.602209  ==

 8081 23:54:11.604876  Dram Type= 6, Freq= 0, CH_0, rank 1

 8082 23:54:11.611473  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8083 23:54:11.611554  ==

 8084 23:54:11.611645  

 8085 23:54:11.611712  

 8086 23:54:11.611771  	TX Vref Scan disable

 8087 23:54:11.615028   == TX Byte 0 ==

 8088 23:54:11.618107  Update DQ  dly =993 (3 ,6, 33)  DQ  OEN =(3 ,3)

 8089 23:54:11.621413  Update DQM dly =993 (3 ,6, 33)  DQM OEN =(3 ,3)

 8090 23:54:11.624722   == TX Byte 1 ==

 8091 23:54:11.628177  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8092 23:54:11.632164  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8093 23:54:11.635242  ==

 8094 23:54:11.638679  Dram Type= 6, Freq= 0, CH_0, rank 1

 8095 23:54:11.642089  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8096 23:54:11.642215  ==

 8097 23:54:11.655508  

 8098 23:54:11.658483  TX Vref early break, caculate TX vref

 8099 23:54:11.662025  TX Vref=16, minBit 1, minWin=23, winSum=387

 8100 23:54:11.665176  TX Vref=18, minBit 1, minWin=23, winSum=396

 8101 23:54:11.668677  TX Vref=20, minBit 1, minWin=23, winSum=407

 8102 23:54:11.671542  TX Vref=22, minBit 3, minWin=24, winSum=414

 8103 23:54:11.674891  TX Vref=24, minBit 1, minWin=25, winSum=420

 8104 23:54:11.681920  TX Vref=26, minBit 0, minWin=25, winSum=426

 8105 23:54:11.685072  TX Vref=28, minBit 3, minWin=25, winSum=426

 8106 23:54:11.688649  TX Vref=30, minBit 0, minWin=25, winSum=416

 8107 23:54:11.691702  TX Vref=32, minBit 0, minWin=25, winSum=412

 8108 23:54:11.694993  TX Vref=34, minBit 0, minWin=24, winSum=401

 8109 23:54:11.702087  [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26

 8110 23:54:11.702168  

 8111 23:54:11.705058  Final TX Range 0 Vref 26

 8112 23:54:11.705178  

 8113 23:54:11.705293  ==

 8114 23:54:11.708553  Dram Type= 6, Freq= 0, CH_0, rank 1

 8115 23:54:11.711684  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8116 23:54:11.711807  ==

 8117 23:54:11.711928  

 8118 23:54:11.712033  

 8119 23:54:11.715180  	TX Vref Scan disable

 8120 23:54:11.721832  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8121 23:54:11.721954   == TX Byte 0 ==

 8122 23:54:11.724724  u2DelayCellOfst[0]=13 cells (4 PI)

 8123 23:54:11.728222  u2DelayCellOfst[1]=16 cells (5 PI)

 8124 23:54:11.731315  u2DelayCellOfst[2]=13 cells (4 PI)

 8125 23:54:11.734798  u2DelayCellOfst[3]=13 cells (4 PI)

 8126 23:54:11.738277  u2DelayCellOfst[4]=10 cells (3 PI)

 8127 23:54:11.741528  u2DelayCellOfst[5]=0 cells (0 PI)

 8128 23:54:11.744622  u2DelayCellOfst[6]=16 cells (5 PI)

 8129 23:54:11.748135  u2DelayCellOfst[7]=16 cells (5 PI)

 8130 23:54:11.751302  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8131 23:54:11.754846  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8132 23:54:11.758114   == TX Byte 1 ==

 8133 23:54:11.761416  u2DelayCellOfst[8]=3 cells (1 PI)

 8134 23:54:11.761522  u2DelayCellOfst[9]=0 cells (0 PI)

 8135 23:54:11.764612  u2DelayCellOfst[10]=10 cells (3 PI)

 8136 23:54:11.767720  u2DelayCellOfst[11]=3 cells (1 PI)

 8137 23:54:11.771387  u2DelayCellOfst[12]=10 cells (3 PI)

 8138 23:54:11.774363  u2DelayCellOfst[13]=10 cells (3 PI)

 8139 23:54:11.778061  u2DelayCellOfst[14]=16 cells (5 PI)

 8140 23:54:11.781407  u2DelayCellOfst[15]=10 cells (3 PI)

 8141 23:54:11.784673  Update DQ  dly =977 (3 ,6, 17)  DQ  OEN =(3 ,3)

 8142 23:54:11.791080  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8143 23:54:11.791184  DramC Write-DBI on

 8144 23:54:11.791280  ==

 8145 23:54:11.794358  Dram Type= 6, Freq= 0, CH_0, rank 1

 8146 23:54:11.801072  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8147 23:54:11.801150  ==

 8148 23:54:11.801217  

 8149 23:54:11.801275  

 8150 23:54:11.801331  	TX Vref Scan disable

 8151 23:54:11.805235   == TX Byte 0 ==

 8152 23:54:11.808513  Update DQM dly =737 (2 ,6, 33)  DQM OEN =(3 ,3)

 8153 23:54:11.812186   == TX Byte 1 ==

 8154 23:54:11.815034  Update DQM dly =720 (2 ,6, 16)  DQM OEN =(3 ,3)

 8155 23:54:11.818499  DramC Write-DBI off

 8156 23:54:11.818578  

 8157 23:54:11.818659  [DATLAT]

 8158 23:54:11.818736  Freq=1600, CH0 RK1

 8159 23:54:11.818815  

 8160 23:54:11.821467  DATLAT Default: 0xf

 8161 23:54:11.821566  0, 0xFFFF, sum = 0

 8162 23:54:11.824689  1, 0xFFFF, sum = 0

 8163 23:54:11.828354  2, 0xFFFF, sum = 0

 8164 23:54:11.828442  3, 0xFFFF, sum = 0

 8165 23:54:11.832114  4, 0xFFFF, sum = 0

 8166 23:54:11.832222  5, 0xFFFF, sum = 0

 8167 23:54:11.835063  6, 0xFFFF, sum = 0

 8168 23:54:11.835143  7, 0xFFFF, sum = 0

 8169 23:54:11.838695  8, 0xFFFF, sum = 0

 8170 23:54:11.838773  9, 0xFFFF, sum = 0

 8171 23:54:11.841484  10, 0xFFFF, sum = 0

 8172 23:54:11.841556  11, 0xFFFF, sum = 0

 8173 23:54:11.845061  12, 0xFFFF, sum = 0

 8174 23:54:11.845136  13, 0xFFFF, sum = 0

 8175 23:54:11.848060  14, 0x0, sum = 1

 8176 23:54:11.848136  15, 0x0, sum = 2

 8177 23:54:11.851270  16, 0x0, sum = 3

 8178 23:54:11.851349  17, 0x0, sum = 4

 8179 23:54:11.854435  best_step = 15

 8180 23:54:11.854540  

 8181 23:54:11.854607  ==

 8182 23:54:11.858354  Dram Type= 6, Freq= 0, CH_0, rank 1

 8183 23:54:11.861200  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8184 23:54:11.861322  ==

 8185 23:54:11.865129  RX Vref Scan: 0

 8186 23:54:11.865237  

 8187 23:54:11.865329  RX Vref 0 -> 0, step: 1

 8188 23:54:11.865422  

 8189 23:54:11.868365  RX Delay 19 -> 252, step: 4

 8190 23:54:11.871768  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8191 23:54:11.878478  iDelay=191, Bit 1, Center 138 (91 ~ 186) 96

 8192 23:54:11.881737  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8193 23:54:11.884966  iDelay=191, Bit 3, Center 132 (79 ~ 186) 108

 8194 23:54:11.888442  iDelay=191, Bit 4, Center 136 (87 ~ 186) 100

 8195 23:54:11.892063  iDelay=191, Bit 5, Center 124 (71 ~ 178) 108

 8196 23:54:11.895741  iDelay=191, Bit 6, Center 138 (87 ~ 190) 104

 8197 23:54:11.901783  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8198 23:54:11.904988  iDelay=191, Bit 8, Center 118 (67 ~ 170) 104

 8199 23:54:11.908431  iDelay=191, Bit 9, Center 116 (67 ~ 166) 100

 8200 23:54:11.911635  iDelay=191, Bit 10, Center 128 (75 ~ 182) 108

 8201 23:54:11.914862  iDelay=191, Bit 11, Center 118 (67 ~ 170) 104

 8202 23:54:11.922074  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8203 23:54:11.925101  iDelay=191, Bit 13, Center 132 (83 ~ 182) 100

 8204 23:54:11.928269  iDelay=191, Bit 14, Center 134 (83 ~ 186) 104

 8205 23:54:11.931531  iDelay=191, Bit 15, Center 134 (87 ~ 182) 96

 8206 23:54:11.931606  ==

 8207 23:54:11.935196  Dram Type= 6, Freq= 0, CH_0, rank 1

 8208 23:54:11.941820  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8209 23:54:11.941905  ==

 8210 23:54:11.941971  DQS Delay:

 8211 23:54:11.945015  DQS0 = 0, DQS1 = 0

 8212 23:54:11.945125  DQM Delay:

 8213 23:54:11.948275  DQM0 = 134, DQM1 = 126

 8214 23:54:11.948365  DQ Delay:

 8215 23:54:11.951524  DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132

 8216 23:54:11.955226  DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140

 8217 23:54:11.958107  DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118

 8218 23:54:11.961185  DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134

 8219 23:54:11.961298  

 8220 23:54:11.961390  

 8221 23:54:11.961475  

 8222 23:54:11.965042  [DramC_TX_OE_Calibration] TA2

 8223 23:54:11.968115  Original DQ_B0 (3 6) =30, OEN = 27

 8224 23:54:11.971188  Original DQ_B1 (3 6) =30, OEN = 27

 8225 23:54:11.974684  24, 0x0, End_B0=24 End_B1=24

 8226 23:54:11.974763  25, 0x0, End_B0=25 End_B1=25

 8227 23:54:11.977717  26, 0x0, End_B0=26 End_B1=26

 8228 23:54:11.981635  27, 0x0, End_B0=27 End_B1=27

 8229 23:54:11.984880  28, 0x0, End_B0=28 End_B1=28

 8230 23:54:11.988289  29, 0x0, End_B0=29 End_B1=29

 8231 23:54:11.988382  30, 0x0, End_B0=30 End_B1=30

 8232 23:54:11.991117  31, 0x4141, End_B0=30 End_B1=30

 8233 23:54:11.994852  Byte0 end_step=30  best_step=27

 8234 23:54:11.997911  Byte1 end_step=30  best_step=27

 8235 23:54:12.001247  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8236 23:54:12.004331  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8237 23:54:12.004422  

 8238 23:54:12.004487  

 8239 23:54:12.011518  [DQSOSCAuto] RK1, (LSB)MR18= 0x2108, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 8240 23:54:12.014622  CH0 RK1: MR19=303, MR18=2108

 8241 23:54:12.021118  CH0_RK1: MR19=0x303, MR18=0x2108, DQSOSC=393, MR23=63, INC=23, DEC=15

 8242 23:54:12.024386  [RxdqsGatingPostProcess] freq 1600

 8243 23:54:12.028299  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8244 23:54:12.031398  best DQS0 dly(2T, 0.5T) = (1, 1)

 8245 23:54:12.035093  best DQS1 dly(2T, 0.5T) = (1, 1)

 8246 23:54:12.038029  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8247 23:54:12.041452  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8248 23:54:12.044785  best DQS0 dly(2T, 0.5T) = (1, 1)

 8249 23:54:12.048007  best DQS1 dly(2T, 0.5T) = (1, 1)

 8250 23:54:12.051184  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8251 23:54:12.054403  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8252 23:54:12.057630  Pre-setting of DQS Precalculation

 8253 23:54:12.060902  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8254 23:54:12.060989  ==

 8255 23:54:12.064199  Dram Type= 6, Freq= 0, CH_1, rank 0

 8256 23:54:12.068208  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8257 23:54:12.071399  ==

 8258 23:54:12.074493  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8259 23:54:12.077784  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8260 23:54:12.084493  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8261 23:54:12.087597  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8262 23:54:12.098409  [CA 0] Center 42 (13~72) winsize 60

 8263 23:54:12.101462  [CA 1] Center 42 (13~72) winsize 60

 8264 23:54:12.104869  [CA 2] Center 39 (10~68) winsize 59

 8265 23:54:12.108150  [CA 3] Center 38 (9~68) winsize 60

 8266 23:54:12.111455  [CA 4] Center 38 (9~68) winsize 60

 8267 23:54:12.114560  [CA 5] Center 37 (8~67) winsize 60

 8268 23:54:12.114640  

 8269 23:54:12.117673  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8270 23:54:12.117753  

 8271 23:54:12.121061  [CATrainingPosCal] consider 1 rank data

 8272 23:54:12.124484  u2DelayCellTimex100 = 290/100 ps

 8273 23:54:12.127759  CA0 delay=42 (13~72),Diff = 5 PI (16 cell)

 8274 23:54:12.134480  CA1 delay=42 (13~72),Diff = 5 PI (16 cell)

 8275 23:54:12.137694  CA2 delay=39 (10~68),Diff = 2 PI (6 cell)

 8276 23:54:12.141280  CA3 delay=38 (9~68),Diff = 1 PI (3 cell)

 8277 23:54:12.144611  CA4 delay=38 (9~68),Diff = 1 PI (3 cell)

 8278 23:54:12.148273  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8279 23:54:12.148369  

 8280 23:54:12.151487  CA PerBit enable=1, Macro0, CA PI delay=37

 8281 23:54:12.151619  

 8282 23:54:12.154551  [CBTSetCACLKResult] CA Dly = 37

 8283 23:54:12.157871  CS Dly: 10 (0~41)

 8284 23:54:12.160970  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8285 23:54:12.164907  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8286 23:54:12.165033  ==

 8287 23:54:12.168032  Dram Type= 6, Freq= 0, CH_1, rank 1

 8288 23:54:12.171168  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8289 23:54:12.171313  ==

 8290 23:54:12.177719  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8291 23:54:12.181493  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8292 23:54:12.187809  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8293 23:54:12.191064  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8294 23:54:12.201965  [CA 0] Center 42 (12~72) winsize 61

 8295 23:54:12.204848  [CA 1] Center 42 (12~72) winsize 61

 8296 23:54:12.208224  [CA 2] Center 38 (9~68) winsize 60

 8297 23:54:12.211655  [CA 3] Center 38 (9~67) winsize 59

 8298 23:54:12.215218  [CA 4] Center 38 (8~68) winsize 61

 8299 23:54:12.217890  [CA 5] Center 37 (8~67) winsize 60

 8300 23:54:12.218025  

 8301 23:54:12.221166  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8302 23:54:12.221304  

 8303 23:54:12.224585  [CATrainingPosCal] consider 2 rank data

 8304 23:54:12.227718  u2DelayCellTimex100 = 290/100 ps

 8305 23:54:12.231646  CA0 delay=42 (13~72),Diff = 5 PI (16 cell)

 8306 23:54:12.237936  CA1 delay=42 (13~72),Diff = 5 PI (16 cell)

 8307 23:54:12.241100  CA2 delay=39 (10~68),Diff = 2 PI (6 cell)

 8308 23:54:12.244726  CA3 delay=38 (9~67),Diff = 1 PI (3 cell)

 8309 23:54:12.248096  CA4 delay=38 (9~68),Diff = 1 PI (3 cell)

 8310 23:54:12.251488  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8311 23:54:12.251615  

 8312 23:54:12.254519  CA PerBit enable=1, Macro0, CA PI delay=37

 8313 23:54:12.254642  

 8314 23:54:12.258170  [CBTSetCACLKResult] CA Dly = 37

 8315 23:54:12.261222  CS Dly: 12 (0~45)

 8316 23:54:12.264720  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8317 23:54:12.267953  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8318 23:54:12.268090  

 8319 23:54:12.271601  ----->DramcWriteLeveling(PI) begin...

 8320 23:54:12.271746  ==

 8321 23:54:12.274730  Dram Type= 6, Freq= 0, CH_1, rank 0

 8322 23:54:12.277913  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8323 23:54:12.281167  ==

 8324 23:54:12.281300  Write leveling (Byte 0): 24 => 24

 8325 23:54:12.284413  Write leveling (Byte 1): 26 => 26

 8326 23:54:12.287710  DramcWriteLeveling(PI) end<-----

 8327 23:54:12.287846  

 8328 23:54:12.287974  ==

 8329 23:54:12.291457  Dram Type= 6, Freq= 0, CH_1, rank 0

 8330 23:54:12.298372  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8331 23:54:12.298521  ==

 8332 23:54:12.301486  [Gating] SW mode calibration

 8333 23:54:12.307848  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8334 23:54:12.311201  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8335 23:54:12.317870   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8336 23:54:12.321371   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8337 23:54:12.324260   1  4  8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 8338 23:54:12.327599   1  4 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)

 8339 23:54:12.334451   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8340 23:54:12.338049   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8341 23:54:12.340927   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8342 23:54:12.348018   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8343 23:54:12.351103   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8344 23:54:12.354179   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8345 23:54:12.360755   1  5  8 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (1 0)

 8346 23:54:12.364042   1  5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 8347 23:54:12.367381   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8348 23:54:12.374620   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8349 23:54:12.377384   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8350 23:54:12.380840   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8351 23:54:12.387422   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8352 23:54:12.391042   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8353 23:54:12.394342   1  6  8 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)

 8354 23:54:12.400990   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8355 23:54:12.404264   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8356 23:54:12.407570   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8357 23:54:12.414207   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8358 23:54:12.417656   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8359 23:54:12.420827   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8360 23:54:12.427597   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8361 23:54:12.430653   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8362 23:54:12.434464   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8363 23:54:12.440797   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8364 23:54:12.444220   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8365 23:54:12.447000   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8366 23:54:12.453782   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8367 23:54:12.457136   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8368 23:54:12.460622   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8369 23:54:12.467247   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8370 23:54:12.470483   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8371 23:54:12.473962   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8372 23:54:12.480222   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8373 23:54:12.483949   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8374 23:54:12.487351   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8375 23:54:12.490957   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8376 23:54:12.497470   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8377 23:54:12.500180   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8378 23:54:12.504082   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8379 23:54:12.510136   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8380 23:54:12.513567  Total UI for P1: 0, mck2ui 16

 8381 23:54:12.517075  best dqsien dly found for B0: ( 1,  9, 10)

 8382 23:54:12.517162  Total UI for P1: 0, mck2ui 16

 8383 23:54:12.523515  best dqsien dly found for B1: ( 1,  9, 10)

 8384 23:54:12.526766  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8385 23:54:12.530801  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8386 23:54:12.530927  

 8387 23:54:12.534171  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8388 23:54:12.537202  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8389 23:54:12.540182  [Gating] SW calibration Done

 8390 23:54:12.540258  ==

 8391 23:54:12.543398  Dram Type= 6, Freq= 0, CH_1, rank 0

 8392 23:54:12.546738  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8393 23:54:12.546814  ==

 8394 23:54:12.550803  RX Vref Scan: 0

 8395 23:54:12.550927  

 8396 23:54:12.551042  RX Vref 0 -> 0, step: 1

 8397 23:54:12.553805  

 8398 23:54:12.553928  RX Delay 0 -> 252, step: 8

 8399 23:54:12.556732  iDelay=200, Bit 0, Center 139 (88 ~ 191) 104

 8400 23:54:12.563449  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8401 23:54:12.566510  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8402 23:54:12.569961  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8403 23:54:12.573594  iDelay=200, Bit 4, Center 135 (88 ~ 183) 96

 8404 23:54:12.576815  iDelay=200, Bit 5, Center 151 (104 ~ 199) 96

 8405 23:54:12.583255  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8406 23:54:12.586480  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8407 23:54:12.590275  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 8408 23:54:12.593179  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8409 23:54:12.597169  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8410 23:54:12.603411  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8411 23:54:12.606773  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8412 23:54:12.609945  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8413 23:54:12.613616  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8414 23:54:12.619778  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8415 23:54:12.619890  ==

 8416 23:54:12.623411  Dram Type= 6, Freq= 0, CH_1, rank 0

 8417 23:54:12.626461  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8418 23:54:12.626568  ==

 8419 23:54:12.626673  DQS Delay:

 8420 23:54:12.629503  DQS0 = 0, DQS1 = 0

 8421 23:54:12.629587  DQM Delay:

 8422 23:54:12.633218  DQM0 = 136, DQM1 = 132

 8423 23:54:12.633298  DQ Delay:

 8424 23:54:12.636412  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8425 23:54:12.639469  DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135

 8426 23:54:12.642871  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127

 8427 23:54:12.646074  DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139

 8428 23:54:12.646152  

 8429 23:54:12.646216  

 8430 23:54:12.650188  ==

 8431 23:54:12.650265  Dram Type= 6, Freq= 0, CH_1, rank 0

 8432 23:54:12.656196  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8433 23:54:12.656308  ==

 8434 23:54:12.656410  

 8435 23:54:12.656489  

 8436 23:54:12.659746  	TX Vref Scan disable

 8437 23:54:12.659855   == TX Byte 0 ==

 8438 23:54:12.662731  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8439 23:54:12.669881  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8440 23:54:12.669962   == TX Byte 1 ==

 8441 23:54:12.672851  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8442 23:54:12.679399  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8443 23:54:12.679506  ==

 8444 23:54:12.682801  Dram Type= 6, Freq= 0, CH_1, rank 0

 8445 23:54:12.685982  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8446 23:54:12.686065  ==

 8447 23:54:12.698920  

 8448 23:54:12.702323  TX Vref early break, caculate TX vref

 8449 23:54:12.705628  TX Vref=16, minBit 11, minWin=22, winSum=382

 8450 23:54:12.708989  TX Vref=18, minBit 1, minWin=23, winSum=390

 8451 23:54:12.712272  TX Vref=20, minBit 1, minWin=24, winSum=404

 8452 23:54:12.715491  TX Vref=22, minBit 6, minWin=24, winSum=410

 8453 23:54:12.718532  TX Vref=24, minBit 0, minWin=25, winSum=418

 8454 23:54:12.725059  TX Vref=26, minBit 0, minWin=26, winSum=433

 8455 23:54:12.728502  TX Vref=28, minBit 0, minWin=25, winSum=431

 8456 23:54:12.731727  TX Vref=30, minBit 2, minWin=25, winSum=422

 8457 23:54:12.735650  TX Vref=32, minBit 0, minWin=25, winSum=420

 8458 23:54:12.738469  TX Vref=34, minBit 0, minWin=24, winSum=404

 8459 23:54:12.745535  [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 26

 8460 23:54:12.745644  

 8461 23:54:12.748901  Final TX Range 0 Vref 26

 8462 23:54:12.748977  

 8463 23:54:12.749039  ==

 8464 23:54:12.752036  Dram Type= 6, Freq= 0, CH_1, rank 0

 8465 23:54:12.755072  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8466 23:54:12.755180  ==

 8467 23:54:12.755281  

 8468 23:54:12.755380  

 8469 23:54:12.758348  	TX Vref Scan disable

 8470 23:54:12.765644  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8471 23:54:12.765739   == TX Byte 0 ==

 8472 23:54:12.768404  u2DelayCellOfst[0]=16 cells (5 PI)

 8473 23:54:12.771913  u2DelayCellOfst[1]=10 cells (3 PI)

 8474 23:54:12.775051  u2DelayCellOfst[2]=0 cells (0 PI)

 8475 23:54:12.778148  u2DelayCellOfst[3]=3 cells (1 PI)

 8476 23:54:12.781537  u2DelayCellOfst[4]=6 cells (2 PI)

 8477 23:54:12.785131  u2DelayCellOfst[5]=16 cells (5 PI)

 8478 23:54:12.788276  u2DelayCellOfst[6]=16 cells (5 PI)

 8479 23:54:12.788398  u2DelayCellOfst[7]=6 cells (2 PI)

 8480 23:54:12.795229  Update DQ  dly =977 (3 ,6, 17)  DQ  OEN =(3 ,3)

 8481 23:54:12.798335  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8482 23:54:12.798437   == TX Byte 1 ==

 8483 23:54:12.802233  u2DelayCellOfst[8]=0 cells (0 PI)

 8484 23:54:12.805093  u2DelayCellOfst[9]=3 cells (1 PI)

 8485 23:54:12.808082  u2DelayCellOfst[10]=13 cells (4 PI)

 8486 23:54:12.811907  u2DelayCellOfst[11]=3 cells (1 PI)

 8487 23:54:12.815380  u2DelayCellOfst[12]=13 cells (4 PI)

 8488 23:54:12.818352  u2DelayCellOfst[13]=13 cells (4 PI)

 8489 23:54:12.821813  u2DelayCellOfst[14]=16 cells (5 PI)

 8490 23:54:12.824875  u2DelayCellOfst[15]=13 cells (4 PI)

 8491 23:54:12.828557  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8492 23:54:12.835056  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8493 23:54:12.835153  DramC Write-DBI on

 8494 23:54:12.835218  ==

 8495 23:54:12.838781  Dram Type= 6, Freq= 0, CH_1, rank 0

 8496 23:54:12.841895  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8497 23:54:12.842045  ==

 8498 23:54:12.845102  

 8499 23:54:12.845208  

 8500 23:54:12.845288  	TX Vref Scan disable

 8501 23:54:12.848375   == TX Byte 0 ==

 8502 23:54:12.852059  Update DQM dly =720 (2 ,6, 16)  DQM OEN =(3 ,3)

 8503 23:54:12.854903   == TX Byte 1 ==

 8504 23:54:12.858234  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8505 23:54:12.858342  DramC Write-DBI off

 8506 23:54:12.861492  

 8507 23:54:12.861598  [DATLAT]

 8508 23:54:12.861707  Freq=1600, CH1 RK0

 8509 23:54:12.861810  

 8510 23:54:12.864924  DATLAT Default: 0xf

 8511 23:54:12.865005  0, 0xFFFF, sum = 0

 8512 23:54:12.868071  1, 0xFFFF, sum = 0

 8513 23:54:12.868143  2, 0xFFFF, sum = 0

 8514 23:54:12.871439  3, 0xFFFF, sum = 0

 8515 23:54:12.871510  4, 0xFFFF, sum = 0

 8516 23:54:12.874716  5, 0xFFFF, sum = 0

 8517 23:54:12.877999  6, 0xFFFF, sum = 0

 8518 23:54:12.878080  7, 0xFFFF, sum = 0

 8519 23:54:12.881621  8, 0xFFFF, sum = 0

 8520 23:54:12.881701  9, 0xFFFF, sum = 0

 8521 23:54:12.885480  10, 0xFFFF, sum = 0

 8522 23:54:12.885554  11, 0xFFFF, sum = 0

 8523 23:54:12.888545  12, 0xFFFF, sum = 0

 8524 23:54:12.888649  13, 0xFFFF, sum = 0

 8525 23:54:12.891771  14, 0x0, sum = 1

 8526 23:54:12.891846  15, 0x0, sum = 2

 8527 23:54:12.895018  16, 0x0, sum = 3

 8528 23:54:12.895095  17, 0x0, sum = 4

 8529 23:54:12.895157  best_step = 15

 8530 23:54:12.898159  

 8531 23:54:12.898230  ==

 8532 23:54:12.901428  Dram Type= 6, Freq= 0, CH_1, rank 0

 8533 23:54:12.905038  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8534 23:54:12.905142  ==

 8535 23:54:12.905232  RX Vref Scan: 1

 8536 23:54:12.905321  

 8537 23:54:12.908539  Set Vref Range= 24 -> 127

 8538 23:54:12.908609  

 8539 23:54:12.911732  RX Vref 24 -> 127, step: 1

 8540 23:54:12.911803  

 8541 23:54:12.914846  RX Delay 27 -> 252, step: 4

 8542 23:54:12.914918  

 8543 23:54:12.918030  Set Vref, RX VrefLevel [Byte0]: 24

 8544 23:54:12.921474                           [Byte1]: 24

 8545 23:54:12.921577  

 8546 23:54:12.924965  Set Vref, RX VrefLevel [Byte0]: 25

 8547 23:54:12.928482                           [Byte1]: 25

 8548 23:54:12.928558  

 8549 23:54:12.931355  Set Vref, RX VrefLevel [Byte0]: 26

 8550 23:54:12.934823                           [Byte1]: 26

 8551 23:54:12.938271  

 8552 23:54:12.938348  Set Vref, RX VrefLevel [Byte0]: 27

 8553 23:54:12.941329                           [Byte1]: 27

 8554 23:54:12.945687  

 8555 23:54:12.945765  Set Vref, RX VrefLevel [Byte0]: 28

 8556 23:54:12.948901                           [Byte1]: 28

 8557 23:54:12.953225  

 8558 23:54:12.953299  Set Vref, RX VrefLevel [Byte0]: 29

 8559 23:54:12.956569                           [Byte1]: 29

 8560 23:54:12.960950  

 8561 23:54:12.961021  Set Vref, RX VrefLevel [Byte0]: 30

 8562 23:54:12.964134                           [Byte1]: 30

 8563 23:54:12.968410  

 8564 23:54:12.968499  Set Vref, RX VrefLevel [Byte0]: 31

 8565 23:54:12.971637                           [Byte1]: 31

 8566 23:54:12.976161  

 8567 23:54:12.976263  Set Vref, RX VrefLevel [Byte0]: 32

 8568 23:54:12.978929                           [Byte1]: 32

 8569 23:54:12.983535  

 8570 23:54:12.983631  Set Vref, RX VrefLevel [Byte0]: 33

 8571 23:54:12.987180                           [Byte1]: 33

 8572 23:54:12.990820  

 8573 23:54:12.990894  Set Vref, RX VrefLevel [Byte0]: 34

 8574 23:54:12.994215                           [Byte1]: 34

 8575 23:54:12.998744  

 8576 23:54:12.998818  Set Vref, RX VrefLevel [Byte0]: 35

 8577 23:54:13.002093                           [Byte1]: 35

 8578 23:54:13.006620  

 8579 23:54:13.006718  Set Vref, RX VrefLevel [Byte0]: 36

 8580 23:54:13.009637                           [Byte1]: 36

 8581 23:54:13.013457  

 8582 23:54:13.013531  Set Vref, RX VrefLevel [Byte0]: 37

 8583 23:54:13.016776                           [Byte1]: 37

 8584 23:54:13.021237  

 8585 23:54:13.021338  Set Vref, RX VrefLevel [Byte0]: 38

 8586 23:54:13.024578                           [Byte1]: 38

 8587 23:54:13.028900  

 8588 23:54:13.028974  Set Vref, RX VrefLevel [Byte0]: 39

 8589 23:54:13.032044                           [Byte1]: 39

 8590 23:54:13.036538  

 8591 23:54:13.036619  Set Vref, RX VrefLevel [Byte0]: 40

 8592 23:54:13.039505                           [Byte1]: 40

 8593 23:54:13.043654  

 8594 23:54:13.043732  Set Vref, RX VrefLevel [Byte0]: 41

 8595 23:54:13.046913                           [Byte1]: 41

 8596 23:54:13.051124  

 8597 23:54:13.051202  Set Vref, RX VrefLevel [Byte0]: 42

 8598 23:54:13.054558                           [Byte1]: 42

 8599 23:54:13.058943  

 8600 23:54:13.059024  Set Vref, RX VrefLevel [Byte0]: 43

 8601 23:54:13.062037                           [Byte1]: 43

 8602 23:54:13.066785  

 8603 23:54:13.066864  Set Vref, RX VrefLevel [Byte0]: 44

 8604 23:54:13.069928                           [Byte1]: 44

 8605 23:54:13.074521  

 8606 23:54:13.074629  Set Vref, RX VrefLevel [Byte0]: 45

 8607 23:54:13.076900                           [Byte1]: 45

 8608 23:54:13.081312  

 8609 23:54:13.081389  Set Vref, RX VrefLevel [Byte0]: 46

 8610 23:54:13.084649                           [Byte1]: 46

 8611 23:54:13.088964  

 8612 23:54:13.089094  Set Vref, RX VrefLevel [Byte0]: 47

 8613 23:54:13.092332                           [Byte1]: 47

 8614 23:54:13.096664  

 8615 23:54:13.096789  Set Vref, RX VrefLevel [Byte0]: 48

 8616 23:54:13.099599                           [Byte1]: 48

 8617 23:54:13.103764  

 8618 23:54:13.103843  Set Vref, RX VrefLevel [Byte0]: 49

 8619 23:54:13.107702                           [Byte1]: 49

 8620 23:54:13.111622  

 8621 23:54:13.111724  Set Vref, RX VrefLevel [Byte0]: 50

 8622 23:54:13.114533                           [Byte1]: 50

 8623 23:54:13.119116  

 8624 23:54:13.119282  Set Vref, RX VrefLevel [Byte0]: 51

 8625 23:54:13.122380                           [Byte1]: 51

 8626 23:54:13.126609  

 8627 23:54:13.126719  Set Vref, RX VrefLevel [Byte0]: 52

 8628 23:54:13.130256                           [Byte1]: 52

 8629 23:54:13.134286  

 8630 23:54:13.134369  Set Vref, RX VrefLevel [Byte0]: 53

 8631 23:54:13.137542                           [Byte1]: 53

 8632 23:54:13.141453  

 8633 23:54:13.141535  Set Vref, RX VrefLevel [Byte0]: 54

 8634 23:54:13.144748                           [Byte1]: 54

 8635 23:54:13.149270  

 8636 23:54:13.149358  Set Vref, RX VrefLevel [Byte0]: 55

 8637 23:54:13.152437                           [Byte1]: 55

 8638 23:54:13.156428  

 8639 23:54:13.156513  Set Vref, RX VrefLevel [Byte0]: 56

 8640 23:54:13.159903                           [Byte1]: 56

 8641 23:54:13.164083  

 8642 23:54:13.164168  Set Vref, RX VrefLevel [Byte0]: 57

 8643 23:54:13.167676                           [Byte1]: 57

 8644 23:54:13.171726  

 8645 23:54:13.171809  Set Vref, RX VrefLevel [Byte0]: 58

 8646 23:54:13.174718                           [Byte1]: 58

 8647 23:54:13.179283  

 8648 23:54:13.179399  Set Vref, RX VrefLevel [Byte0]: 59

 8649 23:54:13.182760                           [Byte1]: 59

 8650 23:54:13.186954  

 8651 23:54:13.187068  Set Vref, RX VrefLevel [Byte0]: 60

 8652 23:54:13.189880                           [Byte1]: 60

 8653 23:54:13.194403  

 8654 23:54:13.194488  Set Vref, RX VrefLevel [Byte0]: 61

 8655 23:54:13.197485                           [Byte1]: 61

 8656 23:54:13.201981  

 8657 23:54:13.202071  Set Vref, RX VrefLevel [Byte0]: 62

 8658 23:54:13.205400                           [Byte1]: 62

 8659 23:54:13.209335  

 8660 23:54:13.209432  Set Vref, RX VrefLevel [Byte0]: 63

 8661 23:54:13.212708                           [Byte1]: 63

 8662 23:54:13.216870  

 8663 23:54:13.216944  Set Vref, RX VrefLevel [Byte0]: 64

 8664 23:54:13.220311                           [Byte1]: 64

 8665 23:54:13.224772  

 8666 23:54:13.224850  Set Vref, RX VrefLevel [Byte0]: 65

 8667 23:54:13.228208                           [Byte1]: 65

 8668 23:54:13.232180  

 8669 23:54:13.232263  Set Vref, RX VrefLevel [Byte0]: 66

 8670 23:54:13.235387                           [Byte1]: 66

 8671 23:54:13.239667  

 8672 23:54:13.239750  Set Vref, RX VrefLevel [Byte0]: 67

 8673 23:54:13.242924                           [Byte1]: 67

 8674 23:54:13.246859  

 8675 23:54:13.246943  Set Vref, RX VrefLevel [Byte0]: 68

 8676 23:54:13.250917                           [Byte1]: 68

 8677 23:54:13.254687  

 8678 23:54:13.254771  Set Vref, RX VrefLevel [Byte0]: 69

 8679 23:54:13.257836                           [Byte1]: 69

 8680 23:54:13.262372  

 8681 23:54:13.262455  Set Vref, RX VrefLevel [Byte0]: 70

 8682 23:54:13.265778                           [Byte1]: 70

 8683 23:54:13.269605  

 8684 23:54:13.269719  Set Vref, RX VrefLevel [Byte0]: 71

 8685 23:54:13.272715                           [Byte1]: 71

 8686 23:54:13.277218  

 8687 23:54:13.277312  Set Vref, RX VrefLevel [Byte0]: 72

 8688 23:54:13.280398                           [Byte1]: 72

 8689 23:54:13.284952  

 8690 23:54:13.285036  Set Vref, RX VrefLevel [Byte0]: 73

 8691 23:54:13.288351                           [Byte1]: 73

 8692 23:54:13.292740  

 8693 23:54:13.292823  Set Vref, RX VrefLevel [Byte0]: 74

 8694 23:54:13.295445                           [Byte1]: 74

 8695 23:54:13.300139  

 8696 23:54:13.300223  Set Vref, RX VrefLevel [Byte0]: 75

 8697 23:54:13.302881                           [Byte1]: 75

 8698 23:54:13.307701  

 8699 23:54:13.307783  Final RX Vref Byte 0 = 57 to rank0

 8700 23:54:13.310612  Final RX Vref Byte 1 = 54 to rank0

 8701 23:54:13.313689  Final RX Vref Byte 0 = 57 to rank1

 8702 23:54:13.317942  Final RX Vref Byte 1 = 54 to rank1==

 8703 23:54:13.320802  Dram Type= 6, Freq= 0, CH_1, rank 0

 8704 23:54:13.323883  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8705 23:54:13.327268  ==

 8706 23:54:13.327344  DQS Delay:

 8707 23:54:13.327406  DQS0 = 0, DQS1 = 0

 8708 23:54:13.330433  DQM Delay:

 8709 23:54:13.330536  DQM0 = 134, DQM1 = 131

 8710 23:54:13.334465  DQ Delay:

 8711 23:54:13.337480  DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130

 8712 23:54:13.340935  DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132

 8713 23:54:13.344516  DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124

 8714 23:54:13.347460  DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140

 8715 23:54:13.347563  

 8716 23:54:13.347662  

 8717 23:54:13.347760  

 8718 23:54:13.350762  [DramC_TX_OE_Calibration] TA2

 8719 23:54:13.353987  Original DQ_B0 (3 6) =30, OEN = 27

 8720 23:54:13.357228  Original DQ_B1 (3 6) =30, OEN = 27

 8721 23:54:13.360699  24, 0x0, End_B0=24 End_B1=24

 8722 23:54:13.360792  25, 0x0, End_B0=25 End_B1=25

 8723 23:54:13.364146  26, 0x0, End_B0=26 End_B1=26

 8724 23:54:13.367383  27, 0x0, End_B0=27 End_B1=27

 8725 23:54:13.370402  28, 0x0, End_B0=28 End_B1=28

 8726 23:54:13.370489  29, 0x0, End_B0=29 End_B1=29

 8727 23:54:13.373713  30, 0x0, End_B0=30 End_B1=30

 8728 23:54:13.376968  31, 0x4141, End_B0=30 End_B1=30

 8729 23:54:13.380700  Byte0 end_step=30  best_step=27

 8730 23:54:13.383988  Byte1 end_step=30  best_step=27

 8731 23:54:13.387318  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8732 23:54:13.390538  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8733 23:54:13.390649  

 8734 23:54:13.390750  

 8735 23:54:13.396929  [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 8736 23:54:13.400644  CH1 RK0: MR19=303, MR18=1927

 8737 23:54:13.407258  CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16

 8738 23:54:13.407339  

 8739 23:54:13.410165  ----->DramcWriteLeveling(PI) begin...

 8740 23:54:13.410240  ==

 8741 23:54:13.413987  Dram Type= 6, Freq= 0, CH_1, rank 1

 8742 23:54:13.417106  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8743 23:54:13.417213  ==

 8744 23:54:13.419874  Write leveling (Byte 0): 27 => 27

 8745 23:54:13.423293  Write leveling (Byte 1): 27 => 27

 8746 23:54:13.426632  DramcWriteLeveling(PI) end<-----

 8747 23:54:13.426706  

 8748 23:54:13.426768  ==

 8749 23:54:13.430242  Dram Type= 6, Freq= 0, CH_1, rank 1

 8750 23:54:13.433416  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8751 23:54:13.433501  ==

 8752 23:54:13.436687  [Gating] SW mode calibration

 8753 23:54:13.442906  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8754 23:54:13.449889  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8755 23:54:13.453154   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8756 23:54:13.459560   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8757 23:54:13.462958   1  4  8 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)

 8758 23:54:13.466551   1  4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)

 8759 23:54:13.472821   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8760 23:54:13.476577   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8761 23:54:13.479871   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8762 23:54:13.483031   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8763 23:54:13.489536   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8764 23:54:13.492768   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8765 23:54:13.496052   1  5  8 | B1->B0 | 2f2f 3434 | 0 1 | (0 1) (1 1)

 8766 23:54:13.503293   1  5 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (1 0)

 8767 23:54:13.506481   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8768 23:54:13.509728   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8769 23:54:13.516278   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8770 23:54:13.519582   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8771 23:54:13.522943   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8772 23:54:13.529309   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8773 23:54:13.532748   1  6  8 | B1->B0 | 3737 2323 | 0 0 | (0 0) (0 0)

 8774 23:54:13.536443   1  6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)

 8775 23:54:13.543022   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8776 23:54:13.545959   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8777 23:54:13.549211   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8778 23:54:13.555910   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8779 23:54:13.559247   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8780 23:54:13.562695   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8781 23:54:13.569129   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8782 23:54:13.573199   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8783 23:54:13.575991   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8784 23:54:13.582366   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8785 23:54:13.585989   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8786 23:54:13.589626   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8787 23:54:13.596301   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8788 23:54:13.599086   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8789 23:54:13.602725   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8790 23:54:13.609170   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8791 23:54:13.612516   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8792 23:54:13.615764   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8793 23:54:13.622291   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8794 23:54:13.625600   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8795 23:54:13.629206   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8796 23:54:13.632870   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8797 23:54:13.639368   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8798 23:54:13.642659   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8799 23:54:13.645651  Total UI for P1: 0, mck2ui 16

 8800 23:54:13.648906  best dqsien dly found for B1: ( 1,  9,  6)

 8801 23:54:13.652318   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8802 23:54:13.659379   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8803 23:54:13.659486  Total UI for P1: 0, mck2ui 16

 8804 23:54:13.665793  best dqsien dly found for B0: ( 1,  9, 14)

 8805 23:54:13.669197  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 8806 23:54:13.672626  best DQS1 dly(MCK, UI, PI) = (1, 9, 6)

 8807 23:54:13.672732  

 8808 23:54:13.676013  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8809 23:54:13.679446  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8810 23:54:13.682905  [Gating] SW calibration Done

 8811 23:54:13.683014  ==

 8812 23:54:13.685905  Dram Type= 6, Freq= 0, CH_1, rank 1

 8813 23:54:13.689068  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8814 23:54:13.689176  ==

 8815 23:54:13.692662  RX Vref Scan: 0

 8816 23:54:13.692768  

 8817 23:54:13.692862  RX Vref 0 -> 0, step: 1

 8818 23:54:13.692962  

 8819 23:54:13.696143  RX Delay 0 -> 252, step: 8

 8820 23:54:13.699266  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8821 23:54:13.705920  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8822 23:54:13.709800  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8823 23:54:13.712670  iDelay=208, Bit 3, Center 131 (80 ~ 183) 104

 8824 23:54:13.715961  iDelay=208, Bit 4, Center 131 (80 ~ 183) 104

 8825 23:54:13.719352  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8826 23:54:13.722629  iDelay=208, Bit 6, Center 147 (96 ~ 199) 104

 8827 23:54:13.729445  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8828 23:54:13.732725  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8829 23:54:13.736167  iDelay=208, Bit 9, Center 123 (72 ~ 175) 104

 8830 23:54:13.739665  iDelay=208, Bit 10, Center 135 (80 ~ 191) 112

 8831 23:54:13.742750  iDelay=208, Bit 11, Center 127 (72 ~ 183) 112

 8832 23:54:13.749220  iDelay=208, Bit 12, Center 143 (88 ~ 199) 112

 8833 23:54:13.752452  iDelay=208, Bit 13, Center 143 (88 ~ 199) 112

 8834 23:54:13.755653  iDelay=208, Bit 14, Center 139 (88 ~ 191) 104

 8835 23:54:13.759389  iDelay=208, Bit 15, Center 143 (88 ~ 199) 112

 8836 23:54:13.759491  ==

 8837 23:54:13.762880  Dram Type= 6, Freq= 0, CH_1, rank 1

 8838 23:54:13.769229  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8839 23:54:13.769312  ==

 8840 23:54:13.769396  DQS Delay:

 8841 23:54:13.772348  DQS0 = 0, DQS1 = 0

 8842 23:54:13.772432  DQM Delay:

 8843 23:54:13.772511  DQM0 = 136, DQM1 = 134

 8844 23:54:13.776162  DQ Delay:

 8845 23:54:13.779353  DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131

 8846 23:54:13.782369  DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135

 8847 23:54:13.785914  DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127

 8848 23:54:13.789522  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143

 8849 23:54:13.789614  

 8850 23:54:13.789698  

 8851 23:54:13.789775  ==

 8852 23:54:13.792642  Dram Type= 6, Freq= 0, CH_1, rank 1

 8853 23:54:13.795985  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8854 23:54:13.799204  ==

 8855 23:54:13.799313  

 8856 23:54:13.799407  

 8857 23:54:13.799496  	TX Vref Scan disable

 8858 23:54:13.802529   == TX Byte 0 ==

 8859 23:54:13.805858  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8860 23:54:13.808930  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8861 23:54:13.812171   == TX Byte 1 ==

 8862 23:54:13.815901  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8863 23:54:13.818870  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8864 23:54:13.822450  ==

 8865 23:54:13.825907  Dram Type= 6, Freq= 0, CH_1, rank 1

 8866 23:54:13.828863  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8867 23:54:13.828986  ==

 8868 23:54:13.842143  

 8869 23:54:13.845109  TX Vref early break, caculate TX vref

 8870 23:54:13.848967  TX Vref=16, minBit 2, minWin=23, winSum=388

 8871 23:54:13.852286  TX Vref=18, minBit 1, minWin=23, winSum=393

 8872 23:54:13.855507  TX Vref=20, minBit 0, minWin=24, winSum=404

 8873 23:54:13.858680  TX Vref=22, minBit 0, minWin=25, winSum=412

 8874 23:54:13.862010  TX Vref=24, minBit 1, minWin=25, winSum=416

 8875 23:54:13.868569  TX Vref=26, minBit 0, minWin=25, winSum=426

 8876 23:54:13.871749  TX Vref=28, minBit 6, minWin=25, winSum=427

 8877 23:54:13.875273  TX Vref=30, minBit 6, minWin=25, winSum=424

 8878 23:54:13.878409  TX Vref=32, minBit 0, minWin=25, winSum=413

 8879 23:54:13.881855  TX Vref=34, minBit 0, minWin=24, winSum=406

 8880 23:54:13.885415  TX Vref=36, minBit 0, minWin=23, winSum=399

 8881 23:54:13.891666  [TxChooseVref] Worse bit 6, Min win 25, Win sum 427, Final Vref 28

 8882 23:54:13.891792  

 8883 23:54:13.895295  Final TX Range 0 Vref 28

 8884 23:54:13.895417  

 8885 23:54:13.895529  ==

 8886 23:54:13.898964  Dram Type= 6, Freq= 0, CH_1, rank 1

 8887 23:54:13.901785  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8888 23:54:13.901888  ==

 8889 23:54:13.901979  

 8890 23:54:13.902067  

 8891 23:54:13.905055  	TX Vref Scan disable

 8892 23:54:13.911637  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8893 23:54:13.911719   == TX Byte 0 ==

 8894 23:54:13.915212  u2DelayCellOfst[0]=16 cells (5 PI)

 8895 23:54:13.918546  u2DelayCellOfst[1]=10 cells (3 PI)

 8896 23:54:13.921610  u2DelayCellOfst[2]=0 cells (0 PI)

 8897 23:54:13.925439  u2DelayCellOfst[3]=6 cells (2 PI)

 8898 23:54:13.928710  u2DelayCellOfst[4]=6 cells (2 PI)

 8899 23:54:13.931974  u2DelayCellOfst[5]=16 cells (5 PI)

 8900 23:54:13.934995  u2DelayCellOfst[6]=16 cells (5 PI)

 8901 23:54:13.938552  u2DelayCellOfst[7]=3 cells (1 PI)

 8902 23:54:13.941443  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8903 23:54:13.944894  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8904 23:54:13.948678   == TX Byte 1 ==

 8905 23:54:13.948808  u2DelayCellOfst[8]=0 cells (0 PI)

 8906 23:54:13.951968  u2DelayCellOfst[9]=6 cells (2 PI)

 8907 23:54:13.955092  u2DelayCellOfst[10]=13 cells (4 PI)

 8908 23:54:13.958705  u2DelayCellOfst[11]=6 cells (2 PI)

 8909 23:54:13.961684  u2DelayCellOfst[12]=16 cells (5 PI)

 8910 23:54:13.964790  u2DelayCellOfst[13]=20 cells (6 PI)

 8911 23:54:13.968250  u2DelayCellOfst[14]=16 cells (5 PI)

 8912 23:54:13.971292  u2DelayCellOfst[15]=20 cells (6 PI)

 8913 23:54:13.975032  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8914 23:54:13.981289  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8915 23:54:13.981372  DramC Write-DBI on

 8916 23:54:13.981438  ==

 8917 23:54:13.984659  Dram Type= 6, Freq= 0, CH_1, rank 1

 8918 23:54:13.991812  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8919 23:54:13.991896  ==

 8920 23:54:13.991960  

 8921 23:54:13.992019  

 8922 23:54:13.992076  	TX Vref Scan disable

 8923 23:54:13.995434   == TX Byte 0 ==

 8924 23:54:13.998541  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8925 23:54:14.001708   == TX Byte 1 ==

 8926 23:54:14.005236  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8927 23:54:14.005361  DramC Write-DBI off

 8928 23:54:14.008590  

 8929 23:54:14.008710  [DATLAT]

 8930 23:54:14.008821  Freq=1600, CH1 RK1

 8931 23:54:14.008927  

 8932 23:54:14.011821  DATLAT Default: 0xf

 8933 23:54:14.011944  0, 0xFFFF, sum = 0

 8934 23:54:14.015537  1, 0xFFFF, sum = 0

 8935 23:54:14.015666  2, 0xFFFF, sum = 0

 8936 23:54:14.018606  3, 0xFFFF, sum = 0

 8937 23:54:14.021519  4, 0xFFFF, sum = 0

 8938 23:54:14.021643  5, 0xFFFF, sum = 0

 8939 23:54:14.025445  6, 0xFFFF, sum = 0

 8940 23:54:14.025564  7, 0xFFFF, sum = 0

 8941 23:54:14.028603  8, 0xFFFF, sum = 0

 8942 23:54:14.028688  9, 0xFFFF, sum = 0

 8943 23:54:14.031949  10, 0xFFFF, sum = 0

 8944 23:54:14.032032  11, 0xFFFF, sum = 0

 8945 23:54:14.035232  12, 0xFFFF, sum = 0

 8946 23:54:14.035346  13, 0xFFFF, sum = 0

 8947 23:54:14.038497  14, 0x0, sum = 1

 8948 23:54:14.038611  15, 0x0, sum = 2

 8949 23:54:14.041811  16, 0x0, sum = 3

 8950 23:54:14.041886  17, 0x0, sum = 4

 8951 23:54:14.044834  best_step = 15

 8952 23:54:14.044911  

 8953 23:54:14.044974  ==

 8954 23:54:14.048454  Dram Type= 6, Freq= 0, CH_1, rank 1

 8955 23:54:14.051553  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8956 23:54:14.051637  ==

 8957 23:54:14.051701  RX Vref Scan: 0

 8958 23:54:14.055453  

 8959 23:54:14.055566  RX Vref 0 -> 0, step: 1

 8960 23:54:14.055657  

 8961 23:54:14.058221  RX Delay 19 -> 252, step: 4

 8962 23:54:14.061403  iDelay=195, Bit 0, Center 138 (91 ~ 186) 96

 8963 23:54:14.068537  iDelay=195, Bit 1, Center 130 (83 ~ 178) 96

 8964 23:54:14.071503  iDelay=195, Bit 2, Center 124 (75 ~ 174) 100

 8965 23:54:14.074801  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 8966 23:54:14.077921  iDelay=195, Bit 4, Center 130 (83 ~ 178) 96

 8967 23:54:14.081745  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 8968 23:54:14.084616  iDelay=195, Bit 6, Center 144 (95 ~ 194) 100

 8969 23:54:14.091102  iDelay=195, Bit 7, Center 134 (83 ~ 186) 104

 8970 23:54:14.095098  iDelay=195, Bit 8, Center 118 (67 ~ 170) 104

 8971 23:54:14.097885  iDelay=195, Bit 9, Center 120 (67 ~ 174) 108

 8972 23:54:14.101674  iDelay=195, Bit 10, Center 132 (83 ~ 182) 100

 8973 23:54:14.104771  iDelay=195, Bit 11, Center 126 (75 ~ 178) 104

 8974 23:54:14.111195  iDelay=195, Bit 12, Center 140 (87 ~ 194) 108

 8975 23:54:14.114366  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 8976 23:54:14.118099  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 8977 23:54:14.121161  iDelay=195, Bit 15, Center 138 (87 ~ 190) 104

 8978 23:54:14.121268  ==

 8979 23:54:14.124882  Dram Type= 6, Freq= 0, CH_1, rank 1

 8980 23:54:14.131072  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8981 23:54:14.131185  ==

 8982 23:54:14.131278  DQS Delay:

 8983 23:54:14.134723  DQS0 = 0, DQS1 = 0

 8984 23:54:14.134829  DQM Delay:

 8985 23:54:14.138038  DQM0 = 134, DQM1 = 131

 8986 23:54:14.138149  DQ Delay:

 8987 23:54:14.141624  DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =130

 8988 23:54:14.144518  DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134

 8989 23:54:14.147716  DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =126

 8990 23:54:14.151457  DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138

 8991 23:54:14.151540  

 8992 23:54:14.151604  

 8993 23:54:14.151664  

 8994 23:54:14.154745  [DramC_TX_OE_Calibration] TA2

 8995 23:54:14.158299  Original DQ_B0 (3 6) =30, OEN = 27

 8996 23:54:14.161313  Original DQ_B1 (3 6) =30, OEN = 27

 8997 23:54:14.164808  24, 0x0, End_B0=24 End_B1=24

 8998 23:54:14.164887  25, 0x0, End_B0=25 End_B1=25

 8999 23:54:14.167874  26, 0x0, End_B0=26 End_B1=26

 9000 23:54:14.171145  27, 0x0, End_B0=27 End_B1=27

 9001 23:54:14.174250  28, 0x0, End_B0=28 End_B1=28

 9002 23:54:14.178080  29, 0x0, End_B0=29 End_B1=29

 9003 23:54:14.178158  30, 0x0, End_B0=30 End_B1=30

 9004 23:54:14.181403  31, 0x4141, End_B0=30 End_B1=30

 9005 23:54:14.184643  Byte0 end_step=30  best_step=27

 9006 23:54:14.188123  Byte1 end_step=30  best_step=27

 9007 23:54:14.191096  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9008 23:54:14.194382  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9009 23:54:14.194492  

 9010 23:54:14.194587  

 9011 23:54:14.201249  [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps

 9012 23:54:14.204757  CH1 RK1: MR19=303, MR18=2207

 9013 23:54:14.211154  CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16

 9014 23:54:14.214256  [RxdqsGatingPostProcess] freq 1600

 9015 23:54:14.217529  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9016 23:54:14.221044  best DQS0 dly(2T, 0.5T) = (1, 1)

 9017 23:54:14.224012  best DQS1 dly(2T, 0.5T) = (1, 1)

 9018 23:54:14.227844  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9019 23:54:14.231135  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9020 23:54:14.234134  best DQS0 dly(2T, 0.5T) = (1, 1)

 9021 23:54:14.237616  best DQS1 dly(2T, 0.5T) = (1, 1)

 9022 23:54:14.241254  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9023 23:54:14.244189  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9024 23:54:14.247422  Pre-setting of DQS Precalculation

 9025 23:54:14.250632  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9026 23:54:14.258011  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9027 23:54:14.267750  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9028 23:54:14.267834  

 9029 23:54:14.267898  

 9030 23:54:14.267957  [Calibration Summary] 3200 Mbps

 9031 23:54:14.270650  CH 0, Rank 0

 9032 23:54:14.270725  SW Impedance     : PASS

 9033 23:54:14.274442  DUTY Scan        : NO K

 9034 23:54:14.277733  ZQ Calibration   : PASS

 9035 23:54:14.277810  Jitter Meter     : NO K

 9036 23:54:14.280961  CBT Training     : PASS

 9037 23:54:14.284129  Write leveling   : PASS

 9038 23:54:14.284236  RX DQS gating    : PASS

 9039 23:54:14.287327  RX DQ/DQS(RDDQC) : PASS

 9040 23:54:14.290649  TX DQ/DQS        : PASS

 9041 23:54:14.290737  RX DATLAT        : PASS

 9042 23:54:14.294191  RX DQ/DQS(Engine): PASS

 9043 23:54:14.298076  TX OE            : PASS

 9044 23:54:14.298155  All Pass.

 9045 23:54:14.298219  

 9046 23:54:14.298282  CH 0, Rank 1

 9047 23:54:14.300923  SW Impedance     : PASS

 9048 23:54:14.304305  DUTY Scan        : NO K

 9049 23:54:14.304423  ZQ Calibration   : PASS

 9050 23:54:14.307872  Jitter Meter     : NO K

 9051 23:54:14.310856  CBT Training     : PASS

 9052 23:54:14.310965  Write leveling   : PASS

 9053 23:54:14.314117  RX DQS gating    : PASS

 9054 23:54:14.317163  RX DQ/DQS(RDDQC) : PASS

 9055 23:54:14.317269  TX DQ/DQS        : PASS

 9056 23:54:14.320415  RX DATLAT        : PASS

 9057 23:54:14.320498  RX DQ/DQS(Engine): PASS

 9058 23:54:14.324066  TX OE            : PASS

 9059 23:54:14.324142  All Pass.

 9060 23:54:14.324208  

 9061 23:54:14.327016  CH 1, Rank 0

 9062 23:54:14.327089  SW Impedance     : PASS

 9063 23:54:14.330484  DUTY Scan        : NO K

 9064 23:54:14.333688  ZQ Calibration   : PASS

 9065 23:54:14.333768  Jitter Meter     : NO K

 9066 23:54:14.336874  CBT Training     : PASS

 9067 23:54:14.340521  Write leveling   : PASS

 9068 23:54:14.340597  RX DQS gating    : PASS

 9069 23:54:14.344062  RX DQ/DQS(RDDQC) : PASS

 9070 23:54:14.347187  TX DQ/DQS        : PASS

 9071 23:54:14.347262  RX DATLAT        : PASS

 9072 23:54:14.350660  RX DQ/DQS(Engine): PASS

 9073 23:54:14.353797  TX OE            : PASS

 9074 23:54:14.353890  All Pass.

 9075 23:54:14.353954  

 9076 23:54:14.354014  CH 1, Rank 1

 9077 23:54:14.356871  SW Impedance     : PASS

 9078 23:54:14.360368  DUTY Scan        : NO K

 9079 23:54:14.360450  ZQ Calibration   : PASS

 9080 23:54:14.363634  Jitter Meter     : NO K

 9081 23:54:14.367337  CBT Training     : PASS

 9082 23:54:14.367418  Write leveling   : PASS

 9083 23:54:14.370436  RX DQS gating    : PASS

 9084 23:54:14.373487  RX DQ/DQS(RDDQC) : PASS

 9085 23:54:14.373599  TX DQ/DQS        : PASS

 9086 23:54:14.376842  RX DATLAT        : PASS

 9087 23:54:14.376945  RX DQ/DQS(Engine): PASS

 9088 23:54:14.380157  TX OE            : PASS

 9089 23:54:14.380238  All Pass.

 9090 23:54:14.380301  

 9091 23:54:14.383442  DramC Write-DBI on

 9092 23:54:14.387001  	PER_BANK_REFRESH: Hybrid Mode

 9093 23:54:14.387079  TX_TRACKING: ON

 9094 23:54:14.397050  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9095 23:54:14.403907  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9096 23:54:14.413681  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9097 23:54:14.416882  [FAST_K] Save calibration result to emmc

 9098 23:54:14.416961  sync common calibartion params.

 9099 23:54:14.420103  sync cbt_mode0:1, 1:1

 9100 23:54:14.423378  dram_init: ddr_geometry: 2

 9101 23:54:14.426648  dram_init: ddr_geometry: 2

 9102 23:54:14.426725  dram_init: ddr_geometry: 2

 9103 23:54:14.429882  0:dram_rank_size:100000000

 9104 23:54:14.433246  1:dram_rank_size:100000000

 9105 23:54:14.436486  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9106 23:54:14.439764  DFS_SHUFFLE_HW_MODE: ON

 9107 23:54:14.443286  dramc_set_vcore_voltage set vcore to 725000

 9108 23:54:14.446591  Read voltage for 1600, 0

 9109 23:54:14.446668  Vio18 = 0

 9110 23:54:14.449675  Vcore = 725000

 9111 23:54:14.449767  Vdram = 0

 9112 23:54:14.449831  Vddq = 0

 9113 23:54:14.449894  Vmddr = 0

 9114 23:54:14.452950  switch to 3200 Mbps bootup

 9115 23:54:14.456576  [DramcRunTimeConfig]

 9116 23:54:14.456657  PHYPLL

 9117 23:54:14.459653  DPM_CONTROL_AFTERK: ON

 9118 23:54:14.459727  PER_BANK_REFRESH: ON

 9119 23:54:14.463064  REFRESH_OVERHEAD_REDUCTION: ON

 9120 23:54:14.466361  CMD_PICG_NEW_MODE: OFF

 9121 23:54:14.466435  XRTWTW_NEW_MODE: ON

 9122 23:54:14.469636  XRTRTR_NEW_MODE: ON

 9123 23:54:14.469708  TX_TRACKING: ON

 9124 23:54:14.472872  RDSEL_TRACKING: OFF

 9125 23:54:14.476633  DQS Precalculation for DVFS: ON

 9126 23:54:14.476722  RX_TRACKING: OFF

 9127 23:54:14.479675  HW_GATING DBG: ON

 9128 23:54:14.479756  ZQCS_ENABLE_LP4: ON

 9129 23:54:14.483059  RX_PICG_NEW_MODE: ON

 9130 23:54:14.483135  TX_PICG_NEW_MODE: ON

 9131 23:54:14.486395  ENABLE_RX_DCM_DPHY: ON

 9132 23:54:14.489378  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9133 23:54:14.492984  DUMMY_READ_FOR_TRACKING: OFF

 9134 23:54:14.493060  !!! SPM_CONTROL_AFTERK: OFF

 9135 23:54:14.496317  !!! SPM could not control APHY

 9136 23:54:14.499458  IMPEDANCE_TRACKING: ON

 9137 23:54:14.499555  TEMP_SENSOR: ON

 9138 23:54:14.503004  HW_SAVE_FOR_SR: OFF

 9139 23:54:14.506145  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9140 23:54:14.509267  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9141 23:54:14.509344  Read ODT Tracking: ON

 9142 23:54:14.512954  Refresh Rate DeBounce: ON

 9143 23:54:14.516142  DFS_NO_QUEUE_FLUSH: ON

 9144 23:54:14.519686  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9145 23:54:14.519766  ENABLE_DFS_RUNTIME_MRW: OFF

 9146 23:54:14.522666  DDR_RESERVE_NEW_MODE: ON

 9147 23:54:14.525819  MR_CBT_SWITCH_FREQ: ON

 9148 23:54:14.525897  =========================

 9149 23:54:14.546161  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9150 23:54:14.549190  dram_init: ddr_geometry: 2

 9151 23:54:14.567838  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9152 23:54:14.571197  dram_init: dram init end (result: 0)

 9153 23:54:14.577608  DRAM-K: Full calibration passed in 24402 msecs

 9154 23:54:14.581400  MRC: failed to locate region type 0.

 9155 23:54:14.581484  DRAM rank0 size:0x100000000,

 9156 23:54:14.584423  DRAM rank1 size=0x100000000

 9157 23:54:14.594509  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9158 23:54:14.601136  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9159 23:54:14.607744  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9160 23:54:14.614445  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9161 23:54:14.617778  DRAM rank0 size:0x100000000,

 9162 23:54:14.620909  DRAM rank1 size=0x100000000

 9163 23:54:14.620989  CBMEM:

 9164 23:54:14.624454  IMD: root @ 0xfffff000 254 entries.

 9165 23:54:14.627622  IMD: root @ 0xffffec00 62 entries.

 9166 23:54:14.631002  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9167 23:54:14.634242  WARNING: RO_VPD is uninitialized or empty.

 9168 23:54:14.640543  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9169 23:54:14.647928  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9170 23:54:14.660368  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9171 23:54:14.671969  BS: romstage times (exec / console): total (unknown) / 23940 ms

 9172 23:54:14.672084  

 9173 23:54:14.672181  

 9174 23:54:14.681641  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9175 23:54:14.685417  ARM64: Exception handlers installed.

 9176 23:54:14.688638  ARM64: Testing exception

 9177 23:54:14.692043  ARM64: Done test exception

 9178 23:54:14.692124  Enumerating buses...

 9179 23:54:14.695269  Show all devs... Before device enumeration.

 9180 23:54:14.698512  Root Device: enabled 1

 9181 23:54:14.701624  CPU_CLUSTER: 0: enabled 1

 9182 23:54:14.701706  CPU: 00: enabled 1

 9183 23:54:14.705781  Compare with tree...

 9184 23:54:14.705862  Root Device: enabled 1

 9185 23:54:14.708912   CPU_CLUSTER: 0: enabled 1

 9186 23:54:14.712249    CPU: 00: enabled 1

 9187 23:54:14.712330  Root Device scanning...

 9188 23:54:14.715224  scan_static_bus for Root Device

 9189 23:54:14.718727  CPU_CLUSTER: 0 enabled

 9190 23:54:14.721966  scan_static_bus for Root Device done

 9191 23:54:14.724922  scan_bus: bus Root Device finished in 8 msecs

 9192 23:54:14.725002  done

 9193 23:54:14.731923  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9194 23:54:14.735224  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9195 23:54:14.741864  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9196 23:54:14.745371  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9197 23:54:14.748594  Allocating resources...

 9198 23:54:14.748679  Reading resources...

 9199 23:54:14.755239  Root Device read_resources bus 0 link: 0

 9200 23:54:14.755323  DRAM rank0 size:0x100000000,

 9201 23:54:14.758647  DRAM rank1 size=0x100000000

 9202 23:54:14.761901  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9203 23:54:14.765099  CPU: 00 missing read_resources

 9204 23:54:14.768271  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9205 23:54:14.775011  Root Device read_resources bus 0 link: 0 done

 9206 23:54:14.775094  Done reading resources.

 9207 23:54:14.781273  Show resources in subtree (Root Device)...After reading.

 9208 23:54:14.785042   Root Device child on link 0 CPU_CLUSTER: 0

 9209 23:54:14.788104    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9210 23:54:14.798075    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9211 23:54:14.798160     CPU: 00

 9212 23:54:14.801412  Root Device assign_resources, bus 0 link: 0

 9213 23:54:14.804773  CPU_CLUSTER: 0 missing set_resources

 9214 23:54:14.807976  Root Device assign_resources, bus 0 link: 0 done

 9215 23:54:14.811561  Done setting resources.

 9216 23:54:14.818287  Show resources in subtree (Root Device)...After assigning values.

 9217 23:54:14.821442   Root Device child on link 0 CPU_CLUSTER: 0

 9218 23:54:14.824724    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9219 23:54:14.834726    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9220 23:54:14.834815     CPU: 00

 9221 23:54:14.838203  Done allocating resources.

 9222 23:54:14.841193  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9223 23:54:14.844609  Enabling resources...

 9224 23:54:14.844683  done.

 9225 23:54:14.850939  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9226 23:54:14.851019  Initializing devices...

 9227 23:54:14.854373  Root Device init

 9228 23:54:14.854453  init hardware done!

 9229 23:54:14.857696  0x00000018: ctrlr->caps

 9230 23:54:14.861467  52.000 MHz: ctrlr->f_max

 9231 23:54:14.861600  0.400 MHz: ctrlr->f_min

 9232 23:54:14.864472  0x40ff8080: ctrlr->voltages

 9233 23:54:14.864584  sclk: 390625

 9234 23:54:14.868139  Bus Width = 1

 9235 23:54:14.868223  sclk: 390625

 9236 23:54:14.871186  Bus Width = 1

 9237 23:54:14.871261  Early init status = 3

 9238 23:54:14.877839  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9239 23:54:14.880937  in-header: 03 fc 00 00 01 00 00 00 

 9240 23:54:14.884620  in-data: 00 

 9241 23:54:14.887777  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9242 23:54:14.892471  in-header: 03 fd 00 00 00 00 00 00 

 9243 23:54:14.896015  in-data: 

 9244 23:54:14.899128  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9245 23:54:14.903230  in-header: 03 fc 00 00 01 00 00 00 

 9246 23:54:14.906848  in-data: 00 

 9247 23:54:14.910052  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9248 23:54:14.915440  in-header: 03 fd 00 00 00 00 00 00 

 9249 23:54:14.918648  in-data: 

 9250 23:54:14.922277  [SSUSB] Setting up USB HOST controller...

 9251 23:54:14.925452  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9252 23:54:14.928817  [SSUSB] phy power-on done.

 9253 23:54:14.932284  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9254 23:54:14.938910  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9255 23:54:14.942027  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9256 23:54:14.948957  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9257 23:54:14.955465  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9258 23:54:14.962011  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9259 23:54:14.968561  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9260 23:54:14.974946  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9261 23:54:14.978911  SPM: binary array size = 0x9dc

 9262 23:54:14.981822  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9263 23:54:14.988266  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9264 23:54:14.995392  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9265 23:54:14.998569  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9266 23:54:15.005172  configure_display: Starting display init

 9267 23:54:15.038594  anx7625_power_on_init: Init interface.

 9268 23:54:15.042256  anx7625_disable_pd_protocol: Disabled PD feature.

 9269 23:54:15.045645  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9270 23:54:15.073440  anx7625_start_dp_work: Secure OCM version=00

 9271 23:54:15.076518  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9272 23:54:15.091345  sp_tx_get_edid_block: EDID Block = 1

 9273 23:54:15.193933  Extracted contents:

 9274 23:54:15.197247  header:          00 ff ff ff ff ff ff 00

 9275 23:54:15.200828  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9276 23:54:15.203905  version:         01 04

 9277 23:54:15.207136  basic params:    95 1f 11 78 0a

 9278 23:54:15.210583  chroma info:     76 90 94 55 54 90 27 21 50 54

 9279 23:54:15.214157  established:     00 00 00

 9280 23:54:15.220253  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9281 23:54:15.224076  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9282 23:54:15.230131  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9283 23:54:15.236740  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9284 23:54:15.243305  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9285 23:54:15.246982  extensions:      00

 9286 23:54:15.247067  checksum:        fb

 9287 23:54:15.247134  

 9288 23:54:15.250591  Manufacturer: IVO Model 57d Serial Number 0

 9289 23:54:15.253926  Made week 0 of 2020

 9290 23:54:15.254019  EDID version: 1.4

 9291 23:54:15.257067  Digital display

 9292 23:54:15.260327  6 bits per primary color channel

 9293 23:54:15.260432  DisplayPort interface

 9294 23:54:15.263575  Maximum image size: 31 cm x 17 cm

 9295 23:54:15.266669  Gamma: 220%

 9296 23:54:15.266751  Check DPMS levels

 9297 23:54:15.270400  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9298 23:54:15.273527  First detailed timing is preferred timing

 9299 23:54:15.276672  Established timings supported:

 9300 23:54:15.280320  Standard timings supported:

 9301 23:54:15.280432  Detailed timings

 9302 23:54:15.287098  Hex of detail: 383680a07038204018303c0035ae10000019

 9303 23:54:15.289949  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9304 23:54:15.297015                 0780 0798 07c8 0820 hborder 0

 9305 23:54:15.300398                 0438 043b 0447 0458 vborder 0

 9306 23:54:15.303607                 -hsync -vsync

 9307 23:54:15.303684  Did detailed timing

 9308 23:54:15.306929  Hex of detail: 000000000000000000000000000000000000

 9309 23:54:15.310235  Manufacturer-specified data, tag 0

 9310 23:54:15.316965  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9311 23:54:15.317047  ASCII string: InfoVision

 9312 23:54:15.323784  Hex of detail: 000000fe00523134304e574635205248200a

 9313 23:54:15.326689  ASCII string: R140NWF5 RH 

 9314 23:54:15.326766  Checksum

 9315 23:54:15.326829  Checksum: 0xfb (valid)

 9316 23:54:15.333545  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9317 23:54:15.337221  DSI data_rate: 832800000 bps

 9318 23:54:15.340355  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9319 23:54:15.343657  anx7625_parse_edid: pixelclock(138800).

 9320 23:54:15.350311   hactive(1920), hsync(48), hfp(24), hbp(88)

 9321 23:54:15.353661   vactive(1080), vsync(12), vfp(3), vbp(17)

 9322 23:54:15.357238  anx7625_dsi_config: config dsi.

 9323 23:54:15.363455  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9324 23:54:15.376234  anx7625_dsi_config: success to config DSI

 9325 23:54:15.379712  anx7625_dp_start: MIPI phy setup OK.

 9326 23:54:15.382851  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9327 23:54:15.386224  mtk_ddp_mode_set invalid vrefresh 60

 9328 23:54:15.389576  main_disp_path_setup

 9329 23:54:15.389654  ovl_layer_smi_id_en

 9330 23:54:15.392656  ovl_layer_smi_id_en

 9331 23:54:15.392743  ccorr_config

 9332 23:54:15.392809  aal_config

 9333 23:54:15.395895  gamma_config

 9334 23:54:15.395980  postmask_config

 9335 23:54:15.398961  dither_config

 9336 23:54:15.403113  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9337 23:54:15.409364                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9338 23:54:15.412435  Root Device init finished in 555 msecs

 9339 23:54:15.416002  CPU_CLUSTER: 0 init

 9340 23:54:15.422726  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9341 23:54:15.425435  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9342 23:54:15.429060  APU_MBOX 0x190000b0 = 0x10001

 9343 23:54:15.432483  APU_MBOX 0x190001b0 = 0x10001

 9344 23:54:15.435385  APU_MBOX 0x190005b0 = 0x10001

 9345 23:54:15.439000  APU_MBOX 0x190006b0 = 0x10001

 9346 23:54:15.442033  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9347 23:54:15.455032  read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps

 9348 23:54:15.467132  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9349 23:54:15.474221  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9350 23:54:15.485870  read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps

 9351 23:54:15.495045  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9352 23:54:15.497730  CPU_CLUSTER: 0 init finished in 81 msecs

 9353 23:54:15.501720  Devices initialized

 9354 23:54:15.504484  Show all devs... After init.

 9355 23:54:15.504561  Root Device: enabled 1

 9356 23:54:15.508542  CPU_CLUSTER: 0: enabled 1

 9357 23:54:15.510999  CPU: 00: enabled 1

 9358 23:54:15.514964  BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms

 9359 23:54:15.518173  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9360 23:54:15.521491  ELOG: NV offset 0x57f000 size 0x1000

 9361 23:54:15.527950  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9362 23:54:15.534518  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9363 23:54:15.538766  ELOG: Event(17) added with size 13 at 2024-05-29 23:49:36 UTC

 9364 23:54:15.544158  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9365 23:54:15.547969  in-header: 03 18 00 00 2c 00 00 00 

 9366 23:54:15.557998  in-data: 47 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9367 23:54:15.564832  ELOG: Event(A1) added with size 10 at 2024-05-29 23:49:36 UTC

 9368 23:54:15.570999  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9369 23:54:15.577747  ELOG: Event(A0) added with size 9 at 2024-05-29 23:49:36 UTC

 9370 23:54:15.580844  elog_add_boot_reason: Logged dev mode boot

 9371 23:54:15.584211  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9372 23:54:15.587866  Finalize devices...

 9373 23:54:15.587950  Devices finalized

 9374 23:54:15.594183  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9375 23:54:15.597227  Writing coreboot table at 0xffe64000

 9376 23:54:15.600704   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9377 23:54:15.604256   1. 0000000040000000-00000000400fffff: RAM

 9378 23:54:15.610778   2. 0000000040100000-000000004032afff: RAMSTAGE

 9379 23:54:15.614588   3. 000000004032b000-00000000545fffff: RAM

 9380 23:54:15.617753   4. 0000000054600000-000000005465ffff: BL31

 9381 23:54:15.620952   5. 0000000054660000-00000000ffe63fff: RAM

 9382 23:54:15.627789   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9383 23:54:15.630890   7. 0000000100000000-000000023fffffff: RAM

 9384 23:54:15.633935  Passing 5 GPIOs to payload:

 9385 23:54:15.638157              NAME |       PORT | POLARITY |     VALUE

 9386 23:54:15.641053          EC in RW | 0x000000aa |      low | undefined

 9387 23:54:15.647578      EC interrupt | 0x00000005 |      low | undefined

 9388 23:54:15.650730     TPM interrupt | 0x000000ab |     high | undefined

 9389 23:54:15.657593    SD card detect | 0x00000011 |     high | undefined

 9390 23:54:15.660790    speaker enable | 0x00000093 |     high | undefined

 9391 23:54:15.664781  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9392 23:54:15.667832  in-header: 03 f9 00 00 02 00 00 00 

 9393 23:54:15.671127  in-data: 02 00 

 9394 23:54:15.671211  ADC[4]: Raw value=904726 ID=7

 9395 23:54:15.674297  ADC[3]: Raw value=213072 ID=1

 9396 23:54:15.677573  RAM Code: 0x71

 9397 23:54:15.677657  ADC[6]: Raw value=75701 ID=0

 9398 23:54:15.680746  ADC[5]: Raw value=212703 ID=1

 9399 23:54:15.684545  SKU Code: 0x1

 9400 23:54:15.687770  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7651

 9401 23:54:15.691012  coreboot table: 964 bytes.

 9402 23:54:15.694256  IMD ROOT    0. 0xfffff000 0x00001000

 9403 23:54:15.697497  IMD SMALL   1. 0xffffe000 0x00001000

 9404 23:54:15.700590  RO MCACHE   2. 0xffffc000 0x00001104

 9405 23:54:15.704243  CONSOLE     3. 0xfff7c000 0x00080000

 9406 23:54:15.707364  FMAP        4. 0xfff7b000 0x00000452

 9407 23:54:15.710816  TIME STAMP  5. 0xfff7a000 0x00000910

 9408 23:54:15.714089  VBOOT WORK  6. 0xfff66000 0x00014000

 9409 23:54:15.717410  RAMOOPS     7. 0xffe66000 0x00100000

 9410 23:54:15.720808  COREBOOT    8. 0xffe64000 0x00002000

 9411 23:54:15.720890  IMD small region:

 9412 23:54:15.723938    IMD ROOT    0. 0xffffec00 0x00000400

 9413 23:54:15.730519    VPD         1. 0xffffeb80 0x0000006c

 9414 23:54:15.733998    MMC STATUS  2. 0xffffeb60 0x00000004

 9415 23:54:15.737593  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9416 23:54:15.740836  Probing TPM:  done!

 9417 23:54:15.743995  Connected to device vid:did:rid of 1ae0:0028:00

 9418 23:54:15.754019  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9419 23:54:15.757900  Initialized TPM device CR50 revision 0

 9420 23:54:15.760837  Checking cr50 for pending updates

 9421 23:54:15.765287  Reading cr50 TPM mode

 9422 23:54:15.773749  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9423 23:54:15.780290  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9424 23:54:15.820734  read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps

 9425 23:54:15.823527  Checking segment from ROM address 0x40100000

 9426 23:54:15.827452  Checking segment from ROM address 0x4010001c

 9427 23:54:15.833513  Loading segment from ROM address 0x40100000

 9428 23:54:15.833600    code (compression=0)

 9429 23:54:15.840283    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9430 23:54:15.850361  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9431 23:54:15.850493  it's not compressed!

 9432 23:54:15.857195  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9433 23:54:15.860210  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9434 23:54:15.881019  Loading segment from ROM address 0x4010001c

 9435 23:54:15.881158    Entry Point 0x80000000

 9436 23:54:15.884064  Loaded segments

 9437 23:54:15.887370  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9438 23:54:15.893913  Jumping to boot code at 0x80000000(0xffe64000)

 9439 23:54:15.900847  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9440 23:54:15.907285  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9441 23:54:15.915077  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9442 23:54:15.918693  Checking segment from ROM address 0x40100000

 9443 23:54:15.921870  Checking segment from ROM address 0x4010001c

 9444 23:54:15.928675  Loading segment from ROM address 0x40100000

 9445 23:54:15.928803    code (compression=1)

 9446 23:54:15.935622    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9447 23:54:15.945430  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9448 23:54:15.945516  using LZMA

 9449 23:54:15.953737  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9450 23:54:15.960083  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9451 23:54:15.963517  Loading segment from ROM address 0x4010001c

 9452 23:54:15.963602    Entry Point 0x54601000

 9453 23:54:15.967085  Loaded segments

 9454 23:54:15.970124  NOTICE:  MT8192 bl31_setup

 9455 23:54:15.976857  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9456 23:54:15.980322  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9457 23:54:15.983937  WARNING: region 0:

 9458 23:54:15.987179  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9459 23:54:15.987305  WARNING: region 1:

 9460 23:54:15.993583  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9461 23:54:15.997117  WARNING: region 2:

 9462 23:54:16.000302  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9463 23:54:16.003765  WARNING: region 3:

 9464 23:54:16.006884  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9465 23:54:16.010686  WARNING: region 4:

 9466 23:54:16.017250  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9467 23:54:16.017381  WARNING: region 5:

 9468 23:54:16.020408  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9469 23:54:16.023507  WARNING: region 6:

 9470 23:54:16.027014  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9471 23:54:16.029952  WARNING: region 7:

 9472 23:54:16.033665  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9473 23:54:16.040036  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9474 23:54:16.043302  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9475 23:54:16.046581  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9476 23:54:16.053786  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9477 23:54:16.056938  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9478 23:54:16.060104  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9479 23:54:16.067157  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9480 23:54:16.070419  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9481 23:54:16.076929  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9482 23:54:16.080530  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9483 23:54:16.083568  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9484 23:54:16.090376  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9485 23:54:16.093677  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9486 23:54:16.096865  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9487 23:54:16.103607  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9488 23:54:16.107150  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9489 23:54:16.113727  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9490 23:54:16.116860  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9491 23:54:16.120260  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9492 23:54:16.127403  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9493 23:54:16.130583  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9494 23:54:16.134004  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9495 23:54:16.140480  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9496 23:54:16.144100  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9497 23:54:16.150695  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9498 23:54:16.154245  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9499 23:54:16.157147  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9500 23:54:16.164093  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9501 23:54:16.167848  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9502 23:54:16.170756  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9503 23:54:16.177610  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9504 23:54:16.180461  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9505 23:54:16.183723  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9506 23:54:16.191256  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9507 23:54:16.194343  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9508 23:54:16.197204  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9509 23:54:16.200464  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9510 23:54:16.207447  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9511 23:54:16.210745  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9512 23:54:16.213975  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9513 23:54:16.217390  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9514 23:54:16.223839  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9515 23:54:16.226995  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9516 23:54:16.230952  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9517 23:54:16.233956  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9518 23:54:16.240690  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9519 23:54:16.244054  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9520 23:54:16.247582  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9521 23:54:16.254339  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9522 23:54:16.257700  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9523 23:54:16.260697  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9524 23:54:16.267657  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9525 23:54:16.270734  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9526 23:54:16.277422  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9527 23:54:16.280914  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9528 23:54:16.287387  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9529 23:54:16.290619  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9530 23:54:16.293951  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9531 23:54:16.301392  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9532 23:54:16.304246  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9533 23:54:16.311208  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9534 23:54:16.314069  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9535 23:54:16.321276  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9536 23:54:16.324403  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9537 23:54:16.327980  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9538 23:54:16.334254  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9539 23:54:16.337954  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9540 23:54:16.344377  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9541 23:54:16.347571  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9542 23:54:16.354105  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9543 23:54:16.357331  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9544 23:54:16.361035  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9545 23:54:16.367739  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9546 23:54:16.371280  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9547 23:54:16.377323  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9548 23:54:16.381030  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9549 23:54:16.387375  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9550 23:54:16.390802  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9551 23:54:16.397579  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9552 23:54:16.401263  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9553 23:54:16.404492  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9554 23:54:16.410741  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9555 23:54:16.414352  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9556 23:54:16.421334  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9557 23:54:16.424588  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9558 23:54:16.428120  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9559 23:54:16.434818  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9560 23:54:16.437847  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9561 23:54:16.444391  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9562 23:54:16.447590  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9563 23:54:16.454494  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9564 23:54:16.458030  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9565 23:54:16.461276  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9566 23:54:16.467624  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9567 23:54:16.471382  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9568 23:54:16.477882  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9569 23:54:16.481136  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9570 23:54:16.484475  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9571 23:54:16.491543  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9572 23:54:16.494757  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9573 23:54:16.497894  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9574 23:54:16.501056  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9575 23:54:16.507649  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9576 23:54:16.511226  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9577 23:54:16.517993  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9578 23:54:16.521211  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9579 23:54:16.524517  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9580 23:54:16.531807  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9581 23:54:16.534619  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9582 23:54:16.541246  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9583 23:54:16.545163  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9584 23:54:16.548153  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9585 23:54:16.554941  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9586 23:54:16.558408  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9587 23:54:16.564774  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9588 23:54:16.568271  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9589 23:54:16.571365  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9590 23:54:16.574712  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9591 23:54:16.582256  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9592 23:54:16.585213  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9593 23:54:16.588250  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9594 23:54:16.591432  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9595 23:54:16.598647  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9596 23:54:16.601359  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9597 23:54:16.605243  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9598 23:54:16.611883  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9599 23:54:16.615469  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9600 23:54:16.618628  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9601 23:54:16.625126  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9602 23:54:16.628672  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9603 23:54:16.635209  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9604 23:54:16.638473  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9605 23:54:16.641766  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9606 23:54:16.648440  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9607 23:54:16.651910  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9608 23:54:16.658753  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9609 23:54:16.662045  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9610 23:54:16.665138  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9611 23:54:16.672315  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9612 23:54:16.675023  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9613 23:54:16.678707  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9614 23:54:16.685976  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9615 23:54:16.688596  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9616 23:54:16.695286  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9617 23:54:16.698417  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9618 23:54:16.701980  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9619 23:54:16.708334  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9620 23:54:16.712200  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9621 23:54:16.718932  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9622 23:54:16.722389  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9623 23:54:16.725345  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9624 23:54:16.731987  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9625 23:54:16.735491  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9626 23:54:16.739029  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9627 23:54:16.745171  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9628 23:54:16.748578  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9629 23:54:16.755831  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9630 23:54:16.758719  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9631 23:54:16.762406  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9632 23:54:16.769067  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9633 23:54:16.772316  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9634 23:54:16.778565  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9635 23:54:16.781829  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9636 23:54:16.785042  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9637 23:54:16.792133  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9638 23:54:16.794985  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9639 23:54:16.798686  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9640 23:54:16.804945  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9641 23:54:16.808595  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9642 23:54:16.815284  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9643 23:54:16.818200  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9644 23:54:16.824796  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9645 23:54:16.828284  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9646 23:54:16.831475  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9647 23:54:16.838083  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9648 23:54:16.841344  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9649 23:54:16.845013  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9650 23:54:16.851637  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9651 23:54:16.854692  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9652 23:54:16.861414  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9653 23:54:16.864692  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9654 23:54:16.867942  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9655 23:54:16.874623  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9656 23:54:16.878418  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9657 23:54:16.884601  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9658 23:54:16.887964  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9659 23:54:16.890964  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9660 23:54:16.898154  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9661 23:54:16.901335  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9662 23:54:16.907847  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9663 23:54:16.911425  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9664 23:54:16.914349  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9665 23:54:16.921376  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9666 23:54:16.924738  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9667 23:54:16.930875  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9668 23:54:16.934647  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9669 23:54:16.938125  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9670 23:54:16.944487  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9671 23:54:16.948038  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9672 23:54:16.955056  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9673 23:54:16.957598  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9674 23:54:16.964468  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9675 23:54:16.967916  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9676 23:54:16.971074  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9677 23:54:16.977765  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9678 23:54:16.980894  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9679 23:54:16.987567  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9680 23:54:16.991354  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9681 23:54:16.994382  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9682 23:54:17.000846  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9683 23:54:17.004798  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9684 23:54:17.011157  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9685 23:54:17.014413  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9686 23:54:17.017923  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9687 23:54:17.024180  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9688 23:54:17.027376  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9689 23:54:17.034385  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9690 23:54:17.037673  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9691 23:54:17.044117  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9692 23:54:17.047823  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9693 23:54:17.051092  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9694 23:54:17.057284  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9695 23:54:17.060745  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9696 23:54:17.067251  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9697 23:54:17.070698  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9698 23:54:17.074424  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9699 23:54:17.081062  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9700 23:54:17.083908  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9701 23:54:17.090761  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9702 23:54:17.094310  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9703 23:54:17.097908  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9704 23:54:17.100520  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9705 23:54:17.107289  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9706 23:54:17.111268  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9707 23:54:17.114204  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9708 23:54:17.120843  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9709 23:54:17.124125  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9710 23:54:17.127533  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9711 23:54:17.133984  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9712 23:54:17.137281  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9713 23:54:17.140880  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9714 23:54:17.147163  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9715 23:54:17.150488  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9716 23:54:17.153779  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9717 23:54:17.160207  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9718 23:54:17.163564  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9719 23:54:17.170662  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9720 23:54:17.173881  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9721 23:54:17.177145  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9722 23:54:17.183424  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9723 23:54:17.187289  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9724 23:54:17.193465  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9725 23:54:17.196941  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9726 23:54:17.200410  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9727 23:54:17.206992  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9728 23:54:17.210288  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9729 23:54:17.213529  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9730 23:54:17.220082  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9731 23:54:17.223148  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9732 23:54:17.226522  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9733 23:54:17.233444  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9734 23:54:17.236753  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9735 23:54:17.243204  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9736 23:54:17.246551  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9737 23:54:17.250036  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9738 23:54:17.256596  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9739 23:54:17.260229  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9740 23:54:17.263506  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9741 23:54:17.269639  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9742 23:54:17.273312  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9743 23:54:17.276423  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9744 23:54:17.279949  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9745 23:54:17.283186  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9746 23:54:17.289927  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9747 23:54:17.293385  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9748 23:54:17.296972  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9749 23:54:17.300011  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9750 23:54:17.306724  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9751 23:54:17.309775  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9752 23:54:17.313051  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9753 23:54:17.320131  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9754 23:54:17.322783  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9755 23:54:17.326856  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9756 23:54:17.333104  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9757 23:54:17.336182  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9758 23:54:17.342668  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9759 23:54:17.346109  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9760 23:54:17.349973  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9761 23:54:17.356032  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9762 23:54:17.360179  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9763 23:54:17.363262  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9764 23:54:17.369461  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9765 23:54:17.372806  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9766 23:54:17.379788  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9767 23:54:17.383037  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9768 23:54:17.389709  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9769 23:54:17.393013  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9770 23:54:17.396276  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9771 23:54:17.403087  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9772 23:54:17.406198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9773 23:54:17.412818  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9774 23:54:17.416193  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9775 23:54:17.419552  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9776 23:54:17.426300  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9777 23:54:17.429893  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9778 23:54:17.436413  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9779 23:54:17.439423  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9780 23:54:17.443101  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9781 23:54:17.449970  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9782 23:54:17.453154  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9783 23:54:17.459602  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9784 23:54:17.462800  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9785 23:54:17.466265  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9786 23:54:17.472745  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9787 23:54:17.476071  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9788 23:54:17.482680  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9789 23:54:17.485839  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9790 23:54:17.489146  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9791 23:54:17.495691  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9792 23:54:17.499093  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9793 23:54:17.505839  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9794 23:54:17.509089  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9795 23:54:17.512317  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9796 23:54:17.519056  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9797 23:54:17.522128  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9798 23:54:17.529002  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9799 23:54:17.532246  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9800 23:54:17.539008  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9801 23:54:17.542296  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9802 23:54:17.545698  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9803 23:54:17.552198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9804 23:54:17.555612  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9805 23:54:17.562504  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9806 23:54:17.565713  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9807 23:54:17.568846  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9808 23:54:17.575863  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9809 23:54:17.578926  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9810 23:54:17.585365  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9811 23:54:17.589422  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9812 23:54:17.592280  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9813 23:54:17.598875  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9814 23:54:17.601840  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9815 23:54:17.608916  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9816 23:54:17.612087  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9817 23:54:17.618970  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9818 23:54:17.622326  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9819 23:54:17.625574  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9820 23:54:17.631917  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9821 23:54:17.635540  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9822 23:54:17.642004  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9823 23:54:17.645418  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9824 23:54:17.648688  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9825 23:54:17.655075  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9826 23:54:17.658995  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9827 23:54:17.665287  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9828 23:54:17.668433  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9829 23:54:17.671811  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9830 23:54:17.678472  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9831 23:54:17.682182  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9832 23:54:17.688269  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9833 23:54:17.691874  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9834 23:54:17.698453  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9835 23:54:17.702084  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9836 23:54:17.704900  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9837 23:54:17.712079  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9838 23:54:17.715429  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9839 23:54:17.721973  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9840 23:54:17.725197  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9841 23:54:17.731473  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9842 23:54:17.735245  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9843 23:54:17.738264  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9844 23:54:17.744902  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9845 23:54:17.748446  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9846 23:54:17.754902  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9847 23:54:17.758226  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9848 23:54:17.765218  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9849 23:54:17.768261  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9850 23:54:17.772167  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9851 23:54:17.778345  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9852 23:54:17.781703  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9853 23:54:17.788105  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9854 23:54:17.792042  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9855 23:54:17.798712  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9856 23:54:17.801772  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9857 23:54:17.808463  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9858 23:54:17.811822  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9859 23:54:17.815104  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9860 23:54:17.821874  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9861 23:54:17.824915  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9862 23:54:17.831150  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9863 23:54:17.834864  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9864 23:54:17.841498  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9865 23:54:17.844497  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9866 23:54:17.847922  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9867 23:54:17.854637  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9868 23:54:17.858294  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9869 23:54:17.864642  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9870 23:54:17.868161  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9871 23:54:17.874827  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9872 23:54:17.878144  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9873 23:54:17.884731  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9874 23:54:17.887654  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9875 23:54:17.891249  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9876 23:54:17.897581  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9877 23:54:17.901443  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9878 23:54:17.907934  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9879 23:54:17.910960  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9880 23:54:17.918030  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9881 23:54:17.921217  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9882 23:54:17.924578  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9883 23:54:17.931469  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9884 23:54:17.934519  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9885 23:54:17.941075  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9886 23:54:17.944524  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9887 23:54:17.951276  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9888 23:54:17.954235  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9889 23:54:17.961125  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9890 23:54:17.964328  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9891 23:54:17.970949  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9892 23:54:17.974294  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9893 23:54:17.981631  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9894 23:54:17.984298  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9895 23:54:17.990974  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9896 23:54:17.994166  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9897 23:54:18.000969  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9898 23:54:18.004487  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9899 23:54:18.010852  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9900 23:54:18.014233  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9901 23:54:18.021275  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9902 23:54:18.024251  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9903 23:54:18.031428  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9904 23:54:18.033996  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9905 23:54:18.041152  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9906 23:54:18.044390  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9907 23:54:18.047570  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9908 23:54:18.050719  INFO:    [APUAPC] vio 0

 9909 23:54:18.057418  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9910 23:54:18.060537  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9911 23:54:18.064013  INFO:    [APUAPC] D0_APC_0: 0x400510

 9912 23:54:18.067375  INFO:    [APUAPC] D0_APC_1: 0x0

 9913 23:54:18.070552  INFO:    [APUAPC] D0_APC_2: 0x1540

 9914 23:54:18.074124  INFO:    [APUAPC] D0_APC_3: 0x0

 9915 23:54:18.077121  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9916 23:54:18.080839  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9917 23:54:18.084006  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9918 23:54:18.087016  INFO:    [APUAPC] D1_APC_3: 0x0

 9919 23:54:18.090624  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9920 23:54:18.093943  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9921 23:54:18.097165  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9922 23:54:18.100231  INFO:    [APUAPC] D2_APC_3: 0x0

 9923 23:54:18.103457  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9924 23:54:18.107203  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9925 23:54:18.110272  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9926 23:54:18.110353  INFO:    [APUAPC] D3_APC_3: 0x0

 9927 23:54:18.113773  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9928 23:54:18.120309  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9929 23:54:18.123658  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9930 23:54:18.123743  INFO:    [APUAPC] D4_APC_3: 0x0

 9931 23:54:18.126922  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9932 23:54:18.130092  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9933 23:54:18.133517  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9934 23:54:18.137169  INFO:    [APUAPC] D5_APC_3: 0x0

 9935 23:54:18.140412  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9936 23:54:18.144115  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9937 23:54:18.147081  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9938 23:54:18.150293  INFO:    [APUAPC] D6_APC_3: 0x0

 9939 23:54:18.153464  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9940 23:54:18.157424  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9941 23:54:18.160740  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9942 23:54:18.163971  INFO:    [APUAPC] D7_APC_3: 0x0

 9943 23:54:18.167091  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9944 23:54:18.170266  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9945 23:54:18.173578  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9946 23:54:18.177002  INFO:    [APUAPC] D8_APC_3: 0x0

 9947 23:54:18.180384  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9948 23:54:18.184035  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9949 23:54:18.187084  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9950 23:54:18.190667  INFO:    [APUAPC] D9_APC_3: 0x0

 9951 23:54:18.193174  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9952 23:54:18.196560  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9953 23:54:18.200017  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9954 23:54:18.203216  INFO:    [APUAPC] D10_APC_3: 0x0

 9955 23:54:18.206503  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9956 23:54:18.209826  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9957 23:54:18.213482  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9958 23:54:18.216459  INFO:    [APUAPC] D11_APC_3: 0x0

 9959 23:54:18.220215  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9960 23:54:18.223462  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9961 23:54:18.226624  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9962 23:54:18.230183  INFO:    [APUAPC] D12_APC_3: 0x0

 9963 23:54:18.233309  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9964 23:54:18.236721  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9965 23:54:18.240156  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9966 23:54:18.242959  INFO:    [APUAPC] D13_APC_3: 0x0

 9967 23:54:18.246547  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9968 23:54:18.249750  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9969 23:54:18.253381  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9970 23:54:18.256392  INFO:    [APUAPC] D14_APC_3: 0x0

 9971 23:54:18.259662  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9972 23:54:18.263154  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9973 23:54:18.266555  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9974 23:54:18.269958  INFO:    [APUAPC] D15_APC_3: 0x0

 9975 23:54:18.273257  INFO:    [APUAPC] APC_CON: 0x4

 9976 23:54:18.276620  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9977 23:54:18.279554  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9978 23:54:18.283009  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9979 23:54:18.286096  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9980 23:54:18.286227  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9981 23:54:18.289668  INFO:    [NOCDAPC] D2_APC_1: 0xfff

 9982 23:54:18.293121  INFO:    [NOCDAPC] D3_APC_0: 0x0

 9983 23:54:18.296634  INFO:    [NOCDAPC] D3_APC_1: 0xfff

 9984 23:54:18.299664  INFO:    [NOCDAPC] D4_APC_0: 0x0

 9985 23:54:18.302721  INFO:    [NOCDAPC] D4_APC_1: 0xfff

 9986 23:54:18.306285  INFO:    [NOCDAPC] D5_APC_0: 0x0

 9987 23:54:18.309909  INFO:    [NOCDAPC] D5_APC_1: 0xfff

 9988 23:54:18.313014  INFO:    [NOCDAPC] D6_APC_0: 0x0

 9989 23:54:18.316584  INFO:    [NOCDAPC] D6_APC_1: 0xfff

 9990 23:54:18.316662  INFO:    [NOCDAPC] D7_APC_0: 0x0

 9991 23:54:18.319746  INFO:    [NOCDAPC] D7_APC_1: 0xfff

 9992 23:54:18.323319  INFO:    [NOCDAPC] D8_APC_0: 0x0

 9993 23:54:18.326623  INFO:    [NOCDAPC] D8_APC_1: 0xfff

 9994 23:54:18.329749  INFO:    [NOCDAPC] D9_APC_0: 0x0

 9995 23:54:18.332943  INFO:    [NOCDAPC] D9_APC_1: 0xfff

 9996 23:54:18.336292  INFO:    [NOCDAPC] D10_APC_0: 0x0

 9997 23:54:18.339608  INFO:    [NOCDAPC] D10_APC_1: 0xfff

 9998 23:54:18.342802  INFO:    [NOCDAPC] D11_APC_0: 0x0

 9999 23:54:18.345956  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10000 23:54:18.349136  INFO:    [NOCDAPC] D12_APC_0: 0x0

10001 23:54:18.352453  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10002 23:54:18.355796  INFO:    [NOCDAPC] D13_APC_0: 0x0

10003 23:54:18.359962  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10004 23:54:18.360042  INFO:    [NOCDAPC] D14_APC_0: 0x0

10005 23:54:18.362377  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10006 23:54:18.365912  INFO:    [NOCDAPC] D15_APC_0: 0x0

10007 23:54:18.369821  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10008 23:54:18.372577  INFO:    [NOCDAPC] APC_CON: 0x4

10009 23:54:18.375978  INFO:    [APUAPC] set_apusys_apc done

10010 23:54:18.379405  INFO:    [DEVAPC] devapc_init done

10011 23:54:18.382460  INFO:    GICv3 without legacy support detected.

10012 23:54:18.389530  INFO:    ARM GICv3 driver initialized in EL3

10013 23:54:18.392998  INFO:    Maximum SPI INTID supported: 639

10014 23:54:18.395984  INFO:    BL31: Initializing runtime services

10015 23:54:18.402484  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10016 23:54:18.402602  INFO:    SPM: enable CPC mode

10017 23:54:18.409322  INFO:    mcdi ready for mcusys-off-idle and system suspend

10018 23:54:18.412598  INFO:    BL31: Preparing for EL3 exit to normal world

10019 23:54:18.416276  INFO:    Entry point address = 0x80000000

10020 23:54:18.419406  INFO:    SPSR = 0x8

10021 23:54:18.425233  

10022 23:54:18.425360  

10023 23:54:18.425472  

10024 23:54:18.428526  Starting depthcharge on Spherion...

10025 23:54:18.428638  

10026 23:54:18.428732  Wipe memory regions:

10027 23:54:18.428821  

10028 23:54:18.429650  end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10029 23:54:18.429779  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10030 23:54:18.429900  Setting prompt string to ['asurada:']
10031 23:54:18.430014  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10032 23:54:18.431926  	[0x00000040000000, 0x00000054600000)

10033 23:54:18.554246  

10034 23:54:18.554407  	[0x00000054660000, 0x00000080000000)

10035 23:54:18.814407  

10036 23:54:18.814549  	[0x000000821a7280, 0x000000ffe64000)

10037 23:54:19.559546  

10038 23:54:19.559693  	[0x00000100000000, 0x00000240000000)

10039 23:54:21.449623  

10040 23:54:21.452971  Initializing XHCI USB controller at 0x11200000.

10041 23:54:22.490605  

10042 23:54:22.493495  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10043 23:54:22.493627  

10044 23:54:22.493746  


10045 23:54:22.494096  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 23:54:22.594625  asurada: tftpboot 192.168.201.1 14084317/tftp-deploy-krm2ljnt/kernel/image.itb 14084317/tftp-deploy-krm2ljnt/kernel/cmdline 

10048 23:54:22.595057  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 23:54:22.595160  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 23:54:22.599423  tftpboot 192.168.201.1 14084317/tftp-deploy-krm2ljnt/kernel/image.ittp-deploy-krm2ljnt/kernel/cmdline 

10051 23:54:22.599504  

10052 23:54:22.599567  Waiting for link

10053 23:54:22.759876  

10054 23:54:22.760006  R8152: Initializing

10055 23:54:22.760074  

10056 23:54:22.762967  Version 9 (ocp_data = 6010)

10057 23:54:22.763036  

10058 23:54:22.766278  R8152: Done initializing

10059 23:54:22.766364  

10060 23:54:22.766422  Adding net device

10061 23:54:24.712057  

10062 23:54:24.712193  done.

10063 23:54:24.712262  

10064 23:54:24.712323  MAC: 00:e0:4c:78:7a:aa

10065 23:54:24.712428  

10066 23:54:24.715780  Sending DHCP discover... done.

10067 23:54:24.715887  

10068 23:54:24.719247  Waiting for reply... done.

10069 23:54:24.719354  

10070 23:54:24.722784  Sending DHCP request... done.

10071 23:54:24.722859  

10072 23:54:24.722953  Waiting for reply... done.

10073 23:54:24.723075  

10074 23:54:24.725936  My ip is 192.168.201.12

10075 23:54:24.726027  

10076 23:54:24.729078  The DHCP server ip is 192.168.201.1

10077 23:54:24.729162  

10078 23:54:24.732285  TFTP server IP predefined by user: 192.168.201.1

10079 23:54:24.732413  

10080 23:54:24.738800  Bootfile predefined by user: 14084317/tftp-deploy-krm2ljnt/kernel/image.itb

10081 23:54:24.738945  

10082 23:54:24.741936  Sending tftp read request... done.

10083 23:54:24.742031  

10084 23:54:24.745212  Waiting for the transfer... 

10085 23:54:24.745316  

10086 23:54:24.999267  00000000 ################################################################

10087 23:54:24.999461  

10088 23:54:25.247280  00080000 ################################################################

10089 23:54:25.247443  

10090 23:54:25.497108  00100000 ################################################################

10091 23:54:25.497239  

10092 23:54:25.758924  00180000 ################################################################

10093 23:54:25.759098  

10094 23:54:26.015298  00200000 ################################################################

10095 23:54:26.015467  

10096 23:54:26.275438  00280000 ################################################################

10097 23:54:26.275570  

10098 23:54:26.527431  00300000 ################################################################

10099 23:54:26.527588  

10100 23:54:26.778042  00380000 ################################################################

10101 23:54:26.778239  

10102 23:54:27.037798  00400000 ################################################################

10103 23:54:27.037946  

10104 23:54:27.298239  00480000 ################################################################

10105 23:54:27.298442  

10106 23:54:27.570168  00500000 ################################################################

10107 23:54:27.570344  

10108 23:54:27.830562  00580000 ################################################################

10109 23:54:27.830771  

10110 23:54:28.097502  00600000 ################################################################

10111 23:54:28.097647  

10112 23:54:28.368753  00680000 ################################################################

10113 23:54:28.368894  

10114 23:54:28.634024  00700000 ################################################################

10115 23:54:28.634175  

10116 23:54:28.916649  00780000 ################################################################

10117 23:54:28.916798  

10118 23:54:29.194642  00800000 ################################################################

10119 23:54:29.194810  

10120 23:54:29.478794  00880000 ################################################################

10121 23:54:29.478961  

10122 23:54:29.740695  00900000 ################################################################

10123 23:54:29.740829  

10124 23:54:29.996386  00980000 ################################################################

10125 23:54:29.996518  

10126 23:54:30.253299  00a00000 ################################################################

10127 23:54:30.253434  

10128 23:54:30.514673  00a80000 ################################################################

10129 23:54:30.514807  

10130 23:54:30.790191  00b00000 ################################################################

10131 23:54:30.790328  

10132 23:54:31.044991  00b80000 ################################################################

10133 23:54:31.045128  

10134 23:54:31.323079  00c00000 ################################################################

10135 23:54:31.323314  

10136 23:54:31.588994  00c80000 ################################################################

10137 23:54:31.589133  

10138 23:54:31.876625  00d00000 ################################################################

10139 23:54:31.876807  

10140 23:54:32.146910  00d80000 ################################################################

10141 23:54:32.147069  

10142 23:54:32.410839  00e00000 ################################################################

10143 23:54:32.411030  

10144 23:54:32.673216  00e80000 ################################################################

10145 23:54:32.673407  

10146 23:54:32.931966  00f00000 ################################################################

10147 23:54:32.932135  

10148 23:54:33.204087  00f80000 ################################################################

10149 23:54:33.204257  

10150 23:54:33.462534  01000000 ################################################################

10151 23:54:33.462696  

10152 23:54:33.719493  01080000 ################################################################

10153 23:54:33.719653  

10154 23:54:33.976174  01100000 ################################################################

10155 23:54:33.976379  

10156 23:54:34.236057  01180000 ################################################################

10157 23:54:34.236262  

10158 23:54:34.498627  01200000 ################################################################

10159 23:54:34.498771  

10160 23:54:34.755142  01280000 ################################################################

10161 23:54:34.755343  

10162 23:54:35.020730  01300000 ################################################################

10163 23:54:35.020936  

10164 23:54:35.283654  01380000 ################################################################

10165 23:54:35.283800  

10166 23:54:35.565269  01400000 ################################################################

10167 23:54:35.565406  

10168 23:54:35.841904  01480000 ################################################################

10169 23:54:35.842053  

10170 23:54:36.093475  01500000 ################################################################

10171 23:54:36.093669  

10172 23:54:36.342145  01580000 ################################################################

10173 23:54:36.342339  

10174 23:54:36.594185  01600000 ################################################################

10175 23:54:36.594359  

10176 23:54:36.849504  01680000 ################################################################

10177 23:54:36.849697  

10178 23:54:37.102731  01700000 ################################################################

10179 23:54:37.102867  

10180 23:54:37.354589  01780000 ################################################################

10181 23:54:37.354752  

10182 23:54:37.599196  01800000 ################################################################

10183 23:54:37.599386  

10184 23:54:37.844926  01880000 ################################################################

10185 23:54:37.845087  

10186 23:54:38.098529  01900000 ################################################################

10187 23:54:38.098676  

10188 23:54:38.361479  01980000 ################################################################

10189 23:54:38.361686  

10190 23:54:38.618391  01a00000 ################################################################

10191 23:54:38.618531  

10192 23:54:38.888378  01a80000 ################################################################

10193 23:54:38.888515  

10194 23:54:39.144110  01b00000 ################################################################

10195 23:54:39.144255  

10196 23:54:39.405415  01b80000 ################################################################

10197 23:54:39.405555  

10198 23:54:39.669208  01c00000 ################################################################

10199 23:54:39.669349  

10200 23:54:39.926861  01c80000 ################################################################

10201 23:54:39.927060  

10202 23:54:40.201872  01d00000 ################################################################

10203 23:54:40.202016  

10204 23:54:40.455254  01d80000 ################################################################

10205 23:54:40.455388  

10206 23:54:40.647740  01e00000 ################################################ done.

10207 23:54:40.647898  

10208 23:54:40.651058  The bootfile was 31843470 bytes long.

10209 23:54:40.651185  

10210 23:54:40.654761  Sending tftp read request... done.

10211 23:54:40.654854  

10212 23:54:40.658003  Waiting for the transfer... 

10213 23:54:40.658089  

10214 23:54:40.658174  00000000 # done.

10215 23:54:40.658255  

10216 23:54:40.664540  Command line loaded dynamically from TFTP file: 14084317/tftp-deploy-krm2ljnt/kernel/cmdline

10217 23:54:40.664626  

10218 23:54:40.687629  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1

10219 23:54:40.687725  

10220 23:54:40.687811  Loading FIT.

10221 23:54:40.690976  

10222 23:54:40.691061  Image ramdisk-1 has 18730692 bytes.

10223 23:54:40.691145  

10224 23:54:40.694428  Image fdt-1 has 47258 bytes.

10225 23:54:40.694514  

10226 23:54:40.697868  Image kernel-1 has 13063488 bytes.

10227 23:54:40.697953  

10228 23:54:40.707908  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10229 23:54:40.707994  

10230 23:54:40.724356  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10231 23:54:40.724466  

10232 23:54:40.730624  Choosing best match conf-1 for compat google,spherion-rev2.

10233 23:54:40.730732  

10234 23:54:40.739005  Connected to device vid:did:rid of 1ae0:0028:00

10235 23:54:40.747094  

10236 23:54:40.750423  tpm_get_response: command 0x17b, return code 0x0

10237 23:54:40.750505  

10238 23:54:40.753809  ec_init: CrosEC protocol v3 supported (256, 248)

10239 23:54:40.757831  

10240 23:54:40.760846  tpm_cleanup: add release locality here.

10241 23:54:40.760943  

10242 23:54:40.761028  Shutting down all USB controllers.

10243 23:54:40.764304  

10244 23:54:40.764411  Removing current net device

10245 23:54:40.764499  

10246 23:54:40.771471  Exiting depthcharge with code 4 at timestamp: 51570525

10247 23:54:40.771555  

10248 23:54:40.774519  LZMA decompressing kernel-1 to 0x821a6718

10249 23:54:40.774609  

10250 23:54:40.777515  LZMA decompressing kernel-1 to 0x40000000

10251 23:54:42.388027  

10252 23:54:42.388239  jumping to kernel

10253 23:54:42.388975  end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10254 23:54:42.389133  start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10255 23:54:42.389260  Setting prompt string to ['Linux version [0-9]']
10256 23:54:42.389377  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10257 23:54:42.389494  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10258 23:54:42.470256  

10259 23:54:42.473641  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10260 23:54:42.476763  start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10261 23:54:42.476862  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10262 23:54:42.476969  Setting prompt string to []
10263 23:54:42.477042  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10264 23:54:42.477112  Using line separator: #'\n'#
10265 23:54:42.477169  No login prompt set.
10266 23:54:42.477227  Parsing kernel messages
10267 23:54:42.477280  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10268 23:54:42.477378  [login-action] Waiting for messages, (timeout 00:04:01)
10269 23:54:42.477443  Waiting using forced prompt support (timeout 00:02:01)
10270 23:54:42.496756  [    0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024

10271 23:54:42.500266  [    0.000000] random: crng init done

10272 23:54:42.506929  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10273 23:54:42.510177  [    0.000000] efi: UEFI not found.

10274 23:54:42.516547  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10275 23:54:42.523111  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10276 23:54:42.533551  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10277 23:54:42.543333  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10278 23:54:42.550142  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10279 23:54:42.556681  [    0.000000] printk: bootconsole [mtk8250] enabled

10280 23:54:42.562970  [    0.000000] NUMA: No NUMA configuration found

10281 23:54:42.569851  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10282 23:54:42.573027  [    0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]

10283 23:54:42.576198  [    0.000000] Zone ranges:

10284 23:54:42.583031  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10285 23:54:42.585969  [    0.000000]   DMA32    empty

10286 23:54:42.593363  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10287 23:54:42.596375  [    0.000000] Movable zone start for each node

10288 23:54:42.599355  [    0.000000] Early memory node ranges

10289 23:54:42.606701  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10290 23:54:42.612719  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10291 23:54:42.619389  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10292 23:54:42.623077  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10293 23:54:42.629433  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10294 23:54:42.635976  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10295 23:54:42.695070  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10296 23:54:42.701572  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10297 23:54:42.708112  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10298 23:54:42.711213  [    0.000000] psci: probing for conduit method from DT.

10299 23:54:42.718506  [    0.000000] psci: PSCIv1.1 detected in firmware.

10300 23:54:42.721360  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10301 23:54:42.727988  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10302 23:54:42.731427  [    0.000000] psci: SMC Calling Convention v1.2

10303 23:54:42.738484  [    0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016

10304 23:54:42.741599  [    0.000000] Detected VIPT I-cache on CPU0

10305 23:54:42.748108  [    0.000000] CPU features: detected: GIC system register CPU interface

10306 23:54:42.754206  [    0.000000] CPU features: detected: Virtualization Host Extensions

10307 23:54:42.761158  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10308 23:54:42.768104  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10309 23:54:42.774893  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10310 23:54:42.784493  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10311 23:54:42.787533  [    0.000000] alternatives: applying boot alternatives

10312 23:54:42.794701  [    0.000000] Fallback order for Node 0: 0 

10313 23:54:42.801201  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10314 23:54:42.804477  [    0.000000] Policy zone: Normal

10315 23:54:42.827474  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1

10316 23:54:42.837577  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10317 23:54:42.848288  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10318 23:54:42.858503  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10319 23:54:42.864481  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10320 23:54:42.868146  <6>[    0.000000] software IO TLB: area num 8.

10321 23:54:42.925235  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10322 23:54:43.074212  <6>[    0.000000] Memory: 7945900K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406868K reserved, 32768K cma-reserved)

10323 23:54:43.081250  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10324 23:54:43.088064  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10325 23:54:43.091252  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10326 23:54:43.097711  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10327 23:54:43.104315  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10328 23:54:43.107514  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10329 23:54:43.118134  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10330 23:54:43.124373  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10331 23:54:43.127506  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10332 23:54:43.135607  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10333 23:54:43.138581  <6>[    0.000000] GICv3: 608 SPIs implemented

10334 23:54:43.145573  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10335 23:54:43.148984  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10336 23:54:43.152095  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10337 23:54:43.161864  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10338 23:54:43.172489  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10339 23:54:43.185387  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10340 23:54:43.191863  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10341 23:54:43.201076  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10342 23:54:43.214514  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10343 23:54:43.221380  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10344 23:54:43.227727  <6>[    0.009231] Console: colour dummy device 80x25

10345 23:54:43.237527  <6>[    0.013960] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10346 23:54:43.243913  <6>[    0.024402] pid_max: default: 32768 minimum: 301

10347 23:54:43.247229  <6>[    0.029273] LSM: Security Framework initializing

10348 23:54:43.253709  <6>[    0.034209] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10349 23:54:43.263887  <6>[    0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10350 23:54:43.270514  <6>[    0.051445] cblist_init_generic: Setting adjustable number of callback queues.

10351 23:54:43.277671  <6>[    0.058936] cblist_init_generic: Setting shift to 3 and lim to 1.

10352 23:54:43.287486  <6>[    0.065313] cblist_init_generic: Setting adjustable number of callback queues.

10353 23:54:43.294229  <6>[    0.072740] cblist_init_generic: Setting shift to 3 and lim to 1.

10354 23:54:43.297343  <6>[    0.079179] rcu: Hierarchical SRCU implementation.

10355 23:54:43.303464  <6>[    0.084194] rcu: 	Max phase no-delay instances is 1000.

10356 23:54:43.310174  <6>[    0.091259] EFI services will not be available.

10357 23:54:43.313613  <6>[    0.096215] smp: Bringing up secondary CPUs ...

10358 23:54:43.322280  <6>[    0.101267] Detected VIPT I-cache on CPU1

10359 23:54:43.328407  <6>[    0.101340] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10360 23:54:43.335204  <6>[    0.101374] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10361 23:54:43.338323  <6>[    0.101714] Detected VIPT I-cache on CPU2

10362 23:54:43.348434  <6>[    0.101768] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10363 23:54:43.354711  <6>[    0.101786] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10364 23:54:43.358541  <6>[    0.102044] Detected VIPT I-cache on CPU3

10365 23:54:43.365261  <6>[    0.102091] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10366 23:54:43.372031  <6>[    0.102105] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10367 23:54:43.375016  <6>[    0.102411] CPU features: detected: Spectre-v4

10368 23:54:43.381419  <6>[    0.102418] CPU features: detected: Spectre-BHB

10369 23:54:43.384568  <6>[    0.102423] Detected PIPT I-cache on CPU4

10370 23:54:43.391340  <6>[    0.102478] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10371 23:54:43.398389  <6>[    0.102494] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10372 23:54:43.405046  <6>[    0.102785] Detected PIPT I-cache on CPU5

10373 23:54:43.411126  <6>[    0.102848] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10374 23:54:43.417483  <6>[    0.102864] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10375 23:54:43.421070  <6>[    0.103146] Detected PIPT I-cache on CPU6

10376 23:54:43.427654  <6>[    0.103214] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10377 23:54:43.434360  <6>[    0.103230] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10378 23:54:43.441177  <6>[    0.103527] Detected PIPT I-cache on CPU7

10379 23:54:43.447508  <6>[    0.103592] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10380 23:54:43.454023  <6>[    0.103608] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10381 23:54:43.458003  <6>[    0.103654] smp: Brought up 1 node, 8 CPUs

10382 23:54:43.464506  <6>[    0.245131] SMP: Total of 8 processors activated.

10383 23:54:43.467675  <6>[    0.250082] CPU features: detected: 32-bit EL0 Support

10384 23:54:43.477251  <6>[    0.255445] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10385 23:54:43.483930  <6>[    0.264246] CPU features: detected: Common not Private translations

10386 23:54:43.491017  <6>[    0.270722] CPU features: detected: CRC32 instructions

10387 23:54:43.494114  <6>[    0.276107] CPU features: detected: RCpc load-acquire (LDAPR)

10388 23:54:43.500609  <6>[    0.282067] CPU features: detected: LSE atomic instructions

10389 23:54:43.507484  <6>[    0.287848] CPU features: detected: Privileged Access Never

10390 23:54:43.514322  <6>[    0.293628] CPU features: detected: RAS Extension Support

10391 23:54:43.520747  <6>[    0.299271] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10392 23:54:43.524062  <6>[    0.306541] CPU: All CPU(s) started at EL2

10393 23:54:43.530396  <6>[    0.310858] alternatives: applying system-wide alternatives

10394 23:54:43.539715  <6>[    0.321717] devtmpfs: initialized

10395 23:54:43.555051  <6>[    0.330504] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10396 23:54:43.562184  <6>[    0.340465] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10397 23:54:43.568530  <6>[    0.348493] pinctrl core: initialized pinctrl subsystem

10398 23:54:43.571654  <6>[    0.355134] DMI not present or invalid.

10399 23:54:43.579064  <6>[    0.359546] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10400 23:54:43.588203  <6>[    0.366418] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10401 23:54:43.595048  <6>[    0.374013] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10402 23:54:43.605107  <6>[    0.382233] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10403 23:54:43.608004  <6>[    0.390476] audit: initializing netlink subsys (disabled)

10404 23:54:43.618219  <5>[    0.396169] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1

10405 23:54:43.624665  <6>[    0.396864] thermal_sys: Registered thermal governor 'step_wise'

10406 23:54:43.631245  <6>[    0.404135] thermal_sys: Registered thermal governor 'power_allocator'

10407 23:54:43.634539  <6>[    0.410388] cpuidle: using governor menu

10408 23:54:43.640841  <6>[    0.421347] NET: Registered PF_QIPCRTR protocol family

10409 23:54:43.648062  <6>[    0.426833] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10410 23:54:43.654663  <6>[    0.433934] ASID allocator initialised with 32768 entries

10411 23:54:43.657639  <6>[    0.440501] Serial: AMBA PL011 UART driver

10412 23:54:43.667260  <4>[    0.449224] Trying to register duplicate clock ID: 134

10413 23:54:43.725755  <6>[    0.510606] KASLR enabled

10414 23:54:43.739757  <6>[    0.518320] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10415 23:54:43.746521  <6>[    0.525337] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10416 23:54:43.752998  <6>[    0.531826] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10417 23:54:43.759618  <6>[    0.538830] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10418 23:54:43.765997  <6>[    0.545318] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10419 23:54:43.772993  <6>[    0.552320] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10420 23:54:43.779287  <6>[    0.558807] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10421 23:54:43.786350  <6>[    0.565812] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10422 23:54:43.789095  <6>[    0.573335] ACPI: Interpreter disabled.

10423 23:54:43.797686  <6>[    0.579752] iommu: Default domain type: Translated 

10424 23:54:43.804490  <6>[    0.584866] iommu: DMA domain TLB invalidation policy: strict mode 

10425 23:54:43.807754  <5>[    0.591524] SCSI subsystem initialized

10426 23:54:43.814218  <6>[    0.595689] usbcore: registered new interface driver usbfs

10427 23:54:43.821062  <6>[    0.601421] usbcore: registered new interface driver hub

10428 23:54:43.824223  <6>[    0.606970] usbcore: registered new device driver usb

10429 23:54:43.831372  <6>[    0.613070] pps_core: LinuxPPS API ver. 1 registered

10430 23:54:43.841319  <6>[    0.618265] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10431 23:54:43.844240  <6>[    0.627609] PTP clock support registered

10432 23:54:43.847904  <6>[    0.631852] EDAC MC: Ver: 3.0.0

10433 23:54:43.855190  <6>[    0.636993] FPGA manager framework

10434 23:54:43.861504  <6>[    0.640678] Advanced Linux Sound Architecture Driver Initialized.

10435 23:54:43.864740  <6>[    0.647451] vgaarb: loaded

10436 23:54:43.871841  <6>[    0.650624] clocksource: Switched to clocksource arch_sys_counter

10437 23:54:43.875046  <5>[    0.657069] VFS: Disk quotas dquot_6.6.0

10438 23:54:43.881410  <6>[    0.661254] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10439 23:54:43.885362  <6>[    0.668443] pnp: PnP ACPI: disabled

10440 23:54:43.893468  <6>[    0.675061] NET: Registered PF_INET protocol family

10441 23:54:43.902871  <6>[    0.680657] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10442 23:54:43.914619  <6>[    0.692979] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10443 23:54:43.924810  <6>[    0.701794] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10444 23:54:43.931541  <6>[    0.709764] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10445 23:54:43.937838  <6>[    0.718464] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10446 23:54:43.950295  <6>[    0.728191] TCP: Hash tables configured (established 65536 bind 65536)

10447 23:54:43.956282  <6>[    0.735055] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10448 23:54:43.962825  <6>[    0.742253] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10449 23:54:43.969328  <6>[    0.749957] NET: Registered PF_UNIX/PF_LOCAL protocol family

10450 23:54:43.976197  <6>[    0.756113] RPC: Registered named UNIX socket transport module.

10451 23:54:43.979197  <6>[    0.762265] RPC: Registered udp transport module.

10452 23:54:43.986668  <6>[    0.767197] RPC: Registered tcp transport module.

10453 23:54:43.992616  <6>[    0.772130] RPC: Registered tcp NFSv4.1 backchannel transport module.

10454 23:54:43.996205  <6>[    0.778795] PCI: CLS 0 bytes, default 64

10455 23:54:43.999229  <6>[    0.783135] Unpacking initramfs...

10456 23:54:44.024537  <6>[    0.802712] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10457 23:54:44.033743  <6>[    0.811324] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10458 23:54:44.037515  <6>[    0.820157] kvm [1]: IPA Size Limit: 40 bits

10459 23:54:44.044365  <6>[    0.824683] kvm [1]: GICv3: no GICV resource entry

10460 23:54:44.047292  <6>[    0.829705] kvm [1]: disabling GICv2 emulation

10461 23:54:44.054003  <6>[    0.834401] kvm [1]: GIC system register CPU interface enabled

10462 23:54:44.057229  <6>[    0.840561] kvm [1]: vgic interrupt IRQ18

10463 23:54:44.064076  <6>[    0.844907] kvm [1]: VHE mode initialized successfully

10464 23:54:44.070531  <5>[    0.851433] Initialise system trusted keyrings

10465 23:54:44.076835  <6>[    0.856295] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10466 23:54:44.084532  <6>[    0.866276] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10467 23:54:44.090904  <5>[    0.872665] NFS: Registering the id_resolver key type

10468 23:54:44.094723  <5>[    0.877968] Key type id_resolver registered

10469 23:54:44.101301  <5>[    0.882384] Key type id_legacy registered

10470 23:54:44.107251  <6>[    0.886660] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10471 23:54:44.114432  <6>[    0.893580] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10472 23:54:44.120677  <6>[    0.901274] 9p: Installing v9fs 9p2000 file system support

10473 23:54:44.157448  <5>[    0.939207] Key type asymmetric registered

10474 23:54:44.160813  <5>[    0.943535] Asymmetric key parser 'x509' registered

10475 23:54:44.170598  <6>[    0.948674] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10476 23:54:44.174059  <6>[    0.956291] io scheduler mq-deadline registered

10477 23:54:44.177150  <6>[    0.961065] io scheduler kyber registered

10478 23:54:44.196637  <6>[    0.977901] EINJ: ACPI disabled.

10479 23:54:44.228720  <4>[    1.003660] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10480 23:54:44.238442  <4>[    1.014304] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10481 23:54:44.253082  <6>[    1.035037] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10482 23:54:44.261127  <6>[    1.042947] printk: console [ttyS0] disabled

10483 23:54:44.289298  <6>[    1.067576] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10484 23:54:44.295739  <6>[    1.077050] printk: console [ttyS0] enabled

10485 23:54:44.299095  <6>[    1.077050] printk: console [ttyS0] enabled

10486 23:54:44.306152  <6>[    1.085949] printk: bootconsole [mtk8250] disabled

10487 23:54:44.308884  <6>[    1.085949] printk: bootconsole [mtk8250] disabled

10488 23:54:44.315279  <6>[    1.096913] SuperH (H)SCI(F) driver initialized

10489 23:54:44.318708  <6>[    1.102177] msm_serial: driver initialized

10490 23:54:44.332316  <6>[    1.111085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10491 23:54:44.342421  <6>[    1.119628] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10492 23:54:44.348942  <6>[    1.128170] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10493 23:54:44.358789  <6>[    1.136797] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10494 23:54:44.365989  <6>[    1.145504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10495 23:54:44.375929  <6>[    1.154218] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10496 23:54:44.385852  <6>[    1.162757] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10497 23:54:44.392107  <6>[    1.171555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10498 23:54:44.402024  <6>[    1.180096] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10499 23:54:44.413638  <6>[    1.195474] loop: module loaded

10500 23:54:44.419841  <6>[    1.201466] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10501 23:54:44.442516  <4>[    1.224708] mtk-pmic-keys: Failed to locate of_node [id: -1]

10502 23:54:44.449624  <6>[    1.231493] megasas: 07.719.03.00-rc1

10503 23:54:44.459199  <6>[    1.241205] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10504 23:54:44.468116  <6>[    1.250018] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10505 23:54:44.485233  <6>[    1.266744] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10506 23:54:44.542466  <6>[    1.316989] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10507 23:54:44.791454  <6>[    1.573274] Freeing initrd memory: 18284K

10508 23:54:44.802750  <6>[    1.584736] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10509 23:54:44.813670  <6>[    1.595838] tun: Universal TUN/TAP device driver, 1.6

10510 23:54:44.817267  <6>[    1.601917] thunder_xcv, ver 1.0

10511 23:54:44.820498  <6>[    1.605425] thunder_bgx, ver 1.0

10512 23:54:44.823824  <6>[    1.608919] nicpf, ver 1.0

10513 23:54:44.834937  <6>[    1.612943] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10514 23:54:44.838120  <6>[    1.620420] hns3: Copyright (c) 2017 Huawei Corporation.

10515 23:54:44.841186  <6>[    1.626006] hclge is initializing

10516 23:54:44.847992  <6>[    1.629588] e1000: Intel(R) PRO/1000 Network Driver

10517 23:54:44.854764  <6>[    1.634718] e1000: Copyright (c) 1999-2006 Intel Corporation.

10518 23:54:44.858054  <6>[    1.640735] e1000e: Intel(R) PRO/1000 Network Driver

10519 23:54:44.864614  <6>[    1.645951] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10520 23:54:44.871365  <6>[    1.652135] igb: Intel(R) Gigabit Ethernet Network Driver

10521 23:54:44.878234  <6>[    1.657785] igb: Copyright (c) 2007-2014 Intel Corporation.

10522 23:54:44.884874  <6>[    1.663621] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10523 23:54:44.888162  <6>[    1.670139] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10524 23:54:44.894539  <6>[    1.676602] sky2: driver version 1.30

10525 23:54:44.901459  <6>[    1.681530] usbcore: registered new device driver r8152-cfgselector

10526 23:54:44.908304  <6>[    1.688064] usbcore: registered new interface driver r8152

10527 23:54:44.911442  <6>[    1.693900] VFIO - User Level meta-driver version: 0.3

10528 23:54:44.920079  <6>[    1.702138] usbcore: registered new interface driver usb-storage

10529 23:54:44.926939  <6>[    1.708592] usbcore: registered new device driver onboard-usb-hub

10530 23:54:44.936150  <6>[    1.717724] mt6397-rtc mt6359-rtc: registered as rtc0

10531 23:54:44.945450  <6>[    1.723185] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:50:05 UTC (1717026605)

10532 23:54:44.949272  <6>[    1.732754] i2c_dev: i2c /dev entries driver

10533 23:54:44.966091  <6>[    1.744588] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10534 23:54:44.972622  <4>[    1.753309] cpu cpu0: supply cpu not found, using dummy regulator

10535 23:54:44.978932  <4>[    1.759730] cpu cpu1: supply cpu not found, using dummy regulator

10536 23:54:44.985541  <4>[    1.766131] cpu cpu2: supply cpu not found, using dummy regulator

10537 23:54:44.992558  <4>[    1.772530] cpu cpu3: supply cpu not found, using dummy regulator

10538 23:54:44.999112  <4>[    1.778946] cpu cpu4: supply cpu not found, using dummy regulator

10539 23:54:45.005835  <4>[    1.785342] cpu cpu5: supply cpu not found, using dummy regulator

10540 23:54:45.012579  <4>[    1.791741] cpu cpu6: supply cpu not found, using dummy regulator

10541 23:54:45.015771  <4>[    1.798133] cpu cpu7: supply cpu not found, using dummy regulator

10542 23:54:45.036671  <6>[    1.818766] cpu cpu0: EM: created perf domain

10543 23:54:45.039951  <6>[    1.823709] cpu cpu4: EM: created perf domain

10544 23:54:45.048194  <6>[    1.829322] sdhci: Secure Digital Host Controller Interface driver

10545 23:54:45.054021  <6>[    1.835755] sdhci: Copyright(c) Pierre Ossman

10546 23:54:45.061130  <6>[    1.840699] Synopsys Designware Multimedia Card Interface Driver

10547 23:54:45.067736  <6>[    1.847332] sdhci-pltfm: SDHCI platform and OF driver helper

10548 23:54:45.070851  <6>[    1.847406] mmc0: CQHCI version 5.10

10549 23:54:45.077841  <6>[    1.857701] ledtrig-cpu: registered to indicate activity on CPUs

10550 23:54:45.084072  <6>[    1.864709] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10551 23:54:45.090894  <6>[    1.871761] usbcore: registered new interface driver usbhid

10552 23:54:45.094031  <6>[    1.877583] usbhid: USB HID core driver

10553 23:54:45.100523  <6>[    1.881789] spi_master spi0: will run message pump with realtime priority

10554 23:54:45.141622  <6>[    1.917037] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10555 23:54:45.160359  <6>[    1.932227] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10556 23:54:45.167720  <6>[    1.946922] cros-ec-spi spi0.0: Chrome EC device registered

10557 23:54:45.171059  <6>[    1.952950] mmc0: Command Queue Engine enabled

10558 23:54:45.177559  <6>[    1.957707] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10559 23:54:45.184427  <6>[    1.965523] mmcblk0: mmc0:0001 DA4128 116 GiB 

10560 23:54:45.192567  <6>[    1.974695]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10561 23:54:45.200256  <6>[    1.982452] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10562 23:54:45.210497  <6>[    1.987654] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10563 23:54:45.213709  <6>[    1.988337] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10564 23:54:45.220185  <6>[    1.998206] NET: Registered PF_PACKET protocol family

10565 23:54:45.227082  <6>[    2.002865] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10566 23:54:45.230626  <6>[    2.007583] 9pnet: Installing 9P2000 support

10567 23:54:45.237438  <5>[    2.018574] Key type dns_resolver registered

10568 23:54:45.240465  <6>[    2.023482] registered taskstats version 1

10569 23:54:45.247046  <5>[    2.027862] Loading compiled-in X.509 certificates

10570 23:54:45.275978  <4>[    2.051475] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10571 23:54:45.286173  <4>[    2.062417] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10572 23:54:45.300183  <6>[    2.082454] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10573 23:54:45.307310  <6>[    2.089304] xhci-mtk 11200000.usb: xHCI Host Controller

10574 23:54:45.314353  <6>[    2.094823] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10575 23:54:45.324726  <6>[    2.102691] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10576 23:54:45.330459  <6>[    2.112121] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10577 23:54:45.337405  <6>[    2.118298] xhci-mtk 11200000.usb: xHCI Host Controller

10578 23:54:45.344275  <6>[    2.123801] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10579 23:54:45.350344  <6>[    2.131454] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10580 23:54:45.357553  <6>[    2.139263] hub 1-0:1.0: USB hub found

10581 23:54:45.360380  <6>[    2.143286] hub 1-0:1.0: 1 port detected

10582 23:54:45.367169  <6>[    2.147563] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10583 23:54:45.374593  <6>[    2.156274] hub 2-0:1.0: USB hub found

10584 23:54:45.378203  <6>[    2.160307] hub 2-0:1.0: 1 port detected

10585 23:54:45.385268  <6>[    2.167263] mtk-msdc 11f70000.mmc: Got CD GPIO

10586 23:54:45.397169  <6>[    2.175819] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10587 23:54:45.404070  <6>[    2.183847] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10588 23:54:45.413543  <4>[    2.191766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10589 23:54:45.423385  <6>[    2.201301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10590 23:54:45.430768  <6>[    2.209379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10591 23:54:45.436927  <6>[    2.217392] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10592 23:54:45.446967  <6>[    2.225308] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10593 23:54:45.453791  <6>[    2.233125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10594 23:54:45.463429  <6>[    2.240944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10595 23:54:45.473741  <6>[    2.251341] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10596 23:54:45.480640  <6>[    2.259723] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10597 23:54:45.490478  <6>[    2.268066] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10598 23:54:45.497031  <6>[    2.276405] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10599 23:54:45.506973  <6>[    2.284742] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10600 23:54:45.513581  <6>[    2.293080] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10601 23:54:45.524104  <6>[    2.301418] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10602 23:54:45.530574  <6>[    2.309755] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10603 23:54:45.540529  <6>[    2.318093] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10604 23:54:45.547443  <6>[    2.326431] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10605 23:54:45.556989  <6>[    2.334769] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10606 23:54:45.563782  <6>[    2.343107] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10607 23:54:45.573760  <6>[    2.351445] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10608 23:54:45.580468  <6>[    2.359782] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10609 23:54:45.590207  <6>[    2.368120] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10610 23:54:45.596672  <6>[    2.376852] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10611 23:54:45.604031  <6>[    2.383997] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10612 23:54:45.610016  <6>[    2.390764] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10613 23:54:45.616920  <6>[    2.397529] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10614 23:54:45.623590  <6>[    2.404459] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10615 23:54:45.633471  <6>[    2.411352] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10616 23:54:45.643758  <6>[    2.420481] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10617 23:54:45.653700  <6>[    2.429600] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10618 23:54:45.659969  <6>[    2.438893] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10619 23:54:45.670209  <6>[    2.448360] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10620 23:54:45.679698  <6>[    2.457827] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10621 23:54:45.689715  <6>[    2.466946] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10622 23:54:45.700008  <6>[    2.476413] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10623 23:54:45.706726  <6>[    2.485537] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10624 23:54:45.716243  <6>[    2.494841] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10625 23:54:45.729267  <6>[    2.505002] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10626 23:54:45.739544  <6>[    2.516475] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10627 23:54:45.745627  <6>[    2.526091] Trying to probe devices needed for running init ...

10628 23:54:45.791950  <6>[    2.570816] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10629 23:54:45.947129  <6>[    2.728992] hub 1-1:1.0: USB hub found

10630 23:54:45.950381  <6>[    2.733522] hub 1-1:1.0: 4 ports detected

10631 23:54:45.959844  <6>[    2.741988] hub 1-1:1.0: USB hub found

10632 23:54:45.963057  <6>[    2.746352] hub 1-1:1.0: 4 ports detected

10633 23:54:46.072234  <6>[    2.851268] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10634 23:54:46.098649  <6>[    2.880877] hub 2-1:1.0: USB hub found

10635 23:54:46.102088  <6>[    2.885386] hub 2-1:1.0: 3 ports detected

10636 23:54:46.111844  <6>[    2.893694] hub 2-1:1.0: USB hub found

10637 23:54:46.114718  <6>[    2.898150] hub 2-1:1.0: 3 ports detected

10638 23:54:46.288458  <6>[    3.066951] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10639 23:54:46.421056  <6>[    3.203070] hub 1-1.4:1.0: USB hub found

10640 23:54:46.424398  <6>[    3.207760] hub 1-1.4:1.0: 2 ports detected

10641 23:54:46.434418  <6>[    3.216559] hub 1-1.4:1.0: USB hub found

10642 23:54:46.437677  <6>[    3.221144] hub 1-1.4:1.0: 2 ports detected

10643 23:54:46.504565  <6>[    3.283174] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10644 23:54:46.613612  <6>[    3.391635] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10645 23:54:46.648480  <4>[    3.427422] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10646 23:54:46.658284  <4>[    3.436518] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10647 23:54:46.702687  <6>[    3.484687] r8152 2-1.3:1.0 eth0: v1.12.13

10648 23:54:46.735743  <6>[    3.514951] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10649 23:54:46.928294  <6>[    3.706798] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10650 23:54:48.352990  <6>[    5.135463] r8152 2-1.3:1.0 eth0: carrier on

10651 23:54:48.396743  <5>[    5.162705] Sending DHCP requests ., OK

10652 23:54:48.403346  <6>[    5.182977] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12

10653 23:54:48.406294  <6>[    5.191261] IP-Config: Complete:

10654 23:54:48.419541  <6>[    5.194764]      device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1

10655 23:54:48.426445  <6>[    5.205478]      host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)

10656 23:54:48.433335  <6>[    5.214101]      bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=

10657 23:54:48.439578  <6>[    5.214112]      nameserver0=192.168.201.1

10658 23:54:48.442656  <6>[    5.226241] clk: Disabling unused clocks

10659 23:54:48.446437  <6>[    5.231818] ALSA device list:

10660 23:54:48.452509  <6>[    5.235077]   No soundcards found.

10661 23:54:48.460654  <6>[    5.242763] Freeing unused kernel memory: 8512K

10662 23:54:48.464067  <6>[    5.247787] Run /init as init process

10663 23:54:48.474133  Loading, please wait...

10664 23:54:48.500589  Starting systemd-udevd version 252.22-1~deb12u1


10665 23:54:48.749861  <6>[    5.529106] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10666 23:54:48.775305  <6>[    5.554375] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10667 23:54:48.782224  <3>[    5.556114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10668 23:54:48.791817  <6>[    5.562214] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10669 23:54:48.795532  <6>[    5.562601] remoteproc remoteproc0: scp is available

10670 23:54:48.801929  <6>[    5.562741] remoteproc remoteproc0: powering up scp

10671 23:54:48.811692  <6>[    5.562751] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10672 23:54:48.815018  <6>[    5.562791] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10673 23:54:48.825317  <3>[    5.570121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10674 23:54:48.831599  <6>[    5.578840] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10675 23:54:48.841739  <4>[    5.589510] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10676 23:54:48.847926  <3>[    5.597775] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10677 23:54:48.854878  <4>[    5.610524] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10678 23:54:48.864698  <3>[    5.627973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10679 23:54:48.871764  <6>[    5.632833] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10680 23:54:48.874814  <6>[    5.639724] mc: Linux media interface: v0.10

10681 23:54:48.884819  <3>[    5.642967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10682 23:54:48.891212  <3>[    5.642977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10683 23:54:48.902015  <3>[    5.642988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10684 23:54:48.908650  <4>[    5.660331] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10685 23:54:48.915376  <4>[    5.660331] Fallback method does not support PEC.

10686 23:54:48.922056  <3>[    5.663250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10687 23:54:48.928810  <3>[    5.663486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10688 23:54:48.938857  <6>[    5.687429] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10689 23:54:48.948918  <3>[    5.687627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10690 23:54:48.955518  <6>[    5.688049] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10691 23:54:48.962151  <6>[    5.688058] remoteproc remoteproc0: remote processor scp is now up

10692 23:54:48.968858  <6>[    5.688059] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10693 23:54:48.978396  <3>[    5.688636] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10694 23:54:48.985232  <6>[    5.699923] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10695 23:54:48.992450  <6>[    5.699928] pci_bus 0000:00: root bus resource [bus 00-ff]

10696 23:54:48.998637  <6>[    5.699935] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10697 23:54:49.008336  <6>[    5.699938] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10698 23:54:49.015204  <6>[    5.699969] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10699 23:54:49.021848  <6>[    5.699982] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10700 23:54:49.028450  <6>[    5.700053] pci 0000:00:00.0: supports D1 D2

10701 23:54:49.035152  <6>[    5.700055] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10702 23:54:49.041547  <6>[    5.701081] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10703 23:54:49.048699  <6>[    5.701166] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10704 23:54:49.055062  <6>[    5.701191] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10705 23:54:49.065196  <6>[    5.701208] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10706 23:54:49.071705  <6>[    5.701223] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10707 23:54:49.081652  <6>[    5.701560] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2

10708 23:54:49.088489  <3>[    5.709292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10709 23:54:49.094976  <3>[    5.709295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10710 23:54:49.104649  <3>[    5.709332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10711 23:54:49.111703  <3>[    5.711700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10712 23:54:49.118337  <6>[    5.717486] pci 0000:01:00.0: supports D1 D2

10713 23:54:49.124928  <3>[    5.727449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10714 23:54:49.131533  <6>[    5.735525] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10715 23:54:49.141501  <3>[    5.744037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10716 23:54:49.151093  <6>[    5.751828] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3

10717 23:54:49.158386  <3>[    5.757495] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10718 23:54:49.164533  <3>[    5.757498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10719 23:54:49.174323  <3>[    5.757511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10720 23:54:49.181157  <6>[    5.763063] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10721 23:54:49.187288  <6>[    5.779458] videodev: Linux video capture interface: v2.00

10722 23:54:49.194303  <6>[    5.784145] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10723 23:54:49.203898  <6>[    5.786313] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10724 23:54:49.210697  <6>[    5.786327] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10725 23:54:49.220608  <6>[    5.786348] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10726 23:54:49.227108  <6>[    5.786363] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10727 23:54:49.233690  <6>[    5.792955] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10728 23:54:49.240596  <6>[    5.803275] Bluetooth: Core ver 2.22

10729 23:54:49.247600  <6>[    5.810191] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10730 23:54:49.253552  <6>[    5.814667] NET: Registered PF_BLUETOOTH protocol family

10731 23:54:49.257092  <6>[    5.821487] pci 0000:00:00.0: PCI bridge to [bus 01]

10732 23:54:49.263834  <6>[    5.829725] Bluetooth: HCI device and connection manager initialized

10733 23:54:49.270387  <6>[    5.829741] Bluetooth: HCI socket layer initialized

10734 23:54:49.276585  <6>[    5.835985] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10735 23:54:49.284055  <6>[    5.843453] Bluetooth: L2CAP socket layer initialized

10736 23:54:49.290396  <6>[    5.851085] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10737 23:54:49.297038  <6>[    5.852398] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10738 23:54:49.309960  <6>[    5.853914] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10739 23:54:49.313263  <6>[    5.854150] usbcore: registered new interface driver uvcvideo

10740 23:54:49.320105  <6>[    5.858401] Bluetooth: SCO socket layer initialized

10741 23:54:49.326152  <6>[    5.867952] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10742 23:54:49.333109  <6>[    5.892445] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10743 23:54:49.339512  <6>[    5.901152] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10744 23:54:49.343307  <6>[    5.920404] usbcore: registered new interface driver btusb

10745 23:54:49.355896  <4>[    5.921246] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10746 23:54:49.359232  <3>[    5.921259] Bluetooth: hci0: Failed to load firmware file (-2)

10747 23:54:49.365886  <3>[    5.921264] Bluetooth: hci0: Failed to set up firmware (-2)

10748 23:54:49.376321  <4>[    5.921269] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10749 23:54:49.385677  <5>[    5.948410] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10750 23:54:49.408962  <5>[    6.187957] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10751 23:54:49.415517  <5>[    6.195097] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'

10752 23:54:49.425476  <4>[    6.203514] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10753 23:54:49.428387  <6>[    6.212387] cfg80211: failed to load regulatory.db

10754 23:54:49.474946  <6>[    6.254250] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10755 23:54:49.481771  <6>[    6.261862] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10756 23:54:49.505926  <6>[    6.288669] mt7921e 0000:01:00.0: ASIC revision: 79610010

10757 23:54:49.607291  <6>[    6.386531] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a

10758 23:54:49.610474  <6>[    6.386531] 

10759 23:54:49.614536  Begin: Loading essential drivers ... done.

10760 23:54:49.617836  Begin: Running /scripts/init-premount ... done.

10761 23:54:49.624197  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10762 23:54:49.634101  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available

10763 23:54:49.637062  Device /sys/class/net/eth0 found

10764 23:54:49.637170  done.

10765 23:54:49.647214  Begin: Waiting up to 180 secs for any network device to become available ... done.

10766 23:54:49.680544  IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP

10767 23:54:49.687297  IP-Config: eth0 complete (dhcp from 192.168.201.1):

10768 23:54:49.694128   address: 192.168.201.12   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10769 23:54:49.700155   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10770 23:54:49.706700   host   : mt8192-asurada-spherion-r0-cbg-0                                

10771 23:54:49.713613   domain : lava-rack                                                       

10772 23:54:49.717041   rootserver: 192.168.201.1 rootpath: 

10773 23:54:49.717116   filename  : 

10774 23:54:49.877561  <6>[    6.657025] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038

10775 23:54:49.877706  done.

10776 23:54:49.887702  Begin: Running /scripts/nfs-bottom ... done.

10777 23:54:49.907421  Begin: Running /scripts/init-bottom ... done.

10778 23:54:51.229351  <6>[    8.011729] NET: Registered PF_INET6 protocol family

10779 23:54:51.236884  <6>[    8.019338] Segment Routing with IPv6

10780 23:54:51.239795  <6>[    8.023339] In-situ OAM (IOAM) with IPv6

10781 23:54:51.409202  <30>[    8.164785] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)

10782 23:54:51.415271  <30>[    8.197911] systemd[1]: Detected architecture arm64.

10783 23:54:51.422638  

10784 23:54:51.426349  Welcome to Debian GNU/Linux 12 (bookworm)!

10785 23:54:51.426432  


10786 23:54:51.449477  <30>[    8.232011] systemd[1]: Hostname set to <debian-bookworm-arm64>.

10787 23:54:52.451553  <30>[    9.231102] systemd[1]: Queued start job for default target graphical.target.

10788 23:54:52.489385  <30>[    9.268825] systemd[1]: Created slice system-getty.slice - Slice /system/getty.

10789 23:54:52.496087  [  OK  ] Created slice system-getty.slice - Slice /system/getty.


10790 23:54:52.517611  <30>[    9.296984] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.

10791 23:54:52.527437  [  OK  ] Created slice system-modpr…lice - Slice /system/modprobe.


10792 23:54:52.545337  <30>[    9.324867] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.

10793 23:54:52.555426  [  OK  ] Created slice system-seria… - Slice /system/serial-getty.


10794 23:54:52.573800  <30>[    9.353337] systemd[1]: Created slice user.slice - User and Session Slice.

10795 23:54:52.580591  [  OK  ] Created slice user.slice - User and Session Slice.


10796 23:54:52.604133  <30>[    9.379858] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.

10797 23:54:52.613284  [  OK  ] Started systemd-ask-passwo…quests to Console Directory Watch.


10798 23:54:52.635931  <30>[    9.411829] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.

10799 23:54:52.642722  [  OK  ] Started systemd-ask-passwo… Requests to Wall Directory Watch.


10800 23:54:52.669397  <30>[    9.439159] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).

10801 23:54:52.679522  <30>[    9.458994] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...

10802 23:54:52.685942           Expecting device dev-ttyS0.device - /dev/ttyS0...


10803 23:54:52.704145  <30>[    9.483380] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.

10804 23:54:52.713712  [  OK  ] Reached target cryptsetup.…get - Local Encrypted Volumes.


10805 23:54:52.731637  <30>[    9.511099] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.

10806 23:54:52.741877  [  OK  ] Reached target integrityse…Local Integrity Protected Volumes.


10807 23:54:52.756746  <30>[    9.539548] systemd[1]: Reached target paths.target - Path Units.

10808 23:54:52.766929  [  OK  ] Reached target paths.target - Path Units.


10809 23:54:52.783629  <30>[    9.563166] systemd[1]: Reached target remote-fs.target - Remote File Systems.

10810 23:54:52.790462  [  OK  ] Reached target remote-fs.target - Remote File Systems.


10811 23:54:52.804021  <30>[    9.586784] systemd[1]: Reached target slices.target - Slice Units.

10812 23:54:52.813740  [  OK  ] Reached target slices.target - Slice Units.


10813 23:54:52.828249  <30>[    9.610809] systemd[1]: Reached target swap.target - Swaps.

10814 23:54:52.834836  [  OK  ] Reached target swap.target - Swaps.


10815 23:54:52.851680  <30>[    9.630958] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.

10816 23:54:52.861367  [  OK  ] Reached target veritysetup… - Local Verity Protected Volumes.


10817 23:54:52.880823  <30>[    9.659939] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.

10818 23:54:52.890578  [  OK  ] Listening on systemd-initc… initctl Compatibility Named Pipe.


10819 23:54:52.910104  <30>[    9.689535] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.

10820 23:54:52.919817  [  OK  ] Listening on systemd-journ…socket - Journal Audit Socket.


10821 23:54:52.937609  <30>[    9.717144] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).

10822 23:54:52.947521  [  OK  ] Listening on systemd-journ…t - Journal Socket (/dev/log).


10823 23:54:52.964251  <30>[    9.743765] systemd[1]: Listening on systemd-journald.socket - Journal Socket.

10824 23:54:52.970749  [  OK  ] Listening on systemd-journald.socket - Journal Socket.


10825 23:54:52.989158  <30>[    9.768463] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.

10826 23:54:52.999001  [  OK  ] Listening on systemd-netwo… - Network Service Netlink Socket.


10827 23:54:53.018357  <30>[    9.797780] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.

10828 23:54:53.028332  [  OK  ] Listening on systemd-udevd….socket - udev Control Socket.


10829 23:54:53.044097  <30>[    9.823541] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.

10830 23:54:53.053739  [  OK  ] Listening on systemd-udevd…l.socket - udev Kernel Socket.


10831 23:54:53.107683  <30>[    9.887136] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...

10832 23:54:53.114498           Mounting dev-hugepages.mount - Huge Pages File System...


10833 23:54:53.136844  <30>[    9.916232] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...

10834 23:54:53.143705           Mounting dev-mqueue.mount…POSIX Message Queue File System...


10835 23:54:53.203681  <30>[    9.983330] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...

10836 23:54:53.210730           Mounting sys-kernel-debug.… - Kernel Debug File System...


10837 23:54:53.238365  <30>[   10.011170] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).

10838 23:54:53.252933  <30>[   10.032373] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...

10839 23:54:53.263002           Starting kmod-static-nodes…ate List of Static Device Nodes...


10840 23:54:53.283761  <30>[   10.063140] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...

10841 23:54:53.290377           Starting modprobe@configfs…m - Load Kernel Module configfs...


10842 23:54:53.315341  <30>[   10.095093] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...

10843 23:54:53.322318           Starting modprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...


10844 23:54:53.362924  <6>[   10.142325] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com

10845 23:54:53.388458  <30>[   10.167754] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...

10846 23:54:53.394617           Starting modprobe@drm.service - Load Kernel Module drm...


10847 23:54:53.421461  <30>[   10.201239] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...

10848 23:54:53.431644           Starting modprobe@efi_psto…- Load Kernel Module efi_pstore...


10849 23:54:53.451753  <30>[   10.230848] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...

10850 23:54:53.457866           Starting modprobe@fuse.ser…e - Load Kernel Module fuse...


10851 23:54:53.479759  <30>[   10.259119] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...

10852 23:54:53.486580           Starting modpr<6>[   10.269813] fuse: init (API version 7.37)

10853 23:54:53.489652  obe@loop.ser…e - Load Kernel Module loop...


10854 23:54:53.517955  <30>[   10.297301] systemd[1]: Starting systemd-journald.service - Journal Service...

10855 23:54:53.524352           Starting systemd-journald.service - Journal Service...


10856 23:54:53.572672  <30>[   10.351846] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...

10857 23:54:53.579154           Starting systemd-modules-l…rvice - Load Kernel Modules...


10858 23:54:53.605710  <30>[   10.381866] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...

10859 23:54:53.612153           Starting systemd-network-g… units from Kernel command line...


10860 23:54:53.635849  <30>[   10.415567] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...

10861 23:54:53.646097           Starting systemd-remount-f…nt Root and Kernel File Systems...


10862 23:54:53.671891  <30>[   10.451235] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...

10863 23:54:53.678677           Starting systemd-udev-trig…[0m - Coldplug All udev Devices...


10864 23:54:53.688756  <3>[   10.467811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10865 23:54:53.704441  <30>[   10.484099] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.

10866 23:54:53.711407  [  OK  ] Mounted dev-hugepages.mount - Huge Pages File System.


10867 23:54:53.732440  <3>[   10.511849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10868 23:54:53.741974  <30>[   10.512138] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.

10869 23:54:53.748872  [  OK  ] Mounted dev-mqueue.mount[…- POSIX Message Queue File System.


10870 23:54:53.767907  <30>[   10.546993] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.

10871 23:54:53.780914  [  OK  ] Mounted sys-kernel-<3>[   10.558301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10872 23:54:53.784515  debug.m…nt - Kernel Debug File System.


10873 23:54:53.805204  <30>[   10.584103] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.

10874 23:54:53.814880  <3>[   10.589248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10875 23:54:53.821856  [  OK  ] Finished kmod-static-nodes…reate List of Static Device Nodes.


10876 23:54:53.841109  <30>[   10.619918] systemd[1]: modprobe@configfs.service: Deactivated successfully.

10877 23:54:53.847591  <3>[   10.622585] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10878 23:54:53.857412  <30>[   10.627839] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.

10879 23:54:53.864360  [  OK  ] Finished modprobe@configfs…[0m - Load Kernel Module configfs.


10880 23:54:53.877028  <3>[   10.657010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10881 23:54:53.888120  <30>[   10.667723] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.

10882 23:54:53.894896  <30>[   10.676261] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.

10883 23:54:53.909087  [  OK  ] Finished [0<3>[   10.686379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10884 23:54:53.912189  ;1;39mmodprobe@dm_mod.s…e - Load Kernel Module dm_mod.


10885 23:54:53.930588  <30>[   10.712774] systemd[1]: modprobe@drm.service: Deactivated successfully.

10886 23:54:53.940279  <3>[   10.716417] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10887 23:54:53.946582  <30>[   10.720247] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.

10888 23:54:53.957038  [  OK  ] Finished modprobe@drm.service - Load Kernel Module drm.


10889 23:54:53.969275  <3>[   10.748383] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10890 23:54:53.979464  <30>[   10.759216] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.

10891 23:54:53.990333  <30>[   10.767681] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.

10892 23:54:54.000211  [  OK  ] Finished modprobe@e<3>[   10.780261] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10893 23:54:54.006737  fi_psto…m - Load Kernel Module efi_pstore.


10894 23:54:54.026060  <30>[   10.808280] systemd[1]: modprobe@fuse.service: Deactivated successfully.

10895 23:54:54.036700  <30>[   10.816170] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.

10896 23:54:54.046267  <3>[   10.824133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10897 23:54:54.052977  [  OK  ] Finished modprobe@fuse.service - Load Kernel Module fuse.


10898 23:54:54.076002  <3>[   10.855632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10899 23:54:54.083036  <30>[   10.856299] systemd[1]: modprobe@loop.service: Deactivated successfully.

10900 23:54:54.093141  <30>[   10.872363] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.

10901 23:54:54.099327  [  OK  ] Finished modprobe@loop.service - Load Kernel Module loop.


10902 23:54:54.120884  <30>[   10.900240] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.

10903 23:54:54.127605  [  OK  ] Finished systemd-modules-l…service - Load Kernel Modules.


10904 23:54:54.141755  <3>[   10.921295] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10905 23:54:54.148512  <3>[   10.922414] power_supply sbs-5-000b: driver failed to report `temp' property: -6

10906 23:54:54.165097  <4>[   10.930242] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10907 23:54:54.175589  <30>[   10.938595] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.

10908 23:54:54.185367  <3>[   10.953372] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5

10909 23:54:54.194959  [  OK  ] Finished systemd-network-g…rk units from Kernel command line.


10910 23:54:54.212891  <30>[   10.991986] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.

10911 23:54:54.222964  <3>[   10.994982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10912 23:54:54.229475  [  OK  ] Finished systemd-remount-f…ount Root and Kernel File Systems.


10913 23:54:54.248493  <30>[   11.027797] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.

10914 23:54:54.258473  <3>[   11.031932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10915 23:54:54.265135  [  OK  ] Finished systemd-udev-trig…e - Coldplug All udev Devices.


10916 23:54:54.285339  <30>[   11.064278] systemd[1]: Reached target network-pre.target - Preparation for Network.

10917 23:54:54.291726  <3>[   11.067097] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10918 23:54:54.301904  [  OK  ] Reached target network-pre…get - Preparation for Network.


10919 23:54:54.352156  <30>[   11.131226] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...

10920 23:54:54.358677           Mounting sys-fs-fuse-conne… - FUSE Control File System...


10921 23:54:54.382387  <30>[   11.161319] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...

10922 23:54:54.389209           Mounting sys-kernel-config…ernel Configuration File System...


10923 23:54:54.410873  <30>[   11.187132] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).

10924 23:54:54.427814  <30>[   11.200816] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).

10925 23:54:54.441754  <30>[   11.221822] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...

10926 23:54:54.449052           Starting systemd-random-se…ice - Load/Save Random Seed...


10927 23:54:54.477370  <30>[   11.253775] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.

10928 23:54:54.492133  <30>[   11.271818] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...

10929 23:54:54.498769           Starting systemd-sysctl.se…ce - Apply Kernel Variables...


10930 23:54:54.528089  <30>[   11.307369] systemd[1]: Starting systemd-sysusers.service - Create System Users...

10931 23:54:54.534154           Starting systemd-sysusers.…rvice - Create System Users...


10932 23:54:54.568657  <30>[   11.348171] systemd[1]: Started systemd-journald.service - Journal Service.

10933 23:54:54.575572  [  OK  ] Started systemd-journald.service - Journal Service.


10934 23:54:54.601526  [  OK  ] Mounted sys-fs-fuse-connec…nt - FUSE Control File System.


10935 23:54:54.620382  [  OK  ] Mounted sys-kernel-config.… Kernel Configuration File System.


10936 23:54:54.640699  [  OK  ] Finished systemd-random-se…rvice - Load/Save Random Seed.


10937 23:54:54.660674  [  OK  ] Finished systemd-sysctl.service - Apply Kernel Variables.


10938 23:54:54.681048  [  OK  ] Finished systemd-sysusers.service - Create System Users.


10939 23:54:54.752095           Starting systemd-journal-f…h Journal to Persistent Storage...


10940 23:54:54.774865           Starting systemd-tmpfiles-…ate Static Device Nodes in /dev...


10941 23:54:54.805956  <46>[   11.585352] systemd-journald[308]: Received client request to flush runtime journal.

10942 23:54:55.572940  [  OK  ] Finished systemd-tmpfiles-…reate Static Device Nodes in /dev.


10943 23:54:55.596707  [  OK  ] Reached target local-fs-pr…reparation for Local File Systems.


10944 23:54:55.619811  [  OK  ] Reached target local-fs.target - Local File Systems.


10945 23:54:55.915758           Starting systemd-udevd.ser…ger for Device Events and Files...


10946 23:54:56.223385  [  OK  ] Finished systemd-journal-f…ush Journal to Persistent Storage.


10947 23:54:56.257925           Starting systemd-tmpfiles-… Volatile Files and Directories...


10948 23:54:56.418991  [  OK  ] Started systemd-udevd.serv…nager for Device Events and Files.


10949 23:54:56.480577           Starting systemd-networkd.…ice - Network Configuration...


10950 23:54:56.546182  [  OK  ] Found device dev-ttyS0.device - /dev/ttyS0.


10951 23:54:56.798876  [  OK  ] Finished systemd-tmpfiles-…te Volatile Files and Directories.


10952 23:54:56.853290  [  OK  ] Created slice system-syste…- Slice /system/systemd-backlight.


10953 23:54:56.892800  <6>[   13.674913] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0

10954 23:54:56.903352           Starting systemd-backlight…ess of leds:white:kbd_backlight...


10955 23:54:57.003962           Starting systemd-timesyncd… - Network Time Synchronization...


10956 23:54:57.030896           Starting systemd-update-ut…rd System Boot/Shutdown in UTMP...


10957 23:54:57.048874  [  OK  ] Finished systemd-backlight…tness of leds:white:kbd_backlight.


10958 23:54:57.095066  [  OK  ] Started systemd-networkd.service - Network Configuration.


10959 23:54:57.140107  [  OK  ] Reached target bluetooth.target - Bluetooth Support.


10960 23:54:57.156713  [  OK  ] Reached target network.target - Network.


10961 23:54:57.175538  [  OK  ] Listening on systemd-rfkil…l Switch Status /dev/rfkill Watch.


10962 23:54:57.192123  [  OK  ] Started systemd-timesyncd.…0m - Network Time Synchronization.


10963 23:54:57.212519  [  OK  ] Finished systemd-update-ut…cord System Boot/Shutdown in UTMP.


10964 23:54:57.236874  [  OK  ] Reached target sysinit.target - System Initialization.


10965 23:54:57.255737  [  OK  ] Started systemd-tmpfiles-c… Cleanup of Temporary Directories.


10966 23:54:57.274898  [  OK  ] Reached target time-set.target - System Time Set.


10967 23:54:57.299019  [  OK  ] Started apt-daily.timer - Daily apt download activities.


10968 23:54:57.317706  [  OK  ] Started apt-daily-upgrade.… apt upgrade and clean activities.


10969 23:54:57.335406  [  OK  ] Started dpkg-db-backup.tim… Daily dpkg database backup timer.


10970 23:54:57.377937  [  OK  ] Started e2scrub_all.timer…etadata Check for All Filesystems.


10971 23:54:57.398528  [  OK  ] Started fstrim.timer - Discard unused blocks once a week.


10972 23:54:57.414990  [  OK  ] Reached target timers.target - Timer Units.


10973 23:54:57.433044  [  OK  ] Listening on dbus.socket[…- D-Bus System Message Bus Socket.


10974 23:54:57.451240  [  OK  ] Reached target sockets.target - Socket Units.


10975 23:54:57.467488  [  OK  ] Reached target basic.target - Basic System.


10976 23:54:57.520739           Starting dbus.service - D-Bus System Message Bus...


10977 23:54:57.551799           Starting e2scrub_reap.serv…e ext4 Metadata Check Snapshots...


10978 23:54:57.652217           Starting systemd-logind.se…ice - User Login Management...


10979 23:54:57.680932           Starting systemd-rfkill.se…Load/Save RF Kill Switch Status...


10980 23:54:57.728005           Starting systemd-user-sess…vice - Permit User Sessions...


10981 23:54:57.754686  [  OK  ] Started systemd-rfkill.ser…- Load/Save RF Kill Switch Status.


10982 23:54:57.777165  [  OK  ] Started dbus.service - D-Bus System Message Bus.


10983 23:54:57.804669  [  OK  ] Finished systemd-user-sess…ervice - Permit User Sessions.


10984 23:54:57.855477  [  OK  ] Started getty@tty1.service - Getty on tty1.


10985 23:54:57.901144  [  OK  ] Started serial-getty@ttyS0…rvice - Serial Getty on ttyS0.


10986 23:54:57.920246  [  OK  ] Reached target getty.target - Login Prompts.


10987 23:54:57.941923  [  OK  ] Started systemd-logind.service - User Login Management.


10988 23:54:58.029936  [  OK  ] Finished e2scrub_reap.serv…ine ext4 Metadata Check Snapshots.


10989 23:54:58.051373  [  OK  ] Reached target multi-user.target - Multi-User System.


10990 23:54:58.068521  [  OK  ] Reached target graphical.target - Graphical Interface.


10991 23:54:58.115103           Starting systemd-update-ut… Record Runlevel Change in UTMP...


10992 23:54:58.167368  [  OK  ] Finished systemd-update-ut… - Record Runlevel Change in UTMP.


10993 23:54:58.274641  


10994 23:54:58.277561  Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0

10995 23:54:58.277651  

10996 23:54:58.281262  debian-bookworm-arm64 login: root (automatic login)

10997 23:54:58.281351  


10998 23:54:58.529177  Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64

10999 23:54:58.529380  

11000 23:54:58.535877  The programs included with the Debian GNU/Linux system are free software;

11001 23:54:58.542359  the exact distribution terms for each program are described in the

11002 23:54:58.545762  individual files in /usr/share/doc/*/copyright.

11003 23:54:58.545888  

11004 23:54:58.553005  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11005 23:54:58.555861  permitted by applicable law.

11006 23:54:58.614650  Matched prompt #10: / #
11008 23:54:58.615026  Setting prompt string to ['/ #']
11009 23:54:58.615175  end: 2.2.5.1 login-action (duration 00:00:16) [common]
11011 23:54:58.615533  end: 2.2.5 auto-login-action (duration 00:00:16) [common]
11012 23:54:58.615680  start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
11013 23:54:58.615803  Setting prompt string to ['/ #']
11014 23:54:58.615911  Forcing a shell prompt, looking for ['/ #']
11016 23:54:58.666200  / # 

11017 23:54:58.666348  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11018 23:54:58.666469  Waiting using forced prompt support (timeout 00:02:30)
11019 23:54:58.671387  

11020 23:54:58.671709  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11021 23:54:58.671853  start: 2.2.7 export-device-env (timeout 00:03:45) [common]
11023 23:54:58.772332  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub'

11024 23:54:58.777891  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084317/extract-nfsrootfs-pbbsczub'

11026 23:54:58.878507  / # export NFS_SERVER_IP='192.168.201.1'

11027 23:54:58.884192  export NFS_SERVER_IP='192.168.201.1'

11028 23:54:58.884532  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 23:54:58.884684  end: 2.2 depthcharge-retry (duration 00:01:15) [common]
11030 23:54:58.884835  end: 2 depthcharge-action (duration 00:01:15) [common]
11031 23:54:58.884982  start: 3 lava-test-retry (timeout 00:01:00) [common]
11032 23:54:58.885130  start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11033 23:54:58.885261  Using namespace: common
11035 23:54:58.985647  / # #

11036 23:54:58.985839  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11037 23:54:58.991530  #

11038 23:54:58.991847  Using /lava-14084317
11040 23:54:59.092215  / # export SHELL=/bin/sh

11041 23:54:59.097749  export SHELL=/bin/sh

11043 23:54:59.198316  / # . /lava-14084317/environment

11044 23:54:59.203293  . /lava-14084317/environment

11046 23:54:59.309178  / # /lava-14084317/bin/lava-test-runner /lava-14084317/0

11047 23:54:59.309352  Test shell timeout: 10s (minimum of the action and connection timeout)
11048 23:54:59.314755  /lava-14084317/bin/lava-test-runner /lava-14084317/0

11049 23:54:59.517543  + export TESTRUN_ID=0_dmesg

11050 23:54:59.520899  + cd /lava-14084317/0/tests/0_dmesg

11051 23:54:59.524191  + cat uuid

11052 23:54:59.530591  + UUID=14084317_<8>[   16.313492] <LAVA_SIGNAL_STARTRUN 0_dmesg 14084317_1.6.2.3.1>

11053 23:54:59.530856  Received signal: <STARTRUN> 0_dmesg 14084317_1.6.2.3.1
11054 23:54:59.530930  Starting test lava.0_dmesg (14084317_1.6.2.3.1)
11055 23:54:59.531013  Skipping test definition patterns.
11056 23:54:59.534240  1.6.2.3.1

11057 23:54:59.534324  + set +x

11058 23:54:59.537226  + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh

11059 23:54:59.629197  <8>[   16.409627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>

11060 23:54:59.629571  Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11062 23:54:59.693189  <8>[   16.473241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>

11063 23:54:59.693526  Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11065 23:54:59.757887  <8>[   16.538100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>

11066 23:54:59.758225  Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11068 23:54:59.761327  + set +x

11069 23:54:59.764318  <8>[   16.547877] <LAVA_SIGNAL_ENDRUN 0_dmesg 14084317_1.6.2.3.1>

11070 23:54:59.764643  Received signal: <ENDRUN> 0_dmesg 14084317_1.6.2.3.1
11071 23:54:59.764777  Ending use of test pattern.
11072 23:54:59.764887  Ending test lava.0_dmesg (14084317_1.6.2.3.1), duration 0.23
11074 23:54:59.770740  <LAVA_TEST_RUNNER EXIT>

11075 23:54:59.771041  ok: lava_test_shell seems to have completed
11076 23:54:59.771221  alert: pass
crit: pass
emerg: pass

11077 23:54:59.771367  end: 3.1 lava-test-shell (duration 00:00:01) [common]
11078 23:54:59.771512  end: 3 lava-test-retry (duration 00:00:01) [common]
11079 23:54:59.771657  start: 4 finalize (timeout 00:08:15) [common]
11080 23:54:59.771805  start: 4.1 power-off (timeout 00:00:30) [common]
11081 23:54:59.772084  Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11082 23:54:59.848087  >> Command sent successfully.

11083 23:54:59.850560  Returned 0 in 0 seconds
11084 23:54:59.950967  end: 4.1 power-off (duration 00:00:00) [common]
11086 23:54:59.951284  start: 4.2 read-feedback (timeout 00:08:15) [common]
11087 23:54:59.951585  Listened to connection for namespace 'common' for up to 1s
11088 23:55:00.952450  Finalising connection for namespace 'common'
11089 23:55:00.952667  Disconnecting from shell: Finalise
11090 23:55:00.952747  / # 
11091 23:55:01.053064  end: 4.2 read-feedback (duration 00:00:01) [common]
11092 23:55:01.053220  end: 4 finalize (duration 00:00:01) [common]
11093 23:55:01.053335  Cleaning after the job
11094 23:55:01.053433  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/ramdisk
11095 23:55:01.055568  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/kernel
11096 23:55:01.066284  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/dtb
11097 23:55:01.066443  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/nfsrootfs
11098 23:55:01.123320  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084317/tftp-deploy-krm2ljnt/modules
11099 23:55:01.128995  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084317
11100 23:55:01.448063  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084317
11101 23:55:01.448240  Job finished correctly