Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 0
- Boot result: UNKNOWN
- Warnings: 0
- Kernel Warnings: 0
1 23:48:15.166698 lava-dispatcher, installed at version: 2024.03
2 23:48:15.166917 start: 0 validate
3 23:48:15.167061 Start time: 2024-05-29 23:48:15.167053+00:00 (UTC)
4 23:48:15.167188 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:48:15.167316 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:48:15.443411 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:48:15.444151 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:48:15.706326 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:48:15.707084 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:48:29.976819 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:48:29.977524 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:48:30.496630 validate duration: 15.33
14 23:48:30.497972 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:48:30.498572 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:48:30.499097 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:48:30.499727 Not decompressing ramdisk as can be used compressed.
18 23:48:30.500194 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 23:48:30.500550 saving as /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/ramdisk/rootfs.cpio.gz
20 23:48:30.500917 total size: 39026414 (37 MB)
21 23:48:33.017858 progress 0 % (0 MB)
22 23:48:33.060905 progress 5 % (1 MB)
23 23:48:33.077536 progress 10 % (3 MB)
24 23:48:33.088811 progress 15 % (5 MB)
25 23:48:33.099018 progress 20 % (7 MB)
26 23:48:33.108961 progress 25 % (9 MB)
27 23:48:33.119025 progress 30 % (11 MB)
28 23:48:33.128882 progress 35 % (13 MB)
29 23:48:33.138967 progress 40 % (14 MB)
30 23:48:33.149003 progress 45 % (16 MB)
31 23:48:33.158975 progress 50 % (18 MB)
32 23:48:33.168934 progress 55 % (20 MB)
33 23:48:33.178833 progress 60 % (22 MB)
34 23:48:33.188781 progress 65 % (24 MB)
35 23:48:33.198730 progress 70 % (26 MB)
36 23:48:33.208887 progress 75 % (27 MB)
37 23:48:33.218819 progress 80 % (29 MB)
38 23:48:33.228818 progress 85 % (31 MB)
39 23:48:33.238636 progress 90 % (33 MB)
40 23:48:33.248355 progress 95 % (35 MB)
41 23:48:33.258072 progress 100 % (37 MB)
42 23:48:33.258320 37 MB downloaded in 2.76 s (13.50 MB/s)
43 23:48:33.258469 end: 1.1.1 http-download (duration 00:00:03) [common]
45 23:48:33.258707 end: 1.1 download-retry (duration 00:00:03) [common]
46 23:48:33.258792 start: 1.2 download-retry (timeout 00:09:57) [common]
47 23:48:33.258875 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 23:48:33.259013 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:48:33.259081 saving as /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/kernel/Image
50 23:48:33.259142 total size: 54682112 (52 MB)
51 23:48:33.259203 No compression specified
52 23:48:33.260328 progress 0 % (0 MB)
53 23:48:33.274121 progress 5 % (2 MB)
54 23:48:33.287742 progress 10 % (5 MB)
55 23:48:33.301702 progress 15 % (7 MB)
56 23:48:33.315602 progress 20 % (10 MB)
57 23:48:33.329623 progress 25 % (13 MB)
58 23:48:33.343330 progress 30 % (15 MB)
59 23:48:33.357208 progress 35 % (18 MB)
60 23:48:33.371043 progress 40 % (20 MB)
61 23:48:33.384849 progress 45 % (23 MB)
62 23:48:33.398883 progress 50 % (26 MB)
63 23:48:33.412690 progress 55 % (28 MB)
64 23:48:33.426684 progress 60 % (31 MB)
65 23:48:33.440346 progress 65 % (33 MB)
66 23:48:33.454154 progress 70 % (36 MB)
67 23:48:33.467808 progress 75 % (39 MB)
68 23:48:33.481792 progress 80 % (41 MB)
69 23:48:33.495707 progress 85 % (44 MB)
70 23:48:33.509833 progress 90 % (46 MB)
71 23:48:33.523750 progress 95 % (49 MB)
72 23:48:33.537335 progress 100 % (52 MB)
73 23:48:33.537599 52 MB downloaded in 0.28 s (187.28 MB/s)
74 23:48:33.537756 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:48:33.537991 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:48:33.538078 start: 1.3 download-retry (timeout 00:09:57) [common]
78 23:48:33.538161 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 23:48:33.538296 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:48:33.538367 saving as /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/dtb/mt8192-asurada-spherion-r0.dtb
81 23:48:33.538428 total size: 47258 (0 MB)
82 23:48:33.538488 No compression specified
83 23:48:33.539724 progress 69 % (0 MB)
84 23:48:33.539999 progress 100 % (0 MB)
85 23:48:33.540151 0 MB downloaded in 0.00 s (26.19 MB/s)
86 23:48:33.540270 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:48:33.540493 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:48:33.540578 start: 1.4 download-retry (timeout 00:09:57) [common]
90 23:48:33.540659 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 23:48:33.540768 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:48:33.540835 saving as /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/modules/modules.tar
93 23:48:33.540894 total size: 8601444 (8 MB)
94 23:48:33.540954 Using unxz to decompress xz
95 23:48:33.545094 progress 0 % (0 MB)
96 23:48:33.564654 progress 5 % (0 MB)
97 23:48:33.588855 progress 10 % (0 MB)
98 23:48:33.614513 progress 15 % (1 MB)
99 23:48:33.639453 progress 20 % (1 MB)
100 23:48:33.664999 progress 25 % (2 MB)
101 23:48:33.689775 progress 30 % (2 MB)
102 23:48:33.713453 progress 35 % (2 MB)
103 23:48:33.738028 progress 40 % (3 MB)
104 23:48:33.765330 progress 45 % (3 MB)
105 23:48:33.789759 progress 50 % (4 MB)
106 23:48:33.815142 progress 55 % (4 MB)
107 23:48:33.841080 progress 60 % (4 MB)
108 23:48:33.866780 progress 65 % (5 MB)
109 23:48:33.893765 progress 70 % (5 MB)
110 23:48:33.920263 progress 75 % (6 MB)
111 23:48:33.944366 progress 80 % (6 MB)
112 23:48:33.970340 progress 85 % (7 MB)
113 23:48:33.994753 progress 90 % (7 MB)
114 23:48:34.024861 progress 95 % (7 MB)
115 23:48:34.053795 progress 100 % (8 MB)
116 23:48:34.059293 8 MB downloaded in 0.52 s (15.82 MB/s)
117 23:48:34.059540 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:48:34.059815 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:48:34.059922 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 23:48:34.060016 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 23:48:34.060095 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:48:34.060183 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 23:48:34.060411 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx
125 23:48:34.060577 makedir: /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin
126 23:48:34.060723 makedir: /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/tests
127 23:48:34.060852 makedir: /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/results
128 23:48:34.060998 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-add-keys
129 23:48:34.061175 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-add-sources
130 23:48:34.061371 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-background-process-start
131 23:48:34.061532 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-background-process-stop
132 23:48:34.061725 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-common-functions
133 23:48:34.061852 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-echo-ipv4
134 23:48:34.061978 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-install-packages
135 23:48:34.062100 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-installed-packages
136 23:48:34.062222 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-os-build
137 23:48:34.062343 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-probe-channel
138 23:48:34.062464 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-probe-ip
139 23:48:34.062585 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-target-ip
140 23:48:34.062709 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-target-mac
141 23:48:34.062830 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-target-storage
142 23:48:34.062956 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-case
143 23:48:34.063078 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-event
144 23:48:34.063198 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-feedback
145 23:48:34.063319 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-raise
146 23:48:34.063439 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-reference
147 23:48:34.063561 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-runner
148 23:48:34.063684 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-set
149 23:48:34.063810 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-test-shell
150 23:48:34.063935 Updating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-install-packages (oe)
151 23:48:34.064081 Updating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/bin/lava-installed-packages (oe)
152 23:48:34.064199 Creating /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/environment
153 23:48:34.064296 LAVA metadata
154 23:48:34.064369 - LAVA_JOB_ID=14084309
155 23:48:34.064433 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:48:34.064549 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 23:48:34.064616 skipped lava-vland-overlay
158 23:48:34.064688 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:48:34.064771 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 23:48:34.064875 skipped lava-multinode-overlay
161 23:48:34.065019 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:48:34.065119 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 23:48:34.065200 Loading test definitions
164 23:48:34.065303 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 23:48:34.065392 Using /lava-14084309 at stage 0
166 23:48:34.065699 uuid=14084309_1.5.2.3.1 testdef=None
167 23:48:34.065786 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:48:34.065870 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 23:48:34.066371 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:48:34.066593 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 23:48:34.067189 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:48:34.067416 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 23:48:34.067986 runner path: /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/0/tests/0_cros-ec test_uuid 14084309_1.5.2.3.1
176 23:48:34.068138 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:48:34.068349 Creating lava-test-runner.conf files
179 23:48:34.068412 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084309/lava-overlay-9x5722gx/lava-14084309/0 for stage 0
180 23:48:34.068500 - 0_cros-ec
181 23:48:34.068626 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:48:34.068709 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 23:48:34.075871 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:48:34.075979 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 23:48:34.076064 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:48:34.076147 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:48:34.076233 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 23:48:35.305327 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:48:35.305712 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 23:48:35.305822 extracting modules file /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084309/extract-overlay-ramdisk-g9nosnzr/ramdisk
191 23:48:35.529168 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:48:35.529359 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 23:48:35.529460 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084309/compress-overlay-6podr_jn/overlay-1.5.2.4.tar.gz to ramdisk
194 23:48:35.529531 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084309/compress-overlay-6podr_jn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084309/extract-overlay-ramdisk-g9nosnzr/ramdisk
195 23:48:35.536212 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:48:35.536330 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 23:48:35.536422 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:48:35.536514 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 23:48:35.536597 Building ramdisk /var/lib/lava/dispatcher/tmp/14084309/extract-overlay-ramdisk-g9nosnzr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084309/extract-overlay-ramdisk-g9nosnzr/ramdisk
200 23:48:36.367765 >> 335872 blocks
201 23:48:41.611895 rename /var/lib/lava/dispatcher/tmp/14084309/extract-overlay-ramdisk-g9nosnzr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/ramdisk/ramdisk.cpio.gz
202 23:48:41.612346 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 23:48:41.612478 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 23:48:41.612578 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 23:48:41.612688 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/kernel/Image']
206 23:48:55.757095 Returned 0 in 14 seconds
207 23:48:55.857826 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/kernel/image.itb
208 23:48:56.632034 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:48:56.632388 output: Created: Thu May 30 00:48:56 2024
210 23:48:56.632464 output: Image 0 (kernel-1)
211 23:48:56.632526 output: Description:
212 23:48:56.632588 output: Created: Thu May 30 00:48:56 2024
213 23:48:56.632648 output: Type: Kernel Image
214 23:48:56.632711 output: Compression: lzma compressed
215 23:48:56.632769 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
216 23:48:56.632831 output: Architecture: AArch64
217 23:48:56.632891 output: OS: Linux
218 23:48:56.632992 output: Load Address: 0x00000000
219 23:48:56.633051 output: Entry Point: 0x00000000
220 23:48:56.633108 output: Hash algo: crc32
221 23:48:56.633168 output: Hash value: 907bf91d
222 23:48:56.633224 output: Image 1 (fdt-1)
223 23:48:56.633281 output: Description: mt8192-asurada-spherion-r0
224 23:48:56.633395 output: Created: Thu May 30 00:48:56 2024
225 23:48:56.633520 output: Type: Flat Device Tree
226 23:48:56.633610 output: Compression: uncompressed
227 23:48:56.633711 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:48:56.633798 output: Architecture: AArch64
229 23:48:56.633852 output: Hash algo: crc32
230 23:48:56.633904 output: Hash value: 0f8e4d2e
231 23:48:56.633958 output: Image 2 (ramdisk-1)
232 23:48:56.634010 output: Description: unavailable
233 23:48:56.634063 output: Created: Thu May 30 00:48:56 2024
234 23:48:56.634117 output: Type: RAMDisk Image
235 23:48:56.634171 output: Compression: Unknown Compression
236 23:48:56.634223 output: Data Size: 52136293 Bytes = 50914.35 KiB = 49.72 MiB
237 23:48:56.634277 output: Architecture: AArch64
238 23:48:56.634330 output: OS: Linux
239 23:48:56.634383 output: Load Address: unavailable
240 23:48:56.634436 output: Entry Point: unavailable
241 23:48:56.634489 output: Hash algo: crc32
242 23:48:56.634558 output: Hash value: 1ca635f0
243 23:48:56.634662 output: Default Configuration: 'conf-1'
244 23:48:56.634753 output: Configuration 0 (conf-1)
245 23:48:56.634840 output: Description: mt8192-asurada-spherion-r0
246 23:48:56.634931 output: Kernel: kernel-1
247 23:48:56.634993 output: Init Ramdisk: ramdisk-1
248 23:48:56.635048 output: FDT: fdt-1
249 23:48:56.635102 output: Loadables: kernel-1
250 23:48:56.635155 output:
251 23:48:56.635358 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 23:48:56.635452 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 23:48:56.635563 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 23:48:56.635657 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 23:48:56.635754 No LXC device requested
256 23:48:56.635852 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:48:56.635937 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 23:48:56.636013 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:48:56.636087 Checking files for TFTP limit of 4294967296 bytes.
260 23:48:56.636587 end: 1 tftp-deploy (duration 00:00:26) [common]
261 23:48:56.636695 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:48:56.636787 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:48:56.636911 substitutions:
264 23:48:56.636976 - {DTB}: 14084309/tftp-deploy-w6qgyi4y/dtb/mt8192-asurada-spherion-r0.dtb
265 23:48:56.637038 - {INITRD}: 14084309/tftp-deploy-w6qgyi4y/ramdisk/ramdisk.cpio.gz
266 23:48:56.637097 - {KERNEL}: 14084309/tftp-deploy-w6qgyi4y/kernel/Image
267 23:48:56.637156 - {LAVA_MAC}: None
268 23:48:56.637212 - {PRESEED_CONFIG}: None
269 23:48:56.637267 - {PRESEED_LOCAL}: None
270 23:48:56.637359 - {RAMDISK}: 14084309/tftp-deploy-w6qgyi4y/ramdisk/ramdisk.cpio.gz
271 23:48:56.637415 - {ROOT_PART}: None
272 23:48:56.637470 - {ROOT}: None
273 23:48:56.637524 - {SERVER_IP}: 192.168.201.1
274 23:48:56.637578 - {TEE}: None
275 23:48:56.637632 Parsed boot commands:
276 23:48:56.637685 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:48:56.637860 Parsed boot commands: tftpboot 192.168.201.1 14084309/tftp-deploy-w6qgyi4y/kernel/image.itb 14084309/tftp-deploy-w6qgyi4y/kernel/cmdline
278 23:48:56.637949 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:48:56.638108 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:48:56.638251 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:48:56.638360 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:48:56.638433 Not connected, no need to disconnect.
283 23:48:56.638509 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:48:56.638630 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:48:56.638720 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 23:48:56.642507 Setting prompt string to ['lava-test: # ']
287 23:48:56.642901 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:48:56.643011 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:48:56.643142 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:48:56.643272 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:48:56.643482 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
292 23:49:01.774101 >> Command sent successfully.
293 23:49:01.776512 Returned 0 in 5 seconds
294 23:49:01.876912 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:49:01.877233 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:49:01.877384 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:49:01.877475 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:49:01.877544 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:49:01.877613 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:49:01.878000 [Enter `^Ec?' for help]
302 23:49:02.059935
303 23:49:02.060083
304 23:49:02.060153 F0: 102B 0000
305 23:49:02.060219
306 23:49:02.060282 F3: 1001 0000 [0200]
307 23:49:02.060344
308 23:49:02.063575 F3: 1001 0000
309 23:49:02.063679
310 23:49:02.063746 F7: 102D 0000
311 23:49:02.063808
312 23:49:02.063867 F1: 0000 0000
313 23:49:02.063926
314 23:49:02.067319 V0: 0000 0000 [0001]
315 23:49:02.067408
316 23:49:02.067475 00: 0007 8000
317 23:49:02.067544
318 23:49:02.070797 01: 0000 0000
319 23:49:02.070885
320 23:49:02.070952 BP: 0C00 0209 [0000]
321 23:49:02.071012
322 23:49:02.071071 G0: 1182 0000
323 23:49:02.074593
324 23:49:02.074680 EC: 0000 0021 [4000]
325 23:49:02.074746
326 23:49:02.078264 S7: 0000 0000 [0000]
327 23:49:02.078364
328 23:49:02.078431 CC: 0000 0000 [0001]
329 23:49:02.078493
330 23:49:02.081538 T0: 0000 0040 [010F]
331 23:49:02.081642
332 23:49:02.081717 Jump to BL
333 23:49:02.081780
334 23:49:02.106566
335 23:49:02.106708
336 23:49:02.113480 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:49:02.117525 ARM64: Exception handlers installed.
338 23:49:02.120614 ARM64: Testing exception
339 23:49:02.123922 ARM64: Done test exception
340 23:49:02.131378 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:49:02.141857 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:49:02.148757 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:49:02.158968 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:49:02.165869 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:49:02.172309 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:49:02.183352 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:49:02.190010 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:49:02.209284 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:49:02.212520 WDT: Last reset was cold boot
350 23:49:02.215716 SPI1(PAD0) initialized at 2873684 Hz
351 23:49:02.219337 SPI5(PAD0) initialized at 992727 Hz
352 23:49:02.222527 VBOOT: Loading verstage.
353 23:49:02.229075 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:49:02.232293 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:49:02.235625 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:49:02.239236 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:49:02.246707 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:49:02.253372 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:49:02.264358 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
360 23:49:02.264491
361 23:49:02.264563
362 23:49:02.274122 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:49:02.277632 ARM64: Exception handlers installed.
364 23:49:02.280577 ARM64: Testing exception
365 23:49:02.280674 ARM64: Done test exception
366 23:49:02.287711 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:49:02.290703 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:49:02.305625 Probing TPM: . done!
369 23:49:02.305766 TPM ready after 0 ms
370 23:49:02.312052 Connected to device vid:did:rid of 1ae0:0028:00
371 23:49:02.318501 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
372 23:49:02.322150 Initialized TPM device CR50 revision 0
373 23:49:02.384170 tlcl_send_startup: Startup return code is 0
374 23:49:02.384316 TPM: setup succeeded
375 23:49:02.395002 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:49:02.403646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:49:02.413452 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:49:02.422203 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:49:02.426108 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:49:02.428800 in-header: 03 07 00 00 08 00 00 00
381 23:49:02.432263 in-data: aa e4 47 04 13 02 00 00
382 23:49:02.435646 Chrome EC: UHEPI supported
383 23:49:02.442231 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:49:02.454235 in-header: 03 95 00 00 08 00 00 00
385 23:49:02.457926 in-data: 18 20 20 08 00 00 00 00
386 23:49:02.458034 Phase 1
387 23:49:02.465044 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:49:02.468957 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:49:02.475414 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:49:02.479612 Recovery requested (1009000e)
391 23:49:02.486668 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:49:02.492140 tlcl_extend: response is 0
393 23:49:02.501641 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:49:02.507037 tlcl_extend: response is 0
395 23:49:02.514229 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:49:02.534966 read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps
397 23:49:02.542875 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:49:02.543036
399 23:49:02.543176
400 23:49:02.550123 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:49:02.553517 ARM64: Exception handlers installed.
402 23:49:02.556635 ARM64: Testing exception
403 23:49:02.560119 ARM64: Done test exception
404 23:49:02.579682 pmic_efuse_setting: Set efuses in 11 msecs
405 23:49:02.583002 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:49:02.589850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:49:02.593335 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:49:02.599772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:49:02.603327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:49:02.609599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:49:02.612859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:49:02.619581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:49:02.622771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:49:02.626239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:49:02.633006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:49:02.636666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:49:02.643170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:49:02.646854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:49:02.653713 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:49:02.657734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:49:02.664819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:49:02.669269 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:49:02.675881 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:49:02.680036 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:49:02.687433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:49:02.690782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:49:02.697904 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:49:02.701618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:49:02.709340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:49:02.713488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:49:02.720146 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:49:02.723851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:49:02.728384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:49:02.734998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:49:02.738727 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:49:02.741997 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:49:02.749240 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:49:02.753408 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:49:02.760547 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:49:02.764162 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:49:02.767629 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:49:02.774764 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:49:02.778709 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:49:02.782180 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:49:02.789134 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:49:02.793074 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:49:02.797225 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:49:02.800462 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:49:02.804377 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:49:02.807829 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:49:02.815090 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:49:02.818616 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:49:02.822959 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:49:02.826353 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:49:02.829711 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:49:02.833771 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:49:02.841458 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:49:02.852319 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:49:02.856375 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:49:02.863238 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:49:02.871087 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:49:02.878140 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:49:02.881214 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:49:02.885016 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:49:02.892886 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1a
466 23:49:02.896618 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:49:02.904960 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 23:49:02.908245 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:49:02.917254 [RTC]rtc_get_frequency_meter,154: input=15, output=764
470 23:49:02.927091 [RTC]rtc_get_frequency_meter,154: input=23, output=949
471 23:49:02.936415 [RTC]rtc_get_frequency_meter,154: input=19, output=857
472 23:49:02.945547 [RTC]rtc_get_frequency_meter,154: input=17, output=811
473 23:49:02.955209 [RTC]rtc_get_frequency_meter,154: input=16, output=788
474 23:49:02.964797 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 23:49:02.974806 [RTC]rtc_get_frequency_meter,154: input=17, output=811
476 23:49:02.978356 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 23:49:02.982209 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 23:49:02.985775 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:49:02.993038 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 23:49:02.996842 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:49:03.000617 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 23:49:03.004576 ADC[4]: Raw value=670063 ID=5
483 23:49:03.004672 ADC[3]: Raw value=212549 ID=1
484 23:49:03.008489 RAM Code: 0x51
485 23:49:03.011928 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:49:03.015541 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:49:03.026427 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
488 23:49:03.030017 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
489 23:49:03.033761 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:49:03.037632 in-header: 03 07 00 00 08 00 00 00
491 23:49:03.041083 in-data: aa e4 47 04 13 02 00 00
492 23:49:03.044991 Chrome EC: UHEPI supported
493 23:49:03.048565 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:49:03.054108 in-header: 03 95 00 00 08 00 00 00
495 23:49:03.057799 in-data: 18 20 20 08 00 00 00 00
496 23:49:03.061312 MRC: failed to locate region type 0.
497 23:49:03.068708 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:49:03.072449 DRAM-K: Running full calibration
499 23:49:03.076226 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
500 23:49:03.079691 header.status = 0x0
501 23:49:03.083333 header.version = 0x6 (expected: 0x6)
502 23:49:03.087164 header.size = 0xd00 (expected: 0xd00)
503 23:49:03.087258 header.flags = 0x0
504 23:49:03.094164 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:49:03.111570 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
506 23:49:03.118693 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:49:03.122471 dram_init: ddr_geometry: 0
508 23:49:03.122578 [EMI] MDL number = 0
509 23:49:03.126257 [EMI] Get MDL freq = 0
510 23:49:03.126347 dram_init: ddr_type: 0
511 23:49:03.130251 is_discrete_lpddr4: 1
512 23:49:03.134132 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:49:03.134231
514 23:49:03.134298
515 23:49:03.134359 [Bian_co] ETT version 0.0.0.1
516 23:49:03.137589 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
517 23:49:03.141432
518 23:49:03.144685 dramc_set_vcore_voltage set vcore to 650000
519 23:49:03.144780 Read voltage for 800, 4
520 23:49:03.148607 Vio18 = 0
521 23:49:03.148698 Vcore = 650000
522 23:49:03.148764 Vdram = 0
523 23:49:03.148824 Vddq = 0
524 23:49:03.152349 Vmddr = 0
525 23:49:03.152435 dram_init: config_dvfs: 1
526 23:49:03.159738 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:49:03.163151 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:49:03.167156 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 23:49:03.170486 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 23:49:03.174356 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 23:49:03.177701 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 23:49:03.181466 MEM_TYPE=3, freq_sel=18
533 23:49:03.185565 sv_algorithm_assistance_LP4_1600
534 23:49:03.188851 ============ PULL DRAM RESETB DOWN ============
535 23:49:03.193010 ========== PULL DRAM RESETB DOWN end =========
536 23:49:03.196901 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:49:03.200112 ===================================
538 23:49:03.203756 LPDDR4 DRAM CONFIGURATION
539 23:49:03.207155 ===================================
540 23:49:03.207253 EX_ROW_EN[0] = 0x0
541 23:49:03.210542 EX_ROW_EN[1] = 0x0
542 23:49:03.210633 LP4Y_EN = 0x0
543 23:49:03.214153 WORK_FSP = 0x0
544 23:49:03.214243 WL = 0x2
545 23:49:03.217766 RL = 0x2
546 23:49:03.217856 BL = 0x2
547 23:49:03.221395 RPST = 0x0
548 23:49:03.221480 RD_PRE = 0x0
549 23:49:03.225267 WR_PRE = 0x1
550 23:49:03.225398 WR_PST = 0x0
551 23:49:03.225465 DBI_WR = 0x0
552 23:49:03.228831 DBI_RD = 0x0
553 23:49:03.228917 OTF = 0x1
554 23:49:03.232675 ===================================
555 23:49:03.236147 ===================================
556 23:49:03.239500 ANA top config
557 23:49:03.243134 ===================================
558 23:49:03.243228 DLL_ASYNC_EN = 0
559 23:49:03.246537 ALL_SLAVE_EN = 1
560 23:49:03.249799 NEW_RANK_MODE = 1
561 23:49:03.253040 DLL_IDLE_MODE = 1
562 23:49:03.253173 LP45_APHY_COMB_EN = 1
563 23:49:03.256698 TX_ODT_DIS = 1
564 23:49:03.259992 NEW_8X_MODE = 1
565 23:49:03.263844 ===================================
566 23:49:03.267773 ===================================
567 23:49:03.267895 data_rate = 1600
568 23:49:03.271303 CKR = 1
569 23:49:03.275018 DQ_P2S_RATIO = 8
570 23:49:03.278817 ===================================
571 23:49:03.281924 CA_P2S_RATIO = 8
572 23:49:03.282020 DQ_CA_OPEN = 0
573 23:49:03.285868 DQ_SEMI_OPEN = 0
574 23:49:03.288859 CA_SEMI_OPEN = 0
575 23:49:03.292099 CA_FULL_RATE = 0
576 23:49:03.295222 DQ_CKDIV4_EN = 1
577 23:49:03.299390 CA_CKDIV4_EN = 1
578 23:49:03.299487 CA_PREDIV_EN = 0
579 23:49:03.303096 PH8_DLY = 0
580 23:49:03.307081 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:49:03.307179 DQ_AAMCK_DIV = 4
582 23:49:03.310259 CA_AAMCK_DIV = 4
583 23:49:03.313669 CA_ADMCK_DIV = 4
584 23:49:03.316771 DQ_TRACK_CA_EN = 0
585 23:49:03.320272 CA_PICK = 800
586 23:49:03.323493 CA_MCKIO = 800
587 23:49:03.323585 MCKIO_SEMI = 0
588 23:49:03.327733 PLL_FREQ = 3068
589 23:49:03.330709 DQ_UI_PI_RATIO = 32
590 23:49:03.334843 CA_UI_PI_RATIO = 0
591 23:49:03.338565 ===================================
592 23:49:03.342507 ===================================
593 23:49:03.342609 memory_type:LPDDR4
594 23:49:03.346045 GP_NUM : 10
595 23:49:03.346133 SRAM_EN : 1
596 23:49:03.349734 MD32_EN : 0
597 23:49:03.353357 ===================================
598 23:49:03.353449 [ANA_INIT] >>>>>>>>>>>>>>
599 23:49:03.357675 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:49:03.360710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:49:03.364395 ===================================
602 23:49:03.367570 data_rate = 1600,PCW = 0X7600
603 23:49:03.371130 ===================================
604 23:49:03.374529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:49:03.377646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:49:03.384435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:49:03.387585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:49:03.391099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:49:03.394399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:49:03.397539 [ANA_INIT] flow start
611 23:49:03.400978 [ANA_INIT] PLL >>>>>>>>
612 23:49:03.401072 [ANA_INIT] PLL <<<<<<<<
613 23:49:03.404192 [ANA_INIT] MIDPI >>>>>>>>
614 23:49:03.408087 [ANA_INIT] MIDPI <<<<<<<<
615 23:49:03.411073 [ANA_INIT] DLL >>>>>>>>
616 23:49:03.411166 [ANA_INIT] flow end
617 23:49:03.414429 ============ LP4 DIFF to SE enter ============
618 23:49:03.421131 ============ LP4 DIFF to SE exit ============
619 23:49:03.421241 [ANA_INIT] <<<<<<<<<<<<<
620 23:49:03.424511 [Flow] Enable top DCM control >>>>>
621 23:49:03.428134 [Flow] Enable top DCM control <<<<<
622 23:49:03.431204 Enable DLL master slave shuffle
623 23:49:03.438051 ==============================================================
624 23:49:03.438176 Gating Mode config
625 23:49:03.444743 ==============================================================
626 23:49:03.447634 Config description:
627 23:49:03.454798 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:49:03.461161 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:49:03.468263 SELPH_MODE 0: By rank 1: By Phase
630 23:49:03.474762 ==============================================================
631 23:49:03.474882 GAT_TRACK_EN = 1
632 23:49:03.478085 RX_GATING_MODE = 2
633 23:49:03.481311 RX_GATING_TRACK_MODE = 2
634 23:49:03.484398 SELPH_MODE = 1
635 23:49:03.487951 PICG_EARLY_EN = 1
636 23:49:03.491233 VALID_LAT_VALUE = 1
637 23:49:03.497673 ==============================================================
638 23:49:03.501446 Enter into Gating configuration >>>>
639 23:49:03.504613 Exit from Gating configuration <<<<
640 23:49:03.507781 Enter into DVFS_PRE_config >>>>>
641 23:49:03.517568 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:49:03.521169 Exit from DVFS_PRE_config <<<<<
643 23:49:03.524283 Enter into PICG configuration >>>>
644 23:49:03.527947 Exit from PICG configuration <<<<
645 23:49:03.531006 [RX_INPUT] configuration >>>>>
646 23:49:03.531098 [RX_INPUT] configuration <<<<<
647 23:49:03.537971 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:49:03.544214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:49:03.547803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:49:03.554467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:49:03.560789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:49:03.567770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:49:03.570757 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:49:03.574154 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:49:03.580921 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:49:03.584648 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:49:03.587891 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:49:03.590996 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:49:03.594402 ===================================
660 23:49:03.597759 LPDDR4 DRAM CONFIGURATION
661 23:49:03.601025 ===================================
662 23:49:03.604993 EX_ROW_EN[0] = 0x0
663 23:49:03.605091 EX_ROW_EN[1] = 0x0
664 23:49:03.607574 LP4Y_EN = 0x0
665 23:49:03.607659 WORK_FSP = 0x0
666 23:49:03.610834 WL = 0x2
667 23:49:03.610925 RL = 0x2
668 23:49:03.614296 BL = 0x2
669 23:49:03.614419 RPST = 0x0
670 23:49:03.617778 RD_PRE = 0x0
671 23:49:03.620789 WR_PRE = 0x1
672 23:49:03.620875 WR_PST = 0x0
673 23:49:03.624312 DBI_WR = 0x0
674 23:49:03.624402 DBI_RD = 0x0
675 23:49:03.627563 OTF = 0x1
676 23:49:03.631109 ===================================
677 23:49:03.634447 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:49:03.637780 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:49:03.641048 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:49:03.644566 ===================================
681 23:49:03.647561 LPDDR4 DRAM CONFIGURATION
682 23:49:03.650952 ===================================
683 23:49:03.654618 EX_ROW_EN[0] = 0x10
684 23:49:03.654712 EX_ROW_EN[1] = 0x0
685 23:49:03.658039 LP4Y_EN = 0x0
686 23:49:03.658125 WORK_FSP = 0x0
687 23:49:03.661002 WL = 0x2
688 23:49:03.661090 RL = 0x2
689 23:49:03.664394 BL = 0x2
690 23:49:03.664496 RPST = 0x0
691 23:49:03.667647 RD_PRE = 0x0
692 23:49:03.667750 WR_PRE = 0x1
693 23:49:03.670892 WR_PST = 0x0
694 23:49:03.670981 DBI_WR = 0x0
695 23:49:03.674265 DBI_RD = 0x0
696 23:49:03.674353 OTF = 0x1
697 23:49:03.677846 ===================================
698 23:49:03.684200 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:49:03.689086 nWR fixed to 40
700 23:49:03.692320 [ModeRegInit_LP4] CH0 RK0
701 23:49:03.692414 [ModeRegInit_LP4] CH0 RK1
702 23:49:03.696167 [ModeRegInit_LP4] CH1 RK0
703 23:49:03.699142 [ModeRegInit_LP4] CH1 RK1
704 23:49:03.699252 match AC timing 12
705 23:49:03.705909 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
706 23:49:03.709343 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:49:03.712427 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:49:03.718992 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:49:03.722417 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:49:03.722521 [EMI DOE] emi_dcm 0
711 23:49:03.728969 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:49:03.729071 ==
713 23:49:03.732361 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:49:03.735368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
715 23:49:03.735460 ==
716 23:49:03.742144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:49:03.748930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:49:03.756222 [CA 0] Center 37 (7~68) winsize 62
719 23:49:03.759590 [CA 1] Center 37 (7~68) winsize 62
720 23:49:03.762838 [CA 2] Center 35 (5~66) winsize 62
721 23:49:03.766267 [CA 3] Center 35 (4~66) winsize 63
722 23:49:03.769698 [CA 4] Center 34 (4~65) winsize 62
723 23:49:03.773109 [CA 5] Center 34 (3~65) winsize 63
724 23:49:03.773240
725 23:49:03.776386 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:49:03.776484
727 23:49:03.779420 [CATrainingPosCal] consider 1 rank data
728 23:49:03.782932 u2DelayCellTimex100 = 270/100 ps
729 23:49:03.786453 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
730 23:49:03.789723 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
731 23:49:03.796321 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 23:49:03.799414 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
733 23:49:03.803048 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
734 23:49:03.806448 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
735 23:49:03.806542
736 23:49:03.809527 CA PerBit enable=1, Macro0, CA PI delay=34
737 23:49:03.809614
738 23:49:03.813213 [CBTSetCACLKResult] CA Dly = 34
739 23:49:03.813340 CS Dly: 6 (0~37)
740 23:49:03.813409 ==
741 23:49:03.816282 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:49:03.822926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
743 23:49:03.823028 ==
744 23:49:03.826397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:49:03.832884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:49:03.842031 [CA 0] Center 37 (7~68) winsize 62
747 23:49:03.845250 [CA 1] Center 37 (6~68) winsize 63
748 23:49:03.849030 [CA 2] Center 35 (4~66) winsize 63
749 23:49:03.852237 [CA 3] Center 35 (4~66) winsize 63
750 23:49:03.855531 [CA 4] Center 33 (3~64) winsize 62
751 23:49:03.858849 [CA 5] Center 34 (3~65) winsize 63
752 23:49:03.858943
753 23:49:03.862293 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:49:03.862383
755 23:49:03.865272 [CATrainingPosCal] consider 2 rank data
756 23:49:03.868746 u2DelayCellTimex100 = 270/100 ps
757 23:49:03.872192 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
758 23:49:03.875817 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
759 23:49:03.882304 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 23:49:03.885705 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
761 23:49:03.888866 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
762 23:49:03.892205 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
763 23:49:03.892296
764 23:49:03.895745 CA PerBit enable=1, Macro0, CA PI delay=34
765 23:49:03.895831
766 23:49:03.898876 [CBTSetCACLKResult] CA Dly = 34
767 23:49:03.898963 CS Dly: 6 (0~37)
768 23:49:03.899030
769 23:49:03.902066 ----->DramcWriteLeveling(PI) begin...
770 23:49:03.905862 ==
771 23:49:03.905955 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:49:03.913071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
773 23:49:03.913184 ==
774 23:49:03.913253 Write leveling (Byte 0): 29 => 29
775 23:49:03.916926 Write leveling (Byte 1): 28 => 28
776 23:49:03.920415 DramcWriteLeveling(PI) end<-----
777 23:49:03.920507
778 23:49:03.920573 ==
779 23:49:03.924088 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:49:03.927253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 23:49:03.927343 ==
782 23:49:03.930560 [Gating] SW mode calibration
783 23:49:03.937565 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:49:03.944369 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:49:03.947441 0 6 0 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0)
786 23:49:03.951161 0 6 4 | B1->B0 | 2a2a 2525 | 0 0 | (1 0) (1 0)
787 23:49:03.957910 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 23:49:03.961176 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:49:03.964239 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:49:03.974299 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:49:03.974670 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:49:03.977951 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:49:03.984894 0 7 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
794 23:49:03.988148 0 7 4 | B1->B0 | 3939 4141 | 0 0 | (1 1) (0 0)
795 23:49:03.990986 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
796 23:49:03.997662 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 23:49:04.001029 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 23:49:04.004578 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 23:49:04.010817 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 23:49:04.014312 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 23:49:04.017907 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
802 23:49:04.024385 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
803 23:49:04.027687 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 23:49:04.031439 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 23:49:04.034316 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 23:49:04.040746 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 23:49:04.044428 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 23:49:04.047438 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 23:49:04.054000 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 23:49:04.057513 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 23:49:04.060790 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 23:49:04.067479 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 23:49:04.070631 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 23:49:04.074400 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 23:49:04.081092 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 23:49:04.084180 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 23:49:04.087847 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 23:49:04.094143 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
819 23:49:04.094257 Total UI for P1: 0, mck2ui 16
820 23:49:04.100678 best dqsien dly found for B0: ( 0, 10, 2)
821 23:49:04.100780 Total UI for P1: 0, mck2ui 16
822 23:49:04.107680 best dqsien dly found for B1: ( 0, 10, 2)
823 23:49:04.110783 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
824 23:49:04.114121 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
825 23:49:04.114213
826 23:49:04.117668 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
827 23:49:04.120746 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 23:49:04.124335 [Gating] SW calibration Done
829 23:49:04.124426 ==
830 23:49:04.127480 Dram Type= 6, Freq= 0, CH_0, rank 0
831 23:49:04.130638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
832 23:49:04.130725 ==
833 23:49:04.134358 RX Vref Scan: 0
834 23:49:04.134446
835 23:49:04.134512 RX Vref 0 -> 0, step: 1
836 23:49:04.134572
837 23:49:04.137501 RX Delay -130 -> 252, step: 16
838 23:49:04.140958 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
839 23:49:04.147302 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
840 23:49:04.150861 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
841 23:49:04.154225 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
842 23:49:04.157930 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
843 23:49:04.161039 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
844 23:49:04.164155 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
845 23:49:04.171146 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
846 23:49:04.174603 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
847 23:49:04.178082 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
848 23:49:04.181199 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
849 23:49:04.184710 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
850 23:49:04.191442 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
851 23:49:04.194831 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
852 23:49:04.198207 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
853 23:49:04.201212 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
854 23:49:04.201343 ==
855 23:49:04.204478 Dram Type= 6, Freq= 0, CH_0, rank 0
856 23:49:04.211079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
857 23:49:04.211182 ==
858 23:49:04.211249 DQS Delay:
859 23:49:04.214733 DQS0 = 0, DQS1 = 0
860 23:49:04.214822 DQM Delay:
861 23:49:04.214887 DQM0 = 82, DQM1 = 75
862 23:49:04.217699 DQ Delay:
863 23:49:04.221142 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
864 23:49:04.224425 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
865 23:49:04.227976 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
866 23:49:04.231187 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
867 23:49:04.231278
868 23:49:04.231344
869 23:49:04.231405 ==
870 23:49:04.234177 Dram Type= 6, Freq= 0, CH_0, rank 0
871 23:49:04.238159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
872 23:49:04.238252 ==
873 23:49:04.238318
874 23:49:04.238379
875 23:49:04.241641 TX Vref Scan disable
876 23:49:04.241728 == TX Byte 0 ==
877 23:49:04.247877 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
878 23:49:04.250868 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
879 23:49:04.250962 == TX Byte 1 ==
880 23:49:04.257814 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
881 23:49:04.261034 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
882 23:49:04.261129 ==
883 23:49:04.264456 Dram Type= 6, Freq= 0, CH_0, rank 0
884 23:49:04.267933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
885 23:49:04.268031 ==
886 23:49:04.281819 TX Vref=22, minBit 0, minWin=27, winSum=443
887 23:49:04.285482 TX Vref=24, minBit 1, minWin=27, winSum=445
888 23:49:04.288048 TX Vref=26, minBit 3, minWin=27, winSum=448
889 23:49:04.291430 TX Vref=28, minBit 3, minWin=27, winSum=453
890 23:49:04.294823 TX Vref=30, minBit 0, minWin=28, winSum=454
891 23:49:04.297919 TX Vref=32, minBit 0, minWin=28, winSum=453
892 23:49:04.305152 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
893 23:49:04.305283
894 23:49:04.308589 Final TX Range 1 Vref 30
895 23:49:04.308681
896 23:49:04.308747 ==
897 23:49:04.311972 Dram Type= 6, Freq= 0, CH_0, rank 0
898 23:49:04.315344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 23:49:04.315435 ==
900 23:49:04.315501
901 23:49:04.315562
902 23:49:04.318874 TX Vref Scan disable
903 23:49:04.321794 == TX Byte 0 ==
904 23:49:04.325075 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
905 23:49:04.328435 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
906 23:49:04.332337 == TX Byte 1 ==
907 23:49:04.335318 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
908 23:49:04.338913 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
909 23:49:04.339009
910 23:49:04.342265 [DATLAT]
911 23:49:04.342352 Freq=800, CH0 RK0
912 23:49:04.342419
913 23:49:04.345109 DATLAT Default: 0xa
914 23:49:04.345192 0, 0xFFFF, sum = 0
915 23:49:04.348883 1, 0xFFFF, sum = 0
916 23:49:04.348972 2, 0xFFFF, sum = 0
917 23:49:04.351853 3, 0xFFFF, sum = 0
918 23:49:04.351950 4, 0xFFFF, sum = 0
919 23:49:04.355138 5, 0xFFFF, sum = 0
920 23:49:04.355225 6, 0xFFFF, sum = 0
921 23:49:04.358535 7, 0xFFFF, sum = 0
922 23:49:04.358621 8, 0x0, sum = 1
923 23:49:04.361838 9, 0x0, sum = 2
924 23:49:04.361931 10, 0x0, sum = 3
925 23:49:04.365178 11, 0x0, sum = 4
926 23:49:04.365264 best_step = 9
927 23:49:04.365390
928 23:49:04.365480 ==
929 23:49:04.369030 Dram Type= 6, Freq= 0, CH_0, rank 0
930 23:49:04.371644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
931 23:49:04.375192 ==
932 23:49:04.375281 RX Vref Scan: 1
933 23:49:04.375347
934 23:49:04.378875 Set Vref Range= 32 -> 127
935 23:49:04.378962
936 23:49:04.381730 RX Vref 32 -> 127, step: 1
937 23:49:04.381814
938 23:49:04.381879 RX Delay -111 -> 252, step: 8
939 23:49:04.381943
940 23:49:04.384921 Set Vref, RX VrefLevel [Byte0]: 32
941 23:49:04.388566 [Byte1]: 32
942 23:49:04.392100
943 23:49:04.392188 Set Vref, RX VrefLevel [Byte0]: 33
944 23:49:04.395999 [Byte1]: 33
945 23:49:04.399787
946 23:49:04.399877 Set Vref, RX VrefLevel [Byte0]: 34
947 23:49:04.403305 [Byte1]: 34
948 23:49:04.407578
949 23:49:04.407669 Set Vref, RX VrefLevel [Byte0]: 35
950 23:49:04.410904 [Byte1]: 35
951 23:49:04.415578
952 23:49:04.415670 Set Vref, RX VrefLevel [Byte0]: 36
953 23:49:04.418768 [Byte1]: 36
954 23:49:04.422963
955 23:49:04.423062 Set Vref, RX VrefLevel [Byte0]: 37
956 23:49:04.426230 [Byte1]: 37
957 23:49:04.430414
958 23:49:04.430503 Set Vref, RX VrefLevel [Byte0]: 38
959 23:49:04.433767 [Byte1]: 38
960 23:49:04.438274
961 23:49:04.438372 Set Vref, RX VrefLevel [Byte0]: 39
962 23:49:04.441640 [Byte1]: 39
963 23:49:04.445844
964 23:49:04.445945 Set Vref, RX VrefLevel [Byte0]: 40
965 23:49:04.448997 [Byte1]: 40
966 23:49:04.453442
967 23:49:04.453539 Set Vref, RX VrefLevel [Byte0]: 41
968 23:49:04.456687 [Byte1]: 41
969 23:49:04.461004
970 23:49:04.461098 Set Vref, RX VrefLevel [Byte0]: 42
971 23:49:04.464471 [Byte1]: 42
972 23:49:04.468724
973 23:49:04.468822 Set Vref, RX VrefLevel [Byte0]: 43
974 23:49:04.472363 [Byte1]: 43
975 23:49:04.476515
976 23:49:04.476602 Set Vref, RX VrefLevel [Byte0]: 44
977 23:49:04.479741 [Byte1]: 44
978 23:49:04.484177
979 23:49:04.484277 Set Vref, RX VrefLevel [Byte0]: 45
980 23:49:04.487658 [Byte1]: 45
981 23:49:04.491674
982 23:49:04.491763 Set Vref, RX VrefLevel [Byte0]: 46
983 23:49:04.494894 [Byte1]: 46
984 23:49:04.499288
985 23:49:04.499380 Set Vref, RX VrefLevel [Byte0]: 47
986 23:49:04.502445 [Byte1]: 47
987 23:49:04.507462
988 23:49:04.507562 Set Vref, RX VrefLevel [Byte0]: 48
989 23:49:04.510152 [Byte1]: 48
990 23:49:04.514458
991 23:49:04.514552 Set Vref, RX VrefLevel [Byte0]: 49
992 23:49:04.518177 [Byte1]: 49
993 23:49:04.522164
994 23:49:04.522259 Set Vref, RX VrefLevel [Byte0]: 50
995 23:49:04.525734 [Byte1]: 50
996 23:49:04.529856
997 23:49:04.529944 Set Vref, RX VrefLevel [Byte0]: 51
998 23:49:04.532978 [Byte1]: 51
999 23:49:04.537357
1000 23:49:04.537468 Set Vref, RX VrefLevel [Byte0]: 52
1001 23:49:04.540840 [Byte1]: 52
1002 23:49:04.545379
1003 23:49:04.545473 Set Vref, RX VrefLevel [Byte0]: 53
1004 23:49:04.548472 [Byte1]: 53
1005 23:49:04.552640
1006 23:49:04.552729 Set Vref, RX VrefLevel [Byte0]: 54
1007 23:49:04.556187 [Byte1]: 54
1008 23:49:04.560344
1009 23:49:04.560437 Set Vref, RX VrefLevel [Byte0]: 55
1010 23:49:04.563673 [Byte1]: 55
1011 23:49:04.568215
1012 23:49:04.568323 Set Vref, RX VrefLevel [Byte0]: 56
1013 23:49:04.571339 [Byte1]: 56
1014 23:49:04.576160
1015 23:49:04.576257 Set Vref, RX VrefLevel [Byte0]: 57
1016 23:49:04.579311 [Byte1]: 57
1017 23:49:04.583877
1018 23:49:04.583969 Set Vref, RX VrefLevel [Byte0]: 58
1019 23:49:04.587067 [Byte1]: 58
1020 23:49:04.591087
1021 23:49:04.591181 Set Vref, RX VrefLevel [Byte0]: 59
1022 23:49:04.594755 [Byte1]: 59
1023 23:49:04.598724
1024 23:49:04.598819 Set Vref, RX VrefLevel [Byte0]: 60
1025 23:49:04.602092 [Byte1]: 60
1026 23:49:04.606655
1027 23:49:04.606778 Set Vref, RX VrefLevel [Byte0]: 61
1028 23:49:04.609752 [Byte1]: 61
1029 23:49:04.613711
1030 23:49:04.613802 Set Vref, RX VrefLevel [Byte0]: 62
1031 23:49:04.617281 [Byte1]: 62
1032 23:49:04.621856
1033 23:49:04.621946 Set Vref, RX VrefLevel [Byte0]: 63
1034 23:49:04.625043 [Byte1]: 63
1035 23:49:04.629540
1036 23:49:04.629630 Set Vref, RX VrefLevel [Byte0]: 64
1037 23:49:04.632459 [Byte1]: 64
1038 23:49:04.636786
1039 23:49:04.636899 Set Vref, RX VrefLevel [Byte0]: 65
1040 23:49:04.640127 [Byte1]: 65
1041 23:49:04.644490
1042 23:49:04.644588 Set Vref, RX VrefLevel [Byte0]: 66
1043 23:49:04.647875 [Byte1]: 66
1044 23:49:04.652230
1045 23:49:04.652324 Set Vref, RX VrefLevel [Byte0]: 67
1046 23:49:04.655448 [Byte1]: 67
1047 23:49:04.659642
1048 23:49:04.659731 Set Vref, RX VrefLevel [Byte0]: 68
1049 23:49:04.663157 [Byte1]: 68
1050 23:49:04.667307
1051 23:49:04.667489 Set Vref, RX VrefLevel [Byte0]: 69
1052 23:49:04.670677 [Byte1]: 69
1053 23:49:04.675071
1054 23:49:04.675166 Set Vref, RX VrefLevel [Byte0]: 70
1055 23:49:04.678246 [Byte1]: 70
1056 23:49:04.682712
1057 23:49:04.682812 Set Vref, RX VrefLevel [Byte0]: 71
1058 23:49:04.686095 [Byte1]: 71
1059 23:49:04.690375
1060 23:49:04.690470 Set Vref, RX VrefLevel [Byte0]: 72
1061 23:49:04.693705 [Byte1]: 72
1062 23:49:04.698136
1063 23:49:04.698228 Final RX Vref Byte 0 = 52 to rank0
1064 23:49:04.701475 Final RX Vref Byte 1 = 55 to rank0
1065 23:49:04.704660 Final RX Vref Byte 0 = 52 to rank1
1066 23:49:04.707831 Final RX Vref Byte 1 = 55 to rank1==
1067 23:49:04.711672 Dram Type= 6, Freq= 0, CH_0, rank 0
1068 23:49:04.718003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1069 23:49:04.718107 ==
1070 23:49:04.718174 DQS Delay:
1071 23:49:04.718233 DQS0 = 0, DQS1 = 0
1072 23:49:04.721570 DQM Delay:
1073 23:49:04.721652 DQM0 = 83, DQM1 = 73
1074 23:49:04.724683 DQ Delay:
1075 23:49:04.727933 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1076 23:49:04.728019 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1077 23:49:04.731791 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1078 23:49:04.734769 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1079 23:49:04.737955
1080 23:49:04.738040
1081 23:49:04.744833 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1082 23:49:04.748011 CH0 RK0: MR19=606, MR18=3636
1083 23:49:04.754587 CH0_RK0: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1084 23:49:04.754699
1085 23:49:04.758529 ----->DramcWriteLeveling(PI) begin...
1086 23:49:04.758617 ==
1087 23:49:04.761216 Dram Type= 6, Freq= 0, CH_0, rank 1
1088 23:49:04.764479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1089 23:49:04.764572 ==
1090 23:49:04.767937 Write leveling (Byte 0): 29 => 29
1091 23:49:04.771376 Write leveling (Byte 1): 28 => 28
1092 23:49:04.774532 DramcWriteLeveling(PI) end<-----
1093 23:49:04.774622
1094 23:49:04.774688 ==
1095 23:49:04.777980 Dram Type= 6, Freq= 0, CH_0, rank 1
1096 23:49:04.781678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1097 23:49:04.781769 ==
1098 23:49:04.784515 [Gating] SW mode calibration
1099 23:49:04.791311 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1100 23:49:04.797932 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1101 23:49:04.801146 0 6 0 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
1102 23:49:04.804647 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (1 1) (1 0)
1103 23:49:04.811305 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1104 23:49:04.814680 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1105 23:49:04.817925 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1106 23:49:04.824745 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1107 23:49:04.828030 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 23:49:04.831576 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 23:49:04.838326 0 7 0 | B1->B0 | 2828 3030 | 1 0 | (0 0) (0 0)
1110 23:49:04.841410 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1111 23:49:04.844974 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1112 23:49:04.848282 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1113 23:49:04.854719 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1114 23:49:04.857999 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1115 23:49:04.861474 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 23:49:04.868242 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 23:49:04.871595 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1118 23:49:04.874843 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1119 23:49:04.881200 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1120 23:49:04.885110 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1121 23:49:04.888128 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1122 23:49:04.894805 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1123 23:49:04.898313 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 23:49:04.901558 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 23:49:04.908163 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 23:49:04.911345 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 23:49:04.914721 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 23:49:04.921264 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 23:49:04.924477 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 23:49:04.927883 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 23:49:04.934395 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 23:49:04.938339 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 23:49:04.941091 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1134 23:49:04.947885 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1135 23:49:04.947995 Total UI for P1: 0, mck2ui 16
1136 23:49:04.951136 best dqsien dly found for B0: ( 0, 10, 0)
1137 23:49:04.954523 Total UI for P1: 0, mck2ui 16
1138 23:49:04.958149 best dqsien dly found for B1: ( 0, 10, 0)
1139 23:49:04.961280 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1140 23:49:04.968101 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1141 23:49:04.968221
1142 23:49:04.971063 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1143 23:49:04.974501 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1144 23:49:04.977993 [Gating] SW calibration Done
1145 23:49:04.978079 ==
1146 23:49:04.981521 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 23:49:04.984438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1148 23:49:04.984512 ==
1149 23:49:05.028005 RX Vref Scan: 0
1150 23:49:05.028157
1151 23:49:05.028223 RX Vref 0 -> 0, step: 1
1152 23:49:05.028283
1153 23:49:05.028360 RX Delay -130 -> 252, step: 16
1154 23:49:05.028617 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1155 23:49:05.028698 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1156 23:49:05.028799 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1157 23:49:05.028856 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1158 23:49:05.028923 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1159 23:49:05.028986 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1160 23:49:05.029042 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1161 23:49:05.029111 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1162 23:49:05.029357 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1163 23:49:05.032576 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1164 23:49:05.035787 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1165 23:49:05.039218 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1166 23:49:05.042427 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1167 23:49:05.045769 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1168 23:49:05.052493 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1169 23:49:05.055847 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1170 23:49:05.055939 ==
1171 23:49:05.059111 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 23:49:05.062736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1173 23:49:05.062833 ==
1174 23:49:05.065955 DQS Delay:
1175 23:49:05.066039 DQS0 = 0, DQS1 = 0
1176 23:49:05.066102 DQM Delay:
1177 23:49:05.068967 DQM0 = 83, DQM1 = 74
1178 23:49:05.069054 DQ Delay:
1179 23:49:05.072670 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =69
1180 23:49:05.075929 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1181 23:49:05.078949 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1182 23:49:05.082709 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1183 23:49:05.082794
1184 23:49:05.082858
1185 23:49:05.082916 ==
1186 23:49:05.085668 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 23:49:05.092518 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1188 23:49:05.092615 ==
1189 23:49:05.092680
1190 23:49:05.092738
1191 23:49:05.092795 TX Vref Scan disable
1192 23:49:05.096138 == TX Byte 0 ==
1193 23:49:05.099480 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1194 23:49:05.102963 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1195 23:49:05.106012 == TX Byte 1 ==
1196 23:49:05.109430 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1197 23:49:05.112631 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1198 23:49:05.115838 ==
1199 23:49:05.119248 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 23:49:05.122481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1201 23:49:05.122568 ==
1202 23:49:05.134922 TX Vref=22, minBit 0, minWin=27, winSum=442
1203 23:49:05.138325 TX Vref=24, minBit 0, minWin=28, winSum=453
1204 23:49:05.141624 TX Vref=26, minBit 0, minWin=28, winSum=455
1205 23:49:05.144980 TX Vref=28, minBit 0, minWin=28, winSum=454
1206 23:49:05.148072 TX Vref=30, minBit 2, minWin=28, winSum=458
1207 23:49:05.151483 TX Vref=32, minBit 2, minWin=28, winSum=459
1208 23:49:05.159206 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 32
1209 23:49:05.159326
1210 23:49:05.162582 Final TX Range 1 Vref 32
1211 23:49:05.162670
1212 23:49:05.162734 ==
1213 23:49:05.166311 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 23:49:05.170167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1215 23:49:05.170266 ==
1216 23:49:05.170332
1217 23:49:05.170390
1218 23:49:05.173281 TX Vref Scan disable
1219 23:49:05.173405 == TX Byte 0 ==
1220 23:49:05.180460 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1221 23:49:05.183721 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1222 23:49:05.183812 == TX Byte 1 ==
1223 23:49:05.190492 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1224 23:49:05.193840 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1225 23:49:05.193932
1226 23:49:05.193997 [DATLAT]
1227 23:49:05.197161 Freq=800, CH0 RK1
1228 23:49:05.197245
1229 23:49:05.197342 DATLAT Default: 0x9
1230 23:49:05.200635 0, 0xFFFF, sum = 0
1231 23:49:05.200718 1, 0xFFFF, sum = 0
1232 23:49:05.204020 2, 0xFFFF, sum = 0
1233 23:49:05.204105 3, 0xFFFF, sum = 0
1234 23:49:05.207092 4, 0xFFFF, sum = 0
1235 23:49:05.207188 5, 0xFFFF, sum = 0
1236 23:49:05.210676 6, 0xFFFF, sum = 0
1237 23:49:05.210759 7, 0xFFFF, sum = 0
1238 23:49:05.213987 8, 0x0, sum = 1
1239 23:49:05.214072 9, 0x0, sum = 2
1240 23:49:05.217545 10, 0x0, sum = 3
1241 23:49:05.217630 11, 0x0, sum = 4
1242 23:49:05.217696 best_step = 9
1243 23:49:05.220441
1244 23:49:05.220522 ==
1245 23:49:05.223724 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 23:49:05.227103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1247 23:49:05.227187 ==
1248 23:49:05.227252 RX Vref Scan: 0
1249 23:49:05.227311
1250 23:49:05.230595 RX Vref 0 -> 0, step: 1
1251 23:49:05.230678
1252 23:49:05.233917 RX Delay -111 -> 252, step: 8
1253 23:49:05.237114 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1254 23:49:05.243746 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1255 23:49:05.247392 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1256 23:49:05.250567 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1257 23:49:05.254431 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1258 23:49:05.257258 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1259 23:49:05.263701 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1260 23:49:05.267503 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1261 23:49:05.270350 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1262 23:49:05.273637 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1263 23:49:05.277349 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1264 23:49:05.283808 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1265 23:49:05.287096 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1266 23:49:05.290357 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1267 23:49:05.293756 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1268 23:49:05.297358 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1269 23:49:05.300736 ==
1270 23:49:05.300825 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 23:49:05.307433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1272 23:49:05.307540 ==
1273 23:49:05.307607 DQS Delay:
1274 23:49:05.310777 DQS0 = 0, DQS1 = 0
1275 23:49:05.310860 DQM Delay:
1276 23:49:05.313645 DQM0 = 85, DQM1 = 74
1277 23:49:05.313727 DQ Delay:
1278 23:49:05.317162 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1279 23:49:05.320574 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1280 23:49:05.323767 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1281 23:49:05.327288 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1282 23:49:05.327380
1283 23:49:05.327446
1284 23:49:05.333928 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1285 23:49:05.337648 CH0 RK1: MR19=606, MR18=4242
1286 23:49:05.343793 CH0_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1287 23:49:05.347194 [RxdqsGatingPostProcess] freq 800
1288 23:49:05.350562 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1289 23:49:05.353788 Pre-setting of DQS Precalculation
1290 23:49:05.360511 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1291 23:49:05.360615 ==
1292 23:49:05.363583 Dram Type= 6, Freq= 0, CH_1, rank 0
1293 23:49:05.367182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1294 23:49:05.367280 ==
1295 23:49:05.373917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1296 23:49:05.380295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1297 23:49:05.387726 [CA 0] Center 37 (6~68) winsize 63
1298 23:49:05.390879 [CA 1] Center 36 (6~67) winsize 62
1299 23:49:05.394317 [CA 2] Center 34 (4~65) winsize 62
1300 23:49:05.397691 [CA 3] Center 34 (4~65) winsize 62
1301 23:49:05.400810 [CA 4] Center 33 (3~64) winsize 62
1302 23:49:05.404297 [CA 5] Center 33 (3~64) winsize 62
1303 23:49:05.404416
1304 23:49:05.407457 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1305 23:49:05.407542
1306 23:49:05.410971 [CATrainingPosCal] consider 1 rank data
1307 23:49:05.414156 u2DelayCellTimex100 = 270/100 ps
1308 23:49:05.417782 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1309 23:49:05.420988 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1310 23:49:05.427916 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1311 23:49:05.430730 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1312 23:49:05.434274 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1313 23:49:05.437418 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1314 23:49:05.437506
1315 23:49:05.440651 CA PerBit enable=1, Macro0, CA PI delay=33
1316 23:49:05.440762
1317 23:49:05.444643 [CBTSetCACLKResult] CA Dly = 33
1318 23:49:05.444727 CS Dly: 5 (0~36)
1319 23:49:05.447685 ==
1320 23:49:05.447768 Dram Type= 6, Freq= 0, CH_1, rank 1
1321 23:49:05.454049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1322 23:49:05.454141 ==
1323 23:49:05.457216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1324 23:49:05.464196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1325 23:49:05.473279 [CA 0] Center 37 (6~68) winsize 63
1326 23:49:05.477014 [CA 1] Center 37 (6~68) winsize 63
1327 23:49:05.479965 [CA 2] Center 34 (4~65) winsize 62
1328 23:49:05.483561 [CA 3] Center 34 (4~65) winsize 62
1329 23:49:05.486706 [CA 4] Center 33 (3~64) winsize 62
1330 23:49:05.489934 [CA 5] Center 33 (3~64) winsize 62
1331 23:49:05.490029
1332 23:49:05.493449 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1333 23:49:05.493532
1334 23:49:05.496765 [CATrainingPosCal] consider 2 rank data
1335 23:49:05.499866 u2DelayCellTimex100 = 270/100 ps
1336 23:49:05.503238 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1337 23:49:05.506681 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1338 23:49:05.513197 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1339 23:49:05.517145 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1340 23:49:05.519910 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1341 23:49:05.523117 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1342 23:49:05.523204
1343 23:49:05.526581 CA PerBit enable=1, Macro0, CA PI delay=33
1344 23:49:05.526665
1345 23:49:05.530124 [CBTSetCACLKResult] CA Dly = 33
1346 23:49:05.530207 CS Dly: 5 (0~36)
1347 23:49:05.530271
1348 23:49:05.533684 ----->DramcWriteLeveling(PI) begin...
1349 23:49:05.536594 ==
1350 23:49:05.540022 Dram Type= 6, Freq= 0, CH_1, rank 0
1351 23:49:05.543294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1352 23:49:05.543385 ==
1353 23:49:05.547028 Write leveling (Byte 0): 25 => 25
1354 23:49:05.550139 Write leveling (Byte 1): 25 => 25
1355 23:49:05.553299 DramcWriteLeveling(PI) end<-----
1356 23:49:05.553384
1357 23:49:05.553454 ==
1358 23:49:05.556522 Dram Type= 6, Freq= 0, CH_1, rank 0
1359 23:49:05.559964 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1360 23:49:05.560048 ==
1361 23:49:05.563314 [Gating] SW mode calibration
1362 23:49:05.569579 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1363 23:49:05.573255 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1364 23:49:05.579840 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1365 23:49:05.583229 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1366 23:49:05.586702 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1367 23:49:05.593165 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1368 23:49:05.596713 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1369 23:49:05.600146 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1370 23:49:05.606609 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 23:49:05.609760 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1372 23:49:05.613599 0 7 0 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0)
1373 23:49:05.620206 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1374 23:49:05.623119 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1375 23:49:05.626277 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1376 23:49:05.633554 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1377 23:49:05.636803 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1378 23:49:05.639611 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1379 23:49:05.646594 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1380 23:49:05.649753 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1381 23:49:05.653103 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1382 23:49:05.660033 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1383 23:49:05.662976 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1384 23:49:05.666298 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1385 23:49:05.669775 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 23:49:05.676332 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 23:49:05.679507 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 23:49:05.683084 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 23:49:05.689823 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 23:49:05.693129 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 23:49:05.696573 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 23:49:05.702924 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 23:49:05.706769 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 23:49:05.710033 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 23:49:05.716559 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1396 23:49:05.719599 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1397 23:49:05.723251 Total UI for P1: 0, mck2ui 16
1398 23:49:05.726180 best dqsien dly found for B0: ( 0, 9, 28)
1399 23:49:05.729664 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1400 23:49:05.732833 Total UI for P1: 0, mck2ui 16
1401 23:49:05.736184 best dqsien dly found for B1: ( 0, 10, 0)
1402 23:49:05.739592 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1403 23:49:05.743310 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1404 23:49:05.743400
1405 23:49:05.749639 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1406 23:49:05.753128 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1407 23:49:05.753248 [Gating] SW calibration Done
1408 23:49:05.756331 ==
1409 23:49:05.759524 Dram Type= 6, Freq= 0, CH_1, rank 0
1410 23:49:05.763026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1411 23:49:05.763113 ==
1412 23:49:05.763179 RX Vref Scan: 0
1413 23:49:05.763238
1414 23:49:05.766341 RX Vref 0 -> 0, step: 1
1415 23:49:05.766424
1416 23:49:05.769585 RX Delay -130 -> 252, step: 16
1417 23:49:05.773140 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1418 23:49:05.776703 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1419 23:49:05.779923 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1420 23:49:05.786723 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1421 23:49:05.789661 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1422 23:49:05.793191 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1423 23:49:05.796378 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1424 23:49:05.799874 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1425 23:49:05.806507 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1426 23:49:05.809685 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1427 23:49:05.813159 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1428 23:49:05.817118 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1429 23:49:05.820239 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1430 23:49:05.824236 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1431 23:49:05.827637 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1432 23:49:05.834823 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1433 23:49:05.834936 ==
1434 23:49:05.839055 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 23:49:05.842661 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1436 23:49:05.842757 ==
1437 23:49:05.842821 DQS Delay:
1438 23:49:05.846285 DQS0 = 0, DQS1 = 0
1439 23:49:05.846377 DQM Delay:
1440 23:49:05.846442 DQM0 = 85, DQM1 = 74
1441 23:49:05.850043 DQ Delay:
1442 23:49:05.850130 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1443 23:49:05.853186 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1444 23:49:05.856568 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1445 23:49:05.860056 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1446 23:49:05.860145
1447 23:49:05.860208
1448 23:49:05.860266 ==
1449 23:49:05.863096 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 23:49:05.869765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1451 23:49:05.869872 ==
1452 23:49:05.869940
1453 23:49:05.869998
1454 23:49:05.870053 TX Vref Scan disable
1455 23:49:05.874318 == TX Byte 0 ==
1456 23:49:05.877326 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1457 23:49:05.880762 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1458 23:49:05.883724 == TX Byte 1 ==
1459 23:49:05.887072 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1460 23:49:05.890911 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1461 23:49:05.893859 ==
1462 23:49:05.897038 Dram Type= 6, Freq= 0, CH_1, rank 0
1463 23:49:05.900667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1464 23:49:05.900755 ==
1465 23:49:05.913061 TX Vref=22, minBit 3, minWin=27, winSum=447
1466 23:49:05.915768 TX Vref=24, minBit 3, minWin=27, winSum=450
1467 23:49:05.919604 TX Vref=26, minBit 3, minWin=27, winSum=453
1468 23:49:05.922766 TX Vref=28, minBit 0, minWin=28, winSum=457
1469 23:49:05.925745 TX Vref=30, minBit 1, minWin=28, winSum=461
1470 23:49:05.929185 TX Vref=32, minBit 9, minWin=27, winSum=454
1471 23:49:05.935882 [TxChooseVref] Worse bit 1, Min win 28, Win sum 461, Final Vref 30
1472 23:49:05.935989
1473 23:49:05.939033 Final TX Range 1 Vref 30
1474 23:49:05.939185
1475 23:49:05.939251 ==
1476 23:49:05.942384 Dram Type= 6, Freq= 0, CH_1, rank 0
1477 23:49:05.945872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1478 23:49:05.945960 ==
1479 23:49:05.946027
1480 23:49:05.949236
1481 23:49:05.949387 TX Vref Scan disable
1482 23:49:05.952465 == TX Byte 0 ==
1483 23:49:05.955746 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1484 23:49:05.962350 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1485 23:49:05.962455 == TX Byte 1 ==
1486 23:49:05.965729 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1487 23:49:05.969172 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1488 23:49:05.972451
1489 23:49:05.972549 [DATLAT]
1490 23:49:05.972614 Freq=800, CH1 RK0
1491 23:49:05.972673
1492 23:49:05.975771 DATLAT Default: 0xa
1493 23:49:05.975879 0, 0xFFFF, sum = 0
1494 23:49:05.978897 1, 0xFFFF, sum = 0
1495 23:49:05.978982 2, 0xFFFF, sum = 0
1496 23:49:05.982271 3, 0xFFFF, sum = 0
1497 23:49:05.982358 4, 0xFFFF, sum = 0
1498 23:49:05.985806 5, 0xFFFF, sum = 0
1499 23:49:05.988936 6, 0xFFFF, sum = 0
1500 23:49:05.989024 7, 0xFFFF, sum = 0
1501 23:49:05.992169 8, 0x0, sum = 1
1502 23:49:05.992256 9, 0x0, sum = 2
1503 23:49:05.992358 10, 0x0, sum = 3
1504 23:49:05.995439 11, 0x0, sum = 4
1505 23:49:05.995522 best_step = 9
1506 23:49:05.995586
1507 23:49:05.995644 ==
1508 23:49:05.999196 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 23:49:06.005563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1510 23:49:06.005664 ==
1511 23:49:06.005730 RX Vref Scan: 1
1512 23:49:06.005788
1513 23:49:06.009142 Set Vref Range= 32 -> 127
1514 23:49:06.009259
1515 23:49:06.012511 RX Vref 32 -> 127, step: 1
1516 23:49:06.012595
1517 23:49:06.015460 RX Delay -111 -> 252, step: 8
1518 23:49:06.015567
1519 23:49:06.018891 Set Vref, RX VrefLevel [Byte0]: 32
1520 23:49:06.022390 [Byte1]: 32
1521 23:49:06.022523
1522 23:49:06.025170 Set Vref, RX VrefLevel [Byte0]: 33
1523 23:49:06.029159 [Byte1]: 33
1524 23:49:06.029272
1525 23:49:06.032253 Set Vref, RX VrefLevel [Byte0]: 34
1526 23:49:06.035232 [Byte1]: 34
1527 23:49:06.038566
1528 23:49:06.038652 Set Vref, RX VrefLevel [Byte0]: 35
1529 23:49:06.041818 [Byte1]: 35
1530 23:49:06.046437
1531 23:49:06.046541 Set Vref, RX VrefLevel [Byte0]: 36
1532 23:49:06.049754 [Byte1]: 36
1533 23:49:06.054038
1534 23:49:06.054127 Set Vref, RX VrefLevel [Byte0]: 37
1535 23:49:06.057126 [Byte1]: 37
1536 23:49:06.061589
1537 23:49:06.061704 Set Vref, RX VrefLevel [Byte0]: 38
1538 23:49:06.064762 [Byte1]: 38
1539 23:49:06.069468
1540 23:49:06.069567 Set Vref, RX VrefLevel [Byte0]: 39
1541 23:49:06.072642 [Byte1]: 39
1542 23:49:06.077045
1543 23:49:06.077141 Set Vref, RX VrefLevel [Byte0]: 40
1544 23:49:06.080082 [Byte1]: 40
1545 23:49:06.084740
1546 23:49:06.084835 Set Vref, RX VrefLevel [Byte0]: 41
1547 23:49:06.087804 [Byte1]: 41
1548 23:49:06.092141
1549 23:49:06.092232 Set Vref, RX VrefLevel [Byte0]: 42
1550 23:49:06.095501 [Byte1]: 42
1551 23:49:06.099998
1552 23:49:06.100094 Set Vref, RX VrefLevel [Byte0]: 43
1553 23:49:06.103093 [Byte1]: 43
1554 23:49:06.107637
1555 23:49:06.107736 Set Vref, RX VrefLevel [Byte0]: 44
1556 23:49:06.111268 [Byte1]: 44
1557 23:49:06.115146
1558 23:49:06.115234 Set Vref, RX VrefLevel [Byte0]: 45
1559 23:49:06.118804 [Byte1]: 45
1560 23:49:06.123094
1561 23:49:06.123183 Set Vref, RX VrefLevel [Byte0]: 46
1562 23:49:06.126319 [Byte1]: 46
1563 23:49:06.130386
1564 23:49:06.130501 Set Vref, RX VrefLevel [Byte0]: 47
1565 23:49:06.133932 [Byte1]: 47
1566 23:49:06.138016
1567 23:49:06.138110 Set Vref, RX VrefLevel [Byte0]: 48
1568 23:49:06.141382 [Byte1]: 48
1569 23:49:06.145882
1570 23:49:06.145975 Set Vref, RX VrefLevel [Byte0]: 49
1571 23:49:06.149160 [Byte1]: 49
1572 23:49:06.153571
1573 23:49:06.153665 Set Vref, RX VrefLevel [Byte0]: 50
1574 23:49:06.156750 [Byte1]: 50
1575 23:49:06.161412
1576 23:49:06.161508 Set Vref, RX VrefLevel [Byte0]: 51
1577 23:49:06.164407 [Byte1]: 51
1578 23:49:06.168800
1579 23:49:06.168915 Set Vref, RX VrefLevel [Byte0]: 52
1580 23:49:06.171957 [Byte1]: 52
1581 23:49:06.176672
1582 23:49:06.176776 Set Vref, RX VrefLevel [Byte0]: 53
1583 23:49:06.179713 [Byte1]: 53
1584 23:49:06.183849
1585 23:49:06.187528 Set Vref, RX VrefLevel [Byte0]: 54
1586 23:49:06.187623 [Byte1]: 54
1587 23:49:06.191998
1588 23:49:06.192089 Set Vref, RX VrefLevel [Byte0]: 55
1589 23:49:06.195121 [Byte1]: 55
1590 23:49:06.199467
1591 23:49:06.199557 Set Vref, RX VrefLevel [Byte0]: 56
1592 23:49:06.202928 [Byte1]: 56
1593 23:49:06.206835
1594 23:49:06.206930 Set Vref, RX VrefLevel [Byte0]: 57
1595 23:49:06.210708 [Byte1]: 57
1596 23:49:06.214589
1597 23:49:06.214680 Set Vref, RX VrefLevel [Byte0]: 58
1598 23:49:06.217939 [Byte1]: 58
1599 23:49:06.222271
1600 23:49:06.222356 Set Vref, RX VrefLevel [Byte0]: 59
1601 23:49:06.225710 [Byte1]: 59
1602 23:49:06.230197
1603 23:49:06.230289 Set Vref, RX VrefLevel [Byte0]: 60
1604 23:49:06.233483 [Byte1]: 60
1605 23:49:06.237674
1606 23:49:06.237764 Set Vref, RX VrefLevel [Byte0]: 61
1607 23:49:06.241068 [Byte1]: 61
1608 23:49:06.245419
1609 23:49:06.245582 Set Vref, RX VrefLevel [Byte0]: 62
1610 23:49:06.248561 [Byte1]: 62
1611 23:49:06.253125
1612 23:49:06.253251 Set Vref, RX VrefLevel [Byte0]: 63
1613 23:49:06.256557 [Byte1]: 63
1614 23:49:06.260711
1615 23:49:06.260842 Set Vref, RX VrefLevel [Byte0]: 64
1616 23:49:06.263961 [Byte1]: 64
1617 23:49:06.268038
1618 23:49:06.268180 Set Vref, RX VrefLevel [Byte0]: 65
1619 23:49:06.271422 [Byte1]: 65
1620 23:49:06.275901
1621 23:49:06.276042 Set Vref, RX VrefLevel [Byte0]: 66
1622 23:49:06.278989 [Byte1]: 66
1623 23:49:06.283382
1624 23:49:06.283509 Set Vref, RX VrefLevel [Byte0]: 67
1625 23:49:06.286604 [Byte1]: 67
1626 23:49:06.290911
1627 23:49:06.291005 Set Vref, RX VrefLevel [Byte0]: 68
1628 23:49:06.294421 [Byte1]: 68
1629 23:49:06.298809
1630 23:49:06.298902 Set Vref, RX VrefLevel [Byte0]: 69
1631 23:49:06.301904 [Byte1]: 69
1632 23:49:06.306313
1633 23:49:06.306404 Set Vref, RX VrefLevel [Byte0]: 70
1634 23:49:06.309854 [Byte1]: 70
1635 23:49:06.314263
1636 23:49:06.314352 Set Vref, RX VrefLevel [Byte0]: 71
1637 23:49:06.317154 [Byte1]: 71
1638 23:49:06.321701
1639 23:49:06.321795 Set Vref, RX VrefLevel [Byte0]: 72
1640 23:49:06.324862 [Byte1]: 72
1641 23:49:06.329162
1642 23:49:06.329292 Set Vref, RX VrefLevel [Byte0]: 73
1643 23:49:06.332288 [Byte1]: 73
1644 23:49:06.337101
1645 23:49:06.337196 Set Vref, RX VrefLevel [Byte0]: 74
1646 23:49:06.340235 [Byte1]: 74
1647 23:49:06.344573
1648 23:49:06.344674 Set Vref, RX VrefLevel [Byte0]: 75
1649 23:49:06.348030 [Byte1]: 75
1650 23:49:06.352290
1651 23:49:06.352390 Set Vref, RX VrefLevel [Byte0]: 76
1652 23:49:06.355425 [Byte1]: 76
1653 23:49:06.359566
1654 23:49:06.359702 Final RX Vref Byte 0 = 58 to rank0
1655 23:49:06.363260 Final RX Vref Byte 1 = 54 to rank0
1656 23:49:06.366784 Final RX Vref Byte 0 = 58 to rank1
1657 23:49:06.369903 Final RX Vref Byte 1 = 54 to rank1==
1658 23:49:06.373423 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 23:49:06.379638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1660 23:49:06.379796 ==
1661 23:49:06.379916 DQS Delay:
1662 23:49:06.380025 DQS0 = 0, DQS1 = 0
1663 23:49:06.383180 DQM Delay:
1664 23:49:06.383284 DQM0 = 81, DQM1 = 75
1665 23:49:06.386548 DQ Delay:
1666 23:49:06.390152 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1667 23:49:06.390267 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1668 23:49:06.393038 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1669 23:49:06.396794 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1670 23:49:06.396912
1671 23:49:06.397003
1672 23:49:06.407087 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1673 23:49:06.410667 CH1 RK0: MR19=606, MR18=4F4F
1674 23:49:06.413789 CH1_RK0: MR19=0x606, MR18=0x4F4F, DQSOSC=390, MR23=63, INC=97, DEC=64
1675 23:49:06.417150
1676 23:49:06.420535 ----->DramcWriteLeveling(PI) begin...
1677 23:49:06.420624 ==
1678 23:49:06.423733 Dram Type= 6, Freq= 0, CH_1, rank 1
1679 23:49:06.427176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1680 23:49:06.427305 ==
1681 23:49:06.430377 Write leveling (Byte 0): 26 => 26
1682 23:49:06.433505 Write leveling (Byte 1): 26 => 26
1683 23:49:06.436747 DramcWriteLeveling(PI) end<-----
1684 23:49:06.436884
1685 23:49:06.436999 ==
1686 23:49:06.440108 Dram Type= 6, Freq= 0, CH_1, rank 1
1687 23:49:06.443766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1688 23:49:06.443878 ==
1689 23:49:06.447002 [Gating] SW mode calibration
1690 23:49:06.453993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1691 23:49:06.460847 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1692 23:49:06.463839 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1693 23:49:06.467355 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1694 23:49:06.470410 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1695 23:49:06.476961 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 23:49:06.480574 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 23:49:06.483812 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 23:49:06.490189 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 23:49:06.494230 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1700 23:49:06.496935 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1701 23:49:06.504021 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1702 23:49:06.507024 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 23:49:06.510241 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 23:49:06.516965 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 23:49:06.520401 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 23:49:06.523994 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1707 23:49:06.530425 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1708 23:49:06.533561 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1709 23:49:06.536868 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 23:49:06.543766 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 23:49:06.547016 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 23:49:06.550532 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 23:49:06.557456 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 23:49:06.560500 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 23:49:06.563765 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 23:49:06.567172 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 23:49:06.573784 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 23:49:06.576957 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 23:49:06.580326 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 23:49:06.586894 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 23:49:06.591047 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 23:49:06.593387 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 23:49:06.600043 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1724 23:49:06.603757 Total UI for P1: 0, mck2ui 16
1725 23:49:06.606737 best dqsien dly found for B0: ( 0, 9, 26)
1726 23:49:06.610282 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1727 23:49:06.613395 Total UI for P1: 0, mck2ui 16
1728 23:49:06.616627 best dqsien dly found for B1: ( 0, 9, 28)
1729 23:49:06.620131 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1730 23:49:06.623248 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1731 23:49:06.623352
1732 23:49:06.626581 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1733 23:49:06.630287 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1734 23:49:06.633252 [Gating] SW calibration Done
1735 23:49:06.633404 ==
1736 23:49:06.636543 Dram Type= 6, Freq= 0, CH_1, rank 1
1737 23:49:06.643155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1738 23:49:06.643338 ==
1739 23:49:06.643509 RX Vref Scan: 0
1740 23:49:06.643610
1741 23:49:06.646556 RX Vref 0 -> 0, step: 1
1742 23:49:06.646664
1743 23:49:06.650125 RX Delay -130 -> 252, step: 16
1744 23:49:06.653239 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1745 23:49:06.656464 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1746 23:49:06.660077 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1747 23:49:06.666771 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1748 23:49:06.670037 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1749 23:49:06.673183 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1750 23:49:06.676359 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1751 23:49:06.679736 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1752 23:49:06.686466 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1753 23:49:06.689891 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1754 23:49:06.692983 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1755 23:49:06.696591 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1756 23:49:06.699717 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1757 23:49:06.706114 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1758 23:49:06.709622 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1759 23:49:06.713074 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1760 23:49:06.713197 ==
1761 23:49:06.716423 Dram Type= 6, Freq= 0, CH_1, rank 1
1762 23:49:06.719869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1763 23:49:06.719978 ==
1764 23:49:06.723145 DQS Delay:
1765 23:49:06.723267 DQS0 = 0, DQS1 = 0
1766 23:49:06.726230 DQM Delay:
1767 23:49:06.726338 DQM0 = 85, DQM1 = 73
1768 23:49:06.726430 DQ Delay:
1769 23:49:06.729712 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1770 23:49:06.732875 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1771 23:49:06.736145 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1772 23:49:06.739633 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1773 23:49:06.739756
1774 23:49:06.739848
1775 23:49:06.743020 ==
1776 23:49:06.746566 Dram Type= 6, Freq= 0, CH_1, rank 1
1777 23:49:06.749604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1778 23:49:06.749696 ==
1779 23:49:06.749761
1780 23:49:06.749819
1781 23:49:06.753093 TX Vref Scan disable
1782 23:49:06.753177 == TX Byte 0 ==
1783 23:49:06.756323 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1784 23:49:06.762957 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1785 23:49:06.763066 == TX Byte 1 ==
1786 23:49:06.766204 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1787 23:49:06.773197 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1788 23:49:06.773320 ==
1789 23:49:06.776496 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 23:49:06.779748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1791 23:49:06.779835 ==
1792 23:49:06.792380 TX Vref=22, minBit 0, minWin=27, winSum=449
1793 23:49:06.796046 TX Vref=24, minBit 0, minWin=27, winSum=449
1794 23:49:06.799388 TX Vref=26, minBit 0, minWin=27, winSum=454
1795 23:49:06.802542 TX Vref=28, minBit 9, minWin=27, winSum=453
1796 23:49:06.806261 TX Vref=30, minBit 9, minWin=27, winSum=456
1797 23:49:06.809377 TX Vref=32, minBit 9, minWin=27, winSum=453
1798 23:49:06.816169 [TxChooseVref] Worse bit 9, Min win 27, Win sum 456, Final Vref 30
1799 23:49:06.816281
1800 23:49:06.819089 Final TX Range 1 Vref 30
1801 23:49:06.819176
1802 23:49:06.819239 ==
1803 23:49:06.822424 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 23:49:06.825777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1805 23:49:06.825859 ==
1806 23:49:06.825922
1807 23:49:06.829189
1808 23:49:06.829293 TX Vref Scan disable
1809 23:49:06.832566 == TX Byte 0 ==
1810 23:49:06.835953 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1811 23:49:06.839493 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1812 23:49:06.842434 == TX Byte 1 ==
1813 23:49:06.845815 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1814 23:49:06.849233 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1815 23:49:06.852412
1816 23:49:06.852503 [DATLAT]
1817 23:49:06.852567 Freq=800, CH1 RK1
1818 23:49:06.852627
1819 23:49:06.855674 DATLAT Default: 0x9
1820 23:49:06.855747 0, 0xFFFF, sum = 0
1821 23:49:06.859497 1, 0xFFFF, sum = 0
1822 23:49:06.859586 2, 0xFFFF, sum = 0
1823 23:49:06.862382 3, 0xFFFF, sum = 0
1824 23:49:06.862470 4, 0xFFFF, sum = 0
1825 23:49:06.865778 5, 0xFFFF, sum = 0
1826 23:49:06.869274 6, 0xFFFF, sum = 0
1827 23:49:06.869405 7, 0xFFFF, sum = 0
1828 23:49:06.869470 8, 0x0, sum = 1
1829 23:49:06.872501 9, 0x0, sum = 2
1830 23:49:06.872593 10, 0x0, sum = 3
1831 23:49:06.875781 11, 0x0, sum = 4
1832 23:49:06.875867 best_step = 9
1833 23:49:06.875930
1834 23:49:06.875988 ==
1835 23:49:06.879103 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 23:49:06.885774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1837 23:49:06.885882 ==
1838 23:49:06.885950 RX Vref Scan: 0
1839 23:49:06.886017
1840 23:49:06.889420 RX Vref 0 -> 0, step: 1
1841 23:49:06.889504
1842 23:49:06.892291 RX Delay -111 -> 252, step: 8
1843 23:49:06.895737 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1844 23:49:06.899104 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
1845 23:49:06.905772 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1846 23:49:06.909261 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1847 23:49:06.912274 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1848 23:49:06.915637 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1849 23:49:06.919119 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1850 23:49:06.925933 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1851 23:49:06.929063 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1852 23:49:06.932364 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1853 23:49:06.935702 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1854 23:49:06.938981 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1855 23:49:06.945887 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1856 23:49:06.949735 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1857 23:49:06.952341 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1858 23:49:06.956027 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1859 23:49:06.956117 ==
1860 23:49:06.959390 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 23:49:06.962410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1862 23:49:06.965969 ==
1863 23:49:06.966057 DQS Delay:
1864 23:49:06.966121 DQS0 = 0, DQS1 = 0
1865 23:49:06.968908 DQM Delay:
1866 23:49:06.968989 DQM0 = 84, DQM1 = 74
1867 23:49:06.972419 DQ Delay:
1868 23:49:06.972509 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =80
1869 23:49:06.975697 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1870 23:49:06.979268 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1871 23:49:06.982297 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1872 23:49:06.985733
1873 23:49:06.985826
1874 23:49:06.992695 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1875 23:49:06.995512 CH1 RK1: MR19=606, MR18=4040
1876 23:49:07.002399 CH1_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63
1877 23:49:07.005605 [RxdqsGatingPostProcess] freq 800
1878 23:49:07.009048 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1879 23:49:07.012366 Pre-setting of DQS Precalculation
1880 23:49:07.015673 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1881 23:49:07.025763 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1882 23:49:07.032363 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1883 23:49:07.032479
1884 23:49:07.032543
1885 23:49:07.035497 [Calibration Summary] 1600 Mbps
1886 23:49:07.035580 CH 0, Rank 0
1887 23:49:07.039036 SW Impedance : PASS
1888 23:49:07.039120 DUTY Scan : NO K
1889 23:49:07.042122 ZQ Calibration : PASS
1890 23:49:07.045281 Jitter Meter : NO K
1891 23:49:07.045432 CBT Training : PASS
1892 23:49:07.048668 Write leveling : PASS
1893 23:49:07.052279 RX DQS gating : PASS
1894 23:49:07.052366 RX DQ/DQS(RDDQC) : PASS
1895 23:49:07.055774 TX DQ/DQS : PASS
1896 23:49:07.058837 RX DATLAT : PASS
1897 23:49:07.058922 RX DQ/DQS(Engine): PASS
1898 23:49:07.062242 TX OE : NO K
1899 23:49:07.062326 All Pass.
1900 23:49:07.062390
1901 23:49:07.065470 CH 0, Rank 1
1902 23:49:07.065553 SW Impedance : PASS
1903 23:49:07.069000 DUTY Scan : NO K
1904 23:49:07.072348 ZQ Calibration : PASS
1905 23:49:07.072439 Jitter Meter : NO K
1906 23:49:07.076074 CBT Training : PASS
1907 23:49:07.076159 Write leveling : PASS
1908 23:49:07.078632 RX DQS gating : PASS
1909 23:49:07.082370 RX DQ/DQS(RDDQC) : PASS
1910 23:49:07.082459 TX DQ/DQS : PASS
1911 23:49:07.085581 RX DATLAT : PASS
1912 23:49:07.088818 RX DQ/DQS(Engine): PASS
1913 23:49:07.088903 TX OE : NO K
1914 23:49:07.092133 All Pass.
1915 23:49:07.092217
1916 23:49:07.092280 CH 1, Rank 0
1917 23:49:07.095379 SW Impedance : PASS
1918 23:49:07.095460 DUTY Scan : NO K
1919 23:49:07.098870 ZQ Calibration : PASS
1920 23:49:07.102008 Jitter Meter : NO K
1921 23:49:07.102096 CBT Training : PASS
1922 23:49:07.105491 Write leveling : PASS
1923 23:49:07.109126 RX DQS gating : PASS
1924 23:49:07.109238 RX DQ/DQS(RDDQC) : PASS
1925 23:49:07.112076 TX DQ/DQS : PASS
1926 23:49:07.115271 RX DATLAT : PASS
1927 23:49:07.115357 RX DQ/DQS(Engine): PASS
1928 23:49:07.118771 TX OE : NO K
1929 23:49:07.118857 All Pass.
1930 23:49:07.118921
1931 23:49:07.122189 CH 1, Rank 1
1932 23:49:07.122271 SW Impedance : PASS
1933 23:49:07.125264 DUTY Scan : NO K
1934 23:49:07.128484 ZQ Calibration : PASS
1935 23:49:07.128571 Jitter Meter : NO K
1936 23:49:07.132111 CBT Training : PASS
1937 23:49:07.132196 Write leveling : PASS
1938 23:49:07.135404 RX DQS gating : PASS
1939 23:49:07.138959 RX DQ/DQS(RDDQC) : PASS
1940 23:49:07.139043 TX DQ/DQS : PASS
1941 23:49:07.141788 RX DATLAT : PASS
1942 23:49:07.145126 RX DQ/DQS(Engine): PASS
1943 23:49:07.145211 TX OE : NO K
1944 23:49:07.148832 All Pass.
1945 23:49:07.148917
1946 23:49:07.148980 DramC Write-DBI off
1947 23:49:07.151850 PER_BANK_REFRESH: Hybrid Mode
1948 23:49:07.155668 TX_TRACKING: ON
1949 23:49:07.159011 [GetDramInforAfterCalByMRR] Vendor 6.
1950 23:49:07.161973 [GetDramInforAfterCalByMRR] Revision 606.
1951 23:49:07.165197 [GetDramInforAfterCalByMRR] Revision 2 0.
1952 23:49:07.165283 MR0 0x3939
1953 23:49:07.165392 MR8 0x1111
1954 23:49:07.168749 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1955 23:49:07.172229
1956 23:49:07.172328 MR0 0x3939
1957 23:49:07.172393 MR8 0x1111
1958 23:49:07.175246 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1959 23:49:07.175330
1960 23:49:07.185241 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1961 23:49:07.188713 [FAST_K] Save calibration result to emmc
1962 23:49:07.191878 [FAST_K] Save calibration result to emmc
1963 23:49:07.194954 dram_init: config_dvfs: 1
1964 23:49:07.198176 dramc_set_vcore_voltage set vcore to 662500
1965 23:49:07.201667 Read voltage for 1200, 2
1966 23:49:07.201758 Vio18 = 0
1967 23:49:07.201844 Vcore = 662500
1968 23:49:07.205206 Vdram = 0
1969 23:49:07.205339 Vddq = 0
1970 23:49:07.205437 Vmddr = 0
1971 23:49:07.211770 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1972 23:49:07.215005 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1973 23:49:07.218349 MEM_TYPE=3, freq_sel=15
1974 23:49:07.221758 sv_algorithm_assistance_LP4_1600
1975 23:49:07.224877 ============ PULL DRAM RESETB DOWN ============
1976 23:49:07.231408 ========== PULL DRAM RESETB DOWN end =========
1977 23:49:07.234540 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1978 23:49:07.237959 ===================================
1979 23:49:07.241264 LPDDR4 DRAM CONFIGURATION
1980 23:49:07.244621 ===================================
1981 23:49:07.244711 EX_ROW_EN[0] = 0x0
1982 23:49:07.248029 EX_ROW_EN[1] = 0x0
1983 23:49:07.248114 LP4Y_EN = 0x0
1984 23:49:07.251521 WORK_FSP = 0x0
1985 23:49:07.251605 WL = 0x4
1986 23:49:07.254693 RL = 0x4
1987 23:49:07.254788 BL = 0x2
1988 23:49:07.257755 RPST = 0x0
1989 23:49:07.257838 RD_PRE = 0x0
1990 23:49:07.261270 WR_PRE = 0x1
1991 23:49:07.261398 WR_PST = 0x0
1992 23:49:07.265247 DBI_WR = 0x0
1993 23:49:07.265397 DBI_RD = 0x0
1994 23:49:07.268207 OTF = 0x1
1995 23:49:07.271257 ===================================
1996 23:49:07.274541 ===================================
1997 23:49:07.274644 ANA top config
1998 23:49:07.277897 ===================================
1999 23:49:07.281776 DLL_ASYNC_EN = 0
2000 23:49:07.284843 ALL_SLAVE_EN = 0
2001 23:49:07.288247 NEW_RANK_MODE = 1
2002 23:49:07.288337 DLL_IDLE_MODE = 1
2003 23:49:07.291443 LP45_APHY_COMB_EN = 1
2004 23:49:07.294953 TX_ODT_DIS = 1
2005 23:49:07.298273 NEW_8X_MODE = 1
2006 23:49:07.301823 ===================================
2007 23:49:07.305087 ===================================
2008 23:49:07.308185 data_rate = 2400
2009 23:49:07.308287 CKR = 1
2010 23:49:07.311368 DQ_P2S_RATIO = 8
2011 23:49:07.314659 ===================================
2012 23:49:07.317981 CA_P2S_RATIO = 8
2013 23:49:07.321595 DQ_CA_OPEN = 0
2014 23:49:07.324767 DQ_SEMI_OPEN = 0
2015 23:49:07.328142 CA_SEMI_OPEN = 0
2016 23:49:07.328230 CA_FULL_RATE = 0
2017 23:49:07.331459 DQ_CKDIV4_EN = 0
2018 23:49:07.335169 CA_CKDIV4_EN = 0
2019 23:49:07.338001 CA_PREDIV_EN = 0
2020 23:49:07.341514 PH8_DLY = 17
2021 23:49:07.344648 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2022 23:49:07.344735 DQ_AAMCK_DIV = 4
2023 23:49:07.348570 CA_AAMCK_DIV = 4
2024 23:49:07.351581 CA_ADMCK_DIV = 4
2025 23:49:07.354662 DQ_TRACK_CA_EN = 0
2026 23:49:07.357988 CA_PICK = 1200
2027 23:49:07.361395 CA_MCKIO = 1200
2028 23:49:07.361484 MCKIO_SEMI = 0
2029 23:49:07.364937 PLL_FREQ = 2366
2030 23:49:07.368069 DQ_UI_PI_RATIO = 32
2031 23:49:07.371599 CA_UI_PI_RATIO = 0
2032 23:49:07.374710 ===================================
2033 23:49:07.378463 ===================================
2034 23:49:07.381238 memory_type:LPDDR4
2035 23:49:07.381381 GP_NUM : 10
2036 23:49:07.384604 SRAM_EN : 1
2037 23:49:07.387987 MD32_EN : 0
2038 23:49:07.391296 ===================================
2039 23:49:07.391383 [ANA_INIT] >>>>>>>>>>>>>>
2040 23:49:07.395022 <<<<<< [CONFIGURE PHASE]: ANA_TX
2041 23:49:07.398030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2042 23:49:07.401297 ===================================
2043 23:49:07.404751 data_rate = 2400,PCW = 0X5b00
2044 23:49:07.408471 ===================================
2045 23:49:07.411399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2046 23:49:07.418496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2047 23:49:07.421560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2048 23:49:07.428124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2049 23:49:07.431507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2050 23:49:07.434741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2051 23:49:07.434833 [ANA_INIT] flow start
2052 23:49:07.438110 [ANA_INIT] PLL >>>>>>>>
2053 23:49:07.441309 [ANA_INIT] PLL <<<<<<<<
2054 23:49:07.441409 [ANA_INIT] MIDPI >>>>>>>>
2055 23:49:07.444631 [ANA_INIT] MIDPI <<<<<<<<
2056 23:49:07.448020 [ANA_INIT] DLL >>>>>>>>
2057 23:49:07.451452 [ANA_INIT] DLL <<<<<<<<
2058 23:49:07.451540 [ANA_INIT] flow end
2059 23:49:07.454720 ============ LP4 DIFF to SE enter ============
2060 23:49:07.461461 ============ LP4 DIFF to SE exit ============
2061 23:49:07.461564 [ANA_INIT] <<<<<<<<<<<<<
2062 23:49:07.464581 [Flow] Enable top DCM control >>>>>
2063 23:49:07.468093 [Flow] Enable top DCM control <<<<<
2064 23:49:07.471610 Enable DLL master slave shuffle
2065 23:49:07.477811 ==============================================================
2066 23:49:07.477926 Gating Mode config
2067 23:49:07.484536 ==============================================================
2068 23:49:07.488246 Config description:
2069 23:49:07.494415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2070 23:49:07.501482 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2071 23:49:07.507795 SELPH_MODE 0: By rank 1: By Phase
2072 23:49:07.515003 ==============================================================
2073 23:49:07.515119 GAT_TRACK_EN = 1
2074 23:49:07.518187 RX_GATING_MODE = 2
2075 23:49:07.521432 RX_GATING_TRACK_MODE = 2
2076 23:49:07.524802 SELPH_MODE = 1
2077 23:49:07.527928 PICG_EARLY_EN = 1
2078 23:49:07.531158 VALID_LAT_VALUE = 1
2079 23:49:07.538107 ==============================================================
2080 23:49:07.541487 Enter into Gating configuration >>>>
2081 23:49:07.544993 Exit from Gating configuration <<<<
2082 23:49:07.548001 Enter into DVFS_PRE_config >>>>>
2083 23:49:07.558244 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2084 23:49:07.561480 Exit from DVFS_PRE_config <<<<<
2085 23:49:07.564986 Enter into PICG configuration >>>>
2086 23:49:07.567900 Exit from PICG configuration <<<<
2087 23:49:07.571477 [RX_INPUT] configuration >>>>>
2088 23:49:07.571593 [RX_INPUT] configuration <<<<<
2089 23:49:07.577967 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2090 23:49:07.584888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2091 23:49:07.587750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2092 23:49:07.594601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2093 23:49:07.601233 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2094 23:49:07.607617 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2095 23:49:07.611225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2096 23:49:07.614127 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2097 23:49:07.620953 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2098 23:49:07.624335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2099 23:49:07.627644 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2100 23:49:07.634059 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2101 23:49:07.637591 ===================================
2102 23:49:07.637687 LPDDR4 DRAM CONFIGURATION
2103 23:49:07.640823 ===================================
2104 23:49:07.644037 EX_ROW_EN[0] = 0x0
2105 23:49:07.644125 EX_ROW_EN[1] = 0x0
2106 23:49:07.647610 LP4Y_EN = 0x0
2107 23:49:07.647696 WORK_FSP = 0x0
2108 23:49:07.650781 WL = 0x4
2109 23:49:07.654120 RL = 0x4
2110 23:49:07.654200 BL = 0x2
2111 23:49:07.657574 RPST = 0x0
2112 23:49:07.657645 RD_PRE = 0x0
2113 23:49:07.660862 WR_PRE = 0x1
2114 23:49:07.660931 WR_PST = 0x0
2115 23:49:07.664333 DBI_WR = 0x0
2116 23:49:07.664416 DBI_RD = 0x0
2117 23:49:07.667967 OTF = 0x1
2118 23:49:07.670605 ===================================
2119 23:49:07.674122 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2120 23:49:07.677249 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2121 23:49:07.681139 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2122 23:49:07.684054 ===================================
2123 23:49:07.687597 LPDDR4 DRAM CONFIGURATION
2124 23:49:07.690744 ===================================
2125 23:49:07.694108 EX_ROW_EN[0] = 0x10
2126 23:49:07.694197 EX_ROW_EN[1] = 0x0
2127 23:49:07.697273 LP4Y_EN = 0x0
2128 23:49:07.697382 WORK_FSP = 0x0
2129 23:49:07.700993 WL = 0x4
2130 23:49:07.701078 RL = 0x4
2131 23:49:07.703965 BL = 0x2
2132 23:49:07.704046 RPST = 0x0
2133 23:49:07.707402 RD_PRE = 0x0
2134 23:49:07.707511 WR_PRE = 0x1
2135 23:49:07.710752 WR_PST = 0x0
2136 23:49:07.710835 DBI_WR = 0x0
2137 23:49:07.714248 DBI_RD = 0x0
2138 23:49:07.717997 OTF = 0x1
2139 23:49:07.718083 ===================================
2140 23:49:07.724509 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2141 23:49:07.724604 ==
2142 23:49:07.727405 Dram Type= 6, Freq= 0, CH_0, rank 0
2143 23:49:07.733980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2144 23:49:07.734062 ==
2145 23:49:07.734154 [Duty_Offset_Calibration]
2146 23:49:07.737571 B0:0 B1:2 CA:1
2147 23:49:07.737651
2148 23:49:07.740661 [DutyScan_Calibration_Flow] k_type=0
2149 23:49:07.749882
2150 23:49:07.749969 ==CLK 0==
2151 23:49:07.753267 Final CLK duty delay cell = 0
2152 23:49:07.756446 [0] MAX Duty = 5093%(X100), DQS PI = 12
2153 23:49:07.760015 [0] MIN Duty = 4938%(X100), DQS PI = 54
2154 23:49:07.760098 [0] AVG Duty = 5015%(X100)
2155 23:49:07.763078
2156 23:49:07.766264 CH0 CLK Duty spec in!! Max-Min= 155%
2157 23:49:07.769627 [DutyScan_Calibration_Flow] ====Done====
2158 23:49:07.769707
2159 23:49:07.772645 [DutyScan_Calibration_Flow] k_type=1
2160 23:49:07.789173
2161 23:49:07.789293 ==DQS 0 ==
2162 23:49:07.792419 Final DQS duty delay cell = 0
2163 23:49:07.796009 [0] MAX Duty = 5125%(X100), DQS PI = 28
2164 23:49:07.799206 [0] MIN Duty = 5031%(X100), DQS PI = 4
2165 23:49:07.799287 [0] AVG Duty = 5078%(X100)
2166 23:49:07.802742
2167 23:49:07.802849 ==DQS 1 ==
2168 23:49:07.805834 Final DQS duty delay cell = 0
2169 23:49:07.809383 [0] MAX Duty = 5031%(X100), DQS PI = 52
2170 23:49:07.812900 [0] MIN Duty = 4906%(X100), DQS PI = 14
2171 23:49:07.812980 [0] AVG Duty = 4968%(X100)
2172 23:49:07.816021
2173 23:49:07.819403 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2174 23:49:07.819537
2175 23:49:07.822446 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2176 23:49:07.825990 [DutyScan_Calibration_Flow] ====Done====
2177 23:49:07.826085
2178 23:49:07.829261 [DutyScan_Calibration_Flow] k_type=3
2179 23:49:07.846122
2180 23:49:07.846218 ==DQM 0 ==
2181 23:49:07.849551 Final DQM duty delay cell = 0
2182 23:49:07.853067 [0] MAX Duty = 5156%(X100), DQS PI = 22
2183 23:49:07.856378 [0] MIN Duty = 4969%(X100), DQS PI = 40
2184 23:49:07.859441 [0] AVG Duty = 5062%(X100)
2185 23:49:07.859526
2186 23:49:07.859599 ==DQM 1 ==
2187 23:49:07.862927 Final DQM duty delay cell = 4
2188 23:49:07.866260 [4] MAX Duty = 5187%(X100), DQS PI = 54
2189 23:49:07.869704 [4] MIN Duty = 5000%(X100), DQS PI = 18
2190 23:49:07.873210 [4] AVG Duty = 5093%(X100)
2191 23:49:07.873347
2192 23:49:07.876739 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2193 23:49:07.876819
2194 23:49:07.879481 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2195 23:49:07.883116 [DutyScan_Calibration_Flow] ====Done====
2196 23:49:07.883197
2197 23:49:07.886269 [DutyScan_Calibration_Flow] k_type=2
2198 23:49:07.901419
2199 23:49:07.901502 ==DQ 0 ==
2200 23:49:07.905090 Final DQ duty delay cell = -4
2201 23:49:07.908011 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2202 23:49:07.911433 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2203 23:49:07.914859 [-4] AVG Duty = 4937%(X100)
2204 23:49:07.914939
2205 23:49:07.915002 ==DQ 1 ==
2206 23:49:07.918267 Final DQ duty delay cell = -4
2207 23:49:07.921436 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2208 23:49:07.924653 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2209 23:49:07.928335 [-4] AVG Duty = 4984%(X100)
2210 23:49:07.928415
2211 23:49:07.931576 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2212 23:49:07.931729
2213 23:49:07.934484 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2214 23:49:07.937991 [DutyScan_Calibration_Flow] ====Done====
2215 23:49:07.938071 ==
2216 23:49:07.941108 Dram Type= 6, Freq= 0, CH_1, rank 0
2217 23:49:07.944284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2218 23:49:07.944372 ==
2219 23:49:07.947805 [Duty_Offset_Calibration]
2220 23:49:07.947886 B0:0 B1:5 CA:-5
2221 23:49:07.947950
2222 23:49:07.950954 [DutyScan_Calibration_Flow] k_type=0
2223 23:49:07.961683
2224 23:49:07.961769 ==CLK 0==
2225 23:49:07.965048 Final CLK duty delay cell = 0
2226 23:49:07.968362 [0] MAX Duty = 5094%(X100), DQS PI = 24
2227 23:49:07.971817 [0] MIN Duty = 4875%(X100), DQS PI = 46
2228 23:49:07.971898 [0] AVG Duty = 4984%(X100)
2229 23:49:07.975294
2230 23:49:07.978891 CH1 CLK Duty spec in!! Max-Min= 219%
2231 23:49:07.982063 [DutyScan_Calibration_Flow] ====Done====
2232 23:49:07.982144
2233 23:49:07.984881 [DutyScan_Calibration_Flow] k_type=1
2234 23:49:08.000662
2235 23:49:08.000750 ==DQS 0 ==
2236 23:49:08.003821 Final DQS duty delay cell = 0
2237 23:49:08.006897 [0] MAX Duty = 5125%(X100), DQS PI = 16
2238 23:49:08.010390 [0] MIN Duty = 4875%(X100), DQS PI = 40
2239 23:49:08.010470 [0] AVG Duty = 5000%(X100)
2240 23:49:08.013832
2241 23:49:08.013911 ==DQS 1 ==
2242 23:49:08.017110 Final DQS duty delay cell = -4
2243 23:49:08.020315 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2244 23:49:08.023573 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2245 23:49:08.027032 [-4] AVG Duty = 4953%(X100)
2246 23:49:08.027111
2247 23:49:08.030472 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2248 23:49:08.030552
2249 23:49:08.033767 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2250 23:49:08.036694 [DutyScan_Calibration_Flow] ====Done====
2251 23:49:08.036774
2252 23:49:08.040107 [DutyScan_Calibration_Flow] k_type=3
2253 23:49:08.055498
2254 23:49:08.055597 ==DQM 0 ==
2255 23:49:08.059122 Final DQM duty delay cell = -4
2256 23:49:08.062709 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2257 23:49:08.065591 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2258 23:49:08.068724 [-4] AVG Duty = 4984%(X100)
2259 23:49:08.068804
2260 23:49:08.068866 ==DQM 1 ==
2261 23:49:08.072224 Final DQM duty delay cell = -4
2262 23:49:08.075451 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2263 23:49:08.078588 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2264 23:49:08.082197 [-4] AVG Duty = 5000%(X100)
2265 23:49:08.082277
2266 23:49:08.085618 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2267 23:49:08.085699
2268 23:49:08.089194 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2269 23:49:08.092038 [DutyScan_Calibration_Flow] ====Done====
2270 23:49:08.092117
2271 23:49:08.095415 [DutyScan_Calibration_Flow] k_type=2
2272 23:49:08.112688
2273 23:49:08.112769 ==DQ 0 ==
2274 23:49:08.115912 Final DQ duty delay cell = 0
2275 23:49:08.119622 [0] MAX Duty = 5062%(X100), DQS PI = 0
2276 23:49:08.122738 [0] MIN Duty = 4969%(X100), DQS PI = 42
2277 23:49:08.122818 [0] AVG Duty = 5015%(X100)
2278 23:49:08.126029
2279 23:49:08.126130 ==DQ 1 ==
2280 23:49:08.129483 Final DQ duty delay cell = 0
2281 23:49:08.132828 [0] MAX Duty = 5031%(X100), DQS PI = 8
2282 23:49:08.136123 [0] MIN Duty = 4907%(X100), DQS PI = 0
2283 23:49:08.136203 [0] AVG Duty = 4969%(X100)
2284 23:49:08.136267
2285 23:49:08.139531 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2286 23:49:08.139610
2287 23:49:08.142569 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2288 23:49:08.149238 [DutyScan_Calibration_Flow] ====Done====
2289 23:49:08.152304 nWR fixed to 30
2290 23:49:08.152385 [ModeRegInit_LP4] CH0 RK0
2291 23:49:08.155819 [ModeRegInit_LP4] CH0 RK1
2292 23:49:08.159125 [ModeRegInit_LP4] CH1 RK0
2293 23:49:08.159205 [ModeRegInit_LP4] CH1 RK1
2294 23:49:08.162673 match AC timing 6
2295 23:49:08.165874 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2296 23:49:08.168950 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2297 23:49:08.175724 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2298 23:49:08.179155 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2299 23:49:08.185841 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2300 23:49:08.185924 ==
2301 23:49:08.189512 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 23:49:08.192670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2303 23:49:08.192749 ==
2304 23:49:08.199055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2305 23:49:08.202538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2306 23:49:08.212607 [CA 0] Center 39 (9~70) winsize 62
2307 23:49:08.215995 [CA 1] Center 39 (8~70) winsize 63
2308 23:49:08.218829 [CA 2] Center 36 (5~67) winsize 63
2309 23:49:08.222280 [CA 3] Center 35 (4~66) winsize 63
2310 23:49:08.225753 [CA 4] Center 34 (3~65) winsize 63
2311 23:49:08.229084 [CA 5] Center 34 (3~65) winsize 63
2312 23:49:08.229162
2313 23:49:08.232130 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2314 23:49:08.232221
2315 23:49:08.235347 [CATrainingPosCal] consider 1 rank data
2316 23:49:08.238672 u2DelayCellTimex100 = 270/100 ps
2317 23:49:08.242383 CA0 delay=39 (9~70),Diff = 5 PI (24 cell)
2318 23:49:08.248693 CA1 delay=39 (8~70),Diff = 5 PI (24 cell)
2319 23:49:08.252035 CA2 delay=36 (5~67),Diff = 2 PI (9 cell)
2320 23:49:08.255411 CA3 delay=35 (4~66),Diff = 1 PI (4 cell)
2321 23:49:08.258727 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
2322 23:49:08.262109 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
2323 23:49:08.262190
2324 23:49:08.265243 CA PerBit enable=1, Macro0, CA PI delay=34
2325 23:49:08.265361
2326 23:49:08.268673 [CBTSetCACLKResult] CA Dly = 34
2327 23:49:08.268754 CS Dly: 7 (0~38)
2328 23:49:08.271931 ==
2329 23:49:08.275524 Dram Type= 6, Freq= 0, CH_0, rank 1
2330 23:49:08.278560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2331 23:49:08.278642 ==
2332 23:49:08.282114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2333 23:49:08.289007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2334 23:49:08.297866 [CA 0] Center 39 (8~70) winsize 63
2335 23:49:08.301118 [CA 1] Center 39 (8~70) winsize 63
2336 23:49:08.304401 [CA 2] Center 35 (5~66) winsize 62
2337 23:49:08.307663 [CA 3] Center 35 (4~66) winsize 63
2338 23:49:08.311012 [CA 4] Center 33 (3~64) winsize 62
2339 23:49:08.314418 [CA 5] Center 34 (3~65) winsize 63
2340 23:49:08.314500
2341 23:49:08.317872 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2342 23:49:08.317954
2343 23:49:08.320900 [CATrainingPosCal] consider 2 rank data
2344 23:49:08.324462 u2DelayCellTimex100 = 270/100 ps
2345 23:49:08.328059 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2346 23:49:08.331088 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2347 23:49:08.337518 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2348 23:49:08.340933 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2349 23:49:08.344361 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2350 23:49:08.348051 CA5 delay=34 (3~65),Diff = 1 PI (4 cell)
2351 23:49:08.348137
2352 23:49:08.350848 CA PerBit enable=1, Macro0, CA PI delay=33
2353 23:49:08.350931
2354 23:49:08.354253 [CBTSetCACLKResult] CA Dly = 33
2355 23:49:08.354335 CS Dly: 7 (0~39)
2356 23:49:08.354400
2357 23:49:08.357588 ----->DramcWriteLeveling(PI) begin...
2358 23:49:08.360700 ==
2359 23:49:08.363921 Dram Type= 6, Freq= 0, CH_0, rank 0
2360 23:49:08.367393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2361 23:49:08.367475 ==
2362 23:49:08.370732 Write leveling (Byte 0): 26 => 26
2363 23:49:08.374036 Write leveling (Byte 1): 26 => 26
2364 23:49:08.376996 DramcWriteLeveling(PI) end<-----
2365 23:49:08.377140
2366 23:49:08.377236 ==
2367 23:49:08.380433 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 23:49:08.383867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2369 23:49:08.383971 ==
2370 23:49:08.386996 [Gating] SW mode calibration
2371 23:49:08.393945 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2372 23:49:08.400589 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2373 23:49:08.403722 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2374 23:49:08.406970 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2375 23:49:08.413550 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 23:49:08.417736 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2377 23:49:08.420508 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2378 23:49:08.427066 0 11 20 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (1 1)
2379 23:49:08.430373 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2380 23:49:08.434023 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2381 23:49:08.437133 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 23:49:08.443890 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 23:49:08.447086 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 23:49:08.450676 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 23:49:08.457081 0 12 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2386 23:49:08.460602 0 12 20 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (1 1)
2387 23:49:08.463818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2388 23:49:08.470488 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2389 23:49:08.473757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 23:49:08.477200 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 23:49:08.484006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 23:49:08.487203 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 23:49:08.490636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 23:49:08.497045 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2395 23:49:08.500466 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2396 23:49:08.503891 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2397 23:49:08.510686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 23:49:08.513688 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 23:49:08.517082 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 23:49:08.523857 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 23:49:08.527886 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 23:49:08.530295 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 23:49:08.533859 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 23:49:08.540182 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 23:49:08.543971 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 23:49:08.547137 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 23:49:08.553805 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 23:49:08.556871 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 23:49:08.560291 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 23:49:08.566785 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2411 23:49:08.570244 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2412 23:49:08.573413 Total UI for P1: 0, mck2ui 16
2413 23:49:08.576966 best dqsien dly found for B0: ( 0, 15, 20)
2414 23:49:08.580163 Total UI for P1: 0, mck2ui 16
2415 23:49:08.583576 best dqsien dly found for B1: ( 0, 15, 20)
2416 23:49:08.587143 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2417 23:49:08.590265 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2418 23:49:08.590370
2419 23:49:08.593773 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2420 23:49:08.596753 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2421 23:49:08.600002 [Gating] SW calibration Done
2422 23:49:08.600086 ==
2423 23:49:08.603301 Dram Type= 6, Freq= 0, CH_0, rank 0
2424 23:49:08.610165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2425 23:49:08.610251 ==
2426 23:49:08.610316 RX Vref Scan: 0
2427 23:49:08.610376
2428 23:49:08.613789 RX Vref 0 -> 0, step: 1
2429 23:49:08.613895
2430 23:49:08.617043 RX Delay -40 -> 252, step: 8
2431 23:49:08.620373 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2432 23:49:08.623488 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2433 23:49:08.627252 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2434 23:49:08.630386 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2435 23:49:08.636740 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2436 23:49:08.640199 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2437 23:49:08.643492 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2438 23:49:08.646850 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2439 23:49:08.650478 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2440 23:49:08.656844 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2441 23:49:08.660153 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2442 23:49:08.663491 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2443 23:49:08.666922 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2444 23:49:08.669959 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2445 23:49:08.676883 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2446 23:49:08.680175 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2447 23:49:08.680277 ==
2448 23:49:08.683430 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 23:49:08.687133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2450 23:49:08.687230 ==
2451 23:49:08.690130 DQS Delay:
2452 23:49:08.690227 DQS0 = 0, DQS1 = 0
2453 23:49:08.690292 DQM Delay:
2454 23:49:08.693716 DQM0 = 115, DQM1 = 106
2455 23:49:08.693805 DQ Delay:
2456 23:49:08.697253 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2457 23:49:08.700037 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2458 23:49:08.703753 DQ8 =95, DQ9 =91, DQ10 =107, DQ11 =103
2459 23:49:08.710310 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2460 23:49:08.710420
2461 23:49:08.710488
2462 23:49:08.710547 ==
2463 23:49:08.713763 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 23:49:08.716592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2465 23:49:08.716675 ==
2466 23:49:08.716739
2467 23:49:08.716798
2468 23:49:08.720375 TX Vref Scan disable
2469 23:49:08.720456 == TX Byte 0 ==
2470 23:49:08.726955 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2471 23:49:08.730208 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2472 23:49:08.730291 == TX Byte 1 ==
2473 23:49:08.736646 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2474 23:49:08.740360 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2475 23:49:08.740443 ==
2476 23:49:08.743819 Dram Type= 6, Freq= 0, CH_0, rank 0
2477 23:49:08.746672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2478 23:49:08.746755 ==
2479 23:49:08.759059 TX Vref=22, minBit 12, minWin=24, winSum=411
2480 23:49:08.762910 TX Vref=24, minBit 4, minWin=25, winSum=416
2481 23:49:08.765847 TX Vref=26, minBit 10, minWin=25, winSum=422
2482 23:49:08.768870 TX Vref=28, minBit 1, minWin=26, winSum=428
2483 23:49:08.772475 TX Vref=30, minBit 5, minWin=26, winSum=427
2484 23:49:08.779406 TX Vref=32, minBit 2, minWin=26, winSum=426
2485 23:49:08.782238 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
2486 23:49:08.782323
2487 23:49:08.785651 Final TX Range 1 Vref 28
2488 23:49:08.785735
2489 23:49:08.785800 ==
2490 23:49:08.788867 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 23:49:08.792354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2492 23:49:08.792437 ==
2493 23:49:08.795534
2494 23:49:08.795621
2495 23:49:08.795685 TX Vref Scan disable
2496 23:49:08.798939 == TX Byte 0 ==
2497 23:49:08.802202 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2498 23:49:08.805735 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2499 23:49:08.808998 == TX Byte 1 ==
2500 23:49:08.812013 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2501 23:49:08.815804 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2502 23:49:08.819083
2503 23:49:08.819165 [DATLAT]
2504 23:49:08.819229 Freq=1200, CH0 RK0
2505 23:49:08.819291
2506 23:49:08.822040 DATLAT Default: 0xd
2507 23:49:08.822122 0, 0xFFFF, sum = 0
2508 23:49:08.826112 1, 0xFFFF, sum = 0
2509 23:49:08.826196 2, 0xFFFF, sum = 0
2510 23:49:08.828823 3, 0xFFFF, sum = 0
2511 23:49:08.828906 4, 0xFFFF, sum = 0
2512 23:49:08.832225 5, 0xFFFF, sum = 0
2513 23:49:08.835495 6, 0xFFFF, sum = 0
2514 23:49:08.835578 7, 0xFFFF, sum = 0
2515 23:49:08.838800 8, 0xFFFF, sum = 0
2516 23:49:08.838886 9, 0xFFFF, sum = 0
2517 23:49:08.842073 10, 0xFFFF, sum = 0
2518 23:49:08.842160 11, 0x0, sum = 1
2519 23:49:08.845263 12, 0x0, sum = 2
2520 23:49:08.845388 13, 0x0, sum = 3
2521 23:49:08.845455 14, 0x0, sum = 4
2522 23:49:08.848821 best_step = 12
2523 23:49:08.848903
2524 23:49:08.848969 ==
2525 23:49:08.852431 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 23:49:08.855682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2527 23:49:08.855765 ==
2528 23:49:08.858918 RX Vref Scan: 1
2529 23:49:08.858999
2530 23:49:08.859063 Set Vref Range= 32 -> 127
2531 23:49:08.862394
2532 23:49:08.862475 RX Vref 32 -> 127, step: 1
2533 23:49:08.862540
2534 23:49:08.866035 RX Delay -21 -> 252, step: 4
2535 23:49:08.866117
2536 23:49:08.868814 Set Vref, RX VrefLevel [Byte0]: 32
2537 23:49:08.872288 [Byte1]: 32
2538 23:49:08.875760
2539 23:49:08.875846 Set Vref, RX VrefLevel [Byte0]: 33
2540 23:49:08.878798 [Byte1]: 33
2541 23:49:08.883703
2542 23:49:08.883786 Set Vref, RX VrefLevel [Byte0]: 34
2543 23:49:08.886522 [Byte1]: 34
2544 23:49:08.891329
2545 23:49:08.891412 Set Vref, RX VrefLevel [Byte0]: 35
2546 23:49:08.894444 [Byte1]: 35
2547 23:49:08.899240
2548 23:49:08.899324 Set Vref, RX VrefLevel [Byte0]: 36
2549 23:49:08.902653 [Byte1]: 36
2550 23:49:08.907118
2551 23:49:08.907200 Set Vref, RX VrefLevel [Byte0]: 37
2552 23:49:08.910295 [Byte1]: 37
2553 23:49:08.915009
2554 23:49:08.915096 Set Vref, RX VrefLevel [Byte0]: 38
2555 23:49:08.918401 [Byte1]: 38
2556 23:49:08.923108
2557 23:49:08.923190 Set Vref, RX VrefLevel [Byte0]: 39
2558 23:49:08.926360 [Byte1]: 39
2559 23:49:08.930865
2560 23:49:08.930946 Set Vref, RX VrefLevel [Byte0]: 40
2561 23:49:08.934046 [Byte1]: 40
2562 23:49:08.939087
2563 23:49:08.939169 Set Vref, RX VrefLevel [Byte0]: 41
2564 23:49:08.942230 [Byte1]: 41
2565 23:49:08.947272
2566 23:49:08.947355 Set Vref, RX VrefLevel [Byte0]: 42
2567 23:49:08.950067 [Byte1]: 42
2568 23:49:08.954795
2569 23:49:08.954877 Set Vref, RX VrefLevel [Byte0]: 43
2570 23:49:08.958050 [Byte1]: 43
2571 23:49:08.962455
2572 23:49:08.962538 Set Vref, RX VrefLevel [Byte0]: 44
2573 23:49:08.965722 [Byte1]: 44
2574 23:49:08.974214
2575 23:49:08.974299 Set Vref, RX VrefLevel [Byte0]: 45
2576 23:49:08.974365 [Byte1]: 45
2577 23:49:08.978327
2578 23:49:08.978417 Set Vref, RX VrefLevel [Byte0]: 46
2579 23:49:08.981876 [Byte1]: 46
2580 23:49:08.986336
2581 23:49:08.986418 Set Vref, RX VrefLevel [Byte0]: 47
2582 23:49:08.989681 [Byte1]: 47
2583 23:49:08.994168
2584 23:49:08.994250 Set Vref, RX VrefLevel [Byte0]: 48
2585 23:49:08.997572 [Byte1]: 48
2586 23:49:09.002238
2587 23:49:09.002321 Set Vref, RX VrefLevel [Byte0]: 49
2588 23:49:09.005420 [Byte1]: 49
2589 23:49:09.010086
2590 23:49:09.010169 Set Vref, RX VrefLevel [Byte0]: 50
2591 23:49:09.013601 [Byte1]: 50
2592 23:49:09.018132
2593 23:49:09.018213 Set Vref, RX VrefLevel [Byte0]: 51
2594 23:49:09.021213 [Byte1]: 51
2595 23:49:09.025963
2596 23:49:09.026046 Set Vref, RX VrefLevel [Byte0]: 52
2597 23:49:09.029154 [Byte1]: 52
2598 23:49:09.033915
2599 23:49:09.033997 Set Vref, RX VrefLevel [Byte0]: 53
2600 23:49:09.037265 [Byte1]: 53
2601 23:49:09.041661
2602 23:49:09.041742 Set Vref, RX VrefLevel [Byte0]: 54
2603 23:49:09.044995 [Byte1]: 54
2604 23:49:09.049979
2605 23:49:09.050065 Set Vref, RX VrefLevel [Byte0]: 55
2606 23:49:09.052912 [Byte1]: 55
2607 23:49:09.058005
2608 23:49:09.058086 Set Vref, RX VrefLevel [Byte0]: 56
2609 23:49:09.060835 [Byte1]: 56
2610 23:49:09.065696
2611 23:49:09.065776 Set Vref, RX VrefLevel [Byte0]: 57
2612 23:49:09.069050 [Byte1]: 57
2613 23:49:09.073742
2614 23:49:09.073823 Set Vref, RX VrefLevel [Byte0]: 58
2615 23:49:09.076916 [Byte1]: 58
2616 23:49:09.081241
2617 23:49:09.081413 Set Vref, RX VrefLevel [Byte0]: 59
2618 23:49:09.084608 [Byte1]: 59
2619 23:49:09.089193
2620 23:49:09.089347 Set Vref, RX VrefLevel [Byte0]: 60
2621 23:49:09.092608 [Byte1]: 60
2622 23:49:09.097468
2623 23:49:09.097550 Set Vref, RX VrefLevel [Byte0]: 61
2624 23:49:09.100646 [Byte1]: 61
2625 23:49:09.105380
2626 23:49:09.105464 Set Vref, RX VrefLevel [Byte0]: 62
2627 23:49:09.108428 [Byte1]: 62
2628 23:49:09.113052
2629 23:49:09.113134 Set Vref, RX VrefLevel [Byte0]: 63
2630 23:49:09.116620 [Byte1]: 63
2631 23:49:09.120933
2632 23:49:09.121020 Set Vref, RX VrefLevel [Byte0]: 64
2633 23:49:09.124703 [Byte1]: 64
2634 23:49:09.128805
2635 23:49:09.128887 Set Vref, RX VrefLevel [Byte0]: 65
2636 23:49:09.132395 [Byte1]: 65
2637 23:49:09.137207
2638 23:49:09.137336 Set Vref, RX VrefLevel [Byte0]: 66
2639 23:49:09.140025 [Byte1]: 66
2640 23:49:09.145068
2641 23:49:09.145150 Final RX Vref Byte 0 = 47 to rank0
2642 23:49:09.148303 Final RX Vref Byte 1 = 50 to rank0
2643 23:49:09.151654 Final RX Vref Byte 0 = 47 to rank1
2644 23:49:09.154679 Final RX Vref Byte 1 = 50 to rank1==
2645 23:49:09.157881 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 23:49:09.164742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2647 23:49:09.164827 ==
2648 23:49:09.164892 DQS Delay:
2649 23:49:09.164951 DQS0 = 0, DQS1 = 0
2650 23:49:09.167857 DQM Delay:
2651 23:49:09.167937 DQM0 = 113, DQM1 = 105
2652 23:49:09.171102 DQ Delay:
2653 23:49:09.174720 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2654 23:49:09.177908 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2655 23:49:09.181443 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98
2656 23:49:09.184742 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2657 23:49:09.184824
2658 23:49:09.184888
2659 23:49:09.191562 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2660 23:49:09.194499 CH0 RK0: MR19=404, MR18=808
2661 23:49:09.201254 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
2662 23:49:09.201378
2663 23:49:09.204703 ----->DramcWriteLeveling(PI) begin...
2664 23:49:09.204786 ==
2665 23:49:09.208143 Dram Type= 6, Freq= 0, CH_0, rank 1
2666 23:49:09.211305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2667 23:49:09.211414 ==
2668 23:49:09.214747 Write leveling (Byte 0): 27 => 27
2669 23:49:09.217894 Write leveling (Byte 1): 24 => 24
2670 23:49:09.221406 DramcWriteLeveling(PI) end<-----
2671 23:49:09.221486
2672 23:49:09.221550 ==
2673 23:49:09.224394 Dram Type= 6, Freq= 0, CH_0, rank 1
2674 23:49:09.231585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2675 23:49:09.231673 ==
2676 23:49:09.231738 [Gating] SW mode calibration
2677 23:49:09.241282 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2678 23:49:09.244672 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2679 23:49:09.248027 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2680 23:49:09.254750 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2681 23:49:09.258130 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2682 23:49:09.261462 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2683 23:49:09.267929 0 11 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
2684 23:49:09.271449 0 11 20 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (1 0)
2685 23:49:09.274831 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2686 23:49:09.281374 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2687 23:49:09.284777 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 23:49:09.287941 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 23:49:09.294921 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 23:49:09.298105 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 23:49:09.301481 0 12 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2692 23:49:09.307763 0 12 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2693 23:49:09.311412 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2694 23:49:09.314506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2695 23:49:09.318129 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 23:49:09.324779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 23:49:09.327832 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 23:49:09.331068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 23:49:09.337869 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2700 23:49:09.341219 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2701 23:49:09.344548 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2702 23:49:09.351011 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2703 23:49:09.354097 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2704 23:49:09.357600 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 23:49:09.364494 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 23:49:09.367488 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 23:49:09.371024 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 23:49:09.377561 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 23:49:09.381206 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 23:49:09.384404 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 23:49:09.390720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 23:49:09.394513 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 23:49:09.397512 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 23:49:09.404207 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 23:49:09.407489 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2716 23:49:09.411102 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 23:49:09.414150 Total UI for P1: 0, mck2ui 16
2718 23:49:09.417696 best dqsien dly found for B0: ( 0, 15, 16)
2719 23:49:09.420949 Total UI for P1: 0, mck2ui 16
2720 23:49:09.424500 best dqsien dly found for B1: ( 0, 15, 18)
2721 23:49:09.427496 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2722 23:49:09.430759 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2723 23:49:09.430840
2724 23:49:09.437710 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2725 23:49:09.440688 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2726 23:49:09.440774 [Gating] SW calibration Done
2727 23:49:09.444381 ==
2728 23:49:09.444468 Dram Type= 6, Freq= 0, CH_0, rank 1
2729 23:49:09.450972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2730 23:49:09.451063 ==
2731 23:49:09.451129 RX Vref Scan: 0
2732 23:49:09.451191
2733 23:49:09.454275 RX Vref 0 -> 0, step: 1
2734 23:49:09.454358
2735 23:49:09.457734 RX Delay -40 -> 252, step: 8
2736 23:49:09.461036 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2737 23:49:09.464435 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2738 23:49:09.467632 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2739 23:49:09.474526 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2740 23:49:09.477661 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2741 23:49:09.480909 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2742 23:49:09.484412 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2743 23:49:09.487570 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2744 23:49:09.494255 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2745 23:49:09.498062 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2746 23:49:09.501016 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2747 23:49:09.504348 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2748 23:49:09.507887 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2749 23:49:09.513901 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2750 23:49:09.517443 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2751 23:49:09.521327 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2752 23:49:09.521425 ==
2753 23:49:09.524466 Dram Type= 6, Freq= 0, CH_0, rank 1
2754 23:49:09.527509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2755 23:49:09.527594 ==
2756 23:49:09.530877 DQS Delay:
2757 23:49:09.530961 DQS0 = 0, DQS1 = 0
2758 23:49:09.534232 DQM Delay:
2759 23:49:09.534314 DQM0 = 114, DQM1 = 107
2760 23:49:09.534380 DQ Delay:
2761 23:49:09.537558 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2762 23:49:09.540856 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2763 23:49:09.544609 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2764 23:49:09.550829 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2765 23:49:09.550926
2766 23:49:09.550990
2767 23:49:09.551049 ==
2768 23:49:09.554710 Dram Type= 6, Freq= 0, CH_0, rank 1
2769 23:49:09.557723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2770 23:49:09.557808 ==
2771 23:49:09.557874
2772 23:49:09.557933
2773 23:49:09.560599 TX Vref Scan disable
2774 23:49:09.560681 == TX Byte 0 ==
2775 23:49:09.567525 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2776 23:49:09.570623 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2777 23:49:09.570708 == TX Byte 1 ==
2778 23:49:09.577666 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2779 23:49:09.581235 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2780 23:49:09.581359 ==
2781 23:49:09.584317 Dram Type= 6, Freq= 0, CH_0, rank 1
2782 23:49:09.587429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2783 23:49:09.587512 ==
2784 23:49:09.600646 TX Vref=22, minBit 8, minWin=25, winSum=419
2785 23:49:09.604135 TX Vref=24, minBit 8, minWin=25, winSum=424
2786 23:49:09.606964 TX Vref=26, minBit 1, minWin=26, winSum=427
2787 23:49:09.610352 TX Vref=28, minBit 8, minWin=26, winSum=435
2788 23:49:09.613999 TX Vref=30, minBit 8, minWin=26, winSum=428
2789 23:49:09.620225 TX Vref=32, minBit 8, minWin=26, winSum=430
2790 23:49:09.623595 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
2791 23:49:09.623679
2792 23:49:09.627069 Final TX Range 1 Vref 28
2793 23:49:09.627152
2794 23:49:09.627217 ==
2795 23:49:09.630208 Dram Type= 6, Freq= 0, CH_0, rank 1
2796 23:49:09.633501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2797 23:49:09.633585 ==
2798 23:49:09.636639
2799 23:49:09.636720
2800 23:49:09.636785 TX Vref Scan disable
2801 23:49:09.640731 == TX Byte 0 ==
2802 23:49:09.643468 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2803 23:49:09.646878 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2804 23:49:09.650153 == TX Byte 1 ==
2805 23:49:09.653248 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2806 23:49:09.660066 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2807 23:49:09.660149
2808 23:49:09.660236 [DATLAT]
2809 23:49:09.660327 Freq=1200, CH0 RK1
2810 23:49:09.660390
2811 23:49:09.663500 DATLAT Default: 0xc
2812 23:49:09.663585 0, 0xFFFF, sum = 0
2813 23:49:09.666879 1, 0xFFFF, sum = 0
2814 23:49:09.666962 2, 0xFFFF, sum = 0
2815 23:49:09.670126 3, 0xFFFF, sum = 0
2816 23:49:09.673523 4, 0xFFFF, sum = 0
2817 23:49:09.673606 5, 0xFFFF, sum = 0
2818 23:49:09.676744 6, 0xFFFF, sum = 0
2819 23:49:09.676831 7, 0xFFFF, sum = 0
2820 23:49:09.680128 8, 0xFFFF, sum = 0
2821 23:49:09.680211 9, 0xFFFF, sum = 0
2822 23:49:09.683676 10, 0xFFFF, sum = 0
2823 23:49:09.683757 11, 0x0, sum = 1
2824 23:49:09.687056 12, 0x0, sum = 2
2825 23:49:09.687136 13, 0x0, sum = 3
2826 23:49:09.687201 14, 0x0, sum = 4
2827 23:49:09.690473 best_step = 12
2828 23:49:09.690553
2829 23:49:09.690617 ==
2830 23:49:09.693760 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 23:49:09.696858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2832 23:49:09.696940 ==
2833 23:49:09.700448 RX Vref Scan: 0
2834 23:49:09.700529
2835 23:49:09.700593 RX Vref 0 -> 0, step: 1
2836 23:49:09.703574
2837 23:49:09.703655 RX Delay -21 -> 252, step: 4
2838 23:49:09.710630 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2839 23:49:09.714334 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2840 23:49:09.717238 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
2841 23:49:09.720533 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2842 23:49:09.724185 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2843 23:49:09.730560 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2844 23:49:09.734033 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2845 23:49:09.737283 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2846 23:49:09.740795 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2847 23:49:09.744322 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2848 23:49:09.750893 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
2849 23:49:09.754165 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2850 23:49:09.757412 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2851 23:49:09.760567 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2852 23:49:09.763962 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2853 23:49:09.770909 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2854 23:49:09.770991 ==
2855 23:49:09.774170 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 23:49:09.777476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2857 23:49:09.777560 ==
2858 23:49:09.777625 DQS Delay:
2859 23:49:09.780632 DQS0 = 0, DQS1 = 0
2860 23:49:09.780712 DQM Delay:
2861 23:49:09.784083 DQM0 = 114, DQM1 = 106
2862 23:49:09.784174 DQ Delay:
2863 23:49:09.787376 DQ0 =110, DQ1 =116, DQ2 =110, DQ3 =108
2864 23:49:09.790792 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2865 23:49:09.793894 DQ8 =94, DQ9 =90, DQ10 =112, DQ11 =96
2866 23:49:09.797254 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =116
2867 23:49:09.797376
2868 23:49:09.797442
2869 23:49:09.807217 [DQSOSCAuto] RK1, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
2870 23:49:09.810677 CH0 RK1: MR19=404, MR18=1515
2871 23:49:09.813895 CH0_RK1: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
2872 23:49:09.817643 [RxdqsGatingPostProcess] freq 1200
2873 23:49:09.824135 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2874 23:49:09.827253 Pre-setting of DQS Precalculation
2875 23:49:09.830881 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2876 23:49:09.833926 ==
2877 23:49:09.834008 Dram Type= 6, Freq= 0, CH_1, rank 0
2878 23:49:09.840706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2879 23:49:09.840789 ==
2880 23:49:09.843848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2881 23:49:09.850448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2882 23:49:09.859458 [CA 0] Center 37 (7~68) winsize 62
2883 23:49:09.862649 [CA 1] Center 37 (7~68) winsize 62
2884 23:49:09.865955 [CA 2] Center 34 (4~65) winsize 62
2885 23:49:09.869569 [CA 3] Center 33 (3~64) winsize 62
2886 23:49:09.872764 [CA 4] Center 32 (1~63) winsize 63
2887 23:49:09.876057 [CA 5] Center 32 (2~63) winsize 62
2888 23:49:09.876139
2889 23:49:09.879208 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2890 23:49:09.879291
2891 23:49:09.882502 [CATrainingPosCal] consider 1 rank data
2892 23:49:09.886109 u2DelayCellTimex100 = 270/100 ps
2893 23:49:09.889151 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2894 23:49:09.892592 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2895 23:49:09.899606 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2896 23:49:09.902455 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2897 23:49:09.905801 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2898 23:49:09.909479 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2899 23:49:09.909561
2900 23:49:09.912507 CA PerBit enable=1, Macro0, CA PI delay=32
2901 23:49:09.912589
2902 23:49:09.915956 [CBTSetCACLKResult] CA Dly = 32
2903 23:49:09.916039 CS Dly: 5 (0~36)
2904 23:49:09.916105 ==
2905 23:49:09.919641 Dram Type= 6, Freq= 0, CH_1, rank 1
2906 23:49:09.925803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2907 23:49:09.925889 ==
2908 23:49:09.929037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2909 23:49:09.935753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2910 23:49:09.944499 [CA 0] Center 37 (6~68) winsize 63
2911 23:49:09.947715 [CA 1] Center 37 (6~68) winsize 63
2912 23:49:09.951585 [CA 2] Center 34 (3~65) winsize 63
2913 23:49:09.954779 [CA 3] Center 33 (3~64) winsize 62
2914 23:49:09.958293 [CA 4] Center 32 (2~63) winsize 62
2915 23:49:09.961507 [CA 5] Center 32 (2~62) winsize 61
2916 23:49:09.961589
2917 23:49:09.964785 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2918 23:49:09.964868
2919 23:49:09.968151 [CATrainingPosCal] consider 2 rank data
2920 23:49:09.971257 u2DelayCellTimex100 = 270/100 ps
2921 23:49:09.974607 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2922 23:49:09.978267 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2923 23:49:09.984605 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2924 23:49:09.988130 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2925 23:49:09.991436 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2926 23:49:09.994504 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2927 23:49:09.994587
2928 23:49:09.998373 CA PerBit enable=1, Macro0, CA PI delay=32
2929 23:49:09.998455
2930 23:49:10.001585 [CBTSetCACLKResult] CA Dly = 32
2931 23:49:10.001667 CS Dly: 6 (0~38)
2932 23:49:10.001732
2933 23:49:10.004630 ----->DramcWriteLeveling(PI) begin...
2934 23:49:10.007968 ==
2935 23:49:10.008050 Dram Type= 6, Freq= 0, CH_1, rank 0
2936 23:49:10.014952 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2937 23:49:10.015039 ==
2938 23:49:10.018249 Write leveling (Byte 0): 21 => 21
2939 23:49:10.021455 Write leveling (Byte 1): 23 => 23
2940 23:49:10.021538 DramcWriteLeveling(PI) end<-----
2941 23:49:10.024699
2942 23:49:10.024780 ==
2943 23:49:10.028029 Dram Type= 6, Freq= 0, CH_1, rank 0
2944 23:49:10.031410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2945 23:49:10.031494 ==
2946 23:49:10.034619 [Gating] SW mode calibration
2947 23:49:10.041184 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2948 23:49:10.044608 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2949 23:49:10.051381 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 23:49:10.054813 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2951 23:49:10.057856 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2952 23:49:10.064302 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 23:49:10.067629 0 11 16 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)
2954 23:49:10.071346 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2955 23:49:10.077890 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 23:49:10.080795 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 23:49:10.084177 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 23:49:10.091061 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 23:49:10.094351 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 23:49:10.097436 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2961 23:49:10.104146 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2962 23:49:10.107633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 23:49:10.111106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 23:49:10.117945 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 23:49:10.121249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 23:49:10.124783 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 23:49:10.131539 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 23:49:10.134679 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 23:49:10.137634 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2970 23:49:10.144134 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2971 23:49:10.147181 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2972 23:49:10.150523 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 23:49:10.157275 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 23:49:10.160841 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 23:49:10.164240 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 23:49:10.170830 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 23:49:10.173883 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 23:49:10.177393 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 23:49:10.183855 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 23:49:10.187440 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 23:49:10.190448 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 23:49:10.193774 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 23:49:10.200558 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 23:49:10.203883 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2985 23:49:10.207052 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2986 23:49:10.213495 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2987 23:49:10.216962 Total UI for P1: 0, mck2ui 16
2988 23:49:10.220275 best dqsien dly found for B0: ( 0, 15, 14)
2989 23:49:10.223559 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 23:49:10.227470 Total UI for P1: 0, mck2ui 16
2991 23:49:10.230699 best dqsien dly found for B1: ( 0, 15, 18)
2992 23:49:10.233652 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2993 23:49:10.237166 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2994 23:49:10.237277
2995 23:49:10.240897 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
2996 23:49:10.244267 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2997 23:49:10.247051 [Gating] SW calibration Done
2998 23:49:10.247160 ==
2999 23:49:10.250402 Dram Type= 6, Freq= 0, CH_1, rank 0
3000 23:49:10.257152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3001 23:49:10.257268 ==
3002 23:49:10.257411 RX Vref Scan: 0
3003 23:49:10.257509
3004 23:49:10.260423 RX Vref 0 -> 0, step: 1
3005 23:49:10.260528
3006 23:49:10.263814 RX Delay -40 -> 252, step: 8
3007 23:49:10.266955 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3008 23:49:10.270231 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3009 23:49:10.273733 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3010 23:49:10.277138 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3011 23:49:10.283807 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3012 23:49:10.286975 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3013 23:49:10.290310 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3014 23:49:10.293776 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3015 23:49:10.296875 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3016 23:49:10.303919 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3017 23:49:10.306835 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3018 23:49:10.310615 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3019 23:49:10.313420 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3020 23:49:10.316781 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3021 23:49:10.323495 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3022 23:49:10.327254 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3023 23:49:10.327338 ==
3024 23:49:10.330081 Dram Type= 6, Freq= 0, CH_1, rank 0
3025 23:49:10.333953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3026 23:49:10.334037 ==
3027 23:49:10.337129 DQS Delay:
3028 23:49:10.337211 DQS0 = 0, DQS1 = 0
3029 23:49:10.337275 DQM Delay:
3030 23:49:10.340451 DQM0 = 117, DQM1 = 108
3031 23:49:10.340533 DQ Delay:
3032 23:49:10.343676 DQ0 =119, DQ1 =111, DQ2 =111, DQ3 =115
3033 23:49:10.346977 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3034 23:49:10.350654 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3035 23:49:10.353752 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3036 23:49:10.356750
3037 23:49:10.356833
3038 23:49:10.356898 ==
3039 23:49:10.360475 Dram Type= 6, Freq= 0, CH_1, rank 0
3040 23:49:10.363783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3041 23:49:10.363868 ==
3042 23:49:10.363933
3043 23:49:10.363992
3044 23:49:10.367154 TX Vref Scan disable
3045 23:49:10.367236 == TX Byte 0 ==
3046 23:49:10.373657 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3047 23:49:10.377092 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3048 23:49:10.377180 == TX Byte 1 ==
3049 23:49:10.384124 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3050 23:49:10.387559 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3051 23:49:10.387648 ==
3052 23:49:10.390231 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 23:49:10.393449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3054 23:49:10.393534 ==
3055 23:49:10.405548 TX Vref=22, minBit 3, minWin=25, winSum=411
3056 23:49:10.409467 TX Vref=24, minBit 11, minWin=25, winSum=420
3057 23:49:10.412258 TX Vref=26, minBit 1, minWin=26, winSum=427
3058 23:49:10.415816 TX Vref=28, minBit 3, minWin=25, winSum=427
3059 23:49:10.419035 TX Vref=30, minBit 0, minWin=26, winSum=426
3060 23:49:10.422833 TX Vref=32, minBit 9, minWin=25, winSum=426
3061 23:49:10.429089 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 26
3062 23:49:10.429172
3063 23:49:10.432844 Final TX Range 1 Vref 26
3064 23:49:10.432927
3065 23:49:10.432991 ==
3066 23:49:10.435883 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 23:49:10.439654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3068 23:49:10.439736 ==
3069 23:49:10.439801
3070 23:49:10.442500
3071 23:49:10.442581 TX Vref Scan disable
3072 23:49:10.446386 == TX Byte 0 ==
3073 23:49:10.448981 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3074 23:49:10.452544 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3075 23:49:10.455637 == TX Byte 1 ==
3076 23:49:10.459186 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3077 23:49:10.462728 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3078 23:49:10.462811
3079 23:49:10.465669 [DATLAT]
3080 23:49:10.465751 Freq=1200, CH1 RK0
3081 23:49:10.465816
3082 23:49:10.469485 DATLAT Default: 0xd
3083 23:49:10.469567 0, 0xFFFF, sum = 0
3084 23:49:10.472447 1, 0xFFFF, sum = 0
3085 23:49:10.472530 2, 0xFFFF, sum = 0
3086 23:49:10.475910 3, 0xFFFF, sum = 0
3087 23:49:10.475993 4, 0xFFFF, sum = 0
3088 23:49:10.478931 5, 0xFFFF, sum = 0
3089 23:49:10.479017 6, 0xFFFF, sum = 0
3090 23:49:10.482138 7, 0xFFFF, sum = 0
3091 23:49:10.485775 8, 0xFFFF, sum = 0
3092 23:49:10.485860 9, 0xFFFF, sum = 0
3093 23:49:10.488949 10, 0xFFFF, sum = 0
3094 23:49:10.489033 11, 0x0, sum = 1
3095 23:49:10.492270 12, 0x0, sum = 2
3096 23:49:10.492353 13, 0x0, sum = 3
3097 23:49:10.492418 14, 0x0, sum = 4
3098 23:49:10.495987 best_step = 12
3099 23:49:10.496069
3100 23:49:10.496133 ==
3101 23:49:10.498970 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 23:49:10.502264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3103 23:49:10.502347 ==
3104 23:49:10.505673 RX Vref Scan: 1
3105 23:49:10.505755
3106 23:49:10.505819 Set Vref Range= 32 -> 127
3107 23:49:10.509104
3108 23:49:10.509222 RX Vref 32 -> 127, step: 1
3109 23:49:10.509344
3110 23:49:10.512357 RX Delay -21 -> 252, step: 4
3111 23:49:10.512458
3112 23:49:10.515967 Set Vref, RX VrefLevel [Byte0]: 32
3113 23:49:10.519116 [Byte1]: 32
3114 23:49:10.522332
3115 23:49:10.522415 Set Vref, RX VrefLevel [Byte0]: 33
3116 23:49:10.525745 [Byte1]: 33
3117 23:49:10.529886
3118 23:49:10.529990 Set Vref, RX VrefLevel [Byte0]: 34
3119 23:49:10.533250 [Byte1]: 34
3120 23:49:10.537985
3121 23:49:10.538092 Set Vref, RX VrefLevel [Byte0]: 35
3122 23:49:10.541430 [Byte1]: 35
3123 23:49:10.545835
3124 23:49:10.545941 Set Vref, RX VrefLevel [Byte0]: 36
3125 23:49:10.549385 [Byte1]: 36
3126 23:49:10.553873
3127 23:49:10.553977 Set Vref, RX VrefLevel [Byte0]: 37
3128 23:49:10.557081 [Byte1]: 37
3129 23:49:10.562106
3130 23:49:10.562211 Set Vref, RX VrefLevel [Byte0]: 38
3131 23:49:10.565019 [Byte1]: 38
3132 23:49:10.569794
3133 23:49:10.569902 Set Vref, RX VrefLevel [Byte0]: 39
3134 23:49:10.572958 [Byte1]: 39
3135 23:49:10.577757
3136 23:49:10.577865 Set Vref, RX VrefLevel [Byte0]: 40
3137 23:49:10.580827 [Byte1]: 40
3138 23:49:10.585717
3139 23:49:10.585802 Set Vref, RX VrefLevel [Byte0]: 41
3140 23:49:10.589062 [Byte1]: 41
3141 23:49:10.593511
3142 23:49:10.593593 Set Vref, RX VrefLevel [Byte0]: 42
3143 23:49:10.596624 [Byte1]: 42
3144 23:49:10.601714
3145 23:49:10.601795 Set Vref, RX VrefLevel [Byte0]: 43
3146 23:49:10.604876 [Byte1]: 43
3147 23:49:10.609460
3148 23:49:10.609542 Set Vref, RX VrefLevel [Byte0]: 44
3149 23:49:10.612625 [Byte1]: 44
3150 23:49:10.617112
3151 23:49:10.617195 Set Vref, RX VrefLevel [Byte0]: 45
3152 23:49:10.620714 [Byte1]: 45
3153 23:49:10.625240
3154 23:49:10.625357 Set Vref, RX VrefLevel [Byte0]: 46
3155 23:49:10.628374 [Byte1]: 46
3156 23:49:10.633245
3157 23:49:10.633365 Set Vref, RX VrefLevel [Byte0]: 47
3158 23:49:10.636330 [Byte1]: 47
3159 23:49:10.641072
3160 23:49:10.641154 Set Vref, RX VrefLevel [Byte0]: 48
3161 23:49:10.644148 [Byte1]: 48
3162 23:49:10.648798
3163 23:49:10.648883 Set Vref, RX VrefLevel [Byte0]: 49
3164 23:49:10.652327 [Byte1]: 49
3165 23:49:10.656787
3166 23:49:10.656871 Set Vref, RX VrefLevel [Byte0]: 50
3167 23:49:10.660091 [Byte1]: 50
3168 23:49:10.664804
3169 23:49:10.664887 Set Vref, RX VrefLevel [Byte0]: 51
3170 23:49:10.668306 [Byte1]: 51
3171 23:49:10.672639
3172 23:49:10.672720 Set Vref, RX VrefLevel [Byte0]: 52
3173 23:49:10.679182 [Byte1]: 52
3174 23:49:10.679271
3175 23:49:10.682670 Set Vref, RX VrefLevel [Byte0]: 53
3176 23:49:10.685531 [Byte1]: 53
3177 23:49:10.685617
3178 23:49:10.689263 Set Vref, RX VrefLevel [Byte0]: 54
3179 23:49:10.692350 [Byte1]: 54
3180 23:49:10.696496
3181 23:49:10.696578 Set Vref, RX VrefLevel [Byte0]: 55
3182 23:49:10.699552 [Byte1]: 55
3183 23:49:10.704447
3184 23:49:10.704531 Set Vref, RX VrefLevel [Byte0]: 56
3185 23:49:10.707662 [Byte1]: 56
3186 23:49:10.712117
3187 23:49:10.712202 Set Vref, RX VrefLevel [Byte0]: 57
3188 23:49:10.715700 [Byte1]: 57
3189 23:49:10.720411
3190 23:49:10.720495 Set Vref, RX VrefLevel [Byte0]: 58
3191 23:49:10.723349 [Byte1]: 58
3192 23:49:10.728000
3193 23:49:10.728085 Set Vref, RX VrefLevel [Byte0]: 59
3194 23:49:10.731396 [Byte1]: 59
3195 23:49:10.736013
3196 23:49:10.736099 Set Vref, RX VrefLevel [Byte0]: 60
3197 23:49:10.739803 [Byte1]: 60
3198 23:49:10.743841
3199 23:49:10.743923 Set Vref, RX VrefLevel [Byte0]: 61
3200 23:49:10.747351 [Byte1]: 61
3201 23:49:10.752017
3202 23:49:10.752103 Set Vref, RX VrefLevel [Byte0]: 62
3203 23:49:10.755238 [Byte1]: 62
3204 23:49:10.759849
3205 23:49:10.759936 Set Vref, RX VrefLevel [Byte0]: 63
3206 23:49:10.762880 [Byte1]: 63
3207 23:49:10.767751
3208 23:49:10.767834 Set Vref, RX VrefLevel [Byte0]: 64
3209 23:49:10.771374 [Byte1]: 64
3210 23:49:10.775385
3211 23:49:10.775467 Set Vref, RX VrefLevel [Byte0]: 65
3212 23:49:10.779019 [Byte1]: 65
3213 23:49:10.783497
3214 23:49:10.783581 Set Vref, RX VrefLevel [Byte0]: 66
3215 23:49:10.787068 [Byte1]: 66
3216 23:49:10.791513
3217 23:49:10.791596 Final RX Vref Byte 0 = 51 to rank0
3218 23:49:10.794561 Final RX Vref Byte 1 = 48 to rank0
3219 23:49:10.797992 Final RX Vref Byte 0 = 51 to rank1
3220 23:49:10.801692 Final RX Vref Byte 1 = 48 to rank1==
3221 23:49:10.805035 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 23:49:10.811462 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3223 23:49:10.811550 ==
3224 23:49:10.811616 DQS Delay:
3225 23:49:10.811676 DQS0 = 0, DQS1 = 0
3226 23:49:10.815012 DQM Delay:
3227 23:49:10.815094 DQM0 = 115, DQM1 = 105
3228 23:49:10.818266 DQ Delay:
3229 23:49:10.821605 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3230 23:49:10.825017 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3231 23:49:10.827992 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3232 23:49:10.831511 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =112
3233 23:49:10.831595
3234 23:49:10.831660
3235 23:49:10.838055 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3236 23:49:10.841709 CH1 RK0: MR19=404, MR18=1C1C
3237 23:49:10.848173 CH1_RK0: MR19=0x404, MR18=0x1C1C, DQSOSC=399, MR23=63, INC=41, DEC=27
3238 23:49:10.848267
3239 23:49:10.851542 ----->DramcWriteLeveling(PI) begin...
3240 23:49:10.851626 ==
3241 23:49:10.854900 Dram Type= 6, Freq= 0, CH_1, rank 1
3242 23:49:10.858609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3243 23:49:10.858700 ==
3244 23:49:10.861450 Write leveling (Byte 0): 23 => 23
3245 23:49:10.864939 Write leveling (Byte 1): 22 => 22
3246 23:49:10.868093 DramcWriteLeveling(PI) end<-----
3247 23:49:10.868177
3248 23:49:10.868246 ==
3249 23:49:10.872163 Dram Type= 6, Freq= 0, CH_1, rank 1
3250 23:49:10.878380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3251 23:49:10.878517 ==
3252 23:49:10.878669 [Gating] SW mode calibration
3253 23:49:10.888489 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3254 23:49:10.891423 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3255 23:49:10.894930 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3256 23:49:10.901629 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3257 23:49:10.905157 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3258 23:49:10.908411 0 11 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3259 23:49:10.914812 0 11 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
3260 23:49:10.918417 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3261 23:49:10.921410 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3262 23:49:10.928347 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3263 23:49:10.931812 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3264 23:49:10.934903 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 23:49:10.941473 0 12 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
3266 23:49:10.944826 0 12 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3267 23:49:10.948034 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
3268 23:49:10.955007 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 23:49:10.958162 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 23:49:10.961334 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3271 23:49:10.968239 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 23:49:10.971160 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 23:49:10.974805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 23:49:10.981530 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3275 23:49:10.985415 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3276 23:49:10.988145 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 23:49:10.991420 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 23:49:10.997764 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 23:49:11.001402 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 23:49:11.004502 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 23:49:11.011391 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 23:49:11.014522 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 23:49:11.018012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 23:49:11.024824 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 23:49:11.027839 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 23:49:11.031175 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 23:49:11.037987 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 23:49:11.041491 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 23:49:11.044708 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 23:49:11.051349 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3291 23:49:11.054640 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3292 23:49:11.057890 Total UI for P1: 0, mck2ui 16
3293 23:49:11.061218 best dqsien dly found for B0: ( 0, 15, 12)
3294 23:49:11.065087 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3295 23:49:11.071133 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3296 23:49:11.071259 Total UI for P1: 0, mck2ui 16
3297 23:49:11.074666 best dqsien dly found for B1: ( 0, 15, 18)
3298 23:49:11.081293 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3299 23:49:11.084290 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3300 23:49:11.084401
3301 23:49:11.087938 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3302 23:49:11.091262 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3303 23:49:11.094689 [Gating] SW calibration Done
3304 23:49:11.094774 ==
3305 23:49:11.097858 Dram Type= 6, Freq= 0, CH_1, rank 1
3306 23:49:11.101422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3307 23:49:11.101510 ==
3308 23:49:11.104780 RX Vref Scan: 0
3309 23:49:11.104862
3310 23:49:11.104925 RX Vref 0 -> 0, step: 1
3311 23:49:11.104984
3312 23:49:11.107794 RX Delay -40 -> 252, step: 8
3313 23:49:11.110952 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3314 23:49:11.118031 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3315 23:49:11.121144 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3316 23:49:11.124672 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3317 23:49:11.128386 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3318 23:49:11.131164 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3319 23:49:11.134769 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3320 23:49:11.141285 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3321 23:49:11.144825 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3322 23:49:11.148067 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3323 23:49:11.151519 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3324 23:49:11.154687 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3325 23:49:11.161179 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3326 23:49:11.165050 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3327 23:49:11.167961 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3328 23:49:11.171132 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3329 23:49:11.171214 ==
3330 23:49:11.174425 Dram Type= 6, Freq= 0, CH_1, rank 1
3331 23:49:11.181202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3332 23:49:11.181352 ==
3333 23:49:11.181419 DQS Delay:
3334 23:49:11.181479 DQS0 = 0, DQS1 = 0
3335 23:49:11.184699 DQM Delay:
3336 23:49:11.184780 DQM0 = 116, DQM1 = 106
3337 23:49:11.188169 DQ Delay:
3338 23:49:11.191349 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3339 23:49:11.195060 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115
3340 23:49:11.197940 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3341 23:49:11.201514 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3342 23:49:11.201598
3343 23:49:11.201661
3344 23:49:11.201719 ==
3345 23:49:11.204636 Dram Type= 6, Freq= 0, CH_1, rank 1
3346 23:49:11.207839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3347 23:49:11.207923 ==
3348 23:49:11.207988
3349 23:49:11.211274
3350 23:49:11.211355 TX Vref Scan disable
3351 23:49:11.214602 == TX Byte 0 ==
3352 23:49:11.217914 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3353 23:49:11.221135 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3354 23:49:11.224629 == TX Byte 1 ==
3355 23:49:11.227860 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3356 23:49:11.231254 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3357 23:49:11.231339 ==
3358 23:49:11.234676 Dram Type= 6, Freq= 0, CH_1, rank 1
3359 23:49:11.241187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3360 23:49:11.241274 ==
3361 23:49:11.251277 TX Vref=22, minBit 1, minWin=25, winSum=419
3362 23:49:11.254817 TX Vref=24, minBit 9, minWin=25, winSum=426
3363 23:49:11.257978 TX Vref=26, minBit 1, minWin=26, winSum=426
3364 23:49:11.261598 TX Vref=28, minBit 3, minWin=26, winSum=430
3365 23:49:11.264674 TX Vref=30, minBit 9, minWin=26, winSum=435
3366 23:49:11.268295 TX Vref=32, minBit 0, minWin=26, winSum=431
3367 23:49:11.274621 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3368 23:49:11.274709
3369 23:49:11.278030 Final TX Range 1 Vref 30
3370 23:49:11.278115
3371 23:49:11.278200 ==
3372 23:49:11.281665 Dram Type= 6, Freq= 0, CH_1, rank 1
3373 23:49:11.284878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3374 23:49:11.284965 ==
3375 23:49:11.285066
3376 23:49:11.288005
3377 23:49:11.288090 TX Vref Scan disable
3378 23:49:11.291367 == TX Byte 0 ==
3379 23:49:11.294912 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3380 23:49:11.297890 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3381 23:49:11.301438 == TX Byte 1 ==
3382 23:49:11.305054 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3383 23:49:11.308191 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3384 23:49:11.308276
3385 23:49:11.311454 [DATLAT]
3386 23:49:11.311537 Freq=1200, CH1 RK1
3387 23:49:11.311622
3388 23:49:11.315221 DATLAT Default: 0xc
3389 23:49:11.315306 0, 0xFFFF, sum = 0
3390 23:49:11.318394 1, 0xFFFF, sum = 0
3391 23:49:11.318481 2, 0xFFFF, sum = 0
3392 23:49:11.321537 3, 0xFFFF, sum = 0
3393 23:49:11.321624 4, 0xFFFF, sum = 0
3394 23:49:11.325147 5, 0xFFFF, sum = 0
3395 23:49:11.325232 6, 0xFFFF, sum = 0
3396 23:49:11.328662 7, 0xFFFF, sum = 0
3397 23:49:11.328748 8, 0xFFFF, sum = 0
3398 23:49:11.331521 9, 0xFFFF, sum = 0
3399 23:49:11.334690 10, 0xFFFF, sum = 0
3400 23:49:11.334784 11, 0x0, sum = 1
3401 23:49:11.334853 12, 0x0, sum = 2
3402 23:49:11.338457 13, 0x0, sum = 3
3403 23:49:11.338540 14, 0x0, sum = 4
3404 23:49:11.341671 best_step = 12
3405 23:49:11.341753
3406 23:49:11.341817 ==
3407 23:49:11.344958 Dram Type= 6, Freq= 0, CH_1, rank 1
3408 23:49:11.348260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3409 23:49:11.348344 ==
3410 23:49:11.351363 RX Vref Scan: 0
3411 23:49:11.351444
3412 23:49:11.351508 RX Vref 0 -> 0, step: 1
3413 23:49:11.351568
3414 23:49:11.354666 RX Delay -29 -> 252, step: 4
3415 23:49:11.361711 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3416 23:49:11.365096 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3417 23:49:11.368181 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3418 23:49:11.371734 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3419 23:49:11.375199 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3420 23:49:11.381792 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3421 23:49:11.385219 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3422 23:49:11.388598 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3423 23:49:11.391583 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3424 23:49:11.394914 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3425 23:49:11.401439 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3426 23:49:11.405263 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3427 23:49:11.408295 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3428 23:49:11.411723 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3429 23:49:11.414871 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3430 23:49:11.421400 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3431 23:49:11.421486 ==
3432 23:49:11.425153 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 23:49:11.428145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3434 23:49:11.428229 ==
3435 23:49:11.428294 DQS Delay:
3436 23:49:11.431721 DQS0 = 0, DQS1 = 0
3437 23:49:11.431803 DQM Delay:
3438 23:49:11.435127 DQM0 = 115, DQM1 = 104
3439 23:49:11.435209 DQ Delay:
3440 23:49:11.438404 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3441 23:49:11.441742 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3442 23:49:11.444678 DQ8 =88, DQ9 =92, DQ10 =106, DQ11 =98
3443 23:49:11.448266 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =110
3444 23:49:11.448348
3445 23:49:11.448412
3446 23:49:11.458071 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3447 23:49:11.461770 CH1 RK1: MR19=404, MR18=B0B
3448 23:49:11.464898 CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3449 23:49:11.468137 [RxdqsGatingPostProcess] freq 1200
3450 23:49:11.474958 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3451 23:49:11.478372 Pre-setting of DQS Precalculation
3452 23:49:11.481693 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3453 23:49:11.491556 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3454 23:49:11.498552 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3455 23:49:11.498637
3456 23:49:11.498701
3457 23:49:11.501635 [Calibration Summary] 2400 Mbps
3458 23:49:11.501717 CH 0, Rank 0
3459 23:49:11.505103 SW Impedance : PASS
3460 23:49:11.505185 DUTY Scan : NO K
3461 23:49:11.508443 ZQ Calibration : PASS
3462 23:49:11.511632 Jitter Meter : NO K
3463 23:49:11.511714 CBT Training : PASS
3464 23:49:11.514939 Write leveling : PASS
3465 23:49:11.518154 RX DQS gating : PASS
3466 23:49:11.518236 RX DQ/DQS(RDDQC) : PASS
3467 23:49:11.521646 TX DQ/DQS : PASS
3468 23:49:11.521728 RX DATLAT : PASS
3469 23:49:11.524677 RX DQ/DQS(Engine): PASS
3470 23:49:11.528029 TX OE : NO K
3471 23:49:11.528111 All Pass.
3472 23:49:11.528176
3473 23:49:11.528235 CH 0, Rank 1
3474 23:49:11.531328 SW Impedance : PASS
3475 23:49:11.534882 DUTY Scan : NO K
3476 23:49:11.534963 ZQ Calibration : PASS
3477 23:49:11.537905 Jitter Meter : NO K
3478 23:49:11.541548 CBT Training : PASS
3479 23:49:11.541628 Write leveling : PASS
3480 23:49:11.544706 RX DQS gating : PASS
3481 23:49:11.547863 RX DQ/DQS(RDDQC) : PASS
3482 23:49:11.547944 TX DQ/DQS : PASS
3483 23:49:11.551227 RX DATLAT : PASS
3484 23:49:11.554510 RX DQ/DQS(Engine): PASS
3485 23:49:11.554591 TX OE : NO K
3486 23:49:11.558487 All Pass.
3487 23:49:11.558568
3488 23:49:11.558632 CH 1, Rank 0
3489 23:49:11.561233 SW Impedance : PASS
3490 23:49:11.561324 DUTY Scan : NO K
3491 23:49:11.564603 ZQ Calibration : PASS
3492 23:49:11.567802 Jitter Meter : NO K
3493 23:49:11.567883 CBT Training : PASS
3494 23:49:11.570948 Write leveling : PASS
3495 23:49:11.574729 RX DQS gating : PASS
3496 23:49:11.574810 RX DQ/DQS(RDDQC) : PASS
3497 23:49:11.577835 TX DQ/DQS : PASS
3498 23:49:11.577916 RX DATLAT : PASS
3499 23:49:11.581235 RX DQ/DQS(Engine): PASS
3500 23:49:11.584901 TX OE : NO K
3501 23:49:11.584984 All Pass.
3502 23:49:11.585048
3503 23:49:11.585107 CH 1, Rank 1
3504 23:49:11.588048 SW Impedance : PASS
3505 23:49:11.591513 DUTY Scan : NO K
3506 23:49:11.591594 ZQ Calibration : PASS
3507 23:49:11.594468 Jitter Meter : NO K
3508 23:49:11.597626 CBT Training : PASS
3509 23:49:11.597708 Write leveling : PASS
3510 23:49:11.600791 RX DQS gating : PASS
3511 23:49:11.604306 RX DQ/DQS(RDDQC) : PASS
3512 23:49:11.604387 TX DQ/DQS : PASS
3513 23:49:11.607490 RX DATLAT : PASS
3514 23:49:11.610790 RX DQ/DQS(Engine): PASS
3515 23:49:11.610871 TX OE : NO K
3516 23:49:11.614433 All Pass.
3517 23:49:11.614513
3518 23:49:11.614577 DramC Write-DBI off
3519 23:49:11.617441 PER_BANK_REFRESH: Hybrid Mode
3520 23:49:11.617551 TX_TRACKING: ON
3521 23:49:11.627887 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3522 23:49:11.630711 [FAST_K] Save calibration result to emmc
3523 23:49:11.634684 dramc_set_vcore_voltage set vcore to 650000
3524 23:49:11.637226 Read voltage for 600, 5
3525 23:49:11.637370 Vio18 = 0
3526 23:49:11.640953 Vcore = 650000
3527 23:49:11.641062 Vdram = 0
3528 23:49:11.641158 Vddq = 0
3529 23:49:11.643991 Vmddr = 0
3530 23:49:11.647747 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3531 23:49:11.654213 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3532 23:49:11.654322 MEM_TYPE=3, freq_sel=19
3533 23:49:11.657616 sv_algorithm_assistance_LP4_1600
3534 23:49:11.660697 ============ PULL DRAM RESETB DOWN ============
3535 23:49:11.667491 ========== PULL DRAM RESETB DOWN end =========
3536 23:49:11.671095 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3537 23:49:11.674027 ===================================
3538 23:49:11.677419 LPDDR4 DRAM CONFIGURATION
3539 23:49:11.681092 ===================================
3540 23:49:11.681203 EX_ROW_EN[0] = 0x0
3541 23:49:11.684298 EX_ROW_EN[1] = 0x0
3542 23:49:11.684403 LP4Y_EN = 0x0
3543 23:49:11.687397 WORK_FSP = 0x0
3544 23:49:11.690702 WL = 0x2
3545 23:49:11.690808 RL = 0x2
3546 23:49:11.694031 BL = 0x2
3547 23:49:11.694137 RPST = 0x0
3548 23:49:11.697398 RD_PRE = 0x0
3549 23:49:11.697504 WR_PRE = 0x1
3550 23:49:11.700687 WR_PST = 0x0
3551 23:49:11.700792 DBI_WR = 0x0
3552 23:49:11.704418 DBI_RD = 0x0
3553 23:49:11.704521 OTF = 0x1
3554 23:49:11.707642 ===================================
3555 23:49:11.710834 ===================================
3556 23:49:11.713856 ANA top config
3557 23:49:11.717213 ===================================
3558 23:49:11.717352 DLL_ASYNC_EN = 0
3559 23:49:11.720652 ALL_SLAVE_EN = 1
3560 23:49:11.724173 NEW_RANK_MODE = 1
3561 23:49:11.727345 DLL_IDLE_MODE = 1
3562 23:49:11.727451 LP45_APHY_COMB_EN = 1
3563 23:49:11.730479 TX_ODT_DIS = 1
3564 23:49:11.734091 NEW_8X_MODE = 1
3565 23:49:11.737574 ===================================
3566 23:49:11.740500 ===================================
3567 23:49:11.744012 data_rate = 1200
3568 23:49:11.747111 CKR = 1
3569 23:49:11.750449 DQ_P2S_RATIO = 8
3570 23:49:11.753705 ===================================
3571 23:49:11.753812 CA_P2S_RATIO = 8
3572 23:49:11.757113 DQ_CA_OPEN = 0
3573 23:49:11.760445 DQ_SEMI_OPEN = 0
3574 23:49:11.764208 CA_SEMI_OPEN = 0
3575 23:49:11.767040 CA_FULL_RATE = 0
3576 23:49:11.770331 DQ_CKDIV4_EN = 1
3577 23:49:11.770415 CA_CKDIV4_EN = 1
3578 23:49:11.773931 CA_PREDIV_EN = 0
3579 23:49:11.776836 PH8_DLY = 0
3580 23:49:11.780322 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3581 23:49:11.783990 DQ_AAMCK_DIV = 4
3582 23:49:11.787121 CA_AAMCK_DIV = 4
3583 23:49:11.787204 CA_ADMCK_DIV = 4
3584 23:49:11.790471 DQ_TRACK_CA_EN = 0
3585 23:49:11.793387 CA_PICK = 600
3586 23:49:11.796906 CA_MCKIO = 600
3587 23:49:11.800079 MCKIO_SEMI = 0
3588 23:49:11.803682 PLL_FREQ = 2288
3589 23:49:11.806811 DQ_UI_PI_RATIO = 32
3590 23:49:11.806894 CA_UI_PI_RATIO = 0
3591 23:49:11.810274 ===================================
3592 23:49:11.813308 ===================================
3593 23:49:11.816978 memory_type:LPDDR4
3594 23:49:11.820304 GP_NUM : 10
3595 23:49:11.820386 SRAM_EN : 1
3596 23:49:11.823308 MD32_EN : 0
3597 23:49:11.826958 ===================================
3598 23:49:11.830138 [ANA_INIT] >>>>>>>>>>>>>>
3599 23:49:11.833587 <<<<<< [CONFIGURE PHASE]: ANA_TX
3600 23:49:11.836734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3601 23:49:11.839967 ===================================
3602 23:49:11.840049 data_rate = 1200,PCW = 0X5800
3603 23:49:11.843522 ===================================
3604 23:49:11.846920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3605 23:49:11.853576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3606 23:49:11.859740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3607 23:49:11.863394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3608 23:49:11.866492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3609 23:49:11.869835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3610 23:49:11.875010 [ANA_INIT] flow start
3611 23:49:11.876389 [ANA_INIT] PLL >>>>>>>>
3612 23:49:11.876472 [ANA_INIT] PLL <<<<<<<<
3613 23:49:11.879555 [ANA_INIT] MIDPI >>>>>>>>
3614 23:49:11.883033 [ANA_INIT] MIDPI <<<<<<<<
3615 23:49:11.883120 [ANA_INIT] DLL >>>>>>>>
3616 23:49:11.886199 [ANA_INIT] flow end
3617 23:49:11.889638 ============ LP4 DIFF to SE enter ============
3618 23:49:11.892811 ============ LP4 DIFF to SE exit ============
3619 23:49:11.896253 [ANA_INIT] <<<<<<<<<<<<<
3620 23:49:11.899554 [Flow] Enable top DCM control >>>>>
3621 23:49:11.903077 [Flow] Enable top DCM control <<<<<
3622 23:49:11.906374 Enable DLL master slave shuffle
3623 23:49:11.912783 ==============================================================
3624 23:49:11.912879 Gating Mode config
3625 23:49:11.919771 ==============================================================
3626 23:49:11.919866 Config description:
3627 23:49:11.929596 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3628 23:49:11.935859 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3629 23:49:11.942757 SELPH_MODE 0: By rank 1: By Phase
3630 23:49:11.946104 ==============================================================
3631 23:49:11.949202 GAT_TRACK_EN = 1
3632 23:49:11.953096 RX_GATING_MODE = 2
3633 23:49:11.956603 RX_GATING_TRACK_MODE = 2
3634 23:49:11.959488 SELPH_MODE = 1
3635 23:49:11.962663 PICG_EARLY_EN = 1
3636 23:49:11.966321 VALID_LAT_VALUE = 1
3637 23:49:11.972547 ==============================================================
3638 23:49:11.975596 Enter into Gating configuration >>>>
3639 23:49:11.978787 Exit from Gating configuration <<<<
3640 23:49:11.982648 Enter into DVFS_PRE_config >>>>>
3641 23:49:11.992445 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3642 23:49:11.995623 Exit from DVFS_PRE_config <<<<<
3643 23:49:11.998788 Enter into PICG configuration >>>>
3644 23:49:12.002338 Exit from PICG configuration <<<<
3645 23:49:12.005518 [RX_INPUT] configuration >>>>>
3646 23:49:12.005626 [RX_INPUT] configuration <<<<<
3647 23:49:12.012128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3648 23:49:12.018779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3649 23:49:12.021982 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3650 23:49:12.028596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3651 23:49:12.035114 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3652 23:49:12.042080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3653 23:49:12.044964 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3654 23:49:12.048316 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3655 23:49:12.054978 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3656 23:49:12.058512 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3657 23:49:12.061800 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3658 23:49:12.068182 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3659 23:49:12.071521 ===================================
3660 23:49:12.071643 LPDDR4 DRAM CONFIGURATION
3661 23:49:12.074811 ===================================
3662 23:49:12.078441 EX_ROW_EN[0] = 0x0
3663 23:49:12.081246 EX_ROW_EN[1] = 0x0
3664 23:49:12.081379 LP4Y_EN = 0x0
3665 23:49:12.084580 WORK_FSP = 0x0
3666 23:49:12.084686 WL = 0x2
3667 23:49:12.088358 RL = 0x2
3668 23:49:12.088465 BL = 0x2
3669 23:49:12.091237 RPST = 0x0
3670 23:49:12.091359 RD_PRE = 0x0
3671 23:49:12.094809 WR_PRE = 0x1
3672 23:49:12.094914 WR_PST = 0x0
3673 23:49:12.098093 DBI_WR = 0x0
3674 23:49:12.098202 DBI_RD = 0x0
3675 23:49:12.101253 OTF = 0x1
3676 23:49:12.104962 ===================================
3677 23:49:12.107942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3678 23:49:12.111186 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3679 23:49:12.117974 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3680 23:49:12.120979 ===================================
3681 23:49:12.121090 LPDDR4 DRAM CONFIGURATION
3682 23:49:12.124559 ===================================
3683 23:49:12.127747 EX_ROW_EN[0] = 0x10
3684 23:49:12.130972 EX_ROW_EN[1] = 0x0
3685 23:49:12.131078 LP4Y_EN = 0x0
3686 23:49:12.134106 WORK_FSP = 0x0
3687 23:49:12.134210 WL = 0x2
3688 23:49:12.137529 RL = 0x2
3689 23:49:12.137644 BL = 0x2
3690 23:49:12.141118 RPST = 0x0
3691 23:49:12.141226 RD_PRE = 0x0
3692 23:49:12.144117 WR_PRE = 0x1
3693 23:49:12.144221 WR_PST = 0x0
3694 23:49:12.147522 DBI_WR = 0x0
3695 23:49:12.147627 DBI_RD = 0x0
3696 23:49:12.150987 OTF = 0x1
3697 23:49:12.154241 ===================================
3698 23:49:12.160803 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3699 23:49:12.164168 nWR fixed to 30
3700 23:49:12.164258 [ModeRegInit_LP4] CH0 RK0
3701 23:49:12.167465 [ModeRegInit_LP4] CH0 RK1
3702 23:49:12.170784 [ModeRegInit_LP4] CH1 RK0
3703 23:49:12.173840 [ModeRegInit_LP4] CH1 RK1
3704 23:49:12.173924 match AC timing 16
3705 23:49:12.177514 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3706 23:49:12.184103 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3707 23:49:12.187164 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3708 23:49:12.194217 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3709 23:49:12.197208 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3710 23:49:12.197356 ==
3711 23:49:12.200261 Dram Type= 6, Freq= 0, CH_0, rank 0
3712 23:49:12.203663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3713 23:49:12.203754 ==
3714 23:49:12.210604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3715 23:49:12.216919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3716 23:49:12.220379 [CA 0] Center 35 (5~66) winsize 62
3717 23:49:12.223584 [CA 1] Center 35 (5~66) winsize 62
3718 23:49:12.227275 [CA 2] Center 34 (4~65) winsize 62
3719 23:49:12.230549 [CA 3] Center 34 (4~65) winsize 62
3720 23:49:12.233650 [CA 4] Center 33 (3~64) winsize 62
3721 23:49:12.237002 [CA 5] Center 33 (3~64) winsize 62
3722 23:49:12.237084
3723 23:49:12.240201 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3724 23:49:12.240284
3725 23:49:12.243598 [CATrainingPosCal] consider 1 rank data
3726 23:49:12.247374 u2DelayCellTimex100 = 270/100 ps
3727 23:49:12.250169 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3728 23:49:12.253424 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3729 23:49:12.256951 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3730 23:49:12.260086 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3731 23:49:12.263954 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3732 23:49:12.267368 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3733 23:49:12.267450
3734 23:49:12.273517 CA PerBit enable=1, Macro0, CA PI delay=33
3735 23:49:12.273603
3736 23:49:12.273688 [CBTSetCACLKResult] CA Dly = 33
3737 23:49:12.276892 CS Dly: 5 (0~36)
3738 23:49:12.277000 ==
3739 23:49:12.280390 Dram Type= 6, Freq= 0, CH_0, rank 1
3740 23:49:12.283390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3741 23:49:12.283476 ==
3742 23:49:12.290264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3743 23:49:12.296758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3744 23:49:12.299914 [CA 0] Center 35 (5~66) winsize 62
3745 23:49:12.303154 [CA 1] Center 35 (5~66) winsize 62
3746 23:49:12.306446 [CA 2] Center 34 (4~65) winsize 62
3747 23:49:12.309750 [CA 3] Center 34 (4~65) winsize 62
3748 23:49:12.313063 [CA 4] Center 33 (3~64) winsize 62
3749 23:49:12.316411 [CA 5] Center 33 (3~64) winsize 62
3750 23:49:12.316496
3751 23:49:12.319825 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3752 23:49:12.319909
3753 23:49:12.323078 [CATrainingPosCal] consider 2 rank data
3754 23:49:12.326746 u2DelayCellTimex100 = 270/100 ps
3755 23:49:12.329724 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3756 23:49:12.333309 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3757 23:49:12.336520 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3758 23:49:12.340063 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3759 23:49:12.343103 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3760 23:49:12.346441 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3761 23:49:12.349979
3762 23:49:12.353488 CA PerBit enable=1, Macro0, CA PI delay=33
3763 23:49:12.353573
3764 23:49:12.356770 [CBTSetCACLKResult] CA Dly = 33
3765 23:49:12.356854 CS Dly: 4 (0~35)
3766 23:49:12.356940
3767 23:49:12.359600 ----->DramcWriteLeveling(PI) begin...
3768 23:49:12.359685 ==
3769 23:49:12.362859 Dram Type= 6, Freq= 0, CH_0, rank 0
3770 23:49:12.366540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3771 23:49:12.369577 ==
3772 23:49:12.369661 Write leveling (Byte 0): 30 => 30
3773 23:49:12.373069 Write leveling (Byte 1): 31 => 31
3774 23:49:12.376324 DramcWriteLeveling(PI) end<-----
3775 23:49:12.376408
3776 23:49:12.376492 ==
3777 23:49:12.379687 Dram Type= 6, Freq= 0, CH_0, rank 0
3778 23:49:12.386313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3779 23:49:12.386401 ==
3780 23:49:12.386487 [Gating] SW mode calibration
3781 23:49:12.396153 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3782 23:49:12.399406 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3783 23:49:12.402620 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3784 23:49:12.409325 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3785 23:49:12.412857 0 5 8 | B1->B0 | 3333 3232 | 1 1 | (0 0) (1 0)
3786 23:49:12.416354 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3787 23:49:12.422555 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3788 23:49:12.426212 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3789 23:49:12.429462 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3790 23:49:12.436173 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 23:49:12.439455 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 23:49:12.442660 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3793 23:49:12.449456 0 6 8 | B1->B0 | 3030 3232 | 0 1 | (0 0) (0 0)
3794 23:49:12.453204 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3795 23:49:12.456190 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3796 23:49:12.462487 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3797 23:49:12.466061 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3798 23:49:12.469265 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 23:49:12.475842 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 23:49:12.478966 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 23:49:12.482578 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3802 23:49:12.489491 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3803 23:49:12.492892 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3804 23:49:12.496000 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3805 23:49:12.502440 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 23:49:12.505536 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 23:49:12.508769 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 23:49:12.515683 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 23:49:12.519081 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 23:49:12.522138 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 23:49:12.528628 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 23:49:12.532093 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 23:49:12.535207 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 23:49:12.541958 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 23:49:12.545453 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 23:49:12.548548 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 23:49:12.555259 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3818 23:49:12.558207 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3819 23:49:12.561650 Total UI for P1: 0, mck2ui 16
3820 23:49:12.565051 best dqsien dly found for B0: ( 0, 9, 8)
3821 23:49:12.568466 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3822 23:49:12.571882 Total UI for P1: 0, mck2ui 16
3823 23:49:12.575101 best dqsien dly found for B1: ( 0, 9, 10)
3824 23:49:12.578418 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3825 23:49:12.581582 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3826 23:49:12.581691
3827 23:49:12.584856 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3828 23:49:12.591408 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3829 23:49:12.591496 [Gating] SW calibration Done
3830 23:49:12.594917 ==
3831 23:49:12.598092 Dram Type= 6, Freq= 0, CH_0, rank 0
3832 23:49:12.601269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3833 23:49:12.601387 ==
3834 23:49:12.601488 RX Vref Scan: 0
3835 23:49:12.601585
3836 23:49:12.604496 RX Vref 0 -> 0, step: 1
3837 23:49:12.604592
3838 23:49:12.608169 RX Delay -230 -> 252, step: 16
3839 23:49:12.611246 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3840 23:49:12.614447 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3841 23:49:12.621556 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3842 23:49:12.624386 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3843 23:49:12.627858 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3844 23:49:12.631020 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3845 23:49:12.638019 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3846 23:49:12.640996 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3847 23:49:12.644169 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3848 23:49:12.647929 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3849 23:49:12.651165 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3850 23:49:12.657509 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3851 23:49:12.660710 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3852 23:49:12.664234 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3853 23:49:12.667743 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3854 23:49:12.674476 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3855 23:49:12.674562 ==
3856 23:49:12.677463 Dram Type= 6, Freq= 0, CH_0, rank 0
3857 23:49:12.680739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3858 23:49:12.680825 ==
3859 23:49:12.680910 DQS Delay:
3860 23:49:12.684107 DQS0 = 0, DQS1 = 0
3861 23:49:12.684193 DQM Delay:
3862 23:49:12.687527 DQM0 = 38, DQM1 = 33
3863 23:49:12.687611 DQ Delay:
3864 23:49:12.690595 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3865 23:49:12.694132 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3866 23:49:12.697201 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3867 23:49:12.700428 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3868 23:49:12.700513
3869 23:49:12.700597
3870 23:49:12.700678 ==
3871 23:49:12.703677 Dram Type= 6, Freq= 0, CH_0, rank 0
3872 23:49:12.707173 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3873 23:49:12.710334 ==
3874 23:49:12.710418
3875 23:49:12.710501
3876 23:49:12.710599 TX Vref Scan disable
3877 23:49:12.713680 == TX Byte 0 ==
3878 23:49:12.716978 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3879 23:49:12.723871 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3880 23:49:12.723957 == TX Byte 1 ==
3881 23:49:12.726787 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3882 23:49:12.733607 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3883 23:49:12.733692 ==
3884 23:49:12.736648 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 23:49:12.740299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 23:49:12.740384 ==
3887 23:49:12.740469
3888 23:49:12.740549
3889 23:49:12.743552 TX Vref Scan disable
3890 23:49:12.746609 == TX Byte 0 ==
3891 23:49:12.750060 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3892 23:49:12.753517 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3893 23:49:12.756391 == TX Byte 1 ==
3894 23:49:12.759729 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3895 23:49:12.763182 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3896 23:49:12.763289
3897 23:49:12.763382 [DATLAT]
3898 23:49:12.766530 Freq=600, CH0 RK0
3899 23:49:12.766635
3900 23:49:12.769850 DATLAT Default: 0x9
3901 23:49:12.769955 0, 0xFFFF, sum = 0
3902 23:49:12.773236 1, 0xFFFF, sum = 0
3903 23:49:12.773382 2, 0xFFFF, sum = 0
3904 23:49:12.776468 3, 0xFFFF, sum = 0
3905 23:49:12.776574 4, 0xFFFF, sum = 0
3906 23:49:12.779635 5, 0xFFFF, sum = 0
3907 23:49:12.779746 6, 0xFFFF, sum = 0
3908 23:49:12.783179 7, 0x0, sum = 1
3909 23:49:12.783290 8, 0x0, sum = 2
3910 23:49:12.786211 9, 0x0, sum = 3
3911 23:49:12.786321 10, 0x0, sum = 4
3912 23:49:12.786414 best_step = 8
3913 23:49:12.786503
3914 23:49:12.789856 ==
3915 23:49:12.792803 Dram Type= 6, Freq= 0, CH_0, rank 0
3916 23:49:12.796561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3917 23:49:12.796667 ==
3918 23:49:12.796760 RX Vref Scan: 1
3919 23:49:12.796848
3920 23:49:12.799570 RX Vref 0 -> 0, step: 1
3921 23:49:12.799673
3922 23:49:12.802920 RX Delay -195 -> 252, step: 8
3923 23:49:12.803024
3924 23:49:12.806180 Set Vref, RX VrefLevel [Byte0]: 47
3925 23:49:12.809555 [Byte1]: 50
3926 23:49:12.809662
3927 23:49:12.812825 Final RX Vref Byte 0 = 47 to rank0
3928 23:49:12.816186 Final RX Vref Byte 1 = 50 to rank0
3929 23:49:12.819218 Final RX Vref Byte 0 = 47 to rank1
3930 23:49:12.822659 Final RX Vref Byte 1 = 50 to rank1==
3931 23:49:12.826010 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 23:49:12.829550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3933 23:49:12.832604 ==
3934 23:49:12.832712 DQS Delay:
3935 23:49:12.832805 DQS0 = 0, DQS1 = 0
3936 23:49:12.835769 DQM Delay:
3937 23:49:12.835872 DQM0 = 40, DQM1 = 31
3938 23:49:12.839410 DQ Delay:
3939 23:49:12.839515 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3940 23:49:12.842763 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52
3941 23:49:12.846206 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =20
3942 23:49:12.849064 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
3943 23:49:12.852750
3944 23:49:12.852856
3945 23:49:12.859026 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3946 23:49:12.862529 CH0 RK0: MR19=808, MR18=5252
3947 23:49:12.869028 CH0_RK0: MR19=0x808, MR18=0x5252, DQSOSC=394, MR23=63, INC=168, DEC=112
3948 23:49:12.869136
3949 23:49:12.872089 ----->DramcWriteLeveling(PI) begin...
3950 23:49:12.872196 ==
3951 23:49:12.875606 Dram Type= 6, Freq= 0, CH_0, rank 1
3952 23:49:12.878775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3953 23:49:12.878881 ==
3954 23:49:12.881973 Write leveling (Byte 0): 30 => 30
3955 23:49:12.885600 Write leveling (Byte 1): 30 => 30
3956 23:49:12.888883 DramcWriteLeveling(PI) end<-----
3957 23:49:12.888992
3958 23:49:12.889086 ==
3959 23:49:12.892072 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 23:49:12.895696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3961 23:49:12.895803 ==
3962 23:49:12.899009 [Gating] SW mode calibration
3963 23:49:12.905376 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 23:49:12.912152 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3965 23:49:12.915187 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 23:49:12.918661 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3967 23:49:12.925063 0 5 8 | B1->B0 | 3434 3232 | 0 0 | (0 1) (1 1)
3968 23:49:12.928420 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3969 23:49:12.931889 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 23:49:12.938193 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 23:49:12.941597 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 23:49:12.944873 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 23:49:12.952009 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 23:49:12.954753 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 23:49:12.958253 0 6 8 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0)
3976 23:49:12.964760 0 6 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
3977 23:49:12.968069 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 23:49:12.971775 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 23:49:12.977849 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 23:49:12.981247 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 23:49:12.984822 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 23:49:12.991055 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 23:49:12.994825 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3984 23:49:12.997604 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 23:49:13.004198 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 23:49:13.007682 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 23:49:13.011037 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 23:49:13.017752 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 23:49:13.020776 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 23:49:13.024073 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 23:49:13.030983 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 23:49:13.034269 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 23:49:13.037503 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:49:13.044083 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:49:13.047585 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:49:13.050624 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:49:13.057146 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:49:13.060612 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3999 23:49:13.063654 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:49:13.070383 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 23:49:13.073832 Total UI for P1: 0, mck2ui 16
4002 23:49:13.077026 best dqsien dly found for B0: ( 0, 9, 10)
4003 23:49:13.077135 Total UI for P1: 0, mck2ui 16
4004 23:49:13.084298 best dqsien dly found for B1: ( 0, 9, 10)
4005 23:49:13.087215 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4006 23:49:13.090706 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4007 23:49:13.090815
4008 23:49:13.093821 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4009 23:49:13.097077 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4010 23:49:13.100179 [Gating] SW calibration Done
4011 23:49:13.100263 ==
4012 23:49:13.103914 Dram Type= 6, Freq= 0, CH_0, rank 1
4013 23:49:13.107189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4014 23:49:13.107271 ==
4015 23:49:13.110118 RX Vref Scan: 0
4016 23:49:13.110199
4017 23:49:13.110263 RX Vref 0 -> 0, step: 1
4018 23:49:13.113577
4019 23:49:13.113661 RX Delay -230 -> 252, step: 16
4020 23:49:13.120466 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4021 23:49:13.123428 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4022 23:49:13.127000 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4023 23:49:13.130043 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4024 23:49:13.136649 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4025 23:49:13.140008 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4026 23:49:13.143644 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4027 23:49:13.146546 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4028 23:49:13.150036 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4029 23:49:13.156559 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4030 23:49:13.159825 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4031 23:49:13.162998 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4032 23:49:13.169445 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4033 23:49:13.172619 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4034 23:49:13.176015 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4035 23:49:13.179350 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4036 23:49:13.179432 ==
4037 23:49:13.182622 Dram Type= 6, Freq= 0, CH_0, rank 1
4038 23:49:13.189193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4039 23:49:13.189344 ==
4040 23:49:13.189438 DQS Delay:
4041 23:49:13.192890 DQS0 = 0, DQS1 = 0
4042 23:49:13.192971 DQM Delay:
4043 23:49:13.193036 DQM0 = 42, DQM1 = 33
4044 23:49:13.195871 DQ Delay:
4045 23:49:13.199416 DQ0 =33, DQ1 =49, DQ2 =41, DQ3 =33
4046 23:49:13.202725 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4047 23:49:13.206096 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4048 23:49:13.209736 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4049 23:49:13.209820
4050 23:49:13.209884
4051 23:49:13.209944 ==
4052 23:49:13.212338 Dram Type= 6, Freq= 0, CH_0, rank 1
4053 23:49:13.215955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4054 23:49:13.216037 ==
4055 23:49:13.216101
4056 23:49:13.216161
4057 23:49:13.219025 TX Vref Scan disable
4058 23:49:13.222325 == TX Byte 0 ==
4059 23:49:13.225858 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4060 23:49:13.229220 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4061 23:49:13.232186 == TX Byte 1 ==
4062 23:49:13.235419 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4063 23:49:13.238865 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4064 23:49:13.238948 ==
4065 23:49:13.241929 Dram Type= 6, Freq= 0, CH_0, rank 1
4066 23:49:13.245408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4067 23:49:13.248689 ==
4068 23:49:13.248770
4069 23:49:13.248853
4070 23:49:13.248926 TX Vref Scan disable
4071 23:49:13.252428 == TX Byte 0 ==
4072 23:49:13.255716 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4073 23:49:13.262308 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4074 23:49:13.262389 == TX Byte 1 ==
4075 23:49:13.265749 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4076 23:49:13.272583 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4077 23:49:13.272669
4078 23:49:13.272755 [DATLAT]
4079 23:49:13.272835 Freq=600, CH0 RK1
4080 23:49:13.272913
4081 23:49:13.275620 DATLAT Default: 0x8
4082 23:49:13.275704 0, 0xFFFF, sum = 0
4083 23:49:13.279328 1, 0xFFFF, sum = 0
4084 23:49:13.279414 2, 0xFFFF, sum = 0
4085 23:49:13.282122 3, 0xFFFF, sum = 0
4086 23:49:13.285848 4, 0xFFFF, sum = 0
4087 23:49:13.285938 5, 0xFFFF, sum = 0
4088 23:49:13.289100 6, 0xFFFF, sum = 0
4089 23:49:13.289186 7, 0x0, sum = 1
4090 23:49:13.289296 8, 0x0, sum = 2
4091 23:49:13.292486 9, 0x0, sum = 3
4092 23:49:13.292571 10, 0x0, sum = 4
4093 23:49:13.295616 best_step = 8
4094 23:49:13.295699
4095 23:49:13.295784 ==
4096 23:49:13.298818 Dram Type= 6, Freq= 0, CH_0, rank 1
4097 23:49:13.302802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4098 23:49:13.302887 ==
4099 23:49:13.305914 RX Vref Scan: 0
4100 23:49:13.305998
4101 23:49:13.306082 RX Vref 0 -> 0, step: 1
4102 23:49:13.306162
4103 23:49:13.308838 RX Delay -195 -> 252, step: 8
4104 23:49:13.315786 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4105 23:49:13.319391 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4106 23:49:13.322636 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4107 23:49:13.326147 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4108 23:49:13.332661 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4109 23:49:13.336013 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4110 23:49:13.339673 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4111 23:49:13.342463 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4112 23:49:13.345636 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4113 23:49:13.352826 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4114 23:49:13.355642 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4115 23:49:13.359324 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4116 23:49:13.362220 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4117 23:49:13.369270 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4118 23:49:13.372385 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4119 23:49:13.375780 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4120 23:49:13.375865 ==
4121 23:49:13.378866 Dram Type= 6, Freq= 0, CH_0, rank 1
4122 23:49:13.382709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4123 23:49:13.385425 ==
4124 23:49:13.385513 DQS Delay:
4125 23:49:13.385597 DQS0 = 0, DQS1 = 0
4126 23:49:13.389300 DQM Delay:
4127 23:49:13.389416 DQM0 = 41, DQM1 = 32
4128 23:49:13.392156 DQ Delay:
4129 23:49:13.395210 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4130 23:49:13.398820 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4131 23:49:13.398948 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4132 23:49:13.405591 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4133 23:49:13.405676
4134 23:49:13.405762
4135 23:49:13.412197 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4136 23:49:13.415556 CH0 RK1: MR19=808, MR18=6E6E
4137 23:49:13.421795 CH0_RK1: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4138 23:49:13.425179 [RxdqsGatingPostProcess] freq 600
4139 23:49:13.428425 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4140 23:49:13.431950 Pre-setting of DQS Precalculation
4141 23:49:13.438607 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4142 23:49:13.438695 ==
4143 23:49:13.441743 Dram Type= 6, Freq= 0, CH_1, rank 0
4144 23:49:13.445092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4145 23:49:13.445177 ==
4146 23:49:13.451644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4147 23:49:13.458104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4148 23:49:13.461443 [CA 0] Center 35 (5~66) winsize 62
4149 23:49:13.464965 [CA 1] Center 35 (5~66) winsize 62
4150 23:49:13.468427 [CA 2] Center 33 (3~64) winsize 62
4151 23:49:13.471449 [CA 3] Center 33 (3~64) winsize 62
4152 23:49:13.474698 [CA 4] Center 33 (2~64) winsize 63
4153 23:49:13.474783 [CA 5] Center 33 (2~64) winsize 63
4154 23:49:13.477900
4155 23:49:13.481562 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4156 23:49:13.481647
4157 23:49:13.484657 [CATrainingPosCal] consider 1 rank data
4158 23:49:13.488244 u2DelayCellTimex100 = 270/100 ps
4159 23:49:13.491606 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4160 23:49:13.494572 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4161 23:49:13.498003 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4162 23:49:13.501555 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4163 23:49:13.505044 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4164 23:49:13.508189 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4165 23:49:13.508274
4166 23:49:13.511595 CA PerBit enable=1, Macro0, CA PI delay=33
4167 23:49:13.511679
4168 23:49:13.514858 [CBTSetCACLKResult] CA Dly = 33
4169 23:49:13.517973 CS Dly: 4 (0~35)
4170 23:49:13.518057 ==
4171 23:49:13.521437 Dram Type= 6, Freq= 0, CH_1, rank 1
4172 23:49:13.524793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4173 23:49:13.524878 ==
4174 23:49:13.531619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4175 23:49:13.538111 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4176 23:49:13.540947 [CA 0] Center 35 (5~66) winsize 62
4177 23:49:13.544824 [CA 1] Center 34 (4~65) winsize 62
4178 23:49:13.547691 [CA 2] Center 33 (3~64) winsize 62
4179 23:49:13.551011 [CA 3] Center 33 (3~64) winsize 62
4180 23:49:13.554661 [CA 4] Center 32 (2~63) winsize 62
4181 23:49:13.558121 [CA 5] Center 32 (2~63) winsize 62
4182 23:49:13.558205
4183 23:49:13.561144 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4184 23:49:13.561230
4185 23:49:13.564136 [CATrainingPosCal] consider 2 rank data
4186 23:49:13.567728 u2DelayCellTimex100 = 270/100 ps
4187 23:49:13.571005 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4188 23:49:13.574370 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4189 23:49:13.577387 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4190 23:49:13.581422 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4191 23:49:13.584434 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4192 23:49:13.587466 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4193 23:49:13.587551
4194 23:49:13.594024 CA PerBit enable=1, Macro0, CA PI delay=32
4195 23:49:13.594111
4196 23:49:13.594196 [CBTSetCACLKResult] CA Dly = 32
4197 23:49:13.597639 CS Dly: 4 (0~35)
4198 23:49:13.597723
4199 23:49:13.601130 ----->DramcWriteLeveling(PI) begin...
4200 23:49:13.601241 ==
4201 23:49:13.604400 Dram Type= 6, Freq= 0, CH_1, rank 0
4202 23:49:13.607421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4203 23:49:13.607506 ==
4204 23:49:13.611025 Write leveling (Byte 0): 26 => 26
4205 23:49:13.614281 Write leveling (Byte 1): 27 => 27
4206 23:49:13.617437 DramcWriteLeveling(PI) end<-----
4207 23:49:13.617522
4208 23:49:13.617607 ==
4209 23:49:13.620631 Dram Type= 6, Freq= 0, CH_1, rank 0
4210 23:49:13.627370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4211 23:49:13.627460 ==
4212 23:49:13.627547 [Gating] SW mode calibration
4213 23:49:13.637190 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 23:49:13.640434 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4215 23:49:13.643816 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 23:49:13.650524 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4217 23:49:13.653724 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4218 23:49:13.656980 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4219 23:49:13.663643 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 23:49:13.667144 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 23:49:13.670309 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 23:49:13.677198 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:49:13.680143 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 23:49:13.684068 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4225 23:49:13.690512 0 6 8 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
4226 23:49:13.693775 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 23:49:13.696616 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 23:49:13.703590 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 23:49:13.706753 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 23:49:13.709894 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 23:49:13.716599 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 23:49:13.720055 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:49:13.723512 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4234 23:49:13.729789 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4235 23:49:13.733039 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:49:13.736291 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:49:13.743488 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:49:13.746669 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:49:13.749718 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:49:13.756275 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:49:13.759524 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:49:13.762801 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:49:13.769398 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:49:13.772593 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:49:13.776152 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:49:13.782881 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:49:13.786505 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:49:13.789560 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:49:13.796009 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4250 23:49:13.799619 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 23:49:13.802729 Total UI for P1: 0, mck2ui 16
4252 23:49:13.806392 best dqsien dly found for B0: ( 0, 9, 8)
4253 23:49:13.809631 Total UI for P1: 0, mck2ui 16
4254 23:49:13.812391 best dqsien dly found for B1: ( 0, 9, 8)
4255 23:49:13.815812 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4256 23:49:13.819572 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4257 23:49:13.819676
4258 23:49:13.822547 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4259 23:49:13.825641 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4260 23:49:13.828930 [Gating] SW calibration Done
4261 23:49:13.829029 ==
4262 23:49:13.832734 Dram Type= 6, Freq= 0, CH_1, rank 0
4263 23:49:13.835744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4264 23:49:13.835849 ==
4265 23:49:13.839022 RX Vref Scan: 0
4266 23:49:13.839120
4267 23:49:13.842294 RX Vref 0 -> 0, step: 1
4268 23:49:13.842392
4269 23:49:13.845626 RX Delay -230 -> 252, step: 16
4270 23:49:13.849140 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4271 23:49:13.852475 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4272 23:49:13.855529 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4273 23:49:13.859129 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4274 23:49:13.865534 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4275 23:49:13.868924 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4276 23:49:13.871908 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4277 23:49:13.875272 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4278 23:49:13.881924 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4279 23:49:13.885283 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4280 23:49:13.888606 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4281 23:49:13.891748 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4282 23:49:13.898578 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4283 23:49:13.901925 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4284 23:49:13.905236 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4285 23:49:13.908423 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4286 23:49:13.908525 ==
4287 23:49:13.911740 Dram Type= 6, Freq= 0, CH_1, rank 0
4288 23:49:13.918376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4289 23:49:13.918479 ==
4290 23:49:13.918568 DQS Delay:
4291 23:49:13.921859 DQS0 = 0, DQS1 = 0
4292 23:49:13.921961 DQM Delay:
4293 23:49:13.922049 DQM0 = 39, DQM1 = 30
4294 23:49:13.924891 DQ Delay:
4295 23:49:13.928331 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4296 23:49:13.931420 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4297 23:49:13.935108 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4298 23:49:13.938147 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4299 23:49:13.938250
4300 23:49:13.938336
4301 23:49:13.938422 ==
4302 23:49:13.941603 Dram Type= 6, Freq= 0, CH_1, rank 0
4303 23:49:13.944718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4304 23:49:13.944843 ==
4305 23:49:13.944971
4306 23:49:13.945058
4307 23:49:13.948100 TX Vref Scan disable
4308 23:49:13.951465 == TX Byte 0 ==
4309 23:49:13.954965 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4310 23:49:13.958096 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4311 23:49:13.961377 == TX Byte 1 ==
4312 23:49:13.964700 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4313 23:49:13.968090 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4314 23:49:13.968193 ==
4315 23:49:13.971626 Dram Type= 6, Freq= 0, CH_1, rank 0
4316 23:49:13.974698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4317 23:49:13.974802 ==
4318 23:49:13.977835
4319 23:49:13.977935
4320 23:49:13.978027 TX Vref Scan disable
4321 23:49:13.981908 == TX Byte 0 ==
4322 23:49:13.984778 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4323 23:49:13.991410 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4324 23:49:13.991515 == TX Byte 1 ==
4325 23:49:13.994999 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4326 23:49:14.001557 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4327 23:49:14.001659
4328 23:49:14.001745 [DATLAT]
4329 23:49:14.001827 Freq=600, CH1 RK0
4330 23:49:14.001909
4331 23:49:14.004721 DATLAT Default: 0x9
4332 23:49:14.004822 0, 0xFFFF, sum = 0
4333 23:49:14.008308 1, 0xFFFF, sum = 0
4334 23:49:14.008414 2, 0xFFFF, sum = 0
4335 23:49:14.011273 3, 0xFFFF, sum = 0
4336 23:49:14.014511 4, 0xFFFF, sum = 0
4337 23:49:14.014618 5, 0xFFFF, sum = 0
4338 23:49:14.018088 6, 0xFFFF, sum = 0
4339 23:49:14.018189 7, 0x0, sum = 1
4340 23:49:14.018278 8, 0x0, sum = 2
4341 23:49:14.021752 9, 0x0, sum = 3
4342 23:49:14.021861 10, 0x0, sum = 4
4343 23:49:14.024664 best_step = 8
4344 23:49:14.024763
4345 23:49:14.024849 ==
4346 23:49:14.028041 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 23:49:14.031125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4348 23:49:14.031228 ==
4349 23:49:14.034405 RX Vref Scan: 1
4350 23:49:14.034506
4351 23:49:14.034596 RX Vref 0 -> 0, step: 1
4352 23:49:14.034680
4353 23:49:14.037749 RX Delay -195 -> 252, step: 8
4354 23:49:14.037850
4355 23:49:14.041164 Set Vref, RX VrefLevel [Byte0]: 51
4356 23:49:14.044198 [Byte1]: 48
4357 23:49:14.049074
4358 23:49:14.049174 Final RX Vref Byte 0 = 51 to rank0
4359 23:49:14.052105 Final RX Vref Byte 1 = 48 to rank0
4360 23:49:14.055364 Final RX Vref Byte 0 = 51 to rank1
4361 23:49:14.058476 Final RX Vref Byte 1 = 48 to rank1==
4362 23:49:14.062136 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 23:49:14.068482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4364 23:49:14.068589 ==
4365 23:49:14.068680 DQS Delay:
4366 23:49:14.068765 DQS0 = 0, DQS1 = 0
4367 23:49:14.071721 DQM Delay:
4368 23:49:14.071823 DQM0 = 37, DQM1 = 31
4369 23:49:14.075168 DQ Delay:
4370 23:49:14.078609 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4371 23:49:14.081889 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4372 23:49:14.084937 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4373 23:49:14.088290 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4374 23:49:14.088391
4375 23:49:14.088479
4376 23:49:14.094896 [DQSOSCAuto] RK0, (LSB)MR18= 0x7777, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4377 23:49:14.098340 CH1 RK0: MR19=808, MR18=7777
4378 23:49:14.105157 CH1_RK0: MR19=0x808, MR18=0x7777, DQSOSC=387, MR23=63, INC=175, DEC=116
4379 23:49:14.105261
4380 23:49:14.108344 ----->DramcWriteLeveling(PI) begin...
4381 23:49:14.108450 ==
4382 23:49:14.111728 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 23:49:14.114978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4384 23:49:14.115083 ==
4385 23:49:14.118040 Write leveling (Byte 0): 28 => 28
4386 23:49:14.121385 Write leveling (Byte 1): 28 => 28
4387 23:49:14.125098 DramcWriteLeveling(PI) end<-----
4388 23:49:14.125206
4389 23:49:14.125303 ==
4390 23:49:14.128345 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 23:49:14.131722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4392 23:49:14.131829 ==
4393 23:49:14.134655 [Gating] SW mode calibration
4394 23:49:14.141399 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4395 23:49:14.148235 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4396 23:49:14.151221 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4397 23:49:14.157937 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4398 23:49:14.161395 0 5 8 | B1->B0 | 3030 2626 | 1 0 | (1 0) (0 0)
4399 23:49:14.164411 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4400 23:49:14.171074 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 23:49:14.174540 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 23:49:14.177805 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 23:49:14.184306 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 23:49:14.187906 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 23:49:14.191383 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4406 23:49:14.197737 0 6 8 | B1->B0 | 3838 4242 | 0 1 | (0 0) (0 0)
4407 23:49:14.201218 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4408 23:49:14.204791 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 23:49:14.207803 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 23:49:14.214328 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 23:49:14.218141 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 23:49:14.221275 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 23:49:14.227922 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4414 23:49:14.231304 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4415 23:49:14.234684 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 23:49:14.241231 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 23:49:14.244734 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 23:49:14.247876 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 23:49:14.254462 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 23:49:14.258131 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 23:49:14.261051 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 23:49:14.267626 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 23:49:14.271078 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 23:49:14.274879 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 23:49:14.281005 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 23:49:14.284636 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 23:49:14.287761 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:49:14.294141 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:49:14.297467 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4430 23:49:14.300528 Total UI for P1: 0, mck2ui 16
4431 23:49:14.304054 best dqsien dly found for B0: ( 0, 9, 2)
4432 23:49:14.307377 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4433 23:49:14.314402 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 23:49:14.314755 Total UI for P1: 0, mck2ui 16
4435 23:49:14.320548 best dqsien dly found for B1: ( 0, 9, 6)
4436 23:49:14.323748 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4437 23:49:14.327509 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4438 23:49:14.327675
4439 23:49:14.330583 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4440 23:49:14.333491 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4441 23:49:14.337211 [Gating] SW calibration Done
4442 23:49:14.337361 ==
4443 23:49:14.340486 Dram Type= 6, Freq= 0, CH_1, rank 1
4444 23:49:14.343585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4445 23:49:14.343732 ==
4446 23:49:14.346793 RX Vref Scan: 0
4447 23:49:14.346892
4448 23:49:14.346959 RX Vref 0 -> 0, step: 1
4449 23:49:14.347020
4450 23:49:14.350170 RX Delay -230 -> 252, step: 16
4451 23:49:14.353793 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4452 23:49:14.360573 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4453 23:49:14.363534 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4454 23:49:14.366943 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4455 23:49:14.370363 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4456 23:49:14.376473 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4457 23:49:14.379743 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4458 23:49:14.383416 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4459 23:49:14.386680 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4460 23:49:14.390168 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4461 23:49:14.396538 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4462 23:49:14.400154 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4463 23:49:14.403520 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4464 23:49:14.406867 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4465 23:49:14.413269 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4466 23:49:14.416916 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4467 23:49:14.416997 ==
4468 23:49:14.419994 Dram Type= 6, Freq= 0, CH_1, rank 1
4469 23:49:14.423168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4470 23:49:14.423249 ==
4471 23:49:14.426696 DQS Delay:
4472 23:49:14.426777 DQS0 = 0, DQS1 = 0
4473 23:49:14.426841 DQM Delay:
4474 23:49:14.429741 DQM0 = 42, DQM1 = 37
4475 23:49:14.429821 DQ Delay:
4476 23:49:14.433101 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4477 23:49:14.436541 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4478 23:49:14.439687 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4479 23:49:14.442895 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4480 23:49:14.442975
4481 23:49:14.443038
4482 23:49:14.443096 ==
4483 23:49:14.446555 Dram Type= 6, Freq= 0, CH_1, rank 1
4484 23:49:14.452864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4485 23:49:14.452947 ==
4486 23:49:14.453010
4487 23:49:14.453070
4488 23:49:14.453126 TX Vref Scan disable
4489 23:49:14.457164 == TX Byte 0 ==
4490 23:49:14.460300 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4491 23:49:14.466642 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4492 23:49:14.466724 == TX Byte 1 ==
4493 23:49:14.470336 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4494 23:49:14.476767 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4495 23:49:14.476848 ==
4496 23:49:14.480025 Dram Type= 6, Freq= 0, CH_1, rank 1
4497 23:49:14.483455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4498 23:49:14.483537 ==
4499 23:49:14.483601
4500 23:49:14.483659
4501 23:49:14.486989 TX Vref Scan disable
4502 23:49:14.489913 == TX Byte 0 ==
4503 23:49:14.493229 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4504 23:49:14.496876 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4505 23:49:14.499843 == TX Byte 1 ==
4506 23:49:14.503443 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4507 23:49:14.506780 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4508 23:49:14.506865
4509 23:49:14.506930 [DATLAT]
4510 23:49:14.510018 Freq=600, CH1 RK1
4511 23:49:14.510100
4512 23:49:14.510162 DATLAT Default: 0x8
4513 23:49:14.513498 0, 0xFFFF, sum = 0
4514 23:49:14.516324 1, 0xFFFF, sum = 0
4515 23:49:14.516405 2, 0xFFFF, sum = 0
4516 23:49:14.520173 3, 0xFFFF, sum = 0
4517 23:49:14.520254 4, 0xFFFF, sum = 0
4518 23:49:14.523054 5, 0xFFFF, sum = 0
4519 23:49:14.523135 6, 0xFFFF, sum = 0
4520 23:49:14.526279 7, 0x0, sum = 1
4521 23:49:14.526360 8, 0x0, sum = 2
4522 23:49:14.526425 9, 0x0, sum = 3
4523 23:49:14.529521 10, 0x0, sum = 4
4524 23:49:14.529606 best_step = 8
4525 23:49:14.529672
4526 23:49:14.529731 ==
4527 23:49:14.533056 Dram Type= 6, Freq= 0, CH_1, rank 1
4528 23:49:14.539671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4529 23:49:14.539757 ==
4530 23:49:14.539821 RX Vref Scan: 0
4531 23:49:14.539880
4532 23:49:14.542964 RX Vref 0 -> 0, step: 1
4533 23:49:14.543044
4534 23:49:14.546413 RX Delay -195 -> 252, step: 8
4535 23:49:14.549830 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4536 23:49:14.556515 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4537 23:49:14.559515 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4538 23:49:14.563104 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4539 23:49:14.566474 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4540 23:49:14.572585 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4541 23:49:14.575884 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4542 23:49:14.579471 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4543 23:49:14.582519 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4544 23:49:14.589531 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4545 23:49:14.592972 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4546 23:49:14.596038 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4547 23:49:14.599255 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4548 23:49:14.605595 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4549 23:49:14.608727 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4550 23:49:14.612101 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4551 23:49:14.612183 ==
4552 23:49:14.615876 Dram Type= 6, Freq= 0, CH_1, rank 1
4553 23:49:14.618991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4554 23:49:14.619073 ==
4555 23:49:14.622271 DQS Delay:
4556 23:49:14.622351 DQS0 = 0, DQS1 = 0
4557 23:49:14.625583 DQM Delay:
4558 23:49:14.625663 DQM0 = 38, DQM1 = 30
4559 23:49:14.625727 DQ Delay:
4560 23:49:14.629007 DQ0 =40, DQ1 =32, DQ2 =32, DQ3 =32
4561 23:49:14.632167 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4562 23:49:14.635565 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4563 23:49:14.638579 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4564 23:49:14.638660
4565 23:49:14.641837
4566 23:49:14.648981 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4567 23:49:14.651857 CH1 RK1: MR19=808, MR18=6060
4568 23:49:14.658654 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4569 23:49:14.662299 [RxdqsGatingPostProcess] freq 600
4570 23:49:14.665225 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4571 23:49:14.668602 Pre-setting of DQS Precalculation
4572 23:49:14.672017 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4573 23:49:14.682342 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4574 23:49:14.688520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4575 23:49:14.688676
4576 23:49:14.688772
4577 23:49:14.692015 [Calibration Summary] 1200 Mbps
4578 23:49:14.692150 CH 0, Rank 0
4579 23:49:14.695082 SW Impedance : PASS
4580 23:49:14.698246 DUTY Scan : NO K
4581 23:49:14.698334 ZQ Calibration : PASS
4582 23:49:14.701856 Jitter Meter : NO K
4583 23:49:14.701941 CBT Training : PASS
4584 23:49:14.704749 Write leveling : PASS
4585 23:49:14.708466 RX DQS gating : PASS
4586 23:49:14.708552 RX DQ/DQS(RDDQC) : PASS
4587 23:49:14.711546 TX DQ/DQS : PASS
4588 23:49:14.714908 RX DATLAT : PASS
4589 23:49:14.714990 RX DQ/DQS(Engine): PASS
4590 23:49:14.718322 TX OE : NO K
4591 23:49:14.718404 All Pass.
4592 23:49:14.718468
4593 23:49:14.721590 CH 0, Rank 1
4594 23:49:14.721671 SW Impedance : PASS
4595 23:49:14.724911 DUTY Scan : NO K
4596 23:49:14.728590 ZQ Calibration : PASS
4597 23:49:14.728672 Jitter Meter : NO K
4598 23:49:14.731441 CBT Training : PASS
4599 23:49:14.734802 Write leveling : PASS
4600 23:49:14.734882 RX DQS gating : PASS
4601 23:49:14.738090 RX DQ/DQS(RDDQC) : PASS
4602 23:49:14.741240 TX DQ/DQS : PASS
4603 23:49:14.741359 RX DATLAT : PASS
4604 23:49:14.744568 RX DQ/DQS(Engine): PASS
4605 23:49:14.748162 TX OE : NO K
4606 23:49:14.748320 All Pass.
4607 23:49:14.748397
4608 23:49:14.748467 CH 1, Rank 0
4609 23:49:14.751225 SW Impedance : PASS
4610 23:49:14.754568 DUTY Scan : NO K
4611 23:49:14.754797 ZQ Calibration : PASS
4612 23:49:14.758002 Jitter Meter : NO K
4613 23:49:14.761192 CBT Training : PASS
4614 23:49:14.761314 Write leveling : PASS
4615 23:49:14.764278 RX DQS gating : PASS
4616 23:49:14.764387 RX DQ/DQS(RDDQC) : PASS
4617 23:49:14.768107 TX DQ/DQS : PASS
4618 23:49:14.771244 RX DATLAT : PASS
4619 23:49:14.771461 RX DQ/DQS(Engine): PASS
4620 23:49:14.774454 TX OE : NO K
4621 23:49:14.774692 All Pass.
4622 23:49:14.774825
4623 23:49:14.777671 CH 1, Rank 1
4624 23:49:14.777903 SW Impedance : PASS
4625 23:49:14.781182 DUTY Scan : NO K
4626 23:49:14.784396 ZQ Calibration : PASS
4627 23:49:14.784672 Jitter Meter : NO K
4628 23:49:14.787661 CBT Training : PASS
4629 23:49:14.791569 Write leveling : PASS
4630 23:49:14.791898 RX DQS gating : PASS
4631 23:49:14.794359 RX DQ/DQS(RDDQC) : PASS
4632 23:49:14.797563 TX DQ/DQS : PASS
4633 23:49:14.797864 RX DATLAT : PASS
4634 23:49:14.801388 RX DQ/DQS(Engine): PASS
4635 23:49:14.804791 TX OE : NO K
4636 23:49:14.805373 All Pass.
4637 23:49:14.805727
4638 23:49:14.806036 DramC Write-DBI off
4639 23:49:14.808147 PER_BANK_REFRESH: Hybrid Mode
4640 23:49:14.811403 TX_TRACKING: ON
4641 23:49:14.817910 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4642 23:49:14.821041 [FAST_K] Save calibration result to emmc
4643 23:49:14.827638 dramc_set_vcore_voltage set vcore to 662500
4644 23:49:14.828148 Read voltage for 933, 3
4645 23:49:14.831285 Vio18 = 0
4646 23:49:14.831807 Vcore = 662500
4647 23:49:14.832137 Vdram = 0
4648 23:49:14.834378 Vddq = 0
4649 23:49:14.834792 Vmddr = 0
4650 23:49:14.837370 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4651 23:49:14.845113 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4652 23:49:14.847763 MEM_TYPE=3, freq_sel=17
4653 23:49:14.850667 sv_algorithm_assistance_LP4_1600
4654 23:49:14.854090 ============ PULL DRAM RESETB DOWN ============
4655 23:49:14.857285 ========== PULL DRAM RESETB DOWN end =========
4656 23:49:14.860757 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4657 23:49:14.864462 ===================================
4658 23:49:14.868150 LPDDR4 DRAM CONFIGURATION
4659 23:49:14.870990 ===================================
4660 23:49:14.873906 EX_ROW_EN[0] = 0x0
4661 23:49:14.874321 EX_ROW_EN[1] = 0x0
4662 23:49:14.877364 LP4Y_EN = 0x0
4663 23:49:14.877781 WORK_FSP = 0x0
4664 23:49:14.881110 WL = 0x3
4665 23:49:14.881676 RL = 0x3
4666 23:49:14.884078 BL = 0x2
4667 23:49:14.884498 RPST = 0x0
4668 23:49:14.887187 RD_PRE = 0x0
4669 23:49:14.890599 WR_PRE = 0x1
4670 23:49:14.891011 WR_PST = 0x0
4671 23:49:14.893597 DBI_WR = 0x0
4672 23:49:14.894026 DBI_RD = 0x0
4673 23:49:14.897023 OTF = 0x1
4674 23:49:14.900502 ===================================
4675 23:49:14.903958 ===================================
4676 23:49:14.904483 ANA top config
4677 23:49:14.907499 ===================================
4678 23:49:14.910613 DLL_ASYNC_EN = 0
4679 23:49:14.913727 ALL_SLAVE_EN = 1
4680 23:49:14.914136 NEW_RANK_MODE = 1
4681 23:49:14.916913 DLL_IDLE_MODE = 1
4682 23:49:14.920315 LP45_APHY_COMB_EN = 1
4683 23:49:14.923976 TX_ODT_DIS = 1
4684 23:49:14.924385 NEW_8X_MODE = 1
4685 23:49:14.927635 ===================================
4686 23:49:14.930442 ===================================
4687 23:49:14.933637 data_rate = 1866
4688 23:49:14.936778 CKR = 1
4689 23:49:14.940225 DQ_P2S_RATIO = 8
4690 23:49:14.944012 ===================================
4691 23:49:14.947352 CA_P2S_RATIO = 8
4692 23:49:14.950065 DQ_CA_OPEN = 0
4693 23:49:14.953565 DQ_SEMI_OPEN = 0
4694 23:49:14.954008 CA_SEMI_OPEN = 0
4695 23:49:14.956785 CA_FULL_RATE = 0
4696 23:49:14.960104 DQ_CKDIV4_EN = 1
4697 23:49:14.963404 CA_CKDIV4_EN = 1
4698 23:49:14.966648 CA_PREDIV_EN = 0
4699 23:49:14.967094 PH8_DLY = 0
4700 23:49:14.969952 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4701 23:49:14.973472 DQ_AAMCK_DIV = 4
4702 23:49:14.976570 CA_AAMCK_DIV = 4
4703 23:49:14.979799 CA_ADMCK_DIV = 4
4704 23:49:14.983264 DQ_TRACK_CA_EN = 0
4705 23:49:14.986747 CA_PICK = 933
4706 23:49:14.987158 CA_MCKIO = 933
4707 23:49:14.990161 MCKIO_SEMI = 0
4708 23:49:14.993238 PLL_FREQ = 3732
4709 23:49:14.996682 DQ_UI_PI_RATIO = 32
4710 23:49:14.999989 CA_UI_PI_RATIO = 0
4711 23:49:15.003072 ===================================
4712 23:49:15.006285 ===================================
4713 23:49:15.009580 memory_type:LPDDR4
4714 23:49:15.010014 GP_NUM : 10
4715 23:49:15.012918 SRAM_EN : 1
4716 23:49:15.013377 MD32_EN : 0
4717 23:49:15.016270 ===================================
4718 23:49:15.019803 [ANA_INIT] >>>>>>>>>>>>>>
4719 23:49:15.023061 <<<<<< [CONFIGURE PHASE]: ANA_TX
4720 23:49:15.026581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4721 23:49:15.029872 ===================================
4722 23:49:15.033416 data_rate = 1866,PCW = 0X8f00
4723 23:49:15.036167 ===================================
4724 23:49:15.039367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4725 23:49:15.046460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4726 23:49:15.049483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4727 23:49:15.055785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4728 23:49:15.059176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4729 23:49:15.062624 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4730 23:49:15.063054 [ANA_INIT] flow start
4731 23:49:15.065906 [ANA_INIT] PLL >>>>>>>>
4732 23:49:15.069306 [ANA_INIT] PLL <<<<<<<<
4733 23:49:15.069765 [ANA_INIT] MIDPI >>>>>>>>
4734 23:49:15.072454 [ANA_INIT] MIDPI <<<<<<<<
4735 23:49:15.076113 [ANA_INIT] DLL >>>>>>>>
4736 23:49:15.076557 [ANA_INIT] flow end
4737 23:49:15.082952 ============ LP4 DIFF to SE enter ============
4738 23:49:15.086465 ============ LP4 DIFF to SE exit ============
4739 23:49:15.089491 [ANA_INIT] <<<<<<<<<<<<<
4740 23:49:15.092979 [Flow] Enable top DCM control >>>>>
4741 23:49:15.096035 [Flow] Enable top DCM control <<<<<
4742 23:49:15.096472 Enable DLL master slave shuffle
4743 23:49:15.102406 ==============================================================
4744 23:49:15.106195 Gating Mode config
4745 23:49:15.109142 ==============================================================
4746 23:49:15.112630 Config description:
4747 23:49:15.122095 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4748 23:49:15.128869 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4749 23:49:15.132109 SELPH_MODE 0: By rank 1: By Phase
4750 23:49:15.138854 ==============================================================
4751 23:49:15.142252 GAT_TRACK_EN = 1
4752 23:49:15.145533 RX_GATING_MODE = 2
4753 23:49:15.148659 RX_GATING_TRACK_MODE = 2
4754 23:49:15.151792 SELPH_MODE = 1
4755 23:49:15.155391 PICG_EARLY_EN = 1
4756 23:49:15.155822 VALID_LAT_VALUE = 1
4757 23:49:15.161821 ==============================================================
4758 23:49:15.165146 Enter into Gating configuration >>>>
4759 23:49:15.168534 Exit from Gating configuration <<<<
4760 23:49:15.172014 Enter into DVFS_PRE_config >>>>>
4761 23:49:15.181661 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4762 23:49:15.184910 Exit from DVFS_PRE_config <<<<<
4763 23:49:15.188616 Enter into PICG configuration >>>>
4764 23:49:15.191857 Exit from PICG configuration <<<<
4765 23:49:15.195029 [RX_INPUT] configuration >>>>>
4766 23:49:15.198442 [RX_INPUT] configuration <<<<<
4767 23:49:15.201468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4768 23:49:15.208195 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4769 23:49:15.214909 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4770 23:49:15.221532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4771 23:49:15.228020 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4772 23:49:15.234603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4773 23:49:15.238334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4774 23:49:15.241663 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4775 23:49:15.244631 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4776 23:49:15.251367 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4777 23:49:15.254682 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4778 23:49:15.258195 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4779 23:49:15.261402 ===================================
4780 23:49:15.264739 LPDDR4 DRAM CONFIGURATION
4781 23:49:15.267785 ===================================
4782 23:49:15.268201 EX_ROW_EN[0] = 0x0
4783 23:49:15.271196 EX_ROW_EN[1] = 0x0
4784 23:49:15.271615 LP4Y_EN = 0x0
4785 23:49:15.274526 WORK_FSP = 0x0
4786 23:49:15.277765 WL = 0x3
4787 23:49:15.278183 RL = 0x3
4788 23:49:15.281087 BL = 0x2
4789 23:49:15.281656 RPST = 0x0
4790 23:49:15.284387 RD_PRE = 0x0
4791 23:49:15.284805 WR_PRE = 0x1
4792 23:49:15.288098 WR_PST = 0x0
4793 23:49:15.288513 DBI_WR = 0x0
4794 23:49:15.291037 DBI_RD = 0x0
4795 23:49:15.291456 OTF = 0x1
4796 23:49:15.294761 ===================================
4797 23:49:15.297819 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4798 23:49:15.304611 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4799 23:49:15.307890 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4800 23:49:15.311318 ===================================
4801 23:49:15.314532 LPDDR4 DRAM CONFIGURATION
4802 23:49:15.317573 ===================================
4803 23:49:15.317995 EX_ROW_EN[0] = 0x10
4804 23:49:15.321097 EX_ROW_EN[1] = 0x0
4805 23:49:15.321558 LP4Y_EN = 0x0
4806 23:49:15.324339 WORK_FSP = 0x0
4807 23:49:15.324755 WL = 0x3
4808 23:49:15.328049 RL = 0x3
4809 23:49:15.328577 BL = 0x2
4810 23:49:15.331019 RPST = 0x0
4811 23:49:15.334340 RD_PRE = 0x0
4812 23:49:15.334756 WR_PRE = 0x1
4813 23:49:15.337833 WR_PST = 0x0
4814 23:49:15.338250 DBI_WR = 0x0
4815 23:49:15.340696 DBI_RD = 0x0
4816 23:49:15.341101 OTF = 0x1
4817 23:49:15.344145 ===================================
4818 23:49:15.351036 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4819 23:49:15.354742 nWR fixed to 30
4820 23:49:15.357844 [ModeRegInit_LP4] CH0 RK0
4821 23:49:15.358263 [ModeRegInit_LP4] CH0 RK1
4822 23:49:15.361340 [ModeRegInit_LP4] CH1 RK0
4823 23:49:15.364970 [ModeRegInit_LP4] CH1 RK1
4824 23:49:15.365516 match AC timing 8
4825 23:49:15.371352 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4826 23:49:15.374340 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4827 23:49:15.377473 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4828 23:49:15.384693 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4829 23:49:15.387835 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4830 23:49:15.388472 ==
4831 23:49:15.391191 Dram Type= 6, Freq= 0, CH_0, rank 0
4832 23:49:15.394874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4833 23:49:15.395296 ==
4834 23:49:15.400898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4835 23:49:15.407509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4836 23:49:15.411372 [CA 0] Center 39 (8~70) winsize 63
4837 23:49:15.414551 [CA 1] Center 38 (8~69) winsize 62
4838 23:49:15.417561 [CA 2] Center 36 (6~67) winsize 62
4839 23:49:15.420857 [CA 3] Center 36 (6~67) winsize 62
4840 23:49:15.424606 [CA 4] Center 34 (4~65) winsize 62
4841 23:49:15.427781 [CA 5] Center 34 (4~65) winsize 62
4842 23:49:15.428197
4843 23:49:15.430591 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4844 23:49:15.431148
4845 23:49:15.433986 [CATrainingPosCal] consider 1 rank data
4846 23:49:15.437630 u2DelayCellTimex100 = 270/100 ps
4847 23:49:15.440837 CA0 delay=39 (8~70),Diff = 5 PI (31 cell)
4848 23:49:15.444105 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4849 23:49:15.447251 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4850 23:49:15.450964 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4851 23:49:15.454323 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4852 23:49:15.460728 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4853 23:49:15.461144
4854 23:49:15.463833 CA PerBit enable=1, Macro0, CA PI delay=34
4855 23:49:15.464248
4856 23:49:15.467156 [CBTSetCACLKResult] CA Dly = 34
4857 23:49:15.467572 CS Dly: 7 (0~38)
4858 23:49:15.467902 ==
4859 23:49:15.470637 Dram Type= 6, Freq= 0, CH_0, rank 1
4860 23:49:15.474016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4861 23:49:15.477195 ==
4862 23:49:15.480393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4863 23:49:15.487092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4864 23:49:15.490850 [CA 0] Center 38 (8~69) winsize 62
4865 23:49:15.493954 [CA 1] Center 38 (8~69) winsize 62
4866 23:49:15.496899 [CA 2] Center 36 (6~67) winsize 62
4867 23:49:15.500232 [CA 3] Center 36 (6~66) winsize 61
4868 23:49:15.504031 [CA 4] Center 34 (4~65) winsize 62
4869 23:49:15.507183 [CA 5] Center 34 (4~65) winsize 62
4870 23:49:15.507601
4871 23:49:15.510421 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4872 23:49:15.510872
4873 23:49:15.513745 [CATrainingPosCal] consider 2 rank data
4874 23:49:15.517198 u2DelayCellTimex100 = 270/100 ps
4875 23:49:15.520067 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4876 23:49:15.523652 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4877 23:49:15.527269 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4878 23:49:15.533743 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4879 23:49:15.536517 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4880 23:49:15.540181 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4881 23:49:15.540597
4882 23:49:15.543713 CA PerBit enable=1, Macro0, CA PI delay=34
4883 23:49:15.544127
4884 23:49:15.546650 [CBTSetCACLKResult] CA Dly = 34
4885 23:49:15.547108 CS Dly: 7 (0~39)
4886 23:49:15.547439
4887 23:49:15.549713 ----->DramcWriteLeveling(PI) begin...
4888 23:49:15.550135 ==
4889 23:49:15.553433 Dram Type= 6, Freq= 0, CH_0, rank 0
4890 23:49:15.559786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4891 23:49:15.560200 ==
4892 23:49:15.563001 Write leveling (Byte 0): 29 => 29
4893 23:49:15.566737 Write leveling (Byte 1): 28 => 28
4894 23:49:15.569968 DramcWriteLeveling(PI) end<-----
4895 23:49:15.570375
4896 23:49:15.570691 ==
4897 23:49:15.572776 Dram Type= 6, Freq= 0, CH_0, rank 0
4898 23:49:15.576213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4899 23:49:15.576625 ==
4900 23:49:15.579784 [Gating] SW mode calibration
4901 23:49:15.586013 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4902 23:49:15.593145 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4903 23:49:15.595922 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4904 23:49:15.599553 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4905 23:49:15.605985 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4906 23:49:15.609130 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4907 23:49:15.612533 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 23:49:15.619234 0 10 20 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4909 23:49:15.622561 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
4910 23:49:15.625734 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4911 23:49:15.628823 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4912 23:49:15.635724 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4913 23:49:15.638962 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 23:49:15.642507 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 23:49:15.649271 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 23:49:15.652293 0 11 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4917 23:49:15.655472 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4918 23:49:15.662503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4919 23:49:15.665777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4920 23:49:15.669215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4921 23:49:15.675798 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 23:49:15.678963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 23:49:15.682199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4924 23:49:15.688724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 23:49:15.692010 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4926 23:49:15.695399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4927 23:49:15.702335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4928 23:49:15.705542 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 23:49:15.709348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 23:49:15.715293 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 23:49:15.719012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 23:49:15.722142 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 23:49:15.728604 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 23:49:15.732435 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 23:49:15.735587 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 23:49:15.741961 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 23:49:15.745505 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 23:49:15.748574 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 23:49:15.755398 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 23:49:15.758364 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4941 23:49:15.762150 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4942 23:49:15.764714 Total UI for P1: 0, mck2ui 16
4943 23:49:15.768793 best dqsien dly found for B0: ( 0, 14, 20)
4944 23:49:15.772117 Total UI for P1: 0, mck2ui 16
4945 23:49:15.775212 best dqsien dly found for B1: ( 0, 14, 20)
4946 23:49:15.778243 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4947 23:49:15.782050 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4948 23:49:15.782570
4949 23:49:15.788561 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4950 23:49:15.791807 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4951 23:49:15.794934 [Gating] SW calibration Done
4952 23:49:15.795598 ==
4953 23:49:15.797792 Dram Type= 6, Freq= 0, CH_0, rank 0
4954 23:49:15.801232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4955 23:49:15.801673 ==
4956 23:49:15.801998 RX Vref Scan: 0
4957 23:49:15.802303
4958 23:49:15.805122 RX Vref 0 -> 0, step: 1
4959 23:49:15.805693
4960 23:49:15.807836 RX Delay -80 -> 252, step: 8
4961 23:49:15.811421 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4962 23:49:15.814690 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4963 23:49:15.817983 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4964 23:49:15.824662 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4965 23:49:15.828468 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4966 23:49:15.831126 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4967 23:49:15.834495 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4968 23:49:15.837792 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4969 23:49:15.844077 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4970 23:49:15.847751 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4971 23:49:15.850904 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4972 23:49:15.854470 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
4973 23:49:15.858170 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4974 23:49:15.861154 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4975 23:49:15.868032 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4976 23:49:15.871395 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4977 23:49:15.871908 ==
4978 23:49:15.874508 Dram Type= 6, Freq= 0, CH_0, rank 0
4979 23:49:15.877478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4980 23:49:15.877892 ==
4981 23:49:15.878216 DQS Delay:
4982 23:49:15.881558 DQS0 = 0, DQS1 = 0
4983 23:49:15.882071 DQM Delay:
4984 23:49:15.884589 DQM0 = 96, DQM1 = 87
4985 23:49:15.885100 DQ Delay:
4986 23:49:15.887656 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
4987 23:49:15.890871 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
4988 23:49:15.894406 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83
4989 23:49:15.897912 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4990 23:49:15.898427
4991 23:49:15.898751
4992 23:49:15.899049 ==
4993 23:49:15.900786 Dram Type= 6, Freq= 0, CH_0, rank 0
4994 23:49:15.907266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4995 23:49:15.907772 ==
4996 23:49:15.908103
4997 23:49:15.908405
4998 23:49:15.908694 TX Vref Scan disable
4999 23:49:15.910768 == TX Byte 0 ==
5000 23:49:15.914082 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5001 23:49:15.920629 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5002 23:49:15.921149 == TX Byte 1 ==
5003 23:49:15.924085 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5004 23:49:15.930608 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5005 23:49:15.931123 ==
5006 23:49:15.933805 Dram Type= 6, Freq= 0, CH_0, rank 0
5007 23:49:15.937283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5008 23:49:15.937847 ==
5009 23:49:15.938289
5010 23:49:15.938817
5011 23:49:15.940359 TX Vref Scan disable
5012 23:49:15.940770 == TX Byte 0 ==
5013 23:49:15.946825 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5014 23:49:15.950536 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5015 23:49:15.951074 == TX Byte 1 ==
5016 23:49:15.956932 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5017 23:49:15.960050 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5018 23:49:15.960470
5019 23:49:15.960810 [DATLAT]
5020 23:49:15.963727 Freq=933, CH0 RK0
5021 23:49:15.964140
5022 23:49:15.964462 DATLAT Default: 0xd
5023 23:49:15.967338 0, 0xFFFF, sum = 0
5024 23:49:15.967861 1, 0xFFFF, sum = 0
5025 23:49:15.970614 2, 0xFFFF, sum = 0
5026 23:49:15.971173 3, 0xFFFF, sum = 0
5027 23:49:15.973607 4, 0xFFFF, sum = 0
5028 23:49:15.976763 5, 0xFFFF, sum = 0
5029 23:49:15.977191 6, 0xFFFF, sum = 0
5030 23:49:15.980166 7, 0xFFFF, sum = 0
5031 23:49:15.980681 8, 0xFFFF, sum = 0
5032 23:49:15.983576 9, 0xFFFF, sum = 0
5033 23:49:15.984088 10, 0x0, sum = 1
5034 23:49:15.986790 11, 0x0, sum = 2
5035 23:49:15.987213 12, 0x0, sum = 3
5036 23:49:15.987547 13, 0x0, sum = 4
5037 23:49:15.989986 best_step = 11
5038 23:49:15.990402
5039 23:49:15.990729 ==
5040 23:49:15.993345 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 23:49:15.996730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 23:49:15.997148 ==
5043 23:49:16.000198 RX Vref Scan: 1
5044 23:49:16.000708
5045 23:49:16.003473 RX Vref 0 -> 0, step: 1
5046 23:49:16.003889
5047 23:49:16.004216 RX Delay -69 -> 252, step: 4
5048 23:49:16.004528
5049 23:49:16.006961 Set Vref, RX VrefLevel [Byte0]: 47
5050 23:49:16.009839 [Byte1]: 50
5051 23:49:16.014809
5052 23:49:16.015314 Final RX Vref Byte 0 = 47 to rank0
5053 23:49:16.018031 Final RX Vref Byte 1 = 50 to rank0
5054 23:49:16.021417 Final RX Vref Byte 0 = 47 to rank1
5055 23:49:16.024569 Final RX Vref Byte 1 = 50 to rank1==
5056 23:49:16.028220 Dram Type= 6, Freq= 0, CH_0, rank 0
5057 23:49:16.034888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5058 23:49:16.035401 ==
5059 23:49:16.035735 DQS Delay:
5060 23:49:16.038053 DQS0 = 0, DQS1 = 0
5061 23:49:16.038470 DQM Delay:
5062 23:49:16.038799 DQM0 = 97, DQM1 = 88
5063 23:49:16.040815 DQ Delay:
5064 23:49:16.044639 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =94
5065 23:49:16.048010 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5066 23:49:16.051091 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5067 23:49:16.054294 DQ12 =94, DQ13 =96, DQ14 =100, DQ15 =98
5068 23:49:16.054914
5069 23:49:16.055254
5070 23:49:16.060782 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5071 23:49:16.064188 CH0 RK0: MR19=505, MR18=2424
5072 23:49:16.070845 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5073 23:49:16.071358
5074 23:49:16.074382 ----->DramcWriteLeveling(PI) begin...
5075 23:49:16.074807 ==
5076 23:49:16.077687 Dram Type= 6, Freq= 0, CH_0, rank 1
5077 23:49:16.081148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5078 23:49:16.081738 ==
5079 23:49:16.084448 Write leveling (Byte 0): 28 => 28
5080 23:49:16.087393 Write leveling (Byte 1): 28 => 28
5081 23:49:16.090952 DramcWriteLeveling(PI) end<-----
5082 23:49:16.091456
5083 23:49:16.091783 ==
5084 23:49:16.093954 Dram Type= 6, Freq= 0, CH_0, rank 1
5085 23:49:16.097444 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5086 23:49:16.100728 ==
5087 23:49:16.101140 [Gating] SW mode calibration
5088 23:49:16.110562 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5089 23:49:16.113890 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5090 23:49:16.117523 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 23:49:16.124362 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 23:49:16.127435 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 23:49:16.130713 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 23:49:16.137117 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 23:49:16.140427 0 10 20 | B1->B0 | 3333 2f2f | 1 1 | (0 1) (1 0)
5096 23:49:16.143753 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5097 23:49:16.150643 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 23:49:16.153654 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 23:49:16.156657 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 23:49:16.163804 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 23:49:16.166888 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 23:49:16.170144 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5103 23:49:16.177056 0 11 20 | B1->B0 | 3030 3737 | 0 1 | (0 0) (0 0)
5104 23:49:16.180360 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5105 23:49:16.183104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 23:49:16.190190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 23:49:16.193734 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 23:49:16.196803 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 23:49:16.203659 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 23:49:16.206797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5111 23:49:16.210141 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5112 23:49:16.216786 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5113 23:49:16.220507 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 23:49:16.223257 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 23:49:16.229874 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 23:49:16.233323 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 23:49:16.236511 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 23:49:16.243077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 23:49:16.246235 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 23:49:16.249800 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 23:49:16.256582 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 23:49:16.259801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 23:49:16.263253 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 23:49:16.269675 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:49:16.272996 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:49:16.276512 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:49:16.279656 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5128 23:49:16.282833 Total UI for P1: 0, mck2ui 16
5129 23:49:16.286290 best dqsien dly found for B0: ( 0, 14, 18)
5130 23:49:16.292977 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 23:49:16.295834 Total UI for P1: 0, mck2ui 16
5132 23:49:16.299673 best dqsien dly found for B1: ( 0, 14, 20)
5133 23:49:16.302815 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5134 23:49:16.305756 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5135 23:49:16.306219
5136 23:49:16.309776 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5137 23:49:16.312536 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5138 23:49:16.315966 [Gating] SW calibration Done
5139 23:49:16.316482 ==
5140 23:49:16.319268 Dram Type= 6, Freq= 0, CH_0, rank 1
5141 23:49:16.322566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5142 23:49:16.323084 ==
5143 23:49:16.325731 RX Vref Scan: 0
5144 23:49:16.326255
5145 23:49:16.329124 RX Vref 0 -> 0, step: 1
5146 23:49:16.329680
5147 23:49:16.330017 RX Delay -80 -> 252, step: 8
5148 23:49:16.335725 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5149 23:49:16.338784 iDelay=200, Bit 1, Center 95 (-8 ~ 199) 208
5150 23:49:16.342233 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5151 23:49:16.345985 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192
5152 23:49:16.348696 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5153 23:49:16.355598 iDelay=200, Bit 5, Center 91 (-8 ~ 191) 200
5154 23:49:16.358981 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5155 23:49:16.362179 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5156 23:49:16.365799 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5157 23:49:16.368873 iDelay=200, Bit 9, Center 67 (-32 ~ 167) 200
5158 23:49:16.372386 iDelay=200, Bit 10, Center 87 (-16 ~ 191) 208
5159 23:49:16.378962 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5160 23:49:16.382245 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5161 23:49:16.385556 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5162 23:49:16.388827 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5163 23:49:16.391917 iDelay=200, Bit 15, Center 91 (-8 ~ 191) 200
5164 23:49:16.395801 ==
5165 23:49:16.398854 Dram Type= 6, Freq= 0, CH_0, rank 1
5166 23:49:16.402002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5167 23:49:16.402423 ==
5168 23:49:16.402749 DQS Delay:
5169 23:49:16.405183 DQS0 = 0, DQS1 = 0
5170 23:49:16.405629 DQM Delay:
5171 23:49:16.408636 DQM0 = 95, DQM1 = 85
5172 23:49:16.409150 DQ Delay:
5173 23:49:16.411860 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5174 23:49:16.415020 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =103
5175 23:49:16.418426 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5176 23:49:16.422050 DQ12 =99, DQ13 =91, DQ14 =91, DQ15 =91
5177 23:49:16.422569
5178 23:49:16.422900
5179 23:49:16.423207 ==
5180 23:49:16.425105 Dram Type= 6, Freq= 0, CH_0, rank 1
5181 23:49:16.428370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5182 23:49:16.428786 ==
5183 23:49:16.429119
5184 23:49:16.431589
5185 23:49:16.432099 TX Vref Scan disable
5186 23:49:16.434559 == TX Byte 0 ==
5187 23:49:16.438186 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5188 23:49:16.441668 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5189 23:49:16.445052 == TX Byte 1 ==
5190 23:49:16.448268 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5191 23:49:16.451422 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5192 23:49:16.451936 ==
5193 23:49:16.454753 Dram Type= 6, Freq= 0, CH_0, rank 1
5194 23:49:16.461086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5195 23:49:16.461673 ==
5196 23:49:16.462021
5197 23:49:16.462345
5198 23:49:16.462706 TX Vref Scan disable
5199 23:49:16.465715 == TX Byte 0 ==
5200 23:49:16.469164 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5201 23:49:16.475301 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5202 23:49:16.475831 == TX Byte 1 ==
5203 23:49:16.478782 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5204 23:49:16.485413 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5205 23:49:16.485833
5206 23:49:16.486160 [DATLAT]
5207 23:49:16.486468 Freq=933, CH0 RK1
5208 23:49:16.486769
5209 23:49:16.488737 DATLAT Default: 0xb
5210 23:49:16.489152 0, 0xFFFF, sum = 0
5211 23:49:16.492178 1, 0xFFFF, sum = 0
5212 23:49:16.492711 2, 0xFFFF, sum = 0
5213 23:49:16.495341 3, 0xFFFF, sum = 0
5214 23:49:16.495866 4, 0xFFFF, sum = 0
5215 23:49:16.498915 5, 0xFFFF, sum = 0
5216 23:49:16.502554 6, 0xFFFF, sum = 0
5217 23:49:16.503070 7, 0xFFFF, sum = 0
5218 23:49:16.505324 8, 0xFFFF, sum = 0
5219 23:49:16.505752 9, 0xFFFF, sum = 0
5220 23:49:16.509144 10, 0x0, sum = 1
5221 23:49:16.509727 11, 0x0, sum = 2
5222 23:49:16.510068 12, 0x0, sum = 3
5223 23:49:16.512082 13, 0x0, sum = 4
5224 23:49:16.512505 best_step = 11
5225 23:49:16.512830
5226 23:49:16.515272 ==
5227 23:49:16.515789 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 23:49:16.521928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 23:49:16.522445 ==
5230 23:49:16.522775 RX Vref Scan: 0
5231 23:49:16.523082
5232 23:49:16.525258 RX Vref 0 -> 0, step: 1
5233 23:49:16.525815
5234 23:49:16.528709 RX Delay -77 -> 252, step: 4
5235 23:49:16.532226 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5236 23:49:16.538159 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5237 23:49:16.542173 iDelay=199, Bit 2, Center 98 (7 ~ 190) 184
5238 23:49:16.545057 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5239 23:49:16.548384 iDelay=199, Bit 4, Center 104 (15 ~ 194) 180
5240 23:49:16.551827 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5241 23:49:16.554827 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5242 23:49:16.561656 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5243 23:49:16.565171 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5244 23:49:16.568117 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5245 23:49:16.571718 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5246 23:49:16.575002 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5247 23:49:16.581835 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5248 23:49:16.584678 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5249 23:49:16.588418 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5250 23:49:16.591293 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5251 23:49:16.591714 ==
5252 23:49:16.594320 Dram Type= 6, Freq= 0, CH_0, rank 1
5253 23:49:16.601234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5254 23:49:16.601692 ==
5255 23:49:16.602021 DQS Delay:
5256 23:49:16.602326 DQS0 = 0, DQS1 = 0
5257 23:49:16.604294 DQM Delay:
5258 23:49:16.604710 DQM0 = 98, DQM1 = 86
5259 23:49:16.608133 DQ Delay:
5260 23:49:16.610921 DQ0 =94, DQ1 =98, DQ2 =98, DQ3 =94
5261 23:49:16.614096 DQ4 =104, DQ5 =88, DQ6 =102, DQ7 =106
5262 23:49:16.617487 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5263 23:49:16.620832 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5264 23:49:16.621251
5265 23:49:16.621633
5266 23:49:16.627884 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5267 23:49:16.631130 CH0 RK1: MR19=505, MR18=2E2E
5268 23:49:16.637635 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5269 23:49:16.640817 [RxdqsGatingPostProcess] freq 933
5270 23:49:16.644221 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5271 23:49:16.647264 Pre-setting of DQS Precalculation
5272 23:49:16.653813 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5273 23:49:16.654231 ==
5274 23:49:16.657150 Dram Type= 6, Freq= 0, CH_1, rank 0
5275 23:49:16.660341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5276 23:49:16.660759 ==
5277 23:49:16.667678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5278 23:49:16.673948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5279 23:49:16.676864 [CA 0] Center 37 (6~68) winsize 63
5280 23:49:16.680458 [CA 1] Center 37 (6~68) winsize 63
5281 23:49:16.683626 [CA 2] Center 34 (4~65) winsize 62
5282 23:49:16.687259 [CA 3] Center 34 (3~65) winsize 63
5283 23:49:16.690043 [CA 4] Center 33 (2~64) winsize 63
5284 23:49:16.698148 [CA 5] Center 33 (2~64) winsize 63
5285 23:49:16.698752
5286 23:49:16.699199 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5287 23:49:16.699519
5288 23:49:16.700157 [CATrainingPosCal] consider 1 rank data
5289 23:49:16.703674 u2DelayCellTimex100 = 270/100 ps
5290 23:49:16.706662 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5291 23:49:16.710515 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5292 23:49:16.713246 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5293 23:49:16.716706 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5294 23:49:16.720356 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5295 23:49:16.723186 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5296 23:49:16.723634
5297 23:49:16.729670 CA PerBit enable=1, Macro0, CA PI delay=33
5298 23:49:16.730086
5299 23:49:16.730412 [CBTSetCACLKResult] CA Dly = 33
5300 23:49:16.733452 CS Dly: 5 (0~36)
5301 23:49:16.733863 ==
5302 23:49:16.736766 Dram Type= 6, Freq= 0, CH_1, rank 1
5303 23:49:16.739671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5304 23:49:16.739969 ==
5305 23:49:16.746693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5306 23:49:16.753253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5307 23:49:16.756707 [CA 0] Center 37 (6~68) winsize 63
5308 23:49:16.759970 [CA 1] Center 37 (6~68) winsize 63
5309 23:49:16.763277 [CA 2] Center 34 (4~65) winsize 62
5310 23:49:16.766662 [CA 3] Center 33 (3~64) winsize 62
5311 23:49:16.769998 [CA 4] Center 33 (3~63) winsize 61
5312 23:49:16.773410 [CA 5] Center 32 (2~63) winsize 62
5313 23:49:16.773795
5314 23:49:16.776235 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5315 23:49:16.776613
5316 23:49:16.779910 [CATrainingPosCal] consider 2 rank data
5317 23:49:16.783580 u2DelayCellTimex100 = 270/100 ps
5318 23:49:16.786914 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5319 23:49:16.789917 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5320 23:49:16.793162 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5321 23:49:16.796650 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5322 23:49:16.803511 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5323 23:49:16.804024 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5324 23:49:16.806700
5325 23:49:16.809931 CA PerBit enable=1, Macro0, CA PI delay=32
5326 23:49:16.810393
5327 23:49:16.813702 [CBTSetCACLKResult] CA Dly = 32
5328 23:49:16.814218 CS Dly: 5 (0~37)
5329 23:49:16.814545
5330 23:49:16.816278 ----->DramcWriteLeveling(PI) begin...
5331 23:49:16.816799 ==
5332 23:49:16.819841 Dram Type= 6, Freq= 0, CH_1, rank 0
5333 23:49:16.822976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5334 23:49:16.826342 ==
5335 23:49:16.826755 Write leveling (Byte 0): 23 => 23
5336 23:49:16.829861 Write leveling (Byte 1): 27 => 27
5337 23:49:16.833069 DramcWriteLeveling(PI) end<-----
5338 23:49:16.833630
5339 23:49:16.833963 ==
5340 23:49:16.836338 Dram Type= 6, Freq= 0, CH_1, rank 0
5341 23:49:16.843049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5342 23:49:16.843565 ==
5343 23:49:16.843902 [Gating] SW mode calibration
5344 23:49:16.852798 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5345 23:49:16.855845 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5346 23:49:16.862660 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 23:49:16.865896 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 23:49:16.869454 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 23:49:16.872573 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 23:49:16.879327 0 10 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5351 23:49:16.882791 0 10 20 | B1->B0 | 3333 2626 | 1 0 | (1 0) (1 0)
5352 23:49:16.885755 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5353 23:49:16.892932 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 23:49:16.896160 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 23:49:16.899107 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 23:49:16.905936 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 23:49:16.908850 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 23:49:16.912474 0 11 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5359 23:49:16.918824 0 11 20 | B1->B0 | 2929 4545 | 0 0 | (1 1) (0 0)
5360 23:49:16.922202 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5361 23:49:16.925327 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 23:49:16.931929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 23:49:16.935368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 23:49:16.938340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 23:49:16.945158 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 23:49:16.948400 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5367 23:49:16.951826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5368 23:49:16.958325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5369 23:49:16.961975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:49:16.965136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:49:16.971666 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:49:16.974825 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:49:16.978126 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:49:16.984535 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:49:16.987927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:49:16.991520 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:49:16.998327 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:49:17.001676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:49:17.004588 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:49:17.011398 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:49:17.014648 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:49:17.017746 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5383 23:49:17.024667 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5384 23:49:17.024757 Total UI for P1: 0, mck2ui 16
5385 23:49:17.031558 best dqsien dly found for B0: ( 0, 14, 16)
5386 23:49:17.034606 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 23:49:17.037800 Total UI for P1: 0, mck2ui 16
5388 23:49:17.041086 best dqsien dly found for B1: ( 0, 14, 20)
5389 23:49:17.044682 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5390 23:49:17.047826 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5391 23:49:17.047911
5392 23:49:17.051225 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5393 23:49:17.054313 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5394 23:49:17.057579 [Gating] SW calibration Done
5395 23:49:17.057662 ==
5396 23:49:17.061263 Dram Type= 6, Freq= 0, CH_1, rank 0
5397 23:49:17.064568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5398 23:49:17.068238 ==
5399 23:49:17.068320 RX Vref Scan: 0
5400 23:49:17.068404
5401 23:49:17.071159 RX Vref 0 -> 0, step: 1
5402 23:49:17.071242
5403 23:49:17.074200 RX Delay -80 -> 252, step: 8
5404 23:49:17.077381 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5405 23:49:17.081211 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5406 23:49:17.084132 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5407 23:49:17.087351 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5408 23:49:17.090886 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5409 23:49:17.097376 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5410 23:49:17.100573 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5411 23:49:17.103753 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5412 23:49:17.107155 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5413 23:49:17.110405 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5414 23:49:17.117120 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5415 23:49:17.120643 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5416 23:49:17.123852 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5417 23:49:17.126963 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5418 23:49:17.130819 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5419 23:49:17.137272 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5420 23:49:17.137364 ==
5421 23:49:17.140476 Dram Type= 6, Freq= 0, CH_1, rank 0
5422 23:49:17.144012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5423 23:49:17.144095 ==
5424 23:49:17.144179 DQS Delay:
5425 23:49:17.146977 DQS0 = 0, DQS1 = 0
5426 23:49:17.147059 DQM Delay:
5427 23:49:17.150501 DQM0 = 95, DQM1 = 87
5428 23:49:17.150584 DQ Delay:
5429 23:49:17.153840 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5430 23:49:17.156971 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5431 23:49:17.160176 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =75
5432 23:49:17.163997 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5433 23:49:17.164082
5434 23:49:17.164166
5435 23:49:17.164245 ==
5436 23:49:17.166911 Dram Type= 6, Freq= 0, CH_1, rank 0
5437 23:49:17.170175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5438 23:49:17.170259 ==
5439 23:49:17.170343
5440 23:49:17.170420
5441 23:49:17.173421 TX Vref Scan disable
5442 23:49:17.177412 == TX Byte 0 ==
5443 23:49:17.180140 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5444 23:49:17.183714 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5445 23:49:17.186965 == TX Byte 1 ==
5446 23:49:17.190536 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5447 23:49:17.193292 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5448 23:49:17.193408 ==
5449 23:49:17.196881 Dram Type= 6, Freq= 0, CH_1, rank 0
5450 23:49:17.203433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5451 23:49:17.203520 ==
5452 23:49:17.203604
5453 23:49:17.203681
5454 23:49:17.203758 TX Vref Scan disable
5455 23:49:17.207718 == TX Byte 0 ==
5456 23:49:17.210784 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5457 23:49:17.217410 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5458 23:49:17.217493 == TX Byte 1 ==
5459 23:49:17.220793 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5460 23:49:17.227369 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5461 23:49:17.227457
5462 23:49:17.227540 [DATLAT]
5463 23:49:17.227618 Freq=933, CH1 RK0
5464 23:49:17.227695
5465 23:49:17.230940 DATLAT Default: 0xd
5466 23:49:17.231047 0, 0xFFFF, sum = 0
5467 23:49:17.234175 1, 0xFFFF, sum = 0
5468 23:49:17.234259 2, 0xFFFF, sum = 0
5469 23:49:17.237400 3, 0xFFFF, sum = 0
5470 23:49:17.240432 4, 0xFFFF, sum = 0
5471 23:49:17.240516 5, 0xFFFF, sum = 0
5472 23:49:17.244011 6, 0xFFFF, sum = 0
5473 23:49:17.244095 7, 0xFFFF, sum = 0
5474 23:49:17.247567 8, 0xFFFF, sum = 0
5475 23:49:17.247650 9, 0xFFFF, sum = 0
5476 23:49:17.250501 10, 0x0, sum = 1
5477 23:49:17.250585 11, 0x0, sum = 2
5478 23:49:17.253879 12, 0x0, sum = 3
5479 23:49:17.253963 13, 0x0, sum = 4
5480 23:49:17.254047 best_step = 11
5481 23:49:17.254125
5482 23:49:17.257235 ==
5483 23:49:17.260841 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 23:49:17.263843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5485 23:49:17.263927 ==
5486 23:49:17.264010 RX Vref Scan: 1
5487 23:49:17.264089
5488 23:49:17.267460 RX Vref 0 -> 0, step: 1
5489 23:49:17.267542
5490 23:49:17.270514 RX Delay -69 -> 252, step: 4
5491 23:49:17.270594
5492 23:49:17.273950 Set Vref, RX VrefLevel [Byte0]: 51
5493 23:49:17.277194 [Byte1]: 48
5494 23:49:17.277274
5495 23:49:17.280432 Final RX Vref Byte 0 = 51 to rank0
5496 23:49:17.283822 Final RX Vref Byte 1 = 48 to rank0
5497 23:49:17.287021 Final RX Vref Byte 0 = 51 to rank1
5498 23:49:17.290515 Final RX Vref Byte 1 = 48 to rank1==
5499 23:49:17.293980 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 23:49:17.297151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5501 23:49:17.300428 ==
5502 23:49:17.300508 DQS Delay:
5503 23:49:17.300570 DQS0 = 0, DQS1 = 0
5504 23:49:17.303826 DQM Delay:
5505 23:49:17.303907 DQM0 = 94, DQM1 = 88
5506 23:49:17.307461 DQ Delay:
5507 23:49:17.307541 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90
5508 23:49:17.310312 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5509 23:49:17.313711 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5510 23:49:17.320338 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98
5511 23:49:17.320418
5512 23:49:17.320480
5513 23:49:17.327128 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5514 23:49:17.330007 CH1 RK0: MR19=505, MR18=3939
5515 23:49:17.336592 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5516 23:49:17.336673
5517 23:49:17.339925 ----->DramcWriteLeveling(PI) begin...
5518 23:49:17.340007 ==
5519 23:49:17.343316 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 23:49:17.346418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 23:49:17.346500 ==
5522 23:49:17.349909 Write leveling (Byte 0): 23 => 23
5523 23:49:17.353423 Write leveling (Byte 1): 24 => 24
5524 23:49:17.356553 DramcWriteLeveling(PI) end<-----
5525 23:49:17.356633
5526 23:49:17.356749 ==
5527 23:49:17.360043 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 23:49:17.363198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5529 23:49:17.363279 ==
5530 23:49:17.366916 [Gating] SW mode calibration
5531 23:49:17.373223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5532 23:49:17.379815 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5533 23:49:17.383527 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5534 23:49:17.389857 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5535 23:49:17.393071 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5536 23:49:17.396345 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5537 23:49:17.403000 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5538 23:49:17.406243 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5539 23:49:17.409701 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5540 23:49:17.412839 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5541 23:49:17.419327 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5542 23:49:17.422892 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 23:49:17.426323 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 23:49:17.432919 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5545 23:49:17.436127 0 11 16 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
5546 23:49:17.439283 0 11 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5547 23:49:17.446096 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 23:49:17.449454 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5549 23:49:17.452730 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5550 23:49:17.459180 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 23:49:17.462418 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 23:49:17.465835 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 23:49:17.472410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5554 23:49:17.475986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5555 23:49:17.479426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5556 23:49:17.485825 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 23:49:17.489012 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 23:49:17.492633 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 23:49:17.498820 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 23:49:17.502550 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 23:49:17.505616 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 23:49:17.512117 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 23:49:17.515291 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 23:49:17.518646 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 23:49:17.525536 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 23:49:17.528708 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 23:49:17.532095 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 23:49:17.538672 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5569 23:49:17.541869 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5570 23:49:17.545531 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 23:49:17.548541 Total UI for P1: 0, mck2ui 16
5572 23:49:17.551696 best dqsien dly found for B0: ( 0, 14, 14)
5573 23:49:17.555136 Total UI for P1: 0, mck2ui 16
5574 23:49:17.558372 best dqsien dly found for B1: ( 0, 14, 16)
5575 23:49:17.562019 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5576 23:49:17.565003 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5577 23:49:17.565084
5578 23:49:17.571592 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5579 23:49:17.575088 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5580 23:49:17.578382 [Gating] SW calibration Done
5581 23:49:17.578464 ==
5582 23:49:17.581338 Dram Type= 6, Freq= 0, CH_1, rank 1
5583 23:49:17.584778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5584 23:49:17.584860 ==
5585 23:49:17.588184 RX Vref Scan: 0
5586 23:49:17.588269
5587 23:49:17.588332 RX Vref 0 -> 0, step: 1
5588 23:49:17.588391
5589 23:49:17.591437 RX Delay -80 -> 252, step: 8
5590 23:49:17.594490 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5591 23:49:17.598169 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5592 23:49:17.604658 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5593 23:49:17.608005 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5594 23:49:17.611256 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5595 23:49:17.614587 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5596 23:49:17.618066 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5597 23:49:17.621154 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5598 23:49:17.627716 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5599 23:49:17.631281 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5600 23:49:17.634424 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5601 23:49:17.638100 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5602 23:49:17.641087 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5603 23:49:17.647744 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5604 23:49:17.650794 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5605 23:49:17.654269 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5606 23:49:17.654372 ==
5607 23:49:17.657530 Dram Type= 6, Freq= 0, CH_1, rank 1
5608 23:49:17.661036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5609 23:49:17.661126 ==
5610 23:49:17.663923 DQS Delay:
5611 23:49:17.664005 DQS0 = 0, DQS1 = 0
5612 23:49:17.664072 DQM Delay:
5613 23:49:17.667514 DQM0 = 94, DQM1 = 86
5614 23:49:17.667597 DQ Delay:
5615 23:49:17.670847 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5616 23:49:17.674094 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5617 23:49:17.677134 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5618 23:49:17.680449 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =91
5619 23:49:17.680537
5620 23:49:17.680601
5621 23:49:17.684046 ==
5622 23:49:17.684128 Dram Type= 6, Freq= 0, CH_1, rank 1
5623 23:49:17.690514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5624 23:49:17.690596 ==
5625 23:49:17.690660
5626 23:49:17.690717
5627 23:49:17.693856 TX Vref Scan disable
5628 23:49:17.693936 == TX Byte 0 ==
5629 23:49:17.697035 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5630 23:49:17.703647 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5631 23:49:17.703729 == TX Byte 1 ==
5632 23:49:17.707229 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5633 23:49:17.714185 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5634 23:49:17.714266 ==
5635 23:49:17.716839 Dram Type= 6, Freq= 0, CH_1, rank 1
5636 23:49:17.720380 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5637 23:49:17.720460 ==
5638 23:49:17.720523
5639 23:49:17.720581
5640 23:49:17.723665 TX Vref Scan disable
5641 23:49:17.727047 == TX Byte 0 ==
5642 23:49:17.730200 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5643 23:49:17.733971 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5644 23:49:17.736719 == TX Byte 1 ==
5645 23:49:17.740409 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5646 23:49:17.743455 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5647 23:49:17.743541
5648 23:49:17.746812 [DATLAT]
5649 23:49:17.746894 Freq=933, CH1 RK1
5650 23:49:17.746958
5651 23:49:17.750258 DATLAT Default: 0xb
5652 23:49:17.750340 0, 0xFFFF, sum = 0
5653 23:49:17.753305 1, 0xFFFF, sum = 0
5654 23:49:17.753401 2, 0xFFFF, sum = 0
5655 23:49:17.756999 3, 0xFFFF, sum = 0
5656 23:49:17.757082 4, 0xFFFF, sum = 0
5657 23:49:17.760219 5, 0xFFFF, sum = 0
5658 23:49:17.760322 6, 0xFFFF, sum = 0
5659 23:49:17.763313 7, 0xFFFF, sum = 0
5660 23:49:17.763394 8, 0xFFFF, sum = 0
5661 23:49:17.766701 9, 0xFFFF, sum = 0
5662 23:49:17.766782 10, 0x0, sum = 1
5663 23:49:17.770037 11, 0x0, sum = 2
5664 23:49:17.770118 12, 0x0, sum = 3
5665 23:49:17.773599 13, 0x0, sum = 4
5666 23:49:17.773680 best_step = 11
5667 23:49:17.773743
5668 23:49:17.773802 ==
5669 23:49:17.776667 Dram Type= 6, Freq= 0, CH_1, rank 1
5670 23:49:17.779786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5671 23:49:17.783095 ==
5672 23:49:17.783175 RX Vref Scan: 0
5673 23:49:17.783237
5674 23:49:17.786629 RX Vref 0 -> 0, step: 1
5675 23:49:17.786708
5676 23:49:17.789952 RX Delay -69 -> 252, step: 4
5677 23:49:17.793138 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176
5678 23:49:17.796662 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5679 23:49:17.803039 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5680 23:49:17.806244 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5681 23:49:17.809281 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5682 23:49:17.812817 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5683 23:49:17.816039 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5684 23:49:17.822785 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5685 23:49:17.825838 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5686 23:49:17.829515 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5687 23:49:17.832715 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5688 23:49:17.835783 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5689 23:49:17.839271 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5690 23:49:17.846174 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5691 23:49:17.849353 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5692 23:49:17.852925 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5693 23:49:17.853064 ==
5694 23:49:17.855789 Dram Type= 6, Freq= 0, CH_1, rank 1
5695 23:49:17.859502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5696 23:49:17.859661 ==
5697 23:49:17.862400 DQS Delay:
5698 23:49:17.862546 DQS0 = 0, DQS1 = 0
5699 23:49:17.865766 DQM Delay:
5700 23:49:17.865856 DQM0 = 96, DQM1 = 87
5701 23:49:17.865920 DQ Delay:
5702 23:49:17.869340 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5703 23:49:17.872372 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5704 23:49:17.875535 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5705 23:49:17.879137 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5706 23:49:17.879221
5707 23:49:17.879283
5708 23:49:17.889177 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5709 23:49:17.892365 CH1 RK1: MR19=505, MR18=2525
5710 23:49:17.898945 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5711 23:49:17.899027 [RxdqsGatingPostProcess] freq 933
5712 23:49:17.905886 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5713 23:49:17.909065 Pre-setting of DQS Precalculation
5714 23:49:17.915380 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5715 23:49:17.922312 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5716 23:49:17.928941 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5717 23:49:17.929022
5718 23:49:17.929084
5719 23:49:17.932221 [Calibration Summary] 1866 Mbps
5720 23:49:17.932302 CH 0, Rank 0
5721 23:49:17.935520 SW Impedance : PASS
5722 23:49:17.935606 DUTY Scan : NO K
5723 23:49:17.938656 ZQ Calibration : PASS
5724 23:49:17.942267 Jitter Meter : NO K
5725 23:49:17.942359 CBT Training : PASS
5726 23:49:17.945221 Write leveling : PASS
5727 23:49:17.948496 RX DQS gating : PASS
5728 23:49:17.948595 RX DQ/DQS(RDDQC) : PASS
5729 23:49:17.951968 TX DQ/DQS : PASS
5730 23:49:17.955513 RX DATLAT : PASS
5731 23:49:17.955923 RX DQ/DQS(Engine): PASS
5732 23:49:17.960437 TX OE : NO K
5733 23:49:17.960862 All Pass.
5734 23:49:17.961186
5735 23:49:17.962269 CH 0, Rank 1
5736 23:49:17.962763 SW Impedance : PASS
5737 23:49:17.965823 DUTY Scan : NO K
5738 23:49:17.968901 ZQ Calibration : PASS
5739 23:49:17.969348 Jitter Meter : NO K
5740 23:49:17.972287 CBT Training : PASS
5741 23:49:17.975374 Write leveling : PASS
5742 23:49:17.975785 RX DQS gating : PASS
5743 23:49:17.979302 RX DQ/DQS(RDDQC) : PASS
5744 23:49:17.982499 TX DQ/DQS : PASS
5745 23:49:17.982975 RX DATLAT : PASS
5746 23:49:17.985501 RX DQ/DQS(Engine): PASS
5747 23:49:17.985910 TX OE : NO K
5748 23:49:17.988986 All Pass.
5749 23:49:17.989562
5750 23:49:17.989907 CH 1, Rank 0
5751 23:49:17.992325 SW Impedance : PASS
5752 23:49:17.992935 DUTY Scan : NO K
5753 23:49:17.995907 ZQ Calibration : PASS
5754 23:49:17.998846 Jitter Meter : NO K
5755 23:49:17.999256 CBT Training : PASS
5756 23:49:18.002304 Write leveling : PASS
5757 23:49:18.005435 RX DQS gating : PASS
5758 23:49:18.005846 RX DQ/DQS(RDDQC) : PASS
5759 23:49:18.008623 TX DQ/DQS : PASS
5760 23:49:18.012301 RX DATLAT : PASS
5761 23:49:18.012810 RX DQ/DQS(Engine): PASS
5762 23:49:18.015402 TX OE : NO K
5763 23:49:18.015814 All Pass.
5764 23:49:18.016136
5765 23:49:18.018609 CH 1, Rank 1
5766 23:49:18.019017 SW Impedance : PASS
5767 23:49:18.022175 DUTY Scan : NO K
5768 23:49:18.025457 ZQ Calibration : PASS
5769 23:49:18.025892 Jitter Meter : NO K
5770 23:49:18.028746 CBT Training : PASS
5771 23:49:18.031927 Write leveling : PASS
5772 23:49:18.032436 RX DQS gating : PASS
5773 23:49:18.035426 RX DQ/DQS(RDDQC) : PASS
5774 23:49:18.038480 TX DQ/DQS : PASS
5775 23:49:18.038912 RX DATLAT : PASS
5776 23:49:18.041731 RX DQ/DQS(Engine): PASS
5777 23:49:18.045056 TX OE : NO K
5778 23:49:18.045655 All Pass.
5779 23:49:18.045995
5780 23:49:18.046296 DramC Write-DBI off
5781 23:49:18.048933 PER_BANK_REFRESH: Hybrid Mode
5782 23:49:18.052095 TX_TRACKING: ON
5783 23:49:18.058275 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5784 23:49:18.061451 [FAST_K] Save calibration result to emmc
5785 23:49:18.068648 dramc_set_vcore_voltage set vcore to 650000
5786 23:49:18.069169 Read voltage for 400, 6
5787 23:49:18.071547 Vio18 = 0
5788 23:49:18.071970 Vcore = 650000
5789 23:49:18.072440 Vdram = 0
5790 23:49:18.075150 Vddq = 0
5791 23:49:18.075672 Vmddr = 0
5792 23:49:18.078295 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5793 23:49:18.085152 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5794 23:49:18.088190 MEM_TYPE=3, freq_sel=20
5795 23:49:18.088710 sv_algorithm_assistance_LP4_800
5796 23:49:18.095174 ============ PULL DRAM RESETB DOWN ============
5797 23:49:18.098343 ========== PULL DRAM RESETB DOWN end =========
5798 23:49:18.101247 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5799 23:49:18.104619 ===================================
5800 23:49:18.108240 LPDDR4 DRAM CONFIGURATION
5801 23:49:18.111298 ===================================
5802 23:49:18.114908 EX_ROW_EN[0] = 0x0
5803 23:49:18.115373 EX_ROW_EN[1] = 0x0
5804 23:49:18.118447 LP4Y_EN = 0x0
5805 23:49:18.119085 WORK_FSP = 0x0
5806 23:49:18.121403 WL = 0x2
5807 23:49:18.121828 RL = 0x2
5808 23:49:18.124629 BL = 0x2
5809 23:49:18.125050 RPST = 0x0
5810 23:49:18.128048 RD_PRE = 0x0
5811 23:49:18.128523 WR_PRE = 0x1
5812 23:49:18.131189 WR_PST = 0x0
5813 23:49:18.131715 DBI_WR = 0x0
5814 23:49:18.135026 DBI_RD = 0x0
5815 23:49:18.135549 OTF = 0x1
5816 23:49:18.137987 ===================================
5817 23:49:18.141139 ===================================
5818 23:49:18.144661 ANA top config
5819 23:49:18.147780 ===================================
5820 23:49:18.151288 DLL_ASYNC_EN = 0
5821 23:49:18.151853 ALL_SLAVE_EN = 1
5822 23:49:18.154487 NEW_RANK_MODE = 1
5823 23:49:18.158028 DLL_IDLE_MODE = 1
5824 23:49:18.161334 LP45_APHY_COMB_EN = 1
5825 23:49:18.164524 TX_ODT_DIS = 1
5826 23:49:18.164937 NEW_8X_MODE = 1
5827 23:49:18.167584 ===================================
5828 23:49:18.171529 ===================================
5829 23:49:18.174715 data_rate = 800
5830 23:49:18.177849 CKR = 1
5831 23:49:18.181351 DQ_P2S_RATIO = 4
5832 23:49:18.185051 ===================================
5833 23:49:18.187717 CA_P2S_RATIO = 4
5834 23:49:18.191056 DQ_CA_OPEN = 0
5835 23:49:18.191609 DQ_SEMI_OPEN = 1
5836 23:49:18.194255 CA_SEMI_OPEN = 1
5837 23:49:18.197913 CA_FULL_RATE = 0
5838 23:49:18.201385 DQ_CKDIV4_EN = 0
5839 23:49:18.204137 CA_CKDIV4_EN = 1
5840 23:49:18.207775 CA_PREDIV_EN = 0
5841 23:49:18.208308 PH8_DLY = 0
5842 23:49:18.211248 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5843 23:49:18.214384 DQ_AAMCK_DIV = 0
5844 23:49:18.217220 CA_AAMCK_DIV = 0
5845 23:49:18.221002 CA_ADMCK_DIV = 4
5846 23:49:18.224262 DQ_TRACK_CA_EN = 0
5847 23:49:18.224846 CA_PICK = 800
5848 23:49:18.227739 CA_MCKIO = 400
5849 23:49:18.230626 MCKIO_SEMI = 400
5850 23:49:18.234043 PLL_FREQ = 3016
5851 23:49:18.237743 DQ_UI_PI_RATIO = 32
5852 23:49:18.240912 CA_UI_PI_RATIO = 32
5853 23:49:18.244161 ===================================
5854 23:49:18.247517 ===================================
5855 23:49:18.248027 memory_type:LPDDR4
5856 23:49:18.250938 GP_NUM : 10
5857 23:49:18.254060 SRAM_EN : 1
5858 23:49:18.254486 MD32_EN : 0
5859 23:49:18.257362 ===================================
5860 23:49:18.260959 [ANA_INIT] >>>>>>>>>>>>>>
5861 23:49:18.264283 <<<<<< [CONFIGURE PHASE]: ANA_TX
5862 23:49:18.267258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5863 23:49:18.270923 ===================================
5864 23:49:18.273910 data_rate = 800,PCW = 0X7400
5865 23:49:18.277520 ===================================
5866 23:49:18.280837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5867 23:49:18.283659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5868 23:49:18.297279 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5869 23:49:18.300097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5870 23:49:18.303785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5871 23:49:18.306822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5872 23:49:18.310359 [ANA_INIT] flow start
5873 23:49:18.313749 [ANA_INIT] PLL >>>>>>>>
5874 23:49:18.314254 [ANA_INIT] PLL <<<<<<<<
5875 23:49:18.316935 [ANA_INIT] MIDPI >>>>>>>>
5876 23:49:18.320287 [ANA_INIT] MIDPI <<<<<<<<
5877 23:49:18.320795 [ANA_INIT] DLL >>>>>>>>
5878 23:49:18.323780 [ANA_INIT] flow end
5879 23:49:18.327012 ============ LP4 DIFF to SE enter ============
5880 23:49:18.333966 ============ LP4 DIFF to SE exit ============
5881 23:49:18.334474 [ANA_INIT] <<<<<<<<<<<<<
5882 23:49:18.337196 [Flow] Enable top DCM control >>>>>
5883 23:49:18.340510 [Flow] Enable top DCM control <<<<<
5884 23:49:18.343822 Enable DLL master slave shuffle
5885 23:49:18.350091 ==============================================================
5886 23:49:18.350601 Gating Mode config
5887 23:49:18.356886 ==============================================================
5888 23:49:18.360116 Config description:
5889 23:49:18.366483 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5890 23:49:18.373547 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5891 23:49:18.380048 SELPH_MODE 0: By rank 1: By Phase
5892 23:49:18.386494 ==============================================================
5893 23:49:18.389907 GAT_TRACK_EN = 0
5894 23:49:18.390426 RX_GATING_MODE = 2
5895 23:49:18.393404 RX_GATING_TRACK_MODE = 2
5896 23:49:18.396302 SELPH_MODE = 1
5897 23:49:18.400168 PICG_EARLY_EN = 1
5898 23:49:18.402968 VALID_LAT_VALUE = 1
5899 23:49:18.409474 ==============================================================
5900 23:49:18.412840 Enter into Gating configuration >>>>
5901 23:49:18.416478 Exit from Gating configuration <<<<
5902 23:49:18.419788 Enter into DVFS_PRE_config >>>>>
5903 23:49:18.429498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5904 23:49:18.433043 Exit from DVFS_PRE_config <<<<<
5905 23:49:18.436129 Enter into PICG configuration >>>>
5906 23:49:18.439391 Exit from PICG configuration <<<<
5907 23:49:18.443216 [RX_INPUT] configuration >>>>>
5908 23:49:18.445748 [RX_INPUT] configuration <<<<<
5909 23:49:18.449243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5910 23:49:18.455978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5911 23:49:18.462599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5912 23:49:18.465845 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5913 23:49:18.472665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5914 23:49:18.478981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5915 23:49:18.482789 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5916 23:49:18.489441 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5917 23:49:18.493002 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5918 23:49:18.495637 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5919 23:49:18.499456 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5920 23:49:18.506041 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5921 23:49:18.508836 ===================================
5922 23:49:18.509329 LPDDR4 DRAM CONFIGURATION
5923 23:49:18.512797 ===================================
5924 23:49:18.515771 EX_ROW_EN[0] = 0x0
5925 23:49:18.519084 EX_ROW_EN[1] = 0x0
5926 23:49:18.519635 LP4Y_EN = 0x0
5927 23:49:18.522800 WORK_FSP = 0x0
5928 23:49:18.523347 WL = 0x2
5929 23:49:18.525772 RL = 0x2
5930 23:49:18.526222 BL = 0x2
5931 23:49:18.528634 RPST = 0x0
5932 23:49:18.529084 RD_PRE = 0x0
5933 23:49:18.532311 WR_PRE = 0x1
5934 23:49:18.532863 WR_PST = 0x0
5935 23:49:18.535527 DBI_WR = 0x0
5936 23:49:18.536087 DBI_RD = 0x0
5937 23:49:18.538875 OTF = 0x1
5938 23:49:18.542024 ===================================
5939 23:49:18.545195 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5940 23:49:18.549081 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5941 23:49:18.555742 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5942 23:49:18.558898 ===================================
5943 23:49:18.559483 LPDDR4 DRAM CONFIGURATION
5944 23:49:18.562068 ===================================
5945 23:49:18.565054 EX_ROW_EN[0] = 0x10
5946 23:49:18.568665 EX_ROW_EN[1] = 0x0
5947 23:49:18.569169 LP4Y_EN = 0x0
5948 23:49:18.571922 WORK_FSP = 0x0
5949 23:49:18.572448 WL = 0x2
5950 23:49:18.575124 RL = 0x2
5951 23:49:18.575627 BL = 0x2
5952 23:49:18.578839 RPST = 0x0
5953 23:49:18.579348 RD_PRE = 0x0
5954 23:49:18.581996 WR_PRE = 0x1
5955 23:49:18.582404 WR_PST = 0x0
5956 23:49:18.585751 DBI_WR = 0x0
5957 23:49:18.586256 DBI_RD = 0x0
5958 23:49:18.588165 OTF = 0x1
5959 23:49:18.591554 ===================================
5960 23:49:18.598899 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5961 23:49:18.601831 nWR fixed to 30
5962 23:49:18.602355 [ModeRegInit_LP4] CH0 RK0
5963 23:49:18.604734 [ModeRegInit_LP4] CH0 RK1
5964 23:49:18.608237 [ModeRegInit_LP4] CH1 RK0
5965 23:49:18.611769 [ModeRegInit_LP4] CH1 RK1
5966 23:49:18.612295 match AC timing 18
5967 23:49:18.618033 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5968 23:49:18.621228 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5969 23:49:18.625362 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5970 23:49:18.631518 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5971 23:49:18.634989 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5972 23:49:18.635508 ==
5973 23:49:18.638140 Dram Type= 6, Freq= 0, CH_0, rank 0
5974 23:49:18.641500 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5975 23:49:18.642009 ==
5976 23:49:18.648148 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5977 23:49:18.654331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5978 23:49:18.658015 [CA 0] Center 36 (8~64) winsize 57
5979 23:49:18.661187 [CA 1] Center 36 (8~64) winsize 57
5980 23:49:18.664292 [CA 2] Center 36 (8~64) winsize 57
5981 23:49:18.664804 [CA 3] Center 36 (8~64) winsize 57
5982 23:49:18.667657 [CA 4] Center 36 (8~64) winsize 57
5983 23:49:18.671013 [CA 5] Center 36 (8~64) winsize 57
5984 23:49:18.671440
5985 23:49:18.674460 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5986 23:49:18.677679
5987 23:49:18.681143 [CATrainingPosCal] consider 1 rank data
5988 23:49:18.681706 u2DelayCellTimex100 = 270/100 ps
5989 23:49:18.687437 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5990 23:49:18.690858 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5991 23:49:18.694240 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5992 23:49:18.697621 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5993 23:49:18.700880 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5994 23:49:18.704499 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5995 23:49:18.705005
5996 23:49:18.707556 CA PerBit enable=1, Macro0, CA PI delay=36
5997 23:49:18.707963
5998 23:49:18.711121 [CBTSetCACLKResult] CA Dly = 36
5999 23:49:18.713827 CS Dly: 1 (0~32)
6000 23:49:18.714277 ==
6001 23:49:18.717407 Dram Type= 6, Freq= 0, CH_0, rank 1
6002 23:49:18.720804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6003 23:49:18.721361 ==
6004 23:49:18.727164 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6005 23:49:18.731007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6006 23:49:18.734059 [CA 0] Center 36 (8~64) winsize 57
6007 23:49:18.737713 [CA 1] Center 36 (8~64) winsize 57
6008 23:49:18.740725 [CA 2] Center 36 (8~64) winsize 57
6009 23:49:18.744325 [CA 3] Center 36 (8~64) winsize 57
6010 23:49:18.747468 [CA 4] Center 36 (8~64) winsize 57
6011 23:49:18.750626 [CA 5] Center 36 (8~64) winsize 57
6012 23:49:18.751137
6013 23:49:18.753776 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6014 23:49:18.754232
6015 23:49:18.757500 [CATrainingPosCal] consider 2 rank data
6016 23:49:18.760492 u2DelayCellTimex100 = 270/100 ps
6017 23:49:18.763769 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6018 23:49:18.766945 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6019 23:49:18.770564 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6020 23:49:18.777262 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6021 23:49:18.780868 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 23:49:18.783962 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 23:49:18.784466
6024 23:49:18.787132 CA PerBit enable=1, Macro0, CA PI delay=36
6025 23:49:18.787684
6026 23:49:18.790369 [CBTSetCACLKResult] CA Dly = 36
6027 23:49:18.790965 CS Dly: 1 (0~32)
6028 23:49:18.791343
6029 23:49:18.793502 ----->DramcWriteLeveling(PI) begin...
6030 23:49:18.793946 ==
6031 23:49:18.796819 Dram Type= 6, Freq= 0, CH_0, rank 0
6032 23:49:18.803686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6033 23:49:18.804199 ==
6034 23:49:18.807023 Write leveling (Byte 0): 32 => 0
6035 23:49:18.810105 Write leveling (Byte 1): 32 => 0
6036 23:49:18.810514 DramcWriteLeveling(PI) end<-----
6037 23:49:18.813282
6038 23:49:18.813733 ==
6039 23:49:18.816963 Dram Type= 6, Freq= 0, CH_0, rank 0
6040 23:49:18.820266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6041 23:49:18.820772 ==
6042 23:49:18.824034 [Gating] SW mode calibration
6043 23:49:18.829798 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6044 23:49:18.833457 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6045 23:49:18.840126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6046 23:49:18.843151 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6047 23:49:18.846943 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6048 23:49:18.853079 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6049 23:49:18.856997 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6050 23:49:18.859670 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6051 23:49:18.866803 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6052 23:49:18.870041 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6053 23:49:18.873100 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6054 23:49:18.876286 Total UI for P1: 0, mck2ui 16
6055 23:49:18.879162 best dqsien dly found for B0: ( 0, 10, 16)
6056 23:49:18.883139 Total UI for P1: 0, mck2ui 16
6057 23:49:18.886140 best dqsien dly found for B1: ( 0, 10, 16)
6058 23:49:18.889257 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6059 23:49:18.895994 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6060 23:49:18.896542
6061 23:49:18.899334 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6062 23:49:18.902574 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6063 23:49:18.905906 [Gating] SW calibration Done
6064 23:49:18.906382 ==
6065 23:49:18.908999 Dram Type= 6, Freq= 0, CH_0, rank 0
6066 23:49:18.912260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6067 23:49:18.912799 ==
6068 23:49:18.915830 RX Vref Scan: 0
6069 23:49:18.916282
6070 23:49:18.916654 RX Vref 0 -> 0, step: 1
6071 23:49:18.916957
6072 23:49:18.918785 RX Delay -410 -> 252, step: 16
6073 23:49:18.925430 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6074 23:49:18.928810 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6075 23:49:18.932129 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6076 23:49:18.935211 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6077 23:49:18.942252 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6078 23:49:18.945518 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6079 23:49:18.948459 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6080 23:49:18.952334 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6081 23:49:18.958601 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6082 23:49:18.962177 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6083 23:49:18.965456 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6084 23:49:18.968386 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6085 23:49:18.975442 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6086 23:49:18.979100 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6087 23:49:18.981881 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6088 23:49:18.985098 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6089 23:49:18.988634 ==
6090 23:49:18.989058 Dram Type= 6, Freq= 0, CH_0, rank 0
6091 23:49:18.995313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6092 23:49:18.995727 ==
6093 23:49:18.996051 DQS Delay:
6094 23:49:18.998406 DQS0 = 51, DQS1 = 59
6095 23:49:18.998812 DQM Delay:
6096 23:49:19.001625 DQM0 = 12, DQM1 = 16
6097 23:49:19.002049 DQ Delay:
6098 23:49:19.004815 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6099 23:49:19.008080 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6100 23:49:19.011670 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6101 23:49:19.014672 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6102 23:49:19.014890
6103 23:49:19.015061
6104 23:49:19.015220 ==
6105 23:49:19.018053 Dram Type= 6, Freq= 0, CH_0, rank 0
6106 23:49:19.021394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6107 23:49:19.021614 ==
6108 23:49:19.021789
6109 23:49:19.021947
6110 23:49:19.025224 TX Vref Scan disable
6111 23:49:19.025668 == TX Byte 0 ==
6112 23:49:19.031311 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6113 23:49:19.034861 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6114 23:49:19.035272 == TX Byte 1 ==
6115 23:49:19.041757 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6116 23:49:19.044705 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6117 23:49:19.045116 ==
6118 23:49:19.047859 Dram Type= 6, Freq= 0, CH_0, rank 0
6119 23:49:19.051543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6120 23:49:19.052179 ==
6121 23:49:19.052518
6122 23:49:19.052817
6123 23:49:19.054686 TX Vref Scan disable
6124 23:49:19.055158 == TX Byte 0 ==
6125 23:49:19.061198 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6126 23:49:19.064808 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6127 23:49:19.068025 == TX Byte 1 ==
6128 23:49:19.071061 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6129 23:49:19.074405 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6130 23:49:19.074814
6131 23:49:19.075136 [DATLAT]
6132 23:49:19.077873 Freq=400, CH0 RK0
6133 23:49:19.078282
6134 23:49:19.080989 DATLAT Default: 0xf
6135 23:49:19.081437 0, 0xFFFF, sum = 0
6136 23:49:19.084472 1, 0xFFFF, sum = 0
6137 23:49:19.084886 2, 0xFFFF, sum = 0
6138 23:49:19.087703 3, 0xFFFF, sum = 0
6139 23:49:19.088119 4, 0xFFFF, sum = 0
6140 23:49:19.090831 5, 0xFFFF, sum = 0
6141 23:49:19.091246 6, 0xFFFF, sum = 0
6142 23:49:19.094702 7, 0xFFFF, sum = 0
6143 23:49:19.095114 8, 0xFFFF, sum = 0
6144 23:49:19.097647 9, 0xFFFF, sum = 0
6145 23:49:19.098061 10, 0xFFFF, sum = 0
6146 23:49:19.100915 11, 0xFFFF, sum = 0
6147 23:49:19.101356 12, 0x0, sum = 1
6148 23:49:19.104204 13, 0x0, sum = 2
6149 23:49:19.104615 14, 0x0, sum = 3
6150 23:49:19.107299 15, 0x0, sum = 4
6151 23:49:19.107716 best_step = 13
6152 23:49:19.108037
6153 23:49:19.108333 ==
6154 23:49:19.110931 Dram Type= 6, Freq= 0, CH_0, rank 0
6155 23:49:19.114027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6156 23:49:19.117561 ==
6157 23:49:19.117976 RX Vref Scan: 1
6158 23:49:19.118303
6159 23:49:19.120983 RX Vref 0 -> 0, step: 1
6160 23:49:19.121566
6161 23:49:19.124348 RX Delay -359 -> 252, step: 8
6162 23:49:19.124866
6163 23:49:19.127482 Set Vref, RX VrefLevel [Byte0]: 47
6164 23:49:19.130839 [Byte1]: 50
6165 23:49:19.131253
6166 23:49:19.133968 Final RX Vref Byte 0 = 47 to rank0
6167 23:49:19.137882 Final RX Vref Byte 1 = 50 to rank0
6168 23:49:19.140491 Final RX Vref Byte 0 = 47 to rank1
6169 23:49:19.143919 Final RX Vref Byte 1 = 50 to rank1==
6170 23:49:19.147434 Dram Type= 6, Freq= 0, CH_0, rank 0
6171 23:49:19.150432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6172 23:49:19.150846 ==
6173 23:49:19.154122 DQS Delay:
6174 23:49:19.154630 DQS0 = 52, DQS1 = 68
6175 23:49:19.157266 DQM Delay:
6176 23:49:19.157846 DQM0 = 10, DQM1 = 17
6177 23:49:19.160367 DQ Delay:
6178 23:49:19.160884 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6179 23:49:19.163763 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6180 23:49:19.167229 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6181 23:49:19.170555 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6182 23:49:19.170965
6183 23:49:19.171289
6184 23:49:19.180423 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6185 23:49:19.184116 CH0 RK0: MR19=C0C, MR18=A9A9
6186 23:49:19.186887 CH0_RK0: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6187 23:49:19.190344 ==
6188 23:49:19.193706 Dram Type= 6, Freq= 0, CH_0, rank 1
6189 23:49:19.196797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6190 23:49:19.197209 ==
6191 23:49:19.200422 [Gating] SW mode calibration
6192 23:49:19.206940 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6193 23:49:19.210597 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6194 23:49:19.217156 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6195 23:49:19.220406 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6196 23:49:19.223798 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6197 23:49:19.230317 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6198 23:49:19.233815 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6199 23:49:19.236628 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6200 23:49:19.243772 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6201 23:49:19.247201 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6202 23:49:19.250038 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6203 23:49:19.253716 Total UI for P1: 0, mck2ui 16
6204 23:49:19.257183 best dqsien dly found for B0: ( 0, 10, 16)
6205 23:49:19.260344 Total UI for P1: 0, mck2ui 16
6206 23:49:19.263328 best dqsien dly found for B1: ( 0, 10, 16)
6207 23:49:19.266403 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6208 23:49:19.269966 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6209 23:49:19.270373
6210 23:49:19.276649 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6211 23:49:19.279870 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6212 23:49:19.283306 [Gating] SW calibration Done
6213 23:49:19.283813 ==
6214 23:49:19.286514 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 23:49:19.289723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6216 23:49:19.290131 ==
6217 23:49:19.290455 RX Vref Scan: 0
6218 23:49:19.290755
6219 23:49:19.293216 RX Vref 0 -> 0, step: 1
6220 23:49:19.293769
6221 23:49:19.296242 RX Delay -410 -> 252, step: 16
6222 23:49:19.300129 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6223 23:49:19.306669 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6224 23:49:19.309670 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6225 23:49:19.312974 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6226 23:49:19.316489 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6227 23:49:19.323404 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6228 23:49:19.326059 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6229 23:49:19.329758 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6230 23:49:19.333583 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6231 23:49:19.339260 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6232 23:49:19.342903 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6233 23:49:19.346432 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6234 23:49:19.349721 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6235 23:49:19.356286 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6236 23:49:19.359522 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6237 23:49:19.362712 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6238 23:49:19.363139 ==
6239 23:49:19.365839 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 23:49:19.372474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6241 23:49:19.372886 ==
6242 23:49:19.373202 DQS Delay:
6243 23:49:19.375788 DQS0 = 43, DQS1 = 59
6244 23:49:19.376195 DQM Delay:
6245 23:49:19.376517 DQM0 = 7, DQM1 = 15
6246 23:49:19.379625 DQ Delay:
6247 23:49:19.380134 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6248 23:49:19.382604 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6249 23:49:19.385863 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6250 23:49:19.389448 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6251 23:49:19.389947
6252 23:49:19.390265
6253 23:49:19.392806 ==
6254 23:49:19.393345 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 23:49:19.399229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6256 23:49:19.399738 ==
6257 23:49:19.400065
6258 23:49:19.400366
6259 23:49:19.402675 TX Vref Scan disable
6260 23:49:19.403178 == TX Byte 0 ==
6261 23:49:19.405881 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6262 23:49:19.412355 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6263 23:49:19.412862 == TX Byte 1 ==
6264 23:49:19.415526 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6265 23:49:19.422448 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6266 23:49:19.422941 ==
6267 23:49:19.425846 Dram Type= 6, Freq= 0, CH_0, rank 1
6268 23:49:19.429085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6269 23:49:19.429525 ==
6270 23:49:19.429851
6271 23:49:19.430152
6272 23:49:19.432343 TX Vref Scan disable
6273 23:49:19.432751 == TX Byte 0 ==
6274 23:49:19.435695 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6275 23:49:19.442229 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6276 23:49:19.442736 == TX Byte 1 ==
6277 23:49:19.445839 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6278 23:49:19.452337 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6279 23:49:19.452956
6280 23:49:19.453461 [DATLAT]
6281 23:49:19.453914 Freq=400, CH0 RK1
6282 23:49:19.454352
6283 23:49:19.455228 DATLAT Default: 0xd
6284 23:49:19.455693 0, 0xFFFF, sum = 0
6285 23:49:19.459046 1, 0xFFFF, sum = 0
6286 23:49:19.459560 2, 0xFFFF, sum = 0
6287 23:49:19.462332 3, 0xFFFF, sum = 0
6288 23:49:19.465481 4, 0xFFFF, sum = 0
6289 23:49:19.465895 5, 0xFFFF, sum = 0
6290 23:49:19.469034 6, 0xFFFF, sum = 0
6291 23:49:19.469544 7, 0xFFFF, sum = 0
6292 23:49:19.472048 8, 0xFFFF, sum = 0
6293 23:49:19.472456 9, 0xFFFF, sum = 0
6294 23:49:19.475461 10, 0xFFFF, sum = 0
6295 23:49:19.475873 11, 0xFFFF, sum = 0
6296 23:49:19.478765 12, 0x0, sum = 1
6297 23:49:19.479174 13, 0x0, sum = 2
6298 23:49:19.481798 14, 0x0, sum = 3
6299 23:49:19.482207 15, 0x0, sum = 4
6300 23:49:19.484973 best_step = 13
6301 23:49:19.485424
6302 23:49:19.485748 ==
6303 23:49:19.488434 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 23:49:19.492334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6305 23:49:19.492741 ==
6306 23:49:19.493118 RX Vref Scan: 0
6307 23:49:19.493453
6308 23:49:19.495112 RX Vref 0 -> 0, step: 1
6309 23:49:19.495513
6310 23:49:19.499112 RX Delay -359 -> 252, step: 8
6311 23:49:19.506633 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6312 23:49:19.509501 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6313 23:49:19.512538 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6314 23:49:19.516391 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6315 23:49:19.522726 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6316 23:49:19.525857 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6317 23:49:19.529409 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6318 23:49:19.532489 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6319 23:49:19.539236 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6320 23:49:19.542557 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6321 23:49:19.546026 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6322 23:49:19.549196 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6323 23:49:19.556077 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6324 23:49:19.559210 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6325 23:49:19.562218 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6326 23:49:19.569060 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6327 23:49:19.569589 ==
6328 23:49:19.572727 Dram Type= 6, Freq= 0, CH_0, rank 1
6329 23:49:19.575697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6330 23:49:19.576242 ==
6331 23:49:19.576642 DQS Delay:
6332 23:49:19.579112 DQS0 = 52, DQS1 = 64
6333 23:49:19.579585 DQM Delay:
6334 23:49:19.582104 DQM0 = 9, DQM1 = 14
6335 23:49:19.582556 DQ Delay:
6336 23:49:19.585718 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6337 23:49:19.588945 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6338 23:49:19.592350 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6339 23:49:19.595504 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6340 23:49:19.596048
6341 23:49:19.596404
6342 23:49:19.602066 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6343 23:49:19.605390 CH0 RK1: MR19=C0C, MR18=BABA
6344 23:49:19.611945 CH0_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264
6345 23:49:19.616087 [RxdqsGatingPostProcess] freq 400
6346 23:49:19.622111 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6347 23:49:19.622673 Pre-setting of DQS Precalculation
6348 23:49:19.629113 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6349 23:49:19.629706 ==
6350 23:49:19.632251 Dram Type= 6, Freq= 0, CH_1, rank 0
6351 23:49:19.635502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6352 23:49:19.636053 ==
6353 23:49:19.642185 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6354 23:49:19.648694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6355 23:49:19.652190 [CA 0] Center 36 (8~64) winsize 57
6356 23:49:19.655259 [CA 1] Center 36 (8~64) winsize 57
6357 23:49:19.658975 [CA 2] Center 36 (8~64) winsize 57
6358 23:49:19.659519 [CA 3] Center 36 (8~64) winsize 57
6359 23:49:19.661859 [CA 4] Center 36 (8~64) winsize 57
6360 23:49:19.665012 [CA 5] Center 36 (8~64) winsize 57
6361 23:49:19.665616
6362 23:49:19.671841 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6363 23:49:19.672389
6364 23:49:19.675395 [CATrainingPosCal] consider 1 rank data
6365 23:49:19.678705 u2DelayCellTimex100 = 270/100 ps
6366 23:49:19.681614 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 23:49:19.685084 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 23:49:19.688578 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 23:49:19.691527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 23:49:19.695011 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 23:49:19.698379 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 23:49:19.698833
6373 23:49:19.701384 CA PerBit enable=1, Macro0, CA PI delay=36
6374 23:49:19.701839
6375 23:49:19.705071 [CBTSetCACLKResult] CA Dly = 36
6376 23:49:19.708259 CS Dly: 1 (0~32)
6377 23:49:19.708802 ==
6378 23:49:19.711358 Dram Type= 6, Freq= 0, CH_1, rank 1
6379 23:49:19.715027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6380 23:49:19.715591 ==
6381 23:49:19.721490 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6382 23:49:19.727715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6383 23:49:19.731350 [CA 0] Center 36 (8~64) winsize 57
6384 23:49:19.731932 [CA 1] Center 36 (8~64) winsize 57
6385 23:49:19.734822 [CA 2] Center 36 (8~64) winsize 57
6386 23:49:19.737857 [CA 3] Center 36 (8~64) winsize 57
6387 23:49:19.741194 [CA 4] Center 36 (8~64) winsize 57
6388 23:49:19.744678 [CA 5] Center 36 (8~64) winsize 57
6389 23:49:19.745256
6390 23:49:19.747970 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6391 23:49:19.748560
6392 23:49:19.754522 [CATrainingPosCal] consider 2 rank data
6393 23:49:19.755100 u2DelayCellTimex100 = 270/100 ps
6394 23:49:19.757741 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6395 23:49:19.764207 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6396 23:49:19.768061 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6397 23:49:19.771244 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6398 23:49:19.774070 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 23:49:19.777928 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 23:49:19.778388
6401 23:49:19.780799 CA PerBit enable=1, Macro0, CA PI delay=36
6402 23:49:19.781258
6403 23:49:19.784049 [CBTSetCACLKResult] CA Dly = 36
6404 23:49:19.784503 CS Dly: 1 (0~32)
6405 23:49:19.787767
6406 23:49:19.791076 ----->DramcWriteLeveling(PI) begin...
6407 23:49:19.791540 ==
6408 23:49:19.793987 Dram Type= 6, Freq= 0, CH_1, rank 0
6409 23:49:19.797458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6410 23:49:19.797874 ==
6411 23:49:19.800775 Write leveling (Byte 0): 32 => 0
6412 23:49:19.803848 Write leveling (Byte 1): 32 => 0
6413 23:49:19.807158 DramcWriteLeveling(PI) end<-----
6414 23:49:19.807575
6415 23:49:19.807896 ==
6416 23:49:19.811040 Dram Type= 6, Freq= 0, CH_1, rank 0
6417 23:49:19.813836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6418 23:49:19.814256 ==
6419 23:49:19.817316 [Gating] SW mode calibration
6420 23:49:19.824395 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 23:49:19.830675 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6422 23:49:19.833841 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 23:49:19.836853 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 23:49:19.843560 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 23:49:19.846976 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6426 23:49:19.850553 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 23:49:19.857144 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 23:49:19.860693 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 23:49:19.863720 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6430 23:49:19.870142 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 23:49:19.870709 Total UI for P1: 0, mck2ui 16
6432 23:49:19.874023 best dqsien dly found for B0: ( 0, 10, 16)
6433 23:49:19.877104 Total UI for P1: 0, mck2ui 16
6434 23:49:19.880073 best dqsien dly found for B1: ( 0, 10, 16)
6435 23:49:19.887016 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6436 23:49:19.890029 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6437 23:49:19.890487
6438 23:49:19.893604 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6439 23:49:19.896968 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6440 23:49:19.900373 [Gating] SW calibration Done
6441 23:49:19.900928 ==
6442 23:49:19.903297 Dram Type= 6, Freq= 0, CH_1, rank 0
6443 23:49:19.907054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6444 23:49:19.907614 ==
6445 23:49:19.910082 RX Vref Scan: 0
6446 23:49:19.910630
6447 23:49:19.910990 RX Vref 0 -> 0, step: 1
6448 23:49:19.911324
6449 23:49:19.913061 RX Delay -410 -> 252, step: 16
6450 23:49:19.919722 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6451 23:49:19.923210 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6452 23:49:19.926484 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6453 23:49:19.929828 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6454 23:49:19.936505 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6455 23:49:19.939652 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6456 23:49:19.943248 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6457 23:49:19.946155 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6458 23:49:19.952749 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6459 23:49:19.956471 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6460 23:49:19.959411 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6461 23:49:19.962689 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6462 23:49:19.969250 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6463 23:49:19.973114 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6464 23:49:19.975787 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6465 23:49:19.982634 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6466 23:49:19.983170 ==
6467 23:49:19.985926 Dram Type= 6, Freq= 0, CH_1, rank 0
6468 23:49:19.989502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6469 23:49:19.989965 ==
6470 23:49:19.990331 DQS Delay:
6471 23:49:19.992368 DQS0 = 43, DQS1 = 59
6472 23:49:19.992991 DQM Delay:
6473 23:49:19.995907 DQM0 = 6, DQM1 = 15
6474 23:49:19.996456 DQ Delay:
6475 23:49:19.999128 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6476 23:49:20.002134 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6477 23:49:20.005902 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6478 23:49:20.008995 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6479 23:49:20.009491
6480 23:49:20.009857
6481 23:49:20.010228 ==
6482 23:49:20.012181 Dram Type= 6, Freq= 0, CH_1, rank 0
6483 23:49:20.015373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6484 23:49:20.016010 ==
6485 23:49:20.016394
6486 23:49:20.016736
6487 23:49:20.018858 TX Vref Scan disable
6488 23:49:20.019325 == TX Byte 0 ==
6489 23:49:20.025719 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6490 23:49:20.028841 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6491 23:49:20.029330 == TX Byte 1 ==
6492 23:49:20.035421 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6493 23:49:20.038653 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6494 23:49:20.039087 ==
6495 23:49:20.042051 Dram Type= 6, Freq= 0, CH_1, rank 0
6496 23:49:20.045182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6497 23:49:20.045835 ==
6498 23:49:20.048469
6499 23:49:20.049075
6500 23:49:20.049557 TX Vref Scan disable
6501 23:49:20.051992 == TX Byte 0 ==
6502 23:49:20.055091 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6503 23:49:20.058894 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6504 23:49:20.061970 == TX Byte 1 ==
6505 23:49:20.065228 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6506 23:49:20.068408 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6507 23:49:20.068823
6508 23:49:20.069144 [DATLAT]
6509 23:49:20.072255 Freq=400, CH1 RK0
6510 23:49:20.072770
6511 23:49:20.076127 DATLAT Default: 0xf
6512 23:49:20.076656 0, 0xFFFF, sum = 0
6513 23:49:20.078797 1, 0xFFFF, sum = 0
6514 23:49:20.079353 2, 0xFFFF, sum = 0
6515 23:49:20.081919 3, 0xFFFF, sum = 0
6516 23:49:20.082443 4, 0xFFFF, sum = 0
6517 23:49:20.085432 5, 0xFFFF, sum = 0
6518 23:49:20.085960 6, 0xFFFF, sum = 0
6519 23:49:20.088547 7, 0xFFFF, sum = 0
6520 23:49:20.088961 8, 0xFFFF, sum = 0
6521 23:49:20.091462 9, 0xFFFF, sum = 0
6522 23:49:20.091878 10, 0xFFFF, sum = 0
6523 23:49:20.095175 11, 0xFFFF, sum = 0
6524 23:49:20.095692 12, 0x0, sum = 1
6525 23:49:20.098513 13, 0x0, sum = 2
6526 23:49:20.099037 14, 0x0, sum = 3
6527 23:49:20.101403 15, 0x0, sum = 4
6528 23:49:20.101821 best_step = 13
6529 23:49:20.102150
6530 23:49:20.102452 ==
6531 23:49:20.105125 Dram Type= 6, Freq= 0, CH_1, rank 0
6532 23:49:20.112052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6533 23:49:20.112588 ==
6534 23:49:20.112924 RX Vref Scan: 1
6535 23:49:20.113231
6536 23:49:20.115042 RX Vref 0 -> 0, step: 1
6537 23:49:20.115459
6538 23:49:20.118327 RX Delay -359 -> 252, step: 8
6539 23:49:20.118744
6540 23:49:20.121685 Set Vref, RX VrefLevel [Byte0]: 51
6541 23:49:20.125078 [Byte1]: 48
6542 23:49:20.125696
6543 23:49:20.128262 Final RX Vref Byte 0 = 51 to rank0
6544 23:49:20.131444 Final RX Vref Byte 1 = 48 to rank0
6545 23:49:20.134796 Final RX Vref Byte 0 = 51 to rank1
6546 23:49:20.137924 Final RX Vref Byte 1 = 48 to rank1==
6547 23:49:20.141609 Dram Type= 6, Freq= 0, CH_1, rank 0
6548 23:49:20.145041 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6549 23:49:20.148561 ==
6550 23:49:20.149131 DQS Delay:
6551 23:49:20.149562 DQS0 = 48, DQS1 = 64
6552 23:49:20.151430 DQM Delay:
6553 23:49:20.152161 DQM0 = 9, DQM1 = 16
6554 23:49:20.154633 DQ Delay:
6555 23:49:20.155087 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6556 23:49:20.157821 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6557 23:49:20.161096 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6558 23:49:20.164616 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6559 23:49:20.165074
6560 23:49:20.165589
6561 23:49:20.174418 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6562 23:49:20.177797 CH1 RK0: MR19=C0C, MR18=D4D4
6563 23:49:20.181564 CH1_RK0: MR19=0xC0C, MR18=0xD4D4, DQSOSC=383, MR23=63, INC=402, DEC=268
6564 23:49:20.185024 ==
6565 23:49:20.188016 Dram Type= 6, Freq= 0, CH_1, rank 1
6566 23:49:20.191049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6567 23:49:20.191512 ==
6568 23:49:20.194718 [Gating] SW mode calibration
6569 23:49:20.201186 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6570 23:49:20.204959 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6571 23:49:20.211476 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6572 23:49:20.214531 0 7 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
6573 23:49:20.217856 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6574 23:49:20.224127 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6575 23:49:20.227629 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6576 23:49:20.230820 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6577 23:49:20.237426 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6578 23:49:20.241031 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6579 23:49:20.244338 Total UI for P1: 0, mck2ui 16
6580 23:49:20.247469 best dqsien dly found for B0: ( 0, 10, 8)
6581 23:49:20.251116 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6582 23:49:20.254026 Total UI for P1: 0, mck2ui 16
6583 23:49:20.257444 best dqsien dly found for B1: ( 0, 10, 16)
6584 23:49:20.260739 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6585 23:49:20.264170 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6586 23:49:20.264583
6587 23:49:20.270593 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6588 23:49:20.274148 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6589 23:49:20.274633 [Gating] SW calibration Done
6590 23:49:20.277243 ==
6591 23:49:20.280599 Dram Type= 6, Freq= 0, CH_1, rank 1
6592 23:49:20.283930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6593 23:49:20.284359 ==
6594 23:49:20.284710 RX Vref Scan: 0
6595 23:49:20.285018
6596 23:49:20.287182 RX Vref 0 -> 0, step: 1
6597 23:49:20.287693
6598 23:49:20.290681 RX Delay -410 -> 252, step: 16
6599 23:49:20.293845 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6600 23:49:20.300796 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6601 23:49:20.303942 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6602 23:49:20.307413 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6603 23:49:20.310447 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6604 23:49:20.317404 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6605 23:49:20.320496 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6606 23:49:20.323960 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6607 23:49:20.327341 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6608 23:49:20.333529 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6609 23:49:20.336968 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6610 23:49:20.340173 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6611 23:49:20.343533 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6612 23:49:20.350553 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6613 23:49:20.353509 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6614 23:49:20.356807 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6615 23:49:20.357223 ==
6616 23:49:20.360311 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 23:49:20.363576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6618 23:49:20.366546 ==
6619 23:49:20.366960 DQS Delay:
6620 23:49:20.367289 DQS0 = 35, DQS1 = 59
6621 23:49:20.370167 DQM Delay:
6622 23:49:20.370582 DQM0 = 3, DQM1 = 17
6623 23:49:20.373219 DQ Delay:
6624 23:49:20.373731 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6625 23:49:20.376813 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6626 23:49:20.379860 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6627 23:49:20.383405 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6628 23:49:20.383914
6629 23:49:20.384240
6630 23:49:20.384544 ==
6631 23:49:20.386814 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 23:49:20.393570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6633 23:49:20.393990 ==
6634 23:49:20.394408
6635 23:49:20.394885
6636 23:49:20.395352 TX Vref Scan disable
6637 23:49:20.396300 == TX Byte 0 ==
6638 23:49:20.399892 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6639 23:49:20.403263 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6640 23:49:20.406860 == TX Byte 1 ==
6641 23:49:20.410031 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6642 23:49:20.413125 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6643 23:49:20.416210 ==
6644 23:49:20.416639 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 23:49:20.423226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6646 23:49:20.423747 ==
6647 23:49:20.424081
6648 23:49:20.424385
6649 23:49:20.426405 TX Vref Scan disable
6650 23:49:20.426917 == TX Byte 0 ==
6651 23:49:20.429879 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6652 23:49:20.436502 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6653 23:49:20.437021 == TX Byte 1 ==
6654 23:49:20.439673 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6655 23:49:20.443000 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6656 23:49:20.446222
6657 23:49:20.446630 [DATLAT]
6658 23:49:20.447031 Freq=400, CH1 RK1
6659 23:49:20.447350
6660 23:49:20.449638 DATLAT Default: 0xd
6661 23:49:20.450050 0, 0xFFFF, sum = 0
6662 23:49:20.452955 1, 0xFFFF, sum = 0
6663 23:49:20.453418 2, 0xFFFF, sum = 0
6664 23:49:20.456194 3, 0xFFFF, sum = 0
6665 23:49:20.459421 4, 0xFFFF, sum = 0
6666 23:49:20.459840 5, 0xFFFF, sum = 0
6667 23:49:20.462884 6, 0xFFFF, sum = 0
6668 23:49:20.463302 7, 0xFFFF, sum = 0
6669 23:49:20.466127 8, 0xFFFF, sum = 0
6670 23:49:20.466544 9, 0xFFFF, sum = 0
6671 23:49:20.469153 10, 0xFFFF, sum = 0
6672 23:49:20.469599 11, 0xFFFF, sum = 0
6673 23:49:20.472936 12, 0x0, sum = 1
6674 23:49:20.473525 13, 0x0, sum = 2
6675 23:49:20.476077 14, 0x0, sum = 3
6676 23:49:20.476596 15, 0x0, sum = 4
6677 23:49:20.479673 best_step = 13
6678 23:49:20.480089
6679 23:49:20.480416 ==
6680 23:49:20.482611 Dram Type= 6, Freq= 0, CH_1, rank 1
6681 23:49:20.485670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6682 23:49:20.486083 ==
6683 23:49:20.486410 RX Vref Scan: 0
6684 23:49:20.486712
6685 23:49:20.489260 RX Vref 0 -> 0, step: 1
6686 23:49:20.489688
6687 23:49:20.492412 RX Delay -359 -> 252, step: 8
6688 23:49:20.499734 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6689 23:49:20.502884 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6690 23:49:20.506815 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6691 23:49:20.509706 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6692 23:49:20.516430 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6693 23:49:20.519681 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6694 23:49:20.523106 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6695 23:49:20.526440 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6696 23:49:20.532632 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6697 23:49:20.536320 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6698 23:49:20.539868 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6699 23:49:20.546082 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6700 23:49:20.549825 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6701 23:49:20.552769 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6702 23:49:20.556303 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6703 23:49:20.562850 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6704 23:49:20.563310 ==
6705 23:49:20.566226 Dram Type= 6, Freq= 0, CH_1, rank 1
6706 23:49:20.569200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6707 23:49:20.569696 ==
6708 23:49:20.570055 DQS Delay:
6709 23:49:20.572495 DQS0 = 48, DQS1 = 64
6710 23:49:20.572945 DQM Delay:
6711 23:49:20.576164 DQM0 = 10, DQM1 = 15
6712 23:49:20.576737 DQ Delay:
6713 23:49:20.579229 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6714 23:49:20.582369 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =12
6715 23:49:20.585659 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6716 23:49:20.589132 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6717 23:49:20.589576
6718 23:49:20.589901
6719 23:49:20.595825 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6720 23:49:20.599438 CH1 RK1: MR19=C0C, MR18=B0B0
6721 23:49:20.605761 CH1_RK1: MR19=0xC0C, MR18=0xB0B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6722 23:49:20.609131 [RxdqsGatingPostProcess] freq 400
6723 23:49:20.615470 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6724 23:49:20.619016 Pre-setting of DQS Precalculation
6725 23:49:20.622532 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6726 23:49:20.628812 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6727 23:49:20.635949 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6728 23:49:20.636527
6729 23:49:20.639341
6730 23:49:20.639912 [Calibration Summary] 800 Mbps
6731 23:49:20.642483 CH 0, Rank 0
6732 23:49:20.643055 SW Impedance : PASS
6733 23:49:20.645605 DUTY Scan : NO K
6734 23:49:20.648828 ZQ Calibration : PASS
6735 23:49:20.649406 Jitter Meter : NO K
6736 23:49:20.652025 CBT Training : PASS
6737 23:49:20.655504 Write leveling : PASS
6738 23:49:20.656063 RX DQS gating : PASS
6739 23:49:20.658772 RX DQ/DQS(RDDQC) : PASS
6740 23:49:20.662028 TX DQ/DQS : PASS
6741 23:49:20.662499 RX DATLAT : PASS
6742 23:49:20.665508 RX DQ/DQS(Engine): PASS
6743 23:49:20.668620 TX OE : NO K
6744 23:49:20.669073 All Pass.
6745 23:49:20.669489
6746 23:49:20.669825 CH 0, Rank 1
6747 23:49:20.672206 SW Impedance : PASS
6748 23:49:20.675281 DUTY Scan : NO K
6749 23:49:20.675837 ZQ Calibration : PASS
6750 23:49:20.678744 Jitter Meter : NO K
6751 23:49:20.679198 CBT Training : PASS
6752 23:49:20.682174 Write leveling : NO K
6753 23:49:20.685626 RX DQS gating : PASS
6754 23:49:20.686080 RX DQ/DQS(RDDQC) : PASS
6755 23:49:20.688671 TX DQ/DQS : PASS
6756 23:49:20.692004 RX DATLAT : PASS
6757 23:49:20.692461 RX DQ/DQS(Engine): PASS
6758 23:49:20.695522 TX OE : NO K
6759 23:49:20.695979 All Pass.
6760 23:49:20.696336
6761 23:49:20.698546 CH 1, Rank 0
6762 23:49:20.698954 SW Impedance : PASS
6763 23:49:20.702227 DUTY Scan : NO K
6764 23:49:20.705674 ZQ Calibration : PASS
6765 23:49:20.706086 Jitter Meter : NO K
6766 23:49:20.708961 CBT Training : PASS
6767 23:49:20.711868 Write leveling : PASS
6768 23:49:20.712280 RX DQS gating : PASS
6769 23:49:20.715165 RX DQ/DQS(RDDQC) : PASS
6770 23:49:20.718714 TX DQ/DQS : PASS
6771 23:49:20.719130 RX DATLAT : PASS
6772 23:49:20.721704 RX DQ/DQS(Engine): PASS
6773 23:49:20.722114 TX OE : NO K
6774 23:49:20.725147 All Pass.
6775 23:49:20.725585
6776 23:49:20.725911 CH 1, Rank 1
6777 23:49:20.728450 SW Impedance : PASS
6778 23:49:20.728865 DUTY Scan : NO K
6779 23:49:20.731641 ZQ Calibration : PASS
6780 23:49:20.735545 Jitter Meter : NO K
6781 23:49:20.735964 CBT Training : PASS
6782 23:49:20.738711 Write leveling : NO K
6783 23:49:20.741836 RX DQS gating : PASS
6784 23:49:20.742256 RX DQ/DQS(RDDQC) : PASS
6785 23:49:20.744919 TX DQ/DQS : PASS
6786 23:49:20.748104 RX DATLAT : PASS
6787 23:49:20.748524 RX DQ/DQS(Engine): PASS
6788 23:49:20.752040 TX OE : NO K
6789 23:49:20.752557 All Pass.
6790 23:49:20.752886
6791 23:49:20.755060 DramC Write-DBI off
6792 23:49:20.758527 PER_BANK_REFRESH: Hybrid Mode
6793 23:49:20.759046 TX_TRACKING: ON
6794 23:49:20.767961 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6795 23:49:20.771343 [FAST_K] Save calibration result to emmc
6796 23:49:20.774824 dramc_set_vcore_voltage set vcore to 725000
6797 23:49:20.778046 Read voltage for 1600, 0
6798 23:49:20.778463 Vio18 = 0
6799 23:49:20.778794 Vcore = 725000
6800 23:49:20.781055 Vdram = 0
6801 23:49:20.781494 Vddq = 0
6802 23:49:20.781826 Vmddr = 0
6803 23:49:20.788380 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6804 23:49:20.794392 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6805 23:49:20.794812 MEM_TYPE=3, freq_sel=13
6806 23:49:20.797683 sv_algorithm_assistance_LP4_3733
6807 23:49:20.800921 ============ PULL DRAM RESETB DOWN ============
6808 23:49:20.807999 ========== PULL DRAM RESETB DOWN end =========
6809 23:49:20.810885 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6810 23:49:20.814616 ===================================
6811 23:49:20.817867 LPDDR4 DRAM CONFIGURATION
6812 23:49:20.821192 ===================================
6813 23:49:20.821654 EX_ROW_EN[0] = 0x0
6814 23:49:20.824050 EX_ROW_EN[1] = 0x0
6815 23:49:20.824462 LP4Y_EN = 0x0
6816 23:49:20.827467 WORK_FSP = 0x1
6817 23:49:20.827882 WL = 0x5
6818 23:49:20.830444 RL = 0x5
6819 23:49:20.833930 BL = 0x2
6820 23:49:20.834343 RPST = 0x0
6821 23:49:20.837353 RD_PRE = 0x0
6822 23:49:20.837769 WR_PRE = 0x1
6823 23:49:20.840708 WR_PST = 0x1
6824 23:49:20.841190 DBI_WR = 0x0
6825 23:49:20.844069 DBI_RD = 0x0
6826 23:49:20.844482 OTF = 0x1
6827 23:49:20.847156 ===================================
6828 23:49:20.850671 ===================================
6829 23:49:20.854046 ANA top config
6830 23:49:20.857017 ===================================
6831 23:49:20.857501 DLL_ASYNC_EN = 0
6832 23:49:20.860414 ALL_SLAVE_EN = 0
6833 23:49:20.863837 NEW_RANK_MODE = 1
6834 23:49:20.867467 DLL_IDLE_MODE = 1
6835 23:49:20.867885 LP45_APHY_COMB_EN = 1
6836 23:49:20.870577 TX_ODT_DIS = 0
6837 23:49:20.873771 NEW_8X_MODE = 1
6838 23:49:20.877394 ===================================
6839 23:49:20.880348 ===================================
6840 23:49:20.883765 data_rate = 3200
6841 23:49:20.887088 CKR = 1
6842 23:49:20.890076 DQ_P2S_RATIO = 8
6843 23:49:20.893523 ===================================
6844 23:49:20.893944 CA_P2S_RATIO = 8
6845 23:49:20.897113 DQ_CA_OPEN = 0
6846 23:49:20.900453 DQ_SEMI_OPEN = 0
6847 23:49:20.903442 CA_SEMI_OPEN = 0
6848 23:49:20.906723 CA_FULL_RATE = 0
6849 23:49:20.910470 DQ_CKDIV4_EN = 0
6850 23:49:20.910988 CA_CKDIV4_EN = 0
6851 23:49:20.913711 CA_PREDIV_EN = 0
6852 23:49:20.916771 PH8_DLY = 12
6853 23:49:20.921497 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6854 23:49:20.923191 DQ_AAMCK_DIV = 4
6855 23:49:20.926803 CA_AAMCK_DIV = 4
6856 23:49:20.927358 CA_ADMCK_DIV = 4
6857 23:49:20.930007 DQ_TRACK_CA_EN = 0
6858 23:49:20.933339 CA_PICK = 1600
6859 23:49:20.936557 CA_MCKIO = 1600
6860 23:49:20.940297 MCKIO_SEMI = 0
6861 23:49:20.943305 PLL_FREQ = 3068
6862 23:49:20.946383 DQ_UI_PI_RATIO = 32
6863 23:49:20.949620 CA_UI_PI_RATIO = 0
6864 23:49:20.952911 ===================================
6865 23:49:20.953373 ===================================
6866 23:49:20.956596 memory_type:LPDDR4
6867 23:49:20.959537 GP_NUM : 10
6868 23:49:20.959950 SRAM_EN : 1
6869 23:49:20.962984 MD32_EN : 0
6870 23:49:20.966840 ===================================
6871 23:49:20.969593 [ANA_INIT] >>>>>>>>>>>>>>
6872 23:49:20.972966 <<<<<< [CONFIGURE PHASE]: ANA_TX
6873 23:49:20.976504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6874 23:49:20.979905 ===================================
6875 23:49:20.980315 data_rate = 3200,PCW = 0X7600
6876 23:49:20.983069 ===================================
6877 23:49:20.989795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6878 23:49:20.993153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6879 23:49:20.999354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6880 23:49:21.002567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6881 23:49:21.005846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6882 23:49:21.009843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6883 23:49:21.012408 [ANA_INIT] flow start
6884 23:49:21.015756 [ANA_INIT] PLL >>>>>>>>
6885 23:49:21.016167 [ANA_INIT] PLL <<<<<<<<
6886 23:49:21.019097 [ANA_INIT] MIDPI >>>>>>>>
6887 23:49:21.022746 [ANA_INIT] MIDPI <<<<<<<<
6888 23:49:21.023163 [ANA_INIT] DLL >>>>>>>>
6889 23:49:21.025935 [ANA_INIT] DLL <<<<<<<<
6890 23:49:21.029035 [ANA_INIT] flow end
6891 23:49:21.032592 ============ LP4 DIFF to SE enter ============
6892 23:49:21.035901 ============ LP4 DIFF to SE exit ============
6893 23:49:21.039324 [ANA_INIT] <<<<<<<<<<<<<
6894 23:49:21.042492 [Flow] Enable top DCM control >>>>>
6895 23:49:21.045578 [Flow] Enable top DCM control <<<<<
6896 23:49:21.049209 Enable DLL master slave shuffle
6897 23:49:21.055513 ==============================================================
6898 23:49:21.055934 Gating Mode config
6899 23:49:21.062221 ==============================================================
6900 23:49:21.062733 Config description:
6901 23:49:21.072310 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6902 23:49:21.078529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6903 23:49:21.085308 SELPH_MODE 0: By rank 1: By Phase
6904 23:49:21.088604 ==============================================================
6905 23:49:21.091755 GAT_TRACK_EN = 1
6906 23:49:21.095114 RX_GATING_MODE = 2
6907 23:49:21.098159 RX_GATING_TRACK_MODE = 2
6908 23:49:21.101915 SELPH_MODE = 1
6909 23:49:21.105141 PICG_EARLY_EN = 1
6910 23:49:21.108021 VALID_LAT_VALUE = 1
6911 23:49:21.111813 ==============================================================
6912 23:49:21.118116 Enter into Gating configuration >>>>
6913 23:49:21.118535 Exit from Gating configuration <<<<
6914 23:49:21.121463 Enter into DVFS_PRE_config >>>>>
6915 23:49:21.134858 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6916 23:49:21.138059 Exit from DVFS_PRE_config <<<<<
6917 23:49:21.141470 Enter into PICG configuration >>>>
6918 23:49:21.144790 Exit from PICG configuration <<<<
6919 23:49:21.145398 [RX_INPUT] configuration >>>>>
6920 23:49:21.148184 [RX_INPUT] configuration <<<<<
6921 23:49:21.154560 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6922 23:49:21.157761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6923 23:49:21.164436 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6924 23:49:21.171247 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6925 23:49:21.177474 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6926 23:49:21.184659 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6927 23:49:21.187776 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6928 23:49:21.191224 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6929 23:49:21.197171 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6930 23:49:21.200930 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6931 23:49:21.204027 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6932 23:49:21.210294 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6933 23:49:21.213418 ===================================
6934 23:49:21.213500 LPDDR4 DRAM CONFIGURATION
6935 23:49:21.216875 ===================================
6936 23:49:21.220069 EX_ROW_EN[0] = 0x0
6937 23:49:21.220152 EX_ROW_EN[1] = 0x0
6938 23:49:21.223615 LP4Y_EN = 0x0
6939 23:49:21.226894 WORK_FSP = 0x1
6940 23:49:21.226974 WL = 0x5
6941 23:49:21.230222 RL = 0x5
6942 23:49:21.230303 BL = 0x2
6943 23:49:21.233446 RPST = 0x0
6944 23:49:21.233527 RD_PRE = 0x0
6945 23:49:21.236802 WR_PRE = 0x1
6946 23:49:21.236883 WR_PST = 0x1
6947 23:49:21.240382 DBI_WR = 0x0
6948 23:49:21.240462 DBI_RD = 0x0
6949 23:49:21.243369 OTF = 0x1
6950 23:49:21.246686 ===================================
6951 23:49:21.249679 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6952 23:49:21.253008 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6953 23:49:21.260286 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6954 23:49:21.263211 ===================================
6955 23:49:21.263293 LPDDR4 DRAM CONFIGURATION
6956 23:49:21.266304 ===================================
6957 23:49:21.269776 EX_ROW_EN[0] = 0x10
6958 23:49:21.269920 EX_ROW_EN[1] = 0x0
6959 23:49:21.273187 LP4Y_EN = 0x0
6960 23:49:21.273270 WORK_FSP = 0x1
6961 23:49:21.276370 WL = 0x5
6962 23:49:21.279552 RL = 0x5
6963 23:49:21.279633 BL = 0x2
6964 23:49:21.283257 RPST = 0x0
6965 23:49:21.283338 RD_PRE = 0x0
6966 23:49:21.286346 WR_PRE = 0x1
6967 23:49:21.286427 WR_PST = 0x1
6968 23:49:21.289575 DBI_WR = 0x0
6969 23:49:21.289678 DBI_RD = 0x0
6970 23:49:21.292693 OTF = 0x1
6971 23:49:21.296210 ===================================
6972 23:49:21.302596 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6973 23:49:21.302677 ==
6974 23:49:21.305898 Dram Type= 6, Freq= 0, CH_0, rank 0
6975 23:49:21.309176 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6976 23:49:21.309260 ==
6977 23:49:21.312599 [Duty_Offset_Calibration]
6978 23:49:21.312679 B0:0 B1:2 CA:1
6979 23:49:21.312743
6980 23:49:21.315718 [DutyScan_Calibration_Flow] k_type=0
6981 23:49:21.326354
6982 23:49:21.326436 ==CLK 0==
6983 23:49:21.329504 Final CLK duty delay cell = 0
6984 23:49:21.332958 [0] MAX Duty = 5156%(X100), DQS PI = 22
6985 23:49:21.336111 [0] MIN Duty = 4938%(X100), DQS PI = 52
6986 23:49:21.339502 [0] AVG Duty = 5047%(X100)
6987 23:49:21.339585
6988 23:49:21.342764 CH0 CLK Duty spec in!! Max-Min= 218%
6989 23:49:21.346037 [DutyScan_Calibration_Flow] ====Done====
6990 23:49:21.346163
6991 23:49:21.349422 [DutyScan_Calibration_Flow] k_type=1
6992 23:49:21.366321
6993 23:49:21.366405 ==DQS 0 ==
6994 23:49:21.369556 Final DQS duty delay cell = 0
6995 23:49:21.373029 [0] MAX Duty = 5125%(X100), DQS PI = 32
6996 23:49:21.376329 [0] MIN Duty = 5031%(X100), DQS PI = 8
6997 23:49:21.379363 [0] AVG Duty = 5078%(X100)
6998 23:49:21.379444
6999 23:49:21.379507 ==DQS 1 ==
7000 23:49:21.382639 Final DQS duty delay cell = 0
7001 23:49:21.386130 [0] MAX Duty = 5031%(X100), DQS PI = 6
7002 23:49:21.389274 [0] MIN Duty = 4876%(X100), DQS PI = 18
7003 23:49:21.392556 [0] AVG Duty = 4953%(X100)
7004 23:49:21.392637
7005 23:49:21.396372 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7006 23:49:21.396486
7007 23:49:21.399480 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7008 23:49:21.402670 [DutyScan_Calibration_Flow] ====Done====
7009 23:49:21.402750
7010 23:49:21.406140 [DutyScan_Calibration_Flow] k_type=3
7011 23:49:21.423253
7012 23:49:21.423341 ==DQM 0 ==
7013 23:49:21.426697 Final DQM duty delay cell = 0
7014 23:49:21.429866 [0] MAX Duty = 5187%(X100), DQS PI = 24
7015 23:49:21.433251 [0] MIN Duty = 4907%(X100), DQS PI = 44
7016 23:49:21.436429 [0] AVG Duty = 5047%(X100)
7017 23:49:21.436510
7018 23:49:21.436574 ==DQM 1 ==
7019 23:49:21.439649 Final DQM duty delay cell = 0
7020 23:49:21.443050 [0] MAX Duty = 5031%(X100), DQS PI = 52
7021 23:49:21.446655 [0] MIN Duty = 4782%(X100), DQS PI = 14
7022 23:49:21.449990 [0] AVG Duty = 4906%(X100)
7023 23:49:21.450070
7024 23:49:21.453228 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7025 23:49:21.453333
7026 23:49:21.456330 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7027 23:49:21.459715 [DutyScan_Calibration_Flow] ====Done====
7028 23:49:21.459844
7029 23:49:21.462711 [DutyScan_Calibration_Flow] k_type=2
7030 23:49:21.479848
7031 23:49:21.479955 ==DQ 0 ==
7032 23:49:21.483256 Final DQ duty delay cell = 0
7033 23:49:21.486487 [0] MAX Duty = 5218%(X100), DQS PI = 18
7034 23:49:21.489670 [0] MIN Duty = 4938%(X100), DQS PI = 54
7035 23:49:21.489774 [0] AVG Duty = 5078%(X100)
7036 23:49:21.493050
7037 23:49:21.493133 ==DQ 1 ==
7038 23:49:21.496124 Final DQ duty delay cell = -4
7039 23:49:21.499399 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7040 23:49:21.502891 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7041 23:49:21.505961 [-4] AVG Duty = 4953%(X100)
7042 23:49:21.506043
7043 23:49:21.509809 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7044 23:49:21.509891
7045 23:49:21.513039 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7046 23:49:21.516299 [DutyScan_Calibration_Flow] ====Done====
7047 23:49:21.516380 ==
7048 23:49:21.519184 Dram Type= 6, Freq= 0, CH_1, rank 0
7049 23:49:21.522603 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7050 23:49:21.522688 ==
7051 23:49:21.526090 [Duty_Offset_Calibration]
7052 23:49:21.526171 B0:0 B1:5 CA:-5
7053 23:49:21.526234
7054 23:49:21.529103 [DutyScan_Calibration_Flow] k_type=0
7055 23:49:21.540408
7056 23:49:21.540490 ==CLK 0==
7057 23:49:21.543596 Final CLK duty delay cell = 0
7058 23:49:21.546830 [0] MAX Duty = 5156%(X100), DQS PI = 20
7059 23:49:21.550450 [0] MIN Duty = 4906%(X100), DQS PI = 52
7060 23:49:21.550532 [0] AVG Duty = 5031%(X100)
7061 23:49:21.553541
7062 23:49:21.556875 CH1 CLK Duty spec in!! Max-Min= 250%
7063 23:49:21.560340 [DutyScan_Calibration_Flow] ====Done====
7064 23:49:21.560422
7065 23:49:21.563407 [DutyScan_Calibration_Flow] k_type=1
7066 23:49:21.579173
7067 23:49:21.579263 ==DQS 0 ==
7068 23:49:21.582274 Final DQS duty delay cell = 0
7069 23:49:21.585681 [0] MAX Duty = 5187%(X100), DQS PI = 20
7070 23:49:21.588801 [0] MIN Duty = 4875%(X100), DQS PI = 44
7071 23:49:21.592510 [0] AVG Duty = 5031%(X100)
7072 23:49:21.592590
7073 23:49:21.592653 ==DQS 1 ==
7074 23:49:21.595480 Final DQS duty delay cell = -4
7075 23:49:21.599047 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7076 23:49:21.602340 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7077 23:49:21.605322 [-4] AVG Duty = 4922%(X100)
7078 23:49:21.605417
7079 23:49:21.608692 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7080 23:49:21.608773
7081 23:49:21.612151 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7082 23:49:21.615510 [DutyScan_Calibration_Flow] ====Done====
7083 23:49:21.615591
7084 23:49:21.618746 [DutyScan_Calibration_Flow] k_type=3
7085 23:49:21.634638
7086 23:49:21.634721 ==DQM 0 ==
7087 23:49:21.637988 Final DQM duty delay cell = -4
7088 23:49:21.641734 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7089 23:49:21.645069 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7090 23:49:21.647975 [-4] AVG Duty = 4922%(X100)
7091 23:49:21.648056
7092 23:49:21.648119 ==DQM 1 ==
7093 23:49:21.651548 Final DQM duty delay cell = -4
7094 23:49:21.654686 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7095 23:49:21.658008 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7096 23:49:21.661258 [-4] AVG Duty = 4984%(X100)
7097 23:49:21.661376
7098 23:49:21.664672 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7099 23:49:21.664752
7100 23:49:21.667859 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7101 23:49:21.671323 [DutyScan_Calibration_Flow] ====Done====
7102 23:49:21.671404
7103 23:49:21.674691 [DutyScan_Calibration_Flow] k_type=2
7104 23:49:21.692618
7105 23:49:21.692699 ==DQ 0 ==
7106 23:49:21.696042 Final DQ duty delay cell = 0
7107 23:49:21.698864 [0] MAX Duty = 5093%(X100), DQS PI = 20
7108 23:49:21.702439 [0] MIN Duty = 4938%(X100), DQS PI = 48
7109 23:49:21.702520 [0] AVG Duty = 5015%(X100)
7110 23:49:21.705984
7111 23:49:21.706065 ==DQ 1 ==
7112 23:49:21.708998 Final DQ duty delay cell = 0
7113 23:49:21.712407 [0] MAX Duty = 5062%(X100), DQS PI = 6
7114 23:49:21.715905 [0] MIN Duty = 4907%(X100), DQS PI = 22
7115 23:49:21.715986 [0] AVG Duty = 4984%(X100)
7116 23:49:21.716050
7117 23:49:21.718883 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7118 23:49:21.722470
7119 23:49:21.725335 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7120 23:49:21.728789 [DutyScan_Calibration_Flow] ====Done====
7121 23:49:21.732050 nWR fixed to 30
7122 23:49:21.732132 [ModeRegInit_LP4] CH0 RK0
7123 23:49:21.735451 [ModeRegInit_LP4] CH0 RK1
7124 23:49:21.738669 [ModeRegInit_LP4] CH1 RK0
7125 23:49:21.738749 [ModeRegInit_LP4] CH1 RK1
7126 23:49:21.742391 match AC timing 4
7127 23:49:21.746176 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7128 23:49:21.749049 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7129 23:49:21.755780 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7130 23:49:21.759094 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7131 23:49:21.765473 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7132 23:49:21.765593 [MiockJmeterHQA]
7133 23:49:21.765684
7134 23:49:21.769139 [DramcMiockJmeter] u1RxGatingPI = 0
7135 23:49:21.772159 0 : 4363, 4138
7136 23:49:21.772257 4 : 4252, 4027
7137 23:49:21.772322 8 : 4363, 4138
7138 23:49:21.775501 12 : 4368, 4140
7139 23:49:21.775583 16 : 4368, 4140
7140 23:49:21.778639 20 : 4363, 4138
7141 23:49:21.778721 24 : 4253, 4026
7142 23:49:21.781964 28 : 4252, 4027
7143 23:49:21.782045 32 : 4363, 4137
7144 23:49:21.785413 36 : 4252, 4027
7145 23:49:21.785494 40 : 4253, 4027
7146 23:49:21.785558 44 : 4252, 4027
7147 23:49:21.788924 48 : 4252, 4027
7148 23:49:21.789006 52 : 4250, 4027
7149 23:49:21.792253 56 : 4250, 4026
7150 23:49:21.792359 60 : 4250, 4027
7151 23:49:21.795443 64 : 4360, 4137
7152 23:49:21.795524 68 : 4250, 4027
7153 23:49:21.798691 72 : 4250, 4026
7154 23:49:21.798773 76 : 4250, 4027
7155 23:49:21.798837 80 : 4250, 4027
7156 23:49:21.802003 84 : 4361, 4137
7157 23:49:21.802084 88 : 4250, 4027
7158 23:49:21.805195 92 : 4363, 4140
7159 23:49:21.805295 96 : 4250, 4027
7160 23:49:21.808501 100 : 4250, 1875
7161 23:49:21.808584 104 : 4363, 0
7162 23:49:21.808648 108 : 4250, 0
7163 23:49:21.811905 112 : 4250, 0
7164 23:49:21.811986 116 : 4363, 0
7165 23:49:21.815233 120 : 4361, 0
7166 23:49:21.815314 124 : 4253, 0
7167 23:49:21.815379 128 : 4250, 0
7168 23:49:21.818420 132 : 4250, 0
7169 23:49:21.818502 136 : 4252, 0
7170 23:49:21.822017 140 : 4361, 0
7171 23:49:21.822099 144 : 4250, 0
7172 23:49:21.822163 148 : 4250, 0
7173 23:49:21.824945 152 : 4360, 0
7174 23:49:21.825027 156 : 4361, 0
7175 23:49:21.828189 160 : 4251, 0
7176 23:49:21.828271 164 : 4250, 0
7177 23:49:21.828336 168 : 4250, 0
7178 23:49:21.831813 172 : 4366, 0
7179 23:49:21.831896 176 : 4250, 0
7180 23:49:21.831960 180 : 4361, 0
7181 23:49:21.834994 184 : 4250, 0
7182 23:49:21.835075 188 : 4250, 0
7183 23:49:21.838483 192 : 4250, 0
7184 23:49:21.838565 196 : 4250, 0
7185 23:49:21.838629 200 : 4252, 0
7186 23:49:21.841736 204 : 4360, 0
7187 23:49:21.841818 208 : 4366, 0
7188 23:49:21.844989 212 : 4250, 0
7189 23:49:21.845071 216 : 4250, 0
7190 23:49:21.845135 220 : 4250, 673
7191 23:49:21.848709 224 : 4252, 4007
7192 23:49:21.848791 228 : 4250, 4027
7193 23:49:21.851807 232 : 4250, 4027
7194 23:49:21.851889 236 : 4250, 4027
7195 23:49:21.854997 240 : 4250, 4027
7196 23:49:21.855079 244 : 4252, 4030
7197 23:49:21.858194 248 : 4250, 4027
7198 23:49:21.858275 252 : 4363, 4140
7199 23:49:21.861928 256 : 4250, 4027
7200 23:49:21.862010 260 : 4252, 4030
7201 23:49:21.864988 264 : 4250, 4026
7202 23:49:21.865069 268 : 4363, 4140
7203 23:49:21.865133 272 : 4361, 4137
7204 23:49:21.868250 276 : 4250, 4027
7205 23:49:21.868347 280 : 4364, 4140
7206 23:49:21.871345 284 : 4252, 4029
7207 23:49:21.871427 288 : 4250, 4026
7208 23:49:21.875087 292 : 4250, 4027
7209 23:49:21.875169 296 : 4252, 4029
7210 23:49:21.878003 300 : 4250, 4027
7211 23:49:21.878085 304 : 4364, 4140
7212 23:49:21.881374 308 : 4250, 4027
7213 23:49:21.881455 312 : 4253, 4029
7214 23:49:21.884917 316 : 4250, 4027
7215 23:49:21.884998 320 : 4361, 4138
7216 23:49:21.888102 324 : 4361, 4137
7217 23:49:21.888185 328 : 4250, 4026
7218 23:49:21.891212 332 : 4250, 4026
7219 23:49:21.891294 336 : 4253, 3841
7220 23:49:21.891358 340 : 4250, 1713
7221 23:49:21.894650
7222 23:49:21.894730 MIOCK jitter meter ch=0
7223 23:49:21.894793
7224 23:49:21.897957 1T = (340-100) = 240 dly cells
7225 23:49:21.904451 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7226 23:49:21.904533 ==
7227 23:49:21.908161 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 23:49:21.911224 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7229 23:49:21.911306 ==
7230 23:49:21.917848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7231 23:49:21.921157 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7232 23:49:21.924322 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7233 23:49:21.931078 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7234 23:49:21.939860 [CA 0] Center 41 (11~72) winsize 62
7235 23:49:21.943158 [CA 1] Center 41 (11~72) winsize 62
7236 23:49:21.946020 [CA 2] Center 37 (7~67) winsize 61
7237 23:49:21.949360 [CA 3] Center 37 (7~67) winsize 61
7238 23:49:21.952716 [CA 4] Center 35 (5~66) winsize 62
7239 23:49:21.955944 [CA 5] Center 35 (5~65) winsize 61
7240 23:49:21.956026
7241 23:49:21.959312 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7242 23:49:21.959397
7243 23:49:21.963075 [CATrainingPosCal] consider 1 rank data
7244 23:49:21.965948 u2DelayCellTimex100 = 271/100 ps
7245 23:49:21.969321 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7246 23:49:21.976243 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7247 23:49:21.979327 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7248 23:49:21.982425 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7249 23:49:21.985759 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7250 23:49:21.989157 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7251 23:49:21.989263
7252 23:49:21.992561 CA PerBit enable=1, Macro0, CA PI delay=35
7253 23:49:21.992642
7254 23:49:21.995789 [CBTSetCACLKResult] CA Dly = 35
7255 23:49:21.998967 CS Dly: 11 (0~42)
7256 23:49:22.002500 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7257 23:49:22.005708 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7258 23:49:22.005788 ==
7259 23:49:22.009096 Dram Type= 6, Freq= 0, CH_0, rank 1
7260 23:49:22.012234 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7261 23:49:22.015845 ==
7262 23:49:22.018866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7263 23:49:22.022453 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7264 23:49:22.028902 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7265 23:49:22.035424 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7266 23:49:22.041987 [CA 0] Center 42 (12~73) winsize 62
7267 23:49:22.045331 [CA 1] Center 42 (12~73) winsize 62
7268 23:49:22.048729 [CA 2] Center 38 (9~68) winsize 60
7269 23:49:22.051878 [CA 3] Center 37 (8~67) winsize 60
7270 23:49:22.055507 [CA 4] Center 36 (6~66) winsize 61
7271 23:49:22.058522 [CA 5] Center 36 (6~66) winsize 61
7272 23:49:22.058603
7273 23:49:22.062064 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7274 23:49:22.062145
7275 23:49:22.065117 [CATrainingPosCal] consider 2 rank data
7276 23:49:22.068249 u2DelayCellTimex100 = 271/100 ps
7277 23:49:22.075108 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7278 23:49:22.078496 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7279 23:49:22.081461 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7280 23:49:22.084827 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7281 23:49:22.088468 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7282 23:49:22.091639 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7283 23:49:22.091719
7284 23:49:22.094971 CA PerBit enable=1, Macro0, CA PI delay=35
7285 23:49:22.095070
7286 23:49:22.098217 [CBTSetCACLKResult] CA Dly = 35
7287 23:49:22.101555 CS Dly: 11 (0~42)
7288 23:49:22.104616 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7289 23:49:22.108298 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7290 23:49:22.108379
7291 23:49:22.111338 ----->DramcWriteLeveling(PI) begin...
7292 23:49:22.111420 ==
7293 23:49:22.114497 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 23:49:22.121184 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7295 23:49:22.121304 ==
7296 23:49:22.124521 Write leveling (Byte 0): 28 => 28
7297 23:49:22.128286 Write leveling (Byte 1): 27 => 27
7298 23:49:22.128366 DramcWriteLeveling(PI) end<-----
7299 23:49:22.131303
7300 23:49:22.131382 ==
7301 23:49:22.134840 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 23:49:22.138072 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7303 23:49:22.138152 ==
7304 23:49:22.141087 [Gating] SW mode calibration
7305 23:49:22.147977 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7306 23:49:22.151005 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7307 23:49:22.157657 0 12 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7308 23:49:22.161237 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7309 23:49:22.164373 0 12 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7310 23:49:22.170991 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7311 23:49:22.174465 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7312 23:49:22.177724 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7313 23:49:22.184281 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7314 23:49:22.187347 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7315 23:49:22.190959 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7316 23:49:22.197438 0 13 4 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
7317 23:49:22.200863 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7318 23:49:22.203810 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7319 23:49:22.210272 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7320 23:49:22.213563 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7321 23:49:22.217018 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7322 23:49:22.223798 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7323 23:49:22.227132 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7324 23:49:22.230549 0 14 4 | B1->B0 | 3131 4545 | 0 0 | (1 1) (0 0)
7325 23:49:22.237209 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7326 23:49:22.240229 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7327 23:49:22.243729 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7328 23:49:22.249988 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7329 23:49:22.253712 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 23:49:22.257199 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7331 23:49:22.263689 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7332 23:49:22.266697 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7333 23:49:22.269851 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7334 23:49:22.276906 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7335 23:49:22.279832 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7336 23:49:22.283074 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7337 23:49:22.290054 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7338 23:49:22.292852 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 23:49:22.296590 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 23:49:22.302942 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 23:49:22.306242 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 23:49:22.309396 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 23:49:22.316210 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 23:49:22.319509 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 23:49:22.323026 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 23:49:22.329834 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7347 23:49:22.332538 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7348 23:49:22.335947 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7349 23:49:22.339355 Total UI for P1: 0, mck2ui 16
7350 23:49:22.342677 best dqsien dly found for B0: ( 1, 0, 30)
7351 23:49:22.349104 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7352 23:49:22.352484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7353 23:49:22.355801 Total UI for P1: 0, mck2ui 16
7354 23:49:22.359033 best dqsien dly found for B1: ( 1, 1, 6)
7355 23:49:22.362724 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7356 23:49:22.365857 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7357 23:49:22.365963
7358 23:49:22.369227 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7359 23:49:22.372176 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7360 23:49:22.375392 [Gating] SW calibration Done
7361 23:49:22.375477 ==
7362 23:49:22.378827 Dram Type= 6, Freq= 0, CH_0, rank 0
7363 23:49:22.382413 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7364 23:49:22.385444 ==
7365 23:49:22.385527 RX Vref Scan: 0
7366 23:49:22.385622
7367 23:49:22.388770 RX Vref 0 -> 0, step: 1
7368 23:49:22.388876
7369 23:49:22.388960 RX Delay 0 -> 252, step: 8
7370 23:49:22.395745 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7371 23:49:22.398705 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7372 23:49:22.402283 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7373 23:49:22.405771 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7374 23:49:22.409010 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7375 23:49:22.415571 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7376 23:49:22.418881 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7377 23:49:22.422342 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7378 23:49:22.425439 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7379 23:49:22.428931 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7380 23:49:22.435413 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7381 23:49:22.438367 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7382 23:49:22.442025 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7383 23:49:22.445002 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7384 23:49:22.451450 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7385 23:49:22.454990 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7386 23:49:22.455070 ==
7387 23:49:22.458444 Dram Type= 6, Freq= 0, CH_0, rank 0
7388 23:49:22.461442 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7389 23:49:22.461558 ==
7390 23:49:22.464908 DQS Delay:
7391 23:49:22.464988 DQS0 = 0, DQS1 = 0
7392 23:49:22.465051 DQM Delay:
7393 23:49:22.468186 DQM0 = 130, DQM1 = 124
7394 23:49:22.468267 DQ Delay:
7395 23:49:22.471355 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7396 23:49:22.474763 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7397 23:49:22.481784 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7398 23:49:22.484788 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7399 23:49:22.484869
7400 23:49:22.484933
7401 23:49:22.484991 ==
7402 23:49:22.488218 Dram Type= 6, Freq= 0, CH_0, rank 0
7403 23:49:22.491334 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7404 23:49:22.491415 ==
7405 23:49:22.491479
7406 23:49:22.491538
7407 23:49:22.495102 TX Vref Scan disable
7408 23:49:22.495183 == TX Byte 0 ==
7409 23:49:22.501521 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7410 23:49:22.504793 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7411 23:49:22.504874 == TX Byte 1 ==
7412 23:49:22.511271 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7413 23:49:22.514988 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7414 23:49:22.515069 ==
7415 23:49:22.518014 Dram Type= 6, Freq= 0, CH_0, rank 0
7416 23:49:22.521254 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7417 23:49:22.521384 ==
7418 23:49:22.534908
7419 23:49:22.538543 TX Vref early break, caculate TX vref
7420 23:49:22.541925 TX Vref=16, minBit 8, minWin=22, winSum=376
7421 23:49:22.544943 TX Vref=18, minBit 4, minWin=23, winSum=387
7422 23:49:22.548208 TX Vref=20, minBit 8, minWin=23, winSum=392
7423 23:49:22.551342 TX Vref=22, minBit 8, minWin=23, winSum=398
7424 23:49:22.554995 TX Vref=24, minBit 8, minWin=24, winSum=410
7425 23:49:22.561808 TX Vref=26, minBit 9, minWin=24, winSum=410
7426 23:49:22.564837 TX Vref=28, minBit 8, minWin=24, winSum=417
7427 23:49:22.568120 TX Vref=30, minBit 3, minWin=25, winSum=415
7428 23:49:22.571631 TX Vref=32, minBit 1, minWin=24, winSum=404
7429 23:49:22.574438 TX Vref=34, minBit 8, minWin=23, winSum=390
7430 23:49:22.581133 [TxChooseVref] Worse bit 3, Min win 25, Win sum 415, Final Vref 30
7431 23:49:22.581215
7432 23:49:22.584513 Final TX Range 0 Vref 30
7433 23:49:22.584594
7434 23:49:22.584657 ==
7435 23:49:22.587844 Dram Type= 6, Freq= 0, CH_0, rank 0
7436 23:49:22.591079 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7437 23:49:22.591161 ==
7438 23:49:22.591225
7439 23:49:22.591284
7440 23:49:22.594332 TX Vref Scan disable
7441 23:49:22.601538 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7442 23:49:22.601620 == TX Byte 0 ==
7443 23:49:22.604197 u2DelayCellOfst[0]=10 cells (3 PI)
7444 23:49:22.607762 u2DelayCellOfst[1]=18 cells (5 PI)
7445 23:49:22.611397 u2DelayCellOfst[2]=14 cells (4 PI)
7446 23:49:22.614195 u2DelayCellOfst[3]=10 cells (3 PI)
7447 23:49:22.617617 u2DelayCellOfst[4]=7 cells (2 PI)
7448 23:49:22.620788 u2DelayCellOfst[5]=0 cells (0 PI)
7449 23:49:22.624169 u2DelayCellOfst[6]=18 cells (5 PI)
7450 23:49:22.627339 u2DelayCellOfst[7]=18 cells (5 PI)
7451 23:49:22.630892 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7452 23:49:22.634315 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7453 23:49:22.637731 == TX Byte 1 ==
7454 23:49:22.640773 u2DelayCellOfst[8]=3 cells (1 PI)
7455 23:49:22.640854 u2DelayCellOfst[9]=0 cells (0 PI)
7456 23:49:22.644264 u2DelayCellOfst[10]=10 cells (3 PI)
7457 23:49:22.647265 u2DelayCellOfst[11]=7 cells (2 PI)
7458 23:49:22.650927 u2DelayCellOfst[12]=14 cells (4 PI)
7459 23:49:22.653986 u2DelayCellOfst[13]=18 cells (5 PI)
7460 23:49:22.657153 u2DelayCellOfst[14]=21 cells (6 PI)
7461 23:49:22.660783 u2DelayCellOfst[15]=18 cells (5 PI)
7462 23:49:22.663857 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7463 23:49:22.670591 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7464 23:49:22.670676 DramC Write-DBI on
7465 23:49:22.670740 ==
7466 23:49:22.674063 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 23:49:22.680751 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7468 23:49:22.680836 ==
7469 23:49:22.680904
7470 23:49:22.680963
7471 23:49:22.681021 TX Vref Scan disable
7472 23:49:22.684519 == TX Byte 0 ==
7473 23:49:22.687595 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7474 23:49:22.691227 == TX Byte 1 ==
7475 23:49:22.694503 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7476 23:49:22.697736 DramC Write-DBI off
7477 23:49:22.697866
7478 23:49:22.697930 [DATLAT]
7479 23:49:22.697989 Freq=1600, CH0 RK0
7480 23:49:22.698046
7481 23:49:22.701049 DATLAT Default: 0xf
7482 23:49:22.701130 0, 0xFFFF, sum = 0
7483 23:49:22.704163 1, 0xFFFF, sum = 0
7484 23:49:22.707767 2, 0xFFFF, sum = 0
7485 23:49:22.707960 3, 0xFFFF, sum = 0
7486 23:49:22.710910 4, 0xFFFF, sum = 0
7487 23:49:22.710992 5, 0xFFFF, sum = 0
7488 23:49:22.714625 6, 0xFFFF, sum = 0
7489 23:49:22.714706 7, 0xFFFF, sum = 0
7490 23:49:22.717635 8, 0xFFFF, sum = 0
7491 23:49:22.717718 9, 0xFFFF, sum = 0
7492 23:49:22.720922 10, 0xFFFF, sum = 0
7493 23:49:22.721004 11, 0xFFFF, sum = 0
7494 23:49:22.724122 12, 0x8FFF, sum = 0
7495 23:49:22.724256 13, 0x0, sum = 1
7496 23:49:22.727500 14, 0x0, sum = 2
7497 23:49:22.727582 15, 0x0, sum = 3
7498 23:49:22.731016 16, 0x0, sum = 4
7499 23:49:22.731099 best_step = 14
7500 23:49:22.731162
7501 23:49:22.731220 ==
7502 23:49:22.734452 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 23:49:22.737472 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7504 23:49:22.740901 ==
7505 23:49:22.740981 RX Vref Scan: 1
7506 23:49:22.741045
7507 23:49:22.744223 Set Vref Range= 24 -> 127
7508 23:49:22.744305
7509 23:49:22.747377 RX Vref 24 -> 127, step: 1
7510 23:49:22.747457
7511 23:49:22.747521 RX Delay 11 -> 252, step: 4
7512 23:49:22.747579
7513 23:49:22.750832 Set Vref, RX VrefLevel [Byte0]: 24
7514 23:49:22.754540 [Byte1]: 24
7515 23:49:22.757714
7516 23:49:22.757795 Set Vref, RX VrefLevel [Byte0]: 25
7517 23:49:22.761027 [Byte1]: 25
7518 23:49:22.765446
7519 23:49:22.765526 Set Vref, RX VrefLevel [Byte0]: 26
7520 23:49:22.768596 [Byte1]: 26
7521 23:49:22.773163
7522 23:49:22.773243 Set Vref, RX VrefLevel [Byte0]: 27
7523 23:49:22.776357 [Byte1]: 27
7524 23:49:22.780625
7525 23:49:22.780705 Set Vref, RX VrefLevel [Byte0]: 28
7526 23:49:22.784317 [Byte1]: 28
7527 23:49:22.788134
7528 23:49:22.788214 Set Vref, RX VrefLevel [Byte0]: 29
7529 23:49:22.791399 [Byte1]: 29
7530 23:49:22.795809
7531 23:49:22.795889 Set Vref, RX VrefLevel [Byte0]: 30
7532 23:49:22.799383 [Byte1]: 30
7533 23:49:22.803633
7534 23:49:22.803714 Set Vref, RX VrefLevel [Byte0]: 31
7535 23:49:22.806572 [Byte1]: 31
7536 23:49:22.811099
7537 23:49:22.811180 Set Vref, RX VrefLevel [Byte0]: 32
7538 23:49:22.814467 [Byte1]: 32
7539 23:49:22.818682
7540 23:49:22.818762 Set Vref, RX VrefLevel [Byte0]: 33
7541 23:49:22.821936 [Byte1]: 33
7542 23:49:22.826271
7543 23:49:22.826351 Set Vref, RX VrefLevel [Byte0]: 34
7544 23:49:22.829444 [Byte1]: 34
7545 23:49:22.834006
7546 23:49:22.834086 Set Vref, RX VrefLevel [Byte0]: 35
7547 23:49:22.837479 [Byte1]: 35
7548 23:49:22.841500
7549 23:49:22.841584 Set Vref, RX VrefLevel [Byte0]: 36
7550 23:49:22.844680 [Byte1]: 36
7551 23:49:22.849203
7552 23:49:22.849283 Set Vref, RX VrefLevel [Byte0]: 37
7553 23:49:22.852213 [Byte1]: 37
7554 23:49:22.856834
7555 23:49:22.856914 Set Vref, RX VrefLevel [Byte0]: 38
7556 23:49:22.860287 [Byte1]: 38
7557 23:49:22.864269
7558 23:49:22.864349 Set Vref, RX VrefLevel [Byte0]: 39
7559 23:49:22.867649 [Byte1]: 39
7560 23:49:22.872091
7561 23:49:22.872171 Set Vref, RX VrefLevel [Byte0]: 40
7562 23:49:22.875316 [Byte1]: 40
7563 23:49:22.879657
7564 23:49:22.879736 Set Vref, RX VrefLevel [Byte0]: 41
7565 23:49:22.882940 [Byte1]: 41
7566 23:49:22.887213
7567 23:49:22.887294 Set Vref, RX VrefLevel [Byte0]: 42
7568 23:49:22.890424 [Byte1]: 42
7569 23:49:22.894727
7570 23:49:22.894807 Set Vref, RX VrefLevel [Byte0]: 43
7571 23:49:22.898080 [Byte1]: 43
7572 23:49:22.902635
7573 23:49:22.902715 Set Vref, RX VrefLevel [Byte0]: 44
7574 23:49:22.906199 [Byte1]: 44
7575 23:49:22.910090
7576 23:49:22.910169 Set Vref, RX VrefLevel [Byte0]: 45
7577 23:49:22.913565 [Byte1]: 45
7578 23:49:22.917696
7579 23:49:22.917776 Set Vref, RX VrefLevel [Byte0]: 46
7580 23:49:22.920989 [Byte1]: 46
7581 23:49:22.925364
7582 23:49:22.925445 Set Vref, RX VrefLevel [Byte0]: 47
7583 23:49:22.928342 [Byte1]: 47
7584 23:49:22.932821
7585 23:49:22.932900 Set Vref, RX VrefLevel [Byte0]: 48
7586 23:49:22.936139 [Byte1]: 48
7587 23:49:22.940383
7588 23:49:22.940464 Set Vref, RX VrefLevel [Byte0]: 49
7589 23:49:22.943490 [Byte1]: 49
7590 23:49:22.948354
7591 23:49:22.948434 Set Vref, RX VrefLevel [Byte0]: 50
7592 23:49:22.951179 [Byte1]: 50
7593 23:49:22.955864
7594 23:49:22.955944 Set Vref, RX VrefLevel [Byte0]: 51
7595 23:49:22.958774 [Byte1]: 51
7596 23:49:22.963166
7597 23:49:22.963246 Set Vref, RX VrefLevel [Byte0]: 52
7598 23:49:22.966511 [Byte1]: 52
7599 23:49:22.971041
7600 23:49:22.971122 Set Vref, RX VrefLevel [Byte0]: 53
7601 23:49:22.974573 [Byte1]: 53
7602 23:49:22.978505
7603 23:49:22.978585 Set Vref, RX VrefLevel [Byte0]: 54
7604 23:49:22.981723 [Byte1]: 54
7605 23:49:22.986175
7606 23:49:22.986256 Set Vref, RX VrefLevel [Byte0]: 55
7607 23:49:22.989304 [Byte1]: 55
7608 23:49:22.993883
7609 23:49:22.993963 Set Vref, RX VrefLevel [Byte0]: 56
7610 23:49:22.996955 [Byte1]: 56
7611 23:49:23.001471
7612 23:49:23.001553 Set Vref, RX VrefLevel [Byte0]: 57
7613 23:49:23.004516 [Byte1]: 57
7614 23:49:23.009143
7615 23:49:23.009223 Set Vref, RX VrefLevel [Byte0]: 58
7616 23:49:23.012126 [Byte1]: 58
7617 23:49:23.017137
7618 23:49:23.017218 Set Vref, RX VrefLevel [Byte0]: 59
7619 23:49:23.020172 [Byte1]: 59
7620 23:49:23.024340
7621 23:49:23.024421 Set Vref, RX VrefLevel [Byte0]: 60
7622 23:49:23.027583 [Byte1]: 60
7623 23:49:23.031710
7624 23:49:23.031790 Set Vref, RX VrefLevel [Byte0]: 61
7625 23:49:23.035157 [Byte1]: 61
7626 23:49:23.039402
7627 23:49:23.039482 Set Vref, RX VrefLevel [Byte0]: 62
7628 23:49:23.042655 [Byte1]: 62
7629 23:49:23.047114
7630 23:49:23.047194 Set Vref, RX VrefLevel [Byte0]: 63
7631 23:49:23.050509 [Byte1]: 63
7632 23:49:23.054468
7633 23:49:23.054548 Set Vref, RX VrefLevel [Byte0]: 64
7634 23:49:23.058049 [Byte1]: 64
7635 23:49:23.062101
7636 23:49:23.062180 Set Vref, RX VrefLevel [Byte0]: 65
7637 23:49:23.065307 [Byte1]: 65
7638 23:49:23.069745
7639 23:49:23.069825 Set Vref, RX VrefLevel [Byte0]: 66
7640 23:49:23.073052 [Byte1]: 66
7641 23:49:23.077396
7642 23:49:23.077476 Set Vref, RX VrefLevel [Byte0]: 67
7643 23:49:23.080639 [Byte1]: 67
7644 23:49:23.085061
7645 23:49:23.085160 Set Vref, RX VrefLevel [Byte0]: 68
7646 23:49:23.088106 [Byte1]: 68
7647 23:49:23.092723
7648 23:49:23.092820 Set Vref, RX VrefLevel [Byte0]: 69
7649 23:49:23.096032 [Byte1]: 69
7650 23:49:23.100277
7651 23:49:23.100376 Set Vref, RX VrefLevel [Byte0]: 70
7652 23:49:23.103602 [Byte1]: 70
7653 23:49:23.108298
7654 23:49:23.108395 Set Vref, RX VrefLevel [Byte0]: 71
7655 23:49:23.111385 [Byte1]: 71
7656 23:49:23.115659
7657 23:49:23.115753 Set Vref, RX VrefLevel [Byte0]: 72
7658 23:49:23.118910 [Byte1]: 72
7659 23:49:23.123020
7660 23:49:23.123098 Final RX Vref Byte 0 = 53 to rank0
7661 23:49:23.126280 Final RX Vref Byte 1 = 57 to rank0
7662 23:49:23.129629 Final RX Vref Byte 0 = 53 to rank1
7663 23:49:23.132991 Final RX Vref Byte 1 = 57 to rank1==
7664 23:49:23.136450 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 23:49:23.142950 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7666 23:49:23.143045 ==
7667 23:49:23.143133 DQS Delay:
7668 23:49:23.143209 DQS0 = 0, DQS1 = 0
7669 23:49:23.146026 DQM Delay:
7670 23:49:23.146097 DQM0 = 126, DQM1 = 121
7671 23:49:23.149683 DQ Delay:
7672 23:49:23.153103 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7673 23:49:23.156378 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7674 23:49:23.159729 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7675 23:49:23.162782 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7676 23:49:23.162886
7677 23:49:23.162969
7678 23:49:23.163045
7679 23:49:23.166105 [DramC_TX_OE_Calibration] TA2
7680 23:49:23.169457 Original DQ_B0 (3 6) =30, OEN = 27
7681 23:49:23.172797 Original DQ_B1 (3 6) =30, OEN = 27
7682 23:49:23.175980 24, 0x0, End_B0=24 End_B1=24
7683 23:49:23.176062 25, 0x0, End_B0=25 End_B1=25
7684 23:49:23.179551 26, 0x0, End_B0=26 End_B1=26
7685 23:49:23.183060 27, 0x0, End_B0=27 End_B1=27
7686 23:49:23.186254 28, 0x0, End_B0=28 End_B1=28
7687 23:49:23.189677 29, 0x0, End_B0=29 End_B1=29
7688 23:49:23.189756 30, 0x0, End_B0=30 End_B1=30
7689 23:49:23.193014 31, 0x4141, End_B0=30 End_B1=30
7690 23:49:23.196171 Byte0 end_step=30 best_step=27
7691 23:49:23.199313 Byte1 end_step=30 best_step=27
7692 23:49:23.202822 Byte0 TX OE(2T, 0.5T) = (3, 3)
7693 23:49:23.205808 Byte1 TX OE(2T, 0.5T) = (3, 3)
7694 23:49:23.205885
7695 23:49:23.205965
7696 23:49:23.212445 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7697 23:49:23.215822 CH0 RK0: MR19=303, MR18=1919
7698 23:49:23.222617 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7699 23:49:23.222707
7700 23:49:23.225893 ----->DramcWriteLeveling(PI) begin...
7701 23:49:23.225972 ==
7702 23:49:23.229078 Dram Type= 6, Freq= 0, CH_0, rank 1
7703 23:49:23.232376 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7704 23:49:23.232477 ==
7705 23:49:23.235685 Write leveling (Byte 0): 29 => 29
7706 23:49:23.238812 Write leveling (Byte 1): 28 => 28
7707 23:49:23.242374 DramcWriteLeveling(PI) end<-----
7708 23:49:23.242467
7709 23:49:23.242569 ==
7710 23:49:23.245805 Dram Type= 6, Freq= 0, CH_0, rank 1
7711 23:49:23.248818 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7712 23:49:23.248917 ==
7713 23:49:23.252256 [Gating] SW mode calibration
7714 23:49:23.258960 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7715 23:49:23.265544 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7716 23:49:23.268782 0 12 0 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7717 23:49:23.275150 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7718 23:49:23.278456 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7719 23:49:23.281820 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7720 23:49:23.288772 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7721 23:49:23.292078 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 23:49:23.295095 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7723 23:49:23.301898 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7724 23:49:23.305410 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7725 23:49:23.308614 0 13 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7726 23:49:23.311987 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7727 23:49:23.318435 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7728 23:49:23.321755 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7729 23:49:23.325066 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 23:49:23.331830 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7731 23:49:23.335097 0 13 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7732 23:49:23.338544 0 14 0 | B1->B0 | 2525 4343 | 0 1 | (0 0) (0 0)
7733 23:49:23.344906 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7734 23:49:23.348780 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7735 23:49:23.351688 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7736 23:49:23.358161 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7737 23:49:23.362153 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 23:49:23.364731 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 23:49:23.371381 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7740 23:49:23.375126 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7741 23:49:23.378267 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7742 23:49:23.384733 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7743 23:49:23.388142 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7744 23:49:23.391846 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7745 23:49:23.398027 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7746 23:49:23.401592 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 23:49:23.404768 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 23:49:23.411383 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 23:49:23.414575 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 23:49:23.418052 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 23:49:23.424735 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 23:49:23.428226 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 23:49:23.431410 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 23:49:23.438015 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 23:49:23.441265 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7756 23:49:23.444704 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7757 23:49:23.451427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7758 23:49:23.451526 Total UI for P1: 0, mck2ui 16
7759 23:49:23.458002 best dqsien dly found for B0: ( 1, 0, 30)
7760 23:49:23.461071 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7761 23:49:23.464560 Total UI for P1: 0, mck2ui 16
7762 23:49:23.467911 best dqsien dly found for B1: ( 1, 1, 2)
7763 23:49:23.470873 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7764 23:49:23.474304 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7765 23:49:23.474376
7766 23:49:23.477577 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7767 23:49:23.481014 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7768 23:49:23.484160 [Gating] SW calibration Done
7769 23:49:23.484259 ==
7770 23:49:23.487789 Dram Type= 6, Freq= 0, CH_0, rank 1
7771 23:49:23.490840 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7772 23:49:23.490939 ==
7773 23:49:23.494348 RX Vref Scan: 0
7774 23:49:23.494421
7775 23:49:23.497609 RX Vref 0 -> 0, step: 1
7776 23:49:23.497683
7777 23:49:23.497742 RX Delay 0 -> 252, step: 8
7778 23:49:23.504000 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7779 23:49:23.507524 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7780 23:49:23.511002 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7781 23:49:23.514137 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7782 23:49:23.517313 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7783 23:49:23.523983 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7784 23:49:23.527472 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7785 23:49:23.530714 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7786 23:49:23.534003 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7787 23:49:23.537424 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7788 23:49:23.544042 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7789 23:49:23.547170 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7790 23:49:23.550602 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7791 23:49:23.554071 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7792 23:49:23.557458 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7793 23:49:23.564061 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7794 23:49:23.564161 ==
7795 23:49:23.567455 Dram Type= 6, Freq= 0, CH_0, rank 1
7796 23:49:23.570922 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7797 23:49:23.570995 ==
7798 23:49:23.571068 DQS Delay:
7799 23:49:23.573873 DQS0 = 0, DQS1 = 0
7800 23:49:23.573947 DQM Delay:
7801 23:49:23.576945 DQM0 = 132, DQM1 = 125
7802 23:49:23.577014 DQ Delay:
7803 23:49:23.580395 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7804 23:49:23.583617 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7805 23:49:23.587387 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7806 23:49:23.590458 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7807 23:49:23.593532
7808 23:49:23.593608
7809 23:49:23.593685 ==
7810 23:49:23.596953 Dram Type= 6, Freq= 0, CH_0, rank 1
7811 23:49:23.600719 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7812 23:49:23.600817 ==
7813 23:49:23.600915
7814 23:49:23.601010
7815 23:49:23.603647 TX Vref Scan disable
7816 23:49:23.603743 == TX Byte 0 ==
7817 23:49:23.610393 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7818 23:49:23.613672 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7819 23:49:23.613772 == TX Byte 1 ==
7820 23:49:23.620831 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7821 23:49:23.623851 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7822 23:49:23.623955 ==
7823 23:49:23.626782 Dram Type= 6, Freq= 0, CH_0, rank 1
7824 23:49:23.630306 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7825 23:49:23.630379 ==
7826 23:49:23.643435
7827 23:49:23.646682 TX Vref early break, caculate TX vref
7828 23:49:23.650647 TX Vref=16, minBit 0, minWin=23, winSum=379
7829 23:49:23.653851 TX Vref=18, minBit 1, minWin=23, winSum=388
7830 23:49:23.656823 TX Vref=20, minBit 1, minWin=23, winSum=395
7831 23:49:23.659864 TX Vref=22, minBit 1, minWin=24, winSum=405
7832 23:49:23.663356 TX Vref=24, minBit 0, minWin=25, winSum=412
7833 23:49:23.669959 TX Vref=26, minBit 1, minWin=25, winSum=416
7834 23:49:23.673106 TX Vref=28, minBit 7, minWin=25, winSum=422
7835 23:49:23.676852 TX Vref=30, minBit 8, minWin=24, winSum=417
7836 23:49:23.679824 TX Vref=32, minBit 8, minWin=24, winSum=412
7837 23:49:23.683278 TX Vref=34, minBit 8, minWin=23, winSum=398
7838 23:49:23.689698 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 28
7839 23:49:23.689768
7840 23:49:23.692755 Final TX Range 0 Vref 28
7841 23:49:23.692847
7842 23:49:23.692932 ==
7843 23:49:23.696000 Dram Type= 6, Freq= 0, CH_0, rank 1
7844 23:49:23.699407 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7845 23:49:23.699475 ==
7846 23:49:23.699536
7847 23:49:23.699591
7848 23:49:23.702616 TX Vref Scan disable
7849 23:49:23.709457 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7850 23:49:23.709530 == TX Byte 0 ==
7851 23:49:23.712834 u2DelayCellOfst[0]=14 cells (4 PI)
7852 23:49:23.716250 u2DelayCellOfst[1]=18 cells (5 PI)
7853 23:49:23.719414 u2DelayCellOfst[2]=14 cells (4 PI)
7854 23:49:23.722717 u2DelayCellOfst[3]=14 cells (4 PI)
7855 23:49:23.725776 u2DelayCellOfst[4]=7 cells (2 PI)
7856 23:49:23.729697 u2DelayCellOfst[5]=0 cells (0 PI)
7857 23:49:23.732450 u2DelayCellOfst[6]=18 cells (5 PI)
7858 23:49:23.735999 u2DelayCellOfst[7]=18 cells (5 PI)
7859 23:49:23.738991 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7860 23:49:23.742442 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7861 23:49:23.745829 == TX Byte 1 ==
7862 23:49:23.749236 u2DelayCellOfst[8]=3 cells (1 PI)
7863 23:49:23.749346 u2DelayCellOfst[9]=0 cells (0 PI)
7864 23:49:23.752489 u2DelayCellOfst[10]=10 cells (3 PI)
7865 23:49:23.755556 u2DelayCellOfst[11]=7 cells (2 PI)
7866 23:49:23.759017 u2DelayCellOfst[12]=14 cells (4 PI)
7867 23:49:23.762681 u2DelayCellOfst[13]=14 cells (4 PI)
7868 23:49:23.765983 u2DelayCellOfst[14]=18 cells (5 PI)
7869 23:49:23.769195 u2DelayCellOfst[15]=14 cells (4 PI)
7870 23:49:23.772643 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7871 23:49:23.779251 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7872 23:49:23.779350 DramC Write-DBI on
7873 23:49:23.779441 ==
7874 23:49:23.782425 Dram Type= 6, Freq= 0, CH_0, rank 1
7875 23:49:23.788698 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7876 23:49:23.788793 ==
7877 23:49:23.788880
7878 23:49:23.788966
7879 23:49:23.789050 TX Vref Scan disable
7880 23:49:23.793134 == TX Byte 0 ==
7881 23:49:23.796461 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7882 23:49:23.799454 == TX Byte 1 ==
7883 23:49:23.802446 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7884 23:49:23.806041 DramC Write-DBI off
7885 23:49:23.806134
7886 23:49:23.806230 [DATLAT]
7887 23:49:23.806319 Freq=1600, CH0 RK1
7888 23:49:23.806404
7889 23:49:23.809076 DATLAT Default: 0xe
7890 23:49:23.812579 0, 0xFFFF, sum = 0
7891 23:49:23.812656 1, 0xFFFF, sum = 0
7892 23:49:23.816051 2, 0xFFFF, sum = 0
7893 23:49:23.816152 3, 0xFFFF, sum = 0
7894 23:49:23.819103 4, 0xFFFF, sum = 0
7895 23:49:23.819204 5, 0xFFFF, sum = 0
7896 23:49:23.822504 6, 0xFFFF, sum = 0
7897 23:49:23.822605 7, 0xFFFF, sum = 0
7898 23:49:23.826085 8, 0xFFFF, sum = 0
7899 23:49:23.826190 9, 0xFFFF, sum = 0
7900 23:49:23.829147 10, 0xFFFF, sum = 0
7901 23:49:23.829253 11, 0xFFFF, sum = 0
7902 23:49:23.832804 12, 0x8FFF, sum = 0
7903 23:49:23.832904 13, 0x0, sum = 1
7904 23:49:23.835979 14, 0x0, sum = 2
7905 23:49:23.836081 15, 0x0, sum = 3
7906 23:49:23.839323 16, 0x0, sum = 4
7907 23:49:23.839426 best_step = 14
7908 23:49:23.839517
7909 23:49:23.839604 ==
7910 23:49:23.842340 Dram Type= 6, Freq= 0, CH_0, rank 1
7911 23:49:23.845901 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7912 23:49:23.849004 ==
7913 23:49:23.849105 RX Vref Scan: 0
7914 23:49:23.849194
7915 23:49:23.852330 RX Vref 0 -> 0, step: 1
7916 23:49:23.852409
7917 23:49:23.855890 RX Delay 11 -> 252, step: 4
7918 23:49:23.858790 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7919 23:49:23.862926 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7920 23:49:23.865496 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7921 23:49:23.872248 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7922 23:49:23.875667 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7923 23:49:23.879023 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7924 23:49:23.882393 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7925 23:49:23.885863 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7926 23:49:23.888986 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
7927 23:49:23.895649 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7928 23:49:23.898873 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7929 23:49:23.902486 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7930 23:49:23.905545 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7931 23:49:23.912152 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7932 23:49:23.915510 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7933 23:49:23.918665 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
7934 23:49:23.918766 ==
7935 23:49:23.921934 Dram Type= 6, Freq= 0, CH_0, rank 1
7936 23:49:23.925460 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7937 23:49:23.925581 ==
7938 23:49:23.928758 DQS Delay:
7939 23:49:23.928859 DQS0 = 0, DQS1 = 0
7940 23:49:23.931934 DQM Delay:
7941 23:49:23.932037 DQM0 = 128, DQM1 = 121
7942 23:49:23.932136 DQ Delay:
7943 23:49:23.938526 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7944 23:49:23.941961 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7945 23:49:23.945384 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
7946 23:49:23.948560 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132
7947 23:49:23.948636
7948 23:49:23.948716
7949 23:49:23.948813
7950 23:49:23.951959 [DramC_TX_OE_Calibration] TA2
7951 23:49:23.955360 Original DQ_B0 (3 6) =30, OEN = 27
7952 23:49:23.958856 Original DQ_B1 (3 6) =30, OEN = 27
7953 23:49:23.958939 24, 0x0, End_B0=24 End_B1=24
7954 23:49:23.961840 25, 0x0, End_B0=25 End_B1=25
7955 23:49:23.965645 26, 0x0, End_B0=26 End_B1=26
7956 23:49:23.968620 27, 0x0, End_B0=27 End_B1=27
7957 23:49:23.971904 28, 0x0, End_B0=28 End_B1=28
7958 23:49:23.972009 29, 0x0, End_B0=29 End_B1=29
7959 23:49:23.974993 30, 0x0, End_B0=30 End_B1=30
7960 23:49:23.978605 31, 0x5151, End_B0=30 End_B1=30
7961 23:49:23.982323 Byte0 end_step=30 best_step=27
7962 23:49:23.985219 Byte1 end_step=30 best_step=27
7963 23:49:23.988500 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 23:49:23.988598 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 23:49:23.988685
7966 23:49:23.988773
7967 23:49:23.998151 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7968 23:49:24.001507 CH0 RK1: MR19=303, MR18=2121
7969 23:49:24.004903 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7970 23:49:24.008658 [RxdqsGatingPostProcess] freq 1600
7971 23:49:24.014935 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7972 23:49:24.018449 Pre-setting of DQS Precalculation
7973 23:49:24.021632 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7974 23:49:24.025050 ==
7975 23:49:24.028102 Dram Type= 6, Freq= 0, CH_1, rank 0
7976 23:49:24.031671 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7977 23:49:24.031768 ==
7978 23:49:24.035017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7979 23:49:24.041653 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7980 23:49:24.044869 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7981 23:49:24.051861 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7982 23:49:24.058777 [CA 0] Center 41 (11~71) winsize 61
7983 23:49:24.062010 [CA 1] Center 40 (10~70) winsize 61
7984 23:49:24.065511 [CA 2] Center 36 (6~66) winsize 61
7985 23:49:24.068779 [CA 3] Center 35 (6~65) winsize 60
7986 23:49:24.072087 [CA 4] Center 33 (3~63) winsize 61
7987 23:49:24.075493 [CA 5] Center 33 (4~63) winsize 60
7988 23:49:24.075565
7989 23:49:24.078868 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7990 23:49:24.078942
7991 23:49:24.082003 [CATrainingPosCal] consider 1 rank data
7992 23:49:24.085200 u2DelayCellTimex100 = 271/100 ps
7993 23:49:24.088513 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
7994 23:49:24.095440 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
7995 23:49:24.098637 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
7996 23:49:24.101865 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
7997 23:49:24.105236 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
7998 23:49:24.108368 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
7999 23:49:24.108443
8000 23:49:24.111892 CA PerBit enable=1, Macro0, CA PI delay=33
8001 23:49:24.111968
8002 23:49:24.115152 [CBTSetCACLKResult] CA Dly = 33
8003 23:49:24.118541 CS Dly: 9 (0~40)
8004 23:49:24.121853 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8005 23:49:24.125133 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8006 23:49:24.125234 ==
8007 23:49:24.128379 Dram Type= 6, Freq= 0, CH_1, rank 1
8008 23:49:24.131648 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8009 23:49:24.134824 ==
8010 23:49:24.138227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8011 23:49:24.141885 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8012 23:49:24.148272 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8013 23:49:24.154956 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8014 23:49:24.161252 [CA 0] Center 41 (11~71) winsize 61
8015 23:49:24.164666 [CA 1] Center 40 (10~71) winsize 62
8016 23:49:24.167970 [CA 2] Center 36 (7~66) winsize 60
8017 23:49:24.171301 [CA 3] Center 36 (7~65) winsize 59
8018 23:49:24.175091 [CA 4] Center 34 (4~64) winsize 61
8019 23:49:24.177868 [CA 5] Center 34 (4~64) winsize 61
8020 23:49:24.177952
8021 23:49:24.181178 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8022 23:49:24.181279
8023 23:49:24.184442 [CATrainingPosCal] consider 2 rank data
8024 23:49:24.187847 u2DelayCellTimex100 = 271/100 ps
8025 23:49:24.191332 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8026 23:49:24.197977 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8027 23:49:24.201070 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8028 23:49:24.204203 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8029 23:49:24.207492 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8030 23:49:24.210911 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8031 23:49:24.210983
8032 23:49:24.214402 CA PerBit enable=1, Macro0, CA PI delay=33
8033 23:49:24.214480
8034 23:49:24.217703 [CBTSetCACLKResult] CA Dly = 33
8035 23:49:24.220897 CS Dly: 9 (0~40)
8036 23:49:24.224174 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8037 23:49:24.227746 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8038 23:49:24.227844
8039 23:49:24.230841 ----->DramcWriteLeveling(PI) begin...
8040 23:49:24.230939 ==
8041 23:49:24.234144 Dram Type= 6, Freq= 0, CH_1, rank 0
8042 23:49:24.240805 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8043 23:49:24.240884 ==
8044 23:49:24.243910 Write leveling (Byte 0): 23 => 23
8045 23:49:24.247639 Write leveling (Byte 1): 22 => 22
8046 23:49:24.247709 DramcWriteLeveling(PI) end<-----
8047 23:49:24.247771
8048 23:49:24.250746 ==
8049 23:49:24.250814 Dram Type= 6, Freq= 0, CH_1, rank 0
8050 23:49:24.257723 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8051 23:49:24.257803 ==
8052 23:49:24.260540 [Gating] SW mode calibration
8053 23:49:24.267175 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8054 23:49:24.270626 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8055 23:49:24.277318 0 12 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8056 23:49:24.280515 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 23:49:24.283678 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 23:49:24.290515 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 23:49:24.294073 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 23:49:24.297052 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 23:49:24.304144 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8062 23:49:24.307187 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8063 23:49:24.310315 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (1 0)
8064 23:49:24.316873 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8065 23:49:24.320556 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 23:49:24.323425 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 23:49:24.330455 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 23:49:24.333453 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 23:49:24.336509 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8070 23:49:24.343658 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8071 23:49:24.346419 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8072 23:49:24.349710 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 23:49:24.356542 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 23:49:24.359945 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 23:49:24.363865 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 23:49:24.369796 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 23:49:24.373368 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8078 23:49:24.376427 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8079 23:49:24.382972 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8080 23:49:24.386487 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 23:49:24.389780 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 23:49:24.396548 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 23:49:24.399369 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 23:49:24.402767 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 23:49:24.409462 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 23:49:24.412496 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 23:49:24.416123 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 23:49:24.422673 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 23:49:24.425790 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:49:24.428991 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:49:24.435922 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:49:24.439296 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 23:49:24.442230 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 23:49:24.449143 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8095 23:49:24.452197 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 23:49:24.455940 Total UI for P1: 0, mck2ui 16
8097 23:49:24.458843 best dqsien dly found for B0: ( 1, 0, 28)
8098 23:49:24.462118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 23:49:24.465396 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 23:49:24.469013 Total UI for P1: 0, mck2ui 16
8101 23:49:24.472430 best dqsien dly found for B1: ( 1, 1, 0)
8102 23:49:24.475788 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8103 23:49:24.482559 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8104 23:49:24.482637
8105 23:49:24.485992 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8106 23:49:24.488792 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8107 23:49:24.492068 [Gating] SW calibration Done
8108 23:49:24.492169 ==
8109 23:49:24.495399 Dram Type= 6, Freq= 0, CH_1, rank 0
8110 23:49:24.499604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8111 23:49:24.499705 ==
8112 23:49:24.499805 RX Vref Scan: 0
8113 23:49:24.502117
8114 23:49:24.502218 RX Vref 0 -> 0, step: 1
8115 23:49:24.502315
8116 23:49:24.505662 RX Delay 0 -> 252, step: 8
8117 23:49:24.508503 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8118 23:49:24.511978 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8119 23:49:24.518487 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8120 23:49:24.521860 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8121 23:49:24.524962 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8122 23:49:24.528405 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8123 23:49:24.531594 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8124 23:49:24.538242 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8125 23:49:24.541542 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8126 23:49:24.545085 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8127 23:49:24.548331 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8128 23:49:24.551601 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8129 23:49:24.558142 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8130 23:49:24.561852 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8131 23:49:24.565017 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8132 23:49:24.568375 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8133 23:49:24.568455 ==
8134 23:49:24.571866 Dram Type= 6, Freq= 0, CH_1, rank 0
8135 23:49:24.578443 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8136 23:49:24.578540 ==
8137 23:49:24.578623 DQS Delay:
8138 23:49:24.581505 DQS0 = 0, DQS1 = 0
8139 23:49:24.581586 DQM Delay:
8140 23:49:24.584899 DQM0 = 130, DQM1 = 125
8141 23:49:24.584999 DQ Delay:
8142 23:49:24.588219 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8143 23:49:24.591397 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8144 23:49:24.594550 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8145 23:49:24.597776 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8146 23:49:24.597854
8147 23:49:24.597951
8148 23:49:24.598046 ==
8149 23:49:24.601489 Dram Type= 6, Freq= 0, CH_1, rank 0
8150 23:49:24.607914 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8151 23:49:24.608016 ==
8152 23:49:24.608114
8153 23:49:24.608209
8154 23:49:24.608307 TX Vref Scan disable
8155 23:49:24.611080 == TX Byte 0 ==
8156 23:49:24.614425 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8157 23:49:24.621100 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8158 23:49:24.621200 == TX Byte 1 ==
8159 23:49:24.624359 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8160 23:49:24.630978 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8161 23:49:24.631055 ==
8162 23:49:24.634036 Dram Type= 6, Freq= 0, CH_1, rank 0
8163 23:49:24.637557 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8164 23:49:24.637634 ==
8165 23:49:24.649842
8166 23:49:24.652630 TX Vref early break, caculate TX vref
8167 23:49:24.656102 TX Vref=16, minBit 3, minWin=21, winSum=366
8168 23:49:24.659332 TX Vref=18, minBit 0, minWin=21, winSum=376
8169 23:49:24.662782 TX Vref=20, minBit 3, minWin=22, winSum=383
8170 23:49:24.666064 TX Vref=22, minBit 3, minWin=23, winSum=395
8171 23:49:24.669313 TX Vref=24, minBit 0, minWin=24, winSum=404
8172 23:49:24.676167 TX Vref=26, minBit 3, minWin=24, winSum=409
8173 23:49:24.679102 TX Vref=28, minBit 0, minWin=25, winSum=410
8174 23:49:24.682619 TX Vref=30, minBit 0, minWin=25, winSum=409
8175 23:49:24.685784 TX Vref=32, minBit 3, minWin=23, winSum=398
8176 23:49:24.689191 TX Vref=34, minBit 1, minWin=23, winSum=386
8177 23:49:24.696063 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8178 23:49:24.696163
8179 23:49:24.699327 Final TX Range 0 Vref 28
8180 23:49:24.699400
8181 23:49:24.699464 ==
8182 23:49:24.702351 Dram Type= 6, Freq= 0, CH_1, rank 0
8183 23:49:24.705753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8184 23:49:24.705826 ==
8185 23:49:24.705886
8186 23:49:24.705946
8187 23:49:24.709279 TX Vref Scan disable
8188 23:49:24.715762 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8189 23:49:24.715835 == TX Byte 0 ==
8190 23:49:24.719012 u2DelayCellOfst[0]=14 cells (4 PI)
8191 23:49:24.722162 u2DelayCellOfst[1]=10 cells (3 PI)
8192 23:49:24.725623 u2DelayCellOfst[2]=0 cells (0 PI)
8193 23:49:24.728932 u2DelayCellOfst[3]=7 cells (2 PI)
8194 23:49:24.732365 u2DelayCellOfst[4]=7 cells (2 PI)
8195 23:49:24.735578 u2DelayCellOfst[5]=14 cells (4 PI)
8196 23:49:24.738865 u2DelayCellOfst[6]=14 cells (4 PI)
8197 23:49:24.738935 u2DelayCellOfst[7]=7 cells (2 PI)
8198 23:49:24.745559 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8199 23:49:24.748952 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8200 23:49:24.749026 == TX Byte 1 ==
8201 23:49:24.752297 u2DelayCellOfst[8]=0 cells (0 PI)
8202 23:49:24.755425 u2DelayCellOfst[9]=7 cells (2 PI)
8203 23:49:24.758545 u2DelayCellOfst[10]=10 cells (3 PI)
8204 23:49:24.761880 u2DelayCellOfst[11]=3 cells (1 PI)
8205 23:49:24.765204 u2DelayCellOfst[12]=18 cells (5 PI)
8206 23:49:24.768700 u2DelayCellOfst[13]=18 cells (5 PI)
8207 23:49:24.772057 u2DelayCellOfst[14]=21 cells (6 PI)
8208 23:49:24.775433 u2DelayCellOfst[15]=21 cells (6 PI)
8209 23:49:24.778669 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8210 23:49:24.784953 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8211 23:49:24.785023 DramC Write-DBI on
8212 23:49:24.785083 ==
8213 23:49:24.788240 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 23:49:24.795411 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 23:49:24.795512 ==
8216 23:49:24.795600
8217 23:49:24.795685
8218 23:49:24.795764 TX Vref Scan disable
8219 23:49:24.798495 == TX Byte 0 ==
8220 23:49:24.802431 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8221 23:49:24.805452 == TX Byte 1 ==
8222 23:49:24.808718 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8223 23:49:24.808788 DramC Write-DBI off
8224 23:49:24.811789
8225 23:49:24.811874 [DATLAT]
8226 23:49:24.811933 Freq=1600, CH1 RK0
8227 23:49:24.811988
8228 23:49:24.815286 DATLAT Default: 0xf
8229 23:49:24.815359 0, 0xFFFF, sum = 0
8230 23:49:24.818363 1, 0xFFFF, sum = 0
8231 23:49:24.821911 2, 0xFFFF, sum = 0
8232 23:49:24.822007 3, 0xFFFF, sum = 0
8233 23:49:24.825419 4, 0xFFFF, sum = 0
8234 23:49:24.825497 5, 0xFFFF, sum = 0
8235 23:49:24.828920 6, 0xFFFF, sum = 0
8236 23:49:24.829015 7, 0xFFFF, sum = 0
8237 23:49:24.832026 8, 0xFFFF, sum = 0
8238 23:49:24.832120 9, 0xFFFF, sum = 0
8239 23:49:24.835232 10, 0xFFFF, sum = 0
8240 23:49:24.835325 11, 0xFFFF, sum = 0
8241 23:49:24.838324 12, 0x8FFF, sum = 0
8242 23:49:24.838391 13, 0x0, sum = 1
8243 23:49:24.841821 14, 0x0, sum = 2
8244 23:49:24.841888 15, 0x0, sum = 3
8245 23:49:24.845062 16, 0x0, sum = 4
8246 23:49:24.845133 best_step = 14
8247 23:49:24.845190
8248 23:49:24.845244 ==
8249 23:49:24.848303 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 23:49:24.851940 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8251 23:49:24.855215 ==
8252 23:49:24.855283 RX Vref Scan: 1
8253 23:49:24.855342
8254 23:49:24.858216 Set Vref Range= 24 -> 127
8255 23:49:24.858300
8256 23:49:24.858375 RX Vref 24 -> 127, step: 1
8257 23:49:24.861863
8258 23:49:24.861932 RX Delay 3 -> 252, step: 4
8259 23:49:24.861990
8260 23:49:24.864880 Set Vref, RX VrefLevel [Byte0]: 24
8261 23:49:24.868029 [Byte1]: 24
8262 23:49:24.871751
8263 23:49:24.871848 Set Vref, RX VrefLevel [Byte0]: 25
8264 23:49:24.875231 [Byte1]: 25
8265 23:49:24.879664
8266 23:49:24.879764 Set Vref, RX VrefLevel [Byte0]: 26
8267 23:49:24.883151 [Byte1]: 26
8268 23:49:24.887205
8269 23:49:24.887276 Set Vref, RX VrefLevel [Byte0]: 27
8270 23:49:24.890411 [Byte1]: 27
8271 23:49:24.894804
8272 23:49:24.894906 Set Vref, RX VrefLevel [Byte0]: 28
8273 23:49:24.898410 [Byte1]: 28
8274 23:49:24.902632
8275 23:49:24.902702 Set Vref, RX VrefLevel [Byte0]: 29
8276 23:49:24.905901 [Byte1]: 29
8277 23:49:24.910193
8278 23:49:24.910261 Set Vref, RX VrefLevel [Byte0]: 30
8279 23:49:24.913554 [Byte1]: 30
8280 23:49:24.918081
8281 23:49:24.918150 Set Vref, RX VrefLevel [Byte0]: 31
8282 23:49:24.921602 [Byte1]: 31
8283 23:49:24.925549
8284 23:49:24.925629 Set Vref, RX VrefLevel [Byte0]: 32
8285 23:49:24.928572 [Byte1]: 32
8286 23:49:24.933066
8287 23:49:24.933159 Set Vref, RX VrefLevel [Byte0]: 33
8288 23:49:24.936473 [Byte1]: 33
8289 23:49:24.940631
8290 23:49:24.940716 Set Vref, RX VrefLevel [Byte0]: 34
8291 23:49:24.943991 [Byte1]: 34
8292 23:49:24.948492
8293 23:49:24.948562 Set Vref, RX VrefLevel [Byte0]: 35
8294 23:49:24.951983 [Byte1]: 35
8295 23:49:24.956483
8296 23:49:24.956553 Set Vref, RX VrefLevel [Byte0]: 36
8297 23:49:24.959189 [Byte1]: 36
8298 23:49:24.963613
8299 23:49:24.963682 Set Vref, RX VrefLevel [Byte0]: 37
8300 23:49:24.967318 [Byte1]: 37
8301 23:49:24.971343
8302 23:49:24.971441 Set Vref, RX VrefLevel [Byte0]: 38
8303 23:49:24.974618 [Byte1]: 38
8304 23:49:24.978953
8305 23:49:24.979056 Set Vref, RX VrefLevel [Byte0]: 39
8306 23:49:24.982314 [Byte1]: 39
8307 23:49:24.986788
8308 23:49:24.986857 Set Vref, RX VrefLevel [Byte0]: 40
8309 23:49:24.990142 [Byte1]: 40
8310 23:49:24.994733
8311 23:49:24.994843 Set Vref, RX VrefLevel [Byte0]: 41
8312 23:49:24.997795 [Byte1]: 41
8313 23:49:25.001973
8314 23:49:25.002042 Set Vref, RX VrefLevel [Byte0]: 42
8315 23:49:25.005703 [Byte1]: 42
8316 23:49:25.009736
8317 23:49:25.009835 Set Vref, RX VrefLevel [Byte0]: 43
8318 23:49:25.012863 [Byte1]: 43
8319 23:49:25.017512
8320 23:49:25.017581 Set Vref, RX VrefLevel [Byte0]: 44
8321 23:49:25.020590 [Byte1]: 44
8322 23:49:25.024741
8323 23:49:25.024843 Set Vref, RX VrefLevel [Byte0]: 45
8324 23:49:25.028128 [Byte1]: 45
8325 23:49:25.032558
8326 23:49:25.032761 Set Vref, RX VrefLevel [Byte0]: 46
8327 23:49:25.035745 [Byte1]: 46
8328 23:49:25.040465
8329 23:49:25.040540 Set Vref, RX VrefLevel [Byte0]: 47
8330 23:49:25.043787 [Byte1]: 47
8331 23:49:25.047945
8332 23:49:25.048043 Set Vref, RX VrefLevel [Byte0]: 48
8333 23:49:25.051316 [Byte1]: 48
8334 23:49:25.056021
8335 23:49:25.056120 Set Vref, RX VrefLevel [Byte0]: 49
8336 23:49:25.058804 [Byte1]: 49
8337 23:49:25.063171
8338 23:49:25.063270 Set Vref, RX VrefLevel [Byte0]: 50
8339 23:49:25.066474 [Byte1]: 50
8340 23:49:25.070924
8341 23:49:25.071021 Set Vref, RX VrefLevel [Byte0]: 51
8342 23:49:25.074041 [Byte1]: 51
8343 23:49:25.078408
8344 23:49:25.078513 Set Vref, RX VrefLevel [Byte0]: 52
8345 23:49:25.081867 [Byte1]: 52
8346 23:49:25.086149
8347 23:49:25.086222 Set Vref, RX VrefLevel [Byte0]: 53
8348 23:49:25.089424 [Byte1]: 53
8349 23:49:25.093787
8350 23:49:25.093862 Set Vref, RX VrefLevel [Byte0]: 54
8351 23:49:25.097522 [Byte1]: 54
8352 23:49:25.101572
8353 23:49:25.101646 Set Vref, RX VrefLevel [Byte0]: 55
8354 23:49:25.105001 [Byte1]: 55
8355 23:49:25.109238
8356 23:49:25.109334 Set Vref, RX VrefLevel [Byte0]: 56
8357 23:49:25.112517 [Byte1]: 56
8358 23:49:25.116676
8359 23:49:25.116780 Set Vref, RX VrefLevel [Byte0]: 57
8360 23:49:25.119963 [Byte1]: 57
8361 23:49:25.124682
8362 23:49:25.124791 Set Vref, RX VrefLevel [Byte0]: 58
8363 23:49:25.127633 [Byte1]: 58
8364 23:49:25.131873
8365 23:49:25.131978 Set Vref, RX VrefLevel [Byte0]: 59
8366 23:49:25.135114 [Byte1]: 59
8367 23:49:25.139673
8368 23:49:25.139773 Set Vref, RX VrefLevel [Byte0]: 60
8369 23:49:25.143104 [Byte1]: 60
8370 23:49:25.147426
8371 23:49:25.147528 Set Vref, RX VrefLevel [Byte0]: 61
8372 23:49:25.150662 [Byte1]: 61
8373 23:49:25.154973
8374 23:49:25.155119 Set Vref, RX VrefLevel [Byte0]: 62
8375 23:49:25.158285 [Byte1]: 62
8376 23:49:25.162814
8377 23:49:25.162913 Set Vref, RX VrefLevel [Byte0]: 63
8378 23:49:25.166136 [Byte1]: 63
8379 23:49:25.170555
8380 23:49:25.170653 Set Vref, RX VrefLevel [Byte0]: 64
8381 23:49:25.173585 [Byte1]: 64
8382 23:49:25.177925
8383 23:49:25.178023 Set Vref, RX VrefLevel [Byte0]: 65
8384 23:49:25.181320 [Byte1]: 65
8385 23:49:25.185956
8386 23:49:25.186036 Set Vref, RX VrefLevel [Byte0]: 66
8387 23:49:25.189063 [Byte1]: 66
8388 23:49:25.193352
8389 23:49:25.193425 Set Vref, RX VrefLevel [Byte0]: 67
8390 23:49:25.196437 [Byte1]: 67
8391 23:49:25.201033
8392 23:49:25.201136 Set Vref, RX VrefLevel [Byte0]: 68
8393 23:49:25.204026 [Byte1]: 68
8394 23:49:25.208413
8395 23:49:25.208485 Set Vref, RX VrefLevel [Byte0]: 69
8396 23:49:25.211764 [Byte1]: 69
8397 23:49:25.216118
8398 23:49:25.216218 Set Vref, RX VrefLevel [Byte0]: 70
8399 23:49:25.219383 [Byte1]: 70
8400 23:49:25.223867
8401 23:49:25.223938 Set Vref, RX VrefLevel [Byte0]: 71
8402 23:49:25.226960 [Byte1]: 71
8403 23:49:25.231972
8404 23:49:25.232077 Set Vref, RX VrefLevel [Byte0]: 72
8405 23:49:25.234829 [Byte1]: 72
8406 23:49:25.239368
8407 23:49:25.239468 Set Vref, RX VrefLevel [Byte0]: 73
8408 23:49:25.242645 [Byte1]: 73
8409 23:49:25.247104
8410 23:49:25.247219 Set Vref, RX VrefLevel [Byte0]: 74
8411 23:49:25.250141 [Byte1]: 74
8412 23:49:25.254649
8413 23:49:25.254722 Set Vref, RX VrefLevel [Byte0]: 75
8414 23:49:25.258044 [Byte1]: 75
8415 23:49:25.262001
8416 23:49:25.262106 Set Vref, RX VrefLevel [Byte0]: 76
8417 23:49:25.265409 [Byte1]: 76
8418 23:49:25.269995
8419 23:49:25.270065 Set Vref, RX VrefLevel [Byte0]: 77
8420 23:49:25.273251 [Byte1]: 77
8421 23:49:25.277444
8422 23:49:25.277543 Final RX Vref Byte 0 = 62 to rank0
8423 23:49:25.280651 Final RX Vref Byte 1 = 52 to rank0
8424 23:49:25.284097 Final RX Vref Byte 0 = 62 to rank1
8425 23:49:25.287343 Final RX Vref Byte 1 = 52 to rank1==
8426 23:49:25.290902 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 23:49:25.297500 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8428 23:49:25.297573 ==
8429 23:49:25.297638 DQS Delay:
8430 23:49:25.297706 DQS0 = 0, DQS1 = 0
8431 23:49:25.300824 DQM Delay:
8432 23:49:25.300924 DQM0 = 129, DQM1 = 122
8433 23:49:25.303769 DQ Delay:
8434 23:49:25.307332 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =128
8435 23:49:25.310312 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8436 23:49:25.313610 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8437 23:49:25.317196 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =130
8438 23:49:25.317301
8439 23:49:25.317431
8440 23:49:25.317491
8441 23:49:25.320229 [DramC_TX_OE_Calibration] TA2
8442 23:49:25.323575 Original DQ_B0 (3 6) =30, OEN = 27
8443 23:49:25.327167 Original DQ_B1 (3 6) =30, OEN = 27
8444 23:49:25.330513 24, 0x0, End_B0=24 End_B1=24
8445 23:49:25.333559 25, 0x0, End_B0=25 End_B1=25
8446 23:49:25.333630 26, 0x0, End_B0=26 End_B1=26
8447 23:49:25.336877 27, 0x0, End_B0=27 End_B1=27
8448 23:49:25.340023 28, 0x0, End_B0=28 End_B1=28
8449 23:49:25.343278 29, 0x0, End_B0=29 End_B1=29
8450 23:49:25.343378 30, 0x0, End_B0=30 End_B1=30
8451 23:49:25.346430 31, 0x4141, End_B0=30 End_B1=30
8452 23:49:25.349946 Byte0 end_step=30 best_step=27
8453 23:49:25.353273 Byte1 end_step=30 best_step=27
8454 23:49:25.356638 Byte0 TX OE(2T, 0.5T) = (3, 3)
8455 23:49:25.359707 Byte1 TX OE(2T, 0.5T) = (3, 3)
8456 23:49:25.359802
8457 23:49:25.359894
8458 23:49:25.366442 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8459 23:49:25.369865 CH1 RK0: MR19=303, MR18=2626
8460 23:49:25.376612 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8461 23:49:25.376711
8462 23:49:25.379529 ----->DramcWriteLeveling(PI) begin...
8463 23:49:25.379624 ==
8464 23:49:25.382922 Dram Type= 6, Freq= 0, CH_1, rank 1
8465 23:49:25.386373 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8466 23:49:25.386469 ==
8467 23:49:25.389467 Write leveling (Byte 0): 21 => 21
8468 23:49:25.392827 Write leveling (Byte 1): 19 => 19
8469 23:49:25.396128 DramcWriteLeveling(PI) end<-----
8470 23:49:25.396222
8471 23:49:25.396317 ==
8472 23:49:25.399438 Dram Type= 6, Freq= 0, CH_1, rank 1
8473 23:49:25.403418 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8474 23:49:25.406191 ==
8475 23:49:25.406261 [Gating] SW mode calibration
8476 23:49:25.416418 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8477 23:49:25.419418 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8478 23:49:25.422782 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8479 23:49:25.429269 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 23:49:25.432667 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 23:49:25.436321 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8482 23:49:25.442712 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 23:49:25.446056 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8484 23:49:25.448873 0 12 24 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8485 23:49:25.455535 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8486 23:49:25.459028 0 13 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8487 23:49:25.462351 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 23:49:25.468961 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 23:49:25.472152 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 23:49:25.475422 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 23:49:25.482200 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8492 23:49:25.485957 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8493 23:49:25.488822 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8494 23:49:25.495193 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8495 23:49:25.498842 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 23:49:25.501921 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 23:49:25.508284 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 23:49:25.512025 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 23:49:25.515101 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 23:49:25.521664 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8501 23:49:25.524863 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8502 23:49:25.528640 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8503 23:49:25.535051 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 23:49:25.538555 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 23:49:25.541779 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 23:49:25.548326 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 23:49:25.551531 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 23:49:25.555123 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 23:49:25.561599 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 23:49:25.564850 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 23:49:25.568205 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 23:49:25.574410 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 23:49:25.577952 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 23:49:25.581174 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 23:49:25.587994 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8516 23:49:25.591033 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8517 23:49:25.594445 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8518 23:49:25.597697 Total UI for P1: 0, mck2ui 16
8519 23:49:25.600883 best dqsien dly found for B0: ( 1, 0, 22)
8520 23:49:25.607760 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8521 23:49:25.611004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8522 23:49:25.614486 Total UI for P1: 0, mck2ui 16
8523 23:49:25.617483 best dqsien dly found for B1: ( 1, 0, 30)
8524 23:49:25.620891 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8525 23:49:25.624311 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8526 23:49:25.624404
8527 23:49:25.627547 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8528 23:49:25.631086 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8529 23:49:25.634225 [Gating] SW calibration Done
8530 23:49:25.634296 ==
8531 23:49:25.637537 Dram Type= 6, Freq= 0, CH_1, rank 1
8532 23:49:25.640913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8533 23:49:25.641010 ==
8534 23:49:25.644159 RX Vref Scan: 0
8535 23:49:25.644253
8536 23:49:25.647672 RX Vref 0 -> 0, step: 1
8537 23:49:25.647766
8538 23:49:25.647855 RX Delay 0 -> 252, step: 8
8539 23:49:25.654190 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8540 23:49:25.657406 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8541 23:49:25.660667 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8542 23:49:25.664329 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8543 23:49:25.667151 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8544 23:49:25.673959 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8545 23:49:25.677486 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8546 23:49:25.681089 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8547 23:49:25.683876 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8548 23:49:25.687080 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8549 23:49:25.693873 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8550 23:49:25.697441 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8551 23:49:25.700758 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8552 23:49:25.703558 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8553 23:49:25.710314 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8554 23:49:25.713698 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8555 23:49:25.713794 ==
8556 23:49:25.716989 Dram Type= 6, Freq= 0, CH_1, rank 1
8557 23:49:25.720387 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8558 23:49:25.720482 ==
8559 23:49:25.723733 DQS Delay:
8560 23:49:25.723874 DQS0 = 0, DQS1 = 0
8561 23:49:25.723960 DQM Delay:
8562 23:49:25.726706 DQM0 = 131, DQM1 = 124
8563 23:49:25.726825 DQ Delay:
8564 23:49:25.730387 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8565 23:49:25.733629 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8566 23:49:25.736990 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8567 23:49:25.743303 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8568 23:49:25.743401
8569 23:49:25.743491
8570 23:49:25.743575 ==
8571 23:49:25.746778 Dram Type= 6, Freq= 0, CH_1, rank 1
8572 23:49:25.750207 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8573 23:49:25.750274 ==
8574 23:49:25.750331
8575 23:49:25.750386
8576 23:49:25.753143 TX Vref Scan disable
8577 23:49:25.753209 == TX Byte 0 ==
8578 23:49:25.759809 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8579 23:49:25.763324 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8580 23:49:25.763396 == TX Byte 1 ==
8581 23:49:25.770244 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8582 23:49:25.773077 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8583 23:49:25.773148 ==
8584 23:49:25.776884 Dram Type= 6, Freq= 0, CH_1, rank 1
8585 23:49:25.779595 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8586 23:49:25.779691 ==
8587 23:49:25.794461
8588 23:49:25.797672 TX Vref early break, caculate TX vref
8589 23:49:25.800950 TX Vref=16, minBit 4, minWin=22, winSum=385
8590 23:49:25.804413 TX Vref=18, minBit 1, minWin=23, winSum=395
8591 23:49:25.808222 TX Vref=20, minBit 3, minWin=23, winSum=402
8592 23:49:25.811118 TX Vref=22, minBit 0, minWin=24, winSum=407
8593 23:49:25.814363 TX Vref=24, minBit 0, minWin=24, winSum=410
8594 23:49:25.821180 TX Vref=26, minBit 1, minWin=25, winSum=421
8595 23:49:25.824348 TX Vref=28, minBit 0, minWin=25, winSum=421
8596 23:49:25.827605 TX Vref=30, minBit 0, minWin=25, winSum=419
8597 23:49:25.831154 TX Vref=32, minBit 0, minWin=24, winSum=410
8598 23:49:25.834580 TX Vref=34, minBit 0, minWin=23, winSum=405
8599 23:49:25.837621 TX Vref=36, minBit 0, minWin=23, winSum=395
8600 23:49:25.844203 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 26
8601 23:49:25.844300
8602 23:49:25.847355 Final TX Range 0 Vref 26
8603 23:49:25.847446
8604 23:49:25.847533 ==
8605 23:49:25.850869 Dram Type= 6, Freq= 0, CH_1, rank 1
8606 23:49:25.854388 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8607 23:49:25.854453 ==
8608 23:49:25.854511
8609 23:49:25.857699
8610 23:49:25.857770 TX Vref Scan disable
8611 23:49:25.863919 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8612 23:49:25.864011 == TX Byte 0 ==
8613 23:49:25.867285 u2DelayCellOfst[0]=18 cells (5 PI)
8614 23:49:25.870682 u2DelayCellOfst[1]=10 cells (3 PI)
8615 23:49:25.874194 u2DelayCellOfst[2]=0 cells (0 PI)
8616 23:49:25.877498 u2DelayCellOfst[3]=7 cells (2 PI)
8617 23:49:25.880800 u2DelayCellOfst[4]=10 cells (3 PI)
8618 23:49:25.883987 u2DelayCellOfst[5]=14 cells (4 PI)
8619 23:49:25.887160 u2DelayCellOfst[6]=18 cells (5 PI)
8620 23:49:25.890783 u2DelayCellOfst[7]=7 cells (2 PI)
8621 23:49:25.893841 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8622 23:49:25.896995 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8623 23:49:25.900730 == TX Byte 1 ==
8624 23:49:25.903879 u2DelayCellOfst[8]=0 cells (0 PI)
8625 23:49:25.907557 u2DelayCellOfst[9]=7 cells (2 PI)
8626 23:49:25.910599 u2DelayCellOfst[10]=10 cells (3 PI)
8627 23:49:25.910668 u2DelayCellOfst[11]=3 cells (1 PI)
8628 23:49:25.913705 u2DelayCellOfst[12]=10 cells (3 PI)
8629 23:49:25.916995 u2DelayCellOfst[13]=18 cells (5 PI)
8630 23:49:25.921929 u2DelayCellOfst[14]=18 cells (5 PI)
8631 23:49:25.923672 u2DelayCellOfst[15]=18 cells (5 PI)
8632 23:49:25.930440 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8633 23:49:25.933600 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8634 23:49:25.933670 DramC Write-DBI on
8635 23:49:25.933733 ==
8636 23:49:25.937119 Dram Type= 6, Freq= 0, CH_1, rank 1
8637 23:49:25.943660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8638 23:49:25.943757 ==
8639 23:49:25.943844
8640 23:49:25.943928
8641 23:49:25.944014 TX Vref Scan disable
8642 23:49:25.947686 == TX Byte 0 ==
8643 23:49:25.951011 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8644 23:49:25.954170 == TX Byte 1 ==
8645 23:49:25.957463 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8646 23:49:25.960857 DramC Write-DBI off
8647 23:49:25.960950
8648 23:49:25.961036 [DATLAT]
8649 23:49:25.961123 Freq=1600, CH1 RK1
8650 23:49:25.961206
8651 23:49:25.964514 DATLAT Default: 0xe
8652 23:49:25.964579 0, 0xFFFF, sum = 0
8653 23:49:25.968147 1, 0xFFFF, sum = 0
8654 23:49:25.968241 2, 0xFFFF, sum = 0
8655 23:49:25.971015 3, 0xFFFF, sum = 0
8656 23:49:25.974125 4, 0xFFFF, sum = 0
8657 23:49:25.974232 5, 0xFFFF, sum = 0
8658 23:49:25.977362 6, 0xFFFF, sum = 0
8659 23:49:25.977456 7, 0xFFFF, sum = 0
8660 23:49:25.980872 8, 0xFFFF, sum = 0
8661 23:49:25.980973 9, 0xFFFF, sum = 0
8662 23:49:25.984081 10, 0xFFFF, sum = 0
8663 23:49:25.984183 11, 0xFFFF, sum = 0
8664 23:49:25.987756 12, 0x8F7F, sum = 0
8665 23:49:25.987856 13, 0x0, sum = 1
8666 23:49:25.990860 14, 0x0, sum = 2
8667 23:49:25.990935 15, 0x0, sum = 3
8668 23:49:25.994971 16, 0x0, sum = 4
8669 23:49:25.995046 best_step = 14
8670 23:49:25.995107
8671 23:49:25.995168 ==
8672 23:49:25.997768 Dram Type= 6, Freq= 0, CH_1, rank 1
8673 23:49:26.000728 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8674 23:49:26.003983 ==
8675 23:49:26.004080 RX Vref Scan: 0
8676 23:49:26.004170
8677 23:49:26.007526 RX Vref 0 -> 0, step: 1
8678 23:49:26.007598
8679 23:49:26.007658 RX Delay 3 -> 252, step: 4
8680 23:49:26.014522 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8681 23:49:26.017914 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8682 23:49:26.021169 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8683 23:49:26.024578 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8684 23:49:26.028177 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8685 23:49:26.034479 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8686 23:49:26.037941 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8687 23:49:26.041236 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8688 23:49:26.044711 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8689 23:49:26.047640 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8690 23:49:26.054285 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8691 23:49:26.057534 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8692 23:49:26.061401 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8693 23:49:26.064212 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8694 23:49:26.071072 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8695 23:49:26.074430 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8696 23:49:26.074504 ==
8697 23:49:26.077669 Dram Type= 6, Freq= 0, CH_1, rank 1
8698 23:49:26.080827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8699 23:49:26.080904 ==
8700 23:49:26.084283 DQS Delay:
8701 23:49:26.084383 DQS0 = 0, DQS1 = 0
8702 23:49:26.084472 DQM Delay:
8703 23:49:26.087296 DQM0 = 127, DQM1 = 122
8704 23:49:26.087367 DQ Delay:
8705 23:49:26.090851 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =126
8706 23:49:26.094096 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8707 23:49:26.097434 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8708 23:49:26.103928 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8709 23:49:26.104029
8710 23:49:26.104117
8711 23:49:26.104202
8712 23:49:26.107276 [DramC_TX_OE_Calibration] TA2
8713 23:49:26.107347 Original DQ_B0 (3 6) =30, OEN = 27
8714 23:49:26.110699 Original DQ_B1 (3 6) =30, OEN = 27
8715 23:49:26.114404 24, 0x0, End_B0=24 End_B1=24
8716 23:49:26.117277 25, 0x0, End_B0=25 End_B1=25
8717 23:49:26.120620 26, 0x0, End_B0=26 End_B1=26
8718 23:49:26.123718 27, 0x0, End_B0=27 End_B1=27
8719 23:49:26.123817 28, 0x0, End_B0=28 End_B1=28
8720 23:49:26.127142 29, 0x0, End_B0=29 End_B1=29
8721 23:49:26.130568 30, 0x0, End_B0=30 End_B1=30
8722 23:49:26.133846 31, 0x4141, End_B0=30 End_B1=30
8723 23:49:26.137044 Byte0 end_step=30 best_step=27
8724 23:49:26.137139 Byte1 end_step=30 best_step=27
8725 23:49:26.140310 Byte0 TX OE(2T, 0.5T) = (3, 3)
8726 23:49:26.143870 Byte1 TX OE(2T, 0.5T) = (3, 3)
8727 23:49:26.143965
8728 23:49:26.144054
8729 23:49:26.153615 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8730 23:49:26.153712 CH1 RK1: MR19=303, MR18=1B1B
8731 23:49:26.160324 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8732 23:49:26.163506 [RxdqsGatingPostProcess] freq 1600
8733 23:49:26.170360 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8734 23:49:26.173795 Pre-setting of DQS Precalculation
8735 23:49:26.176805 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8736 23:49:26.186840 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8737 23:49:26.193403 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8738 23:49:26.193476
8739 23:49:26.193540
8740 23:49:26.196550 [Calibration Summary] 3200 Mbps
8741 23:49:26.196623 CH 0, Rank 0
8742 23:49:26.200147 SW Impedance : PASS
8743 23:49:26.200221 DUTY Scan : NO K
8744 23:49:26.203200 ZQ Calibration : PASS
8745 23:49:26.206855 Jitter Meter : NO K
8746 23:49:26.206928 CBT Training : PASS
8747 23:49:26.209956 Write leveling : PASS
8748 23:49:26.213526 RX DQS gating : PASS
8749 23:49:26.213623 RX DQ/DQS(RDDQC) : PASS
8750 23:49:26.216513 TX DQ/DQS : PASS
8751 23:49:26.219761 RX DATLAT : PASS
8752 23:49:26.219860 RX DQ/DQS(Engine): PASS
8753 23:49:26.223170 TX OE : PASS
8754 23:49:26.223268 All Pass.
8755 23:49:26.223356
8756 23:49:26.226557 CH 0, Rank 1
8757 23:49:26.226628 SW Impedance : PASS
8758 23:49:26.229852 DUTY Scan : NO K
8759 23:49:26.233203 ZQ Calibration : PASS
8760 23:49:26.233323 Jitter Meter : NO K
8761 23:49:26.236263 CBT Training : PASS
8762 23:49:26.236352 Write leveling : PASS
8763 23:49:26.239527 RX DQS gating : PASS
8764 23:49:26.243084 RX DQ/DQS(RDDQC) : PASS
8765 23:49:26.243180 TX DQ/DQS : PASS
8766 23:49:26.246512 RX DATLAT : PASS
8767 23:49:26.249921 RX DQ/DQS(Engine): PASS
8768 23:49:26.249995 TX OE : PASS
8769 23:49:26.252842 All Pass.
8770 23:49:26.252937
8771 23:49:26.253024 CH 1, Rank 0
8772 23:49:26.256282 SW Impedance : PASS
8773 23:49:26.256374 DUTY Scan : NO K
8774 23:49:26.259874 ZQ Calibration : PASS
8775 23:49:26.263111 Jitter Meter : NO K
8776 23:49:26.263208 CBT Training : PASS
8777 23:49:26.266543 Write leveling : PASS
8778 23:49:26.269431 RX DQS gating : PASS
8779 23:49:26.269526 RX DQ/DQS(RDDQC) : PASS
8780 23:49:26.272938 TX DQ/DQS : PASS
8781 23:49:26.276104 RX DATLAT : PASS
8782 23:49:26.276198 RX DQ/DQS(Engine): PASS
8783 23:49:26.279544 TX OE : PASS
8784 23:49:26.279642 All Pass.
8785 23:49:26.279729
8786 23:49:26.282763 CH 1, Rank 1
8787 23:49:26.282859 SW Impedance : PASS
8788 23:49:26.286211 DUTY Scan : NO K
8789 23:49:26.289500 ZQ Calibration : PASS
8790 23:49:26.289569 Jitter Meter : NO K
8791 23:49:26.293012 CBT Training : PASS
8792 23:49:26.296189 Write leveling : PASS
8793 23:49:26.296284 RX DQS gating : PASS
8794 23:49:26.299398 RX DQ/DQS(RDDQC) : PASS
8795 23:49:26.299495 TX DQ/DQS : PASS
8796 23:49:26.302601 RX DATLAT : PASS
8797 23:49:26.305763 RX DQ/DQS(Engine): PASS
8798 23:49:26.305862 TX OE : PASS
8799 23:49:26.309558 All Pass.
8800 23:49:26.309688
8801 23:49:26.309758 DramC Write-DBI on
8802 23:49:26.312564 PER_BANK_REFRESH: Hybrid Mode
8803 23:49:26.315862 TX_TRACKING: ON
8804 23:49:26.322876 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8805 23:49:26.332870 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8806 23:49:26.339343 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8807 23:49:26.342361 [FAST_K] Save calibration result to emmc
8808 23:49:26.345632 sync common calibartion params.
8809 23:49:26.345734 sync cbt_mode0:0, 1:0
8810 23:49:26.349128 dram_init: ddr_geometry: 0
8811 23:49:26.352311 dram_init: ddr_geometry: 0
8812 23:49:26.355691 dram_init: ddr_geometry: 0
8813 23:49:26.355791 0:dram_rank_size:80000000
8814 23:49:26.359044 1:dram_rank_size:80000000
8815 23:49:26.365876 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8816 23:49:26.365979 DFS_SHUFFLE_HW_MODE: ON
8817 23:49:26.369204 dramc_set_vcore_voltage set vcore to 725000
8818 23:49:26.372223 Read voltage for 1600, 0
8819 23:49:26.372323 Vio18 = 0
8820 23:49:26.375736 Vcore = 725000
8821 23:49:26.375838 Vdram = 0
8822 23:49:26.375927 Vddq = 0
8823 23:49:26.378975 Vmddr = 0
8824 23:49:26.379074 switch to 3200 Mbps bootup
8825 23:49:26.382341 [DramcRunTimeConfig]
8826 23:49:26.382439 PHYPLL
8827 23:49:26.385549 DPM_CONTROL_AFTERK: ON
8828 23:49:26.385621 PER_BANK_REFRESH: ON
8829 23:49:26.388689 REFRESH_OVERHEAD_REDUCTION: ON
8830 23:49:26.392187 CMD_PICG_NEW_MODE: OFF
8831 23:49:26.392258 XRTWTW_NEW_MODE: ON
8832 23:49:26.395988 XRTRTR_NEW_MODE: ON
8833 23:49:26.396055 TX_TRACKING: ON
8834 23:49:26.398551 RDSEL_TRACKING: OFF
8835 23:49:26.402112 DQS Precalculation for DVFS: ON
8836 23:49:26.402183 RX_TRACKING: OFF
8837 23:49:26.405446 HW_GATING DBG: ON
8838 23:49:26.405519 ZQCS_ENABLE_LP4: ON
8839 23:49:26.408612 RX_PICG_NEW_MODE: ON
8840 23:49:26.408707 TX_PICG_NEW_MODE: ON
8841 23:49:26.411662 ENABLE_RX_DCM_DPHY: ON
8842 23:49:26.415162 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8843 23:49:26.418285 DUMMY_READ_FOR_TRACKING: OFF
8844 23:49:26.421608 !!! SPM_CONTROL_AFTERK: OFF
8845 23:49:26.421716 !!! SPM could not control APHY
8846 23:49:26.425017 IMPEDANCE_TRACKING: ON
8847 23:49:26.425120 TEMP_SENSOR: ON
8848 23:49:26.428386 HW_SAVE_FOR_SR: OFF
8849 23:49:26.431879 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8850 23:49:26.435144 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8851 23:49:26.438247 Read ODT Tracking: ON
8852 23:49:26.438380 Refresh Rate DeBounce: ON
8853 23:49:26.442043 DFS_NO_QUEUE_FLUSH: ON
8854 23:49:26.445220 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8855 23:49:26.448697 ENABLE_DFS_RUNTIME_MRW: OFF
8856 23:49:26.448771 DDR_RESERVE_NEW_MODE: ON
8857 23:49:26.451898 MR_CBT_SWITCH_FREQ: ON
8858 23:49:26.455198 =========================
8859 23:49:26.472157 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8860 23:49:26.475630 dram_init: ddr_geometry: 0
8861 23:49:26.494008 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8862 23:49:26.496865 dram_init: dram init end (result: 0)
8863 23:49:26.503620 DRAM-K: Full calibration passed in 23421 msecs
8864 23:49:26.506934 MRC: failed to locate region type 0.
8865 23:49:26.507033 DRAM rank0 size:0x80000000,
8866 23:49:26.510391 DRAM rank1 size=0x80000000
8867 23:49:26.520100 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8868 23:49:26.527148 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8869 23:49:26.533332 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8870 23:49:26.540330 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8871 23:49:26.543565 DRAM rank0 size:0x80000000,
8872 23:49:26.546739 DRAM rank1 size=0x80000000
8873 23:49:26.546837 CBMEM:
8874 23:49:26.550241 IMD: root @ 0xfffff000 254 entries.
8875 23:49:26.553242 IMD: root @ 0xffffec00 62 entries.
8876 23:49:26.556773 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8877 23:49:26.560269 WARNING: RO_VPD is uninitialized or empty.
8878 23:49:26.566595 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8879 23:49:26.573264 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8880 23:49:26.585945 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8881 23:49:26.597545 BS: romstage times (exec / console): total (unknown) / 22961 ms
8882 23:49:26.597649
8883 23:49:26.597739
8884 23:49:26.607169 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8885 23:49:26.610520 ARM64: Exception handlers installed.
8886 23:49:26.613628 ARM64: Testing exception
8887 23:49:26.617259 ARM64: Done test exception
8888 23:49:26.617344 Enumerating buses...
8889 23:49:26.620477 Show all devs... Before device enumeration.
8890 23:49:26.624127 Root Device: enabled 1
8891 23:49:26.627553 CPU_CLUSTER: 0: enabled 1
8892 23:49:26.627656 CPU: 00: enabled 1
8893 23:49:26.630324 Compare with tree...
8894 23:49:26.630394 Root Device: enabled 1
8895 23:49:26.633798 CPU_CLUSTER: 0: enabled 1
8896 23:49:26.637119 CPU: 00: enabled 1
8897 23:49:26.637218 Root Device scanning...
8898 23:49:26.640407 scan_static_bus for Root Device
8899 23:49:26.643792 CPU_CLUSTER: 0 enabled
8900 23:49:26.646747 scan_static_bus for Root Device done
8901 23:49:26.650457 scan_bus: bus Root Device finished in 8 msecs
8902 23:49:26.650529 done
8903 23:49:26.656672 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8904 23:49:26.660097 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8905 23:49:26.666780 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8906 23:49:26.669976 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8907 23:49:26.673388 Allocating resources...
8908 23:49:26.677035 Reading resources...
8909 23:49:26.680063 Root Device read_resources bus 0 link: 0
8910 23:49:26.680136 DRAM rank0 size:0x80000000,
8911 23:49:26.683485 DRAM rank1 size=0x80000000
8912 23:49:26.686699 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8913 23:49:26.690020 CPU: 00 missing read_resources
8914 23:49:26.696557 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8915 23:49:26.699870 Root Device read_resources bus 0 link: 0 done
8916 23:49:26.699957 Done reading resources.
8917 23:49:26.706364 Show resources in subtree (Root Device)...After reading.
8918 23:49:26.709985 Root Device child on link 0 CPU_CLUSTER: 0
8919 23:49:26.713319 CPU_CLUSTER: 0 child on link 0 CPU: 00
8920 23:49:26.723057 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8921 23:49:26.723135 CPU: 00
8922 23:49:26.726460 Root Device assign_resources, bus 0 link: 0
8923 23:49:26.729664 CPU_CLUSTER: 0 missing set_resources
8924 23:49:26.735974 Root Device assign_resources, bus 0 link: 0 done
8925 23:49:26.736077 Done setting resources.
8926 23:49:26.742615 Show resources in subtree (Root Device)...After assigning values.
8927 23:49:26.745955 Root Device child on link 0 CPU_CLUSTER: 0
8928 23:49:26.749423 CPU_CLUSTER: 0 child on link 0 CPU: 00
8929 23:49:26.759166 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8930 23:49:26.759272 CPU: 00
8931 23:49:26.762846 Done allocating resources.
8932 23:49:26.769126 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8933 23:49:26.769229 Enabling resources...
8934 23:49:26.769344 done.
8935 23:49:26.775582 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8936 23:49:26.775657 Initializing devices...
8937 23:49:26.778996 Root Device init
8938 23:49:26.782585 init hardware done!
8939 23:49:26.782686 0x00000018: ctrlr->caps
8940 23:49:26.785793 52.000 MHz: ctrlr->f_max
8941 23:49:26.788865 0.400 MHz: ctrlr->f_min
8942 23:49:26.788969 0x40ff8080: ctrlr->voltages
8943 23:49:26.792175 sclk: 390625
8944 23:49:26.792273 Bus Width = 1
8945 23:49:26.792361 sclk: 390625
8946 23:49:26.795782 Bus Width = 1
8947 23:49:26.795852 Early init status = 3
8948 23:49:26.802368 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8949 23:49:26.805785 in-header: 03 fc 00 00 01 00 00 00
8950 23:49:26.809063 in-data: 00
8951 23:49:26.812240 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8952 23:49:26.817930 in-header: 03 fd 00 00 00 00 00 00
8953 23:49:26.821417 in-data:
8954 23:49:26.824514 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8955 23:49:26.829056 in-header: 03 fc 00 00 01 00 00 00
8956 23:49:26.832428 in-data: 00
8957 23:49:26.835706 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8958 23:49:26.841230 in-header: 03 fd 00 00 00 00 00 00
8959 23:49:26.844359 in-data:
8960 23:49:26.848201 [SSUSB] Setting up USB HOST controller...
8961 23:49:26.851287 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8962 23:49:26.854646 [SSUSB] phy power-on done.
8963 23:49:26.857802 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8964 23:49:26.864314 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8965 23:49:26.867808 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8966 23:49:26.874266 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8967 23:49:26.881182 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8968 23:49:26.887698 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8969 23:49:26.894424 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8970 23:49:26.900965 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8971 23:49:26.904056 SPM: binary array size = 0x9dc
8972 23:49:26.907464 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8973 23:49:26.914199 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8974 23:49:26.920633 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8975 23:49:26.927608 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8976 23:49:26.930979 configure_display: Starting display init
8977 23:49:26.964801 anx7625_power_on_init: Init interface.
8978 23:49:26.967623 anx7625_disable_pd_protocol: Disabled PD feature.
8979 23:49:26.971070 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8980 23:49:26.999019 anx7625_start_dp_work: Secure OCM version=00
8981 23:49:27.002167 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8982 23:49:27.017005 sp_tx_get_edid_block: EDID Block = 1
8983 23:49:27.119961 Extracted contents:
8984 23:49:27.123010 header: 00 ff ff ff ff ff ff 00
8985 23:49:27.126217 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8986 23:49:27.129604 version: 01 04
8987 23:49:27.132703 basic params: 95 1f 11 78 0a
8988 23:49:27.136193 chroma info: 76 90 94 55 54 90 27 21 50 54
8989 23:49:27.139310 established: 00 00 00
8990 23:49:27.145898 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8991 23:49:27.149404 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8992 23:49:27.155974 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8993 23:49:27.162345 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8994 23:49:27.168984 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8995 23:49:27.172594 extensions: 00
8996 23:49:27.172693 checksum: fb
8997 23:49:27.172786
8998 23:49:27.175649 Manufacturer: IVO Model 57d Serial Number 0
8999 23:49:27.178909 Made week 0 of 2020
9000 23:49:27.182616 EDID version: 1.4
9001 23:49:27.182688 Digital display
9002 23:49:27.185586 6 bits per primary color channel
9003 23:49:27.185660 DisplayPort interface
9004 23:49:27.189092 Maximum image size: 31 cm x 17 cm
9005 23:49:27.192318 Gamma: 220%
9006 23:49:27.192411 Check DPMS levels
9007 23:49:27.195373 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9008 23:49:27.202499 First detailed timing is preferred timing
9009 23:49:27.202575 Established timings supported:
9010 23:49:27.205578 Standard timings supported:
9011 23:49:27.208787 Detailed timings
9012 23:49:27.212282 Hex of detail: 383680a07038204018303c0035ae10000019
9013 23:49:27.218800 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9014 23:49:27.221866 0780 0798 07c8 0820 hborder 0
9015 23:49:27.225186 0438 043b 0447 0458 vborder 0
9016 23:49:27.228516 -hsync -vsync
9017 23:49:27.228591 Did detailed timing
9018 23:49:27.235553 Hex of detail: 000000000000000000000000000000000000
9019 23:49:27.238579 Manufacturer-specified data, tag 0
9020 23:49:27.241834 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9021 23:49:27.245102 ASCII string: InfoVision
9022 23:49:27.248222 Hex of detail: 000000fe00523134304e574635205248200a
9023 23:49:27.251520 ASCII string: R140NWF5 RH
9024 23:49:27.251589 Checksum
9025 23:49:27.254964 Checksum: 0xfb (valid)
9026 23:49:27.258442 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9027 23:49:27.261640 DSI data_rate: 832800000 bps
9028 23:49:27.268319 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9029 23:49:27.271320 anx7625_parse_edid: pixelclock(138800).
9030 23:49:27.274927 hactive(1920), hsync(48), hfp(24), hbp(88)
9031 23:49:27.278449 vactive(1080), vsync(12), vfp(3), vbp(17)
9032 23:49:27.281386 anx7625_dsi_config: config dsi.
9033 23:49:27.288077 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9034 23:49:27.301577 anx7625_dsi_config: success to config DSI
9035 23:49:27.305175 anx7625_dp_start: MIPI phy setup OK.
9036 23:49:27.308363 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9037 23:49:27.311411 mtk_ddp_mode_set invalid vrefresh 60
9038 23:49:27.314864 main_disp_path_setup
9039 23:49:27.314933 ovl_layer_smi_id_en
9040 23:49:27.318171 ovl_layer_smi_id_en
9041 23:49:27.318239 ccorr_config
9042 23:49:27.318301 aal_config
9043 23:49:27.321551 gamma_config
9044 23:49:27.321618 postmask_config
9045 23:49:27.324793 dither_config
9046 23:49:27.327934 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9047 23:49:27.334913 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9048 23:49:27.338057 Root Device init finished in 555 msecs
9049 23:49:27.341176 CPU_CLUSTER: 0 init
9050 23:49:27.347922 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9051 23:49:27.351253 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9052 23:49:27.354542 APU_MBOX 0x190000b0 = 0x10001
9053 23:49:27.357759 APU_MBOX 0x190001b0 = 0x10001
9054 23:49:27.360960 APU_MBOX 0x190005b0 = 0x10001
9055 23:49:27.364592 APU_MBOX 0x190006b0 = 0x10001
9056 23:49:27.370941 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9057 23:49:27.380575 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9058 23:49:27.393154 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9059 23:49:27.399348 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9060 23:49:27.411256 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9061 23:49:27.420516 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9062 23:49:27.423328 CPU_CLUSTER: 0 init finished in 81 msecs
9063 23:49:27.426932 Devices initialized
9064 23:49:27.430479 Show all devs... After init.
9065 23:49:27.430556 Root Device: enabled 1
9066 23:49:27.433469 CPU_CLUSTER: 0: enabled 1
9067 23:49:27.437195 CPU: 00: enabled 1
9068 23:49:27.440383 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9069 23:49:27.443707 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9070 23:49:27.446653 ELOG: NV offset 0x57f000 size 0x1000
9071 23:49:27.453518 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9072 23:49:27.459880 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9073 23:49:27.463472 ELOG: Event(17) added with size 13 at 2024-05-29 23:49:29 UTC
9074 23:49:27.469832 out: cmd=0x121: 03 db 21 01 00 00 00 00
9075 23:49:27.474040 in-header: 03 e9 00 00 2c 00 00 00
9076 23:49:27.483208 in-data: 7a 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9077 23:49:27.489708 ELOG: Event(A1) added with size 10 at 2024-05-29 23:49:29 UTC
9078 23:49:27.496249 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9079 23:49:27.502750 ELOG: Event(A0) added with size 9 at 2024-05-29 23:49:29 UTC
9080 23:49:27.506102 elog_add_boot_reason: Logged dev mode boot
9081 23:49:27.512971 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9082 23:49:27.513075 Finalize devices...
9083 23:49:27.516110 Devices finalized
9084 23:49:27.519293 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9085 23:49:27.522569 Writing coreboot table at 0xffe64000
9086 23:49:27.525692 0. 000000000010a000-0000000000113fff: RAMSTAGE
9087 23:49:27.529388 1. 0000000040000000-00000000400fffff: RAM
9088 23:49:27.535856 2. 0000000040100000-000000004032afff: RAMSTAGE
9089 23:49:27.538934 3. 000000004032b000-00000000545fffff: RAM
9090 23:49:27.542559 4. 0000000054600000-000000005465ffff: BL31
9091 23:49:27.545736 5. 0000000054660000-00000000ffe63fff: RAM
9092 23:49:27.552312 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9093 23:49:27.555708 7. 0000000100000000-000000013fffffff: RAM
9094 23:49:27.558957 Passing 5 GPIOs to payload:
9095 23:49:27.562482 NAME | PORT | POLARITY | VALUE
9096 23:49:27.569017 EC in RW | 0x000000aa | low | undefined
9097 23:49:27.572384 EC interrupt | 0x00000005 | low | undefined
9098 23:49:27.575447 TPM interrupt | 0x000000ab | high | undefined
9099 23:49:27.582526 SD card detect | 0x00000011 | high | undefined
9100 23:49:27.585390 speaker enable | 0x00000093 | high | undefined
9101 23:49:27.588802 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9102 23:49:27.592014 in-header: 03 f4 00 00 02 00 00 00
9103 23:49:27.595379 in-data: 07 00
9104 23:49:27.598536 ADC[4]: Raw value=668958 ID=5
9105 23:49:27.598644 ADC[3]: Raw value=212549 ID=1
9106 23:49:27.602168 RAM Code: 0x51
9107 23:49:27.605204 ADC[6]: Raw value=74410 ID=0
9108 23:49:27.605329 ADC[5]: Raw value=211444 ID=1
9109 23:49:27.608830 SKU Code: 0x1
9110 23:49:27.611983 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum de67
9111 23:49:27.615255 coreboot table: 964 bytes.
9112 23:49:27.618467 IMD ROOT 0. 0xfffff000 0x00001000
9113 23:49:27.621871 IMD SMALL 1. 0xffffe000 0x00001000
9114 23:49:27.625219 RO MCACHE 2. 0xffffc000 0x00001104
9115 23:49:27.628248 CONSOLE 3. 0xfff7c000 0x00080000
9116 23:49:27.631575 FMAP 4. 0xfff7b000 0x00000452
9117 23:49:27.635007 TIME STAMP 5. 0xfff7a000 0x00000910
9118 23:49:27.638263 VBOOT WORK 6. 0xfff66000 0x00014000
9119 23:49:27.641490 RAMOOPS 7. 0xffe66000 0x00100000
9120 23:49:27.644942 COREBOOT 8. 0xffe64000 0x00002000
9121 23:49:27.648295 IMD small region:
9122 23:49:27.651746 IMD ROOT 0. 0xffffec00 0x00000400
9123 23:49:27.655160 VPD 1. 0xffffeb80 0x0000006c
9124 23:49:27.658215 MMC STATUS 2. 0xffffeb60 0x00000004
9125 23:49:27.661372 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9126 23:49:27.664893 Probing TPM: done!
9127 23:49:27.668063 Connected to device vid:did:rid of 1ae0:0028:00
9128 23:49:27.678820 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9129 23:49:27.682436 Initialized TPM device CR50 revision 0
9130 23:49:27.685976 Checking cr50 for pending updates
9131 23:49:27.689735 Reading cr50 TPM mode
9132 23:49:27.698296 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9133 23:49:27.704995 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9134 23:49:27.745163 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9135 23:49:27.748084 Checking segment from ROM address 0x40100000
9136 23:49:27.751763 Checking segment from ROM address 0x4010001c
9137 23:49:27.758338 Loading segment from ROM address 0x40100000
9138 23:49:27.758413 code (compression=0)
9139 23:49:27.768255 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9140 23:49:27.775038 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9141 23:49:27.775118 it's not compressed!
9142 23:49:27.781498 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9143 23:49:27.784764 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9144 23:49:27.805778 Loading segment from ROM address 0x4010001c
9145 23:49:27.805856 Entry Point 0x80000000
9146 23:49:27.808778 Loaded segments
9147 23:49:27.812018 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9148 23:49:27.818941 Jumping to boot code at 0x80000000(0xffe64000)
9149 23:49:27.825654 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9150 23:49:27.831915 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9151 23:49:27.839824 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9152 23:49:27.843197 Checking segment from ROM address 0x40100000
9153 23:49:27.846320 Checking segment from ROM address 0x4010001c
9154 23:49:27.853237 Loading segment from ROM address 0x40100000
9155 23:49:27.853362 code (compression=1)
9156 23:49:27.859929 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9157 23:49:27.869592 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9158 23:49:27.869669 using LZMA
9159 23:49:27.877972 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9160 23:49:27.885152 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9161 23:49:27.888256 Loading segment from ROM address 0x4010001c
9162 23:49:27.888326 Entry Point 0x54601000
9163 23:49:27.891531 Loaded segments
9164 23:49:27.894815 NOTICE: MT8192 bl31_setup
9165 23:49:27.902336 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9166 23:49:27.905175 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9167 23:49:27.908324 WARNING: region 0:
9168 23:49:27.911836 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9169 23:49:27.911910 WARNING: region 1:
9170 23:49:27.918272 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9171 23:49:27.922088 WARNING: region 2:
9172 23:49:27.925201 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9173 23:49:27.928342 WARNING: region 3:
9174 23:49:27.931776 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9175 23:49:27.934899 WARNING: region 4:
9176 23:49:27.938670 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9177 23:49:27.941701 WARNING: region 5:
9178 23:49:27.945059 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9179 23:49:27.948482 WARNING: region 6:
9180 23:49:27.951695 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9181 23:49:27.954925 WARNING: region 7:
9182 23:49:27.958720 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9183 23:49:27.965109 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9184 23:49:27.968616 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9185 23:49:27.972051 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9186 23:49:27.978702 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9187 23:49:27.981770 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9188 23:49:27.985088 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9189 23:49:27.991684 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9190 23:49:27.995194 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9191 23:49:28.001938 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9192 23:49:28.005463 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9193 23:49:28.008602 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9194 23:49:28.014928 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9195 23:49:28.018567 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9196 23:49:28.021811 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9197 23:49:28.028257 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9198 23:49:28.031639 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9199 23:49:28.038223 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9200 23:49:28.041880 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9201 23:49:28.044729 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9202 23:49:28.051518 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9203 23:49:28.055056 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9204 23:49:28.058221 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9205 23:49:28.064773 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9206 23:49:28.068342 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9207 23:49:28.074714 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9208 23:49:28.078234 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9209 23:49:28.081402 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9210 23:49:28.088143 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9211 23:49:28.091589 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9212 23:49:28.098741 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9213 23:49:28.101464 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9214 23:49:28.104717 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9215 23:49:28.111494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9216 23:49:28.114694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9217 23:49:28.118025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9218 23:49:28.121226 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9219 23:49:28.128078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9220 23:49:28.131266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9221 23:49:28.134728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9222 23:49:28.138341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9223 23:49:28.144762 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9224 23:49:28.147904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9225 23:49:28.151366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9226 23:49:28.154577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9227 23:49:28.161212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9228 23:49:28.164690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9229 23:49:28.167945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9230 23:49:28.171313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9231 23:49:28.178040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9232 23:49:28.181066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9233 23:49:28.187673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9234 23:49:28.191241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9235 23:49:28.197638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9236 23:49:28.201051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9237 23:49:28.204290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9238 23:49:28.211029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9239 23:49:28.214509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9240 23:49:28.221470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9241 23:49:28.224445 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9242 23:49:28.231313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9243 23:49:28.234394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9244 23:49:28.240837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9245 23:49:28.244500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9246 23:49:28.247703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9247 23:49:28.254295 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9248 23:49:28.257618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9249 23:49:28.264695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9250 23:49:28.267600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9251 23:49:28.274259 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9252 23:49:28.277680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9253 23:49:28.281145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9254 23:49:28.287497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9255 23:49:28.291100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9256 23:49:28.298091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9257 23:49:28.300752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9258 23:49:28.308003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9259 23:49:28.310926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9260 23:49:28.314255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9261 23:49:28.320876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9262 23:49:28.324359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9263 23:49:28.331048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9264 23:49:28.334181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9265 23:49:28.340902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9266 23:49:28.344343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9267 23:49:28.347539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9268 23:49:28.354586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9269 23:49:28.357377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9270 23:49:28.364079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9271 23:49:28.367451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9272 23:49:28.374076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9273 23:49:28.377586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9274 23:49:28.380966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9275 23:49:28.387364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9276 23:49:28.391052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9277 23:49:28.397270 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9278 23:49:28.400782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9279 23:49:28.407249 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9280 23:49:28.411048 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9281 23:49:28.413689 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9282 23:49:28.417065 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9283 23:49:28.423938 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9284 23:49:28.427451 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9285 23:49:28.430473 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9286 23:49:28.437258 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9287 23:49:28.440544 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9288 23:49:28.447185 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9289 23:49:28.450560 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9290 23:49:28.453839 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9291 23:49:28.460369 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9292 23:49:28.463850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9293 23:49:28.470537 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9294 23:49:28.473930 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9295 23:49:28.477522 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9296 23:49:28.483577 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9297 23:49:28.486991 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9298 23:49:28.493501 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9299 23:49:28.497179 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9300 23:49:28.500174 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9301 23:49:28.503526 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9302 23:49:28.510327 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9303 23:49:28.513482 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9304 23:49:28.516694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9305 23:49:28.520128 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9306 23:49:28.526995 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9307 23:49:28.530318 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9308 23:49:28.533789 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9309 23:49:28.540338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9310 23:49:28.543526 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9311 23:49:28.550240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9312 23:49:28.553493 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9313 23:49:28.556677 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9314 23:49:28.563465 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9315 23:49:28.566654 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9316 23:49:28.573616 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9317 23:49:28.576882 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9318 23:49:28.580087 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9319 23:49:28.586651 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9320 23:49:28.589969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9321 23:49:28.596741 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9322 23:49:28.599840 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9323 23:49:28.603451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9324 23:49:28.610350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9325 23:49:28.613585 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9326 23:49:28.620300 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9327 23:49:28.623639 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9328 23:49:28.626830 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9329 23:49:28.633610 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9330 23:49:28.636640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9331 23:49:28.640181 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9332 23:49:28.646642 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9333 23:49:28.650070 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9334 23:49:28.656618 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9335 23:49:28.660090 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9336 23:49:28.663733 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9337 23:49:28.669989 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9338 23:49:28.673259 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9339 23:49:28.680189 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9340 23:49:28.683494 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9341 23:49:28.686777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9342 23:49:28.693041 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9343 23:49:28.696471 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9344 23:49:28.699877 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9345 23:49:28.706314 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9346 23:49:28.709920 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9347 23:49:28.716172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9348 23:49:28.719691 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9349 23:49:28.723022 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9350 23:49:28.729557 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9351 23:49:28.732881 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9352 23:49:28.739615 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9353 23:49:28.743416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9354 23:49:28.746517 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9355 23:49:28.752756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9356 23:49:28.756096 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9357 23:49:28.762870 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9358 23:49:28.766223 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9359 23:49:28.769432 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9360 23:49:28.775932 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9361 23:49:28.779146 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9362 23:49:28.785934 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9363 23:49:28.789199 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9364 23:49:28.792778 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9365 23:49:28.799148 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9366 23:49:28.802566 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9367 23:49:28.809012 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9368 23:49:28.812509 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9369 23:49:28.815720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9370 23:49:28.822334 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9371 23:49:28.825534 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9372 23:49:28.832217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9373 23:49:28.835303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9374 23:49:28.838783 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9375 23:49:28.845316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9376 23:49:28.849024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9377 23:49:28.855472 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9378 23:49:28.858391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9379 23:49:28.865669 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9380 23:49:28.868230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9381 23:49:28.871628 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9382 23:49:28.878625 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9383 23:49:28.881669 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9384 23:49:28.888281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9385 23:49:28.891404 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9386 23:49:28.898404 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9387 23:49:28.901640 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9388 23:49:28.904848 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9389 23:49:28.911352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9390 23:49:28.914689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9391 23:49:28.921379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9392 23:49:28.924688 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9393 23:49:28.930992 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9394 23:49:28.934654 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9395 23:49:28.937704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9396 23:49:28.944548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9397 23:49:28.947923 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9398 23:49:28.954250 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9399 23:49:28.957796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9400 23:49:28.960753 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9401 23:49:28.967794 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9402 23:49:28.970956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9403 23:49:28.977089 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9404 23:49:28.980447 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9405 23:49:28.987173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9406 23:49:28.990737 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9407 23:49:28.993977 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9408 23:49:29.000566 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9409 23:49:29.003408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9410 23:49:29.010054 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9411 23:49:29.013686 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9412 23:49:29.016931 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9413 23:49:29.023287 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9414 23:49:29.026537 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9415 23:49:29.030370 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9416 23:49:29.033223 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9417 23:49:29.040033 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9418 23:49:29.043012 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9419 23:49:29.049684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9420 23:49:29.052848 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9421 23:49:29.056121 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9422 23:49:29.063269 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9423 23:49:29.066532 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9424 23:49:29.069621 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9425 23:49:29.076231 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9426 23:49:29.079249 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9427 23:49:29.082883 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9428 23:49:29.089230 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9429 23:49:29.092921 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9430 23:49:29.099505 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9431 23:49:29.102529 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9432 23:49:29.105948 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9433 23:49:29.112530 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9434 23:49:29.115548 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9435 23:49:29.122185 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9436 23:49:29.125928 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9437 23:49:29.129125 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9438 23:49:29.135528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9439 23:49:29.138984 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9440 23:49:29.142013 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9441 23:49:29.148687 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9442 23:49:29.151869 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9443 23:49:29.155581 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9444 23:49:29.162038 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9445 23:49:29.165178 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9446 23:49:29.171632 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9447 23:49:29.174927 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9448 23:49:29.178460 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9449 23:49:29.185466 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9450 23:49:29.188290 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9451 23:49:29.191775 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9452 23:49:29.198105 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9453 23:49:29.201559 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9454 23:49:29.204638 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9455 23:49:29.208012 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9456 23:49:29.211425 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9457 23:49:29.217848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9458 23:49:29.221330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9459 23:49:29.224542 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9460 23:49:29.231331 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9461 23:49:29.234799 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9462 23:49:29.238152 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9463 23:49:29.244655 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9464 23:49:29.248054 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9465 23:49:29.251412 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9466 23:49:29.257604 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9467 23:49:29.260894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9468 23:49:29.264052 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9469 23:49:29.270825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9470 23:49:29.274347 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9471 23:49:29.280791 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9472 23:49:29.284360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9473 23:49:29.290988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9474 23:49:29.294110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9475 23:49:29.297630 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9476 23:49:29.303910 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9477 23:49:29.307119 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9478 23:49:29.313968 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9479 23:49:29.316930 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9480 23:49:29.320455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9481 23:49:29.327296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9482 23:49:29.330346 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9483 23:49:29.337087 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9484 23:49:29.340308 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9485 23:49:29.347018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9486 23:49:29.350079 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9487 23:49:29.353742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9488 23:49:29.359942 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9489 23:49:29.363446 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9490 23:49:29.370218 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9491 23:49:29.373224 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9492 23:49:29.376696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9493 23:49:29.382985 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9494 23:49:29.386378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9495 23:49:29.392917 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9496 23:49:29.396157 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9497 23:49:29.400011 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9498 23:49:29.406070 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9499 23:49:29.409221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9500 23:49:29.416580 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9501 23:49:29.419301 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9502 23:49:29.425808 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9503 23:49:29.429173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9504 23:49:29.432638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9505 23:49:29.439092 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9506 23:49:29.442550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9507 23:49:29.449181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9508 23:49:29.452239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9509 23:49:29.458797 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9510 23:49:29.462293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9511 23:49:29.465851 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9512 23:49:29.472409 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9513 23:49:29.475615 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9514 23:49:29.482048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9515 23:49:29.485425 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9516 23:49:29.488887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9517 23:49:29.495475 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9518 23:49:29.498606 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9519 23:49:29.505123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9520 23:49:29.508564 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9521 23:49:29.511835 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9522 23:49:29.518702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9523 23:49:29.521768 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9524 23:49:29.528253 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9525 23:49:29.531597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9526 23:49:29.538727 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9527 23:49:29.541547 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9528 23:49:29.545286 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9529 23:49:29.551472 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9530 23:49:29.554879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9531 23:49:29.561226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9532 23:49:29.564748 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9533 23:49:29.571424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9534 23:49:29.574619 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9535 23:49:29.578123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9536 23:49:29.584378 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9537 23:49:29.587716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9538 23:49:29.594332 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9539 23:49:29.598032 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9540 23:49:29.601039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9541 23:49:29.608067 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9542 23:49:29.610843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9543 23:49:29.617503 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9544 23:49:29.620952 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9545 23:49:29.627487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9546 23:49:29.630689 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9547 23:49:29.637585 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9548 23:49:29.640627 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9549 23:49:29.647213 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9550 23:49:29.650474 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9551 23:49:29.653674 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9552 23:49:29.660273 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9553 23:49:29.663765 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9554 23:49:29.670191 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9555 23:49:29.674069 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9556 23:49:29.680233 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9557 23:49:29.683853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9558 23:49:29.689940 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9559 23:49:29.693495 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9560 23:49:29.696860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9561 23:49:29.703513 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9562 23:49:29.706964 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9563 23:49:29.713208 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9564 23:49:29.716579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9565 23:49:29.723620 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9566 23:49:29.726418 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9567 23:49:29.732810 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9568 23:49:29.736105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9569 23:49:29.739461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9570 23:49:29.746255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9571 23:49:29.749410 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9572 23:49:29.756054 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9573 23:49:29.759399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9574 23:49:29.765865 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9575 23:49:29.769411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9576 23:49:29.772815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9577 23:49:29.779547 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9578 23:49:29.782780 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9579 23:49:29.789464 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9580 23:49:29.792963 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9581 23:49:29.799390 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9582 23:49:29.802760 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9583 23:49:29.809152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9584 23:49:29.812743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9585 23:49:29.815917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9586 23:49:29.822278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9587 23:49:29.825648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9588 23:49:29.832150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9589 23:49:29.835970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9590 23:49:29.842281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9591 23:49:29.845643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9592 23:49:29.851929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9593 23:49:29.855264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9594 23:49:29.861845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9595 23:49:29.865584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9596 23:49:29.871840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9597 23:49:29.875062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9598 23:49:29.881802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9599 23:49:29.885262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9600 23:49:29.888083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9601 23:49:29.894498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9602 23:49:29.900998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9603 23:49:29.904477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9604 23:49:29.907861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9605 23:49:29.914724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9606 23:49:29.921184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9607 23:49:29.924189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9608 23:49:29.931105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9609 23:49:29.934361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9610 23:49:29.940860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9611 23:49:29.944385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9612 23:49:29.950643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9613 23:49:29.954105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9614 23:49:29.961015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9615 23:49:29.964212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9616 23:49:29.970628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9617 23:49:29.974112 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9618 23:49:29.974190 INFO: [APUAPC] vio 0
9619 23:49:29.981489 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9620 23:49:29.985162 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9621 23:49:29.988151 INFO: [APUAPC] D0_APC_0: 0x400510
9622 23:49:29.991282 INFO: [APUAPC] D0_APC_1: 0x0
9623 23:49:29.994735 INFO: [APUAPC] D0_APC_2: 0x1540
9624 23:49:29.997907 INFO: [APUAPC] D0_APC_3: 0x0
9625 23:49:30.001268 INFO: [APUAPC] D1_APC_0: 0xffffffff
9626 23:49:30.004739 INFO: [APUAPC] D1_APC_1: 0xffffffff
9627 23:49:30.008429 INFO: [APUAPC] D1_APC_2: 0x3fffff
9628 23:49:30.011236 INFO: [APUAPC] D1_APC_3: 0x0
9629 23:49:30.014797 INFO: [APUAPC] D2_APC_0: 0xffffffff
9630 23:49:30.017883 INFO: [APUAPC] D2_APC_1: 0xffffffff
9631 23:49:30.021083 INFO: [APUAPC] D2_APC_2: 0x3fffff
9632 23:49:30.024735 INFO: [APUAPC] D2_APC_3: 0x0
9633 23:49:30.027512 INFO: [APUAPC] D3_APC_0: 0xffffffff
9634 23:49:30.031410 INFO: [APUAPC] D3_APC_1: 0xffffffff
9635 23:49:30.034371 INFO: [APUAPC] D3_APC_2: 0x3fffff
9636 23:49:30.037683 INFO: [APUAPC] D3_APC_3: 0x0
9637 23:49:30.041274 INFO: [APUAPC] D4_APC_0: 0xffffffff
9638 23:49:30.044263 INFO: [APUAPC] D4_APC_1: 0xffffffff
9639 23:49:30.047602 INFO: [APUAPC] D4_APC_2: 0x3fffff
9640 23:49:30.050605 INFO: [APUAPC] D4_APC_3: 0x0
9641 23:49:30.054279 INFO: [APUAPC] D5_APC_0: 0xffffffff
9642 23:49:30.057433 INFO: [APUAPC] D5_APC_1: 0xffffffff
9643 23:49:30.061008 INFO: [APUAPC] D5_APC_2: 0x3fffff
9644 23:49:30.064097 INFO: [APUAPC] D5_APC_3: 0x0
9645 23:49:30.067361 INFO: [APUAPC] D6_APC_0: 0xffffffff
9646 23:49:30.070985 INFO: [APUAPC] D6_APC_1: 0xffffffff
9647 23:49:30.073909 INFO: [APUAPC] D6_APC_2: 0x3fffff
9648 23:49:30.073983 INFO: [APUAPC] D6_APC_3: 0x0
9649 23:49:30.077323 INFO: [APUAPC] D7_APC_0: 0xffffffff
9650 23:49:30.084047 INFO: [APUAPC] D7_APC_1: 0xffffffff
9651 23:49:30.087367 INFO: [APUAPC] D7_APC_2: 0x3fffff
9652 23:49:30.087440 INFO: [APUAPC] D7_APC_3: 0x0
9653 23:49:30.090636 INFO: [APUAPC] D8_APC_0: 0xffffffff
9654 23:49:30.093840 INFO: [APUAPC] D8_APC_1: 0xffffffff
9655 23:49:30.097314 INFO: [APUAPC] D8_APC_2: 0x3fffff
9656 23:49:30.100304 INFO: [APUAPC] D8_APC_3: 0x0
9657 23:49:30.103958 INFO: [APUAPC] D9_APC_0: 0xffffffff
9658 23:49:30.106937 INFO: [APUAPC] D9_APC_1: 0xffffffff
9659 23:49:30.110389 INFO: [APUAPC] D9_APC_2: 0x3fffff
9660 23:49:30.113904 INFO: [APUAPC] D9_APC_3: 0x0
9661 23:49:30.116685 INFO: [APUAPC] D10_APC_0: 0xffffffff
9662 23:49:30.120235 INFO: [APUAPC] D10_APC_1: 0xffffffff
9663 23:49:30.123565 INFO: [APUAPC] D10_APC_2: 0x3fffff
9664 23:49:30.127337 INFO: [APUAPC] D10_APC_3: 0x0
9665 23:49:30.130166 INFO: [APUAPC] D11_APC_0: 0xffffffff
9666 23:49:30.133480 INFO: [APUAPC] D11_APC_1: 0xffffffff
9667 23:49:30.136924 INFO: [APUAPC] D11_APC_2: 0x3fffff
9668 23:49:30.139908 INFO: [APUAPC] D11_APC_3: 0x0
9669 23:49:30.143306 INFO: [APUAPC] D12_APC_0: 0xffffffff
9670 23:49:30.146445 INFO: [APUAPC] D12_APC_1: 0xffffffff
9671 23:49:30.153587 INFO: [APUAPC] D12_APC_2: 0x3fffff
9672 23:49:30.153692 INFO: [APUAPC] D12_APC_3: 0x0
9673 23:49:30.156420 INFO: [APUAPC] D13_APC_0: 0xffffffff
9674 23:49:30.163046 INFO: [APUAPC] D13_APC_1: 0xffffffff
9675 23:49:30.166692 INFO: [APUAPC] D13_APC_2: 0x3fffff
9676 23:49:30.166765 INFO: [APUAPC] D13_APC_3: 0x0
9677 23:49:30.169883 INFO: [APUAPC] D14_APC_0: 0xffffffff
9678 23:49:30.176303 INFO: [APUAPC] D14_APC_1: 0xffffffff
9679 23:49:30.179852 INFO: [APUAPC] D14_APC_2: 0x3fffff
9680 23:49:30.179928 INFO: [APUAPC] D14_APC_3: 0x0
9681 23:49:30.186429 INFO: [APUAPC] D15_APC_0: 0xffffffff
9682 23:49:30.189829 INFO: [APUAPC] D15_APC_1: 0xffffffff
9683 23:49:30.193312 INFO: [APUAPC] D15_APC_2: 0x3fffff
9684 23:49:30.196093 INFO: [APUAPC] D15_APC_3: 0x0
9685 23:49:30.196174 INFO: [APUAPC] APC_CON: 0x4
9686 23:49:30.199715 INFO: [NOCDAPC] D0_APC_0: 0x0
9687 23:49:30.202952 INFO: [NOCDAPC] D0_APC_1: 0x0
9688 23:49:30.206024 INFO: [NOCDAPC] D1_APC_0: 0x0
9689 23:49:30.209554 INFO: [NOCDAPC] D1_APC_1: 0xfff
9690 23:49:30.212713 INFO: [NOCDAPC] D2_APC_0: 0x0
9691 23:49:30.216158 INFO: [NOCDAPC] D2_APC_1: 0xfff
9692 23:49:30.219303 INFO: [NOCDAPC] D3_APC_0: 0x0
9693 23:49:30.223041 INFO: [NOCDAPC] D3_APC_1: 0xfff
9694 23:49:30.223122 INFO: [NOCDAPC] D4_APC_0: 0x0
9695 23:49:30.226319 INFO: [NOCDAPC] D4_APC_1: 0xfff
9696 23:49:30.229256 INFO: [NOCDAPC] D5_APC_0: 0x0
9697 23:49:30.232786 INFO: [NOCDAPC] D5_APC_1: 0xfff
9698 23:49:30.236038 INFO: [NOCDAPC] D6_APC_0: 0x0
9699 23:49:30.239437 INFO: [NOCDAPC] D6_APC_1: 0xfff
9700 23:49:30.242723 INFO: [NOCDAPC] D7_APC_0: 0x0
9701 23:49:30.246284 INFO: [NOCDAPC] D7_APC_1: 0xfff
9702 23:49:30.249030 INFO: [NOCDAPC] D8_APC_0: 0x0
9703 23:49:30.252258 INFO: [NOCDAPC] D8_APC_1: 0xfff
9704 23:49:30.255930 INFO: [NOCDAPC] D9_APC_0: 0x0
9705 23:49:30.258794 INFO: [NOCDAPC] D9_APC_1: 0xfff
9706 23:49:30.258886 INFO: [NOCDAPC] D10_APC_0: 0x0
9707 23:49:30.262070 INFO: [NOCDAPC] D10_APC_1: 0xfff
9708 23:49:30.265485 INFO: [NOCDAPC] D11_APC_0: 0x0
9709 23:49:30.268815 INFO: [NOCDAPC] D11_APC_1: 0xfff
9710 23:49:30.271990 INFO: [NOCDAPC] D12_APC_0: 0x0
9711 23:49:30.275190 INFO: [NOCDAPC] D12_APC_1: 0xfff
9712 23:49:30.278910 INFO: [NOCDAPC] D13_APC_0: 0x0
9713 23:49:30.281800 INFO: [NOCDAPC] D13_APC_1: 0xfff
9714 23:49:30.285168 INFO: [NOCDAPC] D14_APC_0: 0x0
9715 23:49:30.288759 INFO: [NOCDAPC] D14_APC_1: 0xfff
9716 23:49:30.291797 INFO: [NOCDAPC] D15_APC_0: 0x0
9717 23:49:30.295531 INFO: [NOCDAPC] D15_APC_1: 0xfff
9718 23:49:30.298768 INFO: [NOCDAPC] APC_CON: 0x4
9719 23:49:30.301709 INFO: [APUAPC] set_apusys_apc done
9720 23:49:30.305307 INFO: [DEVAPC] devapc_init done
9721 23:49:30.308611 INFO: GICv3 without legacy support detected.
9722 23:49:30.311739 INFO: ARM GICv3 driver initialized in EL3
9723 23:49:30.315270 INFO: Maximum SPI INTID supported: 639
9724 23:49:30.318222 INFO: BL31: Initializing runtime services
9725 23:49:30.325159 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9726 23:49:30.328314 INFO: SPM: enable CPC mode
9727 23:49:30.335167 INFO: mcdi ready for mcusys-off-idle and system suspend
9728 23:49:30.338322 INFO: BL31: Preparing for EL3 exit to normal world
9729 23:49:30.341588 INFO: Entry point address = 0x80000000
9730 23:49:30.344900 INFO: SPSR = 0x8
9731 23:49:30.349771
9732 23:49:30.349853
9733 23:49:30.349916
9734 23:49:30.353136 Starting depthcharge on Spherion...
9735 23:49:30.353217
9736 23:49:30.353280 Wipe memory regions:
9737 23:49:30.353384
9738 23:49:30.354023 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9739 23:49:30.354120 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9740 23:49:30.354202 Setting prompt string to ['asurada:']
9741 23:49:30.354279 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9742 23:49:30.355966 [0x00000040000000, 0x00000054600000)
9743 23:49:30.478629
9744 23:49:30.478774 [0x00000054660000, 0x00000080000000)
9745 23:49:30.738868
9746 23:49:30.739014 [0x000000821a7280, 0x000000ffe64000)
9747 23:49:31.483689
9748 23:49:31.483840 [0x00000100000000, 0x00000140000000)
9749 23:49:31.863668
9750 23:49:31.866821 Initializing XHCI USB controller at 0x11200000.
9751 23:49:32.905133
9752 23:49:32.908656 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9753 23:49:32.909115
9754 23:49:32.909493
9755 23:49:32.910243 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9757 23:49:33.011380 asurada: tftpboot 192.168.201.1 14084309/tftp-deploy-w6qgyi4y/kernel/image.itb 14084309/tftp-deploy-w6qgyi4y/kernel/cmdline
9758 23:49:33.011887 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9759 23:49:33.012284 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9760 23:49:33.016754 tftpboot 192.168.201.1 14084309/tftp-deploy-w6qgyi4y/kernel/image.itp-deploy-w6qgyi4y/kernel/cmdline
9761 23:49:33.017181
9762 23:49:33.017646 Waiting for link
9763 23:49:33.177250
9764 23:49:33.177752 R8152: Initializing
9765 23:49:33.178085
9766 23:49:33.180562 Version 9 (ocp_data = 6010)
9767 23:49:33.180998
9768 23:49:33.183762 R8152: Done initializing
9769 23:49:33.184181
9770 23:49:33.184511 Adding net device
9771 23:49:35.056203
9772 23:49:35.056375 done.
9773 23:49:35.056479
9774 23:49:35.056541 MAC: 00:e0:4c:68:03:bd
9775 23:49:35.056600
9776 23:49:35.059175 Sending DHCP discover... done.
9777 23:49:35.059286
9778 23:49:35.062576 Waiting for reply... done.
9779 23:49:35.062660
9780 23:49:35.066019 Sending DHCP request... done.
9781 23:49:35.066101
9782 23:49:35.066164 Waiting for reply... done.
9783 23:49:35.066224
9784 23:49:35.069167 My ip is 192.168.201.16
9785 23:49:35.069253
9786 23:49:35.072315 The DHCP server ip is 192.168.201.1
9787 23:49:35.072389
9788 23:49:35.075910 TFTP server IP predefined by user: 192.168.201.1
9789 23:49:35.075987
9790 23:49:35.082343 Bootfile predefined by user: 14084309/tftp-deploy-w6qgyi4y/kernel/image.itb
9791 23:49:35.082418
9792 23:49:35.085563 Sending tftp read request... done.
9793 23:49:35.085654
9794 23:49:35.089798 Waiting for the transfer...
9795 23:49:35.089879
9796 23:49:35.344456 00000000 ################################################################
9797 23:49:35.344604
9798 23:49:35.592697 00080000 ################################################################
9799 23:49:35.592832
9800 23:49:35.843528 00100000 ################################################################
9801 23:49:35.843658
9802 23:49:36.087983 00180000 ################################################################
9803 23:49:36.088131
9804 23:49:36.334145 00200000 ################################################################
9805 23:49:36.334310
9806 23:49:36.584662 00280000 ################################################################
9807 23:49:36.584811
9808 23:49:36.832107 00300000 ################################################################
9809 23:49:36.832254
9810 23:49:37.080505 00380000 ################################################################
9811 23:49:37.080665
9812 23:49:37.327612 00400000 ################################################################
9813 23:49:37.327788
9814 23:49:37.578284 00480000 ################################################################
9815 23:49:37.578428
9816 23:49:37.828817 00500000 ################################################################
9817 23:49:37.828952
9818 23:49:38.086803 00580000 ################################################################
9819 23:49:38.086962
9820 23:49:38.360058 00600000 ################################################################
9821 23:49:38.360201
9822 23:49:38.619640 00680000 ################################################################
9823 23:49:38.619830
9824 23:49:38.871059 00700000 ################################################################
9825 23:49:38.871218
9826 23:49:39.129865 00780000 ################################################################
9827 23:49:39.130006
9828 23:49:39.385702 00800000 ################################################################
9829 23:49:39.385841
9830 23:49:39.635514 00880000 ################################################################
9831 23:49:39.635645
9832 23:49:39.886545 00900000 ################################################################
9833 23:49:39.886675
9834 23:49:40.141854 00980000 ################################################################
9835 23:49:40.141986
9836 23:49:40.400736 00a00000 ################################################################
9837 23:49:40.400864
9838 23:49:40.667004 00a80000 ################################################################
9839 23:49:40.667134
9841 23:53:56.355152 end: 2.2.4 bootloader-commands (duration 00:04:26) [common]
9843 23:53:56.356171 depthcharge-retry failed: 1 of 1 attempts. 'bootloader-commands timed out after 266 seconds'
9845 23:53:56.357357 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
9848 23:53:56.359231 end: 2 depthcharge-action (duration 00:05:00) [common]
9850 23:53:56.360719 Cleaning after the job
9851 23:53:56.361192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/ramdisk
9852 23:53:56.385775 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/kernel
9853 23:53:56.410540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/dtb
9854 23:53:56.410812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084309/tftp-deploy-w6qgyi4y/modules
9855 23:53:56.417565 start: 4.1 power-off (timeout 00:00:30) [common]
9856 23:53:56.417756 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
9857 23:53:56.491482 >> Command sent successfully.
9858 23:53:56.502762 Returned 0 in 0 seconds
9859 23:53:56.604173 end: 4.1 power-off (duration 00:00:00) [common]
9861 23:53:56.605769 start: 4.2 read-feedback (timeout 00:10:00) [common]
9862 23:53:56.607047 Listened to connection for namespace 'common' for up to 1s
9863 23:53:57.607689 Finalising connection for namespace 'common'
9864 23:53:57.608361 Disconnecting from shell: Finalise
9865 23:53:57.608749 00b00000 ###########################################
9866 23:53:57.709787 end: 4.2 read-feedback (duration 00:00:01) [common]
9867 23:53:57.710580 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084309
9868 23:53:57.835166 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084309
9869 23:53:57.835359 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.