[Enter `^Ec?' for help] F0: 102B 0000 F3: 1001 0000 [0200] F3: 1001 0000 F7: 102D 0000 F1: 0000 0000 V0: 0000 0000 [0001] 00: 0007 8000 01: 0000 0000 BP: 0C00 0209 [0000] G0: 1182 0000 EC: 0000 0021 [4000] S7: 0000 0000 [0000] CC: 0000 0000 [0001] T0: 0000 0040 [010F] Jump to BL coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal Backing address range [0x00000000:0x40000000) with new page table @0x0010f000 Backing address range [0x00000000:0x00200000) with new page table @0x00110000 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal Backing address range [0x00200000:0x00400000) with new page table @0x00111000 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal WDT: Last reset was cold boot SPI1(PAD0) initialized at 2873684 Hz SPI5(PAD0) initialized at 992727 Hz VBOOT: Loading verstage. SF: Detected 00 0000 with sector size 0x1000, total 0x800000 FMAP: Found "FLASH" version 1.1 at 0x20000. FMAP: base = 0x0 size = 0x800000 #areas = 25 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception FMAP: area RW_NVRAM found @ 57b000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 Phase 1 FMAP: area GBB found @ 3f5000 (12032 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps BS: bootblock times (exec / console): total (unknown) / 148 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception pmic_efuse_setting: Set efuses in 11 msecs pmwrap_interface_init: Select PMIF_VLD_RDY [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1a [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2 [RTC]rtc_osc_init,62: osc32con val = 0xde70 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a [RTC]rtc_get_frequency_meter,154: input=15, output=764 [RTC]rtc_get_frequency_meter,154: input=23, output=949 [RTC]rtc_get_frequency_meter,154: input=19, output=857 [RTC]rtc_get_frequency_meter,154: input=17, output=811 [RTC]rtc_get_frequency_meter,154: input=16, output=788 [RTC]rtc_get_frequency_meter,154: input=16, output=788 [RTC]rtc_get_frequency_meter,154: input=17, output=811 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81 ADC[4]: Raw value=670063 ID=5 ADC[3]: Raw value=212549 ID=1 RAM Code: 0x51 FMAP: area COREBOOT found @ 21000 (4014080 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 MRC: failed to locate region type 0. DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0) DRAM-K: Running full calibration DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2 header.status = 0x0 header.version = 0x6 (expected: 0x6) header.size = 0xd00 (expected: 0xd00) header.flags = 0x0 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6 dram_init: ddr_geometry: 0 [EMI] MDL number = 0 [EMI] Get MDL freq = 0 dram_init: ddr_type: 0 is_discrete_lpddr4: 1 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0 [Bian_co] ETT version 0.0.0.1 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6 dramc_set_vcore_voltage set vcore to 650000 Read voltage for 800, 4 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 dram_init: config_dvfs: 1 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9 MEM_TYPE=3, freq_sel=18 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1600 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 800 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1600,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 40 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 12 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) [EMI DOE] emi_dcm 0 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 35 (5~66) winsize 62 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 3 PI (21 cell) CA1 delay=37 (7~68),Diff = 3 PI (21 cell) CA2 delay=35 (5~66),Diff = 1 PI (7 cell) CA3 delay=35 (4~66),Diff = 1 PI (7 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (3~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 6 (0~37) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 35 (4~66) winsize 63 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 3 PI (21 cell) CA1 delay=37 (7~68),Diff = 3 PI (21 cell) CA2 delay=35 (5~66),Diff = 1 PI (7 cell) CA3 delay=35 (4~66),Diff = 1 PI (7 cell) CA4 delay=34 (4~64),Diff = 0 PI (0 cell) CA5 delay=34 (3~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 6 (0~37) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0) 0 6 4 | B1->B0 | 2a2a 2525 | 0 0 | (1 0) (1 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 3939 4141 | 0 0 | (1 1) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 2) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 2) best DQS0 dly(MCK, UI, PI) = (0, 10, 2) best DQS1 dly(MCK, UI, PI) = (0, 10, 2) best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 82, DQM1 = 75 DQ Delay: DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6) Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=27, winSum=443 TX Vref=24, minBit 1, minWin=27, winSum=445 TX Vref=26, minBit 3, minWin=27, winSum=448 TX Vref=28, minBit 3, minWin=27, winSum=453 TX Vref=30, minBit 0, minWin=28, winSum=454 TX Vref=32, minBit 0, minWin=28, winSum=453 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6) Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -111 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Final RX Vref Byte 0 = 52 to rank0 Final RX Vref Byte 1 = 55 to rank0 Final RX Vref Byte 0 = 52 to rank1 Final RX Vref Byte 1 = 55 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 83, DQM1 = 73 DQ Delay: DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps CH0 RK0: MR19=606, MR18=3636 CH0_RK0: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0) 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (1 1) (1 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2828 3030 | 1 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 0) best DQS0 dly(MCK, UI, PI) = (0, 10, 0) best DQS1 dly(MCK, UI, PI) = (0, 10, 0) best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 83, DQM1 = 74 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =69 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6) Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=27, winSum=442 TX Vref=24, minBit 0, minWin=28, winSum=453 TX Vref=26, minBit 0, minWin=28, winSum=455 TX Vref=28, minBit 0, minWin=28, winSum=454 TX Vref=30, minBit 2, minWin=28, winSum=458 TX Vref=32, minBit 2, minWin=28, winSum=459 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 32 Final TX Range 1 Vref 32 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6) Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -111 -> 252, step: 8 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 85, DQM1 = 74 DQ Delay: DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps CH0 RK1: MR19=606, MR18=4242 CH0_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 36 (6~67) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 4 PI (28 cell) CA1 delay=36 (6~67),Diff = 3 PI (21 cell) CA2 delay=34 (4~65),Diff = 1 PI (7 cell) CA3 delay=34 (4~65),Diff = 1 PI (7 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 4 PI (28 cell) CA1 delay=36 (6~67),Diff = 3 PI (21 cell) CA2 delay=34 (4~65),Diff = 1 PI (7 cell) CA3 delay=34 (4~65),Diff = 1 PI (7 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 25 => 25 Write leveling (Byte 1): 25 => 25 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 28) 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 0) best DQS0 dly(MCK, UI, PI) = (0, 9, 28) best DQS1 dly(MCK, UI, PI) = (0, 10, 0) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28) best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 85, DQM1 = 74 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 3, minWin=27, winSum=447 TX Vref=24, minBit 3, minWin=27, winSum=450 TX Vref=26, minBit 3, minWin=27, winSum=453 TX Vref=28, minBit 0, minWin=28, winSum=457 TX Vref=30, minBit 1, minWin=28, winSum=461 TX Vref=32, minBit 9, minWin=27, winSum=454 [TxChooseVref] Worse bit 1, Min win 28, Win sum 461, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -111 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Set Vref, RX VrefLevel [Byte0]: 76 [Byte1]: 76 Final RX Vref Byte 0 = 58 to rank0 Final RX Vref Byte 1 = 54 to rank0 Final RX Vref Byte 0 = 58 to rank1 Final RX Vref Byte 1 = 54 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 81, DQM1 = 75 DQ Delay: DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps CH1 RK0: MR19=606, MR18=4F4F CH1_RK0: MR19=0x606, MR18=0x4F4F, DQSOSC=390, MR23=63, INC=97, DEC=64 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 26) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 28) best DQS0 dly(MCK, UI, PI) = (0, 9, 26) best DQS1 dly(MCK, UI, PI) = (0, 9, 28) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 85, DQM1 = 73 DQ Delay: DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 0, minWin=27, winSum=449 TX Vref=24, minBit 0, minWin=27, winSum=449 TX Vref=26, minBit 0, minWin=27, winSum=454 TX Vref=28, minBit 9, minWin=27, winSum=453 TX Vref=30, minBit 9, minWin=27, winSum=456 TX Vref=32, minBit 9, minWin=27, winSum=453 [TxChooseVref] Worse bit 9, Min win 27, Win sum 456, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6) Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -111 -> 252, step: 8 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 84, DQM1 = 74 DQ Delay: DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =80 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps CH1 RK1: MR19=606, MR18=4040 CH1_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1600 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [GetDramInforAfterCalByMRR] Vendor 6. [GetDramInforAfterCalByMRR] Revision 606. [GetDramInforAfterCalByMRR] Revision 2 0. MR0 0x3939 MR8 0x1111 RK0, DieNum 1, Density 16Gb, RKsize 16Gb. MR0 0x3939 MR8 0x1111 RK1, DieNum 1, Density 16Gb, RKsize 16Gb. [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc [FAST_K] Save calibration result to emmc dram_init: config_dvfs: 1 dramc_set_vcore_voltage set vcore to 662500 Read voltage for 1200, 2 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=15 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 2400 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 17 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1200 CA_MCKIO = 1200 MCKIO_SEMI = 0 PLL_FREQ = 2366 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 2400,PCW = 0X5b00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:2 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 12 [0] MIN Duty = 4938%(X100), DQS PI = 54 [0] AVG Duty = 5015%(X100) CH0 CLK Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 28 [0] MIN Duty = 5031%(X100), DQS PI = 4 [0] AVG Duty = 5078%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 52 [0] MIN Duty = 4906%(X100), DQS PI = 14 [0] AVG Duty = 4968%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 94% CH0 DQS 1 Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 22 [0] MIN Duty = 4969%(X100), DQS PI = 40 [0] AVG Duty = 5062%(X100) ==DQM 1 == Final DQM duty delay cell = 4 [4] MAX Duty = 5187%(X100), DQS PI = 54 [4] MIN Duty = 5000%(X100), DQS PI = 18 [4] AVG Duty = 5093%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 187% CH0 DQM 1 Duty spec in!! Max-Min= 187% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 16 [-4] MIN Duty = 4813%(X100), DQS PI = 8 [-4] AVG Duty = 4937%(X100) ==DQ 1 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 6 [-4] MIN Duty = 4907%(X100), DQS PI = 0 [-4] AVG Duty = 4984%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 249% CH0 DQ 1 Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:5 CA:-5 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5094%(X100), DQS PI = 24 [0] MIN Duty = 4875%(X100), DQS PI = 46 [0] AVG Duty = 4984%(X100) CH1 CLK Duty spec in!! Max-Min= 219% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 16 [0] MIN Duty = 4875%(X100), DQS PI = 40 [0] AVG Duty = 5000%(X100) ==DQS 1 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 18 [-4] MIN Duty = 4907%(X100), DQS PI = 44 [-4] AVG Duty = 4953%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 250% CH1 DQS 1 Duty spec in!! Max-Min= 93% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5093%(X100), DQS PI = 32 [-4] MIN Duty = 4875%(X100), DQS PI = 38 [-4] AVG Duty = 4984%(X100) ==DQM 1 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5094%(X100), DQS PI = 20 [-4] MIN Duty = 4906%(X100), DQS PI = 44 [-4] AVG Duty = 5000%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 218% CH1 DQM 1 Duty spec in!! Max-Min= 188% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5062%(X100), DQS PI = 0 [0] MIN Duty = 4969%(X100), DQS PI = 42 [0] AVG Duty = 5015%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 8 [0] MIN Duty = 4907%(X100), DQS PI = 0 [0] AVG Duty = 4969%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 93% CH1 DQ 1 Duty spec in!! Max-Min= 124% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 6 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 39 (9~70) winsize 62 [CA 1] Center 39 (8~70) winsize 63 [CA 2] Center 36 (5~67) winsize 63 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 34 (3~65) winsize 63 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (9~70),Diff = 5 PI (24 cell) CA1 delay=39 (8~70),Diff = 5 PI (24 cell) CA2 delay=36 (5~67),Diff = 2 PI (9 cell) CA3 delay=35 (4~66),Diff = 1 PI (4 cell) CA4 delay=34 (3~65),Diff = 0 PI (0 cell) CA5 delay=34 (3~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 39 (8~70) winsize 63 [CA 1] Center 39 (8~70) winsize 63 [CA 2] Center 35 (5~66) winsize 62 [CA 3] Center 35 (4~66) winsize 63 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (9~70),Diff = 6 PI (28 cell) CA1 delay=39 (8~70),Diff = 6 PI (28 cell) CA2 delay=35 (5~66),Diff = 2 PI (9 cell) CA3 delay=35 (4~66),Diff = 2 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=34 (3~65),Diff = 1 PI (4 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 7 (0~39) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0) 0 11 20 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (1 1) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 20) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 20) best DQS0 dly(MCK, UI, PI) = (0, 15, 20) best DQS1 dly(MCK, UI, PI) = (0, 15, 20) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 106 DQ Delay: DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123 DQ8 =95, DQ9 =91, DQ10 =107, DQ11 =103 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7) Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6) Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 12, minWin=24, winSum=411 TX Vref=24, minBit 4, minWin=25, winSum=416 TX Vref=26, minBit 10, minWin=25, winSum=422 TX Vref=28, minBit 1, minWin=26, winSum=428 TX Vref=30, minBit 5, minWin=26, winSum=427 TX Vref=32, minBit 2, minWin=26, winSum=426 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7) Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6) Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -21 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Final RX Vref Byte 0 = 47 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 47 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 113, DQM1 = 105 DQ Delay: DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps CH0 RK0: MR19=404, MR18=808 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 27 => 27 Write leveling (Byte 1): 24 => 24 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0) 0 11 20 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (1 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 18) best DQS0 dly(MCK, UI, PI) = (0, 15, 16) best DQS1 dly(MCK, UI, PI) = (0, 15, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 114, DQM1 = 107 DQ Delay: DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7) Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6) Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 8, minWin=25, winSum=419 TX Vref=24, minBit 8, minWin=25, winSum=424 TX Vref=26, minBit 1, minWin=26, winSum=427 TX Vref=28, minBit 8, minWin=26, winSum=435 TX Vref=30, minBit 8, minWin=26, winSum=428 TX Vref=32, minBit 8, minWin=26, winSum=430 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7) Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH0 RK1 DATLAT Default: 0xc 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -21 -> 252, step: 4 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 114, DQM1 = 106 DQ Delay: DQ0 =110, DQ1 =116, DQ2 =110, DQ3 =108 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124 DQ8 =94, DQ9 =90, DQ10 =112, DQ11 =96 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =116 [DQSOSCAuto] RK1, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps CH0 RK1: MR19=404, MR18=1515 CH0_RK1: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (1~63) winsize 63 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 5 PI (24 cell) CA1 delay=37 (7~68),Diff = 5 PI (24 cell) CA2 delay=34 (4~65),Diff = 2 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (4 cell) CA4 delay=32 (1~63),Diff = 0 PI (0 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (3~65) winsize 63 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (2~62) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 5 PI (24 cell) CA1 delay=37 (7~68),Diff = 5 PI (24 cell) CA2 delay=34 (4~65),Diff = 2 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (4 cell) CA4 delay=32 (2~63),Diff = 0 PI (0 cell) CA5 delay=32 (2~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 6 (0~38) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 21 => 21 Write leveling (Byte 1): 23 => 23 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 16 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0) 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 14) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 18) best DQS0 dly(MCK, UI, PI) = (0, 15, 14) best DQS1 dly(MCK, UI, PI) = (0, 15, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 117, DQM1 = 108 DQ Delay: DQ0 =119, DQ1 =111, DQ2 =111, DQ3 =115 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6) Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6) Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 3, minWin=25, winSum=411 TX Vref=24, minBit 11, minWin=25, winSum=420 TX Vref=26, minBit 1, minWin=26, winSum=427 TX Vref=28, minBit 3, minWin=25, winSum=427 TX Vref=30, minBit 0, minWin=26, winSum=426 TX Vref=32, minBit 9, minWin=25, winSum=426 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 26 Final TX Range 1 Vref 26 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6) Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -21 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Final RX Vref Byte 0 = 51 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 51 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 105 DQ Delay: DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =112 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps CH1 RK0: MR19=404, MR18=1C1C CH1_RK0: MR19=0x404, MR18=0x1C1C, DQSOSC=399, MR23=63, INC=41, DEC=27 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 23 => 23 Write leveling (Byte 1): 22 => 22 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11) 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 11 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0) 0 11 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0) 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0) 0 12 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 15, 12) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 15, 18) best DQS0 dly(MCK, UI, PI) = (0, 15, 12) best DQS1 dly(MCK, UI, PI) = (0, 15, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12) best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 116, DQM1 = 106 DQ Delay: DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6) Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref=22, minBit 1, minWin=25, winSum=419 TX Vref=24, minBit 9, minWin=25, winSum=426 TX Vref=26, minBit 1, minWin=26, winSum=426 TX Vref=28, minBit 3, minWin=26, winSum=430 TX Vref=30, minBit 9, minWin=26, winSum=435 TX Vref=32, minBit 0, minWin=26, winSum=431 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6) Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6) == TX Byte 1 == Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6) Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6) [DATLAT] Freq=1200, CH1 RK1 DATLAT Default: 0xc 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0x0, sum = 1 12, 0x0, sum = 2 13, 0x0, sum = 3 14, 0x0, sum = 4 best_step = 12 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -29 -> 252, step: 4 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 115, DQM1 = 104 DQ Delay: DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114 DQ8 =88, DQ9 =92, DQ10 =106, DQ11 =98 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =110 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps CH1 RK1: MR19=404, MR18=B0B CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 2400 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 600, 5 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=19 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 600 CA_MCKIO = 600 MCKIO_SEMI = 0 PLL_FREQ = 2288 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1200,PCW = 0X5800 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 16 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (4~65),Diff = 1 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (4~65),Diff = 1 PI (9 cell) CA4 delay=33 (3~64),Diff = 0 PI (0 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 4 (0~35) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 30 => 30 Write leveling (Byte 1): 31 => 31 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 8 | B1->B0 | 3333 3232 | 1 1 | (0 0) (1 0) 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3030 3232 | 0 1 | (0 0) (0 0) 0 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 8) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 10) best DQS0 dly(MCK, UI, PI) = (0, 9, 8) best DQS1 dly(MCK, UI, PI) = (0, 9, 10) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 38, DQM1 = 33 DQ Delay: DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 50 Final RX Vref Byte 0 = 47 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 47 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 40, DQM1 = 31 DQ Delay: DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =52 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =20 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps CH0 RK0: MR19=808, MR18=5252 CH0_RK0: MR19=0x808, MR18=0x5252, DQSOSC=394, MR23=63, INC=168, DEC=112 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 30 => 30 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0) 0 5 8 | B1->B0 | 3434 3232 | 0 0 | (0 1) (1 1) 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 10) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 10) best DQS0 dly(MCK, UI, PI) = (0, 9, 10) best DQS1 dly(MCK, UI, PI) = (0, 9, 10) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 42, DQM1 = 33 DQ Delay: DQ0 =33, DQ1 =49, DQ2 =41, DQ3 =33 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK1 DATLAT Default: 0x8 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 41, DQM1 = 32 DQ Delay: DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps CH0 RK1: MR19=808, MR18=6E6E CH0_RK1: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 33 (3~64) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=33 (3~64),Diff = 0 PI (0 cell) CA3 delay=33 (3~64),Diff = 0 PI (0 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 4 (0~35) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 34 (4~65) winsize 62 [CA 2] Center 33 (3~64) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 3 PI (28 cell) CA1 delay=35 (5~65),Diff = 3 PI (28 cell) CA2 delay=33 (3~64),Diff = 1 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (9 cell) CA4 delay=32 (2~63),Diff = 0 PI (0 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 4 (0~35) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1) 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0) 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 8) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 8) best DQS0 dly(MCK, UI, PI) = (0, 9, 8) best DQS1 dly(MCK, UI, PI) = (0, 9, 8) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 39, DQM1 = 30 DQ Delay: DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6) Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6) Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6) Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6) Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 48 Final RX Vref Byte 0 = 51 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 51 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 37, DQM1 = 31 DQ Delay: DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40 [DQSOSCAuto] RK0, (LSB)MR18= 0x7777, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps CH1 RK0: MR19=808, MR18=7777 CH1_RK0: MR19=0x808, MR18=0x7777, DQSOSC=387, MR23=63, INC=175, DEC=116 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5) 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1) 0 5 8 | B1->B0 | 3030 2626 | 1 0 | (1 0) (0 0) 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0) 0 6 8 | B1->B0 | 3838 4242 | 0 1 | (0 0) (0 0) 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 9, 2) 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 9, 6) best DQS0 dly(MCK, UI, PI) = (0, 9, 2) best DQS1 dly(MCK, UI, PI) = (0, 9, 6) best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2) best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 42, DQM1 = 37 DQ Delay: DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK1 DATLAT Default: 0x8 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0x0, sum = 1 8, 0x0, sum = 2 9, 0x0, sum = 3 10, 0x0, sum = 4 best_step = 8 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -195 -> 252, step: 8 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 38, DQM1 = 30 DQ Delay: DQ0 =40, DQ1 =32, DQ2 =32, DQ3 =32 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps CH1 RK1: MR19=808, MR18=6060 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 662500 Read voltage for 933, 3 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=17 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1866 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 933 CA_MCKIO = 933 MCKIO_SEMI = 0 PLL_FREQ = 3732 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1866,PCW = 0X8f00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 8 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 39 (8~70) winsize 63 [CA 1] Center 38 (8~69) winsize 62 [CA 2] Center 36 (6~67) winsize 62 [CA 3] Center 36 (6~67) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~65) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (8~70),Diff = 5 PI (31 cell) CA1 delay=38 (8~69),Diff = 4 PI (24 cell) CA2 delay=36 (6~67),Diff = 2 PI (12 cell) CA3 delay=36 (6~67),Diff = 2 PI (12 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 38 (8~69) winsize 62 [CA 1] Center 38 (8~69) winsize 62 [CA 2] Center 36 (6~67) winsize 62 [CA 3] Center 36 (6~66) winsize 61 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~65) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=38 (8~69),Diff = 4 PI (24 cell) CA1 delay=38 (8~69),Diff = 4 PI (24 cell) CA2 delay=36 (6~67),Diff = 2 PI (12 cell) CA3 delay=36 (6~66),Diff = 2 PI (12 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 7 (0~39) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 20 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1) 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 20) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 20) best DQS0 dly(MCK, UI, PI) = (0, 14, 20) best DQS1 dly(MCK, UI, PI) = (0, 14, 20) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 87 DQ Delay: DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2) Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2) Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 50 Final RX Vref Byte 0 = 47 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 47 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 97, DQM1 = 88 DQ Delay: DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =94 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78 DQ12 =94, DQ13 =96, DQ14 =100, DQ15 =98 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps CH0 RK0: MR19=505, MR18=2424 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 20 | B1->B0 | 3333 2f2f | 1 1 | (0 1) (1 0) 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 3030 3737 | 0 1 | (0 0) (0 0) 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 18) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 20) best DQS0 dly(MCK, UI, PI) = (0, 14, 18) best DQS1 dly(MCK, UI, PI) = (0, 14, 20) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200 iDelay=200, Bit 1, Center 95 (-8 ~ 199) 208 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200 iDelay=200, Bit 5, Center 91 (-8 ~ 191) 200 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184 iDelay=200, Bit 9, Center 67 (-32 ~ 167) 200 iDelay=200, Bit 10, Center 87 (-16 ~ 191) 208 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200 iDelay=200, Bit 15, Center 91 (-8 ~ 191) 200 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 85 DQ Delay: DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =103 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79 DQ12 =99, DQ13 =91, DQ14 =91, DQ15 =91 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2) Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2) Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -77 -> 252, step: 4 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192 iDelay=199, Bit 2, Center 98 (7 ~ 190) 184 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176 iDelay=199, Bit 4, Center 104 (15 ~ 194) 180 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 98, DQM1 = 86 DQ Delay: DQ0 =94, DQ1 =98, DQ2 =98, DQ3 =94 DQ4 =104, DQ5 =88, DQ6 =102, DQ7 =106 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps CH0 RK1: MR19=505, MR18=2E2E CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (3~65) winsize 63 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 33 (2~64) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 4 PI (24 cell) CA1 delay=37 (6~68),Diff = 4 PI (24 cell) CA2 delay=34 (4~65),Diff = 1 PI (6 cell) CA3 delay=34 (3~65),Diff = 1 PI (6 cell) CA4 delay=33 (2~64),Diff = 0 PI (0 cell) CA5 delay=33 (2~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 33 (3~63) winsize 61 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 5 PI (31 cell) CA1 delay=37 (6~68),Diff = 5 PI (31 cell) CA2 delay=34 (4~65),Diff = 2 PI (12 cell) CA3 delay=33 (3~64),Diff = 1 PI (6 cell) CA4 delay=33 (3~63),Diff = 1 PI (6 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~37) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 23 => 23 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1) 0 10 20 | B1->B0 | 3333 2626 | 1 0 | (1 0) (1 0) 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 2929 4545 | 0 0 | (1 1) (0 0) 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 16) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 20) best DQS0 dly(MCK, UI, PI) = (0, 14, 16) best DQS1 dly(MCK, UI, PI) = (0, 14, 20) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 87 DQ Delay: DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =75 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2) Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2) Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 48 Final RX Vref Byte 0 = 51 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 51 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 94, DQM1 = 88 DQ Delay: DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =90 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps CH1 RK0: MR19=505, MR18=3939 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 23 => 23 Write leveling (Byte 1): 24 => 24 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1) 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0) 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 14) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 16) best DQS0 dly(MCK, UI, PI) = (0, 14, 14) best DQS1 dly(MCK, UI, PI) = (0, 14, 16) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 94, DQM1 = 86 DQ Delay: DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =91 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2) Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2) Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -69 -> 252, step: 4 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 87 DQ Delay: DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps CH1 RK1: MR19=505, MR18=2525 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1866 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 400, 6 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=20 sv_algorithm_assistance_LP4_800 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 800 CKR = 1 DQ_P2S_RATIO = 4 =================================== CA_P2S_RATIO = 4 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 1 CA_SEMI_OPEN = 1 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 4 DQ_AAMCK_DIV = 0 CA_AAMCK_DIV = 0 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 400 MCKIO_SEMI = 400 PLL_FREQ = 3016 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 32 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 800,PCW = 0X7400 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 0 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 18 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 39 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == Write leveling (Byte 0): 32 => 0 Write leveling (Byte 1): 32 => 0 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 51, DQS1 = 59 DQM Delay: DQM0 = 12, DQM1 = 16 DQ Delay: DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) [DATLAT] Freq=400, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 50 Final RX Vref Byte 0 = 47 to rank0 Final RX Vref Byte 1 = 50 to rank0 Final RX Vref Byte 0 = 47 to rank1 Final RX Vref Byte 1 = 50 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 52, DQS1 = 68 DQM Delay: DQM0 = 10, DQM1 = 17 DQ Delay: DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps CH0 RK0: MR19=C0C, MR18=A9A9 CH0_RK0: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 43, DQS1 = 59 DQM Delay: DQM0 = 7, DQM1 = 15 DQ Delay: DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH0 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 52, DQS1 = 64 DQM Delay: DQM0 = 9, DQM1 = 14 DQ Delay: DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24 [DQSOSCAuto] RK1, (LSB)MR18= 0xbaba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps CH0 RK1: MR19=C0C, MR18=BABA CH0_RK1: MR19=0xC0C, MR18=0xBABA, DQSOSC=386, MR23=63, INC=396, DEC=264 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == Write leveling (Byte 0): 32 => 0 Write leveling (Byte 1): 32 => 0 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 16) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 16) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 43, DQS1 = 59 DQM Delay: DQM0 = 6, DQM1 = 15 DQ Delay: DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) == TX Byte 1 == Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2) Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2) [DATLAT] Freq=400, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 48 Final RX Vref Byte 0 = 51 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 51 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 48, DQS1 = 64 DQM Delay: DQM0 = 9, DQM1 = 16 DQ Delay: DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps CH1 RK0: MR19=C0C, MR18=D4D4 CH1_RK0: MR19=0xC0C, MR18=0xD4D4, DQSOSC=383, MR23=63, INC=402, DEC=268 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 10, 8) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 10, 16) best DQS0 dly(MCK, UI, PI) = (0, 10, 8) best DQS1 dly(MCK, UI, PI) = (0, 10, 16) best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8) best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 35, DQS1 = 59 DQM Delay: DQM0 = 3, DQM1 = 17 DQ Delay: DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3) Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH1 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -359 -> 252, step: 8 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2 == DQS Delay: DQS0 = 48, DQS1 = 64 DQM Delay: DQM0 = 10, DQM1 = 15 DQ Delay: DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =12 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps CH1 RK1: MR19=C0C, MR18=B0B0 CH1_RK1: MR19=0xC0C, MR18=0xB0B0, DQSOSC=387, MR23=63, INC=394, DEC=262 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 800 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=13 sv_algorithm_assistance_LP4_3733 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 0 NEW_8X_MODE = 1 =================================== =================================== data_rate = 3200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 12 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1600 CA_MCKIO = 1600 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 3200,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:2 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 22 [0] MIN Duty = 4938%(X100), DQS PI = 52 [0] AVG Duty = 5047%(X100) CH0 CLK Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 32 [0] MIN Duty = 5031%(X100), DQS PI = 8 [0] AVG Duty = 5078%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 6 [0] MIN Duty = 4876%(X100), DQS PI = 18 [0] AVG Duty = 4953%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 94% CH0 DQS 1 Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 24 [0] MIN Duty = 4907%(X100), DQS PI = 44 [0] AVG Duty = 5047%(X100) ==DQM 1 == Final DQM duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 52 [0] MIN Duty = 4782%(X100), DQS PI = 14 [0] AVG Duty = 4906%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 280% CH0 DQM 1 Duty spec in!! Max-Min= 249% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5218%(X100), DQS PI = 18 [0] MIN Duty = 4938%(X100), DQS PI = 54 [0] AVG Duty = 5078%(X100) ==DQ 1 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 4 [-4] MIN Duty = 4844%(X100), DQS PI = 34 [-4] AVG Duty = 4953%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 280% CH0 DQ 1 Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Duty_Offset_Calibration] B0:0 B1:5 CA:-5 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 20 [0] MIN Duty = 4906%(X100), DQS PI = 52 [0] AVG Duty = 5031%(X100) CH1 CLK Duty spec in!! Max-Min= 250% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 20 [0] MIN Duty = 4875%(X100), DQS PI = 44 [0] AVG Duty = 5031%(X100) ==DQS 1 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 18 [-4] MIN Duty = 4844%(X100), DQS PI = 40 [-4] AVG Duty = 4922%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 312% CH1 DQS 1 Duty spec in!! Max-Min= 156% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 34 [-4] MIN Duty = 4782%(X100), DQS PI = 44 [-4] AVG Duty = 4922%(X100) ==DQM 1 == Final DQM duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 12 [-4] MIN Duty = 4907%(X100), DQS PI = 36 [-4] AVG Duty = 4984%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 280% CH1 DQM 1 Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 20 [0] MIN Duty = 4938%(X100), DQS PI = 48 [0] AVG Duty = 5015%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5062%(X100), DQS PI = 6 [0] MIN Duty = 4907%(X100), DQS PI = 22 [0] AVG Duty = 4984%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 155% CH1 DQ 1 Duty spec in!! Max-Min= 155% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 4 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2) [MiockJmeterHQA] [DramcMiockJmeter] u1RxGatingPI = 0 0 : 4363, 4138 4 : 4252, 4027 8 : 4363, 4138 12 : 4368, 4140 16 : 4368, 4140 20 : 4363, 4138 24 : 4253, 4026 28 : 4252, 4027 32 : 4363, 4137 36 : 4252, 4027 40 : 4253, 4027 44 : 4252, 4027 48 : 4252, 4027 52 : 4250, 4027 56 : 4250, 4026 60 : 4250, 4027 64 : 4360, 4137 68 : 4250, 4027 72 : 4250, 4026 76 : 4250, 4027 80 : 4250, 4027 84 : 4361, 4137 88 : 4250, 4027 92 : 4363, 4140 96 : 4250, 4027 100 : 4250, 1875 104 : 4363, 0 108 : 4250, 0 112 : 4250, 0 116 : 4363, 0 120 : 4361, 0 124 : 4253, 0 128 : 4250, 0 132 : 4250, 0 136 : 4252, 0 140 : 4361, 0 144 : 4250, 0 148 : 4250, 0 152 : 4360, 0 156 : 4361, 0 160 : 4251, 0 164 : 4250, 0 168 : 4250, 0 172 : 4366, 0 176 : 4250, 0 180 : 4361, 0 184 : 4250, 0 188 : 4250, 0 192 : 4250, 0 196 : 4250, 0 200 : 4252, 0 204 : 4360, 0 208 : 4366, 0 212 : 4250, 0 216 : 4250, 0 220 : 4250, 673 224 : 4252, 4007 228 : 4250, 4027 232 : 4250, 4027 236 : 4250, 4027 240 : 4250, 4027 244 : 4252, 4030 248 : 4250, 4027 252 : 4363, 4140 256 : 4250, 4027 260 : 4252, 4030 264 : 4250, 4026 268 : 4363, 4140 272 : 4361, 4137 276 : 4250, 4027 280 : 4364, 4140 284 : 4252, 4029 288 : 4250, 4026 292 : 4250, 4027 296 : 4252, 4029 300 : 4250, 4027 304 : 4364, 4140 308 : 4250, 4027 312 : 4253, 4029 316 : 4250, 4027 320 : 4361, 4138 324 : 4361, 4137 328 : 4250, 4026 332 : 4250, 4026 336 : 4253, 3841 340 : 4250, 1713 MIOCK jitter meter ch=0 1T = (340-100) = 240 dly cells Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 41 (11~72) winsize 62 [CA 1] Center 41 (11~72) winsize 62 [CA 2] Center 37 (7~67) winsize 61 [CA 3] Center 37 (7~67) winsize 61 [CA 4] Center 35 (5~66) winsize 62 [CA 5] Center 35 (5~65) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=41 (11~72),Diff = 6 PI (21 cell) CA1 delay=41 (11~72),Diff = 6 PI (21 cell) CA2 delay=37 (7~67),Diff = 2 PI (7 cell) CA3 delay=37 (7~67),Diff = 2 PI (7 cell) CA4 delay=35 (5~66),Diff = 0 PI (0 cell) CA5 delay=35 (5~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=35 [CBTSetCACLKResult] CA Dly = 35 CS Dly: 11 (0~42) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~73) winsize 62 [CA 1] Center 42 (12~73) winsize 62 [CA 2] Center 38 (9~68) winsize 60 [CA 3] Center 37 (8~67) winsize 60 [CA 4] Center 36 (6~66) winsize 61 [CA 5] Center 36 (6~66) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=42 (12~72),Diff = 7 PI (25 cell) CA1 delay=42 (12~72),Diff = 7 PI (25 cell) CA2 delay=38 (9~67),Diff = 3 PI (10 cell) CA3 delay=37 (8~67),Diff = 2 PI (7 cell) CA4 delay=36 (6~66),Diff = 1 PI (3 cell) CA5 delay=35 (6~65),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=35 [CBTSetCACLKResult] CA Dly = 35 CS Dly: 11 (0~42) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0) 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1) 0 12 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1) 0 13 4 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 3131 4545 | 0 0 | (1 1) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 30) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 6) best DQS0 dly(MCK, UI, PI) = (1, 0, 30) best DQS1 dly(MCK, UI, PI) = (1, 1, 6) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 130, DQM1 = 124 DQ Delay: DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3) Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3) Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 8, minWin=22, winSum=376 TX Vref=18, minBit 4, minWin=23, winSum=387 TX Vref=20, minBit 8, minWin=23, winSum=392 TX Vref=22, minBit 8, minWin=23, winSum=398 TX Vref=24, minBit 8, minWin=24, winSum=410 TX Vref=26, minBit 9, minWin=24, winSum=410 TX Vref=28, minBit 8, minWin=24, winSum=417 TX Vref=30, minBit 3, minWin=25, winSum=415 TX Vref=32, minBit 1, minWin=24, winSum=404 TX Vref=34, minBit 8, minWin=23, winSum=390 [TxChooseVref] Worse bit 3, Min win 25, Win sum 415, Final Vref 30 Final TX Range 0 Vref 30 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=10 cells (3 PI) u2DelayCellOfst[1]=18 cells (5 PI) u2DelayCellOfst[2]=14 cells (4 PI) u2DelayCellOfst[3]=10 cells (3 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=18 cells (5 PI) u2DelayCellOfst[7]=18 cells (5 PI) Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3) Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=3 cells (1 PI) u2DelayCellOfst[9]=0 cells (0 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=7 cells (2 PI) u2DelayCellOfst[12]=14 cells (4 PI) u2DelayCellOfst[13]=18 cells (5 PI) u2DelayCellOfst[14]=21 cells (6 PI) u2DelayCellOfst[15]=18 cells (5 PI) Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3) Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8FFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 11 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Final RX Vref Byte 0 = 53 to rank0 Final RX Vref Byte 1 = 57 to rank0 Final RX Vref Byte 0 = 53 to rank1 Final RX Vref Byte 1 = 57 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 126, DQM1 = 121 DQ Delay: DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps CH0 RK0: MR19=303, MR18=1919 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0) 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1) 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0) 0 13 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0) 0 13 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 2525 4343 | 0 1 | (0 0) (0 0) 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 30) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 2) best DQS0 dly(MCK, UI, PI) = (1, 0, 30) best DQS1 dly(MCK, UI, PI) = (1, 1, 2) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 132, DQM1 = 125 DQ Delay: DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3) Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 0, minWin=23, winSum=379 TX Vref=18, minBit 1, minWin=23, winSum=388 TX Vref=20, minBit 1, minWin=23, winSum=395 TX Vref=22, minBit 1, minWin=24, winSum=405 TX Vref=24, minBit 0, minWin=25, winSum=412 TX Vref=26, minBit 1, minWin=25, winSum=416 TX Vref=28, minBit 7, minWin=25, winSum=422 TX Vref=30, minBit 8, minWin=24, winSum=417 TX Vref=32, minBit 8, minWin=24, winSum=412 TX Vref=34, minBit 8, minWin=23, winSum=398 [TxChooseVref] Worse bit 7, Min win 25, Win sum 422, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=14 cells (4 PI) u2DelayCellOfst[1]=18 cells (5 PI) u2DelayCellOfst[2]=14 cells (4 PI) u2DelayCellOfst[3]=14 cells (4 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=18 cells (5 PI) u2DelayCellOfst[7]=18 cells (5 PI) Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=3 cells (1 PI) u2DelayCellOfst[9]=0 cells (0 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=7 cells (2 PI) u2DelayCellOfst[12]=14 cells (4 PI) u2DelayCellOfst[13]=14 cells (4 PI) u2DelayCellOfst[14]=18 cells (5 PI) u2DelayCellOfst[15]=14 cells (4 PI) Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3) Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8FFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 11 -> 252, step: 4 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 128, DQM1 = 121 DQ Delay: DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x5151, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps CH0 RK1: MR19=303, MR18=2121 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 41 (11~71) winsize 61 [CA 1] Center 40 (10~70) winsize 61 [CA 2] Center 36 (6~66) winsize 61 [CA 3] Center 35 (6~65) winsize 60 [CA 4] Center 33 (3~63) winsize 61 [CA 5] Center 33 (4~63) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=41 (11~71),Diff = 8 PI (28 cell) CA1 delay=40 (10~70),Diff = 7 PI (25 cell) CA2 delay=36 (6~66),Diff = 3 PI (10 cell) CA3 delay=35 (6~65),Diff = 2 PI (7 cell) CA4 delay=33 (3~63),Diff = 0 PI (0 cell) CA5 delay=33 (4~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 9 (0~40) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 41 (11~71) winsize 61 [CA 1] Center 40 (10~71) winsize 62 [CA 2] Center 36 (7~66) winsize 60 [CA 3] Center 36 (7~65) winsize 59 [CA 4] Center 34 (4~64) winsize 61 [CA 5] Center 34 (4~64) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 271/100 ps CA0 delay=41 (11~71),Diff = 8 PI (28 cell) CA1 delay=40 (10~70),Diff = 7 PI (25 cell) CA2 delay=36 (7~66),Diff = 3 PI (10 cell) CA3 delay=36 (7~65),Diff = 3 PI (10 cell) CA4 delay=33 (4~63),Diff = 0 PI (0 cell) CA5 delay=33 (4~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 9 (0~40) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 23 => 23 Write leveling (Byte 1): 22 => 22 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1) 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0) 0 13 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (1 0) 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 28) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 1, 0) best DQS0 dly(MCK, UI, PI) = (1, 0, 28) best DQS1 dly(MCK, UI, PI) = (1, 1, 0) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28) best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 130, DQM1 = 125 DQ Delay: DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3) Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 3, minWin=21, winSum=366 TX Vref=18, minBit 0, minWin=21, winSum=376 TX Vref=20, minBit 3, minWin=22, winSum=383 TX Vref=22, minBit 3, minWin=23, winSum=395 TX Vref=24, minBit 0, minWin=24, winSum=404 TX Vref=26, minBit 3, minWin=24, winSum=409 TX Vref=28, minBit 0, minWin=25, winSum=410 TX Vref=30, minBit 0, minWin=25, winSum=409 TX Vref=32, minBit 3, minWin=23, winSum=398 TX Vref=34, minBit 1, minWin=23, winSum=386 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=14 cells (4 PI) u2DelayCellOfst[1]=10 cells (3 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=7 cells (2 PI) u2DelayCellOfst[4]=7 cells (2 PI) u2DelayCellOfst[5]=14 cells (4 PI) u2DelayCellOfst[6]=14 cells (4 PI) u2DelayCellOfst[7]=7 cells (2 PI) Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=7 cells (2 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=18 cells (5 PI) u2DelayCellOfst[13]=18 cells (5 PI) u2DelayCellOfst[14]=21 cells (6 PI) u2DelayCellOfst[15]=21 cells (6 PI) Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3) Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8FFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 3 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Set Vref, RX VrefLevel [Byte0]: 76 [Byte1]: 76 Set Vref, RX VrefLevel [Byte0]: 77 [Byte1]: 77 Final RX Vref Byte 0 = 62 to rank0 Final RX Vref Byte 1 = 52 to rank0 Final RX Vref Byte 0 = 62 to rank1 Final RX Vref Byte 1 = 52 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 129, DQM1 = 122 DQ Delay: DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =128 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =130 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps CH1 RK0: MR19=303, MR18=2626 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == Write leveling (Byte 0): 21 => 21 Write leveling (Byte 1): 19 => 19 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12) 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1) 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 12 24 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0) 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0) 0 13 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0) 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0) 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0) 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 0, 22) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 0, 30) best DQS0 dly(MCK, UI, PI) = (1, 0, 22) best DQS1 dly(MCK, UI, PI) = (1, 0, 30) best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22) best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 131, DQM1 = 124 DQ Delay: DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3) Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 4, minWin=22, winSum=385 TX Vref=18, minBit 1, minWin=23, winSum=395 TX Vref=20, minBit 3, minWin=23, winSum=402 TX Vref=22, minBit 0, minWin=24, winSum=407 TX Vref=24, minBit 0, minWin=24, winSum=410 TX Vref=26, minBit 1, minWin=25, winSum=421 TX Vref=28, minBit 0, minWin=25, winSum=421 TX Vref=30, minBit 0, minWin=25, winSum=419 TX Vref=32, minBit 0, minWin=24, winSum=410 TX Vref=34, minBit 0, minWin=23, winSum=405 TX Vref=36, minBit 0, minWin=23, winSum=395 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 26 Final TX Range 0 Vref 26 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps == TX Byte 0 == u2DelayCellOfst[0]=18 cells (5 PI) u2DelayCellOfst[1]=10 cells (3 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=7 cells (2 PI) u2DelayCellOfst[4]=10 cells (3 PI) u2DelayCellOfst[5]=14 cells (4 PI) u2DelayCellOfst[6]=18 cells (5 PI) u2DelayCellOfst[7]=7 cells (2 PI) Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3) Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=7 cells (2 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=10 cells (3 PI) u2DelayCellOfst[13]=18 cells (5 PI) u2DelayCellOfst[14]=18 cells (5 PI) u2DelayCellOfst[15]=18 cells (5 PI) Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3) Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x8F7F, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 3 -> 252, step: 4 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 127, DQM1 = 122 DQ Delay: DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =126 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps CH1 RK1: MR19=303, MR18=1B1B CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 3200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. DramC Write-DBI on PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [FAST_K] Save calibration result to emmc sync common calibartion params. sync cbt_mode0:0, 1:0 dram_init: ddr_geometry: 0 dram_init: ddr_geometry: 0 dram_init: ddr_geometry: 0 0:dram_rank_size:80000000 1:dram_rank_size:80000000 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000 DFS_SHUFFLE_HW_MODE: ON dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 switch to 3200 Mbps bootup [DramcRunTimeConfig] PHYPLL DPM_CONTROL_AFTERK: ON PER_BANK_REFRESH: ON REFRESH_OVERHEAD_REDUCTION: ON CMD_PICG_NEW_MODE: OFF XRTWTW_NEW_MODE: ON XRTRTR_NEW_MODE: ON TX_TRACKING: ON RDSEL_TRACKING: OFF DQS Precalculation for DVFS: ON RX_TRACKING: OFF HW_GATING DBG: ON ZQCS_ENABLE_LP4: ON RX_PICG_NEW_MODE: ON TX_PICG_NEW_MODE: ON ENABLE_RX_DCM_DPHY: ON LOWPOWER_GOLDEN_SETTINGS(DCM): ON DUMMY_READ_FOR_TRACKING: OFF !!! SPM_CONTROL_AFTERK: OFF !!! SPM could not control APHY IMPEDANCE_TRACKING: ON TEMP_SENSOR: ON HW_SAVE_FOR_SR: OFF CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF Read ODT Tracking: ON Refresh Rate DeBounce: ON DFS_NO_QUEUE_FLUSH: ON DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF ENABLE_DFS_RUNTIME_MRW: OFF DDR_RESERVE_NEW_MODE: ON MR_CBT_SWITCH_FREQ: ON ========================= [MEM] 1st complex R/W mem test pass (start addr:0x4c400000) dram_init: ddr_geometry: 0 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1) dram_init: dram init end (result: 0) DRAM-K: Full calibration passed in 23421 msecs MRC: failed to locate region type 0. DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal Backing address range [0x40000000:0x80000000) with new page table @0x00112000 Backing address range [0x40000000:0x40200000) with new page table @0x00113000 DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 CBMEM: IMD: root @ 0xfffff000 254 entries. IMD: root @ 0xffffec00 62 entries. FMAP: area RO_VPD found @ 3f8000 (32768 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 577000 (16384 bytes) CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps BS: romstage times (exec / console): total (unknown) / 22961 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled scan_static_bus for Root Device done scan_bus: bus Root Device finished in 8 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 DRAM rank0 size:0x80000000, DRAM rank1 size=0x80000000 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Root Device assign_resources, bus 0 link: 0 CPU_CLUSTER: 0 missing set_resources Root Device assign_resources, bus 0 link: 0 done Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms Enabling resources... done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms Initializing devices... Root Device init init hardware done! 0x00000018: ctrlr->caps 52.000 MHz: ctrlr->f_max 0.400 MHz: ctrlr->f_min 0x40ff8080: ctrlr->voltages sclk: 390625 Bus Width = 1 sclk: 390625 Bus Width = 1 Early init status = 3 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: [SSUSB] Setting up USB HOST controller... [SSUSB] u3phy_ports_enable u2p:1, u3p:1 [SSUSB] phy power-on done. FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes) CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes) CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps SPM: binary array size = 0x9dc SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16) spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes) SPM: spm_init done in 34 msecs, spm pc = 0x3f4 configure_display: Starting display init anx7625_power_on_init: Init interface. anx7625_disable_pd_protocol: Disabled PD feature. anx7625_power_on_init: Firmware: ver 0x13, rev 0x0. anx7625_start_dp_work: Secure OCM version=00 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91 sp_tx_get_edid_block: EDID Block = 1 Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 Digital display 6 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4, YCrCb 4:2:2 First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: 383680a07038204018303c0035ae10000019 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm 0780 0798 07c8 0820 hborder 0 0438 043b 0447 0458 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 000000000000000000000000000000000000 Manufacturer-specified data, tag 0 Hex of detail: 000000fe00496e666f566973696f6e0a2020 ASCII string: InfoVision Hex of detail: 000000fe00523134304e574635205248200a ASCII string: R140NWF5 RH Checksum Checksum: 0xfb (valid) configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz DSI data_rate: 832800000 bps anx7625_parse_edid: detected IVO panel, use k value 0x3b anx7625_parse_edid: pixelclock(138800). hactive(1920), hsync(48), hfp(24), hbp(88) vactive(1080), vsync(12), vfp(3), vbp(17) anx7625_dsi_config: config dsi. anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4). anx7625_dsi_config: success to config DSI anx7625_dp_start: MIPI phy setup OK. mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4 mtk_ddp_mode_set invalid vrefresh 60 main_disp_path_setup ovl_layer_smi_id_en ovl_layer_smi_id_en ccorr_config aal_config gamma_config postmask_config dither_config framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0 Root Device init finished in 555 msecs CPU_CLUSTER: 0 init Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff APU_MBOX 0x190000b0 = 0x10001 APU_MBOX 0x190001b0 = 0x10001 APU_MBOX 0x190005b0 = 0x10001 APU_MBOX 0x190006b0 = 0x10001 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes) CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes) CPU_CLUSTER: 0 init finished in 81 msecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms FMAP: area RW_ELOG found @ 57f000 (4096 bytes) ELOG: NV offset 0x57f000 size 0x1000 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2024-05-29 23:49:29 UTC out: cmd=0x121: 03 db 21 01 00 00 00 00 in-header: 03 e9 00 00 2c 00 00 00 in-data: 7a 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ELOG: Event(A1) added with size 10 at 2024-05-29 23:49:29 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2024-05-29 23:49:29 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms Writing coreboot table at 0xffe64000 0. 000000000010a000-0000000000113fff: RAMSTAGE 1. 0000000040000000-00000000400fffff: RAM 2. 0000000040100000-000000004032afff: RAMSTAGE 3. 000000004032b000-00000000545fffff: RAM 4. 0000000054600000-000000005465ffff: BL31 5. 0000000054660000-00000000ffe63fff: RAM 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES 7. 0000000100000000-000000013fffffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE EC in RW | 0x000000aa | low | undefined EC interrupt | 0x00000005 | low | undefined TPM interrupt | 0x000000ab | high | undefined SD card detect | 0x00000011 | high | undefined speaker enable | 0x00000093 | high | undefined out: cmd=0x6: 03 f7 06 00 00 00 00 00 in-header: 03 f4 00 00 02 00 00 00 in-data: 07 00 ADC[4]: Raw value=668958 ID=5 ADC[3]: Raw value=212549 ID=1 RAM Code: 0x51 ADC[6]: Raw value=74410 ID=0 ADC[5]: Raw value=211444 ID=1 SKU Code: 0x1 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum de67 coreboot table: 964 bytes. IMD ROOT 0. 0xfffff000 0x00001000 IMD SMALL 1. 0xffffe000 0x00001000 RO MCACHE 2. 0xffffc000 0x00001104 CONSOLE 3. 0xfff7c000 0x00080000 FMAP 4. 0xfff7b000 0x00000452 TIME STAMP 5. 0xfff7a000 0x00000910 VBOOT WORK 6. 0xfff66000 0x00014000 RAMOOPS 7. 0xffe66000 0x00100000 COREBOOT 8. 0xffe64000 0x00002000 IMD small region: IMD ROOT 0. 0xffffec00 0x00000400 VPD 1. 0xffffeb80 0x0000006c MMC STATUS 2. 0xffffeb60 0x00000004 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6 Initialized TPM device CR50 revision 0 Checking cr50 for pending updates Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=0) New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178 it's not compressed! [ 0x80000000, 8004f178, 0x821a7280) <- 40100038 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108 Loading segment from ROM address 0x4010001c Entry Point 0x80000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms Jumping to boot code at 0x80000000(0xffe64000) CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=1) New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470 using LZMA [ 0x54600000, 54614abc, 0x5462e000) <- 40100038 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544 Loading segment from ROM address 0x4010001c Entry Point 0x54601000 Loaded segments NOTICE: MT8192 bl31_setup NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021 WARNING: region 0: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 1: WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d WARNING: region 2: WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d WARNING: region 3: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 4: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 5: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 6: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 7: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0 INFO: [APUAPC] vio 0 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS! INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS! INFO: [APUAPC] D0_APC_0: 0x400510 INFO: [APUAPC] D0_APC_1: 0x0 INFO: [APUAPC] D0_APC_2: 0x1540 INFO: [APUAPC] D0_APC_3: 0x0 INFO: [APUAPC] D1_APC_0: 0xffffffff INFO: [APUAPC] D1_APC_1: 0xffffffff INFO: [APUAPC] D1_APC_2: 0x3fffff INFO: [APUAPC] D1_APC_3: 0x0 INFO: [APUAPC] D2_APC_0: 0xffffffff INFO: [APUAPC] D2_APC_1: 0xffffffff INFO: [APUAPC] D2_APC_2: 0x3fffff INFO: [APUAPC] D2_APC_3: 0x0 INFO: [APUAPC] D3_APC_0: 0xffffffff INFO: [APUAPC] D3_APC_1: 0xffffffff INFO: [APUAPC] D3_APC_2: 0x3fffff INFO: [APUAPC] D3_APC_3: 0x0 INFO: [APUAPC] D4_APC_0: 0xffffffff INFO: [APUAPC] D4_APC_1: 0xffffffff INFO: [APUAPC] D4_APC_2: 0x3fffff INFO: [APUAPC] D4_APC_3: 0x0 INFO: [APUAPC] D5_APC_0: 0xffffffff INFO: [APUAPC] D5_APC_1: 0xffffffff INFO: [APUAPC] D5_APC_2: 0x3fffff INFO: [APUAPC] D5_APC_3: 0x0 INFO: [APUAPC] D6_APC_0: 0xffffffff INFO: [APUAPC] D6_APC_1: 0xffffffff INFO: [APUAPC] D6_APC_2: 0x3fffff INFO: [APUAPC] D6_APC_3: 0x0 INFO: [APUAPC] D7_APC_0: 0xffffffff INFO: [APUAPC] D7_APC_1: 0xffffffff INFO: [APUAPC] D7_APC_2: 0x3fffff INFO: [APUAPC] D7_APC_3: 0x0 INFO: [APUAPC] D8_APC_0: 0xffffffff INFO: [APUAPC] D8_APC_1: 0xffffffff INFO: [APUAPC] D8_APC_2: 0x3fffff INFO: [APUAPC] D8_APC_3: 0x0 INFO: [APUAPC] D9_APC_0: 0xffffffff INFO: [APUAPC] D9_APC_1: 0xffffffff INFO: [APUAPC] D9_APC_2: 0x3fffff INFO: [APUAPC] D9_APC_3: 0x0 INFO: [APUAPC] D10_APC_0: 0xffffffff INFO: [APUAPC] D10_APC_1: 0xffffffff INFO: [APUAPC] D10_APC_2: 0x3fffff INFO: [APUAPC] D10_APC_3: 0x0 INFO: [APUAPC] D11_APC_0: 0xffffffff INFO: [APUAPC] D11_APC_1: 0xffffffff INFO: [APUAPC] D11_APC_2: 0x3fffff INFO: [APUAPC] D11_APC_3: 0x0 INFO: [APUAPC] D12_APC_0: 0xffffffff INFO: [APUAPC] D12_APC_1: 0xffffffff INFO: [APUAPC] D12_APC_2: 0x3fffff INFO: [APUAPC] D12_APC_3: 0x0 INFO: [APUAPC] D13_APC_0: 0xffffffff INFO: [APUAPC] D13_APC_1: 0xffffffff INFO: [APUAPC] D13_APC_2: 0x3fffff INFO: [APUAPC] D13_APC_3: 0x0 INFO: [APUAPC] D14_APC_0: 0xffffffff INFO: [APUAPC] D14_APC_1: 0xffffffff INFO: [APUAPC] D14_APC_2: 0x3fffff INFO: [APUAPC] D14_APC_3: 0x0 INFO: [APUAPC] D15_APC_0: 0xffffffff INFO: [APUAPC] D15_APC_1: 0xffffffff INFO: [APUAPC] D15_APC_2: 0x3fffff INFO: [APUAPC] D15_APC_3: 0x0 INFO: [APUAPC] APC_CON: 0x4 INFO: [NOCDAPC] D0_APC_0: 0x0 INFO: [NOCDAPC] D0_APC_1: 0x0 INFO: [NOCDAPC] D1_APC_0: 0x0 INFO: [NOCDAPC] D1_APC_1: 0xfff INFO: [NOCDAPC] D2_APC_0: 0x0 INFO: [NOCDAPC] D2_APC_1: 0xfff INFO: [NOCDAPC] D3_APC_0: 0x0 INFO: [NOCDAPC] D3_APC_1: 0xfff INFO: [NOCDAPC] D4_APC_0: 0x0 INFO: [NOCDAPC] D4_APC_1: 0xfff INFO: [NOCDAPC] D5_APC_0: 0x0 INFO: [NOCDAPC] D5_APC_1: 0xfff INFO: [NOCDAPC] D6_APC_0: 0x0 INFO: [NOCDAPC] D6_APC_1: 0xfff INFO: [NOCDAPC] D7_APC_0: 0x0 INFO: [NOCDAPC] D7_APC_1: 0xfff INFO: [NOCDAPC] D8_APC_0: 0x0 INFO: [NOCDAPC] D8_APC_1: 0xfff INFO: [NOCDAPC] D9_APC_0: 0x0 INFO: [NOCDAPC] D9_APC_1: 0xfff INFO: [NOCDAPC] D10_APC_0: 0x0 INFO: [NOCDAPC] D10_APC_1: 0xfff INFO: [NOCDAPC] D11_APC_0: 0x0 INFO: [NOCDAPC] D11_APC_1: 0xfff INFO: [NOCDAPC] D12_APC_0: 0x0 INFO: [NOCDAPC] D12_APC_1: 0xfff INFO: [NOCDAPC] D13_APC_0: 0x0 INFO: [NOCDAPC] D13_APC_1: 0xfff INFO: [NOCDAPC] D14_APC_0: 0x0 INFO: [NOCDAPC] D14_APC_1: 0xfff INFO: [NOCDAPC] D15_APC_0: 0x0 INFO: [NOCDAPC] D15_APC_1: 0xfff INFO: [NOCDAPC] APC_CON: 0x4 INFO: [APUAPC] set_apusys_apc done INFO: [DEVAPC] devapc_init done INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 639 INFO: BL31: Initializing runtime services WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing! INFO: SPM: enable CPC mode INFO: mcdi ready for mcusys-off-idle and system suspend INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x80000000 INFO: SPSR = 0x8 Starting depthcharge on Spherion... Wipe memory regions: [0x00000040000000, 0x00000054600000) [0x00000054660000, 0x00000080000000) [0x000000821a7280, 0x000000ffe64000) [0x00000100000000, 0x00000140000000) Initializing XHCI USB controller at 0x11200000. [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38 asurada: tftpboot 192.168.201.1 14084309/tftp-deploy-w6qgyi4y/kernel/image.itb 14084309/tftp-deploy-w6qgyi4y/kernel/cmdline tftpboot 192.168.201.1 14084309/tftp-deploy-w6qgyi4y/kernel/image.itp-deploy-w6qgyi4y/kernel/cmdline Waiting for link R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device done. MAC: 00:e0:4c:68:03:bd Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.16 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 14084309/tftp-deploy-w6qgyi4y/kernel/image.itb Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ###########################################