Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:55:13.843646 lava-dispatcher, installed at version: 2024.03
2 23:55:13.843862 start: 0 validate
3 23:55:13.844002 Start time: 2024-05-29 23:55:13.843993+00:00 (UTC)
4 23:55:13.844129 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:55:13.844259 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:55:14.105650 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:55:14.105912 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:55:14.367621 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:55:14.368291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:55:14.640585 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:55:14.640890 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:55:15.167761 validate duration: 1.32
14 23:55:15.168050 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:55:15.168166 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:55:15.168267 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:55:15.168395 Not decompressing ramdisk as can be used compressed.
18 23:55:15.168477 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:55:15.168541 saving as /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/ramdisk/rootfs.cpio.gz
20 23:55:15.168606 total size: 47897469 (45 MB)
21 23:55:15.169657 progress 0 % (0 MB)
22 23:55:15.183001 progress 5 % (2 MB)
23 23:55:15.195142 progress 10 % (4 MB)
24 23:55:15.207597 progress 15 % (6 MB)
25 23:55:15.219988 progress 20 % (9 MB)
26 23:55:15.232314 progress 25 % (11 MB)
27 23:55:15.244525 progress 30 % (13 MB)
28 23:55:15.256612 progress 35 % (16 MB)
29 23:55:15.268639 progress 40 % (18 MB)
30 23:55:15.281136 progress 45 % (20 MB)
31 23:55:15.293642 progress 50 % (22 MB)
32 23:55:15.306116 progress 55 % (25 MB)
33 23:55:15.318821 progress 60 % (27 MB)
34 23:55:15.331421 progress 65 % (29 MB)
35 23:55:15.343974 progress 70 % (32 MB)
36 23:55:15.356151 progress 75 % (34 MB)
37 23:55:15.369094 progress 80 % (36 MB)
38 23:55:15.381282 progress 85 % (38 MB)
39 23:55:15.393404 progress 90 % (41 MB)
40 23:55:15.405415 progress 95 % (43 MB)
41 23:55:15.417400 progress 100 % (45 MB)
42 23:55:15.417623 45 MB downloaded in 0.25 s (183.44 MB/s)
43 23:55:15.417776 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:55:15.418015 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:55:15.418101 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:55:15.418225 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:55:15.418360 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:55:15.418428 saving as /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/kernel/Image
50 23:55:15.418492 total size: 54682112 (52 MB)
51 23:55:15.418553 No compression specified
52 23:55:15.419713 progress 0 % (0 MB)
53 23:55:15.434020 progress 5 % (2 MB)
54 23:55:15.447813 progress 10 % (5 MB)
55 23:55:15.461787 progress 15 % (7 MB)
56 23:55:15.475662 progress 20 % (10 MB)
57 23:55:15.489934 progress 25 % (13 MB)
58 23:55:15.504241 progress 30 % (15 MB)
59 23:55:15.518399 progress 35 % (18 MB)
60 23:55:15.532424 progress 40 % (20 MB)
61 23:55:15.546823 progress 45 % (23 MB)
62 23:55:15.560959 progress 50 % (26 MB)
63 23:55:15.575088 progress 55 % (28 MB)
64 23:55:15.589069 progress 60 % (31 MB)
65 23:55:15.603237 progress 65 % (33 MB)
66 23:55:15.617685 progress 70 % (36 MB)
67 23:55:15.631819 progress 75 % (39 MB)
68 23:55:15.646365 progress 80 % (41 MB)
69 23:55:15.660783 progress 85 % (44 MB)
70 23:55:15.674622 progress 90 % (46 MB)
71 23:55:15.688896 progress 95 % (49 MB)
72 23:55:15.702702 progress 100 % (52 MB)
73 23:55:15.702952 52 MB downloaded in 0.28 s (183.33 MB/s)
74 23:55:15.703105 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:55:15.703342 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:55:15.703430 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:55:15.703514 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:55:15.703644 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:55:15.703717 saving as /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/dtb/mt8192-asurada-spherion-r0.dtb
81 23:55:15.703778 total size: 47258 (0 MB)
82 23:55:15.703838 No compression specified
83 23:55:15.704967 progress 69 % (0 MB)
84 23:55:15.705236 progress 100 % (0 MB)
85 23:55:15.705391 0 MB downloaded in 0.00 s (27.99 MB/s)
86 23:55:15.705515 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:55:15.705735 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:55:15.705820 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:55:15.705902 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:55:15.706012 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:55:15.706080 saving as /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/modules/modules.tar
93 23:55:15.706139 total size: 8601444 (8 MB)
94 23:55:15.706246 Using unxz to decompress xz
95 23:55:15.710373 progress 0 % (0 MB)
96 23:55:15.731251 progress 5 % (0 MB)
97 23:55:15.757116 progress 10 % (0 MB)
98 23:55:15.782920 progress 15 % (1 MB)
99 23:55:15.807906 progress 20 % (1 MB)
100 23:55:15.833777 progress 25 % (2 MB)
101 23:55:15.858843 progress 30 % (2 MB)
102 23:55:15.882985 progress 35 % (2 MB)
103 23:55:15.907888 progress 40 % (3 MB)
104 23:55:15.936186 progress 45 % (3 MB)
105 23:55:15.960624 progress 50 % (4 MB)
106 23:55:15.985793 progress 55 % (4 MB)
107 23:55:16.010512 progress 60 % (4 MB)
108 23:55:16.034654 progress 65 % (5 MB)
109 23:55:16.061642 progress 70 % (5 MB)
110 23:55:16.086573 progress 75 % (6 MB)
111 23:55:16.110428 progress 80 % (6 MB)
112 23:55:16.136728 progress 85 % (7 MB)
113 23:55:16.161068 progress 90 % (7 MB)
114 23:55:16.190375 progress 95 % (7 MB)
115 23:55:16.219141 progress 100 % (8 MB)
116 23:55:16.224580 8 MB downloaded in 0.52 s (15.82 MB/s)
117 23:55:16.224834 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:55:16.225106 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:55:16.225200 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:55:16.225292 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:55:16.225372 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:55:16.225461 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:55:16.225688 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95
125 23:55:16.225821 makedir: /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin
126 23:55:16.225924 makedir: /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/tests
127 23:55:16.226023 makedir: /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/results
128 23:55:16.226138 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-add-keys
129 23:55:16.226323 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-add-sources
130 23:55:16.226454 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-background-process-start
131 23:55:16.226584 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-background-process-stop
132 23:55:16.226709 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-common-functions
133 23:55:16.226833 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-echo-ipv4
134 23:55:16.226958 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-install-packages
135 23:55:16.227082 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-installed-packages
136 23:55:16.227247 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-os-build
137 23:55:16.227372 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-probe-channel
138 23:55:16.227495 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-probe-ip
139 23:55:16.227618 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-target-ip
140 23:55:16.227740 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-target-mac
141 23:55:16.227862 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-target-storage
142 23:55:16.227988 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-case
143 23:55:16.228111 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-event
144 23:55:16.228232 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-feedback
145 23:55:16.228354 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-raise
146 23:55:16.228476 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-reference
147 23:55:16.228598 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-runner
148 23:55:16.228720 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-set
149 23:55:16.228846 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-test-shell
150 23:55:16.228972 Updating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-install-packages (oe)
151 23:55:16.229129 Updating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/bin/lava-installed-packages (oe)
152 23:55:16.229252 Creating /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/environment
153 23:55:16.229354 LAVA metadata
154 23:55:16.229427 - LAVA_JOB_ID=14084377
155 23:55:16.229491 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:55:16.229593 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:55:16.229660 skipped lava-vland-overlay
158 23:55:16.229734 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:55:16.229818 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:55:16.229928 skipped lava-multinode-overlay
161 23:55:16.230085 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:55:16.230226 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:55:16.230337 Loading test definitions
164 23:55:16.230483 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:55:16.230583 Using /lava-14084377 at stage 0
166 23:55:16.230965 uuid=14084377_1.5.2.3.1 testdef=None
167 23:55:16.231054 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:55:16.231154 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:55:16.231820 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:55:16.232088 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:55:16.232722 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:55:16.232968 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:55:16.233784 runner path: /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/0/tests/0_igt-gpu-panfrost test_uuid 14084377_1.5.2.3.1
176 23:55:16.233987 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:55:16.234350 Creating lava-test-runner.conf files
179 23:55:16.234445 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084377/lava-overlay-d3qgku95/lava-14084377/0 for stage 0
180 23:55:16.234569 - 0_igt-gpu-panfrost
181 23:55:16.234706 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:55:16.234827 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:55:16.244327 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:55:16.244482 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:55:16.244604 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:55:16.244727 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:55:16.244856 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:55:18.002926 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 23:55:18.003357 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:55:18.003478 extracting modules file /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084377/extract-overlay-ramdisk-5ut3ust4/ramdisk
191 23:55:18.240658 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:55:18.240868 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 23:55:18.240965 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084377/compress-overlay-_fv5pj31/overlay-1.5.2.4.tar.gz to ramdisk
194 23:55:18.241039 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084377/compress-overlay-_fv5pj31/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084377/extract-overlay-ramdisk-5ut3ust4/ramdisk
195 23:55:18.248314 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:55:18.248433 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 23:55:18.248521 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:55:18.248618 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 23:55:18.248697 Building ramdisk /var/lib/lava/dispatcher/tmp/14084377/extract-overlay-ramdisk-5ut3ust4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084377/extract-overlay-ramdisk-5ut3ust4/ramdisk
200 23:55:19.474454 >> 465919 blocks
201 23:55:25.681468 rename /var/lib/lava/dispatcher/tmp/14084377/extract-overlay-ramdisk-5ut3ust4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/ramdisk/ramdisk.cpio.gz
202 23:55:25.681908 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 23:55:25.682042 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 23:55:25.682140 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 23:55:25.682348 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/kernel/Image']
206 23:55:38.763136 Returned 0 in 13 seconds
207 23:55:38.864094 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/kernel/image.itb
208 23:55:39.733569 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:55:39.733941 output: Created: Thu May 30 00:55:39 2024
210 23:55:39.734010 output: Image 0 (kernel-1)
211 23:55:39.734075 output: Description:
212 23:55:39.734138 output: Created: Thu May 30 00:55:39 2024
213 23:55:39.734242 output: Type: Kernel Image
214 23:55:39.734305 output: Compression: lzma compressed
215 23:55:39.734363 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
216 23:55:39.734426 output: Architecture: AArch64
217 23:55:39.734483 output: OS: Linux
218 23:55:39.734542 output: Load Address: 0x00000000
219 23:55:39.734602 output: Entry Point: 0x00000000
220 23:55:39.734662 output: Hash algo: crc32
221 23:55:39.734718 output: Hash value: 907bf91d
222 23:55:39.734774 output: Image 1 (fdt-1)
223 23:55:39.734828 output: Description: mt8192-asurada-spherion-r0
224 23:55:39.734882 output: Created: Thu May 30 00:55:39 2024
225 23:55:39.734937 output: Type: Flat Device Tree
226 23:55:39.734990 output: Compression: uncompressed
227 23:55:39.735042 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:55:39.735094 output: Architecture: AArch64
229 23:55:39.735146 output: Hash algo: crc32
230 23:55:39.735198 output: Hash value: 0f8e4d2e
231 23:55:39.735250 output: Image 2 (ramdisk-1)
232 23:55:39.735302 output: Description: unavailable
233 23:55:39.735354 output: Created: Thu May 30 00:55:39 2024
234 23:55:39.735406 output: Type: RAMDisk Image
235 23:55:39.735458 output: Compression: Unknown Compression
236 23:55:39.735510 output: Data Size: 60994925 Bytes = 59565.36 KiB = 58.17 MiB
237 23:55:39.735562 output: Architecture: AArch64
238 23:55:39.735614 output: OS: Linux
239 23:55:39.735666 output: Load Address: unavailable
240 23:55:39.735719 output: Entry Point: unavailable
241 23:55:39.735770 output: Hash algo: crc32
242 23:55:39.735822 output: Hash value: 90705082
243 23:55:39.735874 output: Default Configuration: 'conf-1'
244 23:55:39.735925 output: Configuration 0 (conf-1)
245 23:55:39.735977 output: Description: mt8192-asurada-spherion-r0
246 23:55:39.736030 output: Kernel: kernel-1
247 23:55:39.736081 output: Init Ramdisk: ramdisk-1
248 23:55:39.736133 output: FDT: fdt-1
249 23:55:39.736185 output: Loadables: kernel-1
250 23:55:39.736237 output:
251 23:55:39.736440 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:55:39.736534 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:55:39.736639 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 23:55:39.736750 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 23:55:39.736829 No LXC device requested
256 23:55:39.736909 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:55:39.736993 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 23:55:39.737067 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:55:39.737133 Checking files for TFTP limit of 4294967296 bytes.
260 23:55:39.737626 end: 1 tftp-deploy (duration 00:00:25) [common]
261 23:55:39.737732 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:55:39.737826 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:55:39.737943 substitutions:
264 23:55:39.738008 - {DTB}: 14084377/tftp-deploy-kbi4ick9/dtb/mt8192-asurada-spherion-r0.dtb
265 23:55:39.738071 - {INITRD}: 14084377/tftp-deploy-kbi4ick9/ramdisk/ramdisk.cpio.gz
266 23:55:39.738130 - {KERNEL}: 14084377/tftp-deploy-kbi4ick9/kernel/Image
267 23:55:39.738244 - {LAVA_MAC}: None
268 23:55:39.738331 - {PRESEED_CONFIG}: None
269 23:55:39.738413 - {PRESEED_LOCAL}: None
270 23:55:39.738471 - {RAMDISK}: 14084377/tftp-deploy-kbi4ick9/ramdisk/ramdisk.cpio.gz
271 23:55:39.738527 - {ROOT_PART}: None
272 23:55:39.738581 - {ROOT}: None
273 23:55:39.738635 - {SERVER_IP}: 192.168.201.1
274 23:55:39.738689 - {TEE}: None
275 23:55:39.738742 Parsed boot commands:
276 23:55:39.738794 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:55:39.738966 Parsed boot commands: tftpboot 192.168.201.1 14084377/tftp-deploy-kbi4ick9/kernel/image.itb 14084377/tftp-deploy-kbi4ick9/kernel/cmdline
278 23:55:39.739056 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:55:39.739185 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:55:39.739276 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:55:39.739362 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:55:39.739434 Not connected, no need to disconnect.
283 23:55:39.739507 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:55:39.739590 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:55:39.739655 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 23:55:39.743418 Setting prompt string to ['lava-test: # ']
287 23:55:39.743787 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:55:39.743892 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:55:39.743993 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:55:39.744083 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:55:39.744257 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
292 23:55:53.896130 Returned 0 in 14 seconds
293 23:55:53.997266 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 23:55:54.000100 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 23:55:54.000653 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 23:55:54.001134 Setting prompt string to 'Starting depthcharge on Spherion...'
298 23:55:54.001516 Changing prompt to 'Starting depthcharge on Spherion...'
299 23:55:54.001890 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 23:55:54.004054 [Enter `^Ec?' for help]
301 23:55:54.004513
302 23:55:54.004875
303 23:55:54.005230 F0: 102B 0000
304 23:55:54.005576
305 23:55:54.005898 F3: 1001 0000 [0200]
306 23:55:54.006262
307 23:55:54.006616 F3: 1001 0000
308 23:55:54.006950
309 23:55:54.007276 F7: 102D 0000
310 23:55:54.007704
311 23:55:54.008021 F1: 0000 0000
312 23:55:54.008327
313 23:55:54.008631 V0: 0000 0000 [0001]
314 23:55:54.008952
315 23:55:54.009259 00: 0007 8000
316 23:55:54.009584
317 23:55:54.009982 01: 0000 0000
318 23:55:54.010346
319 23:55:54.010656 BP: 0C00 0209 [0000]
320 23:55:54.010961
321 23:55:54.011263 G0: 1182 0000
322 23:55:54.011569
323 23:55:54.011869 EC: 0000 0021 [4000]
324 23:55:54.012172
325 23:55:54.012475 S7: 0000 0000 [0000]
326 23:55:54.012775
327 23:55:54.013158 CC: 0000 0000 [0001]
328 23:55:54.013476
329 23:55:54.013780 T0: 0000 0040 [010F]
330 23:55:54.014086
331 23:55:54.014426 Jump to BL
332 23:55:54.014730
333 23:55:54.015030
334 23:55:54.015337
335 23:55:54.015609 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 23:55:54.015898 ARM64: Exception handlers installed.
337 23:55:54.016177 ARM64: Testing exception
338 23:55:54.016450 ARM64: Done test exception
339 23:55:54.016724 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 23:55:54.017005 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 23:55:54.017288 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 23:55:54.017568 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 23:55:54.017845 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 23:55:54.018123 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 23:55:54.018447 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 23:55:54.018728 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 23:55:54.019004 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 23:55:54.019285 WDT: Last reset was cold boot
349 23:55:54.019561 SPI1(PAD0) initialized at 2873684 Hz
350 23:55:54.019838 SPI5(PAD0) initialized at 992727 Hz
351 23:55:54.020113 VBOOT: Loading verstage.
352 23:55:54.020388 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 23:55:54.020666 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 23:55:54.020945 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 23:55:54.021223 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 23:55:54.021506 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 23:55:54.021785 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 23:55:54.022061 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 23:55:54.022384
360 23:55:54.022661
361 23:55:54.022937 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 23:55:54.023217 ARM64: Exception handlers installed.
363 23:55:54.023507 ARM64: Testing exception
364 23:55:54.023782 ARM64: Done test exception
365 23:55:54.024053 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 23:55:54.024328 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 23:55:54.024604 Probing TPM: . done!
368 23:55:54.024876 TPM ready after 0 ms
369 23:55:54.025151 Connected to device vid:did:rid of 1ae0:0028:00
370 23:55:54.025426 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
371 23:55:54.025708 Initialized TPM device CR50 revision 0
372 23:55:54.025985 tlcl_send_startup: Startup return code is 0
373 23:55:54.026283 TPM: setup succeeded
374 23:55:54.026563 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 23:55:54.026841 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 23:55:54.027118 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 23:55:54.027395 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:55:54.027768 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 23:55:54.028057 in-header: 03 07 00 00 08 00 00 00
380 23:55:54.028335 in-data: aa e4 47 04 13 02 00 00
381 23:55:54.028611 Chrome EC: UHEPI supported
382 23:55:54.028887 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 23:55:54.029165 in-header: 03 a9 00 00 08 00 00 00
384 23:55:54.029384 in-data: 84 60 60 08 00 00 00 00
385 23:55:54.029581 Phase 1
386 23:55:54.029779 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 23:55:54.029979 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 23:55:54.030303 VB2:vb2_check_recovery() Recovery was requested manually
389 23:55:54.030511 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 23:55:54.030711 Recovery requested (1009000e)
391 23:55:54.030910 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:55:54.031110 tlcl_extend: response is 0
393 23:55:54.031345 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:55:54.031551 tlcl_extend: response is 0
395 23:55:54.031750 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:55:54.031949 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 23:55:54.032147 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:55:54.032343
399 23:55:54.032537
400 23:55:54.032870 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:55:54.033137 ARM64: Exception handlers installed.
402 23:55:54.033341 ARM64: Testing exception
403 23:55:54.033542 ARM64: Done test exception
404 23:55:54.033835 pmic_efuse_setting: Set efuses in 11 msecs
405 23:55:54.034145 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:55:54.034354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:55:54.034506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:55:54.034910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:55:54.035081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:55:54.035234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:55:54.035385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:55:54.035535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:55:54.035683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:55:54.035832 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:55:54.035981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:55:54.036130 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:55:54.036277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:55:54.036424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:55:54.036570 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:55:54.036718 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:55:54.036866 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:55:54.037015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:55:54.037162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:55:54.037310 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:55:54.037456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:55:54.037604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:55:54.037752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:55:54.037899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:55:54.038048 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:55:54.038218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:55:54.038372 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:55:54.038588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:55:54.038744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:55:54.038894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:55:54.039044 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:55:54.039193 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:55:54.039327 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:55:54.039445 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:55:54.039564 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:55:54.039683 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:55:54.039802 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:55:54.039921 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:55:54.040040 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:55:54.040157 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:55:54.040275 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:55:54.040394 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:55:54.040511 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:55:54.040630 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:55:54.040748 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:55:54.040865 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:55:54.040983 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:55:54.041101 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:55:54.041219 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:55:54.041337 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:55:54.041455 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:55:54.041573 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:55:54.041692 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 23:55:54.041812 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:55:54.041932 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:55:54.042050 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:55:54.042183 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:55:54.042307 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:55:54.042427 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:55:54.042545 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:55:54.042665 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2b
466 23:55:54.042784 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:55:54.042904 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
468 23:55:54.043022 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:55:54.043141 [RTC]rtc_get_frequency_meter,154: input=15, output=834
470 23:55:54.043260 [RTC]rtc_get_frequency_meter,154: input=7, output=708
471 23:55:54.043378 [RTC]rtc_get_frequency_meter,154: input=11, output=771
472 23:55:54.043497 [RTC]rtc_get_frequency_meter,154: input=13, output=802
473 23:55:54.043615 [RTC]rtc_get_frequency_meter,154: input=12, output=787
474 23:55:54.043732 [RTC]rtc_get_frequency_meter,154: input=12, output=786
475 23:55:54.043848 [RTC]rtc_get_frequency_meter,154: input=13, output=802
476 23:55:54.043966 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
477 23:55:54.044085 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
478 23:55:54.044416 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:55:54.044526 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 23:55:54.044628 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:55:54.044728 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 23:55:54.044827 ADC[4]: Raw value=901922 ID=7
483 23:55:54.044927 ADC[3]: Raw value=213282 ID=1
484 23:55:54.045025 RAM Code: 0x71
485 23:55:54.045125 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:55:54.045225 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:55:54.045325 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:55:54.045426 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:55:54.045526 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:55:54.045626 in-header: 03 07 00 00 08 00 00 00
491 23:55:54.045725 in-data: aa e4 47 04 13 02 00 00
492 23:55:54.045825 Chrome EC: UHEPI supported
493 23:55:54.045924 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:55:54.046025 in-header: 03 a9 00 00 08 00 00 00
495 23:55:54.046124 in-data: 84 60 60 08 00 00 00 00
496 23:55:54.046240 MRC: failed to locate region type 0.
497 23:55:54.046341 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:55:54.046441 DRAM-K: Running full calibration
499 23:55:54.046540 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:55:54.046639 header.status = 0x0
501 23:55:54.046736 header.version = 0x6 (expected: 0x6)
502 23:55:54.046834 header.size = 0xd00 (expected: 0xd00)
503 23:55:54.046932 header.flags = 0x0
504 23:55:54.047030 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:55:54.047129 read SPI 0x72590 0x1c583: 12496 us, 9290 KB/s, 74.320 Mbps
506 23:55:54.047229 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:55:54.047328 dram_init: ddr_geometry: 2
508 23:55:54.047427 [EMI] MDL number = 2
509 23:55:54.047524 [EMI] Get MDL freq = 0
510 23:55:54.047624 dram_init: ddr_type: 0
511 23:55:54.047723 is_discrete_lpddr4: 1
512 23:55:54.047821 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:55:54.047920
514 23:55:54.048020
515 23:55:54.048117 [Bian_co] ETT version 0.0.0.1
516 23:55:54.048216 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:55:54.048315
518 23:55:54.048414 dramc_set_vcore_voltage set vcore to 650000
519 23:55:54.048513 Read voltage for 800, 4
520 23:55:54.048613 Vio18 = 0
521 23:55:54.048712 Vcore = 650000
522 23:55:54.048810 Vdram = 0
523 23:55:54.048908 Vddq = 0
524 23:55:54.049007 Vmddr = 0
525 23:55:54.049104 dram_init: config_dvfs: 1
526 23:55:54.049204 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:55:54.049304 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:55:54.049390 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
529 23:55:54.049474 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
530 23:55:54.049560 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
531 23:55:54.049645 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
532 23:55:54.049732 MEM_TYPE=3, freq_sel=18
533 23:55:54.049816 sv_algorithm_assistance_LP4_1600
534 23:55:54.049900 ============ PULL DRAM RESETB DOWN ============
535 23:55:54.049986 ========== PULL DRAM RESETB DOWN end =========
536 23:55:54.050072 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:55:54.050157 ===================================
538 23:55:54.050257 LPDDR4 DRAM CONFIGURATION
539 23:55:54.050342 ===================================
540 23:55:54.050427 EX_ROW_EN[0] = 0x0
541 23:55:54.050512 EX_ROW_EN[1] = 0x0
542 23:55:54.050597 LP4Y_EN = 0x0
543 23:55:54.050682 WORK_FSP = 0x0
544 23:55:54.050765 WL = 0x2
545 23:55:54.050850 RL = 0x2
546 23:55:54.050934 BL = 0x2
547 23:55:54.051019 RPST = 0x0
548 23:55:54.051102 RD_PRE = 0x0
549 23:55:54.051187 WR_PRE = 0x1
550 23:55:54.051271 WR_PST = 0x0
551 23:55:54.051356 DBI_WR = 0x0
552 23:55:54.051439 DBI_RD = 0x0
553 23:55:54.051523 OTF = 0x1
554 23:55:54.051608 ===================================
555 23:55:54.051693 ===================================
556 23:55:54.051778 ANA top config
557 23:55:54.051862 ===================================
558 23:55:54.051947 DLL_ASYNC_EN = 0
559 23:55:54.052036 ALL_SLAVE_EN = 1
560 23:55:54.052120 NEW_RANK_MODE = 1
561 23:55:54.052206 DLL_IDLE_MODE = 1
562 23:55:54.052290 LP45_APHY_COMB_EN = 1
563 23:55:54.052376 TX_ODT_DIS = 1
564 23:55:54.052460 NEW_8X_MODE = 1
565 23:55:54.052546 ===================================
566 23:55:54.052632 ===================================
567 23:55:54.052753 data_rate = 1600
568 23:55:54.052842 CKR = 1
569 23:55:54.052928 DQ_P2S_RATIO = 8
570 23:55:54.053014 ===================================
571 23:55:54.053099 CA_P2S_RATIO = 8
572 23:55:54.053184 DQ_CA_OPEN = 0
573 23:55:54.053269 DQ_SEMI_OPEN = 0
574 23:55:54.053354 CA_SEMI_OPEN = 0
575 23:55:54.053439 CA_FULL_RATE = 0
576 23:55:54.053523 DQ_CKDIV4_EN = 1
577 23:55:54.053608 CA_CKDIV4_EN = 1
578 23:55:54.053693 CA_PREDIV_EN = 0
579 23:55:54.053777 PH8_DLY = 0
580 23:55:54.053862 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:55:54.053947 DQ_AAMCK_DIV = 4
582 23:55:54.054032 CA_AAMCK_DIV = 4
583 23:55:54.054117 CA_ADMCK_DIV = 4
584 23:55:54.054227 DQ_TRACK_CA_EN = 0
585 23:55:54.054303 CA_PICK = 800
586 23:55:54.054377 CA_MCKIO = 800
587 23:55:54.054452 MCKIO_SEMI = 0
588 23:55:54.054527 PLL_FREQ = 3068
589 23:55:54.054601 DQ_UI_PI_RATIO = 32
590 23:55:54.054675 CA_UI_PI_RATIO = 0
591 23:55:54.054754 ===================================
592 23:55:54.054829 ===================================
593 23:55:54.054904 memory_type:LPDDR4
594 23:55:54.054979 GP_NUM : 10
595 23:55:54.055054 SRAM_EN : 1
596 23:55:54.055129 MD32_EN : 0
597 23:55:54.055428 ===================================
598 23:55:54.055516 [ANA_INIT] >>>>>>>>>>>>>>
599 23:55:54.055592 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:55:54.055672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:55:54.055749 ===================================
602 23:55:54.055825 data_rate = 1600,PCW = 0X7600
603 23:55:54.055899 ===================================
604 23:55:54.055975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:55:54.056050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:55:54.056124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:55:54.056200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:55:54.056275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:55:54.056350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:55:54.056425 [ANA_INIT] flow start
611 23:55:54.056500 [ANA_INIT] PLL >>>>>>>>
612 23:55:54.056574 [ANA_INIT] PLL <<<<<<<<
613 23:55:54.056648 [ANA_INIT] MIDPI >>>>>>>>
614 23:55:54.056721 [ANA_INIT] MIDPI <<<<<<<<
615 23:55:54.056795 [ANA_INIT] DLL >>>>>>>>
616 23:55:54.056869 [ANA_INIT] flow end
617 23:55:54.056943 ============ LP4 DIFF to SE enter ============
618 23:55:54.057018 ============ LP4 DIFF to SE exit ============
619 23:55:54.057093 [ANA_INIT] <<<<<<<<<<<<<
620 23:55:54.057167 [Flow] Enable top DCM control >>>>>
621 23:55:54.057242 [Flow] Enable top DCM control <<<<<
622 23:55:54.057316 Enable DLL master slave shuffle
623 23:55:54.057391 ==============================================================
624 23:55:54.057465 Gating Mode config
625 23:55:54.057539 ==============================================================
626 23:55:54.057613 Config description:
627 23:55:54.057687 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:55:54.057763 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:55:54.057839 SELPH_MODE 0: By rank 1: By Phase
630 23:55:54.057915 ==============================================================
631 23:55:54.057990 GAT_TRACK_EN = 1
632 23:55:54.058065 RX_GATING_MODE = 2
633 23:55:54.058139 RX_GATING_TRACK_MODE = 2
634 23:55:54.058229 SELPH_MODE = 1
635 23:55:54.058305 PICG_EARLY_EN = 1
636 23:55:54.058380 VALID_LAT_VALUE = 1
637 23:55:54.058454 ==============================================================
638 23:55:54.058529 Enter into Gating configuration >>>>
639 23:55:54.058603 Exit from Gating configuration <<<<
640 23:55:54.058678 Enter into DVFS_PRE_config >>>>>
641 23:55:54.058752 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:55:54.058832 Exit from DVFS_PRE_config <<<<<
643 23:55:54.058907 Enter into PICG configuration >>>>
644 23:55:54.058982 Exit from PICG configuration <<<<
645 23:55:54.059056 [RX_INPUT] configuration >>>>>
646 23:55:54.059130 [RX_INPUT] configuration <<<<<
647 23:55:54.059216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:55:54.059283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:55:54.059360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:55:54.059432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:55:54.059499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:55:54.059566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:55:54.059632 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:55:54.059699 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:55:54.059765 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:55:54.059831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:55:54.059897 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:55:54.059963 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:55:54.060029 ===================================
660 23:55:54.060096 LPDDR4 DRAM CONFIGURATION
661 23:55:54.060162 ===================================
662 23:55:54.060228 EX_ROW_EN[0] = 0x0
663 23:55:54.060294 EX_ROW_EN[1] = 0x0
664 23:55:54.060359 LP4Y_EN = 0x0
665 23:55:54.060426 WORK_FSP = 0x0
666 23:55:54.060492 WL = 0x2
667 23:55:54.060557 RL = 0x2
668 23:55:54.060622 BL = 0x2
669 23:55:54.060688 RPST = 0x0
670 23:55:54.060753 RD_PRE = 0x0
671 23:55:54.060819 WR_PRE = 0x1
672 23:55:54.060885 WR_PST = 0x0
673 23:55:54.060960 DBI_WR = 0x0
674 23:55:54.061055 DBI_RD = 0x0
675 23:55:54.061124 OTF = 0x1
676 23:55:54.061190 ===================================
677 23:55:54.061257 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:55:54.061324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:55:54.061391 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:55:54.061458 ===================================
681 23:55:54.061526 LPDDR4 DRAM CONFIGURATION
682 23:55:54.061610 ===================================
683 23:55:54.061677 EX_ROW_EN[0] = 0x10
684 23:55:54.061744 EX_ROW_EN[1] = 0x0
685 23:55:54.061810 LP4Y_EN = 0x0
686 23:55:54.061877 WORK_FSP = 0x0
687 23:55:54.061943 WL = 0x2
688 23:55:54.062009 RL = 0x2
689 23:55:54.062095 BL = 0x2
690 23:55:54.062167 RPST = 0x0
691 23:55:54.062236 RD_PRE = 0x0
692 23:55:54.062302 WR_PRE = 0x1
693 23:55:54.062389 WR_PST = 0x0
694 23:55:54.062459 DBI_WR = 0x0
695 23:55:54.062524 DBI_RD = 0x0
696 23:55:54.062591 OTF = 0x1
697 23:55:54.062657 ===================================
698 23:55:54.062724 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:55:54.062797 nWR fixed to 40
700 23:55:54.062876 [ModeRegInit_LP4] CH0 RK0
701 23:55:54.062943 [ModeRegInit_LP4] CH0 RK1
702 23:55:54.063010 [ModeRegInit_LP4] CH1 RK0
703 23:55:54.063077 [ModeRegInit_LP4] CH1 RK1
704 23:55:54.063143 match AC timing 13
705 23:55:54.063209 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:55:54.063476 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:55:54.063569 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:55:54.063642 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:55:54.063710 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:55:54.063800 [EMI DOE] emi_dcm 0
711 23:55:54.063869 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:55:54.063937 ==
713 23:55:54.064005 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:55:54.064073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:55:54.064157 ==
716 23:55:54.064226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:55:54.064301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:55:54.064361 [CA 0] Center 37 (7~68) winsize 62
719 23:55:54.064421 [CA 1] Center 37 (6~68) winsize 63
720 23:55:54.064480 [CA 2] Center 34 (4~65) winsize 62
721 23:55:54.064540 [CA 3] Center 34 (4~65) winsize 62
722 23:55:54.064600 [CA 4] Center 33 (3~64) winsize 62
723 23:55:54.064660 [CA 5] Center 33 (3~64) winsize 62
724 23:55:54.064719
725 23:55:54.064778 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:55:54.064838
727 23:55:54.064898 [CATrainingPosCal] consider 1 rank data
728 23:55:54.064957 u2DelayCellTimex100 = 270/100 ps
729 23:55:54.065017 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 23:55:54.065077 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 23:55:54.065137 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 23:55:54.065197 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 23:55:54.065256 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 23:55:54.065315 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:55:54.065375
736 23:55:54.065433 CA PerBit enable=1, Macro0, CA PI delay=33
737 23:55:54.065493
738 23:55:54.065552 [CBTSetCACLKResult] CA Dly = 33
739 23:55:54.065611 CS Dly: 6 (0~37)
740 23:55:54.065670 ==
741 23:55:54.065730 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:55:54.065789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:55:54.065849 ==
744 23:55:54.065909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:55:54.065969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:55:54.066029 [CA 0] Center 37 (6~68) winsize 63
747 23:55:54.066089 [CA 1] Center 37 (7~68) winsize 62
748 23:55:54.066149 [CA 2] Center 34 (4~65) winsize 62
749 23:55:54.066216 [CA 3] Center 34 (4~65) winsize 62
750 23:55:54.066276 [CA 4] Center 33 (3~64) winsize 62
751 23:55:54.066336 [CA 5] Center 33 (3~64) winsize 62
752 23:55:54.066395
753 23:55:54.066455 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:55:54.066514
755 23:55:54.066573 [CATrainingPosCal] consider 2 rank data
756 23:55:54.066633 u2DelayCellTimex100 = 270/100 ps
757 23:55:54.066693 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 23:55:54.066753 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:55:54.066813 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 23:55:54.066872 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 23:55:54.066932 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 23:55:54.066992 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:55:54.067052
764 23:55:54.067111 CA PerBit enable=1, Macro0, CA PI delay=33
765 23:55:54.067171
766 23:55:54.067230 [CBTSetCACLKResult] CA Dly = 33
767 23:55:54.067290 CS Dly: 7 (0~39)
768 23:55:54.067349
769 23:55:54.067408 ----->DramcWriteLeveling(PI) begin...
770 23:55:54.067469 ==
771 23:55:54.067529 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:55:54.067589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:55:54.067649 ==
774 23:55:54.067708 Write leveling (Byte 0): 31 => 31
775 23:55:54.067767 Write leveling (Byte 1): 30 => 30
776 23:55:54.067826 DramcWriteLeveling(PI) end<-----
777 23:55:54.067886
778 23:55:54.067944 ==
779 23:55:54.068004 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:55:54.068063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:55:54.068124 ==
782 23:55:54.068183 [Gating] SW mode calibration
783 23:55:54.068243 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:55:54.068303 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:55:54.068364 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:55:54.068424 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 23:55:54.068484 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 23:55:54.068544 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:55:54.068604 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:55:54.068664 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:55:54.068724 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:55:54.068784 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:55:54.068843 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:55:54.068903 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:55:54.068963 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:55:54.069022 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:55:54.069082 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:55:54.069142 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:55:54.069201 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:55:54.069272 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:55:54.069326 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:55:54.069381 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 23:55:54.069435 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 23:55:54.069490 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 23:55:54.069544 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:55:54.069598 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:55:54.069652 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:55:54.069707 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:55:54.069761 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:55:54.069815 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:55:54.069869 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
812 23:55:54.069924 0 9 12 | B1->B0 | 2a29 3434 | 1 1 | (1 1) (1 1)
813 23:55:54.069979 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:55:54.070201 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:55:54.070262 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:55:54.070318 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:55:54.070373 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:55:54.070428 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:55:54.070483 0 10 8 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
820 23:55:54.070538 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
821 23:55:54.070592 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:55:54.070647 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:55:54.070701 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:55:54.070756 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:55:54.070810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:55:54.070864 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:55:54.070919 0 11 8 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
828 23:55:54.070973 0 11 12 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
829 23:55:54.071028 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 23:55:54.071082 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:55:54.071137 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:55:54.071191 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:55:54.071245 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:55:54.071300 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 23:55:54.071353 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 23:55:54.071407 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 23:55:54.071461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:55:54.071515 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:55:54.071569 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:55:54.071623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:55:54.071677 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:55:54.071731 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:55:54.071785 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:55:54.071839 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:55:54.071894 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:55:54.071948 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:55:54.072002 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:55:54.072056 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:55:54.072111 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:55:54.072165 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:55:54.072219 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 23:55:54.072273 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 23:55:54.072327 Total UI for P1: 0, mck2ui 16
854 23:55:54.072382 best dqsien dly found for B0: ( 0, 14, 8)
855 23:55:54.072438 Total UI for P1: 0, mck2ui 16
856 23:55:54.072492 best dqsien dly found for B1: ( 0, 14, 8)
857 23:55:54.072547 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 23:55:54.072602 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 23:55:54.072656
860 23:55:54.072710 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 23:55:54.072765 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 23:55:54.072819 [Gating] SW calibration Done
863 23:55:54.072873 ==
864 23:55:54.072927 Dram Type= 6, Freq= 0, CH_0, rank 0
865 23:55:54.072982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 23:55:54.073037 ==
867 23:55:54.073091 RX Vref Scan: 0
868 23:55:54.073146
869 23:55:54.073200 RX Vref 0 -> 0, step: 1
870 23:55:54.073254
871 23:55:54.073309 RX Delay -130 -> 252, step: 16
872 23:55:54.073363 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 23:55:54.073418 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 23:55:54.073472 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 23:55:54.073526 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 23:55:54.073580 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 23:55:54.073634 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 23:55:54.073689 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
879 23:55:54.073742 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
880 23:55:54.073796 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 23:55:54.073850 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 23:55:54.073904 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 23:55:54.073958 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 23:55:54.074012 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
885 23:55:54.074066 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 23:55:54.074120 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 23:55:54.074192 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 23:55:54.074282 ==
889 23:55:54.074336 Dram Type= 6, Freq= 0, CH_0, rank 0
890 23:55:54.074389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 23:55:54.074442 ==
892 23:55:54.074495 DQS Delay:
893 23:55:54.074547 DQS0 = 0, DQS1 = 0
894 23:55:54.074600 DQM Delay:
895 23:55:54.074652 DQM0 = 86, DQM1 = 76
896 23:55:54.074706 DQ Delay:
897 23:55:54.074759 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 23:55:54.074812 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
899 23:55:54.074865 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
900 23:55:54.074918 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
901 23:55:54.074970
902 23:55:54.075023
903 23:55:54.075074 ==
904 23:55:54.075128 Dram Type= 6, Freq= 0, CH_0, rank 0
905 23:55:54.075181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 23:55:54.075234 ==
907 23:55:54.075287
908 23:55:54.075340
909 23:55:54.075392 TX Vref Scan disable
910 23:55:54.075445 == TX Byte 0 ==
911 23:55:54.075498 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 23:55:54.075552 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 23:55:54.075605 == TX Byte 1 ==
914 23:55:54.075657 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 23:55:54.075710 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 23:55:54.075763 ==
917 23:55:54.075816 Dram Type= 6, Freq= 0, CH_0, rank 0
918 23:55:54.075870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 23:55:54.075923 ==
920 23:55:54.075977 TX Vref=22, minBit 4, minWin=27, winSum=439
921 23:55:54.076031 TX Vref=24, minBit 5, minWin=27, winSum=445
922 23:55:54.076276 TX Vref=26, minBit 5, minWin=27, winSum=443
923 23:55:54.076334 TX Vref=28, minBit 8, minWin=27, winSum=447
924 23:55:54.076390 TX Vref=30, minBit 9, minWin=27, winSum=446
925 23:55:54.076444 TX Vref=32, minBit 4, minWin=27, winSum=442
926 23:55:54.076498 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
927 23:55:54.076552
928 23:55:54.076606 Final TX Range 1 Vref 28
929 23:55:54.076659
930 23:55:54.076712 ==
931 23:55:54.076765 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:55:54.076820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:55:54.076874 ==
934 23:55:54.076927
935 23:55:54.076980
936 23:55:54.077033 TX Vref Scan disable
937 23:55:54.077086 == TX Byte 0 ==
938 23:55:54.077139 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 23:55:54.077193 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 23:55:54.077246 == TX Byte 1 ==
941 23:55:54.077300 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 23:55:54.077353 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 23:55:54.077410
944 23:55:54.077463 [DATLAT]
945 23:55:54.077516 Freq=800, CH0 RK0
946 23:55:54.077569
947 23:55:54.077622 DATLAT Default: 0xa
948 23:55:54.077676 0, 0xFFFF, sum = 0
949 23:55:54.077730 1, 0xFFFF, sum = 0
950 23:55:54.077784 2, 0xFFFF, sum = 0
951 23:55:54.077838 3, 0xFFFF, sum = 0
952 23:55:54.077892 4, 0xFFFF, sum = 0
953 23:55:54.077946 5, 0xFFFF, sum = 0
954 23:55:54.078000 6, 0xFFFF, sum = 0
955 23:55:54.078054 7, 0xFFFF, sum = 0
956 23:55:54.078108 8, 0xFFFF, sum = 0
957 23:55:54.078170 9, 0x0, sum = 1
958 23:55:54.078261 10, 0x0, sum = 2
959 23:55:54.078315 11, 0x0, sum = 3
960 23:55:54.078370 12, 0x0, sum = 4
961 23:55:54.078423 best_step = 10
962 23:55:54.078476
963 23:55:54.078529 ==
964 23:55:54.078583 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:55:54.078636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 23:55:54.078690 ==
967 23:55:54.078743 RX Vref Scan: 1
968 23:55:54.078796
969 23:55:54.078849 Set Vref Range= 32 -> 127
970 23:55:54.078903
971 23:55:54.078956 RX Vref 32 -> 127, step: 1
972 23:55:54.079010
973 23:55:54.079062 RX Delay -95 -> 252, step: 8
974 23:55:54.079115
975 23:55:54.079169 Set Vref, RX VrefLevel [Byte0]: 32
976 23:55:54.079222 [Byte1]: 32
977 23:55:54.079275
978 23:55:54.079328 Set Vref, RX VrefLevel [Byte0]: 33
979 23:55:54.079382 [Byte1]: 33
980 23:55:54.079435
981 23:55:54.079488 Set Vref, RX VrefLevel [Byte0]: 34
982 23:55:54.079541 [Byte1]: 34
983 23:55:54.079594
984 23:55:54.079647 Set Vref, RX VrefLevel [Byte0]: 35
985 23:55:54.079700 [Byte1]: 35
986 23:55:54.079752
987 23:55:54.079806 Set Vref, RX VrefLevel [Byte0]: 36
988 23:55:54.079860 [Byte1]: 36
989 23:55:54.079913
990 23:55:54.079966 Set Vref, RX VrefLevel [Byte0]: 37
991 23:55:54.080019 [Byte1]: 37
992 23:55:54.080072
993 23:55:54.080125 Set Vref, RX VrefLevel [Byte0]: 38
994 23:55:54.080178 [Byte1]: 38
995 23:55:54.080230
996 23:55:54.080283 Set Vref, RX VrefLevel [Byte0]: 39
997 23:55:54.080336 [Byte1]: 39
998 23:55:54.080389
999 23:55:54.080442 Set Vref, RX VrefLevel [Byte0]: 40
1000 23:55:54.080514 [Byte1]: 40
1001 23:55:54.080569
1002 23:55:54.080622 Set Vref, RX VrefLevel [Byte0]: 41
1003 23:55:54.080675 [Byte1]: 41
1004 23:55:54.080728
1005 23:55:54.080781 Set Vref, RX VrefLevel [Byte0]: 42
1006 23:55:54.080834 [Byte1]: 42
1007 23:55:54.080887
1008 23:55:54.080940 Set Vref, RX VrefLevel [Byte0]: 43
1009 23:55:54.080994 [Byte1]: 43
1010 23:55:54.081046
1011 23:55:54.081099 Set Vref, RX VrefLevel [Byte0]: 44
1012 23:55:54.081152 [Byte1]: 44
1013 23:55:54.081206
1014 23:55:54.081258 Set Vref, RX VrefLevel [Byte0]: 45
1015 23:55:54.081311 [Byte1]: 45
1016 23:55:54.081364
1017 23:55:54.081417 Set Vref, RX VrefLevel [Byte0]: 46
1018 23:55:54.081471 [Byte1]: 46
1019 23:55:54.081524
1020 23:55:54.081577 Set Vref, RX VrefLevel [Byte0]: 47
1021 23:55:54.081631 [Byte1]: 47
1022 23:55:54.081684
1023 23:55:54.081737 Set Vref, RX VrefLevel [Byte0]: 48
1024 23:55:54.081790 [Byte1]: 48
1025 23:55:54.081849
1026 23:55:54.081904 Set Vref, RX VrefLevel [Byte0]: 49
1027 23:55:54.081957 [Byte1]: 49
1028 23:55:54.082011
1029 23:55:54.082064 Set Vref, RX VrefLevel [Byte0]: 50
1030 23:55:54.082117 [Byte1]: 50
1031 23:55:54.082178
1032 23:55:54.082232 Set Vref, RX VrefLevel [Byte0]: 51
1033 23:55:54.082286 [Byte1]: 51
1034 23:55:54.082339
1035 23:55:54.082391 Set Vref, RX VrefLevel [Byte0]: 52
1036 23:55:54.082443 [Byte1]: 52
1037 23:55:54.082496
1038 23:55:54.082548 Set Vref, RX VrefLevel [Byte0]: 53
1039 23:55:54.082601 [Byte1]: 53
1040 23:55:54.082654
1041 23:55:54.082706 Set Vref, RX VrefLevel [Byte0]: 54
1042 23:55:54.082759 [Byte1]: 54
1043 23:55:54.082811
1044 23:55:54.082863 Set Vref, RX VrefLevel [Byte0]: 55
1045 23:55:54.082916 [Byte1]: 55
1046 23:55:54.082968
1047 23:55:54.083021 Set Vref, RX VrefLevel [Byte0]: 56
1048 23:55:54.083073 [Byte1]: 56
1049 23:55:54.083127
1050 23:55:54.083179 Set Vref, RX VrefLevel [Byte0]: 57
1051 23:55:54.083232 [Byte1]: 57
1052 23:55:54.083285
1053 23:55:54.083337 Set Vref, RX VrefLevel [Byte0]: 58
1054 23:55:54.083390 [Byte1]: 58
1055 23:55:54.083443
1056 23:55:54.083496 Set Vref, RX VrefLevel [Byte0]: 59
1057 23:55:54.083548 [Byte1]: 59
1058 23:55:54.083600
1059 23:55:54.083652 Set Vref, RX VrefLevel [Byte0]: 60
1060 23:55:54.083705 [Byte1]: 60
1061 23:55:54.083758
1062 23:55:54.083810 Set Vref, RX VrefLevel [Byte0]: 61
1063 23:55:54.083862 [Byte1]: 61
1064 23:55:54.083915
1065 23:55:54.083986 Set Vref, RX VrefLevel [Byte0]: 62
1066 23:55:54.084040 [Byte1]: 62
1067 23:55:54.084093
1068 23:55:54.084145 Set Vref, RX VrefLevel [Byte0]: 63
1069 23:55:54.084199 [Byte1]: 63
1070 23:55:54.084251
1071 23:55:54.084304 Set Vref, RX VrefLevel [Byte0]: 64
1072 23:55:54.084357 [Byte1]: 64
1073 23:55:54.084409
1074 23:55:54.084461 Set Vref, RX VrefLevel [Byte0]: 65
1075 23:55:54.084515 [Byte1]: 65
1076 23:55:54.084568
1077 23:55:54.084620 Set Vref, RX VrefLevel [Byte0]: 66
1078 23:55:54.084673 [Byte1]: 66
1079 23:55:54.084725
1080 23:55:54.084777 Set Vref, RX VrefLevel [Byte0]: 67
1081 23:55:54.084830 [Byte1]: 67
1082 23:55:54.084883
1083 23:55:54.084936 Set Vref, RX VrefLevel [Byte0]: 68
1084 23:55:54.084989 [Byte1]: 68
1085 23:55:54.085042
1086 23:55:54.085094 Set Vref, RX VrefLevel [Byte0]: 69
1087 23:55:54.085147 [Byte1]: 69
1088 23:55:54.085199
1089 23:55:54.085252 Set Vref, RX VrefLevel [Byte0]: 70
1090 23:55:54.085495 [Byte1]: 70
1091 23:55:54.085556
1092 23:55:54.085610 Set Vref, RX VrefLevel [Byte0]: 71
1093 23:55:54.085664 [Byte1]: 71
1094 23:55:54.085717
1095 23:55:54.085770 Set Vref, RX VrefLevel [Byte0]: 72
1096 23:55:54.085822 [Byte1]: 72
1097 23:55:54.085875
1098 23:55:54.085926 Set Vref, RX VrefLevel [Byte0]: 73
1099 23:55:54.085979 [Byte1]: 73
1100 23:55:54.086031
1101 23:55:54.086083 Set Vref, RX VrefLevel [Byte0]: 74
1102 23:55:54.086136 [Byte1]: 74
1103 23:55:54.086200
1104 23:55:54.086253 Set Vref, RX VrefLevel [Byte0]: 75
1105 23:55:54.086306 [Byte1]: 75
1106 23:55:54.086358
1107 23:55:54.086411 Set Vref, RX VrefLevel [Byte0]: 76
1108 23:55:54.086463 [Byte1]: 76
1109 23:55:54.086515
1110 23:55:54.086568 Set Vref, RX VrefLevel [Byte0]: 77
1111 23:55:54.086621 [Byte1]: 77
1112 23:55:54.086674
1113 23:55:54.086726 Set Vref, RX VrefLevel [Byte0]: 78
1114 23:55:54.086778 [Byte1]: 78
1115 23:55:54.086831
1116 23:55:54.086883 Set Vref, RX VrefLevel [Byte0]: 79
1117 23:55:54.086936 [Byte1]: 79
1118 23:55:54.086988
1119 23:55:54.087040 Set Vref, RX VrefLevel [Byte0]: 80
1120 23:55:54.087093 [Byte1]: 80
1121 23:55:54.087146
1122 23:55:54.087198 Set Vref, RX VrefLevel [Byte0]: 81
1123 23:55:54.087250 [Byte1]: 81
1124 23:55:54.087302
1125 23:55:54.087355 Set Vref, RX VrefLevel [Byte0]: 82
1126 23:55:54.087407 [Byte1]: 82
1127 23:55:54.087459
1128 23:55:54.087512 Set Vref, RX VrefLevel [Byte0]: 83
1129 23:55:54.087564 [Byte1]: 83
1130 23:55:54.087617
1131 23:55:54.087670 Final RX Vref Byte 0 = 63 to rank0
1132 23:55:54.087723 Final RX Vref Byte 1 = 57 to rank0
1133 23:55:54.087776 Final RX Vref Byte 0 = 63 to rank1
1134 23:55:54.087829 Final RX Vref Byte 1 = 57 to rank1==
1135 23:55:54.087881 Dram Type= 6, Freq= 0, CH_0, rank 0
1136 23:55:54.087934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 23:55:54.087987 ==
1138 23:55:54.088040 DQS Delay:
1139 23:55:54.088092 DQS0 = 0, DQS1 = 0
1140 23:55:54.088145 DQM Delay:
1141 23:55:54.088197 DQM0 = 87, DQM1 = 75
1142 23:55:54.088249 DQ Delay:
1143 23:55:54.088301 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1144 23:55:54.088354 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1145 23:55:54.088406 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1146 23:55:54.088459 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1147 23:55:54.088511
1148 23:55:54.088563
1149 23:55:54.088615 [DQSOSCAuto] RK0, (LSB)MR18= 0x4223, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1150 23:55:54.088670 CH0 RK0: MR19=606, MR18=4223
1151 23:55:54.088723 CH0_RK0: MR19=0x606, MR18=0x4223, DQSOSC=393, MR23=63, INC=95, DEC=63
1152 23:55:54.088775
1153 23:55:54.088828 ----->DramcWriteLeveling(PI) begin...
1154 23:55:54.088881 ==
1155 23:55:54.088934 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 23:55:54.088987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 23:55:54.089040 ==
1158 23:55:54.089093 Write leveling (Byte 0): 33 => 33
1159 23:55:54.089146 Write leveling (Byte 1): 30 => 30
1160 23:55:54.089199 DramcWriteLeveling(PI) end<-----
1161 23:55:54.089251
1162 23:55:54.089304 ==
1163 23:55:54.089356 Dram Type= 6, Freq= 0, CH_0, rank 1
1164 23:55:54.089409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1165 23:55:54.089462 ==
1166 23:55:54.089515 [Gating] SW mode calibration
1167 23:55:54.089568 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1168 23:55:54.089621 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1169 23:55:54.089674 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 23:55:54.089727 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 23:55:54.089780 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1172 23:55:54.089833 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:55:54.089886 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:55:54.089939 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:55:54.089992 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:55:54.090044 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:55:54.090097 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:55:54.090149 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:55:54.090206 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:55:54.090259 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:55:54.090312 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:55:54.090364 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:55:54.090417 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:55:54.090470 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:55:54.090522 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:55:54.090574 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1187 23:55:54.090627 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1188 23:55:54.090679 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1189 23:55:54.090732 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:55:54.090784 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:55:54.090837 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:55:54.090890 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:55:54.090943 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:55:54.090995 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:55:54.091048 0 9 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1196 23:55:54.091101 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 23:55:54.091153 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 23:55:54.091206 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 23:55:54.091259 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 23:55:54.091312 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 23:55:54.091365 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 23:55:54.091418 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1203 23:55:54.091471 0 10 8 | B1->B0 | 3030 2b2b | 1 1 | (1 1) (1 0)
1204 23:55:54.091524 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1205 23:55:54.091577 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:55:54.091817 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:55:54.091876 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:55:54.091929 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:55:54.091983 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 23:55:54.092037 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1211 23:55:54.092090 0 11 8 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
1212 23:55:54.092143 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1213 23:55:54.092196 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 23:55:54.092248 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 23:55:54.092302 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 23:55:54.092355 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 23:55:54.092408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 23:55:54.092460 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1219 23:55:54.092513 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1220 23:55:54.092566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:55:54.092618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:55:54.092671 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:55:54.092723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:55:54.092776 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 23:55:54.092829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 23:55:54.092882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 23:55:54.092934 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 23:55:54.092987 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 23:55:54.093039 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 23:55:54.093093 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 23:55:54.093146 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 23:55:54.093198 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 23:55:54.093251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 23:55:54.093304 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 23:55:54.093356 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1236 23:55:54.093408 Total UI for P1: 0, mck2ui 16
1237 23:55:54.093462 best dqsien dly found for B0: ( 0, 14, 6)
1238 23:55:54.093515 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 23:55:54.093567 Total UI for P1: 0, mck2ui 16
1240 23:55:54.093621 best dqsien dly found for B1: ( 0, 14, 8)
1241 23:55:54.093674 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1242 23:55:54.093727 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1243 23:55:54.093779
1244 23:55:54.093832 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1245 23:55:54.093885 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1246 23:55:54.093938 [Gating] SW calibration Done
1247 23:55:54.093991 ==
1248 23:55:54.094043 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 23:55:54.094096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 23:55:54.094149 ==
1251 23:55:54.094208 RX Vref Scan: 0
1252 23:55:54.094260
1253 23:55:54.094313 RX Vref 0 -> 0, step: 1
1254 23:55:54.094366
1255 23:55:54.094418 RX Delay -130 -> 252, step: 16
1256 23:55:54.094471 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1257 23:55:54.094523 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1258 23:55:54.094576 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1259 23:55:54.094629 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1260 23:55:54.094682 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1261 23:55:54.094735 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1262 23:55:54.094788 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1263 23:55:54.094840 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1264 23:55:54.094893 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1265 23:55:54.094946 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1266 23:55:54.094998 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1267 23:55:54.095051 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1268 23:55:54.095103 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1269 23:55:54.095155 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1270 23:55:54.095208 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1271 23:55:54.095261 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1272 23:55:54.095313 ==
1273 23:55:54.095366 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 23:55:54.095418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 23:55:54.095471 ==
1276 23:55:54.095524 DQS Delay:
1277 23:55:54.095576 DQS0 = 0, DQS1 = 0
1278 23:55:54.095628 DQM Delay:
1279 23:55:54.095681 DQM0 = 84, DQM1 = 75
1280 23:55:54.095734 DQ Delay:
1281 23:55:54.095787 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1282 23:55:54.095840 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1283 23:55:54.095893 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1284 23:55:54.095946 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1285 23:55:54.095998
1286 23:55:54.096051
1287 23:55:54.096102 ==
1288 23:55:54.096155 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 23:55:54.096208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 23:55:54.096261 ==
1291 23:55:54.096313
1292 23:55:54.096366
1293 23:55:54.096418 TX Vref Scan disable
1294 23:55:54.096470 == TX Byte 0 ==
1295 23:55:54.096522 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1296 23:55:54.096574 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1297 23:55:54.096626 == TX Byte 1 ==
1298 23:55:54.096678 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1299 23:55:54.096730 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1300 23:55:54.096782 ==
1301 23:55:54.096834 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 23:55:54.096887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 23:55:54.096939 ==
1304 23:55:54.096991 TX Vref=22, minBit 8, minWin=26, winSum=442
1305 23:55:54.097044 TX Vref=24, minBit 8, minWin=27, winSum=446
1306 23:55:54.097097 TX Vref=26, minBit 8, minWin=27, winSum=447
1307 23:55:54.097150 TX Vref=28, minBit 0, minWin=28, winSum=451
1308 23:55:54.097202 TX Vref=30, minBit 9, minWin=27, winSum=451
1309 23:55:54.097255 TX Vref=32, minBit 9, minWin=27, winSum=447
1310 23:55:54.097308 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 28
1311 23:55:54.097360
1312 23:55:54.097411 Final TX Range 1 Vref 28
1313 23:55:54.097463
1314 23:55:54.097515 ==
1315 23:55:54.097567 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 23:55:54.097619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 23:55:54.097671 ==
1318 23:55:54.097723
1319 23:55:54.097774
1320 23:55:54.097826 TX Vref Scan disable
1321 23:55:54.097878 == TX Byte 0 ==
1322 23:55:54.098120 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1323 23:55:54.098184 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1324 23:55:54.098238 == TX Byte 1 ==
1325 23:55:54.098291 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1326 23:55:54.098344 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1327 23:55:54.098396
1328 23:55:54.098447 [DATLAT]
1329 23:55:54.098499 Freq=800, CH0 RK1
1330 23:55:54.098571
1331 23:55:54.098625 DATLAT Default: 0xa
1332 23:55:54.098678 0, 0xFFFF, sum = 0
1333 23:55:54.098732 1, 0xFFFF, sum = 0
1334 23:55:54.098785 2, 0xFFFF, sum = 0
1335 23:55:54.098840 3, 0xFFFF, sum = 0
1336 23:55:54.098893 4, 0xFFFF, sum = 0
1337 23:55:54.098946 5, 0xFFFF, sum = 0
1338 23:55:54.098998 6, 0xFFFF, sum = 0
1339 23:55:54.099051 7, 0xFFFF, sum = 0
1340 23:55:54.099104 8, 0xFFFF, sum = 0
1341 23:55:54.099157 9, 0x0, sum = 1
1342 23:55:54.099209 10, 0x0, sum = 2
1343 23:55:54.099263 11, 0x0, sum = 3
1344 23:55:54.099316 12, 0x0, sum = 4
1345 23:55:54.099368 best_step = 10
1346 23:55:54.099420
1347 23:55:54.099472 ==
1348 23:55:54.099524 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 23:55:54.099576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 23:55:54.099629 ==
1351 23:55:54.099681 RX Vref Scan: 0
1352 23:55:54.099732
1353 23:55:54.099784 RX Vref 0 -> 0, step: 1
1354 23:55:54.099835
1355 23:55:54.099886 RX Delay -111 -> 252, step: 8
1356 23:55:54.099938 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1357 23:55:54.099990 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1358 23:55:54.100043 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1359 23:55:54.100095 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1360 23:55:54.100147 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1361 23:55:54.100199 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1362 23:55:54.100251 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1363 23:55:54.100303 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1364 23:55:54.100355 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1365 23:55:54.100407 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1366 23:55:54.100459 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1367 23:55:54.100511 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1368 23:55:54.100563 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1369 23:55:54.100615 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1370 23:55:54.100667 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1371 23:55:54.100719 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1372 23:55:54.100770 ==
1373 23:55:54.100822 Dram Type= 6, Freq= 0, CH_0, rank 1
1374 23:55:54.100874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 23:55:54.100928 ==
1376 23:55:54.100980 DQS Delay:
1377 23:55:54.101032 DQS0 = 0, DQS1 = 0
1378 23:55:54.101083 DQM Delay:
1379 23:55:54.101135 DQM0 = 85, DQM1 = 76
1380 23:55:54.101187 DQ Delay:
1381 23:55:54.101238 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1382 23:55:54.101290 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1383 23:55:54.101342 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1384 23:55:54.101394 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =84
1385 23:55:54.101445
1386 23:55:54.101497
1387 23:55:54.101549 [DQSOSCAuto] RK1, (LSB)MR18= 0x4007, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1388 23:55:54.101610 CH0 RK1: MR19=606, MR18=4007
1389 23:55:54.101684 CH0_RK1: MR19=0x606, MR18=0x4007, DQSOSC=393, MR23=63, INC=95, DEC=63
1390 23:55:54.101748 [RxdqsGatingPostProcess] freq 800
1391 23:55:54.101802 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1392 23:55:54.101854 Pre-setting of DQS Precalculation
1393 23:55:54.101906 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1394 23:55:54.101962 ==
1395 23:55:54.102015 Dram Type= 6, Freq= 0, CH_1, rank 0
1396 23:55:54.102068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 23:55:54.102149 ==
1398 23:55:54.102244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 23:55:54.102299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 23:55:54.102352 [CA 0] Center 36 (6~67) winsize 62
1401 23:55:54.102404 [CA 1] Center 36 (6~67) winsize 62
1402 23:55:54.102456 [CA 2] Center 34 (4~65) winsize 62
1403 23:55:54.102509 [CA 3] Center 34 (3~65) winsize 63
1404 23:55:54.102561 [CA 4] Center 34 (4~65) winsize 62
1405 23:55:54.102613 [CA 5] Center 34 (3~65) winsize 63
1406 23:55:54.102665
1407 23:55:54.102717 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1408 23:55:54.102770
1409 23:55:54.102822 [CATrainingPosCal] consider 1 rank data
1410 23:55:54.102874 u2DelayCellTimex100 = 270/100 ps
1411 23:55:54.102926 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 23:55:54.102979 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 23:55:54.103031 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 23:55:54.103084 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1415 23:55:54.103137 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 23:55:54.103188 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1417 23:55:54.103240
1418 23:55:54.103292 CA PerBit enable=1, Macro0, CA PI delay=34
1419 23:55:54.103344
1420 23:55:54.103396 [CBTSetCACLKResult] CA Dly = 34
1421 23:55:54.103448 CS Dly: 5 (0~36)
1422 23:55:54.103500 ==
1423 23:55:54.103551 Dram Type= 6, Freq= 0, CH_1, rank 1
1424 23:55:54.103603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 23:55:54.103656 ==
1426 23:55:54.103709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1427 23:55:54.103761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1428 23:55:54.103814 [CA 0] Center 36 (6~67) winsize 62
1429 23:55:54.103866 [CA 1] Center 36 (6~67) winsize 62
1430 23:55:54.103918 [CA 2] Center 34 (4~65) winsize 62
1431 23:55:54.103970 [CA 3] Center 34 (3~65) winsize 63
1432 23:55:54.104022 [CA 4] Center 34 (4~65) winsize 62
1433 23:55:54.104074 [CA 5] Center 34 (3~65) winsize 63
1434 23:55:54.104135
1435 23:55:54.104189 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1436 23:55:54.104242
1437 23:55:54.104294 [CATrainingPosCal] consider 2 rank data
1438 23:55:54.104346 u2DelayCellTimex100 = 270/100 ps
1439 23:55:54.104398 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1440 23:55:54.104450 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1441 23:55:54.104503 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 23:55:54.104555 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1443 23:55:54.104607 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 23:55:54.104659 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1445 23:55:54.104710
1446 23:55:54.104762 CA PerBit enable=1, Macro0, CA PI delay=34
1447 23:55:54.104814
1448 23:55:54.104865 [CBTSetCACLKResult] CA Dly = 34
1449 23:55:54.104917 CS Dly: 6 (0~38)
1450 23:55:54.104969
1451 23:55:54.105020 ----->DramcWriteLeveling(PI) begin...
1452 23:55:54.105086 ==
1453 23:55:54.105142 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 23:55:54.105389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 23:55:54.105453 ==
1456 23:55:54.105507 Write leveling (Byte 0): 28 => 28
1457 23:55:54.105561 Write leveling (Byte 1): 28 => 28
1458 23:55:54.105626 DramcWriteLeveling(PI) end<-----
1459 23:55:54.105680
1460 23:55:54.105733 ==
1461 23:55:54.105785 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 23:55:54.105838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 23:55:54.105891 ==
1464 23:55:54.105943 [Gating] SW mode calibration
1465 23:55:54.105995 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1466 23:55:54.106048 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1467 23:55:54.106101 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1468 23:55:54.106154 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1469 23:55:54.106213 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:55:54.106266 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:55:54.106318 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:55:54.106371 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:55:54.106422 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:55:54.106474 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:55:54.106526 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:55:54.106578 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:55:54.106630 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:55:54.106682 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:55:54.106734 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:55:54.106786 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:55:54.106839 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:55:54.106890 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:55:54.106942 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1484 23:55:54.106994 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1485 23:55:54.107046 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:55:54.107097 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:55:54.107149 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:55:54.107200 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:55:54.107253 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:55:54.107306 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:55:54.107358 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:55:54.107410 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:55:54.107462 0 9 8 | B1->B0 | 2c2c 2e2e | 1 0 | (0 0) (0 0)
1494 23:55:54.107514 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 23:55:54.107566 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 23:55:54.107618 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 23:55:54.107670 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 23:55:54.107722 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 23:55:54.107774 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 23:55:54.107827 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 1)
1501 23:55:54.107879 0 10 8 | B1->B0 | 2929 2828 | 0 0 | (1 0) (1 1)
1502 23:55:54.107931 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:55:54.107984 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:55:54.108035 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:55:54.108087 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:55:54.108139 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:55:54.108191 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:55:54.108243 0 11 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (1 1)
1509 23:55:54.108295 0 11 8 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (1 1)
1510 23:55:54.108347 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 23:55:54.108399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 23:55:54.108451 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 23:55:54.108503 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 23:55:54.108555 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 23:55:54.108608 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 23:55:54.108660 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 23:55:54.108712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1518 23:55:54.108764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:55:54.108816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:55:54.108867 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:55:54.108920 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 23:55:54.108972 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 23:55:54.109025 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 23:55:54.109077 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 23:55:54.109129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 23:55:54.109180 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 23:55:54.109232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 23:55:54.109284 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 23:55:54.109336 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 23:55:54.109388 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 23:55:54.109440 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 23:55:54.109491 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1533 23:55:54.109543 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 23:55:54.109595 Total UI for P1: 0, mck2ui 16
1535 23:55:54.109647 best dqsien dly found for B0: ( 0, 14, 4)
1536 23:55:54.109700 Total UI for P1: 0, mck2ui 16
1537 23:55:54.109752 best dqsien dly found for B1: ( 0, 14, 4)
1538 23:55:54.109804 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1539 23:55:54.109856 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1540 23:55:54.109909
1541 23:55:54.109960 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1542 23:55:54.110204 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1543 23:55:54.110262 [Gating] SW calibration Done
1544 23:55:54.110315 ==
1545 23:55:54.110368 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 23:55:54.110420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 23:55:54.110473 ==
1548 23:55:54.110525 RX Vref Scan: 0
1549 23:55:54.110576
1550 23:55:54.110628 RX Vref 0 -> 0, step: 1
1551 23:55:54.110680
1552 23:55:54.110732 RX Delay -130 -> 252, step: 16
1553 23:55:54.110784 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1554 23:55:54.110836 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1555 23:55:54.110888 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1556 23:55:54.110940 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1557 23:55:54.110992 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1558 23:55:54.111044 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1559 23:55:54.111097 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1560 23:55:54.111149 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1561 23:55:54.111201 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1562 23:55:54.111253 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1563 23:55:54.111305 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1564 23:55:54.111357 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1565 23:55:54.111409 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1566 23:55:54.111461 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1567 23:55:54.111513 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1568 23:55:54.111564 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1569 23:55:54.111616 ==
1570 23:55:54.111668 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 23:55:54.111720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 23:55:54.111773 ==
1573 23:55:54.111825 DQS Delay:
1574 23:55:54.111877 DQS0 = 0, DQS1 = 0
1575 23:55:54.111929 DQM Delay:
1576 23:55:54.111980 DQM0 = 89, DQM1 = 78
1577 23:55:54.112032 DQ Delay:
1578 23:55:54.112083 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1579 23:55:54.112135 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1580 23:55:54.112187 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1581 23:55:54.112240 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1582 23:55:54.112291
1583 23:55:54.112343
1584 23:55:54.112394 ==
1585 23:55:54.112446 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 23:55:54.112497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 23:55:54.112549 ==
1588 23:55:54.112600
1589 23:55:54.112651
1590 23:55:54.112703 TX Vref Scan disable
1591 23:55:54.112755 == TX Byte 0 ==
1592 23:55:54.112807 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1593 23:55:54.112859 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1594 23:55:54.112911 == TX Byte 1 ==
1595 23:55:54.112962 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1596 23:55:54.113014 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1597 23:55:54.113065 ==
1598 23:55:54.113117 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 23:55:54.113170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 23:55:54.113223 ==
1601 23:55:54.113275 TX Vref=22, minBit 15, minWin=26, winSum=442
1602 23:55:54.113327 TX Vref=24, minBit 9, minWin=27, winSum=448
1603 23:55:54.113380 TX Vref=26, minBit 9, minWin=27, winSum=452
1604 23:55:54.113432 TX Vref=28, minBit 11, minWin=27, winSum=453
1605 23:55:54.113485 TX Vref=30, minBit 9, minWin=27, winSum=447
1606 23:55:54.113538 TX Vref=32, minBit 8, minWin=27, winSum=449
1607 23:55:54.113590 [TxChooseVref] Worse bit 11, Min win 27, Win sum 453, Final Vref 28
1608 23:55:54.113643
1609 23:55:54.113694 Final TX Range 1 Vref 28
1610 23:55:54.113746
1611 23:55:54.113798 ==
1612 23:55:54.113849 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 23:55:54.113902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 23:55:54.113954 ==
1615 23:55:54.114005
1616 23:55:54.114057
1617 23:55:54.114108 TX Vref Scan disable
1618 23:55:54.114168 == TX Byte 0 ==
1619 23:55:54.114221 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1620 23:55:54.114275 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1621 23:55:54.114327 == TX Byte 1 ==
1622 23:55:54.114379 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1623 23:55:54.114431 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1624 23:55:54.114483
1625 23:55:54.114534 [DATLAT]
1626 23:55:54.114585 Freq=800, CH1 RK0
1627 23:55:54.114638
1628 23:55:54.114689 DATLAT Default: 0xa
1629 23:55:54.114741 0, 0xFFFF, sum = 0
1630 23:55:54.114795 1, 0xFFFF, sum = 0
1631 23:55:54.114851 2, 0xFFFF, sum = 0
1632 23:55:54.114903 3, 0xFFFF, sum = 0
1633 23:55:54.114956 4, 0xFFFF, sum = 0
1634 23:55:54.115009 5, 0xFFFF, sum = 0
1635 23:55:54.115074 6, 0xFFFF, sum = 0
1636 23:55:54.115127 7, 0xFFFF, sum = 0
1637 23:55:54.115180 8, 0xFFFF, sum = 0
1638 23:55:54.115244 9, 0x0, sum = 1
1639 23:55:54.115299 10, 0x0, sum = 2
1640 23:55:54.115352 11, 0x0, sum = 3
1641 23:55:54.115406 12, 0x0, sum = 4
1642 23:55:54.115469 best_step = 10
1643 23:55:54.115521
1644 23:55:54.115572 ==
1645 23:55:54.115634 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 23:55:54.115688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 23:55:54.115740 ==
1648 23:55:54.115804 RX Vref Scan: 1
1649 23:55:54.115857
1650 23:55:54.115909 Set Vref Range= 32 -> 127
1651 23:55:54.115963
1652 23:55:54.116015 RX Vref 32 -> 127, step: 1
1653 23:55:54.116067
1654 23:55:54.116118 RX Delay -95 -> 252, step: 8
1655 23:55:54.116173
1656 23:55:54.116225 Set Vref, RX VrefLevel [Byte0]: 32
1657 23:55:54.116277 [Byte1]: 32
1658 23:55:54.116329
1659 23:55:54.116383 Set Vref, RX VrefLevel [Byte0]: 33
1660 23:55:54.116435 [Byte1]: 33
1661 23:55:54.116487
1662 23:55:54.116538 Set Vref, RX VrefLevel [Byte0]: 34
1663 23:55:54.116590 [Byte1]: 34
1664 23:55:54.116643
1665 23:55:54.116694 Set Vref, RX VrefLevel [Byte0]: 35
1666 23:55:54.116746 [Byte1]: 35
1667 23:55:54.116798
1668 23:55:54.116850 Set Vref, RX VrefLevel [Byte0]: 36
1669 23:55:54.116901 [Byte1]: 36
1670 23:55:54.116953
1671 23:55:54.117005 Set Vref, RX VrefLevel [Byte0]: 37
1672 23:55:54.117057 [Byte1]: 37
1673 23:55:54.117109
1674 23:55:54.117160 Set Vref, RX VrefLevel [Byte0]: 38
1675 23:55:54.117212 [Byte1]: 38
1676 23:55:54.117264
1677 23:55:54.117316 Set Vref, RX VrefLevel [Byte0]: 39
1678 23:55:54.117367 [Byte1]: 39
1679 23:55:54.117419
1680 23:55:54.117470 Set Vref, RX VrefLevel [Byte0]: 40
1681 23:55:54.117522 [Byte1]: 40
1682 23:55:54.117574
1683 23:55:54.117626 Set Vref, RX VrefLevel [Byte0]: 41
1684 23:55:54.117677 [Byte1]: 41
1685 23:55:54.117730
1686 23:55:54.117781 Set Vref, RX VrefLevel [Byte0]: 42
1687 23:55:54.117833 [Byte1]: 42
1688 23:55:54.117885
1689 23:55:54.117937 Set Vref, RX VrefLevel [Byte0]: 43
1690 23:55:54.117989 [Byte1]: 43
1691 23:55:54.118042
1692 23:55:54.118093 Set Vref, RX VrefLevel [Byte0]: 44
1693 23:55:54.118145 [Byte1]: 44
1694 23:55:54.118202
1695 23:55:54.118254 Set Vref, RX VrefLevel [Byte0]: 45
1696 23:55:54.118306 [Byte1]: 45
1697 23:55:54.118358
1698 23:55:54.118600 Set Vref, RX VrefLevel [Byte0]: 46
1699 23:55:54.118658 [Byte1]: 46
1700 23:55:54.118711
1701 23:55:54.118764 Set Vref, RX VrefLevel [Byte0]: 47
1702 23:55:54.118816 [Byte1]: 47
1703 23:55:54.118868
1704 23:55:54.118919 Set Vref, RX VrefLevel [Byte0]: 48
1705 23:55:54.118971 [Byte1]: 48
1706 23:55:54.119023
1707 23:55:54.119075 Set Vref, RX VrefLevel [Byte0]: 49
1708 23:55:54.119126 [Byte1]: 49
1709 23:55:54.119178
1710 23:55:54.119230 Set Vref, RX VrefLevel [Byte0]: 50
1711 23:55:54.119282 [Byte1]: 50
1712 23:55:54.119333
1713 23:55:54.119384 Set Vref, RX VrefLevel [Byte0]: 51
1714 23:55:54.119436 [Byte1]: 51
1715 23:55:54.119488
1716 23:55:54.119539 Set Vref, RX VrefLevel [Byte0]: 52
1717 23:55:54.119591 [Byte1]: 52
1718 23:55:54.119642
1719 23:55:54.119694 Set Vref, RX VrefLevel [Byte0]: 53
1720 23:55:54.119745 [Byte1]: 53
1721 23:55:54.119797
1722 23:55:54.119848 Set Vref, RX VrefLevel [Byte0]: 54
1723 23:55:54.119900 [Byte1]: 54
1724 23:55:54.119952
1725 23:55:54.120004 Set Vref, RX VrefLevel [Byte0]: 55
1726 23:55:54.120056 [Byte1]: 55
1727 23:55:54.120109
1728 23:55:54.120161 Set Vref, RX VrefLevel [Byte0]: 56
1729 23:55:54.120213 [Byte1]: 56
1730 23:55:54.120265
1731 23:55:54.120317 Set Vref, RX VrefLevel [Byte0]: 57
1732 23:55:54.120369 [Byte1]: 57
1733 23:55:54.120421
1734 23:55:54.120472 Set Vref, RX VrefLevel [Byte0]: 58
1735 23:55:54.120524 [Byte1]: 58
1736 23:55:54.120576
1737 23:55:54.120627 Set Vref, RX VrefLevel [Byte0]: 59
1738 23:55:54.120679 [Byte1]: 59
1739 23:55:54.120731
1740 23:55:54.120782 Set Vref, RX VrefLevel [Byte0]: 60
1741 23:55:54.120835 [Byte1]: 60
1742 23:55:54.120887
1743 23:55:54.120948 Set Vref, RX VrefLevel [Byte0]: 61
1744 23:55:54.121007 [Byte1]: 61
1745 23:55:54.121060
1746 23:55:54.121111 Set Vref, RX VrefLevel [Byte0]: 62
1747 23:55:54.121163 [Byte1]: 62
1748 23:55:54.121215
1749 23:55:54.121267 Set Vref, RX VrefLevel [Byte0]: 63
1750 23:55:54.121319 [Byte1]: 63
1751 23:55:54.121370
1752 23:55:54.121422 Set Vref, RX VrefLevel [Byte0]: 64
1753 23:55:54.121474 [Byte1]: 64
1754 23:55:54.121526
1755 23:55:54.121578 Set Vref, RX VrefLevel [Byte0]: 65
1756 23:55:54.121630 [Byte1]: 65
1757 23:55:54.121681
1758 23:55:54.121733 Set Vref, RX VrefLevel [Byte0]: 66
1759 23:55:54.121785 [Byte1]: 66
1760 23:55:54.121837
1761 23:55:54.121889 Set Vref, RX VrefLevel [Byte0]: 67
1762 23:55:54.121940 [Byte1]: 67
1763 23:55:54.121992
1764 23:55:54.122044 Set Vref, RX VrefLevel [Byte0]: 68
1765 23:55:54.122096 [Byte1]: 68
1766 23:55:54.122148
1767 23:55:54.122210 Set Vref, RX VrefLevel [Byte0]: 69
1768 23:55:54.122263 [Byte1]: 69
1769 23:55:54.122317
1770 23:55:54.122368 Set Vref, RX VrefLevel [Byte0]: 70
1771 23:55:54.122437 [Byte1]: 70
1772 23:55:54.122492
1773 23:55:54.122544 Set Vref, RX VrefLevel [Byte0]: 71
1774 23:55:54.122596 [Byte1]: 71
1775 23:55:54.122649
1776 23:55:54.122700 Set Vref, RX VrefLevel [Byte0]: 72
1777 23:55:54.122752 [Byte1]: 72
1778 23:55:54.122804
1779 23:55:54.122855 Set Vref, RX VrefLevel [Byte0]: 73
1780 23:55:54.122908 [Byte1]: 73
1781 23:55:54.122959
1782 23:55:54.123011 Set Vref, RX VrefLevel [Byte0]: 74
1783 23:55:54.123062 [Byte1]: 74
1784 23:55:54.123114
1785 23:55:54.123166 Set Vref, RX VrefLevel [Byte0]: 75
1786 23:55:54.123218 [Byte1]: 75
1787 23:55:54.123269
1788 23:55:54.123320 Set Vref, RX VrefLevel [Byte0]: 76
1789 23:55:54.123373 [Byte1]: 76
1790 23:55:54.123426
1791 23:55:54.123477 Set Vref, RX VrefLevel [Byte0]: 77
1792 23:55:54.123529 [Byte1]: 77
1793 23:55:54.123581
1794 23:55:54.123633 Final RX Vref Byte 0 = 58 to rank0
1795 23:55:54.123685 Final RX Vref Byte 1 = 66 to rank0
1796 23:55:54.123738 Final RX Vref Byte 0 = 58 to rank1
1797 23:55:54.123791 Final RX Vref Byte 1 = 66 to rank1==
1798 23:55:54.123843 Dram Type= 6, Freq= 0, CH_1, rank 0
1799 23:55:54.123896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 23:55:54.123949 ==
1801 23:55:54.124001 DQS Delay:
1802 23:55:54.124053 DQS0 = 0, DQS1 = 0
1803 23:55:54.124104 DQM Delay:
1804 23:55:54.124156 DQM0 = 86, DQM1 = 78
1805 23:55:54.124208 DQ Delay:
1806 23:55:54.124260 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1807 23:55:54.124312 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1808 23:55:54.124364 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1809 23:55:54.124416 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1810 23:55:54.124469
1811 23:55:54.124522
1812 23:55:54.124573 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1813 23:55:54.124627 CH1 RK0: MR19=606, MR18=301C
1814 23:55:54.124679 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1815 23:55:54.124732
1816 23:55:54.124784 ----->DramcWriteLeveling(PI) begin...
1817 23:55:54.124837 ==
1818 23:55:54.124890 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 23:55:54.124942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 23:55:54.124995 ==
1821 23:55:54.125047 Write leveling (Byte 0): 28 => 28
1822 23:55:54.125100 Write leveling (Byte 1): 28 => 28
1823 23:55:54.125152 DramcWriteLeveling(PI) end<-----
1824 23:55:54.125204
1825 23:55:54.125256 ==
1826 23:55:54.125308 Dram Type= 6, Freq= 0, CH_1, rank 1
1827 23:55:54.125361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 23:55:54.125413 ==
1829 23:55:54.125466 [Gating] SW mode calibration
1830 23:55:54.125518 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1831 23:55:54.125582 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1832 23:55:54.125639 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1833 23:55:54.125692 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1834 23:55:54.125745 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1835 23:55:54.125797 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:55:54.125850 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:55:54.125902 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:55:54.125955 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:55:54.126007 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:55:54.126059 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:55:54.126112 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:55:54.126364 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:55:54.126426 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:55:54.126479 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:55:54.126532 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:55:54.126584 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:55:54.126636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:55:54.126690 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:55:54.126742 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1850 23:55:54.126795 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1851 23:55:54.126847 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:55:54.126899 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:55:54.126951 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:55:54.127004 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:55:54.127055 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:55:54.127107 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:55:54.127159 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:55:54.127211 0 9 8 | B1->B0 | 3030 2424 | 1 1 | (1 1) (0 0)
1859 23:55:54.127263 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1860 23:55:54.127315 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1861 23:55:54.127367 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1862 23:55:54.127419 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 23:55:54.127473 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 23:55:54.127525 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 23:55:54.127577 0 10 4 | B1->B0 | 3030 3434 | 1 0 | (1 0) (0 0)
1866 23:55:54.127629 0 10 8 | B1->B0 | 2828 2e2e | 0 1 | (0 0) (1 0)
1867 23:55:54.127695 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:55:54.127748 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:55:54.127801 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:55:54.127863 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:55:54.127917 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:55:54.127968 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:55:54.128021 0 11 4 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
1874 23:55:54.128085 0 11 8 | B1->B0 | 4545 3636 | 0 0 | (0 0) (0 0)
1875 23:55:54.128138 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1876 23:55:54.128191 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 23:55:54.128254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 23:55:54.128307 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 23:55:54.128359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 23:55:54.128413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 23:55:54.128466 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1882 23:55:54.128519 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1883 23:55:54.128571 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:55:54.128635 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:55:54.128688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 23:55:54.128740 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 23:55:54.128795 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 23:55:54.128847 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 23:55:54.128899 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 23:55:54.128952 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 23:55:54.129013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 23:55:54.129066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 23:55:54.129117 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 23:55:54.129173 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 23:55:54.129225 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 23:55:54.129278 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 23:55:54.129331 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1898 23:55:54.129384 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 23:55:54.129436 Total UI for P1: 0, mck2ui 16
1900 23:55:54.129490 best dqsien dly found for B0: ( 0, 14, 4)
1901 23:55:54.129542 Total UI for P1: 0, mck2ui 16
1902 23:55:54.129595 best dqsien dly found for B1: ( 0, 14, 4)
1903 23:55:54.129647 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1904 23:55:54.129699 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1905 23:55:54.129751
1906 23:55:54.129802 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1907 23:55:54.129854 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1908 23:55:54.129906 [Gating] SW calibration Done
1909 23:55:54.129958 ==
1910 23:55:54.130011 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 23:55:54.130064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 23:55:54.130116 ==
1913 23:55:54.130212 RX Vref Scan: 0
1914 23:55:54.130266
1915 23:55:54.130317 RX Vref 0 -> 0, step: 1
1916 23:55:54.130369
1917 23:55:54.130421 RX Delay -130 -> 252, step: 16
1918 23:55:54.299924 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1919 23:55:54.300420 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1920 23:55:54.300750 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1921 23:55:54.301057 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1922 23:55:54.301348 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1923 23:55:54.301637 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1924 23:55:54.301922 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1925 23:55:54.302251 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1926 23:55:54.302540 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1927 23:55:54.302814 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1928 23:55:54.303090 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1929 23:55:54.303400 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1930 23:55:54.303678 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1931 23:55:54.303951 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1932 23:55:54.304637 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1933 23:55:54.305182 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1934 23:55:54.305611 ==
1935 23:55:54.306099 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 23:55:54.306755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 23:55:54.307223 ==
1938 23:55:54.307651 DQS Delay:
1939 23:55:54.308087 DQS0 = 0, DQS1 = 0
1940 23:55:54.308512 DQM Delay:
1941 23:55:54.308932 DQM0 = 88, DQM1 = 79
1942 23:55:54.309350 DQ Delay:
1943 23:55:54.309671 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1944 23:55:54.309951 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1945 23:55:54.310262 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1946 23:55:54.310544 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1947 23:55:54.310844
1948 23:55:54.311119
1949 23:55:54.311388 ==
1950 23:55:54.311688 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 23:55:54.311962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 23:55:54.312236 ==
1953 23:55:54.312506
1954 23:55:54.312774
1955 23:55:54.313096 TX Vref Scan disable
1956 23:55:54.313379 == TX Byte 0 ==
1957 23:55:54.313648 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1958 23:55:54.313922 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1959 23:55:54.314227 == TX Byte 1 ==
1960 23:55:54.314506 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1961 23:55:54.314777 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1962 23:55:54.315046 ==
1963 23:55:54.315316 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 23:55:54.315617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 23:55:54.315892 ==
1966 23:55:54.316204 TX Vref=22, minBit 8, minWin=27, winSum=446
1967 23:55:54.316493 TX Vref=24, minBit 8, minWin=27, winSum=446
1968 23:55:54.316765 TX Vref=26, minBit 13, minWin=27, winSum=452
1969 23:55:54.317037 TX Vref=28, minBit 8, minWin=27, winSum=449
1970 23:55:54.317311 TX Vref=30, minBit 8, minWin=27, winSum=448
1971 23:55:54.317583 TX Vref=32, minBit 0, minWin=28, winSum=452
1972 23:55:54.317853 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1973 23:55:54.318123
1974 23:55:54.318430 Final TX Range 1 Vref 32
1975 23:55:54.318704
1976 23:55:54.318971 ==
1977 23:55:54.319377 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 23:55:54.319810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 23:55:54.320104 ==
1980 23:55:54.320381
1981 23:55:54.320653
1982 23:55:54.320922 TX Vref Scan disable
1983 23:55:54.321197 == TX Byte 0 ==
1984 23:55:54.321470 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1985 23:55:54.321743 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1986 23:55:54.322014 == TX Byte 1 ==
1987 23:55:54.322324 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1988 23:55:54.322600 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1989 23:55:54.322899
1990 23:55:54.323172 [DATLAT]
1991 23:55:54.323440 Freq=800, CH1 RK1
1992 23:55:54.323712
1993 23:55:54.323976 DATLAT Default: 0xa
1994 23:55:54.324248 0, 0xFFFF, sum = 0
1995 23:55:54.324444 1, 0xFFFF, sum = 0
1996 23:55:54.324649 2, 0xFFFF, sum = 0
1997 23:55:54.324843 3, 0xFFFF, sum = 0
1998 23:55:54.325036 4, 0xFFFF, sum = 0
1999 23:55:54.325230 5, 0xFFFF, sum = 0
2000 23:55:54.325425 6, 0xFFFF, sum = 0
2001 23:55:54.325617 7, 0xFFFF, sum = 0
2002 23:55:54.325828 8, 0x0, sum = 1
2003 23:55:54.326029 9, 0x0, sum = 2
2004 23:55:54.326248 10, 0x0, sum = 3
2005 23:55:54.326448 11, 0x0, sum = 4
2006 23:55:54.326644 best_step = 9
2007 23:55:54.326833
2008 23:55:54.327022 ==
2009 23:55:54.327211 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 23:55:54.327407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 23:55:54.327601 ==
2012 23:55:54.327794 RX Vref Scan: 0
2013 23:55:54.327985
2014 23:55:54.328173 RX Vref 0 -> 0, step: 1
2015 23:55:54.328364
2016 23:55:54.328572 RX Delay -95 -> 252, step: 8
2017 23:55:54.328766 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2018 23:55:54.328962 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2019 23:55:54.329175 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2020 23:55:54.329430 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2021 23:55:54.329656 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2022 23:55:54.329839 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2023 23:55:54.329988 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2024 23:55:54.330135 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2025 23:55:54.330311 iDelay=217, Bit 8, Center 72 (-39 ~ 184) 224
2026 23:55:54.330461 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2027 23:55:54.330610 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
2028 23:55:54.330756 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2029 23:55:54.330903 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2030 23:55:54.331049 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2031 23:55:54.331197 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2032 23:55:54.331344 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2033 23:55:54.331490 ==
2034 23:55:54.331635 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 23:55:54.331818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 23:55:54.331973 ==
2037 23:55:54.332119 DQS Delay:
2038 23:55:54.332264 DQS0 = 0, DQS1 = 0
2039 23:55:54.332409 DQM Delay:
2040 23:55:54.332555 DQM0 = 87, DQM1 = 79
2041 23:55:54.332720 DQ Delay:
2042 23:55:54.332867 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2043 23:55:54.333013 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2044 23:55:54.333161 DQ8 =72, DQ9 =72, DQ10 =76, DQ11 =72
2045 23:55:54.333307 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2046 23:55:54.333454
2047 23:55:54.333605
2048 23:55:54.333773 [DQSOSCAuto] RK1, (LSB)MR18= 0x1911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2049 23:55:54.334031 CH1 RK1: MR19=606, MR18=1911
2050 23:55:54.334273 CH1_RK1: MR19=0x606, MR18=0x1911, DQSOSC=403, MR23=63, INC=90, DEC=60
2051 23:55:54.334400 [RxdqsGatingPostProcess] freq 800
2052 23:55:54.334520 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2053 23:55:54.334640 Pre-setting of DQS Precalculation
2054 23:55:54.334759 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
2055 23:55:54.334878 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2056 23:55:54.334999 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2057 23:55:54.335119
2058 23:55:54.335237
2059 23:55:54.335359 [Calibration Summary] 1600 Mbps
2060 23:55:54.335478 CH 0, Rank 0
2061 23:55:54.335596 SW Impedance : PASS
2062 23:55:54.335713 DUTY Scan : NO K
2063 23:55:54.335845 ZQ Calibration : PASS
2064 23:55:54.335963 Jitter Meter : NO K
2065 23:55:54.336080 CBT Training : PASS
2066 23:55:54.336197 Write leveling : PASS
2067 23:55:54.336314 RX DQS gating : PASS
2068 23:55:54.336430 RX DQ/DQS(RDDQC) : PASS
2069 23:55:54.336547 TX DQ/DQS : PASS
2070 23:55:54.336664 RX DATLAT : PASS
2071 23:55:54.336781 RX DQ/DQS(Engine): PASS
2072 23:55:54.336896 TX OE : NO K
2073 23:55:54.337015 All Pass.
2074 23:55:54.337130
2075 23:55:54.337245 CH 0, Rank 1
2076 23:55:54.337362 SW Impedance : PASS
2077 23:55:54.337479 DUTY Scan : NO K
2078 23:55:54.337856 ZQ Calibration : PASS
2079 23:55:54.338078 Jitter Meter : NO K
2080 23:55:54.338345 CBT Training : PASS
2081 23:55:54.338596 Write leveling : PASS
2082 23:55:54.338834 RX DQS gating : PASS
2083 23:55:54.339020 RX DQ/DQS(RDDQC) : PASS
2084 23:55:54.339202 TX DQ/DQS : PASS
2085 23:55:54.339368 RX DATLAT : PASS
2086 23:55:54.339471 RX DQ/DQS(Engine): PASS
2087 23:55:54.339570 TX OE : NO K
2088 23:55:54.339669 All Pass.
2089 23:55:54.339768
2090 23:55:54.339865 CH 1, Rank 0
2091 23:55:54.339963 SW Impedance : PASS
2092 23:55:54.340060 DUTY Scan : NO K
2093 23:55:54.340157 ZQ Calibration : PASS
2094 23:55:54.340254 Jitter Meter : NO K
2095 23:55:54.340351 CBT Training : PASS
2096 23:55:54.340448 Write leveling : PASS
2097 23:55:54.340545 RX DQS gating : PASS
2098 23:55:54.340643 RX DQ/DQS(RDDQC) : PASS
2099 23:55:54.340740 TX DQ/DQS : PASS
2100 23:55:54.340839 RX DATLAT : PASS
2101 23:55:54.340936 RX DQ/DQS(Engine): PASS
2102 23:55:54.341033 TX OE : NO K
2103 23:55:54.341130 All Pass.
2104 23:55:54.341227
2105 23:55:54.341322 CH 1, Rank 1
2106 23:55:54.341419 SW Impedance : PASS
2107 23:55:54.341516 DUTY Scan : NO K
2108 23:55:54.341613 ZQ Calibration : PASS
2109 23:55:54.341710 Jitter Meter : NO K
2110 23:55:54.341807 CBT Training : PASS
2111 23:55:54.341904 Write leveling : PASS
2112 23:55:54.342001 RX DQS gating : PASS
2113 23:55:54.342099 RX DQ/DQS(RDDQC) : PASS
2114 23:55:54.342208 TX DQ/DQS : PASS
2115 23:55:54.342309 RX DATLAT : PASS
2116 23:55:54.342405 RX DQ/DQS(Engine): PASS
2117 23:55:54.342503 TX OE : NO K
2118 23:55:54.342600 All Pass.
2119 23:55:54.342696
2120 23:55:54.342801 DramC Write-DBI off
2121 23:55:54.342902 PER_BANK_REFRESH: Hybrid Mode
2122 23:55:54.343000 TX_TRACKING: ON
2123 23:55:54.343098 [GetDramInforAfterCalByMRR] Vendor 6.
2124 23:55:54.343196 [GetDramInforAfterCalByMRR] Revision 606.
2125 23:55:54.343293 [GetDramInforAfterCalByMRR] Revision 2 0.
2126 23:55:54.343391 MR0 0x3b3b
2127 23:55:54.343488 MR8 0x5151
2128 23:55:54.343586 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2129 23:55:54.343683
2130 23:55:54.343781 MR0 0x3b3b
2131 23:55:54.343878 MR8 0x5151
2132 23:55:54.343974 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2133 23:55:54.344073
2134 23:55:54.344170 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2135 23:55:54.344274 [FAST_K] Save calibration result to emmc
2136 23:55:54.344358 [FAST_K] Save calibration result to emmc
2137 23:55:54.344442 dram_init: config_dvfs: 1
2138 23:55:54.344524 dramc_set_vcore_voltage set vcore to 662500
2139 23:55:54.344609 Read voltage for 1200, 2
2140 23:55:54.344692 Vio18 = 0
2141 23:55:54.344775 Vcore = 662500
2142 23:55:54.344859 Vdram = 0
2143 23:55:54.344942 Vddq = 0
2144 23:55:54.345024 Vmddr = 0
2145 23:55:54.345107 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2146 23:55:54.345191 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2147 23:55:54.345274 MEM_TYPE=3, freq_sel=15
2148 23:55:54.345358 sv_algorithm_assistance_LP4_1600
2149 23:55:54.345441 ============ PULL DRAM RESETB DOWN ============
2150 23:55:54.345526 ========== PULL DRAM RESETB DOWN end =========
2151 23:55:54.345610 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2152 23:55:54.345696 ===================================
2153 23:55:54.345785 LPDDR4 DRAM CONFIGURATION
2154 23:55:54.345880 ===================================
2155 23:55:54.345965 EX_ROW_EN[0] = 0x0
2156 23:55:54.346049 EX_ROW_EN[1] = 0x0
2157 23:55:54.346131 LP4Y_EN = 0x0
2158 23:55:54.346223 WORK_FSP = 0x0
2159 23:55:54.346307 WL = 0x4
2160 23:55:54.346391 RL = 0x4
2161 23:55:54.346475 BL = 0x2
2162 23:55:54.346557 RPST = 0x0
2163 23:55:54.346641 RD_PRE = 0x0
2164 23:55:54.346724 WR_PRE = 0x1
2165 23:55:54.346807 WR_PST = 0x0
2166 23:55:54.346890 DBI_WR = 0x0
2167 23:55:54.346972 DBI_RD = 0x0
2168 23:55:54.347056 OTF = 0x1
2169 23:55:54.347139 ===================================
2170 23:55:54.347223 ===================================
2171 23:55:54.347308 ANA top config
2172 23:55:54.347391 ===================================
2173 23:55:54.347475 DLL_ASYNC_EN = 0
2174 23:55:54.347558 ALL_SLAVE_EN = 0
2175 23:55:54.347641 NEW_RANK_MODE = 1
2176 23:55:54.347727 DLL_IDLE_MODE = 1
2177 23:55:54.347826 LP45_APHY_COMB_EN = 1
2178 23:55:54.347911 TX_ODT_DIS = 1
2179 23:55:54.347995 NEW_8X_MODE = 1
2180 23:55:54.348081 ===================================
2181 23:55:54.348166 ===================================
2182 23:55:54.348250 data_rate = 2400
2183 23:55:54.348334 CKR = 1
2184 23:55:54.348418 DQ_P2S_RATIO = 8
2185 23:55:54.348502 ===================================
2186 23:55:54.348586 CA_P2S_RATIO = 8
2187 23:55:54.348670 DQ_CA_OPEN = 0
2188 23:55:54.348754 DQ_SEMI_OPEN = 0
2189 23:55:54.348838 CA_SEMI_OPEN = 0
2190 23:55:54.348923 CA_FULL_RATE = 0
2191 23:55:54.349008 DQ_CKDIV4_EN = 0
2192 23:55:54.349091 CA_CKDIV4_EN = 0
2193 23:55:54.349184 CA_PREDIV_EN = 0
2194 23:55:54.349276 PH8_DLY = 17
2195 23:55:54.349349 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2196 23:55:54.349422 DQ_AAMCK_DIV = 4
2197 23:55:54.349495 CA_AAMCK_DIV = 4
2198 23:55:54.349568 CA_ADMCK_DIV = 4
2199 23:55:54.349642 DQ_TRACK_CA_EN = 0
2200 23:55:54.349715 CA_PICK = 1200
2201 23:55:54.349789 CA_MCKIO = 1200
2202 23:55:54.349863 MCKIO_SEMI = 0
2203 23:55:54.349936 PLL_FREQ = 2366
2204 23:55:54.350010 DQ_UI_PI_RATIO = 32
2205 23:55:54.350083 CA_UI_PI_RATIO = 0
2206 23:55:54.350157 ===================================
2207 23:55:54.350237 ===================================
2208 23:55:54.350311 memory_type:LPDDR4
2209 23:55:54.350385 GP_NUM : 10
2210 23:55:54.350459 SRAM_EN : 1
2211 23:55:54.350533 MD32_EN : 0
2212 23:55:54.350606 ===================================
2213 23:55:54.350679 [ANA_INIT] >>>>>>>>>>>>>>
2214 23:55:54.350753 <<<<<< [CONFIGURE PHASE]: ANA_TX
2215 23:55:54.350827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2216 23:55:54.350901 ===================================
2217 23:55:54.350975 data_rate = 2400,PCW = 0X5b00
2218 23:55:54.351048 ===================================
2219 23:55:54.351122 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2220 23:55:54.351196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2221 23:55:54.351487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2222 23:55:54.351571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2223 23:55:54.351650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2224 23:55:54.351725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2225 23:55:54.351800 [ANA_INIT] flow start
2226 23:55:54.351875 [ANA_INIT] PLL >>>>>>>>
2227 23:55:54.351948 [ANA_INIT] PLL <<<<<<<<
2228 23:55:54.352021 [ANA_INIT] MIDPI >>>>>>>>
2229 23:55:54.352094 [ANA_INIT] MIDPI <<<<<<<<
2230 23:55:54.352177 [ANA_INIT] DLL >>>>>>>>
2231 23:55:54.352252 [ANA_INIT] DLL <<<<<<<<
2232 23:55:54.352326 [ANA_INIT] flow end
2233 23:55:54.352399 ============ LP4 DIFF to SE enter ============
2234 23:55:54.352474 ============ LP4 DIFF to SE exit ============
2235 23:55:54.352549 [ANA_INIT] <<<<<<<<<<<<<
2236 23:55:54.352624 [Flow] Enable top DCM control >>>>>
2237 23:55:54.352698 [Flow] Enable top DCM control <<<<<
2238 23:55:54.352770 Enable DLL master slave shuffle
2239 23:55:54.352844 ==============================================================
2240 23:55:54.352918 Gating Mode config
2241 23:55:54.352992 ==============================================================
2242 23:55:54.353065 Config description:
2243 23:55:54.353139 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2244 23:55:54.353214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2245 23:55:54.353288 SELPH_MODE 0: By rank 1: By Phase
2246 23:55:54.353362 ==============================================================
2247 23:55:54.353436 GAT_TRACK_EN = 1
2248 23:55:54.353510 RX_GATING_MODE = 2
2249 23:55:54.353583 RX_GATING_TRACK_MODE = 2
2250 23:55:54.353657 SELPH_MODE = 1
2251 23:55:54.353731 PICG_EARLY_EN = 1
2252 23:55:54.353804 VALID_LAT_VALUE = 1
2253 23:55:54.353879 ==============================================================
2254 23:55:54.353952 Enter into Gating configuration >>>>
2255 23:55:54.354026 Exit from Gating configuration <<<<
2256 23:55:54.354099 Enter into DVFS_PRE_config >>>>>
2257 23:55:54.354182 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2258 23:55:54.354269 Exit from DVFS_PRE_config <<<<<
2259 23:55:54.354334 Enter into PICG configuration >>>>
2260 23:55:54.354400 Exit from PICG configuration <<<<
2261 23:55:54.354466 [RX_INPUT] configuration >>>>>
2262 23:55:54.354532 [RX_INPUT] configuration <<<<<
2263 23:55:54.354598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2264 23:55:54.354665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2265 23:55:54.354730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2266 23:55:54.354796 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2267 23:55:54.354861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2268 23:55:54.354927 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2269 23:55:54.354992 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2270 23:55:54.355058 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2271 23:55:54.355124 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2272 23:55:54.355190 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2273 23:55:54.355255 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2274 23:55:54.355321 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2275 23:55:54.355387 ===================================
2276 23:55:54.355453 LPDDR4 DRAM CONFIGURATION
2277 23:55:54.355524 ===================================
2278 23:55:54.355592 EX_ROW_EN[0] = 0x0
2279 23:55:54.355657 EX_ROW_EN[1] = 0x0
2280 23:55:54.355723 LP4Y_EN = 0x0
2281 23:55:54.355790 WORK_FSP = 0x0
2282 23:55:54.355855 WL = 0x4
2283 23:55:54.355919 RL = 0x4
2284 23:55:54.355984 BL = 0x2
2285 23:55:54.356051 RPST = 0x0
2286 23:55:54.356116 RD_PRE = 0x0
2287 23:55:54.356181 WR_PRE = 0x1
2288 23:55:54.356245 WR_PST = 0x0
2289 23:55:54.356310 DBI_WR = 0x0
2290 23:55:54.356375 DBI_RD = 0x0
2291 23:55:54.356440 OTF = 0x1
2292 23:55:54.356505 ===================================
2293 23:55:54.356571 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2294 23:55:54.356636 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2295 23:55:54.356702 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2296 23:55:54.356772 ===================================
2297 23:55:54.356840 LPDDR4 DRAM CONFIGURATION
2298 23:55:54.356905 ===================================
2299 23:55:54.356980 EX_ROW_EN[0] = 0x10
2300 23:55:54.357045 EX_ROW_EN[1] = 0x0
2301 23:55:54.357109 LP4Y_EN = 0x0
2302 23:55:54.357173 WORK_FSP = 0x0
2303 23:55:54.357237 WL = 0x4
2304 23:55:54.357302 RL = 0x4
2305 23:55:54.357365 BL = 0x2
2306 23:55:54.357430 RPST = 0x0
2307 23:55:54.357494 RD_PRE = 0x0
2308 23:55:54.357558 WR_PRE = 0x1
2309 23:55:54.357622 WR_PST = 0x0
2310 23:55:54.357687 DBI_WR = 0x0
2311 23:55:54.357751 DBI_RD = 0x0
2312 23:55:54.357815 OTF = 0x1
2313 23:55:54.357880 ===================================
2314 23:55:54.357945 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2315 23:55:54.358010 ==
2316 23:55:54.358075 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 23:55:54.358139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2318 23:55:54.358218 ==
2319 23:55:54.358283 [Duty_Offset_Calibration]
2320 23:55:54.358350 B0:1 B1:-1 CA:0
2321 23:55:54.358415
2322 23:55:54.358479 [DutyScan_Calibration_Flow] k_type=0
2323 23:55:54.358544
2324 23:55:54.358609 ==CLK 0==
2325 23:55:54.358673 Final CLK duty delay cell = 0
2326 23:55:54.358738 [0] MAX Duty = 5094%(X100), DQS PI = 16
2327 23:55:54.358803 [0] MIN Duty = 4875%(X100), DQS PI = 8
2328 23:55:54.358868 [0] AVG Duty = 4984%(X100)
2329 23:55:54.358940
2330 23:55:54.359007 CH0 CLK Duty spec in!! Max-Min= 219%
2331 23:55:54.359072 [DutyScan_Calibration_Flow] ====Done====
2332 23:55:54.359137
2333 23:55:54.359212 [DutyScan_Calibration_Flow] k_type=1
2334 23:55:54.359270
2335 23:55:54.359328 ==DQS 0 ==
2336 23:55:54.359389 Final DQS duty delay cell = -4
2337 23:55:54.359448 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2338 23:55:54.359717 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2339 23:55:54.359825 [-4] AVG Duty = 4968%(X100)
2340 23:55:54.359944
2341 23:55:54.360062 ==DQS 1 ==
2342 23:55:54.360180 Final DQS duty delay cell = 0
2343 23:55:54.360299 [0] MAX Duty = 5124%(X100), DQS PI = 6
2344 23:55:54.360417 [0] MIN Duty = 5000%(X100), DQS PI = 20
2345 23:55:54.360535 [0] AVG Duty = 5062%(X100)
2346 23:55:54.360653
2347 23:55:54.360757 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2348 23:55:54.360858
2349 23:55:54.360922 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2350 23:55:54.360982 [DutyScan_Calibration_Flow] ====Done====
2351 23:55:54.361042
2352 23:55:54.361100 [DutyScan_Calibration_Flow] k_type=3
2353 23:55:54.361159
2354 23:55:54.361218 ==DQM 0 ==
2355 23:55:54.361276 Final DQM duty delay cell = 0
2356 23:55:54.361336 [0] MAX Duty = 5062%(X100), DQS PI = 20
2357 23:55:54.361395 [0] MIN Duty = 4875%(X100), DQS PI = 48
2358 23:55:54.361453 [0] AVG Duty = 4968%(X100)
2359 23:55:54.361511
2360 23:55:54.361569 ==DQM 1 ==
2361 23:55:54.361627 Final DQM duty delay cell = 4
2362 23:55:54.361686 [4] MAX Duty = 5156%(X100), DQS PI = 6
2363 23:55:54.361744 [4] MIN Duty = 5000%(X100), DQS PI = 24
2364 23:55:54.361802 [4] AVG Duty = 5078%(X100)
2365 23:55:54.361860
2366 23:55:54.361918 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2367 23:55:54.361976
2368 23:55:54.362034 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2369 23:55:54.362092 [DutyScan_Calibration_Flow] ====Done====
2370 23:55:54.362159
2371 23:55:54.362233 [DutyScan_Calibration_Flow] k_type=2
2372 23:55:54.362291
2373 23:55:54.362350 ==DQ 0 ==
2374 23:55:54.362408 Final DQ duty delay cell = -4
2375 23:55:54.362467 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2376 23:55:54.362525 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2377 23:55:54.362583 [-4] AVG Duty = 4969%(X100)
2378 23:55:54.362642
2379 23:55:54.362701 ==DQ 1 ==
2380 23:55:54.362759 Final DQ duty delay cell = -4
2381 23:55:54.362818 [-4] MAX Duty = 4969%(X100), DQS PI = 54
2382 23:55:54.362876 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2383 23:55:54.362935 [-4] AVG Duty = 4922%(X100)
2384 23:55:54.362993
2385 23:55:54.363050 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2386 23:55:54.363109
2387 23:55:54.363166 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2388 23:55:54.363225 [DutyScan_Calibration_Flow] ====Done====
2389 23:55:54.363282 ==
2390 23:55:54.363341 Dram Type= 6, Freq= 0, CH_1, rank 0
2391 23:55:54.363399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2392 23:55:54.363459 ==
2393 23:55:54.363517 [Duty_Offset_Calibration]
2394 23:55:54.363575 B0:-1 B1:1 CA:2
2395 23:55:54.363633
2396 23:55:54.363691 [DutyScan_Calibration_Flow] k_type=0
2397 23:55:54.363748
2398 23:55:54.363805 ==CLK 0==
2399 23:55:54.363863 Final CLK duty delay cell = 0
2400 23:55:54.363922 [0] MAX Duty = 5156%(X100), DQS PI = 22
2401 23:55:54.363981 [0] MIN Duty = 4969%(X100), DQS PI = 60
2402 23:55:54.364039 [0] AVG Duty = 5062%(X100)
2403 23:55:54.364097
2404 23:55:54.364155 CH1 CLK Duty spec in!! Max-Min= 187%
2405 23:55:54.364214 [DutyScan_Calibration_Flow] ====Done====
2406 23:55:54.364282
2407 23:55:54.364335 [DutyScan_Calibration_Flow] k_type=1
2408 23:55:54.364387
2409 23:55:54.364440 ==DQS 0 ==
2410 23:55:54.364493 Final DQS duty delay cell = 0
2411 23:55:54.364546 [0] MAX Duty = 5093%(X100), DQS PI = 16
2412 23:55:54.364598 [0] MIN Duty = 4875%(X100), DQS PI = 6
2413 23:55:54.364652 [0] AVG Duty = 4984%(X100)
2414 23:55:54.364705
2415 23:55:54.364757 ==DQS 1 ==
2416 23:55:54.364810 Final DQS duty delay cell = 0
2417 23:55:54.364863 [0] MAX Duty = 5062%(X100), DQS PI = 12
2418 23:55:54.364916 [0] MIN Duty = 4969%(X100), DQS PI = 56
2419 23:55:54.364969 [0] AVG Duty = 5015%(X100)
2420 23:55:54.365021
2421 23:55:54.365075 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2422 23:55:54.365129
2423 23:55:54.365181 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2424 23:55:54.365233 [DutyScan_Calibration_Flow] ====Done====
2425 23:55:54.365286
2426 23:55:54.365338 [DutyScan_Calibration_Flow] k_type=3
2427 23:55:54.365396
2428 23:55:54.365451 ==DQM 0 ==
2429 23:55:54.365503 Final DQM duty delay cell = -4
2430 23:55:54.365557 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2431 23:55:54.365610 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2432 23:55:54.365663 [-4] AVG Duty = 4937%(X100)
2433 23:55:54.365716
2434 23:55:54.365769 ==DQM 1 ==
2435 23:55:54.365822 Final DQM duty delay cell = 0
2436 23:55:54.365876 [0] MAX Duty = 5156%(X100), DQS PI = 6
2437 23:55:54.365932 [0] MIN Duty = 4969%(X100), DQS PI = 28
2438 23:55:54.365985 [0] AVG Duty = 5062%(X100)
2439 23:55:54.366038
2440 23:55:54.366091 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2441 23:55:54.366144
2442 23:55:54.366201 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2443 23:55:54.366254 [DutyScan_Calibration_Flow] ====Done====
2444 23:55:54.366307
2445 23:55:54.366359 [DutyScan_Calibration_Flow] k_type=2
2446 23:55:54.366412
2447 23:55:54.366464 ==DQ 0 ==
2448 23:55:54.366517 Final DQ duty delay cell = 0
2449 23:55:54.366571 [0] MAX Duty = 5187%(X100), DQS PI = 32
2450 23:55:54.366624 [0] MIN Duty = 4876%(X100), DQS PI = 8
2451 23:55:54.366677 [0] AVG Duty = 5031%(X100)
2452 23:55:54.366730
2453 23:55:54.366783 ==DQ 1 ==
2454 23:55:54.366836 Final DQ duty delay cell = 0
2455 23:55:54.366888 [0] MAX Duty = 5124%(X100), DQS PI = 10
2456 23:55:54.366942 [0] MIN Duty = 4969%(X100), DQS PI = 34
2457 23:55:54.366995 [0] AVG Duty = 5046%(X100)
2458 23:55:54.367048
2459 23:55:54.367100 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2460 23:55:54.367152
2461 23:55:54.367205 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2462 23:55:54.367258 [DutyScan_Calibration_Flow] ====Done====
2463 23:55:54.367311 nWR fixed to 30
2464 23:55:54.367366 [ModeRegInit_LP4] CH0 RK0
2465 23:55:54.367419 [ModeRegInit_LP4] CH0 RK1
2466 23:55:54.367472 [ModeRegInit_LP4] CH1 RK0
2467 23:55:54.367525 [ModeRegInit_LP4] CH1 RK1
2468 23:55:54.367578 match AC timing 7
2469 23:55:54.367631 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2470 23:55:54.367685 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2471 23:55:54.367739 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2472 23:55:54.367792 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2473 23:55:54.367845 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2474 23:55:54.367898 ==
2475 23:55:54.367951 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 23:55:54.368005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 23:55:54.368058 ==
2478 23:55:54.368111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 23:55:54.368165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 23:55:54.368219 [CA 0] Center 39 (9~70) winsize 62
2481 23:55:54.368273 [CA 1] Center 39 (9~69) winsize 61
2482 23:55:54.368326 [CA 2] Center 35 (5~66) winsize 62
2483 23:55:54.368379 [CA 3] Center 35 (5~66) winsize 62
2484 23:55:54.368432 [CA 4] Center 33 (4~63) winsize 60
2485 23:55:54.368485 [CA 5] Center 33 (3~63) winsize 61
2486 23:55:54.368537
2487 23:55:54.368590 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2488 23:55:54.368643
2489 23:55:54.368696 [CATrainingPosCal] consider 1 rank data
2490 23:55:54.368749 u2DelayCellTimex100 = 270/100 ps
2491 23:55:54.368999 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2492 23:55:54.369093 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2493 23:55:54.369216 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 23:55:54.369322 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2495 23:55:54.369427 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2496 23:55:54.369520 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2497 23:55:54.369609
2498 23:55:54.369663 CA PerBit enable=1, Macro0, CA PI delay=33
2499 23:55:54.369717
2500 23:55:54.369770 [CBTSetCACLKResult] CA Dly = 33
2501 23:55:54.369823 CS Dly: 8 (0~39)
2502 23:55:54.369875 ==
2503 23:55:54.369929 Dram Type= 6, Freq= 0, CH_0, rank 1
2504 23:55:54.369982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 23:55:54.370034 ==
2506 23:55:54.370087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 23:55:54.370139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 23:55:54.370238 [CA 0] Center 39 (9~70) winsize 62
2509 23:55:54.370291 [CA 1] Center 39 (9~70) winsize 62
2510 23:55:54.370343 [CA 2] Center 35 (5~66) winsize 62
2511 23:55:54.370394 [CA 3] Center 34 (4~65) winsize 62
2512 23:55:54.370446 [CA 4] Center 33 (3~64) winsize 62
2513 23:55:54.370497 [CA 5] Center 33 (3~63) winsize 61
2514 23:55:54.370549
2515 23:55:54.370600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 23:55:54.370652
2517 23:55:54.370704 [CATrainingPosCal] consider 2 rank data
2518 23:55:54.370756 u2DelayCellTimex100 = 270/100 ps
2519 23:55:54.370808 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2520 23:55:54.370860 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2521 23:55:54.370912 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 23:55:54.370964 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2523 23:55:54.371016 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2524 23:55:54.371068 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2525 23:55:54.371120
2526 23:55:54.371171 CA PerBit enable=1, Macro0, CA PI delay=33
2527 23:55:54.371224
2528 23:55:54.371274 [CBTSetCACLKResult] CA Dly = 33
2529 23:55:54.371326 CS Dly: 9 (0~41)
2530 23:55:54.371378
2531 23:55:54.371430 ----->DramcWriteLeveling(PI) begin...
2532 23:55:54.371483 ==
2533 23:55:54.371535 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 23:55:54.371587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 23:55:54.371640 ==
2536 23:55:54.371692 Write leveling (Byte 0): 33 => 33
2537 23:55:54.371744 Write leveling (Byte 1): 29 => 29
2538 23:55:54.371796 DramcWriteLeveling(PI) end<-----
2539 23:55:54.371848
2540 23:55:54.371905 ==
2541 23:55:54.371958 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 23:55:54.372010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 23:55:54.372064 ==
2544 23:55:54.372116 [Gating] SW mode calibration
2545 23:55:54.372169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2546 23:55:54.372222 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2547 23:55:54.372275 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2548 23:55:54.372327 0 15 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2549 23:55:54.372379 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 23:55:54.372432 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2551 23:55:54.372484 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2552 23:55:54.372536 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 23:55:54.372588 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2554 23:55:54.372640 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
2555 23:55:54.372692 1 0 0 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2556 23:55:54.372744 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2557 23:55:54.372796 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 23:55:54.372847 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2559 23:55:54.372899 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 23:55:54.372951 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 23:55:54.373003 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 23:55:54.373055 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2563 23:55:54.373107 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2564 23:55:54.373159 1 1 4 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
2565 23:55:54.373211 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 23:55:54.373263 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 23:55:54.373315 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 23:55:54.373368 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 23:55:54.373420 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 23:55:54.373472 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2571 23:55:54.373524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2572 23:55:54.373576 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:55:54.373628 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:55:54.373680 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:55:54.373731 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:55:54.373783 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 23:55:54.373835 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 23:55:54.373888 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 23:55:54.373942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 23:55:54.373995 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 23:55:54.374047 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 23:55:54.374099 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 23:55:54.374151 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 23:55:54.374248 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 23:55:54.374300 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2586 23:55:54.374351 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2587 23:55:54.374404 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2588 23:55:54.374455 Total UI for P1: 0, mck2ui 16
2589 23:55:54.374508 best dqsien dly found for B0: ( 1, 3, 26)
2590 23:55:54.374560 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 23:55:54.374613 Total UI for P1: 0, mck2ui 16
2592 23:55:54.374665 best dqsien dly found for B1: ( 1, 4, 0)
2593 23:55:54.374717 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2594 23:55:54.374964 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2595 23:55:54.375054
2596 23:55:54.375159 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2597 23:55:54.375256 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2598 23:55:54.375347 [Gating] SW calibration Done
2599 23:55:54.375409 ==
2600 23:55:54.375462 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 23:55:54.375516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 23:55:54.375569 ==
2603 23:55:54.375622 RX Vref Scan: 0
2604 23:55:54.375673
2605 23:55:54.375724 RX Vref 0 -> 0, step: 1
2606 23:55:54.375776
2607 23:55:54.375827 RX Delay -40 -> 252, step: 8
2608 23:55:54.375879 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2609 23:55:54.375931 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2610 23:55:54.375984 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2611 23:55:54.376036 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2612 23:55:54.376088 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2613 23:55:54.376140 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2614 23:55:54.376192 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2615 23:55:54.376244 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2616 23:55:54.376296 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2617 23:55:54.376348 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2618 23:55:54.376399 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2619 23:55:54.376451 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2620 23:55:54.376503 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2621 23:55:54.376556 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2622 23:55:54.376608 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2623 23:55:54.376660 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2624 23:55:54.376711 ==
2625 23:55:54.376762 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 23:55:54.376815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 23:55:54.376867 ==
2628 23:55:54.376919 DQS Delay:
2629 23:55:54.376970 DQS0 = 0, DQS1 = 0
2630 23:55:54.377022 DQM Delay:
2631 23:55:54.377074 DQM0 = 119, DQM1 = 107
2632 23:55:54.377126 DQ Delay:
2633 23:55:54.377177 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2634 23:55:54.377229 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2635 23:55:54.377281 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2636 23:55:54.377333 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2637 23:55:54.377384
2638 23:55:54.377435
2639 23:55:54.377487 ==
2640 23:55:54.377539 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 23:55:54.377591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 23:55:54.377643 ==
2643 23:55:54.377694
2644 23:55:54.377745
2645 23:55:54.377796 TX Vref Scan disable
2646 23:55:54.377848 == TX Byte 0 ==
2647 23:55:54.377899 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2648 23:55:54.377952 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2649 23:55:54.378009 == TX Byte 1 ==
2650 23:55:54.378093 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2651 23:55:54.378213 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2652 23:55:54.378269 ==
2653 23:55:54.378322 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 23:55:54.378375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 23:55:54.378428 ==
2656 23:55:54.378481 TX Vref=22, minBit 6, minWin=25, winSum=416
2657 23:55:54.378535 TX Vref=24, minBit 0, minWin=26, winSum=421
2658 23:55:54.378587 TX Vref=26, minBit 13, minWin=25, winSum=428
2659 23:55:54.378640 TX Vref=28, minBit 13, minWin=26, winSum=436
2660 23:55:54.378694 TX Vref=30, minBit 5, minWin=26, winSum=437
2661 23:55:54.378746 TX Vref=32, minBit 10, minWin=25, winSum=432
2662 23:55:54.378799 [TxChooseVref] Worse bit 5, Min win 26, Win sum 437, Final Vref 30
2663 23:55:54.378851
2664 23:55:54.378903 Final TX Range 1 Vref 30
2665 23:55:54.378955
2666 23:55:54.379007 ==
2667 23:55:54.379058 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 23:55:54.379111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 23:55:54.379163 ==
2670 23:55:54.379215
2671 23:55:54.379266
2672 23:55:54.379317 TX Vref Scan disable
2673 23:55:54.379369 == TX Byte 0 ==
2674 23:55:54.379421 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2675 23:55:54.379473 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2676 23:55:54.379524 == TX Byte 1 ==
2677 23:55:54.379575 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2678 23:55:54.379627 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2679 23:55:54.379679
2680 23:55:54.379730 [DATLAT]
2681 23:55:54.379782 Freq=1200, CH0 RK0
2682 23:55:54.379835
2683 23:55:54.379887 DATLAT Default: 0xd
2684 23:55:54.379938 0, 0xFFFF, sum = 0
2685 23:55:54.379992 1, 0xFFFF, sum = 0
2686 23:55:54.380045 2, 0xFFFF, sum = 0
2687 23:55:54.380098 3, 0xFFFF, sum = 0
2688 23:55:54.380151 4, 0xFFFF, sum = 0
2689 23:55:54.380203 5, 0xFFFF, sum = 0
2690 23:55:54.380257 6, 0xFFFF, sum = 0
2691 23:55:54.380310 7, 0xFFFF, sum = 0
2692 23:55:54.380363 8, 0xFFFF, sum = 0
2693 23:55:54.380416 9, 0xFFFF, sum = 0
2694 23:55:54.380468 10, 0xFFFF, sum = 0
2695 23:55:54.380521 11, 0xFFFF, sum = 0
2696 23:55:54.380575 12, 0x0, sum = 1
2697 23:55:54.380628 13, 0x0, sum = 2
2698 23:55:54.380680 14, 0x0, sum = 3
2699 23:55:54.380733 15, 0x0, sum = 4
2700 23:55:54.380786 best_step = 13
2701 23:55:54.380837
2702 23:55:54.380888 ==
2703 23:55:54.380940 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 23:55:54.380992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 23:55:54.381044 ==
2706 23:55:54.381096 RX Vref Scan: 1
2707 23:55:54.381148
2708 23:55:54.381200 Set Vref Range= 32 -> 127
2709 23:55:54.381252
2710 23:55:54.381303 RX Vref 32 -> 127, step: 1
2711 23:55:54.381355
2712 23:55:54.381407 RX Delay -21 -> 252, step: 4
2713 23:55:54.381458
2714 23:55:54.381510 Set Vref, RX VrefLevel [Byte0]: 32
2715 23:55:54.381562 [Byte1]: 32
2716 23:55:54.381614
2717 23:55:54.381666 Set Vref, RX VrefLevel [Byte0]: 33
2718 23:55:54.381717 [Byte1]: 33
2719 23:55:54.381769
2720 23:55:54.381821 Set Vref, RX VrefLevel [Byte0]: 34
2721 23:55:54.381873 [Byte1]: 34
2722 23:55:54.381924
2723 23:55:54.381975 Set Vref, RX VrefLevel [Byte0]: 35
2724 23:55:54.382052 [Byte1]: 35
2725 23:55:54.382139
2726 23:55:54.382246 Set Vref, RX VrefLevel [Byte0]: 36
2727 23:55:54.382300 [Byte1]: 36
2728 23:55:54.382353
2729 23:55:54.382405 Set Vref, RX VrefLevel [Byte0]: 37
2730 23:55:54.382458 [Byte1]: 37
2731 23:55:54.382510
2732 23:55:54.382561 Set Vref, RX VrefLevel [Byte0]: 38
2733 23:55:54.382613 [Byte1]: 38
2734 23:55:54.382665
2735 23:55:54.382717 Set Vref, RX VrefLevel [Byte0]: 39
2736 23:55:54.382769 [Byte1]: 39
2737 23:55:54.382821
2738 23:55:54.382872 Set Vref, RX VrefLevel [Byte0]: 40
2739 23:55:54.382924 [Byte1]: 40
2740 23:55:54.382977
2741 23:55:54.383029 Set Vref, RX VrefLevel [Byte0]: 41
2742 23:55:54.383081 [Byte1]: 41
2743 23:55:54.383132
2744 23:55:54.383184 Set Vref, RX VrefLevel [Byte0]: 42
2745 23:55:54.383235 [Byte1]: 42
2746 23:55:54.383287
2747 23:55:54.383338 Set Vref, RX VrefLevel [Byte0]: 43
2748 23:55:54.383390 [Byte1]: 43
2749 23:55:54.383441
2750 23:55:54.383685 Set Vref, RX VrefLevel [Byte0]: 44
2751 23:55:54.383746 [Byte1]: 44
2752 23:55:54.383800
2753 23:55:54.383853 Set Vref, RX VrefLevel [Byte0]: 45
2754 23:55:54.383905 [Byte1]: 45
2755 23:55:54.383957
2756 23:55:54.384008 Set Vref, RX VrefLevel [Byte0]: 46
2757 23:55:54.384060 [Byte1]: 46
2758 23:55:54.384112
2759 23:55:54.384163 Set Vref, RX VrefLevel [Byte0]: 47
2760 23:55:54.384216 [Byte1]: 47
2761 23:55:54.384268
2762 23:55:54.384319 Set Vref, RX VrefLevel [Byte0]: 48
2763 23:55:54.384371 [Byte1]: 48
2764 23:55:54.384422
2765 23:55:54.384473 Set Vref, RX VrefLevel [Byte0]: 49
2766 23:55:54.384526 [Byte1]: 49
2767 23:55:54.384577
2768 23:55:54.384628 Set Vref, RX VrefLevel [Byte0]: 50
2769 23:55:54.384680 [Byte1]: 50
2770 23:55:54.384732
2771 23:55:54.384783 Set Vref, RX VrefLevel [Byte0]: 51
2772 23:55:54.384834 [Byte1]: 51
2773 23:55:54.384886
2774 23:55:54.384937 Set Vref, RX VrefLevel [Byte0]: 52
2775 23:55:54.384989 [Byte1]: 52
2776 23:55:54.385040
2777 23:55:54.385091 Set Vref, RX VrefLevel [Byte0]: 53
2778 23:55:54.385143 [Byte1]: 53
2779 23:55:54.385195
2780 23:55:54.385246 Set Vref, RX VrefLevel [Byte0]: 54
2781 23:55:54.385298 [Byte1]: 54
2782 23:55:54.385350
2783 23:55:54.385401 Set Vref, RX VrefLevel [Byte0]: 55
2784 23:55:54.385453 [Byte1]: 55
2785 23:55:54.385505
2786 23:55:54.385556 Set Vref, RX VrefLevel [Byte0]: 56
2787 23:55:54.385608 [Byte1]: 56
2788 23:55:54.385659
2789 23:55:54.385711 Set Vref, RX VrefLevel [Byte0]: 57
2790 23:55:54.385762 [Byte1]: 57
2791 23:55:54.385814
2792 23:55:54.385866 Set Vref, RX VrefLevel [Byte0]: 58
2793 23:55:54.385917 [Byte1]: 58
2794 23:55:54.385969
2795 23:55:54.386020 Set Vref, RX VrefLevel [Byte0]: 59
2796 23:55:54.386072 [Byte1]: 59
2797 23:55:54.386123
2798 23:55:54.386182 Set Vref, RX VrefLevel [Byte0]: 60
2799 23:55:54.386236 [Byte1]: 60
2800 23:55:54.386288
2801 23:55:54.386340 Set Vref, RX VrefLevel [Byte0]: 61
2802 23:55:54.386392 [Byte1]: 61
2803 23:55:54.386444
2804 23:55:54.386496 Set Vref, RX VrefLevel [Byte0]: 62
2805 23:55:54.386548 [Byte1]: 62
2806 23:55:54.386600
2807 23:55:54.386651 Set Vref, RX VrefLevel [Byte0]: 63
2808 23:55:54.386703 [Byte1]: 63
2809 23:55:54.386755
2810 23:55:54.386807 Set Vref, RX VrefLevel [Byte0]: 64
2811 23:55:54.386860 [Byte1]: 64
2812 23:55:54.386911
2813 23:55:54.386963 Set Vref, RX VrefLevel [Byte0]: 65
2814 23:55:54.387015 [Byte1]: 65
2815 23:55:54.387067
2816 23:55:54.387119 Set Vref, RX VrefLevel [Byte0]: 66
2817 23:55:54.387171 [Byte1]: 66
2818 23:55:54.387223
2819 23:55:54.387274 Set Vref, RX VrefLevel [Byte0]: 67
2820 23:55:54.387325 [Byte1]: 67
2821 23:55:54.387377
2822 23:55:54.387429 Set Vref, RX VrefLevel [Byte0]: 68
2823 23:55:54.387481 [Byte1]: 68
2824 23:55:54.387533
2825 23:55:54.387585 Set Vref, RX VrefLevel [Byte0]: 69
2826 23:55:54.387636 [Byte1]: 69
2827 23:55:54.387688
2828 23:55:54.387739 Set Vref, RX VrefLevel [Byte0]: 70
2829 23:55:54.387790 [Byte1]: 70
2830 23:55:54.387842
2831 23:55:54.387893 Set Vref, RX VrefLevel [Byte0]: 71
2832 23:55:54.387945 [Byte1]: 71
2833 23:55:54.387997
2834 23:55:54.388047 Set Vref, RX VrefLevel [Byte0]: 72
2835 23:55:54.388099 [Byte1]: 72
2836 23:55:54.388151
2837 23:55:54.388202 Set Vref, RX VrefLevel [Byte0]: 73
2838 23:55:54.388254 [Byte1]: 73
2839 23:55:54.388305
2840 23:55:54.388356 Set Vref, RX VrefLevel [Byte0]: 74
2841 23:55:54.388408 [Byte1]: 74
2842 23:55:54.388461
2843 23:55:54.388512 Set Vref, RX VrefLevel [Byte0]: 75
2844 23:55:54.388563 [Byte1]: 75
2845 23:55:54.388616
2846 23:55:54.388667 Set Vref, RX VrefLevel [Byte0]: 76
2847 23:55:54.388719 [Byte1]: 76
2848 23:55:54.388770
2849 23:55:54.388822 Set Vref, RX VrefLevel [Byte0]: 77
2850 23:55:54.388874 [Byte1]: 77
2851 23:55:54.388926
2852 23:55:54.388977 Set Vref, RX VrefLevel [Byte0]: 78
2853 23:55:54.389029 [Byte1]: 78
2854 23:55:54.389081
2855 23:55:54.389132 Final RX Vref Byte 0 = 58 to rank0
2856 23:55:54.389185 Final RX Vref Byte 1 = 58 to rank0
2857 23:55:54.389236 Final RX Vref Byte 0 = 58 to rank1
2858 23:55:54.389289 Final RX Vref Byte 1 = 58 to rank1==
2859 23:55:54.389341 Dram Type= 6, Freq= 0, CH_0, rank 0
2860 23:55:54.389393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 23:55:54.389445 ==
2862 23:55:54.389498 DQS Delay:
2863 23:55:54.389550 DQS0 = 0, DQS1 = 0
2864 23:55:54.389602 DQM Delay:
2865 23:55:54.389653 DQM0 = 118, DQM1 = 107
2866 23:55:54.389706 DQ Delay:
2867 23:55:54.389758 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2868 23:55:54.389810 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =124
2869 23:55:54.389862 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =102
2870 23:55:54.389914 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2871 23:55:54.389966
2872 23:55:54.390017
2873 23:55:54.390069 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2874 23:55:54.390122 CH0 RK0: MR19=403, MR18=10FC
2875 23:55:54.390196 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2876 23:55:54.390252
2877 23:55:54.390304 ----->DramcWriteLeveling(PI) begin...
2878 23:55:54.390358 ==
2879 23:55:54.390410 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 23:55:54.390463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 23:55:54.390516 ==
2882 23:55:54.390568 Write leveling (Byte 0): 33 => 33
2883 23:55:54.390620 Write leveling (Byte 1): 30 => 30
2884 23:55:54.390671 DramcWriteLeveling(PI) end<-----
2885 23:55:54.390723
2886 23:55:54.390774 ==
2887 23:55:54.390826 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 23:55:54.390878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 23:55:54.390930 ==
2890 23:55:54.390982 [Gating] SW mode calibration
2891 23:55:54.391034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2892 23:55:54.391086 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2893 23:55:54.391139 0 15 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2894 23:55:54.391191 0 15 4 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
2895 23:55:54.391243 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 23:55:54.391295 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 23:55:54.391347 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 23:55:54.391588 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:55:54.391647 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2900 23:55:54.391701 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2901 23:55:54.391753 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2902 23:55:54.391806 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 23:55:54.391858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 23:55:54.391911 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 23:55:54.391976 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 23:55:54.392030 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:55:54.392082 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 23:55:54.392135 1 0 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2909 23:55:54.392188 1 1 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
2910 23:55:54.392240 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 23:55:54.392292 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 23:55:54.392344 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:55:54.392396 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:55:54.392448 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:55:54.392500 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2916 23:55:54.392552 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2917 23:55:54.392604 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2918 23:55:54.392657 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 23:55:54.392709 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 23:55:54.392761 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 23:55:54.392813 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:55:54.392865 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:55:54.392918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:55:54.392969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:55:54.393021 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:55:54.393073 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:55:54.393125 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:55:54.393176 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:55:54.393228 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:55:54.393279 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:55:54.393332 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:55:54.393384 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 23:55:54.393436 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2934 23:55:54.393488 Total UI for P1: 0, mck2ui 16
2935 23:55:54.393541 best dqsien dly found for B0: ( 1, 3, 28)
2936 23:55:54.393594 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 23:55:54.393646 Total UI for P1: 0, mck2ui 16
2938 23:55:54.575849 best dqsien dly found for B1: ( 1, 4, 0)
2939 23:55:54.576384 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2940 23:55:54.576750 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2941 23:55:54.577093
2942 23:55:54.577419 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2943 23:55:54.577743 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2944 23:55:54.578055 [Gating] SW calibration Done
2945 23:55:54.578494 ==
2946 23:55:54.578815 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 23:55:54.579122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 23:55:54.579431 ==
2949 23:55:54.579731 RX Vref Scan: 0
2950 23:55:54.580105
2951 23:55:54.580409 RX Vref 0 -> 0, step: 1
2952 23:55:54.580713
2953 23:55:54.581012 RX Delay -40 -> 252, step: 8
2954 23:55:54.581314 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2955 23:55:54.581614 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2956 23:55:54.581916 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2957 23:55:54.582264 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2958 23:55:54.582577 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2959 23:55:54.582877 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2960 23:55:54.583178 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 23:55:54.583474 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2962 23:55:54.583771 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2963 23:55:54.584068 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2964 23:55:54.584365 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2965 23:55:54.584662 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2966 23:55:54.584960 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2967 23:55:54.585254 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2968 23:55:54.585548 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2969 23:55:54.585844 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2970 23:55:54.586140 ==
2971 23:55:54.586479 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 23:55:54.586780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 23:55:54.587079 ==
2974 23:55:54.587376 DQS Delay:
2975 23:55:54.587671 DQS0 = 0, DQS1 = 0
2976 23:55:54.587963 DQM Delay:
2977 23:55:54.588258 DQM0 = 117, DQM1 = 108
2978 23:55:54.588552 DQ Delay:
2979 23:55:54.588846 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2980 23:55:54.589146 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2981 23:55:54.589444 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2982 23:55:54.589742 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2983 23:55:54.590037
2984 23:55:54.590394
2985 23:55:54.590694 ==
2986 23:55:54.590995 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 23:55:54.591291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 23:55:54.591592 ==
2989 23:55:54.591886
2990 23:55:54.592180
2991 23:55:54.592476 TX Vref Scan disable
2992 23:55:54.592770 == TX Byte 0 ==
2993 23:55:54.593086 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2994 23:55:54.593392 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2995 23:55:54.593692 == TX Byte 1 ==
2996 23:55:54.593987 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2997 23:55:54.594351 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2998 23:55:54.594656 ==
2999 23:55:54.594976 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 23:55:54.595313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 23:55:54.595590 ==
3002 23:55:54.595883 TX Vref=22, minBit 1, minWin=26, winSum=425
3003 23:55:54.596174 TX Vref=24, minBit 0, minWin=26, winSum=431
3004 23:55:54.596457 TX Vref=26, minBit 1, minWin=26, winSum=430
3005 23:55:54.597166 TX Vref=28, minBit 10, minWin=26, winSum=439
3006 23:55:54.597760 TX Vref=30, minBit 1, minWin=27, winSum=438
3007 23:55:54.598406 TX Vref=32, minBit 4, minWin=26, winSum=437
3008 23:55:54.599027 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 30
3009 23:55:54.599499
3010 23:55:54.599823 Final TX Range 1 Vref 30
3011 23:55:54.600134
3012 23:55:54.600434 ==
3013 23:55:54.600736 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 23:55:54.601039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 23:55:54.601339 ==
3016 23:55:54.601635
3017 23:55:54.601928
3018 23:55:54.602245 TX Vref Scan disable
3019 23:55:54.602545 == TX Byte 0 ==
3020 23:55:54.602844 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3021 23:55:54.603145 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3022 23:55:54.603440 == TX Byte 1 ==
3023 23:55:54.603736 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 23:55:54.604033 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 23:55:54.604309
3026 23:55:54.604530 [DATLAT]
3027 23:55:54.604751 Freq=1200, CH0 RK1
3028 23:55:54.604975
3029 23:55:54.605197 DATLAT Default: 0xd
3030 23:55:54.605420 0, 0xFFFF, sum = 0
3031 23:55:54.605651 1, 0xFFFF, sum = 0
3032 23:55:54.605890 2, 0xFFFF, sum = 0
3033 23:55:54.606120 3, 0xFFFF, sum = 0
3034 23:55:54.606366 4, 0xFFFF, sum = 0
3035 23:55:54.606560 5, 0xFFFF, sum = 0
3036 23:55:54.606715 6, 0xFFFF, sum = 0
3037 23:55:54.606864 7, 0xFFFF, sum = 0
3038 23:55:54.607013 8, 0xFFFF, sum = 0
3039 23:55:54.607162 9, 0xFFFF, sum = 0
3040 23:55:54.607312 10, 0xFFFF, sum = 0
3041 23:55:54.607479 11, 0xFFFF, sum = 0
3042 23:55:54.607633 12, 0x0, sum = 1
3043 23:55:54.607783 13, 0x0, sum = 2
3044 23:55:54.607931 14, 0x0, sum = 3
3045 23:55:54.608079 15, 0x0, sum = 4
3046 23:55:54.608228 best_step = 13
3047 23:55:54.608373
3048 23:55:54.608519 ==
3049 23:55:54.608665 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 23:55:54.608813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 23:55:54.608962 ==
3052 23:55:54.609108 RX Vref Scan: 0
3053 23:55:54.609260
3054 23:55:54.609376 RX Vref 0 -> 0, step: 1
3055 23:55:54.609493
3056 23:55:54.609661 RX Delay -21 -> 252, step: 4
3057 23:55:54.609853 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3058 23:55:54.609982 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3059 23:55:54.610101 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3060 23:55:54.610238 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3061 23:55:54.610360 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3062 23:55:54.610478 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3063 23:55:54.610596 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3064 23:55:54.610712 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3065 23:55:54.610829 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3066 23:55:54.610947 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3067 23:55:54.611064 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3068 23:55:54.611180 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3069 23:55:54.611296 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3070 23:55:54.611415 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3071 23:55:54.611534 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3072 23:55:54.611651 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3073 23:55:54.611769 ==
3074 23:55:54.611887 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 23:55:54.612006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 23:55:54.612125 ==
3077 23:55:54.612241 DQS Delay:
3078 23:55:54.612357 DQS0 = 0, DQS1 = 0
3079 23:55:54.612474 DQM Delay:
3080 23:55:54.612590 DQM0 = 116, DQM1 = 109
3081 23:55:54.612708 DQ Delay:
3082 23:55:54.612824 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3083 23:55:54.612944 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3084 23:55:54.613061 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =102
3085 23:55:54.613179 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118
3086 23:55:54.613307
3087 23:55:54.613492
3088 23:55:54.613616 [DQSOSCAuto] RK1, (LSB)MR18= 0xae4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3089 23:55:54.613738 CH0 RK1: MR19=403, MR18=AE4
3090 23:55:54.613859 CH0_RK1: MR19=0x403, MR18=0xAE4, DQSOSC=406, MR23=63, INC=39, DEC=26
3091 23:55:54.613979 [RxdqsGatingPostProcess] freq 1200
3092 23:55:54.614096 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 23:55:54.614248 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 23:55:54.614348 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 23:55:54.614447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 23:55:54.614546 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 23:55:54.614643 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 23:55:54.614741 best DQS1 dly(2T, 0.5T) = (0, 12)
3099 23:55:54.614839 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 23:55:54.614937 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3101 23:55:54.615035 Pre-setting of DQS Precalculation
3102 23:55:54.615133 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 23:55:54.615232 ==
3104 23:55:54.615330 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 23:55:54.615428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 23:55:54.615528 ==
3107 23:55:54.615625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 23:55:54.615725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 23:55:54.615823 [CA 0] Center 37 (7~67) winsize 61
3110 23:55:54.615922 [CA 1] Center 37 (7~68) winsize 62
3111 23:55:54.616021 [CA 2] Center 34 (4~64) winsize 61
3112 23:55:54.616119 [CA 3] Center 33 (3~64) winsize 62
3113 23:55:54.616234 [CA 4] Center 34 (4~64) winsize 61
3114 23:55:54.616377 [CA 5] Center 33 (3~64) winsize 62
3115 23:55:54.616480
3116 23:55:54.616578 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3117 23:55:54.616678
3118 23:55:54.616776 [CATrainingPosCal] consider 1 rank data
3119 23:55:54.616875 u2DelayCellTimex100 = 270/100 ps
3120 23:55:54.616974 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3121 23:55:54.617073 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 23:55:54.617171 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 23:55:54.617270 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 23:55:54.617367 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 23:55:54.617464 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3126 23:55:54.617562
3127 23:55:54.617659 CA PerBit enable=1, Macro0, CA PI delay=33
3128 23:55:54.617758
3129 23:55:54.617854 [CBTSetCACLKResult] CA Dly = 33
3130 23:55:54.617952 CS Dly: 5 (0~36)
3131 23:55:54.618051 ==
3132 23:55:54.618149 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 23:55:54.618264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 23:55:54.618363 ==
3135 23:55:54.618461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 23:55:54.618560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3137 23:55:54.618659 [CA 0] Center 37 (7~68) winsize 62
3138 23:55:54.618757 [CA 1] Center 38 (8~68) winsize 61
3139 23:55:54.619114 [CA 2] Center 34 (4~65) winsize 62
3140 23:55:54.619234 [CA 3] Center 33 (3~64) winsize 62
3141 23:55:54.619338 [CA 4] Center 34 (3~65) winsize 63
3142 23:55:54.619424 [CA 5] Center 33 (3~64) winsize 62
3143 23:55:54.619510
3144 23:55:54.619594 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3145 23:55:54.619680
3146 23:55:54.619783 [CATrainingPosCal] consider 2 rank data
3147 23:55:54.619870 u2DelayCellTimex100 = 270/100 ps
3148 23:55:54.619955 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3149 23:55:54.620041 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3150 23:55:54.620126 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 23:55:54.620211 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3152 23:55:54.620296 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 23:55:54.620380 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3154 23:55:54.620465
3155 23:55:54.620549 CA PerBit enable=1, Macro0, CA PI delay=33
3156 23:55:54.620634
3157 23:55:54.620717 [CBTSetCACLKResult] CA Dly = 33
3158 23:55:54.620802 CS Dly: 7 (0~40)
3159 23:55:54.620886
3160 23:55:54.620970 ----->DramcWriteLeveling(PI) begin...
3161 23:55:54.621055 ==
3162 23:55:54.621139 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 23:55:54.621223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 23:55:54.621308 ==
3165 23:55:54.621392 Write leveling (Byte 0): 26 => 26
3166 23:55:54.621476 Write leveling (Byte 1): 28 => 28
3167 23:55:54.621561 DramcWriteLeveling(PI) end<-----
3168 23:55:54.621645
3169 23:55:54.621746 ==
3170 23:55:54.621838 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 23:55:54.621924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 23:55:54.622010 ==
3173 23:55:54.622095 [Gating] SW mode calibration
3174 23:55:54.622190 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 23:55:54.622279 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 23:55:54.622365 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3177 23:55:54.622450 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 23:55:54.622534 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 23:55:54.622618 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:55:54.622703 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:55:54.622787 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:55:54.622871 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
3183 23:55:54.622955 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3184 23:55:54.623040 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 23:55:54.623124 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 23:55:54.623208 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 23:55:54.623291 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:55:54.623376 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:55:54.623460 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:55:54.623544 1 0 24 | B1->B0 | 2424 3534 | 0 1 | (0 0) (1 1)
3191 23:55:54.623629 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3192 23:55:54.623713 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 23:55:54.623831 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 23:55:54.623969 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:55:54.624059 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:55:54.624144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:55:54.624240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:55:54.624315 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3199 23:55:54.624389 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 23:55:54.624464 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 23:55:54.624597 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 23:55:54.624680 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:55:54.624756 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:55:54.624830 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:55:54.624904 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:55:54.624978 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:55:54.625052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:55:54.625125 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:55:54.625203 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:55:54.625278 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:55:54.625352 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:55:54.625425 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:55:54.625499 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:55:54.625572 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3215 23:55:54.625646 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 23:55:54.625719 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 23:55:54.625793 Total UI for P1: 0, mck2ui 16
3218 23:55:54.625868 best dqsien dly found for B0: ( 1, 3, 26)
3219 23:55:54.625943 Total UI for P1: 0, mck2ui 16
3220 23:55:54.626017 best dqsien dly found for B1: ( 1, 3, 28)
3221 23:55:54.626092 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3222 23:55:54.626170 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3223 23:55:54.626246
3224 23:55:54.626319 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3225 23:55:54.626393 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3226 23:55:54.626467 [Gating] SW calibration Done
3227 23:55:54.626541 ==
3228 23:55:54.626615 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 23:55:54.626688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 23:55:54.626763 ==
3231 23:55:54.626836 RX Vref Scan: 0
3232 23:55:54.626910
3233 23:55:54.626983 RX Vref 0 -> 0, step: 1
3234 23:55:54.627056
3235 23:55:54.627129 RX Delay -40 -> 252, step: 8
3236 23:55:54.627202 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3237 23:55:54.627276 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3238 23:55:54.627350 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3239 23:55:54.627423 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3240 23:55:54.627497 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3241 23:55:54.627571 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3242 23:55:54.627644 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3243 23:55:54.627718 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3244 23:55:54.627998 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3245 23:55:54.628081 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3246 23:55:54.628156 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3247 23:55:54.628230 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3248 23:55:54.628303 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3249 23:55:54.628376 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3250 23:55:54.628450 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3251 23:55:54.628525 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3252 23:55:54.628598 ==
3253 23:55:54.628672 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 23:55:54.628745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 23:55:54.628820 ==
3256 23:55:54.628893 DQS Delay:
3257 23:55:54.628967 DQS0 = 0, DQS1 = 0
3258 23:55:54.629040 DQM Delay:
3259 23:55:54.629113 DQM0 = 118, DQM1 = 110
3260 23:55:54.629200 DQ Delay:
3261 23:55:54.629266 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3262 23:55:54.629332 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3263 23:55:54.629398 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3264 23:55:54.629463 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3265 23:55:54.629529
3266 23:55:54.629594
3267 23:55:54.629658 ==
3268 23:55:54.629724 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 23:55:54.629790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 23:55:54.629856 ==
3271 23:55:54.629921
3272 23:55:54.629986
3273 23:55:54.630050 TX Vref Scan disable
3274 23:55:54.630115 == TX Byte 0 ==
3275 23:55:54.630187 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 23:55:54.630254 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 23:55:54.630320 == TX Byte 1 ==
3278 23:55:54.630385 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 23:55:54.630451 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 23:55:54.630516 ==
3281 23:55:54.630582 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 23:55:54.630647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 23:55:54.630713 ==
3284 23:55:54.630778 TX Vref=22, minBit 8, minWin=25, winSum=415
3285 23:55:54.630845 TX Vref=24, minBit 9, minWin=25, winSum=421
3286 23:55:54.630911 TX Vref=26, minBit 8, minWin=25, winSum=426
3287 23:55:54.630977 TX Vref=28, minBit 9, minWin=26, winSum=429
3288 23:55:54.631043 TX Vref=30, minBit 9, minWin=26, winSum=430
3289 23:55:54.631108 TX Vref=32, minBit 11, minWin=25, winSum=426
3290 23:55:54.631174 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
3291 23:55:54.631240
3292 23:55:54.631304 Final TX Range 1 Vref 30
3293 23:55:54.631370
3294 23:55:54.631434 ==
3295 23:55:54.631499 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 23:55:54.631564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 23:55:54.631628 ==
3298 23:55:54.631692
3299 23:55:54.631756
3300 23:55:54.631820 TX Vref Scan disable
3301 23:55:54.631885 == TX Byte 0 ==
3302 23:55:54.631949 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 23:55:54.632014 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 23:55:54.632079 == TX Byte 1 ==
3305 23:55:54.632143 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 23:55:54.632207 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 23:55:54.632271
3308 23:55:54.632335 [DATLAT]
3309 23:55:54.632399 Freq=1200, CH1 RK0
3310 23:55:54.632463
3311 23:55:54.632527 DATLAT Default: 0xd
3312 23:55:54.632592 0, 0xFFFF, sum = 0
3313 23:55:54.632658 1, 0xFFFF, sum = 0
3314 23:55:54.632724 2, 0xFFFF, sum = 0
3315 23:55:54.632790 3, 0xFFFF, sum = 0
3316 23:55:54.632856 4, 0xFFFF, sum = 0
3317 23:55:54.632921 5, 0xFFFF, sum = 0
3318 23:55:54.632986 6, 0xFFFF, sum = 0
3319 23:55:54.633051 7, 0xFFFF, sum = 0
3320 23:55:54.633117 8, 0xFFFF, sum = 0
3321 23:55:54.633183 9, 0xFFFF, sum = 0
3322 23:55:54.633248 10, 0xFFFF, sum = 0
3323 23:55:54.633315 11, 0xFFFF, sum = 0
3324 23:55:54.633381 12, 0x0, sum = 1
3325 23:55:54.633446 13, 0x0, sum = 2
3326 23:55:54.633512 14, 0x0, sum = 3
3327 23:55:54.633578 15, 0x0, sum = 4
3328 23:55:54.633643 best_step = 13
3329 23:55:54.633707
3330 23:55:54.633770 ==
3331 23:55:54.633835 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 23:55:54.633900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 23:55:54.633965 ==
3334 23:55:54.634029 RX Vref Scan: 1
3335 23:55:54.634094
3336 23:55:54.634158 Set Vref Range= 32 -> 127
3337 23:55:54.634243
3338 23:55:54.634301 RX Vref 32 -> 127, step: 1
3339 23:55:54.634360
3340 23:55:54.634418 RX Delay -21 -> 252, step: 4
3341 23:55:54.634477
3342 23:55:54.634535 Set Vref, RX VrefLevel [Byte0]: 32
3343 23:55:54.634593 [Byte1]: 32
3344 23:55:54.634651
3345 23:55:54.634709 Set Vref, RX VrefLevel [Byte0]: 33
3346 23:55:54.634767 [Byte1]: 33
3347 23:55:54.634826
3348 23:55:54.634884 Set Vref, RX VrefLevel [Byte0]: 34
3349 23:55:54.634942 [Byte1]: 34
3350 23:55:54.635000
3351 23:55:54.635059 Set Vref, RX VrefLevel [Byte0]: 35
3352 23:55:54.635116 [Byte1]: 35
3353 23:55:54.635175
3354 23:55:54.635233 Set Vref, RX VrefLevel [Byte0]: 36
3355 23:55:54.635291 [Byte1]: 36
3356 23:55:54.635348
3357 23:55:54.635406 Set Vref, RX VrefLevel [Byte0]: 37
3358 23:55:54.635463 [Byte1]: 37
3359 23:55:54.635521
3360 23:55:54.635579 Set Vref, RX VrefLevel [Byte0]: 38
3361 23:55:54.635638 [Byte1]: 38
3362 23:55:54.635695
3363 23:55:54.635752 Set Vref, RX VrefLevel [Byte0]: 39
3364 23:55:54.635810 [Byte1]: 39
3365 23:55:54.635868
3366 23:55:54.635925 Set Vref, RX VrefLevel [Byte0]: 40
3367 23:55:54.635983 [Byte1]: 40
3368 23:55:54.636041
3369 23:55:54.636099 Set Vref, RX VrefLevel [Byte0]: 41
3370 23:55:54.636157 [Byte1]: 41
3371 23:55:54.636215
3372 23:55:54.636273 Set Vref, RX VrefLevel [Byte0]: 42
3373 23:55:54.636331 [Byte1]: 42
3374 23:55:54.636388
3375 23:55:54.636446 Set Vref, RX VrefLevel [Byte0]: 43
3376 23:55:54.636505 [Byte1]: 43
3377 23:55:54.636563
3378 23:55:54.636622 Set Vref, RX VrefLevel [Byte0]: 44
3379 23:55:54.636680 [Byte1]: 44
3380 23:55:54.636738
3381 23:55:54.636796 Set Vref, RX VrefLevel [Byte0]: 45
3382 23:55:54.636856 [Byte1]: 45
3383 23:55:54.636914
3384 23:55:54.636972 Set Vref, RX VrefLevel [Byte0]: 46
3385 23:55:54.637031 [Byte1]: 46
3386 23:55:54.637127
3387 23:55:54.637190 Set Vref, RX VrefLevel [Byte0]: 47
3388 23:55:54.637249 [Byte1]: 47
3389 23:55:54.637308
3390 23:55:54.637366 Set Vref, RX VrefLevel [Byte0]: 48
3391 23:55:54.637425 [Byte1]: 48
3392 23:55:54.637484
3393 23:55:54.637542 Set Vref, RX VrefLevel [Byte0]: 49
3394 23:55:54.637601 [Byte1]: 49
3395 23:55:54.637659
3396 23:55:54.637717 Set Vref, RX VrefLevel [Byte0]: 50
3397 23:55:54.637776 [Byte1]: 50
3398 23:55:54.637835
3399 23:55:54.637892 Set Vref, RX VrefLevel [Byte0]: 51
3400 23:55:54.637951 [Byte1]: 51
3401 23:55:54.638010
3402 23:55:54.638068 Set Vref, RX VrefLevel [Byte0]: 52
3403 23:55:54.638126 [Byte1]: 52
3404 23:55:54.638218
3405 23:55:54.638282 Set Vref, RX VrefLevel [Byte0]: 53
3406 23:55:54.638542 [Byte1]: 53
3407 23:55:54.638611
3408 23:55:54.638671 Set Vref, RX VrefLevel [Byte0]: 54
3409 23:55:54.638730 [Byte1]: 54
3410 23:55:54.638790
3411 23:55:54.638848 Set Vref, RX VrefLevel [Byte0]: 55
3412 23:55:54.638907 [Byte1]: 55
3413 23:55:54.638966
3414 23:55:54.639024 Set Vref, RX VrefLevel [Byte0]: 56
3415 23:55:54.639083 [Byte1]: 56
3416 23:55:54.639142
3417 23:55:54.639213 Set Vref, RX VrefLevel [Byte0]: 57
3418 23:55:54.639266 [Byte1]: 57
3419 23:55:54.639318
3420 23:55:54.639370 Set Vref, RX VrefLevel [Byte0]: 58
3421 23:55:54.639424 [Byte1]: 58
3422 23:55:54.639478
3423 23:55:54.639531 Set Vref, RX VrefLevel [Byte0]: 59
3424 23:55:54.639586 [Byte1]: 59
3425 23:55:54.639639
3426 23:55:54.639691 Set Vref, RX VrefLevel [Byte0]: 60
3427 23:55:54.639744 [Byte1]: 60
3428 23:55:54.639797
3429 23:55:54.639849 Set Vref, RX VrefLevel [Byte0]: 61
3430 23:55:54.639903 [Byte1]: 61
3431 23:55:54.639955
3432 23:55:54.640008 Set Vref, RX VrefLevel [Byte0]: 62
3433 23:55:54.640061 [Byte1]: 62
3434 23:55:54.640114
3435 23:55:54.640167 Set Vref, RX VrefLevel [Byte0]: 63
3436 23:55:54.640220 [Byte1]: 63
3437 23:55:54.640272
3438 23:55:54.640325 Set Vref, RX VrefLevel [Byte0]: 64
3439 23:55:54.640377 [Byte1]: 64
3440 23:55:54.640431
3441 23:55:54.640483 Set Vref, RX VrefLevel [Byte0]: 65
3442 23:55:54.640536 [Byte1]: 65
3443 23:55:54.640589
3444 23:55:54.640642 Set Vref, RX VrefLevel [Byte0]: 66
3445 23:55:54.640694 [Byte1]: 66
3446 23:55:54.640748
3447 23:55:54.640800 Set Vref, RX VrefLevel [Byte0]: 67
3448 23:55:54.640853 [Byte1]: 67
3449 23:55:54.640906
3450 23:55:54.640959 Set Vref, RX VrefLevel [Byte0]: 68
3451 23:55:54.641012 [Byte1]: 68
3452 23:55:54.641065
3453 23:55:54.641118 Final RX Vref Byte 0 = 52 to rank0
3454 23:55:54.641171 Final RX Vref Byte 1 = 52 to rank0
3455 23:55:54.641225 Final RX Vref Byte 0 = 52 to rank1
3456 23:55:54.641277 Final RX Vref Byte 1 = 52 to rank1==
3457 23:55:54.641330 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 23:55:54.641383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 23:55:54.641437 ==
3460 23:55:54.641491 DQS Delay:
3461 23:55:54.641544 DQS0 = 0, DQS1 = 0
3462 23:55:54.641597 DQM Delay:
3463 23:55:54.641650 DQM0 = 116, DQM1 = 109
3464 23:55:54.641702 DQ Delay:
3465 23:55:54.641755 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3466 23:55:54.641809 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =112
3467 23:55:54.641863 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3468 23:55:54.641916 DQ12 =116, DQ13 =114, DQ14 =118, DQ15 =116
3469 23:55:54.641970
3470 23:55:54.642023
3471 23:55:54.642075 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3472 23:55:54.642130 CH1 RK0: MR19=403, MR18=F3
3473 23:55:54.642186 CH1_RK0: MR19=0x403, MR18=0xF3, DQSOSC=410, MR23=63, INC=39, DEC=26
3474 23:55:54.642241
3475 23:55:54.642293 ----->DramcWriteLeveling(PI) begin...
3476 23:55:54.642348 ==
3477 23:55:54.642401 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 23:55:54.642454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 23:55:54.642507 ==
3480 23:55:54.642561 Write leveling (Byte 0): 24 => 24
3481 23:55:54.642615 Write leveling (Byte 1): 28 => 28
3482 23:55:54.642668 DramcWriteLeveling(PI) end<-----
3483 23:55:54.642722
3484 23:55:54.642774 ==
3485 23:55:54.642827 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 23:55:54.642881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 23:55:54.642934 ==
3488 23:55:54.642987 [Gating] SW mode calibration
3489 23:55:54.643041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3490 23:55:54.643095 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3491 23:55:54.643148 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 23:55:54.643202 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 23:55:54.643256 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 23:55:54.643309 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 23:55:54.643362 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 23:55:54.643415 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 23:55:54.643468 0 15 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
3498 23:55:54.643521 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
3499 23:55:54.643573 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 23:55:54.643627 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 23:55:54.643680 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 23:55:54.643733 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 23:55:54.643787 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 23:55:54.643840 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 23:55:54.643893 1 0 24 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 0)
3506 23:55:54.643946 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3507 23:55:54.643998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 23:55:54.644051 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 23:55:54.644104 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 23:55:54.644157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 23:55:54.644223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 23:55:54.644275 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 23:55:54.644327 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:55:54.644379 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3515 23:55:54.644430 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 23:55:54.644482 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:55:54.644534 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:55:54.644586 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:55:54.644638 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:55:54.644689 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:55:54.644742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:55:54.644793 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:55:54.644845 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:55:54.644896 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:55:54.645138 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:55:54.645196 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:55:54.645249 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:55:54.645302 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:55:54.645354 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3530 23:55:54.645405 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3531 23:55:54.645457 Total UI for P1: 0, mck2ui 16
3532 23:55:54.645510 best dqsien dly found for B1: ( 1, 3, 24)
3533 23:55:54.645562 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 23:55:54.645614 Total UI for P1: 0, mck2ui 16
3535 23:55:54.645667 best dqsien dly found for B0: ( 1, 3, 28)
3536 23:55:54.645719 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3537 23:55:54.645772 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3538 23:55:54.645824
3539 23:55:54.645875 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3540 23:55:54.645928 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3541 23:55:54.645980 [Gating] SW calibration Done
3542 23:55:54.646032 ==
3543 23:55:54.646083 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 23:55:54.646135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 23:55:54.646222 ==
3546 23:55:54.646288 RX Vref Scan: 0
3547 23:55:54.646339
3548 23:55:54.646390 RX Vref 0 -> 0, step: 1
3549 23:55:54.646442
3550 23:55:54.646494 RX Delay -40 -> 252, step: 8
3551 23:55:54.646547 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3552 23:55:54.646599 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3553 23:55:54.646650 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3554 23:55:54.646703 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3555 23:55:54.646755 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3556 23:55:54.646806 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3557 23:55:54.646857 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3558 23:55:54.646909 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3559 23:55:54.646961 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3560 23:55:54.647013 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3561 23:55:54.647065 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3562 23:55:54.647118 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3563 23:55:54.647170 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3564 23:55:54.647221 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3565 23:55:54.647273 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3566 23:55:54.647326 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3567 23:55:54.647378 ==
3568 23:55:54.647429 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 23:55:54.647481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 23:55:54.647534 ==
3571 23:55:54.647586 DQS Delay:
3572 23:55:54.647638 DQS0 = 0, DQS1 = 0
3573 23:55:54.647689 DQM Delay:
3574 23:55:54.647741 DQM0 = 117, DQM1 = 109
3575 23:55:54.647793 DQ Delay:
3576 23:55:54.647845 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3577 23:55:54.647899 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3578 23:55:54.647951 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3579 23:55:54.648003 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3580 23:55:54.648055
3581 23:55:54.648107
3582 23:55:54.648158 ==
3583 23:55:54.648210 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 23:55:54.648262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 23:55:54.648314 ==
3586 23:55:54.648366
3587 23:55:54.648417
3588 23:55:54.648468 TX Vref Scan disable
3589 23:55:54.648520 == TX Byte 0 ==
3590 23:55:54.648572 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3591 23:55:54.648625 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3592 23:55:54.648676 == TX Byte 1 ==
3593 23:55:54.648728 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3594 23:55:54.648780 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3595 23:55:54.648836 ==
3596 23:55:54.648888 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 23:55:54.648940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 23:55:54.648992 ==
3599 23:55:54.649045 TX Vref=22, minBit 8, minWin=25, winSum=425
3600 23:55:54.649097 TX Vref=24, minBit 8, minWin=26, winSum=430
3601 23:55:54.649150 TX Vref=26, minBit 9, minWin=26, winSum=433
3602 23:55:54.649203 TX Vref=28, minBit 8, minWin=26, winSum=436
3603 23:55:54.649255 TX Vref=30, minBit 8, minWin=26, winSum=435
3604 23:55:54.649307 TX Vref=32, minBit 8, minWin=26, winSum=432
3605 23:55:54.649359 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
3606 23:55:54.649411
3607 23:55:54.649462 Final TX Range 1 Vref 28
3608 23:55:54.649514
3609 23:55:54.649565 ==
3610 23:55:54.649617 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 23:55:54.649670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 23:55:54.649722 ==
3613 23:55:54.649773
3614 23:55:54.649825
3615 23:55:54.649876 TX Vref Scan disable
3616 23:55:54.649928 == TX Byte 0 ==
3617 23:55:54.649980 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3618 23:55:54.650032 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3619 23:55:54.650085 == TX Byte 1 ==
3620 23:55:54.650137 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3621 23:55:54.650230 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3622 23:55:54.650282
3623 23:55:54.650334 [DATLAT]
3624 23:55:54.650385 Freq=1200, CH1 RK1
3625 23:55:54.650437
3626 23:55:54.650488 DATLAT Default: 0xd
3627 23:55:54.650540 0, 0xFFFF, sum = 0
3628 23:55:54.650593 1, 0xFFFF, sum = 0
3629 23:55:54.650646 2, 0xFFFF, sum = 0
3630 23:55:54.650699 3, 0xFFFF, sum = 0
3631 23:55:54.650752 4, 0xFFFF, sum = 0
3632 23:55:54.650805 5, 0xFFFF, sum = 0
3633 23:55:54.650857 6, 0xFFFF, sum = 0
3634 23:55:54.650910 7, 0xFFFF, sum = 0
3635 23:55:54.650962 8, 0xFFFF, sum = 0
3636 23:55:54.651014 9, 0xFFFF, sum = 0
3637 23:55:54.651067 10, 0xFFFF, sum = 0
3638 23:55:54.651119 11, 0xFFFF, sum = 0
3639 23:55:54.651172 12, 0x0, sum = 1
3640 23:55:54.651225 13, 0x0, sum = 2
3641 23:55:54.651278 14, 0x0, sum = 3
3642 23:55:54.651330 15, 0x0, sum = 4
3643 23:55:54.651383 best_step = 13
3644 23:55:54.651434
3645 23:55:54.651485 ==
3646 23:55:54.651536 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 23:55:54.651589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 23:55:54.651641 ==
3649 23:55:54.651692 RX Vref Scan: 0
3650 23:55:54.651744
3651 23:55:54.651796 RX Vref 0 -> 0, step: 1
3652 23:55:54.651847
3653 23:55:54.651898 RX Delay -21 -> 252, step: 4
3654 23:55:54.651950 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3655 23:55:54.652002 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3656 23:55:54.652055 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3657 23:55:54.652107 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3658 23:55:54.652158 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3659 23:55:54.652210 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3660 23:55:54.652262 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3661 23:55:54.652315 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3662 23:55:54.652367 iDelay=199, Bit 8, Center 94 (27 ~ 162) 136
3663 23:55:54.652610 iDelay=199, Bit 9, Center 98 (31 ~ 166) 136
3664 23:55:54.652670 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3665 23:55:54.652723 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3666 23:55:54.652783 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3667 23:55:54.652867 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3668 23:55:54.652948 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3669 23:55:54.653030 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3670 23:55:54.653110 ==
3671 23:55:54.653192 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 23:55:54.653274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 23:55:54.653355 ==
3674 23:55:54.653436 DQS Delay:
3675 23:55:54.653517 DQS0 = 0, DQS1 = 0
3676 23:55:54.653598 DQM Delay:
3677 23:55:54.653678 DQM0 = 117, DQM1 = 109
3678 23:55:54.653758 DQ Delay:
3679 23:55:54.653839 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3680 23:55:54.653921 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3681 23:55:54.654002 DQ8 =94, DQ9 =98, DQ10 =112, DQ11 =100
3682 23:55:54.654084 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3683 23:55:54.654197
3684 23:55:54.654267
3685 23:55:54.654320 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0eb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3686 23:55:54.654374 CH1 RK1: MR19=303, MR18=F0EB
3687 23:55:54.654427 CH1_RK1: MR19=0x303, MR18=0xF0EB, DQSOSC=416, MR23=63, INC=37, DEC=25
3688 23:55:54.654479 [RxdqsGatingPostProcess] freq 1200
3689 23:55:54.654532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3690 23:55:54.654585 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 23:55:54.654637 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 23:55:54.654689 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 23:55:54.654742 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 23:55:54.654794 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 23:55:54.654846 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 23:55:54.654897 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 23:55:54.654949 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 23:55:54.655001 Pre-setting of DQS Precalculation
3699 23:55:54.655054 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3700 23:55:54.655107 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3701 23:55:54.655160 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3702 23:55:54.655212
3703 23:55:54.655263
3704 23:55:54.655314 [Calibration Summary] 2400 Mbps
3705 23:55:54.655367 CH 0, Rank 0
3706 23:55:54.655418 SW Impedance : PASS
3707 23:55:54.655470 DUTY Scan : NO K
3708 23:55:54.655522 ZQ Calibration : PASS
3709 23:55:54.655574 Jitter Meter : NO K
3710 23:55:54.655626 CBT Training : PASS
3711 23:55:54.655678 Write leveling : PASS
3712 23:55:54.655730 RX DQS gating : PASS
3713 23:55:54.655782 RX DQ/DQS(RDDQC) : PASS
3714 23:55:54.655834 TX DQ/DQS : PASS
3715 23:55:54.655885 RX DATLAT : PASS
3716 23:55:54.655937 RX DQ/DQS(Engine): PASS
3717 23:55:54.655988 TX OE : NO K
3718 23:55:54.656040 All Pass.
3719 23:55:54.656092
3720 23:55:54.656143 CH 0, Rank 1
3721 23:55:54.656195 SW Impedance : PASS
3722 23:55:54.656247 DUTY Scan : NO K
3723 23:55:54.656298 ZQ Calibration : PASS
3724 23:55:54.656350 Jitter Meter : NO K
3725 23:55:54.656401 CBT Training : PASS
3726 23:55:54.656453 Write leveling : PASS
3727 23:55:54.656504 RX DQS gating : PASS
3728 23:55:54.656556 RX DQ/DQS(RDDQC) : PASS
3729 23:55:54.656607 TX DQ/DQS : PASS
3730 23:55:54.656659 RX DATLAT : PASS
3731 23:55:54.656711 RX DQ/DQS(Engine): PASS
3732 23:55:54.656762 TX OE : NO K
3733 23:55:54.656814 All Pass.
3734 23:55:54.656866
3735 23:55:54.656917 CH 1, Rank 0
3736 23:55:54.656969 SW Impedance : PASS
3737 23:55:54.657021 DUTY Scan : NO K
3738 23:55:54.657073 ZQ Calibration : PASS
3739 23:55:54.657125 Jitter Meter : NO K
3740 23:55:54.657176 CBT Training : PASS
3741 23:55:54.657228 Write leveling : PASS
3742 23:55:54.657280 RX DQS gating : PASS
3743 23:55:54.657332 RX DQ/DQS(RDDQC) : PASS
3744 23:55:54.657383 TX DQ/DQS : PASS
3745 23:55:54.657436 RX DATLAT : PASS
3746 23:55:54.657488 RX DQ/DQS(Engine): PASS
3747 23:55:54.657539 TX OE : NO K
3748 23:55:54.657591 All Pass.
3749 23:55:54.657643
3750 23:55:54.657694 CH 1, Rank 1
3751 23:55:54.657746 SW Impedance : PASS
3752 23:55:54.657797 DUTY Scan : NO K
3753 23:55:54.657849 ZQ Calibration : PASS
3754 23:55:54.657900 Jitter Meter : NO K
3755 23:55:54.657952 CBT Training : PASS
3756 23:55:54.658004 Write leveling : PASS
3757 23:55:54.658055 RX DQS gating : PASS
3758 23:55:54.658107 RX DQ/DQS(RDDQC) : PASS
3759 23:55:54.658158 TX DQ/DQS : PASS
3760 23:55:54.658257 RX DATLAT : PASS
3761 23:55:54.658310 RX DQ/DQS(Engine): PASS
3762 23:55:54.658362 TX OE : NO K
3763 23:55:54.658413 All Pass.
3764 23:55:54.658464
3765 23:55:54.658516 DramC Write-DBI off
3766 23:55:54.658567 PER_BANK_REFRESH: Hybrid Mode
3767 23:55:54.658619 TX_TRACKING: ON
3768 23:55:54.658671 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3769 23:55:54.658724 [FAST_K] Save calibration result to emmc
3770 23:55:54.658776 dramc_set_vcore_voltage set vcore to 650000
3771 23:55:54.658829 Read voltage for 600, 5
3772 23:55:54.658881 Vio18 = 0
3773 23:55:54.658933 Vcore = 650000
3774 23:55:54.658984 Vdram = 0
3775 23:55:54.659035 Vddq = 0
3776 23:55:54.659086 Vmddr = 0
3777 23:55:54.659138 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3778 23:55:54.659190 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3779 23:55:54.659242 MEM_TYPE=3, freq_sel=19
3780 23:55:54.659294 sv_algorithm_assistance_LP4_1600
3781 23:55:54.659347 ============ PULL DRAM RESETB DOWN ============
3782 23:55:54.659399 ========== PULL DRAM RESETB DOWN end =========
3783 23:55:54.659453 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3784 23:55:54.659505 ===================================
3785 23:55:54.659557 LPDDR4 DRAM CONFIGURATION
3786 23:55:54.659609 ===================================
3787 23:55:54.659660 EX_ROW_EN[0] = 0x0
3788 23:55:54.659712 EX_ROW_EN[1] = 0x0
3789 23:55:54.659763 LP4Y_EN = 0x0
3790 23:55:54.659815 WORK_FSP = 0x0
3791 23:55:54.659866 WL = 0x2
3792 23:55:54.659917 RL = 0x2
3793 23:55:54.659969 BL = 0x2
3794 23:55:54.660020 RPST = 0x0
3795 23:55:54.660071 RD_PRE = 0x0
3796 23:55:54.660123 WR_PRE = 0x1
3797 23:55:54.660174 WR_PST = 0x0
3798 23:55:54.660225 DBI_WR = 0x0
3799 23:55:54.660276 DBI_RD = 0x0
3800 23:55:54.660328 OTF = 0x1
3801 23:55:54.660380 ===================================
3802 23:55:54.660433 ===================================
3803 23:55:54.660484 ANA top config
3804 23:55:54.660536 ===================================
3805 23:55:54.660588 DLL_ASYNC_EN = 0
3806 23:55:54.660842 ALL_SLAVE_EN = 1
3807 23:55:54.660915 NEW_RANK_MODE = 1
3808 23:55:54.660971 DLL_IDLE_MODE = 1
3809 23:55:54.661025 LP45_APHY_COMB_EN = 1
3810 23:55:54.661078 TX_ODT_DIS = 1
3811 23:55:54.661132 NEW_8X_MODE = 1
3812 23:55:54.661185 ===================================
3813 23:55:54.661238 ===================================
3814 23:55:54.661291 data_rate = 1200
3815 23:55:54.661343 CKR = 1
3816 23:55:54.661396 DQ_P2S_RATIO = 8
3817 23:55:54.661447 ===================================
3818 23:55:54.661500 CA_P2S_RATIO = 8
3819 23:55:54.661551 DQ_CA_OPEN = 0
3820 23:55:54.661603 DQ_SEMI_OPEN = 0
3821 23:55:54.661655 CA_SEMI_OPEN = 0
3822 23:55:54.661707 CA_FULL_RATE = 0
3823 23:55:54.661759 DQ_CKDIV4_EN = 1
3824 23:55:54.661812 CA_CKDIV4_EN = 1
3825 23:55:54.661864 CA_PREDIV_EN = 0
3826 23:55:54.661916 PH8_DLY = 0
3827 23:55:54.661969 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3828 23:55:54.662020 DQ_AAMCK_DIV = 4
3829 23:55:54.662072 CA_AAMCK_DIV = 4
3830 23:55:54.662124 CA_ADMCK_DIV = 4
3831 23:55:54.662208 DQ_TRACK_CA_EN = 0
3832 23:55:54.662276 CA_PICK = 600
3833 23:55:54.662329 CA_MCKIO = 600
3834 23:55:54.662380 MCKIO_SEMI = 0
3835 23:55:54.662432 PLL_FREQ = 2288
3836 23:55:54.662484 DQ_UI_PI_RATIO = 32
3837 23:55:54.662537 CA_UI_PI_RATIO = 0
3838 23:55:54.662588 ===================================
3839 23:55:54.662640 ===================================
3840 23:55:54.662694 memory_type:LPDDR4
3841 23:55:54.662746 GP_NUM : 10
3842 23:55:54.662798 SRAM_EN : 1
3843 23:55:54.662849 MD32_EN : 0
3844 23:55:54.662901 ===================================
3845 23:55:54.662953 [ANA_INIT] >>>>>>>>>>>>>>
3846 23:55:54.663006 <<<<<< [CONFIGURE PHASE]: ANA_TX
3847 23:55:54.663058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3848 23:55:54.663110 ===================================
3849 23:55:54.663162 data_rate = 1200,PCW = 0X5800
3850 23:55:54.663215 ===================================
3851 23:55:54.663267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3852 23:55:54.663319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 23:55:54.663372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 23:55:54.663424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3855 23:55:54.663477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3856 23:55:54.663528 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3857 23:55:54.663580 [ANA_INIT] flow start
3858 23:55:54.663632 [ANA_INIT] PLL >>>>>>>>
3859 23:55:54.663684 [ANA_INIT] PLL <<<<<<<<
3860 23:55:54.663735 [ANA_INIT] MIDPI >>>>>>>>
3861 23:55:54.663787 [ANA_INIT] MIDPI <<<<<<<<
3862 23:55:54.663838 [ANA_INIT] DLL >>>>>>>>
3863 23:55:54.663890 [ANA_INIT] flow end
3864 23:55:54.663942 ============ LP4 DIFF to SE enter ============
3865 23:55:54.663994 ============ LP4 DIFF to SE exit ============
3866 23:55:54.664047 [ANA_INIT] <<<<<<<<<<<<<
3867 23:55:54.664099 [Flow] Enable top DCM control >>>>>
3868 23:55:54.664151 [Flow] Enable top DCM control <<<<<
3869 23:55:54.664202 Enable DLL master slave shuffle
3870 23:55:54.664255 ==============================================================
3871 23:55:54.664307 Gating Mode config
3872 23:55:54.664359 ==============================================================
3873 23:55:54.664411 Config description:
3874 23:55:54.664463 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3875 23:55:54.664529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3876 23:55:54.669010 SELPH_MODE 0: By rank 1: By Phase
3877 23:55:54.672845 ==============================================================
3878 23:55:54.676055 GAT_TRACK_EN = 1
3879 23:55:54.679362 RX_GATING_MODE = 2
3880 23:55:54.682437 RX_GATING_TRACK_MODE = 2
3881 23:55:54.686037 SELPH_MODE = 1
3882 23:55:54.689731 PICG_EARLY_EN = 1
3883 23:55:54.692677 VALID_LAT_VALUE = 1
3884 23:55:54.699468 ==============================================================
3885 23:55:54.702621 Enter into Gating configuration >>>>
3886 23:55:54.705634 Exit from Gating configuration <<<<
3887 23:55:54.708950 Enter into DVFS_PRE_config >>>>>
3888 23:55:54.719098 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3889 23:55:54.721913 Exit from DVFS_PRE_config <<<<<
3890 23:55:54.725188 Enter into PICG configuration >>>>
3891 23:55:54.728545 Exit from PICG configuration <<<<
3892 23:55:54.732030 [RX_INPUT] configuration >>>>>
3893 23:55:54.732193 [RX_INPUT] configuration <<<<<
3894 23:55:54.738377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3895 23:55:54.745190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3896 23:55:54.752073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 23:55:54.754973 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 23:55:54.762125 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 23:55:54.768420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 23:55:54.771905 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3901 23:55:54.775235 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3902 23:55:54.781872 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3903 23:55:54.785386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3904 23:55:54.789231 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3905 23:55:54.795137 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 23:55:54.798374 ===================================
3907 23:55:54.798832 LPDDR4 DRAM CONFIGURATION
3908 23:55:54.801480 ===================================
3909 23:55:54.804807 EX_ROW_EN[0] = 0x0
3910 23:55:54.808051 EX_ROW_EN[1] = 0x0
3911 23:55:54.808506 LP4Y_EN = 0x0
3912 23:55:54.811814 WORK_FSP = 0x0
3913 23:55:54.812428 WL = 0x2
3914 23:55:54.814689 RL = 0x2
3915 23:55:54.815141 BL = 0x2
3916 23:55:54.818671 RPST = 0x0
3917 23:55:54.819122 RD_PRE = 0x0
3918 23:55:54.821218 WR_PRE = 0x1
3919 23:55:54.821667 WR_PST = 0x0
3920 23:55:54.824688 DBI_WR = 0x0
3921 23:55:54.825099 DBI_RD = 0x0
3922 23:55:54.828018 OTF = 0x1
3923 23:55:54.831440 ===================================
3924 23:55:54.834970 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3925 23:55:54.837745 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3926 23:55:54.844854 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 23:55:54.847806 ===================================
3928 23:55:54.848318 LPDDR4 DRAM CONFIGURATION
3929 23:55:54.850835 ===================================
3930 23:55:54.854127 EX_ROW_EN[0] = 0x10
3931 23:55:54.857459 EX_ROW_EN[1] = 0x0
3932 23:55:54.857869 LP4Y_EN = 0x0
3933 23:55:54.861255 WORK_FSP = 0x0
3934 23:55:54.861769 WL = 0x2
3935 23:55:54.864313 RL = 0x2
3936 23:55:54.864824 BL = 0x2
3937 23:55:54.879693 RPST = 0x0
3938 23:55:54.880164 RD_PRE = 0x0
3939 23:55:54.880498 WR_PRE = 0x1
3940 23:55:54.880812 WR_PST = 0x0
3941 23:55:54.881108 DBI_WR = 0x0
3942 23:55:54.881398 DBI_RD = 0x0
3943 23:55:54.881684 OTF = 0x1
3944 23:55:54.882025 ===================================
3945 23:55:54.887096 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3946 23:55:54.890340 nWR fixed to 30
3947 23:55:54.893749 [ModeRegInit_LP4] CH0 RK0
3948 23:55:54.894192 [ModeRegInit_LP4] CH0 RK1
3949 23:55:54.897009 [ModeRegInit_LP4] CH1 RK0
3950 23:55:54.900289 [ModeRegInit_LP4] CH1 RK1
3951 23:55:54.900584 match AC timing 17
3952 23:55:54.906839 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3953 23:55:54.910545 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3954 23:55:54.913841 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3955 23:55:54.919772 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3956 23:55:54.923180 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3957 23:55:54.923464 ==
3958 23:55:54.926366 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 23:55:54.930195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 23:55:54.930524 ==
3961 23:55:54.936380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 23:55:54.943370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3963 23:55:54.946542 [CA 0] Center 36 (6~66) winsize 61
3964 23:55:54.949956 [CA 1] Center 36 (6~66) winsize 61
3965 23:55:54.953327 [CA 2] Center 34 (3~65) winsize 63
3966 23:55:54.956544 [CA 3] Center 34 (3~65) winsize 63
3967 23:55:54.959866 [CA 4] Center 33 (3~64) winsize 62
3968 23:55:54.963236 [CA 5] Center 33 (3~64) winsize 62
3969 23:55:54.963825
3970 23:55:54.966099 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3971 23:55:54.966609
3972 23:55:54.969436 [CATrainingPosCal] consider 1 rank data
3973 23:55:54.972933 u2DelayCellTimex100 = 270/100 ps
3974 23:55:54.976231 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 23:55:54.979489 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3976 23:55:54.982683 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3977 23:55:54.986346 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3978 23:55:54.992925 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 23:55:54.995693 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 23:55:54.996201
3981 23:55:54.999423 CA PerBit enable=1, Macro0, CA PI delay=33
3982 23:55:54.999995
3983 23:55:55.002826 [CBTSetCACLKResult] CA Dly = 33
3984 23:55:55.003376 CS Dly: 5 (0~36)
3985 23:55:55.003745 ==
3986 23:55:55.006305 Dram Type= 6, Freq= 0, CH_0, rank 1
3987 23:55:55.012326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 23:55:55.012870 ==
3989 23:55:55.015518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 23:55:55.022574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 23:55:55.025871 [CA 0] Center 36 (6~66) winsize 61
3992 23:55:55.029196 [CA 1] Center 36 (6~66) winsize 61
3993 23:55:55.032188 [CA 2] Center 34 (4~64) winsize 61
3994 23:55:55.035639 [CA 3] Center 33 (3~64) winsize 62
3995 23:55:55.038911 [CA 4] Center 33 (2~64) winsize 63
3996 23:55:55.042458 [CA 5] Center 33 (2~64) winsize 63
3997 23:55:55.042920
3998 23:55:55.045429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 23:55:55.045892
4000 23:55:55.049201 [CATrainingPosCal] consider 2 rank data
4001 23:55:55.052513 u2DelayCellTimex100 = 270/100 ps
4002 23:55:55.055241 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4003 23:55:55.061933 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4004 23:55:55.065038 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4005 23:55:55.068320 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 23:55:55.072073 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 23:55:55.075031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 23:55:55.075527
4009 23:55:55.078462 CA PerBit enable=1, Macro0, CA PI delay=33
4010 23:55:55.079051
4011 23:55:55.082078 [CBTSetCACLKResult] CA Dly = 33
4012 23:55:55.084940 CS Dly: 5 (0~36)
4013 23:55:55.085491
4014 23:55:55.088406 ----->DramcWriteLeveling(PI) begin...
4015 23:55:55.088972 ==
4016 23:55:55.091593 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 23:55:55.095300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 23:55:55.095856 ==
4019 23:55:55.098480 Write leveling (Byte 0): 33 => 33
4020 23:55:55.101941 Write leveling (Byte 1): 29 => 29
4021 23:55:55.105451 DramcWriteLeveling(PI) end<-----
4022 23:55:55.106001
4023 23:55:55.106428 ==
4024 23:55:55.108238 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 23:55:55.111537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 23:55:55.112101 ==
4027 23:55:55.114812 [Gating] SW mode calibration
4028 23:55:55.121675 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4029 23:55:55.128211 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4030 23:55:55.131569 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 23:55:55.134664 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 23:55:55.141608 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 23:55:55.144228 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4034 23:55:55.147892 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4035 23:55:55.154401 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 23:55:55.157716 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 23:55:55.161368 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 23:55:55.167636 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 23:55:55.170682 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 23:55:55.174040 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 23:55:55.180873 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4042 23:55:55.183710 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4043 23:55:55.187344 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 23:55:55.194262 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 23:55:55.197341 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 23:55:55.200482 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 23:55:55.206850 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 23:55:55.210517 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 23:55:55.214125 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:55:55.220339 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4051 23:55:55.223398 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:55:55.226823 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:55:55.233673 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:55:55.236728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:55:55.240037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:55:55.246710 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:55:55.250285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:55:55.253526 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:55:55.260342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:55:55.263308 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:55:55.266478 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:55:55.273231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:55:55.276409 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:55:55.279545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:55:55.286151 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4066 23:55:55.289629 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4067 23:55:55.292923 Total UI for P1: 0, mck2ui 16
4068 23:55:55.296170 best dqsien dly found for B0: ( 0, 13, 12)
4069 23:55:55.299566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:55:55.302700 Total UI for P1: 0, mck2ui 16
4071 23:55:55.306349 best dqsien dly found for B1: ( 0, 13, 14)
4072 23:55:55.309411 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4073 23:55:55.313455 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4074 23:55:55.315970
4075 23:55:55.319475 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4076 23:55:55.322848 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 23:55:55.325814 [Gating] SW calibration Done
4078 23:55:55.326303 ==
4079 23:55:55.329393 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 23:55:55.332947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 23:55:55.333534 ==
4082 23:55:55.333907 RX Vref Scan: 0
4083 23:55:55.335846
4084 23:55:55.336307 RX Vref 0 -> 0, step: 1
4085 23:55:55.336675
4086 23:55:55.339081 RX Delay -230 -> 252, step: 16
4087 23:55:55.342584 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4088 23:55:55.349063 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4089 23:55:55.352776 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4090 23:55:55.355759 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4091 23:55:55.358683 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4092 23:55:55.365443 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4093 23:55:55.368649 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4094 23:55:55.372094 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4095 23:55:55.375032 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4096 23:55:55.378730 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4097 23:55:55.384929 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4098 23:55:55.388416 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4099 23:55:55.392028 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4100 23:55:55.394885 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4101 23:55:55.401504 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4102 23:55:55.404847 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4103 23:55:55.405355 ==
4104 23:55:55.407986 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 23:55:55.411489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 23:55:55.411915 ==
4107 23:55:55.414689 DQS Delay:
4108 23:55:55.415108 DQS0 = 0, DQS1 = 0
4109 23:55:55.418200 DQM Delay:
4110 23:55:55.418722 DQM0 = 48, DQM1 = 30
4111 23:55:55.419062 DQ Delay:
4112 23:55:55.421264 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4113 23:55:55.424772 DQ4 =57, DQ5 =33, DQ6 =57, DQ7 =57
4114 23:55:55.428122 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4115 23:55:55.430982 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4116 23:55:55.431409
4117 23:55:55.431744
4118 23:55:55.434347 ==
4119 23:55:55.437769 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:55:55.441075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:55:55.441504 ==
4122 23:55:55.441843
4123 23:55:55.442155
4124 23:55:55.444489 TX Vref Scan disable
4125 23:55:55.444908 == TX Byte 0 ==
4126 23:55:55.451027 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4127 23:55:55.454126 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4128 23:55:55.454607 == TX Byte 1 ==
4129 23:55:55.460769 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4130 23:55:55.463806 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4131 23:55:55.464231 ==
4132 23:55:55.467334 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 23:55:55.470765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 23:55:55.471202 ==
4135 23:55:55.471541
4136 23:55:55.471849
4137 23:55:55.474042 TX Vref Scan disable
4138 23:55:55.477098 == TX Byte 0 ==
4139 23:55:55.480410 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4140 23:55:55.486687 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4141 23:55:55.487112 == TX Byte 1 ==
4142 23:55:55.490329 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4143 23:55:55.496527 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4144 23:55:55.497042
4145 23:55:55.497377 [DATLAT]
4146 23:55:55.497688 Freq=600, CH0 RK0
4147 23:55:55.497993
4148 23:55:55.499926 DATLAT Default: 0x9
4149 23:55:55.503742 0, 0xFFFF, sum = 0
4150 23:55:55.504283 1, 0xFFFF, sum = 0
4151 23:55:55.506550 2, 0xFFFF, sum = 0
4152 23:55:55.506980 3, 0xFFFF, sum = 0
4153 23:55:55.509868 4, 0xFFFF, sum = 0
4154 23:55:55.510350 5, 0xFFFF, sum = 0
4155 23:55:55.512986 6, 0xFFFF, sum = 0
4156 23:55:55.513505 7, 0xFFFF, sum = 0
4157 23:55:55.516545 8, 0x0, sum = 1
4158 23:55:55.517118 9, 0x0, sum = 2
4159 23:55:55.519604 10, 0x0, sum = 3
4160 23:55:55.520055 11, 0x0, sum = 4
4161 23:55:55.520397 best_step = 9
4162 23:55:55.520710
4163 23:55:55.522926 ==
4164 23:55:55.526256 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 23:55:55.529930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 23:55:55.530511 ==
4167 23:55:55.530918 RX Vref Scan: 1
4168 23:55:55.531243
4169 23:55:55.533285 RX Vref 0 -> 0, step: 1
4170 23:55:55.533703
4171 23:55:55.536175 RX Delay -195 -> 252, step: 8
4172 23:55:55.536594
4173 23:55:55.539441 Set Vref, RX VrefLevel [Byte0]: 58
4174 23:55:55.542827 [Byte1]: 58
4175 23:55:55.543249
4176 23:55:55.546078 Final RX Vref Byte 0 = 58 to rank0
4177 23:55:55.549682 Final RX Vref Byte 1 = 58 to rank0
4178 23:55:55.552868 Final RX Vref Byte 0 = 58 to rank1
4179 23:55:55.556001 Final RX Vref Byte 1 = 58 to rank1==
4180 23:55:55.559286 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 23:55:55.565956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 23:55:55.566425 ==
4183 23:55:55.566768 DQS Delay:
4184 23:55:55.567079 DQS0 = 0, DQS1 = 0
4185 23:55:55.569110 DQM Delay:
4186 23:55:55.569440 DQM0 = 44, DQM1 = 32
4187 23:55:55.572845 DQ Delay:
4188 23:55:55.575634 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4189 23:55:55.579223 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4190 23:55:55.582439 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4191 23:55:55.585550 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4192 23:55:55.585971
4193 23:55:55.586361
4194 23:55:55.592242 [DQSOSCAuto] RK0, (LSB)MR18= 0x633b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4195 23:55:55.595391 CH0 RK0: MR19=808, MR18=633B
4196 23:55:55.602247 CH0_RK0: MR19=0x808, MR18=0x633B, DQSOSC=391, MR23=63, INC=171, DEC=114
4197 23:55:55.602759
4198 23:55:55.605651 ----->DramcWriteLeveling(PI) begin...
4199 23:55:55.606296 ==
4200 23:55:55.608792 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 23:55:55.612419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 23:55:55.612896 ==
4203 23:55:55.615845 Write leveling (Byte 0): 32 => 32
4204 23:55:55.618828 Write leveling (Byte 1): 32 => 32
4205 23:55:55.621829 DramcWriteLeveling(PI) end<-----
4206 23:55:55.622330
4207 23:55:55.622698 ==
4208 23:55:55.625224 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 23:55:55.628547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 23:55:55.629207 ==
4211 23:55:55.631843 [Gating] SW mode calibration
4212 23:55:55.638559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4213 23:55:55.645370 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4214 23:55:55.648567 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 23:55:55.654929 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 23:55:55.658330 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 23:55:55.661988 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
4218 23:55:55.668452 0 9 16 | B1->B0 | 2929 2626 | 1 1 | (1 0) (1 0)
4219 23:55:55.671438 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 23:55:55.675075 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 23:55:55.681261 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 23:55:55.684546 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:55:55.688073 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 23:55:55.695080 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:55:55.698449 0 10 12 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
4226 23:55:55.701472 0 10 16 | B1->B0 | 3838 3d3d | 0 1 | (1 1) (0 0)
4227 23:55:55.707718 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 23:55:55.711246 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 23:55:55.714737 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 23:55:55.721092 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 23:55:55.724393 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 23:55:55.727525 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:55:55.734308 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4234 23:55:55.737597 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4235 23:55:55.740624 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:55:55.747459 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:55:55.750638 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:55:55.754371 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:55:55.760752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:55:55.764005 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:55:55.767212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:55:55.773872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:55:55.776984 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:55:55.780700 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:55:55.787123 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:55:55.790387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:55:55.793585 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:55:55.800454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:55:55.803657 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:55:55.806876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4251 23:55:55.810423 Total UI for P1: 0, mck2ui 16
4252 23:55:55.813513 best dqsien dly found for B0: ( 0, 13, 14)
4253 23:55:55.820371 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 23:55:55.820947 Total UI for P1: 0, mck2ui 16
4255 23:55:55.826393 best dqsien dly found for B1: ( 0, 13, 16)
4256 23:55:55.830127 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4257 23:55:55.833347 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4258 23:55:55.833932
4259 23:55:55.836451 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4260 23:55:55.839515 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4261 23:55:55.843292 [Gating] SW calibration Done
4262 23:55:55.843966 ==
4263 23:55:55.846222 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 23:55:55.849509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 23:55:55.850270 ==
4266 23:55:55.852848 RX Vref Scan: 0
4267 23:55:55.853308
4268 23:55:55.853673 RX Vref 0 -> 0, step: 1
4269 23:55:55.856277
4270 23:55:55.856753 RX Delay -230 -> 252, step: 16
4271 23:55:55.862793 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4272 23:55:55.866310 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4273 23:55:55.869266 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4274 23:55:55.872409 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4275 23:55:55.879037 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4276 23:55:55.882501 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4277 23:55:55.885889 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4278 23:55:55.889095 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4279 23:55:55.892343 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4280 23:55:55.899151 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4281 23:55:55.902320 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4282 23:55:55.905811 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4283 23:55:55.911726 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4284 23:55:55.915089 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4285 23:55:55.918810 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4286 23:55:55.921897 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4287 23:55:55.922570 ==
4288 23:55:55.924937 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 23:55:55.931684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 23:55:55.932155 ==
4291 23:55:55.932524 DQS Delay:
4292 23:55:55.935219 DQS0 = 0, DQS1 = 0
4293 23:55:55.935802 DQM Delay:
4294 23:55:55.936178 DQM0 = 40, DQM1 = 34
4295 23:55:55.938221 DQ Delay:
4296 23:55:55.941688 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4297 23:55:55.945517 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4298 23:55:55.947924 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4299 23:55:55.951610 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4300 23:55:55.952089
4301 23:55:55.952456
4302 23:55:55.952792 ==
4303 23:55:55.954741 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 23:55:55.957995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 23:55:55.958444 ==
4306 23:55:55.958777
4307 23:55:55.959081
4308 23:55:55.961092 TX Vref Scan disable
4309 23:55:55.964369 == TX Byte 0 ==
4310 23:55:55.967678 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4311 23:55:55.970930 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4312 23:55:55.974462 == TX Byte 1 ==
4313 23:55:55.978246 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4314 23:55:55.981054 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4315 23:55:55.981482 ==
4316 23:55:55.984688 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 23:55:55.990668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 23:55:55.991180 ==
4319 23:55:55.991511
4320 23:55:55.991819
4321 23:55:55.992114 TX Vref Scan disable
4322 23:55:55.995114 == TX Byte 0 ==
4323 23:55:55.998316 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4324 23:55:56.004683 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4325 23:55:56.005118 == TX Byte 1 ==
4326 23:55:56.007913 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4327 23:55:56.014847 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4328 23:55:56.015368
4329 23:55:56.015703 [DATLAT]
4330 23:55:56.016018 Freq=600, CH0 RK1
4331 23:55:56.016400
4332 23:55:56.018234 DATLAT Default: 0x9
4333 23:55:56.018756 0, 0xFFFF, sum = 0
4334 23:55:56.022117 1, 0xFFFF, sum = 0
4335 23:55:56.024998 2, 0xFFFF, sum = 0
4336 23:55:56.025528 3, 0xFFFF, sum = 0
4337 23:55:56.027851 4, 0xFFFF, sum = 0
4338 23:55:56.028276 5, 0xFFFF, sum = 0
4339 23:55:56.031370 6, 0xFFFF, sum = 0
4340 23:55:56.031901 7, 0xFFFF, sum = 0
4341 23:55:56.034628 8, 0x0, sum = 1
4342 23:55:56.035161 9, 0x0, sum = 2
4343 23:55:56.035505 10, 0x0, sum = 3
4344 23:55:56.038141 11, 0x0, sum = 4
4345 23:55:56.038700 best_step = 9
4346 23:55:56.039126
4347 23:55:56.041278 ==
4348 23:55:56.041698 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 23:55:56.047698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 23:55:56.048119 ==
4351 23:55:56.048453 RX Vref Scan: 0
4352 23:55:56.048758
4353 23:55:56.050917 RX Vref 0 -> 0, step: 1
4354 23:55:56.051331
4355 23:55:56.054270 RX Delay -195 -> 252, step: 8
4356 23:55:56.060849 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4357 23:55:56.064054 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4358 23:55:56.067617 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4359 23:55:56.070686 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4360 23:55:56.074087 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4361 23:55:56.081017 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4362 23:55:56.084099 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4363 23:55:56.087260 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4364 23:55:56.090484 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4365 23:55:56.097366 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4366 23:55:56.100513 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4367 23:55:56.104120 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4368 23:55:56.106950 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4369 23:55:56.113718 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4370 23:55:56.116935 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4371 23:55:56.120611 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4372 23:55:56.121163 ==
4373 23:55:56.123387 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 23:55:56.129812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 23:55:56.130407 ==
4376 23:55:56.130778 DQS Delay:
4377 23:55:56.131113 DQS0 = 0, DQS1 = 0
4378 23:55:56.133123 DQM Delay:
4379 23:55:56.133574 DQM0 = 42, DQM1 = 35
4380 23:55:56.136414 DQ Delay:
4381 23:55:56.139682 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4382 23:55:56.143003 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4383 23:55:56.146356 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4384 23:55:56.149885 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4385 23:55:56.150508
4386 23:55:56.150877
4387 23:55:56.156017 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c0e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4388 23:55:56.159418 CH0 RK1: MR19=808, MR18=5C0E
4389 23:55:56.166112 CH0_RK1: MR19=0x808, MR18=0x5C0E, DQSOSC=392, MR23=63, INC=170, DEC=113
4390 23:55:56.169615 [RxdqsGatingPostProcess] freq 600
4391 23:55:56.173236 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 23:55:56.175885 Pre-setting of DQS Precalculation
4393 23:55:56.182378 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 23:55:56.182910 ==
4395 23:55:56.186209 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 23:55:56.189208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 23:55:56.189667 ==
4398 23:55:56.195686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 23:55:56.202118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4400 23:55:56.205351 [CA 0] Center 35 (5~66) winsize 62
4401 23:55:56.208712 [CA 1] Center 35 (5~66) winsize 62
4402 23:55:56.211993 [CA 2] Center 34 (3~65) winsize 63
4403 23:55:56.215572 [CA 3] Center 33 (3~64) winsize 62
4404 23:55:56.218909 [CA 4] Center 34 (4~65) winsize 62
4405 23:55:56.222753 [CA 5] Center 33 (3~64) winsize 62
4406 23:55:56.223308
4407 23:55:56.225708 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4408 23:55:56.226332
4409 23:55:56.229150 [CATrainingPosCal] consider 1 rank data
4410 23:55:56.231793 u2DelayCellTimex100 = 270/100 ps
4411 23:55:56.235126 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 23:55:56.238714 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 23:55:56.242720 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4414 23:55:56.245058 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 23:55:56.248734 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 23:55:56.251480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 23:55:56.255133
4418 23:55:56.258355 CA PerBit enable=1, Macro0, CA PI delay=33
4419 23:55:56.258828
4420 23:55:56.261927 [CBTSetCACLKResult] CA Dly = 33
4421 23:55:56.262618 CS Dly: 5 (0~36)
4422 23:55:56.262994 ==
4423 23:55:56.265080 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 23:55:56.268587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 23:55:56.269166 ==
4426 23:55:56.274792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 23:55:56.281354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4428 23:55:56.285170 [CA 0] Center 35 (5~66) winsize 62
4429 23:55:56.287860 [CA 1] Center 36 (6~66) winsize 61
4430 23:55:56.291550 [CA 2] Center 34 (4~65) winsize 62
4431 23:55:56.294825 [CA 3] Center 34 (4~64) winsize 61
4432 23:55:56.297767 [CA 4] Center 34 (3~65) winsize 63
4433 23:55:56.302019 [CA 5] Center 34 (3~65) winsize 63
4434 23:55:56.302618
4435 23:55:56.304386 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4436 23:55:56.304846
4437 23:55:56.307517 [CATrainingPosCal] consider 2 rank data
4438 23:55:56.310948 u2DelayCellTimex100 = 270/100 ps
4439 23:55:56.314636 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 23:55:56.317704 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4441 23:55:56.321065 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 23:55:56.327647 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4443 23:55:56.330712 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 23:55:56.334301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 23:55:56.334867
4446 23:55:56.337565 CA PerBit enable=1, Macro0, CA PI delay=33
4447 23:55:56.338021
4448 23:55:56.340633 [CBTSetCACLKResult] CA Dly = 33
4449 23:55:56.341183 CS Dly: 5 (0~37)
4450 23:55:56.341558
4451 23:55:56.343958 ----->DramcWriteLeveling(PI) begin...
4452 23:55:56.344444 ==
4453 23:55:56.347343 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 23:55:56.353954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 23:55:56.354452 ==
4456 23:55:56.357181 Write leveling (Byte 0): 29 => 29
4457 23:55:56.360622 Write leveling (Byte 1): 29 => 29
4458 23:55:56.364118 DramcWriteLeveling(PI) end<-----
4459 23:55:56.364692
4460 23:55:56.365084 ==
4461 23:55:56.367102 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 23:55:56.370685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 23:55:56.371150 ==
4464 23:55:56.373493 [Gating] SW mode calibration
4465 23:55:56.380290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 23:55:56.387037 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 23:55:56.390720 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 23:55:56.393743 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 23:55:56.400610 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 23:55:56.403354 0 9 12 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (1 1)
4471 23:55:56.406802 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4472 23:55:56.413336 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 23:55:56.417076 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 23:55:56.419967 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 23:55:56.423323 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 23:55:56.430070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 23:55:56.433350 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4478 23:55:56.436462 0 10 12 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (1 1)
4479 23:55:56.443216 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 23:55:56.446914 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 23:55:56.450028 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 23:55:56.456323 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 23:55:56.459610 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:55:56.462888 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:55:56.469643 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:55:56.472795 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:55:56.476258 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4488 23:55:56.483123 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:55:56.486016 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:55:56.489151 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:55:56.495984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:55:56.499567 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:55:56.502371 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:55:56.509280 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:55:56.512477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:55:56.515807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:55:56.522406 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:55:56.532182 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:55:56.532836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:55:56.535533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:55:56.538804 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:55:56.541758 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 23:55:56.548286 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 23:55:56.551672 Total UI for P1: 0, mck2ui 16
4505 23:55:56.555097 best dqsien dly found for B0: ( 0, 13, 12)
4506 23:55:56.558136 Total UI for P1: 0, mck2ui 16
4507 23:55:56.561558 best dqsien dly found for B1: ( 0, 13, 12)
4508 23:55:56.564789 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4509 23:55:56.568039 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 23:55:56.568680
4511 23:55:56.571264 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4512 23:55:56.574723 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 23:55:56.577760 [Gating] SW calibration Done
4514 23:55:56.578263 ==
4515 23:55:56.581584 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 23:55:56.584654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 23:55:56.588274 ==
4518 23:55:56.588691 RX Vref Scan: 0
4519 23:55:56.589027
4520 23:55:56.591396 RX Vref 0 -> 0, step: 1
4521 23:55:56.591817
4522 23:55:56.594814 RX Delay -230 -> 252, step: 16
4523 23:55:56.597484 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4524 23:55:56.601159 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4525 23:55:56.604410 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4526 23:55:56.610811 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4527 23:55:56.614372 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4528 23:55:56.617282 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4529 23:55:56.620646 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4530 23:55:56.627313 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4531 23:55:56.630687 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4532 23:55:56.633698 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4533 23:55:56.637066 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4534 23:55:56.643531 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4535 23:55:56.647130 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4536 23:55:56.650233 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4537 23:55:56.653474 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4538 23:55:56.660455 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4539 23:55:56.660871 ==
4540 23:55:56.663644 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 23:55:56.666831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 23:55:56.667273 ==
4543 23:55:56.667774 DQS Delay:
4544 23:55:56.669933 DQS0 = 0, DQS1 = 0
4545 23:55:56.670415 DQM Delay:
4546 23:55:56.673232 DQM0 = 44, DQM1 = 37
4547 23:55:56.673646 DQ Delay:
4548 23:55:56.676781 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4549 23:55:56.679905 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4550 23:55:56.682994 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4551 23:55:56.686490 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4552 23:55:56.687086
4553 23:55:56.687725
4554 23:55:56.688191 ==
4555 23:55:56.689848 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 23:55:56.692685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 23:55:56.693290 ==
4558 23:55:56.696161
4559 23:55:56.696586
4560 23:55:56.697017 TX Vref Scan disable
4561 23:55:56.699361 == TX Byte 0 ==
4562 23:55:56.702657 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4563 23:55:56.706140 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4564 23:55:56.709568 == TX Byte 1 ==
4565 23:55:56.712823 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4566 23:55:56.716827 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4567 23:55:56.719550 ==
4568 23:55:56.722678 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 23:55:56.725897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 23:55:56.726532 ==
4571 23:55:56.727084
4572 23:55:56.727513
4573 23:55:56.729360 TX Vref Scan disable
4574 23:55:56.729920 == TX Byte 0 ==
4575 23:55:56.735684 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4576 23:55:56.739195 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4577 23:55:56.742334 == TX Byte 1 ==
4578 23:55:56.745700 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4579 23:55:56.748785 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4580 23:55:56.749263
4581 23:55:56.749740 [DATLAT]
4582 23:55:56.752356 Freq=600, CH1 RK0
4583 23:55:56.752830
4584 23:55:56.753306 DATLAT Default: 0x9
4585 23:55:56.755658 0, 0xFFFF, sum = 0
4586 23:55:56.758834 1, 0xFFFF, sum = 0
4587 23:55:56.759317 2, 0xFFFF, sum = 0
4588 23:55:56.762017 3, 0xFFFF, sum = 0
4589 23:55:56.762544 4, 0xFFFF, sum = 0
4590 23:55:56.765630 5, 0xFFFF, sum = 0
4591 23:55:56.766113 6, 0xFFFF, sum = 0
4592 23:55:56.768813 7, 0xFFFF, sum = 0
4593 23:55:56.769393 8, 0x0, sum = 1
4594 23:55:56.772082 9, 0x0, sum = 2
4595 23:55:56.772678 10, 0x0, sum = 3
4596 23:55:56.775680 11, 0x0, sum = 4
4597 23:55:56.776256 best_step = 9
4598 23:55:56.776755
4599 23:55:56.777202 ==
4600 23:55:56.778641 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 23:55:56.781854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 23:55:56.782464 ==
4603 23:55:56.785084 RX Vref Scan: 1
4604 23:55:56.785671
4605 23:55:56.788902 RX Vref 0 -> 0, step: 1
4606 23:55:56.789477
4607 23:55:56.789981 RX Delay -195 -> 252, step: 8
4608 23:55:56.790498
4609 23:55:56.791552 Set Vref, RX VrefLevel [Byte0]: 52
4610 23:55:56.795159 [Byte1]: 52
4611 23:55:56.799585
4612 23:55:56.800153 Final RX Vref Byte 0 = 52 to rank0
4613 23:55:56.803058 Final RX Vref Byte 1 = 52 to rank0
4614 23:55:56.806253 Final RX Vref Byte 0 = 52 to rank1
4615 23:55:56.809561 Final RX Vref Byte 1 = 52 to rank1==
4616 23:55:56.812434 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 23:55:56.819578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 23:55:56.820126 ==
4619 23:55:56.820610 DQS Delay:
4620 23:55:56.822390 DQS0 = 0, DQS1 = 0
4621 23:55:56.822865 DQM Delay:
4622 23:55:56.823346 DQM0 = 44, DQM1 = 34
4623 23:55:56.826658 DQ Delay:
4624 23:55:56.829489 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =40
4625 23:55:56.832646 DQ4 =40, DQ5 =56, DQ6 =52, DQ7 =44
4626 23:55:56.835577 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4627 23:55:56.838927 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4628 23:55:56.839416
4629 23:55:56.839979
4630 23:55:56.845604 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4631 23:55:56.848827 CH1 RK0: MR19=808, MR18=4A2F
4632 23:55:56.855574 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4633 23:55:56.856197
4634 23:55:56.858713 ----->DramcWriteLeveling(PI) begin...
4635 23:55:56.859196 ==
4636 23:55:56.862031 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 23:55:56.865791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 23:55:56.866361 ==
4639 23:55:56.869144 Write leveling (Byte 0): 32 => 32
4640 23:55:56.872249 Write leveling (Byte 1): 30 => 30
4641 23:55:56.875771 DramcWriteLeveling(PI) end<-----
4642 23:55:56.876299
4643 23:55:56.876747 ==
4644 23:55:56.878642 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 23:55:56.885044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 23:55:56.885575 ==
4647 23:55:56.886023 [Gating] SW mode calibration
4648 23:55:56.894833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 23:55:56.898261 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 23:55:56.902051 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 23:55:56.908138 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 23:55:56.911979 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 23:55:56.915073 0 9 12 | B1->B0 | 3030 3131 | 0 1 | (1 0) (1 0)
4654 23:55:56.921796 0 9 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4655 23:55:56.924807 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 23:55:56.928341 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 23:55:56.934591 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 23:55:56.938120 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 23:55:56.941134 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 23:55:56.947824 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 23:55:56.951230 0 10 12 | B1->B0 | 3838 2e2e | 1 1 | (0 0) (0 0)
4662 23:55:56.954237 0 10 16 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
4663 23:55:56.961089 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 23:55:56.964388 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 23:55:56.967495 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 23:55:56.974349 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 23:55:56.977243 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 23:55:56.981051 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:55:56.987474 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:55:56.991085 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4671 23:55:56.994072 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:55:57.000483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:55:57.003923 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:55:57.007338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:55:57.013833 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:55:57.017255 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:55:57.020523 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:55:57.027207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:55:57.030790 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:55:57.033864 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:55:57.039579 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:55:57.043227 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:55:57.049724 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:55:57.052913 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:55:57.056556 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:55:57.063082 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 23:55:57.063549 Total UI for P1: 0, mck2ui 16
4688 23:55:57.066540 best dqsien dly found for B0: ( 0, 13, 14)
4689 23:55:57.069502 Total UI for P1: 0, mck2ui 16
4690 23:55:57.072695 best dqsien dly found for B1: ( 0, 13, 14)
4691 23:55:57.079322 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4692 23:55:57.082966 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4693 23:55:57.083431
4694 23:55:57.086344 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4695 23:55:57.089383 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4696 23:55:57.092909 [Gating] SW calibration Done
4697 23:55:57.093465 ==
4698 23:55:57.095702 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 23:55:57.099609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 23:55:57.100074 ==
4701 23:55:57.102622 RX Vref Scan: 0
4702 23:55:57.103174
4703 23:55:57.103546 RX Vref 0 -> 0, step: 1
4704 23:55:57.103886
4705 23:55:57.105879 RX Delay -230 -> 252, step: 16
4706 23:55:57.112154 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4707 23:55:57.115813 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4708 23:55:57.119049 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4709 23:55:57.122855 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4710 23:55:57.125486 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4711 23:55:57.132478 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4712 23:55:57.135844 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4713 23:55:57.138922 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4714 23:55:57.142034 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4715 23:55:57.148771 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4716 23:55:57.151853 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4717 23:55:57.155186 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4718 23:55:57.158474 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4719 23:55:57.165279 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4720 23:55:57.168820 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4721 23:55:57.172046 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4722 23:55:57.172516 ==
4723 23:55:57.174976 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 23:55:57.178507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 23:55:57.181776 ==
4726 23:55:57.182364 DQS Delay:
4727 23:55:57.182790 DQS0 = 0, DQS1 = 0
4728 23:55:57.184687 DQM Delay:
4729 23:55:57.185243 DQM0 = 41, DQM1 = 35
4730 23:55:57.187908 DQ Delay:
4731 23:55:57.191298 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4732 23:55:57.191789 DQ4 =33, DQ5 =49, DQ6 =57, DQ7 =33
4733 23:55:57.194852 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4734 23:55:57.201394 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4735 23:55:57.201974
4736 23:55:57.202397
4737 23:55:57.202743 ==
4738 23:55:57.204416 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 23:55:57.208021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 23:55:57.208485 ==
4741 23:55:57.208851
4742 23:55:57.209185
4743 23:55:57.210986 TX Vref Scan disable
4744 23:55:57.211446 == TX Byte 0 ==
4745 23:55:57.217650 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4746 23:55:57.221667 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4747 23:55:57.223945 == TX Byte 1 ==
4748 23:55:57.227685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4749 23:55:57.230928 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4750 23:55:57.231393 ==
4751 23:55:57.234062 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 23:55:57.237326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 23:55:57.240599 ==
4754 23:55:57.241154
4755 23:55:57.241518
4756 23:55:57.241857 TX Vref Scan disable
4757 23:55:57.244364 == TX Byte 0 ==
4758 23:55:57.247393 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4759 23:55:57.254360 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4760 23:55:57.254826 == TX Byte 1 ==
4761 23:55:57.257708 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4762 23:55:57.264170 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4763 23:55:57.264654
4764 23:55:57.265135 [DATLAT]
4765 23:55:57.265586 Freq=600, CH1 RK1
4766 23:55:57.266032
4767 23:55:57.267148 DATLAT Default: 0x9
4768 23:55:57.270774 0, 0xFFFF, sum = 0
4769 23:55:57.271416 1, 0xFFFF, sum = 0
4770 23:55:57.274008 2, 0xFFFF, sum = 0
4771 23:55:57.274678 3, 0xFFFF, sum = 0
4772 23:55:57.277417 4, 0xFFFF, sum = 0
4773 23:55:57.278237 5, 0xFFFF, sum = 0
4774 23:55:57.280843 6, 0xFFFF, sum = 0
4775 23:55:57.281404 7, 0xFFFF, sum = 0
4776 23:55:57.283776 8, 0x0, sum = 1
4777 23:55:57.284245 9, 0x0, sum = 2
4778 23:55:57.284620 10, 0x0, sum = 3
4779 23:55:57.287366 11, 0x0, sum = 4
4780 23:55:57.287836 best_step = 9
4781 23:55:57.288208
4782 23:55:57.288549 ==
4783 23:55:57.290265 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 23:55:57.297357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 23:55:57.297838 ==
4786 23:55:57.298258 RX Vref Scan: 0
4787 23:55:57.298620
4788 23:55:57.300273 RX Vref 0 -> 0, step: 1
4789 23:55:57.300737
4790 23:55:57.304042 RX Delay -195 -> 252, step: 8
4791 23:55:57.310685 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4792 23:55:57.313632 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4793 23:55:57.317022 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4794 23:55:57.320469 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4795 23:55:57.323532 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4796 23:55:57.330109 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4797 23:55:57.333491 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4798 23:55:57.336773 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4799 23:55:57.340363 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4800 23:55:57.346987 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4801 23:55:57.349919 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4802 23:55:57.353291 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4803 23:55:57.356303 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4804 23:55:57.363142 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4805 23:55:57.366408 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4806 23:55:57.369837 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4807 23:55:57.370458 ==
4808 23:55:57.372998 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 23:55:57.375944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 23:55:57.379272 ==
4811 23:55:57.379746 DQS Delay:
4812 23:55:57.380228 DQS0 = 0, DQS1 = 0
4813 23:55:57.382705 DQM Delay:
4814 23:55:57.383177 DQM0 = 43, DQM1 = 33
4815 23:55:57.386055 DQ Delay:
4816 23:55:57.389390 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4817 23:55:57.389869 DQ4 =40, DQ5 =56, DQ6 =60, DQ7 =40
4818 23:55:57.393116 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4819 23:55:57.395994 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4820 23:55:57.399218
4821 23:55:57.399708
4822 23:55:57.405849 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4823 23:55:57.409010 CH1 RK1: MR19=808, MR18=2A20
4824 23:55:57.415581 CH1_RK1: MR19=0x808, MR18=0x2A20, DQSOSC=401, MR23=63, INC=163, DEC=108
4825 23:55:57.419040 [RxdqsGatingPostProcess] freq 600
4826 23:55:57.422521 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 23:55:57.425640 Pre-setting of DQS Precalculation
4828 23:55:57.432462 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 23:55:57.438647 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 23:55:57.445864 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 23:55:57.446430
4832 23:55:57.446879
4833 23:55:57.448648 [Calibration Summary] 1200 Mbps
4834 23:55:57.449084 CH 0, Rank 0
4835 23:55:57.451753 SW Impedance : PASS
4836 23:55:57.455086 DUTY Scan : NO K
4837 23:55:57.455517 ZQ Calibration : PASS
4838 23:55:57.458479 Jitter Meter : NO K
4839 23:55:57.461787 CBT Training : PASS
4840 23:55:57.462249 Write leveling : PASS
4841 23:55:57.465340 RX DQS gating : PASS
4842 23:55:57.468473 RX DQ/DQS(RDDQC) : PASS
4843 23:55:57.469074 TX DQ/DQS : PASS
4844 23:55:57.471814 RX DATLAT : PASS
4845 23:55:57.475051 RX DQ/DQS(Engine): PASS
4846 23:55:57.475484 TX OE : NO K
4847 23:55:57.475919 All Pass.
4848 23:55:57.478330
4849 23:55:57.478758 CH 0, Rank 1
4850 23:55:57.481903 SW Impedance : PASS
4851 23:55:57.482369 DUTY Scan : NO K
4852 23:55:57.485247 ZQ Calibration : PASS
4853 23:55:57.488405 Jitter Meter : NO K
4854 23:55:57.489006 CBT Training : PASS
4855 23:55:57.491859 Write leveling : PASS
4856 23:55:57.492292 RX DQS gating : PASS
4857 23:55:57.494664 RX DQ/DQS(RDDQC) : PASS
4858 23:55:57.498099 TX DQ/DQS : PASS
4859 23:55:57.498577 RX DATLAT : PASS
4860 23:55:57.501526 RX DQ/DQS(Engine): PASS
4861 23:55:57.504841 TX OE : NO K
4862 23:55:57.505375 All Pass.
4863 23:55:57.505815
4864 23:55:57.506347 CH 1, Rank 0
4865 23:55:57.508015 SW Impedance : PASS
4866 23:55:57.511091 DUTY Scan : NO K
4867 23:55:57.511521 ZQ Calibration : PASS
4868 23:55:57.514532 Jitter Meter : NO K
4869 23:55:57.518341 CBT Training : PASS
4870 23:55:57.518862 Write leveling : PASS
4871 23:55:57.521152 RX DQS gating : PASS
4872 23:55:57.524706 RX DQ/DQS(RDDQC) : PASS
4873 23:55:57.525272 TX DQ/DQS : PASS
4874 23:55:57.527945 RX DATLAT : PASS
4875 23:55:57.531122 RX DQ/DQS(Engine): PASS
4876 23:55:57.531555 TX OE : NO K
4877 23:55:57.534244 All Pass.
4878 23:55:57.534675
4879 23:55:57.535102 CH 1, Rank 1
4880 23:55:57.537615 SW Impedance : PASS
4881 23:55:57.538145 DUTY Scan : NO K
4882 23:55:57.540859 ZQ Calibration : PASS
4883 23:55:57.544785 Jitter Meter : NO K
4884 23:55:57.545316 CBT Training : PASS
4885 23:55:57.547494 Write leveling : PASS
4886 23:55:57.551226 RX DQS gating : PASS
4887 23:55:57.551700 RX DQ/DQS(RDDQC) : PASS
4888 23:55:57.554235 TX DQ/DQS : PASS
4889 23:55:57.554713 RX DATLAT : PASS
4890 23:55:57.557657 RX DQ/DQS(Engine): PASS
4891 23:55:57.560730 TX OE : NO K
4892 23:55:57.561206 All Pass.
4893 23:55:57.561686
4894 23:55:57.564170 DramC Write-DBI off
4895 23:55:57.567365 PER_BANK_REFRESH: Hybrid Mode
4896 23:55:57.567850 TX_TRACKING: ON
4897 23:55:57.577431 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 23:55:57.580847 [FAST_K] Save calibration result to emmc
4899 23:55:57.584322 dramc_set_vcore_voltage set vcore to 662500
4900 23:55:57.587782 Read voltage for 933, 3
4901 23:55:57.588394 Vio18 = 0
4902 23:55:57.589004 Vcore = 662500
4903 23:55:57.590733 Vdram = 0
4904 23:55:57.591446 Vddq = 0
4905 23:55:57.591889 Vmddr = 0
4906 23:55:57.597481 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 23:55:57.600320 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 23:55:57.604017 MEM_TYPE=3, freq_sel=17
4909 23:55:57.607113 sv_algorithm_assistance_LP4_1600
4910 23:55:57.611037 ============ PULL DRAM RESETB DOWN ============
4911 23:55:57.614389 ========== PULL DRAM RESETB DOWN end =========
4912 23:55:57.620673 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 23:55:57.624218 ===================================
4914 23:55:57.624777 LPDDR4 DRAM CONFIGURATION
4915 23:55:57.627285 ===================================
4916 23:55:57.630193 EX_ROW_EN[0] = 0x0
4917 23:55:57.634357 EX_ROW_EN[1] = 0x0
4918 23:55:57.634972 LP4Y_EN = 0x0
4919 23:55:57.636877 WORK_FSP = 0x0
4920 23:55:57.637339 WL = 0x3
4921 23:55:57.640159 RL = 0x3
4922 23:55:57.640618 BL = 0x2
4923 23:55:57.643600 RPST = 0x0
4924 23:55:57.644067 RD_PRE = 0x0
4925 23:55:57.646669 WR_PRE = 0x1
4926 23:55:57.647130 WR_PST = 0x0
4927 23:55:57.650052 DBI_WR = 0x0
4928 23:55:57.650711 DBI_RD = 0x0
4929 23:55:57.653398 OTF = 0x1
4930 23:55:57.656782 ===================================
4931 23:55:57.659970 ===================================
4932 23:55:57.660434 ANA top config
4933 23:55:57.663278 ===================================
4934 23:55:57.666830 DLL_ASYNC_EN = 0
4935 23:55:57.670258 ALL_SLAVE_EN = 1
4936 23:55:57.673319 NEW_RANK_MODE = 1
4937 23:55:57.674006 DLL_IDLE_MODE = 1
4938 23:55:57.676730 LP45_APHY_COMB_EN = 1
4939 23:55:57.679734 TX_ODT_DIS = 1
4940 23:55:57.682988 NEW_8X_MODE = 1
4941 23:55:57.686133 ===================================
4942 23:55:57.689562 ===================================
4943 23:55:57.692992 data_rate = 1866
4944 23:55:57.696361 CKR = 1
4945 23:55:57.696924 DQ_P2S_RATIO = 8
4946 23:55:57.699639 ===================================
4947 23:55:57.702806 CA_P2S_RATIO = 8
4948 23:55:57.706417 DQ_CA_OPEN = 0
4949 23:55:57.709672 DQ_SEMI_OPEN = 0
4950 23:55:57.713010 CA_SEMI_OPEN = 0
4951 23:55:57.713573 CA_FULL_RATE = 0
4952 23:55:57.716346 DQ_CKDIV4_EN = 1
4953 23:55:57.719276 CA_CKDIV4_EN = 1
4954 23:55:57.722740 CA_PREDIV_EN = 0
4955 23:55:57.726402 PH8_DLY = 0
4956 23:55:57.729369 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 23:55:57.732641 DQ_AAMCK_DIV = 4
4958 23:55:57.733195 CA_AAMCK_DIV = 4
4959 23:55:57.735618 CA_ADMCK_DIV = 4
4960 23:55:57.738980 DQ_TRACK_CA_EN = 0
4961 23:55:57.742214 CA_PICK = 933
4962 23:55:57.745588 CA_MCKIO = 933
4963 23:55:57.748983 MCKIO_SEMI = 0
4964 23:55:57.752041 PLL_FREQ = 3732
4965 23:55:57.752715 DQ_UI_PI_RATIO = 32
4966 23:55:57.755783 CA_UI_PI_RATIO = 0
4967 23:55:57.758909 ===================================
4968 23:55:57.762123 ===================================
4969 23:55:57.765611 memory_type:LPDDR4
4970 23:55:57.769122 GP_NUM : 10
4971 23:55:57.769580 SRAM_EN : 1
4972 23:55:57.771969 MD32_EN : 0
4973 23:55:57.775201 ===================================
4974 23:55:57.778564 [ANA_INIT] >>>>>>>>>>>>>>
4975 23:55:57.778988 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 23:55:57.781992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 23:55:57.785432 ===================================
4978 23:55:57.788171 data_rate = 1866,PCW = 0X8f00
4979 23:55:57.792501 ===================================
4980 23:55:57.794801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 23:55:57.801883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 23:55:57.808540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 23:55:57.811393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 23:55:57.814952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 23:55:57.818057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 23:55:57.821880 [ANA_INIT] flow start
4987 23:55:57.822586 [ANA_INIT] PLL >>>>>>>>
4988 23:55:57.824742 [ANA_INIT] PLL <<<<<<<<
4989 23:55:57.828037 [ANA_INIT] MIDPI >>>>>>>>
4990 23:55:57.831333 [ANA_INIT] MIDPI <<<<<<<<
4991 23:55:57.831757 [ANA_INIT] DLL >>>>>>>>
4992 23:55:57.834646 [ANA_INIT] flow end
4993 23:55:57.838012 ============ LP4 DIFF to SE enter ============
4994 23:55:57.841043 ============ LP4 DIFF to SE exit ============
4995 23:55:57.844668 [ANA_INIT] <<<<<<<<<<<<<
4996 23:55:57.847728 [Flow] Enable top DCM control >>>>>
4997 23:55:57.851033 [Flow] Enable top DCM control <<<<<
4998 23:55:57.854641 Enable DLL master slave shuffle
4999 23:55:57.860631 ==============================================================
5000 23:55:57.861321 Gating Mode config
5001 23:55:57.867582 ==============================================================
5002 23:55:57.868001 Config description:
5003 23:55:57.877100 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 23:55:57.884361 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 23:55:57.890724 SELPH_MODE 0: By rank 1: By Phase
5006 23:55:57.897041 ==============================================================
5007 23:55:57.897607 GAT_TRACK_EN = 1
5008 23:55:57.900721 RX_GATING_MODE = 2
5009 23:55:57.903988 RX_GATING_TRACK_MODE = 2
5010 23:55:57.907362 SELPH_MODE = 1
5011 23:55:57.910411 PICG_EARLY_EN = 1
5012 23:55:57.913786 VALID_LAT_VALUE = 1
5013 23:55:57.920512 ==============================================================
5014 23:55:57.923489 Enter into Gating configuration >>>>
5015 23:55:57.927081 Exit from Gating configuration <<<<
5016 23:55:57.930352 Enter into DVFS_PRE_config >>>>>
5017 23:55:57.940042 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 23:55:57.943346 Exit from DVFS_PRE_config <<<<<
5019 23:55:57.947097 Enter into PICG configuration >>>>
5020 23:55:57.950412 Exit from PICG configuration <<<<
5021 23:55:57.953479 [RX_INPUT] configuration >>>>>
5022 23:55:57.953936 [RX_INPUT] configuration <<<<<
5023 23:55:57.960088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 23:55:57.966766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 23:55:57.973544 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 23:55:57.976702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 23:55:57.983006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 23:55:57.989776 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 23:55:57.993259 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 23:55:58.000081 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 23:55:58.003491 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 23:55:58.006433 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 23:55:58.009245 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 23:55:58.015795 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 23:55:58.019593 ===================================
5036 23:55:58.020152 LPDDR4 DRAM CONFIGURATION
5037 23:55:58.023084 ===================================
5038 23:55:58.026080 EX_ROW_EN[0] = 0x0
5039 23:55:58.029869 EX_ROW_EN[1] = 0x0
5040 23:55:58.030492 LP4Y_EN = 0x0
5041 23:55:58.033001 WORK_FSP = 0x0
5042 23:55:58.033458 WL = 0x3
5043 23:55:58.036072 RL = 0x3
5044 23:55:58.036528 BL = 0x2
5045 23:55:58.039058 RPST = 0x0
5046 23:55:58.039523 RD_PRE = 0x0
5047 23:55:58.042434 WR_PRE = 0x1
5048 23:55:58.042976 WR_PST = 0x0
5049 23:55:58.045627 DBI_WR = 0x0
5050 23:55:58.046089 DBI_RD = 0x0
5051 23:55:58.048845 OTF = 0x1
5052 23:55:58.052179 ===================================
5053 23:55:58.055469 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 23:55:58.058956 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 23:55:58.065675 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 23:55:58.069079 ===================================
5057 23:55:58.069695 LPDDR4 DRAM CONFIGURATION
5058 23:55:58.072640 ===================================
5059 23:55:58.075936 EX_ROW_EN[0] = 0x10
5060 23:55:58.078708 EX_ROW_EN[1] = 0x0
5061 23:55:58.079168 LP4Y_EN = 0x0
5062 23:55:58.082109 WORK_FSP = 0x0
5063 23:55:58.082715 WL = 0x3
5064 23:55:58.085559 RL = 0x3
5065 23:55:58.086131 BL = 0x2
5066 23:55:58.088519 RPST = 0x0
5067 23:55:58.089074 RD_PRE = 0x0
5068 23:55:58.092084 WR_PRE = 0x1
5069 23:55:58.092665 WR_PST = 0x0
5070 23:55:58.095123 DBI_WR = 0x0
5071 23:55:58.095581 DBI_RD = 0x0
5072 23:55:58.098360 OTF = 0x1
5073 23:55:58.102098 ===================================
5074 23:55:58.108693 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 23:55:58.111541 nWR fixed to 30
5076 23:55:58.114826 [ModeRegInit_LP4] CH0 RK0
5077 23:55:58.115297 [ModeRegInit_LP4] CH0 RK1
5078 23:55:58.117983 [ModeRegInit_LP4] CH1 RK0
5079 23:55:58.121562 [ModeRegInit_LP4] CH1 RK1
5080 23:55:58.122119 match AC timing 9
5081 23:55:58.128168 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 23:55:58.131477 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 23:55:58.134650 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 23:55:58.141288 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 23:55:58.144403 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 23:55:58.144863 ==
5087 23:55:58.147870 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 23:55:58.151021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 23:55:58.151489 ==
5090 23:55:58.157414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 23:55:58.164116 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5092 23:55:58.167972 [CA 0] Center 37 (7~68) winsize 62
5093 23:55:58.170738 [CA 1] Center 37 (7~68) winsize 62
5094 23:55:58.174147 [CA 2] Center 34 (4~65) winsize 62
5095 23:55:58.177515 [CA 3] Center 34 (4~65) winsize 62
5096 23:55:58.181256 [CA 4] Center 33 (3~64) winsize 62
5097 23:55:58.184458 [CA 5] Center 33 (3~64) winsize 62
5098 23:55:58.185022
5099 23:55:58.187357 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5100 23:55:58.187821
5101 23:55:58.190765 [CATrainingPosCal] consider 1 rank data
5102 23:55:58.194122 u2DelayCellTimex100 = 270/100 ps
5103 23:55:58.197268 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5104 23:55:58.200517 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5105 23:55:58.204211 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5106 23:55:58.210482 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5107 23:55:58.213717 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5108 23:55:58.216841 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5109 23:55:58.217346
5110 23:55:58.220604 CA PerBit enable=1, Macro0, CA PI delay=33
5111 23:55:58.221161
5112 23:55:58.224042 [CBTSetCACLKResult] CA Dly = 33
5113 23:55:58.224599 CS Dly: 7 (0~38)
5114 23:55:58.224969 ==
5115 23:55:58.227645 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 23:55:58.233280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 23:55:58.233769 ==
5118 23:55:58.236734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 23:55:58.243609 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5120 23:55:58.246915 [CA 0] Center 37 (7~68) winsize 62
5121 23:55:58.250092 [CA 1] Center 37 (7~68) winsize 62
5122 23:55:58.253217 [CA 2] Center 34 (4~65) winsize 62
5123 23:55:58.256724 [CA 3] Center 34 (4~65) winsize 62
5124 23:55:58.259899 [CA 4] Center 33 (3~64) winsize 62
5125 23:55:58.263004 [CA 5] Center 33 (3~63) winsize 61
5126 23:55:58.263471
5127 23:55:58.266514 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5128 23:55:58.266982
5129 23:55:58.270028 [CATrainingPosCal] consider 2 rank data
5130 23:55:58.273256 u2DelayCellTimex100 = 270/100 ps
5131 23:55:58.276488 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5132 23:55:58.283237 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5133 23:55:58.286320 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 23:55:58.289270 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5135 23:55:58.292610 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5136 23:55:58.296309 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5137 23:55:58.296864
5138 23:55:58.299274 CA PerBit enable=1, Macro0, CA PI delay=33
5139 23:55:58.299737
5140 23:55:58.302741 [CBTSetCACLKResult] CA Dly = 33
5141 23:55:58.306289 CS Dly: 7 (0~39)
5142 23:55:58.306746
5143 23:55:58.309286 ----->DramcWriteLeveling(PI) begin...
5144 23:55:58.309845 ==
5145 23:55:58.312476 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 23:55:58.315892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 23:55:58.316355 ==
5148 23:55:58.319318 Write leveling (Byte 0): 32 => 32
5149 23:55:58.322552 Write leveling (Byte 1): 29 => 29
5150 23:55:58.325779 DramcWriteLeveling(PI) end<-----
5151 23:55:58.326383
5152 23:55:58.326754 ==
5153 23:55:58.329334 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 23:55:58.332088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 23:55:58.332593 ==
5156 23:55:58.335575 [Gating] SW mode calibration
5157 23:55:58.342552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 23:55:58.349197 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 23:55:58.351976 0 14 0 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
5160 23:55:58.355413 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5161 23:55:58.362397 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:55:58.365251 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 23:55:58.368263 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 23:55:58.375581 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 23:55:58.378635 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 23:55:58.382069 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
5167 23:55:58.388517 0 15 0 | B1->B0 | 3131 2424 | 1 0 | (0 1) (1 0)
5168 23:55:58.391519 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 23:55:58.395078 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:55:58.401695 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 23:55:58.404763 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 23:55:58.408090 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 23:55:58.414989 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 23:55:58.417786 0 15 28 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
5175 23:55:58.421467 1 0 0 | B1->B0 | 2c2c 4242 | 0 0 | (0 0) (0 0)
5176 23:55:58.427817 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5177 23:55:58.431116 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:55:58.434922 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 23:55:58.441372 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:55:58.444952 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 23:55:58.447855 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 23:55:58.454633 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 23:55:58.457539 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 23:55:58.461054 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 23:55:58.466998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:55:58.470569 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:55:58.477468 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:55:58.480480 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:55:58.483762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:55:58.486882 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:55:58.493731 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:55:58.497071 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:55:58.500336 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:55:58.506985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:55:58.510183 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:55:58.516739 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:55:58.519948 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5198 23:55:58.523507 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5199 23:55:58.529861 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 23:55:58.530454 Total UI for P1: 0, mck2ui 16
5201 23:55:58.533030 best dqsien dly found for B0: ( 1, 2, 26)
5202 23:55:58.539542 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 23:55:58.543465 Total UI for P1: 0, mck2ui 16
5204 23:55:58.546756 best dqsien dly found for B1: ( 1, 2, 30)
5205 23:55:58.549821 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5206 23:55:58.553053 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5207 23:55:58.553649
5208 23:55:58.556293 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5209 23:55:58.559409 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5210 23:55:58.562858 [Gating] SW calibration Done
5211 23:55:58.563319 ==
5212 23:55:58.565929 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 23:55:58.569836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 23:55:58.570477 ==
5215 23:55:58.572958 RX Vref Scan: 0
5216 23:55:58.573527
5217 23:55:58.575968 RX Vref 0 -> 0, step: 1
5218 23:55:58.576436
5219 23:55:58.576801 RX Delay -80 -> 252, step: 8
5220 23:55:58.582776 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5221 23:55:58.586338 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5222 23:55:58.589526 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5223 23:55:58.592927 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5224 23:55:58.596180 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5225 23:55:58.599317 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5226 23:55:58.605817 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5227 23:55:58.609131 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5228 23:55:58.612635 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5229 23:55:58.615649 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5230 23:55:58.618812 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5231 23:55:58.625908 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5232 23:55:58.629062 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5233 23:55:58.632501 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5234 23:55:58.635427 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5235 23:55:58.638754 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5236 23:55:58.642465 ==
5237 23:55:58.645814 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 23:55:58.648883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 23:55:58.649445 ==
5240 23:55:58.649816 DQS Delay:
5241 23:55:58.652598 DQS0 = 0, DQS1 = 0
5242 23:55:58.653183 DQM Delay:
5243 23:55:58.655979 DQM0 = 96, DQM1 = 85
5244 23:55:58.656550 DQ Delay:
5245 23:55:58.658703 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5246 23:55:58.662407 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5247 23:55:58.665424 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5248 23:55:58.668506 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5249 23:55:58.669063
5250 23:55:58.669429
5251 23:55:58.669776 ==
5252 23:55:58.672024 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 23:55:58.675157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 23:55:58.675626 ==
5255 23:55:58.675997
5256 23:55:58.678553
5257 23:55:58.679012 TX Vref Scan disable
5258 23:55:58.682087 == TX Byte 0 ==
5259 23:55:58.685302 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5260 23:55:58.688482 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5261 23:55:58.691802 == TX Byte 1 ==
5262 23:55:58.694805 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5263 23:55:58.698660 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5264 23:55:58.699231 ==
5265 23:55:58.701977 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 23:55:58.708457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 23:55:58.709020 ==
5268 23:55:58.709395
5269 23:55:58.709739
5270 23:55:58.710064 TX Vref Scan disable
5271 23:55:58.712750 == TX Byte 0 ==
5272 23:55:58.715663 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5273 23:55:58.722749 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5274 23:55:58.723307 == TX Byte 1 ==
5275 23:55:58.726274 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5276 23:55:58.732381 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5277 23:55:58.732962
5278 23:55:58.733333 [DATLAT]
5279 23:55:58.733680 Freq=933, CH0 RK0
5280 23:55:58.734017
5281 23:55:58.735688 DATLAT Default: 0xd
5282 23:55:58.736151 0, 0xFFFF, sum = 0
5283 23:55:58.738686 1, 0xFFFF, sum = 0
5284 23:55:58.741983 2, 0xFFFF, sum = 0
5285 23:55:58.742636 3, 0xFFFF, sum = 0
5286 23:55:58.745146 4, 0xFFFF, sum = 0
5287 23:55:58.745617 5, 0xFFFF, sum = 0
5288 23:55:58.748557 6, 0xFFFF, sum = 0
5289 23:55:58.749027 7, 0xFFFF, sum = 0
5290 23:55:58.752691 8, 0xFFFF, sum = 0
5291 23:55:58.753253 9, 0xFFFF, sum = 0
5292 23:55:58.755009 10, 0x0, sum = 1
5293 23:55:58.755481 11, 0x0, sum = 2
5294 23:55:58.758528 12, 0x0, sum = 3
5295 23:55:58.758993 13, 0x0, sum = 4
5296 23:55:58.761624 best_step = 11
5297 23:55:58.762082
5298 23:55:58.762507 ==
5299 23:55:58.765055 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 23:55:58.768844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 23:55:58.769307 ==
5302 23:55:58.769672 RX Vref Scan: 1
5303 23:55:58.770014
5304 23:55:58.771815 RX Vref 0 -> 0, step: 1
5305 23:55:58.772272
5306 23:55:58.774926 RX Delay -61 -> 252, step: 4
5307 23:55:58.775530
5308 23:55:58.778219 Set Vref, RX VrefLevel [Byte0]: 58
5309 23:55:58.781485 [Byte1]: 58
5310 23:55:58.785091
5311 23:55:58.785543 Final RX Vref Byte 0 = 58 to rank0
5312 23:55:58.788703 Final RX Vref Byte 1 = 58 to rank0
5313 23:55:58.791420 Final RX Vref Byte 0 = 58 to rank1
5314 23:55:58.794764 Final RX Vref Byte 1 = 58 to rank1==
5315 23:55:58.797984 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 23:55:58.804846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 23:55:58.805258 ==
5318 23:55:58.805626 DQS Delay:
5319 23:55:58.807791 DQS0 = 0, DQS1 = 0
5320 23:55:58.808178 DQM Delay:
5321 23:55:58.808418 DQM0 = 97, DQM1 = 86
5322 23:55:58.810873 DQ Delay:
5323 23:55:58.814793 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5324 23:55:58.817813 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =108
5325 23:55:58.821415 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =82
5326 23:55:58.824790 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5327 23:55:58.825342
5328 23:55:58.825707
5329 23:55:58.830965 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5330 23:55:58.834306 CH0 RK0: MR19=505, MR18=2B11
5331 23:55:58.841041 CH0_RK0: MR19=0x505, MR18=0x2B11, DQSOSC=408, MR23=63, INC=65, DEC=43
5332 23:55:58.841507
5333 23:55:58.844386 ----->DramcWriteLeveling(PI) begin...
5334 23:55:58.844943 ==
5335 23:55:58.847057 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 23:55:58.850726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 23:55:58.851297 ==
5338 23:55:58.853712 Write leveling (Byte 0): 32 => 32
5339 23:55:58.856833 Write leveling (Byte 1): 30 => 30
5340 23:55:58.860209 DramcWriteLeveling(PI) end<-----
5341 23:55:58.860663
5342 23:55:58.861015 ==
5343 23:55:58.863690 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 23:55:58.870401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 23:55:58.870952 ==
5346 23:55:58.871315 [Gating] SW mode calibration
5347 23:55:58.880068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5348 23:55:58.883375 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5349 23:55:58.889880 0 14 0 | B1->B0 | 3131 3232 | 1 0 | (1 1) (0 0)
5350 23:55:58.893491 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 23:55:58.896861 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 23:55:58.903315 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 23:55:58.906801 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:55:58.910130 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:55:58.916380 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5356 23:55:58.919654 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
5357 23:55:58.924282 0 15 0 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (0 0)
5358 23:55:58.929662 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5359 23:55:58.933317 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:55:58.936049 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:55:58.942512 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:55:58.946141 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 23:55:58.949149 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 23:55:58.956006 0 15 28 | B1->B0 | 2525 3535 | 0 1 | (0 0) (0 0)
5365 23:55:58.959019 1 0 0 | B1->B0 | 4343 4040 | 0 0 | (0 0) (0 0)
5366 23:55:58.962279 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:55:58.968819 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:55:58.972387 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:55:58.975360 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:55:58.982110 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:55:58.985671 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:55:58.988669 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:55:58.995442 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5374 23:55:58.998455 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:55:59.002113 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:55:59.008881 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:55:59.011846 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:55:59.015139 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:55:59.021739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:55:59.025110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:55:59.028350 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:55:59.034797 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:55:59.038390 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:55:59.041705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:55:59.047846 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:55:59.051798 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:55:59.054828 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:55:59.061244 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5389 23:55:59.064363 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 23:55:59.067912 Total UI for P1: 0, mck2ui 16
5391 23:55:59.071146 best dqsien dly found for B0: ( 1, 2, 28)
5392 23:55:59.074782 Total UI for P1: 0, mck2ui 16
5393 23:55:59.077592 best dqsien dly found for B1: ( 1, 2, 28)
5394 23:55:59.080974 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5395 23:55:59.084312 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5396 23:55:59.084862
5397 23:55:59.087608 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5398 23:55:59.090940 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5399 23:55:59.093964 [Gating] SW calibration Done
5400 23:55:59.094557 ==
5401 23:55:59.097559 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 23:55:59.100892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 23:55:59.104198 ==
5404 23:55:59.104609 RX Vref Scan: 0
5405 23:55:59.104940
5406 23:55:59.107150 RX Vref 0 -> 0, step: 1
5407 23:55:59.107561
5408 23:55:59.110487 RX Delay -80 -> 252, step: 8
5409 23:55:59.113854 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5410 23:55:59.117303 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5411 23:55:59.120692 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5412 23:55:59.124100 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5413 23:55:59.127626 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5414 23:55:59.134048 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5415 23:55:59.137062 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5416 23:55:59.140295 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5417 23:55:59.143721 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5418 23:55:59.147312 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5419 23:55:59.153560 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5420 23:55:59.156848 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5421 23:55:59.160198 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5422 23:55:59.163415 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5423 23:55:59.166672 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5424 23:55:59.173409 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5425 23:55:59.173840 ==
5426 23:55:59.176701 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 23:55:59.179996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 23:55:59.180432 ==
5429 23:55:59.180778 DQS Delay:
5430 23:55:59.183493 DQS0 = 0, DQS1 = 0
5431 23:55:59.183904 DQM Delay:
5432 23:55:59.186639 DQM0 = 95, DQM1 = 89
5433 23:55:59.187088 DQ Delay:
5434 23:55:59.190525 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5435 23:55:59.193442 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =107
5436 23:55:59.196909 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5437 23:55:59.200374 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5438 23:55:59.200897
5439 23:55:59.201230
5440 23:55:59.201533 ==
5441 23:55:59.203627 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 23:55:59.206995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 23:55:59.207531 ==
5444 23:55:59.207867
5445 23:55:59.208171
5446 23:55:59.210101 TX Vref Scan disable
5447 23:55:59.213147 == TX Byte 0 ==
5448 23:55:59.216457 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5449 23:55:59.219855 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5450 23:55:59.223603 == TX Byte 1 ==
5451 23:55:59.226337 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5452 23:55:59.229993 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5453 23:55:59.230563 ==
5454 23:55:59.233506 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 23:55:59.239380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 23:55:59.239833 ==
5457 23:55:59.240164
5458 23:55:59.240554
5459 23:55:59.240857 TX Vref Scan disable
5460 23:55:59.243557 == TX Byte 0 ==
5461 23:55:59.247115 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5462 23:55:59.253770 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5463 23:55:59.254431 == TX Byte 1 ==
5464 23:55:59.256763 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5465 23:55:59.263278 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5466 23:55:59.263756
5467 23:55:59.264235 [DATLAT]
5468 23:55:59.264687 Freq=933, CH0 RK1
5469 23:55:59.265146
5470 23:55:59.266547 DATLAT Default: 0xb
5471 23:55:59.270085 0, 0xFFFF, sum = 0
5472 23:55:59.270705 1, 0xFFFF, sum = 0
5473 23:55:59.273494 2, 0xFFFF, sum = 0
5474 23:55:59.273954 3, 0xFFFF, sum = 0
5475 23:55:59.276932 4, 0xFFFF, sum = 0
5476 23:55:59.277552 5, 0xFFFF, sum = 0
5477 23:55:59.280128 6, 0xFFFF, sum = 0
5478 23:55:59.280570 7, 0xFFFF, sum = 0
5479 23:55:59.283853 8, 0xFFFF, sum = 0
5480 23:55:59.284420 9, 0xFFFF, sum = 0
5481 23:55:59.286415 10, 0x0, sum = 1
5482 23:55:59.286908 11, 0x0, sum = 2
5483 23:55:59.289822 12, 0x0, sum = 3
5484 23:55:59.290353 13, 0x0, sum = 4
5485 23:55:59.293142 best_step = 11
5486 23:55:59.293569
5487 23:55:59.294002 ==
5488 23:55:59.296569 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 23:55:59.299812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 23:55:59.300355 ==
5491 23:55:59.300803 RX Vref Scan: 0
5492 23:55:59.301217
5493 23:55:59.303290 RX Vref 0 -> 0, step: 1
5494 23:55:59.303829
5495 23:55:59.306843 RX Delay -61 -> 252, step: 4
5496 23:55:59.313127 iDelay=203, Bit 0, Center 90 (-1 ~ 182) 184
5497 23:55:59.316172 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5498 23:55:59.319363 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5499 23:55:59.323065 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5500 23:55:59.326529 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5501 23:55:59.329542 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5502 23:55:59.335877 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5503 23:55:59.339134 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5504 23:55:59.342437 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5505 23:55:59.345802 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5506 23:55:59.352338 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5507 23:55:59.355402 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5508 23:55:59.358583 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5509 23:55:59.362003 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5510 23:55:59.365324 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5511 23:55:59.371910 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5512 23:55:59.372371 ==
5513 23:55:59.375380 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 23:55:59.378465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 23:55:59.378899 ==
5516 23:55:59.379230 DQS Delay:
5517 23:55:59.382012 DQS0 = 0, DQS1 = 0
5518 23:55:59.382568 DQM Delay:
5519 23:55:59.385203 DQM0 = 95, DQM1 = 88
5520 23:55:59.385727 DQ Delay:
5521 23:55:59.388474 DQ0 =90, DQ1 =96, DQ2 =90, DQ3 =94
5522 23:55:59.391863 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =104
5523 23:55:59.394944 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =82
5524 23:55:59.398398 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5525 23:55:59.398815
5526 23:55:59.399144
5527 23:55:59.408181 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5528 23:55:59.408750 CH0 RK1: MR19=504, MR18=26F7
5529 23:55:59.414946 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5530 23:55:59.418263 [RxdqsGatingPostProcess] freq 933
5531 23:55:59.424839 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5532 23:55:59.428314 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 23:55:59.431355 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 23:55:59.435091 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 23:55:59.438262 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 23:55:59.441260 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 23:55:59.441975 best DQS1 dly(2T, 0.5T) = (0, 10)
5538 23:55:59.444566 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 23:55:59.447714 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5540 23:55:59.450843 Pre-setting of DQS Precalculation
5541 23:55:59.457625 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5542 23:55:59.458234 ==
5543 23:55:59.460794 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 23:55:59.463947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 23:55:59.464412 ==
5546 23:55:59.470744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 23:55:59.477408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5548 23:55:59.480501 [CA 0] Center 37 (7~67) winsize 61
5549 23:55:59.483569 [CA 1] Center 37 (7~68) winsize 62
5550 23:55:59.486754 [CA 2] Center 34 (4~65) winsize 62
5551 23:55:59.490203 [CA 3] Center 33 (3~64) winsize 62
5552 23:55:59.493431 [CA 4] Center 34 (4~65) winsize 62
5553 23:55:59.496886 [CA 5] Center 33 (3~64) winsize 62
5554 23:55:59.497445
5555 23:55:59.500503 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5556 23:55:59.501062
5557 23:55:59.503524 [CATrainingPosCal] consider 1 rank data
5558 23:55:59.507060 u2DelayCellTimex100 = 270/100 ps
5559 23:55:59.510069 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5560 23:55:59.513387 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5561 23:55:59.516383 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 23:55:59.519828 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 23:55:59.526604 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5564 23:55:59.529830 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5565 23:55:59.530450
5566 23:55:59.533446 CA PerBit enable=1, Macro0, CA PI delay=33
5567 23:55:59.534026
5568 23:55:59.536264 [CBTSetCACLKResult] CA Dly = 33
5569 23:55:59.536727 CS Dly: 6 (0~37)
5570 23:55:59.537091 ==
5571 23:55:59.539478 Dram Type= 6, Freq= 0, CH_1, rank 1
5572 23:55:59.546391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 23:55:59.546951 ==
5574 23:55:59.550059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 23:55:59.555814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5576 23:55:59.559184 [CA 0] Center 37 (7~67) winsize 61
5577 23:55:59.562510 [CA 1] Center 37 (7~68) winsize 62
5578 23:55:59.565960 [CA 2] Center 34 (4~65) winsize 62
5579 23:55:59.569302 [CA 3] Center 34 (3~65) winsize 63
5580 23:55:59.572371 [CA 4] Center 34 (4~65) winsize 62
5581 23:55:59.575633 [CA 5] Center 33 (3~64) winsize 62
5582 23:55:59.576123
5583 23:55:59.578872 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5584 23:55:59.579346
5585 23:55:59.582301 [CATrainingPosCal] consider 2 rank data
5586 23:55:59.585991 u2DelayCellTimex100 = 270/100 ps
5587 23:55:59.589049 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5588 23:55:59.592497 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5589 23:55:59.598830 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5590 23:55:59.601967 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5591 23:55:59.605678 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5592 23:55:59.608536 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 23:55:59.608994
5594 23:55:59.611782 CA PerBit enable=1, Macro0, CA PI delay=33
5595 23:55:59.612245
5596 23:55:59.615467 [CBTSetCACLKResult] CA Dly = 33
5597 23:55:59.616063 CS Dly: 7 (0~39)
5598 23:55:59.618414
5599 23:55:59.621796 ----->DramcWriteLeveling(PI) begin...
5600 23:55:59.622643 ==
5601 23:55:59.625041 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 23:55:59.628533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 23:55:59.628991 ==
5604 23:55:59.631795 Write leveling (Byte 0): 26 => 26
5605 23:55:59.635396 Write leveling (Byte 1): 27 => 27
5606 23:55:59.637970 DramcWriteLeveling(PI) end<-----
5607 23:55:59.638469
5608 23:55:59.638836 ==
5609 23:55:59.641958 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 23:55:59.645038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 23:55:59.645457 ==
5612 23:55:59.647930 [Gating] SW mode calibration
5613 23:55:59.654723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5614 23:55:59.661309 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5615 23:55:59.664354 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 23:55:59.667558 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 23:55:59.674521 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 23:55:59.678129 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 23:55:59.681204 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 23:55:59.687736 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5621 23:55:59.690948 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5622 23:55:59.694156 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (0 1) (1 1)
5623 23:55:59.700630 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 23:55:59.704025 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 23:55:59.707420 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 23:55:59.713610 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 23:55:59.717131 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 23:55:59.720325 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 23:55:59.726893 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5630 23:55:59.730582 0 15 28 | B1->B0 | 3434 3b3b | 0 0 | (0 0) (0 0)
5631 23:55:59.733385 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 23:55:59.740064 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 23:55:59.743315 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 23:55:59.746784 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 23:55:59.753499 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:55:59.757188 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5637 23:55:59.760010 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5638 23:55:59.766725 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5639 23:55:59.770079 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5640 23:55:59.773451 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:55:59.780157 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:55:59.782863 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:55:59.786280 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:55:59.793036 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:55:59.796299 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:55:59.802720 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:55:59.806003 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:55:59.809660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:55:59.815984 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:55:59.819076 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:55:59.822401 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:55:59.828871 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:55:59.832050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5654 23:55:59.835711 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 23:55:59.839014 Total UI for P1: 0, mck2ui 16
5656 23:55:59.842230 best dqsien dly found for B0: ( 1, 2, 24)
5657 23:55:59.845229 Total UI for P1: 0, mck2ui 16
5658 23:55:59.849240 best dqsien dly found for B1: ( 1, 2, 24)
5659 23:55:59.852130 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5660 23:55:59.855611 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5661 23:55:59.856178
5662 23:55:59.858552 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5663 23:55:59.865390 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5664 23:55:59.865935 [Gating] SW calibration Done
5665 23:55:59.866358 ==
5666 23:55:59.869175 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 23:55:59.876036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 23:55:59.876605 ==
5669 23:55:59.877013 RX Vref Scan: 0
5670 23:55:59.877476
5671 23:55:59.878534 RX Vref 0 -> 0, step: 1
5672 23:55:59.878999
5673 23:55:59.881676 RX Delay -80 -> 252, step: 8
5674 23:55:59.885569 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5675 23:55:59.888843 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5676 23:55:59.892031 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5677 23:55:59.898855 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5678 23:55:59.901377 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5679 23:55:59.905108 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5680 23:55:59.908585 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5681 23:55:59.911510 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5682 23:55:59.914853 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5683 23:55:59.921290 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5684 23:55:59.924967 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5685 23:55:59.928510 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5686 23:55:59.931135 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5687 23:55:59.934380 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5688 23:55:59.941011 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5689 23:55:59.944223 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5690 23:55:59.944689 ==
5691 23:55:59.947425 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 23:55:59.950799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 23:55:59.951360 ==
5694 23:55:59.954389 DQS Delay:
5695 23:55:59.954962 DQS0 = 0, DQS1 = 0
5696 23:55:59.955334 DQM Delay:
5697 23:55:59.957396 DQM0 = 102, DQM1 = 91
5698 23:55:59.957895 DQ Delay:
5699 23:55:59.960797 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5700 23:55:59.964368 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5701 23:55:59.967370 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5702 23:55:59.970484 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5703 23:55:59.970946
5704 23:55:59.971312
5705 23:55:59.973773 ==
5706 23:55:59.977867 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 23:55:59.981186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 23:55:59.981752 ==
5709 23:55:59.982119
5710 23:55:59.982538
5711 23:55:59.983784 TX Vref Scan disable
5712 23:55:59.984241 == TX Byte 0 ==
5713 23:55:59.990693 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5714 23:55:59.993746 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5715 23:55:59.994364 == TX Byte 1 ==
5716 23:56:00.000280 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5717 23:56:00.003582 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5718 23:56:00.004053 ==
5719 23:56:00.007417 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 23:56:00.010267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 23:56:00.010826 ==
5722 23:56:00.011195
5723 23:56:00.011535
5724 23:56:00.014286 TX Vref Scan disable
5725 23:56:00.016911 == TX Byte 0 ==
5726 23:56:00.020310 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5727 23:56:00.023559 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5728 23:56:00.027103 == TX Byte 1 ==
5729 23:56:00.029730 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5730 23:56:00.033297 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5731 23:56:00.033757
5732 23:56:00.036571 [DATLAT]
5733 23:56:00.037026 Freq=933, CH1 RK0
5734 23:56:00.037390
5735 23:56:00.039975 DATLAT Default: 0xd
5736 23:56:00.040387 0, 0xFFFF, sum = 0
5737 23:56:00.043074 1, 0xFFFF, sum = 0
5738 23:56:00.043492 2, 0xFFFF, sum = 0
5739 23:56:00.046326 3, 0xFFFF, sum = 0
5740 23:56:00.046952 4, 0xFFFF, sum = 0
5741 23:56:00.049606 5, 0xFFFF, sum = 0
5742 23:56:00.050112 6, 0xFFFF, sum = 0
5743 23:56:00.053261 7, 0xFFFF, sum = 0
5744 23:56:00.053760 8, 0xFFFF, sum = 0
5745 23:56:00.056540 9, 0xFFFF, sum = 0
5746 23:56:00.057030 10, 0x0, sum = 1
5747 23:56:00.059337 11, 0x0, sum = 2
5748 23:56:00.059756 12, 0x0, sum = 3
5749 23:56:00.063100 13, 0x0, sum = 4
5750 23:56:00.063847 best_step = 11
5751 23:56:00.064472
5752 23:56:00.064912 ==
5753 23:56:00.066142 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 23:56:00.073181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 23:56:00.073597 ==
5756 23:56:00.073929 RX Vref Scan: 1
5757 23:56:00.074282
5758 23:56:00.076068 RX Vref 0 -> 0, step: 1
5759 23:56:00.076478
5760 23:56:00.079672 RX Delay -61 -> 252, step: 4
5761 23:56:00.080182
5762 23:56:00.082503 Set Vref, RX VrefLevel [Byte0]: 52
5763 23:56:00.085864 [Byte1]: 52
5764 23:56:00.086517
5765 23:56:00.089668 Final RX Vref Byte 0 = 52 to rank0
5766 23:56:00.092770 Final RX Vref Byte 1 = 52 to rank0
5767 23:56:00.096002 Final RX Vref Byte 0 = 52 to rank1
5768 23:56:00.100341 Final RX Vref Byte 1 = 52 to rank1==
5769 23:56:00.102518 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 23:56:00.105757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 23:56:00.106212 ==
5772 23:56:00.109231 DQS Delay:
5773 23:56:00.109643 DQS0 = 0, DQS1 = 0
5774 23:56:00.112560 DQM Delay:
5775 23:56:00.113094 DQM0 = 101, DQM1 = 93
5776 23:56:00.113601 DQ Delay:
5777 23:56:00.115573 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5778 23:56:00.119017 DQ4 =100, DQ5 =112, DQ6 =110, DQ7 =96
5779 23:56:00.122626 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =84
5780 23:56:00.129311 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5781 23:56:00.129826
5782 23:56:00.130157
5783 23:56:00.135446 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5784 23:56:00.139030 CH1 RK0: MR19=505, MR18=1B0B
5785 23:56:00.145345 CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42
5786 23:56:00.145761
5787 23:56:00.148791 ----->DramcWriteLeveling(PI) begin...
5788 23:56:00.149211 ==
5789 23:56:00.152029 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 23:56:00.155698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 23:56:00.156216 ==
5792 23:56:00.158822 Write leveling (Byte 0): 27 => 27
5793 23:56:00.162260 Write leveling (Byte 1): 27 => 27
5794 23:56:00.165440 DramcWriteLeveling(PI) end<-----
5795 23:56:00.165854
5796 23:56:00.166219 ==
5797 23:56:00.168902 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 23:56:00.172324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 23:56:00.172897 ==
5800 23:56:00.175347 [Gating] SW mode calibration
5801 23:56:00.182203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5802 23:56:00.188655 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5803 23:56:00.191497 0 14 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5804 23:56:00.198496 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 23:56:00.201419 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 23:56:00.204841 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 23:56:00.212218 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 23:56:00.214682 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 23:56:00.218080 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5810 23:56:00.224535 0 14 28 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (1 0)
5811 23:56:00.228178 0 15 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
5812 23:56:00.231146 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 23:56:00.237634 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 23:56:00.241392 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 23:56:00.244462 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 23:56:00.251292 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 23:56:00.254252 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5818 23:56:00.257541 0 15 28 | B1->B0 | 3c3c 2424 | 0 0 | (0 0) (0 0)
5819 23:56:00.264144 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (1 1)
5820 23:56:00.267720 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 23:56:00.270659 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 23:56:00.277349 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 23:56:00.280753 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 23:56:00.284219 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 23:56:00.290867 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5826 23:56:00.293689 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5827 23:56:00.297203 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5828 23:56:00.303916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:56:00.307017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:56:00.310473 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:56:00.316854 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:56:00.320162 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:56:00.323611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:56:00.330262 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:56:00.333285 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:56:00.336918 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:56:00.343349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:56:00.346692 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:56:00.349909 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:56:00.356789 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5841 23:56:00.360222 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5842 23:56:00.363114 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 23:56:00.370034 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 23:56:00.370498 Total UI for P1: 0, mck2ui 16
5845 23:56:00.376955 best dqsien dly found for B0: ( 1, 2, 26)
5846 23:56:00.377540 Total UI for P1: 0, mck2ui 16
5847 23:56:00.380224 best dqsien dly found for B1: ( 1, 2, 24)
5848 23:56:00.386364 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5849 23:56:00.389878 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5850 23:56:00.390331
5851 23:56:00.393008 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5852 23:56:00.396099 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5853 23:56:00.399616 [Gating] SW calibration Done
5854 23:56:00.400132 ==
5855 23:56:00.403136 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 23:56:00.406523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 23:56:00.407042 ==
5858 23:56:00.409551 RX Vref Scan: 0
5859 23:56:00.410066
5860 23:56:00.410462 RX Vref 0 -> 0, step: 1
5861 23:56:00.410775
5862 23:56:00.412724 RX Delay -80 -> 252, step: 8
5863 23:56:00.416210 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5864 23:56:00.422565 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5865 23:56:00.426058 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5866 23:56:00.429222 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5867 23:56:00.432854 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5868 23:56:00.436085 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5869 23:56:00.439220 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5870 23:56:00.445620 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5871 23:56:00.449092 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5872 23:56:00.452034 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5873 23:56:00.455360 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5874 23:56:00.458759 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5875 23:56:00.465643 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5876 23:56:00.468617 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5877 23:56:00.471936 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5878 23:56:00.475006 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5879 23:56:00.475445 ==
5880 23:56:00.478245 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 23:56:00.485499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 23:56:00.486014 ==
5883 23:56:00.486409 DQS Delay:
5884 23:56:00.486722 DQS0 = 0, DQS1 = 0
5885 23:56:00.488367 DQM Delay:
5886 23:56:00.488777 DQM0 = 100, DQM1 = 90
5887 23:56:00.491777 DQ Delay:
5888 23:56:00.494632 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5889 23:56:00.498363 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =95
5890 23:56:00.501895 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5891 23:56:00.505099 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5892 23:56:00.505612
5893 23:56:00.505941
5894 23:56:00.506283 ==
5895 23:56:00.508012 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 23:56:00.511763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 23:56:00.512285 ==
5898 23:56:00.512620
5899 23:56:00.512925
5900 23:56:00.514622 TX Vref Scan disable
5901 23:56:00.518022 == TX Byte 0 ==
5902 23:56:00.521023 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5903 23:56:00.524839 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5904 23:56:00.527676 == TX Byte 1 ==
5905 23:56:00.531341 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5906 23:56:00.534520 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5907 23:56:00.534979 ==
5908 23:56:00.537502 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 23:56:00.541247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 23:56:00.544587 ==
5911 23:56:00.545040
5912 23:56:00.545398
5913 23:56:00.545731 TX Vref Scan disable
5914 23:56:00.547941 == TX Byte 0 ==
5915 23:56:00.551255 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5916 23:56:00.557868 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5917 23:56:00.558441 == TX Byte 1 ==
5918 23:56:00.561007 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5919 23:56:00.567449 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5920 23:56:00.567895
5921 23:56:00.568330 [DATLAT]
5922 23:56:00.568743 Freq=933, CH1 RK1
5923 23:56:00.569151
5924 23:56:00.570749 DATLAT Default: 0xb
5925 23:56:00.574257 0, 0xFFFF, sum = 0
5926 23:56:00.574699 1, 0xFFFF, sum = 0
5927 23:56:00.577448 2, 0xFFFF, sum = 0
5928 23:56:00.577898 3, 0xFFFF, sum = 0
5929 23:56:00.580841 4, 0xFFFF, sum = 0
5930 23:56:00.581498 5, 0xFFFF, sum = 0
5931 23:56:00.583888 6, 0xFFFF, sum = 0
5932 23:56:00.584316 7, 0xFFFF, sum = 0
5933 23:56:00.587261 8, 0xFFFF, sum = 0
5934 23:56:00.587706 9, 0xFFFF, sum = 0
5935 23:56:00.590862 10, 0x0, sum = 1
5936 23:56:00.591304 11, 0x0, sum = 2
5937 23:56:00.594257 12, 0x0, sum = 3
5938 23:56:00.594813 13, 0x0, sum = 4
5939 23:56:00.597076 best_step = 11
5940 23:56:00.597524
5941 23:56:00.597963 ==
5942 23:56:00.600639 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 23:56:00.603910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 23:56:00.604453 ==
5945 23:56:00.604901 RX Vref Scan: 0
5946 23:56:00.607320
5947 23:56:00.607847 RX Vref 0 -> 0, step: 1
5948 23:56:00.608294
5949 23:56:00.610491 RX Delay -61 -> 252, step: 4
5950 23:56:00.617170 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5951 23:56:00.620275 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5952 23:56:00.624003 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5953 23:56:00.626923 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5954 23:56:00.630414 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5955 23:56:00.636878 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5956 23:56:00.640105 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5957 23:56:00.643252 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5958 23:56:00.646682 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
5959 23:56:00.650598 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5960 23:56:00.653629 iDelay=207, Bit 10, Center 92 (3 ~ 182) 180
5961 23:56:00.659708 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5962 23:56:00.662897 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5963 23:56:00.666282 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
5964 23:56:00.669613 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5965 23:56:00.676073 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5966 23:56:00.676533 ==
5967 23:56:00.679270 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 23:56:00.682629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 23:56:00.683090 ==
5970 23:56:00.683451 DQS Delay:
5971 23:56:00.686211 DQS0 = 0, DQS1 = 0
5972 23:56:00.686669 DQM Delay:
5973 23:56:00.689174 DQM0 = 101, DQM1 = 93
5974 23:56:00.689605 DQ Delay:
5975 23:56:00.692400 DQ0 =106, DQ1 =94, DQ2 =88, DQ3 =98
5976 23:56:00.696093 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =98
5977 23:56:00.699067 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
5978 23:56:00.702636 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5979 23:56:00.703062
5980 23:56:00.703390
5981 23:56:00.712503 [DQSOSCAuto] RK1, (LSB)MR18= 0x2fb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 421 ps
5982 23:56:00.713036 CH1 RK1: MR19=504, MR18=2FB
5983 23:56:00.719186 CH1_RK1: MR19=0x504, MR18=0x2FB, DQSOSC=421, MR23=63, INC=61, DEC=40
5984 23:56:00.722558 [RxdqsGatingPostProcess] freq 933
5985 23:56:00.729245 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5986 23:56:00.732419 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 23:56:00.735443 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 23:56:00.738848 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 23:56:00.742547 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 23:56:00.745675 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 23:56:00.748906 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 23:56:00.752454 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 23:56:00.755572 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 23:56:00.756205 Pre-setting of DQS Precalculation
5995 23:56:00.762316 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5996 23:56:00.768662 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5997 23:56:00.775382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5998 23:56:00.775934
5999 23:56:00.776294
6000 23:56:00.778452 [Calibration Summary] 1866 Mbps
6001 23:56:00.781731 CH 0, Rank 0
6002 23:56:00.782234 SW Impedance : PASS
6003 23:56:00.785263 DUTY Scan : NO K
6004 23:56:00.788587 ZQ Calibration : PASS
6005 23:56:00.789188 Jitter Meter : NO K
6006 23:56:00.791958 CBT Training : PASS
6007 23:56:00.794936 Write leveling : PASS
6008 23:56:00.795392 RX DQS gating : PASS
6009 23:56:00.798201 RX DQ/DQS(RDDQC) : PASS
6010 23:56:00.798663 TX DQ/DQS : PASS
6011 23:56:00.801939 RX DATLAT : PASS
6012 23:56:00.804807 RX DQ/DQS(Engine): PASS
6013 23:56:00.805267 TX OE : NO K
6014 23:56:00.808465 All Pass.
6015 23:56:00.809018
6016 23:56:00.809379 CH 0, Rank 1
6017 23:56:00.811429 SW Impedance : PASS
6018 23:56:00.811990 DUTY Scan : NO K
6019 23:56:00.814818 ZQ Calibration : PASS
6020 23:56:00.818022 Jitter Meter : NO K
6021 23:56:00.818600 CBT Training : PASS
6022 23:56:00.821322 Write leveling : PASS
6023 23:56:00.824397 RX DQS gating : PASS
6024 23:56:00.824854 RX DQ/DQS(RDDQC) : PASS
6025 23:56:00.828279 TX DQ/DQS : PASS
6026 23:56:00.831110 RX DATLAT : PASS
6027 23:56:00.831678 RX DQ/DQS(Engine): PASS
6028 23:56:00.834666 TX OE : NO K
6029 23:56:00.835132 All Pass.
6030 23:56:00.835497
6031 23:56:00.837797 CH 1, Rank 0
6032 23:56:00.838301 SW Impedance : PASS
6033 23:56:00.841164 DUTY Scan : NO K
6034 23:56:00.844814 ZQ Calibration : PASS
6035 23:56:00.845372 Jitter Meter : NO K
6036 23:56:00.848124 CBT Training : PASS
6037 23:56:00.851116 Write leveling : PASS
6038 23:56:00.851676 RX DQS gating : PASS
6039 23:56:00.854328 RX DQ/DQS(RDDQC) : PASS
6040 23:56:00.857762 TX DQ/DQS : PASS
6041 23:56:00.858375 RX DATLAT : PASS
6042 23:56:00.861245 RX DQ/DQS(Engine): PASS
6043 23:56:00.861798 TX OE : NO K
6044 23:56:00.864543 All Pass.
6045 23:56:00.865103
6046 23:56:00.865492 CH 1, Rank 1
6047 23:56:00.867643 SW Impedance : PASS
6048 23:56:00.870757 DUTY Scan : NO K
6049 23:56:00.871213 ZQ Calibration : PASS
6050 23:56:00.874554 Jitter Meter : NO K
6051 23:56:00.875013 CBT Training : PASS
6052 23:56:00.877468 Write leveling : PASS
6053 23:56:00.880847 RX DQS gating : PASS
6054 23:56:00.881404 RX DQ/DQS(RDDQC) : PASS
6055 23:56:00.883907 TX DQ/DQS : PASS
6056 23:56:00.887318 RX DATLAT : PASS
6057 23:56:00.887813 RX DQ/DQS(Engine): PASS
6058 23:56:00.890647 TX OE : NO K
6059 23:56:00.891127 All Pass.
6060 23:56:00.891495
6061 23:56:00.894123 DramC Write-DBI off
6062 23:56:00.897608 PER_BANK_REFRESH: Hybrid Mode
6063 23:56:00.898232 TX_TRACKING: ON
6064 23:56:00.907200 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6065 23:56:00.910539 [FAST_K] Save calibration result to emmc
6066 23:56:00.913961 dramc_set_vcore_voltage set vcore to 650000
6067 23:56:00.917254 Read voltage for 400, 6
6068 23:56:00.917812 Vio18 = 0
6069 23:56:00.920317 Vcore = 650000
6070 23:56:00.920791 Vdram = 0
6071 23:56:00.921153 Vddq = 0
6072 23:56:00.921489 Vmddr = 0
6073 23:56:00.927097 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6074 23:56:00.933544 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6075 23:56:00.934002 MEM_TYPE=3, freq_sel=20
6076 23:56:00.936834 sv_algorithm_assistance_LP4_800
6077 23:56:00.939850 ============ PULL DRAM RESETB DOWN ============
6078 23:56:00.946724 ========== PULL DRAM RESETB DOWN end =========
6079 23:56:00.949989 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6080 23:56:00.953170 ===================================
6081 23:56:00.956500 LPDDR4 DRAM CONFIGURATION
6082 23:56:00.959724 ===================================
6083 23:56:00.960184 EX_ROW_EN[0] = 0x0
6084 23:56:00.963462 EX_ROW_EN[1] = 0x0
6085 23:56:00.964019 LP4Y_EN = 0x0
6086 23:56:00.966015 WORK_FSP = 0x0
6087 23:56:00.969734 WL = 0x2
6088 23:56:00.970240 RL = 0x2
6089 23:56:00.972955 BL = 0x2
6090 23:56:00.973511 RPST = 0x0
6091 23:56:00.976534 RD_PRE = 0x0
6092 23:56:00.977091 WR_PRE = 0x1
6093 23:56:00.979534 WR_PST = 0x0
6094 23:56:00.979990 DBI_WR = 0x0
6095 23:56:00.983084 DBI_RD = 0x0
6096 23:56:00.983541 OTF = 0x1
6097 23:56:00.986197 ===================================
6098 23:56:00.989279 ===================================
6099 23:56:00.993236 ANA top config
6100 23:56:00.996021 ===================================
6101 23:56:00.996481 DLL_ASYNC_EN = 0
6102 23:56:00.999180 ALL_SLAVE_EN = 1
6103 23:56:01.002396 NEW_RANK_MODE = 1
6104 23:56:01.006016 DLL_IDLE_MODE = 1
6105 23:56:01.009588 LP45_APHY_COMB_EN = 1
6106 23:56:01.010141 TX_ODT_DIS = 1
6107 23:56:01.012674 NEW_8X_MODE = 1
6108 23:56:01.016032 ===================================
6109 23:56:01.019243 ===================================
6110 23:56:01.022334 data_rate = 800
6111 23:56:01.025751 CKR = 1
6112 23:56:01.029021 DQ_P2S_RATIO = 4
6113 23:56:01.032258 ===================================
6114 23:56:01.036300 CA_P2S_RATIO = 4
6115 23:56:01.036812 DQ_CA_OPEN = 0
6116 23:56:01.038815 DQ_SEMI_OPEN = 1
6117 23:56:01.042394 CA_SEMI_OPEN = 1
6118 23:56:01.045537 CA_FULL_RATE = 0
6119 23:56:01.048394 DQ_CKDIV4_EN = 0
6120 23:56:01.051824 CA_CKDIV4_EN = 1
6121 23:56:01.052309 CA_PREDIV_EN = 0
6122 23:56:01.055273 PH8_DLY = 0
6123 23:56:01.058562 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6124 23:56:01.061949 DQ_AAMCK_DIV = 0
6125 23:56:01.065077 CA_AAMCK_DIV = 0
6126 23:56:01.068425 CA_ADMCK_DIV = 4
6127 23:56:01.068837 DQ_TRACK_CA_EN = 0
6128 23:56:01.072065 CA_PICK = 800
6129 23:56:01.075040 CA_MCKIO = 400
6130 23:56:01.078316 MCKIO_SEMI = 400
6131 23:56:01.081577 PLL_FREQ = 3016
6132 23:56:01.085174 DQ_UI_PI_RATIO = 32
6133 23:56:01.088712 CA_UI_PI_RATIO = 32
6134 23:56:01.091282 ===================================
6135 23:56:01.094799 ===================================
6136 23:56:01.095262 memory_type:LPDDR4
6137 23:56:01.098227 GP_NUM : 10
6138 23:56:01.101752 SRAM_EN : 1
6139 23:56:01.102353 MD32_EN : 0
6140 23:56:01.104778 ===================================
6141 23:56:01.108506 [ANA_INIT] >>>>>>>>>>>>>>
6142 23:56:01.111162 <<<<<< [CONFIGURE PHASE]: ANA_TX
6143 23:56:01.115068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6144 23:56:01.117698 ===================================
6145 23:56:01.121428 data_rate = 800,PCW = 0X7400
6146 23:56:01.124540 ===================================
6147 23:56:01.127552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6148 23:56:01.130977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 23:56:01.144147 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 23:56:01.147458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6151 23:56:01.150619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6152 23:56:01.154321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6153 23:56:01.157606 [ANA_INIT] flow start
6154 23:56:01.160648 [ANA_INIT] PLL >>>>>>>>
6155 23:56:01.161105 [ANA_INIT] PLL <<<<<<<<
6156 23:56:01.164612 [ANA_INIT] MIDPI >>>>>>>>
6157 23:56:01.167023 [ANA_INIT] MIDPI <<<<<<<<
6158 23:56:01.170299 [ANA_INIT] DLL >>>>>>>>
6159 23:56:01.170771 [ANA_INIT] flow end
6160 23:56:01.173910 ============ LP4 DIFF to SE enter ============
6161 23:56:01.180226 ============ LP4 DIFF to SE exit ============
6162 23:56:01.180779 [ANA_INIT] <<<<<<<<<<<<<
6163 23:56:01.183634 [Flow] Enable top DCM control >>>>>
6164 23:56:01.187298 [Flow] Enable top DCM control <<<<<
6165 23:56:01.190261 Enable DLL master slave shuffle
6166 23:56:01.196805 ==============================================================
6167 23:56:01.197362 Gating Mode config
6168 23:56:01.203379 ==============================================================
6169 23:56:01.206913 Config description:
6170 23:56:01.216564 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6171 23:56:01.223287 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6172 23:56:01.226202 SELPH_MODE 0: By rank 1: By Phase
6173 23:56:01.232899 ==============================================================
6174 23:56:01.236292 GAT_TRACK_EN = 0
6175 23:56:01.239648 RX_GATING_MODE = 2
6176 23:56:01.242824 RX_GATING_TRACK_MODE = 2
6177 23:56:01.243280 SELPH_MODE = 1
6178 23:56:01.246376 PICG_EARLY_EN = 1
6179 23:56:01.249482 VALID_LAT_VALUE = 1
6180 23:56:01.256206 ==============================================================
6181 23:56:01.259342 Enter into Gating configuration >>>>
6182 23:56:01.262539 Exit from Gating configuration <<<<
6183 23:56:01.265726 Enter into DVFS_PRE_config >>>>>
6184 23:56:01.276269 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6185 23:56:01.279361 Exit from DVFS_PRE_config <<<<<
6186 23:56:01.282137 Enter into PICG configuration >>>>
6187 23:56:01.285620 Exit from PICG configuration <<<<
6188 23:56:01.289233 [RX_INPUT] configuration >>>>>
6189 23:56:01.292189 [RX_INPUT] configuration <<<<<
6190 23:56:01.295728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6191 23:56:01.302226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6192 23:56:01.308863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 23:56:01.315514 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 23:56:01.321831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 23:56:01.328691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 23:56:01.331726 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6197 23:56:01.335156 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6198 23:56:01.338700 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6199 23:56:01.345433 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6200 23:56:01.348729 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6201 23:56:01.351791 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 23:56:01.355120 ===================================
6203 23:56:01.358621 LPDDR4 DRAM CONFIGURATION
6204 23:56:01.361810 ===================================
6205 23:56:01.362321 EX_ROW_EN[0] = 0x0
6206 23:56:01.364889 EX_ROW_EN[1] = 0x0
6207 23:56:01.368079 LP4Y_EN = 0x0
6208 23:56:01.368546 WORK_FSP = 0x0
6209 23:56:01.371785 WL = 0x2
6210 23:56:01.372249 RL = 0x2
6211 23:56:01.374630 BL = 0x2
6212 23:56:01.375093 RPST = 0x0
6213 23:56:01.378039 RD_PRE = 0x0
6214 23:56:01.378533 WR_PRE = 0x1
6215 23:56:01.381392 WR_PST = 0x0
6216 23:56:01.381855 DBI_WR = 0x0
6217 23:56:01.384858 DBI_RD = 0x0
6218 23:56:01.385430 OTF = 0x1
6219 23:56:01.388153 ===================================
6220 23:56:01.391392 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6221 23:56:01.397977 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6222 23:56:01.401553 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 23:56:01.405071 ===================================
6224 23:56:01.407976 LPDDR4 DRAM CONFIGURATION
6225 23:56:01.411154 ===================================
6226 23:56:01.411771 EX_ROW_EN[0] = 0x10
6227 23:56:01.414631 EX_ROW_EN[1] = 0x0
6228 23:56:01.418101 LP4Y_EN = 0x0
6229 23:56:01.418693 WORK_FSP = 0x0
6230 23:56:01.420999 WL = 0x2
6231 23:56:01.421509 RL = 0x2
6232 23:56:01.423941 BL = 0x2
6233 23:56:01.424433 RPST = 0x0
6234 23:56:01.428056 RD_PRE = 0x0
6235 23:56:01.428500 WR_PRE = 0x1
6236 23:56:01.430592 WR_PST = 0x0
6237 23:56:01.431008 DBI_WR = 0x0
6238 23:56:01.433997 DBI_RD = 0x0
6239 23:56:01.434452 OTF = 0x1
6240 23:56:01.437201 ===================================
6241 23:56:01.444069 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6242 23:56:01.448335 nWR fixed to 30
6243 23:56:01.451697 [ModeRegInit_LP4] CH0 RK0
6244 23:56:01.452230 [ModeRegInit_LP4] CH0 RK1
6245 23:56:01.454686 [ModeRegInit_LP4] CH1 RK0
6246 23:56:01.458220 [ModeRegInit_LP4] CH1 RK1
6247 23:56:01.458722 match AC timing 19
6248 23:56:01.464795 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6249 23:56:01.467897 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6250 23:56:01.471118 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6251 23:56:01.477989 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6252 23:56:01.481116 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6253 23:56:01.481613 ==
6254 23:56:01.484326 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 23:56:01.488252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 23:56:01.488810 ==
6257 23:56:01.494156 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 23:56:01.500941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6259 23:56:01.504019 [CA 0] Center 36 (8~64) winsize 57
6260 23:56:01.508007 [CA 1] Center 36 (8~64) winsize 57
6261 23:56:01.511293 [CA 2] Center 36 (8~64) winsize 57
6262 23:56:01.514071 [CA 3] Center 36 (8~64) winsize 57
6263 23:56:01.517345 [CA 4] Center 36 (8~64) winsize 57
6264 23:56:01.520719 [CA 5] Center 36 (8~64) winsize 57
6265 23:56:01.521149
6266 23:56:01.524220 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6267 23:56:01.524747
6268 23:56:01.527302 [CATrainingPosCal] consider 1 rank data
6269 23:56:01.530526 u2DelayCellTimex100 = 270/100 ps
6270 23:56:01.534574 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:56:01.537056 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:56:01.540663 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:56:01.543659 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:56:01.546617 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:56:01.550017 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:56:01.550473
6277 23:56:01.556667 CA PerBit enable=1, Macro0, CA PI delay=36
6278 23:56:01.557096
6279 23:56:01.560019 [CBTSetCACLKResult] CA Dly = 36
6280 23:56:01.560582 CS Dly: 1 (0~32)
6281 23:56:01.561030 ==
6282 23:56:01.563186 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 23:56:01.566564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 23:56:01.566996 ==
6285 23:56:01.573302 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 23:56:01.580076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6287 23:56:01.583559 [CA 0] Center 36 (8~64) winsize 57
6288 23:56:01.586375 [CA 1] Center 36 (8~64) winsize 57
6289 23:56:01.589848 [CA 2] Center 36 (8~64) winsize 57
6290 23:56:01.593257 [CA 3] Center 36 (8~64) winsize 57
6291 23:56:01.596563 [CA 4] Center 36 (8~64) winsize 57
6292 23:56:01.597021 [CA 5] Center 36 (8~64) winsize 57
6293 23:56:01.600166
6294 23:56:01.602936 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6295 23:56:01.603388
6296 23:56:01.606283 [CATrainingPosCal] consider 2 rank data
6297 23:56:01.609979 u2DelayCellTimex100 = 270/100 ps
6298 23:56:01.612641 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:56:01.616189 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:56:01.619174 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:56:01.622663 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:56:01.626327 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 23:56:01.629109 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 23:56:01.629422
6305 23:56:01.635768 CA PerBit enable=1, Macro0, CA PI delay=36
6306 23:56:01.636168
6307 23:56:01.636438 [CBTSetCACLKResult] CA Dly = 36
6308 23:56:01.639005 CS Dly: 1 (0~32)
6309 23:56:01.639294
6310 23:56:01.642097 ----->DramcWriteLeveling(PI) begin...
6311 23:56:01.642426 ==
6312 23:56:01.645345 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:56:01.648933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:56:01.649367 ==
6315 23:56:01.651985 Write leveling (Byte 0): 40 => 8
6316 23:56:01.655456 Write leveling (Byte 1): 32 => 0
6317 23:56:01.658732 DramcWriteLeveling(PI) end<-----
6318 23:56:01.659284
6319 23:56:01.659642 ==
6320 23:56:01.662113 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 23:56:01.668510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 23:56:01.668995 ==
6323 23:56:01.669398 [Gating] SW mode calibration
6324 23:56:01.678098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6325 23:56:01.681750 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6326 23:56:01.684929 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 23:56:01.691507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 23:56:01.694887 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 23:56:01.698333 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 23:56:01.704757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 23:56:01.708217 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 23:56:01.711673 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 23:56:01.718412 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 23:56:01.721364 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 23:56:01.724732 Total UI for P1: 0, mck2ui 16
6336 23:56:01.728127 best dqsien dly found for B0: ( 0, 14, 24)
6337 23:56:01.731058 Total UI for P1: 0, mck2ui 16
6338 23:56:01.734750 best dqsien dly found for B1: ( 0, 14, 24)
6339 23:56:01.737709 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6340 23:56:01.740942 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6341 23:56:01.741497
6342 23:56:01.747908 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 23:56:01.750715 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 23:56:01.751174 [Gating] SW calibration Done
6345 23:56:01.753886 ==
6346 23:56:01.757513 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 23:56:01.760711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 23:56:01.761264 ==
6349 23:56:01.761706 RX Vref Scan: 0
6350 23:56:01.762256
6351 23:56:01.763889 RX Vref 0 -> 0, step: 1
6352 23:56:01.764340
6353 23:56:01.767404 RX Delay -410 -> 252, step: 16
6354 23:56:01.770483 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6355 23:56:01.773647 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6356 23:56:01.780389 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6357 23:56:01.783777 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6358 23:56:01.787435 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6359 23:56:01.793725 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6360 23:56:01.797091 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6361 23:56:01.801155 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6362 23:56:01.803828 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6363 23:56:01.810346 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6364 23:56:01.813517 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6365 23:56:01.816797 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6366 23:56:01.820065 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6367 23:56:01.826631 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6368 23:56:01.830212 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6369 23:56:01.833123 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6370 23:56:01.833770 ==
6371 23:56:01.836491 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 23:56:01.843413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 23:56:01.843978 ==
6374 23:56:01.844469 DQS Delay:
6375 23:56:01.847403 DQS0 = 43, DQS1 = 59
6376 23:56:01.847872 DQM Delay:
6377 23:56:01.848345 DQM0 = 9, DQM1 = 11
6378 23:56:01.849777 DQ Delay:
6379 23:56:01.852961 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6380 23:56:01.853436 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6381 23:56:01.856375 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6382 23:56:01.860050 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6383 23:56:01.860637
6384 23:56:01.862729
6385 23:56:01.863200 ==
6386 23:56:01.866498 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 23:56:01.869244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 23:56:01.869727 ==
6389 23:56:01.870335
6390 23:56:01.870789
6391 23:56:01.872511 TX Vref Scan disable
6392 23:56:01.872982 == TX Byte 0 ==
6393 23:56:01.875963 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 23:56:01.882455 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 23:56:01.882928 == TX Byte 1 ==
6396 23:56:01.885710 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6397 23:56:01.892675 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6398 23:56:01.893335 ==
6399 23:56:01.895683 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 23:56:01.898910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 23:56:01.899384 ==
6402 23:56:01.899857
6403 23:56:01.900302
6404 23:56:01.902287 TX Vref Scan disable
6405 23:56:01.902757 == TX Byte 0 ==
6406 23:56:01.909177 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 23:56:01.912186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 23:56:01.912719 == TX Byte 1 ==
6409 23:56:01.918715 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6410 23:56:01.921980 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6411 23:56:01.922440
6412 23:56:01.922875 [DATLAT]
6413 23:56:01.925301 Freq=400, CH0 RK0
6414 23:56:01.925729
6415 23:56:01.926155 DATLAT Default: 0xf
6416 23:56:01.928620 0, 0xFFFF, sum = 0
6417 23:56:01.929158 1, 0xFFFF, sum = 0
6418 23:56:01.931970 2, 0xFFFF, sum = 0
6419 23:56:01.932509 3, 0xFFFF, sum = 0
6420 23:56:01.935545 4, 0xFFFF, sum = 0
6421 23:56:01.936090 5, 0xFFFF, sum = 0
6422 23:56:01.938522 6, 0xFFFF, sum = 0
6423 23:56:01.941985 7, 0xFFFF, sum = 0
6424 23:56:01.942583 8, 0xFFFF, sum = 0
6425 23:56:01.945195 9, 0xFFFF, sum = 0
6426 23:56:01.945738 10, 0xFFFF, sum = 0
6427 23:56:01.948841 11, 0xFFFF, sum = 0
6428 23:56:01.949377 12, 0xFFFF, sum = 0
6429 23:56:01.951706 13, 0x0, sum = 1
6430 23:56:01.952250 14, 0x0, sum = 2
6431 23:56:01.955086 15, 0x0, sum = 3
6432 23:56:01.955638 16, 0x0, sum = 4
6433 23:56:01.956087 best_step = 14
6434 23:56:01.958701
6435 23:56:01.959244 ==
6436 23:56:01.962007 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 23:56:01.965185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 23:56:01.965722 ==
6439 23:56:01.966192 RX Vref Scan: 1
6440 23:56:01.966606
6441 23:56:01.968391 RX Vref 0 -> 0, step: 1
6442 23:56:01.968819
6443 23:56:01.971676 RX Delay -359 -> 252, step: 8
6444 23:56:01.972106
6445 23:56:01.974617 Set Vref, RX VrefLevel [Byte0]: 58
6446 23:56:01.978031 [Byte1]: 58
6447 23:56:01.982284
6448 23:56:01.982755 Final RX Vref Byte 0 = 58 to rank0
6449 23:56:01.985236 Final RX Vref Byte 1 = 58 to rank0
6450 23:56:01.988751 Final RX Vref Byte 0 = 58 to rank1
6451 23:56:01.992353 Final RX Vref Byte 1 = 58 to rank1==
6452 23:56:01.995581 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 23:56:02.002048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 23:56:02.002690 ==
6455 23:56:02.003061 DQS Delay:
6456 23:56:02.005404 DQS0 = 48, DQS1 = 64
6457 23:56:02.005964 DQM Delay:
6458 23:56:02.006378 DQM0 = 11, DQM1 = 14
6459 23:56:02.008342 DQ Delay:
6460 23:56:02.011937 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6461 23:56:02.015083 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6462 23:56:02.018868 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6463 23:56:02.021722 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6464 23:56:02.022386
6465 23:56:02.022762
6466 23:56:02.028330 [DQSOSCAuto] RK0, (LSB)MR18= 0xb97c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6467 23:56:02.031699 CH0 RK0: MR19=C0C, MR18=B97C
6468 23:56:02.038476 CH0_RK0: MR19=0xC0C, MR18=0xB97C, DQSOSC=386, MR23=63, INC=396, DEC=264
6469 23:56:02.039033 ==
6470 23:56:02.041171 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 23:56:02.044489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 23:56:02.044953 ==
6473 23:56:02.047992 [Gating] SW mode calibration
6474 23:56:02.054853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 23:56:02.061585 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6476 23:56:02.065247 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 23:56:02.067493 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 23:56:02.074288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 23:56:02.077540 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 23:56:02.081246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 23:56:02.087320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 23:56:02.090813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 23:56:02.094279 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 23:56:02.100854 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 23:56:02.104352 Total UI for P1: 0, mck2ui 16
6486 23:56:02.107338 best dqsien dly found for B0: ( 0, 14, 24)
6487 23:56:02.110738 Total UI for P1: 0, mck2ui 16
6488 23:56:02.114070 best dqsien dly found for B1: ( 0, 14, 24)
6489 23:56:02.116917 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6490 23:56:02.120463 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6491 23:56:02.121037
6492 23:56:02.123646 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 23:56:02.126847 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 23:56:02.130540 [Gating] SW calibration Done
6495 23:56:02.130998 ==
6496 23:56:02.133500 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 23:56:02.137072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 23:56:02.140083 ==
6499 23:56:02.140835 RX Vref Scan: 0
6500 23:56:02.141492
6501 23:56:02.143217 RX Vref 0 -> 0, step: 1
6502 23:56:02.143675
6503 23:56:02.146319 RX Delay -410 -> 252, step: 16
6504 23:56:02.149566 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6505 23:56:02.152865 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6506 23:56:02.156863 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6507 23:56:02.163070 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6508 23:56:02.166741 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6509 23:56:02.169578 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6510 23:56:02.172810 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6511 23:56:02.179686 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6512 23:56:02.182518 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6513 23:56:02.185886 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6514 23:56:02.192843 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6515 23:56:02.195923 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6516 23:56:02.199199 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6517 23:56:02.202351 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6518 23:56:02.209269 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6519 23:56:02.212687 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6520 23:56:02.213266 ==
6521 23:56:02.215690 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 23:56:02.219257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 23:56:02.219719 ==
6524 23:56:02.222457 DQS Delay:
6525 23:56:02.222912 DQS0 = 43, DQS1 = 59
6526 23:56:02.226056 DQM Delay:
6527 23:56:02.226655 DQM0 = 10, DQM1 = 13
6528 23:56:02.227023 DQ Delay:
6529 23:56:02.228988 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6530 23:56:02.232081 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6531 23:56:02.235523 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6532 23:56:02.238771 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6533 23:56:02.239332
6534 23:56:02.239696
6535 23:56:02.240030 ==
6536 23:56:02.241956 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 23:56:02.249088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 23:56:02.249653 ==
6539 23:56:02.250018
6540 23:56:02.250405
6541 23:56:02.250729 TX Vref Scan disable
6542 23:56:02.252799 == TX Byte 0 ==
6543 23:56:02.255053 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6544 23:56:02.258339 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6545 23:56:02.262668 == TX Byte 1 ==
6546 23:56:02.265104 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6547 23:56:02.268487 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6548 23:56:02.268948 ==
6549 23:56:02.271461 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 23:56:02.278056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 23:56:02.278578 ==
6552 23:56:02.278945
6553 23:56:02.279280
6554 23:56:02.281237 TX Vref Scan disable
6555 23:56:02.281693 == TX Byte 0 ==
6556 23:56:02.284908 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6557 23:56:02.288514 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6558 23:56:02.291595 == TX Byte 1 ==
6559 23:56:02.294740 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6560 23:56:02.298069 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6561 23:56:02.301468
6562 23:56:02.302039 [DATLAT]
6563 23:56:02.302449 Freq=400, CH0 RK1
6564 23:56:02.302794
6565 23:56:02.304952 DATLAT Default: 0xe
6566 23:56:02.305520 0, 0xFFFF, sum = 0
6567 23:56:02.307763 1, 0xFFFF, sum = 0
6568 23:56:02.308376 2, 0xFFFF, sum = 0
6569 23:56:02.310973 3, 0xFFFF, sum = 0
6570 23:56:02.314467 4, 0xFFFF, sum = 0
6571 23:56:02.315047 5, 0xFFFF, sum = 0
6572 23:56:02.318343 6, 0xFFFF, sum = 0
6573 23:56:02.319031 7, 0xFFFF, sum = 0
6574 23:56:02.321255 8, 0xFFFF, sum = 0
6575 23:56:02.321718 9, 0xFFFF, sum = 0
6576 23:56:02.324095 10, 0xFFFF, sum = 0
6577 23:56:02.324559 11, 0xFFFF, sum = 0
6578 23:56:02.327912 12, 0xFFFF, sum = 0
6579 23:56:02.328474 13, 0x0, sum = 1
6580 23:56:02.330948 14, 0x0, sum = 2
6581 23:56:02.331514 15, 0x0, sum = 3
6582 23:56:02.334115 16, 0x0, sum = 4
6583 23:56:02.334719 best_step = 14
6584 23:56:02.335088
6585 23:56:02.335425 ==
6586 23:56:02.337035 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 23:56:02.343760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 23:56:02.344309 ==
6589 23:56:02.344761 RX Vref Scan: 0
6590 23:56:02.345107
6591 23:56:02.347189 RX Vref 0 -> 0, step: 1
6592 23:56:02.347642
6593 23:56:02.350091 RX Delay -359 -> 252, step: 8
6594 23:56:02.357191 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6595 23:56:02.360668 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6596 23:56:02.363502 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6597 23:56:02.366776 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6598 23:56:02.373357 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6599 23:56:02.376806 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6600 23:56:02.380022 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6601 23:56:02.383534 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6602 23:56:02.389826 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6603 23:56:02.393012 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6604 23:56:02.396317 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6605 23:56:02.403280 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6606 23:56:02.406399 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6607 23:56:02.409764 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6608 23:56:02.413534 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6609 23:56:02.419136 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6610 23:56:02.419687 ==
6611 23:56:02.422757 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 23:56:02.425893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 23:56:02.426388 ==
6614 23:56:02.426757 DQS Delay:
6615 23:56:02.429353 DQS0 = 44, DQS1 = 60
6616 23:56:02.429922 DQM Delay:
6617 23:56:02.432535 DQM0 = 7, DQM1 = 14
6618 23:56:02.432993 DQ Delay:
6619 23:56:02.435669 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6620 23:56:02.439447 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6621 23:56:02.442263 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6622 23:56:02.445688 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6623 23:56:02.446149
6624 23:56:02.446579
6625 23:56:02.452271 [DQSOSCAuto] RK1, (LSB)MR18= 0xac38, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6626 23:56:02.455729 CH0 RK1: MR19=C0C, MR18=AC38
6627 23:56:02.462807 CH0_RK1: MR19=0xC0C, MR18=0xAC38, DQSOSC=388, MR23=63, INC=392, DEC=261
6628 23:56:02.465785 [RxdqsGatingPostProcess] freq 400
6629 23:56:02.472155 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6630 23:56:02.475662 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 23:56:02.476121 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 23:56:02.478852 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 23:56:02.482385 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 23:56:02.485858 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 23:56:02.488905 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 23:56:02.492007 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 23:56:02.495204 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 23:56:02.499129 Pre-setting of DQS Precalculation
6639 23:56:02.505610 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6640 23:56:02.506076 ==
6641 23:56:02.508596 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 23:56:02.511986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 23:56:02.512546 ==
6644 23:56:02.518285 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 23:56:02.524894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6646 23:56:02.528341 [CA 0] Center 36 (8~64) winsize 57
6647 23:56:02.528806 [CA 1] Center 36 (8~64) winsize 57
6648 23:56:02.531554 [CA 2] Center 36 (8~64) winsize 57
6649 23:56:02.534888 [CA 3] Center 36 (8~64) winsize 57
6650 23:56:02.538453 [CA 4] Center 36 (8~64) winsize 57
6651 23:56:02.541689 [CA 5] Center 36 (8~64) winsize 57
6652 23:56:02.542293
6653 23:56:02.544901 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6654 23:56:02.545373
6655 23:56:02.551420 [CATrainingPosCal] consider 1 rank data
6656 23:56:02.551935 u2DelayCellTimex100 = 270/100 ps
6657 23:56:02.557716 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:56:02.561163 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:56:02.564777 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:56:02.567838 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:56:02.570858 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:56:02.574344 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:56:02.574803
6664 23:56:02.577738 CA PerBit enable=1, Macro0, CA PI delay=36
6665 23:56:02.578405
6666 23:56:02.580868 [CBTSetCACLKResult] CA Dly = 36
6667 23:56:02.584302 CS Dly: 1 (0~32)
6668 23:56:02.584759 ==
6669 23:56:02.587273 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 23:56:02.590890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 23:56:02.591307 ==
6672 23:56:02.597323 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 23:56:02.600507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6674 23:56:02.604024 [CA 0] Center 36 (8~64) winsize 57
6675 23:56:02.606976 [CA 1] Center 36 (8~64) winsize 57
6676 23:56:02.610652 [CA 2] Center 36 (8~64) winsize 57
6677 23:56:02.613879 [CA 3] Center 36 (8~64) winsize 57
6678 23:56:02.617275 [CA 4] Center 36 (8~64) winsize 57
6679 23:56:02.620632 [CA 5] Center 36 (8~64) winsize 57
6680 23:56:02.621045
6681 23:56:02.623829 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6682 23:56:02.624243
6683 23:56:02.626961 [CATrainingPosCal] consider 2 rank data
6684 23:56:02.630251 u2DelayCellTimex100 = 270/100 ps
6685 23:56:02.633710 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:56:02.640673 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:56:02.643655 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:56:02.647087 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:56:02.650670 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 23:56:02.653436 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 23:56:02.653851
6692 23:56:02.656702 CA PerBit enable=1, Macro0, CA PI delay=36
6693 23:56:02.657139
6694 23:56:02.660110 [CBTSetCACLKResult] CA Dly = 36
6695 23:56:02.660619 CS Dly: 1 (0~32)
6696 23:56:02.663248
6697 23:56:02.666718 ----->DramcWriteLeveling(PI) begin...
6698 23:56:02.667139 ==
6699 23:56:02.669969 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:56:02.673461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:56:02.673954 ==
6702 23:56:02.676490 Write leveling (Byte 0): 40 => 8
6703 23:56:02.679810 Write leveling (Byte 1): 32 => 0
6704 23:56:02.682989 DramcWriteLeveling(PI) end<-----
6705 23:56:02.683404
6706 23:56:02.683726 ==
6707 23:56:02.686668 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 23:56:02.689798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 23:56:02.690269 ==
6710 23:56:02.692989 [Gating] SW mode calibration
6711 23:56:02.699431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6712 23:56:02.706376 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6713 23:56:02.709848 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 23:56:02.712884 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 23:56:02.719265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 23:56:02.722797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 23:56:02.726269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 23:56:02.732539 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 23:56:02.736173 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 23:56:02.739065 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 23:56:02.745934 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 23:56:02.746412 Total UI for P1: 0, mck2ui 16
6723 23:56:02.753056 best dqsien dly found for B0: ( 0, 14, 24)
6724 23:56:02.753588 Total UI for P1: 0, mck2ui 16
6725 23:56:02.759034 best dqsien dly found for B1: ( 0, 14, 24)
6726 23:56:02.762272 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6727 23:56:02.765554 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6728 23:56:02.765965
6729 23:56:02.769375 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 23:56:02.772159 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 23:56:02.775536 [Gating] SW calibration Done
6732 23:56:02.776050 ==
6733 23:56:02.778585 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 23:56:02.781926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 23:56:02.782394 ==
6736 23:56:02.785102 RX Vref Scan: 0
6737 23:56:02.785514
6738 23:56:02.788416 RX Vref 0 -> 0, step: 1
6739 23:56:02.788826
6740 23:56:02.789149 RX Delay -410 -> 252, step: 16
6741 23:56:02.795416 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6742 23:56:02.798439 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6743 23:56:02.801892 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6744 23:56:02.805375 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6745 23:56:02.811814 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6746 23:56:02.815373 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6747 23:56:02.818216 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6748 23:56:02.824612 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6749 23:56:02.828112 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6750 23:56:02.831778 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6751 23:56:02.834850 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6752 23:56:02.841360 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6753 23:56:02.844273 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6754 23:56:02.847747 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6755 23:56:02.851099 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6756 23:56:02.857529 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6757 23:56:02.857989 ==
6758 23:56:02.861396 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 23:56:02.864414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 23:56:02.864974 ==
6761 23:56:02.865339 DQS Delay:
6762 23:56:02.867827 DQS0 = 43, DQS1 = 51
6763 23:56:02.868386 DQM Delay:
6764 23:56:02.870800 DQM0 = 12, DQM1 = 14
6765 23:56:02.871257 DQ Delay:
6766 23:56:02.873977 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6767 23:56:02.877660 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6768 23:56:02.881253 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6769 23:56:02.884311 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6770 23:56:02.884768
6771 23:56:02.885128
6772 23:56:02.885502 ==
6773 23:56:02.887580 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 23:56:02.891276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 23:56:02.891736 ==
6776 23:56:02.894082
6777 23:56:02.894580
6778 23:56:02.894942 TX Vref Scan disable
6779 23:56:02.897175 == TX Byte 0 ==
6780 23:56:02.900603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 23:56:02.903871 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 23:56:02.907648 == TX Byte 1 ==
6783 23:56:02.910336 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6784 23:56:02.913896 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6785 23:56:02.914482 ==
6786 23:56:02.917195 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 23:56:02.923966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 23:56:02.924535 ==
6789 23:56:02.924904
6790 23:56:02.925242
6791 23:56:02.925566 TX Vref Scan disable
6792 23:56:02.926870 == TX Byte 0 ==
6793 23:56:02.930392 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 23:56:02.933660 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 23:56:02.937112 == TX Byte 1 ==
6796 23:56:02.939943 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6797 23:56:02.943366 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6798 23:56:02.943826
6799 23:56:02.946610 [DATLAT]
6800 23:56:02.947064 Freq=400, CH1 RK0
6801 23:56:02.947424
6802 23:56:02.950108 DATLAT Default: 0xf
6803 23:56:02.950751 0, 0xFFFF, sum = 0
6804 23:56:02.953015 1, 0xFFFF, sum = 0
6805 23:56:02.953507 2, 0xFFFF, sum = 0
6806 23:56:02.956681 3, 0xFFFF, sum = 0
6807 23:56:02.957146 4, 0xFFFF, sum = 0
6808 23:56:02.959576 5, 0xFFFF, sum = 0
6809 23:56:02.960043 6, 0xFFFF, sum = 0
6810 23:56:02.963162 7, 0xFFFF, sum = 0
6811 23:56:02.966655 8, 0xFFFF, sum = 0
6812 23:56:02.967119 9, 0xFFFF, sum = 0
6813 23:56:02.969440 10, 0xFFFF, sum = 0
6814 23:56:02.969895 11, 0xFFFF, sum = 0
6815 23:56:02.973023 12, 0xFFFF, sum = 0
6816 23:56:02.973439 13, 0x0, sum = 1
6817 23:56:02.976248 14, 0x0, sum = 2
6818 23:56:02.976667 15, 0x0, sum = 3
6819 23:56:02.979419 16, 0x0, sum = 4
6820 23:56:02.979872 best_step = 14
6821 23:56:02.980203
6822 23:56:02.980511 ==
6823 23:56:02.982628 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 23:56:02.985728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 23:56:02.989222 ==
6826 23:56:02.989636 RX Vref Scan: 1
6827 23:56:02.989966
6828 23:56:02.992468 RX Vref 0 -> 0, step: 1
6829 23:56:02.992881
6830 23:56:02.995600 RX Delay -343 -> 252, step: 8
6831 23:56:02.996019
6832 23:56:02.999470 Set Vref, RX VrefLevel [Byte0]: 52
6833 23:56:03.002288 [Byte1]: 52
6834 23:56:03.002709
6835 23:56:03.006041 Final RX Vref Byte 0 = 52 to rank0
6836 23:56:03.009118 Final RX Vref Byte 1 = 52 to rank0
6837 23:56:03.012442 Final RX Vref Byte 0 = 52 to rank1
6838 23:56:03.015438 Final RX Vref Byte 1 = 52 to rank1==
6839 23:56:03.018719 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 23:56:03.022445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 23:56:03.022982 ==
6842 23:56:03.025661 DQS Delay:
6843 23:56:03.026078 DQS0 = 44, DQS1 = 56
6844 23:56:03.029000 DQM Delay:
6845 23:56:03.029511 DQM0 = 7, DQM1 = 12
6846 23:56:03.032067 DQ Delay:
6847 23:56:03.032599 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6848 23:56:03.035340 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =0
6849 23:56:03.038446 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6850 23:56:03.041840 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6851 23:56:03.042385
6852 23:56:03.042724
6853 23:56:03.051559 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f66, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6854 23:56:03.054950 CH1 RK0: MR19=C0C, MR18=8F66
6855 23:56:03.061601 CH1_RK0: MR19=0xC0C, MR18=0x8F66, DQSOSC=391, MR23=63, INC=386, DEC=257
6856 23:56:03.062110 ==
6857 23:56:03.064889 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 23:56:03.068184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 23:56:03.068707 ==
6860 23:56:03.071460 [Gating] SW mode calibration
6861 23:56:03.078140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6862 23:56:03.084784 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6863 23:56:03.088100 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 23:56:03.090997 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 23:56:03.097959 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 23:56:03.101122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 23:56:03.104500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 23:56:03.111159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 23:56:03.114776 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 23:56:03.117790 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 23:56:03.124182 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 23:56:03.124847 Total UI for P1: 0, mck2ui 16
6873 23:56:03.127341 best dqsien dly found for B0: ( 0, 14, 24)
6874 23:56:03.131013 Total UI for P1: 0, mck2ui 16
6875 23:56:03.134137 best dqsien dly found for B1: ( 0, 14, 24)
6876 23:56:03.140771 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6877 23:56:03.143832 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6878 23:56:03.144295
6879 23:56:03.147252 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 23:56:03.150731 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 23:56:03.154058 [Gating] SW calibration Done
6882 23:56:03.154548 ==
6883 23:56:03.157002 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 23:56:03.160411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 23:56:03.160875 ==
6886 23:56:03.164066 RX Vref Scan: 0
6887 23:56:03.164620
6888 23:56:03.164987 RX Vref 0 -> 0, step: 1
6889 23:56:03.165323
6890 23:56:03.167067 RX Delay -410 -> 252, step: 16
6891 23:56:03.173559 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6892 23:56:03.177147 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6893 23:56:03.180321 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6894 23:56:03.183454 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6895 23:56:03.189890 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6896 23:56:03.193313 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6897 23:56:03.196591 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6898 23:56:03.200695 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6899 23:56:03.206779 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6900 23:56:03.210201 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6901 23:56:03.213072 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6902 23:56:03.216110 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6903 23:56:03.222742 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6904 23:56:03.226125 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6905 23:56:03.229874 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6906 23:56:03.236206 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6907 23:56:03.236764 ==
6908 23:56:03.239157 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 23:56:03.242502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 23:56:03.242965 ==
6911 23:56:03.243328 DQS Delay:
6912 23:56:03.246212 DQS0 = 43, DQS1 = 51
6913 23:56:03.246723 DQM Delay:
6914 23:56:03.249050 DQM0 = 12, DQM1 = 13
6915 23:56:03.249505 DQ Delay:
6916 23:56:03.253001 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6917 23:56:03.256310 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6918 23:56:03.259148 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6919 23:56:03.262704 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6920 23:56:03.263160
6921 23:56:03.263516
6922 23:56:03.263848 ==
6923 23:56:03.265686 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 23:56:03.268919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 23:56:03.269382 ==
6926 23:56:03.269745
6927 23:56:03.270085
6928 23:56:03.272293 TX Vref Scan disable
6929 23:56:03.272786 == TX Byte 0 ==
6930 23:56:03.278922 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6931 23:56:03.282508 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6932 23:56:03.282972 == TX Byte 1 ==
6933 23:56:03.289039 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6934 23:56:03.292545 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6935 23:56:03.293004 ==
6936 23:56:03.295608 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 23:56:03.299273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 23:56:03.299690 ==
6939 23:56:03.300017
6940 23:56:03.300319
6941 23:56:03.302199 TX Vref Scan disable
6942 23:56:03.305912 == TX Byte 0 ==
6943 23:56:03.309107 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6944 23:56:03.312194 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6945 23:56:03.315470 == TX Byte 1 ==
6946 23:56:03.318750 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6947 23:56:03.321760 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6948 23:56:03.322200
6949 23:56:03.322531 [DATLAT]
6950 23:56:03.325737 Freq=400, CH1 RK1
6951 23:56:03.326293
6952 23:56:03.326626 DATLAT Default: 0xe
6953 23:56:03.329014 0, 0xFFFF, sum = 0
6954 23:56:03.329551 1, 0xFFFF, sum = 0
6955 23:56:03.331794 2, 0xFFFF, sum = 0
6956 23:56:03.335433 3, 0xFFFF, sum = 0
6957 23:56:03.336139 4, 0xFFFF, sum = 0
6958 23:56:03.338298 5, 0xFFFF, sum = 0
6959 23:56:03.338860 6, 0xFFFF, sum = 0
6960 23:56:03.341733 7, 0xFFFF, sum = 0
6961 23:56:03.342239 8, 0xFFFF, sum = 0
6962 23:56:03.344878 9, 0xFFFF, sum = 0
6963 23:56:03.345346 10, 0xFFFF, sum = 0
6964 23:56:03.348115 11, 0xFFFF, sum = 0
6965 23:56:03.348582 12, 0xFFFF, sum = 0
6966 23:56:03.351535 13, 0x0, sum = 1
6967 23:56:03.352051 14, 0x0, sum = 2
6968 23:56:03.354699 15, 0x0, sum = 3
6969 23:56:03.355167 16, 0x0, sum = 4
6970 23:56:03.358132 best_step = 14
6971 23:56:03.358635
6972 23:56:03.359002 ==
6973 23:56:03.361222 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 23:56:03.365029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 23:56:03.365548 ==
6976 23:56:03.368027 RX Vref Scan: 0
6977 23:56:03.368543
6978 23:56:03.368873 RX Vref 0 -> 0, step: 1
6979 23:56:03.369183
6980 23:56:03.371011 RX Delay -343 -> 252, step: 8
6981 23:56:03.379133 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6982 23:56:03.382087 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6983 23:56:03.385527 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6984 23:56:03.392281 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6985 23:56:03.395518 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6986 23:56:03.399075 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6987 23:56:03.402356 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6988 23:56:03.409064 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6989 23:56:03.411867 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6990 23:56:03.415852 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6991 23:56:03.418735 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6992 23:56:03.425374 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6993 23:56:03.428738 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6994 23:56:03.432256 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6995 23:56:03.435546 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6996 23:56:03.442066 iDelay=225, Bit 15, Center -36 (-279 ~ 208) 488
6997 23:56:03.442642 ==
6998 23:56:03.445138 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 23:56:03.448551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 23:56:03.449128 ==
7001 23:56:03.449499 DQS Delay:
7002 23:56:03.451893 DQS0 = 44, DQS1 = 56
7003 23:56:03.452452 DQM Delay:
7004 23:56:03.455011 DQM0 = 8, DQM1 = 10
7005 23:56:03.455467 DQ Delay:
7006 23:56:03.458466 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7007 23:56:03.462083 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7008 23:56:03.465384 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7009 23:56:03.467939 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7010 23:56:03.468408
7011 23:56:03.468767
7012 23:56:03.474512 [DQSOSCAuto] RK1, (LSB)MR18= 0x6253, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7013 23:56:03.478155 CH1 RK1: MR19=C0C, MR18=6253
7014 23:56:03.484450 CH1_RK1: MR19=0xC0C, MR18=0x6253, DQSOSC=397, MR23=63, INC=374, DEC=249
7015 23:56:03.488274 [RxdqsGatingPostProcess] freq 400
7016 23:56:03.495081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7017 23:56:03.497894 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 23:56:03.501407 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 23:56:03.504463 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 23:56:03.507949 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 23:56:03.508508 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 23:56:03.510935 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 23:56:03.514790 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 23:56:03.517788 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 23:56:03.521326 Pre-setting of DQS Precalculation
7026 23:56:03.527275 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7027 23:56:03.534345 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7028 23:56:03.540845 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7029 23:56:03.541368
7030 23:56:03.541726
7031 23:56:03.543912 [Calibration Summary] 800 Mbps
7032 23:56:03.544369 CH 0, Rank 0
7033 23:56:03.547034 SW Impedance : PASS
7034 23:56:03.550527 DUTY Scan : NO K
7035 23:56:03.551005 ZQ Calibration : PASS
7036 23:56:03.553555 Jitter Meter : NO K
7037 23:56:03.557333 CBT Training : PASS
7038 23:56:03.557918 Write leveling : PASS
7039 23:56:03.560510 RX DQS gating : PASS
7040 23:56:03.564020 RX DQ/DQS(RDDQC) : PASS
7041 23:56:03.564574 TX DQ/DQS : PASS
7042 23:56:03.566739 RX DATLAT : PASS
7043 23:56:03.570259 RX DQ/DQS(Engine): PASS
7044 23:56:03.570713 TX OE : NO K
7045 23:56:03.573493 All Pass.
7046 23:56:03.573947
7047 23:56:03.574341 CH 0, Rank 1
7048 23:56:03.576951 SW Impedance : PASS
7049 23:56:03.577407 DUTY Scan : NO K
7050 23:56:03.579892 ZQ Calibration : PASS
7051 23:56:03.583149 Jitter Meter : NO K
7052 23:56:03.583632 CBT Training : PASS
7053 23:56:03.586790 Write leveling : NO K
7054 23:56:03.589893 RX DQS gating : PASS
7055 23:56:03.590346 RX DQ/DQS(RDDQC) : PASS
7056 23:56:03.593541 TX DQ/DQS : PASS
7057 23:56:03.596830 RX DATLAT : PASS
7058 23:56:03.597399 RX DQ/DQS(Engine): PASS
7059 23:56:03.599835 TX OE : NO K
7060 23:56:03.600251 All Pass.
7061 23:56:03.600578
7062 23:56:03.602958 CH 1, Rank 0
7063 23:56:03.603371 SW Impedance : PASS
7064 23:56:03.606302 DUTY Scan : NO K
7065 23:56:03.610030 ZQ Calibration : PASS
7066 23:56:03.610583 Jitter Meter : NO K
7067 23:56:03.613090 CBT Training : PASS
7068 23:56:03.616337 Write leveling : PASS
7069 23:56:03.616881 RX DQS gating : PASS
7070 23:56:03.619459 RX DQ/DQS(RDDQC) : PASS
7071 23:56:03.619871 TX DQ/DQS : PASS
7072 23:56:03.622756 RX DATLAT : PASS
7073 23:56:03.626316 RX DQ/DQS(Engine): PASS
7074 23:56:03.626949 TX OE : NO K
7075 23:56:03.629618 All Pass.
7076 23:56:03.630131
7077 23:56:03.630497 CH 1, Rank 1
7078 23:56:03.633487 SW Impedance : PASS
7079 23:56:03.633999 DUTY Scan : NO K
7080 23:56:03.636736 ZQ Calibration : PASS
7081 23:56:03.639336 Jitter Meter : NO K
7082 23:56:03.639747 CBT Training : PASS
7083 23:56:03.642902 Write leveling : NO K
7084 23:56:03.646492 RX DQS gating : PASS
7085 23:56:03.647007 RX DQ/DQS(RDDQC) : PASS
7086 23:56:03.649367 TX DQ/DQS : PASS
7087 23:56:03.652870 RX DATLAT : PASS
7088 23:56:03.653382 RX DQ/DQS(Engine): PASS
7089 23:56:03.655736 TX OE : NO K
7090 23:56:03.656151 All Pass.
7091 23:56:03.656476
7092 23:56:03.659378 DramC Write-DBI off
7093 23:56:03.662112 PER_BANK_REFRESH: Hybrid Mode
7094 23:56:03.662584 TX_TRACKING: ON
7095 23:56:03.672596 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7096 23:56:03.675639 [FAST_K] Save calibration result to emmc
7097 23:56:03.679057 dramc_set_vcore_voltage set vcore to 725000
7098 23:56:03.682072 Read voltage for 1600, 0
7099 23:56:03.682516 Vio18 = 0
7100 23:56:03.682846 Vcore = 725000
7101 23:56:03.685519 Vdram = 0
7102 23:56:03.685929 Vddq = 0
7103 23:56:03.686302 Vmddr = 0
7104 23:56:03.692404 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7105 23:56:03.695291 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7106 23:56:03.698664 MEM_TYPE=3, freq_sel=13
7107 23:56:03.702062 sv_algorithm_assistance_LP4_3733
7108 23:56:03.705344 ============ PULL DRAM RESETB DOWN ============
7109 23:56:03.712157 ========== PULL DRAM RESETB DOWN end =========
7110 23:56:03.716101 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7111 23:56:03.718605 ===================================
7112 23:56:03.722259 LPDDR4 DRAM CONFIGURATION
7113 23:56:03.725424 ===================================
7114 23:56:03.725942 EX_ROW_EN[0] = 0x0
7115 23:56:03.728773 EX_ROW_EN[1] = 0x0
7116 23:56:03.729300 LP4Y_EN = 0x0
7117 23:56:03.731864 WORK_FSP = 0x1
7118 23:56:03.732275 WL = 0x5
7119 23:56:03.735379 RL = 0x5
7120 23:56:03.735929 BL = 0x2
7121 23:56:03.738348 RPST = 0x0
7122 23:56:03.738759 RD_PRE = 0x0
7123 23:56:03.741953 WR_PRE = 0x1
7124 23:56:03.744904 WR_PST = 0x1
7125 23:56:03.745317 DBI_WR = 0x0
7126 23:56:03.748628 DBI_RD = 0x0
7127 23:56:03.749042 OTF = 0x1
7128 23:56:03.751536 ===================================
7129 23:56:03.754738 ===================================
7130 23:56:03.758113 ANA top config
7131 23:56:03.761636 ===================================
7132 23:56:03.762064 DLL_ASYNC_EN = 0
7133 23:56:03.764790 ALL_SLAVE_EN = 0
7134 23:56:03.767962 NEW_RANK_MODE = 1
7135 23:56:03.771176 DLL_IDLE_MODE = 1
7136 23:56:03.771636 LP45_APHY_COMB_EN = 1
7137 23:56:03.774444 TX_ODT_DIS = 0
7138 23:56:03.777834 NEW_8X_MODE = 1
7139 23:56:03.781377 ===================================
7140 23:56:03.784424 ===================================
7141 23:56:03.787853 data_rate = 3200
7142 23:56:03.790948 CKR = 1
7143 23:56:03.794553 DQ_P2S_RATIO = 8
7144 23:56:03.797477 ===================================
7145 23:56:03.797899 CA_P2S_RATIO = 8
7146 23:56:03.800716 DQ_CA_OPEN = 0
7147 23:56:03.804103 DQ_SEMI_OPEN = 0
7148 23:56:03.807731 CA_SEMI_OPEN = 0
7149 23:56:03.810757 CA_FULL_RATE = 0
7150 23:56:03.813962 DQ_CKDIV4_EN = 0
7151 23:56:03.814404 CA_CKDIV4_EN = 0
7152 23:56:03.817571 CA_PREDIV_EN = 0
7153 23:56:03.820535 PH8_DLY = 12
7154 23:56:03.824051 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7155 23:56:03.827103 DQ_AAMCK_DIV = 4
7156 23:56:03.830485 CA_AAMCK_DIV = 4
7157 23:56:03.833683 CA_ADMCK_DIV = 4
7158 23:56:03.834093 DQ_TRACK_CA_EN = 0
7159 23:56:03.837241 CA_PICK = 1600
7160 23:56:03.840228 CA_MCKIO = 1600
7161 23:56:03.843446 MCKIO_SEMI = 0
7162 23:56:03.846784 PLL_FREQ = 3068
7163 23:56:03.850041 DQ_UI_PI_RATIO = 32
7164 23:56:03.853220 CA_UI_PI_RATIO = 0
7165 23:56:03.857007 ===================================
7166 23:56:03.860172 ===================================
7167 23:56:03.860816 memory_type:LPDDR4
7168 23:56:03.863614 GP_NUM : 10
7169 23:56:03.866666 SRAM_EN : 1
7170 23:56:03.867216 MD32_EN : 0
7171 23:56:03.869812 ===================================
7172 23:56:03.873402 [ANA_INIT] >>>>>>>>>>>>>>
7173 23:56:03.876344 <<<<<< [CONFIGURE PHASE]: ANA_TX
7174 23:56:03.879521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7175 23:56:03.883373 ===================================
7176 23:56:03.886233 data_rate = 3200,PCW = 0X7600
7177 23:56:03.890078 ===================================
7178 23:56:03.893130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7179 23:56:03.896037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 23:56:03.903357 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 23:56:03.909638 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7182 23:56:03.912614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7183 23:56:03.916137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7184 23:56:03.916696 [ANA_INIT] flow start
7185 23:56:03.919411 [ANA_INIT] PLL >>>>>>>>
7186 23:56:03.922430 [ANA_INIT] PLL <<<<<<<<
7187 23:56:03.922885 [ANA_INIT] MIDPI >>>>>>>>
7188 23:56:03.925960 [ANA_INIT] MIDPI <<<<<<<<
7189 23:56:03.928942 [ANA_INIT] DLL >>>>>>>>
7190 23:56:03.929396 [ANA_INIT] DLL <<<<<<<<
7191 23:56:03.932535 [ANA_INIT] flow end
7192 23:56:03.935664 ============ LP4 DIFF to SE enter ============
7193 23:56:03.942569 ============ LP4 DIFF to SE exit ============
7194 23:56:03.943081 [ANA_INIT] <<<<<<<<<<<<<
7195 23:56:03.945495 [Flow] Enable top DCM control >>>>>
7196 23:56:03.948762 [Flow] Enable top DCM control <<<<<
7197 23:56:03.951921 Enable DLL master slave shuffle
7198 23:56:03.958737 ==============================================================
7199 23:56:03.959272 Gating Mode config
7200 23:56:03.965160 ==============================================================
7201 23:56:03.968384 Config description:
7202 23:56:03.978880 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7203 23:56:03.985004 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7204 23:56:03.988452 SELPH_MODE 0: By rank 1: By Phase
7205 23:56:03.995161 ==============================================================
7206 23:56:03.998080 GAT_TRACK_EN = 1
7207 23:56:04.001436 RX_GATING_MODE = 2
7208 23:56:04.001987 RX_GATING_TRACK_MODE = 2
7209 23:56:04.004545 SELPH_MODE = 1
7210 23:56:04.007807 PICG_EARLY_EN = 1
7211 23:56:04.010894 VALID_LAT_VALUE = 1
7212 23:56:04.017938 ==============================================================
7213 23:56:04.021750 Enter into Gating configuration >>>>
7214 23:56:04.024238 Exit from Gating configuration <<<<
7215 23:56:04.028067 Enter into DVFS_PRE_config >>>>>
7216 23:56:04.037581 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7217 23:56:04.040840 Exit from DVFS_PRE_config <<<<<
7218 23:56:04.044481 Enter into PICG configuration >>>>
7219 23:56:04.047360 Exit from PICG configuration <<<<
7220 23:56:04.050842 [RX_INPUT] configuration >>>>>
7221 23:56:04.054277 [RX_INPUT] configuration <<<<<
7222 23:56:04.057364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7223 23:56:04.064214 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7224 23:56:04.070803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 23:56:04.077054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 23:56:04.083944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 23:56:04.090096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 23:56:04.093664 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7229 23:56:04.097098 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7230 23:56:04.100604 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7231 23:56:04.106756 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7232 23:56:04.110467 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7233 23:56:04.113271 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 23:56:04.116702 ===================================
7235 23:56:04.119920 LPDDR4 DRAM CONFIGURATION
7236 23:56:04.123580 ===================================
7237 23:56:04.124191 EX_ROW_EN[0] = 0x0
7238 23:56:04.126296 EX_ROW_EN[1] = 0x0
7239 23:56:04.129551 LP4Y_EN = 0x0
7240 23:56:04.130006 WORK_FSP = 0x1
7241 23:56:04.133408 WL = 0x5
7242 23:56:04.133971 RL = 0x5
7243 23:56:04.136675 BL = 0x2
7244 23:56:04.137231 RPST = 0x0
7245 23:56:04.139823 RD_PRE = 0x0
7246 23:56:04.140377 WR_PRE = 0x1
7247 23:56:04.143096 WR_PST = 0x1
7248 23:56:04.143553 DBI_WR = 0x0
7249 23:56:04.146600 DBI_RD = 0x0
7250 23:56:04.147160 OTF = 0x1
7251 23:56:04.149288 ===================================
7252 23:56:04.152814 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7253 23:56:04.159288 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7254 23:56:04.162980 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 23:56:04.165909 ===================================
7256 23:56:04.169466 LPDDR4 DRAM CONFIGURATION
7257 23:56:04.172301 ===================================
7258 23:56:04.172762 EX_ROW_EN[0] = 0x10
7259 23:56:04.175914 EX_ROW_EN[1] = 0x0
7260 23:56:04.179550 LP4Y_EN = 0x0
7261 23:56:04.180104 WORK_FSP = 0x1
7262 23:56:04.182827 WL = 0x5
7263 23:56:04.183381 RL = 0x5
7264 23:56:04.185866 BL = 0x2
7265 23:56:04.186578 RPST = 0x0
7266 23:56:04.189270 RD_PRE = 0x0
7267 23:56:04.189843 WR_PRE = 0x1
7268 23:56:04.192178 WR_PST = 0x1
7269 23:56:04.192639 DBI_WR = 0x0
7270 23:56:04.195727 DBI_RD = 0x0
7271 23:56:04.196285 OTF = 0x1
7272 23:56:04.198862 ===================================
7273 23:56:04.205519 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7274 23:56:04.206151 ==
7275 23:56:04.209262 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 23:56:04.212416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 23:56:04.215366 ==
7278 23:56:04.215827 [Duty_Offset_Calibration]
7279 23:56:04.219047 B0:1 B1:-1 CA:0
7280 23:56:04.219666
7281 23:56:04.222478 [DutyScan_Calibration_Flow] k_type=0
7282 23:56:04.231213
7283 23:56:04.231768 ==CLK 0==
7284 23:56:04.234465 Final CLK duty delay cell = 0
7285 23:56:04.237812 [0] MAX Duty = 5093%(X100), DQS PI = 20
7286 23:56:04.241202 [0] MIN Duty = 4907%(X100), DQS PI = 4
7287 23:56:04.241762 [0] AVG Duty = 5000%(X100)
7288 23:56:04.244761
7289 23:56:04.247791 CH0 CLK Duty spec in!! Max-Min= 186%
7290 23:56:04.250823 [DutyScan_Calibration_Flow] ====Done====
7291 23:56:04.251297
7292 23:56:04.254583 [DutyScan_Calibration_Flow] k_type=1
7293 23:56:04.269982
7294 23:56:04.270436 ==DQS 0 ==
7295 23:56:04.273098 Final DQS duty delay cell = -4
7296 23:56:04.276569 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7297 23:56:04.279823 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7298 23:56:04.283101 [-4] AVG Duty = 4906%(X100)
7299 23:56:04.283516
7300 23:56:04.283843 ==DQS 1 ==
7301 23:56:04.286399 Final DQS duty delay cell = 0
7302 23:56:04.289912 [0] MAX Duty = 5156%(X100), DQS PI = 2
7303 23:56:04.292780 [0] MIN Duty = 5000%(X100), DQS PI = 20
7304 23:56:04.296298 [0] AVG Duty = 5078%(X100)
7305 23:56:04.296710
7306 23:56:04.299655 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7307 23:56:04.300094
7308 23:56:04.303116 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7309 23:56:04.305999 [DutyScan_Calibration_Flow] ====Done====
7310 23:56:04.306464
7311 23:56:04.309267 [DutyScan_Calibration_Flow] k_type=3
7312 23:56:04.327844
7313 23:56:04.328345 ==DQM 0 ==
7314 23:56:04.330901 Final DQM duty delay cell = 0
7315 23:56:04.334044 [0] MAX Duty = 5093%(X100), DQS PI = 18
7316 23:56:04.337663 [0] MIN Duty = 4907%(X100), DQS PI = 8
7317 23:56:04.340909 [0] AVG Duty = 5000%(X100)
7318 23:56:04.341462
7319 23:56:04.341830 ==DQM 1 ==
7320 23:56:04.343931 Final DQM duty delay cell = 0
7321 23:56:04.347267 [0] MAX Duty = 5000%(X100), DQS PI = 4
7322 23:56:04.350647 [0] MIN Duty = 4813%(X100), DQS PI = 20
7323 23:56:04.353987 [0] AVG Duty = 4906%(X100)
7324 23:56:04.354595
7325 23:56:04.357265 CH0 DQM 0 Duty spec in!! Max-Min= 186%
7326 23:56:04.357736
7327 23:56:04.360461 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7328 23:56:04.363872 [DutyScan_Calibration_Flow] ====Done====
7329 23:56:04.364423
7330 23:56:04.367173 [DutyScan_Calibration_Flow] k_type=2
7331 23:56:04.384033
7332 23:56:04.384606 ==DQ 0 ==
7333 23:56:04.387226 Final DQ duty delay cell = -4
7334 23:56:04.390641 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7335 23:56:04.393666 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7336 23:56:04.397041 [-4] AVG Duty = 4953%(X100)
7337 23:56:04.397538
7338 23:56:04.398081 ==DQ 1 ==
7339 23:56:04.400502 Final DQ duty delay cell = 0
7340 23:56:04.403784 [0] MAX Duty = 5125%(X100), DQS PI = 4
7341 23:56:04.407369 [0] MIN Duty = 5000%(X100), DQS PI = 36
7342 23:56:04.410622 [0] AVG Duty = 5062%(X100)
7343 23:56:04.411159
7344 23:56:04.413717 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7345 23:56:04.414316
7346 23:56:04.416963 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7347 23:56:04.420421 [DutyScan_Calibration_Flow] ====Done====
7348 23:56:04.420986 ==
7349 23:56:04.423604 Dram Type= 6, Freq= 0, CH_1, rank 0
7350 23:56:04.427024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 23:56:04.427487 ==
7352 23:56:04.430118 [Duty_Offset_Calibration]
7353 23:56:04.430712 B0:-1 B1:1 CA:2
7354 23:56:04.431076
7355 23:56:04.433546 [DutyScan_Calibration_Flow] k_type=0
7356 23:56:04.444647
7357 23:56:04.445224 ==CLK 0==
7358 23:56:04.447581 Final CLK duty delay cell = 0
7359 23:56:04.450923 [0] MAX Duty = 5187%(X100), DQS PI = 22
7360 23:56:04.454765 [0] MIN Duty = 4969%(X100), DQS PI = 0
7361 23:56:04.457977 [0] AVG Duty = 5078%(X100)
7362 23:56:04.458556
7363 23:56:04.460819 CH1 CLK Duty spec in!! Max-Min= 218%
7364 23:56:04.464027 [DutyScan_Calibration_Flow] ====Done====
7365 23:56:04.464488
7366 23:56:04.467459 [DutyScan_Calibration_Flow] k_type=1
7367 23:56:04.484454
7368 23:56:04.484987 ==DQS 0 ==
7369 23:56:04.487302 Final DQS duty delay cell = 0
7370 23:56:04.490549 [0] MAX Duty = 5124%(X100), DQS PI = 18
7371 23:56:04.493996 [0] MIN Duty = 4907%(X100), DQS PI = 8
7372 23:56:04.497349 [0] AVG Duty = 5015%(X100)
7373 23:56:04.497875
7374 23:56:04.498426 ==DQS 1 ==
7375 23:56:04.500572 Final DQS duty delay cell = 0
7376 23:56:04.503789 [0] MAX Duty = 5093%(X100), DQS PI = 28
7377 23:56:04.507218 [0] MIN Duty = 4938%(X100), DQS PI = 58
7378 23:56:04.510423 [0] AVG Duty = 5015%(X100)
7379 23:56:04.510878
7380 23:56:04.513870 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7381 23:56:04.514430
7382 23:56:04.517304 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7383 23:56:04.520527 [DutyScan_Calibration_Flow] ====Done====
7384 23:56:04.521060
7385 23:56:04.523830 [DutyScan_Calibration_Flow] k_type=3
7386 23:56:04.540973
7387 23:56:04.541543 ==DQM 0 ==
7388 23:56:04.544461 Final DQM duty delay cell = 0
7389 23:56:04.548012 [0] MAX Duty = 5218%(X100), DQS PI = 36
7390 23:56:04.550871 [0] MIN Duty = 5000%(X100), DQS PI = 8
7391 23:56:04.551354 [0] AVG Duty = 5109%(X100)
7392 23:56:04.554461
7393 23:56:04.555027 ==DQM 1 ==
7394 23:56:04.557599 Final DQM duty delay cell = 0
7395 23:56:04.561815 [0] MAX Duty = 5156%(X100), DQS PI = 2
7396 23:56:04.564081 [0] MIN Duty = 4969%(X100), DQS PI = 30
7397 23:56:04.567532 [0] AVG Duty = 5062%(X100)
7398 23:56:04.568068
7399 23:56:04.570848 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7400 23:56:04.571312
7401 23:56:04.573923 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7402 23:56:04.577406 [DutyScan_Calibration_Flow] ====Done====
7403 23:56:04.577869
7404 23:56:04.580720 [DutyScan_Calibration_Flow] k_type=2
7405 23:56:04.598031
7406 23:56:04.598650 ==DQ 0 ==
7407 23:56:04.601458 Final DQ duty delay cell = 0
7408 23:56:04.604552 [0] MAX Duty = 5156%(X100), DQS PI = 28
7409 23:56:04.607768 [0] MIN Duty = 4906%(X100), DQS PI = 8
7410 23:56:04.608329 [0] AVG Duty = 5031%(X100)
7411 23:56:04.611107
7412 23:56:04.611568 ==DQ 1 ==
7413 23:56:04.614768 Final DQ duty delay cell = 0
7414 23:56:04.617875 [0] MAX Duty = 5125%(X100), DQS PI = 8
7415 23:56:04.620875 [0] MIN Duty = 4969%(X100), DQS PI = 56
7416 23:56:04.621432 [0] AVG Duty = 5047%(X100)
7417 23:56:04.621803
7418 23:56:04.627343 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7419 23:56:04.627886
7420 23:56:04.630760 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7421 23:56:04.634090 [DutyScan_Calibration_Flow] ====Done====
7422 23:56:04.637244 nWR fixed to 30
7423 23:56:04.637806 [ModeRegInit_LP4] CH0 RK0
7424 23:56:04.640814 [ModeRegInit_LP4] CH0 RK1
7425 23:56:04.643671 [ModeRegInit_LP4] CH1 RK0
7426 23:56:04.647378 [ModeRegInit_LP4] CH1 RK1
7427 23:56:04.647956 match AC timing 5
7428 23:56:04.654078 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7429 23:56:04.657010 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7430 23:56:04.660429 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7431 23:56:04.666772 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7432 23:56:04.670388 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7433 23:56:04.670947 [MiockJmeterHQA]
7434 23:56:04.671319
7435 23:56:04.673549 [DramcMiockJmeter] u1RxGatingPI = 0
7436 23:56:04.676847 0 : 4255, 4029
7437 23:56:04.677385 4 : 4252, 4027
7438 23:56:04.680336 8 : 4363, 4138
7439 23:56:04.680904 12 : 4253, 4026
7440 23:56:04.683554 16 : 4253, 4027
7441 23:56:04.684141 20 : 4363, 4138
7442 23:56:04.684522 24 : 4360, 4138
7443 23:56:04.686550 28 : 4252, 4027
7444 23:56:04.687023 32 : 4250, 4027
7445 23:56:04.690346 36 : 4251, 4027
7446 23:56:04.690815 40 : 4363, 4137
7447 23:56:04.693164 44 : 4250, 4027
7448 23:56:04.693589 48 : 4361, 4137
7449 23:56:04.696471 52 : 4250, 4027
7450 23:56:04.696895 56 : 4250, 4027
7451 23:56:04.697229 60 : 4250, 4026
7452 23:56:04.700235 64 : 4252, 4029
7453 23:56:04.700661 68 : 4250, 4027
7454 23:56:04.702991 72 : 4250, 4027
7455 23:56:04.703413 76 : 4363, 4140
7456 23:56:04.706366 80 : 4250, 4026
7457 23:56:04.706789 84 : 4252, 4029
7458 23:56:04.709508 88 : 4250, 4027
7459 23:56:04.709930 92 : 4361, 1017
7460 23:56:04.710307 96 : 4250, 0
7461 23:56:04.712812 100 : 4253, 0
7462 23:56:04.713246 104 : 4251, 0
7463 23:56:04.716640 108 : 4250, 0
7464 23:56:04.717165 112 : 4252, 0
7465 23:56:04.717506 116 : 4250, 0
7466 23:56:04.720354 120 : 4250, 0
7467 23:56:04.720871 124 : 4252, 0
7468 23:56:04.721214 128 : 4360, 0
7469 23:56:04.722800 132 : 4361, 0
7470 23:56:04.723250 136 : 4250, 0
7471 23:56:04.726668 140 : 4250, 0
7472 23:56:04.727112 144 : 4250, 0
7473 23:56:04.727447 148 : 4250, 0
7474 23:56:04.729451 152 : 4252, 0
7475 23:56:04.729873 156 : 4250, 0
7476 23:56:04.733013 160 : 4250, 0
7477 23:56:04.733531 164 : 4253, 0
7478 23:56:04.733873 168 : 4250, 0
7479 23:56:04.736131 172 : 4250, 0
7480 23:56:04.736651 176 : 4252, 0
7481 23:56:04.739758 180 : 4250, 0
7482 23:56:04.740486 184 : 4361, 0
7483 23:56:04.740998 188 : 4360, 0
7484 23:56:04.742520 192 : 4250, 0
7485 23:56:04.742943 196 : 4250, 0
7486 23:56:04.745889 200 : 4250, 0
7487 23:56:04.746347 204 : 4252, 0
7488 23:56:04.746688 208 : 4250, 0
7489 23:56:04.749279 212 : 4251, 0
7490 23:56:04.749703 216 : 4252, 0
7491 23:56:04.752689 220 : 4361, 0
7492 23:56:04.753113 224 : 4250, 138
7493 23:56:04.753453 228 : 4252, 2858
7494 23:56:04.755831 232 : 4250, 4027
7495 23:56:04.756253 236 : 4250, 4027
7496 23:56:04.759411 240 : 4361, 4137
7497 23:56:04.759933 244 : 4361, 4137
7498 23:56:04.762401 248 : 4250, 4027
7499 23:56:04.762826 252 : 4360, 4138
7500 23:56:04.765644 256 : 4250, 4027
7501 23:56:04.766065 260 : 4250, 4026
7502 23:56:04.769121 264 : 4250, 4027
7503 23:56:04.769683 268 : 4252, 4029
7504 23:56:04.772283 272 : 4250, 4027
7505 23:56:04.772727 276 : 4250, 4026
7506 23:56:04.775244 280 : 4250, 4027
7507 23:56:04.775681 284 : 4252, 4030
7508 23:56:04.778568 288 : 4249, 4027
7509 23:56:04.778992 292 : 4361, 4138
7510 23:56:04.779327 296 : 4361, 4137
7511 23:56:04.781854 300 : 4250, 4027
7512 23:56:04.782345 304 : 4363, 4140
7513 23:56:04.785443 308 : 4361, 4138
7514 23:56:04.785865 312 : 4250, 4026
7515 23:56:04.788358 316 : 4250, 4027
7516 23:56:04.788782 320 : 4252, 4029
7517 23:56:04.791673 324 : 4250, 4027
7518 23:56:04.792095 328 : 4250, 4027
7519 23:56:04.794714 332 : 4250, 4027
7520 23:56:04.795093 336 : 4252, 3860
7521 23:56:04.798382 340 : 4250, 2121
7522 23:56:04.798803
7523 23:56:04.799131 MIOCK jitter meter ch=0
7524 23:56:04.799437
7525 23:56:04.801933 1T = (340-92) = 248 dly cells
7526 23:56:04.808775 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7527 23:56:04.809293 ==
7528 23:56:04.811666 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 23:56:04.814656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 23:56:04.815074 ==
7531 23:56:04.821860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 23:56:04.824560 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 23:56:04.831439 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 23:56:04.834724 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 23:56:04.845296 [CA 0] Center 43 (12~74) winsize 63
7536 23:56:04.848313 [CA 1] Center 42 (12~73) winsize 62
7537 23:56:04.851245 [CA 2] Center 38 (9~68) winsize 60
7538 23:56:04.854880 [CA 3] Center 38 (9~68) winsize 60
7539 23:56:04.857967 [CA 4] Center 36 (7~66) winsize 60
7540 23:56:04.861661 [CA 5] Center 35 (6~65) winsize 60
7541 23:56:04.862073
7542 23:56:04.864881 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 23:56:04.865307
7544 23:56:04.867892 [CATrainingPosCal] consider 1 rank data
7545 23:56:04.871459 u2DelayCellTimex100 = 262/100 ps
7546 23:56:04.877929 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7547 23:56:04.881148 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7548 23:56:04.884930 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7549 23:56:04.887853 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7550 23:56:04.891028 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7551 23:56:04.894235 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7552 23:56:04.894700
7553 23:56:04.898146 CA PerBit enable=1, Macro0, CA PI delay=35
7554 23:56:04.898753
7555 23:56:04.900951 [CBTSetCACLKResult] CA Dly = 35
7556 23:56:04.904250 CS Dly: 12 (0~43)
7557 23:56:04.907475 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 23:56:04.911064 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 23:56:04.911531 ==
7560 23:56:04.914039 Dram Type= 6, Freq= 0, CH_0, rank 1
7561 23:56:04.921017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 23:56:04.921603 ==
7563 23:56:04.924079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 23:56:04.931022 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 23:56:04.933727 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 23:56:04.940277 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 23:56:04.948575 [CA 0] Center 42 (12~73) winsize 62
7568 23:56:04.951979 [CA 1] Center 43 (13~73) winsize 61
7569 23:56:04.954612 [CA 2] Center 37 (8~67) winsize 60
7570 23:56:04.958088 [CA 3] Center 37 (7~67) winsize 61
7571 23:56:04.961220 [CA 4] Center 35 (6~65) winsize 60
7572 23:56:04.964894 [CA 5] Center 35 (5~66) winsize 62
7573 23:56:04.965324
7574 23:56:04.967922 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 23:56:04.968334
7576 23:56:04.974560 [CATrainingPosCal] consider 2 rank data
7577 23:56:04.975078 u2DelayCellTimex100 = 262/100 ps
7578 23:56:04.981631 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7579 23:56:04.984869 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7580 23:56:04.987837 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7581 23:56:04.991346 CA3 delay=38 (9~67),Diff = 3 PI (11 cell)
7582 23:56:04.994617 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7583 23:56:04.997871 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7584 23:56:04.998432
7585 23:56:05.001432 CA PerBit enable=1, Macro0, CA PI delay=35
7586 23:56:05.002142
7587 23:56:05.004447 [CBTSetCACLKResult] CA Dly = 35
7588 23:56:05.007757 CS Dly: 12 (0~43)
7589 23:56:05.011207 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 23:56:05.014104 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 23:56:05.014549
7592 23:56:05.018043 ----->DramcWriteLeveling(PI) begin...
7593 23:56:05.018667 ==
7594 23:56:05.021004 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 23:56:05.027777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 23:56:05.028203 ==
7597 23:56:05.030940 Write leveling (Byte 0): 35 => 35
7598 23:56:05.034271 Write leveling (Byte 1): 29 => 29
7599 23:56:05.037506 DramcWriteLeveling(PI) end<-----
7600 23:56:05.038122
7601 23:56:05.038527 ==
7602 23:56:05.040478 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 23:56:05.044212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 23:56:05.044724 ==
7605 23:56:05.047334 [Gating] SW mode calibration
7606 23:56:05.053904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7607 23:56:05.060249 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7608 23:56:05.063782 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 23:56:05.066815 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 23:56:05.073445 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 23:56:05.076468 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7612 23:56:05.079815 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7613 23:56:05.086792 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7614 23:56:05.090004 1 4 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7615 23:56:05.093401 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 23:56:05.099789 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 23:56:05.102817 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 23:56:05.106270 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 23:56:05.113629 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7620 23:56:05.116489 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7621 23:56:05.119664 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7622 23:56:05.125963 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7623 23:56:05.129987 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 23:56:05.132473 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 23:56:05.139418 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 23:56:05.142456 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 23:56:05.145772 1 6 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
7628 23:56:05.152586 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7629 23:56:05.155618 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7630 23:56:05.158828 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7631 23:56:05.165751 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 23:56:05.169063 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 23:56:05.172450 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 23:56:05.178723 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 23:56:05.182346 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 23:56:05.185406 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7637 23:56:05.192054 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7638 23:56:05.195621 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 23:56:05.199139 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:56:05.205202 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:56:05.209014 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:56:05.212096 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:56:05.218723 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:56:05.221667 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:56:05.224761 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:56:05.231463 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:56:05.234701 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:56:05.238250 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:56:05.245010 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:56:05.248139 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:56:05.251398 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 23:56:05.257738 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7653 23:56:05.258219 Total UI for P1: 0, mck2ui 16
7654 23:56:05.264578 best dqsien dly found for B0: ( 1, 9, 12)
7655 23:56:05.268094 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7656 23:56:05.271347 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 23:56:05.274582 Total UI for P1: 0, mck2ui 16
7658 23:56:05.277605 best dqsien dly found for B1: ( 1, 9, 18)
7659 23:56:05.280908 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7660 23:56:05.284433 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7661 23:56:05.285024
7662 23:56:05.290981 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7663 23:56:05.293855 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7664 23:56:05.297247 [Gating] SW calibration Done
7665 23:56:05.297812 ==
7666 23:56:05.300544 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 23:56:05.304033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 23:56:05.304498 ==
7669 23:56:05.304863 RX Vref Scan: 0
7670 23:56:05.305203
7671 23:56:05.307216 RX Vref 0 -> 0, step: 1
7672 23:56:05.307634
7673 23:56:05.310616 RX Delay 0 -> 252, step: 8
7674 23:56:05.313734 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7675 23:56:05.317534 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7676 23:56:05.324054 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7677 23:56:05.327031 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7678 23:56:05.330496 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7679 23:56:05.333593 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7680 23:56:05.337185 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7681 23:56:05.343847 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7682 23:56:05.347639 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7683 23:56:05.350119 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7684 23:56:05.353655 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7685 23:56:05.356978 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7686 23:56:05.363300 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7687 23:56:05.366640 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7688 23:56:05.370005 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7689 23:56:05.373111 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7690 23:56:05.373570 ==
7691 23:56:05.376520 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 23:56:05.383349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 23:56:05.383904 ==
7694 23:56:05.384272 DQS Delay:
7695 23:56:05.386539 DQS0 = 0, DQS1 = 0
7696 23:56:05.387002 DQM Delay:
7697 23:56:05.389551 DQM0 = 135, DQM1 = 126
7698 23:56:05.390014 DQ Delay:
7699 23:56:05.392975 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7700 23:56:05.396586 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7701 23:56:05.399886 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7702 23:56:05.402758 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7703 23:56:05.403237
7704 23:56:05.403603
7705 23:56:05.403937 ==
7706 23:56:05.406252 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 23:56:05.412783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 23:56:05.413351 ==
7709 23:56:05.413716
7710 23:56:05.414049
7711 23:56:05.414435 TX Vref Scan disable
7712 23:56:05.416064 == TX Byte 0 ==
7713 23:56:05.419319 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7714 23:56:05.426236 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7715 23:56:05.426653 == TX Byte 1 ==
7716 23:56:05.429189 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7717 23:56:05.436339 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7718 23:56:05.436856 ==
7719 23:56:05.439412 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 23:56:05.442697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 23:56:05.443116 ==
7722 23:56:05.455525
7723 23:56:05.458956 TX Vref early break, caculate TX vref
7724 23:56:05.462067 TX Vref=16, minBit 6, minWin=22, winSum=371
7725 23:56:05.465675 TX Vref=18, minBit 0, minWin=23, winSum=384
7726 23:56:05.468503 TX Vref=20, minBit 4, minWin=23, winSum=388
7727 23:56:05.471780 TX Vref=22, minBit 1, minWin=24, winSum=402
7728 23:56:05.474869 TX Vref=24, minBit 0, minWin=25, winSum=410
7729 23:56:05.482074 TX Vref=26, minBit 0, minWin=25, winSum=419
7730 23:56:05.485214 TX Vref=28, minBit 0, minWin=25, winSum=421
7731 23:56:05.488206 TX Vref=30, minBit 0, minWin=24, winSum=413
7732 23:56:05.491751 TX Vref=32, minBit 5, minWin=23, winSum=404
7733 23:56:05.494943 TX Vref=34, minBit 4, minWin=23, winSum=395
7734 23:56:05.501604 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
7735 23:56:05.502157
7736 23:56:05.505038 Final TX Range 0 Vref 28
7737 23:56:05.505498
7738 23:56:05.505859 ==
7739 23:56:05.508665 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 23:56:05.511807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 23:56:05.512372 ==
7742 23:56:05.512745
7743 23:56:05.513086
7744 23:56:05.514818 TX Vref Scan disable
7745 23:56:05.521646 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7746 23:56:05.522258 == TX Byte 0 ==
7747 23:56:05.525170 u2DelayCellOfst[0]=14 cells (4 PI)
7748 23:56:05.527886 u2DelayCellOfst[1]=18 cells (5 PI)
7749 23:56:05.531286 u2DelayCellOfst[2]=14 cells (4 PI)
7750 23:56:05.534563 u2DelayCellOfst[3]=14 cells (4 PI)
7751 23:56:05.538054 u2DelayCellOfst[4]=11 cells (3 PI)
7752 23:56:05.541053 u2DelayCellOfst[5]=0 cells (0 PI)
7753 23:56:05.544186 u2DelayCellOfst[6]=18 cells (5 PI)
7754 23:56:05.547685 u2DelayCellOfst[7]=18 cells (5 PI)
7755 23:56:05.550948 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7756 23:56:05.554308 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7757 23:56:05.557477 == TX Byte 1 ==
7758 23:56:05.560891 u2DelayCellOfst[8]=0 cells (0 PI)
7759 23:56:05.564422 u2DelayCellOfst[9]=0 cells (0 PI)
7760 23:56:05.567611 u2DelayCellOfst[10]=7 cells (2 PI)
7761 23:56:05.571039 u2DelayCellOfst[11]=3 cells (1 PI)
7762 23:56:05.574064 u2DelayCellOfst[12]=14 cells (4 PI)
7763 23:56:05.574589 u2DelayCellOfst[13]=11 cells (3 PI)
7764 23:56:05.577094 u2DelayCellOfst[14]=14 cells (4 PI)
7765 23:56:05.580619 u2DelayCellOfst[15]=11 cells (3 PI)
7766 23:56:05.587286 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7767 23:56:05.590541 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7768 23:56:05.593620 DramC Write-DBI on
7769 23:56:05.594314 ==
7770 23:56:05.596877 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 23:56:05.600271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 23:56:05.600843 ==
7773 23:56:05.601309
7774 23:56:05.601665
7775 23:56:05.603957 TX Vref Scan disable
7776 23:56:05.604418 == TX Byte 0 ==
7777 23:56:05.610576 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7778 23:56:05.611133 == TX Byte 1 ==
7779 23:56:05.613661 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7780 23:56:05.617036 DramC Write-DBI off
7781 23:56:05.617594
7782 23:56:05.617958 [DATLAT]
7783 23:56:05.620064 Freq=1600, CH0 RK0
7784 23:56:05.620623
7785 23:56:05.620987 DATLAT Default: 0xf
7786 23:56:05.623359 0, 0xFFFF, sum = 0
7787 23:56:05.626720 1, 0xFFFF, sum = 0
7788 23:56:05.627286 2, 0xFFFF, sum = 0
7789 23:56:05.629665 3, 0xFFFF, sum = 0
7790 23:56:05.630135 4, 0xFFFF, sum = 0
7791 23:56:05.633138 5, 0xFFFF, sum = 0
7792 23:56:05.633698 6, 0xFFFF, sum = 0
7793 23:56:05.636789 7, 0xFFFF, sum = 0
7794 23:56:05.637352 8, 0xFFFF, sum = 0
7795 23:56:05.640034 9, 0xFFFF, sum = 0
7796 23:56:05.640635 10, 0xFFFF, sum = 0
7797 23:56:05.642655 11, 0xFFFF, sum = 0
7798 23:56:05.643124 12, 0xFFFF, sum = 0
7799 23:56:05.646261 13, 0xFFFF, sum = 0
7800 23:56:05.646897 14, 0x0, sum = 1
7801 23:56:05.649636 15, 0x0, sum = 2
7802 23:56:05.650231 16, 0x0, sum = 3
7803 23:56:05.652697 17, 0x0, sum = 4
7804 23:56:05.653165 best_step = 15
7805 23:56:05.653526
7806 23:56:05.653882 ==
7807 23:56:05.655725 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 23:56:05.662629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 23:56:05.663185 ==
7810 23:56:05.663552 RX Vref Scan: 1
7811 23:56:05.663892
7812 23:56:05.665945 Set Vref Range= 24 -> 127
7813 23:56:05.666556
7814 23:56:05.669804 RX Vref 24 -> 127, step: 1
7815 23:56:05.670405
7816 23:56:05.672823 RX Delay 11 -> 252, step: 4
7817 23:56:05.673646
7818 23:56:05.675466 Set Vref, RX VrefLevel [Byte0]: 24
7819 23:56:05.678915 [Byte1]: 24
7820 23:56:05.679377
7821 23:56:05.682736 Set Vref, RX VrefLevel [Byte0]: 25
7822 23:56:05.685750 [Byte1]: 25
7823 23:56:05.686368
7824 23:56:05.688654 Set Vref, RX VrefLevel [Byte0]: 26
7825 23:56:05.692024 [Byte1]: 26
7826 23:56:05.695465
7827 23:56:05.695925 Set Vref, RX VrefLevel [Byte0]: 27
7828 23:56:05.698660 [Byte1]: 27
7829 23:56:05.702964
7830 23:56:05.703421 Set Vref, RX VrefLevel [Byte0]: 28
7831 23:56:05.706337 [Byte1]: 28
7832 23:56:05.710667
7833 23:56:05.711123 Set Vref, RX VrefLevel [Byte0]: 29
7834 23:56:05.714006 [Byte1]: 29
7835 23:56:05.718413
7836 23:56:05.718965 Set Vref, RX VrefLevel [Byte0]: 30
7837 23:56:05.721537 [Byte1]: 30
7838 23:56:05.726111
7839 23:56:05.726718 Set Vref, RX VrefLevel [Byte0]: 31
7840 23:56:05.729621 [Byte1]: 31
7841 23:56:05.733433
7842 23:56:05.733987 Set Vref, RX VrefLevel [Byte0]: 32
7843 23:56:05.737214 [Byte1]: 32
7844 23:56:05.741303
7845 23:56:05.741850 Set Vref, RX VrefLevel [Byte0]: 33
7846 23:56:05.744601 [Byte1]: 33
7847 23:56:05.748741
7848 23:56:05.749294 Set Vref, RX VrefLevel [Byte0]: 34
7849 23:56:05.752120 [Byte1]: 34
7850 23:56:05.756329
7851 23:56:05.756787 Set Vref, RX VrefLevel [Byte0]: 35
7852 23:56:05.759403 [Byte1]: 35
7853 23:56:05.763914
7854 23:56:05.764468 Set Vref, RX VrefLevel [Byte0]: 36
7855 23:56:05.766966 [Byte1]: 36
7856 23:56:05.771603
7857 23:56:05.772154 Set Vref, RX VrefLevel [Byte0]: 37
7858 23:56:05.774705 [Byte1]: 37
7859 23:56:05.778921
7860 23:56:05.779380 Set Vref, RX VrefLevel [Byte0]: 38
7861 23:56:05.782211 [Byte1]: 38
7862 23:56:05.786570
7863 23:56:05.787032 Set Vref, RX VrefLevel [Byte0]: 39
7864 23:56:05.790039 [Byte1]: 39
7865 23:56:05.794372
7866 23:56:05.795143 Set Vref, RX VrefLevel [Byte0]: 40
7867 23:56:05.797546 [Byte1]: 40
7868 23:56:05.802126
7869 23:56:05.802726 Set Vref, RX VrefLevel [Byte0]: 41
7870 23:56:05.805219 [Byte1]: 41
7871 23:56:05.809781
7872 23:56:05.810425 Set Vref, RX VrefLevel [Byte0]: 42
7873 23:56:05.812963 [Byte1]: 42
7874 23:56:05.817393
7875 23:56:05.817949 Set Vref, RX VrefLevel [Byte0]: 43
7876 23:56:05.820791 [Byte1]: 43
7877 23:56:05.824789
7878 23:56:05.825337 Set Vref, RX VrefLevel [Byte0]: 44
7879 23:56:05.828215 [Byte1]: 44
7880 23:56:05.832474
7881 23:56:05.832936 Set Vref, RX VrefLevel [Byte0]: 45
7882 23:56:05.835875 [Byte1]: 45
7883 23:56:05.840232
7884 23:56:05.840783 Set Vref, RX VrefLevel [Byte0]: 46
7885 23:56:05.843515 [Byte1]: 46
7886 23:56:05.847474
7887 23:56:05.848024 Set Vref, RX VrefLevel [Byte0]: 47
7888 23:56:05.851103 [Byte1]: 47
7889 23:56:05.855017
7890 23:56:05.855475 Set Vref, RX VrefLevel [Byte0]: 48
7891 23:56:05.858671 [Byte1]: 48
7892 23:56:05.863171
7893 23:56:05.863724 Set Vref, RX VrefLevel [Byte0]: 49
7894 23:56:05.865980 [Byte1]: 49
7895 23:56:05.870510
7896 23:56:05.871068 Set Vref, RX VrefLevel [Byte0]: 50
7897 23:56:05.873852 [Byte1]: 50
7898 23:56:05.878255
7899 23:56:05.878715 Set Vref, RX VrefLevel [Byte0]: 51
7900 23:56:05.881640 [Byte1]: 51
7901 23:56:05.885592
7902 23:56:05.886050 Set Vref, RX VrefLevel [Byte0]: 52
7903 23:56:05.888897 [Byte1]: 52
7904 23:56:05.893087
7905 23:56:05.893590 Set Vref, RX VrefLevel [Byte0]: 53
7906 23:56:05.896580 [Byte1]: 53
7907 23:56:05.900970
7908 23:56:05.901427 Set Vref, RX VrefLevel [Byte0]: 54
7909 23:56:05.903923 [Byte1]: 54
7910 23:56:05.908367
7911 23:56:05.908825 Set Vref, RX VrefLevel [Byte0]: 55
7912 23:56:05.912237 [Byte1]: 55
7913 23:56:05.916355
7914 23:56:05.916867 Set Vref, RX VrefLevel [Byte0]: 56
7915 23:56:05.919617 [Byte1]: 56
7916 23:56:05.923454
7917 23:56:05.923875 Set Vref, RX VrefLevel [Byte0]: 57
7918 23:56:05.927204 [Byte1]: 57
7919 23:56:05.931130
7920 23:56:05.931545 Set Vref, RX VrefLevel [Byte0]: 58
7921 23:56:05.934778 [Byte1]: 58
7922 23:56:05.938894
7923 23:56:05.939406 Set Vref, RX VrefLevel [Byte0]: 59
7924 23:56:05.942327 [Byte1]: 59
7925 23:56:05.946392
7926 23:56:05.946807 Set Vref, RX VrefLevel [Byte0]: 60
7927 23:56:05.949940 [Byte1]: 60
7928 23:56:05.954517
7929 23:56:05.955032 Set Vref, RX VrefLevel [Byte0]: 61
7930 23:56:05.957516 [Byte1]: 61
7931 23:56:05.961954
7932 23:56:05.962395 Set Vref, RX VrefLevel [Byte0]: 62
7933 23:56:05.965425 [Byte1]: 62
7934 23:56:05.969582
7935 23:56:05.970231 Set Vref, RX VrefLevel [Byte0]: 63
7936 23:56:05.972748 [Byte1]: 63
7937 23:56:05.977229
7938 23:56:05.977643 Set Vref, RX VrefLevel [Byte0]: 64
7939 23:56:05.980445 [Byte1]: 64
7940 23:56:05.985092
7941 23:56:05.985602 Set Vref, RX VrefLevel [Byte0]: 65
7942 23:56:05.987771 [Byte1]: 65
7943 23:56:05.992757
7944 23:56:05.993268 Set Vref, RX VrefLevel [Byte0]: 66
7945 23:56:05.995495 [Byte1]: 66
7946 23:56:05.999913
7947 23:56:06.000431 Set Vref, RX VrefLevel [Byte0]: 67
7948 23:56:06.002975 [Byte1]: 67
7949 23:56:06.007530
7950 23:56:06.008044 Set Vref, RX VrefLevel [Byte0]: 68
7951 23:56:06.010659 [Byte1]: 68
7952 23:56:06.014858
7953 23:56:06.015318 Set Vref, RX VrefLevel [Byte0]: 69
7954 23:56:06.018553 [Byte1]: 69
7955 23:56:06.022716
7956 23:56:06.023186 Set Vref, RX VrefLevel [Byte0]: 70
7957 23:56:06.026002 [Byte1]: 70
7958 23:56:06.030278
7959 23:56:06.030700 Set Vref, RX VrefLevel [Byte0]: 71
7960 23:56:06.033606 [Byte1]: 71
7961 23:56:06.038263
7962 23:56:06.038771 Set Vref, RX VrefLevel [Byte0]: 72
7963 23:56:06.041249 [Byte1]: 72
7964 23:56:06.045918
7965 23:56:06.046469 Set Vref, RX VrefLevel [Byte0]: 73
7966 23:56:06.048755 [Byte1]: 73
7967 23:56:06.053140
7968 23:56:06.053554 Set Vref, RX VrefLevel [Byte0]: 74
7969 23:56:06.056349 [Byte1]: 74
7970 23:56:06.060906
7971 23:56:06.061414 Set Vref, RX VrefLevel [Byte0]: 75
7972 23:56:06.064072 [Byte1]: 75
7973 23:56:06.068530
7974 23:56:06.069039 Set Vref, RX VrefLevel [Byte0]: 76
7975 23:56:06.071601 [Byte1]: 76
7976 23:56:06.075778
7977 23:56:06.076437 Set Vref, RX VrefLevel [Byte0]: 77
7978 23:56:06.079366 [Byte1]: 77
7979 23:56:06.083420
7980 23:56:06.083833 Set Vref, RX VrefLevel [Byte0]: 78
7981 23:56:06.086900 [Byte1]: 78
7982 23:56:06.091193
7983 23:56:06.091698 Set Vref, RX VrefLevel [Byte0]: 79
7984 23:56:06.094657 [Byte1]: 79
7985 23:56:06.098860
7986 23:56:06.099321 Final RX Vref Byte 0 = 66 to rank0
7987 23:56:06.102670 Final RX Vref Byte 1 = 59 to rank0
7988 23:56:06.105397 Final RX Vref Byte 0 = 66 to rank1
7989 23:56:06.108587 Final RX Vref Byte 1 = 59 to rank1==
7990 23:56:06.112124 Dram Type= 6, Freq= 0, CH_0, rank 0
7991 23:56:06.118756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 23:56:06.119326 ==
7993 23:56:06.119697 DQS Delay:
7994 23:56:06.121881 DQS0 = 0, DQS1 = 0
7995 23:56:06.122474 DQM Delay:
7996 23:56:06.122843 DQM0 = 132, DQM1 = 123
7997 23:56:06.125229 DQ Delay:
7998 23:56:06.128276 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
7999 23:56:06.132015 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
8000 23:56:06.135061 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8001 23:56:06.138475 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8002 23:56:06.138937
8003 23:56:06.139299
8004 23:56:06.139635
8005 23:56:06.141691 [DramC_TX_OE_Calibration] TA2
8006 23:56:06.145133 Original DQ_B0 (3 6) =30, OEN = 27
8007 23:56:06.148439 Original DQ_B1 (3 6) =30, OEN = 27
8008 23:56:06.151558 24, 0x0, End_B0=24 End_B1=24
8009 23:56:06.152120 25, 0x0, End_B0=25 End_B1=25
8010 23:56:06.154919 26, 0x0, End_B0=26 End_B1=26
8011 23:56:06.158562 27, 0x0, End_B0=27 End_B1=27
8012 23:56:06.161564 28, 0x0, End_B0=28 End_B1=28
8013 23:56:06.164497 29, 0x0, End_B0=29 End_B1=29
8014 23:56:06.164966 30, 0x0, End_B0=30 End_B1=30
8015 23:56:06.168533 31, 0x4141, End_B0=30 End_B1=30
8016 23:56:06.171307 Byte0 end_step=30 best_step=27
8017 23:56:06.174866 Byte1 end_step=30 best_step=27
8018 23:56:06.178226 Byte0 TX OE(2T, 0.5T) = (3, 3)
8019 23:56:06.181088 Byte1 TX OE(2T, 0.5T) = (3, 3)
8020 23:56:06.181552
8021 23:56:06.181919
8022 23:56:06.188094 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 394 ps
8023 23:56:06.191465 CH0 RK0: MR19=303, MR18=1E0F
8024 23:56:06.197538 CH0_RK0: MR19=0x303, MR18=0x1E0F, DQSOSC=394, MR23=63, INC=23, DEC=15
8025 23:56:06.198083
8026 23:56:06.201530 ----->DramcWriteLeveling(PI) begin...
8027 23:56:06.202105 ==
8028 23:56:06.204557 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 23:56:06.207550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 23:56:06.208021 ==
8031 23:56:06.211598 Write leveling (Byte 0): 36 => 36
8032 23:56:06.214074 Write leveling (Byte 1): 29 => 29
8033 23:56:06.217369 DramcWriteLeveling(PI) end<-----
8034 23:56:06.217832
8035 23:56:06.218248 ==
8036 23:56:06.221236 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 23:56:06.224146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 23:56:06.227594 ==
8039 23:56:06.228164 [Gating] SW mode calibration
8040 23:56:06.237369 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8041 23:56:06.240644 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8042 23:56:06.244251 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 23:56:06.250695 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 23:56:06.253707 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 23:56:06.257042 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 23:56:06.263636 1 4 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8047 23:56:06.266783 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
8048 23:56:06.270301 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 23:56:06.276759 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 23:56:06.280186 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 23:56:06.283178 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8052 23:56:06.289895 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8053 23:56:06.293011 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8054 23:56:06.296751 1 5 16 | B1->B0 | 3434 2727 | 1 1 | (1 0) (1 0)
8055 23:56:06.303538 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8056 23:56:06.306219 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8057 23:56:06.309618 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 23:56:06.316567 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 23:56:06.319506 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 23:56:06.322855 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 23:56:06.329663 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
8062 23:56:06.333113 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8063 23:56:06.335995 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8064 23:56:06.342417 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8065 23:56:06.345879 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 23:56:06.349333 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 23:56:06.356131 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 23:56:06.359061 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 23:56:06.362493 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8070 23:56:06.369218 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8071 23:56:06.372692 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8072 23:56:06.375667 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:56:06.382462 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:56:06.386189 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:56:06.388869 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:56:06.395507 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:56:06.398755 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:56:06.402038 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:56:06.408613 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 23:56:06.412225 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 23:56:06.415173 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 23:56:06.421713 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 23:56:06.425244 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 23:56:06.428570 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8085 23:56:06.434852 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8086 23:56:06.438530 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8087 23:56:06.441583 Total UI for P1: 0, mck2ui 16
8088 23:56:06.444706 best dqsien dly found for B0: ( 1, 9, 10)
8089 23:56:06.448235 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8090 23:56:06.454542 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 23:56:06.458065 Total UI for P1: 0, mck2ui 16
8092 23:56:06.461297 best dqsien dly found for B1: ( 1, 9, 18)
8093 23:56:06.464273 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8094 23:56:06.467646 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8095 23:56:06.468301
8096 23:56:06.470766 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8097 23:56:06.474490 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8098 23:56:06.477503 [Gating] SW calibration Done
8099 23:56:06.477914 ==
8100 23:56:06.480872 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 23:56:06.483857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 23:56:06.487363 ==
8103 23:56:06.487873 RX Vref Scan: 0
8104 23:56:06.488204
8105 23:56:06.490490 RX Vref 0 -> 0, step: 1
8106 23:56:06.490903
8107 23:56:06.494066 RX Delay 0 -> 252, step: 8
8108 23:56:06.497447 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8109 23:56:06.500516 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8110 23:56:06.503978 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8111 23:56:06.507077 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8112 23:56:06.513637 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8113 23:56:06.516901 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8114 23:56:06.520554 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8115 23:56:06.523511 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8116 23:56:06.526639 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8117 23:56:06.533536 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8118 23:56:06.536946 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8119 23:56:06.540210 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8120 23:56:06.543190 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8121 23:56:06.549828 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8122 23:56:06.553253 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8123 23:56:06.556171 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8124 23:56:06.556627 ==
8125 23:56:06.559981 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 23:56:06.562842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 23:56:06.563303 ==
8128 23:56:06.566394 DQS Delay:
8129 23:56:06.566978 DQS0 = 0, DQS1 = 0
8130 23:56:06.569852 DQM Delay:
8131 23:56:06.570467 DQM0 = 133, DQM1 = 128
8132 23:56:06.573158 DQ Delay:
8133 23:56:06.575917 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8134 23:56:06.579358 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8135 23:56:06.582435 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8136 23:56:06.585687 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8137 23:56:06.586153
8138 23:56:06.586572
8139 23:56:06.586909 ==
8140 23:56:06.589354 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 23:56:06.592685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 23:56:06.593146 ==
8143 23:56:06.593509
8144 23:56:06.595541
8145 23:56:06.595991 TX Vref Scan disable
8146 23:56:06.599010 == TX Byte 0 ==
8147 23:56:06.602373 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8148 23:56:06.605501 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8149 23:56:06.609065 == TX Byte 1 ==
8150 23:56:06.612266 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8151 23:56:06.615275 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8152 23:56:06.615737 ==
8153 23:56:06.618646 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 23:56:06.625359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 23:56:06.625916 ==
8156 23:56:06.637845
8157 23:56:06.641495 TX Vref early break, caculate TX vref
8158 23:56:06.644525 TX Vref=16, minBit 0, minWin=22, winSum=378
8159 23:56:06.648169 TX Vref=18, minBit 0, minWin=23, winSum=388
8160 23:56:06.651370 TX Vref=20, minBit 3, minWin=23, winSum=394
8161 23:56:06.654157 TX Vref=22, minBit 0, minWin=24, winSum=406
8162 23:56:06.657713 TX Vref=24, minBit 3, minWin=24, winSum=413
8163 23:56:06.664506 TX Vref=26, minBit 1, minWin=24, winSum=413
8164 23:56:06.667757 TX Vref=28, minBit 1, minWin=24, winSum=412
8165 23:56:06.671074 TX Vref=30, minBit 0, minWin=24, winSum=405
8166 23:56:06.674293 TX Vref=32, minBit 5, minWin=23, winSum=398
8167 23:56:06.677525 TX Vref=34, minBit 4, minWin=22, winSum=389
8168 23:56:06.684437 [TxChooseVref] Worse bit 3, Min win 24, Win sum 413, Final Vref 24
8169 23:56:06.684998
8170 23:56:06.687487 Final TX Range 0 Vref 24
8171 23:56:06.688015
8172 23:56:06.688483 ==
8173 23:56:06.690567 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 23:56:06.693861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 23:56:06.694467 ==
8176 23:56:06.694842
8177 23:56:06.695180
8178 23:56:06.697402 TX Vref Scan disable
8179 23:56:06.703632 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8180 23:56:06.704305 == TX Byte 0 ==
8181 23:56:06.706910 u2DelayCellOfst[0]=14 cells (4 PI)
8182 23:56:06.710277 u2DelayCellOfst[1]=18 cells (5 PI)
8183 23:56:06.713844 u2DelayCellOfst[2]=14 cells (4 PI)
8184 23:56:06.717236 u2DelayCellOfst[3]=14 cells (4 PI)
8185 23:56:06.720425 u2DelayCellOfst[4]=11 cells (3 PI)
8186 23:56:06.723432 u2DelayCellOfst[5]=0 cells (0 PI)
8187 23:56:06.727135 u2DelayCellOfst[6]=18 cells (5 PI)
8188 23:56:06.730045 u2DelayCellOfst[7]=18 cells (5 PI)
8189 23:56:06.733740 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8190 23:56:06.736533 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8191 23:56:06.739830 == TX Byte 1 ==
8192 23:56:06.743201 u2DelayCellOfst[8]=0 cells (0 PI)
8193 23:56:06.746800 u2DelayCellOfst[9]=3 cells (1 PI)
8194 23:56:06.749665 u2DelayCellOfst[10]=7 cells (2 PI)
8195 23:56:06.752821 u2DelayCellOfst[11]=3 cells (1 PI)
8196 23:56:06.753307 u2DelayCellOfst[12]=14 cells (4 PI)
8197 23:56:06.756523 u2DelayCellOfst[13]=11 cells (3 PI)
8198 23:56:06.760075 u2DelayCellOfst[14]=18 cells (5 PI)
8199 23:56:06.763007 u2DelayCellOfst[15]=14 cells (4 PI)
8200 23:56:06.769900 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8201 23:56:06.773285 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8202 23:56:06.773842 DramC Write-DBI on
8203 23:56:06.776118 ==
8204 23:56:06.779359 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 23:56:06.783104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 23:56:06.783524 ==
8207 23:56:06.783871
8208 23:56:06.784398
8209 23:56:06.786224 TX Vref Scan disable
8210 23:56:06.786767 == TX Byte 0 ==
8211 23:56:06.792419 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8212 23:56:06.792875 == TX Byte 1 ==
8213 23:56:06.796315 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8214 23:56:06.799386 DramC Write-DBI off
8215 23:56:06.799935
8216 23:56:06.800294 [DATLAT]
8217 23:56:06.802654 Freq=1600, CH0 RK1
8218 23:56:06.803126
8219 23:56:06.803597 DATLAT Default: 0xf
8220 23:56:06.805939 0, 0xFFFF, sum = 0
8221 23:56:06.806467 1, 0xFFFF, sum = 0
8222 23:56:06.809362 2, 0xFFFF, sum = 0
8223 23:56:06.812533 3, 0xFFFF, sum = 0
8224 23:56:06.813102 4, 0xFFFF, sum = 0
8225 23:56:06.815492 5, 0xFFFF, sum = 0
8226 23:56:06.816002 6, 0xFFFF, sum = 0
8227 23:56:06.818998 7, 0xFFFF, sum = 0
8228 23:56:06.819533 8, 0xFFFF, sum = 0
8229 23:56:06.822258 9, 0xFFFF, sum = 0
8230 23:56:06.822698 10, 0xFFFF, sum = 0
8231 23:56:06.825779 11, 0xFFFF, sum = 0
8232 23:56:06.826239 12, 0xFFFF, sum = 0
8233 23:56:06.828736 13, 0xFFFF, sum = 0
8234 23:56:06.829165 14, 0x0, sum = 1
8235 23:56:06.832558 15, 0x0, sum = 2
8236 23:56:06.832990 16, 0x0, sum = 3
8237 23:56:06.835645 17, 0x0, sum = 4
8238 23:56:06.836075 best_step = 15
8239 23:56:06.836503
8240 23:56:06.837008 ==
8241 23:56:06.838731 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 23:56:06.845794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 23:56:06.846361 ==
8244 23:56:06.846696 RX Vref Scan: 0
8245 23:56:06.847002
8246 23:56:06.848814 RX Vref 0 -> 0, step: 1
8247 23:56:06.849324
8248 23:56:06.851865 RX Delay 11 -> 252, step: 4
8249 23:56:06.855468 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8250 23:56:06.858497 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8251 23:56:06.861657 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8252 23:56:06.868228 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8253 23:56:06.871896 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8254 23:56:06.875313 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8255 23:56:06.878332 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8256 23:56:06.881682 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8257 23:56:06.888366 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8258 23:56:06.891989 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8259 23:56:06.894744 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8260 23:56:06.898192 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8261 23:56:06.904387 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8262 23:56:06.907578 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8263 23:56:06.910744 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8264 23:56:06.914569 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8265 23:56:06.915130 ==
8266 23:56:06.918239 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 23:56:06.924474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 23:56:06.925220 ==
8269 23:56:06.925608 DQS Delay:
8270 23:56:06.927238 DQS0 = 0, DQS1 = 0
8271 23:56:06.927702 DQM Delay:
8272 23:56:06.930891 DQM0 = 130, DQM1 = 125
8273 23:56:06.931464 DQ Delay:
8274 23:56:06.934398 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8275 23:56:06.937769 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8276 23:56:06.940894 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8277 23:56:06.943842 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8278 23:56:06.944305
8279 23:56:06.944668
8280 23:56:06.945004
8281 23:56:06.947339 [DramC_TX_OE_Calibration] TA2
8282 23:56:06.950720 Original DQ_B0 (3 6) =30, OEN = 27
8283 23:56:06.954155 Original DQ_B1 (3 6) =30, OEN = 27
8284 23:56:06.957476 24, 0x0, End_B0=24 End_B1=24
8285 23:56:06.960632 25, 0x0, End_B0=25 End_B1=25
8286 23:56:06.961105 26, 0x0, End_B0=26 End_B1=26
8287 23:56:06.963775 27, 0x0, End_B0=27 End_B1=27
8288 23:56:06.966953 28, 0x0, End_B0=28 End_B1=28
8289 23:56:06.970688 29, 0x0, End_B0=29 End_B1=29
8290 23:56:06.971262 30, 0x0, End_B0=30 End_B1=30
8291 23:56:06.973908 31, 0x4545, End_B0=30 End_B1=30
8292 23:56:06.977031 Byte0 end_step=30 best_step=27
8293 23:56:06.980374 Byte1 end_step=30 best_step=27
8294 23:56:06.983527 Byte0 TX OE(2T, 0.5T) = (3, 3)
8295 23:56:06.986821 Byte1 TX OE(2T, 0.5T) = (3, 3)
8296 23:56:06.987396
8297 23:56:06.987899
8298 23:56:06.993903 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8299 23:56:06.996870 CH0 RK1: MR19=303, MR18=1C00
8300 23:56:07.003380 CH0_RK1: MR19=0x303, MR18=0x1C00, DQSOSC=395, MR23=63, INC=23, DEC=15
8301 23:56:07.006733 [RxdqsGatingPostProcess] freq 1600
8302 23:56:07.013417 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8303 23:56:07.013927 best DQS0 dly(2T, 0.5T) = (1, 1)
8304 23:56:07.016922 best DQS1 dly(2T, 0.5T) = (1, 1)
8305 23:56:07.020158 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8306 23:56:07.023398 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8307 23:56:07.026729 best DQS0 dly(2T, 0.5T) = (1, 1)
8308 23:56:07.030140 best DQS1 dly(2T, 0.5T) = (1, 1)
8309 23:56:07.033041 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8310 23:56:07.036648 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8311 23:56:07.039788 Pre-setting of DQS Precalculation
8312 23:56:07.043065 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8313 23:56:07.043653 ==
8314 23:56:07.046096 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 23:56:07.052942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 23:56:07.053506 ==
8317 23:56:07.055926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8318 23:56:07.062613 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8319 23:56:07.065613 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8320 23:56:07.072710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8321 23:56:07.080510 [CA 0] Center 42 (13~72) winsize 60
8322 23:56:07.083688 [CA 1] Center 43 (14~72) winsize 59
8323 23:56:07.086884 [CA 2] Center 37 (9~66) winsize 58
8324 23:56:07.090055 [CA 3] Center 37 (8~66) winsize 59
8325 23:56:07.093786 [CA 4] Center 38 (8~68) winsize 61
8326 23:56:07.096679 [CA 5] Center 37 (8~67) winsize 60
8327 23:56:07.097137
8328 23:56:07.100000 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8329 23:56:07.100462
8330 23:56:07.106723 [CATrainingPosCal] consider 1 rank data
8331 23:56:07.107211 u2DelayCellTimex100 = 262/100 ps
8332 23:56:07.113630 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8333 23:56:07.116299 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8334 23:56:07.120179 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8335 23:56:07.123104 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8336 23:56:07.126289 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8337 23:56:07.130246 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8338 23:56:07.130760
8339 23:56:07.133316 CA PerBit enable=1, Macro0, CA PI delay=37
8340 23:56:07.133736
8341 23:56:07.136558 [CBTSetCACLKResult] CA Dly = 37
8342 23:56:07.140478 CS Dly: 9 (0~40)
8343 23:56:07.143241 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8344 23:56:07.146312 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8345 23:56:07.146817 ==
8346 23:56:07.149427 Dram Type= 6, Freq= 0, CH_1, rank 1
8347 23:56:07.156170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 23:56:07.156672 ==
8349 23:56:07.159884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 23:56:07.165974 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 23:56:07.169025 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 23:56:07.175826 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 23:56:07.183748 [CA 0] Center 42 (12~72) winsize 61
8354 23:56:07.186807 [CA 1] Center 42 (13~72) winsize 60
8355 23:56:07.190052 [CA 2] Center 37 (8~67) winsize 60
8356 23:56:07.193648 [CA 3] Center 36 (7~66) winsize 60
8357 23:56:07.196796 [CA 4] Center 37 (8~67) winsize 60
8358 23:56:07.200301 [CA 5] Center 37 (7~67) winsize 61
8359 23:56:07.200857
8360 23:56:07.203254 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8361 23:56:07.203732
8362 23:56:07.210063 [CATrainingPosCal] consider 2 rank data
8363 23:56:07.210595 u2DelayCellTimex100 = 262/100 ps
8364 23:56:07.216775 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8365 23:56:07.220112 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8366 23:56:07.222972 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8367 23:56:07.226952 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8368 23:56:07.230090 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8369 23:56:07.232893 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8370 23:56:07.233356
8371 23:56:07.236195 CA PerBit enable=1, Macro0, CA PI delay=37
8372 23:56:07.236645
8373 23:56:07.240135 [CBTSetCACLKResult] CA Dly = 37
8374 23:56:07.243084 CS Dly: 10 (0~43)
8375 23:56:07.246322 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 23:56:07.249527 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 23:56:07.249982
8378 23:56:07.253188 ----->DramcWriteLeveling(PI) begin...
8379 23:56:07.253746 ==
8380 23:56:07.256020 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 23:56:07.263121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 23:56:07.263741 ==
8383 23:56:07.266308 Write leveling (Byte 0): 23 => 23
8384 23:56:07.269606 Write leveling (Byte 1): 27 => 27
8385 23:56:07.270189 DramcWriteLeveling(PI) end<-----
8386 23:56:07.272529
8387 23:56:07.272977 ==
8388 23:56:07.275861 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 23:56:07.279288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 23:56:07.279859 ==
8391 23:56:07.282803 [Gating] SW mode calibration
8392 23:56:07.289329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8393 23:56:07.292925 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8394 23:56:07.299338 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 23:56:07.302800 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 23:56:07.305687 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:56:07.312258 1 4 12 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
8398 23:56:07.315529 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 23:56:07.319116 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 23:56:07.325724 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 23:56:07.329291 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 23:56:07.331893 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 23:56:07.338995 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 23:56:07.342313 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8405 23:56:07.345552 1 5 12 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
8406 23:56:07.352313 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8407 23:56:07.355508 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 23:56:07.358661 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 23:56:07.365703 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 23:56:07.368565 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 23:56:07.371928 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 23:56:07.378517 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8413 23:56:07.381928 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8414 23:56:07.385014 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 23:56:07.391646 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 23:56:07.395072 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 23:56:07.398029 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 23:56:07.404815 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 23:56:07.407908 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 23:56:07.410984 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 23:56:07.417961 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8422 23:56:07.421232 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8423 23:56:07.424545 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:56:07.430884 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:56:07.434328 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:56:07.437684 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:56:07.444403 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:56:07.447480 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:56:07.450707 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:56:07.457110 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:56:07.460581 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 23:56:07.467067 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 23:56:07.470002 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 23:56:07.473625 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 23:56:07.476953 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 23:56:07.483608 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8437 23:56:07.486887 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8438 23:56:07.489895 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8439 23:56:07.493952 Total UI for P1: 0, mck2ui 16
8440 23:56:07.497379 best dqsien dly found for B0: ( 1, 9, 10)
8441 23:56:07.503315 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 23:56:07.506730 Total UI for P1: 0, mck2ui 16
8443 23:56:07.510302 best dqsien dly found for B1: ( 1, 9, 14)
8444 23:56:07.513056 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8445 23:56:07.517023 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8446 23:56:07.517595
8447 23:56:07.519781 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8448 23:56:07.523730 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8449 23:56:07.526549 [Gating] SW calibration Done
8450 23:56:07.527011 ==
8451 23:56:07.530043 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 23:56:07.533133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 23:56:07.533600 ==
8454 23:56:07.536354 RX Vref Scan: 0
8455 23:56:07.536813
8456 23:56:07.540066 RX Vref 0 -> 0, step: 1
8457 23:56:07.540527
8458 23:56:07.540887 RX Delay 0 -> 252, step: 8
8459 23:56:07.546333 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8460 23:56:07.549756 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8461 23:56:07.552755 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8462 23:56:07.556347 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8463 23:56:07.562617 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8464 23:56:07.566243 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8465 23:56:07.569140 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8466 23:56:07.572566 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8467 23:56:07.575929 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8468 23:56:07.579276 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8469 23:56:07.585686 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8470 23:56:07.589129 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8471 23:56:07.592164 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8472 23:56:07.595467 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8473 23:56:07.602033 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8474 23:56:07.605606 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8475 23:56:07.606045 ==
8476 23:56:07.608719 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 23:56:07.611953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 23:56:07.612417 ==
8479 23:56:07.615364 DQS Delay:
8480 23:56:07.615775 DQS0 = 0, DQS1 = 0
8481 23:56:07.616107 DQM Delay:
8482 23:56:07.618600 DQM0 = 138, DQM1 = 129
8483 23:56:07.619010 DQ Delay:
8484 23:56:07.622023 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8485 23:56:07.625222 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8486 23:56:07.631782 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8487 23:56:07.635561 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8488 23:56:07.636077
8489 23:56:07.636554
8490 23:56:07.636970 ==
8491 23:56:07.638356 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:56:07.641927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:56:07.642496 ==
8494 23:56:07.642833
8495 23:56:07.643137
8496 23:56:07.645251 TX Vref Scan disable
8497 23:56:07.648302 == TX Byte 0 ==
8498 23:56:07.651536 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8499 23:56:07.655277 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8500 23:56:07.658350 == TX Byte 1 ==
8501 23:56:07.661552 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8502 23:56:07.665208 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8503 23:56:07.665731 ==
8504 23:56:07.668539 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 23:56:07.674984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 23:56:07.675497 ==
8507 23:56:07.685000
8508 23:56:07.688408 TX Vref early break, caculate TX vref
8509 23:56:07.691496 TX Vref=16, minBit 0, minWin=21, winSum=376
8510 23:56:07.695080 TX Vref=18, minBit 0, minWin=22, winSum=380
8511 23:56:07.698485 TX Vref=20, minBit 0, minWin=22, winSum=387
8512 23:56:07.701528 TX Vref=22, minBit 0, minWin=23, winSum=403
8513 23:56:07.704638 TX Vref=24, minBit 0, minWin=24, winSum=410
8514 23:56:07.711107 TX Vref=26, minBit 0, minWin=25, winSum=418
8515 23:56:07.714570 TX Vref=28, minBit 0, minWin=24, winSum=421
8516 23:56:07.717892 TX Vref=30, minBit 5, minWin=24, winSum=412
8517 23:56:07.721150 TX Vref=32, minBit 0, minWin=23, winSum=395
8518 23:56:07.727420 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8519 23:56:07.727955
8520 23:56:07.730900 Final TX Range 0 Vref 26
8521 23:56:07.731358
8522 23:56:07.731724 ==
8523 23:56:07.734088 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 23:56:07.737655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 23:56:07.738255 ==
8526 23:56:07.738625
8527 23:56:07.738956
8528 23:56:07.741250 TX Vref Scan disable
8529 23:56:07.747926 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8530 23:56:07.748479 == TX Byte 0 ==
8531 23:56:07.750739 u2DelayCellOfst[0]=18 cells (5 PI)
8532 23:56:07.754244 u2DelayCellOfst[1]=11 cells (3 PI)
8533 23:56:07.757471 u2DelayCellOfst[2]=0 cells (0 PI)
8534 23:56:07.760945 u2DelayCellOfst[3]=3 cells (1 PI)
8535 23:56:07.763903 u2DelayCellOfst[4]=7 cells (2 PI)
8536 23:56:07.767655 u2DelayCellOfst[5]=22 cells (6 PI)
8537 23:56:07.770467 u2DelayCellOfst[6]=18 cells (5 PI)
8538 23:56:07.770924 u2DelayCellOfst[7]=3 cells (1 PI)
8539 23:56:07.777595 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8540 23:56:07.780365 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8541 23:56:07.783730 == TX Byte 1 ==
8542 23:56:07.784284 u2DelayCellOfst[8]=0 cells (0 PI)
8543 23:56:07.787297 u2DelayCellOfst[9]=3 cells (1 PI)
8544 23:56:07.790341 u2DelayCellOfst[10]=11 cells (3 PI)
8545 23:56:07.793845 u2DelayCellOfst[11]=3 cells (1 PI)
8546 23:56:07.796968 u2DelayCellOfst[12]=14 cells (4 PI)
8547 23:56:07.800342 u2DelayCellOfst[13]=18 cells (5 PI)
8548 23:56:07.803575 u2DelayCellOfst[14]=18 cells (5 PI)
8549 23:56:07.806784 u2DelayCellOfst[15]=18 cells (5 PI)
8550 23:56:07.810090 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8551 23:56:07.816705 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8552 23:56:07.817267 DramC Write-DBI on
8553 23:56:07.817635 ==
8554 23:56:07.820111 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 23:56:07.826496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 23:56:07.826962 ==
8557 23:56:07.827330
8558 23:56:07.827669
8559 23:56:07.827999 TX Vref Scan disable
8560 23:56:07.830655 == TX Byte 0 ==
8561 23:56:07.833508 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8562 23:56:07.836912 == TX Byte 1 ==
8563 23:56:07.840034 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8564 23:56:07.843549 DramC Write-DBI off
8565 23:56:07.844095
8566 23:56:07.844453 [DATLAT]
8567 23:56:07.844850 Freq=1600, CH1 RK0
8568 23:56:07.845187
8569 23:56:07.846807 DATLAT Default: 0xf
8570 23:56:07.850306 0, 0xFFFF, sum = 0
8571 23:56:07.850903 1, 0xFFFF, sum = 0
8572 23:56:07.853548 2, 0xFFFF, sum = 0
8573 23:56:07.854125 3, 0xFFFF, sum = 0
8574 23:56:07.856802 4, 0xFFFF, sum = 0
8575 23:56:07.857267 5, 0xFFFF, sum = 0
8576 23:56:07.859997 6, 0xFFFF, sum = 0
8577 23:56:07.860568 7, 0xFFFF, sum = 0
8578 23:56:07.863110 8, 0xFFFF, sum = 0
8579 23:56:07.863579 9, 0xFFFF, sum = 0
8580 23:56:07.866310 10, 0xFFFF, sum = 0
8581 23:56:07.866778 11, 0xFFFF, sum = 0
8582 23:56:07.870330 12, 0xFFFF, sum = 0
8583 23:56:07.870891 13, 0xFFFF, sum = 0
8584 23:56:07.873567 14, 0x0, sum = 1
8585 23:56:07.874123 15, 0x0, sum = 2
8586 23:56:07.876468 16, 0x0, sum = 3
8587 23:56:07.876929 17, 0x0, sum = 4
8588 23:56:07.879895 best_step = 15
8589 23:56:07.880353
8590 23:56:07.880714 ==
8591 23:56:07.883083 Dram Type= 6, Freq= 0, CH_1, rank 0
8592 23:56:07.886059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8593 23:56:07.886559 ==
8594 23:56:07.889612 RX Vref Scan: 1
8595 23:56:07.890068
8596 23:56:07.890494 Set Vref Range= 24 -> 127
8597 23:56:07.890839
8598 23:56:07.892647 RX Vref 24 -> 127, step: 1
8599 23:56:07.893078
8600 23:56:07.896517 RX Delay 11 -> 252, step: 4
8601 23:56:07.897072
8602 23:56:07.900004 Set Vref, RX VrefLevel [Byte0]: 24
8603 23:56:07.902649 [Byte1]: 24
8604 23:56:07.903122
8605 23:56:07.906212 Set Vref, RX VrefLevel [Byte0]: 25
8606 23:56:07.909149 [Byte1]: 25
8607 23:56:07.913074
8608 23:56:07.913707 Set Vref, RX VrefLevel [Byte0]: 26
8609 23:56:07.916464 [Byte1]: 26
8610 23:56:07.920997
8611 23:56:07.921565 Set Vref, RX VrefLevel [Byte0]: 27
8612 23:56:07.924108 [Byte1]: 27
8613 23:56:07.928044
8614 23:56:07.928502 Set Vref, RX VrefLevel [Byte0]: 28
8615 23:56:07.931651 [Byte1]: 28
8616 23:56:07.936305
8617 23:56:07.936862 Set Vref, RX VrefLevel [Byte0]: 29
8618 23:56:07.939034 [Byte1]: 29
8619 23:56:07.943734
8620 23:56:07.944295 Set Vref, RX VrefLevel [Byte0]: 30
8621 23:56:07.946775 [Byte1]: 30
8622 23:56:07.951297
8623 23:56:07.951861 Set Vref, RX VrefLevel [Byte0]: 31
8624 23:56:07.954625 [Byte1]: 31
8625 23:56:07.958967
8626 23:56:07.959516 Set Vref, RX VrefLevel [Byte0]: 32
8627 23:56:07.962514 [Byte1]: 32
8628 23:56:07.966533
8629 23:56:07.966994 Set Vref, RX VrefLevel [Byte0]: 33
8630 23:56:07.970064 [Byte1]: 33
8631 23:56:07.974021
8632 23:56:07.977223 Set Vref, RX VrefLevel [Byte0]: 34
8633 23:56:07.977683 [Byte1]: 34
8634 23:56:07.982115
8635 23:56:07.982746 Set Vref, RX VrefLevel [Byte0]: 35
8636 23:56:07.984995 [Byte1]: 35
8637 23:56:07.988985
8638 23:56:07.989476 Set Vref, RX VrefLevel [Byte0]: 36
8639 23:56:07.992522 [Byte1]: 36
8640 23:56:07.996932
8641 23:56:07.997499 Set Vref, RX VrefLevel [Byte0]: 37
8642 23:56:07.999997 [Byte1]: 37
8643 23:56:08.004317
8644 23:56:08.004771 Set Vref, RX VrefLevel [Byte0]: 38
8645 23:56:08.007841 [Byte1]: 38
8646 23:56:08.011723
8647 23:56:08.012201 Set Vref, RX VrefLevel [Byte0]: 39
8648 23:56:08.015212 [Byte1]: 39
8649 23:56:08.019666
8650 23:56:08.020076 Set Vref, RX VrefLevel [Byte0]: 40
8651 23:56:08.023443 [Byte1]: 40
8652 23:56:08.027417
8653 23:56:08.027967 Set Vref, RX VrefLevel [Byte0]: 41
8654 23:56:08.030552 [Byte1]: 41
8655 23:56:08.035273
8656 23:56:08.035832 Set Vref, RX VrefLevel [Byte0]: 42
8657 23:56:08.037966 [Byte1]: 42
8658 23:56:08.042764
8659 23:56:08.043314 Set Vref, RX VrefLevel [Byte0]: 43
8660 23:56:08.045935 [Byte1]: 43
8661 23:56:08.050481
8662 23:56:08.051048 Set Vref, RX VrefLevel [Byte0]: 44
8663 23:56:08.054121 [Byte1]: 44
8664 23:56:08.057510
8665 23:56:08.057968 Set Vref, RX VrefLevel [Byte0]: 45
8666 23:56:08.061214 [Byte1]: 45
8667 23:56:08.065405
8668 23:56:08.066041 Set Vref, RX VrefLevel [Byte0]: 46
8669 23:56:08.068899 [Byte1]: 46
8670 23:56:08.072747
8671 23:56:08.076439 Set Vref, RX VrefLevel [Byte0]: 47
8672 23:56:08.079356 [Byte1]: 47
8673 23:56:08.079815
8674 23:56:08.082755 Set Vref, RX VrefLevel [Byte0]: 48
8675 23:56:08.085898 [Byte1]: 48
8676 23:56:08.086437
8677 23:56:08.089075 Set Vref, RX VrefLevel [Byte0]: 49
8678 23:56:08.092259 [Byte1]: 49
8679 23:56:08.095629
8680 23:56:08.096089 Set Vref, RX VrefLevel [Byte0]: 50
8681 23:56:08.098917 [Byte1]: 50
8682 23:56:08.103691
8683 23:56:08.104305 Set Vref, RX VrefLevel [Byte0]: 51
8684 23:56:08.106434 [Byte1]: 51
8685 23:56:08.111179
8686 23:56:08.111751 Set Vref, RX VrefLevel [Byte0]: 52
8687 23:56:08.114536 [Byte1]: 52
8688 23:56:08.118947
8689 23:56:08.119553 Set Vref, RX VrefLevel [Byte0]: 53
8690 23:56:08.121950 [Byte1]: 53
8691 23:56:08.126357
8692 23:56:08.126813 Set Vref, RX VrefLevel [Byte0]: 54
8693 23:56:08.129512 [Byte1]: 54
8694 23:56:08.134206
8695 23:56:08.134641 Set Vref, RX VrefLevel [Byte0]: 55
8696 23:56:08.137399 [Byte1]: 55
8697 23:56:08.141965
8698 23:56:08.142598 Set Vref, RX VrefLevel [Byte0]: 56
8699 23:56:08.145105 [Byte1]: 56
8700 23:56:08.149637
8701 23:56:08.150243 Set Vref, RX VrefLevel [Byte0]: 57
8702 23:56:08.152824 [Byte1]: 57
8703 23:56:08.156997
8704 23:56:08.157555 Set Vref, RX VrefLevel [Byte0]: 58
8705 23:56:08.159777 [Byte1]: 58
8706 23:56:08.164476
8707 23:56:08.165027 Set Vref, RX VrefLevel [Byte0]: 59
8708 23:56:08.167561 [Byte1]: 59
8709 23:56:08.172087
8710 23:56:08.175075 Set Vref, RX VrefLevel [Byte0]: 60
8711 23:56:08.178117 [Byte1]: 60
8712 23:56:08.178668
8713 23:56:08.181700 Set Vref, RX VrefLevel [Byte0]: 61
8714 23:56:08.184887 [Byte1]: 61
8715 23:56:08.185481
8716 23:56:08.188260 Set Vref, RX VrefLevel [Byte0]: 62
8717 23:56:08.191386 [Byte1]: 62
8718 23:56:08.194711
8719 23:56:08.195171 Set Vref, RX VrefLevel [Byte0]: 63
8720 23:56:08.197995 [Byte1]: 63
8721 23:56:08.202055
8722 23:56:08.202558 Set Vref, RX VrefLevel [Byte0]: 64
8723 23:56:08.206149 [Byte1]: 64
8724 23:56:08.210307
8725 23:56:08.210765 Set Vref, RX VrefLevel [Byte0]: 65
8726 23:56:08.213092 [Byte1]: 65
8727 23:56:08.217899
8728 23:56:08.218504 Set Vref, RX VrefLevel [Byte0]: 66
8729 23:56:08.221406 [Byte1]: 66
8730 23:56:08.225688
8731 23:56:08.226296 Set Vref, RX VrefLevel [Byte0]: 67
8732 23:56:08.228496 [Byte1]: 67
8733 23:56:08.232572
8734 23:56:08.233030 Set Vref, RX VrefLevel [Byte0]: 68
8735 23:56:08.236238 [Byte1]: 68
8736 23:56:08.240498
8737 23:56:08.241049 Set Vref, RX VrefLevel [Byte0]: 69
8738 23:56:08.243955 [Byte1]: 69
8739 23:56:08.248101
8740 23:56:08.248652 Set Vref, RX VrefLevel [Byte0]: 70
8741 23:56:08.251144 [Byte1]: 70
8742 23:56:08.255734
8743 23:56:08.256192 Set Vref, RX VrefLevel [Byte0]: 71
8744 23:56:08.258843 [Byte1]: 71
8745 23:56:08.263383
8746 23:56:08.263933 Set Vref, RX VrefLevel [Byte0]: 72
8747 23:56:08.266861 [Byte1]: 72
8748 23:56:08.270804
8749 23:56:08.271326 Final RX Vref Byte 0 = 51 to rank0
8750 23:56:08.274392 Final RX Vref Byte 1 = 58 to rank0
8751 23:56:08.277337 Final RX Vref Byte 0 = 51 to rank1
8752 23:56:08.280916 Final RX Vref Byte 1 = 58 to rank1==
8753 23:56:08.283917 Dram Type= 6, Freq= 0, CH_1, rank 0
8754 23:56:08.290686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 23:56:08.291201 ==
8756 23:56:08.291537 DQS Delay:
8757 23:56:08.293591 DQS0 = 0, DQS1 = 0
8758 23:56:08.294036 DQM Delay:
8759 23:56:08.294403 DQM0 = 134, DQM1 = 129
8760 23:56:08.297422 DQ Delay:
8761 23:56:08.300192 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =132
8762 23:56:08.303573 DQ4 =132, DQ5 =148, DQ6 =142, DQ7 =128
8763 23:56:08.306746 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =118
8764 23:56:08.309870 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8765 23:56:08.310338
8766 23:56:08.310672
8767 23:56:08.310973
8768 23:56:08.313666 [DramC_TX_OE_Calibration] TA2
8769 23:56:08.316494 Original DQ_B0 (3 6) =30, OEN = 27
8770 23:56:08.320146 Original DQ_B1 (3 6) =30, OEN = 27
8771 23:56:08.323558 24, 0x0, End_B0=24 End_B1=24
8772 23:56:08.326542 25, 0x0, End_B0=25 End_B1=25
8773 23:56:08.326961 26, 0x0, End_B0=26 End_B1=26
8774 23:56:08.330324 27, 0x0, End_B0=27 End_B1=27
8775 23:56:08.333313 28, 0x0, End_B0=28 End_B1=28
8776 23:56:08.336494 29, 0x0, End_B0=29 End_B1=29
8777 23:56:08.340040 30, 0x0, End_B0=30 End_B1=30
8778 23:56:08.340554 31, 0x4141, End_B0=30 End_B1=30
8779 23:56:08.342870 Byte0 end_step=30 best_step=27
8780 23:56:08.346319 Byte1 end_step=30 best_step=27
8781 23:56:08.349756 Byte0 TX OE(2T, 0.5T) = (3, 3)
8782 23:56:08.352824 Byte1 TX OE(2T, 0.5T) = (3, 3)
8783 23:56:08.353240
8784 23:56:08.353564
8785 23:56:08.359525 [DQSOSCAuto] RK0, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8786 23:56:08.363032 CH1 RK0: MR19=303, MR18=180D
8787 23:56:08.369536 CH1_RK0: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8788 23:56:08.370048
8789 23:56:08.372865 ----->DramcWriteLeveling(PI) begin...
8790 23:56:08.373376 ==
8791 23:56:08.376303 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 23:56:08.379329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 23:56:08.379748 ==
8794 23:56:08.382660 Write leveling (Byte 0): 24 => 24
8795 23:56:08.385972 Write leveling (Byte 1): 26 => 26
8796 23:56:08.389176 DramcWriteLeveling(PI) end<-----
8797 23:56:08.389587
8798 23:56:08.390008 ==
8799 23:56:08.392232 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 23:56:08.398977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 23:56:08.399475 ==
8802 23:56:08.402207 [Gating] SW mode calibration
8803 23:56:08.409017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8804 23:56:08.412128 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8805 23:56:08.418684 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 23:56:08.421751 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 23:56:08.425063 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 23:56:08.431869 1 4 12 | B1->B0 | 3333 2423 | 1 1 | (1 1) (0 0)
8809 23:56:08.434963 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 23:56:08.438489 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 23:56:08.445179 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 23:56:08.448151 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 23:56:08.451481 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 23:56:08.457845 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 23:56:08.461499 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8816 23:56:08.464775 1 5 12 | B1->B0 | 2929 3434 | 0 1 | (0 1) (1 0)
8817 23:56:08.471445 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8818 23:56:08.474474 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 23:56:08.478007 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 23:56:08.484446 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 23:56:08.487659 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 23:56:08.491056 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 23:56:08.497716 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 23:56:08.500875 1 6 12 | B1->B0 | 4545 2626 | 0 1 | (0 0) (0 0)
8825 23:56:08.504265 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 23:56:08.510951 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 23:56:08.513718 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 23:56:08.517195 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 23:56:08.525077 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 23:56:08.527010 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 23:56:08.530114 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8832 23:56:08.536587 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8833 23:56:08.540125 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8834 23:56:08.543604 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:56:08.550247 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:56:08.553378 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:56:08.556792 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 23:56:08.563217 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 23:56:08.566115 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 23:56:08.569632 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 23:56:08.576317 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 23:56:08.579470 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 23:56:08.582705 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 23:56:08.589783 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 23:56:08.593133 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 23:56:08.596215 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 23:56:08.602265 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8848 23:56:08.606266 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8849 23:56:08.609506 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8850 23:56:08.615938 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 23:56:08.618852 Total UI for P1: 0, mck2ui 16
8852 23:56:08.622660 best dqsien dly found for B0: ( 1, 9, 14)
8853 23:56:08.625428 Total UI for P1: 0, mck2ui 16
8854 23:56:08.629057 best dqsien dly found for B1: ( 1, 9, 12)
8855 23:56:08.632577 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8856 23:56:08.635509 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8857 23:56:08.635965
8858 23:56:08.638881 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8859 23:56:08.642496 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8860 23:56:08.645173 [Gating] SW calibration Done
8861 23:56:08.645587 ==
8862 23:56:08.648693 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 23:56:08.651961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 23:56:08.652418 ==
8865 23:56:08.655297 RX Vref Scan: 0
8866 23:56:08.655726
8867 23:56:08.658455 RX Vref 0 -> 0, step: 1
8868 23:56:08.658998
8869 23:56:08.659469 RX Delay 0 -> 252, step: 8
8870 23:56:08.665468 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8871 23:56:08.668578 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8872 23:56:08.671871 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8873 23:56:08.674899 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8874 23:56:08.678318 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8875 23:56:08.685229 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8876 23:56:08.688032 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8877 23:56:08.691251 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8878 23:56:08.695022 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8879 23:56:08.697980 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8880 23:56:08.704821 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8881 23:56:08.707875 iDelay=208, Bit 11, Center 115 (56 ~ 175) 120
8882 23:56:08.711148 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8883 23:56:08.714459 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8884 23:56:08.721357 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8885 23:56:08.724546 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8886 23:56:08.725172 ==
8887 23:56:08.727934 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 23:56:08.731001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 23:56:08.731314 ==
8890 23:56:08.734542 DQS Delay:
8891 23:56:08.734838 DQS0 = 0, DQS1 = 0
8892 23:56:08.735072 DQM Delay:
8893 23:56:08.737344 DQM0 = 136, DQM1 = 128
8894 23:56:08.737640 DQ Delay:
8895 23:56:08.741263 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8896 23:56:08.744766 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8897 23:56:08.748032 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =115
8898 23:56:08.754108 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8899 23:56:08.754669
8900 23:56:08.755173
8901 23:56:08.755525 ==
8902 23:56:08.757490 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 23:56:08.760864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 23:56:08.761448 ==
8905 23:56:08.761798
8906 23:56:08.762105
8907 23:56:08.764069 TX Vref Scan disable
8908 23:56:08.764625 == TX Byte 0 ==
8909 23:56:08.770795 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8910 23:56:08.774011 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8911 23:56:08.777414 == TX Byte 1 ==
8912 23:56:08.780701 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8913 23:56:08.783894 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 23:56:08.784314 ==
8915 23:56:08.787136 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 23:56:08.790653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 23:56:08.793672 ==
8918 23:56:08.804770
8919 23:56:08.807943 TX Vref early break, caculate TX vref
8920 23:56:08.811372 TX Vref=16, minBit 1, minWin=22, winSum=384
8921 23:56:08.814610 TX Vref=18, minBit 0, minWin=24, winSum=396
8922 23:56:08.818087 TX Vref=20, minBit 0, minWin=24, winSum=403
8923 23:56:08.821353 TX Vref=22, minBit 1, minWin=24, winSum=414
8924 23:56:08.824926 TX Vref=24, minBit 5, minWin=25, winSum=421
8925 23:56:08.831051 TX Vref=26, minBit 0, minWin=25, winSum=426
8926 23:56:08.834404 TX Vref=28, minBit 0, minWin=25, winSum=428
8927 23:56:08.838038 TX Vref=30, minBit 0, minWin=25, winSum=417
8928 23:56:08.840571 TX Vref=32, minBit 0, minWin=24, winSum=408
8929 23:56:08.844414 TX Vref=34, minBit 0, minWin=23, winSum=400
8930 23:56:08.850779 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8931 23:56:08.851322
8932 23:56:08.854197 Final TX Range 0 Vref 28
8933 23:56:08.854664
8934 23:56:08.855029 ==
8935 23:56:08.857188 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 23:56:08.860524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 23:56:08.860988 ==
8938 23:56:08.861377
8939 23:56:08.861743
8940 23:56:08.863787 TX Vref Scan disable
8941 23:56:08.870742 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8942 23:56:08.871297 == TX Byte 0 ==
8943 23:56:08.873866 u2DelayCellOfst[0]=18 cells (5 PI)
8944 23:56:08.877090 u2DelayCellOfst[1]=11 cells (3 PI)
8945 23:56:08.880158 u2DelayCellOfst[2]=0 cells (0 PI)
8946 23:56:08.883819 u2DelayCellOfst[3]=7 cells (2 PI)
8947 23:56:08.886639 u2DelayCellOfst[4]=11 cells (3 PI)
8948 23:56:08.890311 u2DelayCellOfst[5]=22 cells (6 PI)
8949 23:56:08.893532 u2DelayCellOfst[6]=22 cells (6 PI)
8950 23:56:08.896752 u2DelayCellOfst[7]=7 cells (2 PI)
8951 23:56:08.899894 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8952 23:56:08.903378 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8953 23:56:08.906598 == TX Byte 1 ==
8954 23:56:08.909901 u2DelayCellOfst[8]=0 cells (0 PI)
8955 23:56:08.913414 u2DelayCellOfst[9]=3 cells (1 PI)
8956 23:56:08.916467 u2DelayCellOfst[10]=7 cells (2 PI)
8957 23:56:08.919834 u2DelayCellOfst[11]=3 cells (1 PI)
8958 23:56:08.920333 u2DelayCellOfst[12]=11 cells (3 PI)
8959 23:56:08.922836 u2DelayCellOfst[13]=14 cells (4 PI)
8960 23:56:08.926244 u2DelayCellOfst[14]=18 cells (5 PI)
8961 23:56:08.930311 u2DelayCellOfst[15]=14 cells (4 PI)
8962 23:56:08.936061 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8963 23:56:08.939579 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8964 23:56:08.940138 DramC Write-DBI on
8965 23:56:08.942747 ==
8966 23:56:08.946314 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 23:56:08.949531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 23:56:08.950020 ==
8969 23:56:08.950425
8970 23:56:08.950767
8971 23:56:08.952494 TX Vref Scan disable
8972 23:56:08.952952 == TX Byte 0 ==
8973 23:56:08.959498 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8974 23:56:08.960053 == TX Byte 1 ==
8975 23:56:08.962951 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8976 23:56:08.965959 DramC Write-DBI off
8977 23:56:08.966562
8978 23:56:08.966940 [DATLAT]
8979 23:56:08.969124 Freq=1600, CH1 RK1
8980 23:56:08.969583
8981 23:56:08.969946 DATLAT Default: 0xf
8982 23:56:08.972616 0, 0xFFFF, sum = 0
8983 23:56:08.973172 1, 0xFFFF, sum = 0
8984 23:56:08.976028 2, 0xFFFF, sum = 0
8985 23:56:08.976584 3, 0xFFFF, sum = 0
8986 23:56:08.979088 4, 0xFFFF, sum = 0
8987 23:56:08.982285 5, 0xFFFF, sum = 0
8988 23:56:08.982767 6, 0xFFFF, sum = 0
8989 23:56:08.985637 7, 0xFFFF, sum = 0
8990 23:56:08.986106 8, 0xFFFF, sum = 0
8991 23:56:08.988807 9, 0xFFFF, sum = 0
8992 23:56:08.989275 10, 0xFFFF, sum = 0
8993 23:56:08.992445 11, 0xFFFF, sum = 0
8994 23:56:08.993037 12, 0xFFFF, sum = 0
8995 23:56:08.995987 13, 0xFFFF, sum = 0
8996 23:56:08.996454 14, 0x0, sum = 1
8997 23:56:08.998915 15, 0x0, sum = 2
8998 23:56:08.999381 16, 0x0, sum = 3
8999 23:56:09.002356 17, 0x0, sum = 4
9000 23:56:09.002822 best_step = 15
9001 23:56:09.003189
9002 23:56:09.003530 ==
9003 23:56:09.005859 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 23:56:09.008822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 23:56:09.012508 ==
9006 23:56:09.013013 RX Vref Scan: 0
9007 23:56:09.013488
9008 23:56:09.015392 RX Vref 0 -> 0, step: 1
9009 23:56:09.015864
9010 23:56:09.018747 RX Delay 11 -> 252, step: 4
9011 23:56:09.021904 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9012 23:56:09.025326 iDelay=203, Bit 1, Center 126 (75 ~ 178) 104
9013 23:56:09.028387 iDelay=203, Bit 2, Center 120 (67 ~ 174) 108
9014 23:56:09.035491 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9015 23:56:09.038580 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9016 23:56:09.041963 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9017 23:56:09.044929 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9018 23:56:09.048372 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9019 23:56:09.054791 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9020 23:56:09.058429 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9021 23:56:09.061369 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9022 23:56:09.065046 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9023 23:56:09.068068 iDelay=203, Bit 12, Center 136 (79 ~ 194) 116
9024 23:56:09.074912 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9025 23:56:09.078221 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9026 23:56:09.081450 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9027 23:56:09.081970 ==
9028 23:56:09.084586 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 23:56:09.091028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 23:56:09.091582 ==
9031 23:56:09.091953 DQS Delay:
9032 23:56:09.092295 DQS0 = 0, DQS1 = 0
9033 23:56:09.094359 DQM Delay:
9034 23:56:09.094853 DQM0 = 133, DQM1 = 126
9035 23:56:09.097718 DQ Delay:
9036 23:56:09.100835 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
9037 23:56:09.104432 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9038 23:56:09.107586 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9039 23:56:09.110854 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
9040 23:56:09.111331
9041 23:56:09.111823
9042 23:56:09.112271
9043 23:56:09.114058 [DramC_TX_OE_Calibration] TA2
9044 23:56:09.117375 Original DQ_B0 (3 6) =30, OEN = 27
9045 23:56:09.120514 Original DQ_B1 (3 6) =30, OEN = 27
9046 23:56:09.124320 24, 0x0, End_B0=24 End_B1=24
9047 23:56:09.124895 25, 0x0, End_B0=25 End_B1=25
9048 23:56:09.127272 26, 0x0, End_B0=26 End_B1=26
9049 23:56:09.130526 27, 0x0, End_B0=27 End_B1=27
9050 23:56:09.133936 28, 0x0, End_B0=28 End_B1=28
9051 23:56:09.137543 29, 0x0, End_B0=29 End_B1=29
9052 23:56:09.138080 30, 0x0, End_B0=30 End_B1=30
9053 23:56:09.140503 31, 0x4141, End_B0=30 End_B1=30
9054 23:56:09.143999 Byte0 end_step=30 best_step=27
9055 23:56:09.147640 Byte1 end_step=30 best_step=27
9056 23:56:09.150344 Byte0 TX OE(2T, 0.5T) = (3, 3)
9057 23:56:09.153870 Byte1 TX OE(2T, 0.5T) = (3, 3)
9058 23:56:09.154479
9059 23:56:09.154928
9060 23:56:09.160148 [DQSOSCAuto] RK1, (LSB)MR18= 0xb06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9061 23:56:09.163683 CH1 RK1: MR19=303, MR18=B06
9062 23:56:09.170329 CH1_RK1: MR19=0x303, MR18=0xB06, DQSOSC=404, MR23=63, INC=22, DEC=15
9063 23:56:09.173201 [RxdqsGatingPostProcess] freq 1600
9064 23:56:09.177099 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9065 23:56:09.179932 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 23:56:09.183273 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 23:56:09.186898 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 23:56:09.189991 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 23:56:09.193786 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 23:56:09.196588 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 23:56:09.199639 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 23:56:09.203126 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 23:56:09.206345 Pre-setting of DQS Precalculation
9074 23:56:09.209748 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9075 23:56:09.219556 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9076 23:56:09.226118 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 23:56:09.226641
9078 23:56:09.227114
9079 23:56:09.229392 [Calibration Summary] 3200 Mbps
9080 23:56:09.229871 CH 0, Rank 0
9081 23:56:09.232860 SW Impedance : PASS
9082 23:56:09.233430 DUTY Scan : NO K
9083 23:56:09.235988 ZQ Calibration : PASS
9084 23:56:09.239703 Jitter Meter : NO K
9085 23:56:09.240281 CBT Training : PASS
9086 23:56:09.242801 Write leveling : PASS
9087 23:56:09.245782 RX DQS gating : PASS
9088 23:56:09.246265 RX DQ/DQS(RDDQC) : PASS
9089 23:56:09.249307 TX DQ/DQS : PASS
9090 23:56:09.252336 RX DATLAT : PASS
9091 23:56:09.252813 RX DQ/DQS(Engine): PASS
9092 23:56:09.255789 TX OE : PASS
9093 23:56:09.256220 All Pass.
9094 23:56:09.256654
9095 23:56:09.259135 CH 0, Rank 1
9096 23:56:09.259571 SW Impedance : PASS
9097 23:56:09.262192 DUTY Scan : NO K
9098 23:56:09.265872 ZQ Calibration : PASS
9099 23:56:09.266433 Jitter Meter : NO K
9100 23:56:09.269602 CBT Training : PASS
9101 23:56:09.270017 Write leveling : PASS
9102 23:56:09.272512 RX DQS gating : PASS
9103 23:56:09.275962 RX DQ/DQS(RDDQC) : PASS
9104 23:56:09.276480 TX DQ/DQS : PASS
9105 23:56:09.278884 RX DATLAT : PASS
9106 23:56:09.282454 RX DQ/DQS(Engine): PASS
9107 23:56:09.282969 TX OE : PASS
9108 23:56:09.285269 All Pass.
9109 23:56:09.285683
9110 23:56:09.286011 CH 1, Rank 0
9111 23:56:09.288728 SW Impedance : PASS
9112 23:56:09.289243 DUTY Scan : NO K
9113 23:56:09.292092 ZQ Calibration : PASS
9114 23:56:09.295647 Jitter Meter : NO K
9115 23:56:09.296109 CBT Training : PASS
9116 23:56:09.298811 Write leveling : PASS
9117 23:56:09.302145 RX DQS gating : PASS
9118 23:56:09.302707 RX DQ/DQS(RDDQC) : PASS
9119 23:56:09.305301 TX DQ/DQS : PASS
9120 23:56:09.308706 RX DATLAT : PASS
9121 23:56:09.309237 RX DQ/DQS(Engine): PASS
9122 23:56:09.311864 TX OE : PASS
9123 23:56:09.312297 All Pass.
9124 23:56:09.312726
9125 23:56:09.315410 CH 1, Rank 1
9126 23:56:09.316030 SW Impedance : PASS
9127 23:56:09.318276 DUTY Scan : NO K
9128 23:56:09.321910 ZQ Calibration : PASS
9129 23:56:09.322367 Jitter Meter : NO K
9130 23:56:09.325181 CBT Training : PASS
9131 23:56:09.328791 Write leveling : PASS
9132 23:56:09.329303 RX DQS gating : PASS
9133 23:56:09.331391 RX DQ/DQS(RDDQC) : PASS
9134 23:56:09.334611 TX DQ/DQS : PASS
9135 23:56:09.335078 RX DATLAT : PASS
9136 23:56:09.337860 RX DQ/DQS(Engine): PASS
9137 23:56:09.341619 TX OE : PASS
9138 23:56:09.342237 All Pass.
9139 23:56:09.342625
9140 23:56:09.342972 DramC Write-DBI on
9141 23:56:09.345108 PER_BANK_REFRESH: Hybrid Mode
9142 23:56:09.348236 TX_TRACKING: ON
9143 23:56:09.354633 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9144 23:56:09.364636 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9145 23:56:09.371114 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 23:56:09.374432 [FAST_K] Save calibration result to emmc
9147 23:56:09.377510 sync common calibartion params.
9148 23:56:09.381280 sync cbt_mode0:1, 1:1
9149 23:56:09.381834 dram_init: ddr_geometry: 2
9150 23:56:09.384009 dram_init: ddr_geometry: 2
9151 23:56:09.387423 dram_init: ddr_geometry: 2
9152 23:56:09.390806 0:dram_rank_size:100000000
9153 23:56:09.391281 1:dram_rank_size:100000000
9154 23:56:09.397122 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9155 23:56:09.400799 DFS_SHUFFLE_HW_MODE: ON
9156 23:56:09.403825 dramc_set_vcore_voltage set vcore to 725000
9157 23:56:09.404292 Read voltage for 1600, 0
9158 23:56:09.407106 Vio18 = 0
9159 23:56:09.407620 Vcore = 725000
9160 23:56:09.407988 Vdram = 0
9161 23:56:09.410597 Vddq = 0
9162 23:56:09.411062 Vmddr = 0
9163 23:56:09.413747 switch to 3200 Mbps bootup
9164 23:56:09.414240 [DramcRunTimeConfig]
9165 23:56:09.417231 PHYPLL
9166 23:56:09.417693 DPM_CONTROL_AFTERK: ON
9167 23:56:09.420479 PER_BANK_REFRESH: ON
9168 23:56:09.423595 REFRESH_OVERHEAD_REDUCTION: ON
9169 23:56:09.424064 CMD_PICG_NEW_MODE: OFF
9170 23:56:09.427333 XRTWTW_NEW_MODE: ON
9171 23:56:09.427796 XRTRTR_NEW_MODE: ON
9172 23:56:09.430317 TX_TRACKING: ON
9173 23:56:09.430780 RDSEL_TRACKING: OFF
9174 23:56:09.433755 DQS Precalculation for DVFS: ON
9175 23:56:09.436677 RX_TRACKING: OFF
9176 23:56:09.437142 HW_GATING DBG: ON
9177 23:56:09.440467 ZQCS_ENABLE_LP4: ON
9178 23:56:09.441072 RX_PICG_NEW_MODE: ON
9179 23:56:09.443394 TX_PICG_NEW_MODE: ON
9180 23:56:09.443923 ENABLE_RX_DCM_DPHY: ON
9181 23:56:09.447017 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9182 23:56:09.449987 DUMMY_READ_FOR_TRACKING: OFF
9183 23:56:09.453687 !!! SPM_CONTROL_AFTERK: OFF
9184 23:56:09.456775 !!! SPM could not control APHY
9185 23:56:09.457339 IMPEDANCE_TRACKING: ON
9186 23:56:09.459923 TEMP_SENSOR: ON
9187 23:56:09.460387 HW_SAVE_FOR_SR: OFF
9188 23:56:09.462998 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9189 23:56:09.466634 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9190 23:56:09.469927 Read ODT Tracking: ON
9191 23:56:09.472932 Refresh Rate DeBounce: ON
9192 23:56:09.473354 DFS_NO_QUEUE_FLUSH: ON
9193 23:56:09.476603 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9194 23:56:09.480103 ENABLE_DFS_RUNTIME_MRW: OFF
9195 23:56:09.482898 DDR_RESERVE_NEW_MODE: ON
9196 23:56:09.483382 MR_CBT_SWITCH_FREQ: ON
9197 23:56:09.486000 =========================
9198 23:56:09.505248 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9199 23:56:09.508587 dram_init: ddr_geometry: 2
9200 23:56:09.526755 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9201 23:56:09.530250 dram_init: dram init end (result: 0)
9202 23:56:09.537015 DRAM-K: Full calibration passed in 24634 msecs
9203 23:56:09.540102 MRC: failed to locate region type 0.
9204 23:56:09.540556 DRAM rank0 size:0x100000000,
9205 23:56:09.543585 DRAM rank1 size=0x100000000
9206 23:56:09.553380 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9207 23:56:09.560048 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9208 23:56:09.566616 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9209 23:56:09.576552 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9210 23:56:09.577110 DRAM rank0 size:0x100000000,
9211 23:56:09.579594 DRAM rank1 size=0x100000000
9212 23:56:09.580056 CBMEM:
9213 23:56:09.582872 IMD: root @ 0xfffff000 254 entries.
9214 23:56:09.585989 IMD: root @ 0xffffec00 62 entries.
9215 23:56:09.592439 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9216 23:56:09.596506 WARNING: RO_VPD is uninitialized or empty.
9217 23:56:09.599126 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9218 23:56:09.607089 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9219 23:56:09.620055 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9220 23:56:09.631024 BS: romstage times (exec / console): total (unknown) / 24124 ms
9221 23:56:09.631568
9222 23:56:09.631932
9223 23:56:09.641139 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9224 23:56:09.644504 ARM64: Exception handlers installed.
9225 23:56:09.647955 ARM64: Testing exception
9226 23:56:09.651277 ARM64: Done test exception
9227 23:56:09.651832 Enumerating buses...
9228 23:56:09.654466 Show all devs... Before device enumeration.
9229 23:56:09.657496 Root Device: enabled 1
9230 23:56:09.660851 CPU_CLUSTER: 0: enabled 1
9231 23:56:09.661310 CPU: 00: enabled 1
9232 23:56:09.664545 Compare with tree...
9233 23:56:09.665101 Root Device: enabled 1
9234 23:56:09.667432 CPU_CLUSTER: 0: enabled 1
9235 23:56:09.670497 CPU: 00: enabled 1
9236 23:56:09.670954 Root Device scanning...
9237 23:56:09.674019 scan_static_bus for Root Device
9238 23:56:09.677451 CPU_CLUSTER: 0 enabled
9239 23:56:09.680378 scan_static_bus for Root Device done
9240 23:56:09.683897 scan_bus: bus Root Device finished in 8 msecs
9241 23:56:09.684361 done
9242 23:56:09.690557 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9243 23:56:09.693713 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9244 23:56:09.700649 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9245 23:56:09.703663 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9246 23:56:09.706867 Allocating resources...
9247 23:56:09.710118 Reading resources...
9248 23:56:09.713319 Root Device read_resources bus 0 link: 0
9249 23:56:09.716882 DRAM rank0 size:0x100000000,
9250 23:56:09.717448 DRAM rank1 size=0x100000000
9251 23:56:09.723558 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9252 23:56:09.724115 CPU: 00 missing read_resources
9253 23:56:09.730216 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9254 23:56:09.733443 Root Device read_resources bus 0 link: 0 done
9255 23:56:09.736737 Done reading resources.
9256 23:56:09.739943 Show resources in subtree (Root Device)...After reading.
9257 23:56:09.742889 Root Device child on link 0 CPU_CLUSTER: 0
9258 23:56:09.746740 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 23:56:09.755933 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 23:56:09.756486 CPU: 00
9261 23:56:09.762811 Root Device assign_resources, bus 0 link: 0
9262 23:56:09.766391 CPU_CLUSTER: 0 missing set_resources
9263 23:56:09.769540 Root Device assign_resources, bus 0 link: 0 done
9264 23:56:09.770002 Done setting resources.
9265 23:56:09.776070 Show resources in subtree (Root Device)...After assigning values.
9266 23:56:09.779123 Root Device child on link 0 CPU_CLUSTER: 0
9267 23:56:09.785954 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 23:56:09.792627 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 23:56:09.797016 CPU: 00
9270 23:56:09.797436 Done allocating resources.
9271 23:56:09.802229 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9272 23:56:09.802651 Enabling resources...
9273 23:56:09.805809 done.
9274 23:56:09.809013 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9275 23:56:09.812639 Initializing devices...
9276 23:56:09.813097 Root Device init
9277 23:56:09.815439 init hardware done!
9278 23:56:09.815853 0x00000018: ctrlr->caps
9279 23:56:09.818953 52.000 MHz: ctrlr->f_max
9280 23:56:09.822073 0.400 MHz: ctrlr->f_min
9281 23:56:09.822550 0x40ff8080: ctrlr->voltages
9282 23:56:09.826042 sclk: 390625
9283 23:56:09.826541 Bus Width = 1
9284 23:56:09.828616 sclk: 390625
9285 23:56:09.829042 Bus Width = 1
9286 23:56:09.832027 Early init status = 3
9287 23:56:09.835380 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9288 23:56:09.838635 in-header: 03 fc 00 00 01 00 00 00
9289 23:56:09.841908 in-data: 00
9290 23:56:09.845070 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9291 23:56:09.849889 in-header: 03 fd 00 00 00 00 00 00
9292 23:56:09.853280 in-data:
9293 23:56:09.856106 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9294 23:56:09.859651 in-header: 03 fc 00 00 01 00 00 00
9295 23:56:09.862853 in-data: 00
9296 23:56:09.866184 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9297 23:56:09.871013 in-header: 03 fd 00 00 00 00 00 00
9298 23:56:09.874149 in-data:
9299 23:56:09.877638 [SSUSB] Setting up USB HOST controller...
9300 23:56:09.881022 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9301 23:56:09.884484 [SSUSB] phy power-on done.
9302 23:56:09.887317 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9303 23:56:09.893896 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9304 23:56:09.897799 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9305 23:56:09.904212 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9306 23:56:09.910784 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9307 23:56:09.917658 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9308 23:56:09.923991 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9309 23:56:09.930262 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9310 23:56:09.933733 SPM: binary array size = 0x9dc
9311 23:56:09.937038 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9312 23:56:09.943903 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9313 23:56:09.950387 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9314 23:56:09.957109 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9315 23:56:09.959887 configure_display: Starting display init
9316 23:56:09.994460 anx7625_power_on_init: Init interface.
9317 23:56:09.997928 anx7625_disable_pd_protocol: Disabled PD feature.
9318 23:56:10.001051 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9319 23:56:10.028886 anx7625_start_dp_work: Secure OCM version=00
9320 23:56:10.032370 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9321 23:56:10.047247 sp_tx_get_edid_block: EDID Block = 1
9322 23:56:10.149543 Extracted contents:
9323 23:56:10.153121 header: 00 ff ff ff ff ff ff 00
9324 23:56:10.156010 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9325 23:56:10.159069 version: 01 04
9326 23:56:10.162421 basic params: 95 1f 11 78 0a
9327 23:56:10.166125 chroma info: 76 90 94 55 54 90 27 21 50 54
9328 23:56:10.169408 established: 00 00 00
9329 23:56:10.175829 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9330 23:56:10.182785 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9331 23:56:10.185790 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9332 23:56:10.192008 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9333 23:56:10.198771 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9334 23:56:10.202032 extensions: 00
9335 23:56:10.202617 checksum: fb
9336 23:56:10.203122
9337 23:56:10.208805 Manufacturer: IVO Model 57d Serial Number 0
9338 23:56:10.209365 Made week 0 of 2020
9339 23:56:10.211720 EDID version: 1.4
9340 23:56:10.212180 Digital display
9341 23:56:10.215212 6 bits per primary color channel
9342 23:56:10.218536 DisplayPort interface
9343 23:56:10.219013 Maximum image size: 31 cm x 17 cm
9344 23:56:10.221821 Gamma: 220%
9345 23:56:10.222344 Check DPMS levels
9346 23:56:10.228378 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9347 23:56:10.231620 First detailed timing is preferred timing
9348 23:56:10.234988 Established timings supported:
9349 23:56:10.235422 Standard timings supported:
9350 23:56:10.238019 Detailed timings
9351 23:56:10.241615 Hex of detail: 383680a07038204018303c0035ae10000019
9352 23:56:10.248131 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9353 23:56:10.251464 0780 0798 07c8 0820 hborder 0
9354 23:56:10.254827 0438 043b 0447 0458 vborder 0
9355 23:56:10.258206 -hsync -vsync
9356 23:56:10.258767 Did detailed timing
9357 23:56:10.264719 Hex of detail: 000000000000000000000000000000000000
9358 23:56:10.268357 Manufacturer-specified data, tag 0
9359 23:56:10.271242 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9360 23:56:10.274698 ASCII string: InfoVision
9361 23:56:10.277650 Hex of detail: 000000fe00523134304e574635205248200a
9362 23:56:10.281126 ASCII string: R140NWF5 RH
9363 23:56:10.281681 Checksum
9364 23:56:10.284157 Checksum: 0xfb (valid)
9365 23:56:10.288106 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9366 23:56:10.290838 DSI data_rate: 832800000 bps
9367 23:56:10.297291 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9368 23:56:10.300698 anx7625_parse_edid: pixelclock(138800).
9369 23:56:10.303799 hactive(1920), hsync(48), hfp(24), hbp(88)
9370 23:56:10.307452 vactive(1080), vsync(12), vfp(3), vbp(17)
9371 23:56:10.310341 anx7625_dsi_config: config dsi.
9372 23:56:10.317270 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9373 23:56:10.331183 anx7625_dsi_config: success to config DSI
9374 23:56:10.334878 anx7625_dp_start: MIPI phy setup OK.
9375 23:56:10.337779 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9376 23:56:10.341349 mtk_ddp_mode_set invalid vrefresh 60
9377 23:56:10.344764 main_disp_path_setup
9378 23:56:10.345341 ovl_layer_smi_id_en
9379 23:56:10.348324 ovl_layer_smi_id_en
9380 23:56:10.348881 ccorr_config
9381 23:56:10.349249 aal_config
9382 23:56:10.351203 gamma_config
9383 23:56:10.351660 postmask_config
9384 23:56:10.354391 dither_config
9385 23:56:10.358020 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9386 23:56:10.364483 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9387 23:56:10.367865 Root Device init finished in 551 msecs
9388 23:56:10.371773 CPU_CLUSTER: 0 init
9389 23:56:10.377780 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9390 23:56:10.384561 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9391 23:56:10.385118 APU_MBOX 0x190000b0 = 0x10001
9392 23:56:10.387539 APU_MBOX 0x190001b0 = 0x10001
9393 23:56:10.390901 APU_MBOX 0x190005b0 = 0x10001
9394 23:56:10.394554 APU_MBOX 0x190006b0 = 0x10001
9395 23:56:10.400599 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9396 23:56:10.410807 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9397 23:56:10.423151 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9398 23:56:10.429788 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9399 23:56:10.441076 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9400 23:56:10.450386 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9401 23:56:10.453584 CPU_CLUSTER: 0 init finished in 81 msecs
9402 23:56:10.456987 Devices initialized
9403 23:56:10.460188 Show all devs... After init.
9404 23:56:10.460743 Root Device: enabled 1
9405 23:56:10.463205 CPU_CLUSTER: 0: enabled 1
9406 23:56:10.466927 CPU: 00: enabled 1
9407 23:56:10.470157 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9408 23:56:10.473182 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9409 23:56:10.476744 ELOG: NV offset 0x57f000 size 0x1000
9410 23:56:10.484051 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9411 23:56:10.489727 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9412 23:56:10.493011 ELOG: Event(17) added with size 13 at 2024-05-29 23:56:10 UTC
9413 23:56:10.499755 out: cmd=0x121: 03 db 21 01 00 00 00 00
9414 23:56:10.502851 in-header: 03 28 00 00 2c 00 00 00
9415 23:56:10.512886 in-data: 14 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9416 23:56:10.519690 ELOG: Event(A1) added with size 10 at 2024-05-29 23:56:10 UTC
9417 23:56:10.526239 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9418 23:56:10.532823 ELOG: Event(A0) added with size 9 at 2024-05-29 23:56:10 UTC
9419 23:56:10.536431 elog_add_boot_reason: Logged dev mode boot
9420 23:56:10.542994 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9421 23:56:10.543555 Finalize devices...
9422 23:56:10.546425 Devices finalized
9423 23:56:10.549434 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9424 23:56:10.552897 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9425 23:56:10.556182 in-header: 03 07 00 00 08 00 00 00
9426 23:56:10.559044 in-data: aa e4 47 04 13 02 00 00
9427 23:56:10.562346 Chrome EC: UHEPI supported
9428 23:56:10.569220 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9429 23:56:10.572698 in-header: 03 a9 00 00 08 00 00 00
9430 23:56:10.575414 in-data: 84 60 60 08 00 00 00 00
9431 23:56:10.582443 ELOG: Event(91) added with size 10 at 2024-05-29 23:56:10 UTC
9432 23:56:10.585473 Chrome EC: clear events_b mask to 0x0000000020004000
9433 23:56:10.591858 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9434 23:56:10.596904 in-header: 03 fd 00 00 00 00 00 00
9435 23:56:10.600436 in-data:
9436 23:56:10.603353 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9437 23:56:10.607025 Writing coreboot table at 0xffe64000
9438 23:56:10.613745 0. 000000000010a000-0000000000113fff: RAMSTAGE
9439 23:56:10.616558 1. 0000000040000000-00000000400fffff: RAM
9440 23:56:10.620065 2. 0000000040100000-000000004032afff: RAMSTAGE
9441 23:56:10.623246 3. 000000004032b000-00000000545fffff: RAM
9442 23:56:10.626611 4. 0000000054600000-000000005465ffff: BL31
9443 23:56:10.629967 5. 0000000054660000-00000000ffe63fff: RAM
9444 23:56:10.636812 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9445 23:56:10.639862 7. 0000000100000000-000000023fffffff: RAM
9446 23:56:10.643221 Passing 5 GPIOs to payload:
9447 23:56:10.646548 NAME | PORT | POLARITY | VALUE
9448 23:56:10.653246 EC in RW | 0x000000aa | low | undefined
9449 23:56:10.656489 EC interrupt | 0x00000005 | low | undefined
9450 23:56:10.663187 TPM interrupt | 0x000000ab | high | undefined
9451 23:56:10.666129 SD card detect | 0x00000011 | high | undefined
9452 23:56:10.669664 speaker enable | 0x00000093 | high | undefined
9453 23:56:10.676105 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9454 23:56:10.679549 in-header: 03 f9 00 00 02 00 00 00
9455 23:56:10.680137 in-data: 02 00
9456 23:56:10.682708 ADC[4]: Raw value=904139 ID=7
9457 23:56:10.685955 ADC[3]: Raw value=212912 ID=1
9458 23:56:10.686564 RAM Code: 0x71
9459 23:56:10.689310 ADC[6]: Raw value=75036 ID=0
9460 23:56:10.692651 ADC[5]: Raw value=212912 ID=1
9461 23:56:10.693110 SKU Code: 0x1
9462 23:56:10.698956 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c9a9
9463 23:56:10.702406 coreboot table: 964 bytes.
9464 23:56:10.705826 IMD ROOT 0. 0xfffff000 0x00001000
9465 23:56:10.709504 IMD SMALL 1. 0xffffe000 0x00001000
9466 23:56:10.712034 RO MCACHE 2. 0xffffc000 0x00001104
9467 23:56:10.715272 CONSOLE 3. 0xfff7c000 0x00080000
9468 23:56:10.718816 FMAP 4. 0xfff7b000 0x00000452
9469 23:56:10.722353 TIME STAMP 5. 0xfff7a000 0x00000910
9470 23:56:10.725462 VBOOT WORK 6. 0xfff66000 0x00014000
9471 23:56:10.728597 RAMOOPS 7. 0xffe66000 0x00100000
9472 23:56:10.732223 COREBOOT 8. 0xffe64000 0x00002000
9473 23:56:10.732778 IMD small region:
9474 23:56:10.735355 IMD ROOT 0. 0xffffec00 0x00000400
9475 23:56:10.738738 VPD 1. 0xffffeb80 0x0000006c
9476 23:56:10.741744 MMC STATUS 2. 0xffffeb60 0x00000004
9477 23:56:10.749325 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9478 23:56:10.754840 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9479 23:56:10.794291 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9480 23:56:10.797155 Checking segment from ROM address 0x40100000
9481 23:56:10.801203 Checking segment from ROM address 0x4010001c
9482 23:56:10.807237 Loading segment from ROM address 0x40100000
9483 23:56:10.807818 code (compression=0)
9484 23:56:10.816957 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9485 23:56:10.823467 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9486 23:56:10.824003 it's not compressed!
9487 23:56:10.830456 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9488 23:56:10.836905 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9489 23:56:10.854459 Loading segment from ROM address 0x4010001c
9490 23:56:10.855062 Entry Point 0x80000000
9491 23:56:10.858243 Loaded segments
9492 23:56:10.861357 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9493 23:56:10.867561 Jumping to boot code at 0x80000000(0xffe64000)
9494 23:56:10.874374 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9495 23:56:10.880672 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9496 23:56:10.888919 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9497 23:56:10.892442 Checking segment from ROM address 0x40100000
9498 23:56:10.895504 Checking segment from ROM address 0x4010001c
9499 23:56:10.902035 Loading segment from ROM address 0x40100000
9500 23:56:10.902679 code (compression=1)
9501 23:56:10.908548 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9502 23:56:10.918273 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9503 23:56:10.918742 using LZMA
9504 23:56:10.927380 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9505 23:56:10.933929 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9506 23:56:10.936803 Loading segment from ROM address 0x4010001c
9507 23:56:10.940534 Entry Point 0x54601000
9508 23:56:10.940993 Loaded segments
9509 23:56:10.943331 NOTICE: MT8192 bl31_setup
9510 23:56:10.950669 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9511 23:56:10.954289 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9512 23:56:10.957942 WARNING: region 0:
9513 23:56:10.960761 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 23:56:10.961317 WARNING: region 1:
9515 23:56:10.967475 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9516 23:56:10.970718 WARNING: region 2:
9517 23:56:10.973461 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9518 23:56:10.977135 WARNING: region 3:
9519 23:56:10.983580 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 23:56:10.984042 WARNING: region 4:
9521 23:56:10.990368 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9522 23:56:10.990830 WARNING: region 5:
9523 23:56:10.993667 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 23:56:10.996732 WARNING: region 6:
9525 23:56:11.000278 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 23:56:11.003429 WARNING: region 7:
9527 23:56:11.006357 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 23:56:11.013288 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9529 23:56:11.016584 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9530 23:56:11.023172 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9531 23:56:11.026608 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9532 23:56:11.029746 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9533 23:56:11.036572 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9534 23:56:11.039792 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9535 23:56:11.042904 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9536 23:56:11.049455 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9537 23:56:11.052554 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9538 23:56:11.059095 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9539 23:56:11.062431 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9540 23:56:11.066211 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9541 23:56:11.072278 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9542 23:56:11.075452 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9543 23:56:11.082562 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9544 23:56:11.085685 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9545 23:56:11.088814 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9546 23:56:11.095980 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9547 23:56:11.099091 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9548 23:56:11.105531 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9549 23:56:11.108805 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9550 23:56:11.112667 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9551 23:56:11.118754 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9552 23:56:11.121889 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9553 23:56:11.128931 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9554 23:56:11.131682 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9555 23:56:11.135444 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9556 23:56:11.141864 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9557 23:56:11.145472 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9558 23:56:11.151441 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9559 23:56:11.154735 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9560 23:56:11.158035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9561 23:56:11.164801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9562 23:56:11.168062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9563 23:56:11.171422 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9564 23:56:11.175001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9565 23:56:11.180885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9566 23:56:11.184468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9567 23:56:11.187601 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9568 23:56:11.190920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9569 23:56:11.197667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9570 23:56:11.200647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9571 23:56:11.204528 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9572 23:56:11.208076 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9573 23:56:11.214007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9574 23:56:11.217534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9575 23:56:11.220865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9576 23:56:11.227420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9577 23:56:11.230457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9578 23:56:11.237327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9579 23:56:11.240504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9580 23:56:11.246901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9581 23:56:11.250272 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9582 23:56:11.254071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9583 23:56:11.260531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9584 23:56:11.263757 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9585 23:56:11.270204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9586 23:56:11.273480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9587 23:56:11.279964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9588 23:56:11.283389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9589 23:56:11.289858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9590 23:56:11.293181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9591 23:56:11.296571 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9592 23:56:11.302797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9593 23:56:11.306318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9594 23:56:11.313202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9595 23:56:11.316309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9596 23:56:11.322981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9597 23:56:11.326062 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9598 23:56:11.333722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9599 23:56:11.336388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9600 23:56:11.339597 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9601 23:56:11.346239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9602 23:56:11.349888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9603 23:56:11.356591 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9604 23:56:11.359475 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9605 23:56:11.366340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9606 23:56:11.369033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9607 23:56:11.376007 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9608 23:56:11.379272 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9609 23:56:11.382363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9610 23:56:11.389157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9611 23:56:11.392150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9612 23:56:11.398610 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9613 23:56:11.402449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9614 23:56:11.408852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9615 23:56:11.412484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9616 23:56:11.418758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9617 23:56:11.421910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9618 23:56:11.425279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9619 23:56:11.432202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9620 23:56:11.435263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9621 23:56:11.441643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9622 23:56:11.444882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9623 23:56:11.451745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9624 23:56:11.454753 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9625 23:56:11.458115 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9626 23:56:11.464788 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9627 23:56:11.467825 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9628 23:56:11.471428 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9629 23:56:11.474893 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9630 23:56:11.481065 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9631 23:56:11.484501 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9632 23:56:11.491213 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9633 23:56:11.494458 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9634 23:56:11.500819 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9635 23:56:11.504100 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9636 23:56:11.507730 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9637 23:56:11.513891 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9638 23:56:11.517630 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9639 23:56:11.524426 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9640 23:56:11.527717 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9641 23:56:11.530761 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9642 23:56:11.537654 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9643 23:56:11.540738 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9644 23:56:11.544409 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9645 23:56:11.550612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9646 23:56:11.553867 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9647 23:56:11.557309 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9648 23:56:11.563915 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9649 23:56:11.567354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9650 23:56:11.570259 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9651 23:56:11.573623 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9652 23:56:11.580197 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9653 23:56:11.583445 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9654 23:56:11.590483 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9655 23:56:11.593452 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9656 23:56:11.599958 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9657 23:56:11.603176 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9658 23:56:11.606449 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9659 23:56:11.613150 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9660 23:56:11.616849 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9661 23:56:11.619506 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9662 23:56:11.626527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9663 23:56:11.629326 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9664 23:56:11.636315 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9665 23:56:11.639459 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9666 23:56:11.642639 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9667 23:56:11.649609 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9668 23:56:11.652826 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9669 23:56:11.659157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9670 23:56:11.662490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9671 23:56:11.669558 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9672 23:56:11.672911 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9673 23:56:11.675556 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9674 23:56:11.682151 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9675 23:56:11.685686 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9676 23:56:11.689081 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9677 23:56:11.695562 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9678 23:56:11.699374 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9679 23:56:11.705825 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9680 23:56:11.708559 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9681 23:56:11.712392 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9682 23:56:11.718612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9683 23:56:11.721952 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9684 23:56:11.728804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9685 23:56:11.732010 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9686 23:56:11.735508 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9687 23:56:11.742205 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9688 23:56:11.745397 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9689 23:56:11.752542 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9690 23:56:11.754994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9691 23:56:11.758251 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9692 23:56:11.764697 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9693 23:56:11.767994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9694 23:56:11.774836 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9695 23:56:11.778320 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9696 23:56:11.781205 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9697 23:56:11.787977 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9698 23:56:11.791366 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9699 23:56:11.797709 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9700 23:56:11.801069 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9701 23:56:11.804324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9702 23:56:11.810756 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9703 23:56:11.814098 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9704 23:56:11.821411 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9705 23:56:11.824501 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9706 23:56:11.827534 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9707 23:56:11.834109 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9708 23:56:11.837404 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9709 23:56:11.844151 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9710 23:56:11.847337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9711 23:56:11.850850 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9712 23:56:11.857504 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9713 23:56:11.860928 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9714 23:56:11.867202 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9715 23:56:11.870843 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9716 23:56:11.874057 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9717 23:56:11.880702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9718 23:56:11.883607 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9719 23:56:11.890049 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9720 23:56:11.893271 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9721 23:56:11.900347 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9722 23:56:11.903262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9723 23:56:11.906551 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9724 23:56:11.913358 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9725 23:56:11.916613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9726 23:56:11.923159 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9727 23:56:11.926771 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9728 23:56:11.933322 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9729 23:56:11.936282 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9730 23:56:11.939657 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9731 23:56:11.946022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9732 23:56:11.949815 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9733 23:56:11.956148 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9734 23:56:11.959429 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9735 23:56:11.965994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9736 23:56:11.968978 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9737 23:56:11.972732 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9738 23:56:11.979153 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9739 23:56:11.982627 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9740 23:56:11.989712 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9741 23:56:11.992511 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9742 23:56:11.999113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9743 23:56:12.002352 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9744 23:56:12.005659 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9745 23:56:12.012345 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9746 23:56:12.015712 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9747 23:56:12.022059 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9748 23:56:12.025420 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9749 23:56:12.031820 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9750 23:56:12.035586 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9751 23:56:12.038402 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9752 23:56:12.045256 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9753 23:56:12.048912 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9754 23:56:12.055278 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9755 23:56:12.058810 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9756 23:56:12.064802 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9757 23:56:12.068017 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9758 23:56:12.071533 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9759 23:56:12.075170 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9760 23:56:12.078336 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9761 23:56:12.084877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9762 23:56:12.088297 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9763 23:56:12.091353 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9764 23:56:12.097872 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9765 23:56:12.101319 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9766 23:56:12.104758 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9767 23:56:12.111216 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9768 23:56:12.114725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9769 23:56:12.121084 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9770 23:56:12.124665 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9771 23:56:12.127528 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9772 23:56:12.134460 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9773 23:56:12.137658 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9774 23:56:12.144495 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9775 23:56:12.147765 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9776 23:56:12.150992 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9777 23:56:12.157681 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9778 23:56:12.160936 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9779 23:56:12.164558 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9780 23:56:12.170923 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9781 23:56:12.173870 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9782 23:56:12.177303 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9783 23:56:12.184055 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9784 23:56:12.187361 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9785 23:56:12.193983 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9786 23:56:12.196924 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9787 23:56:12.200859 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9788 23:56:12.206746 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9789 23:56:12.209950 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9790 23:56:12.216681 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9791 23:56:12.219891 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9792 23:56:12.223293 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9793 23:56:12.230066 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9794 23:56:12.232988 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9795 23:56:12.236457 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9796 23:56:12.243130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9797 23:56:12.246633 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9798 23:56:12.250146 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9799 23:56:12.253002 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9800 23:56:12.259772 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9801 23:56:12.262866 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9802 23:56:12.266227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9803 23:56:12.269842 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9804 23:56:12.276808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9805 23:56:12.279561 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9806 23:56:12.282544 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9807 23:56:12.286016 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9808 23:56:12.293129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9809 23:56:12.295978 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9810 23:56:12.299366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9811 23:56:12.305575 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9812 23:56:12.309173 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9813 23:56:12.315846 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9814 23:56:12.318966 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9815 23:56:12.325813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9816 23:56:12.329132 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9817 23:56:12.332230 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9818 23:56:12.339209 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9819 23:56:12.342083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9820 23:56:12.348860 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9821 23:56:12.352066 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9822 23:56:12.358540 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9823 23:56:12.361648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9824 23:56:12.365160 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9825 23:56:12.371806 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9826 23:56:12.374770 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9827 23:56:12.381529 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9828 23:56:12.384753 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9829 23:56:12.388305 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9830 23:56:12.394916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9831 23:56:12.397953 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9832 23:56:12.404383 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9833 23:56:12.407777 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9834 23:56:12.411581 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9835 23:56:12.417666 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9836 23:56:12.421366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9837 23:56:12.427830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9838 23:56:12.430952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9839 23:56:12.438305 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9840 23:56:12.441713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9841 23:56:12.444462 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9842 23:56:12.450813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9843 23:56:12.454219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9844 23:56:12.461327 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9845 23:56:12.464533 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9846 23:56:12.467570 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9847 23:56:12.474434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9848 23:56:12.477324 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9849 23:56:12.484491 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9850 23:56:12.487317 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9851 23:56:12.494233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9852 23:56:12.497160 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9853 23:56:12.500828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9854 23:56:12.507229 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9855 23:56:12.510813 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9856 23:56:12.517612 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9857 23:56:12.520828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9858 23:56:12.523847 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9859 23:56:12.530994 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9860 23:56:12.533657 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9861 23:56:12.540538 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9862 23:56:12.543781 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9863 23:56:12.550534 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9864 23:56:12.554081 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9865 23:56:12.556730 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9866 23:56:12.564064 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9867 23:56:12.566579 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9868 23:56:12.573652 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9869 23:56:12.576402 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9870 23:56:12.579868 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9871 23:56:12.586874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9872 23:56:12.589961 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9873 23:56:12.596213 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9874 23:56:12.599467 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9875 23:56:12.602981 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9876 23:56:12.609408 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9877 23:56:12.613399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9878 23:56:12.619729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9879 23:56:12.622986 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9880 23:56:12.629295 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9881 23:56:12.632534 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9882 23:56:12.635942 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9883 23:56:12.642794 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9884 23:56:12.646005 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9885 23:56:12.652726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9886 23:56:12.655443 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9887 23:56:12.662303 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9888 23:56:12.666315 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9889 23:56:12.672211 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9890 23:56:12.675528 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9891 23:56:12.678730 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9892 23:56:12.685435 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9893 23:56:12.688611 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9894 23:56:12.695113 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9895 23:56:12.698640 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9896 23:56:12.705096 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9897 23:56:12.708376 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9898 23:56:12.715232 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9899 23:56:12.718348 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9900 23:56:12.721426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9901 23:56:12.728022 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9902 23:56:12.731210 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9903 23:56:12.738093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9904 23:56:12.741377 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9905 23:56:12.747870 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9906 23:56:12.750995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9907 23:56:12.757969 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9908 23:56:12.761374 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9909 23:56:12.767584 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9910 23:56:12.770937 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9911 23:56:12.774280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9912 23:56:12.780827 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9913 23:56:12.784541 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9914 23:56:12.790860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9915 23:56:12.794272 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9916 23:56:12.800949 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9917 23:56:12.804340 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9918 23:56:12.810802 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9919 23:56:12.813970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9920 23:56:12.817194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9921 23:56:12.824084 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9922 23:56:12.827255 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9923 23:56:12.833591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9924 23:56:12.837124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9925 23:56:12.843914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9926 23:56:12.846922 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9927 23:56:12.853387 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9928 23:56:12.856919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9929 23:56:12.860040 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9930 23:56:12.866468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9931 23:56:12.870211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9932 23:56:12.876631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9933 23:56:12.879718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9934 23:56:12.886531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9935 23:56:12.889884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9936 23:56:12.896247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9937 23:56:12.900017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9938 23:56:12.906336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9939 23:56:12.909877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9940 23:56:12.913279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9941 23:56:12.919512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9942 23:56:12.923039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9943 23:56:12.929264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9944 23:56:12.932817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9945 23:56:12.938938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9946 23:56:12.942545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9947 23:56:12.949120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9948 23:56:12.952381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9949 23:56:12.959354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9950 23:56:12.962419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9951 23:56:12.968683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9952 23:56:12.972213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9953 23:56:12.978900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9954 23:56:12.982259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9955 23:56:12.989168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9956 23:56:12.991866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9957 23:56:12.998570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9958 23:56:13.005483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9959 23:56:13.008300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9960 23:56:13.015327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9961 23:56:13.018570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9962 23:56:13.021770 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9963 23:56:13.025055 INFO: [APUAPC] vio 0
9964 23:56:13.028076 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9965 23:56:13.035225 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9966 23:56:13.038242 INFO: [APUAPC] D0_APC_0: 0x400510
9967 23:56:13.041804 INFO: [APUAPC] D0_APC_1: 0x0
9968 23:56:13.044849 INFO: [APUAPC] D0_APC_2: 0x1540
9969 23:56:13.045383 INFO: [APUAPC] D0_APC_3: 0x0
9970 23:56:13.051507 INFO: [APUAPC] D1_APC_0: 0xffffffff
9971 23:56:13.054742 INFO: [APUAPC] D1_APC_1: 0xffffffff
9972 23:56:13.058326 INFO: [APUAPC] D1_APC_2: 0x3fffff
9973 23:56:13.058886 INFO: [APUAPC] D1_APC_3: 0x0
9974 23:56:13.061356 INFO: [APUAPC] D2_APC_0: 0xffffffff
9975 23:56:13.067902 INFO: [APUAPC] D2_APC_1: 0xffffffff
9976 23:56:13.071334 INFO: [APUAPC] D2_APC_2: 0x3fffff
9977 23:56:13.071802 INFO: [APUAPC] D2_APC_3: 0x0
9978 23:56:13.074554 INFO: [APUAPC] D3_APC_0: 0xffffffff
9979 23:56:13.077802 INFO: [APUAPC] D3_APC_1: 0xffffffff
9980 23:56:13.081572 INFO: [APUAPC] D3_APC_2: 0x3fffff
9981 23:56:13.084395 INFO: [APUAPC] D3_APC_3: 0x0
9982 23:56:13.087811 INFO: [APUAPC] D4_APC_0: 0xffffffff
9983 23:56:13.091180 INFO: [APUAPC] D4_APC_1: 0xffffffff
9984 23:56:13.094291 INFO: [APUAPC] D4_APC_2: 0x3fffff
9985 23:56:13.097618 INFO: [APUAPC] D4_APC_3: 0x0
9986 23:56:13.101225 INFO: [APUAPC] D5_APC_0: 0xffffffff
9987 23:56:13.104668 INFO: [APUAPC] D5_APC_1: 0xffffffff
9988 23:56:13.107550 INFO: [APUAPC] D5_APC_2: 0x3fffff
9989 23:56:13.111151 INFO: [APUAPC] D5_APC_3: 0x0
9990 23:56:13.114460 INFO: [APUAPC] D6_APC_0: 0xffffffff
9991 23:56:13.117426 INFO: [APUAPC] D6_APC_1: 0xffffffff
9992 23:56:13.120501 INFO: [APUAPC] D6_APC_2: 0x3fffff
9993 23:56:13.123802 INFO: [APUAPC] D6_APC_3: 0x0
9994 23:56:13.127086 INFO: [APUAPC] D7_APC_0: 0xffffffff
9995 23:56:13.130581 INFO: [APUAPC] D7_APC_1: 0xffffffff
9996 23:56:13.134085 INFO: [APUAPC] D7_APC_2: 0x3fffff
9997 23:56:13.137222 INFO: [APUAPC] D7_APC_3: 0x0
9998 23:56:13.140468 INFO: [APUAPC] D8_APC_0: 0xffffffff
9999 23:56:13.143811 INFO: [APUAPC] D8_APC_1: 0xffffffff
10000 23:56:13.147028 INFO: [APUAPC] D8_APC_2: 0x3fffff
10001 23:56:13.150201 INFO: [APUAPC] D8_APC_3: 0x0
10002 23:56:13.154003 INFO: [APUAPC] D9_APC_0: 0xffffffff
10003 23:56:13.156827 INFO: [APUAPC] D9_APC_1: 0xffffffff
10004 23:56:13.160123 INFO: [APUAPC] D9_APC_2: 0x3fffff
10005 23:56:13.163379 INFO: [APUAPC] D9_APC_3: 0x0
10006 23:56:13.167145 INFO: [APUAPC] D10_APC_0: 0xffffffff
10007 23:56:13.170503 INFO: [APUAPC] D10_APC_1: 0xffffffff
10008 23:56:13.173455 INFO: [APUAPC] D10_APC_2: 0x3fffff
10009 23:56:13.176883 INFO: [APUAPC] D10_APC_3: 0x0
10010 23:56:13.179916 INFO: [APUAPC] D11_APC_0: 0xffffffff
10011 23:56:13.183335 INFO: [APUAPC] D11_APC_1: 0xffffffff
10012 23:56:13.186916 INFO: [APUAPC] D11_APC_2: 0x3fffff
10013 23:56:13.190331 INFO: [APUAPC] D11_APC_3: 0x0
10014 23:56:13.193786 INFO: [APUAPC] D12_APC_0: 0xffffffff
10015 23:56:13.197064 INFO: [APUAPC] D12_APC_1: 0xffffffff
10016 23:56:13.200066 INFO: [APUAPC] D12_APC_2: 0x3fffff
10017 23:56:13.203473 INFO: [APUAPC] D12_APC_3: 0x0
10018 23:56:13.206635 INFO: [APUAPC] D13_APC_0: 0xffffffff
10019 23:56:13.209957 INFO: [APUAPC] D13_APC_1: 0xffffffff
10020 23:56:13.212997 INFO: [APUAPC] D13_APC_2: 0x3fffff
10021 23:56:13.216254 INFO: [APUAPC] D13_APC_3: 0x0
10022 23:56:13.219655 INFO: [APUAPC] D14_APC_0: 0xffffffff
10023 23:56:13.222812 INFO: [APUAPC] D14_APC_1: 0xffffffff
10024 23:56:13.226326 INFO: [APUAPC] D14_APC_2: 0x3fffff
10025 23:56:13.229261 INFO: [APUAPC] D14_APC_3: 0x0
10026 23:56:13.233136 INFO: [APUAPC] D15_APC_0: 0xffffffff
10027 23:56:13.236054 INFO: [APUAPC] D15_APC_1: 0xffffffff
10028 23:56:13.239353 INFO: [APUAPC] D15_APC_2: 0x3fffff
10029 23:56:13.242457 INFO: [APUAPC] D15_APC_3: 0x0
10030 23:56:13.245996 INFO: [APUAPC] APC_CON: 0x4
10031 23:56:13.249275 INFO: [NOCDAPC] D0_APC_0: 0x0
10032 23:56:13.253216 INFO: [NOCDAPC] D0_APC_1: 0x0
10033 23:56:13.256664 INFO: [NOCDAPC] D1_APC_0: 0x0
10034 23:56:13.259166 INFO: [NOCDAPC] D1_APC_1: 0xfff
10035 23:56:13.262374 INFO: [NOCDAPC] D2_APC_0: 0x0
10036 23:56:13.265715 INFO: [NOCDAPC] D2_APC_1: 0xfff
10037 23:56:13.266246 INFO: [NOCDAPC] D3_APC_0: 0x0
10038 23:56:13.269150 INFO: [NOCDAPC] D3_APC_1: 0xfff
10039 23:56:13.272253 INFO: [NOCDAPC] D4_APC_0: 0x0
10040 23:56:13.276266 INFO: [NOCDAPC] D4_APC_1: 0xfff
10041 23:56:13.279108 INFO: [NOCDAPC] D5_APC_0: 0x0
10042 23:56:13.282602 INFO: [NOCDAPC] D5_APC_1: 0xfff
10043 23:56:13.285599 INFO: [NOCDAPC] D6_APC_0: 0x0
10044 23:56:13.288982 INFO: [NOCDAPC] D6_APC_1: 0xfff
10045 23:56:13.292301 INFO: [NOCDAPC] D7_APC_0: 0x0
10046 23:56:13.295659 INFO: [NOCDAPC] D7_APC_1: 0xfff
10047 23:56:13.299021 INFO: [NOCDAPC] D8_APC_0: 0x0
10048 23:56:13.302305 INFO: [NOCDAPC] D8_APC_1: 0xfff
10049 23:56:13.302900 INFO: [NOCDAPC] D9_APC_0: 0x0
10050 23:56:13.305511 INFO: [NOCDAPC] D9_APC_1: 0xfff
10051 23:56:13.308809 INFO: [NOCDAPC] D10_APC_0: 0x0
10052 23:56:13.312322 INFO: [NOCDAPC] D10_APC_1: 0xfff
10053 23:56:13.315660 INFO: [NOCDAPC] D11_APC_0: 0x0
10054 23:56:13.319010 INFO: [NOCDAPC] D11_APC_1: 0xfff
10055 23:56:13.322136 INFO: [NOCDAPC] D12_APC_0: 0x0
10056 23:56:13.325546 INFO: [NOCDAPC] D12_APC_1: 0xfff
10057 23:56:13.329003 INFO: [NOCDAPC] D13_APC_0: 0x0
10058 23:56:13.331938 INFO: [NOCDAPC] D13_APC_1: 0xfff
10059 23:56:13.335408 INFO: [NOCDAPC] D14_APC_0: 0x0
10060 23:56:13.338858 INFO: [NOCDAPC] D14_APC_1: 0xfff
10061 23:56:13.341758 INFO: [NOCDAPC] D15_APC_0: 0x0
10062 23:56:13.345138 INFO: [NOCDAPC] D15_APC_1: 0xfff
10063 23:56:13.345613 INFO: [NOCDAPC] APC_CON: 0x4
10064 23:56:13.348422 INFO: [APUAPC] set_apusys_apc done
10065 23:56:13.352119 INFO: [DEVAPC] devapc_init done
10066 23:56:13.358488 INFO: GICv3 without legacy support detected.
10067 23:56:13.361415 INFO: ARM GICv3 driver initialized in EL3
10068 23:56:13.364962 INFO: Maximum SPI INTID supported: 639
10069 23:56:13.368355 INFO: BL31: Initializing runtime services
10070 23:56:13.374708 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10071 23:56:13.378360 INFO: SPM: enable CPC mode
10072 23:56:13.381262 INFO: mcdi ready for mcusys-off-idle and system suspend
10073 23:56:13.388171 INFO: BL31: Preparing for EL3 exit to normal world
10074 23:56:13.390972 INFO: Entry point address = 0x80000000
10075 23:56:13.394468 INFO: SPSR = 0x8
10076 23:56:13.398985
10077 23:56:13.399448
10078 23:56:13.399815
10079 23:56:13.402234 Starting depthcharge on Spherion...
10080 23:56:13.402713
10081 23:56:13.403117 Wipe memory regions:
10082 23:56:13.403460
10083 23:56:13.405885 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10084 23:56:13.406452 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10085 23:56:13.406919 Setting prompt string to ['asurada:']
10086 23:56:13.407352 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10087 23:56:13.408080 [0x00000040000000, 0x00000054600000)
10088 23:56:13.527555
10089 23:56:13.528137 [0x00000054660000, 0x00000080000000)
10090 23:56:13.788256
10091 23:56:13.788797 [0x000000821a7280, 0x000000ffe64000)
10092 23:56:14.532965
10093 23:56:14.535863 [0x00000100000000, 0x00000240000000)
10094 23:56:16.423372
10095 23:56:16.426291 Initializing XHCI USB controller at 0x11200000.
10096 23:56:17.466243
10097 23:56:17.469057 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10098 23:56:17.469630
10099 23:56:17.470121
10100 23:56:17.471089 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 23:56:17.572600 asurada: tftpboot 192.168.201.1 14084377/tftp-deploy-kbi4ick9/kernel/image.itb 14084377/tftp-deploy-kbi4ick9/kernel/cmdline
10103 23:56:17.573283 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 23:56:17.573809 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10105 23:56:17.578228 tftpboot 192.168.201.1 14084377/tftp-deploy-kbi4ick9/kernel/image.itp-deploy-kbi4ick9/kernel/cmdline
10106 23:56:17.578714
10107 23:56:17.579184 Waiting for link
10108 23:56:17.736524
10109 23:56:17.737107 R8152: Initializing
10110 23:56:17.737601
10111 23:56:17.739916 Version 6 (ocp_data = 5c30)
10112 23:56:17.740465
10113 23:56:17.742946 R8152: Done initializing
10114 23:56:17.743404
10115 23:56:17.743764 Adding net device
10116 23:56:19.639402
10117 23:56:19.640040 done.
10118 23:56:19.640412
10119 23:56:19.640757 MAC: 00:e0:4c:68:02:81
10120 23:56:19.641088
10121 23:56:19.642656 Sending DHCP discover... done.
10122 23:56:19.643177
10123 23:56:30.031017 Waiting for reply... R8152: Bulk read error 0xffffffbf
10124 23:56:30.031594
10125 23:56:30.034202 Receive failed.
10126 23:56:30.034827
10127 23:56:30.035491 done.
10128 23:56:30.035873
10129 23:56:30.037401 Sending DHCP request... done.
10130 23:56:30.037855
10131 23:56:30.040809 Waiting for reply... done.
10132 23:56:30.041263
10133 23:56:30.041621 My ip is 192.168.201.14
10134 23:56:30.043852
10135 23:56:30.044306 The DHCP server ip is 192.168.201.1
10136 23:56:30.044668
10137 23:56:30.050769 TFTP server IP predefined by user: 192.168.201.1
10138 23:56:30.051230
10139 23:56:30.057392 Bootfile predefined by user: 14084377/tftp-deploy-kbi4ick9/kernel/image.itb
10140 23:56:30.057850
10141 23:56:30.060640 Sending tftp read request... done.
10142 23:56:30.061193
10143 23:56:30.068197 Waiting for the transfer...
10144 23:56:30.068778
10145 23:56:30.743325 00000000 ################################################################
10146 23:56:30.743855
10147 23:56:31.425857 00080000 ################################################################
10148 23:56:31.426423
10149 23:56:32.104303 00100000 ################################################################
10150 23:56:32.104826
10151 23:56:32.780452 00180000 ################################################################
10152 23:56:32.780973
10153 23:56:33.428983 00200000 ################################################################
10154 23:56:33.429580
10155 23:56:34.110130 00280000 ################################################################
10156 23:56:34.110689
10157 23:56:34.801250 00300000 ################################################################
10158 23:56:34.801755
10159 23:56:35.478350 00380000 ################################################################
10160 23:56:35.478877
10161 23:56:36.158652 00400000 ################################################################
10162 23:56:36.159163
10163 23:56:36.842199 00480000 ################################################################
10164 23:56:36.842741
10165 23:56:37.525545 00500000 ################################################################
10166 23:56:37.526050
10167 23:56:38.205334 00580000 ################################################################
10168 23:56:38.206023
10169 23:56:38.881486 00600000 ################################################################
10170 23:56:38.882017
10171 23:56:39.563182 00680000 ################################################################
10172 23:56:39.563759
10173 23:56:40.244467 00700000 ################################################################
10174 23:56:40.245084
10175 23:56:40.914711 00780000 ################################################################
10176 23:56:40.915238
10177 23:56:41.591720 00800000 ################################################################
10178 23:56:41.592302
10179 23:56:42.275062 00880000 ################################################################
10180 23:56:42.275567
10181 23:56:42.963262 00900000 ################################################################
10182 23:56:42.963994
10183 23:56:43.647556 00980000 ################################################################
10184 23:56:43.648184
10185 23:56:44.330432 00a00000 ################################################################
10186 23:56:44.331140
10187 23:56:45.004782 00a80000 ################################################################
10188 23:56:45.005437
10189 23:56:45.680476 00b00000 ################################################################
10190 23:56:45.680997
10191 23:56:46.333552 00b80000 ################################################################
10192 23:56:46.334058
10193 23:56:47.018443 00c00000 ################################################################
10194 23:56:47.018960
10195 23:56:47.713937 00c80000 ################################################################
10196 23:56:47.714501
10197 23:56:48.394273 00d00000 ################################################################
10198 23:56:48.394825
10199 23:56:49.078229 00d80000 ################################################################
10200 23:56:49.078852
10201 23:56:49.759457 00e00000 ################################################################
10202 23:56:49.759961
10203 23:56:50.437601 00e80000 ################################################################
10204 23:56:50.438107
10205 23:56:51.107319 00f00000 ################################################################
10206 23:56:51.107828
10207 23:56:51.792159 00f80000 ################################################################
10208 23:56:51.792707
10209 23:56:52.455033 01000000 ################################################################
10210 23:56:52.455541
10211 23:56:53.127605 01080000 ################################################################
10212 23:56:53.128111
10213 23:56:53.804192 01100000 ################################################################
10214 23:56:53.804741
10215 23:56:54.479599 01180000 ################################################################
10216 23:56:54.480107
10217 23:56:55.155645 01200000 ################################################################
10218 23:56:55.156168
10219 23:56:55.836033 01280000 ################################################################
10220 23:56:55.836559
10221 23:56:56.508025 01300000 ################################################################
10222 23:56:56.508547
10223 23:56:57.190275 01380000 ################################################################
10224 23:56:57.190852
10225 23:56:57.873655 01400000 ################################################################
10226 23:56:57.874230
10227 23:56:58.549693 01480000 ################################################################
10228 23:56:58.550349
10229 23:56:59.223419 01500000 ################################################################
10230 23:56:59.223937
10231 23:56:59.879566 01580000 ################################################################
10232 23:56:59.879714
10233 23:57:00.505750 01600000 ################################################################
10234 23:57:00.505904
10235 23:57:01.178074 01680000 ################################################################
10236 23:57:01.178669
10237 23:57:01.852287 01700000 ################################################################
10238 23:57:01.852801
10239 23:57:02.503935 01780000 ################################################################
10240 23:57:02.504450
10241 23:57:03.175138 01800000 ################################################################
10242 23:57:03.175649
10243 23:57:03.846113 01880000 ################################################################
10244 23:57:03.846656
10245 23:57:04.510827 01900000 ################################################################
10246 23:57:04.511333
10247 23:57:05.167158 01980000 ################################################################
10248 23:57:05.167675
10249 23:57:05.836331 01a00000 ################################################################
10250 23:57:05.836851
10251 23:57:06.521619 01a80000 ################################################################
10252 23:57:06.522251
10253 23:57:07.201641 01b00000 ################################################################
10254 23:57:07.202192
10255 23:57:07.879227 01b80000 ################################################################
10256 23:57:07.879750
10257 23:57:08.556299 01c00000 ################################################################
10258 23:57:08.556923
10259 23:57:09.221983 01c80000 ################################################################
10260 23:57:09.222700
10261 23:57:09.905452 01d00000 ################################################################
10262 23:57:09.905967
10263 23:57:10.574588 01d80000 ################################################################
10264 23:57:10.575136
10265 23:57:11.253067 01e00000 ################################################################
10266 23:57:11.253638
10267 23:57:11.908727 01e80000 ################################################################
10268 23:57:11.909473
10269 23:57:12.581994 01f00000 ################################################################
10270 23:57:12.582768
10271 23:57:13.263133 01f80000 ################################################################
10272 23:57:13.263668
10273 23:57:13.934250 02000000 ################################################################
10274 23:57:13.934910
10275 23:57:14.616906 02080000 ################################################################
10276 23:57:14.617450
10277 23:57:15.295829 02100000 ################################################################
10278 23:57:15.296351
10279 23:57:15.970099 02180000 ################################################################
10280 23:57:15.970639
10281 23:57:16.643348 02200000 ################################################################
10282 23:57:16.643865
10283 23:57:17.318825 02280000 ################################################################
10284 23:57:17.319331
10285 23:57:17.991594 02300000 ################################################################
10286 23:57:17.992109
10287 23:57:18.647018 02380000 ################################################################
10288 23:57:18.647540
10289 23:57:19.316425 02400000 ################################################################
10290 23:57:19.316962
10291 23:57:19.972270 02480000 ################################################################
10292 23:57:19.972766
10293 23:57:20.634649 02500000 ################################################################
10294 23:57:20.635159
10295 23:57:21.307419 02580000 ################################################################
10296 23:57:21.307978
10297 23:57:21.954959 02600000 ################################################################
10298 23:57:21.955474
10299 23:57:22.600895 02680000 ################################################################
10300 23:57:22.601409
10301 23:57:23.263685 02700000 ################################################################
10302 23:57:23.264194
10303 23:57:23.905934 02780000 ################################################################
10304 23:57:23.906590
10305 23:57:24.557649 02800000 ################################################################
10306 23:57:24.558276
10307 23:57:25.222844 02880000 ################################################################
10308 23:57:25.223524
10309 23:57:25.890837 02900000 ################################################################
10310 23:57:25.891350
10311 23:57:26.530916 02980000 ################################################################
10312 23:57:26.531634
10313 23:57:27.201879 02a00000 ################################################################
10314 23:57:27.202505
10315 23:57:27.870817 02a80000 ################################################################
10316 23:57:27.871487
10317 23:57:28.546435 02b00000 ################################################################
10318 23:57:28.546941
10319 23:57:29.205554 02b80000 ################################################################
10320 23:57:29.206062
10321 23:57:29.871539 02c00000 ################################################################
10322 23:57:29.872051
10323 23:57:30.536386 02c80000 ################################################################
10324 23:57:30.536893
10325 23:57:31.206203 02d00000 ################################################################
10326 23:57:31.206724
10327 23:57:31.880284 02d80000 ################################################################
10328 23:57:31.880807
10329 23:57:32.563036 02e00000 ################################################################
10330 23:57:32.563679
10331 23:57:33.245822 02e80000 ################################################################
10332 23:57:33.246387
10333 23:57:33.930821 02f00000 ################################################################
10334 23:57:33.931336
10335 23:57:34.609484 02f80000 ################################################################
10336 23:57:34.610023
10337 23:57:35.281377 03000000 ################################################################
10338 23:57:35.281919
10339 23:57:35.955848 03080000 ################################################################
10340 23:57:35.956369
10341 23:57:36.632894 03100000 ################################################################
10342 23:57:36.633411
10343 23:57:37.298387 03180000 ################################################################
10344 23:57:37.298903
10345 23:57:37.978533 03200000 ################################################################
10346 23:57:37.979058
10347 23:57:38.656090 03280000 ################################################################
10348 23:57:38.656611
10349 23:57:39.318761 03300000 ################################################################
10350 23:57:39.319279
10351 23:57:39.983934 03380000 ################################################################
10352 23:57:39.984447
10353 23:57:40.651337 03400000 ################################################################
10354 23:57:40.651851
10355 23:57:41.326525 03480000 ################################################################
10356 23:57:41.327035
10357 23:57:41.990935 03500000 ################################################################
10358 23:57:41.991437
10359 23:57:42.658241 03580000 ################################################################
10360 23:57:42.658757
10361 23:57:43.346348 03600000 ################################################################
10362 23:57:43.346857
10363 23:57:44.031130 03680000 ################################################################
10364 23:57:44.031644
10365 23:57:44.716060 03700000 ################################################################
10366 23:57:44.716572
10367 23:57:45.392529 03780000 ################################################################
10368 23:57:45.393097
10369 23:57:46.059814 03800000 ################################################################
10370 23:57:46.060328
10371 23:57:46.706552 03880000 ################################################################
10372 23:57:46.707059
10373 23:57:47.384045 03900000 ################################################################
10374 23:57:47.384752
10375 23:57:48.066821 03980000 ################################################################
10376 23:57:48.067355
10377 23:57:48.743036 03a00000 ################################################################
10378 23:57:48.743547
10379 23:57:49.420600 03a80000 ################################################################
10380 23:57:49.420745
10381 23:57:50.061425 03b00000 ################################################################
10382 23:57:50.061951
10383 23:57:50.742031 03b80000 ################################################################
10384 23:57:50.742589
10385 23:57:51.423595 03c00000 ################################################################
10386 23:57:51.424129
10387 23:57:52.110228 03c80000 ################################################################
10388 23:57:52.110761
10389 23:57:52.780377 03d00000 ################################################################
10390 23:57:52.780926
10391 23:57:53.430116 03d80000 ################################################################
10392 23:57:53.430648
10393 23:57:54.106925 03e00000 ################################################################
10394 23:57:54.107440
10395 23:57:54.779845 03e80000 ################################################################
10396 23:57:54.780355
10397 23:57:55.442520 03f00000 ################################################################
10398 23:57:55.443030
10399 23:57:56.125845 03f80000 ################################################################
10400 23:57:56.126610
10401 23:57:56.806235 04000000 ################################################################
10402 23:57:56.806741
10403 23:57:57.490140 04080000 ################################################################
10404 23:57:57.490770
10405 23:57:58.168277 04100000 ################################################################
10406 23:57:58.168816
10407 23:57:58.854720 04180000 ################################################################
10408 23:57:58.855232
10409 23:57:59.551248 04200000 ################################################################
10410 23:57:59.551762
10411 23:58:00.209799 04280000 ################################################################
10412 23:58:00.210361
10413 23:58:00.865024 04300000 ################################################################
10414 23:58:00.865538
10415 23:58:01.490059 04380000 ################################################################
10416 23:58:01.490613
10417 23:58:02.141466 04400000 ################################################################
10418 23:58:02.141985
10419 23:58:02.808107 04480000 ################################################################
10420 23:58:02.808626
10421 23:58:03.462811 04500000 ################################################################
10422 23:58:03.462981
10423 23:58:04.121649 04580000 ################################################################
10424 23:58:04.122217
10425 23:58:04.804709 04600000 ################################################################
10426 23:58:04.805314
10427 23:58:05.045772 04680000 ####################### done.
10428 23:58:05.046340
10429 23:58:05.049009 The bootfile was 74107706 bytes long.
10430 23:58:05.049439
10431 23:58:05.052036 Sending tftp read request... done.
10432 23:58:05.052464
10433 23:58:05.055980 Waiting for the transfer...
10434 23:58:05.056408
10435 23:58:05.056835 00000000 # done.
10436 23:58:05.057245
10437 23:58:05.062346 Command line loaded dynamically from TFTP file: 14084377/tftp-deploy-kbi4ick9/kernel/cmdline
10438 23:58:05.065688
10439 23:58:05.078764 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10440 23:58:05.079198
10441 23:58:05.079628 Loading FIT.
10442 23:58:05.080032
10443 23:58:05.082580 Image ramdisk-1 has 60994925 bytes.
10444 23:58:05.083006
10445 23:58:05.085379 Image fdt-1 has 47258 bytes.
10446 23:58:05.085805
10447 23:58:05.088801 Image kernel-1 has 13063488 bytes.
10448 23:58:05.089226
10449 23:58:05.095212 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10450 23:58:05.095642
10451 23:58:05.115441 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10452 23:58:05.115968
10453 23:58:05.118638 Choosing best match conf-1 for compat google,spherion-rev2.
10454 23:58:05.123650
10455 23:58:05.127539 Connected to device vid:did:rid of 1ae0:0028:00
10456 23:58:05.134953
10457 23:58:05.138132 tpm_get_response: command 0x17b, return code 0x0
10458 23:58:05.138681
10459 23:58:05.141619 ec_init: CrosEC protocol v3 supported (256, 248)
10460 23:58:05.146273
10461 23:58:05.149794 tpm_cleanup: add release locality here.
10462 23:58:05.150365
10463 23:58:05.150711 Shutting down all USB controllers.
10464 23:58:05.152974
10465 23:58:05.153392 Removing current net device
10466 23:58:05.153729
10467 23:58:05.159716 Exiting depthcharge with code 4 at timestamp: 141210934
10468 23:58:05.160138
10469 23:58:05.162820 LZMA decompressing kernel-1 to 0x821a6718
10470 23:58:05.163243
10471 23:58:05.166353 LZMA decompressing kernel-1 to 0x40000000
10472 23:58:06.776784
10473 23:58:06.777335 jumping to kernel
10474 23:58:06.779897 end: 2.2.4 bootloader-commands (duration 00:01:53) [common]
10475 23:58:06.780441 start: 2.2.5 auto-login-action (timeout 00:02:33) [common]
10476 23:58:06.780864 Setting prompt string to ['Linux version [0-9]']
10477 23:58:06.781247 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10478 23:58:06.781629 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10479 23:58:06.858990
10480 23:58:06.862303 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10481 23:58:06.865855 start: 2.2.5.1 login-action (timeout 00:02:33) [common]
10482 23:58:06.866450 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10483 23:58:06.866856 Setting prompt string to []
10484 23:58:06.867280 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10485 23:58:06.867641 Using line separator: #'\n'#
10486 23:58:06.867979 No login prompt set.
10487 23:58:06.868298 Parsing kernel messages
10488 23:58:06.868585 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10489 23:58:06.869085 [login-action] Waiting for messages, (timeout 00:02:33)
10490 23:58:06.869418 Waiting using forced prompt support (timeout 00:01:16)
10491 23:58:06.885195 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10492 23:58:06.888458 [ 0.000000] random: crng init done
10493 23:58:06.895224 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10494 23:58:06.898486 [ 0.000000] efi: UEFI not found.
10495 23:58:06.904994 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10496 23:58:06.914746 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10497 23:58:06.921496 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10498 23:58:06.931782 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10499 23:58:06.937811 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10500 23:58:06.944634 [ 0.000000] printk: bootconsole [mtk8250] enabled
10501 23:58:06.950947 [ 0.000000] NUMA: No NUMA configuration found
10502 23:58:06.957476 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10503 23:58:06.964398 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10504 23:58:06.964820 [ 0.000000] Zone ranges:
10505 23:58:06.970724 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10506 23:58:06.974060 [ 0.000000] DMA32 empty
10507 23:58:06.980825 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10508 23:58:06.984133 [ 0.000000] Movable zone start for each node
10509 23:58:06.987334 [ 0.000000] Early memory node ranges
10510 23:58:06.993969 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10511 23:58:07.000749 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10512 23:58:07.006813 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10513 23:58:07.013619 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10514 23:58:07.019991 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10515 23:58:07.026439 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10516 23:58:07.083798 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10517 23:58:07.090151 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10518 23:58:07.096878 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10519 23:58:07.100007 [ 0.000000] psci: probing for conduit method from DT.
10520 23:58:07.106731 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10521 23:58:07.110402 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10522 23:58:07.116644 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10523 23:58:07.120245 [ 0.000000] psci: SMC Calling Convention v1.2
10524 23:58:07.126676 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10525 23:58:07.129924 [ 0.000000] Detected VIPT I-cache on CPU0
10526 23:58:07.136511 [ 0.000000] CPU features: detected: GIC system register CPU interface
10527 23:58:07.142907 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10528 23:58:07.150107 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10529 23:58:07.156283 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10530 23:58:07.165970 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10531 23:58:07.172248 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10532 23:58:07.175685 [ 0.000000] alternatives: applying boot alternatives
10533 23:58:07.182457 [ 0.000000] Fallback order for Node 0: 0
10534 23:58:07.189119 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10535 23:58:07.192307 [ 0.000000] Policy zone: Normal
10536 23:58:07.205495 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10537 23:58:07.215731 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10538 23:58:07.228057 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10539 23:58:07.237986 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10540 23:58:07.244815 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10541 23:58:07.247500 <6>[ 0.000000] software IO TLB: area num 8.
10542 23:58:07.304356 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10543 23:58:07.454057 <6>[ 0.000000] Memory: 7904624K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448144K reserved, 32768K cma-reserved)
10544 23:58:07.460831 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10545 23:58:07.467387 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10546 23:58:07.470733 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10547 23:58:07.477334 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10548 23:58:07.484278 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10549 23:58:07.486735 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10550 23:58:07.496660 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10551 23:58:07.504037 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10552 23:58:07.510157 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10553 23:58:07.517180 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10554 23:58:07.520212 <6>[ 0.000000] GICv3: 608 SPIs implemented
10555 23:58:07.523330 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10556 23:58:07.530096 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10557 23:58:07.533395 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10558 23:58:07.539977 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10559 23:58:07.553306 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10560 23:58:07.563226 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10561 23:58:07.573349 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10562 23:58:07.580266 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10563 23:58:07.593427 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10564 23:58:07.600419 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10565 23:58:07.606758 <6>[ 0.009231] Console: colour dummy device 80x25
10566 23:58:07.616793 <6>[ 0.013979] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10567 23:58:07.623248 <6>[ 0.024486] pid_max: default: 32768 minimum: 301
10568 23:58:07.626769 <6>[ 0.029359] LSM: Security Framework initializing
10569 23:58:07.633236 <6>[ 0.034325] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10570 23:58:07.643156 <6>[ 0.042138] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10571 23:58:07.652720 <6>[ 0.051563] cblist_init_generic: Setting adjustable number of callback queues.
10572 23:58:07.659300 <6>[ 0.059007] cblist_init_generic: Setting shift to 3 and lim to 1.
10573 23:58:07.666084 <6>[ 0.065384] cblist_init_generic: Setting adjustable number of callback queues.
10574 23:58:07.672943 <6>[ 0.072811] cblist_init_generic: Setting shift to 3 and lim to 1.
10575 23:58:07.675758 <6>[ 0.079209] rcu: Hierarchical SRCU implementation.
10576 23:58:07.682827 <6>[ 0.084255] rcu: Max phase no-delay instances is 1000.
10577 23:58:07.689248 <6>[ 0.091277] EFI services will not be available.
10578 23:58:07.692624 <6>[ 0.096235] smp: Bringing up secondary CPUs ...
10579 23:58:07.701124 <6>[ 0.101312] Detected VIPT I-cache on CPU1
10580 23:58:07.707855 <6>[ 0.101385] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10581 23:58:07.714523 <6>[ 0.101417] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10582 23:58:07.717906 <6>[ 0.101745] Detected VIPT I-cache on CPU2
10583 23:58:07.727794 <6>[ 0.101794] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10584 23:58:07.734194 <6>[ 0.101810] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10585 23:58:07.737283 <6>[ 0.102066] Detected VIPT I-cache on CPU3
10586 23:58:07.743911 <6>[ 0.102113] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10587 23:58:07.750907 <6>[ 0.102127] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10588 23:58:07.757222 <6>[ 0.102429] CPU features: detected: Spectre-v4
10589 23:58:07.760184 <6>[ 0.102436] CPU features: detected: Spectre-BHB
10590 23:58:07.763608 <6>[ 0.102441] Detected PIPT I-cache on CPU4
10591 23:58:07.773431 <6>[ 0.102497] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10592 23:58:07.779941 <6>[ 0.102513] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10593 23:58:07.783060 <6>[ 0.102803] Detected PIPT I-cache on CPU5
10594 23:58:07.789869 <6>[ 0.102864] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10595 23:58:07.796762 <6>[ 0.102880] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10596 23:58:07.799568 <6>[ 0.103160] Detected PIPT I-cache on CPU6
10597 23:58:07.810016 <6>[ 0.103225] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10598 23:58:07.816497 <6>[ 0.103241] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10599 23:58:07.819342 <6>[ 0.103540] Detected PIPT I-cache on CPU7
10600 23:58:07.826008 <6>[ 0.103604] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10601 23:58:07.832567 <6>[ 0.103620] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10602 23:58:07.836094 <6>[ 0.103667] smp: Brought up 1 node, 8 CPUs
10603 23:58:07.842703 <6>[ 0.245007] SMP: Total of 8 processors activated.
10604 23:58:07.849423 <6>[ 0.249958] CPU features: detected: 32-bit EL0 Support
10605 23:58:07.855836 <6>[ 0.255321] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10606 23:58:07.862113 <6>[ 0.264122] CPU features: detected: Common not Private translations
10607 23:58:07.868795 <6>[ 0.270598] CPU features: detected: CRC32 instructions
10608 23:58:07.875655 <6>[ 0.275983] CPU features: detected: RCpc load-acquire (LDAPR)
10609 23:58:07.878834 <6>[ 0.281980] CPU features: detected: LSE atomic instructions
10610 23:58:07.885713 <6>[ 0.287797] CPU features: detected: Privileged Access Never
10611 23:58:07.891996 <6>[ 0.293577] CPU features: detected: RAS Extension Support
10612 23:58:07.898852 <6>[ 0.299186] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10613 23:58:07.901737 <6>[ 0.306455] CPU: All CPU(s) started at EL2
10614 23:58:07.908641 <6>[ 0.310772] alternatives: applying system-wide alternatives
10615 23:58:07.919047 <6>[ 0.321619] devtmpfs: initialized
10616 23:58:07.931529 <6>[ 0.330472] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10617 23:58:07.941318 <6>[ 0.340437] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10618 23:58:07.948163 <6>[ 0.348456] pinctrl core: initialized pinctrl subsystem
10619 23:58:07.951025 <6>[ 0.355098] DMI not present or invalid.
10620 23:58:07.957660 <6>[ 0.359511] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10621 23:58:07.967594 <6>[ 0.366287] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10622 23:58:07.974435 <6>[ 0.373878] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10623 23:58:07.984340 <6>[ 0.382096] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10624 23:58:07.987836 <6>[ 0.390342] audit: initializing netlink subsys (disabled)
10625 23:58:07.997295 <5>[ 0.396033] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10626 23:58:08.004120 <6>[ 0.396727] thermal_sys: Registered thermal governor 'step_wise'
10627 23:58:08.010936 <6>[ 0.403997] thermal_sys: Registered thermal governor 'power_allocator'
10628 23:58:08.013984 <6>[ 0.410249] cpuidle: using governor menu
10629 23:58:08.020390 <6>[ 0.421205] NET: Registered PF_QIPCRTR protocol family
10630 23:58:08.027143 <6>[ 0.426679] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10631 23:58:08.030582 <6>[ 0.433780] ASID allocator initialised with 32768 entries
10632 23:58:08.037954 <6>[ 0.440355] Serial: AMBA PL011 UART driver
10633 23:58:08.046931 <4>[ 0.449075] Trying to register duplicate clock ID: 134
10634 23:58:08.104326 <6>[ 0.510334] KASLR enabled
10635 23:58:08.119127 <6>[ 0.518169] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10636 23:58:08.125784 <6>[ 0.525179] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10637 23:58:08.132560 <6>[ 0.531672] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10638 23:58:08.138883 <6>[ 0.538679] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10639 23:58:08.145423 <6>[ 0.545164] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10640 23:58:08.151710 <6>[ 0.552164] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10641 23:58:08.158400 <6>[ 0.558649] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10642 23:58:08.164772 <6>[ 0.565651] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10643 23:58:08.168395 <6>[ 0.573112] ACPI: Interpreter disabled.
10644 23:58:08.177220 <6>[ 0.579558] iommu: Default domain type: Translated
10645 23:58:08.183919 <6>[ 0.584671] iommu: DMA domain TLB invalidation policy: strict mode
10646 23:58:08.186707 <5>[ 0.591334] SCSI subsystem initialized
10647 23:58:08.193703 <6>[ 0.595579] usbcore: registered new interface driver usbfs
10648 23:58:08.199991 <6>[ 0.601312] usbcore: registered new interface driver hub
10649 23:58:08.203303 <6>[ 0.606861] usbcore: registered new device driver usb
10650 23:58:08.210668 <6>[ 0.612972] pps_core: LinuxPPS API ver. 1 registered
10651 23:58:08.220607 <6>[ 0.618165] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10652 23:58:08.223639 <6>[ 0.627509] PTP clock support registered
10653 23:58:08.226876 <6>[ 0.631748] EDAC MC: Ver: 3.0.0
10654 23:58:08.234513 <6>[ 0.636925] FPGA manager framework
10655 23:58:08.241024 <6>[ 0.640604] Advanced Linux Sound Architecture Driver Initialized.
10656 23:58:08.244177 <6>[ 0.647381] vgaarb: loaded
10657 23:58:08.251131 <6>[ 0.650535] clocksource: Switched to clocksource arch_sys_counter
10658 23:58:08.254145 <5>[ 0.656981] VFS: Disk quotas dquot_6.6.0
10659 23:58:08.260524 <6>[ 0.661170] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10660 23:58:08.263914 <6>[ 0.668362] pnp: PnP ACPI: disabled
10661 23:58:08.272369 <6>[ 0.674999] NET: Registered PF_INET protocol family
10662 23:58:08.282251 <6>[ 0.680588] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10663 23:58:08.293626 <6>[ 0.692890] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10664 23:58:08.303508 <6>[ 0.701702] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10665 23:58:08.309969 <6>[ 0.709676] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10666 23:58:08.320028 <6>[ 0.718376] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10667 23:58:08.326869 <6>[ 0.728130] TCP: Hash tables configured (established 65536 bind 65536)
10668 23:58:08.332989 <6>[ 0.734994] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10669 23:58:08.343103 <6>[ 0.742188] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10670 23:58:08.349774 <6>[ 0.749896] NET: Registered PF_UNIX/PF_LOCAL protocol family
10671 23:58:08.356519 <6>[ 0.756041] RPC: Registered named UNIX socket transport module.
10672 23:58:08.359442 <6>[ 0.762194] RPC: Registered udp transport module.
10673 23:58:08.366422 <6>[ 0.767126] RPC: Registered tcp transport module.
10674 23:58:08.372706 <6>[ 0.772060] RPC: Registered tcp NFSv4.1 backchannel transport module.
10675 23:58:08.376051 <6>[ 0.778727] PCI: CLS 0 bytes, default 64
10676 23:58:08.379065 <6>[ 0.783067] Unpacking initramfs...
10677 23:58:08.403367 <6>[ 0.802658] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10678 23:58:08.413113 <6>[ 0.811301] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10679 23:58:08.416575 <6>[ 0.820128] kvm [1]: IPA Size Limit: 40 bits
10680 23:58:08.423082 <6>[ 0.824654] kvm [1]: GICv3: no GICV resource entry
10681 23:58:08.426512 <6>[ 0.829677] kvm [1]: disabling GICv2 emulation
10682 23:58:08.433030 <6>[ 0.834360] kvm [1]: GIC system register CPU interface enabled
10683 23:58:08.436595 <6>[ 0.840514] kvm [1]: vgic interrupt IRQ18
10684 23:58:08.442624 <6>[ 0.844868] kvm [1]: VHE mode initialized successfully
10685 23:58:08.450006 <5>[ 0.851379] Initialise system trusted keyrings
10686 23:58:08.455932 <6>[ 0.856236] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10687 23:58:08.463927 <6>[ 0.866302] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10688 23:58:08.470727 <5>[ 0.872707] NFS: Registering the id_resolver key type
10689 23:58:08.473681 <5>[ 0.878011] Key type id_resolver registered
10690 23:58:08.480238 <5>[ 0.882423] Key type id_legacy registered
10691 23:58:08.486863 <6>[ 0.886703] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10692 23:58:08.493239 <6>[ 0.893623] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10693 23:58:08.499708 <6>[ 0.901338] 9p: Installing v9fs 9p2000 file system support
10694 23:58:08.536921 <5>[ 0.939304] Key type asymmetric registered
10695 23:58:08.540003 <5>[ 0.943632] Asymmetric key parser 'x509' registered
10696 23:58:08.549886 <6>[ 0.948766] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10697 23:58:08.553396 <6>[ 0.956380] io scheduler mq-deadline registered
10698 23:58:08.556331 <6>[ 0.961139] io scheduler kyber registered
10699 23:58:08.575216 <6>[ 0.978042] EINJ: ACPI disabled.
10700 23:58:08.607480 <4>[ 1.003542] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10701 23:58:08.617431 <4>[ 1.014159] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10702 23:58:08.635433 <6>[ 1.034905] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10703 23:58:08.638705 <6>[ 1.042805] printk: console [ttyS0] disabled
10704 23:58:08.668279 <6>[ 1.067429] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10705 23:58:08.674751 <6>[ 1.076903] printk: console [ttyS0] enabled
10706 23:58:08.677974 <6>[ 1.076903] printk: console [ttyS0] enabled
10707 23:58:08.684934 <6>[ 1.085799] printk: bootconsole [mtk8250] disabled
10708 23:58:08.688000 <6>[ 1.085799] printk: bootconsole [mtk8250] disabled
10709 23:58:08.694943 <6>[ 1.096816] SuperH (H)SCI(F) driver initialized
10710 23:58:08.697779 <6>[ 1.102076] msm_serial: driver initialized
10711 23:58:08.711843 <6>[ 1.110945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10712 23:58:08.721493 <6>[ 1.119491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10713 23:58:08.727816 <6>[ 1.128033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10714 23:58:08.737973 <6>[ 1.136661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10715 23:58:08.747925 <6>[ 1.145367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10716 23:58:08.754142 <6>[ 1.154086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10717 23:58:08.763920 <6>[ 1.162626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10718 23:58:08.773943 <6>[ 1.171421] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10719 23:58:08.780799 <6>[ 1.179964] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10720 23:58:08.792581 <6>[ 1.195317] loop: module loaded
10721 23:58:08.799142 <6>[ 1.201270] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10722 23:58:08.822109 <4>[ 1.224578] mtk-pmic-keys: Failed to locate of_node [id: -1]
10723 23:58:08.829327 <6>[ 1.231355] megasas: 07.719.03.00-rc1
10724 23:58:08.838851 <6>[ 1.241118] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10725 23:58:08.851854 <6>[ 1.253913] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10726 23:58:08.867928 <6>[ 1.270491] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10727 23:58:08.928717 <6>[ 1.324210] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10728 23:58:11.061718 <6>[ 3.464251] Freeing initrd memory: 59560K
10729 23:58:11.073256 <6>[ 3.475907] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10730 23:58:11.084435 <6>[ 3.486833] tun: Universal TUN/TAP device driver, 1.6
10731 23:58:11.087462 <6>[ 3.492881] thunder_xcv, ver 1.0
10732 23:58:11.090750 <6>[ 3.496390] thunder_bgx, ver 1.0
10733 23:58:11.093830 <6>[ 3.499883] nicpf, ver 1.0
10734 23:58:11.104634 <6>[ 3.503886] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10735 23:58:11.107735 <6>[ 3.511361] hns3: Copyright (c) 2017 Huawei Corporation.
10736 23:58:11.114261 <6>[ 3.516949] hclge is initializing
10737 23:58:11.117427 <6>[ 3.520528] e1000: Intel(R) PRO/1000 Network Driver
10738 23:58:11.124104 <6>[ 3.525657] e1000: Copyright (c) 1999-2006 Intel Corporation.
10739 23:58:11.130755 <6>[ 3.531668] e1000e: Intel(R) PRO/1000 Network Driver
10740 23:58:11.134203 <6>[ 3.536884] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10741 23:58:11.140872 <6>[ 3.543069] igb: Intel(R) Gigabit Ethernet Network Driver
10742 23:58:11.147733 <6>[ 3.548718] igb: Copyright (c) 2007-2014 Intel Corporation.
10743 23:58:11.154073 <6>[ 3.554557] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10744 23:58:11.160795 <6>[ 3.561074] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10745 23:58:11.163641 <6>[ 3.567533] sky2: driver version 1.30
10746 23:58:11.170445 <6>[ 3.572468] usbcore: registered new device driver r8152-cfgselector
10747 23:58:11.177020 <6>[ 3.579003] usbcore: registered new interface driver r8152
10748 23:58:11.183893 <6>[ 3.584813] VFIO - User Level meta-driver version: 0.3
10749 23:58:11.190259 <6>[ 3.593055] usbcore: registered new interface driver usb-storage
10750 23:58:11.197083 <6>[ 3.599500] usbcore: registered new device driver onboard-usb-hub
10751 23:58:11.205566 <6>[ 3.608624] mt6397-rtc mt6359-rtc: registered as rtc0
10752 23:58:11.215822 <6>[ 3.614084] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:58:11 UTC (1717027091)
10753 23:58:11.218661 <6>[ 3.623643] i2c_dev: i2c /dev entries driver
10754 23:58:11.236015 <6>[ 3.635316] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10755 23:58:11.242596 <4>[ 3.644040] cpu cpu0: supply cpu not found, using dummy regulator
10756 23:58:11.249215 <4>[ 3.650459] cpu cpu1: supply cpu not found, using dummy regulator
10757 23:58:11.255690 <4>[ 3.656861] cpu cpu2: supply cpu not found, using dummy regulator
10758 23:58:11.262345 <4>[ 3.663268] cpu cpu3: supply cpu not found, using dummy regulator
10759 23:58:11.268608 <4>[ 3.669681] cpu cpu4: supply cpu not found, using dummy regulator
10760 23:58:11.275487 <4>[ 3.676079] cpu cpu5: supply cpu not found, using dummy regulator
10761 23:58:11.281720 <4>[ 3.682474] cpu cpu6: supply cpu not found, using dummy regulator
10762 23:58:11.288269 <4>[ 3.688869] cpu cpu7: supply cpu not found, using dummy regulator
10763 23:58:11.306476 <6>[ 3.709527] cpu cpu0: EM: created perf domain
10764 23:58:11.310088 <6>[ 3.714441] cpu cpu4: EM: created perf domain
10765 23:58:11.316926 <6>[ 3.720070] sdhci: Secure Digital Host Controller Interface driver
10766 23:58:11.323478 <6>[ 3.726505] sdhci: Copyright(c) Pierre Ossman
10767 23:58:11.330496 <6>[ 3.731461] Synopsys Designware Multimedia Card Interface Driver
10768 23:58:11.337254 <6>[ 3.738089] sdhci-pltfm: SDHCI platform and OF driver helper
10769 23:58:11.340580 <6>[ 3.738139] mmc0: CQHCI version 5.10
10770 23:58:11.346774 <6>[ 3.748351] ledtrig-cpu: registered to indicate activity on CPUs
10771 23:58:11.353382 <6>[ 3.755368] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10772 23:58:11.360154 <6>[ 3.762417] usbcore: registered new interface driver usbhid
10773 23:58:11.363586 <6>[ 3.768238] usbhid: USB HID core driver
10774 23:58:11.372644 <6>[ 3.772438] spi_master spi0: will run message pump with realtime priority
10775 23:58:11.414580 <6>[ 3.810959] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10776 23:58:11.432994 <6>[ 3.826080] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10777 23:58:11.440399 <6>[ 3.840957] cros-ec-spi spi0.0: Chrome EC device registered
10778 23:58:11.443385 <6>[ 3.846942] mmc0: Command Queue Engine enabled
10779 23:58:11.450326 <6>[ 3.851692] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10780 23:58:11.456770 <6>[ 3.859562] mmcblk0: mmc0:0001 DA4128 116 GiB
10781 23:58:11.474733 <6>[ 3.874309] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10782 23:58:11.481608 <6>[ 3.875316] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10783 23:58:11.488331 <6>[ 3.884869] NET: Registered PF_PACKET protocol family
10784 23:58:11.491228 <6>[ 3.890454] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10785 23:58:11.498000 <6>[ 3.894919] 9pnet: Installing 9P2000 support
10786 23:58:11.500940 <6>[ 3.900836] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10787 23:58:11.507799 <5>[ 3.904617] Key type dns_resolver registered
10788 23:58:11.514437 <6>[ 3.910405] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10789 23:58:11.517989 <6>[ 3.914740] registered taskstats version 1
10790 23:58:11.521087 <5>[ 3.925229] Loading compiled-in X.509 certificates
10791 23:58:11.551705 <4>[ 3.947602] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10792 23:58:11.561260 <4>[ 3.958379] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10793 23:58:11.576007 <6>[ 3.978645] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10794 23:58:11.582504 <6>[ 3.985496] xhci-mtk 11200000.usb: xHCI Host Controller
10795 23:58:11.589113 <6>[ 3.991002] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10796 23:58:11.599064 <6>[ 3.998871] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10797 23:58:11.606089 <6>[ 4.008303] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10798 23:58:11.612469 <6>[ 4.014473] xhci-mtk 11200000.usb: xHCI Host Controller
10799 23:58:11.619707 <6>[ 4.019978] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10800 23:58:11.625597 <6>[ 4.027634] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10801 23:58:11.632654 <6>[ 4.035428] hub 1-0:1.0: USB hub found
10802 23:58:11.635907 <6>[ 4.039459] hub 1-0:1.0: 1 port detected
10803 23:58:11.645623 <6>[ 4.043740] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10804 23:58:11.648826 <6>[ 4.052451] hub 2-0:1.0: USB hub found
10805 23:58:11.652010 <6>[ 4.056478] hub 2-0:1.0: 1 port detected
10806 23:58:11.660507 <6>[ 4.063466] mtk-msdc 11f70000.mmc: Got CD GPIO
10807 23:58:11.672744 <6>[ 4.072367] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10808 23:58:11.679452 <6>[ 4.080400] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10809 23:58:11.689226 <4>[ 4.088329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10810 23:58:11.699242 <6>[ 4.097858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10811 23:58:11.706113 <6>[ 4.105935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10812 23:58:11.712747 <6>[ 4.113947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10813 23:58:11.722467 <6>[ 4.121885] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10814 23:58:11.729301 <6>[ 4.129702] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10815 23:58:11.739085 <6>[ 4.137522] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10816 23:58:11.748605 <6>[ 4.147918] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10817 23:58:11.755040 <6>[ 4.156282] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10818 23:58:11.765330 <6>[ 4.164628] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10819 23:58:11.775027 <6>[ 4.172965] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10820 23:58:11.781407 <6>[ 4.181303] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10821 23:58:11.791848 <6>[ 4.189641] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10822 23:58:11.798083 <6>[ 4.197980] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10823 23:58:11.808132 <6>[ 4.206317] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10824 23:58:11.814631 <6>[ 4.214656] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10825 23:58:11.824549 <6>[ 4.222995] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10826 23:58:11.831283 <6>[ 4.231332] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10827 23:58:11.841014 <6>[ 4.239677] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10828 23:58:11.847557 <6>[ 4.248016] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10829 23:58:11.857527 <6>[ 4.256353] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10830 23:58:11.864216 <6>[ 4.264691] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10831 23:58:11.870747 <6>[ 4.273425] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10832 23:58:11.877653 <6>[ 4.280594] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10833 23:58:11.884488 <6>[ 4.287341] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10834 23:58:11.891467 <6>[ 4.294117] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10835 23:58:11.901425 <6>[ 4.301054] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10836 23:58:11.907838 <6>[ 4.307899] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10837 23:58:11.918128 <6>[ 4.317029] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10838 23:58:11.928047 <6>[ 4.326150] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10839 23:58:11.937802 <6>[ 4.335445] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10840 23:58:11.947953 <6>[ 4.344913] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10841 23:58:11.954738 <6>[ 4.354380] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10842 23:58:11.964450 <6>[ 4.363500] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10843 23:58:11.973975 <6>[ 4.372967] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10844 23:58:11.983993 <6>[ 4.382086] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10845 23:58:11.993814 <6>[ 4.391391] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10846 23:58:12.003402 <6>[ 4.401552] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10847 23:58:12.013744 <6>[ 4.413333] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10848 23:58:12.067269 <6>[ 4.466804] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10849 23:58:12.222057 <6>[ 4.624517] hub 1-1:1.0: USB hub found
10850 23:58:12.224912 <6>[ 4.629042] hub 1-1:1.0: 4 ports detected
10851 23:58:12.234992 <6>[ 4.637711] hub 1-1:1.0: USB hub found
10852 23:58:12.237964 <6>[ 4.642027] hub 1-1:1.0: 4 ports detected
10853 23:58:12.347556 <6>[ 4.747145] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10854 23:58:12.374014 <6>[ 4.776509] hub 2-1:1.0: USB hub found
10855 23:58:12.376957 <6>[ 4.780998] hub 2-1:1.0: 3 ports detected
10856 23:58:12.386007 <6>[ 4.789095] hub 2-1:1.0: USB hub found
10857 23:58:12.389324 <6>[ 4.793548] hub 2-1:1.0: 3 ports detected
10858 23:58:12.562964 <6>[ 4.962899] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10859 23:58:12.695520 <6>[ 5.098314] hub 1-1.4:1.0: USB hub found
10860 23:58:12.698612 <6>[ 5.102939] hub 1-1.4:1.0: 2 ports detected
10861 23:58:12.708807 <6>[ 5.111642] hub 1-1.4:1.0: USB hub found
10862 23:58:12.712142 <6>[ 5.116294] hub 1-1.4:1.0: 2 ports detected
10863 23:58:12.775258 <6>[ 5.174936] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10864 23:58:12.883442 <6>[ 5.283393] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10865 23:58:12.919295 <4>[ 5.318617] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10866 23:58:12.928841 <4>[ 5.327760] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10867 23:58:12.965352 <6>[ 5.368166] r8152 2-1.3:1.0 eth0: v1.12.13
10868 23:58:13.007143 <6>[ 5.406829] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10869 23:58:13.199133 <6>[ 5.598658] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10870 23:58:14.594426 <6>[ 6.997718] r8152 2-1.3:1.0 eth0: carrier on
10871 23:58:16.635341 <5>[ 7.018650] Sending DHCP requests .., OK
10872 23:58:16.642144 <6>[ 9.042977] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10873 23:58:16.645166 <6>[ 9.051256] IP-Config: Complete:
10874 23:58:16.658846 <6>[ 9.054753] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10875 23:58:16.665128 <6>[ 9.065472] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10876 23:58:16.671777 <6>[ 9.074092] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10877 23:58:16.678150 <6>[ 9.074102] nameserver0=192.168.201.1
10878 23:58:16.681608 <6>[ 9.086248] clk: Disabling unused clocks
10879 23:58:16.684982 <6>[ 9.091657] ALSA device list:
10880 23:58:16.691236 <6>[ 9.094974] No soundcards found.
10881 23:58:16.698882 <6>[ 9.102454] Freeing unused kernel memory: 8512K
10882 23:58:16.702733 <6>[ 9.107466] Run /init as init process
10883 23:58:16.731663 <6>[ 9.134681] NET: Registered PF_INET6 protocol family
10884 23:58:16.738236 <6>[ 9.141627] Segment Routing with IPv6
10885 23:58:16.741996 <6>[ 9.145613] In-situ OAM (IOAM) with IPv6
10886 23:58:16.785421 <30>[ 9.162308] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10887 23:58:16.792191 <30>[ 9.195368] systemd[1]: Detected architecture arm64.
10888 23:58:16.792654
10889 23:58:16.798345 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10890 23:58:16.798830
10891 23:58:16.811414 <30>[ 9.214947] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10892 23:58:16.928560 <30>[ 9.328604] systemd[1]: Queued start job for default target graphical.target.
10893 23:58:16.968362 <30>[ 9.368344] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10894 23:58:16.974662 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10895 23:58:16.995347 <30>[ 9.395366] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10896 23:58:17.005085 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10897 23:58:17.023348 <30>[ 9.423446] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10898 23:58:17.032874 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10899 23:58:17.052513 <30>[ 9.452367] systemd[1]: Created slice user.slice - User and Session Slice.
10900 23:58:17.058933 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10901 23:58:17.082519 <30>[ 9.479384] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10902 23:58:17.092158 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10903 23:58:17.109620 <30>[ 9.506738] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10904 23:58:17.116015 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10905 23:58:17.144585 <30>[ 9.534737] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10906 23:58:17.154100 <30>[ 9.554451] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10907 23:58:17.160715 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10908 23:58:17.179260 <30>[ 9.579268] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10909 23:58:17.188822 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10910 23:58:17.206671 <30>[ 9.607178] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10911 23:58:17.217153 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10912 23:58:17.231933 <30>[ 9.635327] systemd[1]: Reached target paths.target - Path Units.
10913 23:58:17.241603 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10914 23:58:17.259095 <30>[ 9.659276] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10915 23:58:17.265759 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10916 23:58:17.279478 <30>[ 9.682823] systemd[1]: Reached target slices.target - Slice Units.
10917 23:58:17.289212 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10918 23:58:17.303504 <30>[ 9.707310] systemd[1]: Reached target swap.target - Swaps.
10919 23:58:17.310284 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10920 23:58:17.331107 <30>[ 9.731331] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10921 23:58:17.340915 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10922 23:58:17.358987 <30>[ 9.759319] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10923 23:58:17.368633 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10924 23:58:17.388916 <30>[ 9.789096] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10925 23:58:17.398519 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10926 23:58:17.415146 <30>[ 9.815477] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10927 23:58:17.425007 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10928 23:58:17.442989 <30>[ 9.843437] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10929 23:58:17.449658 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10930 23:58:17.467165 <30>[ 9.867461] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10931 23:58:17.477512 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10932 23:58:17.495149 <30>[ 9.895320] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10933 23:58:17.505156 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10934 23:58:17.558803 <30>[ 9.958942] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10935 23:58:17.565556 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10936 23:58:17.578374 <30>[ 9.978554] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10937 23:58:17.585054 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10938 23:58:17.607076 <30>[ 10.007279] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10939 23:58:17.613510 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10940 23:58:17.641699 <30>[ 10.035351] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10941 23:58:17.679090 <30>[ 10.079140] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10942 23:58:17.688937 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10943 23:58:17.711345 <30>[ 10.111545] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10944 23:58:17.717965 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10945 23:58:17.743935 <30>[ 10.144002] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10946 23:58:17.757288 Starting [0;1;39mmodpr<6>[ 10.155192] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10947 23:58:17.760426 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10948 23:58:17.815374 <30>[ 10.215340] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10949 23:58:17.821787 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10950 23:58:17.843690 <30>[ 10.243644] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10951 23:58:17.853314 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10952 23:58:17.875885 <30>[ 10.276002] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10953 23:58:17.882292 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10954 23:58:17.931486 <30>[ 10.331206] systemd[1]: Starting systemd-journald.service - Journal Service...
10955 23:58:17.937772 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10956 23:58:17.957593 <30>[ 10.357863] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10957 23:58:17.964126 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10958 23:58:17.991386 <30>[ 10.388318] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10959 23:58:17.998102 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10960 23:58:18.063580 <30>[ 10.463473] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10961 23:58:18.073202 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10962 23:58:18.094293 <30>[ 10.494403] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10963 23:58:18.103704 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10964 23:58:18.126290 <30>[ 10.526872] systemd[1]: Started systemd-journald.service - Journal Service.
10965 23:58:18.133148 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10966 23:58:18.153373 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10967 23:58:18.171186 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10968 23:58:18.191644 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10969 23:58:18.212026 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10970 23:58:18.233022 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10971 23:58:18.253400 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10972 23:58:18.278369 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10973 23:58:18.298315 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10974 23:58:18.316361 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10975 23:58:18.336302 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10976 23:58:18.356400 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10977 23:58:18.377659 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10978 23:58:18.391392 See 'systemctl status systemd-remount-fs.service' for details.
10979 23:58:18.402342 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10980 23:58:18.421513 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10981 23:58:18.467229 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10982 23:58:18.489232 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10983 23:58:18.504576 <46>[ 10.904563] systemd-journald[196]: Received client request to flush runtime journal.
10984 23:58:18.516354 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10985 23:58:18.538771 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10986 23:58:18.559666 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10987 23:58:18.584374 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10988 23:58:18.603979 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10989 23:58:18.623799 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10990 23:58:18.644178 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10991 23:58:18.663755 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10992 23:58:18.711639 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10993 23:58:18.743122 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10994 23:58:18.763156 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10995 23:58:18.778863 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10996 23:58:18.827085 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10997 23:58:18.846922 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10998 23:58:18.869843 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10999 23:58:18.939879 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11000 23:58:18.970242 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11001 23:58:18.995133 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11002 23:58:19.054825 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11003 23:58:19.073033 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11004 23:58:19.115608 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11005 23:58:19.221477 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11006 23:58:19.243614 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11007 23:58:19.263476 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11008 23:58:19.287688 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11009 23:58:19.307382 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11010 23:58:19.323999 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11011 23:58:19.342780 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11012 23:58:19.363448 <6>[ 11.763124] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11013 23:58:19.369376 <6>[ 11.770971] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11014 23:58:19.379651 <6>[ 11.779687] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11015 23:58:19.392750 [[0;32m OK [0m] Reached target [0;1;39mbasi<3>[ 11.791504] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11016 23:58:19.402345 c.target[0m - B<3>[ 11.800733] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11017 23:58:19.402914 asic System.
11018 23:58:19.412941 <3>[ 11.810178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 23:58:19.418802 <6>[ 11.813997] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11020 23:58:19.445216 <3>[ 11.845315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11021 23:58:19.451455 <3>[ 11.853485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11022 23:58:19.460322 <6>[ 11.863907] remoteproc remoteproc0: scp is available
11023 23:58:19.470041 <3>[ 11.865321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11024 23:58:19.473658 <6>[ 11.869246] remoteproc remoteproc0: powering up scp
11025 23:58:19.483516 <3>[ 11.877285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11026 23:58:19.490420 <6>[ 11.882417] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11027 23:58:19.500205 <3>[ 11.890499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11028 23:58:19.503021 <6>[ 11.899315] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11029 23:58:19.512991 <3>[ 11.913096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11030 23:58:19.539498 <3>[ 11.940096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11031 23:58:19.546461 <3>[ 11.948216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11032 23:58:19.556435 <3>[ 11.956308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11033 23:58:19.572956 <3>[ 11.973652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11034 23:58:19.579937 <3>[ 11.981773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11035 23:58:19.589732 <3>[ 11.989862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11036 23:58:19.596562 <3>[ 11.997951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11037 23:58:19.606212 <3>[ 12.006032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11038 23:58:19.612516 <6>[ 12.012106] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11039 23:58:19.622456 <3>[ 12.014142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11040 23:58:19.629782 <6>[ 12.024347] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11041 23:58:19.632777 <6>[ 12.036839] pci_bus 0000:00: root bus resource [bus 00-ff]
11042 23:58:19.642134 <6>[ 12.038446] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11043 23:58:19.649066 <6>[ 12.038507] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11044 23:58:19.655506 <6>[ 12.038516] remoteproc remoteproc0: remote processor scp is now up
11045 23:58:19.662121 <6>[ 12.043148] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11046 23:58:19.671801 <4>[ 12.051418] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11047 23:58:19.675573 <4>[ 12.051418] Fallback method does not support PEC.
11048 23:58:19.685397 <6>[ 12.062110] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11049 23:58:19.695430 <3>[ 12.084202] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11050 23:58:19.701836 <6>[ 12.085787] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11051 23:58:19.708921 <6>[ 12.110460] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11052 23:58:19.715267 <6>[ 12.118027] pci 0000:00:00.0: supports D1 D2
11053 23:58:19.721824 <6>[ 12.122550] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11054 23:58:19.729343 Starting [0;1;39mdbus.service[0m - D-<6>[ 12.133388] mc: Linux media interface: v0.10
11055 23:58:19.739008 Bus System Messa<3>[ 12.137298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 23:58:19.739430 ge Bus...
11057 23:58:19.754850 <6>[ 12.155160] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11058 23:58:19.772581 <6>[ 12.169179] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11059 23:58:19.788022 <6>[ 12.188571] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11060 23:58:19.794832 <6>[ 12.198449] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11061 23:58:19.804286 <6>[ 12.204761] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11062 23:58:19.811220 <6>[ 12.212256] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11063 23:58:19.818321 <6>[ 12.219749] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11064 23:58:19.824847 <6>[ 12.227354] pci 0000:01:00.0: supports D1 D2
11065 23:58:19.830963 <6>[ 12.231879] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11066 23:58:19.840882 <6>[ 12.244555] videodev: Linux video capture interface: v2.00
11067 23:58:19.847492 <4>[ 12.244592] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11068 23:58:19.857317 <6>[ 12.256026] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11069 23:58:19.863974 <4>[ 12.261878] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11070 23:58:19.870252 <6>[ 12.264595] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11071 23:58:19.880507 <6>[ 12.279967] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11072 23:58:19.887007 <6>[ 12.287975] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11073 23:58:19.894135 <6>[ 12.295981] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11074 23:58:19.903608 <6>[ 12.303988] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11075 23:58:19.906858 <6>[ 12.311995] pci 0000:00:00.0: PCI bridge to [bus 01]
11076 23:58:19.916832 <6>[ 12.317215] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11077 23:58:19.939813 <6>[ 12.343406] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11078 23:58:19.952927 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11079 23:58:19.963585 <3>[ 12.363873] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11080 23:58:20.000315 <6>[ 12.400808] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11081 23:58:20.044152 <3>[ 12.444350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11082 23:58:20.057006 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11083 23:58:20.090297 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11084 23:58:20.118314 <3>[ 12.518808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11085 23:58:20.146877 <6>[ 12.547239] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11086 23:58:20.153266 <6>[ 12.547604] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11087 23:58:20.162940 <6>[ 12.557071] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11088 23:58:20.173729 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11089 23:58:20.218082 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/system<3>[ 12.616664] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11090 23:58:20.218815 d-backlight.
11091 23:58:20.224639 <6>[ 12.628497] usbcore: registered new interface driver uvcvideo
11092 23:58:20.247805 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11093 23:58:20.258920 <6>[ 12.659383] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11094 23:58:20.262232 <6>[ 12.668788] Bluetooth: Core ver 2.22
11095 23:58:20.272864 <6>[ 12.676764] NET: Registered PF_BLUETOOTH protocol family
11096 23:58:20.279707 <6>[ 12.682658] Bluetooth: HCI device and connection manager initialized
11097 23:58:20.286319 <6>[ 12.689536] Bluetooth: HCI socket layer initialized
11098 23:58:20.292750 <6>[ 12.694907] Bluetooth: L2CAP socket layer initialized
11099 23:58:20.300521 <6>[ 12.701305] Bluetooth: SCO socket layer initialized
11100 23:58:20.350660 <6>[ 12.754354] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11101 23:58:20.364788 <3>[ 12.765240] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11102 23:58:20.379848 <6>[ 12.780437] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11103 23:58:20.398606 <6>[ 12.801881] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11104 23:58:20.419827 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11105 23:58:20.437981 <3>[ 12.838684] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11106 23:58:20.467182 <4>[ 12.864466] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11107 23:58:20.471080 <6>[ 12.867960] usbcore: registered new interface driver btusb
11108 23:58:20.480777 <5>[ 12.871923] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11109 23:58:20.487704 <3>[ 12.875017] Bluetooth: hci0: Failed to load firmware file (-2)
11110 23:58:20.493665 <3>[ 12.883398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11111 23:58:20.500025 <3>[ 12.888761] Bluetooth: hci0: Failed to set up firmware (-2)
11112 23:58:20.507214 <5>[ 12.903380] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11113 23:58:20.517165 <4>[ 12.903622] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11114 23:58:20.527266 <5>[ 12.910497] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11115 23:58:20.533615 <3>[ 12.921206] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11116 23:58:20.543730 <4>[ 12.926764] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11117 23:58:20.547231 <6>[ 12.952811] cfg80211: failed to load regulatory.db
11118 23:58:20.558087 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11119 23:58:20.579521 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11120 23:58:20.596146 <6>[ 12.996731] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11121 23:58:20.602874 <6>[ 13.004243] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11122 23:58:20.629750 Starting [0;1;39msyste<6>[ 13.031627] mt7921e 0000:01:00.0: ASIC revision: 79610010
11123 23:58:20.649545 <46>[ 13.033269] systemd-journald[196]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1540 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11124 23:58:20.665717 md-backlight…e<46>[ 13.059715] systemd-journald[196]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11125 23:58:20.668758 ss of leds:white:kbd_backlight...
11126 23:58:20.698422 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11127 23:58:20.735498 <6>[ 13.136101] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11128 23:58:20.738491 <6>[ 13.136101]
11129 23:58:20.745091 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11130 23:58:20.767718 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11131 23:58:20.787266 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11132 23:58:20.807537 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11133 23:58:20.857526 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11134 23:58:20.883453 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11135 23:58:20.904224 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11136 23:58:20.939795 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11137 23:58:20.977735
11138 23:58:20.980738 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11139 23:58:20.981516
11140 23:58:20.984154 debian-bookworm-arm64 login: root (automatic login)
11141 23:58:20.984645
11142 23:58:21.003769 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May <6>[ 13.402610] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11143 23:58:21.007299 29 23:36:28 UTC 2024 aarch64
11144 23:58:21.007717
11145 23:58:21.013705 The programs included with the Debian GNU/Linux system are free software;
11146 23:58:21.017316 the exact distribution terms for each program are described in the
11147 23:58:21.023320 individual files in /usr/share/doc/*/copyright.
11148 23:58:21.023740
11149 23:58:21.030222 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11150 23:58:21.030644 permitted by applicable law.
11151 23:58:21.031842 Matched prompt #10: / #
11153 23:58:21.032804 Setting prompt string to ['/ #']
11154 23:58:21.033226 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11156 23:58:21.034233 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11157 23:58:21.034813 start: 2.2.6 expect-shell-connection (timeout 00:02:19) [common]
11158 23:58:21.035171 Setting prompt string to ['/ #']
11159 23:58:21.035471 Forcing a shell prompt, looking for ['/ #']
11161 23:58:21.086403 / #
11162 23:58:21.087242 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11163 23:58:21.087710 Waiting using forced prompt support (timeout 00:02:30)
11164 23:58:21.092746
11165 23:58:21.093557 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11166 23:58:21.094068 start: 2.2.7 export-device-env (timeout 00:02:19) [common]
11167 23:58:21.094619 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11168 23:58:21.095102 end: 2.2 depthcharge-retry (duration 00:02:41) [common]
11169 23:58:21.095622 end: 2 depthcharge-action (duration 00:02:41) [common]
11170 23:58:21.096111 start: 3 lava-test-retry (timeout 00:06:54) [common]
11171 23:58:21.096585 start: 3.1 lava-test-shell (timeout 00:06:54) [common]
11172 23:58:21.096999 Using namespace: common
11174 23:58:21.198252 / # #
11175 23:58:21.198886 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11176 23:58:21.204654 #
11177 23:58:21.205552 Using /lava-14084377
11179 23:58:21.306873 / # export SHELL=/bin/sh
11180 23:58:21.313251 export SHELL=/bin/sh
11182 23:58:21.415017 / # . /lava-14084377/environment
11183 23:58:21.421477 . /lava-14084377/environment
11185 23:58:21.523279 / # /lava-14084377/bin/lava-test-runner /lava-14084377/0
11186 23:58:21.523932 Test shell timeout: 10s (minimum of the action and connection timeout)
11187 23:58:21.529778 /lava-14084377/bin/lava-test-runner /lava-14084377/0
11188 23:58:21.556024 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14084377_1.5.2.3.1
11189 23:58:21.556581 Starting test lava.0_igt-gpu-panfrost (14084377_1.5.2.3.1)
11190 23:58:21.557035 Skipping test definition patterns.
11191 23:58:21.559344 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 13.958644] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14084377_1.5.2.3.1>
11192 23:58:21.559968 rost
11193 23:58:21.562052 + cd /lava-14084377/0/tests/0_igt-gpu-panfrost
11194 23:58:21.562650 + cat uuid
11195 23:58:21.565431 + UUID=14084377_1.5.2.3.1
11196 23:58:21.565899 + set +x
11197 23:58:21.581825 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime pan<8>[ 13.984295] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11198 23:58:21.582442 frost_submit
11199 23:58:21.583084 Received signal: <TESTSET> START panfrost_gem_new
11200 23:58:21.583471 Starting test_set panfrost_gem_new
11201 23:58:21.601799 <14>[ 14.005553] [IGT] panfrost_gem_new: executing
11202 23:58:21.608537 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 14.012754] [IGT] panfrost_gem_new: exiting, ret=77
11203 23:58:21.611810 h64) (Linux: 6.1.91-cip21 aarch64)
11204 23:58:21.621530 Using IGT_SRANDOM=1717027101<8>[ 14.023122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11205 23:58:21.622348 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11207 23:58:21.624457 for randomisation
11208 23:58:21.631214 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11209 23:58:21.634695 Test requirement: !(fd<0)
11210 23:58:21.641363 No known gpu found for chipset <14>[ 14.044184] [IGT] panfrost_gem_new: executing
11211 23:58:21.641964 flags 0x32 (panfrost)
11212 23:58:21.647470 Last errn<14>[ 14.052004] [IGT] panfrost_gem_new: exiting, ret=77
11213 23:58:21.651258 o: 2, No such file or directory
11214 23:58:21.660986 [1mSubtest gem-new-4096: SKIP <8>[ 14.062165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11215 23:58:21.661452 (0.000s)[0m
11216 23:58:21.662238 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11218 23:58:21.667482 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11219 23:58:21.670729 Using IGT_SRANDOM=1717027101 for randomisation
11220 23:58:21.681220 Test requirement not met in fu<14>[ 14.083890] [IGT] panfrost_gem_new: executing
11221 23:58:21.687128 nction drm_open_driver, file ../<14>[ 14.090858] [IGT] panfrost_gem_new: exiting, ret=77
11222 23:58:21.690353 lib/drmtest.c:694:
11223 23:58:21.690781 Test requirement: !(fd<0)
11224 23:58:21.700498 No known gpu foun<8>[ 14.101241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11225 23:58:21.701339 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11227 23:58:21.706758 d for chipset fl<8>[ 14.110911] <LAVA_SIGNAL_TESTSET STOP>
11228 23:58:21.707198 ags 0x32 (panfrost)
11229 23:58:21.707895 Received signal: <TESTSET> STOP
11230 23:58:21.708280 Closing test_set panfrost_gem_new
11231 23:58:21.710342 Last errno: 2, No such file or directory
11232 23:58:21.716479 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11233 23:58:21.720067 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11234 23:58:21.729951 Using IGT_SRANDOM=1<8>[ 14.131628] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11235 23:58:21.730722 717027101 for randomisation
11236 23:58:21.731378 Received signal: <TESTSET> START panfrost_get_param
11237 23:58:21.731722 Starting test_set panfrost_get_param
11238 23:58:21.740764 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11239 23:58:21.741333 Test requirement: !(fd<0)
11240 23:58:21.749579 No known gpu found for chipset flags 0<14>[ 14.151558] [IGT] panfrost_get_param: executing
11241 23:58:21.750147 x32 (panfrost)
11242 23:58:21.756081 Last errno: 2, N<14>[ 14.159760] [IGT] panfrost_get_param: exiting, ret=77
11243 23:58:21.759744 o such file or directory
11244 23:58:21.769618 [1mSubtest gem-new-zeroed: SKIP (0.00<8>[ 14.170672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11245 23:58:21.770207 0s)[0m
11246 23:58:21.770882 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11248 23:58:21.775900 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11249 23:58:21.779354 Using IGT_SRANDOM=1717027101 for randomisation
11250 23:58:21.789163 Test requirement not met in functio<14>[ 14.191741] [IGT] panfrost_get_param: executing
11251 23:58:21.795485 n drm_open_driver, file ../lib/d<14>[ 14.199427] [IGT] panfrost_get_param: exiting, ret=77
11252 23:58:21.799126 rmtest.c:694:
11253 23:58:21.799583 Test requirement: !(fd<0)
11254 23:58:21.808618 No known gpu found for<8>[ 14.210304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11255 23:58:21.809303 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11257 23:58:21.811934 chipset flags 0x32 (panfrost)
11258 23:58:21.815415 Last errno: 2, No such file or directory
11259 23:58:21.819006 [1mSubtest base-params: SKIP (0.000s)[0m
11260 23:58:21.828885 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<14>[ 14.231429] [IGT] panfrost_get_param: executing
11261 23:58:21.832023 x: 6.1.91-cip21 aarch64)
11262 23:58:21.838612 Using IGT_SRANDOM=1717<14>[ 14.240175] [IGT] panfrost_get_param: exiting, ret=77
11263 23:58:21.839138 027102 for randomisation
11264 23:58:21.851428 Test requirement not met in function drm_open_driver, <8>[ 14.252529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11265 23:58:21.852197 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11267 23:58:21.855129 file ../lib/drmtest.c:694:
11268 23:58:21.858271 Test<8>[ 14.262462] <LAVA_SIGNAL_TESTSET STOP>
11269 23:58:21.858946 Received signal: <TESTSET> STOP
11270 23:58:21.859293 Closing test_set panfrost_get_param
11271 23:58:21.861464 requirement: !(fd<0)
11272 23:58:21.864630 No known gpu found for chipset flags 0x32 (panfrost)
11273 23:58:21.871637 Las<6>[ 14.273559] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11274 23:58:21.874987 t errno: 2, No such file or directory
11275 23:58:21.881892 [1mSubte<8>[ 14.284607] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11276 23:58:21.882731 Received signal: <TESTSET> START panfrost_prime
11277 23:58:21.883090 Starting test_set panfrost_prime
11278 23:58:21.884926 st get-bad-param: SKIP (0.000s)[0m
11279 23:58:21.891280 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11280 23:58:21.894738 Using IGT_SRANDOM=1717027102 for randomisation
11281 23:58:21.901449 Test requirement not me<14>[ 14.304400] [IGT] panfrost_prime: executing
11282 23:58:21.907931 t in function drm_open_driver, f<14>[ 14.312717] [IGT] panfrost_prime: exiting, ret=77
11283 23:58:21.910925 ile ../lib/drmtest.c:694:
11284 23:58:21.914265 Test requirement: !(fd<0)
11285 23:58:21.924330 No known gpu found for chi<8>[ 14.324259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11286 23:58:21.924848 pset flags 0x32 (panfrost)
11287 23:58:21.925443 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11289 23:58:21.930723 Last errno: 2, No su<8>[ 14.335854] <LAVA_SIGNAL_TESTSET STOP>
11290 23:58:21.931515 Received signal: <TESTSET> STOP
11291 23:58:21.931965 Closing test_set panfrost_prime
11292 23:58:21.933849 ch file or directory
11293 23:58:21.937140 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11294 23:58:21.943774 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11295 23:58:21.947470 Using IGT_SRANDOM=1717027102 for randomisation
11296 23:58:21.953767 Test r<8>[ 14.356710] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11297 23:58:21.954653 Received signal: <TESTSET> START panfrost_submit
11298 23:58:21.955099 Starting test_set panfrost_submit
11299 23:58:21.960177 equirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11300 23:58:21.963531 Test requirement: !(fd<0)
11301 23:58:21.966803 No known gpu found for chipset flags 0x32 (panfrost)
11302 23:58:21.973427 Las<14>[ 14.376299] [IGT] panfrost_submit: executing
11303 23:58:21.980349 t errno: 2, No such file or dire<14>[ 14.383502] [IGT] panfrost_submit: exiting, ret=77
11304 23:58:21.980919 ctory
11305 23:58:21.986725 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11306 23:58:21.993310 IGT-Vers<8>[ 14.393763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11307 23:58:21.994149 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11309 23:58:21.996570 ion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11310 23:58:22.003192 Using IGT_SRANDOM=1717027102 for randomisation
11311 23:58:22.009904 Test requirement not met in function drm_open_driver<14>[ 14.414697] [IGT] panfrost_submit: executing
11312 23:58:22.013253 , file ../lib/drmtest.c:694:
11313 23:58:22.020224 Te<14>[ 14.422369] [IGT] panfrost_submit: exiting, ret=77
11314 23:58:22.023110 st requirement: !(fd<0)
11315 23:58:22.032728 No known gpu found for chipset flags 0x<8>[ 14.432885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11316 23:58:22.033289 32 (panfrost)
11317 23:58:22.033936 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11319 23:58:22.036066 Last errno: 2, No such file or directory
11320 23:58:22.043132 [1mSubtest pan-submit: SKIP (0.000s)[0m
11321 23:58:22.052434 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aa<14>[ 14.454919] [IGT] panfrost_submit: executing
11322 23:58:22.052853 rch64)
11323 23:58:22.059394 Using IGT_SRANDOM=171702<14>[ 14.462363] [IGT] panfrost_submit: exiting, ret=77
11324 23:58:22.062499 7102 for randomisation
11325 23:58:22.075531 Test requirement not met in function drm_open_driver, fi<8>[ 14.474033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11326 23:58:22.076066 le ../lib/drmtest.c:694:
11327 23:58:22.076668 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11329 23:58:22.078797 Test requirement: !(fd<0)
11330 23:58:22.082092 No known gpu found for chipset flags 0x32 (panfrost)
11331 23:58:22.088872 Last errno: 2, No such file or directory
11332 23:58:22.095370 [1mSubtest pan-submit-erro<14>[ 14.498541] [IGT] panfrost_submit: executing
11333 23:58:22.095841 r-no-jc: SKIP (0.000s)[0m
11334 23:58:22.102158 IGT-<14>[ 14.505795] [IGT] panfrost_submit: exiting, ret=77
11335 23:58:22.108661 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11336 23:58:22.115045 <8>[ 14.516894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11337 23:58:22.116175 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11339 23:58:22.121674 Using IGT_SRANDOM=1717027102 for randomisation
11340 23:58:22.128616 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11341 23:58:22.131711 Test requirement: !(fd<0)
11342 23:58:22.134927 No <14>[ 14.539188] [IGT] panfrost_submit: executing
11343 23:58:22.141559 known gpu found for chipset flag<14>[ 14.546448] [IGT] panfrost_submit: exiting, ret=77
11344 23:58:22.145538 s 0x32 (panfrost)
11345 23:58:22.148257 Last errno: 2, No such file or directory
11346 23:58:22.158372 [1mSubtest pan-sub<8>[ 14.558744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11347 23:58:22.159212 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11349 23:58:22.161649 mit-error-bad-in-syncs: SKIP (0.000s)[0m
11350 23:58:22.168045 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11351 23:58:22.171232 Using IGT_SRANDOM=1717027102 for randomisation
11352 23:58:22.181368 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11353 23:58:22.181840 Test requirement: !(fd<0)
11354 23:58:22.187896 No known gpu found for chipset flags 0x32 (panfrost)
11355 23:58:22.194104 Last errno: 2, No such file or<14>[ 14.597075] [IGT] panfrost_submit: executing
11356 23:58:22.194574 directory
11357 23:58:22.204004 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0<14>[ 14.607339] [IGT] panfrost_submit: exiting, ret=77
11358 23:58:22.207793 .000s)[0m
11359 23:58:22.217314 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-<8>[ 14.619254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11360 23:58:22.217997 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11362 23:58:22.220642 cip21 aarch64)
11363 23:58:22.224011 Using IGT_SRANDOM=1717027102 for randomisation
11364 23:58:22.230444 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11365 23:58:22.233976 Test requirement: !(fd<0)
11366 23:58:22.237494 No <14>[ 14.642207] [IGT] panfrost_submit: executing
11367 23:58:22.246717 known gpu found for chipset flag<14>[ 14.649964] [IGT] panfrost_submit: exiting, ret=77
11368 23:58:22.247218 s 0x32 (panfrost)
11369 23:58:22.253556 Last errno: 2, No such file or directory
11370 23:58:22.260445 [1<8>[ 14.661233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11371 23:58:22.261128 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11373 23:58:22.263598 mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11374 23:58:22.270311 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11375 23:58:22.276721 Using IGT_SRANDOM=1717027102 <14>[ 14.681933] [IGT] panfrost_submit: executing
11376 23:58:22.280005 for randomisation
11377 23:58:22.286839 Test requirem<14>[ 14.689012] [IGT] panfrost_submit: exiting, ret=77
11378 23:58:22.299629 ent not met in function drm_open_driver, file ../lib/drmtest.c:6<8>[ 14.700098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11379 23:58:22.300067 94:
11380 23:58:22.300758 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11382 23:58:22.303021 Test requirement: !(fd<0)
11383 23:58:22.306490 No known gpu found for chipset flags 0x32 (panfrost)
11384 23:58:22.309938 Last errno: 2, No such file or directory
11385 23:58:22.319413 [1mSubtest pan-submit-error-bad-out-sync: SKIP <14>[ 14.721998] [IGT] panfrost_submit: executing
11386 23:58:22.319893 (0.000s)[0m
11387 23:58:22.326327 IGT-Version: 1.28-<14>[ 14.730221] [IGT] panfrost_submit: exiting, ret=77
11388 23:58:22.329285 ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11389 23:58:22.339295 Using IGT_SRAN<8>[ 14.741018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11390 23:58:22.339983 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11392 23:58:22.346392 DOM=1717027102 for randomisation<8>[ 14.751029] <LAVA_SIGNAL_TESTSET STOP>
11393 23:58:22.346914
11394 23:58:22.347511 Received signal: <TESTSET> STOP
11395 23:58:22.347847 Closing test_set panfrost_submit
11396 23:58:22.355942 Test requireme<8>[ 14.756873] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14084377_1.5.2.3.1>
11397 23:58:22.356759 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14084377_1.5.2.3.1
11398 23:58:22.357211 Ending use of test pattern.
11399 23:58:22.357592 Ending test lava.0_igt-gpu-panfrost (14084377_1.5.2.3.1), duration 0.80
11401 23:58:22.362332 nt not met in function drm_open_driver, file ../lib/drmtest.c:694:
11402 23:58:22.362757 Test requirement: !(fd<0)
11403 23:58:22.369090 No known gpu found for chipset flags 0x32 (panfrost)
11404 23:58:22.372774 Last errno: 2, No such file or directory
11405 23:58:22.375584 [1mSubtest pan-reset: SKIP (0.000s)[0m
11406 23:58:22.381966 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11407 23:58:22.385535 Using IGT_SRANDOM=1717027102 for randomisation
11408 23:58:22.392265 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11409 23:58:22.395570 Test requirement: !(fd<0)
11410 23:58:22.398885 No known gpu found for chipset flags 0x32 (panfrost)
11411 23:58:22.401936 Last errno: 2, No such file or directory
11412 23:58:22.408681 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11413 23:58:22.415380 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11414 23:58:22.418600 Using IGT_SRANDOM=1717027102 for randomisation
11415 23:58:22.425157 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11416 23:58:22.428520 Test requirement: !(fd<0)
11417 23:58:22.431660 No known gpu found for chipset flags 0x32 (panfrost)
11418 23:58:22.434895 Last errno: 2, No such file or directory
11419 23:58:22.441639 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11420 23:58:22.442057 + set +x
11421 23:58:22.444693 <LAVA_TEST_RUNNER EXIT>
11422 23:58:22.445375 ok: lava_test_shell seems to have completed
11423 23:58:22.447007 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11424 23:58:22.447492 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11425 23:58:22.447909 end: 3 lava-test-retry (duration 00:00:01) [common]
11426 23:58:22.448328 start: 4 finalize (timeout 00:06:53) [common]
11427 23:58:22.448782 start: 4.1 power-off (timeout 00:00:30) [common]
11428 23:58:22.449516 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11429 23:58:22.716981 >> Command sent successfully.
11430 23:58:22.728462 Returned 0 in 0 seconds
11431 23:58:22.829759 end: 4.1 power-off (duration 00:00:00) [common]
11433 23:58:22.831403 start: 4.2 read-feedback (timeout 00:06:52) [common]
11434 23:58:22.832680 Listened to connection for namespace 'common' for up to 1s
11435 23:58:23.833329 Finalising connection for namespace 'common'
11436 23:58:23.834033 Disconnecting from shell: Finalise
11437 23:58:23.834478 / #
11438 23:58:23.935657 end: 4.2 read-feedback (duration 00:00:01) [common]
11439 23:58:23.936389 end: 4 finalize (duration 00:00:01) [common]
11440 23:58:23.936989 Cleaning after the job
11441 23:58:23.937495 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/ramdisk
11442 23:58:23.967518 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/kernel
11443 23:58:23.995482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/dtb
11444 23:58:23.995764 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084377/tftp-deploy-kbi4ick9/modules
11445 23:58:24.002477 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084377
11446 23:58:24.109919 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084377
11447 23:58:24.110092 Job finished correctly