Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:50:33.904162 lava-dispatcher, installed at version: 2024.03
2 23:50:33.904353 start: 0 validate
3 23:50:33.904486 Start time: 2024-05-29 23:50:33.904478+00:00 (UTC)
4 23:50:33.904602 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:50:33.904733 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:50:34.173499 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:50:34.173709 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:50:34.433820 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:50:34.434001 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:50:34.700293 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:50:34.700454 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:50:35.230892 validate duration: 1.33
14 23:50:35.231183 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:50:35.231301 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:50:35.231403 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:50:35.231535 Not decompressing ramdisk as can be used compressed.
18 23:50:35.231624 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:50:35.231687 saving as /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/ramdisk/rootfs.cpio.gz
20 23:50:35.231752 total size: 47897469 (45 MB)
21 23:50:35.232803 progress 0 % (0 MB)
22 23:50:35.245152 progress 5 % (2 MB)
23 23:50:35.257176 progress 10 % (4 MB)
24 23:50:35.269253 progress 15 % (6 MB)
25 23:50:35.281353 progress 20 % (9 MB)
26 23:50:35.293603 progress 25 % (11 MB)
27 23:50:35.305738 progress 30 % (13 MB)
28 23:50:35.317833 progress 35 % (16 MB)
29 23:50:35.330098 progress 40 % (18 MB)
30 23:50:35.342327 progress 45 % (20 MB)
31 23:50:35.354564 progress 50 % (22 MB)
32 23:50:35.366610 progress 55 % (25 MB)
33 23:50:35.378839 progress 60 % (27 MB)
34 23:50:35.390979 progress 65 % (29 MB)
35 23:50:35.403095 progress 70 % (32 MB)
36 23:50:35.415354 progress 75 % (34 MB)
37 23:50:35.427795 progress 80 % (36 MB)
38 23:50:35.439937 progress 85 % (38 MB)
39 23:50:35.452061 progress 90 % (41 MB)
40 23:50:35.463999 progress 95 % (43 MB)
41 23:50:35.475841 progress 100 % (45 MB)
42 23:50:35.476054 45 MB downloaded in 0.24 s (186.98 MB/s)
43 23:50:35.476205 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:50:35.476443 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:50:35.476528 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:50:35.476610 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:50:35.476739 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:50:35.476807 saving as /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/kernel/Image
50 23:50:35.476870 total size: 54682112 (52 MB)
51 23:50:35.476930 No compression specified
52 23:50:35.478134 progress 0 % (0 MB)
53 23:50:35.492020 progress 5 % (2 MB)
54 23:50:35.505761 progress 10 % (5 MB)
55 23:50:35.519619 progress 15 % (7 MB)
56 23:50:35.533511 progress 20 % (10 MB)
57 23:50:35.547408 progress 25 % (13 MB)
58 23:50:35.561035 progress 30 % (15 MB)
59 23:50:35.574891 progress 35 % (18 MB)
60 23:50:35.588745 progress 40 % (20 MB)
61 23:50:35.602754 progress 45 % (23 MB)
62 23:50:35.616594 progress 50 % (26 MB)
63 23:50:35.630490 progress 55 % (28 MB)
64 23:50:35.644523 progress 60 % (31 MB)
65 23:50:35.658373 progress 65 % (33 MB)
66 23:50:35.672384 progress 70 % (36 MB)
67 23:50:35.686135 progress 75 % (39 MB)
68 23:50:35.700070 progress 80 % (41 MB)
69 23:50:35.713993 progress 85 % (44 MB)
70 23:50:35.727725 progress 90 % (46 MB)
71 23:50:35.741655 progress 95 % (49 MB)
72 23:50:35.755257 progress 100 % (52 MB)
73 23:50:35.755486 52 MB downloaded in 0.28 s (187.17 MB/s)
74 23:50:35.755639 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:50:35.755896 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:50:35.755998 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:50:35.756082 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:50:35.756215 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:50:35.756289 saving as /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/dtb/mt8192-asurada-spherion-r0.dtb
81 23:50:35.756350 total size: 47258 (0 MB)
82 23:50:35.756409 No compression specified
83 23:50:35.757570 progress 69 % (0 MB)
84 23:50:35.757842 progress 100 % (0 MB)
85 23:50:35.757996 0 MB downloaded in 0.00 s (27.41 MB/s)
86 23:50:35.758117 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:50:35.758334 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:50:35.758417 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:50:35.758499 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:50:35.758609 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:50:35.758677 saving as /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/modules/modules.tar
93 23:50:35.758737 total size: 8601444 (8 MB)
94 23:50:35.758797 Using unxz to decompress xz
95 23:50:35.763017 progress 0 % (0 MB)
96 23:50:35.783092 progress 5 % (0 MB)
97 23:50:35.808065 progress 10 % (0 MB)
98 23:50:35.834192 progress 15 % (1 MB)
99 23:50:35.859295 progress 20 % (1 MB)
100 23:50:35.884837 progress 25 % (2 MB)
101 23:50:35.909733 progress 30 % (2 MB)
102 23:50:35.933185 progress 35 % (2 MB)
103 23:50:35.957310 progress 40 % (3 MB)
104 23:50:35.983541 progress 45 % (3 MB)
105 23:50:36.007090 progress 50 % (4 MB)
106 23:50:36.031472 progress 55 % (4 MB)
107 23:50:36.055610 progress 60 % (4 MB)
108 23:50:36.078982 progress 65 % (5 MB)
109 23:50:36.105219 progress 70 % (5 MB)
110 23:50:36.129931 progress 75 % (6 MB)
111 23:50:36.153222 progress 80 % (6 MB)
112 23:50:36.179274 progress 85 % (7 MB)
113 23:50:36.203190 progress 90 % (7 MB)
114 23:50:36.232032 progress 95 % (7 MB)
115 23:50:36.259805 progress 100 % (8 MB)
116 23:50:36.265165 8 MB downloaded in 0.51 s (16.20 MB/s)
117 23:50:36.265411 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:50:36.265666 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:50:36.265757 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:50:36.265851 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:50:36.265933 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:50:36.266022 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:50:36.266250 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7
125 23:50:36.266382 makedir: /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin
126 23:50:36.266488 makedir: /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/tests
127 23:50:36.266586 makedir: /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/results
128 23:50:36.266701 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-add-keys
129 23:50:36.266848 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-add-sources
130 23:50:36.266979 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-background-process-start
131 23:50:36.267112 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-background-process-stop
132 23:50:36.267238 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-common-functions
133 23:50:36.267362 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-echo-ipv4
134 23:50:36.267493 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-install-packages
135 23:50:36.267619 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-installed-packages
136 23:50:36.267742 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-os-build
137 23:50:36.267867 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-probe-channel
138 23:50:36.267990 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-probe-ip
139 23:50:36.268113 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-target-ip
140 23:50:36.268237 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-target-mac
141 23:50:36.268359 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-target-storage
142 23:50:36.268486 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-case
143 23:50:36.268609 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-event
144 23:50:36.268730 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-feedback
145 23:50:36.268852 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-raise
146 23:50:36.268980 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-reference
147 23:50:36.269157 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-runner
148 23:50:36.269282 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-set
149 23:50:36.269406 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-test-shell
150 23:50:36.269532 Updating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-install-packages (oe)
151 23:50:36.269682 Updating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/bin/lava-installed-packages (oe)
152 23:50:36.269804 Creating /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/environment
153 23:50:36.269903 LAVA metadata
154 23:50:36.269976 - LAVA_JOB_ID=14084325
155 23:50:36.270041 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:50:36.270142 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:50:36.270209 skipped lava-vland-overlay
158 23:50:36.270283 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:50:36.270363 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:50:36.270435 skipped lava-multinode-overlay
161 23:50:36.270507 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:50:36.270590 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:50:36.270663 Loading test definitions
164 23:50:36.270752 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:50:36.270824 Using /lava-14084325 at stage 0
166 23:50:36.271135 uuid=14084325_1.5.2.3.1 testdef=None
167 23:50:36.271223 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:50:36.271306 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:50:36.271819 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:50:36.272044 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:50:36.272657 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:50:36.272885 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:50:36.273521 runner path: /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/0/tests/0_igt-kms-mediatek test_uuid 14084325_1.5.2.3.1
176 23:50:36.273681 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:50:36.273886 Creating lava-test-runner.conf files
179 23:50:36.273949 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084325/lava-overlay-72kluzv7/lava-14084325/0 for stage 0
180 23:50:36.274038 - 0_igt-kms-mediatek
181 23:50:36.274136 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:50:36.274221 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:50:36.281461 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:50:36.281564 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:50:36.281649 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:50:36.281733 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:50:36.281815 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:50:38.018509 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 23:50:38.018901 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:50:38.019014 extracting modules file /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084325/extract-overlay-ramdisk-q55eidov/ramdisk
191 23:50:38.237729 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:50:38.237900 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 23:50:38.237992 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084325/compress-overlay-px9gn82f/overlay-1.5.2.4.tar.gz to ramdisk
194 23:50:38.238064 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084325/compress-overlay-px9gn82f/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084325/extract-overlay-ramdisk-q55eidov/ramdisk
195 23:50:38.244576 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:50:38.244698 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 23:50:38.244786 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:50:38.244880 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 23:50:38.244962 Building ramdisk /var/lib/lava/dispatcher/tmp/14084325/extract-overlay-ramdisk-q55eidov/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084325/extract-overlay-ramdisk-q55eidov/ramdisk
200 23:50:39.461391 >> 465919 blocks
201 23:50:45.732795 rename /var/lib/lava/dispatcher/tmp/14084325/extract-overlay-ramdisk-q55eidov/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/ramdisk/ramdisk.cpio.gz
202 23:50:45.733302 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 23:50:45.733435 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 23:50:45.733536 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 23:50:45.733651 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/kernel/Image']
206 23:50:58.849182 Returned 0 in 13 seconds
207 23:50:58.949859 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/kernel/image.itb
208 23:50:59.824374 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:50:59.824751 output: Created: Thu May 30 00:50:59 2024
210 23:50:59.824861 output: Image 0 (kernel-1)
211 23:50:59.824963 output: Description:
212 23:50:59.825079 output: Created: Thu May 30 00:50:59 2024
213 23:50:59.825163 output: Type: Kernel Image
214 23:50:59.825246 output: Compression: lzma compressed
215 23:50:59.825326 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
216 23:50:59.825426 output: Architecture: AArch64
217 23:50:59.825527 output: OS: Linux
218 23:50:59.825629 output: Load Address: 0x00000000
219 23:50:59.825728 output: Entry Point: 0x00000000
220 23:50:59.825825 output: Hash algo: crc32
221 23:50:59.825925 output: Hash value: 907bf91d
222 23:50:59.826021 output: Image 1 (fdt-1)
223 23:50:59.826114 output: Description: mt8192-asurada-spherion-r0
224 23:50:59.826210 output: Created: Thu May 30 00:50:59 2024
225 23:50:59.826303 output: Type: Flat Device Tree
226 23:50:59.826398 output: Compression: uncompressed
227 23:50:59.826490 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:50:59.826582 output: Architecture: AArch64
229 23:50:59.826681 output: Hash algo: crc32
230 23:50:59.826852 output: Hash value: 0f8e4d2e
231 23:50:59.826959 output: Image 2 (ramdisk-1)
232 23:50:59.827048 output: Description: unavailable
233 23:50:59.827132 output: Created: Thu May 30 00:50:59 2024
234 23:50:59.827217 output: Type: RAMDisk Image
235 23:50:59.827300 output: Compression: Unknown Compression
236 23:50:59.827383 output: Data Size: 61001105 Bytes = 59571.39 KiB = 58.18 MiB
237 23:50:59.827466 output: Architecture: AArch64
238 23:50:59.827548 output: OS: Linux
239 23:50:59.827631 output: Load Address: unavailable
240 23:50:59.827713 output: Entry Point: unavailable
241 23:50:59.827795 output: Hash algo: crc32
242 23:50:59.827877 output: Hash value: c2e2d98d
243 23:50:59.827959 output: Default Configuration: 'conf-1'
244 23:50:59.828041 output: Configuration 0 (conf-1)
245 23:50:59.828123 output: Description: mt8192-asurada-spherion-r0
246 23:50:59.828205 output: Kernel: kernel-1
247 23:50:59.828287 output: Init Ramdisk: ramdisk-1
248 23:50:59.828368 output: FDT: fdt-1
249 23:50:59.828450 output: Loadables: kernel-1
250 23:50:59.828532 output:
251 23:50:59.828767 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:50:59.828892 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:50:59.829072 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 23:50:59.829198 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 23:50:59.829305 No LXC device requested
256 23:50:59.829416 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:50:59.829531 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 23:50:59.829636 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:50:59.829732 Checking files for TFTP limit of 4294967296 bytes.
260 23:50:59.830416 end: 1 tftp-deploy (duration 00:00:25) [common]
261 23:50:59.830550 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:50:59.830674 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:50:59.830834 substitutions:
264 23:50:59.830926 - {DTB}: 14084325/tftp-deploy-7j3mdvgy/dtb/mt8192-asurada-spherion-r0.dtb
265 23:50:59.831017 - {INITRD}: 14084325/tftp-deploy-7j3mdvgy/ramdisk/ramdisk.cpio.gz
266 23:50:59.831104 - {KERNEL}: 14084325/tftp-deploy-7j3mdvgy/kernel/Image
267 23:50:59.831190 - {LAVA_MAC}: None
268 23:50:59.831274 - {PRESEED_CONFIG}: None
269 23:50:59.831358 - {PRESEED_LOCAL}: None
270 23:50:59.831441 - {RAMDISK}: 14084325/tftp-deploy-7j3mdvgy/ramdisk/ramdisk.cpio.gz
271 23:50:59.831524 - {ROOT_PART}: None
272 23:50:59.831607 - {ROOT}: None
273 23:50:59.831690 - {SERVER_IP}: 192.168.201.1
274 23:50:59.831773 - {TEE}: None
275 23:50:59.831855 Parsed boot commands:
276 23:50:59.831937 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:50:59.832152 Parsed boot commands: tftpboot 192.168.201.1 14084325/tftp-deploy-7j3mdvgy/kernel/image.itb 14084325/tftp-deploy-7j3mdvgy/kernel/cmdline
278 23:50:59.832268 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:50:59.832386 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:50:59.832511 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:50:59.832625 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:50:59.832721 Not connected, no need to disconnect.
283 23:50:59.832824 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:50:59.832933 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:50:59.833055 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 23:50:59.836749 Setting prompt string to ['lava-test: # ']
287 23:50:59.837151 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:50:59.837264 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:50:59.837375 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:50:59.837487 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:50:59.837705 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 23:51:04.972099 >> Command sent successfully.
293 23:51:04.974518 Returned 0 in 5 seconds
294 23:51:05.074913 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:51:05.075277 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:51:05.075395 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:51:05.075492 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:51:05.075572 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:51:05.075660 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:51:05.076212 [Enter `^Ec?' for help]
302 23:51:05.249648
303 23:51:05.249804
304 23:51:05.249899 F0: 102B 0000
305 23:51:05.249984
306 23:51:05.250068 F3: 1001 0000 [0200]
307 23:51:05.250148
308 23:51:05.252712 F3: 1001 0000
309 23:51:05.252807
310 23:51:05.252873 F7: 102D 0000
311 23:51:05.252935
312 23:51:05.253034 F1: 0000 0000
313 23:51:05.256409
314 23:51:05.256492 V0: 0000 0000 [0001]
315 23:51:05.256565
316 23:51:05.256626 00: 0007 8000
317 23:51:05.256690
318 23:51:05.259824 01: 0000 0000
319 23:51:05.259908
320 23:51:05.259974 BP: 0C00 0209 [0000]
321 23:51:05.260033
322 23:51:05.263578 G0: 1182 0000
323 23:51:05.263662
324 23:51:05.263728 EC: 0000 0021 [4000]
325 23:51:05.263788
326 23:51:05.267285 S7: 0000 0000 [0000]
327 23:51:05.267372
328 23:51:05.267438 CC: 0000 0000 [0001]
329 23:51:05.267503
330 23:51:05.271036 T0: 0000 0040 [010F]
331 23:51:05.271121
332 23:51:05.271187 Jump to BL
333 23:51:05.271248
334 23:51:05.296379
335 23:51:05.296518
336 23:51:05.304263 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:51:05.307785 ARM64: Exception handlers installed.
338 23:51:05.311356 ARM64: Testing exception
339 23:51:05.311441 ARM64: Done test exception
340 23:51:05.318290 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:51:05.329955 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:51:05.336810 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:51:05.346432 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:51:05.353504 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:51:05.363019 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:51:05.373386 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:51:05.380506 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:51:05.399032 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:51:05.401844 WDT: Last reset was cold boot
350 23:51:05.405375 SPI1(PAD0) initialized at 2873684 Hz
351 23:51:05.409348 SPI5(PAD0) initialized at 992727 Hz
352 23:51:05.412605 VBOOT: Loading verstage.
353 23:51:05.418444 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:51:05.422042 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:51:05.425651 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:51:05.428799 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:51:05.435587 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:51:05.442302 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:51:05.453652 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 23:51:05.453789
361 23:51:05.453856
362 23:51:05.463483 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:51:05.466849 ARM64: Exception handlers installed.
364 23:51:05.470101 ARM64: Testing exception
365 23:51:05.470191 ARM64: Done test exception
366 23:51:05.476918 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:51:05.479962 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:51:05.494525 Probing TPM: . done!
369 23:51:05.494714 TPM ready after 0 ms
370 23:51:05.501737 Connected to device vid:did:rid of 1ae0:0028:00
371 23:51:05.508498 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:51:05.566556 Initialized TPM device CR50 revision 0
373 23:51:05.578326 tlcl_send_startup: Startup return code is 0
374 23:51:05.578472 TPM: setup succeeded
375 23:51:05.590438 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:51:05.598269 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:51:05.612688 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:51:05.620504 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:51:05.623191 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:51:05.630098 in-header: 03 07 00 00 08 00 00 00
381 23:51:05.633759 in-data: aa e4 47 04 13 02 00 00
382 23:51:05.637615 Chrome EC: UHEPI supported
383 23:51:05.644771 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:51:05.648202 in-header: 03 ad 00 00 08 00 00 00
385 23:51:05.651918 in-data: 00 20 20 08 00 00 00 00
386 23:51:05.652030 Phase 1
387 23:51:05.655634 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:51:05.663378 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:51:05.666808 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:51:05.670291 Recovery requested (1009000e)
391 23:51:05.679085 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:51:05.684080 tlcl_extend: response is 0
393 23:51:05.694132 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:51:05.699213 tlcl_extend: response is 0
395 23:51:05.707027 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:51:05.725912 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 23:51:05.732444 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:51:05.732592
399 23:51:05.732685
400 23:51:05.743072 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:51:05.746538 ARM64: Exception handlers installed.
402 23:51:05.746654 ARM64: Testing exception
403 23:51:05.750537 ARM64: Done test exception
404 23:51:05.771208 pmic_efuse_setting: Set efuses in 11 msecs
405 23:51:05.775119 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:51:05.782164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:51:05.785212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:51:05.792081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:51:05.795859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:51:05.799064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:51:05.806184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:51:05.810625 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:51:05.814000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:51:05.817856 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:51:05.825709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:51:05.828718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:51:05.832227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:51:05.836064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:51:05.843813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:51:05.851491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:51:05.855180 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:51:05.862342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:51:05.865904 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:51:05.874273 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:51:05.877572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:51:05.884610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:51:05.888397 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:51:05.896758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:51:05.899320 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:51:05.906598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:51:05.911190 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:51:05.915359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:51:05.921998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:51:05.925768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:51:05.929743 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:51:05.937168 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:51:05.940647 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:51:05.944597 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:51:05.952022 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:51:05.955389 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:51:05.959191 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:51:05.967204 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:51:05.970742 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:51:05.974197 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:51:05.977912 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:51:05.985701 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:51:05.989149 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:51:05.992659 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:51:05.996706 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:51:06.000829 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:51:06.004401 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:51:06.011975 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:51:06.015254 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:51:06.019248 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:51:06.022856 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:51:06.026337 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:51:06.033568 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:51:06.041723 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:51:06.049129 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:51:06.056754 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:51:06.063808 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:51:06.068009 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:51:06.074851 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:51:06.078904 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:51:06.086567 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 23:51:06.089635 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:51:06.096862 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 23:51:06.099913 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:51:06.109239 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 23:51:06.119868 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 23:51:06.128050 [RTC]rtc_get_frequency_meter,154: input=19, output=883
472 23:51:06.137342 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 23:51:06.147407 [RTC]rtc_get_frequency_meter,154: input=16, output=812
474 23:51:06.157560 [RTC]rtc_get_frequency_meter,154: input=15, output=789
475 23:51:06.167378 [RTC]rtc_get_frequency_meter,154: input=16, output=813
476 23:51:06.170594 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 23:51:06.174856 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 23:51:06.178698 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:51:06.185695 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 23:51:06.190063 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:51:06.193752 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 23:51:06.197299 ADC[4]: Raw value=902066 ID=7
483 23:51:06.197663 ADC[3]: Raw value=213336 ID=1
484 23:51:06.200851 RAM Code: 0x71
485 23:51:06.205052 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:51:06.208794 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:51:06.215559 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:51:06.223766 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:51:06.227157 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:51:06.230543 in-header: 03 07 00 00 08 00 00 00
491 23:51:06.234648 in-data: aa e4 47 04 13 02 00 00
492 23:51:06.238829 Chrome EC: UHEPI supported
493 23:51:06.241924 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:51:06.245786 in-header: 03 ed 00 00 08 00 00 00
495 23:51:06.249671 in-data: 80 20 60 08 00 00 00 00
496 23:51:06.253487 MRC: failed to locate region type 0.
497 23:51:06.260645 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:51:06.264352 DRAM-K: Running full calibration
499 23:51:06.268122 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:51:06.271815 header.status = 0x0
501 23:51:06.275775 header.version = 0x6 (expected: 0x6)
502 23:51:06.279777 header.size = 0xd00 (expected: 0xd00)
503 23:51:06.280340 header.flags = 0x0
504 23:51:06.286736 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:51:06.304294 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 23:51:06.311026 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:51:06.314782 dram_init: ddr_geometry: 2
508 23:51:06.315144 [EMI] MDL number = 2
509 23:51:06.318674 [EMI] Get MDL freq = 0
510 23:51:06.319036 dram_init: ddr_type: 0
511 23:51:06.321896 is_discrete_lpddr4: 1
512 23:51:06.325892 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:51:06.326272
514 23:51:06.326584
515 23:51:06.326907 [Bian_co] ETT version 0.0.0.1
516 23:51:06.333215 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:51:06.333594
518 23:51:06.336933 dramc_set_vcore_voltage set vcore to 650000
519 23:51:06.337344 Read voltage for 800, 4
520 23:51:06.340657 Vio18 = 0
521 23:51:06.341056 Vcore = 650000
522 23:51:06.341346 Vdram = 0
523 23:51:06.341613 Vddq = 0
524 23:51:06.344342 Vmddr = 0
525 23:51:06.344730 dram_init: config_dvfs: 1
526 23:51:06.351553 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:51:06.354892 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:51:06.358172 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 23:51:06.364762 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 23:51:06.368174 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 23:51:06.372415 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 23:51:06.372782 MEM_TYPE=3, freq_sel=18
533 23:51:06.374992 sv_algorithm_assistance_LP4_1600
534 23:51:06.381585 ============ PULL DRAM RESETB DOWN ============
535 23:51:06.385128 ========== PULL DRAM RESETB DOWN end =========
536 23:51:06.388546 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:51:06.392482 ===================================
538 23:51:06.395548 LPDDR4 DRAM CONFIGURATION
539 23:51:06.398505 ===================================
540 23:51:06.398972 EX_ROW_EN[0] = 0x0
541 23:51:06.401842 EX_ROW_EN[1] = 0x0
542 23:51:06.405116 LP4Y_EN = 0x0
543 23:51:06.405491 WORK_FSP = 0x0
544 23:51:06.408339 WL = 0x2
545 23:51:06.408698 RL = 0x2
546 23:51:06.411728 BL = 0x2
547 23:51:06.412090 RPST = 0x0
548 23:51:06.415109 RD_PRE = 0x0
549 23:51:06.415515 WR_PRE = 0x1
550 23:51:06.418911 WR_PST = 0x0
551 23:51:06.419386 DBI_WR = 0x0
552 23:51:06.421955 DBI_RD = 0x0
553 23:51:06.422317 OTF = 0x1
554 23:51:06.426115 ===================================
555 23:51:06.428607 ===================================
556 23:51:06.432101 ANA top config
557 23:51:06.435442 ===================================
558 23:51:06.435807 DLL_ASYNC_EN = 0
559 23:51:06.438756 ALL_SLAVE_EN = 1
560 23:51:06.442456 NEW_RANK_MODE = 1
561 23:51:06.445437 DLL_IDLE_MODE = 1
562 23:51:06.445818 LP45_APHY_COMB_EN = 1
563 23:51:06.448894 TX_ODT_DIS = 1
564 23:51:06.453034 NEW_8X_MODE = 1
565 23:51:06.455284 ===================================
566 23:51:06.459460 ===================================
567 23:51:06.462016 data_rate = 1600
568 23:51:06.465466 CKR = 1
569 23:51:06.465832 DQ_P2S_RATIO = 8
570 23:51:06.468742 ===================================
571 23:51:06.471962 CA_P2S_RATIO = 8
572 23:51:06.475453 DQ_CA_OPEN = 0
573 23:51:06.479043 DQ_SEMI_OPEN = 0
574 23:51:06.482214 CA_SEMI_OPEN = 0
575 23:51:06.486092 CA_FULL_RATE = 0
576 23:51:06.486478 DQ_CKDIV4_EN = 1
577 23:51:06.489225 CA_CKDIV4_EN = 1
578 23:51:06.492243 CA_PREDIV_EN = 0
579 23:51:06.495263 PH8_DLY = 0
580 23:51:06.498928 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:51:06.502322 DQ_AAMCK_DIV = 4
582 23:51:06.502759 CA_AAMCK_DIV = 4
583 23:51:06.505628 CA_ADMCK_DIV = 4
584 23:51:06.508933 DQ_TRACK_CA_EN = 0
585 23:51:06.512090 CA_PICK = 800
586 23:51:06.515353 CA_MCKIO = 800
587 23:51:06.518736 MCKIO_SEMI = 0
588 23:51:06.518939 PLL_FREQ = 3068
589 23:51:06.522732 DQ_UI_PI_RATIO = 32
590 23:51:06.526015 CA_UI_PI_RATIO = 0
591 23:51:06.530197 ===================================
592 23:51:06.533502 ===================================
593 23:51:06.533615 memory_type:LPDDR4
594 23:51:06.537736 GP_NUM : 10
595 23:51:06.537853 SRAM_EN : 1
596 23:51:06.541177 MD32_EN : 0
597 23:51:06.545118 ===================================
598 23:51:06.545236 [ANA_INIT] >>>>>>>>>>>>>>
599 23:51:06.548605 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:51:06.552715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:51:06.556354 ===================================
602 23:51:06.559529 data_rate = 1600,PCW = 0X7600
603 23:51:06.563096 ===================================
604 23:51:06.566291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:51:06.570789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:51:06.577034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:51:06.580006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:51:06.583240 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:51:06.586990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:51:06.589803 [ANA_INIT] flow start
611 23:51:06.593363 [ANA_INIT] PLL >>>>>>>>
612 23:51:06.593447 [ANA_INIT] PLL <<<<<<<<
613 23:51:06.596896 [ANA_INIT] MIDPI >>>>>>>>
614 23:51:06.599732 [ANA_INIT] MIDPI <<<<<<<<
615 23:51:06.599814 [ANA_INIT] DLL >>>>>>>>
616 23:51:06.603470 [ANA_INIT] flow end
617 23:51:06.606566 ============ LP4 DIFF to SE enter ============
618 23:51:06.613426 ============ LP4 DIFF to SE exit ============
619 23:51:06.613510 [ANA_INIT] <<<<<<<<<<<<<
620 23:51:06.616691 [Flow] Enable top DCM control >>>>>
621 23:51:06.620141 [Flow] Enable top DCM control <<<<<
622 23:51:06.623448 Enable DLL master slave shuffle
623 23:51:06.630587 ==============================================================
624 23:51:06.630675 Gating Mode config
625 23:51:06.637102 ==============================================================
626 23:51:06.637227 Config description:
627 23:51:06.646747 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:51:06.653968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:51:06.660607 SELPH_MODE 0: By rank 1: By Phase
630 23:51:06.663835 ==============================================================
631 23:51:06.667367 GAT_TRACK_EN = 1
632 23:51:06.670855 RX_GATING_MODE = 2
633 23:51:06.673773 RX_GATING_TRACK_MODE = 2
634 23:51:06.677035 SELPH_MODE = 1
635 23:51:06.680494 PICG_EARLY_EN = 1
636 23:51:06.684090 VALID_LAT_VALUE = 1
637 23:51:06.687152 ==============================================================
638 23:51:06.690954 Enter into Gating configuration >>>>
639 23:51:06.694120 Exit from Gating configuration <<<<
640 23:51:06.697374 Enter into DVFS_PRE_config >>>>>
641 23:51:06.710644 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:51:06.714038 Exit from DVFS_PRE_config <<<<<
643 23:51:06.714123 Enter into PICG configuration >>>>
644 23:51:06.717229 Exit from PICG configuration <<<<
645 23:51:06.721475 [RX_INPUT] configuration >>>>>
646 23:51:06.724419 [RX_INPUT] configuration <<<<<
647 23:51:06.731003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:51:06.734088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:51:06.741065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:51:06.747664 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:51:06.754488 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:51:06.761340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:51:06.764324 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:51:06.767974 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:51:06.771096 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:51:06.774421 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:51:06.781802 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:51:06.785072 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:51:06.788430 ===================================
660 23:51:06.791143 LPDDR4 DRAM CONFIGURATION
661 23:51:06.794582 ===================================
662 23:51:06.794666 EX_ROW_EN[0] = 0x0
663 23:51:06.797728 EX_ROW_EN[1] = 0x0
664 23:51:06.797811 LP4Y_EN = 0x0
665 23:51:06.801220 WORK_FSP = 0x0
666 23:51:06.801324 WL = 0x2
667 23:51:06.804770 RL = 0x2
668 23:51:06.804898 BL = 0x2
669 23:51:06.808320 RPST = 0x0
670 23:51:06.808402 RD_PRE = 0x0
671 23:51:06.811539 WR_PRE = 0x1
672 23:51:06.811646 WR_PST = 0x0
673 23:51:06.815210 DBI_WR = 0x0
674 23:51:06.815324 DBI_RD = 0x0
675 23:51:06.818177 OTF = 0x1
676 23:51:06.821924 ===================================
677 23:51:06.824854 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:51:06.828760 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:51:06.836041 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:51:06.838634 ===================================
681 23:51:06.838722 LPDDR4 DRAM CONFIGURATION
682 23:51:06.841846 ===================================
683 23:51:06.845175 EX_ROW_EN[0] = 0x10
684 23:51:06.848196 EX_ROW_EN[1] = 0x0
685 23:51:06.848275 LP4Y_EN = 0x0
686 23:51:06.852043 WORK_FSP = 0x0
687 23:51:06.852125 WL = 0x2
688 23:51:06.855349 RL = 0x2
689 23:51:06.855429 BL = 0x2
690 23:51:06.858179 RPST = 0x0
691 23:51:06.858259 RD_PRE = 0x0
692 23:51:06.861708 WR_PRE = 0x1
693 23:51:06.861785 WR_PST = 0x0
694 23:51:06.865710 DBI_WR = 0x0
695 23:51:06.865794 DBI_RD = 0x0
696 23:51:06.868412 OTF = 0x1
697 23:51:06.871722 ===================================
698 23:51:06.878918 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:51:06.881721 nWR fixed to 40
700 23:51:06.881816 [ModeRegInit_LP4] CH0 RK0
701 23:51:06.884936 [ModeRegInit_LP4] CH0 RK1
702 23:51:06.888633 [ModeRegInit_LP4] CH1 RK0
703 23:51:06.888714 [ModeRegInit_LP4] CH1 RK1
704 23:51:06.891925 match AC timing 13
705 23:51:06.895254 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:51:06.898471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:51:06.905295 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:51:06.908390 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:51:06.916175 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:51:06.916268 [EMI DOE] emi_dcm 0
711 23:51:06.918753 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:51:06.922056 ==
713 23:51:06.922138 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:51:06.929797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:51:06.929880 ==
716 23:51:06.932129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:51:06.939333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:51:06.948478 [CA 0] Center 37 (7~68) winsize 62
719 23:51:06.951839 [CA 1] Center 37 (6~68) winsize 63
720 23:51:06.955152 [CA 2] Center 35 (5~66) winsize 62
721 23:51:06.958601 [CA 3] Center 34 (4~65) winsize 62
722 23:51:06.961537 [CA 4] Center 34 (3~65) winsize 63
723 23:51:06.964932 [CA 5] Center 33 (3~64) winsize 62
724 23:51:06.965061
725 23:51:06.968609 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:51:06.968691
727 23:51:06.972031 [CATrainingPosCal] consider 1 rank data
728 23:51:06.975132 u2DelayCellTimex100 = 270/100 ps
729 23:51:06.978567 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 23:51:06.982512 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 23:51:06.988670 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 23:51:06.991842 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 23:51:06.995833 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 23:51:06.999239 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:51:06.999322
736 23:51:07.002116 CA PerBit enable=1, Macro0, CA PI delay=33
737 23:51:07.002208
738 23:51:07.005344 [CBTSetCACLKResult] CA Dly = 33
739 23:51:07.005426 CS Dly: 5 (0~36)
740 23:51:07.005492 ==
741 23:51:07.008628 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:51:07.015509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:51:07.015595 ==
744 23:51:07.018794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:51:07.025590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:51:07.035230 [CA 0] Center 37 (6~68) winsize 63
747 23:51:07.038402 [CA 1] Center 37 (6~68) winsize 63
748 23:51:07.042700 [CA 2] Center 35 (5~66) winsize 62
749 23:51:07.044686 [CA 3] Center 35 (4~66) winsize 63
750 23:51:07.048832 [CA 4] Center 34 (4~65) winsize 62
751 23:51:07.051585 [CA 5] Center 33 (3~64) winsize 62
752 23:51:07.051667
753 23:51:07.054716 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:51:07.054799
755 23:51:07.058743 [CATrainingPosCal] consider 2 rank data
756 23:51:07.061667 u2DelayCellTimex100 = 270/100 ps
757 23:51:07.064888 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 23:51:07.068451 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
759 23:51:07.072266 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 23:51:07.078526 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 23:51:07.082058 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 23:51:07.084924 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:51:07.085043
764 23:51:07.088275 CA PerBit enable=1, Macro0, CA PI delay=33
765 23:51:07.088357
766 23:51:07.092079 [CBTSetCACLKResult] CA Dly = 33
767 23:51:07.092163 CS Dly: 5 (0~37)
768 23:51:07.092282
769 23:51:07.095611 ----->DramcWriteLeveling(PI) begin...
770 23:51:07.095694 ==
771 23:51:07.098558 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:51:07.105604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:51:07.105702 ==
774 23:51:07.105808 Write leveling (Byte 0): 31 => 31
775 23:51:07.109334 Write leveling (Byte 1): 30 => 30
776 23:51:07.113039 DramcWriteLeveling(PI) end<-----
777 23:51:07.113125
778 23:51:07.113230 ==
779 23:51:07.117257 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:51:07.121678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:51:07.121765 ==
782 23:51:07.124451 [Gating] SW mode calibration
783 23:51:07.130864 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:51:07.135759 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:51:07.141311 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:51:07.145410 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:51:07.148892 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 23:51:07.155313 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 23:51:07.158162 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:51:07.161864 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:51:07.168353 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:51:07.172073 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:51:07.175398 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:51:07.181901 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:51:07.185308 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:51:07.188297 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:51:07.192271 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:51:07.198460 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:51:07.202216 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:51:07.205400 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:51:07.211826 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:51:07.215339 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:51:07.218427 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 23:51:07.225357 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:51:07.229099 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:51:07.231862 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:51:07.239463 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:51:07.242629 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:51:07.245334 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:51:07.251791 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:51:07.255522 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:51:07.258814 0 9 12 | B1->B0 | 2727 3030 | 0 1 | (0 0) (1 1)
813 23:51:07.262215 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:51:07.269375 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:51:07.272674 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:51:07.275398 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:51:07.282327 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:51:07.285694 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
819 23:51:07.289444 0 10 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
820 23:51:07.295914 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
821 23:51:07.299014 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:51:07.302228 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:51:07.308929 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:51:07.312346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:51:07.315961 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:51:07.319073 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:51:07.326061 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
828 23:51:07.329546 0 11 12 | B1->B0 | 3434 3f3f | 0 0 | (0 0) (0 0)
829 23:51:07.333125 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 23:51:07.339454 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:51:07.342655 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:51:07.347948 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:51:07.352465 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:51:07.355856 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:51:07.359588 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:51:07.366214 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 23:51:07.369984 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:51:07.373197 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:51:07.376242 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:51:07.382986 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:51:07.386326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:51:07.389930 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:51:07.396330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:51:07.400185 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:51:07.404100 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:51:07.409934 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:51:07.413220 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:51:07.417031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:51:07.423050 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:51:07.426881 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 23:51:07.430183 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:51:07.434215 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 23:51:07.436461 Total UI for P1: 0, mck2ui 16
854 23:51:07.439952 best dqsien dly found for B0: ( 0, 14, 10)
855 23:51:07.444009 Total UI for P1: 0, mck2ui 16
856 23:51:07.447021 best dqsien dly found for B1: ( 0, 14, 10)
857 23:51:07.449891 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
858 23:51:07.453492 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 23:51:07.457256
860 23:51:07.461164 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
861 23:51:07.463417 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 23:51:07.467644 [Gating] SW calibration Done
863 23:51:07.467719 ==
864 23:51:07.470668 Dram Type= 6, Freq= 0, CH_0, rank 0
865 23:51:07.473303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 23:51:07.473390 ==
867 23:51:07.473476 RX Vref Scan: 0
868 23:51:07.473538
869 23:51:07.476562 RX Vref 0 -> 0, step: 1
870 23:51:07.476658
871 23:51:07.480060 RX Delay -130 -> 252, step: 16
872 23:51:07.483343 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
873 23:51:07.487003 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
874 23:51:07.493383 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
875 23:51:07.497269 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
876 23:51:07.500678 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
877 23:51:07.503604 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
878 23:51:07.506684 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
879 23:51:07.510258 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
880 23:51:07.517518 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
881 23:51:07.520293 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
882 23:51:07.524084 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
883 23:51:07.527017 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
884 23:51:07.531361 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
885 23:51:07.537664 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
886 23:51:07.541202 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
887 23:51:07.543755 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
888 23:51:07.543830 ==
889 23:51:07.547219 Dram Type= 6, Freq= 0, CH_0, rank 0
890 23:51:07.551820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 23:51:07.551934 ==
892 23:51:07.554007 DQS Delay:
893 23:51:07.554082 DQS0 = 0, DQS1 = 0
894 23:51:07.557436 DQM Delay:
895 23:51:07.557510 DQM0 = 82, DQM1 = 76
896 23:51:07.557571 DQ Delay:
897 23:51:07.560819 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
898 23:51:07.565208 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
899 23:51:07.567211 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
900 23:51:07.570897 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
901 23:51:07.570973
902 23:51:07.571035
903 23:51:07.575587 ==
904 23:51:07.575691 Dram Type= 6, Freq= 0, CH_0, rank 0
905 23:51:07.580843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 23:51:07.580949 ==
907 23:51:07.581071
908 23:51:07.581133
909 23:51:07.581223 TX Vref Scan disable
910 23:51:07.585089 == TX Byte 0 ==
911 23:51:07.588266 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
912 23:51:07.591489 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
913 23:51:07.595707 == TX Byte 1 ==
914 23:51:07.598880 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 23:51:07.601804 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 23:51:07.604980 ==
917 23:51:07.608087 Dram Type= 6, Freq= 0, CH_0, rank 0
918 23:51:07.611273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 23:51:07.611374 ==
920 23:51:07.624213 TX Vref=22, minBit 5, minWin=27, winSum=442
921 23:51:07.627484 TX Vref=24, minBit 5, minWin=27, winSum=445
922 23:51:07.630964 TX Vref=26, minBit 5, minWin=27, winSum=449
923 23:51:07.633799 TX Vref=28, minBit 12, minWin=27, winSum=454
924 23:51:07.637407 TX Vref=30, minBit 12, minWin=27, winSum=456
925 23:51:07.643919 TX Vref=32, minBit 12, minWin=27, winSum=455
926 23:51:07.647412 [TxChooseVref] Worse bit 12, Min win 27, Win sum 456, Final Vref 30
927 23:51:07.647496
928 23:51:07.650517 Final TX Range 1 Vref 30
929 23:51:07.650600
930 23:51:07.650665 ==
931 23:51:07.654237 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:51:07.657319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:51:07.657401 ==
934 23:51:07.661489
935 23:51:07.661570
936 23:51:07.661635 TX Vref Scan disable
937 23:51:07.664340 == TX Byte 0 ==
938 23:51:07.667594 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
939 23:51:07.670845 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
940 23:51:07.674273 == TX Byte 1 ==
941 23:51:07.678362 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 23:51:07.680940 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 23:51:07.681060
944 23:51:07.685168 [DATLAT]
945 23:51:07.685263 Freq=800, CH0 RK0
946 23:51:07.685340
947 23:51:07.688119 DATLAT Default: 0xa
948 23:51:07.688200 0, 0xFFFF, sum = 0
949 23:51:07.690822 1, 0xFFFF, sum = 0
950 23:51:07.690905 2, 0xFFFF, sum = 0
951 23:51:07.694574 3, 0xFFFF, sum = 0
952 23:51:07.694657 4, 0xFFFF, sum = 0
953 23:51:07.697768 5, 0xFFFF, sum = 0
954 23:51:07.697851 6, 0xFFFF, sum = 0
955 23:51:07.701176 7, 0xFFFF, sum = 0
956 23:51:07.701259 8, 0xFFFF, sum = 0
957 23:51:07.704337 9, 0x0, sum = 1
958 23:51:07.704409 10, 0x0, sum = 2
959 23:51:07.708185 11, 0x0, sum = 3
960 23:51:07.708267 12, 0x0, sum = 4
961 23:51:07.711805 best_step = 10
962 23:51:07.711886
963 23:51:07.711950 ==
964 23:51:07.714703 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:51:07.718061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 23:51:07.718135 ==
967 23:51:07.721861 RX Vref Scan: 1
968 23:51:07.721930
969 23:51:07.721989 Set Vref Range= 32 -> 127
970 23:51:07.722049
971 23:51:07.724246 RX Vref 32 -> 127, step: 1
972 23:51:07.724312
973 23:51:07.728040 RX Delay -111 -> 252, step: 8
974 23:51:07.728109
975 23:51:07.731252 Set Vref, RX VrefLevel [Byte0]: 32
976 23:51:07.734875 [Byte1]: 32
977 23:51:07.734957
978 23:51:07.738096 Set Vref, RX VrefLevel [Byte0]: 33
979 23:51:07.742099 [Byte1]: 33
980 23:51:07.745286
981 23:51:07.745363 Set Vref, RX VrefLevel [Byte0]: 34
982 23:51:07.748417 [Byte1]: 34
983 23:51:07.752424
984 23:51:07.752496 Set Vref, RX VrefLevel [Byte0]: 35
985 23:51:07.755963 [Byte1]: 35
986 23:51:07.759835
987 23:51:07.759911 Set Vref, RX VrefLevel [Byte0]: 36
988 23:51:07.763398 [Byte1]: 36
989 23:51:07.767469
990 23:51:07.767540 Set Vref, RX VrefLevel [Byte0]: 37
991 23:51:07.771367 [Byte1]: 37
992 23:51:07.776863
993 23:51:07.776945 Set Vref, RX VrefLevel [Byte0]: 38
994 23:51:07.780465 [Byte1]: 38
995 23:51:07.783942
996 23:51:07.784024 Set Vref, RX VrefLevel [Byte0]: 39
997 23:51:07.786960 [Byte1]: 39
998 23:51:07.790710
999 23:51:07.790792 Set Vref, RX VrefLevel [Byte0]: 40
1000 23:51:07.794183 [Byte1]: 40
1001 23:51:07.798502
1002 23:51:07.798585 Set Vref, RX VrefLevel [Byte0]: 41
1003 23:51:07.802598 [Byte1]: 41
1004 23:51:07.805815
1005 23:51:07.805896 Set Vref, RX VrefLevel [Byte0]: 42
1006 23:51:07.809539 [Byte1]: 42
1007 23:51:07.813278
1008 23:51:07.813359 Set Vref, RX VrefLevel [Byte0]: 43
1009 23:51:07.816540 [Byte1]: 43
1010 23:51:07.820983
1011 23:51:07.821065 Set Vref, RX VrefLevel [Byte0]: 44
1012 23:51:07.824313 [Byte1]: 44
1013 23:51:07.828916
1014 23:51:07.829003 Set Vref, RX VrefLevel [Byte0]: 45
1015 23:51:07.831965 [Byte1]: 45
1016 23:51:07.836562
1017 23:51:07.836643 Set Vref, RX VrefLevel [Byte0]: 46
1018 23:51:07.840267 [Byte1]: 46
1019 23:51:07.843758
1020 23:51:07.843848 Set Vref, RX VrefLevel [Byte0]: 47
1021 23:51:07.847197 [Byte1]: 47
1022 23:51:07.851914
1023 23:51:07.851995 Set Vref, RX VrefLevel [Byte0]: 48
1024 23:51:07.854744 [Byte1]: 48
1025 23:51:07.859431
1026 23:51:07.859510 Set Vref, RX VrefLevel [Byte0]: 49
1027 23:51:07.862717 [Byte1]: 49
1028 23:51:07.866824
1029 23:51:07.866904 Set Vref, RX VrefLevel [Byte0]: 50
1030 23:51:07.870291 [Byte1]: 50
1031 23:51:07.874615
1032 23:51:07.874695 Set Vref, RX VrefLevel [Byte0]: 51
1033 23:51:07.877893 [Byte1]: 51
1034 23:51:07.882984
1035 23:51:07.883064 Set Vref, RX VrefLevel [Byte0]: 52
1036 23:51:07.886020 [Byte1]: 52
1037 23:51:07.889736
1038 23:51:07.889816 Set Vref, RX VrefLevel [Byte0]: 53
1039 23:51:07.892993 [Byte1]: 53
1040 23:51:07.897478
1041 23:51:07.897558 Set Vref, RX VrefLevel [Byte0]: 54
1042 23:51:07.901163 [Byte1]: 54
1043 23:51:07.905151
1044 23:51:07.905231 Set Vref, RX VrefLevel [Byte0]: 55
1045 23:51:07.908506 [Byte1]: 55
1046 23:51:07.913160
1047 23:51:07.913239 Set Vref, RX VrefLevel [Byte0]: 56
1048 23:51:07.916142 [Byte1]: 56
1049 23:51:07.920684
1050 23:51:07.920763 Set Vref, RX VrefLevel [Byte0]: 57
1051 23:51:07.923903 [Byte1]: 57
1052 23:51:07.928298
1053 23:51:07.928378 Set Vref, RX VrefLevel [Byte0]: 58
1054 23:51:07.931456 [Byte1]: 58
1055 23:51:07.935636
1056 23:51:07.935716 Set Vref, RX VrefLevel [Byte0]: 59
1057 23:51:07.938947 [Byte1]: 59
1058 23:51:07.943521
1059 23:51:07.943601 Set Vref, RX VrefLevel [Byte0]: 60
1060 23:51:07.946409 [Byte1]: 60
1061 23:51:07.950936
1062 23:51:07.951016 Set Vref, RX VrefLevel [Byte0]: 61
1063 23:51:07.954588 [Byte1]: 61
1064 23:51:07.959427
1065 23:51:07.959506 Set Vref, RX VrefLevel [Byte0]: 62
1066 23:51:07.962295 [Byte1]: 62
1067 23:51:07.966069
1068 23:51:07.966148 Set Vref, RX VrefLevel [Byte0]: 63
1069 23:51:07.969746 [Byte1]: 63
1070 23:51:07.974352
1071 23:51:07.974432 Set Vref, RX VrefLevel [Byte0]: 64
1072 23:51:07.977443 [Byte1]: 64
1073 23:51:07.981823
1074 23:51:07.981903 Set Vref, RX VrefLevel [Byte0]: 65
1075 23:51:07.985299 [Byte1]: 65
1076 23:51:07.989514
1077 23:51:07.989594 Set Vref, RX VrefLevel [Byte0]: 66
1078 23:51:07.992929 [Byte1]: 66
1079 23:51:07.996697
1080 23:51:07.996776 Set Vref, RX VrefLevel [Byte0]: 67
1081 23:51:08.000925 [Byte1]: 67
1082 23:51:08.004786
1083 23:51:08.004866 Set Vref, RX VrefLevel [Byte0]: 68
1084 23:51:08.007663 [Byte1]: 68
1085 23:51:08.012050
1086 23:51:08.012131 Set Vref, RX VrefLevel [Byte0]: 69
1087 23:51:08.015914 [Byte1]: 69
1088 23:51:08.019688
1089 23:51:08.019768 Set Vref, RX VrefLevel [Byte0]: 70
1090 23:51:08.023564 [Byte1]: 70
1091 23:51:08.027522
1092 23:51:08.027601 Set Vref, RX VrefLevel [Byte0]: 71
1093 23:51:08.030567 [Byte1]: 71
1094 23:51:08.034817
1095 23:51:08.034897 Set Vref, RX VrefLevel [Byte0]: 72
1096 23:51:08.038692 [Byte1]: 72
1097 23:51:08.042415
1098 23:51:08.042544 Set Vref, RX VrefLevel [Byte0]: 73
1099 23:51:08.046471 [Byte1]: 73
1100 23:51:08.050836
1101 23:51:08.050916 Set Vref, RX VrefLevel [Byte0]: 74
1102 23:51:08.054025 [Byte1]: 74
1103 23:51:08.058065
1104 23:51:08.058147 Set Vref, RX VrefLevel [Byte0]: 75
1105 23:51:08.061306 [Byte1]: 75
1106 23:51:08.065888
1107 23:51:08.065962 Set Vref, RX VrefLevel [Byte0]: 76
1108 23:51:08.068877 [Byte1]: 76
1109 23:51:08.073639
1110 23:51:08.073718 Final RX Vref Byte 0 = 60 to rank0
1111 23:51:08.076955 Final RX Vref Byte 1 = 58 to rank0
1112 23:51:08.080470 Final RX Vref Byte 0 = 60 to rank1
1113 23:51:08.083887 Final RX Vref Byte 1 = 58 to rank1==
1114 23:51:08.086497 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 23:51:08.090459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 23:51:08.093401 ==
1117 23:51:08.093481 DQS Delay:
1118 23:51:08.093544 DQS0 = 0, DQS1 = 0
1119 23:51:08.097580 DQM Delay:
1120 23:51:08.097660 DQM0 = 88, DQM1 = 79
1121 23:51:08.099927 DQ Delay:
1122 23:51:08.103644 DQ0 =92, DQ1 =92, DQ2 =84, DQ3 =84
1123 23:51:08.103723 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1124 23:51:08.106974 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1125 23:51:08.110369 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1126 23:51:08.110449
1127 23:51:08.114116
1128 23:51:08.120140 [DQSOSCAuto] RK0, (LSB)MR18= 0x230b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
1129 23:51:08.123662 CH0 RK0: MR19=606, MR18=230B
1130 23:51:08.130673 CH0_RK0: MR19=0x606, MR18=0x230B, DQSOSC=401, MR23=63, INC=91, DEC=61
1131 23:51:08.130754
1132 23:51:08.133844 ----->DramcWriteLeveling(PI) begin...
1133 23:51:08.133926 ==
1134 23:51:08.136911 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 23:51:08.141527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 23:51:08.141608 ==
1137 23:51:08.143851 Write leveling (Byte 0): 29 => 29
1138 23:51:08.147197 Write leveling (Byte 1): 29 => 29
1139 23:51:08.151642 DramcWriteLeveling(PI) end<-----
1140 23:51:08.151722
1141 23:51:08.151796 ==
1142 23:51:08.154049 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:51:08.157667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:51:08.157749 ==
1145 23:51:08.160881 [Gating] SW mode calibration
1146 23:51:08.167759 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 23:51:08.170800 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 23:51:08.177906 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1149 23:51:08.180593 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 23:51:08.224635 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 23:51:08.225747 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 23:51:08.226441 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 23:51:08.226523 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:51:08.226770 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:51:08.227372 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:51:08.227638 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:51:08.228245 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:51:08.228326 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:51:08.228870 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:51:08.238072 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:51:08.238579 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:51:08.242384 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:51:08.242506 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:51:08.248171 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:51:08.252602 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1166 23:51:08.255107 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1167 23:51:08.262159 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:51:08.264520 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:51:08.268014 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:51:08.274966 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:51:08.278403 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:51:08.281906 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:51:08.285187 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:51:08.291962 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1175 23:51:08.295137 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1176 23:51:08.298486 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 23:51:08.305046 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:51:08.308317 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:51:08.312405 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:51:08.318888 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:51:08.322195 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1182 23:51:08.325158 0 10 8 | B1->B0 | 3232 2c2c | 1 1 | (1 1) (1 0)
1183 23:51:08.331591 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1184 23:51:08.335520 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:51:08.338601 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:51:08.345995 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:51:08.349731 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:51:08.351916 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:51:08.355781 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1190 23:51:08.363260 0 11 8 | B1->B0 | 2828 4141 | 0 0 | (0 0) (0 0)
1191 23:51:08.366987 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1192 23:51:08.370237 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:51:08.373422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:51:08.381099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:51:08.385118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:51:08.388414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:51:08.391395 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1198 23:51:08.395273 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1199 23:51:08.401839 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:51:08.404532 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:51:08.408909 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:51:08.415216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:51:08.418450 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:51:08.421910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:51:08.428243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:51:08.431815 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:51:08.435433 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:51:08.442580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:51:08.445366 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:51:08.448576 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:51:08.454918 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:51:08.459242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:51:08.461744 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 23:51:08.465490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1215 23:51:08.468877 Total UI for P1: 0, mck2ui 16
1216 23:51:08.471878 best dqsien dly found for B0: ( 0, 14, 4)
1217 23:51:08.478491 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 23:51:08.481656 Total UI for P1: 0, mck2ui 16
1219 23:51:08.485366 best dqsien dly found for B1: ( 0, 14, 8)
1220 23:51:08.488316 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 23:51:08.491789 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 23:51:08.492055
1223 23:51:08.495633 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 23:51:08.499519 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 23:51:08.502399 [Gating] SW calibration Done
1226 23:51:08.502632 ==
1227 23:51:08.504938 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 23:51:08.508263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 23:51:08.508517 ==
1230 23:51:08.511673 RX Vref Scan: 0
1231 23:51:08.511914
1232 23:51:08.512101 RX Vref 0 -> 0, step: 1
1233 23:51:08.512273
1234 23:51:08.515262 RX Delay -130 -> 252, step: 16
1235 23:51:08.518927 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 23:51:08.525002 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1237 23:51:08.528649 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 23:51:08.532206 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1239 23:51:08.535476 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1240 23:51:08.538687 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1241 23:51:08.545838 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 23:51:08.549432 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1243 23:51:08.552437 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1244 23:51:08.555938 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1245 23:51:08.559682 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1246 23:51:08.566618 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1247 23:51:08.568861 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1248 23:51:08.572794 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1249 23:51:08.575793 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1250 23:51:08.579232 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1251 23:51:08.579529 ==
1252 23:51:08.582574 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 23:51:08.589070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 23:51:08.589377 ==
1255 23:51:08.589654 DQS Delay:
1256 23:51:08.592220 DQS0 = 0, DQS1 = 0
1257 23:51:08.592596 DQM Delay:
1258 23:51:08.592938 DQM0 = 86, DQM1 = 77
1259 23:51:08.595822 DQ Delay:
1260 23:51:08.600043 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1261 23:51:08.602417 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1262 23:51:08.606219 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1263 23:51:08.609539 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1264 23:51:08.609906
1265 23:51:08.610221
1266 23:51:08.610536 ==
1267 23:51:08.612868 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 23:51:08.615948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 23:51:08.616238 ==
1270 23:51:08.616537
1271 23:51:08.616852
1272 23:51:08.619383 TX Vref Scan disable
1273 23:51:08.619693 == TX Byte 0 ==
1274 23:51:08.626711 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1275 23:51:08.629687 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1276 23:51:08.629997 == TX Byte 1 ==
1277 23:51:08.636379 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1278 23:51:08.639387 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1279 23:51:08.639679 ==
1280 23:51:08.642862 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 23:51:08.646076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 23:51:08.646369 ==
1283 23:51:08.660256 TX Vref=22, minBit 1, minWin=27, winSum=441
1284 23:51:08.662969 TX Vref=24, minBit 3, minWin=27, winSum=448
1285 23:51:08.666497 TX Vref=26, minBit 3, minWin=27, winSum=451
1286 23:51:08.670074 TX Vref=28, minBit 0, minWin=28, winSum=452
1287 23:51:08.673425 TX Vref=30, minBit 9, minWin=27, winSum=452
1288 23:51:08.676686 TX Vref=32, minBit 0, minWin=28, winSum=453
1289 23:51:08.683955 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1290 23:51:08.684251
1291 23:51:08.687207 Final TX Range 1 Vref 32
1292 23:51:08.687501
1293 23:51:08.687728 ==
1294 23:51:08.689665 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 23:51:08.693308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 23:51:08.693602 ==
1297 23:51:08.693829
1298 23:51:08.694039
1299 23:51:08.697564 TX Vref Scan disable
1300 23:51:08.700365 == TX Byte 0 ==
1301 23:51:08.704388 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1302 23:51:08.707565 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1303 23:51:08.710033 == TX Byte 1 ==
1304 23:51:08.713380 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1305 23:51:08.716760 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1306 23:51:08.717007
1307 23:51:08.720239 [DATLAT]
1308 23:51:08.720456 Freq=800, CH0 RK1
1309 23:51:08.720630
1310 23:51:08.723699 DATLAT Default: 0xa
1311 23:51:08.723926 0, 0xFFFF, sum = 0
1312 23:51:08.727028 1, 0xFFFF, sum = 0
1313 23:51:08.727208 2, 0xFFFF, sum = 0
1314 23:51:08.730005 3, 0xFFFF, sum = 0
1315 23:51:08.730176 4, 0xFFFF, sum = 0
1316 23:51:08.733902 5, 0xFFFF, sum = 0
1317 23:51:08.734052 6, 0xFFFF, sum = 0
1318 23:51:08.736539 7, 0xFFFF, sum = 0
1319 23:51:08.736688 8, 0xFFFF, sum = 0
1320 23:51:08.740614 9, 0x0, sum = 1
1321 23:51:08.740765 10, 0x0, sum = 2
1322 23:51:08.743884 11, 0x0, sum = 3
1323 23:51:08.743965 12, 0x0, sum = 4
1324 23:51:08.747342 best_step = 10
1325 23:51:08.747421
1326 23:51:08.747484 ==
1327 23:51:08.749975 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 23:51:08.753534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 23:51:08.753618 ==
1330 23:51:08.756878 RX Vref Scan: 0
1331 23:51:08.756958
1332 23:51:08.757060 RX Vref 0 -> 0, step: 1
1333 23:51:08.757120
1334 23:51:08.761234 RX Delay -95 -> 252, step: 8
1335 23:51:08.766981 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1336 23:51:08.769789 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1337 23:51:08.773837 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1338 23:51:08.776763 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1339 23:51:08.780328 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1340 23:51:08.783370 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1341 23:51:08.790101 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1342 23:51:08.793167 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1343 23:51:08.796842 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1344 23:51:08.800379 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 23:51:08.803710 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1346 23:51:08.809870 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1347 23:51:08.814365 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1348 23:51:08.817127 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1349 23:51:08.820029 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1350 23:51:08.823648 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1351 23:51:08.827220 ==
1352 23:51:08.830424 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 23:51:08.833652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 23:51:08.833733 ==
1355 23:51:08.833795 DQS Delay:
1356 23:51:08.837089 DQS0 = 0, DQS1 = 0
1357 23:51:08.837172 DQM Delay:
1358 23:51:08.841167 DQM0 = 87, DQM1 = 78
1359 23:51:08.841578 DQ Delay:
1360 23:51:08.844107 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1361 23:51:08.847277 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1362 23:51:08.851159 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1363 23:51:08.854207 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1364 23:51:08.854633
1365 23:51:08.854978
1366 23:51:08.860710 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1367 23:51:08.864117 CH0 RK1: MR19=606, MR18=2D18
1368 23:51:08.871054 CH0_RK1: MR19=0x606, MR18=0x2D18, DQSOSC=398, MR23=63, INC=93, DEC=62
1369 23:51:08.874149 [RxdqsGatingPostProcess] freq 800
1370 23:51:08.877336 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 23:51:08.880965 Pre-setting of DQS Precalculation
1372 23:51:08.887974 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 23:51:08.888386 ==
1374 23:51:08.891129 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 23:51:08.894515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 23:51:08.894936 ==
1377 23:51:08.900624 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 23:51:08.904447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 23:51:08.914924 [CA 0] Center 36 (6~66) winsize 61
1380 23:51:08.917969 [CA 1] Center 36 (6~66) winsize 61
1381 23:51:08.921655 [CA 2] Center 34 (4~65) winsize 62
1382 23:51:08.924318 [CA 3] Center 33 (3~64) winsize 62
1383 23:51:08.927511 [CA 4] Center 34 (4~65) winsize 62
1384 23:51:08.931421 [CA 5] Center 33 (3~64) winsize 62
1385 23:51:08.931511
1386 23:51:08.934728 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1387 23:51:08.934807
1388 23:51:08.938007 [CATrainingPosCal] consider 1 rank data
1389 23:51:08.941361 u2DelayCellTimex100 = 270/100 ps
1390 23:51:08.944725 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1391 23:51:08.948037 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 23:51:08.951305 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 23:51:08.958312 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 23:51:08.961804 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 23:51:08.965115 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 23:51:08.965200
1397 23:51:08.967958 CA PerBit enable=1, Macro0, CA PI delay=33
1398 23:51:08.968044
1399 23:51:08.971419 [CBTSetCACLKResult] CA Dly = 33
1400 23:51:08.971510 CS Dly: 5 (0~36)
1401 23:51:08.971583 ==
1402 23:51:08.974792 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 23:51:08.981588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:51:08.981669 ==
1405 23:51:08.985383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 23:51:08.991492 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 23:51:09.000427 [CA 0] Center 36 (6~66) winsize 61
1408 23:51:09.003683 [CA 1] Center 36 (6~66) winsize 61
1409 23:51:09.007274 [CA 2] Center 34 (4~65) winsize 62
1410 23:51:09.011309 [CA 3] Center 34 (3~65) winsize 63
1411 23:51:09.014039 [CA 4] Center 34 (4~65) winsize 62
1412 23:51:09.017371 [CA 5] Center 33 (3~63) winsize 61
1413 23:51:09.017452
1414 23:51:09.021262 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1415 23:51:09.021343
1416 23:51:09.024849 [CATrainingPosCal] consider 2 rank data
1417 23:51:09.028232 u2DelayCellTimex100 = 270/100 ps
1418 23:51:09.032127 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1419 23:51:09.035825 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 23:51:09.039950 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1421 23:51:09.043940 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 23:51:09.047220 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 23:51:09.051102 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1424 23:51:09.051182
1425 23:51:09.054493 CA PerBit enable=1, Macro0, CA PI delay=33
1426 23:51:09.054574
1427 23:51:09.058935 [CBTSetCACLKResult] CA Dly = 33
1428 23:51:09.059015 CS Dly: 5 (0~37)
1429 23:51:09.059078
1430 23:51:09.061715 ----->DramcWriteLeveling(PI) begin...
1431 23:51:09.061798 ==
1432 23:51:09.065208 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 23:51:09.067862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 23:51:09.072220 ==
1435 23:51:09.072300 Write leveling (Byte 0): 27 => 27
1436 23:51:09.074504 Write leveling (Byte 1): 28 => 28
1437 23:51:09.077757 DramcWriteLeveling(PI) end<-----
1438 23:51:09.077837
1439 23:51:09.077899 ==
1440 23:51:09.081344 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 23:51:09.087864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 23:51:09.087945 ==
1443 23:51:09.091408 [Gating] SW mode calibration
1444 23:51:09.097809 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 23:51:09.101117 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 23:51:09.104537 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 23:51:09.111590 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 23:51:09.114968 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1449 23:51:09.118174 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 23:51:09.124567 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:51:09.128104 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1452 23:51:09.131241 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:51:09.138180 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:51:09.141368 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:51:09.144357 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:51:09.151438 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1457 23:51:09.154277 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1458 23:51:09.158079 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1459 23:51:09.165526 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:51:09.168029 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1461 23:51:09.171299 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:51:09.178070 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:51:09.181536 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1464 23:51:09.184835 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:51:09.191400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:51:09.194607 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:51:09.198803 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:51:09.202344 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:51:09.208300 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:51:09.211208 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:51:09.215009 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:51:09.221690 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1473 23:51:09.224786 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 23:51:09.227999 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 23:51:09.234806 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:51:09.238900 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:51:09.241857 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:51:09.248288 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1479 23:51:09.251703 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1480 23:51:09.255461 0 10 8 | B1->B0 | 2d2d 2f2f | 1 1 | (1 0) (1 1)
1481 23:51:09.258616 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1482 23:51:09.265229 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1483 23:51:09.268429 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:51:09.271951 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:51:09.278477 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:51:09.282179 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:51:09.285319 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:51:09.292073 0 11 8 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
1489 23:51:09.295092 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 23:51:09.299384 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:51:09.305237 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:51:09.308712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:51:09.312684 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:51:09.316726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:51:09.322135 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:51:09.325781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1497 23:51:09.328807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 23:51:09.335786 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:51:09.339981 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:51:09.342233 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:51:09.349304 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:51:09.353303 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:51:09.355567 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:51:09.362348 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:51:09.365700 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:51:09.369058 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:51:09.372434 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:51:09.379361 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:51:09.383459 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:51:09.386099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:51:09.392900 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1512 23:51:09.395794 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 23:51:09.399632 Total UI for P1: 0, mck2ui 16
1514 23:51:09.402803 best dqsien dly found for B0: ( 0, 14, 6)
1515 23:51:09.405994 Total UI for P1: 0, mck2ui 16
1516 23:51:09.409324 best dqsien dly found for B1: ( 0, 14, 4)
1517 23:51:09.412912 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1518 23:51:09.416359 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1519 23:51:09.416441
1520 23:51:09.419495 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1521 23:51:09.422986 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 23:51:09.426161 [Gating] SW calibration Done
1523 23:51:09.426244 ==
1524 23:51:09.430184 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 23:51:09.432627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 23:51:09.432737 ==
1527 23:51:09.436371 RX Vref Scan: 0
1528 23:51:09.436454
1529 23:51:09.439572 RX Vref 0 -> 0, step: 1
1530 23:51:09.439653
1531 23:51:09.439717 RX Delay -130 -> 252, step: 16
1532 23:51:09.446018 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1533 23:51:09.449696 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1534 23:51:09.453308 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1535 23:51:09.456781 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1536 23:51:09.459668 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1537 23:51:09.466769 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1538 23:51:09.469719 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1539 23:51:09.472751 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1540 23:51:09.476967 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1541 23:51:09.479653 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1542 23:51:09.486687 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1543 23:51:09.489576 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1544 23:51:09.493544 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1545 23:51:09.497031 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1546 23:51:09.500312 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1547 23:51:09.506451 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1548 23:51:09.506585 ==
1549 23:51:09.509776 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 23:51:09.513184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 23:51:09.513304 ==
1552 23:51:09.513403 DQS Delay:
1553 23:51:09.516508 DQS0 = 0, DQS1 = 0
1554 23:51:09.516629 DQM Delay:
1555 23:51:09.519755 DQM0 = 83, DQM1 = 76
1556 23:51:09.519877 DQ Delay:
1557 23:51:09.523174 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1558 23:51:09.527114 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1559 23:51:09.530406 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1560 23:51:09.533171 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 23:51:09.533253
1562 23:51:09.533317
1563 23:51:09.533376 ==
1564 23:51:09.536786 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 23:51:09.540006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 23:51:09.540091 ==
1567 23:51:09.540155
1568 23:51:09.540214
1569 23:51:09.543626 TX Vref Scan disable
1570 23:51:09.546921 == TX Byte 0 ==
1571 23:51:09.549935 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1572 23:51:09.552971 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1573 23:51:09.557243 == TX Byte 1 ==
1574 23:51:09.560427 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1575 23:51:09.563766 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1576 23:51:09.563851 ==
1577 23:51:09.567752 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 23:51:09.569809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 23:51:09.573826 ==
1580 23:51:09.584625 TX Vref=22, minBit 0, minWin=27, winSum=438
1581 23:51:09.588494 TX Vref=24, minBit 4, minWin=27, winSum=441
1582 23:51:09.592169 TX Vref=26, minBit 11, minWin=27, winSum=449
1583 23:51:09.594616 TX Vref=28, minBit 11, minWin=27, winSum=451
1584 23:51:09.597975 TX Vref=30, minBit 11, minWin=27, winSum=456
1585 23:51:09.605098 TX Vref=32, minBit 1, minWin=28, winSum=457
1586 23:51:09.608917 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 32
1587 23:51:09.609064
1588 23:51:09.612137 Final TX Range 1 Vref 32
1589 23:51:09.612220
1590 23:51:09.612284 ==
1591 23:51:09.615507 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 23:51:09.618940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 23:51:09.619026 ==
1594 23:51:09.619093
1595 23:51:09.619151
1596 23:51:09.622108 TX Vref Scan disable
1597 23:51:09.625740 == TX Byte 0 ==
1598 23:51:09.628411 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1599 23:51:09.632077 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1600 23:51:09.635662 == TX Byte 1 ==
1601 23:51:09.639016 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 23:51:09.642973 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 23:51:09.643055
1604 23:51:09.645765 [DATLAT]
1605 23:51:09.645846 Freq=800, CH1 RK0
1606 23:51:09.645911
1607 23:51:09.648814 DATLAT Default: 0xa
1608 23:51:09.648896 0, 0xFFFF, sum = 0
1609 23:51:09.652374 1, 0xFFFF, sum = 0
1610 23:51:09.652456 2, 0xFFFF, sum = 0
1611 23:51:09.655776 3, 0xFFFF, sum = 0
1612 23:51:09.655859 4, 0xFFFF, sum = 0
1613 23:51:09.659011 5, 0xFFFF, sum = 0
1614 23:51:09.659093 6, 0xFFFF, sum = 0
1615 23:51:09.662715 7, 0xFFFF, sum = 0
1616 23:51:09.662799 8, 0xFFFF, sum = 0
1617 23:51:09.665501 9, 0x0, sum = 1
1618 23:51:09.665584 10, 0x0, sum = 2
1619 23:51:09.669127 11, 0x0, sum = 3
1620 23:51:09.669208 12, 0x0, sum = 4
1621 23:51:09.672573 best_step = 10
1622 23:51:09.672656
1623 23:51:09.672719 ==
1624 23:51:09.675967 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 23:51:09.678874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 23:51:09.678992 ==
1627 23:51:09.679070 RX Vref Scan: 1
1628 23:51:09.679131
1629 23:51:09.682333 Set Vref Range= 32 -> 127
1630 23:51:09.682414
1631 23:51:09.686081 RX Vref 32 -> 127, step: 1
1632 23:51:09.686164
1633 23:51:09.689092 RX Delay -95 -> 252, step: 8
1634 23:51:09.689174
1635 23:51:09.692463 Set Vref, RX VrefLevel [Byte0]: 32
1636 23:51:09.695800 [Byte1]: 32
1637 23:51:09.695885
1638 23:51:09.699518 Set Vref, RX VrefLevel [Byte0]: 33
1639 23:51:09.702392 [Byte1]: 33
1640 23:51:09.702474
1641 23:51:09.706265 Set Vref, RX VrefLevel [Byte0]: 34
1642 23:51:09.708961 [Byte1]: 34
1643 23:51:09.712838
1644 23:51:09.712919 Set Vref, RX VrefLevel [Byte0]: 35
1645 23:51:09.715841 [Byte1]: 35
1646 23:51:09.720289
1647 23:51:09.720375 Set Vref, RX VrefLevel [Byte0]: 36
1648 23:51:09.724134 [Byte1]: 36
1649 23:51:09.728481
1650 23:51:09.728563 Set Vref, RX VrefLevel [Byte0]: 37
1651 23:51:09.731591 [Byte1]: 37
1652 23:51:09.735213
1653 23:51:09.735294 Set Vref, RX VrefLevel [Byte0]: 38
1654 23:51:09.739109 [Byte1]: 38
1655 23:51:09.742804
1656 23:51:09.742891 Set Vref, RX VrefLevel [Byte0]: 39
1657 23:51:09.746776 [Byte1]: 39
1658 23:51:09.750667
1659 23:51:09.750751 Set Vref, RX VrefLevel [Byte0]: 40
1660 23:51:09.753861 [Byte1]: 40
1661 23:51:09.758530
1662 23:51:09.758677 Set Vref, RX VrefLevel [Byte0]: 41
1663 23:51:09.761728 [Byte1]: 41
1664 23:51:09.765828
1665 23:51:09.765914 Set Vref, RX VrefLevel [Byte0]: 42
1666 23:51:09.769449 [Byte1]: 42
1667 23:51:09.773384
1668 23:51:09.773510 Set Vref, RX VrefLevel [Byte0]: 43
1669 23:51:09.776485 [Byte1]: 43
1670 23:51:09.781135
1671 23:51:09.781233 Set Vref, RX VrefLevel [Byte0]: 44
1672 23:51:09.784770 [Byte1]: 44
1673 23:51:09.788707
1674 23:51:09.788798 Set Vref, RX VrefLevel [Byte0]: 45
1675 23:51:09.791934 [Byte1]: 45
1676 23:51:09.796238
1677 23:51:09.796322 Set Vref, RX VrefLevel [Byte0]: 46
1678 23:51:09.799313 [Byte1]: 46
1679 23:51:09.803905
1680 23:51:09.803996 Set Vref, RX VrefLevel [Byte0]: 47
1681 23:51:09.807055 [Byte1]: 47
1682 23:51:09.811184
1683 23:51:09.811266 Set Vref, RX VrefLevel [Byte0]: 48
1684 23:51:09.814896 [Byte1]: 48
1685 23:51:09.818723
1686 23:51:09.818803 Set Vref, RX VrefLevel [Byte0]: 49
1687 23:51:09.822118 [Byte1]: 49
1688 23:51:09.826683
1689 23:51:09.826764 Set Vref, RX VrefLevel [Byte0]: 50
1690 23:51:09.829765 [Byte1]: 50
1691 23:51:09.834232
1692 23:51:09.834312 Set Vref, RX VrefLevel [Byte0]: 51
1693 23:51:09.837733 [Byte1]: 51
1694 23:51:09.841654
1695 23:51:09.841734 Set Vref, RX VrefLevel [Byte0]: 52
1696 23:51:09.844969 [Byte1]: 52
1697 23:51:09.849620
1698 23:51:09.849700 Set Vref, RX VrefLevel [Byte0]: 53
1699 23:51:09.852562 [Byte1]: 53
1700 23:51:09.857358
1701 23:51:09.857438 Set Vref, RX VrefLevel [Byte0]: 54
1702 23:51:09.860582 [Byte1]: 54
1703 23:51:09.865243
1704 23:51:09.865323 Set Vref, RX VrefLevel [Byte0]: 55
1705 23:51:09.867577 [Byte1]: 55
1706 23:51:09.872317
1707 23:51:09.872398 Set Vref, RX VrefLevel [Byte0]: 56
1708 23:51:09.875149 [Byte1]: 56
1709 23:51:09.879674
1710 23:51:09.879755 Set Vref, RX VrefLevel [Byte0]: 57
1711 23:51:09.883022 [Byte1]: 57
1712 23:51:09.887683
1713 23:51:09.887764 Set Vref, RX VrefLevel [Byte0]: 58
1714 23:51:09.890982 [Byte1]: 58
1715 23:51:09.895137
1716 23:51:09.895218 Set Vref, RX VrefLevel [Byte0]: 59
1717 23:51:09.898717 [Byte1]: 59
1718 23:51:09.902386
1719 23:51:09.902466 Set Vref, RX VrefLevel [Byte0]: 60
1720 23:51:09.906339 [Byte1]: 60
1721 23:51:09.909813
1722 23:51:09.909894 Set Vref, RX VrefLevel [Byte0]: 61
1723 23:51:09.913405 [Byte1]: 61
1724 23:51:09.917780
1725 23:51:09.917861 Set Vref, RX VrefLevel [Byte0]: 62
1726 23:51:09.922476 [Byte1]: 62
1727 23:51:09.925681
1728 23:51:09.928676 Set Vref, RX VrefLevel [Byte0]: 63
1729 23:51:09.928757 [Byte1]: 63
1730 23:51:09.932737
1731 23:51:09.932817 Set Vref, RX VrefLevel [Byte0]: 64
1732 23:51:09.936244 [Byte1]: 64
1733 23:51:09.940758
1734 23:51:09.940837 Set Vref, RX VrefLevel [Byte0]: 65
1735 23:51:09.943836 [Byte1]: 65
1736 23:51:09.948842
1737 23:51:09.948940 Set Vref, RX VrefLevel [Byte0]: 66
1738 23:51:09.951244 [Byte1]: 66
1739 23:51:09.955908
1740 23:51:09.955993 Set Vref, RX VrefLevel [Byte0]: 67
1741 23:51:09.958934 [Byte1]: 67
1742 23:51:09.963410
1743 23:51:09.963490 Set Vref, RX VrefLevel [Byte0]: 68
1744 23:51:09.967088 [Byte1]: 68
1745 23:51:09.971270
1746 23:51:09.971350 Set Vref, RX VrefLevel [Byte0]: 69
1747 23:51:09.974593 [Byte1]: 69
1748 23:51:09.978806
1749 23:51:09.978886 Set Vref, RX VrefLevel [Byte0]: 70
1750 23:51:09.981721 [Byte1]: 70
1751 23:51:09.986773
1752 23:51:09.986852 Set Vref, RX VrefLevel [Byte0]: 71
1753 23:51:09.989427 [Byte1]: 71
1754 23:51:09.993607
1755 23:51:09.993687 Set Vref, RX VrefLevel [Byte0]: 72
1756 23:51:09.996892 [Byte1]: 72
1757 23:51:10.001462
1758 23:51:10.001541 Set Vref, RX VrefLevel [Byte0]: 73
1759 23:51:10.004699 [Byte1]: 73
1760 23:51:10.008765
1761 23:51:10.008844 Set Vref, RX VrefLevel [Byte0]: 74
1762 23:51:10.012321 [Byte1]: 74
1763 23:51:10.016598
1764 23:51:10.016678 Set Vref, RX VrefLevel [Byte0]: 75
1765 23:51:10.020286 [Byte1]: 75
1766 23:51:10.024577
1767 23:51:10.024656 Set Vref, RX VrefLevel [Byte0]: 76
1768 23:51:10.028223 [Byte1]: 76
1769 23:51:10.032477
1770 23:51:10.032557 Set Vref, RX VrefLevel [Byte0]: 77
1771 23:51:10.035043 [Byte1]: 77
1772 23:51:10.039734
1773 23:51:10.039814 Set Vref, RX VrefLevel [Byte0]: 78
1774 23:51:10.042703 [Byte1]: 78
1775 23:51:10.046996
1776 23:51:10.047079 Set Vref, RX VrefLevel [Byte0]: 79
1777 23:51:10.050206 [Byte1]: 79
1778 23:51:10.054336
1779 23:51:10.054415 Set Vref, RX VrefLevel [Byte0]: 80
1780 23:51:10.058394 [Byte1]: 80
1781 23:51:10.062215
1782 23:51:10.062299 Final RX Vref Byte 0 = 63 to rank0
1783 23:51:10.065356 Final RX Vref Byte 1 = 55 to rank0
1784 23:51:10.068681 Final RX Vref Byte 0 = 63 to rank1
1785 23:51:10.072261 Final RX Vref Byte 1 = 55 to rank1==
1786 23:51:10.075721 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 23:51:10.078798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 23:51:10.082461 ==
1789 23:51:10.082541 DQS Delay:
1790 23:51:10.082603 DQS0 = 0, DQS1 = 0
1791 23:51:10.085724 DQM Delay:
1792 23:51:10.085804 DQM0 = 83, DQM1 = 74
1793 23:51:10.088894 DQ Delay:
1794 23:51:10.089033 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1795 23:51:10.092527 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1796 23:51:10.096362 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1797 23:51:10.099686 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1798 23:51:10.099767
1799 23:51:10.102573
1800 23:51:10.109368 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1801 23:51:10.112329 CH1 RK0: MR19=605, MR18=28FD
1802 23:51:10.119481 CH1_RK0: MR19=0x605, MR18=0x28FD, DQSOSC=399, MR23=63, INC=92, DEC=61
1803 23:51:10.119566
1804 23:51:10.122350 ----->DramcWriteLeveling(PI) begin...
1805 23:51:10.122431 ==
1806 23:51:10.125722 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 23:51:10.129488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 23:51:10.129581 ==
1809 23:51:10.132887 Write leveling (Byte 0): 27 => 27
1810 23:51:10.135900 Write leveling (Byte 1): 28 => 28
1811 23:51:10.139760 DramcWriteLeveling(PI) end<-----
1812 23:51:10.139840
1813 23:51:10.139902 ==
1814 23:51:10.143281 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 23:51:10.146579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 23:51:10.146659 ==
1817 23:51:10.149583 [Gating] SW mode calibration
1818 23:51:10.156214 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 23:51:10.162567 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 23:51:10.166141 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1821 23:51:10.169711 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1822 23:51:10.172932 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:51:10.179179 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:51:10.182734 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:51:10.186314 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:51:10.193287 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:51:10.196564 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:51:10.199924 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:51:10.206500 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:51:10.209894 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:51:10.212858 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:51:10.219597 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:51:10.223018 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:51:10.226720 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:51:10.230057 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:51:10.237177 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1837 23:51:10.240217 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1838 23:51:10.243324 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:51:10.250128 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:51:10.253175 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:51:10.256600 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:51:10.263422 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:51:10.266887 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:51:10.270308 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:51:10.276950 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1846 23:51:10.280582 0 9 8 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
1847 23:51:10.284347 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 23:51:10.290400 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 23:51:10.293693 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 23:51:10.296894 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1851 23:51:10.300611 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 23:51:10.307731 0 10 0 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
1853 23:51:10.310530 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1854 23:51:10.313730 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1855 23:51:10.320333 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:51:10.323879 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1857 23:51:10.327351 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:51:10.333736 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:51:10.336918 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:51:10.340435 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:51:10.347484 0 11 4 | B1->B0 | 2b2b 3838 | 0 0 | (0 0) (0 0)
1862 23:51:10.350564 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1863 23:51:10.354548 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 23:51:10.357293 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 23:51:10.364046 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 23:51:10.367559 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 23:51:10.370474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 23:51:10.377819 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1869 23:51:10.381070 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1870 23:51:10.384326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1871 23:51:10.391221 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:51:10.394588 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:51:10.397907 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:51:10.404653 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:51:10.407258 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:51:10.410933 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:51:10.417396 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:51:10.420924 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:51:10.424362 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:51:10.427970 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:51:10.434492 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 23:51:10.437638 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:51:10.440884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:51:10.449717 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:51:10.451561 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1886 23:51:10.454767 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1887 23:51:10.461494 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 23:51:10.461575 Total UI for P1: 0, mck2ui 16
1889 23:51:10.467447 best dqsien dly found for B0: ( 0, 14, 6)
1890 23:51:10.467553 Total UI for P1: 0, mck2ui 16
1891 23:51:10.470998 best dqsien dly found for B1: ( 0, 14, 6)
1892 23:51:10.477791 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1893 23:51:10.481242 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1894 23:51:10.481323
1895 23:51:10.484623 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 23:51:10.488564 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 23:51:10.491047 [Gating] SW calibration Done
1898 23:51:10.491127 ==
1899 23:51:10.494326 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 23:51:10.498456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 23:51:10.498537 ==
1902 23:51:10.498599 RX Vref Scan: 0
1903 23:51:10.501522
1904 23:51:10.501606 RX Vref 0 -> 0, step: 1
1905 23:51:10.501669
1906 23:51:10.505424 RX Delay -130 -> 252, step: 16
1907 23:51:10.507958 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1908 23:51:10.511229 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1909 23:51:10.518325 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1910 23:51:10.521657 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1911 23:51:10.524396 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1912 23:51:10.528457 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1913 23:51:10.531367 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1914 23:51:10.538179 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1915 23:51:10.541985 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1916 23:51:10.544705 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1917 23:51:10.549293 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1918 23:51:10.551921 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1919 23:51:10.558445 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1920 23:51:10.561797 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1921 23:51:10.564998 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1922 23:51:10.568107 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1923 23:51:10.568188 ==
1924 23:51:10.571429 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 23:51:10.574683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 23:51:10.578700 ==
1927 23:51:10.578781 DQS Delay:
1928 23:51:10.578844 DQS0 = 0, DQS1 = 0
1929 23:51:10.581649 DQM Delay:
1930 23:51:10.581730 DQM0 = 81, DQM1 = 77
1931 23:51:10.585424 DQ Delay:
1932 23:51:10.585504 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1933 23:51:10.588473 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1934 23:51:10.591678 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1935 23:51:10.594994 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1936 23:51:10.595075
1937 23:51:10.595138
1938 23:51:10.598440 ==
1939 23:51:10.601628 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 23:51:10.605043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 23:51:10.605125 ==
1942 23:51:10.605189
1943 23:51:10.605247
1944 23:51:10.608247 TX Vref Scan disable
1945 23:51:10.608327 == TX Byte 0 ==
1946 23:51:10.611811 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1947 23:51:10.618568 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1948 23:51:10.618649 == TX Byte 1 ==
1949 23:51:10.621998 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1950 23:51:10.628534 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1951 23:51:10.628615 ==
1952 23:51:10.631781 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 23:51:10.635554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 23:51:10.635636 ==
1955 23:51:10.648679 TX Vref=22, minBit 1, minWin=27, winSum=442
1956 23:51:10.651720 TX Vref=24, minBit 0, minWin=27, winSum=443
1957 23:51:10.655372 TX Vref=26, minBit 1, minWin=27, winSum=446
1958 23:51:10.658016 TX Vref=28, minBit 15, minWin=27, winSum=450
1959 23:51:10.662504 TX Vref=30, minBit 15, minWin=27, winSum=451
1960 23:51:10.665830 TX Vref=32, minBit 0, minWin=28, winSum=452
1961 23:51:10.672330 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1962 23:51:10.672412
1963 23:51:10.674990 Final TX Range 1 Vref 32
1964 23:51:10.675071
1965 23:51:10.675135 ==
1966 23:51:10.678318 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 23:51:10.681611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 23:51:10.681693 ==
1969 23:51:10.681756
1970 23:51:10.684821
1971 23:51:10.684901 TX Vref Scan disable
1972 23:51:10.688445 == TX Byte 0 ==
1973 23:51:10.691472 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1974 23:51:10.695501 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1975 23:51:10.698677 == TX Byte 1 ==
1976 23:51:10.701871 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 23:51:10.705726 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 23:51:10.705807
1979 23:51:10.708854 [DATLAT]
1980 23:51:10.708934 Freq=800, CH1 RK1
1981 23:51:10.709026
1982 23:51:10.711890 DATLAT Default: 0xa
1983 23:51:10.711970 0, 0xFFFF, sum = 0
1984 23:51:10.716017 1, 0xFFFF, sum = 0
1985 23:51:10.716099 2, 0xFFFF, sum = 0
1986 23:51:10.718584 3, 0xFFFF, sum = 0
1987 23:51:10.718667 4, 0xFFFF, sum = 0
1988 23:51:10.722187 5, 0xFFFF, sum = 0
1989 23:51:10.722269 6, 0xFFFF, sum = 0
1990 23:51:10.725961 7, 0xFFFF, sum = 0
1991 23:51:10.726042 8, 0xFFFF, sum = 0
1992 23:51:10.729171 9, 0x0, sum = 1
1993 23:51:10.729253 10, 0x0, sum = 2
1994 23:51:10.732130 11, 0x0, sum = 3
1995 23:51:10.732212 12, 0x0, sum = 4
1996 23:51:10.736180 best_step = 10
1997 23:51:10.736260
1998 23:51:10.736323 ==
1999 23:51:10.738616 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 23:51:10.742295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 23:51:10.742376 ==
2002 23:51:10.742439 RX Vref Scan: 0
2003 23:51:10.745826
2004 23:51:10.745906 RX Vref 0 -> 0, step: 1
2005 23:51:10.745968
2006 23:51:10.748929 RX Delay -111 -> 252, step: 8
2007 23:51:10.752462 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2008 23:51:10.759567 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2009 23:51:10.762464 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2010 23:51:10.766211 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2011 23:51:10.769736 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2012 23:51:10.772548 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2013 23:51:10.776590 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2014 23:51:10.782691 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2015 23:51:10.785840 iDelay=201, Bit 8, Center 68 (-47 ~ 184) 232
2016 23:51:10.789466 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2017 23:51:10.793368 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2018 23:51:10.796493 iDelay=201, Bit 11, Center 72 (-39 ~ 184) 224
2019 23:51:10.802648 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2020 23:51:10.806210 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2021 23:51:10.809459 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2022 23:51:10.812803 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2023 23:51:10.812909 ==
2024 23:51:10.816314 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 23:51:10.823307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 23:51:10.823388 ==
2027 23:51:10.823451 DQS Delay:
2028 23:51:10.823510 DQS0 = 0, DQS1 = 0
2029 23:51:10.826835 DQM Delay:
2030 23:51:10.826917 DQM0 = 79, DQM1 = 76
2031 23:51:10.830048 DQ Delay:
2032 23:51:10.833469 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2033 23:51:10.833549 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
2034 23:51:10.837275 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =72
2035 23:51:10.839740 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2036 23:51:10.843383
2037 23:51:10.843464
2038 23:51:10.850007 [DQSOSCAuto] RK1, (LSB)MR18= 0x232e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2039 23:51:10.853568 CH1 RK1: MR19=606, MR18=232E
2040 23:51:10.860099 CH1_RK1: MR19=0x606, MR18=0x232E, DQSOSC=398, MR23=63, INC=93, DEC=62
2041 23:51:10.860181 [RxdqsGatingPostProcess] freq 800
2042 23:51:10.866609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 23:51:10.870545 Pre-setting of DQS Precalculation
2044 23:51:10.874130 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 23:51:10.883804 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 23:51:10.890574 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 23:51:10.890657
2048 23:51:10.890720
2049 23:51:10.893495 [Calibration Summary] 1600 Mbps
2050 23:51:10.893577 CH 0, Rank 0
2051 23:51:10.897900 SW Impedance : PASS
2052 23:51:10.897981 DUTY Scan : NO K
2053 23:51:10.900735 ZQ Calibration : PASS
2054 23:51:10.903595 Jitter Meter : NO K
2055 23:51:10.903676 CBT Training : PASS
2056 23:51:10.907292 Write leveling : PASS
2057 23:51:10.910273 RX DQS gating : PASS
2058 23:51:10.910353 RX DQ/DQS(RDDQC) : PASS
2059 23:51:10.913630 TX DQ/DQS : PASS
2060 23:51:10.917089 RX DATLAT : PASS
2061 23:51:10.917169 RX DQ/DQS(Engine): PASS
2062 23:51:10.920308 TX OE : NO K
2063 23:51:10.920391 All Pass.
2064 23:51:10.920455
2065 23:51:10.923959 CH 0, Rank 1
2066 23:51:10.924040 SW Impedance : PASS
2067 23:51:10.927062 DUTY Scan : NO K
2068 23:51:10.927142 ZQ Calibration : PASS
2069 23:51:10.930264 Jitter Meter : NO K
2070 23:51:10.933581 CBT Training : PASS
2071 23:51:10.933661 Write leveling : PASS
2072 23:51:10.936901 RX DQS gating : PASS
2073 23:51:10.940245 RX DQ/DQS(RDDQC) : PASS
2074 23:51:10.940326 TX DQ/DQS : PASS
2075 23:51:10.943843 RX DATLAT : PASS
2076 23:51:10.947567 RX DQ/DQS(Engine): PASS
2077 23:51:10.947647 TX OE : NO K
2078 23:51:10.950663 All Pass.
2079 23:51:10.950743
2080 23:51:10.950805 CH 1, Rank 0
2081 23:51:10.953695 SW Impedance : PASS
2082 23:51:10.953775 DUTY Scan : NO K
2083 23:51:10.957779 ZQ Calibration : PASS
2084 23:51:10.960866 Jitter Meter : NO K
2085 23:51:10.960978 CBT Training : PASS
2086 23:51:10.963985 Write leveling : PASS
2087 23:51:10.964064 RX DQS gating : PASS
2088 23:51:10.967536 RX DQ/DQS(RDDQC) : PASS
2089 23:51:10.971177 TX DQ/DQS : PASS
2090 23:51:10.971257 RX DATLAT : PASS
2091 23:51:10.973794 RX DQ/DQS(Engine): PASS
2092 23:51:10.977247 TX OE : NO K
2093 23:51:10.977331 All Pass.
2094 23:51:10.977393
2095 23:51:10.977451 CH 1, Rank 1
2096 23:51:10.980937 SW Impedance : PASS
2097 23:51:10.984590 DUTY Scan : NO K
2098 23:51:10.984670 ZQ Calibration : PASS
2099 23:51:10.987464 Jitter Meter : NO K
2100 23:51:10.991182 CBT Training : PASS
2101 23:51:10.991262 Write leveling : PASS
2102 23:51:10.993999 RX DQS gating : PASS
2103 23:51:10.994080 RX DQ/DQS(RDDQC) : PASS
2104 23:51:10.997760 TX DQ/DQS : PASS
2105 23:51:11.000610 RX DATLAT : PASS
2106 23:51:11.000695 RX DQ/DQS(Engine): PASS
2107 23:51:11.003974 TX OE : NO K
2108 23:51:11.004054 All Pass.
2109 23:51:11.004116
2110 23:51:11.007640 DramC Write-DBI off
2111 23:51:11.010762 PER_BANK_REFRESH: Hybrid Mode
2112 23:51:11.010845 TX_TRACKING: ON
2113 23:51:11.014309 [GetDramInforAfterCalByMRR] Vendor 6.
2114 23:51:11.017824 [GetDramInforAfterCalByMRR] Revision 606.
2115 23:51:11.021058 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 23:51:11.024214 MR0 0x3b3b
2117 23:51:11.024294 MR8 0x5151
2118 23:51:11.028376 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 23:51:11.028455
2120 23:51:11.028517 MR0 0x3b3b
2121 23:51:11.031257 MR8 0x5151
2122 23:51:11.035134 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 23:51:11.035213
2124 23:51:11.044907 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 23:51:11.048722 [FAST_K] Save calibration result to emmc
2126 23:51:11.051198 [FAST_K] Save calibration result to emmc
2127 23:51:11.051278 dram_init: config_dvfs: 1
2128 23:51:11.057930 dramc_set_vcore_voltage set vcore to 662500
2129 23:51:11.058009 Read voltage for 1200, 2
2130 23:51:11.058092 Vio18 = 0
2131 23:51:11.061199 Vcore = 662500
2132 23:51:11.061278 Vdram = 0
2133 23:51:11.061340 Vddq = 0
2134 23:51:11.064767 Vmddr = 0
2135 23:51:11.069700 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 23:51:11.074857 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 23:51:11.074938 MEM_TYPE=3, freq_sel=15
2138 23:51:11.077995 sv_algorithm_assistance_LP4_1600
2139 23:51:11.085964 ============ PULL DRAM RESETB DOWN ============
2140 23:51:11.088307 ========== PULL DRAM RESETB DOWN end =========
2141 23:51:11.091138 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 23:51:11.095206 ===================================
2143 23:51:11.098221 LPDDR4 DRAM CONFIGURATION
2144 23:51:11.101347 ===================================
2145 23:51:11.104804 EX_ROW_EN[0] = 0x0
2146 23:51:11.104884 EX_ROW_EN[1] = 0x0
2147 23:51:11.108199 LP4Y_EN = 0x0
2148 23:51:11.108287 WORK_FSP = 0x0
2149 23:51:11.111523 WL = 0x4
2150 23:51:11.111602 RL = 0x4
2151 23:51:11.114881 BL = 0x2
2152 23:51:11.114961 RPST = 0x0
2153 23:51:11.118155 RD_PRE = 0x0
2154 23:51:11.118235 WR_PRE = 0x1
2155 23:51:11.121610 WR_PST = 0x0
2156 23:51:11.121690 DBI_WR = 0x0
2157 23:51:11.124964 DBI_RD = 0x0
2158 23:51:11.125077 OTF = 0x1
2159 23:51:11.127943 ===================================
2160 23:51:11.131467 ===================================
2161 23:51:11.135343 ANA top config
2162 23:51:11.138529 ===================================
2163 23:51:11.138610 DLL_ASYNC_EN = 0
2164 23:51:11.142462 ALL_SLAVE_EN = 0
2165 23:51:11.145464 NEW_RANK_MODE = 1
2166 23:51:11.148552 DLL_IDLE_MODE = 1
2167 23:51:11.148632 LP45_APHY_COMB_EN = 1
2168 23:51:11.151694 TX_ODT_DIS = 1
2169 23:51:11.155204 NEW_8X_MODE = 1
2170 23:51:11.158727 ===================================
2171 23:51:11.161744 ===================================
2172 23:51:11.165549 data_rate = 2400
2173 23:51:11.168868 CKR = 1
2174 23:51:11.171764 DQ_P2S_RATIO = 8
2175 23:51:11.171843 ===================================
2176 23:51:11.175425 CA_P2S_RATIO = 8
2177 23:51:11.178288 DQ_CA_OPEN = 0
2178 23:51:11.182729 DQ_SEMI_OPEN = 0
2179 23:51:11.185077 CA_SEMI_OPEN = 0
2180 23:51:11.188926 CA_FULL_RATE = 0
2181 23:51:11.189043 DQ_CKDIV4_EN = 0
2182 23:51:11.192143 CA_CKDIV4_EN = 0
2183 23:51:11.196148 CA_PREDIV_EN = 0
2184 23:51:11.198469 PH8_DLY = 17
2185 23:51:11.201796 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 23:51:11.205379 DQ_AAMCK_DIV = 4
2187 23:51:11.205460 CA_AAMCK_DIV = 4
2188 23:51:11.209466 CA_ADMCK_DIV = 4
2189 23:51:11.212173 DQ_TRACK_CA_EN = 0
2190 23:51:11.215440 CA_PICK = 1200
2191 23:51:11.218504 CA_MCKIO = 1200
2192 23:51:11.222481 MCKIO_SEMI = 0
2193 23:51:11.225619 PLL_FREQ = 2366
2194 23:51:11.225699 DQ_UI_PI_RATIO = 32
2195 23:51:11.228879 CA_UI_PI_RATIO = 0
2196 23:51:11.232365 ===================================
2197 23:51:11.235455 ===================================
2198 23:51:11.239087 memory_type:LPDDR4
2199 23:51:11.242453 GP_NUM : 10
2200 23:51:11.242533 SRAM_EN : 1
2201 23:51:11.246089 MD32_EN : 0
2202 23:51:11.248762 ===================================
2203 23:51:11.248842 [ANA_INIT] >>>>>>>>>>>>>>
2204 23:51:11.252142 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 23:51:11.255603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 23:51:11.258825 ===================================
2207 23:51:11.262466 data_rate = 2400,PCW = 0X5b00
2208 23:51:11.265787 ===================================
2209 23:51:11.269194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 23:51:11.275811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 23:51:11.279336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 23:51:11.285516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 23:51:11.289138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 23:51:11.292801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 23:51:11.292882 [ANA_INIT] flow start
2216 23:51:11.295469 [ANA_INIT] PLL >>>>>>>>
2217 23:51:11.299344 [ANA_INIT] PLL <<<<<<<<
2218 23:51:11.302171 [ANA_INIT] MIDPI >>>>>>>>
2219 23:51:11.302251 [ANA_INIT] MIDPI <<<<<<<<
2220 23:51:11.305388 [ANA_INIT] DLL >>>>>>>>
2221 23:51:11.309319 [ANA_INIT] DLL <<<<<<<<
2222 23:51:11.309399 [ANA_INIT] flow end
2223 23:51:11.312466 ============ LP4 DIFF to SE enter ============
2224 23:51:11.318848 ============ LP4 DIFF to SE exit ============
2225 23:51:11.318928 [ANA_INIT] <<<<<<<<<<<<<
2226 23:51:11.322867 [Flow] Enable top DCM control >>>>>
2227 23:51:11.326647 [Flow] Enable top DCM control <<<<<
2228 23:51:11.329147 Enable DLL master slave shuffle
2229 23:51:11.336938 ==============================================================
2230 23:51:11.337056 Gating Mode config
2231 23:51:11.342871 ==============================================================
2232 23:51:11.345976 Config description:
2233 23:51:11.352612 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 23:51:11.359677 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 23:51:11.365878 SELPH_MODE 0: By rank 1: By Phase
2236 23:51:11.369965 ==============================================================
2237 23:51:11.373409 GAT_TRACK_EN = 1
2238 23:51:11.376144 RX_GATING_MODE = 2
2239 23:51:11.379439 RX_GATING_TRACK_MODE = 2
2240 23:51:11.382884 SELPH_MODE = 1
2241 23:51:11.386156 PICG_EARLY_EN = 1
2242 23:51:11.390078 VALID_LAT_VALUE = 1
2243 23:51:11.393274 ==============================================================
2244 23:51:11.396395 Enter into Gating configuration >>>>
2245 23:51:11.400317 Exit from Gating configuration <<<<
2246 23:51:11.403018 Enter into DVFS_PRE_config >>>>>
2247 23:51:11.416334 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 23:51:11.419855 Exit from DVFS_PRE_config <<<<<
2249 23:51:11.423513 Enter into PICG configuration >>>>
2250 23:51:11.423592 Exit from PICG configuration <<<<
2251 23:51:11.426689 [RX_INPUT] configuration >>>>>
2252 23:51:11.430156 [RX_INPUT] configuration <<<<<
2253 23:51:11.437119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 23:51:11.439775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 23:51:11.446982 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 23:51:11.453287 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 23:51:11.460693 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 23:51:11.467103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 23:51:11.470287 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 23:51:11.474098 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 23:51:11.477112 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 23:51:11.480370 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 23:51:11.487892 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 23:51:11.490829 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 23:51:11.494178 ===================================
2266 23:51:11.497029 LPDDR4 DRAM CONFIGURATION
2267 23:51:11.500704 ===================================
2268 23:51:11.500810 EX_ROW_EN[0] = 0x0
2269 23:51:11.504015 EX_ROW_EN[1] = 0x0
2270 23:51:11.504093 LP4Y_EN = 0x0
2271 23:51:11.507161 WORK_FSP = 0x0
2272 23:51:11.507240 WL = 0x4
2273 23:51:11.510638 RL = 0x4
2274 23:51:11.510718 BL = 0x2
2275 23:51:11.514519 RPST = 0x0
2276 23:51:11.517530 RD_PRE = 0x0
2277 23:51:11.517609 WR_PRE = 0x1
2278 23:51:11.520440 WR_PST = 0x0
2279 23:51:11.520525 DBI_WR = 0x0
2280 23:51:11.523605 DBI_RD = 0x0
2281 23:51:11.523685 OTF = 0x1
2282 23:51:11.528399 ===================================
2283 23:51:11.530717 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 23:51:11.533657 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 23:51:11.541464 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 23:51:11.543902 ===================================
2287 23:51:11.543983 LPDDR4 DRAM CONFIGURATION
2288 23:51:11.550856 ===================================
2289 23:51:11.550960 EX_ROW_EN[0] = 0x10
2290 23:51:11.554319 EX_ROW_EN[1] = 0x0
2291 23:51:11.554399 LP4Y_EN = 0x0
2292 23:51:11.558115 WORK_FSP = 0x0
2293 23:51:11.558195 WL = 0x4
2294 23:51:11.561017 RL = 0x4
2295 23:51:11.561096 BL = 0x2
2296 23:51:11.564637 RPST = 0x0
2297 23:51:11.564716 RD_PRE = 0x0
2298 23:51:11.567060 WR_PRE = 0x1
2299 23:51:11.567139 WR_PST = 0x0
2300 23:51:11.571403 DBI_WR = 0x0
2301 23:51:11.571482 DBI_RD = 0x0
2302 23:51:11.574248 OTF = 0x1
2303 23:51:11.577238 ===================================
2304 23:51:11.583683 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 23:51:11.583781 ==
2306 23:51:11.587803 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 23:51:11.590932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 23:51:11.591011 ==
2309 23:51:11.594211 [Duty_Offset_Calibration]
2310 23:51:11.594315 B0:2 B1:-1 CA:1
2311 23:51:11.594404
2312 23:51:11.597585 [DutyScan_Calibration_Flow] k_type=0
2313 23:51:11.607574
2314 23:51:11.607678 ==CLK 0==
2315 23:51:11.610661 Final CLK duty delay cell = -4
2316 23:51:11.613533 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2317 23:51:11.617934 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2318 23:51:11.620362 [-4] AVG Duty = 4953%(X100)
2319 23:51:11.620441
2320 23:51:11.623686 CH0 CLK Duty spec in!! Max-Min= 156%
2321 23:51:11.627145 [DutyScan_Calibration_Flow] ====Done====
2322 23:51:11.627224
2323 23:51:11.630315 [DutyScan_Calibration_Flow] k_type=1
2324 23:51:11.645293
2325 23:51:11.645372 ==DQS 0 ==
2326 23:51:11.648803 Final DQS duty delay cell = -4
2327 23:51:11.651655 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2328 23:51:11.654949 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2329 23:51:11.658157 [-4] AVG Duty = 4938%(X100)
2330 23:51:11.658235
2331 23:51:11.658296 ==DQS 1 ==
2332 23:51:11.661628 Final DQS duty delay cell = -4
2333 23:51:11.664859 [-4] MAX Duty = 5093%(X100), DQS PI = 16
2334 23:51:11.668607 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2335 23:51:11.672582 [-4] AVG Duty = 5046%(X100)
2336 23:51:11.672689
2337 23:51:11.675209 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2338 23:51:11.675287
2339 23:51:11.678591 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2340 23:51:11.681839 [DutyScan_Calibration_Flow] ====Done====
2341 23:51:11.681942
2342 23:51:11.685403 [DutyScan_Calibration_Flow] k_type=3
2343 23:51:11.701989
2344 23:51:11.702068 ==DQM 0 ==
2345 23:51:11.705845 Final DQM duty delay cell = 0
2346 23:51:11.709324 [0] MAX Duty = 5000%(X100), DQS PI = 46
2347 23:51:11.712743 [0] MIN Duty = 4907%(X100), DQS PI = 0
2348 23:51:11.712848 [0] AVG Duty = 4953%(X100)
2349 23:51:11.712946
2350 23:51:11.715838 ==DQM 1 ==
2351 23:51:11.718932 Final DQM duty delay cell = 0
2352 23:51:11.722196 [0] MAX Duty = 5156%(X100), DQS PI = 62
2353 23:51:11.726275 [0] MIN Duty = 4969%(X100), DQS PI = 10
2354 23:51:11.726384 [0] AVG Duty = 5062%(X100)
2355 23:51:11.726477
2356 23:51:11.729308 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2357 23:51:11.732678
2358 23:51:11.736139 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2359 23:51:11.738871 [DutyScan_Calibration_Flow] ====Done====
2360 23:51:11.738963
2361 23:51:11.742512 [DutyScan_Calibration_Flow] k_type=2
2362 23:51:11.757832
2363 23:51:11.757936 ==DQ 0 ==
2364 23:51:11.761162 Final DQ duty delay cell = -4
2365 23:51:11.764439 [-4] MAX Duty = 5093%(X100), DQS PI = 54
2366 23:51:11.767838 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2367 23:51:11.771281 [-4] AVG Duty = 4968%(X100)
2368 23:51:11.771362
2369 23:51:11.771427 ==DQ 1 ==
2370 23:51:11.774499 Final DQ duty delay cell = 0
2371 23:51:11.778041 [0] MAX Duty = 5031%(X100), DQS PI = 18
2372 23:51:11.781743 [0] MIN Duty = 4907%(X100), DQS PI = 46
2373 23:51:11.781941 [0] AVG Duty = 4969%(X100)
2374 23:51:11.782046
2375 23:51:11.785243 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2376 23:51:11.788240
2377 23:51:11.791750 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2378 23:51:11.794575 [DutyScan_Calibration_Flow] ====Done====
2379 23:51:11.794656 ==
2380 23:51:11.798439 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 23:51:11.801630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 23:51:11.801713 ==
2383 23:51:11.804852 [Duty_Offset_Calibration]
2384 23:51:11.804930 B0:1 B1:1 CA:2
2385 23:51:11.805030
2386 23:51:11.808154 [DutyScan_Calibration_Flow] k_type=0
2387 23:51:11.818084
2388 23:51:11.818189 ==CLK 0==
2389 23:51:11.821388 Final CLK duty delay cell = 0
2390 23:51:11.825245 [0] MAX Duty = 5156%(X100), DQS PI = 24
2391 23:51:11.828184 [0] MIN Duty = 4938%(X100), DQS PI = 40
2392 23:51:11.828263 [0] AVG Duty = 5047%(X100)
2393 23:51:11.831520
2394 23:51:11.835127 CH1 CLK Duty spec in!! Max-Min= 218%
2395 23:51:11.838262 [DutyScan_Calibration_Flow] ====Done====
2396 23:51:11.838344
2397 23:51:11.841538 [DutyScan_Calibration_Flow] k_type=1
2398 23:51:11.857416
2399 23:51:11.857497 ==DQS 0 ==
2400 23:51:11.860840 Final DQS duty delay cell = 0
2401 23:51:11.864968 [0] MAX Duty = 5031%(X100), DQS PI = 18
2402 23:51:11.867876 [0] MIN Duty = 4813%(X100), DQS PI = 48
2403 23:51:11.867954 [0] AVG Duty = 4922%(X100)
2404 23:51:11.871018
2405 23:51:11.871096 ==DQS 1 ==
2406 23:51:11.874499 Final DQS duty delay cell = 0
2407 23:51:11.877634 [0] MAX Duty = 5062%(X100), DQS PI = 36
2408 23:51:11.881261 [0] MIN Duty = 4875%(X100), DQS PI = 16
2409 23:51:11.881341 [0] AVG Duty = 4968%(X100)
2410 23:51:11.884891
2411 23:51:11.887928 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2412 23:51:11.888008
2413 23:51:11.891049 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2414 23:51:11.894521 [DutyScan_Calibration_Flow] ====Done====
2415 23:51:11.894603
2416 23:51:11.897592 [DutyScan_Calibration_Flow] k_type=3
2417 23:51:11.914367
2418 23:51:11.914446 ==DQM 0 ==
2419 23:51:11.917156 Final DQM duty delay cell = 0
2420 23:51:11.920523 [0] MAX Duty = 5093%(X100), DQS PI = 18
2421 23:51:11.924056 [0] MIN Duty = 4876%(X100), DQS PI = 50
2422 23:51:11.924137 [0] AVG Duty = 4984%(X100)
2423 23:51:11.927545
2424 23:51:11.927625 ==DQM 1 ==
2425 23:51:11.930848 Final DQM duty delay cell = 0
2426 23:51:11.934905 [0] MAX Duty = 5156%(X100), DQS PI = 62
2427 23:51:11.937574 [0] MIN Duty = 4938%(X100), DQS PI = 22
2428 23:51:11.937655 [0] AVG Duty = 5047%(X100)
2429 23:51:11.940901
2430 23:51:11.944070 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2431 23:51:11.944169
2432 23:51:11.947702 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2433 23:51:11.950428 [DutyScan_Calibration_Flow] ====Done====
2434 23:51:11.950508
2435 23:51:11.953705 [DutyScan_Calibration_Flow] k_type=2
2436 23:51:11.970741
2437 23:51:11.970822 ==DQ 0 ==
2438 23:51:11.973847 Final DQ duty delay cell = 0
2439 23:51:11.977477 [0] MAX Duty = 5124%(X100), DQS PI = 18
2440 23:51:11.980948 [0] MIN Duty = 4938%(X100), DQS PI = 50
2441 23:51:11.981067 [0] AVG Duty = 5031%(X100)
2442 23:51:11.981131
2443 23:51:11.984062 ==DQ 1 ==
2444 23:51:11.987457 Final DQ duty delay cell = 0
2445 23:51:11.991359 [0] MAX Duty = 5093%(X100), DQS PI = 10
2446 23:51:11.994041 [0] MIN Duty = 5031%(X100), DQS PI = 2
2447 23:51:11.994122 [0] AVG Duty = 5062%(X100)
2448 23:51:11.994185
2449 23:51:11.997231 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2450 23:51:11.997311
2451 23:51:12.000743 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2452 23:51:12.007674 [DutyScan_Calibration_Flow] ====Done====
2453 23:51:12.010782 nWR fixed to 30
2454 23:51:12.010862 [ModeRegInit_LP4] CH0 RK0
2455 23:51:12.014859 [ModeRegInit_LP4] CH0 RK1
2456 23:51:12.017919 [ModeRegInit_LP4] CH1 RK0
2457 23:51:12.017999 [ModeRegInit_LP4] CH1 RK1
2458 23:51:12.021138 match AC timing 7
2459 23:51:12.024253 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 23:51:12.027546 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 23:51:12.034118 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 23:51:12.037348 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 23:51:12.044177 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 23:51:12.044257 ==
2465 23:51:12.047708 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 23:51:12.051241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 23:51:12.051322 ==
2468 23:51:12.055091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 23:51:12.060883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 23:51:12.070542 [CA 0] Center 40 (10~71) winsize 62
2471 23:51:12.073821 [CA 1] Center 39 (9~70) winsize 62
2472 23:51:12.077378 [CA 2] Center 36 (6~67) winsize 62
2473 23:51:12.080445 [CA 3] Center 36 (6~66) winsize 61
2474 23:51:12.084487 [CA 4] Center 34 (4~65) winsize 62
2475 23:51:12.087684 [CA 5] Center 34 (4~64) winsize 61
2476 23:51:12.087764
2477 23:51:12.090592 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 23:51:12.090672
2479 23:51:12.094226 [CATrainingPosCal] consider 1 rank data
2480 23:51:12.097344 u2DelayCellTimex100 = 270/100 ps
2481 23:51:12.100437 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2482 23:51:12.103974 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2483 23:51:12.110704 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2484 23:51:12.114832 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2485 23:51:12.117843 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2486 23:51:12.120758 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2487 23:51:12.120881
2488 23:51:12.124901 CA PerBit enable=1, Macro0, CA PI delay=34
2489 23:51:12.124988
2490 23:51:12.127628 [CBTSetCACLKResult] CA Dly = 34
2491 23:51:12.127726 CS Dly: 7 (0~38)
2492 23:51:12.127791 ==
2493 23:51:12.131045 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 23:51:12.137516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 23:51:12.137597 ==
2496 23:51:12.140969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 23:51:12.147767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2498 23:51:12.157088 [CA 0] Center 39 (9~70) winsize 62
2499 23:51:12.159874 [CA 1] Center 39 (9~70) winsize 62
2500 23:51:12.162945 [CA 2] Center 36 (6~67) winsize 62
2501 23:51:12.166287 [CA 3] Center 35 (5~66) winsize 62
2502 23:51:12.169901 [CA 4] Center 34 (4~65) winsize 62
2503 23:51:12.173258 [CA 5] Center 34 (4~64) winsize 61
2504 23:51:12.173339
2505 23:51:12.177645 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 23:51:12.177726
2507 23:51:12.180552 [CATrainingPosCal] consider 2 rank data
2508 23:51:12.183350 u2DelayCellTimex100 = 270/100 ps
2509 23:51:12.187151 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2510 23:51:12.190167 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2511 23:51:12.193356 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2512 23:51:12.200800 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2513 23:51:12.204008 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2514 23:51:12.206885 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2515 23:51:12.206965
2516 23:51:12.210217 CA PerBit enable=1, Macro0, CA PI delay=34
2517 23:51:12.210298
2518 23:51:12.213865 [CBTSetCACLKResult] CA Dly = 34
2519 23:51:12.213945 CS Dly: 8 (0~41)
2520 23:51:12.214007
2521 23:51:12.216843 ----->DramcWriteLeveling(PI) begin...
2522 23:51:12.216967 ==
2523 23:51:12.220200 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 23:51:12.227329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 23:51:12.227409 ==
2526 23:51:12.230720 Write leveling (Byte 0): 30 => 30
2527 23:51:12.233903 Write leveling (Byte 1): 28 => 28
2528 23:51:12.233983 DramcWriteLeveling(PI) end<-----
2529 23:51:12.234045
2530 23:51:12.236965 ==
2531 23:51:12.237052 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 23:51:12.244282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 23:51:12.244363 ==
2534 23:51:12.247147 [Gating] SW mode calibration
2535 23:51:12.253800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 23:51:12.257198 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 23:51:12.263876 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 23:51:12.267475 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2539 23:51:12.270852 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2540 23:51:12.277341 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 23:51:12.280988 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 23:51:12.284067 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 23:51:12.287618 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 23:51:12.293794 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 23:51:12.297660 1 0 0 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
2546 23:51:12.300390 1 0 4 | B1->B0 | 2929 2424 | 0 0 | (1 0) (0 0)
2547 23:51:12.307305 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 23:51:12.310992 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 23:51:12.314377 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 23:51:12.320850 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 23:51:12.323760 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 23:51:12.327685 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 23:51:12.334103 1 1 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
2554 23:51:12.337608 1 1 4 | B1->B0 | 3c3c 4545 | 1 0 | (0 0) (0 0)
2555 23:51:12.340661 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 23:51:12.347787 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 23:51:12.351198 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 23:51:12.354258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 23:51:12.358001 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 23:51:12.364017 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 23:51:12.368100 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 23:51:12.370676 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 23:51:12.377689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 23:51:12.380593 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:51:12.383850 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:51:12.390774 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:51:12.394163 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:51:12.397810 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:51:12.404515 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:51:12.407587 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:51:12.411061 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:51:12.417662 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:51:12.421310 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:51:12.424689 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:51:12.431327 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:51:12.434418 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 23:51:12.438094 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2578 23:51:12.441073 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 23:51:12.444758 Total UI for P1: 0, mck2ui 16
2580 23:51:12.447844 best dqsien dly found for B0: ( 1, 3, 30)
2581 23:51:12.451278 Total UI for P1: 0, mck2ui 16
2582 23:51:12.454729 best dqsien dly found for B1: ( 1, 4, 0)
2583 23:51:12.457643 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2584 23:51:12.461256 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2585 23:51:12.461338
2586 23:51:12.467933 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2587 23:51:12.471980 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2588 23:51:12.472060 [Gating] SW calibration Done
2589 23:51:12.474369 ==
2590 23:51:12.477632 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 23:51:12.481422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 23:51:12.481503 ==
2593 23:51:12.481566 RX Vref Scan: 0
2594 23:51:12.481625
2595 23:51:12.484622 RX Vref 0 -> 0, step: 1
2596 23:51:12.484701
2597 23:51:12.488101 RX Delay -40 -> 252, step: 8
2598 23:51:12.491356 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2599 23:51:12.494484 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2600 23:51:12.498953 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2601 23:51:12.504993 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2602 23:51:12.507907 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2603 23:51:12.511883 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2604 23:51:12.514932 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2605 23:51:12.518130 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2606 23:51:12.522245 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 23:51:12.528409 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 23:51:12.532623 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2609 23:51:12.534991 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2610 23:51:12.537991 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2611 23:51:12.541711 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2612 23:51:12.548427 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 23:51:12.551491 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2614 23:51:12.551572 ==
2615 23:51:12.555166 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 23:51:12.558877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 23:51:12.558959 ==
2618 23:51:12.561840 DQS Delay:
2619 23:51:12.561919 DQS0 = 0, DQS1 = 0
2620 23:51:12.561982 DQM Delay:
2621 23:51:12.565029 DQM0 = 115, DQM1 = 107
2622 23:51:12.565109 DQ Delay:
2623 23:51:12.569245 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2624 23:51:12.572149 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2625 23:51:12.575024 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2626 23:51:12.581589 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2627 23:51:12.581669
2628 23:51:12.581731
2629 23:51:12.581788 ==
2630 23:51:12.585191 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 23:51:12.588894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 23:51:12.589037 ==
2633 23:51:12.589102
2634 23:51:12.589161
2635 23:51:12.591905 TX Vref Scan disable
2636 23:51:12.591985 == TX Byte 0 ==
2637 23:51:12.598436 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2638 23:51:12.602165 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2639 23:51:12.602246 == TX Byte 1 ==
2640 23:51:12.608819 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2641 23:51:12.612123 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2642 23:51:12.612204 ==
2643 23:51:12.615101 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 23:51:12.618543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 23:51:12.618624 ==
2646 23:51:12.631267 TX Vref=22, minBit 1, minWin=24, winSum=417
2647 23:51:12.635228 TX Vref=24, minBit 1, minWin=25, winSum=420
2648 23:51:12.637902 TX Vref=26, minBit 1, minWin=25, winSum=425
2649 23:51:12.640885 TX Vref=28, minBit 0, minWin=26, winSum=431
2650 23:51:12.644635 TX Vref=30, minBit 0, minWin=26, winSum=430
2651 23:51:12.647582 TX Vref=32, minBit 0, minWin=26, winSum=432
2652 23:51:12.654541 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 32
2653 23:51:12.654622
2654 23:51:12.657753 Final TX Range 1 Vref 32
2655 23:51:12.657833
2656 23:51:12.657896 ==
2657 23:51:12.661212 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 23:51:12.664380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 23:51:12.664460 ==
2660 23:51:12.664522
2661 23:51:12.664580
2662 23:51:12.667928 TX Vref Scan disable
2663 23:51:12.671202 == TX Byte 0 ==
2664 23:51:12.674828 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2665 23:51:12.678008 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2666 23:51:12.681288 == TX Byte 1 ==
2667 23:51:12.684600 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2668 23:51:12.688112 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2669 23:51:12.688193
2670 23:51:12.691287 [DATLAT]
2671 23:51:12.691367 Freq=1200, CH0 RK0
2672 23:51:12.691429
2673 23:51:12.694756 DATLAT Default: 0xd
2674 23:51:12.694836 0, 0xFFFF, sum = 0
2675 23:51:12.697961 1, 0xFFFF, sum = 0
2676 23:51:12.698043 2, 0xFFFF, sum = 0
2677 23:51:12.701372 3, 0xFFFF, sum = 0
2678 23:51:12.701453 4, 0xFFFF, sum = 0
2679 23:51:12.705304 5, 0xFFFF, sum = 0
2680 23:51:12.705385 6, 0xFFFF, sum = 0
2681 23:51:12.709553 7, 0xFFFF, sum = 0
2682 23:51:12.709634 8, 0xFFFF, sum = 0
2683 23:51:12.711330 9, 0xFFFF, sum = 0
2684 23:51:12.711411 10, 0xFFFF, sum = 0
2685 23:51:12.714601 11, 0xFFFF, sum = 0
2686 23:51:12.714683 12, 0x0, sum = 1
2687 23:51:12.717899 13, 0x0, sum = 2
2688 23:51:12.717980 14, 0x0, sum = 3
2689 23:51:12.721533 15, 0x0, sum = 4
2690 23:51:12.721615 best_step = 13
2691 23:51:12.721677
2692 23:51:12.721734 ==
2693 23:51:12.725007 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 23:51:12.732046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 23:51:12.732127 ==
2696 23:51:12.732200 RX Vref Scan: 1
2697 23:51:12.732261
2698 23:51:12.735314 Set Vref Range= 32 -> 127
2699 23:51:12.735395
2700 23:51:12.738045 RX Vref 32 -> 127, step: 1
2701 23:51:12.738125
2702 23:51:12.738187 RX Delay -21 -> 252, step: 4
2703 23:51:12.738247
2704 23:51:12.741989 Set Vref, RX VrefLevel [Byte0]: 32
2705 23:51:12.744889 [Byte1]: 32
2706 23:51:12.749217
2707 23:51:12.749296 Set Vref, RX VrefLevel [Byte0]: 33
2708 23:51:12.752669 [Byte1]: 33
2709 23:51:12.756953
2710 23:51:12.757047 Set Vref, RX VrefLevel [Byte0]: 34
2711 23:51:12.761558 [Byte1]: 34
2712 23:51:12.765320
2713 23:51:12.765400 Set Vref, RX VrefLevel [Byte0]: 35
2714 23:51:12.768908 [Byte1]: 35
2715 23:51:12.772874
2716 23:51:12.773013 Set Vref, RX VrefLevel [Byte0]: 36
2717 23:51:12.776479 [Byte1]: 36
2718 23:51:12.781319
2719 23:51:12.781398 Set Vref, RX VrefLevel [Byte0]: 37
2720 23:51:12.785019 [Byte1]: 37
2721 23:51:12.789281
2722 23:51:12.789360 Set Vref, RX VrefLevel [Byte0]: 38
2723 23:51:12.792214 [Byte1]: 38
2724 23:51:12.797207
2725 23:51:12.797287 Set Vref, RX VrefLevel [Byte0]: 39
2726 23:51:12.800578 [Byte1]: 39
2727 23:51:12.804826
2728 23:51:12.808018 Set Vref, RX VrefLevel [Byte0]: 40
2729 23:51:12.811037 [Byte1]: 40
2730 23:51:12.811119
2731 23:51:12.814815 Set Vref, RX VrefLevel [Byte0]: 41
2732 23:51:12.818686 [Byte1]: 41
2733 23:51:12.818766
2734 23:51:12.821257 Set Vref, RX VrefLevel [Byte0]: 42
2735 23:51:12.825281 [Byte1]: 42
2736 23:51:12.829113
2737 23:51:12.829193 Set Vref, RX VrefLevel [Byte0]: 43
2738 23:51:12.832007 [Byte1]: 43
2739 23:51:12.836900
2740 23:51:12.837001 Set Vref, RX VrefLevel [Byte0]: 44
2741 23:51:12.839610 [Byte1]: 44
2742 23:51:12.844244
2743 23:51:12.844324 Set Vref, RX VrefLevel [Byte0]: 45
2744 23:51:12.847571 [Byte1]: 45
2745 23:51:12.852325
2746 23:51:12.852405 Set Vref, RX VrefLevel [Byte0]: 46
2747 23:51:12.855744 [Byte1]: 46
2748 23:51:12.860565
2749 23:51:12.860645 Set Vref, RX VrefLevel [Byte0]: 47
2750 23:51:12.863348 [Byte1]: 47
2751 23:51:12.867908
2752 23:51:12.867987 Set Vref, RX VrefLevel [Byte0]: 48
2753 23:51:12.871387 [Byte1]: 48
2754 23:51:12.876375
2755 23:51:12.876455 Set Vref, RX VrefLevel [Byte0]: 49
2756 23:51:12.879279 [Byte1]: 49
2757 23:51:12.884337
2758 23:51:12.884417 Set Vref, RX VrefLevel [Byte0]: 50
2759 23:51:12.887741 [Byte1]: 50
2760 23:51:12.892073
2761 23:51:12.892152 Set Vref, RX VrefLevel [Byte0]: 51
2762 23:51:12.895468 [Byte1]: 51
2763 23:51:12.900097
2764 23:51:12.900176 Set Vref, RX VrefLevel [Byte0]: 52
2765 23:51:12.903324 [Byte1]: 52
2766 23:51:12.907832
2767 23:51:12.907913 Set Vref, RX VrefLevel [Byte0]: 53
2768 23:51:12.911308 [Byte1]: 53
2769 23:51:12.915930
2770 23:51:12.916010 Set Vref, RX VrefLevel [Byte0]: 54
2771 23:51:12.919629 [Byte1]: 54
2772 23:51:12.923405
2773 23:51:12.923485 Set Vref, RX VrefLevel [Byte0]: 55
2774 23:51:12.926952 [Byte1]: 55
2775 23:51:12.931717
2776 23:51:12.931797 Set Vref, RX VrefLevel [Byte0]: 56
2777 23:51:12.934937 [Byte1]: 56
2778 23:51:12.939564
2779 23:51:12.939644 Set Vref, RX VrefLevel [Byte0]: 57
2780 23:51:12.942725 [Byte1]: 57
2781 23:51:12.947785
2782 23:51:12.947865 Set Vref, RX VrefLevel [Byte0]: 58
2783 23:51:12.950781 [Byte1]: 58
2784 23:51:12.955103
2785 23:51:12.955183 Set Vref, RX VrefLevel [Byte0]: 59
2786 23:51:12.958659 [Byte1]: 59
2787 23:51:12.963594
2788 23:51:12.963674 Set Vref, RX VrefLevel [Byte0]: 60
2789 23:51:12.966835 [Byte1]: 60
2790 23:51:12.971090
2791 23:51:12.971170 Set Vref, RX VrefLevel [Byte0]: 61
2792 23:51:12.974366 [Byte1]: 61
2793 23:51:12.979638
2794 23:51:12.979718 Set Vref, RX VrefLevel [Byte0]: 62
2795 23:51:12.982638 [Byte1]: 62
2796 23:51:12.987135
2797 23:51:12.987218 Set Vref, RX VrefLevel [Byte0]: 63
2798 23:51:12.990306 [Byte1]: 63
2799 23:51:12.994905
2800 23:51:12.994985 Set Vref, RX VrefLevel [Byte0]: 64
2801 23:51:12.998419 [Byte1]: 64
2802 23:51:13.003073
2803 23:51:13.003154 Set Vref, RX VrefLevel [Byte0]: 65
2804 23:51:13.006303 [Byte1]: 65
2805 23:51:13.011238
2806 23:51:13.011318 Set Vref, RX VrefLevel [Byte0]: 66
2807 23:51:13.013911 [Byte1]: 66
2808 23:51:13.018672
2809 23:51:13.018753 Set Vref, RX VrefLevel [Byte0]: 67
2810 23:51:13.022284 [Byte1]: 67
2811 23:51:13.026972
2812 23:51:13.027052 Set Vref, RX VrefLevel [Byte0]: 68
2813 23:51:13.030183 [Byte1]: 68
2814 23:51:13.034872
2815 23:51:13.034952 Set Vref, RX VrefLevel [Byte0]: 69
2816 23:51:13.038076 [Byte1]: 69
2817 23:51:13.042671
2818 23:51:13.042752 Final RX Vref Byte 0 = 53 to rank0
2819 23:51:13.045794 Final RX Vref Byte 1 = 56 to rank0
2820 23:51:13.049604 Final RX Vref Byte 0 = 53 to rank1
2821 23:51:13.052732 Final RX Vref Byte 1 = 56 to rank1==
2822 23:51:13.055995 Dram Type= 6, Freq= 0, CH_0, rank 0
2823 23:51:13.059460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2824 23:51:13.062745 ==
2825 23:51:13.062825 DQS Delay:
2826 23:51:13.062889 DQS0 = 0, DQS1 = 0
2827 23:51:13.065885 DQM Delay:
2828 23:51:13.065965 DQM0 = 115, DQM1 = 106
2829 23:51:13.069671 DQ Delay:
2830 23:51:13.072443 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2831 23:51:13.076047 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2832 23:51:13.079419 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =96
2833 23:51:13.082772 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2834 23:51:13.082854
2835 23:51:13.082917
2836 23:51:13.089198 [DQSOSCAuto] RK0, (LSB)MR18= 0xfded, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
2837 23:51:13.093149 CH0 RK0: MR19=303, MR18=FDED
2838 23:51:13.099608 CH0_RK0: MR19=0x303, MR18=0xFDED, DQSOSC=411, MR23=63, INC=38, DEC=25
2839 23:51:13.099690
2840 23:51:13.102844 ----->DramcWriteLeveling(PI) begin...
2841 23:51:13.102926 ==
2842 23:51:13.106175 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 23:51:13.109444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 23:51:13.109525 ==
2845 23:51:13.112717 Write leveling (Byte 0): 32 => 32
2846 23:51:13.116219 Write leveling (Byte 1): 29 => 29
2847 23:51:13.119298 DramcWriteLeveling(PI) end<-----
2848 23:51:13.119379
2849 23:51:13.119441 ==
2850 23:51:13.123145 Dram Type= 6, Freq= 0, CH_0, rank 1
2851 23:51:13.126439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 23:51:13.129907 ==
2853 23:51:13.129986 [Gating] SW mode calibration
2854 23:51:13.136276 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2855 23:51:13.142892 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2856 23:51:13.146017 0 15 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2857 23:51:13.152864 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2858 23:51:13.156235 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 23:51:13.159661 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 23:51:13.166900 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 23:51:13.169843 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 23:51:13.172989 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2863 23:51:13.176722 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2864 23:51:13.183223 1 0 0 | B1->B0 | 3030 2828 | 1 1 | (1 0) (0 0)
2865 23:51:13.186211 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2866 23:51:13.190357 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 23:51:13.196783 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 23:51:13.200130 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 23:51:13.204411 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 23:51:13.209750 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2871 23:51:13.213739 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2872 23:51:13.216887 1 1 0 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
2873 23:51:13.223372 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2874 23:51:13.227139 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 23:51:13.230294 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 23:51:13.238225 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 23:51:13.240181 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 23:51:13.243303 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 23:51:13.246593 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2880 23:51:13.253505 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2881 23:51:13.256807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2882 23:51:13.260576 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:51:13.266750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:51:13.270295 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:51:13.273596 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:51:13.280235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:51:13.283484 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:51:13.287357 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:51:13.293643 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:51:13.297421 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:51:13.300487 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:51:13.307197 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:51:13.310222 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:51:13.313911 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:51:13.317718 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 23:51:13.323744 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2897 23:51:13.326888 Total UI for P1: 0, mck2ui 16
2898 23:51:13.330246 best dqsien dly found for B0: ( 1, 3, 28)
2899 23:51:13.334152 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 23:51:13.337145 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 23:51:13.340706 Total UI for P1: 0, mck2ui 16
2902 23:51:13.344490 best dqsien dly found for B1: ( 1, 4, 2)
2903 23:51:13.347268 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2904 23:51:13.350657 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2905 23:51:13.350739
2906 23:51:13.358033 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 23:51:13.360696 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2908 23:51:13.360778 [Gating] SW calibration Done
2909 23:51:13.360877 ==
2910 23:51:13.364132 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 23:51:13.370502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 23:51:13.370585 ==
2913 23:51:13.370668 RX Vref Scan: 0
2914 23:51:13.370747
2915 23:51:13.374090 RX Vref 0 -> 0, step: 1
2916 23:51:13.374172
2917 23:51:13.378022 RX Delay -40 -> 252, step: 8
2918 23:51:13.380879 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2919 23:51:13.384570 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2920 23:51:13.387537 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2921 23:51:13.394031 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2922 23:51:13.397941 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2923 23:51:13.400897 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2924 23:51:13.404617 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2925 23:51:13.407389 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2926 23:51:13.410793 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2927 23:51:13.417960 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 23:51:13.421021 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2929 23:51:13.424628 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2930 23:51:13.428216 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2931 23:51:13.431801 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2932 23:51:13.438548 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 23:51:13.441222 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2934 23:51:13.441305 ==
2935 23:51:13.444581 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 23:51:13.447978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 23:51:13.448061 ==
2938 23:51:13.448159 DQS Delay:
2939 23:51:13.451112 DQS0 = 0, DQS1 = 0
2940 23:51:13.451194 DQM Delay:
2941 23:51:13.454936 DQM0 = 115, DQM1 = 108
2942 23:51:13.455018 DQ Delay:
2943 23:51:13.458890 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2944 23:51:13.461264 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2945 23:51:13.464672 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2946 23:51:13.468142 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
2947 23:51:13.471033
2948 23:51:13.471117
2949 23:51:13.471199 ==
2950 23:51:13.474855 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 23:51:13.478218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 23:51:13.478300 ==
2953 23:51:13.478387
2954 23:51:13.478467
2955 23:51:13.481515 TX Vref Scan disable
2956 23:51:13.481597 == TX Byte 0 ==
2957 23:51:13.484572 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2958 23:51:13.491395 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2959 23:51:13.491483 == TX Byte 1 ==
2960 23:51:13.494770 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2961 23:51:13.501605 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2962 23:51:13.501690 ==
2963 23:51:13.504734 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 23:51:13.508289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 23:51:13.508371 ==
2966 23:51:13.520989 TX Vref=22, minBit 0, minWin=25, winSum=420
2967 23:51:13.523627 TX Vref=24, minBit 3, minWin=25, winSum=424
2968 23:51:13.526857 TX Vref=26, minBit 2, minWin=26, winSum=434
2969 23:51:13.530940 TX Vref=28, minBit 2, minWin=26, winSum=433
2970 23:51:13.533742 TX Vref=30, minBit 0, minWin=27, winSum=438
2971 23:51:13.537492 TX Vref=32, minBit 12, minWin=26, winSum=434
2972 23:51:13.544358 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30
2973 23:51:13.544442
2974 23:51:13.547367 Final TX Range 1 Vref 30
2975 23:51:13.547449
2976 23:51:13.547531 ==
2977 23:51:13.550975 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 23:51:13.553932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 23:51:13.554014 ==
2980 23:51:13.554097
2981 23:51:13.554174
2982 23:51:13.557563 TX Vref Scan disable
2983 23:51:13.561093 == TX Byte 0 ==
2984 23:51:13.564011 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2985 23:51:13.567603 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2986 23:51:13.570743 == TX Byte 1 ==
2987 23:51:13.574225 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2988 23:51:13.577953 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2989 23:51:13.578035
2990 23:51:13.580767 [DATLAT]
2991 23:51:13.580848 Freq=1200, CH0 RK1
2992 23:51:13.580947
2993 23:51:13.584326 DATLAT Default: 0xd
2994 23:51:13.584408 0, 0xFFFF, sum = 0
2995 23:51:13.587966 1, 0xFFFF, sum = 0
2996 23:51:13.588052 2, 0xFFFF, sum = 0
2997 23:51:13.591060 3, 0xFFFF, sum = 0
2998 23:51:13.591143 4, 0xFFFF, sum = 0
2999 23:51:13.594525 5, 0xFFFF, sum = 0
3000 23:51:13.594608 6, 0xFFFF, sum = 0
3001 23:51:13.597517 7, 0xFFFF, sum = 0
3002 23:51:13.597600 8, 0xFFFF, sum = 0
3003 23:51:13.600994 9, 0xFFFF, sum = 0
3004 23:51:13.601095 10, 0xFFFF, sum = 0
3005 23:51:13.604097 11, 0xFFFF, sum = 0
3006 23:51:13.604181 12, 0x0, sum = 1
3007 23:51:13.608366 13, 0x0, sum = 2
3008 23:51:13.608453 14, 0x0, sum = 3
3009 23:51:13.611244 15, 0x0, sum = 4
3010 23:51:13.611328 best_step = 13
3011 23:51:13.611410
3012 23:51:13.611487 ==
3013 23:51:13.614165 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 23:51:13.621283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 23:51:13.621365 ==
3016 23:51:13.621448 RX Vref Scan: 0
3017 23:51:13.621526
3018 23:51:13.624311 RX Vref 0 -> 0, step: 1
3019 23:51:13.624393
3020 23:51:13.628105 RX Delay -21 -> 252, step: 4
3021 23:51:13.631631 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3022 23:51:13.634801 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3023 23:51:13.638234 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3024 23:51:13.644447 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3025 23:51:13.648394 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3026 23:51:13.651925 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3027 23:51:13.654197 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3028 23:51:13.658292 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3029 23:51:13.665509 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3030 23:51:13.668060 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3031 23:51:13.671272 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3032 23:51:13.674291 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3033 23:51:13.677786 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3034 23:51:13.685195 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3035 23:51:13.688074 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3036 23:51:13.690908 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3037 23:51:13.690995 ==
3038 23:51:13.694894 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 23:51:13.698330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 23:51:13.698416 ==
3041 23:51:13.701301 DQS Delay:
3042 23:51:13.701413 DQS0 = 0, DQS1 = 0
3043 23:51:13.701515 DQM Delay:
3044 23:51:13.704490 DQM0 = 114, DQM1 = 105
3045 23:51:13.704601 DQ Delay:
3046 23:51:13.708682 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3047 23:51:13.711455 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3048 23:51:13.715036 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3049 23:51:13.721184 DQ12 =110, DQ13 =112, DQ14 =118, DQ15 =114
3050 23:51:13.721275
3051 23:51:13.721360
3052 23:51:13.728392 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3053 23:51:13.731634 CH0 RK1: MR19=403, MR18=2F4
3054 23:51:13.738180 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3055 23:51:13.741927 [RxdqsGatingPostProcess] freq 1200
3056 23:51:13.744603 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 23:51:13.748222 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 23:51:13.751402 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 23:51:13.755044 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 23:51:13.758094 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 23:51:13.761969 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 23:51:13.765340 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 23:51:13.768274 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 23:51:13.771958 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 23:51:13.775649 Pre-setting of DQS Precalculation
3066 23:51:13.778606 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 23:51:13.778703 ==
3068 23:51:13.781749 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 23:51:13.784808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 23:51:13.784918 ==
3071 23:51:13.792103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 23:51:13.798305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3073 23:51:13.806121 [CA 0] Center 38 (9~68) winsize 60
3074 23:51:13.809114 [CA 1] Center 38 (8~68) winsize 61
3075 23:51:13.812796 [CA 2] Center 35 (5~65) winsize 61
3076 23:51:13.816163 [CA 3] Center 34 (4~65) winsize 62
3077 23:51:13.819186 [CA 4] Center 34 (4~65) winsize 62
3078 23:51:13.823169 [CA 5] Center 34 (4~64) winsize 61
3079 23:51:13.823256
3080 23:51:13.825949 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3081 23:51:13.826065
3082 23:51:13.829359 [CATrainingPosCal] consider 1 rank data
3083 23:51:13.833474 u2DelayCellTimex100 = 270/100 ps
3084 23:51:13.836615 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3085 23:51:13.839492 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3086 23:51:13.843092 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3087 23:51:13.850089 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3088 23:51:13.853682 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3089 23:51:13.856698 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3090 23:51:13.856791
3091 23:51:13.859556 CA PerBit enable=1, Macro0, CA PI delay=34
3092 23:51:13.859637
3093 23:51:13.863380 [CBTSetCACLKResult] CA Dly = 34
3094 23:51:13.863461 CS Dly: 5 (0~36)
3095 23:51:13.863525 ==
3096 23:51:13.866459 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 23:51:13.873158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 23:51:13.873240 ==
3099 23:51:13.876723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 23:51:13.883175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3101 23:51:13.892173 [CA 0] Center 38 (8~68) winsize 61
3102 23:51:13.895150 [CA 1] Center 38 (9~68) winsize 60
3103 23:51:13.898251 [CA 2] Center 34 (4~65) winsize 62
3104 23:51:13.902037 [CA 3] Center 34 (3~65) winsize 63
3105 23:51:13.905098 [CA 4] Center 34 (4~65) winsize 62
3106 23:51:13.908853 [CA 5] Center 33 (3~63) winsize 61
3107 23:51:13.908958
3108 23:51:13.911720 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3109 23:51:13.911800
3110 23:51:13.915048 [CATrainingPosCal] consider 2 rank data
3111 23:51:13.918621 u2DelayCellTimex100 = 270/100 ps
3112 23:51:13.922279 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3113 23:51:13.925994 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3114 23:51:13.928859 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3115 23:51:13.935877 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3116 23:51:13.938459 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3117 23:51:13.942018 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3118 23:51:13.942098
3119 23:51:13.944995 CA PerBit enable=1, Macro0, CA PI delay=33
3120 23:51:13.945076
3121 23:51:13.948623 [CBTSetCACLKResult] CA Dly = 33
3122 23:51:13.948703 CS Dly: 7 (0~40)
3123 23:51:13.948765
3124 23:51:13.951788 ----->DramcWriteLeveling(PI) begin...
3125 23:51:13.951869 ==
3126 23:51:13.955221 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 23:51:13.962315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 23:51:13.962397 ==
3129 23:51:13.965294 Write leveling (Byte 0): 26 => 26
3130 23:51:13.968526 Write leveling (Byte 1): 29 => 29
3131 23:51:13.968607 DramcWriteLeveling(PI) end<-----
3132 23:51:13.968691
3133 23:51:13.972167 ==
3134 23:51:13.972246 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 23:51:13.979102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 23:51:13.979185 ==
3137 23:51:13.982167 [Gating] SW mode calibration
3138 23:51:13.988847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 23:51:13.992087 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 23:51:13.999274 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3141 23:51:14.002265 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 23:51:14.005908 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3143 23:51:14.009347 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 23:51:14.015752 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 23:51:14.018950 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 23:51:14.022355 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3147 23:51:14.029768 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3148 23:51:14.033012 1 0 0 | B1->B0 | 2323 2b2b | 0 1 | (1 0) (1 0)
3149 23:51:14.036053 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 23:51:14.042492 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3151 23:51:14.045691 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 23:51:14.049620 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 23:51:14.056277 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 23:51:14.059039 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 23:51:14.062833 1 0 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3156 23:51:14.069302 1 1 0 | B1->B0 | 4141 2f2f | 1 0 | (0 0) (0 0)
3157 23:51:14.073521 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 23:51:14.075978 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 23:51:14.080018 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 23:51:14.086046 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 23:51:14.089438 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 23:51:14.092538 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 23:51:14.099543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3164 23:51:14.102915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3165 23:51:14.106405 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:51:14.113354 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:51:14.116470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:51:14.120063 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:51:14.126224 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:51:14.129566 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:51:14.133045 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:51:14.139647 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:51:14.143256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:51:14.146359 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:51:14.149937 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:51:14.156719 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:51:14.160765 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:51:14.163285 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:51:14.169889 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3180 23:51:14.173566 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3181 23:51:14.176645 Total UI for P1: 0, mck2ui 16
3182 23:51:14.180155 best dqsien dly found for B1: ( 1, 3, 30)
3183 23:51:14.183890 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 23:51:14.186985 Total UI for P1: 0, mck2ui 16
3185 23:51:14.189813 best dqsien dly found for B0: ( 1, 3, 30)
3186 23:51:14.193275 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3187 23:51:14.196693 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3188 23:51:14.196776
3189 23:51:14.199895 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3190 23:51:14.206802 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3191 23:51:14.206888 [Gating] SW calibration Done
3192 23:51:14.206955 ==
3193 23:51:14.209991 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 23:51:14.217614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 23:51:14.217697 ==
3196 23:51:14.217761 RX Vref Scan: 0
3197 23:51:14.217821
3198 23:51:14.220386 RX Vref 0 -> 0, step: 1
3199 23:51:14.220466
3200 23:51:14.223564 RX Delay -40 -> 252, step: 8
3201 23:51:14.226797 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3202 23:51:14.230435 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3203 23:51:14.233672 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3204 23:51:14.236906 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3205 23:51:14.243434 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3206 23:51:14.247207 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3207 23:51:14.250068 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3208 23:51:14.253820 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3209 23:51:14.257229 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3210 23:51:14.260476 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3211 23:51:14.267962 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3212 23:51:14.270447 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3213 23:51:14.274027 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3214 23:51:14.277314 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3215 23:51:14.284384 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3216 23:51:14.288135 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3217 23:51:14.288217 ==
3218 23:51:14.290852 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 23:51:14.294107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 23:51:14.294188 ==
3221 23:51:14.294252 DQS Delay:
3222 23:51:14.297338 DQS0 = 0, DQS1 = 0
3223 23:51:14.297418 DQM Delay:
3224 23:51:14.300787 DQM0 = 116, DQM1 = 109
3225 23:51:14.300868 DQ Delay:
3226 23:51:14.304292 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3227 23:51:14.307765 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3228 23:51:14.310702 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3229 23:51:14.313929 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3230 23:51:14.314001
3231 23:51:14.314062
3232 23:51:14.318001 ==
3233 23:51:14.318072 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 23:51:14.324441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 23:51:14.324513 ==
3236 23:51:14.324573
3237 23:51:14.324629
3238 23:51:14.327637 TX Vref Scan disable
3239 23:51:14.327711 == TX Byte 0 ==
3240 23:51:14.331134 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3241 23:51:14.338219 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3242 23:51:14.338298 == TX Byte 1 ==
3243 23:51:14.341304 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3244 23:51:14.347788 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3245 23:51:14.347859 ==
3246 23:51:14.351267 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 23:51:14.354440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 23:51:14.354520 ==
3249 23:51:14.366378 TX Vref=22, minBit 3, minWin=24, winSum=411
3250 23:51:14.369407 TX Vref=24, minBit 0, minWin=26, winSum=417
3251 23:51:14.372913 TX Vref=26, minBit 0, minWin=26, winSum=425
3252 23:51:14.376624 TX Vref=28, minBit 0, minWin=26, winSum=428
3253 23:51:14.379838 TX Vref=30, minBit 3, minWin=26, winSum=431
3254 23:51:14.382967 TX Vref=32, minBit 2, minWin=26, winSum=431
3255 23:51:14.389682 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 30
3256 23:51:14.389767
3257 23:51:14.392961 Final TX Range 1 Vref 30
3258 23:51:14.393149
3259 23:51:14.393220 ==
3260 23:51:14.396083 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 23:51:14.399640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 23:51:14.399723 ==
3263 23:51:14.399788
3264 23:51:14.399846
3265 23:51:14.402595 TX Vref Scan disable
3266 23:51:14.406846 == TX Byte 0 ==
3267 23:51:14.409814 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 23:51:14.413585 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 23:51:14.416252 == TX Byte 1 ==
3270 23:51:14.419387 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3271 23:51:14.422859 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3272 23:51:14.422939
3273 23:51:14.426130 [DATLAT]
3274 23:51:14.426210 Freq=1200, CH1 RK0
3275 23:51:14.426273
3276 23:51:14.430138 DATLAT Default: 0xd
3277 23:51:14.430218 0, 0xFFFF, sum = 0
3278 23:51:14.432924 1, 0xFFFF, sum = 0
3279 23:51:14.433043 2, 0xFFFF, sum = 0
3280 23:51:14.436665 3, 0xFFFF, sum = 0
3281 23:51:14.436746 4, 0xFFFF, sum = 0
3282 23:51:14.440141 5, 0xFFFF, sum = 0
3283 23:51:14.440223 6, 0xFFFF, sum = 0
3284 23:51:14.443382 7, 0xFFFF, sum = 0
3285 23:51:14.443463 8, 0xFFFF, sum = 0
3286 23:51:14.446230 9, 0xFFFF, sum = 0
3287 23:51:14.446312 10, 0xFFFF, sum = 0
3288 23:51:14.449715 11, 0xFFFF, sum = 0
3289 23:51:14.449797 12, 0x0, sum = 1
3290 23:51:14.453620 13, 0x0, sum = 2
3291 23:51:14.453706 14, 0x0, sum = 3
3292 23:51:14.456580 15, 0x0, sum = 4
3293 23:51:14.456660 best_step = 13
3294 23:51:14.456723
3295 23:51:14.456781 ==
3296 23:51:14.460732 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 23:51:14.466718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 23:51:14.466798 ==
3299 23:51:14.466861 RX Vref Scan: 1
3300 23:51:14.466918
3301 23:51:14.470248 Set Vref Range= 32 -> 127
3302 23:51:14.470328
3303 23:51:14.473568 RX Vref 32 -> 127, step: 1
3304 23:51:14.473657
3305 23:51:14.473721 RX Delay -21 -> 252, step: 4
3306 23:51:14.473780
3307 23:51:14.476454 Set Vref, RX VrefLevel [Byte0]: 32
3308 23:51:14.480455 [Byte1]: 32
3309 23:51:14.484398
3310 23:51:14.484477 Set Vref, RX VrefLevel [Byte0]: 33
3311 23:51:14.487401 [Byte1]: 33
3312 23:51:14.492242
3313 23:51:14.492324 Set Vref, RX VrefLevel [Byte0]: 34
3314 23:51:14.495344 [Byte1]: 34
3315 23:51:14.500370
3316 23:51:14.500449 Set Vref, RX VrefLevel [Byte0]: 35
3317 23:51:14.503969 [Byte1]: 35
3318 23:51:14.508224
3319 23:51:14.508304 Set Vref, RX VrefLevel [Byte0]: 36
3320 23:51:14.511312 [Byte1]: 36
3321 23:51:14.515744
3322 23:51:14.515824 Set Vref, RX VrefLevel [Byte0]: 37
3323 23:51:14.519542 [Byte1]: 37
3324 23:51:14.524344
3325 23:51:14.524423 Set Vref, RX VrefLevel [Byte0]: 38
3326 23:51:14.527238 [Byte1]: 38
3327 23:51:14.531894
3328 23:51:14.531973 Set Vref, RX VrefLevel [Byte0]: 39
3329 23:51:14.535237 [Byte1]: 39
3330 23:51:14.540071
3331 23:51:14.540153 Set Vref, RX VrefLevel [Byte0]: 40
3332 23:51:14.543168 [Byte1]: 40
3333 23:51:14.547443
3334 23:51:14.547522 Set Vref, RX VrefLevel [Byte0]: 41
3335 23:51:14.551128 [Byte1]: 41
3336 23:51:14.555645
3337 23:51:14.555726 Set Vref, RX VrefLevel [Byte0]: 42
3338 23:51:14.558903 [Byte1]: 42
3339 23:51:14.564465
3340 23:51:14.564544 Set Vref, RX VrefLevel [Byte0]: 43
3341 23:51:14.566642 [Byte1]: 43
3342 23:51:14.571638
3343 23:51:14.571718 Set Vref, RX VrefLevel [Byte0]: 44
3344 23:51:14.574583 [Byte1]: 44
3345 23:51:14.579597
3346 23:51:14.579676 Set Vref, RX VrefLevel [Byte0]: 45
3347 23:51:14.582519 [Byte1]: 45
3348 23:51:14.587630
3349 23:51:14.587710 Set Vref, RX VrefLevel [Byte0]: 46
3350 23:51:14.590755 [Byte1]: 46
3351 23:51:14.595122
3352 23:51:14.595201 Set Vref, RX VrefLevel [Byte0]: 47
3353 23:51:14.599021 [Byte1]: 47
3354 23:51:14.603201
3355 23:51:14.603280 Set Vref, RX VrefLevel [Byte0]: 48
3356 23:51:14.606316 [Byte1]: 48
3357 23:51:14.611615
3358 23:51:14.611694 Set Vref, RX VrefLevel [Byte0]: 49
3359 23:51:14.614260 [Byte1]: 49
3360 23:51:14.619534
3361 23:51:14.619614 Set Vref, RX VrefLevel [Byte0]: 50
3362 23:51:14.622439 [Byte1]: 50
3363 23:51:14.627114
3364 23:51:14.627193 Set Vref, RX VrefLevel [Byte0]: 51
3365 23:51:14.630359 [Byte1]: 51
3366 23:51:14.634896
3367 23:51:14.634976 Set Vref, RX VrefLevel [Byte0]: 52
3368 23:51:14.638076 [Byte1]: 52
3369 23:51:14.642685
3370 23:51:14.642765 Set Vref, RX VrefLevel [Byte0]: 53
3371 23:51:14.646423 [Byte1]: 53
3372 23:51:14.650847
3373 23:51:14.650929 Set Vref, RX VrefLevel [Byte0]: 54
3374 23:51:14.654200 [Byte1]: 54
3375 23:51:14.658392
3376 23:51:14.658471 Set Vref, RX VrefLevel [Byte0]: 55
3377 23:51:14.662199 [Byte1]: 55
3378 23:51:14.666308
3379 23:51:14.666386 Set Vref, RX VrefLevel [Byte0]: 56
3380 23:51:14.669833 [Byte1]: 56
3381 23:51:14.674703
3382 23:51:14.674785 Set Vref, RX VrefLevel [Byte0]: 57
3383 23:51:14.678144 [Byte1]: 57
3384 23:51:14.682181
3385 23:51:14.682263 Set Vref, RX VrefLevel [Byte0]: 58
3386 23:51:14.685457 [Byte1]: 58
3387 23:51:14.690687
3388 23:51:14.690783 Set Vref, RX VrefLevel [Byte0]: 59
3389 23:51:14.693742 [Byte1]: 59
3390 23:51:14.698019
3391 23:51:14.698101 Set Vref, RX VrefLevel [Byte0]: 60
3392 23:51:14.701213 [Byte1]: 60
3393 23:51:14.707043
3394 23:51:14.707129 Set Vref, RX VrefLevel [Byte0]: 61
3395 23:51:14.709779 [Byte1]: 61
3396 23:51:14.713835
3397 23:51:14.713918 Set Vref, RX VrefLevel [Byte0]: 62
3398 23:51:14.717436 [Byte1]: 62
3399 23:51:14.721929
3400 23:51:14.722010 Set Vref, RX VrefLevel [Byte0]: 63
3401 23:51:14.726006 [Byte1]: 63
3402 23:51:14.729785
3403 23:51:14.729871 Set Vref, RX VrefLevel [Byte0]: 64
3404 23:51:14.732851 [Byte1]: 64
3405 23:51:14.737919
3406 23:51:14.738001 Set Vref, RX VrefLevel [Byte0]: 65
3407 23:51:14.740789 [Byte1]: 65
3408 23:51:14.745315
3409 23:51:14.745397 Set Vref, RX VrefLevel [Byte0]: 66
3410 23:51:14.748921 [Byte1]: 66
3411 23:51:14.753871
3412 23:51:14.753953 Set Vref, RX VrefLevel [Byte0]: 67
3413 23:51:14.757029 [Byte1]: 67
3414 23:51:14.761454
3415 23:51:14.761534 Set Vref, RX VrefLevel [Byte0]: 68
3416 23:51:14.764901 [Byte1]: 68
3417 23:51:14.769226
3418 23:51:14.769307 Set Vref, RX VrefLevel [Byte0]: 69
3419 23:51:14.772703 [Byte1]: 69
3420 23:51:14.777651
3421 23:51:14.777732 Set Vref, RX VrefLevel [Byte0]: 70
3422 23:51:14.780667 [Byte1]: 70
3423 23:51:14.785084
3424 23:51:14.785163 Final RX Vref Byte 0 = 56 to rank0
3425 23:51:14.788897 Final RX Vref Byte 1 = 53 to rank0
3426 23:51:14.791962 Final RX Vref Byte 0 = 56 to rank1
3427 23:51:14.795684 Final RX Vref Byte 1 = 53 to rank1==
3428 23:51:14.798878 Dram Type= 6, Freq= 0, CH_1, rank 0
3429 23:51:14.801860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 23:51:14.805721 ==
3431 23:51:14.805803 DQS Delay:
3432 23:51:14.805885 DQS0 = 0, DQS1 = 0
3433 23:51:14.808575 DQM Delay:
3434 23:51:14.808656 DQM0 = 115, DQM1 = 110
3435 23:51:14.812499 DQ Delay:
3436 23:51:14.815547 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3437 23:51:14.819006 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3438 23:51:14.822222 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3439 23:51:14.825242 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3440 23:51:14.825325
3441 23:51:14.825406
3442 23:51:14.833286 [DQSOSCAuto] RK0, (LSB)MR18= 0xfadf, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
3443 23:51:14.836023 CH1 RK0: MR19=303, MR18=FADF
3444 23:51:14.842384 CH1_RK0: MR19=0x303, MR18=0xFADF, DQSOSC=412, MR23=63, INC=38, DEC=25
3445 23:51:14.842467
3446 23:51:14.846063 ----->DramcWriteLeveling(PI) begin...
3447 23:51:14.846152 ==
3448 23:51:14.848943 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 23:51:14.852053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 23:51:14.852135 ==
3451 23:51:14.855931 Write leveling (Byte 0): 27 => 27
3452 23:51:14.858979 Write leveling (Byte 1): 27 => 27
3453 23:51:14.862234 DramcWriteLeveling(PI) end<-----
3454 23:51:14.862317
3455 23:51:14.862399 ==
3456 23:51:14.865861 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 23:51:14.869113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 23:51:14.869196 ==
3459 23:51:14.872894 [Gating] SW mode calibration
3460 23:51:14.879208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3461 23:51:14.885864 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3462 23:51:14.889663 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3463 23:51:14.896517 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 23:51:14.899335 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 23:51:14.903559 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 23:51:14.906042 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 23:51:14.913263 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3468 23:51:14.916315 0 15 24 | B1->B0 | 3333 2626 | 0 0 | (0 1) (1 0)
3469 23:51:14.919235 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3470 23:51:14.926351 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 23:51:14.929512 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 23:51:14.932926 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 23:51:14.939142 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 23:51:14.942370 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 23:51:14.946230 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 23:51:14.952542 1 0 24 | B1->B0 | 2525 4040 | 1 0 | (0 0) (0 0)
3477 23:51:14.955710 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3478 23:51:14.959349 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:51:14.965591 1 1 4 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
3480 23:51:14.968866 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 23:51:14.971996 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 23:51:14.979387 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 23:51:14.982290 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 23:51:14.985650 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3485 23:51:14.992761 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3486 23:51:14.995612 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:51:14.998894 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:51:15.005422 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:51:15.009400 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:51:15.012640 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:51:15.019802 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:51:15.021840 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:51:15.025463 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:51:15.032184 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:51:15.035800 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:51:15.038991 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:51:15.045729 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:51:15.049056 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 23:51:15.051863 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 23:51:15.055645 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3501 23:51:15.062054 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3502 23:51:15.065589 Total UI for P1: 0, mck2ui 16
3503 23:51:15.069049 best dqsien dly found for B0: ( 1, 3, 22)
3504 23:51:15.072046 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 23:51:15.075555 Total UI for P1: 0, mck2ui 16
3506 23:51:15.079187 best dqsien dly found for B1: ( 1, 3, 26)
3507 23:51:15.082465 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3508 23:51:15.085771 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3509 23:51:15.085855
3510 23:51:15.088547 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3511 23:51:15.095004 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3512 23:51:15.095087 [Gating] SW calibration Done
3513 23:51:15.095170 ==
3514 23:51:15.098464 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 23:51:15.105117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 23:51:15.105199 ==
3517 23:51:15.105284 RX Vref Scan: 0
3518 23:51:15.105362
3519 23:51:15.109261 RX Vref 0 -> 0, step: 1
3520 23:51:15.109357
3521 23:51:15.111944 RX Delay -40 -> 252, step: 8
3522 23:51:15.114978 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3523 23:51:15.118818 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3524 23:51:15.123669 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3525 23:51:15.124992 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3526 23:51:15.131809 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3527 23:51:15.135193 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3528 23:51:15.138738 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3529 23:51:15.142608 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3530 23:51:15.145447 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3531 23:51:15.151835 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3532 23:51:15.155078 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3533 23:51:15.158305 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3534 23:51:15.161917 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3535 23:51:15.165457 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3536 23:51:15.171712 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3537 23:51:15.174883 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3538 23:51:15.174970 ==
3539 23:51:15.179039 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 23:51:15.181973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 23:51:15.182060 ==
3542 23:51:15.185540 DQS Delay:
3543 23:51:15.185623 DQS0 = 0, DQS1 = 0
3544 23:51:15.185707 DQM Delay:
3545 23:51:15.189183 DQM0 = 113, DQM1 = 110
3546 23:51:15.189267 DQ Delay:
3547 23:51:15.192412 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3548 23:51:15.195808 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3549 23:51:15.199100 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3550 23:51:15.202185 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3551 23:51:15.205481
3552 23:51:15.205564
3553 23:51:15.205647 ==
3554 23:51:15.209281 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 23:51:15.212188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 23:51:15.212271 ==
3557 23:51:15.212355
3558 23:51:15.212432
3559 23:51:15.215597 TX Vref Scan disable
3560 23:51:15.215679 == TX Byte 0 ==
3561 23:51:15.222181 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3562 23:51:15.225486 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3563 23:51:15.225569 == TX Byte 1 ==
3564 23:51:15.232112 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 23:51:15.235461 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 23:51:15.235544 ==
3567 23:51:15.238949 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 23:51:15.242360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 23:51:15.242445 ==
3570 23:51:15.253812 TX Vref=22, minBit 0, minWin=25, winSum=410
3571 23:51:15.257539 TX Vref=24, minBit 1, minWin=25, winSum=423
3572 23:51:15.261329 TX Vref=26, minBit 1, minWin=26, winSum=425
3573 23:51:15.264925 TX Vref=28, minBit 2, minWin=26, winSum=429
3574 23:51:15.267480 TX Vref=30, minBit 2, minWin=26, winSum=432
3575 23:51:15.274045 TX Vref=32, minBit 2, minWin=26, winSum=429
3576 23:51:15.277985 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
3577 23:51:15.278069
3578 23:51:15.281000 Final TX Range 1 Vref 30
3579 23:51:15.281096
3580 23:51:15.281180 ==
3581 23:51:15.284255 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 23:51:15.287409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 23:51:15.287492 ==
3584 23:51:15.287574
3585 23:51:15.291455
3586 23:51:15.291538 TX Vref Scan disable
3587 23:51:15.294448 == TX Byte 0 ==
3588 23:51:15.297338 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3589 23:51:15.300650 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3590 23:51:15.304646 == TX Byte 1 ==
3591 23:51:15.308219 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 23:51:15.311383 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 23:51:15.311467
3594 23:51:15.314347 [DATLAT]
3595 23:51:15.314431 Freq=1200, CH1 RK1
3596 23:51:15.314515
3597 23:51:15.317742 DATLAT Default: 0xd
3598 23:51:15.317824 0, 0xFFFF, sum = 0
3599 23:51:15.320665 1, 0xFFFF, sum = 0
3600 23:51:15.320780 2, 0xFFFF, sum = 0
3601 23:51:15.323967 3, 0xFFFF, sum = 0
3602 23:51:15.324088 4, 0xFFFF, sum = 0
3603 23:51:15.327726 5, 0xFFFF, sum = 0
3604 23:51:15.327816 6, 0xFFFF, sum = 0
3605 23:51:15.331183 7, 0xFFFF, sum = 0
3606 23:51:15.334043 8, 0xFFFF, sum = 0
3607 23:51:15.334127 9, 0xFFFF, sum = 0
3608 23:51:15.337485 10, 0xFFFF, sum = 0
3609 23:51:15.337569 11, 0xFFFF, sum = 0
3610 23:51:15.340796 12, 0x0, sum = 1
3611 23:51:15.340880 13, 0x0, sum = 2
3612 23:51:15.344072 14, 0x0, sum = 3
3613 23:51:15.344155 15, 0x0, sum = 4
3614 23:51:15.344241 best_step = 13
3615 23:51:15.344319
3616 23:51:15.347414 ==
3617 23:51:15.351363 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 23:51:15.354123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 23:51:15.354205 ==
3620 23:51:15.354268 RX Vref Scan: 0
3621 23:51:15.354327
3622 23:51:15.357909 RX Vref 0 -> 0, step: 1
3623 23:51:15.357989
3624 23:51:15.361230 RX Delay -21 -> 252, step: 4
3625 23:51:15.364801 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3626 23:51:15.371318 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3627 23:51:15.373954 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3628 23:51:15.377311 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3629 23:51:15.380572 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3630 23:51:15.384812 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3631 23:51:15.387415 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3632 23:51:15.394200 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3633 23:51:15.397345 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3634 23:51:15.400879 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3635 23:51:15.404160 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3636 23:51:15.407510 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3637 23:51:15.414350 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3638 23:51:15.417445 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3639 23:51:15.420792 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3640 23:51:15.424055 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3641 23:51:15.424140 ==
3642 23:51:15.428315 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 23:51:15.430758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 23:51:15.434334 ==
3645 23:51:15.434418 DQS Delay:
3646 23:51:15.434505 DQS0 = 0, DQS1 = 0
3647 23:51:15.437642 DQM Delay:
3648 23:51:15.437724 DQM0 = 113, DQM1 = 109
3649 23:51:15.440865 DQ Delay:
3650 23:51:15.444412 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3651 23:51:15.448068 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3652 23:51:15.451162 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3653 23:51:15.454393 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3654 23:51:15.454470
3655 23:51:15.454551
3656 23:51:15.461176 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3657 23:51:15.464852 CH1 RK1: MR19=303, MR18=F6FD
3658 23:51:15.470844 CH1_RK1: MR19=0x303, MR18=0xF6FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3659 23:51:15.474527 [RxdqsGatingPostProcess] freq 1200
3660 23:51:15.480988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3661 23:51:15.484191 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 23:51:15.484275 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 23:51:15.488176 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 23:51:15.491310 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 23:51:15.494815 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 23:51:15.497674 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 23:51:15.500798 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 23:51:15.503956 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 23:51:15.507727 Pre-setting of DQS Precalculation
3670 23:51:15.514072 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3671 23:51:15.520642 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3672 23:51:15.527536 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3673 23:51:15.527624
3674 23:51:15.527708
3675 23:51:15.530645 [Calibration Summary] 2400 Mbps
3676 23:51:15.530728 CH 0, Rank 0
3677 23:51:15.534258 SW Impedance : PASS
3678 23:51:15.537456 DUTY Scan : NO K
3679 23:51:15.537539 ZQ Calibration : PASS
3680 23:51:15.541488 Jitter Meter : NO K
3681 23:51:15.541571 CBT Training : PASS
3682 23:51:15.543879 Write leveling : PASS
3683 23:51:15.548069 RX DQS gating : PASS
3684 23:51:15.548151 RX DQ/DQS(RDDQC) : PASS
3685 23:51:15.552228 TX DQ/DQS : PASS
3686 23:51:15.554120 RX DATLAT : PASS
3687 23:51:15.554203 RX DQ/DQS(Engine): PASS
3688 23:51:15.557435 TX OE : NO K
3689 23:51:15.557518 All Pass.
3690 23:51:15.557601
3691 23:51:15.560652 CH 0, Rank 1
3692 23:51:15.560735 SW Impedance : PASS
3693 23:51:15.564636 DUTY Scan : NO K
3694 23:51:15.567273 ZQ Calibration : PASS
3695 23:51:15.567356 Jitter Meter : NO K
3696 23:51:15.570710 CBT Training : PASS
3697 23:51:15.574572 Write leveling : PASS
3698 23:51:15.574656 RX DQS gating : PASS
3699 23:51:15.577659 RX DQ/DQS(RDDQC) : PASS
3700 23:51:15.581308 TX DQ/DQS : PASS
3701 23:51:15.581392 RX DATLAT : PASS
3702 23:51:15.584144 RX DQ/DQS(Engine): PASS
3703 23:51:15.587390 TX OE : NO K
3704 23:51:15.587473 All Pass.
3705 23:51:15.587556
3706 23:51:15.587634 CH 1, Rank 0
3707 23:51:15.590598 SW Impedance : PASS
3708 23:51:15.594462 DUTY Scan : NO K
3709 23:51:15.594547 ZQ Calibration : PASS
3710 23:51:15.597239 Jitter Meter : NO K
3711 23:51:15.597321 CBT Training : PASS
3712 23:51:15.600886 Write leveling : PASS
3713 23:51:15.604272 RX DQS gating : PASS
3714 23:51:15.604355 RX DQ/DQS(RDDQC) : PASS
3715 23:51:15.607388 TX DQ/DQS : PASS
3716 23:51:15.613153 RX DATLAT : PASS
3717 23:51:15.613284 RX DQ/DQS(Engine): PASS
3718 23:51:15.614018 TX OE : NO K
3719 23:51:15.614101 All Pass.
3720 23:51:15.614184
3721 23:51:15.618044 CH 1, Rank 1
3722 23:51:15.618125 SW Impedance : PASS
3723 23:51:15.620709 DUTY Scan : NO K
3724 23:51:15.623986 ZQ Calibration : PASS
3725 23:51:15.624080 Jitter Meter : NO K
3726 23:51:15.627629 CBT Training : PASS
3727 23:51:15.627713 Write leveling : PASS
3728 23:51:15.630880 RX DQS gating : PASS
3729 23:51:15.634823 RX DQ/DQS(RDDQC) : PASS
3730 23:51:15.634904 TX DQ/DQS : PASS
3731 23:51:15.637522 RX DATLAT : PASS
3732 23:51:15.641209 RX DQ/DQS(Engine): PASS
3733 23:51:15.641289 TX OE : NO K
3734 23:51:15.644570 All Pass.
3735 23:51:15.644651
3736 23:51:15.644713 DramC Write-DBI off
3737 23:51:15.647520 PER_BANK_REFRESH: Hybrid Mode
3738 23:51:15.647600 TX_TRACKING: ON
3739 23:51:15.657426 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3740 23:51:15.660801 [FAST_K] Save calibration result to emmc
3741 23:51:15.664314 dramc_set_vcore_voltage set vcore to 650000
3742 23:51:15.667891 Read voltage for 600, 5
3743 23:51:15.668010 Vio18 = 0
3744 23:51:15.670762 Vcore = 650000
3745 23:51:15.670870 Vdram = 0
3746 23:51:15.670968 Vddq = 0
3747 23:51:15.674435 Vmddr = 0
3748 23:51:15.677614 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3749 23:51:15.684422 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3750 23:51:15.684535 MEM_TYPE=3, freq_sel=19
3751 23:51:15.687794 sv_algorithm_assistance_LP4_1600
3752 23:51:15.691144 ============ PULL DRAM RESETB DOWN ============
3753 23:51:15.697276 ========== PULL DRAM RESETB DOWN end =========
3754 23:51:15.700711 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3755 23:51:15.704302 ===================================
3756 23:51:15.707662 LPDDR4 DRAM CONFIGURATION
3757 23:51:15.711055 ===================================
3758 23:51:15.711165 EX_ROW_EN[0] = 0x0
3759 23:51:15.714087 EX_ROW_EN[1] = 0x0
3760 23:51:15.714196 LP4Y_EN = 0x0
3761 23:51:15.717974 WORK_FSP = 0x0
3762 23:51:15.718080 WL = 0x2
3763 23:51:15.720903 RL = 0x2
3764 23:51:15.724410 BL = 0x2
3765 23:51:15.724521 RPST = 0x0
3766 23:51:15.727898 RD_PRE = 0x0
3767 23:51:15.728006 WR_PRE = 0x1
3768 23:51:15.731001 WR_PST = 0x0
3769 23:51:15.731108 DBI_WR = 0x0
3770 23:51:15.734287 DBI_RD = 0x0
3771 23:51:15.734396 OTF = 0x1
3772 23:51:15.738448 ===================================
3773 23:51:15.741339 ===================================
3774 23:51:15.741451 ANA top config
3775 23:51:15.745147 ===================================
3776 23:51:15.748114 DLL_ASYNC_EN = 0
3777 23:51:15.751092 ALL_SLAVE_EN = 1
3778 23:51:15.755163 NEW_RANK_MODE = 1
3779 23:51:15.758008 DLL_IDLE_MODE = 1
3780 23:51:15.758127 LP45_APHY_COMB_EN = 1
3781 23:51:15.761781 TX_ODT_DIS = 1
3782 23:51:15.764556 NEW_8X_MODE = 1
3783 23:51:15.767821 ===================================
3784 23:51:15.771724 ===================================
3785 23:51:15.774921 data_rate = 1200
3786 23:51:15.777997 CKR = 1
3787 23:51:15.778104 DQ_P2S_RATIO = 8
3788 23:51:15.781166 ===================================
3789 23:51:15.784674 CA_P2S_RATIO = 8
3790 23:51:15.788039 DQ_CA_OPEN = 0
3791 23:51:15.791381 DQ_SEMI_OPEN = 0
3792 23:51:15.794827 CA_SEMI_OPEN = 0
3793 23:51:15.798078 CA_FULL_RATE = 0
3794 23:51:15.798192 DQ_CKDIV4_EN = 1
3795 23:51:15.801265 CA_CKDIV4_EN = 1
3796 23:51:15.804384 CA_PREDIV_EN = 0
3797 23:51:15.808525 PH8_DLY = 0
3798 23:51:15.811147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3799 23:51:15.811220 DQ_AAMCK_DIV = 4
3800 23:51:15.814972 CA_AAMCK_DIV = 4
3801 23:51:15.818133 CA_ADMCK_DIV = 4
3802 23:51:15.821333 DQ_TRACK_CA_EN = 0
3803 23:51:15.825272 CA_PICK = 600
3804 23:51:15.827945 CA_MCKIO = 600
3805 23:51:15.831700 MCKIO_SEMI = 0
3806 23:51:15.831772 PLL_FREQ = 2288
3807 23:51:15.834383 DQ_UI_PI_RATIO = 32
3808 23:51:15.837795 CA_UI_PI_RATIO = 0
3809 23:51:15.841081 ===================================
3810 23:51:15.844491 ===================================
3811 23:51:15.847908 memory_type:LPDDR4
3812 23:51:15.847983 GP_NUM : 10
3813 23:51:15.851064 SRAM_EN : 1
3814 23:51:15.855334 MD32_EN : 0
3815 23:51:15.858266 ===================================
3816 23:51:15.858367 [ANA_INIT] >>>>>>>>>>>>>>
3817 23:51:15.861773 <<<<<< [CONFIGURE PHASE]: ANA_TX
3818 23:51:15.865076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3819 23:51:15.868309 ===================================
3820 23:51:15.871523 data_rate = 1200,PCW = 0X5800
3821 23:51:15.875028 ===================================
3822 23:51:15.878335 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3823 23:51:15.884846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 23:51:15.888230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 23:51:15.894789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3826 23:51:15.898006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3827 23:51:15.901803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3828 23:51:15.901913 [ANA_INIT] flow start
3829 23:51:15.904466 [ANA_INIT] PLL >>>>>>>>
3830 23:51:15.908129 [ANA_INIT] PLL <<<<<<<<
3831 23:51:15.908235 [ANA_INIT] MIDPI >>>>>>>>
3832 23:51:15.911116 [ANA_INIT] MIDPI <<<<<<<<
3833 23:51:15.914699 [ANA_INIT] DLL >>>>>>>>
3834 23:51:15.914805 [ANA_INIT] flow end
3835 23:51:15.921331 ============ LP4 DIFF to SE enter ============
3836 23:51:15.924536 ============ LP4 DIFF to SE exit ============
3837 23:51:15.928267 [ANA_INIT] <<<<<<<<<<<<<
3838 23:51:15.931479 [Flow] Enable top DCM control >>>>>
3839 23:51:15.935536 [Flow] Enable top DCM control <<<<<
3840 23:51:15.935643 Enable DLL master slave shuffle
3841 23:51:15.941438 ==============================================================
3842 23:51:15.945125 Gating Mode config
3843 23:51:15.948784 ==============================================================
3844 23:51:15.951505 Config description:
3845 23:51:15.961494 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3846 23:51:15.968069 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3847 23:51:15.971844 SELPH_MODE 0: By rank 1: By Phase
3848 23:51:15.978339 ==============================================================
3849 23:51:15.982275 GAT_TRACK_EN = 1
3850 23:51:15.985350 RX_GATING_MODE = 2
3851 23:51:15.985456 RX_GATING_TRACK_MODE = 2
3852 23:51:15.988957 SELPH_MODE = 1
3853 23:51:15.991905 PICG_EARLY_EN = 1
3854 23:51:15.995222 VALID_LAT_VALUE = 1
3855 23:51:16.001810 ==============================================================
3856 23:51:16.005329 Enter into Gating configuration >>>>
3857 23:51:16.008347 Exit from Gating configuration <<<<
3858 23:51:16.012443 Enter into DVFS_PRE_config >>>>>
3859 23:51:16.021953 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3860 23:51:16.025325 Exit from DVFS_PRE_config <<<<<
3861 23:51:16.028443 Enter into PICG configuration >>>>
3862 23:51:16.031544 Exit from PICG configuration <<<<
3863 23:51:16.035255 [RX_INPUT] configuration >>>>>
3864 23:51:16.038615 [RX_INPUT] configuration <<<<<
3865 23:51:16.041761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3866 23:51:16.048152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3867 23:51:16.054884 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 23:51:16.061391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 23:51:16.064790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 23:51:16.071336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 23:51:16.075718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3872 23:51:16.081945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3873 23:51:16.085768 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3874 23:51:16.088187 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3875 23:51:16.091631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3876 23:51:16.098472 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 23:51:16.101650 ===================================
3878 23:51:16.101722 LPDDR4 DRAM CONFIGURATION
3879 23:51:16.105087 ===================================
3880 23:51:16.108263 EX_ROW_EN[0] = 0x0
3881 23:51:16.111303 EX_ROW_EN[1] = 0x0
3882 23:51:16.111383 LP4Y_EN = 0x0
3883 23:51:16.114743 WORK_FSP = 0x0
3884 23:51:16.114822 WL = 0x2
3885 23:51:16.118801 RL = 0x2
3886 23:51:16.118882 BL = 0x2
3887 23:51:16.121867 RPST = 0x0
3888 23:51:16.121973 RD_PRE = 0x0
3889 23:51:16.124925 WR_PRE = 0x1
3890 23:51:16.125053 WR_PST = 0x0
3891 23:51:16.128765 DBI_WR = 0x0
3892 23:51:16.128845 DBI_RD = 0x0
3893 23:51:16.131160 OTF = 0x1
3894 23:51:16.135218 ===================================
3895 23:51:16.138326 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3896 23:51:16.141390 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3897 23:51:16.148085 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 23:51:16.151671 ===================================
3899 23:51:16.151752 LPDDR4 DRAM CONFIGURATION
3900 23:51:16.154886 ===================================
3901 23:51:16.158576 EX_ROW_EN[0] = 0x10
3902 23:51:16.158686 EX_ROW_EN[1] = 0x0
3903 23:51:16.161929 LP4Y_EN = 0x0
3904 23:51:16.162013 WORK_FSP = 0x0
3905 23:51:16.165274 WL = 0x2
3906 23:51:16.165353 RL = 0x2
3907 23:51:16.168620 BL = 0x2
3908 23:51:16.172105 RPST = 0x0
3909 23:51:16.172185 RD_PRE = 0x0
3910 23:51:16.175105 WR_PRE = 0x1
3911 23:51:16.175185 WR_PST = 0x0
3912 23:51:16.178528 DBI_WR = 0x0
3913 23:51:16.178612 DBI_RD = 0x0
3914 23:51:16.181911 OTF = 0x1
3915 23:51:16.184921 ===================================
3916 23:51:16.188607 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3917 23:51:16.193638 nWR fixed to 30
3918 23:51:16.196890 [ModeRegInit_LP4] CH0 RK0
3919 23:51:16.197016 [ModeRegInit_LP4] CH0 RK1
3920 23:51:16.200707 [ModeRegInit_LP4] CH1 RK0
3921 23:51:16.203715 [ModeRegInit_LP4] CH1 RK1
3922 23:51:16.203794 match AC timing 17
3923 23:51:16.210715 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3924 23:51:16.213541 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3925 23:51:16.216785 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3926 23:51:16.223507 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3927 23:51:16.227053 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3928 23:51:16.227134 ==
3929 23:51:16.230454 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 23:51:16.233651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 23:51:16.233732 ==
3932 23:51:16.240379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 23:51:16.246930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 23:51:16.250405 [CA 0] Center 36 (6~67) winsize 62
3935 23:51:16.254675 [CA 1] Center 36 (6~66) winsize 61
3936 23:51:16.257530 [CA 2] Center 34 (4~65) winsize 62
3937 23:51:16.260643 [CA 3] Center 34 (4~65) winsize 62
3938 23:51:16.263552 [CA 4] Center 33 (3~64) winsize 62
3939 23:51:16.267222 [CA 5] Center 33 (3~64) winsize 62
3940 23:51:16.267327
3941 23:51:16.270516 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 23:51:16.270596
3943 23:51:16.273846 [CATrainingPosCal] consider 1 rank data
3944 23:51:16.277254 u2DelayCellTimex100 = 270/100 ps
3945 23:51:16.280475 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 23:51:16.284045 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3947 23:51:16.287300 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 23:51:16.290691 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 23:51:16.294012 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 23:51:16.297403 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 23:51:16.297483
3952 23:51:16.301367 CA PerBit enable=1, Macro0, CA PI delay=33
3953 23:51:16.303918
3954 23:51:16.304023 [CBTSetCACLKResult] CA Dly = 33
3955 23:51:16.307449 CS Dly: 5 (0~36)
3956 23:51:16.307529 ==
3957 23:51:16.310790 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 23:51:16.314140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 23:51:16.314220 ==
3960 23:51:16.320757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 23:51:16.327239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3962 23:51:16.330655 [CA 0] Center 36 (6~67) winsize 62
3963 23:51:16.335112 [CA 1] Center 36 (6~66) winsize 61
3964 23:51:16.336970 [CA 2] Center 34 (4~65) winsize 62
3965 23:51:16.340437 [CA 3] Center 34 (4~65) winsize 62
3966 23:51:16.343956 [CA 4] Center 34 (3~65) winsize 63
3967 23:51:16.347540 [CA 5] Center 33 (3~64) winsize 62
3968 23:51:16.347623
3969 23:51:16.350687 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3970 23:51:16.350767
3971 23:51:16.354111 [CATrainingPosCal] consider 2 rank data
3972 23:51:16.357738 u2DelayCellTimex100 = 270/100 ps
3973 23:51:16.361328 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3974 23:51:16.363955 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 23:51:16.367485 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 23:51:16.370435 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 23:51:16.374932 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 23:51:16.377246 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 23:51:16.377330
3980 23:51:16.383834 CA PerBit enable=1, Macro0, CA PI delay=33
3981 23:51:16.383914
3982 23:51:16.383977 [CBTSetCACLKResult] CA Dly = 33
3983 23:51:16.387985 CS Dly: 4 (0~35)
3984 23:51:16.388065
3985 23:51:16.390835 ----->DramcWriteLeveling(PI) begin...
3986 23:51:16.390947 ==
3987 23:51:16.394496 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 23:51:16.397489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 23:51:16.397570 ==
3990 23:51:16.400451 Write leveling (Byte 0): 33 => 33
3991 23:51:16.403971 Write leveling (Byte 1): 29 => 29
3992 23:51:16.407457 DramcWriteLeveling(PI) end<-----
3993 23:51:16.407537
3994 23:51:16.407599 ==
3995 23:51:16.410448 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 23:51:16.414382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 23:51:16.414462 ==
3998 23:51:16.417056 [Gating] SW mode calibration
3999 23:51:16.424274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4000 23:51:16.430731 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4001 23:51:16.434228 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 23:51:16.440861 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 23:51:16.443968 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 23:51:16.447165 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 23:51:16.454145 0 9 16 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
4006 23:51:16.457263 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4007 23:51:16.460870 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 23:51:16.464822 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 23:51:16.470345 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 23:51:16.474206 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 23:51:16.478075 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 23:51:16.483782 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 23:51:16.487028 0 10 16 | B1->B0 | 3434 3b3b | 0 1 | (0 0) (0 0)
4014 23:51:16.491091 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:51:16.497255 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 23:51:16.500851 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 23:51:16.503816 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:51:16.510848 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 23:51:16.513868 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:51:16.517361 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4021 23:51:16.523976 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4022 23:51:16.527099 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:51:16.531180 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:51:16.537773 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:51:16.540442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:51:16.544394 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:51:16.547429 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:51:16.554424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:51:16.557412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:51:16.560707 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:51:16.567845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:51:16.571232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:51:16.574584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:51:16.580857 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:51:16.584915 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:51:16.587831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4037 23:51:16.593970 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4038 23:51:16.597948 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4039 23:51:16.600788 Total UI for P1: 0, mck2ui 16
4040 23:51:16.604534 best dqsien dly found for B0: ( 0, 13, 16)
4041 23:51:16.607612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 23:51:16.610857 Total UI for P1: 0, mck2ui 16
4043 23:51:16.614684 best dqsien dly found for B1: ( 0, 13, 16)
4044 23:51:16.617389 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4045 23:51:16.621648 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4046 23:51:16.621729
4047 23:51:16.624435 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4048 23:51:16.630967 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4049 23:51:16.631060 [Gating] SW calibration Done
4050 23:51:16.631126 ==
4051 23:51:16.634477 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 23:51:16.641559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 23:51:16.641643 ==
4054 23:51:16.641707 RX Vref Scan: 0
4055 23:51:16.641766
4056 23:51:16.645537 RX Vref 0 -> 0, step: 1
4057 23:51:16.645620
4058 23:51:16.648386 RX Delay -230 -> 252, step: 16
4059 23:51:16.651179 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4060 23:51:16.654124 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4061 23:51:16.657723 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4062 23:51:16.664488 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4063 23:51:16.667481 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4064 23:51:16.670980 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4065 23:51:16.674600 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4066 23:51:16.678229 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4067 23:51:16.684905 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4068 23:51:16.687898 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4069 23:51:16.690962 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4070 23:51:16.694801 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4071 23:51:16.700890 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4072 23:51:16.704828 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4073 23:51:16.708149 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4074 23:51:16.711540 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4075 23:51:16.711624 ==
4076 23:51:16.715211 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 23:51:16.720842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 23:51:16.720924 ==
4079 23:51:16.721031 DQS Delay:
4080 23:51:16.724614 DQS0 = 0, DQS1 = 0
4081 23:51:16.724696 DQM Delay:
4082 23:51:16.724796 DQM0 = 41, DQM1 = 33
4083 23:51:16.727859 DQ Delay:
4084 23:51:16.730976 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4085 23:51:16.734537 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4086 23:51:16.737845 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4087 23:51:16.741590 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4088 23:51:16.741678
4089 23:51:16.741761
4090 23:51:16.741839 ==
4091 23:51:16.744295 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 23:51:16.747602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 23:51:16.747683 ==
4094 23:51:16.747748
4095 23:51:16.747806
4096 23:51:16.751921 TX Vref Scan disable
4097 23:51:16.754411 == TX Byte 0 ==
4098 23:51:16.757835 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4099 23:51:16.761126 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4100 23:51:16.764753 == TX Byte 1 ==
4101 23:51:16.768217 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4102 23:51:16.771469 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4103 23:51:16.771550 ==
4104 23:51:16.774357 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 23:51:16.778190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 23:51:16.778271 ==
4107 23:51:16.778335
4108 23:51:16.780937
4109 23:51:16.781055 TX Vref Scan disable
4110 23:51:16.784773 == TX Byte 0 ==
4111 23:51:16.788536 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4112 23:51:16.795192 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4113 23:51:16.795279 == TX Byte 1 ==
4114 23:51:16.798313 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4115 23:51:16.802507 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4116 23:51:16.804723
4117 23:51:16.804805 [DATLAT]
4118 23:51:16.804907 Freq=600, CH0 RK0
4119 23:51:16.805042
4120 23:51:16.808269 DATLAT Default: 0x9
4121 23:51:16.808351 0, 0xFFFF, sum = 0
4122 23:51:16.811300 1, 0xFFFF, sum = 0
4123 23:51:16.811409 2, 0xFFFF, sum = 0
4124 23:51:16.814499 3, 0xFFFF, sum = 0
4125 23:51:16.814583 4, 0xFFFF, sum = 0
4126 23:51:16.818627 5, 0xFFFF, sum = 0
4127 23:51:16.821631 6, 0xFFFF, sum = 0
4128 23:51:16.821714 7, 0xFFFF, sum = 0
4129 23:51:16.821816 8, 0x0, sum = 1
4130 23:51:16.825115 9, 0x0, sum = 2
4131 23:51:16.825199 10, 0x0, sum = 3
4132 23:51:16.828566 11, 0x0, sum = 4
4133 23:51:16.828650 best_step = 9
4134 23:51:16.828733
4135 23:51:16.828810 ==
4136 23:51:16.831164 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 23:51:16.838118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 23:51:16.838205 ==
4139 23:51:16.838289 RX Vref Scan: 1
4140 23:51:16.838366
4141 23:51:16.841473 RX Vref 0 -> 0, step: 1
4142 23:51:16.841556
4143 23:51:16.844790 RX Delay -195 -> 252, step: 8
4144 23:51:16.844872
4145 23:51:16.848065 Set Vref, RX VrefLevel [Byte0]: 53
4146 23:51:16.851611 [Byte1]: 56
4147 23:51:16.851697
4148 23:51:16.854834 Final RX Vref Byte 0 = 53 to rank0
4149 23:51:16.858071 Final RX Vref Byte 1 = 56 to rank0
4150 23:51:16.861194 Final RX Vref Byte 0 = 53 to rank1
4151 23:51:16.864599 Final RX Vref Byte 1 = 56 to rank1==
4152 23:51:16.868081 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 23:51:16.872467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 23:51:16.872546 ==
4155 23:51:16.874932 DQS Delay:
4156 23:51:16.875014 DQS0 = 0, DQS1 = 0
4157 23:51:16.875096 DQM Delay:
4158 23:51:16.878248 DQM0 = 41, DQM1 = 33
4159 23:51:16.878330 DQ Delay:
4160 23:51:16.882184 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4161 23:51:16.885038 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4162 23:51:16.888304 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4163 23:51:16.892277 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4164 23:51:16.892359
4165 23:51:16.892422
4166 23:51:16.901860 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d1c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4167 23:51:16.901945 CH0 RK0: MR19=808, MR18=3D1C
4168 23:51:16.908000 CH0_RK0: MR19=0x808, MR18=0x3D1C, DQSOSC=398, MR23=63, INC=165, DEC=110
4169 23:51:16.908082
4170 23:51:16.911443 ----->DramcWriteLeveling(PI) begin...
4171 23:51:16.911529 ==
4172 23:51:16.915062 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 23:51:16.921512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 23:51:16.921598 ==
4175 23:51:16.925570 Write leveling (Byte 0): 33 => 33
4176 23:51:16.928392 Write leveling (Byte 1): 32 => 32
4177 23:51:16.928476 DramcWriteLeveling(PI) end<-----
4178 23:51:16.931957
4179 23:51:16.932040 ==
4180 23:51:16.934957 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 23:51:16.938355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 23:51:16.938439 ==
4183 23:51:16.941563 [Gating] SW mode calibration
4184 23:51:16.948574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4185 23:51:16.951742 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4186 23:51:16.959054 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 23:51:16.962195 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 23:51:16.965195 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 23:51:16.971616 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
4190 23:51:16.975676 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
4191 23:51:16.978046 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 23:51:16.984760 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 23:51:16.988029 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 23:51:16.991589 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 23:51:16.998526 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 23:51:17.001382 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 23:51:17.004995 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4198 23:51:17.008620 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4199 23:51:17.014731 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 23:51:17.017895 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:51:17.021872 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 23:51:17.028643 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 23:51:17.031864 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 23:51:17.035085 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 23:51:17.041306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4206 23:51:17.044892 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4207 23:51:17.048349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:51:17.054946 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:51:17.058560 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:51:17.061284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:51:17.068026 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:51:17.071812 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:51:17.075182 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:51:17.081740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:51:17.084807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:51:17.088571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:51:17.094854 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:51:17.098523 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:51:17.101433 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:51:17.105395 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4221 23:51:17.111691 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4222 23:51:17.114910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4223 23:51:17.118319 Total UI for P1: 0, mck2ui 16
4224 23:51:17.121640 best dqsien dly found for B0: ( 0, 13, 10)
4225 23:51:17.124960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 23:51:17.128594 Total UI for P1: 0, mck2ui 16
4227 23:51:17.132122 best dqsien dly found for B1: ( 0, 13, 16)
4228 23:51:17.135378 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4229 23:51:17.138767 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4230 23:51:17.138861
4231 23:51:17.145279 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4232 23:51:17.148536 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4233 23:51:17.152019 [Gating] SW calibration Done
4234 23:51:17.152113 ==
4235 23:51:17.155163 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 23:51:17.159048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 23:51:17.159131 ==
4238 23:51:17.159195 RX Vref Scan: 0
4239 23:51:17.159253
4240 23:51:17.161964 RX Vref 0 -> 0, step: 1
4241 23:51:17.162095
4242 23:51:17.165862 RX Delay -230 -> 252, step: 16
4243 23:51:17.168332 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4244 23:51:17.172220 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4245 23:51:17.178874 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4246 23:51:17.182024 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4247 23:51:17.185473 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4248 23:51:17.188587 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4249 23:51:17.191768 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4250 23:51:17.199134 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4251 23:51:17.202381 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4252 23:51:17.205791 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4253 23:51:17.208877 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4254 23:51:17.215834 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4255 23:51:17.218791 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4256 23:51:17.222355 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4257 23:51:17.225535 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4258 23:51:17.231792 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4259 23:51:17.231951 ==
4260 23:51:17.235358 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 23:51:17.238959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 23:51:17.239101 ==
4263 23:51:17.239223 DQS Delay:
4264 23:51:17.242450 DQS0 = 0, DQS1 = 0
4265 23:51:17.242587 DQM Delay:
4266 23:51:17.245466 DQM0 = 39, DQM1 = 30
4267 23:51:17.245606 DQ Delay:
4268 23:51:17.248753 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4269 23:51:17.252243 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4270 23:51:17.255508 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4271 23:51:17.258962 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4272 23:51:17.259092
4273 23:51:17.259214
4274 23:51:17.259322 ==
4275 23:51:17.262682 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 23:51:17.265652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 23:51:17.265738 ==
4278 23:51:17.265813
4279 23:51:17.265872
4280 23:51:17.269276 TX Vref Scan disable
4281 23:51:17.272820 == TX Byte 0 ==
4282 23:51:17.276113 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4283 23:51:17.279133 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4284 23:51:17.282346 == TX Byte 1 ==
4285 23:51:17.285733 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4286 23:51:17.289255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4287 23:51:17.289336 ==
4288 23:51:17.292643 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 23:51:17.296885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 23:51:17.297029 ==
4291 23:51:17.297095
4292 23:51:17.299558
4293 23:51:17.299638 TX Vref Scan disable
4294 23:51:17.302409 == TX Byte 0 ==
4295 23:51:17.306116 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4296 23:51:17.313150 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4297 23:51:17.313235 == TX Byte 1 ==
4298 23:51:17.315927 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4299 23:51:17.319326 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4300 23:51:17.322856
4301 23:51:17.322936 [DATLAT]
4302 23:51:17.322998 Freq=600, CH0 RK1
4303 23:51:17.323056
4304 23:51:17.325857 DATLAT Default: 0x9
4305 23:51:17.325937 0, 0xFFFF, sum = 0
4306 23:51:17.329387 1, 0xFFFF, sum = 0
4307 23:51:17.329468 2, 0xFFFF, sum = 0
4308 23:51:17.332698 3, 0xFFFF, sum = 0
4309 23:51:17.332779 4, 0xFFFF, sum = 0
4310 23:51:17.335975 5, 0xFFFF, sum = 0
4311 23:51:17.336057 6, 0xFFFF, sum = 0
4312 23:51:17.339921 7, 0xFFFF, sum = 0
4313 23:51:17.340002 8, 0x0, sum = 1
4314 23:51:17.342944 9, 0x0, sum = 2
4315 23:51:17.343025 10, 0x0, sum = 3
4316 23:51:17.346237 11, 0x0, sum = 4
4317 23:51:17.346318 best_step = 9
4318 23:51:17.346380
4319 23:51:17.346437 ==
4320 23:51:17.349500 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 23:51:17.356210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 23:51:17.356291 ==
4323 23:51:17.356353 RX Vref Scan: 0
4324 23:51:17.356411
4325 23:51:17.359244 RX Vref 0 -> 0, step: 1
4326 23:51:17.359323
4327 23:51:17.363108 RX Delay -195 -> 252, step: 8
4328 23:51:17.365843 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4329 23:51:17.372643 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4330 23:51:17.375771 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4331 23:51:17.380115 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4332 23:51:17.383990 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4333 23:51:17.386116 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4334 23:51:17.392821 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4335 23:51:17.395848 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4336 23:51:17.400277 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4337 23:51:17.402761 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4338 23:51:17.409446 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4339 23:51:17.412532 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4340 23:51:17.415819 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4341 23:51:17.419217 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4342 23:51:17.422878 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4343 23:51:17.430183 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4344 23:51:17.430267 ==
4345 23:51:17.433138 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 23:51:17.436093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 23:51:17.436174 ==
4348 23:51:17.436237 DQS Delay:
4349 23:51:17.439455 DQS0 = 0, DQS1 = 0
4350 23:51:17.439536 DQM Delay:
4351 23:51:17.443433 DQM0 = 39, DQM1 = 32
4352 23:51:17.443514 DQ Delay:
4353 23:51:17.445971 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4354 23:51:17.449274 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4355 23:51:17.452583 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4356 23:51:17.456722 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4357 23:51:17.456838
4358 23:51:17.456901
4359 23:51:17.466459 [DQSOSCAuto] RK1, (LSB)MR18= 0x492b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4360 23:51:17.466546 CH0 RK1: MR19=808, MR18=492B
4361 23:51:17.473176 CH0_RK1: MR19=0x808, MR18=0x492B, DQSOSC=396, MR23=63, INC=167, DEC=111
4362 23:51:17.476459 [RxdqsGatingPostProcess] freq 600
4363 23:51:17.483084 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4364 23:51:17.486133 Pre-setting of DQS Precalculation
4365 23:51:17.489337 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4366 23:51:17.489420 ==
4367 23:51:17.492757 Dram Type= 6, Freq= 0, CH_1, rank 0
4368 23:51:17.495985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 23:51:17.496076 ==
4370 23:51:17.502627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 23:51:17.509319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4372 23:51:17.512677 [CA 0] Center 35 (5~65) winsize 61
4373 23:51:17.516368 [CA 1] Center 35 (5~66) winsize 62
4374 23:51:17.519707 [CA 2] Center 34 (3~65) winsize 63
4375 23:51:17.522390 [CA 3] Center 33 (3~64) winsize 62
4376 23:51:17.526249 [CA 4] Center 34 (3~65) winsize 63
4377 23:51:17.529158 [CA 5] Center 33 (2~64) winsize 63
4378 23:51:17.529240
4379 23:51:17.532776 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4380 23:51:17.532911
4381 23:51:17.536904 [CATrainingPosCal] consider 1 rank data
4382 23:51:17.539962 u2DelayCellTimex100 = 270/100 ps
4383 23:51:17.543506 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4384 23:51:17.547186 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 23:51:17.549690 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4386 23:51:17.552969 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 23:51:17.556157 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4388 23:51:17.559704 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4389 23:51:17.562834
4390 23:51:17.566986 CA PerBit enable=1, Macro0, CA PI delay=33
4391 23:51:17.567070
4392 23:51:17.570306 [CBTSetCACLKResult] CA Dly = 33
4393 23:51:17.570391 CS Dly: 4 (0~35)
4394 23:51:17.570456 ==
4395 23:51:17.573187 Dram Type= 6, Freq= 0, CH_1, rank 1
4396 23:51:17.575953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 23:51:17.576036 ==
4398 23:51:17.582931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 23:51:17.589193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4400 23:51:17.592644 [CA 0] Center 35 (5~66) winsize 62
4401 23:51:17.596023 [CA 1] Center 35 (5~66) winsize 62
4402 23:51:17.599551 [CA 2] Center 34 (3~65) winsize 63
4403 23:51:17.602820 [CA 3] Center 34 (3~65) winsize 63
4404 23:51:17.607051 [CA 4] Center 34 (3~65) winsize 63
4405 23:51:17.610111 [CA 5] Center 33 (3~64) winsize 62
4406 23:51:17.610194
4407 23:51:17.613178 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4408 23:51:17.613260
4409 23:51:17.616228 [CATrainingPosCal] consider 2 rank data
4410 23:51:17.619902 u2DelayCellTimex100 = 270/100 ps
4411 23:51:17.623674 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4412 23:51:17.626015 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 23:51:17.629948 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4414 23:51:17.633737 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 23:51:17.636526 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4416 23:51:17.639474 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 23:51:17.642919
4418 23:51:17.646113 CA PerBit enable=1, Macro0, CA PI delay=33
4419 23:51:17.646198
4420 23:51:17.649406 [CBTSetCACLKResult] CA Dly = 33
4421 23:51:17.649489 CS Dly: 4 (0~35)
4422 23:51:17.649554
4423 23:51:17.653305 ----->DramcWriteLeveling(PI) begin...
4424 23:51:17.653388 ==
4425 23:51:17.656013 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 23:51:17.659961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 23:51:17.660044 ==
4428 23:51:17.663059 Write leveling (Byte 0): 29 => 29
4429 23:51:17.666231 Write leveling (Byte 1): 30 => 30
4430 23:51:17.669837 DramcWriteLeveling(PI) end<-----
4431 23:51:17.669922
4432 23:51:17.669987 ==
4433 23:51:17.672678 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 23:51:17.679163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 23:51:17.679247 ==
4436 23:51:17.679312 [Gating] SW mode calibration
4437 23:51:17.689773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4438 23:51:17.693503 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4439 23:51:17.696798 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 23:51:17.703158 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 23:51:17.706208 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 23:51:17.709373 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
4443 23:51:17.715984 0 9 16 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 0)
4444 23:51:17.719469 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:51:17.722525 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4446 23:51:17.729492 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 23:51:17.732851 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 23:51:17.736348 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 23:51:17.742828 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 23:51:17.746539 0 10 12 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (0 0)
4451 23:51:17.749306 0 10 16 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
4452 23:51:17.756119 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:51:17.759496 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:51:17.762650 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:51:17.769666 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 23:51:17.772749 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 23:51:17.775628 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 23:51:17.782824 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 23:51:17.785753 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4460 23:51:17.789162 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:51:17.792543 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:51:17.798902 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:51:17.802215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:51:17.806075 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:51:17.812725 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:51:17.815838 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:51:17.819192 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:51:17.825732 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:51:17.829893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:51:17.833053 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:51:17.839555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:51:17.842567 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:51:17.846010 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:51:17.852506 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4475 23:51:17.852605 Total UI for P1: 0, mck2ui 16
4476 23:51:17.859583 best dqsien dly found for B1: ( 0, 13, 10)
4477 23:51:17.863273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4478 23:51:17.866054 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 23:51:17.869757 Total UI for P1: 0, mck2ui 16
4480 23:51:17.872890 best dqsien dly found for B0: ( 0, 13, 14)
4481 23:51:17.875729 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4482 23:51:17.879542 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4483 23:51:17.879629
4484 23:51:17.882652 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4485 23:51:17.889280 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4486 23:51:17.889383 [Gating] SW calibration Done
4487 23:51:17.889451 ==
4488 23:51:17.893093 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 23:51:17.899139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 23:51:17.899277 ==
4491 23:51:17.899384 RX Vref Scan: 0
4492 23:51:17.899474
4493 23:51:17.902965 RX Vref 0 -> 0, step: 1
4494 23:51:17.903049
4495 23:51:17.906393 RX Delay -230 -> 252, step: 16
4496 23:51:17.909431 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4497 23:51:17.913404 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4498 23:51:17.919274 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4499 23:51:17.923237 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4500 23:51:17.926696 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4501 23:51:17.929712 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4502 23:51:17.933027 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4503 23:51:17.939761 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4504 23:51:17.942630 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4505 23:51:17.946068 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4506 23:51:17.949421 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4507 23:51:17.956227 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4508 23:51:17.959853 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4509 23:51:17.962782 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4510 23:51:17.965920 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4511 23:51:17.969344 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4512 23:51:17.972473 ==
4513 23:51:17.975690 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 23:51:17.980018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 23:51:17.980099 ==
4516 23:51:17.980162 DQS Delay:
4517 23:51:17.982400 DQS0 = 0, DQS1 = 0
4518 23:51:17.982480 DQM Delay:
4519 23:51:17.985923 DQM0 = 45, DQM1 = 35
4520 23:51:17.986032 DQ Delay:
4521 23:51:17.989303 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4522 23:51:17.992279 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4523 23:51:17.996018 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4524 23:51:17.999310 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4525 23:51:17.999395
4526 23:51:17.999460
4527 23:51:17.999519 ==
4528 23:51:18.003741 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 23:51:18.006485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 23:51:18.006566 ==
4531 23:51:18.006634
4532 23:51:18.006707
4533 23:51:18.009703 TX Vref Scan disable
4534 23:51:18.013207 == TX Byte 0 ==
4535 23:51:18.015981 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 23:51:18.019680 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 23:51:18.023241 == TX Byte 1 ==
4538 23:51:18.026052 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 23:51:18.030506 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 23:51:18.030586 ==
4541 23:51:18.033382 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 23:51:18.036505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 23:51:18.036586 ==
4544 23:51:18.039421
4545 23:51:18.039501
4546 23:51:18.039564 TX Vref Scan disable
4547 23:51:18.043402 == TX Byte 0 ==
4548 23:51:18.046370 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4549 23:51:18.050161 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4550 23:51:18.052939 == TX Byte 1 ==
4551 23:51:18.056217 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4552 23:51:18.059910 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4553 23:51:18.063550
4554 23:51:18.063634 [DATLAT]
4555 23:51:18.063697 Freq=600, CH1 RK0
4556 23:51:18.063757
4557 23:51:18.066744 DATLAT Default: 0x9
4558 23:51:18.066825 0, 0xFFFF, sum = 0
4559 23:51:18.070315 1, 0xFFFF, sum = 0
4560 23:51:18.070398 2, 0xFFFF, sum = 0
4561 23:51:18.073842 3, 0xFFFF, sum = 0
4562 23:51:18.073925 4, 0xFFFF, sum = 0
4563 23:51:18.076579 5, 0xFFFF, sum = 0
4564 23:51:18.076661 6, 0xFFFF, sum = 0
4565 23:51:18.080734 7, 0xFFFF, sum = 0
4566 23:51:18.080844 8, 0x0, sum = 1
4567 23:51:18.084299 9, 0x0, sum = 2
4568 23:51:18.084389 10, 0x0, sum = 3
4569 23:51:18.086568 11, 0x0, sum = 4
4570 23:51:18.086677 best_step = 9
4571 23:51:18.086767
4572 23:51:18.086828 ==
4573 23:51:18.089857 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 23:51:18.093564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 23:51:18.096641 ==
4576 23:51:18.096726 RX Vref Scan: 1
4577 23:51:18.096832
4578 23:51:18.099740 RX Vref 0 -> 0, step: 1
4579 23:51:18.099822
4580 23:51:18.103088 RX Delay -195 -> 252, step: 8
4581 23:51:18.103170
4582 23:51:18.106800 Set Vref, RX VrefLevel [Byte0]: 56
4583 23:51:18.110019 [Byte1]: 53
4584 23:51:18.110107
4585 23:51:18.113232 Final RX Vref Byte 0 = 56 to rank0
4586 23:51:18.116560 Final RX Vref Byte 1 = 53 to rank0
4587 23:51:18.120192 Final RX Vref Byte 0 = 56 to rank1
4588 23:51:18.123107 Final RX Vref Byte 1 = 53 to rank1==
4589 23:51:18.126711 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 23:51:18.130243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 23:51:18.130331 ==
4592 23:51:18.133150 DQS Delay:
4593 23:51:18.133232 DQS0 = 0, DQS1 = 0
4594 23:51:18.133297 DQM Delay:
4595 23:51:18.136928 DQM0 = 40, DQM1 = 33
4596 23:51:18.137032 DQ Delay:
4597 23:51:18.139868 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4598 23:51:18.143088 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4599 23:51:18.146757 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4600 23:51:18.149780 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4601 23:51:18.149868
4602 23:51:18.149932
4603 23:51:18.160669 [DQSOSCAuto] RK0, (LSB)MR18= 0x450b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4604 23:51:18.160806 CH1 RK0: MR19=808, MR18=450B
4605 23:51:18.167019 CH1_RK0: MR19=0x808, MR18=0x450B, DQSOSC=396, MR23=63, INC=167, DEC=111
4606 23:51:18.167107
4607 23:51:18.169423 ----->DramcWriteLeveling(PI) begin...
4608 23:51:18.173312 ==
4609 23:51:18.173394 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 23:51:18.179589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 23:51:18.179671 ==
4612 23:51:18.183118 Write leveling (Byte 0): 29 => 29
4613 23:51:18.186579 Write leveling (Byte 1): 30 => 30
4614 23:51:18.189558 DramcWriteLeveling(PI) end<-----
4615 23:51:18.189638
4616 23:51:18.189700 ==
4617 23:51:18.192655 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 23:51:18.196646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 23:51:18.196730 ==
4620 23:51:18.199607 [Gating] SW mode calibration
4621 23:51:18.206113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4622 23:51:18.212683 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4623 23:51:18.215877 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 23:51:18.219126 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 23:51:18.222792 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (0 1)
4626 23:51:18.229194 0 9 12 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (1 1)
4627 23:51:18.232925 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4628 23:51:18.236281 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 23:51:18.242727 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 23:51:18.246566 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 23:51:18.249229 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 23:51:18.255747 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 23:51:18.259045 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4634 23:51:18.262991 0 10 12 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
4635 23:51:18.269111 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:51:18.272369 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:51:18.275634 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 23:51:18.282614 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 23:51:18.286880 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 23:51:18.289371 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 23:51:18.295621 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 23:51:18.298932 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4643 23:51:18.302426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:51:18.309698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:51:18.312947 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:51:18.315921 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:51:18.322650 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:51:18.326047 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:51:18.329030 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:51:18.332268 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:51:18.339288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:51:18.342633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:51:18.345850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:51:18.352506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:51:18.356389 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:51:18.359331 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:51:18.366071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 23:51:18.368965 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4659 23:51:18.372556 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 23:51:18.376601 Total UI for P1: 0, mck2ui 16
4661 23:51:18.379865 best dqsien dly found for B0: ( 0, 13, 12)
4662 23:51:18.382615 Total UI for P1: 0, mck2ui 16
4663 23:51:18.385518 best dqsien dly found for B1: ( 0, 13, 14)
4664 23:51:18.389234 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4665 23:51:18.392335 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4666 23:51:18.392415
4667 23:51:18.398780 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4668 23:51:18.402299 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4669 23:51:18.405934 [Gating] SW calibration Done
4670 23:51:18.406016 ==
4671 23:51:18.409290 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 23:51:18.412551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 23:51:18.412633 ==
4674 23:51:18.412762 RX Vref Scan: 0
4675 23:51:18.412850
4676 23:51:18.415607 RX Vref 0 -> 0, step: 1
4677 23:51:18.415678
4678 23:51:18.419925 RX Delay -230 -> 252, step: 16
4679 23:51:18.422851 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4680 23:51:18.425612 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4681 23:51:18.432813 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4682 23:51:18.435459 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4683 23:51:18.439510 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4684 23:51:18.442499 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4685 23:51:18.445566 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4686 23:51:18.452780 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4687 23:51:18.455537 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4688 23:51:18.459454 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4689 23:51:18.462402 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4690 23:51:18.469307 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4691 23:51:18.472404 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4692 23:51:18.476129 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4693 23:51:18.479446 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4694 23:51:18.487284 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4695 23:51:18.487379 ==
4696 23:51:18.489604 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 23:51:18.492679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 23:51:18.492760 ==
4699 23:51:18.492824 DQS Delay:
4700 23:51:18.496608 DQS0 = 0, DQS1 = 0
4701 23:51:18.496689 DQM Delay:
4702 23:51:18.499329 DQM0 = 41, DQM1 = 37
4703 23:51:18.499410 DQ Delay:
4704 23:51:18.502414 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4705 23:51:18.506119 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4706 23:51:18.509465 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4707 23:51:18.512959 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4708 23:51:18.513103
4709 23:51:18.513202
4710 23:51:18.513288 ==
4711 23:51:18.515861 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 23:51:18.519080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 23:51:18.519162 ==
4714 23:51:18.519226
4715 23:51:18.519284
4716 23:51:18.523563 TX Vref Scan disable
4717 23:51:18.525722 == TX Byte 0 ==
4718 23:51:18.529291 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4719 23:51:18.532801 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4720 23:51:18.535887 == TX Byte 1 ==
4721 23:51:18.539912 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 23:51:18.542644 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 23:51:18.542724 ==
4724 23:51:18.545919 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 23:51:18.549312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 23:51:18.552328 ==
4727 23:51:18.552444
4728 23:51:18.552512
4729 23:51:18.552572 TX Vref Scan disable
4730 23:51:18.556904 == TX Byte 0 ==
4731 23:51:18.559962 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4732 23:51:18.563159 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4733 23:51:18.566940 == TX Byte 1 ==
4734 23:51:18.569950 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 23:51:18.573204 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 23:51:18.576798
4737 23:51:18.576878 [DATLAT]
4738 23:51:18.576942 Freq=600, CH1 RK1
4739 23:51:18.577040
4740 23:51:18.580640 DATLAT Default: 0x9
4741 23:51:18.580720 0, 0xFFFF, sum = 0
4742 23:51:18.582992 1, 0xFFFF, sum = 0
4743 23:51:18.583074 2, 0xFFFF, sum = 0
4744 23:51:18.586666 3, 0xFFFF, sum = 0
4745 23:51:18.586747 4, 0xFFFF, sum = 0
4746 23:51:18.589804 5, 0xFFFF, sum = 0
4747 23:51:18.589887 6, 0xFFFF, sum = 0
4748 23:51:18.593849 7, 0xFFFF, sum = 0
4749 23:51:18.593940 8, 0x0, sum = 1
4750 23:51:18.596866 9, 0x0, sum = 2
4751 23:51:18.596970 10, 0x0, sum = 3
4752 23:51:18.599600 11, 0x0, sum = 4
4753 23:51:18.599682 best_step = 9
4754 23:51:18.599746
4755 23:51:18.599806 ==
4756 23:51:18.603648 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 23:51:18.609925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 23:51:18.610006 ==
4759 23:51:18.610070 RX Vref Scan: 0
4760 23:51:18.610128
4761 23:51:18.613500 RX Vref 0 -> 0, step: 1
4762 23:51:18.613580
4763 23:51:18.616530 RX Delay -195 -> 252, step: 8
4764 23:51:18.620028 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4765 23:51:18.626552 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4766 23:51:18.629865 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4767 23:51:18.633218 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4768 23:51:18.636736 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4769 23:51:18.640257 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4770 23:51:18.647166 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4771 23:51:18.649891 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4772 23:51:18.653576 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4773 23:51:18.656613 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4774 23:51:18.660059 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4775 23:51:18.669100 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4776 23:51:18.669668 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4777 23:51:18.673159 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4778 23:51:18.676595 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4779 23:51:18.683978 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4780 23:51:18.684065 ==
4781 23:51:18.686737 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 23:51:18.690296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 23:51:18.690379 ==
4784 23:51:18.690443 DQS Delay:
4785 23:51:18.693171 DQS0 = 0, DQS1 = 0
4786 23:51:18.693270 DQM Delay:
4787 23:51:18.696453 DQM0 = 38, DQM1 = 33
4788 23:51:18.696536 DQ Delay:
4789 23:51:18.700234 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4790 23:51:18.703267 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =36
4791 23:51:18.706382 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4792 23:51:18.710359 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4793 23:51:18.710443
4794 23:51:18.710508
4795 23:51:18.720110 [DQSOSCAuto] RK1, (LSB)MR18= 0x3645, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4796 23:51:18.720196 CH1 RK1: MR19=808, MR18=3645
4797 23:51:18.727026 CH1_RK1: MR19=0x808, MR18=0x3645, DQSOSC=396, MR23=63, INC=167, DEC=111
4798 23:51:18.730210 [RxdqsGatingPostProcess] freq 600
4799 23:51:18.736393 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4800 23:51:18.740011 Pre-setting of DQS Precalculation
4801 23:51:18.743868 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4802 23:51:18.749839 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4803 23:51:18.756979 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4804 23:51:18.757063
4805 23:51:18.757126
4806 23:51:18.760024 [Calibration Summary] 1200 Mbps
4807 23:51:18.763165 CH 0, Rank 0
4808 23:51:18.763245 SW Impedance : PASS
4809 23:51:18.767131 DUTY Scan : NO K
4810 23:51:18.770636 ZQ Calibration : PASS
4811 23:51:18.770716 Jitter Meter : NO K
4812 23:51:18.773869 CBT Training : PASS
4813 23:51:18.777407 Write leveling : PASS
4814 23:51:18.777488 RX DQS gating : PASS
4815 23:51:18.780083 RX DQ/DQS(RDDQC) : PASS
4816 23:51:18.780163 TX DQ/DQS : PASS
4817 23:51:18.783412 RX DATLAT : PASS
4818 23:51:18.787112 RX DQ/DQS(Engine): PASS
4819 23:51:18.787193 TX OE : NO K
4820 23:51:18.790545 All Pass.
4821 23:51:18.790638
4822 23:51:18.790700 CH 0, Rank 1
4823 23:51:18.793296 SW Impedance : PASS
4824 23:51:18.793377 DUTY Scan : NO K
4825 23:51:18.796845 ZQ Calibration : PASS
4826 23:51:18.800326 Jitter Meter : NO K
4827 23:51:18.800409 CBT Training : PASS
4828 23:51:18.803510 Write leveling : PASS
4829 23:51:18.807424 RX DQS gating : PASS
4830 23:51:18.807504 RX DQ/DQS(RDDQC) : PASS
4831 23:51:18.810166 TX DQ/DQS : PASS
4832 23:51:18.814560 RX DATLAT : PASS
4833 23:51:18.814641 RX DQ/DQS(Engine): PASS
4834 23:51:18.816894 TX OE : NO K
4835 23:51:18.817041 All Pass.
4836 23:51:18.817107
4837 23:51:18.817166 CH 1, Rank 0
4838 23:51:18.820866 SW Impedance : PASS
4839 23:51:18.823422 DUTY Scan : NO K
4840 23:51:18.823507 ZQ Calibration : PASS
4841 23:51:18.827242 Jitter Meter : NO K
4842 23:51:18.830564 CBT Training : PASS
4843 23:51:18.830671 Write leveling : PASS
4844 23:51:18.833686 RX DQS gating : PASS
4845 23:51:18.836944 RX DQ/DQS(RDDQC) : PASS
4846 23:51:18.837079 TX DQ/DQS : PASS
4847 23:51:18.840184 RX DATLAT : PASS
4848 23:51:18.843341 RX DQ/DQS(Engine): PASS
4849 23:51:18.843436 TX OE : NO K
4850 23:51:18.846762 All Pass.
4851 23:51:18.846842
4852 23:51:18.846905 CH 1, Rank 1
4853 23:51:18.850346 SW Impedance : PASS
4854 23:51:18.850426 DUTY Scan : NO K
4855 23:51:18.854036 ZQ Calibration : PASS
4856 23:51:18.857401 Jitter Meter : NO K
4857 23:51:18.857482 CBT Training : PASS
4858 23:51:18.861459 Write leveling : PASS
4859 23:51:18.861540 RX DQS gating : PASS
4860 23:51:18.863427 RX DQ/DQS(RDDQC) : PASS
4861 23:51:18.867584 TX DQ/DQS : PASS
4862 23:51:18.867665 RX DATLAT : PASS
4863 23:51:18.870093 RX DQ/DQS(Engine): PASS
4864 23:51:18.874097 TX OE : NO K
4865 23:51:18.874177 All Pass.
4866 23:51:18.874241
4867 23:51:18.877515 DramC Write-DBI off
4868 23:51:18.877596 PER_BANK_REFRESH: Hybrid Mode
4869 23:51:18.880181 TX_TRACKING: ON
4870 23:51:18.887040 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4871 23:51:18.890684 [FAST_K] Save calibration result to emmc
4872 23:51:18.897097 dramc_set_vcore_voltage set vcore to 662500
4873 23:51:18.897210 Read voltage for 933, 3
4874 23:51:18.900117 Vio18 = 0
4875 23:51:18.900197 Vcore = 662500
4876 23:51:18.900260 Vdram = 0
4877 23:51:18.903927 Vddq = 0
4878 23:51:18.904007 Vmddr = 0
4879 23:51:18.907161 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4880 23:51:18.913874 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4881 23:51:18.917438 MEM_TYPE=3, freq_sel=17
4882 23:51:18.920675 sv_algorithm_assistance_LP4_1600
4883 23:51:18.924249 ============ PULL DRAM RESETB DOWN ============
4884 23:51:18.927276 ========== PULL DRAM RESETB DOWN end =========
4885 23:51:18.930814 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4886 23:51:18.933770 ===================================
4887 23:51:18.937014 LPDDR4 DRAM CONFIGURATION
4888 23:51:18.940682 ===================================
4889 23:51:18.943577 EX_ROW_EN[0] = 0x0
4890 23:51:18.943657 EX_ROW_EN[1] = 0x0
4891 23:51:18.947547 LP4Y_EN = 0x0
4892 23:51:18.947627 WORK_FSP = 0x0
4893 23:51:18.950555 WL = 0x3
4894 23:51:18.950635 RL = 0x3
4895 23:51:18.953869 BL = 0x2
4896 23:51:18.953949 RPST = 0x0
4897 23:51:18.958208 RD_PRE = 0x0
4898 23:51:18.958287 WR_PRE = 0x1
4899 23:51:18.960809 WR_PST = 0x0
4900 23:51:18.960914 DBI_WR = 0x0
4901 23:51:18.964663 DBI_RD = 0x0
4902 23:51:18.964742 OTF = 0x1
4903 23:51:18.967514 ===================================
4904 23:51:18.970400 ===================================
4905 23:51:18.974023 ANA top config
4906 23:51:18.977532 ===================================
4907 23:51:18.981002 DLL_ASYNC_EN = 0
4908 23:51:18.981096 ALL_SLAVE_EN = 1
4909 23:51:18.984522 NEW_RANK_MODE = 1
4910 23:51:18.987476 DLL_IDLE_MODE = 1
4911 23:51:18.990427 LP45_APHY_COMB_EN = 1
4912 23:51:18.990506 TX_ODT_DIS = 1
4913 23:51:18.994025 NEW_8X_MODE = 1
4914 23:51:18.997348 ===================================
4915 23:51:19.000930 ===================================
4916 23:51:19.003831 data_rate = 1866
4917 23:51:19.007543 CKR = 1
4918 23:51:19.010732 DQ_P2S_RATIO = 8
4919 23:51:19.014191 ===================================
4920 23:51:19.017455 CA_P2S_RATIO = 8
4921 23:51:19.017536 DQ_CA_OPEN = 0
4922 23:51:19.020416 DQ_SEMI_OPEN = 0
4923 23:51:19.024240 CA_SEMI_OPEN = 0
4924 23:51:19.027124 CA_FULL_RATE = 0
4925 23:51:19.030457 DQ_CKDIV4_EN = 1
4926 23:51:19.030537 CA_CKDIV4_EN = 1
4927 23:51:19.033879 CA_PREDIV_EN = 0
4928 23:51:19.037302 PH8_DLY = 0
4929 23:51:19.040733 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4930 23:51:19.044402 DQ_AAMCK_DIV = 4
4931 23:51:19.047458 CA_AAMCK_DIV = 4
4932 23:51:19.047538 CA_ADMCK_DIV = 4
4933 23:51:19.050673 DQ_TRACK_CA_EN = 0
4934 23:51:19.054596 CA_PICK = 933
4935 23:51:19.057262 CA_MCKIO = 933
4936 23:51:19.061042 MCKIO_SEMI = 0
4937 23:51:19.064464 PLL_FREQ = 3732
4938 23:51:19.067659 DQ_UI_PI_RATIO = 32
4939 23:51:19.067739 CA_UI_PI_RATIO = 0
4940 23:51:19.070565 ===================================
4941 23:51:19.074022 ===================================
4942 23:51:19.077231 memory_type:LPDDR4
4943 23:51:19.081091 GP_NUM : 10
4944 23:51:19.081171 SRAM_EN : 1
4945 23:51:19.084118 MD32_EN : 0
4946 23:51:19.087659 ===================================
4947 23:51:19.090789 [ANA_INIT] >>>>>>>>>>>>>>
4948 23:51:19.094293 <<<<<< [CONFIGURE PHASE]: ANA_TX
4949 23:51:19.097848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4950 23:51:19.100622 ===================================
4951 23:51:19.100721 data_rate = 1866,PCW = 0X8f00
4952 23:51:19.104341 ===================================
4953 23:51:19.107012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4954 23:51:19.114417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 23:51:19.120812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 23:51:19.124105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4957 23:51:19.127236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4958 23:51:19.130780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4959 23:51:19.133898 [ANA_INIT] flow start
4960 23:51:19.133978 [ANA_INIT] PLL >>>>>>>>
4961 23:51:19.137363 [ANA_INIT] PLL <<<<<<<<
4962 23:51:19.140856 [ANA_INIT] MIDPI >>>>>>>>
4963 23:51:19.143695 [ANA_INIT] MIDPI <<<<<<<<
4964 23:51:19.143776 [ANA_INIT] DLL >>>>>>>>
4965 23:51:19.147578 [ANA_INIT] flow end
4966 23:51:19.150895 ============ LP4 DIFF to SE enter ============
4967 23:51:19.154133 ============ LP4 DIFF to SE exit ============
4968 23:51:19.156933 [ANA_INIT] <<<<<<<<<<<<<
4969 23:51:19.160680 [Flow] Enable top DCM control >>>>>
4970 23:51:19.164233 [Flow] Enable top DCM control <<<<<
4971 23:51:19.167636 Enable DLL master slave shuffle
4972 23:51:19.174038 ==============================================================
4973 23:51:19.174120 Gating Mode config
4974 23:51:19.180471 ==============================================================
4975 23:51:19.180552 Config description:
4976 23:51:19.191454 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4977 23:51:19.196872 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4978 23:51:19.203559 SELPH_MODE 0: By rank 1: By Phase
4979 23:51:19.207460 ==============================================================
4980 23:51:19.210227 GAT_TRACK_EN = 1
4981 23:51:19.214130 RX_GATING_MODE = 2
4982 23:51:19.216861 RX_GATING_TRACK_MODE = 2
4983 23:51:19.220238 SELPH_MODE = 1
4984 23:51:19.223724 PICG_EARLY_EN = 1
4985 23:51:19.227348 VALID_LAT_VALUE = 1
4986 23:51:19.230315 ==============================================================
4987 23:51:19.233554 Enter into Gating configuration >>>>
4988 23:51:19.237733 Exit from Gating configuration <<<<
4989 23:51:19.240367 Enter into DVFS_PRE_config >>>>>
4990 23:51:19.254314 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4991 23:51:19.254405 Exit from DVFS_PRE_config <<<<<
4992 23:51:19.257638 Enter into PICG configuration >>>>
4993 23:51:19.260563 Exit from PICG configuration <<<<
4994 23:51:19.263426 [RX_INPUT] configuration >>>>>
4995 23:51:19.267496 [RX_INPUT] configuration <<<<<
4996 23:51:19.274094 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4997 23:51:19.277418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4998 23:51:19.284076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 23:51:19.290471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 23:51:19.297832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 23:51:19.304332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 23:51:19.307170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5003 23:51:19.310570 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5004 23:51:19.314200 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5005 23:51:19.320806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5006 23:51:19.323740 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5007 23:51:19.327242 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 23:51:19.330436 ===================================
5009 23:51:19.334173 LPDDR4 DRAM CONFIGURATION
5010 23:51:19.337273 ===================================
5011 23:51:19.337361 EX_ROW_EN[0] = 0x0
5012 23:51:19.340423 EX_ROW_EN[1] = 0x0
5013 23:51:19.343544 LP4Y_EN = 0x0
5014 23:51:19.343624 WORK_FSP = 0x0
5015 23:51:19.347649 WL = 0x3
5016 23:51:19.347728 RL = 0x3
5017 23:51:19.350214 BL = 0x2
5018 23:51:19.350293 RPST = 0x0
5019 23:51:19.353927 RD_PRE = 0x0
5020 23:51:19.354006 WR_PRE = 0x1
5021 23:51:19.357311 WR_PST = 0x0
5022 23:51:19.357391 DBI_WR = 0x0
5023 23:51:19.361047 DBI_RD = 0x0
5024 23:51:19.361152 OTF = 0x1
5025 23:51:19.363772 ===================================
5026 23:51:19.367027 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5027 23:51:19.373479 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5028 23:51:19.377343 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 23:51:19.380883 ===================================
5030 23:51:19.383620 LPDDR4 DRAM CONFIGURATION
5031 23:51:19.386757 ===================================
5032 23:51:19.386839 EX_ROW_EN[0] = 0x10
5033 23:51:19.390473 EX_ROW_EN[1] = 0x0
5034 23:51:19.390554 LP4Y_EN = 0x0
5035 23:51:19.394055 WORK_FSP = 0x0
5036 23:51:19.394136 WL = 0x3
5037 23:51:19.397172 RL = 0x3
5038 23:51:19.397254 BL = 0x2
5039 23:51:19.400457 RPST = 0x0
5040 23:51:19.400538 RD_PRE = 0x0
5041 23:51:19.403929 WR_PRE = 0x1
5042 23:51:19.404009 WR_PST = 0x0
5043 23:51:19.407285 DBI_WR = 0x0
5044 23:51:19.410631 DBI_RD = 0x0
5045 23:51:19.410712 OTF = 0x1
5046 23:51:19.414566 ===================================
5047 23:51:19.420564 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5048 23:51:19.423974 nWR fixed to 30
5049 23:51:19.427879 [ModeRegInit_LP4] CH0 RK0
5050 23:51:19.427960 [ModeRegInit_LP4] CH0 RK1
5051 23:51:19.430537 [ModeRegInit_LP4] CH1 RK0
5052 23:51:19.434641 [ModeRegInit_LP4] CH1 RK1
5053 23:51:19.434722 match AC timing 9
5054 23:51:19.441108 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5055 23:51:19.443763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5056 23:51:19.447705 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5057 23:51:19.453977 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5058 23:51:19.457188 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5059 23:51:19.457269 ==
5060 23:51:19.461025 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 23:51:19.464079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 23:51:19.464160 ==
5063 23:51:19.470430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 23:51:19.477545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 23:51:19.480629 [CA 0] Center 38 (8~69) winsize 62
5066 23:51:19.483799 [CA 1] Center 38 (7~69) winsize 63
5067 23:51:19.487123 [CA 2] Center 35 (5~66) winsize 62
5068 23:51:19.491109 [CA 3] Center 35 (5~66) winsize 62
5069 23:51:19.493964 [CA 4] Center 34 (4~65) winsize 62
5070 23:51:19.497388 [CA 5] Center 34 (4~64) winsize 61
5071 23:51:19.497470
5072 23:51:19.500471 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 23:51:19.500552
5074 23:51:19.504076 [CATrainingPosCal] consider 1 rank data
5075 23:51:19.507124 u2DelayCellTimex100 = 270/100 ps
5076 23:51:19.510923 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5077 23:51:19.513867 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5078 23:51:19.517181 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5079 23:51:19.520332 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5080 23:51:19.523796 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5081 23:51:19.527064 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5082 23:51:19.527147
5083 23:51:19.533731 CA PerBit enable=1, Macro0, CA PI delay=34
5084 23:51:19.533813
5085 23:51:19.533877 [CBTSetCACLKResult] CA Dly = 34
5086 23:51:19.537410 CS Dly: 6 (0~37)
5087 23:51:19.537491 ==
5088 23:51:19.541258 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 23:51:19.543812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 23:51:19.543915 ==
5091 23:51:19.550700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 23:51:19.557642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5093 23:51:19.560984 [CA 0] Center 38 (7~69) winsize 63
5094 23:51:19.563883 [CA 1] Center 38 (7~69) winsize 63
5095 23:51:19.567192 [CA 2] Center 35 (5~66) winsize 62
5096 23:51:19.570242 [CA 3] Center 35 (4~66) winsize 63
5097 23:51:19.573789 [CA 4] Center 34 (4~65) winsize 62
5098 23:51:19.578311 [CA 5] Center 33 (3~64) winsize 62
5099 23:51:19.578393
5100 23:51:19.580463 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5101 23:51:19.580544
5102 23:51:19.583892 [CATrainingPosCal] consider 2 rank data
5103 23:51:19.588167 u2DelayCellTimex100 = 270/100 ps
5104 23:51:19.591261 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5105 23:51:19.593855 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5106 23:51:19.597206 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5107 23:51:19.600622 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5108 23:51:19.603969 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5109 23:51:19.607486 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5110 23:51:19.607567
5111 23:51:19.614568 CA PerBit enable=1, Macro0, CA PI delay=34
5112 23:51:19.614650
5113 23:51:19.614714 [CBTSetCACLKResult] CA Dly = 34
5114 23:51:19.617491 CS Dly: 7 (0~39)
5115 23:51:19.617571
5116 23:51:19.620162 ----->DramcWriteLeveling(PI) begin...
5117 23:51:19.620244 ==
5118 23:51:19.624403 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 23:51:19.627278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 23:51:19.627405 ==
5121 23:51:19.630660 Write leveling (Byte 0): 29 => 29
5122 23:51:19.633576 Write leveling (Byte 1): 29 => 29
5123 23:51:19.637126 DramcWriteLeveling(PI) end<-----
5124 23:51:19.637254
5125 23:51:19.637369 ==
5126 23:51:19.640452 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 23:51:19.643855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 23:51:19.647128 ==
5129 23:51:19.647250 [Gating] SW mode calibration
5130 23:51:19.654109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5131 23:51:19.660531 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5132 23:51:19.663540 0 14 0 | B1->B0 | 2323 2a2a | 0 1 | (1 1) (1 1)
5133 23:51:19.670832 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5134 23:51:19.673867 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 23:51:19.677929 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 23:51:19.684187 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 23:51:19.687325 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 23:51:19.690933 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 23:51:19.698266 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5140 23:51:19.701376 0 15 0 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
5141 23:51:19.704078 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5142 23:51:19.707162 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 23:51:19.713796 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 23:51:19.717219 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 23:51:19.720475 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 23:51:19.727691 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 23:51:19.730830 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5148 23:51:19.734025 1 0 0 | B1->B0 | 2626 3838 | 0 1 | (1 1) (0 0)
5149 23:51:19.740844 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:51:19.743744 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 23:51:19.748024 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 23:51:19.754453 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 23:51:19.757544 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 23:51:19.762521 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 23:51:19.767341 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 23:51:19.771290 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5157 23:51:19.773987 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5158 23:51:19.781318 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:51:19.784052 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:51:19.787536 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:51:19.790493 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:51:19.797507 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:51:19.800426 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:51:19.804042 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:51:19.811017 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:51:19.814104 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:51:19.817404 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:51:19.824375 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:51:19.827442 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 23:51:19.831181 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 23:51:19.837575 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5172 23:51:19.841486 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5173 23:51:19.844656 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 23:51:19.847888 Total UI for P1: 0, mck2ui 16
5175 23:51:19.851322 best dqsien dly found for B0: ( 1, 3, 2)
5176 23:51:19.854315 Total UI for P1: 0, mck2ui 16
5177 23:51:19.857403 best dqsien dly found for B1: ( 1, 2, 30)
5178 23:51:19.860598 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5179 23:51:19.864086 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5180 23:51:19.864190
5181 23:51:19.867306 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5182 23:51:19.874481 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5183 23:51:19.874592 [Gating] SW calibration Done
5184 23:51:19.874685 ==
5185 23:51:19.877720 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 23:51:19.884326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 23:51:19.884435 ==
5188 23:51:19.884526 RX Vref Scan: 0
5189 23:51:19.884613
5190 23:51:19.887228 RX Vref 0 -> 0, step: 1
5191 23:51:19.887331
5192 23:51:19.890572 RX Delay -80 -> 252, step: 8
5193 23:51:19.893835 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5194 23:51:19.897696 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5195 23:51:19.900437 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5196 23:51:19.904265 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5197 23:51:19.910753 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5198 23:51:19.914105 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5199 23:51:19.917385 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5200 23:51:19.920835 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5201 23:51:19.924782 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5202 23:51:19.927355 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5203 23:51:19.933708 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5204 23:51:19.937504 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5205 23:51:19.940413 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5206 23:51:19.943865 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5207 23:51:19.947606 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5208 23:51:19.950577 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5209 23:51:19.953855 ==
5210 23:51:19.957334 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 23:51:19.960971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 23:51:19.961100 ==
5213 23:51:19.961192 DQS Delay:
5214 23:51:19.963996 DQS0 = 0, DQS1 = 0
5215 23:51:19.964098 DQM Delay:
5216 23:51:19.967503 DQM0 = 99, DQM1 = 87
5217 23:51:19.967605 DQ Delay:
5218 23:51:19.971015 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5219 23:51:19.975610 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5220 23:51:19.979727 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5221 23:51:19.981640 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5222 23:51:19.981746
5223 23:51:19.981839
5224 23:51:19.981951 ==
5225 23:51:19.984057 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 23:51:19.987216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 23:51:19.987324 ==
5228 23:51:19.987415
5229 23:51:19.987503
5230 23:51:19.990815 TX Vref Scan disable
5231 23:51:19.994332 == TX Byte 0 ==
5232 23:51:19.998178 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5233 23:51:20.000787 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5234 23:51:20.004963 == TX Byte 1 ==
5235 23:51:20.007457 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5236 23:51:20.010720 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5237 23:51:20.010855 ==
5238 23:51:20.013932 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 23:51:20.018330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 23:51:20.021029 ==
5241 23:51:20.021155
5242 23:51:20.021267
5243 23:51:20.021383 TX Vref Scan disable
5244 23:51:20.024073 == TX Byte 0 ==
5245 23:51:20.027950 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5246 23:51:20.035065 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5247 23:51:20.035200 == TX Byte 1 ==
5248 23:51:20.038428 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5249 23:51:20.040823 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5250 23:51:20.044657
5251 23:51:20.044788 [DATLAT]
5252 23:51:20.044908 Freq=933, CH0 RK0
5253 23:51:20.045067
5254 23:51:20.048068 DATLAT Default: 0xd
5255 23:51:20.048199 0, 0xFFFF, sum = 0
5256 23:51:20.051584 1, 0xFFFF, sum = 0
5257 23:51:20.051716 2, 0xFFFF, sum = 0
5258 23:51:20.054225 3, 0xFFFF, sum = 0
5259 23:51:20.054357 4, 0xFFFF, sum = 0
5260 23:51:20.057695 5, 0xFFFF, sum = 0
5261 23:51:20.057824 6, 0xFFFF, sum = 0
5262 23:51:20.061113 7, 0xFFFF, sum = 0
5263 23:51:20.064901 8, 0xFFFF, sum = 0
5264 23:51:20.065060 9, 0xFFFF, sum = 0
5265 23:51:20.067595 10, 0x0, sum = 1
5266 23:51:20.067728 11, 0x0, sum = 2
5267 23:51:20.067857 12, 0x0, sum = 3
5268 23:51:20.071097 13, 0x0, sum = 4
5269 23:51:20.071225 best_step = 11
5270 23:51:20.071347
5271 23:51:20.071465 ==
5272 23:51:20.074328 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 23:51:20.081651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 23:51:20.081783 ==
5275 23:51:20.081902 RX Vref Scan: 1
5276 23:51:20.082014
5277 23:51:20.085480 RX Vref 0 -> 0, step: 1
5278 23:51:20.085614
5279 23:51:20.088534 RX Delay -61 -> 252, step: 4
5280 23:51:20.088656
5281 23:51:20.090930 Set Vref, RX VrefLevel [Byte0]: 53
5282 23:51:20.094549 [Byte1]: 56
5283 23:51:20.094683
5284 23:51:20.097800 Final RX Vref Byte 0 = 53 to rank0
5285 23:51:20.100918 Final RX Vref Byte 1 = 56 to rank0
5286 23:51:20.104842 Final RX Vref Byte 0 = 53 to rank1
5287 23:51:20.108165 Final RX Vref Byte 1 = 56 to rank1==
5288 23:51:20.111231 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 23:51:20.114534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 23:51:20.114669 ==
5291 23:51:20.117934 DQS Delay:
5292 23:51:20.118068 DQS0 = 0, DQS1 = 0
5293 23:51:20.118188 DQM Delay:
5294 23:51:20.121175 DQM0 = 97, DQM1 = 89
5295 23:51:20.121305 DQ Delay:
5296 23:51:20.124673 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96
5297 23:51:20.127724 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =104
5298 23:51:20.132180 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =80
5299 23:51:20.134609 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =98
5300 23:51:20.134741
5301 23:51:20.134861
5302 23:51:20.144613 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5303 23:51:20.148757 CH0 RK0: MR19=504, MR18=10FC
5304 23:51:20.151384 CH0_RK0: MR19=0x504, MR18=0x10FC, DQSOSC=416, MR23=63, INC=62, DEC=41
5305 23:51:20.151514
5306 23:51:20.155024 ----->DramcWriteLeveling(PI) begin...
5307 23:51:20.157776 ==
5308 23:51:20.161385 Dram Type= 6, Freq= 0, CH_0, rank 1
5309 23:51:20.164348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 23:51:20.164476 ==
5311 23:51:20.167865 Write leveling (Byte 0): 32 => 32
5312 23:51:20.171952 Write leveling (Byte 1): 30 => 30
5313 23:51:20.174484 DramcWriteLeveling(PI) end<-----
5314 23:51:20.174566
5315 23:51:20.174629 ==
5316 23:51:20.177682 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 23:51:20.181670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 23:51:20.181775 ==
5319 23:51:20.184756 [Gating] SW mode calibration
5320 23:51:20.191056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5321 23:51:20.194827 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5322 23:51:20.201512 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5323 23:51:20.204610 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5324 23:51:20.208226 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 23:51:20.215726 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 23:51:20.217881 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 23:51:20.221512 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 23:51:20.228757 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5329 23:51:20.231339 0 14 28 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
5330 23:51:20.234613 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5331 23:51:20.241320 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 23:51:20.244368 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 23:51:20.248177 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 23:51:20.254596 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 23:51:20.257698 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 23:51:20.261095 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 23:51:20.267836 0 15 28 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
5338 23:51:20.272100 1 0 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5339 23:51:20.275166 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 23:51:20.278246 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:51:20.284649 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 23:51:20.288734 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 23:51:20.291326 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 23:51:20.298196 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 23:51:20.301289 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5346 23:51:20.304720 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5347 23:51:20.312082 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 23:51:20.315064 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:51:20.319171 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:51:20.324851 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:51:20.327867 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:51:20.331251 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:51:20.337888 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:51:20.341824 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:51:20.344546 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:51:20.351302 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:51:20.355047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:51:20.358251 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 23:51:20.364782 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 23:51:20.368413 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 23:51:20.371734 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5362 23:51:20.375533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5363 23:51:20.381687 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 23:51:20.384741 Total UI for P1: 0, mck2ui 16
5365 23:51:20.387836 best dqsien dly found for B0: ( 1, 2, 30)
5366 23:51:20.392273 Total UI for P1: 0, mck2ui 16
5367 23:51:20.394885 best dqsien dly found for B1: ( 1, 3, 2)
5368 23:51:20.399260 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5369 23:51:20.401360 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5370 23:51:20.401465
5371 23:51:20.405550 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5372 23:51:20.407873 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5373 23:51:20.411471 [Gating] SW calibration Done
5374 23:51:20.411575 ==
5375 23:51:20.414812 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 23:51:20.419035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 23:51:20.419142 ==
5378 23:51:20.421339 RX Vref Scan: 0
5379 23:51:20.421443
5380 23:51:20.421533 RX Vref 0 -> 0, step: 1
5381 23:51:20.421622
5382 23:51:20.424596 RX Delay -80 -> 252, step: 8
5383 23:51:20.428542 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5384 23:51:20.434801 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5385 23:51:20.438130 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5386 23:51:20.441582 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5387 23:51:20.444801 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5388 23:51:20.448351 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5389 23:51:20.451642 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5390 23:51:20.455376 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5391 23:51:20.461886 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5392 23:51:20.464813 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5393 23:51:20.468619 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5394 23:51:20.471641 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5395 23:51:20.475113 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5396 23:51:20.481598 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5397 23:51:20.485008 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5398 23:51:20.488675 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5399 23:51:20.488775 ==
5400 23:51:20.492124 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 23:51:20.495384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 23:51:20.495489 ==
5403 23:51:20.498305 DQS Delay:
5404 23:51:20.498410 DQS0 = 0, DQS1 = 0
5405 23:51:20.498500 DQM Delay:
5406 23:51:20.502130 DQM0 = 96, DQM1 = 87
5407 23:51:20.502234 DQ Delay:
5408 23:51:20.505231 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5409 23:51:20.508649 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5410 23:51:20.511396 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =79
5411 23:51:20.515141 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5412 23:51:20.515241
5413 23:51:20.515330
5414 23:51:20.515416 ==
5415 23:51:20.518728 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 23:51:20.525267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 23:51:20.525374 ==
5418 23:51:20.525465
5419 23:51:20.525552
5420 23:51:20.525639 TX Vref Scan disable
5421 23:51:20.528411 == TX Byte 0 ==
5422 23:51:20.532799 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5423 23:51:20.536680 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5424 23:51:20.538242 == TX Byte 1 ==
5425 23:51:20.541908 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5426 23:51:20.544904 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5427 23:51:20.548712 ==
5428 23:51:20.551547 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 23:51:20.555469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 23:51:20.555572 ==
5431 23:51:20.555657
5432 23:51:20.555740
5433 23:51:20.558339 TX Vref Scan disable
5434 23:51:20.558443 == TX Byte 0 ==
5435 23:51:20.564890 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5436 23:51:20.568229 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5437 23:51:20.568335 == TX Byte 1 ==
5438 23:51:20.574982 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5439 23:51:20.578941 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5440 23:51:20.579045
5441 23:51:20.579135 [DATLAT]
5442 23:51:20.581418 Freq=933, CH0 RK1
5443 23:51:20.581521
5444 23:51:20.581616 DATLAT Default: 0xb
5445 23:51:20.585162 0, 0xFFFF, sum = 0
5446 23:51:20.585269 1, 0xFFFF, sum = 0
5447 23:51:20.588553 2, 0xFFFF, sum = 0
5448 23:51:20.588658 3, 0xFFFF, sum = 0
5449 23:51:20.591733 4, 0xFFFF, sum = 0
5450 23:51:20.591837 5, 0xFFFF, sum = 0
5451 23:51:20.596080 6, 0xFFFF, sum = 0
5452 23:51:20.596184 7, 0xFFFF, sum = 0
5453 23:51:20.599719 8, 0xFFFF, sum = 0
5454 23:51:20.601944 9, 0xFFFF, sum = 0
5455 23:51:20.602048 10, 0x0, sum = 1
5456 23:51:20.602141 11, 0x0, sum = 2
5457 23:51:20.605306 12, 0x0, sum = 3
5458 23:51:20.605412 13, 0x0, sum = 4
5459 23:51:20.608918 best_step = 11
5460 23:51:20.609060
5461 23:51:20.609151 ==
5462 23:51:20.612092 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 23:51:20.615185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 23:51:20.615291 ==
5465 23:51:20.618393 RX Vref Scan: 0
5466 23:51:20.618496
5467 23:51:20.618579 RX Vref 0 -> 0, step: 1
5468 23:51:20.618666
5469 23:51:20.621736 RX Delay -61 -> 252, step: 4
5470 23:51:20.629421 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5471 23:51:20.631888 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5472 23:51:20.635499 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5473 23:51:20.639073 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5474 23:51:20.642707 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5475 23:51:20.646116 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5476 23:51:20.652493 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5477 23:51:20.656719 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5478 23:51:20.659278 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5479 23:51:20.662077 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5480 23:51:20.665615 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5481 23:51:20.669053 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5482 23:51:20.675794 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5483 23:51:20.678692 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5484 23:51:20.682577 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5485 23:51:20.685716 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5486 23:51:20.685819 ==
5487 23:51:20.689044 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 23:51:20.692401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 23:51:20.695696 ==
5490 23:51:20.695803 DQS Delay:
5491 23:51:20.695894 DQS0 = 0, DQS1 = 0
5492 23:51:20.699307 DQM Delay:
5493 23:51:20.699411 DQM0 = 95, DQM1 = 88
5494 23:51:20.702400 DQ Delay:
5495 23:51:20.702502 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5496 23:51:20.706543 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =102
5497 23:51:20.709265 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5498 23:51:20.712511 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5499 23:51:20.712614
5500 23:51:20.715591
5501 23:51:20.722093 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5502 23:51:20.725877 CH0 RK1: MR19=505, MR18=1A08
5503 23:51:20.732419 CH0_RK1: MR19=0x505, MR18=0x1A08, DQSOSC=413, MR23=63, INC=63, DEC=42
5504 23:51:20.732527 [RxdqsGatingPostProcess] freq 933
5505 23:51:20.739697 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5506 23:51:20.742378 best DQS0 dly(2T, 0.5T) = (0, 11)
5507 23:51:20.745560 best DQS1 dly(2T, 0.5T) = (0, 10)
5508 23:51:20.751200 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5509 23:51:20.752401 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5510 23:51:20.755845 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 23:51:20.759756 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 23:51:20.762811 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 23:51:20.765670 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 23:51:20.769375 Pre-setting of DQS Precalculation
5515 23:51:20.772425 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5516 23:51:20.772527 ==
5517 23:51:20.775846 Dram Type= 6, Freq= 0, CH_1, rank 0
5518 23:51:20.779745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 23:51:20.779850 ==
5520 23:51:20.786461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 23:51:20.792632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5522 23:51:20.795781 [CA 0] Center 36 (6~67) winsize 62
5523 23:51:20.799376 [CA 1] Center 36 (6~67) winsize 62
5524 23:51:20.803040 [CA 2] Center 34 (4~64) winsize 61
5525 23:51:20.805777 [CA 3] Center 33 (3~64) winsize 62
5526 23:51:20.809168 [CA 4] Center 33 (3~64) winsize 62
5527 23:51:20.812487 [CA 5] Center 33 (3~64) winsize 62
5528 23:51:20.812587
5529 23:51:20.816108 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5530 23:51:20.816214
5531 23:51:20.818942 [CATrainingPosCal] consider 1 rank data
5532 23:51:20.822447 u2DelayCellTimex100 = 270/100 ps
5533 23:51:20.826172 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 23:51:20.829504 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 23:51:20.832725 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5536 23:51:20.836612 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 23:51:20.839277 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 23:51:20.842380 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5539 23:51:20.842488
5540 23:51:20.850335 CA PerBit enable=1, Macro0, CA PI delay=33
5541 23:51:20.850442
5542 23:51:20.852942 [CBTSetCACLKResult] CA Dly = 33
5543 23:51:20.853049 CS Dly: 4 (0~35)
5544 23:51:20.853142 ==
5545 23:51:20.855802 Dram Type= 6, Freq= 0, CH_1, rank 1
5546 23:51:20.859284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 23:51:20.859388 ==
5548 23:51:20.866158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 23:51:20.872814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5550 23:51:20.875891 [CA 0] Center 36 (6~67) winsize 62
5551 23:51:20.879623 [CA 1] Center 36 (6~67) winsize 62
5552 23:51:20.883374 [CA 2] Center 33 (3~64) winsize 62
5553 23:51:20.886165 [CA 3] Center 33 (3~64) winsize 62
5554 23:51:20.889154 [CA 4] Center 34 (4~64) winsize 61
5555 23:51:20.892829 [CA 5] Center 33 (2~64) winsize 63
5556 23:51:20.892931
5557 23:51:20.896531 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5558 23:51:20.896634
5559 23:51:20.899260 [CATrainingPosCal] consider 2 rank data
5560 23:51:20.902392 u2DelayCellTimex100 = 270/100 ps
5561 23:51:20.906094 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 23:51:20.909603 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 23:51:20.912624 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 23:51:20.915780 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5565 23:51:20.919442 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 23:51:20.922390 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5567 23:51:20.922493
5568 23:51:20.929295 CA PerBit enable=1, Macro0, CA PI delay=33
5569 23:51:20.929399
5570 23:51:20.929490 [CBTSetCACLKResult] CA Dly = 33
5571 23:51:20.932910 CS Dly: 5 (0~38)
5572 23:51:20.933019
5573 23:51:20.936298 ----->DramcWriteLeveling(PI) begin...
5574 23:51:20.936404 ==
5575 23:51:20.939105 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 23:51:20.942403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 23:51:20.942507 ==
5578 23:51:20.947068 Write leveling (Byte 0): 26 => 26
5579 23:51:20.949150 Write leveling (Byte 1): 31 => 31
5580 23:51:20.953148 DramcWriteLeveling(PI) end<-----
5581 23:51:20.953252
5582 23:51:20.953342 ==
5583 23:51:20.956571 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 23:51:20.959384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 23:51:20.964008 ==
5586 23:51:20.964112 [Gating] SW mode calibration
5587 23:51:20.972400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5588 23:51:20.975795 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5589 23:51:20.979590 0 14 0 | B1->B0 | 3030 3232 | 1 1 | (0 0) (0 0)
5590 23:51:20.985692 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 23:51:20.989692 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 23:51:20.992730 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 23:51:20.999964 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5594 23:51:21.002652 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5595 23:51:21.005654 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5596 23:51:21.012876 0 14 28 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
5597 23:51:21.016612 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5598 23:51:21.019160 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:51:21.026522 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 23:51:21.029445 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5601 23:51:21.032531 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 23:51:21.036444 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5603 23:51:21.042787 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 23:51:21.045777 0 15 28 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
5605 23:51:21.049292 1 0 0 | B1->B0 | 4141 3e3e | 0 0 | (0 0) (0 0)
5606 23:51:21.056117 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:51:21.059323 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 23:51:21.062678 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 23:51:21.069796 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 23:51:21.072916 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 23:51:21.076554 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 23:51:21.082606 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5613 23:51:21.085871 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:51:21.089928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:51:21.096351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:51:21.099356 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:51:21.102822 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:51:21.109602 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:51:21.113352 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:51:21.116310 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:51:21.120101 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:51:21.125876 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:51:21.129792 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:51:21.133264 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:51:21.139853 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:51:21.142724 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:51:21.145936 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 23:51:21.152915 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5629 23:51:21.156773 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 23:51:21.159253 Total UI for P1: 0, mck2ui 16
5631 23:51:21.162512 best dqsien dly found for B0: ( 1, 2, 28)
5632 23:51:21.166532 Total UI for P1: 0, mck2ui 16
5633 23:51:21.169343 best dqsien dly found for B1: ( 1, 2, 30)
5634 23:51:21.172836 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5635 23:51:21.176004 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5636 23:51:21.176106
5637 23:51:21.179771 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5638 23:51:21.183156 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5639 23:51:21.186529 [Gating] SW calibration Done
5640 23:51:21.186630 ==
5641 23:51:21.189290 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 23:51:21.192899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 23:51:21.196359 ==
5644 23:51:21.196464 RX Vref Scan: 0
5645 23:51:21.196555
5646 23:51:21.199880 RX Vref 0 -> 0, step: 1
5647 23:51:21.199984
5648 23:51:21.200075 RX Delay -80 -> 252, step: 8
5649 23:51:21.206054 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5650 23:51:21.210102 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5651 23:51:21.213119 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5652 23:51:21.216380 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5653 23:51:21.220268 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5654 23:51:21.223732 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5655 23:51:21.229877 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5656 23:51:21.233207 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5657 23:51:21.237315 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5658 23:51:21.239919 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5659 23:51:21.243104 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5660 23:51:21.249653 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5661 23:51:21.253692 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5662 23:51:21.256358 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5663 23:51:21.260390 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5664 23:51:21.263196 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5665 23:51:21.263301 ==
5666 23:51:21.266076 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 23:51:21.272925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 23:51:21.273071 ==
5669 23:51:21.273161 DQS Delay:
5670 23:51:21.273254 DQS0 = 0, DQS1 = 0
5671 23:51:21.275893 DQM Delay:
5672 23:51:21.275994 DQM0 = 95, DQM1 = 89
5673 23:51:21.279866 DQ Delay:
5674 23:51:21.282664 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =95
5675 23:51:21.286532 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5676 23:51:21.290060 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =87
5677 23:51:21.292568 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5678 23:51:21.292669
5679 23:51:21.292760
5680 23:51:21.292847 ==
5681 23:51:21.296387 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 23:51:21.299149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 23:51:21.299256 ==
5684 23:51:21.299346
5685 23:51:21.299450
5686 23:51:21.302568 TX Vref Scan disable
5687 23:51:21.302672 == TX Byte 0 ==
5688 23:51:21.310313 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5689 23:51:21.313050 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5690 23:51:21.313154 == TX Byte 1 ==
5691 23:51:21.319404 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5692 23:51:21.322869 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5693 23:51:21.322971 ==
5694 23:51:21.326542 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 23:51:21.329734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 23:51:21.329842 ==
5697 23:51:21.329934
5698 23:51:21.330022
5699 23:51:21.333797 TX Vref Scan disable
5700 23:51:21.336561 == TX Byte 0 ==
5701 23:51:21.340302 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 23:51:21.343898 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 23:51:21.346188 == TX Byte 1 ==
5704 23:51:21.349783 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5705 23:51:21.352762 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5706 23:51:21.352868
5707 23:51:21.356203 [DATLAT]
5708 23:51:21.356308 Freq=933, CH1 RK0
5709 23:51:21.356400
5710 23:51:21.359357 DATLAT Default: 0xd
5711 23:51:21.359461 0, 0xFFFF, sum = 0
5712 23:51:21.363114 1, 0xFFFF, sum = 0
5713 23:51:21.363220 2, 0xFFFF, sum = 0
5714 23:51:21.366638 3, 0xFFFF, sum = 0
5715 23:51:21.366747 4, 0xFFFF, sum = 0
5716 23:51:21.369126 5, 0xFFFF, sum = 0
5717 23:51:21.369232 6, 0xFFFF, sum = 0
5718 23:51:21.373499 7, 0xFFFF, sum = 0
5719 23:51:21.373604 8, 0xFFFF, sum = 0
5720 23:51:21.376375 9, 0xFFFF, sum = 0
5721 23:51:21.376481 10, 0x0, sum = 1
5722 23:51:21.379272 11, 0x0, sum = 2
5723 23:51:21.379376 12, 0x0, sum = 3
5724 23:51:21.382877 13, 0x0, sum = 4
5725 23:51:21.382984 best_step = 11
5726 23:51:21.383072
5727 23:51:21.383156 ==
5728 23:51:21.385897 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 23:51:21.392499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 23:51:21.392600 ==
5731 23:51:21.392696 RX Vref Scan: 1
5732 23:51:21.392785
5733 23:51:21.395960 RX Vref 0 -> 0, step: 1
5734 23:51:21.396065
5735 23:51:21.399949 RX Delay -69 -> 252, step: 4
5736 23:51:21.400054
5737 23:51:21.402901 Set Vref, RX VrefLevel [Byte0]: 56
5738 23:51:21.405920 [Byte1]: 53
5739 23:51:21.406032
5740 23:51:21.409425 Final RX Vref Byte 0 = 56 to rank0
5741 23:51:21.413073 Final RX Vref Byte 1 = 53 to rank0
5742 23:51:21.417148 Final RX Vref Byte 0 = 56 to rank1
5743 23:51:21.419906 Final RX Vref Byte 1 = 53 to rank1==
5744 23:51:21.423162 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 23:51:21.425747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 23:51:21.425854 ==
5747 23:51:21.429645 DQS Delay:
5748 23:51:21.429747 DQS0 = 0, DQS1 = 0
5749 23:51:21.429836 DQM Delay:
5750 23:51:21.433726 DQM0 = 98, DQM1 = 90
5751 23:51:21.433832 DQ Delay:
5752 23:51:21.437518 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =98
5753 23:51:21.439467 DQ4 =98, DQ5 =108, DQ6 =110, DQ7 =94
5754 23:51:21.442827 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =86
5755 23:51:21.446195 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5756 23:51:21.446300
5757 23:51:21.446391
5758 23:51:21.455611 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5759 23:51:21.460613 CH1 RK0: MR19=504, MR18=15F2
5760 23:51:21.462409 CH1_RK0: MR19=0x504, MR18=0x15F2, DQSOSC=415, MR23=63, INC=62, DEC=41
5761 23:51:21.462511
5762 23:51:21.466057 ----->DramcWriteLeveling(PI) begin...
5763 23:51:21.469053 ==
5764 23:51:21.473548 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 23:51:21.476198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 23:51:21.476289 ==
5767 23:51:21.480028 Write leveling (Byte 0): 28 => 28
5768 23:51:21.482374 Write leveling (Byte 1): 29 => 29
5769 23:51:21.485602 DramcWriteLeveling(PI) end<-----
5770 23:51:21.485693
5771 23:51:21.485757 ==
5772 23:51:21.489010 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 23:51:21.492402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 23:51:21.492486 ==
5775 23:51:21.495916 [Gating] SW mode calibration
5776 23:51:21.502955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5777 23:51:21.509431 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5778 23:51:21.512180 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 23:51:21.515986 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5780 23:51:21.519084 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 23:51:21.525860 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5782 23:51:21.530228 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5783 23:51:21.532801 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 23:51:21.539629 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (1 0) (1 1)
5785 23:51:21.542521 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5786 23:51:21.546377 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 23:51:21.552412 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 23:51:21.557157 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 23:51:21.559930 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 23:51:21.565718 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 23:51:21.569935 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5792 23:51:21.572351 0 15 24 | B1->B0 | 2a2a 3636 | 0 0 | (1 1) (0 0)
5793 23:51:21.579309 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5794 23:51:21.582905 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:51:21.585811 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 23:51:21.593016 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 23:51:21.596409 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 23:51:21.599133 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 23:51:21.605848 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 23:51:21.608947 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5801 23:51:21.612311 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:51:21.616324 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:51:21.622192 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:51:21.625808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:51:21.628908 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:51:21.636832 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:51:21.639426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:51:21.642619 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:51:21.649714 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:51:21.652250 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:51:21.655939 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:51:21.663200 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:51:21.665945 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:51:21.669691 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 23:51:21.675955 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 23:51:21.679532 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5817 23:51:21.682336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 23:51:21.686094 Total UI for P1: 0, mck2ui 16
5819 23:51:21.689215 best dqsien dly found for B0: ( 1, 2, 24)
5820 23:51:21.692463 Total UI for P1: 0, mck2ui 16
5821 23:51:21.695898 best dqsien dly found for B1: ( 1, 2, 26)
5822 23:51:21.699863 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5823 23:51:21.702096 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5824 23:51:21.702203
5825 23:51:21.706006 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5826 23:51:21.712824 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5827 23:51:21.712945 [Gating] SW calibration Done
5828 23:51:21.713061 ==
5829 23:51:21.716953 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 23:51:21.722318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 23:51:21.722407 ==
5832 23:51:21.722472 RX Vref Scan: 0
5833 23:51:21.722537
5834 23:51:21.726006 RX Vref 0 -> 0, step: 1
5835 23:51:21.726092
5836 23:51:21.730179 RX Delay -80 -> 252, step: 8
5837 23:51:21.732499 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5838 23:51:21.735943 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5839 23:51:21.739638 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5840 23:51:21.742323 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5841 23:51:21.749182 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5842 23:51:21.752300 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5843 23:51:21.755927 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5844 23:51:21.759278 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5845 23:51:21.762776 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5846 23:51:21.765864 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5847 23:51:21.772540 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5848 23:51:21.776596 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5849 23:51:21.779163 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5850 23:51:21.782431 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5851 23:51:21.785645 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5852 23:51:21.789139 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5853 23:51:21.792389 ==
5854 23:51:21.795664 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 23:51:21.799158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 23:51:21.799253 ==
5857 23:51:21.799318 DQS Delay:
5858 23:51:21.802478 DQS0 = 0, DQS1 = 0
5859 23:51:21.802563 DQM Delay:
5860 23:51:21.807849 DQM0 = 94, DQM1 = 89
5861 23:51:21.807932 DQ Delay:
5862 23:51:21.809171 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5863 23:51:21.812428 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5864 23:51:21.816081 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5865 23:51:21.820175 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5866 23:51:21.820262
5867 23:51:21.820325
5868 23:51:21.820382 ==
5869 23:51:21.823112 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 23:51:21.825598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 23:51:21.825680 ==
5872 23:51:21.825744
5873 23:51:21.825802
5874 23:51:21.829522 TX Vref Scan disable
5875 23:51:21.832288 == TX Byte 0 ==
5876 23:51:21.837332 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5877 23:51:21.838886 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5878 23:51:21.842925 == TX Byte 1 ==
5879 23:51:21.845923 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5880 23:51:21.849226 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5881 23:51:21.849337 ==
5882 23:51:21.853119 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 23:51:21.855863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 23:51:21.858892 ==
5885 23:51:21.858974
5886 23:51:21.859036
5887 23:51:21.859094 TX Vref Scan disable
5888 23:51:21.863105 == TX Byte 0 ==
5889 23:51:21.865869 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5890 23:51:21.872605 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5891 23:51:21.872714 == TX Byte 1 ==
5892 23:51:21.875949 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5893 23:51:21.882484 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5894 23:51:21.882577
5895 23:51:21.882640 [DATLAT]
5896 23:51:21.882699 Freq=933, CH1 RK1
5897 23:51:21.882758
5898 23:51:21.886160 DATLAT Default: 0xb
5899 23:51:21.886242 0, 0xFFFF, sum = 0
5900 23:51:21.889047 1, 0xFFFF, sum = 0
5901 23:51:21.889131 2, 0xFFFF, sum = 0
5902 23:51:21.892959 3, 0xFFFF, sum = 0
5903 23:51:21.896318 4, 0xFFFF, sum = 0
5904 23:51:21.896403 5, 0xFFFF, sum = 0
5905 23:51:21.899365 6, 0xFFFF, sum = 0
5906 23:51:21.899449 7, 0xFFFF, sum = 0
5907 23:51:21.902698 8, 0xFFFF, sum = 0
5908 23:51:21.902783 9, 0xFFFF, sum = 0
5909 23:51:21.906094 10, 0x0, sum = 1
5910 23:51:21.906177 11, 0x0, sum = 2
5911 23:51:21.909362 12, 0x0, sum = 3
5912 23:51:21.909445 13, 0x0, sum = 4
5913 23:51:21.909510 best_step = 11
5914 23:51:21.909568
5915 23:51:21.912861 ==
5916 23:51:21.912969 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 23:51:21.919391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 23:51:21.919485 ==
5919 23:51:21.919549 RX Vref Scan: 0
5920 23:51:21.919608
5921 23:51:21.922370 RX Vref 0 -> 0, step: 1
5922 23:51:21.922452
5923 23:51:21.926599 RX Delay -61 -> 252, step: 4
5924 23:51:21.929151 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5925 23:51:21.935814 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5926 23:51:21.939349 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5927 23:51:21.942477 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5928 23:51:21.945692 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5929 23:51:21.949352 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5930 23:51:21.954185 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5931 23:51:21.959328 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5932 23:51:21.962851 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5933 23:51:21.965962 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5934 23:51:21.969199 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5935 23:51:21.972704 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5936 23:51:21.975766 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5937 23:51:21.982863 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5938 23:51:21.985994 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5939 23:51:21.989956 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5940 23:51:21.990045 ==
5941 23:51:21.992435 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 23:51:21.995695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 23:51:21.999522 ==
5944 23:51:21.999612 DQS Delay:
5945 23:51:21.999675 DQS0 = 0, DQS1 = 0
5946 23:51:22.002271 DQM Delay:
5947 23:51:22.002354 DQM0 = 95, DQM1 = 91
5948 23:51:22.005716 DQ Delay:
5949 23:51:22.005799 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5950 23:51:22.009542 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5951 23:51:22.012474 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5952 23:51:22.019298 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5953 23:51:22.019397
5954 23:51:22.019461
5955 23:51:22.026348 [DQSOSCAuto] RK1, (LSB)MR18= 0x912, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 419 ps
5956 23:51:22.029342 CH1 RK1: MR19=505, MR18=912
5957 23:51:22.036551 CH1_RK1: MR19=0x505, MR18=0x912, DQSOSC=416, MR23=63, INC=62, DEC=41
5958 23:51:22.036653 [RxdqsGatingPostProcess] freq 933
5959 23:51:22.042608 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5960 23:51:22.045999 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 23:51:22.049254 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 23:51:22.052743 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 23:51:22.056798 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 23:51:22.060001 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 23:51:22.062497 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 23:51:22.065508 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 23:51:22.069413 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 23:51:22.072489 Pre-setting of DQS Precalculation
5969 23:51:22.075596 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5970 23:51:22.082265 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5971 23:51:22.088720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5972 23:51:22.092312
5973 23:51:22.092413
5974 23:51:22.092478 [Calibration Summary] 1866 Mbps
5975 23:51:22.095894 CH 0, Rank 0
5976 23:51:22.095986 SW Impedance : PASS
5977 23:51:22.099306 DUTY Scan : NO K
5978 23:51:22.102316 ZQ Calibration : PASS
5979 23:51:22.102421 Jitter Meter : NO K
5980 23:51:22.106093 CBT Training : PASS
5981 23:51:22.109529 Write leveling : PASS
5982 23:51:22.109630 RX DQS gating : PASS
5983 23:51:22.112284 RX DQ/DQS(RDDQC) : PASS
5984 23:51:22.115618 TX DQ/DQS : PASS
5985 23:51:22.115712 RX DATLAT : PASS
5986 23:51:22.119267 RX DQ/DQS(Engine): PASS
5987 23:51:22.122428 TX OE : NO K
5988 23:51:22.122520 All Pass.
5989 23:51:22.122584
5990 23:51:22.122643 CH 0, Rank 1
5991 23:51:22.125819 SW Impedance : PASS
5992 23:51:22.129295 DUTY Scan : NO K
5993 23:51:22.129397 ZQ Calibration : PASS
5994 23:51:22.133534 Jitter Meter : NO K
5995 23:51:22.133629 CBT Training : PASS
5996 23:51:22.135528 Write leveling : PASS
5997 23:51:22.138853 RX DQS gating : PASS
5998 23:51:22.138943 RX DQ/DQS(RDDQC) : PASS
5999 23:51:22.142380 TX DQ/DQS : PASS
6000 23:51:22.146178 RX DATLAT : PASS
6001 23:51:22.146274 RX DQ/DQS(Engine): PASS
6002 23:51:22.148992 TX OE : NO K
6003 23:51:22.149077 All Pass.
6004 23:51:22.149143
6005 23:51:22.153100 CH 1, Rank 0
6006 23:51:22.153188 SW Impedance : PASS
6007 23:51:22.155895 DUTY Scan : NO K
6008 23:51:22.159147 ZQ Calibration : PASS
6009 23:51:22.159236 Jitter Meter : NO K
6010 23:51:22.162265 CBT Training : PASS
6011 23:51:22.165755 Write leveling : PASS
6012 23:51:22.165862 RX DQS gating : PASS
6013 23:51:22.169555 RX DQ/DQS(RDDQC) : PASS
6014 23:51:22.169642 TX DQ/DQS : PASS
6015 23:51:22.172296 RX DATLAT : PASS
6016 23:51:22.176178 RX DQ/DQS(Engine): PASS
6017 23:51:22.176278 TX OE : NO K
6018 23:51:22.179188 All Pass.
6019 23:51:22.179278
6020 23:51:22.179344 CH 1, Rank 1
6021 23:51:22.182410 SW Impedance : PASS
6022 23:51:22.182497 DUTY Scan : NO K
6023 23:51:22.185899 ZQ Calibration : PASS
6024 23:51:22.189762 Jitter Meter : NO K
6025 23:51:22.189869 CBT Training : PASS
6026 23:51:22.192760 Write leveling : PASS
6027 23:51:22.196160 RX DQS gating : PASS
6028 23:51:22.196268 RX DQ/DQS(RDDQC) : PASS
6029 23:51:22.199358 TX DQ/DQS : PASS
6030 23:51:22.203135 RX DATLAT : PASS
6031 23:51:22.203245 RX DQ/DQS(Engine): PASS
6032 23:51:22.205644 TX OE : NO K
6033 23:51:22.205731 All Pass.
6034 23:51:22.205796
6035 23:51:22.208929 DramC Write-DBI off
6036 23:51:22.213213 PER_BANK_REFRESH: Hybrid Mode
6037 23:51:22.213319 TX_TRACKING: ON
6038 23:51:22.222235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6039 23:51:22.225678 [FAST_K] Save calibration result to emmc
6040 23:51:22.229431 dramc_set_vcore_voltage set vcore to 650000
6041 23:51:22.232652 Read voltage for 400, 6
6042 23:51:22.232776 Vio18 = 0
6043 23:51:22.232869 Vcore = 650000
6044 23:51:22.235790 Vdram = 0
6045 23:51:22.235877 Vddq = 0
6046 23:51:22.235940 Vmddr = 0
6047 23:51:22.243250 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6048 23:51:22.246037 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6049 23:51:22.249082 MEM_TYPE=3, freq_sel=20
6050 23:51:22.253458 sv_algorithm_assistance_LP4_800
6051 23:51:22.256086 ============ PULL DRAM RESETB DOWN ============
6052 23:51:22.259073 ========== PULL DRAM RESETB DOWN end =========
6053 23:51:22.266170 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6054 23:51:22.268941 ===================================
6055 23:51:22.269052 LPDDR4 DRAM CONFIGURATION
6056 23:51:22.272848 ===================================
6057 23:51:22.276063 EX_ROW_EN[0] = 0x0
6058 23:51:22.276168 EX_ROW_EN[1] = 0x0
6059 23:51:22.279199 LP4Y_EN = 0x0
6060 23:51:22.282270 WORK_FSP = 0x0
6061 23:51:22.282364 WL = 0x2
6062 23:51:22.285690 RL = 0x2
6063 23:51:22.285796 BL = 0x2
6064 23:51:22.288888 RPST = 0x0
6065 23:51:22.289012 RD_PRE = 0x0
6066 23:51:22.292121 WR_PRE = 0x1
6067 23:51:22.292212 WR_PST = 0x0
6068 23:51:22.295762 DBI_WR = 0x0
6069 23:51:22.295855 DBI_RD = 0x0
6070 23:51:22.299217 OTF = 0x1
6071 23:51:22.302480 ===================================
6072 23:51:22.305997 ===================================
6073 23:51:22.306109 ANA top config
6074 23:51:22.309275 ===================================
6075 23:51:22.312626 DLL_ASYNC_EN = 0
6076 23:51:22.315783 ALL_SLAVE_EN = 1
6077 23:51:22.315882 NEW_RANK_MODE = 1
6078 23:51:22.319328 DLL_IDLE_MODE = 1
6079 23:51:22.323065 LP45_APHY_COMB_EN = 1
6080 23:51:22.325574 TX_ODT_DIS = 1
6081 23:51:22.325683 NEW_8X_MODE = 1
6082 23:51:22.329072 ===================================
6083 23:51:22.332989 ===================================
6084 23:51:22.335760 data_rate = 800
6085 23:51:22.339121 CKR = 1
6086 23:51:22.343421 DQ_P2S_RATIO = 4
6087 23:51:22.346019 ===================================
6088 23:51:22.349780 CA_P2S_RATIO = 4
6089 23:51:22.352858 DQ_CA_OPEN = 0
6090 23:51:22.352987 DQ_SEMI_OPEN = 1
6091 23:51:22.355647 CA_SEMI_OPEN = 1
6092 23:51:22.359039 CA_FULL_RATE = 0
6093 23:51:22.362868 DQ_CKDIV4_EN = 0
6094 23:51:22.367426 CA_CKDIV4_EN = 1
6095 23:51:22.369182 CA_PREDIV_EN = 0
6096 23:51:22.369277 PH8_DLY = 0
6097 23:51:22.372843 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6098 23:51:22.375554 DQ_AAMCK_DIV = 0
6099 23:51:22.379578 CA_AAMCK_DIV = 0
6100 23:51:22.382717 CA_ADMCK_DIV = 4
6101 23:51:22.386484 DQ_TRACK_CA_EN = 0
6102 23:51:22.386589 CA_PICK = 800
6103 23:51:22.388883 CA_MCKIO = 400
6104 23:51:22.392647 MCKIO_SEMI = 400
6105 23:51:22.395805 PLL_FREQ = 3016
6106 23:51:22.398970 DQ_UI_PI_RATIO = 32
6107 23:51:22.402101 CA_UI_PI_RATIO = 32
6108 23:51:22.406297 ===================================
6109 23:51:22.409288 ===================================
6110 23:51:22.412518 memory_type:LPDDR4
6111 23:51:22.412630 GP_NUM : 10
6112 23:51:22.415405 SRAM_EN : 1
6113 23:51:22.415495 MD32_EN : 0
6114 23:51:22.419166 ===================================
6115 23:51:22.422424 [ANA_INIT] >>>>>>>>>>>>>>
6116 23:51:22.426007 <<<<<< [CONFIGURE PHASE]: ANA_TX
6117 23:51:22.429245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6118 23:51:22.432314 ===================================
6119 23:51:22.435622 data_rate = 800,PCW = 0X7400
6120 23:51:22.439419 ===================================
6121 23:51:22.442052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6122 23:51:22.445546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 23:51:22.458979 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 23:51:22.462233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6125 23:51:22.465902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6126 23:51:22.469342 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6127 23:51:22.472577 [ANA_INIT] flow start
6128 23:51:22.476855 [ANA_INIT] PLL >>>>>>>>
6129 23:51:22.477022 [ANA_INIT] PLL <<<<<<<<
6130 23:51:22.479179 [ANA_INIT] MIDPI >>>>>>>>
6131 23:51:22.482378 [ANA_INIT] MIDPI <<<<<<<<
6132 23:51:22.482483 [ANA_INIT] DLL >>>>>>>>
6133 23:51:22.486876 [ANA_INIT] flow end
6134 23:51:22.488811 ============ LP4 DIFF to SE enter ============
6135 23:51:22.493290 ============ LP4 DIFF to SE exit ============
6136 23:51:22.496604 [ANA_INIT] <<<<<<<<<<<<<
6137 23:51:22.499936 [Flow] Enable top DCM control >>>>>
6138 23:51:22.502669 [Flow] Enable top DCM control <<<<<
6139 23:51:22.505350 Enable DLL master slave shuffle
6140 23:51:22.512397 ==============================================================
6141 23:51:22.512536 Gating Mode config
6142 23:51:22.519886 ==============================================================
6143 23:51:22.520029 Config description:
6144 23:51:22.528921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6145 23:51:22.535609 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6146 23:51:22.541990 SELPH_MODE 0: By rank 1: By Phase
6147 23:51:22.545276 ==============================================================
6148 23:51:22.548665 GAT_TRACK_EN = 0
6149 23:51:22.551849 RX_GATING_MODE = 2
6150 23:51:22.556062 RX_GATING_TRACK_MODE = 2
6151 23:51:22.559331 SELPH_MODE = 1
6152 23:51:22.561954 PICG_EARLY_EN = 1
6153 23:51:22.565637 VALID_LAT_VALUE = 1
6154 23:51:22.572122 ==============================================================
6155 23:51:22.576014 Enter into Gating configuration >>>>
6156 23:51:22.579204 Exit from Gating configuration <<<<
6157 23:51:22.579316 Enter into DVFS_PRE_config >>>>>
6158 23:51:22.592626 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6159 23:51:22.596258 Exit from DVFS_PRE_config <<<<<
6160 23:51:22.598720 Enter into PICG configuration >>>>
6161 23:51:22.601949 Exit from PICG configuration <<<<
6162 23:51:22.602068 [RX_INPUT] configuration >>>>>
6163 23:51:22.605796 [RX_INPUT] configuration <<<<<
6164 23:51:22.611860 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6165 23:51:22.618245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6166 23:51:22.622751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 23:51:22.628516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 23:51:22.635340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6169 23:51:22.642875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6170 23:51:22.645191 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6171 23:51:22.649031 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6172 23:51:22.652229 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6173 23:51:22.658494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6174 23:51:22.661898 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6175 23:51:22.665426 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 23:51:22.668787 ===================================
6177 23:51:22.672704 LPDDR4 DRAM CONFIGURATION
6178 23:51:22.675128 ===================================
6179 23:51:22.679741 EX_ROW_EN[0] = 0x0
6180 23:51:22.679870 EX_ROW_EN[1] = 0x0
6181 23:51:22.683216 LP4Y_EN = 0x0
6182 23:51:22.683315 WORK_FSP = 0x0
6183 23:51:22.685294 WL = 0x2
6184 23:51:22.685383 RL = 0x2
6185 23:51:22.688945 BL = 0x2
6186 23:51:22.689054 RPST = 0x0
6187 23:51:22.692170 RD_PRE = 0x0
6188 23:51:22.692261 WR_PRE = 0x1
6189 23:51:22.695209 WR_PST = 0x0
6190 23:51:22.695301 DBI_WR = 0x0
6191 23:51:22.698969 DBI_RD = 0x0
6192 23:51:22.699074 OTF = 0x1
6193 23:51:22.702045 ===================================
6194 23:51:22.705525 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6195 23:51:22.712742 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6196 23:51:22.715559 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 23:51:22.718591 ===================================
6198 23:51:22.722589 LPDDR4 DRAM CONFIGURATION
6199 23:51:22.725835 ===================================
6200 23:51:22.725946 EX_ROW_EN[0] = 0x10
6201 23:51:22.729242 EX_ROW_EN[1] = 0x0
6202 23:51:22.731861 LP4Y_EN = 0x0
6203 23:51:22.731959 WORK_FSP = 0x0
6204 23:51:22.735425 WL = 0x2
6205 23:51:22.735540 RL = 0x2
6206 23:51:22.739110 BL = 0x2
6207 23:51:22.739210 RPST = 0x0
6208 23:51:22.742263 RD_PRE = 0x0
6209 23:51:22.742356 WR_PRE = 0x1
6210 23:51:22.745515 WR_PST = 0x0
6211 23:51:22.745609 DBI_WR = 0x0
6212 23:51:22.748950 DBI_RD = 0x0
6213 23:51:22.749086 OTF = 0x1
6214 23:51:22.753362 ===================================
6215 23:51:22.759471 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6216 23:51:22.762608 nWR fixed to 30
6217 23:51:22.766573 [ModeRegInit_LP4] CH0 RK0
6218 23:51:22.766688 [ModeRegInit_LP4] CH0 RK1
6219 23:51:22.769595 [ModeRegInit_LP4] CH1 RK0
6220 23:51:22.773015 [ModeRegInit_LP4] CH1 RK1
6221 23:51:22.773149 match AC timing 19
6222 23:51:22.780023 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6223 23:51:22.783009 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6224 23:51:22.787216 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6225 23:51:22.793144 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6226 23:51:22.796775 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6227 23:51:22.796893 ==
6228 23:51:22.799778 Dram Type= 6, Freq= 0, CH_0, rank 0
6229 23:51:22.802793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 23:51:22.802911 ==
6231 23:51:22.809383 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 23:51:22.815989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 23:51:22.819711 [CA 0] Center 36 (8~64) winsize 57
6234 23:51:22.823228 [CA 1] Center 36 (8~64) winsize 57
6235 23:51:22.823357 [CA 2] Center 36 (8~64) winsize 57
6236 23:51:22.826124 [CA 3] Center 36 (8~64) winsize 57
6237 23:51:22.830401 [CA 4] Center 36 (8~64) winsize 57
6238 23:51:22.832860 [CA 5] Center 36 (8~64) winsize 57
6239 23:51:22.832956
6240 23:51:22.836341 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 23:51:22.839930
6242 23:51:22.843166 [CATrainingPosCal] consider 1 rank data
6243 23:51:22.843273 u2DelayCellTimex100 = 270/100 ps
6244 23:51:22.849679 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:51:22.853120 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 23:51:22.856149 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 23:51:22.859564 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 23:51:22.862918 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 23:51:22.866199 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 23:51:22.866312
6251 23:51:22.869805 CA PerBit enable=1, Macro0, CA PI delay=36
6252 23:51:22.869912
6253 23:51:22.873032 [CBTSetCACLKResult] CA Dly = 36
6254 23:51:22.876725 CS Dly: 1 (0~32)
6255 23:51:22.876840 ==
6256 23:51:22.879623 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 23:51:22.883255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 23:51:22.883364 ==
6259 23:51:22.887268 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6260 23:51:22.892967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6261 23:51:22.896087 [CA 0] Center 36 (8~64) winsize 57
6262 23:51:22.899775 [CA 1] Center 36 (8~64) winsize 57
6263 23:51:22.902623 [CA 2] Center 36 (8~64) winsize 57
6264 23:51:22.906875 [CA 3] Center 36 (8~64) winsize 57
6265 23:51:22.910238 [CA 4] Center 36 (8~64) winsize 57
6266 23:51:22.912895 [CA 5] Center 36 (8~64) winsize 57
6267 23:51:22.913035
6268 23:51:22.916687 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6269 23:51:22.916806
6270 23:51:22.920127 [CATrainingPosCal] consider 2 rank data
6271 23:51:22.923276 u2DelayCellTimex100 = 270/100 ps
6272 23:51:22.926438 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:51:22.929652 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:51:22.933033 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:51:22.936406 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:51:22.940684 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:51:22.947376 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 23:51:22.947509
6279 23:51:22.949625 CA PerBit enable=1, Macro0, CA PI delay=36
6280 23:51:22.949713
6281 23:51:22.953375 [CBTSetCACLKResult] CA Dly = 36
6282 23:51:22.953476 CS Dly: 1 (0~32)
6283 23:51:22.953541
6284 23:51:22.956184 ----->DramcWriteLeveling(PI) begin...
6285 23:51:22.956274 ==
6286 23:51:22.959466 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 23:51:22.962939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 23:51:22.966318 ==
6289 23:51:22.966424 Write leveling (Byte 0): 40 => 8
6290 23:51:22.969659 Write leveling (Byte 1): 32 => 0
6291 23:51:22.972800 DramcWriteLeveling(PI) end<-----
6292 23:51:22.972911
6293 23:51:22.973009 ==
6294 23:51:22.976007 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 23:51:22.982956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 23:51:22.983136 ==
6297 23:51:22.983208 [Gating] SW mode calibration
6298 23:51:22.992992 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6299 23:51:22.996192 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6300 23:51:23.000362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 23:51:23.005988 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 23:51:23.009255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 23:51:23.013324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 23:51:23.020179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 23:51:23.022776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 23:51:23.026159 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 23:51:23.033064 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 23:51:23.036009 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 23:51:23.039366 Total UI for P1: 0, mck2ui 16
6310 23:51:23.043179 best dqsien dly found for B0: ( 0, 14, 24)
6311 23:51:23.046906 Total UI for P1: 0, mck2ui 16
6312 23:51:23.049192 best dqsien dly found for B1: ( 0, 14, 24)
6313 23:51:23.052921 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6314 23:51:23.055958 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6315 23:51:23.056059
6316 23:51:23.059288 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 23:51:23.062529 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 23:51:23.066836 [Gating] SW calibration Done
6319 23:51:23.066954 ==
6320 23:51:23.069301 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 23:51:23.076312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 23:51:23.076457 ==
6323 23:51:23.076526 RX Vref Scan: 0
6324 23:51:23.076587
6325 23:51:23.079276 RX Vref 0 -> 0, step: 1
6326 23:51:23.079366
6327 23:51:23.082696 RX Delay -410 -> 252, step: 16
6328 23:51:23.085910 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6329 23:51:23.089731 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6330 23:51:23.092742 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6331 23:51:23.101169 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6332 23:51:23.103217 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6333 23:51:23.105792 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6334 23:51:23.109570 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6335 23:51:23.115775 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6336 23:51:23.119412 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6337 23:51:23.123020 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6338 23:51:23.126060 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6339 23:51:23.133154 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6340 23:51:23.136082 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6341 23:51:23.139884 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6342 23:51:23.143656 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6343 23:51:23.149585 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6344 23:51:23.149714 ==
6345 23:51:23.153286 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 23:51:23.156209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 23:51:23.156311 ==
6348 23:51:23.156377 DQS Delay:
6349 23:51:23.159955 DQS0 = 35, DQS1 = 51
6350 23:51:23.160049 DQM Delay:
6351 23:51:23.162593 DQM0 = 8, DQM1 = 11
6352 23:51:23.162680 DQ Delay:
6353 23:51:23.167057 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6354 23:51:23.169774 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6355 23:51:23.173146 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6356 23:51:23.176243 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6357 23:51:23.176367
6358 23:51:23.176434
6359 23:51:23.176492 ==
6360 23:51:23.179481 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 23:51:23.182952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 23:51:23.183056 ==
6363 23:51:23.183121
6364 23:51:23.183180
6365 23:51:23.186273 TX Vref Scan disable
6366 23:51:23.186366 == TX Byte 0 ==
6367 23:51:23.193502 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 23:51:23.196116 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 23:51:23.196220 == TX Byte 1 ==
6370 23:51:23.202877 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6371 23:51:23.206025 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6372 23:51:23.206143 ==
6373 23:51:23.211450 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 23:51:23.212823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 23:51:23.212937 ==
6376 23:51:23.213058
6377 23:51:23.213119
6378 23:51:23.216209 TX Vref Scan disable
6379 23:51:23.219957 == TX Byte 0 ==
6380 23:51:23.222978 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 23:51:23.226096 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 23:51:23.226197 == TX Byte 1 ==
6383 23:51:23.232882 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6384 23:51:23.237278 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6385 23:51:23.237405
6386 23:51:23.237473 [DATLAT]
6387 23:51:23.239884 Freq=400, CH0 RK0
6388 23:51:23.239971
6389 23:51:23.240035 DATLAT Default: 0xf
6390 23:51:23.243043 0, 0xFFFF, sum = 0
6391 23:51:23.243139 1, 0xFFFF, sum = 0
6392 23:51:23.246749 2, 0xFFFF, sum = 0
6393 23:51:23.246851 3, 0xFFFF, sum = 0
6394 23:51:23.249370 4, 0xFFFF, sum = 0
6395 23:51:23.253169 5, 0xFFFF, sum = 0
6396 23:51:23.253288 6, 0xFFFF, sum = 0
6397 23:51:23.256286 7, 0xFFFF, sum = 0
6398 23:51:23.256379 8, 0xFFFF, sum = 0
6399 23:51:23.259383 9, 0xFFFF, sum = 0
6400 23:51:23.259476 10, 0xFFFF, sum = 0
6401 23:51:23.263291 11, 0xFFFF, sum = 0
6402 23:51:23.263393 12, 0xFFFF, sum = 0
6403 23:51:23.266461 13, 0x0, sum = 1
6404 23:51:23.266555 14, 0x0, sum = 2
6405 23:51:23.269696 15, 0x0, sum = 3
6406 23:51:23.269788 16, 0x0, sum = 4
6407 23:51:23.269854 best_step = 14
6408 23:51:23.269914
6409 23:51:23.273059 ==
6410 23:51:23.276188 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 23:51:23.279916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 23:51:23.280041 ==
6413 23:51:23.280106 RX Vref Scan: 1
6414 23:51:23.280166
6415 23:51:23.283102 RX Vref 0 -> 0, step: 1
6416 23:51:23.283189
6417 23:51:23.286330 RX Delay -343 -> 252, step: 8
6418 23:51:23.286420
6419 23:51:23.290129 Set Vref, RX VrefLevel [Byte0]: 53
6420 23:51:23.293355 [Byte1]: 56
6421 23:51:23.296666
6422 23:51:23.300125 Final RX Vref Byte 0 = 53 to rank0
6423 23:51:23.300235 Final RX Vref Byte 1 = 56 to rank0
6424 23:51:23.303376 Final RX Vref Byte 0 = 53 to rank1
6425 23:51:23.307976 Final RX Vref Byte 1 = 56 to rank1==
6426 23:51:23.310080 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 23:51:23.316488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 23:51:23.316629 ==
6429 23:51:23.316698 DQS Delay:
6430 23:51:23.320271 DQS0 = 44, DQS1 = 60
6431 23:51:23.320374 DQM Delay:
6432 23:51:23.320440 DQM0 = 11, DQM1 = 14
6433 23:51:23.323000 DQ Delay:
6434 23:51:23.328073 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6435 23:51:23.328201 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6436 23:51:23.329650 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6437 23:51:23.336683 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6438 23:51:23.336815
6439 23:51:23.336883
6440 23:51:23.343322 [DQSOSCAuto] RK0, (LSB)MR18= 0x8250, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6441 23:51:23.346221 CH0 RK0: MR19=C0C, MR18=8250
6442 23:51:23.352911 CH0_RK0: MR19=0xC0C, MR18=0x8250, DQSOSC=393, MR23=63, INC=382, DEC=254
6443 23:51:23.353092 ==
6444 23:51:23.356260 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 23:51:23.361027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 23:51:23.361156 ==
6447 23:51:23.362692 [Gating] SW mode calibration
6448 23:51:23.370132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6449 23:51:23.376712 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6450 23:51:23.380099 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 23:51:23.383121 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 23:51:23.389839 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 23:51:23.393461 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 23:51:23.396071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 23:51:23.399687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 23:51:23.406721 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 23:51:23.409367 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 23:51:23.413486 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 23:51:23.416269 Total UI for P1: 0, mck2ui 16
6460 23:51:23.420195 best dqsien dly found for B0: ( 0, 14, 24)
6461 23:51:23.423790 Total UI for P1: 0, mck2ui 16
6462 23:51:23.426995 best dqsien dly found for B1: ( 0, 14, 24)
6463 23:51:23.429625 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6464 23:51:23.433418 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6465 23:51:23.436656
6466 23:51:23.439730 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 23:51:23.442885 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 23:51:23.446636 [Gating] SW calibration Done
6469 23:51:23.446749 ==
6470 23:51:23.449805 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 23:51:23.453230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 23:51:23.453347 ==
6473 23:51:23.453412 RX Vref Scan: 0
6474 23:51:23.453473
6475 23:51:23.456934 RX Vref 0 -> 0, step: 1
6476 23:51:23.457052
6477 23:51:23.460202 RX Delay -410 -> 252, step: 16
6478 23:51:23.463289 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6479 23:51:23.470412 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6480 23:51:23.473363 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6481 23:51:23.476347 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6482 23:51:23.479978 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6483 23:51:23.484421 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6484 23:51:23.489882 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6485 23:51:23.493234 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6486 23:51:23.496900 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6487 23:51:23.500113 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6488 23:51:23.507265 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6489 23:51:23.509996 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6490 23:51:23.513459 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6491 23:51:23.519822 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6492 23:51:23.523310 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6493 23:51:23.526571 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6494 23:51:23.526688 ==
6495 23:51:23.529887 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 23:51:23.532922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 23:51:23.533047 ==
6498 23:51:23.536904 DQS Delay:
6499 23:51:23.537038 DQS0 = 43, DQS1 = 51
6500 23:51:23.540160 DQM Delay:
6501 23:51:23.540249 DQM0 = 11, DQM1 = 10
6502 23:51:23.540313 DQ Delay:
6503 23:51:23.543669 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6504 23:51:23.546236 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6505 23:51:23.551443 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6506 23:51:23.553263 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6507 23:51:23.553352
6508 23:51:23.553417
6509 23:51:23.553476 ==
6510 23:51:23.556652 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 23:51:23.563953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 23:51:23.564098 ==
6513 23:51:23.564166
6514 23:51:23.564254
6515 23:51:23.564309 TX Vref Scan disable
6516 23:51:23.566272 == TX Byte 0 ==
6517 23:51:23.569753 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6518 23:51:23.573269 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6519 23:51:23.576635 == TX Byte 1 ==
6520 23:51:23.579573 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6521 23:51:23.583513 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6522 23:51:23.583632 ==
6523 23:51:23.586494 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 23:51:23.593337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 23:51:23.593491 ==
6526 23:51:23.593588
6527 23:51:23.593669
6528 23:51:23.593746 TX Vref Scan disable
6529 23:51:23.596575 == TX Byte 0 ==
6530 23:51:23.600277 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6531 23:51:23.603565 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6532 23:51:23.606393 == TX Byte 1 ==
6533 23:51:23.609755 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6534 23:51:23.613335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6535 23:51:23.613445
6536 23:51:23.616276 [DATLAT]
6537 23:51:23.616368 Freq=400, CH0 RK1
6538 23:51:23.616434
6539 23:51:23.619727 DATLAT Default: 0xe
6540 23:51:23.619822 0, 0xFFFF, sum = 0
6541 23:51:23.623163 1, 0xFFFF, sum = 0
6542 23:51:23.623262 2, 0xFFFF, sum = 0
6543 23:51:23.626660 3, 0xFFFF, sum = 0
6544 23:51:23.626757 4, 0xFFFF, sum = 0
6545 23:51:23.629796 5, 0xFFFF, sum = 0
6546 23:51:23.629892 6, 0xFFFF, sum = 0
6547 23:51:23.633155 7, 0xFFFF, sum = 0
6548 23:51:23.633257 8, 0xFFFF, sum = 0
6549 23:51:23.636722 9, 0xFFFF, sum = 0
6550 23:51:23.636826 10, 0xFFFF, sum = 0
6551 23:51:23.639524 11, 0xFFFF, sum = 0
6552 23:51:23.639616 12, 0xFFFF, sum = 0
6553 23:51:23.643037 13, 0x0, sum = 1
6554 23:51:23.643132 14, 0x0, sum = 2
6555 23:51:23.646595 15, 0x0, sum = 3
6556 23:51:23.646697 16, 0x0, sum = 4
6557 23:51:23.650918 best_step = 14
6558 23:51:23.651022
6559 23:51:23.651088 ==
6560 23:51:23.653455 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 23:51:23.656118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 23:51:23.656213 ==
6563 23:51:23.659897 RX Vref Scan: 0
6564 23:51:23.660004
6565 23:51:23.660070 RX Vref 0 -> 0, step: 1
6566 23:51:23.660130
6567 23:51:23.663281 RX Delay -343 -> 252, step: 8
6568 23:51:23.671503 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6569 23:51:23.674102 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6570 23:51:23.677522 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6571 23:51:23.680840 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6572 23:51:23.688154 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6573 23:51:23.691109 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6574 23:51:23.694401 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6575 23:51:23.698768 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6576 23:51:23.705013 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6577 23:51:23.707919 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6578 23:51:23.710982 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6579 23:51:23.714179 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6580 23:51:23.721357 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6581 23:51:23.724864 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6582 23:51:23.728915 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6583 23:51:23.731406 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6584 23:51:23.734347 ==
6585 23:51:23.738071 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 23:51:23.741947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 23:51:23.742075 ==
6588 23:51:23.742144 DQS Delay:
6589 23:51:23.744376 DQS0 = 48, DQS1 = 56
6590 23:51:23.744461 DQM Delay:
6591 23:51:23.747750 DQM0 = 12, DQM1 = 10
6592 23:51:23.747843 DQ Delay:
6593 23:51:23.751303 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6594 23:51:23.755175 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6595 23:51:23.757916 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6596 23:51:23.761208 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6597 23:51:23.761321
6598 23:51:23.761387
6599 23:51:23.768168 [DQSOSCAuto] RK1, (LSB)MR18= 0x966b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6600 23:51:23.771857 CH0 RK1: MR19=C0C, MR18=966B
6601 23:51:23.777767 CH0_RK1: MR19=0xC0C, MR18=0x966B, DQSOSC=391, MR23=63, INC=386, DEC=257
6602 23:51:23.781340 [RxdqsGatingPostProcess] freq 400
6603 23:51:23.785826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6604 23:51:23.787723 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 23:51:23.792128 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 23:51:23.794338 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 23:51:23.797698 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 23:51:23.801666 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 23:51:23.805173 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 23:51:23.807575 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 23:51:23.810977 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 23:51:23.814425 Pre-setting of DQS Precalculation
6613 23:51:23.818030 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6614 23:51:23.818154 ==
6615 23:51:23.821959 Dram Type= 6, Freq= 0, CH_1, rank 0
6616 23:51:23.828186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 23:51:23.828329 ==
6618 23:51:23.831160 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 23:51:23.838543 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 23:51:23.841717 [CA 0] Center 36 (8~64) winsize 57
6621 23:51:23.845022 [CA 1] Center 36 (8~64) winsize 57
6622 23:51:23.848600 [CA 2] Center 36 (8~64) winsize 57
6623 23:51:23.851683 [CA 3] Center 36 (8~64) winsize 57
6624 23:51:23.854173 [CA 4] Center 36 (8~64) winsize 57
6625 23:51:23.857945 [CA 5] Center 36 (8~64) winsize 57
6626 23:51:23.858065
6627 23:51:23.861723 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 23:51:23.861833
6629 23:51:23.864566 [CATrainingPosCal] consider 1 rank data
6630 23:51:23.868368 u2DelayCellTimex100 = 270/100 ps
6631 23:51:23.871017 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:51:23.874732 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 23:51:23.878528 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 23:51:23.881434 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 23:51:23.884358 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 23:51:23.887848 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 23:51:23.887961
6638 23:51:23.894590 CA PerBit enable=1, Macro0, CA PI delay=36
6639 23:51:23.894727
6640 23:51:23.897788 [CBTSetCACLKResult] CA Dly = 36
6641 23:51:23.897889 CS Dly: 1 (0~32)
6642 23:51:23.897957 ==
6643 23:51:23.901262 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 23:51:23.904680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 23:51:23.904809 ==
6646 23:51:23.912045 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6647 23:51:23.918550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6648 23:51:23.920947 [CA 0] Center 36 (8~64) winsize 57
6649 23:51:23.924449 [CA 1] Center 36 (8~64) winsize 57
6650 23:51:23.928031 [CA 2] Center 36 (8~64) winsize 57
6651 23:51:23.931366 [CA 3] Center 36 (8~64) winsize 57
6652 23:51:23.931465 [CA 4] Center 36 (8~64) winsize 57
6653 23:51:23.934286 [CA 5] Center 36 (8~64) winsize 57
6654 23:51:23.934377
6655 23:51:23.941332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6656 23:51:23.941471
6657 23:51:23.944571 [CATrainingPosCal] consider 2 rank data
6658 23:51:23.948283 u2DelayCellTimex100 = 270/100 ps
6659 23:51:23.951255 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:51:23.954349 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:51:23.958065 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:51:23.961174 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:51:23.964792 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:51:23.967913 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 23:51:23.968013
6666 23:51:23.971151 CA PerBit enable=1, Macro0, CA PI delay=36
6667 23:51:23.971247
6668 23:51:23.975213 [CBTSetCACLKResult] CA Dly = 36
6669 23:51:23.978064 CS Dly: 1 (0~32)
6670 23:51:23.978183
6671 23:51:23.981306 ----->DramcWriteLeveling(PI) begin...
6672 23:51:23.981406 ==
6673 23:51:23.984713 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 23:51:23.988311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 23:51:23.988421 ==
6676 23:51:23.991834 Write leveling (Byte 0): 40 => 8
6677 23:51:23.995368 Write leveling (Byte 1): 40 => 8
6678 23:51:23.998142 DramcWriteLeveling(PI) end<-----
6679 23:51:23.998247
6680 23:51:23.998312 ==
6681 23:51:24.001349 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 23:51:24.004980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 23:51:24.005129 ==
6684 23:51:24.008006 [Gating] SW mode calibration
6685 23:51:24.014697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6686 23:51:24.021676 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6687 23:51:24.024536 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6688 23:51:24.028347 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6689 23:51:24.034536 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 23:51:24.038224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 23:51:24.041589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 23:51:24.045625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 23:51:24.051374 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 23:51:24.054842 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 23:51:24.058084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 23:51:24.061424 Total UI for P1: 0, mck2ui 16
6697 23:51:24.064949 best dqsien dly found for B0: ( 0, 14, 24)
6698 23:51:24.068424 Total UI for P1: 0, mck2ui 16
6699 23:51:24.071677 best dqsien dly found for B1: ( 0, 14, 24)
6700 23:51:24.075066 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6701 23:51:24.077871 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6702 23:51:24.081297
6703 23:51:24.084703 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 23:51:24.087806 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 23:51:24.091386 [Gating] SW calibration Done
6706 23:51:24.091505 ==
6707 23:51:24.096221 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 23:51:24.098182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 23:51:24.098280 ==
6710 23:51:24.098366 RX Vref Scan: 0
6711 23:51:24.098447
6712 23:51:24.101055 RX Vref 0 -> 0, step: 1
6713 23:51:24.101147
6714 23:51:24.105303 RX Delay -410 -> 252, step: 16
6715 23:51:24.108388 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6716 23:51:24.114506 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6717 23:51:24.118268 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6718 23:51:24.121222 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6719 23:51:24.125327 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6720 23:51:24.131578 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6721 23:51:24.134864 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6722 23:51:24.139234 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6723 23:51:24.142996 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6724 23:51:24.145284 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6725 23:51:24.151441 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6726 23:51:24.154789 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6727 23:51:24.158132 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6728 23:51:24.164857 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6729 23:51:24.167996 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6730 23:51:24.171100 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6731 23:51:24.171208 ==
6732 23:51:24.174537 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 23:51:24.177871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 23:51:24.182576 ==
6735 23:51:24.182716 DQS Delay:
6736 23:51:24.182809 DQS0 = 51, DQS1 = 59
6737 23:51:24.184662 DQM Delay:
6738 23:51:24.184748 DQM0 = 18, DQM1 = 16
6739 23:51:24.188451 DQ Delay:
6740 23:51:24.188556 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6741 23:51:24.191231 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6742 23:51:24.194851 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6743 23:51:24.198116 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6744 23:51:24.198228
6745 23:51:24.198318
6746 23:51:24.201357 ==
6747 23:51:24.201449 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 23:51:24.208750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 23:51:24.208903 ==
6750 23:51:24.209049
6751 23:51:24.209133
6752 23:51:24.211874 TX Vref Scan disable
6753 23:51:24.211965 == TX Byte 0 ==
6754 23:51:24.214832 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 23:51:24.221242 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 23:51:24.221386 == TX Byte 1 ==
6757 23:51:24.224686 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 23:51:24.228128 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 23:51:24.231691 ==
6760 23:51:24.234324 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 23:51:24.237956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 23:51:24.238084 ==
6763 23:51:24.238176
6764 23:51:24.238257
6765 23:51:24.243272 TX Vref Scan disable
6766 23:51:24.243391 == TX Byte 0 ==
6767 23:51:24.244547 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 23:51:24.251011 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 23:51:24.251149 == TX Byte 1 ==
6770 23:51:24.254618 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 23:51:24.261379 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 23:51:24.261526
6773 23:51:24.261621 [DATLAT]
6774 23:51:24.261704 Freq=400, CH1 RK0
6775 23:51:24.261784
6776 23:51:24.264760 DATLAT Default: 0xf
6777 23:51:24.264855 0, 0xFFFF, sum = 0
6778 23:51:24.267841 1, 0xFFFF, sum = 0
6779 23:51:24.267956 2, 0xFFFF, sum = 0
6780 23:51:24.271777 3, 0xFFFF, sum = 0
6781 23:51:24.271885 4, 0xFFFF, sum = 0
6782 23:51:24.274592 5, 0xFFFF, sum = 0
6783 23:51:24.274681 6, 0xFFFF, sum = 0
6784 23:51:24.278575 7, 0xFFFF, sum = 0
6785 23:51:24.281598 8, 0xFFFF, sum = 0
6786 23:51:24.281722 9, 0xFFFF, sum = 0
6787 23:51:24.284920 10, 0xFFFF, sum = 0
6788 23:51:24.285070 11, 0xFFFF, sum = 0
6789 23:51:24.287884 12, 0xFFFF, sum = 0
6790 23:51:24.287975 13, 0x0, sum = 1
6791 23:51:24.292650 14, 0x0, sum = 2
6792 23:51:24.292770 15, 0x0, sum = 3
6793 23:51:24.294556 16, 0x0, sum = 4
6794 23:51:24.294643 best_step = 14
6795 23:51:24.294707
6796 23:51:24.294767 ==
6797 23:51:24.297985 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 23:51:24.301272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 23:51:24.301374 ==
6800 23:51:24.304890 RX Vref Scan: 1
6801 23:51:24.305050
6802 23:51:24.308928 RX Vref 0 -> 0, step: 1
6803 23:51:24.309084
6804 23:51:24.309150 RX Delay -359 -> 252, step: 8
6805 23:51:24.309210
6806 23:51:24.311445 Set Vref, RX VrefLevel [Byte0]: 56
6807 23:51:24.315315 [Byte1]: 53
6808 23:51:24.320071
6809 23:51:24.320196 Final RX Vref Byte 0 = 56 to rank0
6810 23:51:24.323137 Final RX Vref Byte 1 = 53 to rank0
6811 23:51:24.326721 Final RX Vref Byte 0 = 56 to rank1
6812 23:51:24.331245 Final RX Vref Byte 1 = 53 to rank1==
6813 23:51:24.333865 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 23:51:24.339731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 23:51:24.339863 ==
6816 23:51:24.339931 DQS Delay:
6817 23:51:24.344633 DQS0 = 48, DQS1 = 60
6818 23:51:24.344743 DQM Delay:
6819 23:51:24.344807 DQM0 = 13, DQM1 = 13
6820 23:51:24.346600 DQ Delay:
6821 23:51:24.349768 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6822 23:51:24.349865 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6823 23:51:24.353454 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6824 23:51:24.357461 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6825 23:51:24.357574
6826 23:51:24.359960
6827 23:51:24.366962 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6828 23:51:24.370445 CH1 RK0: MR19=C0C, MR18=8A32
6829 23:51:24.376905 CH1_RK0: MR19=0xC0C, MR18=0x8A32, DQSOSC=392, MR23=63, INC=384, DEC=256
6830 23:51:24.377096 ==
6831 23:51:24.380040 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 23:51:24.383384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 23:51:24.383507 ==
6834 23:51:24.387227 [Gating] SW mode calibration
6835 23:51:24.393235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6836 23:51:24.398802 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6837 23:51:24.403132 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6838 23:51:24.406648 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 23:51:24.410291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 23:51:24.416437 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 23:51:24.420674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 23:51:24.423625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 23:51:24.429975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 23:51:24.433496 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 23:51:24.436628 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 23:51:24.440038 Total UI for P1: 0, mck2ui 16
6847 23:51:24.443431 best dqsien dly found for B0: ( 0, 14, 24)
6848 23:51:24.446752 Total UI for P1: 0, mck2ui 16
6849 23:51:24.450041 best dqsien dly found for B1: ( 0, 14, 24)
6850 23:51:24.453870 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6851 23:51:24.457139 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6852 23:51:24.457240
6853 23:51:24.463434 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 23:51:24.466697 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 23:51:24.466808 [Gating] SW calibration Done
6856 23:51:24.470554 ==
6857 23:51:24.473551 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 23:51:24.477088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 23:51:24.477224 ==
6860 23:51:24.477319 RX Vref Scan: 0
6861 23:51:24.477406
6862 23:51:24.481177 RX Vref 0 -> 0, step: 1
6863 23:51:24.481307
6864 23:51:24.483399 RX Delay -410 -> 252, step: 16
6865 23:51:24.487019 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6866 23:51:24.490202 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6867 23:51:24.497237 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6868 23:51:24.501313 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6869 23:51:24.503453 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6870 23:51:24.507425 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6871 23:51:24.513517 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6872 23:51:24.517411 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6873 23:51:24.521167 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6874 23:51:24.523657 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6875 23:51:24.531850 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6876 23:51:24.533426 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6877 23:51:24.536852 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6878 23:51:24.540426 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6879 23:51:24.546880 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6880 23:51:24.551801 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6881 23:51:24.551925 ==
6882 23:51:24.553243 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 23:51:24.557030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 23:51:24.557129 ==
6885 23:51:24.560596 DQS Delay:
6886 23:51:24.560690 DQS0 = 43, DQS1 = 59
6887 23:51:24.564003 DQM Delay:
6888 23:51:24.564092 DQM0 = 11, DQM1 = 18
6889 23:51:24.564155 DQ Delay:
6890 23:51:24.566718 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6891 23:51:24.571308 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6892 23:51:24.574272 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6893 23:51:24.577209 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6894 23:51:24.577314
6895 23:51:24.577380
6896 23:51:24.577438 ==
6897 23:51:24.579867 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 23:51:24.587255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 23:51:24.587394 ==
6900 23:51:24.587462
6901 23:51:24.587521
6902 23:51:24.587577 TX Vref Scan disable
6903 23:51:24.590045 == TX Byte 0 ==
6904 23:51:24.593293 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6905 23:51:24.596942 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6906 23:51:24.599890 == TX Byte 1 ==
6907 23:51:24.603982 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6908 23:51:24.606756 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6909 23:51:24.606875 ==
6910 23:51:24.610006 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 23:51:24.616874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 23:51:24.617070 ==
6913 23:51:24.617138
6914 23:51:24.617197
6915 23:51:24.617253 TX Vref Scan disable
6916 23:51:24.620640 == TX Byte 0 ==
6917 23:51:24.623468 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6918 23:51:24.626572 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6919 23:51:24.630037 == TX Byte 1 ==
6920 23:51:24.633582 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6921 23:51:24.637193 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6922 23:51:24.637307
6923 23:51:24.637371 [DATLAT]
6924 23:51:24.640220 Freq=400, CH1 RK1
6925 23:51:24.640310
6926 23:51:24.643345 DATLAT Default: 0xe
6927 23:51:24.643439 0, 0xFFFF, sum = 0
6928 23:51:24.646854 1, 0xFFFF, sum = 0
6929 23:51:24.646948 2, 0xFFFF, sum = 0
6930 23:51:24.650345 3, 0xFFFF, sum = 0
6931 23:51:24.650442 4, 0xFFFF, sum = 0
6932 23:51:24.653370 5, 0xFFFF, sum = 0
6933 23:51:24.653463 6, 0xFFFF, sum = 0
6934 23:51:24.657171 7, 0xFFFF, sum = 0
6935 23:51:24.657274 8, 0xFFFF, sum = 0
6936 23:51:24.660433 9, 0xFFFF, sum = 0
6937 23:51:24.660528 10, 0xFFFF, sum = 0
6938 23:51:24.663376 11, 0xFFFF, sum = 0
6939 23:51:24.663468 12, 0xFFFF, sum = 0
6940 23:51:24.666864 13, 0x0, sum = 1
6941 23:51:24.666961 14, 0x0, sum = 2
6942 23:51:24.670003 15, 0x0, sum = 3
6943 23:51:24.670094 16, 0x0, sum = 4
6944 23:51:24.673218 best_step = 14
6945 23:51:24.673309
6946 23:51:24.673373 ==
6947 23:51:24.676746 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 23:51:24.680537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 23:51:24.680648 ==
6950 23:51:24.684355 RX Vref Scan: 0
6951 23:51:24.684453
6952 23:51:24.684517 RX Vref 0 -> 0, step: 1
6953 23:51:24.684577
6954 23:51:24.686566 RX Delay -359 -> 252, step: 8
6955 23:51:24.694517 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6956 23:51:24.698229 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6957 23:51:24.701302 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6958 23:51:24.704784 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6959 23:51:24.710959 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6960 23:51:24.714437 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6961 23:51:24.717651 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6962 23:51:24.721242 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6963 23:51:24.728279 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6964 23:51:24.731208 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6965 23:51:24.735426 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6966 23:51:24.738540 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6967 23:51:24.744473 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6968 23:51:24.748263 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6969 23:51:24.751444 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6970 23:51:24.754641 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6971 23:51:24.758286 ==
6972 23:51:24.761563 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 23:51:24.765132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 23:51:24.765242 ==
6975 23:51:24.765308 DQS Delay:
6976 23:51:24.767934 DQS0 = 52, DQS1 = 60
6977 23:51:24.768018 DQM Delay:
6978 23:51:24.771615 DQM0 = 13, DQM1 = 12
6979 23:51:24.771715 DQ Delay:
6980 23:51:24.774695 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6981 23:51:24.778216 DQ4 =16, DQ5 =28, DQ6 =24, DQ7 =8
6982 23:51:24.781260 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6983 23:51:24.784458 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6984 23:51:24.784591
6985 23:51:24.784684
6986 23:51:24.791455 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6987 23:51:24.794519 CH1 RK1: MR19=C0C, MR18=6F85
6988 23:51:24.801130 CH1_RK1: MR19=0xC0C, MR18=0x6F85, DQSOSC=393, MR23=63, INC=382, DEC=254
6989 23:51:24.804951 [RxdqsGatingPostProcess] freq 400
6990 23:51:24.808106 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6991 23:51:24.811163 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 23:51:24.815868 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 23:51:24.817950 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 23:51:24.822357 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 23:51:24.825091 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 23:51:24.827965 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 23:51:24.831011 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 23:51:24.834402 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 23:51:24.837654 Pre-setting of DQS Precalculation
7000 23:51:24.841922 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7001 23:51:24.850947 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7002 23:51:24.857861 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7003 23:51:24.858000
7004 23:51:24.858069
7005 23:51:24.861374 [Calibration Summary] 800 Mbps
7006 23:51:24.861474 CH 0, Rank 0
7007 23:51:24.864831 SW Impedance : PASS
7008 23:51:24.864931 DUTY Scan : NO K
7009 23:51:24.868484 ZQ Calibration : PASS
7010 23:51:24.871026 Jitter Meter : NO K
7011 23:51:24.871124 CBT Training : PASS
7012 23:51:24.874702 Write leveling : PASS
7013 23:51:24.874804 RX DQS gating : PASS
7014 23:51:24.877819 RX DQ/DQS(RDDQC) : PASS
7015 23:51:24.881035 TX DQ/DQS : PASS
7016 23:51:24.881141 RX DATLAT : PASS
7017 23:51:24.885690 RX DQ/DQS(Engine): PASS
7018 23:51:24.888673 TX OE : NO K
7019 23:51:24.888776 All Pass.
7020 23:51:24.888843
7021 23:51:24.888902 CH 0, Rank 1
7022 23:51:24.891440 SW Impedance : PASS
7023 23:51:24.894717 DUTY Scan : NO K
7024 23:51:24.894821 ZQ Calibration : PASS
7025 23:51:24.898710 Jitter Meter : NO K
7026 23:51:24.901294 CBT Training : PASS
7027 23:51:24.901392 Write leveling : NO K
7028 23:51:24.905092 RX DQS gating : PASS
7029 23:51:24.908033 RX DQ/DQS(RDDQC) : PASS
7030 23:51:24.908140 TX DQ/DQS : PASS
7031 23:51:24.911510 RX DATLAT : PASS
7032 23:51:24.911616 RX DQ/DQS(Engine): PASS
7033 23:51:24.915200 TX OE : NO K
7034 23:51:24.915304 All Pass.
7035 23:51:24.915369
7036 23:51:24.919193 CH 1, Rank 0
7037 23:51:24.921481 SW Impedance : PASS
7038 23:51:24.921580 DUTY Scan : NO K
7039 23:51:24.924404 ZQ Calibration : PASS
7040 23:51:24.924498 Jitter Meter : NO K
7041 23:51:24.927927 CBT Training : PASS
7042 23:51:24.931136 Write leveling : PASS
7043 23:51:24.931245 RX DQS gating : PASS
7044 23:51:24.935176 RX DQ/DQS(RDDQC) : PASS
7045 23:51:24.937953 TX DQ/DQS : PASS
7046 23:51:24.938056 RX DATLAT : PASS
7047 23:51:24.941494 RX DQ/DQS(Engine): PASS
7048 23:51:24.944566 TX OE : NO K
7049 23:51:24.944670 All Pass.
7050 23:51:24.944778
7051 23:51:24.944837 CH 1, Rank 1
7052 23:51:24.947681 SW Impedance : PASS
7053 23:51:24.951105 DUTY Scan : NO K
7054 23:51:24.951215 ZQ Calibration : PASS
7055 23:51:24.954281 Jitter Meter : NO K
7056 23:51:24.957499 CBT Training : PASS
7057 23:51:24.957601 Write leveling : NO K
7058 23:51:24.961308 RX DQS gating : PASS
7059 23:51:24.964595 RX DQ/DQS(RDDQC) : PASS
7060 23:51:24.964718 TX DQ/DQS : PASS
7061 23:51:24.969363 RX DATLAT : PASS
7062 23:51:24.969480 RX DQ/DQS(Engine): PASS
7063 23:51:24.971315 TX OE : NO K
7064 23:51:24.971401 All Pass.
7065 23:51:24.971467
7066 23:51:24.974341 DramC Write-DBI off
7067 23:51:24.978080 PER_BANK_REFRESH: Hybrid Mode
7068 23:51:24.978187 TX_TRACKING: ON
7069 23:51:24.988307 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7070 23:51:24.990842 [FAST_K] Save calibration result to emmc
7071 23:51:24.994339 dramc_set_vcore_voltage set vcore to 725000
7072 23:51:24.997605 Read voltage for 1600, 0
7073 23:51:24.997714 Vio18 = 0
7074 23:51:25.001396 Vcore = 725000
7075 23:51:25.001493 Vdram = 0
7076 23:51:25.001558 Vddq = 0
7077 23:51:25.001616 Vmddr = 0
7078 23:51:25.008592 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7079 23:51:25.011238 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7080 23:51:25.014695 MEM_TYPE=3, freq_sel=13
7081 23:51:25.018523 sv_algorithm_assistance_LP4_3733
7082 23:51:25.021480 ============ PULL DRAM RESETB DOWN ============
7083 23:51:25.027825 ========== PULL DRAM RESETB DOWN end =========
7084 23:51:25.030905 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7085 23:51:25.034853 ===================================
7086 23:51:25.037965 LPDDR4 DRAM CONFIGURATION
7087 23:51:25.040894 ===================================
7088 23:51:25.041045 EX_ROW_EN[0] = 0x0
7089 23:51:25.044877 EX_ROW_EN[1] = 0x0
7090 23:51:25.045039 LP4Y_EN = 0x0
7091 23:51:25.048473 WORK_FSP = 0x1
7092 23:51:25.048592 WL = 0x5
7093 23:51:25.050859 RL = 0x5
7094 23:51:25.050948 BL = 0x2
7095 23:51:25.054346 RPST = 0x0
7096 23:51:25.054438 RD_PRE = 0x0
7097 23:51:25.057470 WR_PRE = 0x1
7098 23:51:25.060880 WR_PST = 0x1
7099 23:51:25.061061 DBI_WR = 0x0
7100 23:51:25.063848 DBI_RD = 0x0
7101 23:51:25.063939 OTF = 0x1
7102 23:51:25.067915 ===================================
7103 23:51:25.071024 ===================================
7104 23:51:25.071158 ANA top config
7105 23:51:25.074362 ===================================
7106 23:51:25.077235 DLL_ASYNC_EN = 0
7107 23:51:25.080675 ALL_SLAVE_EN = 0
7108 23:51:25.084180 NEW_RANK_MODE = 1
7109 23:51:25.087847 DLL_IDLE_MODE = 1
7110 23:51:25.087961 LP45_APHY_COMB_EN = 1
7111 23:51:25.091062 TX_ODT_DIS = 0
7112 23:51:25.094578 NEW_8X_MODE = 1
7113 23:51:25.097583 ===================================
7114 23:51:25.100766 ===================================
7115 23:51:25.104130 data_rate = 3200
7116 23:51:25.107644 CKR = 1
7117 23:51:25.107771 DQ_P2S_RATIO = 8
7118 23:51:25.110803 ===================================
7119 23:51:25.114467 CA_P2S_RATIO = 8
7120 23:51:25.117907 DQ_CA_OPEN = 0
7121 23:51:25.120963 DQ_SEMI_OPEN = 0
7122 23:51:25.124169 CA_SEMI_OPEN = 0
7123 23:51:25.124278 CA_FULL_RATE = 0
7124 23:51:25.128331 DQ_CKDIV4_EN = 0
7125 23:51:25.131251 CA_CKDIV4_EN = 0
7126 23:51:25.134479 CA_PREDIV_EN = 0
7127 23:51:25.137549 PH8_DLY = 12
7128 23:51:25.140542 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7129 23:51:25.140644 DQ_AAMCK_DIV = 4
7130 23:51:25.143919 CA_AAMCK_DIV = 4
7131 23:51:25.147196 CA_ADMCK_DIV = 4
7132 23:51:25.150779 DQ_TRACK_CA_EN = 0
7133 23:51:25.154114 CA_PICK = 1600
7134 23:51:25.157290 CA_MCKIO = 1600
7135 23:51:25.161476 MCKIO_SEMI = 0
7136 23:51:25.164044 PLL_FREQ = 3068
7137 23:51:25.164146 DQ_UI_PI_RATIO = 32
7138 23:51:25.167617 CA_UI_PI_RATIO = 0
7139 23:51:25.171354 ===================================
7140 23:51:25.174056 ===================================
7141 23:51:25.178171 memory_type:LPDDR4
7142 23:51:25.180440 GP_NUM : 10
7143 23:51:25.180536 SRAM_EN : 1
7144 23:51:25.184277 MD32_EN : 0
7145 23:51:25.187669 ===================================
7146 23:51:25.187786 [ANA_INIT] >>>>>>>>>>>>>>
7147 23:51:25.190938 <<<<<< [CONFIGURE PHASE]: ANA_TX
7148 23:51:25.194368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7149 23:51:25.197421 ===================================
7150 23:51:25.200834 data_rate = 3200,PCW = 0X7600
7151 23:51:25.204043 ===================================
7152 23:51:25.208252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7153 23:51:25.214574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 23:51:25.217693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 23:51:25.224216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7156 23:51:25.227810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7157 23:51:25.231242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7158 23:51:25.231367 [ANA_INIT] flow start
7159 23:51:25.234201 [ANA_INIT] PLL >>>>>>>>
7160 23:51:25.238781 [ANA_INIT] PLL <<<<<<<<
7161 23:51:25.241639 [ANA_INIT] MIDPI >>>>>>>>
7162 23:51:25.241745 [ANA_INIT] MIDPI <<<<<<<<
7163 23:51:25.243870 [ANA_INIT] DLL >>>>>>>>
7164 23:51:25.248820 [ANA_INIT] DLL <<<<<<<<
7165 23:51:25.248946 [ANA_INIT] flow end
7166 23:51:25.250831 ============ LP4 DIFF to SE enter ============
7167 23:51:25.257664 ============ LP4 DIFF to SE exit ============
7168 23:51:25.257802 [ANA_INIT] <<<<<<<<<<<<<
7169 23:51:25.260770 [Flow] Enable top DCM control >>>>>
7170 23:51:25.264280 [Flow] Enable top DCM control <<<<<
7171 23:51:25.268123 Enable DLL master slave shuffle
7172 23:51:25.274508 ==============================================================
7173 23:51:25.274649 Gating Mode config
7174 23:51:25.281012 ==============================================================
7175 23:51:25.284594 Config description:
7176 23:51:25.291200 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7177 23:51:25.297669 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7178 23:51:25.304179 SELPH_MODE 0: By rank 1: By Phase
7179 23:51:25.311008 ==============================================================
7180 23:51:25.314556 GAT_TRACK_EN = 1
7181 23:51:25.314678 RX_GATING_MODE = 2
7182 23:51:25.317401 RX_GATING_TRACK_MODE = 2
7183 23:51:25.321136 SELPH_MODE = 1
7184 23:51:25.323875 PICG_EARLY_EN = 1
7185 23:51:25.327189 VALID_LAT_VALUE = 1
7186 23:51:25.333881 ==============================================================
7187 23:51:25.337636 Enter into Gating configuration >>>>
7188 23:51:25.340961 Exit from Gating configuration <<<<
7189 23:51:25.344007 Enter into DVFS_PRE_config >>>>>
7190 23:51:25.354468 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7191 23:51:25.357894 Exit from DVFS_PRE_config <<<<<
7192 23:51:25.360747 Enter into PICG configuration >>>>
7193 23:51:25.364098 Exit from PICG configuration <<<<
7194 23:51:25.367420 [RX_INPUT] configuration >>>>>
7195 23:51:25.367533 [RX_INPUT] configuration <<<<<
7196 23:51:25.374361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7197 23:51:25.380619 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7198 23:51:25.384196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 23:51:25.390621 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 23:51:25.397867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7201 23:51:25.404287 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7202 23:51:25.407423 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7203 23:51:25.410839 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7204 23:51:25.417604 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7205 23:51:25.420894 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7206 23:51:25.424511 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7207 23:51:25.428273 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 23:51:25.431330 ===================================
7209 23:51:25.434640 LPDDR4 DRAM CONFIGURATION
7210 23:51:25.437750 ===================================
7211 23:51:25.441449 EX_ROW_EN[0] = 0x0
7212 23:51:25.441576 EX_ROW_EN[1] = 0x0
7213 23:51:25.444470 LP4Y_EN = 0x0
7214 23:51:25.444561 WORK_FSP = 0x1
7215 23:51:25.448245 WL = 0x5
7216 23:51:25.448344 RL = 0x5
7217 23:51:25.451071 BL = 0x2
7218 23:51:25.451161 RPST = 0x0
7219 23:51:25.454765 RD_PRE = 0x0
7220 23:51:25.454860 WR_PRE = 0x1
7221 23:51:25.457763 WR_PST = 0x1
7222 23:51:25.457852 DBI_WR = 0x0
7223 23:51:25.461285 DBI_RD = 0x0
7224 23:51:25.461381 OTF = 0x1
7225 23:51:25.464952 ===================================
7226 23:51:25.471493 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7227 23:51:25.474395 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7228 23:51:25.477767 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 23:51:25.481532 ===================================
7230 23:51:25.484323 LPDDR4 DRAM CONFIGURATION
7231 23:51:25.487903 ===================================
7232 23:51:25.492349 EX_ROW_EN[0] = 0x10
7233 23:51:25.492473 EX_ROW_EN[1] = 0x0
7234 23:51:25.494642 LP4Y_EN = 0x0
7235 23:51:25.494731 WORK_FSP = 0x1
7236 23:51:25.497615 WL = 0x5
7237 23:51:25.497703 RL = 0x5
7238 23:51:25.501519 BL = 0x2
7239 23:51:25.501627 RPST = 0x0
7240 23:51:25.504603 RD_PRE = 0x0
7241 23:51:25.504701 WR_PRE = 0x1
7242 23:51:25.508304 WR_PST = 0x1
7243 23:51:25.508422 DBI_WR = 0x0
7244 23:51:25.511045 DBI_RD = 0x0
7245 23:51:25.511135 OTF = 0x1
7246 23:51:25.514307 ===================================
7247 23:51:25.520961 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7248 23:51:25.521143 ==
7249 23:51:25.524300 Dram Type= 6, Freq= 0, CH_0, rank 0
7250 23:51:25.531253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7251 23:51:25.531401 ==
7252 23:51:25.531470 [Duty_Offset_Calibration]
7253 23:51:25.534132 B0:2 B1:-1 CA:1
7254 23:51:25.534227
7255 23:51:25.537901 [DutyScan_Calibration_Flow] k_type=0
7256 23:51:25.545908
7257 23:51:25.546058 ==CLK 0==
7258 23:51:25.549401 Final CLK duty delay cell = -4
7259 23:51:25.552632 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7260 23:51:25.556243 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7261 23:51:25.559397 [-4] AVG Duty = 4937%(X100)
7262 23:51:25.559507
7263 23:51:25.562698 CH0 CLK Duty spec in!! Max-Min= 187%
7264 23:51:25.565553 [DutyScan_Calibration_Flow] ====Done====
7265 23:51:25.565655
7266 23:51:25.569216 [DutyScan_Calibration_Flow] k_type=1
7267 23:51:25.585888
7268 23:51:25.586047 ==DQS 0 ==
7269 23:51:25.588896 Final DQS duty delay cell = 0
7270 23:51:25.592935 [0] MAX Duty = 5125%(X100), DQS PI = 56
7271 23:51:25.595617 [0] MIN Duty = 5000%(X100), DQS PI = 14
7272 23:51:25.598528 [0] AVG Duty = 5062%(X100)
7273 23:51:25.598633
7274 23:51:25.598702 ==DQS 1 ==
7275 23:51:25.602029 Final DQS duty delay cell = -4
7276 23:51:25.606323 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7277 23:51:25.608687 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7278 23:51:25.612772 [-4] AVG Duty = 5046%(X100)
7279 23:51:25.612889
7280 23:51:25.615341 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7281 23:51:25.615430
7282 23:51:25.619088 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7283 23:51:25.621809 [DutyScan_Calibration_Flow] ====Done====
7284 23:51:25.621920
7285 23:51:25.625241 [DutyScan_Calibration_Flow] k_type=3
7286 23:51:25.643349
7287 23:51:25.643508 ==DQM 0 ==
7288 23:51:25.646205 Final DQM duty delay cell = 0
7289 23:51:25.649533 [0] MAX Duty = 5000%(X100), DQS PI = 18
7290 23:51:25.653046 [0] MIN Duty = 4875%(X100), DQS PI = 4
7291 23:51:25.656171 [0] AVG Duty = 4937%(X100)
7292 23:51:25.656281
7293 23:51:25.656347 ==DQM 1 ==
7294 23:51:25.659787 Final DQM duty delay cell = 0
7295 23:51:25.662736 [0] MAX Duty = 5218%(X100), DQS PI = 58
7296 23:51:25.665850 [0] MIN Duty = 4969%(X100), DQS PI = 18
7297 23:51:25.670271 [0] AVG Duty = 5093%(X100)
7298 23:51:25.670394
7299 23:51:25.672667 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7300 23:51:25.672753
7301 23:51:25.676696 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7302 23:51:25.679027 [DutyScan_Calibration_Flow] ====Done====
7303 23:51:25.679122
7304 23:51:25.682524 [DutyScan_Calibration_Flow] k_type=2
7305 23:51:25.699032
7306 23:51:25.699210 ==DQ 0 ==
7307 23:51:25.702542 Final DQ duty delay cell = -4
7308 23:51:25.705632 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7309 23:51:25.709164 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7310 23:51:25.712842 [-4] AVG Duty = 4922%(X100)
7311 23:51:25.712967
7312 23:51:25.713078 ==DQ 1 ==
7313 23:51:25.716195 Final DQ duty delay cell = 0
7314 23:51:25.719479 [0] MAX Duty = 5031%(X100), DQS PI = 38
7315 23:51:25.722628 [0] MIN Duty = 4907%(X100), DQS PI = 18
7316 23:51:25.722732 [0] AVG Duty = 4969%(X100)
7317 23:51:25.725825
7318 23:51:25.729762 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7319 23:51:25.729878
7320 23:51:25.732429 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7321 23:51:25.735742 [DutyScan_Calibration_Flow] ====Done====
7322 23:51:25.735851 ==
7323 23:51:25.739551 Dram Type= 6, Freq= 0, CH_1, rank 0
7324 23:51:25.742894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7325 23:51:25.743001 ==
7326 23:51:25.746780 [Duty_Offset_Calibration]
7327 23:51:25.746884 B0:1 B1:1 CA:2
7328 23:51:25.746949
7329 23:51:25.750121 [DutyScan_Calibration_Flow] k_type=0
7330 23:51:25.759814
7331 23:51:25.759967 ==CLK 0==
7332 23:51:25.762929 Final CLK duty delay cell = 0
7333 23:51:25.766257 [0] MAX Duty = 5187%(X100), DQS PI = 24
7334 23:51:25.770457 [0] MIN Duty = 4938%(X100), DQS PI = 50
7335 23:51:25.770595 [0] AVG Duty = 5062%(X100)
7336 23:51:25.772768
7337 23:51:25.776109 CH1 CLK Duty spec in!! Max-Min= 249%
7338 23:51:25.780173 [DutyScan_Calibration_Flow] ====Done====
7339 23:51:25.780288
7340 23:51:25.783062 [DutyScan_Calibration_Flow] k_type=1
7341 23:51:25.800261
7342 23:51:25.800414 ==DQS 0 ==
7343 23:51:25.802650 Final DQS duty delay cell = 0
7344 23:51:25.805914 [0] MAX Duty = 5031%(X100), DQS PI = 20
7345 23:51:25.809309 [0] MIN Duty = 4813%(X100), DQS PI = 52
7346 23:51:25.813255 [0] AVG Duty = 4922%(X100)
7347 23:51:25.813375
7348 23:51:25.813440 ==DQS 1 ==
7349 23:51:25.815767 Final DQS duty delay cell = 0
7350 23:51:25.820755 [0] MAX Duty = 5031%(X100), DQS PI = 34
7351 23:51:25.822837 [0] MIN Duty = 4938%(X100), DQS PI = 12
7352 23:51:25.826259 [0] AVG Duty = 4984%(X100)
7353 23:51:25.826414
7354 23:51:25.829150 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7355 23:51:25.829241
7356 23:51:25.832821 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7357 23:51:25.836284 [DutyScan_Calibration_Flow] ====Done====
7358 23:51:25.836393
7359 23:51:25.839257 [DutyScan_Calibration_Flow] k_type=3
7360 23:51:25.856508
7361 23:51:25.856668 ==DQM 0 ==
7362 23:51:25.859644 Final DQM duty delay cell = 0
7363 23:51:25.862859 [0] MAX Duty = 5156%(X100), DQS PI = 20
7364 23:51:25.866473 [0] MIN Duty = 4844%(X100), DQS PI = 50
7365 23:51:25.866589 [0] AVG Duty = 5000%(X100)
7366 23:51:25.870128
7367 23:51:25.870231 ==DQM 1 ==
7368 23:51:25.872843 Final DQM duty delay cell = 0
7369 23:51:25.876287 [0] MAX Duty = 5156%(X100), DQS PI = 60
7370 23:51:25.879764 [0] MIN Duty = 4907%(X100), DQS PI = 20
7371 23:51:25.883393 [0] AVG Duty = 5031%(X100)
7372 23:51:25.883516
7373 23:51:25.886785 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7374 23:51:25.886883
7375 23:51:25.889499 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7376 23:51:25.893201 [DutyScan_Calibration_Flow] ====Done====
7377 23:51:25.893303
7378 23:51:25.896080 [DutyScan_Calibration_Flow] k_type=2
7379 23:51:25.914444
7380 23:51:25.914601 ==DQ 0 ==
7381 23:51:25.916793 Final DQ duty delay cell = 0
7382 23:51:25.920130 [0] MAX Duty = 5125%(X100), DQS PI = 20
7383 23:51:25.923702 [0] MIN Duty = 4907%(X100), DQS PI = 54
7384 23:51:25.923814 [0] AVG Duty = 5016%(X100)
7385 23:51:25.926662
7386 23:51:25.926760 ==DQ 1 ==
7387 23:51:25.930627 Final DQ duty delay cell = 0
7388 23:51:25.933924 [0] MAX Duty = 5093%(X100), DQS PI = 8
7389 23:51:25.936646 [0] MIN Duty = 5031%(X100), DQS PI = 0
7390 23:51:25.936751 [0] AVG Duty = 5062%(X100)
7391 23:51:25.936816
7392 23:51:25.940071 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7393 23:51:25.940165
7394 23:51:25.943405 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7395 23:51:25.949820 [DutyScan_Calibration_Flow] ====Done====
7396 23:51:25.954448 nWR fixed to 30
7397 23:51:25.954583 [ModeRegInit_LP4] CH0 RK0
7398 23:51:25.957310 [ModeRegInit_LP4] CH0 RK1
7399 23:51:25.959987 [ModeRegInit_LP4] CH1 RK0
7400 23:51:25.960080 [ModeRegInit_LP4] CH1 RK1
7401 23:51:25.963678 match AC timing 5
7402 23:51:25.966433 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7403 23:51:25.970425 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7404 23:51:25.976403 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7405 23:51:25.979822 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7406 23:51:25.986946 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7407 23:51:25.987226 [MiockJmeterHQA]
7408 23:51:25.987337
7409 23:51:25.989802 [DramcMiockJmeter] u1RxGatingPI = 0
7410 23:51:25.993563 0 : 4258, 4029
7411 23:51:25.993701 4 : 4363, 4137
7412 23:51:25.993797 8 : 4253, 4027
7413 23:51:25.997297 12 : 4363, 4138
7414 23:51:25.997396 16 : 4252, 4027
7415 23:51:26.000570 20 : 4252, 4027
7416 23:51:26.000663 24 : 4253, 4027
7417 23:51:26.005262 28 : 4255, 4030
7418 23:51:26.005372 32 : 4363, 4138
7419 23:51:26.005438 36 : 4252, 4027
7420 23:51:26.006481 40 : 4255, 4029
7421 23:51:26.006565 44 : 4253, 4026
7422 23:51:26.010544 48 : 4254, 4029
7423 23:51:26.010663 52 : 4252, 4027
7424 23:51:26.013291 56 : 4361, 4137
7425 23:51:26.013385 60 : 4360, 4137
7426 23:51:26.016368 64 : 4250, 4027
7427 23:51:26.016466 68 : 4250, 4027
7428 23:51:26.016534 72 : 4250, 4027
7429 23:51:26.020434 76 : 4252, 4029
7430 23:51:26.020535 80 : 4253, 4030
7431 23:51:26.022914 84 : 4360, 4138
7432 23:51:26.023006 88 : 4250, 4027
7433 23:51:26.026603 92 : 4250, 4026
7434 23:51:26.026710 96 : 4250, 3429
7435 23:51:26.026777 100 : 4252, 0
7436 23:51:26.030108 104 : 4250, 0
7437 23:51:26.030205 108 : 4253, 0
7438 23:51:26.033392 112 : 4250, 0
7439 23:51:26.033491 116 : 4250, 0
7440 23:51:26.033558 120 : 4250, 0
7441 23:51:26.036971 124 : 4252, 0
7442 23:51:26.037096 128 : 4361, 0
7443 23:51:26.039733 132 : 4361, 0
7444 23:51:26.039826 136 : 4363, 0
7445 23:51:26.039892 140 : 4249, 0
7446 23:51:26.043012 144 : 4250, 0
7447 23:51:26.043136 148 : 4250, 0
7448 23:51:26.043231 152 : 4250, 0
7449 23:51:26.046508 156 : 4250, 0
7450 23:51:26.046603 160 : 4250, 0
7451 23:51:26.050002 164 : 4253, 0
7452 23:51:26.050102 168 : 4250, 0
7453 23:51:26.050170 172 : 4250, 0
7454 23:51:26.053232 176 : 4252, 0
7455 23:51:26.053327 180 : 4360, 0
7456 23:51:26.056171 184 : 4250, 0
7457 23:51:26.056262 188 : 4360, 0
7458 23:51:26.056328 192 : 4252, 0
7459 23:51:26.059515 196 : 4250, 0
7460 23:51:26.059631 200 : 4250, 0
7461 23:51:26.062636 204 : 4249, 0
7462 23:51:26.062734 208 : 4250, 0
7463 23:51:26.062802 212 : 4250, 37
7464 23:51:26.066875 216 : 4252, 3334
7465 23:51:26.066987 220 : 4361, 4138
7466 23:51:26.070040 224 : 4250, 4027
7467 23:51:26.070160 228 : 4250, 4026
7468 23:51:26.073339 232 : 4252, 4030
7469 23:51:26.073443 236 : 4252, 4029
7470 23:51:26.076905 240 : 4250, 4027
7471 23:51:26.077030 244 : 4250, 4026
7472 23:51:26.079433 248 : 4361, 4137
7473 23:51:26.079528 252 : 4250, 4026
7474 23:51:26.079608 256 : 4250, 4027
7475 23:51:26.082749 260 : 4360, 4137
7476 23:51:26.082843 264 : 4250, 4027
7477 23:51:26.086268 268 : 4250, 4027
7478 23:51:26.086371 272 : 4363, 4139
7479 23:51:26.089617 276 : 4250, 4027
7480 23:51:26.089712 280 : 4250, 4026
7481 23:51:26.093001 284 : 4250, 4027
7482 23:51:26.093110 288 : 4252, 4030
7483 23:51:26.096685 292 : 4250, 4027
7484 23:51:26.096822 296 : 4250, 4027
7485 23:51:26.100096 300 : 4361, 4137
7486 23:51:26.100193 304 : 4250, 4027
7487 23:51:26.100261 308 : 4250, 4027
7488 23:51:26.102879 312 : 4363, 4139
7489 23:51:26.102970 316 : 4250, 4027
7490 23:51:26.106551 320 : 4250, 4027
7491 23:51:26.106656 324 : 4363, 4140
7492 23:51:26.109403 328 : 4250, 4027
7493 23:51:26.109508 332 : 4250, 3170
7494 23:51:26.112948 336 : 4250, 139
7495 23:51:26.113075
7496 23:51:26.113141 MIOCK jitter meter ch=0
7497 23:51:26.116861
7498 23:51:26.116963 1T = (336-100) = 236 dly cells
7499 23:51:26.123116 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7500 23:51:26.123245 ==
7501 23:51:26.126656 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 23:51:26.129509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 23:51:26.129669 ==
7504 23:51:26.137135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 23:51:26.139885 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 23:51:26.146369 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 23:51:26.149592 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 23:51:26.159681 [CA 0] Center 44 (14~75) winsize 62
7509 23:51:26.163080 [CA 1] Center 44 (14~75) winsize 62
7510 23:51:26.167062 [CA 2] Center 40 (11~69) winsize 59
7511 23:51:26.169897 [CA 3] Center 39 (10~69) winsize 60
7512 23:51:26.172964 [CA 4] Center 37 (8~67) winsize 60
7513 23:51:26.176321 [CA 5] Center 37 (8~67) winsize 60
7514 23:51:26.176430
7515 23:51:26.179815 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 23:51:26.179913
7517 23:51:26.183316 [CATrainingPosCal] consider 1 rank data
7518 23:51:26.186624 u2DelayCellTimex100 = 275/100 ps
7519 23:51:26.192888 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7520 23:51:26.196185 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7521 23:51:26.199784 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7522 23:51:26.202997 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7523 23:51:26.206657 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7524 23:51:26.209507 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
7525 23:51:26.209628
7526 23:51:26.212878 CA PerBit enable=1, Macro0, CA PI delay=37
7527 23:51:26.213007
7528 23:51:26.217767 [CBTSetCACLKResult] CA Dly = 37
7529 23:51:26.219475 CS Dly: 11 (0~42)
7530 23:51:26.222910 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 23:51:26.226151 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 23:51:26.226259 ==
7533 23:51:26.229986 Dram Type= 6, Freq= 0, CH_0, rank 1
7534 23:51:26.233210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 23:51:26.236672 ==
7536 23:51:26.240199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 23:51:26.243131 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 23:51:26.250042 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 23:51:26.253510 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 23:51:26.263892 [CA 0] Center 44 (14~74) winsize 61
7541 23:51:26.267555 [CA 1] Center 43 (13~74) winsize 62
7542 23:51:26.270708 [CA 2] Center 39 (10~69) winsize 60
7543 23:51:26.273653 [CA 3] Center 38 (9~68) winsize 60
7544 23:51:26.276859 [CA 4] Center 37 (7~67) winsize 61
7545 23:51:26.280886 [CA 5] Center 37 (7~67) winsize 61
7546 23:51:26.281066
7547 23:51:26.283284 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 23:51:26.283394
7549 23:51:26.287041 [CATrainingPosCal] consider 2 rank data
7550 23:51:26.290158 u2DelayCellTimex100 = 275/100 ps
7551 23:51:26.293665 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7552 23:51:26.300703 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7553 23:51:26.303526 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7554 23:51:26.307309 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7555 23:51:26.310585 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7556 23:51:26.313707 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
7557 23:51:26.313821
7558 23:51:26.317075 CA PerBit enable=1, Macro0, CA PI delay=37
7559 23:51:26.317173
7560 23:51:26.320572 [CBTSetCACLKResult] CA Dly = 37
7561 23:51:26.323974 CS Dly: 11 (0~43)
7562 23:51:26.327010 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 23:51:26.330311 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 23:51:26.330424
7565 23:51:26.333927 ----->DramcWriteLeveling(PI) begin...
7566 23:51:26.334031 ==
7567 23:51:26.336617 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 23:51:26.340606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 23:51:26.343938 ==
7570 23:51:26.344036 Write leveling (Byte 0): 33 => 33
7571 23:51:26.347282 Write leveling (Byte 1): 31 => 31
7572 23:51:26.351030 DramcWriteLeveling(PI) end<-----
7573 23:51:26.351142
7574 23:51:26.351206 ==
7575 23:51:26.353413 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 23:51:26.360592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 23:51:26.360735 ==
7578 23:51:26.360805 [Gating] SW mode calibration
7579 23:51:26.370984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7580 23:51:26.373271 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7581 23:51:26.380763 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 23:51:26.383659 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 23:51:26.386955 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 23:51:26.393569 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 23:51:26.396947 1 4 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7586 23:51:26.401814 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7587 23:51:26.403309 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7588 23:51:26.409860 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 23:51:26.414135 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 23:51:26.416889 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 23:51:26.423818 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 23:51:26.426925 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7593 23:51:26.429814 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7594 23:51:26.436619 1 5 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
7595 23:51:26.440066 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7596 23:51:26.443149 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:51:26.450268 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 23:51:26.453138 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 23:51:26.456747 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 23:51:26.463821 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 23:51:26.466736 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7602 23:51:26.470866 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7603 23:51:26.476479 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 23:51:26.479911 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 23:51:26.484141 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 23:51:26.489958 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 23:51:26.494235 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 23:51:26.496884 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 23:51:26.499873 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 23:51:26.507031 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7611 23:51:26.510783 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 23:51:26.513558 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:51:26.519953 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:51:26.524250 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:51:26.526980 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:51:26.533148 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:51:26.537267 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:51:26.540463 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:51:26.546855 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:51:26.550357 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:51:26.553699 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:51:26.560033 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:51:26.563343 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:51:26.567013 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 23:51:26.573271 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 23:51:26.577119 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 23:51:26.580463 Total UI for P1: 0, mck2ui 16
7628 23:51:26.583898 best dqsien dly found for B0: ( 1, 9, 16)
7629 23:51:26.587236 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 23:51:26.589782 Total UI for P1: 0, mck2ui 16
7631 23:51:26.593750 best dqsien dly found for B1: ( 1, 9, 20)
7632 23:51:26.596679 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7633 23:51:26.599872 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7634 23:51:26.599986
7635 23:51:26.603904 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7636 23:51:26.611040 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7637 23:51:26.611198 [Gating] SW calibration Done
7638 23:51:26.611293 ==
7639 23:51:26.613552 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 23:51:26.620421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 23:51:26.620565 ==
7642 23:51:26.620659 RX Vref Scan: 0
7643 23:51:26.620757
7644 23:51:26.623508 RX Vref 0 -> 0, step: 1
7645 23:51:26.623596
7646 23:51:26.626875 RX Delay 0 -> 252, step: 8
7647 23:51:26.630647 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7648 23:51:26.633507 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7649 23:51:26.636780 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7650 23:51:26.640748 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7651 23:51:26.647234 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7652 23:51:26.649761 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7653 23:51:26.653727 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7654 23:51:26.657079 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7655 23:51:26.659954 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7656 23:51:26.666783 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7657 23:51:26.670036 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7658 23:51:26.673502 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7659 23:51:26.676525 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7660 23:51:26.679892 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7661 23:51:26.686431 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7662 23:51:26.689758 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7663 23:51:26.689880 ==
7664 23:51:26.693945 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 23:51:26.696885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 23:51:26.697060 ==
7667 23:51:26.700337 DQS Delay:
7668 23:51:26.700437 DQS0 = 0, DQS1 = 0
7669 23:51:26.700523 DQM Delay:
7670 23:51:26.703453 DQM0 = 132, DQM1 = 125
7671 23:51:26.703543 DQ Delay:
7672 23:51:26.707150 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7673 23:51:26.709899 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7674 23:51:26.713381 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7675 23:51:26.720212 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7676 23:51:26.720361
7677 23:51:26.720456
7678 23:51:26.720536 ==
7679 23:51:26.723433 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 23:51:26.727331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 23:51:26.727445 ==
7682 23:51:26.727512
7683 23:51:26.727572
7684 23:51:26.730549 TX Vref Scan disable
7685 23:51:26.730638 == TX Byte 0 ==
7686 23:51:26.736801 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7687 23:51:26.741161 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7688 23:51:26.741284 == TX Byte 1 ==
7689 23:51:26.746921 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7690 23:51:26.750262 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7691 23:51:26.750374 ==
7692 23:51:26.753903 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 23:51:26.756995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 23:51:26.757098 ==
7695 23:51:26.771716
7696 23:51:26.775092 TX Vref early break, caculate TX vref
7697 23:51:26.778890 TX Vref=16, minBit 4, minWin=21, winSum=361
7698 23:51:26.782037 TX Vref=18, minBit 0, minWin=22, winSum=370
7699 23:51:26.785529 TX Vref=20, minBit 4, minWin=22, winSum=384
7700 23:51:26.789094 TX Vref=22, minBit 1, minWin=22, winSum=386
7701 23:51:26.792945 TX Vref=24, minBit 1, minWin=23, winSum=403
7702 23:51:26.798400 TX Vref=26, minBit 0, minWin=24, winSum=410
7703 23:51:26.802937 TX Vref=28, minBit 1, minWin=24, winSum=417
7704 23:51:26.805832 TX Vref=30, minBit 4, minWin=24, winSum=416
7705 23:51:26.808535 TX Vref=32, minBit 0, minWin=24, winSum=408
7706 23:51:26.812649 TX Vref=34, minBit 4, minWin=23, winSum=399
7707 23:51:26.815015 TX Vref=36, minBit 0, minWin=23, winSum=389
7708 23:51:26.822198 [TxChooseVref] Worse bit 1, Min win 24, Win sum 417, Final Vref 28
7709 23:51:26.822347
7710 23:51:26.825680 Final TX Range 0 Vref 28
7711 23:51:26.825782
7712 23:51:26.825870 ==
7713 23:51:26.828806 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 23:51:26.832187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 23:51:26.832298 ==
7716 23:51:26.832388
7717 23:51:26.832467
7718 23:51:26.835325 TX Vref Scan disable
7719 23:51:26.841741 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7720 23:51:26.841884 == TX Byte 0 ==
7721 23:51:26.844846 u2DelayCellOfst[0]=14 cells (4 PI)
7722 23:51:26.848307 u2DelayCellOfst[1]=21 cells (6 PI)
7723 23:51:26.852471 u2DelayCellOfst[2]=10 cells (3 PI)
7724 23:51:26.855191 u2DelayCellOfst[3]=14 cells (4 PI)
7725 23:51:26.859017 u2DelayCellOfst[4]=7 cells (2 PI)
7726 23:51:26.861613 u2DelayCellOfst[5]=0 cells (0 PI)
7727 23:51:26.865160 u2DelayCellOfst[6]=17 cells (5 PI)
7728 23:51:26.868569 u2DelayCellOfst[7]=17 cells (5 PI)
7729 23:51:26.872287 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7730 23:51:26.875787 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7731 23:51:26.878371 == TX Byte 1 ==
7732 23:51:26.878477 u2DelayCellOfst[8]=0 cells (0 PI)
7733 23:51:26.881567 u2DelayCellOfst[9]=3 cells (1 PI)
7734 23:51:26.885011 u2DelayCellOfst[10]=10 cells (3 PI)
7735 23:51:26.888584 u2DelayCellOfst[11]=3 cells (1 PI)
7736 23:51:26.891872 u2DelayCellOfst[12]=14 cells (4 PI)
7737 23:51:26.894715 u2DelayCellOfst[13]=14 cells (4 PI)
7738 23:51:26.898642 u2DelayCellOfst[14]=17 cells (5 PI)
7739 23:51:26.901707 u2DelayCellOfst[15]=14 cells (4 PI)
7740 23:51:26.904958 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7741 23:51:26.912141 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7742 23:51:26.912291 DramC Write-DBI on
7743 23:51:26.912386 ==
7744 23:51:26.915164 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 23:51:26.918501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 23:51:26.921589 ==
7747 23:51:26.921693
7748 23:51:26.921781
7749 23:51:26.921861 TX Vref Scan disable
7750 23:51:26.924901 == TX Byte 0 ==
7751 23:51:26.928316 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7752 23:51:26.931665 == TX Byte 1 ==
7753 23:51:26.934758 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7754 23:51:26.934872 DramC Write-DBI off
7755 23:51:26.938527
7756 23:51:26.938628 [DATLAT]
7757 23:51:26.938716 Freq=1600, CH0 RK0
7758 23:51:26.938796
7759 23:51:26.942170 DATLAT Default: 0xf
7760 23:51:26.942267 0, 0xFFFF, sum = 0
7761 23:51:26.944792 1, 0xFFFF, sum = 0
7762 23:51:26.944882 2, 0xFFFF, sum = 0
7763 23:51:26.948224 3, 0xFFFF, sum = 0
7764 23:51:26.952039 4, 0xFFFF, sum = 0
7765 23:51:26.952161 5, 0xFFFF, sum = 0
7766 23:51:26.955984 6, 0xFFFF, sum = 0
7767 23:51:26.956090 7, 0xFFFF, sum = 0
7768 23:51:26.958173 8, 0xFFFF, sum = 0
7769 23:51:26.958262 9, 0xFFFF, sum = 0
7770 23:51:26.961932 10, 0xFFFF, sum = 0
7771 23:51:26.962032 11, 0xFFFF, sum = 0
7772 23:51:26.965182 12, 0xFFFF, sum = 0
7773 23:51:26.965279 13, 0xFFFF, sum = 0
7774 23:51:26.968940 14, 0x0, sum = 1
7775 23:51:26.969053 15, 0x0, sum = 2
7776 23:51:26.974364 16, 0x0, sum = 3
7777 23:51:26.974487 17, 0x0, sum = 4
7778 23:51:26.975533 best_step = 15
7779 23:51:26.975616
7780 23:51:26.975700 ==
7781 23:51:26.978577 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 23:51:26.982075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 23:51:26.982180 ==
7784 23:51:26.982269 RX Vref Scan: 1
7785 23:51:26.982349
7786 23:51:26.984862 Set Vref Range= 24 -> 127
7787 23:51:26.984950
7788 23:51:26.988484 RX Vref 24 -> 127, step: 1
7789 23:51:26.988585
7790 23:51:26.992023 RX Delay 11 -> 252, step: 4
7791 23:51:26.992119
7792 23:51:26.994846 Set Vref, RX VrefLevel [Byte0]: 24
7793 23:51:26.998406 [Byte1]: 24
7794 23:51:26.998511
7795 23:51:27.002038 Set Vref, RX VrefLevel [Byte0]: 25
7796 23:51:27.004745 [Byte1]: 25
7797 23:51:27.004847
7798 23:51:27.007938 Set Vref, RX VrefLevel [Byte0]: 26
7799 23:51:27.011283 [Byte1]: 26
7800 23:51:27.015319
7801 23:51:27.015445 Set Vref, RX VrefLevel [Byte0]: 27
7802 23:51:27.018798 [Byte1]: 27
7803 23:51:27.023700
7804 23:51:27.023840 Set Vref, RX VrefLevel [Byte0]: 28
7805 23:51:27.026204 [Byte1]: 28
7806 23:51:27.030892
7807 23:51:27.031017 Set Vref, RX VrefLevel [Byte0]: 29
7808 23:51:27.034096 [Byte1]: 29
7809 23:51:27.038560
7810 23:51:27.038687 Set Vref, RX VrefLevel [Byte0]: 30
7811 23:51:27.042051 [Byte1]: 30
7812 23:51:27.045912
7813 23:51:27.046029 Set Vref, RX VrefLevel [Byte0]: 31
7814 23:51:27.049142 [Byte1]: 31
7815 23:51:27.053841
7816 23:51:27.053969 Set Vref, RX VrefLevel [Byte0]: 32
7817 23:51:27.056707 [Byte1]: 32
7818 23:51:27.060942
7819 23:51:27.061095 Set Vref, RX VrefLevel [Byte0]: 33
7820 23:51:27.064226 [Byte1]: 33
7821 23:51:27.068601
7822 23:51:27.068731 Set Vref, RX VrefLevel [Byte0]: 34
7823 23:51:27.072449 [Byte1]: 34
7824 23:51:27.076027
7825 23:51:27.076138 Set Vref, RX VrefLevel [Byte0]: 35
7826 23:51:27.079551 [Byte1]: 35
7827 23:51:27.084024
7828 23:51:27.084147 Set Vref, RX VrefLevel [Byte0]: 36
7829 23:51:27.087456 [Byte1]: 36
7830 23:51:27.091234
7831 23:51:27.091351 Set Vref, RX VrefLevel [Byte0]: 37
7832 23:51:27.094521 [Byte1]: 37
7833 23:51:27.099039
7834 23:51:27.099166 Set Vref, RX VrefLevel [Byte0]: 38
7835 23:51:27.102631 [Byte1]: 38
7836 23:51:27.106915
7837 23:51:27.107040 Set Vref, RX VrefLevel [Byte0]: 39
7838 23:51:27.110709 [Byte1]: 39
7839 23:51:27.114159
7840 23:51:27.114275 Set Vref, RX VrefLevel [Byte0]: 40
7841 23:51:27.118285 [Byte1]: 40
7842 23:51:27.121770
7843 23:51:27.121893 Set Vref, RX VrefLevel [Byte0]: 41
7844 23:51:27.125090 [Byte1]: 41
7845 23:51:27.129812
7846 23:51:27.129943 Set Vref, RX VrefLevel [Byte0]: 42
7847 23:51:27.133101 [Byte1]: 42
7848 23:51:27.138264
7849 23:51:27.138393 Set Vref, RX VrefLevel [Byte0]: 43
7850 23:51:27.140358 [Byte1]: 43
7851 23:51:27.144586
7852 23:51:27.144699 Set Vref, RX VrefLevel [Byte0]: 44
7853 23:51:27.147831 [Byte1]: 44
7854 23:51:27.154147
7855 23:51:27.154288 Set Vref, RX VrefLevel [Byte0]: 45
7856 23:51:27.156936 [Byte1]: 45
7857 23:51:27.159759
7858 23:51:27.159858 Set Vref, RX VrefLevel [Byte0]: 46
7859 23:51:27.163278 [Byte1]: 46
7860 23:51:27.167644
7861 23:51:27.167773 Set Vref, RX VrefLevel [Byte0]: 47
7862 23:51:27.171084 [Byte1]: 47
7863 23:51:27.175712
7864 23:51:27.175843 Set Vref, RX VrefLevel [Byte0]: 48
7865 23:51:27.178785 [Byte1]: 48
7866 23:51:27.182625
7867 23:51:27.182741 Set Vref, RX VrefLevel [Byte0]: 49
7868 23:51:27.186321 [Byte1]: 49
7869 23:51:27.190906
7870 23:51:27.191033 Set Vref, RX VrefLevel [Byte0]: 50
7871 23:51:27.193960 [Byte1]: 50
7872 23:51:27.198105
7873 23:51:27.198222 Set Vref, RX VrefLevel [Byte0]: 51
7874 23:51:27.202419 [Byte1]: 51
7875 23:51:27.206461
7876 23:51:27.206578 Set Vref, RX VrefLevel [Byte0]: 52
7877 23:51:27.208924 [Byte1]: 52
7878 23:51:27.214463
7879 23:51:27.214601 Set Vref, RX VrefLevel [Byte0]: 53
7880 23:51:27.216555 [Byte1]: 53
7881 23:51:27.221261
7882 23:51:27.221386 Set Vref, RX VrefLevel [Byte0]: 54
7883 23:51:27.224875 [Byte1]: 54
7884 23:51:27.228463
7885 23:51:27.228583 Set Vref, RX VrefLevel [Byte0]: 55
7886 23:51:27.232071 [Byte1]: 55
7887 23:51:27.236384
7888 23:51:27.236507 Set Vref, RX VrefLevel [Byte0]: 56
7889 23:51:27.239232 [Byte1]: 56
7890 23:51:27.244312
7891 23:51:27.244442 Set Vref, RX VrefLevel [Byte0]: 57
7892 23:51:27.248093 [Byte1]: 57
7893 23:51:27.252011
7894 23:51:27.252129 Set Vref, RX VrefLevel [Byte0]: 58
7895 23:51:27.254641 [Byte1]: 58
7896 23:51:27.259364
7897 23:51:27.259484 Set Vref, RX VrefLevel [Byte0]: 59
7898 23:51:27.262429 [Byte1]: 59
7899 23:51:27.266851
7900 23:51:27.266969 Set Vref, RX VrefLevel [Byte0]: 60
7901 23:51:27.269970 [Byte1]: 60
7902 23:51:27.274064
7903 23:51:27.274183 Set Vref, RX VrefLevel [Byte0]: 61
7904 23:51:27.277667 [Byte1]: 61
7905 23:51:27.281909
7906 23:51:27.282037 Set Vref, RX VrefLevel [Byte0]: 62
7907 23:51:27.285188 [Byte1]: 62
7908 23:51:27.289257
7909 23:51:27.289437 Set Vref, RX VrefLevel [Byte0]: 63
7910 23:51:27.293935 [Byte1]: 63
7911 23:51:27.297405
7912 23:51:27.297547 Set Vref, RX VrefLevel [Byte0]: 64
7913 23:51:27.300343 [Byte1]: 64
7914 23:51:27.305093
7915 23:51:27.305205 Set Vref, RX VrefLevel [Byte0]: 65
7916 23:51:27.308145 [Byte1]: 65
7917 23:51:27.313128
7918 23:51:27.313264 Set Vref, RX VrefLevel [Byte0]: 66
7919 23:51:27.315415 [Byte1]: 66
7920 23:51:27.319687
7921 23:51:27.319800 Set Vref, RX VrefLevel [Byte0]: 67
7922 23:51:27.323651 [Byte1]: 67
7923 23:51:27.328087
7924 23:51:27.328214 Set Vref, RX VrefLevel [Byte0]: 68
7925 23:51:27.332005 [Byte1]: 68
7926 23:51:27.335055
7927 23:51:27.335169 Set Vref, RX VrefLevel [Byte0]: 69
7928 23:51:27.338556 [Byte1]: 69
7929 23:51:27.343128
7930 23:51:27.343295 Set Vref, RX VrefLevel [Byte0]: 70
7931 23:51:27.345973 [Byte1]: 70
7932 23:51:27.350277
7933 23:51:27.350400 Set Vref, RX VrefLevel [Byte0]: 71
7934 23:51:27.353934 [Byte1]: 71
7935 23:51:27.358527
7936 23:51:27.358662 Set Vref, RX VrefLevel [Byte0]: 72
7937 23:51:27.361507 [Byte1]: 72
7938 23:51:27.366545
7939 23:51:27.366671 Set Vref, RX VrefLevel [Byte0]: 73
7940 23:51:27.369324 [Byte1]: 73
7941 23:51:27.373159
7942 23:51:27.373273 Set Vref, RX VrefLevel [Byte0]: 74
7943 23:51:27.376636 [Byte1]: 74
7944 23:51:27.381096
7945 23:51:27.381218 Set Vref, RX VrefLevel [Byte0]: 75
7946 23:51:27.384185 [Byte1]: 75
7947 23:51:27.388501
7948 23:51:27.388624 Set Vref, RX VrefLevel [Byte0]: 76
7949 23:51:27.391670 [Byte1]: 76
7950 23:51:27.396011
7951 23:51:27.396137 Final RX Vref Byte 0 = 62 to rank0
7952 23:51:27.399270 Final RX Vref Byte 1 = 60 to rank0
7953 23:51:27.402679 Final RX Vref Byte 0 = 62 to rank1
7954 23:51:27.406488 Final RX Vref Byte 1 = 60 to rank1==
7955 23:51:27.409144 Dram Type= 6, Freq= 0, CH_0, rank 0
7956 23:51:27.416087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 23:51:27.416236 ==
7958 23:51:27.416305 DQS Delay:
7959 23:51:27.416365 DQS0 = 0, DQS1 = 0
7960 23:51:27.419454 DQM Delay:
7961 23:51:27.419579 DQM0 = 129, DQM1 = 122
7962 23:51:27.422426 DQ Delay:
7963 23:51:27.425609 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =126
7964 23:51:27.430041 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7965 23:51:27.432295 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7966 23:51:27.436034 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7967 23:51:27.436149
7968 23:51:27.436240
7969 23:51:27.436320
7970 23:51:27.438953 [DramC_TX_OE_Calibration] TA2
7971 23:51:27.442236 Original DQ_B0 (3 6) =30, OEN = 27
7972 23:51:27.445805 Original DQ_B1 (3 6) =30, OEN = 27
7973 23:51:27.449367 24, 0x0, End_B0=24 End_B1=24
7974 23:51:27.449488 25, 0x0, End_B0=25 End_B1=25
7975 23:51:27.452330 26, 0x0, End_B0=26 End_B1=26
7976 23:51:27.455580 27, 0x0, End_B0=27 End_B1=27
7977 23:51:27.458851 28, 0x0, End_B0=28 End_B1=28
7978 23:51:27.462065 29, 0x0, End_B0=29 End_B1=29
7979 23:51:27.462179 30, 0x0, End_B0=30 End_B1=30
7980 23:51:27.465298 31, 0x5151, End_B0=30 End_B1=30
7981 23:51:27.468400 Byte0 end_step=30 best_step=27
7982 23:51:27.471886 Byte1 end_step=30 best_step=27
7983 23:51:27.475452 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 23:51:27.478812 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 23:51:27.478929
7986 23:51:27.479019
7987 23:51:27.486455 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7988 23:51:27.488528 CH0 RK0: MR19=303, MR18=1206
7989 23:51:27.495184 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7990 23:51:27.495330
7991 23:51:27.498673 ----->DramcWriteLeveling(PI) begin...
7992 23:51:27.498777 ==
7993 23:51:27.502449 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 23:51:27.505375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 23:51:27.505488 ==
7996 23:51:27.508609 Write leveling (Byte 0): 34 => 34
7997 23:51:27.512260 Write leveling (Byte 1): 25 => 25
7998 23:51:27.514931 DramcWriteLeveling(PI) end<-----
7999 23:51:27.515035
8000 23:51:27.515123 ==
8001 23:51:27.519503 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 23:51:27.522246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 23:51:27.522351 ==
8004 23:51:27.524895 [Gating] SW mode calibration
8005 23:51:27.531560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8006 23:51:27.538722 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8007 23:51:27.542539 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 23:51:27.548496 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 23:51:27.551720 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 23:51:27.555386 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8011 23:51:27.561437 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8012 23:51:27.565477 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8013 23:51:27.567938 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 23:51:27.576430 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 23:51:27.578708 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 23:51:27.581829 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 23:51:27.588313 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8018 23:51:27.591520 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
8019 23:51:27.595017 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8020 23:51:27.598050 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8021 23:51:27.604652 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8022 23:51:27.608518 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:51:27.611631 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 23:51:27.618250 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 23:51:27.621557 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8026 23:51:27.625197 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8027 23:51:27.631929 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8028 23:51:27.635025 1 6 20 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
8029 23:51:27.638227 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 23:51:27.645436 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 23:51:27.648521 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 23:51:27.651652 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 23:51:27.658039 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 23:51:27.661435 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 23:51:27.664943 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 23:51:27.671561 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 23:51:27.675008 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 23:51:27.678665 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:51:27.682271 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:51:27.688650 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:51:27.691342 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:51:27.694722 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:51:27.701610 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:51:27.704965 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:51:27.708266 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:51:27.715468 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:51:27.718618 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 23:51:27.722039 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 23:51:27.728842 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 23:51:27.732438 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8051 23:51:27.735114 Total UI for P1: 0, mck2ui 16
8052 23:51:27.738092 best dqsien dly found for B0: ( 1, 9, 8)
8053 23:51:27.742348 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8054 23:51:27.747949 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8055 23:51:27.751351 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 23:51:27.755628 Total UI for P1: 0, mck2ui 16
8057 23:51:27.758937 best dqsien dly found for B1: ( 1, 9, 20)
8058 23:51:27.761712 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8059 23:51:27.765280 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8060 23:51:27.765399
8061 23:51:27.768287 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8062 23:51:27.771422 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8063 23:51:27.774673 [Gating] SW calibration Done
8064 23:51:27.774783 ==
8065 23:51:27.779365 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 23:51:27.782008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 23:51:27.782113 ==
8068 23:51:27.785378 RX Vref Scan: 0
8069 23:51:27.785470
8070 23:51:27.789106 RX Vref 0 -> 0, step: 1
8071 23:51:27.789203
8072 23:51:27.789288 RX Delay 0 -> 252, step: 8
8073 23:51:27.795200 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8074 23:51:27.798450 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8075 23:51:27.801842 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8076 23:51:27.804819 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8077 23:51:27.808142 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8078 23:51:27.811808 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8079 23:51:27.819444 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8080 23:51:27.822433 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8081 23:51:27.825234 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8082 23:51:27.829153 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8083 23:51:27.831742 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8084 23:51:27.838926 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8085 23:51:27.841896 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8086 23:51:27.844949 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8087 23:51:27.848355 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8088 23:51:27.851604 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8089 23:51:27.855177 ==
8090 23:51:27.858745 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 23:51:27.862656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 23:51:27.862773 ==
8093 23:51:27.862864 DQS Delay:
8094 23:51:27.865545 DQS0 = 0, DQS1 = 0
8095 23:51:27.865636 DQM Delay:
8096 23:51:27.868907 DQM0 = 130, DQM1 = 125
8097 23:51:27.869018 DQ Delay:
8098 23:51:27.872057 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8099 23:51:27.875199 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8100 23:51:27.879227 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
8101 23:51:27.883144 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =135
8102 23:51:27.883269
8103 23:51:27.883362
8104 23:51:27.883442 ==
8105 23:51:27.884990 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 23:51:27.891581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 23:51:27.891713 ==
8108 23:51:27.891805
8109 23:51:27.891885
8110 23:51:27.891962 TX Vref Scan disable
8111 23:51:27.895242 == TX Byte 0 ==
8112 23:51:27.898676 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8113 23:51:27.903104 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8114 23:51:27.905225 == TX Byte 1 ==
8115 23:51:27.908885 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8116 23:51:27.912185 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8117 23:51:27.916000 ==
8118 23:51:27.919661 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 23:51:27.922366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 23:51:27.922470 ==
8121 23:51:27.936442
8122 23:51:27.940225 TX Vref early break, caculate TX vref
8123 23:51:27.943179 TX Vref=16, minBit 4, minWin=22, winSum=368
8124 23:51:27.946498 TX Vref=18, minBit 8, minWin=22, winSum=378
8125 23:51:27.949742 TX Vref=20, minBit 5, minWin=23, winSum=387
8126 23:51:27.952979 TX Vref=22, minBit 8, minWin=23, winSum=395
8127 23:51:27.956394 TX Vref=24, minBit 4, minWin=24, winSum=402
8128 23:51:27.963328 TX Vref=26, minBit 5, minWin=24, winSum=414
8129 23:51:27.966184 TX Vref=28, minBit 2, minWin=25, winSum=417
8130 23:51:27.969958 TX Vref=30, minBit 4, minWin=25, winSum=415
8131 23:51:27.973410 TX Vref=32, minBit 8, minWin=24, winSum=413
8132 23:51:27.976907 TX Vref=34, minBit 1, minWin=24, winSum=404
8133 23:51:27.979793 TX Vref=36, minBit 1, minWin=24, winSum=395
8134 23:51:27.986361 [TxChooseVref] Worse bit 2, Min win 25, Win sum 417, Final Vref 28
8135 23:51:27.986509
8136 23:51:27.990417 Final TX Range 0 Vref 28
8137 23:51:27.990538
8138 23:51:27.990679 ==
8139 23:51:27.993275 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 23:51:27.996317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 23:51:27.996417 ==
8142 23:51:27.996504
8143 23:51:27.996584
8144 23:51:28.000082 TX Vref Scan disable
8145 23:51:28.006209 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8146 23:51:28.006348 == TX Byte 0 ==
8147 23:51:28.009738 u2DelayCellOfst[0]=7 cells (2 PI)
8148 23:51:28.013083 u2DelayCellOfst[1]=14 cells (4 PI)
8149 23:51:28.016203 u2DelayCellOfst[2]=7 cells (2 PI)
8150 23:51:28.019674 u2DelayCellOfst[3]=7 cells (2 PI)
8151 23:51:28.023752 u2DelayCellOfst[4]=7 cells (2 PI)
8152 23:51:28.027452 u2DelayCellOfst[5]=0 cells (0 PI)
8153 23:51:28.029931 u2DelayCellOfst[6]=14 cells (4 PI)
8154 23:51:28.033034 u2DelayCellOfst[7]=14 cells (4 PI)
8155 23:51:28.036377 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8156 23:51:28.039503 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8157 23:51:28.043515 == TX Byte 1 ==
8158 23:51:28.043640 u2DelayCellOfst[8]=0 cells (0 PI)
8159 23:51:28.047184 u2DelayCellOfst[9]=0 cells (0 PI)
8160 23:51:28.049458 u2DelayCellOfst[10]=3 cells (1 PI)
8161 23:51:28.053034 u2DelayCellOfst[11]=0 cells (0 PI)
8162 23:51:28.056582 u2DelayCellOfst[12]=10 cells (3 PI)
8163 23:51:28.059428 u2DelayCellOfst[13]=7 cells (2 PI)
8164 23:51:28.064382 u2DelayCellOfst[14]=14 cells (4 PI)
8165 23:51:28.068810 u2DelayCellOfst[15]=10 cells (3 PI)
8166 23:51:28.069426 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8167 23:51:28.076222 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8168 23:51:28.076366 DramC Write-DBI on
8169 23:51:28.076465 ==
8170 23:51:28.080027 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 23:51:28.082900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 23:51:28.083007 ==
8173 23:51:28.086970
8174 23:51:28.087077
8175 23:51:28.087165 TX Vref Scan disable
8176 23:51:28.089921 == TX Byte 0 ==
8177 23:51:28.093742 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8178 23:51:28.097536 == TX Byte 1 ==
8179 23:51:28.099499 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8180 23:51:28.099596 DramC Write-DBI off
8181 23:51:28.103440
8182 23:51:28.103551 [DATLAT]
8183 23:51:28.103638 Freq=1600, CH0 RK1
8184 23:51:28.103719
8185 23:51:28.106423 DATLAT Default: 0xf
8186 23:51:28.106504 0, 0xFFFF, sum = 0
8187 23:51:28.109787 1, 0xFFFF, sum = 0
8188 23:51:28.109888 2, 0xFFFF, sum = 0
8189 23:51:28.112928 3, 0xFFFF, sum = 0
8190 23:51:28.113077 4, 0xFFFF, sum = 0
8191 23:51:28.116220 5, 0xFFFF, sum = 0
8192 23:51:28.120033 6, 0xFFFF, sum = 0
8193 23:51:28.120141 7, 0xFFFF, sum = 0
8194 23:51:28.122793 8, 0xFFFF, sum = 0
8195 23:51:28.122885 9, 0xFFFF, sum = 0
8196 23:51:28.126434 10, 0xFFFF, sum = 0
8197 23:51:28.126533 11, 0xFFFF, sum = 0
8198 23:51:28.129958 12, 0xFFFF, sum = 0
8199 23:51:28.130059 13, 0xFFFF, sum = 0
8200 23:51:28.133966 14, 0x0, sum = 1
8201 23:51:28.134072 15, 0x0, sum = 2
8202 23:51:28.136549 16, 0x0, sum = 3
8203 23:51:28.136637 17, 0x0, sum = 4
8204 23:51:28.139861 best_step = 15
8205 23:51:28.139956
8206 23:51:28.140041 ==
8207 23:51:28.143054 Dram Type= 6, Freq= 0, CH_0, rank 1
8208 23:51:28.146671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8209 23:51:28.146779 ==
8210 23:51:28.146870 RX Vref Scan: 0
8211 23:51:28.146950
8212 23:51:28.150044 RX Vref 0 -> 0, step: 1
8213 23:51:28.150159
8214 23:51:28.153108 RX Delay 11 -> 252, step: 4
8215 23:51:28.156455 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8216 23:51:28.162742 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8217 23:51:28.166420 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8218 23:51:28.169642 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8219 23:51:28.173217 iDelay=191, Bit 4, Center 126 (71 ~ 182) 112
8220 23:51:28.176206 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8221 23:51:28.180000 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8222 23:51:28.186575 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8223 23:51:28.190378 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8224 23:51:28.193698 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8225 23:51:28.197175 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8226 23:51:28.199845 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8227 23:51:28.206366 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8228 23:51:28.209974 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8229 23:51:28.213091 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8230 23:51:28.217118 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8231 23:51:28.217246 ==
8232 23:51:28.220008 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 23:51:28.226474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 23:51:28.226617 ==
8235 23:51:28.226713 DQS Delay:
8236 23:51:28.226795 DQS0 = 0, DQS1 = 0
8237 23:51:28.230025 DQM Delay:
8238 23:51:28.230119 DQM0 = 127, DQM1 = 123
8239 23:51:28.233557 DQ Delay:
8240 23:51:28.236658 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8241 23:51:28.240153 DQ4 =126, DQ5 =116, DQ6 =136, DQ7 =136
8242 23:51:28.243532 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118
8243 23:51:28.246552 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8244 23:51:28.246659
8245 23:51:28.246748
8246 23:51:28.246827
8247 23:51:28.250197 [DramC_TX_OE_Calibration] TA2
8248 23:51:28.254562 Original DQ_B0 (3 6) =30, OEN = 27
8249 23:51:28.256878 Original DQ_B1 (3 6) =30, OEN = 27
8250 23:51:28.260168 24, 0x0, End_B0=24 End_B1=24
8251 23:51:28.260275 25, 0x0, End_B0=25 End_B1=25
8252 23:51:28.263306 26, 0x0, End_B0=26 End_B1=26
8253 23:51:28.266560 27, 0x0, End_B0=27 End_B1=27
8254 23:51:28.269703 28, 0x0, End_B0=28 End_B1=28
8255 23:51:28.273102 29, 0x0, End_B0=29 End_B1=29
8256 23:51:28.273213 30, 0x0, End_B0=30 End_B1=30
8257 23:51:28.277256 31, 0x4141, End_B0=30 End_B1=30
8258 23:51:28.279473 Byte0 end_step=30 best_step=27
8259 23:51:28.283248 Byte1 end_step=30 best_step=27
8260 23:51:28.286877 Byte0 TX OE(2T, 0.5T) = (3, 3)
8261 23:51:28.289678 Byte1 TX OE(2T, 0.5T) = (3, 3)
8262 23:51:28.289786
8263 23:51:28.289851
8264 23:51:28.296102 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8265 23:51:28.299499 CH0 RK1: MR19=303, MR18=160B
8266 23:51:28.306403 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8267 23:51:28.311032 [RxdqsGatingPostProcess] freq 1600
8268 23:51:28.313325 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8269 23:51:28.316092 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 23:51:28.319922 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 23:51:28.322890 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 23:51:28.326134 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 23:51:28.329784 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 23:51:28.333498 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 23:51:28.336599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 23:51:28.339425 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 23:51:28.343155 Pre-setting of DQS Precalculation
8278 23:51:28.346616 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8279 23:51:28.346727 ==
8280 23:51:28.349421 Dram Type= 6, Freq= 0, CH_1, rank 0
8281 23:51:28.352806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 23:51:28.352908 ==
8283 23:51:28.359317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 23:51:28.362744 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 23:51:28.369274 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 23:51:28.373198 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 23:51:28.382969 [CA 0] Center 42 (13~71) winsize 59
8288 23:51:28.385984 [CA 1] Center 42 (13~71) winsize 59
8289 23:51:28.389427 [CA 2] Center 37 (9~66) winsize 58
8290 23:51:28.392935 [CA 3] Center 36 (7~65) winsize 59
8291 23:51:28.397556 [CA 4] Center 37 (8~67) winsize 60
8292 23:51:28.399464 [CA 5] Center 36 (7~66) winsize 60
8293 23:51:28.399590
8294 23:51:28.402962 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8295 23:51:28.403071
8296 23:51:28.406160 [CATrainingPosCal] consider 1 rank data
8297 23:51:28.409478 u2DelayCellTimex100 = 275/100 ps
8298 23:51:28.413410 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8299 23:51:28.420079 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8300 23:51:28.422768 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8301 23:51:28.426095 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8302 23:51:28.431008 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8303 23:51:28.433828 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8304 23:51:28.433934
8305 23:51:28.436957 CA PerBit enable=1, Macro0, CA PI delay=36
8306 23:51:28.437090
8307 23:51:28.439397 [CBTSetCACLKResult] CA Dly = 36
8308 23:51:28.439480 CS Dly: 9 (0~40)
8309 23:51:28.446017 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 23:51:28.450183 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 23:51:28.450301 ==
8312 23:51:28.453075 Dram Type= 6, Freq= 0, CH_1, rank 1
8313 23:51:28.456321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 23:51:28.456426 ==
8315 23:51:28.463437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 23:51:28.466126 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 23:51:28.470136 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 23:51:28.475778 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 23:51:28.485761 [CA 0] Center 42 (13~72) winsize 60
8320 23:51:28.489365 [CA 1] Center 43 (14~72) winsize 59
8321 23:51:28.492298 [CA 2] Center 37 (8~67) winsize 60
8322 23:51:28.495765 [CA 3] Center 36 (7~66) winsize 60
8323 23:51:28.499302 [CA 4] Center 37 (8~67) winsize 60
8324 23:51:28.502490 [CA 5] Center 36 (7~66) winsize 60
8325 23:51:28.502603
8326 23:51:28.505732 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 23:51:28.505826
8328 23:51:28.509241 [CATrainingPosCal] consider 2 rank data
8329 23:51:28.512551 u2DelayCellTimex100 = 275/100 ps
8330 23:51:28.515436 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8331 23:51:28.522517 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8332 23:51:28.526583 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8333 23:51:28.529230 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8334 23:51:28.532351 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8335 23:51:28.536313 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8336 23:51:28.536438
8337 23:51:28.539363 CA PerBit enable=1, Macro0, CA PI delay=36
8338 23:51:28.539480
8339 23:51:28.542720 [CBTSetCACLKResult] CA Dly = 36
8340 23:51:28.542863 CS Dly: 11 (0~45)
8341 23:51:28.549248 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 23:51:28.552459 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 23:51:28.552580
8344 23:51:28.555618 ----->DramcWriteLeveling(PI) begin...
8345 23:51:28.555719 ==
8346 23:51:28.559199 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 23:51:28.562534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 23:51:28.562658 ==
8349 23:51:28.566011 Write leveling (Byte 0): 24 => 24
8350 23:51:28.570029 Write leveling (Byte 1): 29 => 29
8351 23:51:28.572721 DramcWriteLeveling(PI) end<-----
8352 23:51:28.572854
8353 23:51:28.572954 ==
8354 23:51:28.576533 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 23:51:28.582730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 23:51:28.582874 ==
8357 23:51:28.582970 [Gating] SW mode calibration
8358 23:51:28.592362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8359 23:51:28.595394 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8360 23:51:28.599130 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 23:51:28.605547 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:51:28.608925 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 23:51:28.612112 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 23:51:28.618831 1 4 16 | B1->B0 | 2626 2323 | 1 1 | (1 1) (1 1)
8365 23:51:28.622684 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8366 23:51:28.626213 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 23:51:28.632350 1 4 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
8368 23:51:28.636324 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 23:51:28.639314 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 23:51:28.645624 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 23:51:28.648853 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8372 23:51:28.652713 1 5 16 | B1->B0 | 2f2f 2e2e | 0 1 | (0 1) (1 0)
8373 23:51:28.659091 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (1 0) (0 0)
8374 23:51:28.662705 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 23:51:28.666015 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 23:51:28.673846 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 23:51:28.676325 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 23:51:28.678819 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 23:51:28.682199 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 23:51:28.688839 1 6 16 | B1->B0 | 3838 3636 | 0 1 | (0 0) (0 0)
8381 23:51:28.692773 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 23:51:28.696191 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 23:51:28.702404 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 23:51:28.706316 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 23:51:28.709114 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 23:51:28.716904 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 23:51:28.719203 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8388 23:51:28.722236 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 23:51:28.728922 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8390 23:51:28.732452 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:51:28.735692 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:51:28.742583 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:51:28.745485 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:51:28.748890 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:51:28.755825 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:51:28.758884 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:51:28.762705 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:51:28.769451 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:51:28.772297 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:51:28.775470 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:51:28.782382 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:51:28.785593 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:51:28.789531 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8404 23:51:28.792388 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8405 23:51:28.795793 Total UI for P1: 0, mck2ui 16
8406 23:51:28.798907 best dqsien dly found for B1: ( 1, 9, 12)
8407 23:51:28.805635 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 23:51:28.805757 Total UI for P1: 0, mck2ui 16
8409 23:51:28.812667 best dqsien dly found for B0: ( 1, 9, 16)
8410 23:51:28.816293 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8411 23:51:28.819187 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8412 23:51:28.819278
8413 23:51:28.822025 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8414 23:51:28.825754 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8415 23:51:28.828842 [Gating] SW calibration Done
8416 23:51:28.828930 ==
8417 23:51:28.832820 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 23:51:28.835824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 23:51:28.835917 ==
8420 23:51:28.839257 RX Vref Scan: 0
8421 23:51:28.839343
8422 23:51:28.839408 RX Vref 0 -> 0, step: 1
8423 23:51:28.843432
8424 23:51:28.843520 RX Delay 0 -> 252, step: 8
8425 23:51:28.845338 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8426 23:51:28.852832 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8427 23:51:28.855476 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8428 23:51:28.858692 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8429 23:51:28.862462 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8430 23:51:28.865307 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8431 23:51:28.872230 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8432 23:51:28.875467 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8433 23:51:28.878737 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8434 23:51:28.882403 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8435 23:51:28.885984 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8436 23:51:28.892393 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8437 23:51:28.895179 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8438 23:51:28.898958 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8439 23:51:28.902002 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8440 23:51:28.905409 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8441 23:51:28.908753 ==
8442 23:51:28.912617 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 23:51:28.915486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 23:51:28.915587 ==
8445 23:51:28.915654 DQS Delay:
8446 23:51:28.918959 DQS0 = 0, DQS1 = 0
8447 23:51:28.919045 DQM Delay:
8448 23:51:28.922050 DQM0 = 135, DQM1 = 127
8449 23:51:28.922134 DQ Delay:
8450 23:51:28.925239 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8451 23:51:28.928735 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8452 23:51:28.932731 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8453 23:51:28.935730 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8454 23:51:28.935823
8455 23:51:28.935887
8456 23:51:28.935946 ==
8457 23:51:28.938840 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 23:51:28.945568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 23:51:28.945681 ==
8460 23:51:28.945748
8461 23:51:28.945808
8462 23:51:28.945864 TX Vref Scan disable
8463 23:51:28.949303 == TX Byte 0 ==
8464 23:51:28.952453 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8465 23:51:28.955502 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8466 23:51:28.959561 == TX Byte 1 ==
8467 23:51:28.962548 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8468 23:51:28.965736 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8469 23:51:28.969035 ==
8470 23:51:28.973592 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 23:51:28.975397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 23:51:28.975487 ==
8473 23:51:28.989432
8474 23:51:28.992820 TX Vref early break, caculate TX vref
8475 23:51:28.995863 TX Vref=16, minBit 11, minWin=20, winSum=360
8476 23:51:28.999220 TX Vref=18, minBit 8, minWin=21, winSum=371
8477 23:51:29.003094 TX Vref=20, minBit 8, minWin=22, winSum=385
8478 23:51:29.006464 TX Vref=22, minBit 8, minWin=22, winSum=392
8479 23:51:29.009089 TX Vref=24, minBit 8, minWin=24, winSum=405
8480 23:51:29.015827 TX Vref=26, minBit 8, minWin=24, winSum=411
8481 23:51:29.019527 TX Vref=28, minBit 8, minWin=25, winSum=418
8482 23:51:29.022392 TX Vref=30, minBit 8, minWin=25, winSum=417
8483 23:51:29.025738 TX Vref=32, minBit 0, minWin=24, winSum=409
8484 23:51:29.029544 TX Vref=34, minBit 8, minWin=23, winSum=400
8485 23:51:29.032610 TX Vref=36, minBit 8, minWin=23, winSum=387
8486 23:51:29.040381 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8487 23:51:29.040519
8488 23:51:29.042628 Final TX Range 0 Vref 28
8489 23:51:29.042714
8490 23:51:29.042777 ==
8491 23:51:29.046202 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:51:29.049281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:51:29.049373 ==
8494 23:51:29.049439
8495 23:51:29.049499
8496 23:51:29.053922 TX Vref Scan disable
8497 23:51:29.059173 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8498 23:51:29.059277 == TX Byte 0 ==
8499 23:51:29.063177 u2DelayCellOfst[0]=17 cells (5 PI)
8500 23:51:29.066141 u2DelayCellOfst[1]=10 cells (3 PI)
8501 23:51:29.069705 u2DelayCellOfst[2]=0 cells (0 PI)
8502 23:51:29.072964 u2DelayCellOfst[3]=7 cells (2 PI)
8503 23:51:29.076550 u2DelayCellOfst[4]=7 cells (2 PI)
8504 23:51:29.079936 u2DelayCellOfst[5]=21 cells (6 PI)
8505 23:51:29.082953 u2DelayCellOfst[6]=17 cells (5 PI)
8506 23:51:29.083056 u2DelayCellOfst[7]=7 cells (2 PI)
8507 23:51:29.089810 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8508 23:51:29.093392 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8509 23:51:29.096818 == TX Byte 1 ==
8510 23:51:29.096908 u2DelayCellOfst[8]=0 cells (0 PI)
8511 23:51:29.100192 u2DelayCellOfst[9]=7 cells (2 PI)
8512 23:51:29.102551 u2DelayCellOfst[10]=10 cells (3 PI)
8513 23:51:29.106479 u2DelayCellOfst[11]=7 cells (2 PI)
8514 23:51:29.109907 u2DelayCellOfst[12]=14 cells (4 PI)
8515 23:51:29.113208 u2DelayCellOfst[13]=17 cells (5 PI)
8516 23:51:29.115957 u2DelayCellOfst[14]=17 cells (5 PI)
8517 23:51:29.119554 u2DelayCellOfst[15]=17 cells (5 PI)
8518 23:51:29.123815 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8519 23:51:29.129133 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8520 23:51:29.129241 DramC Write-DBI on
8521 23:51:29.129307 ==
8522 23:51:29.132911 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 23:51:29.136322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 23:51:29.139355 ==
8525 23:51:29.139443
8526 23:51:29.139507
8527 23:51:29.139567 TX Vref Scan disable
8528 23:51:29.142404 == TX Byte 0 ==
8529 23:51:29.145999 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8530 23:51:29.149668 == TX Byte 1 ==
8531 23:51:29.152880 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8532 23:51:29.153005 DramC Write-DBI off
8533 23:51:29.155809
8534 23:51:29.155894 [DATLAT]
8535 23:51:29.155957 Freq=1600, CH1 RK0
8536 23:51:29.156017
8537 23:51:29.159053 DATLAT Default: 0xf
8538 23:51:29.159164 0, 0xFFFF, sum = 0
8539 23:51:29.162887 1, 0xFFFF, sum = 0
8540 23:51:29.162973 2, 0xFFFF, sum = 0
8541 23:51:29.166170 3, 0xFFFF, sum = 0
8542 23:51:29.168927 4, 0xFFFF, sum = 0
8543 23:51:29.169066 5, 0xFFFF, sum = 0
8544 23:51:29.173648 6, 0xFFFF, sum = 0
8545 23:51:29.173738 7, 0xFFFF, sum = 0
8546 23:51:29.175810 8, 0xFFFF, sum = 0
8547 23:51:29.175894 9, 0xFFFF, sum = 0
8548 23:51:29.179928 10, 0xFFFF, sum = 0
8549 23:51:29.180015 11, 0xFFFF, sum = 0
8550 23:51:29.183220 12, 0xFFFF, sum = 0
8551 23:51:29.183305 13, 0xFFFF, sum = 0
8552 23:51:29.185680 14, 0x0, sum = 1
8553 23:51:29.185764 15, 0x0, sum = 2
8554 23:51:29.189630 16, 0x0, sum = 3
8555 23:51:29.189722 17, 0x0, sum = 4
8556 23:51:29.192626 best_step = 15
8557 23:51:29.192712
8558 23:51:29.192775 ==
8559 23:51:29.196319 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 23:51:29.198970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 23:51:29.199055 ==
8562 23:51:29.199119 RX Vref Scan: 1
8563 23:51:29.199179
8564 23:51:29.202625 Set Vref Range= 24 -> 127
8565 23:51:29.202712
8566 23:51:29.206547 RX Vref 24 -> 127, step: 1
8567 23:51:29.206638
8568 23:51:29.209162 RX Delay 19 -> 252, step: 4
8569 23:51:29.209246
8570 23:51:29.212781 Set Vref, RX VrefLevel [Byte0]: 24
8571 23:51:29.216209 [Byte1]: 24
8572 23:51:29.216305
8573 23:51:29.219430 Set Vref, RX VrefLevel [Byte0]: 25
8574 23:51:29.222377 [Byte1]: 25
8575 23:51:29.222463
8576 23:51:29.225706 Set Vref, RX VrefLevel [Byte0]: 26
8577 23:51:29.229548 [Byte1]: 26
8578 23:51:29.232854
8579 23:51:29.232982 Set Vref, RX VrefLevel [Byte0]: 27
8580 23:51:29.235953 [Byte1]: 27
8581 23:51:29.241390
8582 23:51:29.241493 Set Vref, RX VrefLevel [Byte0]: 28
8583 23:51:29.243978 [Byte1]: 28
8584 23:51:29.247762
8585 23:51:29.247854 Set Vref, RX VrefLevel [Byte0]: 29
8586 23:51:29.252178 [Byte1]: 29
8587 23:51:29.255858
8588 23:51:29.255952 Set Vref, RX VrefLevel [Byte0]: 30
8589 23:51:29.259410 [Byte1]: 30
8590 23:51:29.263696
8591 23:51:29.263793 Set Vref, RX VrefLevel [Byte0]: 31
8592 23:51:29.266431 [Byte1]: 31
8593 23:51:29.271080
8594 23:51:29.271174 Set Vref, RX VrefLevel [Byte0]: 32
8595 23:51:29.273977 [Byte1]: 32
8596 23:51:29.278128
8597 23:51:29.278222 Set Vref, RX VrefLevel [Byte0]: 33
8598 23:51:29.281753 [Byte1]: 33
8599 23:51:29.286305
8600 23:51:29.286403 Set Vref, RX VrefLevel [Byte0]: 34
8601 23:51:29.288812 [Byte1]: 34
8602 23:51:29.293435
8603 23:51:29.293537 Set Vref, RX VrefLevel [Byte0]: 35
8604 23:51:29.297043 [Byte1]: 35
8605 23:51:29.302016
8606 23:51:29.302113 Set Vref, RX VrefLevel [Byte0]: 36
8607 23:51:29.304856 [Byte1]: 36
8608 23:51:29.308724
8609 23:51:29.308812 Set Vref, RX VrefLevel [Byte0]: 37
8610 23:51:29.312247 [Byte1]: 37
8611 23:51:29.316295
8612 23:51:29.316393 Set Vref, RX VrefLevel [Byte0]: 38
8613 23:51:29.320937 [Byte1]: 38
8614 23:51:29.324576
8615 23:51:29.324658 Set Vref, RX VrefLevel [Byte0]: 39
8616 23:51:29.327122 [Byte1]: 39
8617 23:51:29.331157
8618 23:51:29.331239 Set Vref, RX VrefLevel [Byte0]: 40
8619 23:51:29.334537 [Byte1]: 40
8620 23:51:29.339508
8621 23:51:29.339590 Set Vref, RX VrefLevel [Byte0]: 41
8622 23:51:29.342328 [Byte1]: 41
8623 23:51:29.346316
8624 23:51:29.346400 Set Vref, RX VrefLevel [Byte0]: 42
8625 23:51:29.350623 [Byte1]: 42
8626 23:51:29.353893
8627 23:51:29.353977 Set Vref, RX VrefLevel [Byte0]: 43
8628 23:51:29.358366 [Byte1]: 43
8629 23:51:29.361761
8630 23:51:29.361843 Set Vref, RX VrefLevel [Byte0]: 44
8631 23:51:29.364678 [Byte1]: 44
8632 23:51:29.368879
8633 23:51:29.369029 Set Vref, RX VrefLevel [Byte0]: 45
8634 23:51:29.372215 [Byte1]: 45
8635 23:51:29.377765
8636 23:51:29.377849 Set Vref, RX VrefLevel [Byte0]: 46
8637 23:51:29.380120 [Byte1]: 46
8638 23:51:29.384225
8639 23:51:29.384311 Set Vref, RX VrefLevel [Byte0]: 47
8640 23:51:29.387286 [Byte1]: 47
8641 23:51:29.391613
8642 23:51:29.391696 Set Vref, RX VrefLevel [Byte0]: 48
8643 23:51:29.396222 [Byte1]: 48
8644 23:51:29.399440
8645 23:51:29.399525 Set Vref, RX VrefLevel [Byte0]: 49
8646 23:51:29.402436 [Byte1]: 49
8647 23:51:29.407060
8648 23:51:29.407142 Set Vref, RX VrefLevel [Byte0]: 50
8649 23:51:29.410331 [Byte1]: 50
8650 23:51:29.414383
8651 23:51:29.414466 Set Vref, RX VrefLevel [Byte0]: 51
8652 23:51:29.417972 [Byte1]: 51
8653 23:51:29.422013
8654 23:51:29.422094 Set Vref, RX VrefLevel [Byte0]: 52
8655 23:51:29.425308 [Byte1]: 52
8656 23:51:29.430047
8657 23:51:29.430130 Set Vref, RX VrefLevel [Byte0]: 53
8658 23:51:29.433491 [Byte1]: 53
8659 23:51:29.437538
8660 23:51:29.437621 Set Vref, RX VrefLevel [Byte0]: 54
8661 23:51:29.440525 [Byte1]: 54
8662 23:51:29.445005
8663 23:51:29.445102 Set Vref, RX VrefLevel [Byte0]: 55
8664 23:51:29.448828 [Byte1]: 55
8665 23:51:29.452388
8666 23:51:29.452470 Set Vref, RX VrefLevel [Byte0]: 56
8667 23:51:29.456682 [Byte1]: 56
8668 23:51:29.460459
8669 23:51:29.460542 Set Vref, RX VrefLevel [Byte0]: 57
8670 23:51:29.463123 [Byte1]: 57
8671 23:51:29.467557
8672 23:51:29.467640 Set Vref, RX VrefLevel [Byte0]: 58
8673 23:51:29.470862 [Byte1]: 58
8674 23:51:29.475168
8675 23:51:29.475252 Set Vref, RX VrefLevel [Byte0]: 59
8676 23:51:29.478823 [Byte1]: 59
8677 23:51:29.482726
8678 23:51:29.482810 Set Vref, RX VrefLevel [Byte0]: 60
8679 23:51:29.486128 [Byte1]: 60
8680 23:51:29.490262
8681 23:51:29.490344 Set Vref, RX VrefLevel [Byte0]: 61
8682 23:51:29.493951 [Byte1]: 61
8683 23:51:29.498248
8684 23:51:29.498331 Set Vref, RX VrefLevel [Byte0]: 62
8685 23:51:29.501317 [Byte1]: 62
8686 23:51:29.505694
8687 23:51:29.505777 Set Vref, RX VrefLevel [Byte0]: 63
8688 23:51:29.509603 [Byte1]: 63
8689 23:51:29.513108
8690 23:51:29.513192 Set Vref, RX VrefLevel [Byte0]: 64
8691 23:51:29.516488 [Byte1]: 64
8692 23:51:29.520705
8693 23:51:29.520817 Set Vref, RX VrefLevel [Byte0]: 65
8694 23:51:29.524285 [Byte1]: 65
8695 23:51:29.528705
8696 23:51:29.528817 Set Vref, RX VrefLevel [Byte0]: 66
8697 23:51:29.531379 [Byte1]: 66
8698 23:51:29.535613
8699 23:51:29.535725 Set Vref, RX VrefLevel [Byte0]: 67
8700 23:51:29.539040 [Byte1]: 67
8701 23:51:29.543257
8702 23:51:29.543345 Set Vref, RX VrefLevel [Byte0]: 68
8703 23:51:29.546560 [Byte1]: 68
8704 23:51:29.551141
8705 23:51:29.551235 Set Vref, RX VrefLevel [Byte0]: 69
8706 23:51:29.554154 [Byte1]: 69
8707 23:51:29.558507
8708 23:51:29.558595 Set Vref, RX VrefLevel [Byte0]: 70
8709 23:51:29.562237 [Byte1]: 70
8710 23:51:29.566229
8711 23:51:29.566318 Set Vref, RX VrefLevel [Byte0]: 71
8712 23:51:29.569356 [Byte1]: 71
8713 23:51:29.573580
8714 23:51:29.573671 Set Vref, RX VrefLevel [Byte0]: 72
8715 23:51:29.577141 [Byte1]: 72
8716 23:51:29.581355
8717 23:51:29.581442 Set Vref, RX VrefLevel [Byte0]: 73
8718 23:51:29.584435 [Byte1]: 73
8719 23:51:29.590192
8720 23:51:29.590285 Set Vref, RX VrefLevel [Byte0]: 74
8721 23:51:29.591946 [Byte1]: 74
8722 23:51:29.596247
8723 23:51:29.596334 Set Vref, RX VrefLevel [Byte0]: 75
8724 23:51:29.600075 [Byte1]: 75
8725 23:51:29.603699
8726 23:51:29.603784 Final RX Vref Byte 0 = 59 to rank0
8727 23:51:29.607285 Final RX Vref Byte 1 = 57 to rank0
8728 23:51:29.610810 Final RX Vref Byte 0 = 59 to rank1
8729 23:51:29.613710 Final RX Vref Byte 1 = 57 to rank1==
8730 23:51:29.617178 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 23:51:29.623920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 23:51:29.624021 ==
8733 23:51:29.624087 DQS Delay:
8734 23:51:29.624148 DQS0 = 0, DQS1 = 0
8735 23:51:29.627308 DQM Delay:
8736 23:51:29.627391 DQM0 = 131, DQM1 = 124
8737 23:51:29.630906 DQ Delay:
8738 23:51:29.634228 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8739 23:51:29.637192 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8740 23:51:29.640919 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8741 23:51:29.644556 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8742 23:51:29.644646
8743 23:51:29.644710
8744 23:51:29.644769
8745 23:51:29.647230 [DramC_TX_OE_Calibration] TA2
8746 23:51:29.650815 Original DQ_B0 (3 6) =30, OEN = 27
8747 23:51:29.654039 Original DQ_B1 (3 6) =30, OEN = 27
8748 23:51:29.657371 24, 0x0, End_B0=24 End_B1=24
8749 23:51:29.657481 25, 0x0, End_B0=25 End_B1=25
8750 23:51:29.660600 26, 0x0, End_B0=26 End_B1=26
8751 23:51:29.664138 27, 0x0, End_B0=27 End_B1=27
8752 23:51:29.667269 28, 0x0, End_B0=28 End_B1=28
8753 23:51:29.667376 29, 0x0, End_B0=29 End_B1=29
8754 23:51:29.671122 30, 0x0, End_B0=30 End_B1=30
8755 23:51:29.674466 31, 0x4141, End_B0=30 End_B1=30
8756 23:51:29.677462 Byte0 end_step=30 best_step=27
8757 23:51:29.680587 Byte1 end_step=30 best_step=27
8758 23:51:29.684081 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 23:51:29.684189 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 23:51:29.684256
8761 23:51:29.684315
8762 23:51:29.694768 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8763 23:51:29.698268 CH1 RK0: MR19=302, MR18=15FF
8764 23:51:29.700958 CH1_RK0: MR19=0x302, MR18=0x15FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8765 23:51:29.704435
8766 23:51:29.707734 ----->DramcWriteLeveling(PI) begin...
8767 23:51:29.707842 ==
8768 23:51:29.710503 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 23:51:29.714081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 23:51:29.714212 ==
8771 23:51:29.717653 Write leveling (Byte 0): 22 => 22
8772 23:51:29.721078 Write leveling (Byte 1): 28 => 28
8773 23:51:29.724170 DramcWriteLeveling(PI) end<-----
8774 23:51:29.724306
8775 23:51:29.724399 ==
8776 23:51:29.728227 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 23:51:29.730821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 23:51:29.730916 ==
8779 23:51:29.733975 [Gating] SW mode calibration
8780 23:51:29.740511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 23:51:29.748482 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 23:51:29.750942 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 23:51:29.754046 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:51:29.761427 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8785 23:51:29.764457 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8786 23:51:29.767830 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 23:51:29.770982 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 23:51:29.777465 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 23:51:29.780704 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 23:51:29.784225 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 23:51:29.790477 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8792 23:51:29.795131 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
8793 23:51:29.797542 1 5 12 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (0 0)
8794 23:51:29.803840 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 23:51:29.807286 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:51:29.810416 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:51:29.817383 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 23:51:29.820870 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 23:51:29.824163 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8800 23:51:29.831218 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8801 23:51:29.834265 1 6 12 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
8802 23:51:29.838616 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 23:51:29.844339 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 23:51:29.847578 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:51:29.851451 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 23:51:29.854870 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 23:51:29.861005 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 23:51:29.864399 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 23:51:29.867276 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8810 23:51:29.874747 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8811 23:51:29.878000 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:51:29.880932 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:51:29.888597 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:51:29.891397 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:51:29.894375 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:51:29.901531 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:51:29.904216 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:51:29.908054 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:51:29.915001 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:51:29.917486 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:51:29.920709 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:51:29.927372 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:51:29.930731 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:51:29.934155 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8825 23:51:29.941279 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 23:51:29.941381 Total UI for P1: 0, mck2ui 16
8827 23:51:29.944598 best dqsien dly found for B0: ( 1, 9, 8)
8828 23:51:29.951123 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8829 23:51:29.954696 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 23:51:29.958142 Total UI for P1: 0, mck2ui 16
8831 23:51:29.961284 best dqsien dly found for B1: ( 1, 9, 14)
8832 23:51:29.964093 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8833 23:51:29.967877 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8834 23:51:29.967960
8835 23:51:29.970889 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8836 23:51:29.974197 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8837 23:51:29.977350 [Gating] SW calibration Done
8838 23:51:29.977434 ==
8839 23:51:29.981629 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:51:29.987751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:51:29.987842 ==
8842 23:51:29.987907 RX Vref Scan: 0
8843 23:51:29.987968
8844 23:51:29.990649 RX Vref 0 -> 0, step: 1
8845 23:51:29.990731
8846 23:51:29.993853 RX Delay 0 -> 252, step: 8
8847 23:51:29.997424 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8848 23:51:30.001054 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8849 23:51:30.005048 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8850 23:51:30.007765 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8851 23:51:30.014185 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8852 23:51:30.017285 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8853 23:51:30.020596 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8854 23:51:30.024117 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8855 23:51:30.027785 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8856 23:51:30.034846 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8857 23:51:30.037997 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8858 23:51:30.041917 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8859 23:51:30.044335 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8860 23:51:30.047776 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8861 23:51:30.054067 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8862 23:51:30.057367 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8863 23:51:30.057500 ==
8864 23:51:30.060781 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 23:51:30.064059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 23:51:30.064174 ==
8867 23:51:30.067586 DQS Delay:
8868 23:51:30.067700 DQS0 = 0, DQS1 = 0
8869 23:51:30.067793 DQM Delay:
8870 23:51:30.070991 DQM0 = 132, DQM1 = 127
8871 23:51:30.071102 DQ Delay:
8872 23:51:30.074401 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8873 23:51:30.077855 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =127
8874 23:51:30.081060 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8875 23:51:30.087817 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8876 23:51:30.087948
8877 23:51:30.088047
8878 23:51:30.088135 ==
8879 23:51:30.091039 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:51:30.093896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:51:30.094014 ==
8882 23:51:30.094107
8883 23:51:30.094197
8884 23:51:30.097718 TX Vref Scan disable
8885 23:51:30.097833 == TX Byte 0 ==
8886 23:51:30.104276 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8887 23:51:30.107757 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8888 23:51:30.107883 == TX Byte 1 ==
8889 23:51:30.114000 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8890 23:51:30.119084 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8891 23:51:30.119244 ==
8892 23:51:30.120749 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 23:51:30.123871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 23:51:30.123981 ==
8895 23:51:30.139329
8896 23:51:30.142689 TX Vref early break, caculate TX vref
8897 23:51:30.145783 TX Vref=16, minBit 0, minWin=22, winSum=373
8898 23:51:30.149150 TX Vref=18, minBit 9, minWin=22, winSum=385
8899 23:51:30.152662 TX Vref=20, minBit 8, minWin=23, winSum=393
8900 23:51:30.155682 TX Vref=22, minBit 8, minWin=24, winSum=400
8901 23:51:30.158999 TX Vref=24, minBit 15, minWin=24, winSum=406
8902 23:51:30.165586 TX Vref=26, minBit 1, minWin=26, winSum=422
8903 23:51:30.169570 TX Vref=28, minBit 11, minWin=25, winSum=422
8904 23:51:30.172064 TX Vref=30, minBit 2, minWin=25, winSum=418
8905 23:51:30.175981 TX Vref=32, minBit 3, minWin=25, winSum=415
8906 23:51:30.178923 TX Vref=34, minBit 0, minWin=24, winSum=402
8907 23:51:30.186163 TX Vref=36, minBit 0, minWin=24, winSum=395
8908 23:51:30.188920 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 26
8909 23:51:30.189076
8910 23:51:30.192506 Final TX Range 0 Vref 26
8911 23:51:30.192619
8912 23:51:30.192712 ==
8913 23:51:30.195715 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 23:51:30.200084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 23:51:30.200211 ==
8916 23:51:30.200304
8917 23:51:30.202519
8918 23:51:30.202622 TX Vref Scan disable
8919 23:51:30.209013 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8920 23:51:30.209139 == TX Byte 0 ==
8921 23:51:30.212491 u2DelayCellOfst[0]=17 cells (5 PI)
8922 23:51:30.216220 u2DelayCellOfst[1]=10 cells (3 PI)
8923 23:51:30.218669 u2DelayCellOfst[2]=0 cells (0 PI)
8924 23:51:30.222702 u2DelayCellOfst[3]=3 cells (1 PI)
8925 23:51:30.225918 u2DelayCellOfst[4]=3 cells (1 PI)
8926 23:51:30.228819 u2DelayCellOfst[5]=17 cells (5 PI)
8927 23:51:30.232817 u2DelayCellOfst[6]=17 cells (5 PI)
8928 23:51:30.235598 u2DelayCellOfst[7]=3 cells (1 PI)
8929 23:51:30.238658 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8930 23:51:30.242409 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8931 23:51:30.245974 == TX Byte 1 ==
8932 23:51:30.248793 u2DelayCellOfst[8]=0 cells (0 PI)
8933 23:51:30.248918 u2DelayCellOfst[9]=3 cells (1 PI)
8934 23:51:30.252585 u2DelayCellOfst[10]=10 cells (3 PI)
8935 23:51:30.255766 u2DelayCellOfst[11]=3 cells (1 PI)
8936 23:51:30.259589 u2DelayCellOfst[12]=10 cells (3 PI)
8937 23:51:30.262623 u2DelayCellOfst[13]=17 cells (5 PI)
8938 23:51:30.265625 u2DelayCellOfst[14]=17 cells (5 PI)
8939 23:51:30.269283 u2DelayCellOfst[15]=14 cells (4 PI)
8940 23:51:30.272439 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8941 23:51:30.278890 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8942 23:51:30.279069 DramC Write-DBI on
8943 23:51:30.279222 ==
8944 23:51:30.282444 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 23:51:30.288756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 23:51:30.288919 ==
8947 23:51:30.289054
8948 23:51:30.289137
8949 23:51:30.289217 TX Vref Scan disable
8950 23:51:30.292707 == TX Byte 0 ==
8951 23:51:30.295774 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8952 23:51:30.299209 == TX Byte 1 ==
8953 23:51:30.303328 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8954 23:51:30.306416 DramC Write-DBI off
8955 23:51:30.306556
8956 23:51:30.306649 [DATLAT]
8957 23:51:30.306733 Freq=1600, CH1 RK1
8958 23:51:30.306816
8959 23:51:30.309239 DATLAT Default: 0xf
8960 23:51:30.309347 0, 0xFFFF, sum = 0
8961 23:51:30.312796 1, 0xFFFF, sum = 0
8962 23:51:30.312915 2, 0xFFFF, sum = 0
8963 23:51:30.316058 3, 0xFFFF, sum = 0
8964 23:51:30.316192 4, 0xFFFF, sum = 0
8965 23:51:30.320425 5, 0xFFFF, sum = 0
8966 23:51:30.322651 6, 0xFFFF, sum = 0
8967 23:51:30.322764 7, 0xFFFF, sum = 0
8968 23:51:30.325984 8, 0xFFFF, sum = 0
8969 23:51:30.326091 9, 0xFFFF, sum = 0
8970 23:51:30.330180 10, 0xFFFF, sum = 0
8971 23:51:30.330291 11, 0xFFFF, sum = 0
8972 23:51:30.333011 12, 0xFFFF, sum = 0
8973 23:51:30.333120 13, 0xFFFF, sum = 0
8974 23:51:30.336642 14, 0x0, sum = 1
8975 23:51:30.336754 15, 0x0, sum = 2
8976 23:51:30.339834 16, 0x0, sum = 3
8977 23:51:30.339943 17, 0x0, sum = 4
8978 23:51:30.342511 best_step = 15
8979 23:51:30.342614
8980 23:51:30.342707 ==
8981 23:51:30.346385 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 23:51:30.350228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 23:51:30.350341 ==
8984 23:51:30.350434 RX Vref Scan: 0
8985 23:51:30.350521
8986 23:51:30.352778 RX Vref 0 -> 0, step: 1
8987 23:51:30.352881
8988 23:51:30.356142 RX Delay 11 -> 252, step: 4
8989 23:51:30.359198 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8990 23:51:30.366276 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8991 23:51:30.369571 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8992 23:51:30.372955 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8993 23:51:30.376084 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8994 23:51:30.380353 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8995 23:51:30.382960 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8996 23:51:30.389296 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8997 23:51:30.393201 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8998 23:51:30.396404 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8999 23:51:30.399866 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9000 23:51:30.402420 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9001 23:51:30.409437 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9002 23:51:30.412956 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9003 23:51:30.416005 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9004 23:51:30.419193 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9005 23:51:30.419297 ==
9006 23:51:30.422935 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 23:51:30.429363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 23:51:30.429472 ==
9009 23:51:30.429538 DQS Delay:
9010 23:51:30.433385 DQS0 = 0, DQS1 = 0
9011 23:51:30.433473 DQM Delay:
9012 23:51:30.433537 DQM0 = 130, DQM1 = 126
9013 23:51:30.436725 DQ Delay:
9014 23:51:30.440420 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9015 23:51:30.442537 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9016 23:51:30.446293 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9017 23:51:30.449539 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
9018 23:51:30.449627
9019 23:51:30.449692
9020 23:51:30.449750
9021 23:51:30.453381 [DramC_TX_OE_Calibration] TA2
9022 23:51:30.456001 Original DQ_B0 (3 6) =30, OEN = 27
9023 23:51:30.460147 Original DQ_B1 (3 6) =30, OEN = 27
9024 23:51:30.462844 24, 0x0, End_B0=24 End_B1=24
9025 23:51:30.462934 25, 0x0, End_B0=25 End_B1=25
9026 23:51:30.466195 26, 0x0, End_B0=26 End_B1=26
9027 23:51:30.469328 27, 0x0, End_B0=27 End_B1=27
9028 23:51:30.473296 28, 0x0, End_B0=28 End_B1=28
9029 23:51:30.476457 29, 0x0, End_B0=29 End_B1=29
9030 23:51:30.476548 30, 0x0, End_B0=30 End_B1=30
9031 23:51:30.479951 31, 0x4141, End_B0=30 End_B1=30
9032 23:51:30.483082 Byte0 end_step=30 best_step=27
9033 23:51:30.485994 Byte1 end_step=30 best_step=27
9034 23:51:30.489409 Byte0 TX OE(2T, 0.5T) = (3, 3)
9035 23:51:30.489498 Byte1 TX OE(2T, 0.5T) = (3, 3)
9036 23:51:30.493243
9037 23:51:30.493330
9038 23:51:30.499538 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9039 23:51:30.503053 CH1 RK1: MR19=303, MR18=D13
9040 23:51:30.509413 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9041 23:51:30.513407 [RxdqsGatingPostProcess] freq 1600
9042 23:51:30.516166 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9043 23:51:30.519231 best DQS0 dly(2T, 0.5T) = (1, 1)
9044 23:51:30.522757 best DQS1 dly(2T, 0.5T) = (1, 1)
9045 23:51:30.527348 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9046 23:51:30.529931 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9047 23:51:30.532802 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 23:51:30.536255 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 23:51:30.539858 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 23:51:30.542672 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 23:51:30.542758 Pre-setting of DQS Precalculation
9052 23:51:30.549379 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9053 23:51:30.556201 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9054 23:51:30.563016 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9055 23:51:30.563126
9056 23:51:30.563192
9057 23:51:30.566525 [Calibration Summary] 3200 Mbps
9058 23:51:30.569307 CH 0, Rank 0
9059 23:51:30.569396 SW Impedance : PASS
9060 23:51:30.572739 DUTY Scan : NO K
9061 23:51:30.575938 ZQ Calibration : PASS
9062 23:51:30.576026 Jitter Meter : NO K
9063 23:51:30.579141 CBT Training : PASS
9064 23:51:30.579228 Write leveling : PASS
9065 23:51:30.582595 RX DQS gating : PASS
9066 23:51:30.585955 RX DQ/DQS(RDDQC) : PASS
9067 23:51:30.586041 TX DQ/DQS : PASS
9068 23:51:30.589524 RX DATLAT : PASS
9069 23:51:30.592988 RX DQ/DQS(Engine): PASS
9070 23:51:30.593072 TX OE : PASS
9071 23:51:30.596147 All Pass.
9072 23:51:30.596232
9073 23:51:30.596296 CH 0, Rank 1
9074 23:51:30.599356 SW Impedance : PASS
9075 23:51:30.599440 DUTY Scan : NO K
9076 23:51:30.603121 ZQ Calibration : PASS
9077 23:51:30.606519 Jitter Meter : NO K
9078 23:51:30.606607 CBT Training : PASS
9079 23:51:30.610399 Write leveling : PASS
9080 23:51:30.612834 RX DQS gating : PASS
9081 23:51:30.612922 RX DQ/DQS(RDDQC) : PASS
9082 23:51:30.615731 TX DQ/DQS : PASS
9083 23:51:30.619278 RX DATLAT : PASS
9084 23:51:30.619400 RX DQ/DQS(Engine): PASS
9085 23:51:30.622617 TX OE : PASS
9086 23:51:30.622728 All Pass.
9087 23:51:30.622822
9088 23:51:30.626065 CH 1, Rank 0
9089 23:51:30.626172 SW Impedance : PASS
9090 23:51:30.629122 DUTY Scan : NO K
9091 23:51:30.632217 ZQ Calibration : PASS
9092 23:51:30.632324 Jitter Meter : NO K
9093 23:51:30.635819 CBT Training : PASS
9094 23:51:30.635928 Write leveling : PASS
9095 23:51:30.640112 RX DQS gating : PASS
9096 23:51:30.642816 RX DQ/DQS(RDDQC) : PASS
9097 23:51:30.642931 TX DQ/DQS : PASS
9098 23:51:30.645555 RX DATLAT : PASS
9099 23:51:30.649092 RX DQ/DQS(Engine): PASS
9100 23:51:30.649202 TX OE : PASS
9101 23:51:30.652278 All Pass.
9102 23:51:30.652382
9103 23:51:30.652473 CH 1, Rank 1
9104 23:51:30.655450 SW Impedance : PASS
9105 23:51:30.655554 DUTY Scan : NO K
9106 23:51:30.658851 ZQ Calibration : PASS
9107 23:51:30.662468 Jitter Meter : NO K
9108 23:51:30.662573 CBT Training : PASS
9109 23:51:30.665578 Write leveling : PASS
9110 23:51:30.669012 RX DQS gating : PASS
9111 23:51:30.669128 RX DQ/DQS(RDDQC) : PASS
9112 23:51:30.672231 TX DQ/DQS : PASS
9113 23:51:30.675529 RX DATLAT : PASS
9114 23:51:30.675633 RX DQ/DQS(Engine): PASS
9115 23:51:30.678824 TX OE : PASS
9116 23:51:30.678931 All Pass.
9117 23:51:30.679023
9118 23:51:30.682467 DramC Write-DBI on
9119 23:51:30.685720 PER_BANK_REFRESH: Hybrid Mode
9120 23:51:30.685826 TX_TRACKING: ON
9121 23:51:30.695758 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9122 23:51:30.702796 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9123 23:51:30.709137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9124 23:51:30.713004 [FAST_K] Save calibration result to emmc
9125 23:51:30.715303 sync common calibartion params.
9126 23:51:30.719556 sync cbt_mode0:1, 1:1
9127 23:51:30.719678 dram_init: ddr_geometry: 2
9128 23:51:30.722272 dram_init: ddr_geometry: 2
9129 23:51:30.725789 dram_init: ddr_geometry: 2
9130 23:51:30.728783 0:dram_rank_size:100000000
9131 23:51:30.728890 1:dram_rank_size:100000000
9132 23:51:30.735693 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9133 23:51:30.738878 DFS_SHUFFLE_HW_MODE: ON
9134 23:51:30.741957 dramc_set_vcore_voltage set vcore to 725000
9135 23:51:30.745544 Read voltage for 1600, 0
9136 23:51:30.745650 Vio18 = 0
9137 23:51:30.745740 Vcore = 725000
9138 23:51:30.748619 Vdram = 0
9139 23:51:30.748719 Vddq = 0
9140 23:51:30.748807 Vmddr = 0
9141 23:51:30.752021 switch to 3200 Mbps bootup
9142 23:51:30.752123 [DramcRunTimeConfig]
9143 23:51:30.755195 PHYPLL
9144 23:51:30.755299 DPM_CONTROL_AFTERK: ON
9145 23:51:30.758691 PER_BANK_REFRESH: ON
9146 23:51:30.761843 REFRESH_OVERHEAD_REDUCTION: ON
9147 23:51:30.761948 CMD_PICG_NEW_MODE: OFF
9148 23:51:30.765568 XRTWTW_NEW_MODE: ON
9149 23:51:30.765673 XRTRTR_NEW_MODE: ON
9150 23:51:30.768783 TX_TRACKING: ON
9151 23:51:30.768885 RDSEL_TRACKING: OFF
9152 23:51:30.772813 DQS Precalculation for DVFS: ON
9153 23:51:30.775829 RX_TRACKING: OFF
9154 23:51:30.775934 HW_GATING DBG: ON
9155 23:51:30.779329 ZQCS_ENABLE_LP4: ON
9156 23:51:30.779433 RX_PICG_NEW_MODE: ON
9157 23:51:30.781919 TX_PICG_NEW_MODE: ON
9158 23:51:30.782021 ENABLE_RX_DCM_DPHY: ON
9159 23:51:30.785544 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9160 23:51:30.789207 DUMMY_READ_FOR_TRACKING: OFF
9161 23:51:30.792508 !!! SPM_CONTROL_AFTERK: OFF
9162 23:51:30.796251 !!! SPM could not control APHY
9163 23:51:30.796360 IMPEDANCE_TRACKING: ON
9164 23:51:30.798640 TEMP_SENSOR: ON
9165 23:51:30.798742 HW_SAVE_FOR_SR: OFF
9166 23:51:30.802951 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9167 23:51:30.805631 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9168 23:51:30.809204 Read ODT Tracking: ON
9169 23:51:30.812503 Refresh Rate DeBounce: ON
9170 23:51:30.812613 DFS_NO_QUEUE_FLUSH: ON
9171 23:51:30.815511 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9172 23:51:30.819357 ENABLE_DFS_RUNTIME_MRW: OFF
9173 23:51:30.822149 DDR_RESERVE_NEW_MODE: ON
9174 23:51:30.822261 MR_CBT_SWITCH_FREQ: ON
9175 23:51:30.825420 =========================
9176 23:51:30.845177 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9177 23:51:30.847529 dram_init: ddr_geometry: 2
9178 23:51:30.865824 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9179 23:51:30.868848 dram_init: dram init end (result: 0)
9180 23:51:30.875420 DRAM-K: Full calibration passed in 24601 msecs
9181 23:51:30.878991 MRC: failed to locate region type 0.
9182 23:51:30.879106 DRAM rank0 size:0x100000000,
9183 23:51:30.882170 DRAM rank1 size=0x100000000
9184 23:51:30.892583 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9185 23:51:30.898960 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9186 23:51:30.905440 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9187 23:51:30.912247 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9188 23:51:30.915862 DRAM rank0 size:0x100000000,
9189 23:51:30.919435 DRAM rank1 size=0x100000000
9190 23:51:30.919527 CBMEM:
9191 23:51:30.922435 IMD: root @ 0xfffff000 254 entries.
9192 23:51:30.925736 IMD: root @ 0xffffec00 62 entries.
9193 23:51:30.928639 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9194 23:51:30.932167 WARNING: RO_VPD is uninitialized or empty.
9195 23:51:30.938807 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9196 23:51:30.945329 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9197 23:51:30.958356 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9198 23:51:30.970259 BS: romstage times (exec / console): total (unknown) / 24102 ms
9199 23:51:30.970394
9200 23:51:30.970458
9201 23:51:30.980054 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9202 23:51:30.983107 ARM64: Exception handlers installed.
9203 23:51:30.986416 ARM64: Testing exception
9204 23:51:30.989969 ARM64: Done test exception
9205 23:51:30.990094 Enumerating buses...
9206 23:51:30.992880 Show all devs... Before device enumeration.
9207 23:51:30.996077 Root Device: enabled 1
9208 23:51:30.999605 CPU_CLUSTER: 0: enabled 1
9209 23:51:30.999699 CPU: 00: enabled 1
9210 23:51:31.002857 Compare with tree...
9211 23:51:31.002941 Root Device: enabled 1
9212 23:51:31.005876 CPU_CLUSTER: 0: enabled 1
9213 23:51:31.009480 CPU: 00: enabled 1
9214 23:51:31.009608 Root Device scanning...
9215 23:51:31.012859 scan_static_bus for Root Device
9216 23:51:31.016367 CPU_CLUSTER: 0 enabled
9217 23:51:31.020275 scan_static_bus for Root Device done
9218 23:51:31.023089 scan_bus: bus Root Device finished in 8 msecs
9219 23:51:31.023186 done
9220 23:51:31.029493 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9221 23:51:31.033032 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9222 23:51:31.039836 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9223 23:51:31.043021 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9224 23:51:31.046790 Allocating resources...
9225 23:51:31.046884 Reading resources...
9226 23:51:31.053650 Root Device read_resources bus 0 link: 0
9227 23:51:31.053778 DRAM rank0 size:0x100000000,
9228 23:51:31.056896 DRAM rank1 size=0x100000000
9229 23:51:31.059602 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9230 23:51:31.062940 CPU: 00 missing read_resources
9231 23:51:31.066177 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9232 23:51:31.073841 Root Device read_resources bus 0 link: 0 done
9233 23:51:31.073958 Done reading resources.
9234 23:51:31.080301 Show resources in subtree (Root Device)...After reading.
9235 23:51:31.082957 Root Device child on link 0 CPU_CLUSTER: 0
9236 23:51:31.086303 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 23:51:31.096589 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 23:51:31.096722 CPU: 00
9239 23:51:31.099531 Root Device assign_resources, bus 0 link: 0
9240 23:51:31.103488 CPU_CLUSTER: 0 missing set_resources
9241 23:51:31.105952 Root Device assign_resources, bus 0 link: 0 done
9242 23:51:31.109494 Done setting resources.
9243 23:51:31.116555 Show resources in subtree (Root Device)...After assigning values.
9244 23:51:31.120218 Root Device child on link 0 CPU_CLUSTER: 0
9245 23:51:31.122860 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 23:51:31.132800 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 23:51:31.132949 CPU: 00
9248 23:51:31.135941 Done allocating resources.
9249 23:51:31.139774 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9250 23:51:31.143289 Enabling resources...
9251 23:51:31.143410 done.
9252 23:51:31.147155 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9253 23:51:31.149436 Initializing devices...
9254 23:51:31.153230 Root Device init
9255 23:51:31.153367 init hardware done!
9256 23:51:31.156519 0x00000018: ctrlr->caps
9257 23:51:31.156626 52.000 MHz: ctrlr->f_max
9258 23:51:31.160046 0.400 MHz: ctrlr->f_min
9259 23:51:31.163200 0x40ff8080: ctrlr->voltages
9260 23:51:31.163309 sclk: 390625
9261 23:51:31.166332 Bus Width = 1
9262 23:51:31.166441 sclk: 390625
9263 23:51:31.166534 Bus Width = 1
9264 23:51:31.169553 Early init status = 3
9265 23:51:31.173139 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9266 23:51:31.178353 in-header: 03 fc 00 00 01 00 00 00
9267 23:51:31.181511 in-data: 00
9268 23:51:31.185206 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9269 23:51:31.190448 in-header: 03 fd 00 00 00 00 00 00
9270 23:51:31.193935 in-data:
9271 23:51:31.196661 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9272 23:51:31.201555 in-header: 03 fc 00 00 01 00 00 00
9273 23:51:31.204449 in-data: 00
9274 23:51:31.208128 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9275 23:51:31.213303 in-header: 03 fd 00 00 00 00 00 00
9276 23:51:31.216616 in-data:
9277 23:51:31.221167 [SSUSB] Setting up USB HOST controller...
9278 23:51:31.223743 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9279 23:51:31.227226 [SSUSB] phy power-on done.
9280 23:51:31.230317 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9281 23:51:31.236763 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9282 23:51:31.240017 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9283 23:51:31.246989 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9284 23:51:31.253358 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9285 23:51:31.260253 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9286 23:51:31.267548 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9287 23:51:31.274268 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9288 23:51:31.274405 SPM: binary array size = 0x9dc
9289 23:51:31.280566 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9290 23:51:31.287539 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9291 23:51:31.293999 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9292 23:51:31.298379 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9293 23:51:31.301443 configure_display: Starting display init
9294 23:51:31.337153 anx7625_power_on_init: Init interface.
9295 23:51:31.340423 anx7625_disable_pd_protocol: Disabled PD feature.
9296 23:51:31.344074 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9297 23:51:31.371221 anx7625_start_dp_work: Secure OCM version=00
9298 23:51:31.374529 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9299 23:51:31.389237 sp_tx_get_edid_block: EDID Block = 1
9300 23:51:31.492905 Extracted contents:
9301 23:51:31.495422 header: 00 ff ff ff ff ff ff 00
9302 23:51:31.498513 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9303 23:51:31.501496 version: 01 04
9304 23:51:31.505294 basic params: 95 1f 11 78 0a
9305 23:51:31.508559 chroma info: 76 90 94 55 54 90 27 21 50 54
9306 23:51:31.512152 established: 00 00 00
9307 23:51:31.518396 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9308 23:51:31.521715 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9309 23:51:31.528244 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9310 23:51:31.535066 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9311 23:51:31.542354 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9312 23:51:31.544996 extensions: 00
9313 23:51:31.545114 checksum: fb
9314 23:51:31.545201
9315 23:51:31.548665 Manufacturer: IVO Model 57d Serial Number 0
9316 23:51:31.551594 Made week 0 of 2020
9317 23:51:31.551696 EDID version: 1.4
9318 23:51:31.555961 Digital display
9319 23:51:31.558401 6 bits per primary color channel
9320 23:51:31.558503 DisplayPort interface
9321 23:51:31.561498 Maximum image size: 31 cm x 17 cm
9322 23:51:31.565948 Gamma: 220%
9323 23:51:31.566055 Check DPMS levels
9324 23:51:31.568786 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9325 23:51:31.571584 First detailed timing is preferred timing
9326 23:51:31.575262 Established timings supported:
9327 23:51:31.578504 Standard timings supported:
9328 23:51:31.581671 Detailed timings
9329 23:51:31.584717 Hex of detail: 383680a07038204018303c0035ae10000019
9330 23:51:31.588143 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9331 23:51:31.594737 0780 0798 07c8 0820 hborder 0
9332 23:51:31.597980 0438 043b 0447 0458 vborder 0
9333 23:51:31.601992 -hsync -vsync
9334 23:51:31.602100 Did detailed timing
9335 23:51:31.607998 Hex of detail: 000000000000000000000000000000000000
9336 23:51:31.608110 Manufacturer-specified data, tag 0
9337 23:51:31.614853 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9338 23:51:31.617795 ASCII string: InfoVision
9339 23:51:31.622060 Hex of detail: 000000fe00523134304e574635205248200a
9340 23:51:31.624607 ASCII string: R140NWF5 RH
9341 23:51:31.624699 Checksum
9342 23:51:31.627829 Checksum: 0xfb (valid)
9343 23:51:31.631089 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9344 23:51:31.634214 DSI data_rate: 832800000 bps
9345 23:51:31.640921 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9346 23:51:31.644175 anx7625_parse_edid: pixelclock(138800).
9347 23:51:31.648298 hactive(1920), hsync(48), hfp(24), hbp(88)
9348 23:51:31.651104 vactive(1080), vsync(12), vfp(3), vbp(17)
9349 23:51:31.654455 anx7625_dsi_config: config dsi.
9350 23:51:31.660811 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9351 23:51:31.674054 anx7625_dsi_config: success to config DSI
9352 23:51:31.677865 anx7625_dp_start: MIPI phy setup OK.
9353 23:51:31.680689 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9354 23:51:31.684533 mtk_ddp_mode_set invalid vrefresh 60
9355 23:51:31.687537 main_disp_path_setup
9356 23:51:31.687624 ovl_layer_smi_id_en
9357 23:51:31.692010 ovl_layer_smi_id_en
9358 23:51:31.692096 ccorr_config
9359 23:51:31.692160 aal_config
9360 23:51:31.694751 gamma_config
9361 23:51:31.694845 postmask_config
9362 23:51:31.697396 dither_config
9363 23:51:31.700674 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9364 23:51:31.707170 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9365 23:51:31.711069 Root Device init finished in 555 msecs
9366 23:51:31.711161 CPU_CLUSTER: 0 init
9367 23:51:31.720594 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9368 23:51:31.723875 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9369 23:51:31.727484 APU_MBOX 0x190000b0 = 0x10001
9370 23:51:31.731130 APU_MBOX 0x190001b0 = 0x10001
9371 23:51:31.734156 APU_MBOX 0x190005b0 = 0x10001
9372 23:51:31.737405 APU_MBOX 0x190006b0 = 0x10001
9373 23:51:31.740345 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9374 23:51:31.753286 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9375 23:51:31.765648 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9376 23:51:31.772044 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9377 23:51:31.783738 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9378 23:51:31.793205 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9379 23:51:31.795949 CPU_CLUSTER: 0 init finished in 81 msecs
9380 23:51:31.799777 Devices initialized
9381 23:51:31.803092 Show all devs... After init.
9382 23:51:31.803187 Root Device: enabled 1
9383 23:51:31.806795 CPU_CLUSTER: 0: enabled 1
9384 23:51:31.809765 CPU: 00: enabled 1
9385 23:51:31.812830 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9386 23:51:31.816815 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9387 23:51:31.820154 ELOG: NV offset 0x57f000 size 0x1000
9388 23:51:31.826318 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9389 23:51:31.833328 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9390 23:51:31.835960 ELOG: Event(17) added with size 13 at 2024-05-29 23:51:31 UTC
9391 23:51:31.843195 ELOG: Event(16) added with size 11 at 2024-05-29 23:51:31 UTC
9392 23:51:31.949455 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9393 23:51:31.952520 out: cmd=0x121: 03 db 21 01 00 00 00 00
9394 23:51:31.955605 in-header: 03 4c 00 00 2c 00 00 00
9395 23:51:31.969927 in-data: 12 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9396 23:51:31.975964 ELOG: Event(A1) added with size 10 at 2024-05-29 23:51:32 UTC
9397 23:51:31.982456 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9398 23:51:31.986370 ELOG: Event(A0) added with size 9 at 2024-05-29 23:51:32 UTC
9399 23:51:31.990021 elog_add_boot_reason: Logged dev mode boot
9400 23:51:31.996019 BS: BS_POST_DEVICE entry times (exec / console): 104 / 74 ms
9401 23:51:32.000147 Finalize devices...
9402 23:51:32.000266 Devices finalized
9403 23:51:32.006008 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9404 23:51:32.009432 Writing coreboot table at 0xffe64000
9405 23:51:32.012764 0. 000000000010a000-0000000000113fff: RAMSTAGE
9406 23:51:32.016345 1. 0000000040000000-00000000400fffff: RAM
9407 23:51:32.019177 2. 0000000040100000-000000004032afff: RAMSTAGE
9408 23:51:32.023080 3. 000000004032b000-00000000545fffff: RAM
9409 23:51:32.029202 4. 0000000054600000-000000005465ffff: BL31
9410 23:51:32.032812 5. 0000000054660000-00000000ffe63fff: RAM
9411 23:51:32.035722 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9412 23:51:32.039211 7. 0000000100000000-000000023fffffff: RAM
9413 23:51:32.042788 Passing 5 GPIOs to payload:
9414 23:51:32.046386 NAME | PORT | POLARITY | VALUE
9415 23:51:32.053444 EC in RW | 0x000000aa | low | undefined
9416 23:51:32.056878 EC interrupt | 0x00000005 | low | undefined
9417 23:51:32.062777 TPM interrupt | 0x000000ab | high | undefined
9418 23:51:32.066219 SD card detect | 0x00000011 | high | undefined
9419 23:51:32.069268 speaker enable | 0x00000093 | high | undefined
9420 23:51:32.075801 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9421 23:51:32.079444 in-header: 03 f9 00 00 02 00 00 00
9422 23:51:32.079572 in-data: 02 00
9423 23:51:32.082724 ADC[4]: Raw value=900221 ID=7
9424 23:51:32.086565 ADC[3]: Raw value=213336 ID=1
9425 23:51:32.086687 RAM Code: 0x71
9426 23:51:32.089439 ADC[6]: Raw value=74926 ID=0
9427 23:51:32.093364 ADC[5]: Raw value=212229 ID=1
9428 23:51:32.093491 SKU Code: 0x1
9429 23:51:32.100108 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a74a
9430 23:51:32.100259 coreboot table: 964 bytes.
9431 23:51:32.102455 IMD ROOT 0. 0xfffff000 0x00001000
9432 23:51:32.106028 IMD SMALL 1. 0xffffe000 0x00001000
9433 23:51:32.109378 RO MCACHE 2. 0xffffc000 0x00001104
9434 23:51:32.112653 CONSOLE 3. 0xfff7c000 0x00080000
9435 23:51:32.116923 FMAP 4. 0xfff7b000 0x00000452
9436 23:51:32.119804 TIME STAMP 5. 0xfff7a000 0x00000910
9437 23:51:32.122451 VBOOT WORK 6. 0xfff66000 0x00014000
9438 23:51:32.125981 RAMOOPS 7. 0xffe66000 0x00100000
9439 23:51:32.128964 COREBOOT 8. 0xffe64000 0x00002000
9440 23:51:32.132930 IMD small region:
9441 23:51:32.136422 IMD ROOT 0. 0xffffec00 0x00000400
9442 23:51:32.139451 VPD 1. 0xffffeb80 0x0000006c
9443 23:51:32.142251 MMC STATUS 2. 0xffffeb60 0x00000004
9444 23:51:32.149348 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9445 23:51:32.149472 Probing TPM: done!
9446 23:51:32.152409 Connected to device vid:did:rid of 1ae0:0028:00
9447 23:51:32.164006 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9448 23:51:32.167637 Initialized TPM device CR50 revision 0
9449 23:51:32.171236 Checking cr50 for pending updates
9450 23:51:32.174654 Reading cr50 TPM mode
9451 23:51:32.183214 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9452 23:51:32.190968 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9453 23:51:32.229937 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9454 23:51:32.233974 Checking segment from ROM address 0x40100000
9455 23:51:32.236771 Checking segment from ROM address 0x4010001c
9456 23:51:32.243362 Loading segment from ROM address 0x40100000
9457 23:51:32.243512 code (compression=0)
9458 23:51:32.253487 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9459 23:51:32.259894 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9460 23:51:32.260042 it's not compressed!
9461 23:51:32.267569 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9462 23:51:32.269992 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9463 23:51:32.291414 Loading segment from ROM address 0x4010001c
9464 23:51:32.291594 Entry Point 0x80000000
9465 23:51:32.294602 Loaded segments
9466 23:51:32.298264 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9467 23:51:32.304794 Jumping to boot code at 0x80000000(0xffe64000)
9468 23:51:32.312312 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9469 23:51:32.318578 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9470 23:51:32.325618 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9471 23:51:32.329082 Checking segment from ROM address 0x40100000
9472 23:51:32.332351 Checking segment from ROM address 0x4010001c
9473 23:51:32.339495 Loading segment from ROM address 0x40100000
9474 23:51:32.339660 code (compression=1)
9475 23:51:32.346139 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9476 23:51:32.355826 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9477 23:51:32.355959 using LZMA
9478 23:51:32.364145 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9479 23:51:32.371219 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9480 23:51:32.374215 Loading segment from ROM address 0x4010001c
9481 23:51:32.374312 Entry Point 0x54601000
9482 23:51:32.377572 Loaded segments
9483 23:51:32.381213 NOTICE: MT8192 bl31_setup
9484 23:51:32.387848 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9485 23:51:32.391159 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9486 23:51:32.394491 WARNING: region 0:
9487 23:51:32.398324 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 23:51:32.398421 WARNING: region 1:
9489 23:51:32.404927 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9490 23:51:32.408394 WARNING: region 2:
9491 23:51:32.411146 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9492 23:51:32.414638 WARNING: region 3:
9493 23:51:32.418383 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 23:51:32.421620 WARNING: region 4:
9495 23:51:32.424464 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9496 23:51:32.428286 WARNING: region 5:
9497 23:51:32.431270 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 23:51:32.434654 WARNING: region 6:
9499 23:51:32.438044 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 23:51:32.438142 WARNING: region 7:
9501 23:51:32.446493 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 23:51:32.451461 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9503 23:51:32.454945 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9504 23:51:32.458415 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9505 23:51:32.464756 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9506 23:51:32.468761 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9507 23:51:32.471690 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9508 23:51:32.478116 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9509 23:51:32.481322 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9510 23:51:32.485337 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9511 23:51:32.491625 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9512 23:51:32.494576 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9513 23:51:32.498251 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9514 23:51:32.504593 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9515 23:51:32.507958 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9516 23:51:32.515204 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9517 23:51:32.518231 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9518 23:51:32.521517 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9519 23:51:32.527993 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9520 23:51:32.532336 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9521 23:51:32.535281 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9522 23:51:32.541661 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9523 23:51:32.544929 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9524 23:51:32.552220 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9525 23:51:32.555936 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9526 23:51:32.558800 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9527 23:51:32.565080 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9528 23:51:32.568632 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9529 23:51:32.572041 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9530 23:51:32.579481 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9531 23:51:32.581747 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9532 23:51:32.588817 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9533 23:51:32.592213 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9534 23:51:32.595892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9535 23:51:32.598899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9536 23:51:32.605599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9537 23:51:32.609267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9538 23:51:32.612111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9539 23:51:32.615345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9540 23:51:32.622043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9541 23:51:32.626000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9542 23:51:32.629299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9543 23:51:32.632791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9544 23:51:32.639175 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9545 23:51:32.643011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9546 23:51:32.645615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9547 23:51:32.648937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9548 23:51:32.656428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9549 23:51:32.659007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9550 23:51:32.662462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9551 23:51:32.669175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9552 23:51:32.673240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9553 23:51:32.679752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9554 23:51:32.682216 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9555 23:51:32.686237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9556 23:51:32.692826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9557 23:51:32.695578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9558 23:51:32.702372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9559 23:51:32.706088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9560 23:51:32.712459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9561 23:51:32.716045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9562 23:51:32.719429 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9563 23:51:32.726119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9564 23:51:32.729630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9565 23:51:32.736296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9566 23:51:32.739185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9567 23:51:32.745972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9568 23:51:32.749476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9569 23:51:32.752933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9570 23:51:32.759844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9571 23:51:32.763085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9572 23:51:32.769530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9573 23:51:32.773659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9574 23:51:32.776384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9575 23:51:32.784276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9576 23:51:32.786340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9577 23:51:32.793544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9578 23:51:32.796350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9579 23:51:32.803429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9580 23:51:32.807424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9581 23:51:32.809674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9582 23:51:32.816774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9583 23:51:32.819984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9584 23:51:32.826401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9585 23:51:32.830166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9586 23:51:32.837597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9587 23:51:32.840529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9588 23:51:32.843703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9589 23:51:32.850662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9590 23:51:32.853543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9591 23:51:32.860325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9592 23:51:32.863381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9593 23:51:32.866896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9594 23:51:32.873589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9595 23:51:32.877038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9596 23:51:32.883354 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9597 23:51:32.887139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9598 23:51:32.890523 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9599 23:51:32.897865 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9600 23:51:32.900182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9601 23:51:32.903434 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9602 23:51:32.907889 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9603 23:51:32.913762 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9604 23:51:32.916912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9605 23:51:32.924085 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9606 23:51:32.927132 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9607 23:51:32.930792 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9608 23:51:32.937212 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9609 23:51:32.940823 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9610 23:51:32.947323 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9611 23:51:32.951158 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9612 23:51:32.954192 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9613 23:51:32.960866 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9614 23:51:32.964579 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9615 23:51:32.971248 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9616 23:51:32.974417 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9617 23:51:32.977391 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9618 23:51:32.981642 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9619 23:51:32.987545 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9620 23:51:32.991172 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9621 23:51:32.994225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9622 23:51:32.997616 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9623 23:51:33.005131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9624 23:51:33.008862 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9625 23:51:33.011408 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9626 23:51:33.018516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9627 23:51:33.021664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9628 23:51:33.024544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9629 23:51:33.031275 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9630 23:51:33.034839 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9631 23:51:33.042996 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9632 23:51:33.044427 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9633 23:51:33.047834 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9634 23:51:33.055018 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9635 23:51:33.058387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9636 23:51:33.061634 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9637 23:51:33.068195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9638 23:51:33.071563 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9639 23:51:33.078678 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9640 23:51:33.081475 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9641 23:51:33.084664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9642 23:51:33.091519 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9643 23:51:33.096402 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9644 23:51:33.098462 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9645 23:51:33.104735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9646 23:51:33.108106 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9647 23:51:33.115882 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9648 23:51:33.118547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9649 23:51:33.121865 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9650 23:51:33.128651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9651 23:51:33.131782 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9652 23:51:33.135313 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9653 23:51:33.141872 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9654 23:51:33.145231 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9655 23:51:33.152162 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9656 23:51:33.155703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9657 23:51:33.158956 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9658 23:51:33.165557 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9659 23:51:33.168972 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9660 23:51:33.172068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9661 23:51:33.178885 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9662 23:51:33.182218 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9663 23:51:33.188775 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9664 23:51:33.192454 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9665 23:51:33.196056 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9666 23:51:33.202053 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9667 23:51:33.206204 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9668 23:51:33.209401 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9669 23:51:33.215406 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9670 23:51:33.218903 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9671 23:51:33.225424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9672 23:51:33.229353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9673 23:51:33.232672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9674 23:51:33.238794 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9675 23:51:33.242266 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9676 23:51:33.249640 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9677 23:51:33.252660 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9678 23:51:33.256605 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9679 23:51:33.263031 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9680 23:51:33.265626 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9681 23:51:33.269221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9682 23:51:33.276608 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9683 23:51:33.279105 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9684 23:51:33.283311 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9685 23:51:33.289591 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9686 23:51:33.293210 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9687 23:51:33.299912 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9688 23:51:33.302919 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9689 23:51:33.306261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9690 23:51:33.313206 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9691 23:51:33.316037 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9692 23:51:33.323219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9693 23:51:33.326498 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9694 23:51:33.333056 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9695 23:51:33.336130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9696 23:51:33.339548 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9697 23:51:33.346554 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9698 23:51:33.350588 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9699 23:51:33.356512 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9700 23:51:33.359495 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9701 23:51:33.363188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9702 23:51:33.370373 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9703 23:51:33.372813 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9704 23:51:33.379285 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9705 23:51:33.383265 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9706 23:51:33.386309 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9707 23:51:33.393168 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9708 23:51:33.396433 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9709 23:51:33.403358 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9710 23:51:33.406457 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9711 23:51:33.410000 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9712 23:51:33.416527 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9713 23:51:33.419424 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9714 23:51:33.426383 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9715 23:51:33.430333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9716 23:51:33.433077 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9717 23:51:33.439929 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9718 23:51:33.443144 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9719 23:51:33.449516 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9720 23:51:33.453406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9721 23:51:33.459814 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9722 23:51:33.463347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9723 23:51:33.466900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9724 23:51:33.473155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9725 23:51:33.476637 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9726 23:51:33.482755 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9727 23:51:33.486034 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9728 23:51:33.490504 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9729 23:51:33.496183 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9730 23:51:33.499642 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9731 23:51:33.503230 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9732 23:51:33.509678 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9733 23:51:33.513037 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9734 23:51:33.516486 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9735 23:51:33.520447 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9736 23:51:33.526263 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9737 23:51:33.530074 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9738 23:51:33.533008 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9739 23:51:33.539493 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9740 23:51:33.543221 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9741 23:51:33.546282 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9742 23:51:33.553014 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9743 23:51:33.558684 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9744 23:51:33.563203 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9745 23:51:33.566142 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9746 23:51:33.569741 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9747 23:51:33.577320 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9748 23:51:33.579501 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9749 23:51:33.583463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9750 23:51:33.590598 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9751 23:51:33.593156 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9752 23:51:33.597344 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9753 23:51:33.603684 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9754 23:51:33.606591 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9755 23:51:33.610207 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9756 23:51:33.616556 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9757 23:51:33.620209 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9758 23:51:33.626442 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9759 23:51:33.630038 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9760 23:51:33.634157 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9761 23:51:33.639928 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9762 23:51:33.642946 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9763 23:51:33.646210 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9764 23:51:33.652923 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9765 23:51:33.656723 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9766 23:51:33.659785 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9767 23:51:33.666396 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9768 23:51:33.670335 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9769 23:51:33.676445 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9770 23:51:33.680078 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9771 23:51:33.683428 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9772 23:51:33.686358 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9773 23:51:33.690091 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9774 23:51:33.696776 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9775 23:51:33.700098 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9776 23:51:33.703478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9777 23:51:33.706894 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9778 23:51:33.713525 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9779 23:51:33.716435 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9780 23:51:33.720482 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9781 23:51:33.723545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9782 23:51:33.729868 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9783 23:51:33.733213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9784 23:51:33.736536 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9785 23:51:33.743391 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9786 23:51:33.747062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9787 23:51:33.753295 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9788 23:51:33.757276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9789 23:51:33.760431 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9790 23:51:33.767081 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9791 23:51:33.769676 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9792 23:51:33.776487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9793 23:51:33.780354 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9794 23:51:33.783585 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9795 23:51:33.790521 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9796 23:51:33.793080 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9797 23:51:33.799864 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9798 23:51:33.803339 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9799 23:51:33.806835 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9800 23:51:33.814020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9801 23:51:33.817179 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9802 23:51:33.824310 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9803 23:51:33.826543 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9804 23:51:33.829945 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9805 23:51:33.836394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9806 23:51:33.840328 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9807 23:51:33.846697 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9808 23:51:33.850129 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9809 23:51:33.853189 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9810 23:51:33.859967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9811 23:51:33.864118 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9812 23:51:33.869713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9813 23:51:33.873601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9814 23:51:33.879973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9815 23:51:33.883478 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9816 23:51:33.887183 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9817 23:51:33.893219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9818 23:51:33.896945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9819 23:51:33.900217 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9820 23:51:33.906581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9821 23:51:33.910110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9822 23:51:33.916711 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9823 23:51:33.920257 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9824 23:51:33.923554 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9825 23:51:33.931146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9826 23:51:33.933292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9827 23:51:33.939927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9828 23:51:33.943441 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9829 23:51:33.946838 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9830 23:51:33.953605 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9831 23:51:33.956405 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9832 23:51:33.964048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9833 23:51:33.968071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9834 23:51:33.970528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9835 23:51:33.976991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9836 23:51:33.980204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9837 23:51:33.987597 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9838 23:51:33.989981 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9839 23:51:33.993434 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9840 23:51:34.000007 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9841 23:51:34.003957 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9842 23:51:34.010115 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9843 23:51:34.013491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9844 23:51:34.020520 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9845 23:51:34.023381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9846 23:51:34.026513 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9847 23:51:34.033334 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9848 23:51:34.036556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9849 23:51:34.040041 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9850 23:51:34.046428 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9851 23:51:34.050149 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9852 23:51:34.056402 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9853 23:51:34.060172 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9854 23:51:34.066580 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9855 23:51:34.070634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9856 23:51:34.074347 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9857 23:51:34.080123 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9858 23:51:34.083120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9859 23:51:34.089388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9860 23:51:34.092881 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9861 23:51:34.100497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9862 23:51:34.102950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9863 23:51:34.106189 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9864 23:51:34.113436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9865 23:51:34.117117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9866 23:51:34.122756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9867 23:51:34.126550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9868 23:51:34.133764 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9869 23:51:34.136194 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9870 23:51:34.139850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9871 23:51:34.146348 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9872 23:51:34.149956 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9873 23:51:34.156286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9874 23:51:34.159588 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9875 23:51:34.166343 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9876 23:51:34.170007 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9877 23:51:34.173250 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9878 23:51:34.179765 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9879 23:51:34.182960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9880 23:51:34.189800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9881 23:51:34.193051 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9882 23:51:34.200144 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9883 23:51:34.203149 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9884 23:51:34.206272 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9885 23:51:34.213826 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9886 23:51:34.216906 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9887 23:51:34.222904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9888 23:51:34.227683 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9889 23:51:34.232824 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9890 23:51:34.236783 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9891 23:51:34.239973 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9892 23:51:34.246391 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9893 23:51:34.249472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9894 23:51:34.256727 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9895 23:51:34.259502 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9896 23:51:34.267104 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9897 23:51:34.270190 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9898 23:51:34.273008 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9899 23:51:34.280272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9900 23:51:34.283079 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9901 23:51:34.290111 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9902 23:51:34.292965 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9903 23:51:34.296213 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9904 23:51:34.303024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9905 23:51:34.306746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9906 23:51:34.313968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9907 23:51:34.316362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9908 23:51:34.323069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9909 23:51:34.326746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9910 23:51:34.332846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9911 23:51:34.336257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9912 23:51:34.343145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9913 23:51:34.346168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9914 23:51:34.353636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9915 23:51:34.356341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9916 23:51:34.359676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9917 23:51:34.366468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9918 23:51:34.369894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9919 23:51:34.376368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9920 23:51:34.379893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9921 23:51:34.386390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9922 23:51:34.389765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9923 23:51:34.396926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9924 23:51:34.400275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9925 23:51:34.406363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9926 23:51:34.409461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9927 23:51:34.416526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9928 23:51:34.419497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9929 23:51:34.426578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9930 23:51:34.429559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9931 23:51:34.437148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9932 23:51:34.439786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9933 23:51:34.446801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9934 23:51:34.449383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9935 23:51:34.456969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9936 23:51:34.459941 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9937 23:51:34.463317 INFO: [APUAPC] vio 0
9938 23:51:34.466409 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9939 23:51:34.469649 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9940 23:51:34.473012 INFO: [APUAPC] D0_APC_0: 0x400510
9941 23:51:34.476838 INFO: [APUAPC] D0_APC_1: 0x0
9942 23:51:34.479929 INFO: [APUAPC] D0_APC_2: 0x1540
9943 23:51:34.483873 INFO: [APUAPC] D0_APC_3: 0x0
9944 23:51:34.486447 INFO: [APUAPC] D1_APC_0: 0xffffffff
9945 23:51:34.489880 INFO: [APUAPC] D1_APC_1: 0xffffffff
9946 23:51:34.493291 INFO: [APUAPC] D1_APC_2: 0x3fffff
9947 23:51:34.496314 INFO: [APUAPC] D1_APC_3: 0x0
9948 23:51:34.500195 INFO: [APUAPC] D2_APC_0: 0xffffffff
9949 23:51:34.503357 INFO: [APUAPC] D2_APC_1: 0xffffffff
9950 23:51:34.506610 INFO: [APUAPC] D2_APC_2: 0x3fffff
9951 23:51:34.509742 INFO: [APUAPC] D2_APC_3: 0x0
9952 23:51:34.513104 INFO: [APUAPC] D3_APC_0: 0xffffffff
9953 23:51:34.516204 INFO: [APUAPC] D3_APC_1: 0xffffffff
9954 23:51:34.520481 INFO: [APUAPC] D3_APC_2: 0x3fffff
9955 23:51:34.524405 INFO: [APUAPC] D3_APC_3: 0x0
9956 23:51:34.526775 INFO: [APUAPC] D4_APC_0: 0xffffffff
9957 23:51:34.529682 INFO: [APUAPC] D4_APC_1: 0xffffffff
9958 23:51:34.533394 INFO: [APUAPC] D4_APC_2: 0x3fffff
9959 23:51:34.536528 INFO: [APUAPC] D4_APC_3: 0x0
9960 23:51:34.539800 INFO: [APUAPC] D5_APC_0: 0xffffffff
9961 23:51:34.543099 INFO: [APUAPC] D5_APC_1: 0xffffffff
9962 23:51:34.546332 INFO: [APUAPC] D5_APC_2: 0x3fffff
9963 23:51:34.549566 INFO: [APUAPC] D5_APC_3: 0x0
9964 23:51:34.553202 INFO: [APUAPC] D6_APC_0: 0xffffffff
9965 23:51:34.556239 INFO: [APUAPC] D6_APC_1: 0xffffffff
9966 23:51:34.559467 INFO: [APUAPC] D6_APC_2: 0x3fffff
9967 23:51:34.562779 INFO: [APUAPC] D6_APC_3: 0x0
9968 23:51:34.566272 INFO: [APUAPC] D7_APC_0: 0xffffffff
9969 23:51:34.569577 INFO: [APUAPC] D7_APC_1: 0xffffffff
9970 23:51:34.572829 INFO: [APUAPC] D7_APC_2: 0x3fffff
9971 23:51:34.572912 INFO: [APUAPC] D7_APC_3: 0x0
9972 23:51:34.576745 INFO: [APUAPC] D8_APC_0: 0xffffffff
9973 23:51:34.582858 INFO: [APUAPC] D8_APC_1: 0xffffffff
9974 23:51:34.586941 INFO: [APUAPC] D8_APC_2: 0x3fffff
9975 23:51:34.587032 INFO: [APUAPC] D8_APC_3: 0x0
9976 23:51:34.590152 INFO: [APUAPC] D9_APC_0: 0xffffffff
9977 23:51:34.592944 INFO: [APUAPC] D9_APC_1: 0xffffffff
9978 23:51:34.596702 INFO: [APUAPC] D9_APC_2: 0x3fffff
9979 23:51:34.599802 INFO: [APUAPC] D9_APC_3: 0x0
9980 23:51:34.603225 INFO: [APUAPC] D10_APC_0: 0xffffffff
9981 23:51:34.606041 INFO: [APUAPC] D10_APC_1: 0xffffffff
9982 23:51:34.610097 INFO: [APUAPC] D10_APC_2: 0x3fffff
9983 23:51:34.612799 INFO: [APUAPC] D10_APC_3: 0x0
9984 23:51:34.616171 INFO: [APUAPC] D11_APC_0: 0xffffffff
9985 23:51:34.619852 INFO: [APUAPC] D11_APC_1: 0xffffffff
9986 23:51:34.623019 INFO: [APUAPC] D11_APC_2: 0x3fffff
9987 23:51:34.625875 INFO: [APUAPC] D11_APC_3: 0x0
9988 23:51:34.629352 INFO: [APUAPC] D12_APC_0: 0xffffffff
9989 23:51:34.633651 INFO: [APUAPC] D12_APC_1: 0xffffffff
9990 23:51:34.636214 INFO: [APUAPC] D12_APC_2: 0x3fffff
9991 23:51:34.639521 INFO: [APUAPC] D12_APC_3: 0x0
9992 23:51:34.642985 INFO: [APUAPC] D13_APC_0: 0xffffffff
9993 23:51:34.645996 INFO: [APUAPC] D13_APC_1: 0xffffffff
9994 23:51:34.649721 INFO: [APUAPC] D13_APC_2: 0x3fffff
9995 23:51:34.652682 INFO: [APUAPC] D13_APC_3: 0x0
9996 23:51:34.656228 INFO: [APUAPC] D14_APC_0: 0xffffffff
9997 23:51:34.660535 INFO: [APUAPC] D14_APC_1: 0xffffffff
9998 23:51:34.662868 INFO: [APUAPC] D14_APC_2: 0x3fffff
9999 23:51:34.666213 INFO: [APUAPC] D14_APC_3: 0x0
10000 23:51:34.669655 INFO: [APUAPC] D15_APC_0: 0xffffffff
10001 23:51:34.672848 INFO: [APUAPC] D15_APC_1: 0xffffffff
10002 23:51:34.676149 INFO: [APUAPC] D15_APC_2: 0x3fffff
10003 23:51:34.680791 INFO: [APUAPC] D15_APC_3: 0x0
10004 23:51:34.683338 INFO: [APUAPC] APC_CON: 0x4
10005 23:51:34.686677 INFO: [NOCDAPC] D0_APC_0: 0x0
10006 23:51:34.689516 INFO: [NOCDAPC] D0_APC_1: 0x0
10007 23:51:34.693329 INFO: [NOCDAPC] D1_APC_0: 0x0
10008 23:51:34.696097 INFO: [NOCDAPC] D1_APC_1: 0xfff
10009 23:51:34.700285 INFO: [NOCDAPC] D2_APC_0: 0x0
10010 23:51:34.703293 INFO: [NOCDAPC] D2_APC_1: 0xfff
10011 23:51:34.703379 INFO: [NOCDAPC] D3_APC_0: 0x0
10012 23:51:34.706834 INFO: [NOCDAPC] D3_APC_1: 0xfff
10013 23:51:34.709422 INFO: [NOCDAPC] D4_APC_0: 0x0
10014 23:51:34.713989 INFO: [NOCDAPC] D4_APC_1: 0xfff
10015 23:51:34.717551 INFO: [NOCDAPC] D5_APC_0: 0x0
10016 23:51:34.719831 INFO: [NOCDAPC] D5_APC_1: 0xfff
10017 23:51:34.723191 INFO: [NOCDAPC] D6_APC_0: 0x0
10018 23:51:34.727027 INFO: [NOCDAPC] D6_APC_1: 0xfff
10019 23:51:34.729929 INFO: [NOCDAPC] D7_APC_0: 0x0
10020 23:51:34.734380 INFO: [NOCDAPC] D7_APC_1: 0xfff
10021 23:51:34.734472 INFO: [NOCDAPC] D8_APC_0: 0x0
10022 23:51:34.736751 INFO: [NOCDAPC] D8_APC_1: 0xfff
10023 23:51:34.740033 INFO: [NOCDAPC] D9_APC_0: 0x0
10024 23:51:34.742995 INFO: [NOCDAPC] D9_APC_1: 0xfff
10025 23:51:34.746977 INFO: [NOCDAPC] D10_APC_0: 0x0
10026 23:51:34.749643 INFO: [NOCDAPC] D10_APC_1: 0xfff
10027 23:51:34.754483 INFO: [NOCDAPC] D11_APC_0: 0x0
10028 23:51:34.756609 INFO: [NOCDAPC] D11_APC_1: 0xfff
10029 23:51:34.760252 INFO: [NOCDAPC] D12_APC_0: 0x0
10030 23:51:34.763048 INFO: [NOCDAPC] D12_APC_1: 0xfff
10031 23:51:34.766214 INFO: [NOCDAPC] D13_APC_0: 0x0
10032 23:51:34.769583 INFO: [NOCDAPC] D13_APC_1: 0xfff
10033 23:51:34.773486 INFO: [NOCDAPC] D14_APC_0: 0x0
10034 23:51:34.773578 INFO: [NOCDAPC] D14_APC_1: 0xfff
10035 23:51:34.776561 INFO: [NOCDAPC] D15_APC_0: 0x0
10036 23:51:34.779699 INFO: [NOCDAPC] D15_APC_1: 0xfff
10037 23:51:34.783182 INFO: [NOCDAPC] APC_CON: 0x4
10038 23:51:34.786982 INFO: [APUAPC] set_apusys_apc done
10039 23:51:34.789690 INFO: [DEVAPC] devapc_init done
10040 23:51:34.792651 INFO: GICv3 without legacy support detected.
10041 23:51:34.799755 INFO: ARM GICv3 driver initialized in EL3
10042 23:51:34.803062 INFO: Maximum SPI INTID supported: 639
10043 23:51:34.806124 INFO: BL31: Initializing runtime services
10044 23:51:34.812895 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10045 23:51:34.813033 INFO: SPM: enable CPC mode
10046 23:51:34.819764 INFO: mcdi ready for mcusys-off-idle and system suspend
10047 23:51:34.824288 INFO: BL31: Preparing for EL3 exit to normal world
10048 23:51:34.829447 INFO: Entry point address = 0x80000000
10049 23:51:34.829551 INFO: SPSR = 0x8
10050 23:51:34.835738
10051 23:51:34.835830
10052 23:51:34.835895
10053 23:51:34.838962 Starting depthcharge on Spherion...
10054 23:51:34.839046
10055 23:51:34.839111 Wipe memory regions:
10056 23:51:34.839171
10057 23:51:34.839843 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10058 23:51:34.839948 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10059 23:51:34.840030 Setting prompt string to ['asurada:']
10060 23:51:34.840104 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10061 23:51:34.842899 [0x00000040000000, 0x00000054600000)
10062 23:51:34.965214
10063 23:51:34.965370 [0x00000054660000, 0x00000080000000)
10064 23:51:35.224295
10065 23:51:35.224453 [0x000000821a7280, 0x000000ffe64000)
10066 23:51:35.969280
10067 23:51:35.969647 [0x00000100000000, 0x00000240000000)
10068 23:51:37.858324
10069 23:51:37.861179 Initializing XHCI USB controller at 0x11200000.
10070 23:51:38.900085
10071 23:51:38.903223 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10072 23:51:38.903791
10073 23:51:38.904150
10074 23:51:38.904943 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 23:51:39.006429 asurada: tftpboot 192.168.201.1 14084325/tftp-deploy-7j3mdvgy/kernel/image.itb 14084325/tftp-deploy-7j3mdvgy/kernel/cmdline
10077 23:51:39.007079 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 23:51:39.007546 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10079 23:51:39.012170 tftpboot 192.168.201.1 14084325/tftp-deploy-7j3mdvgy/kernel/image.ittp-deploy-7j3mdvgy/kernel/cmdline
10080 23:51:39.012737
10081 23:51:39.013139 Waiting for link
10082 23:51:39.170566
10083 23:51:39.171132 R8152: Initializing
10084 23:51:39.171498
10085 23:51:39.173839 Version 6 (ocp_data = 5c30)
10086 23:51:39.174390
10087 23:51:39.177262 R8152: Done initializing
10088 23:51:39.177814
10089 23:51:39.178169 Adding net device
10090 23:51:41.047161
10091 23:51:41.047704 done.
10092 23:51:41.048067
10093 23:51:41.048397 MAC: 00:24:32:30:78:52
10094 23:51:41.048718
10095 23:51:41.049892 Sending DHCP discover... done.
10096 23:51:41.050343
10097 23:51:45.921921 Waiting for reply... done.
10098 23:51:45.922066
10099 23:51:45.922166 Sending DHCP request... done.
10100 23:51:45.924941
10101 23:51:45.925050 Waiting for reply... done.
10102 23:51:45.925119
10103 23:51:45.928170 My ip is 192.168.201.14
10104 23:51:45.928277
10105 23:51:45.931336 The DHCP server ip is 192.168.201.1
10106 23:51:45.931453
10107 23:51:45.934882 TFTP server IP predefined by user: 192.168.201.1
10108 23:51:45.934983
10109 23:51:45.941374 Bootfile predefined by user: 14084325/tftp-deploy-7j3mdvgy/kernel/image.itb
10110 23:51:45.941499
10111 23:51:45.945129 Sending tftp read request... done.
10112 23:51:45.945209
10113 23:51:45.948154 Waiting for the transfer...
10114 23:51:45.948271
10115 23:51:46.478069 00000000 ################################################################
10116 23:51:46.478222
10117 23:51:46.997290 00080000 ################################################################
10118 23:51:46.997456
10119 23:51:47.523405 00100000 ################################################################
10120 23:51:47.523550
10121 23:51:48.043257 00180000 ################################################################
10122 23:51:48.043401
10123 23:51:48.565198 00200000 ################################################################
10124 23:51:48.565347
10125 23:51:49.090421 00280000 ################################################################
10126 23:51:49.090564
10127 23:51:49.617500 00300000 ################################################################
10128 23:51:49.617649
10129 23:51:50.145225 00380000 ################################################################
10130 23:51:50.145362
10131 23:51:50.671542 00400000 ################################################################
10132 23:51:50.671676
10133 23:51:51.195575 00480000 ################################################################
10134 23:51:51.195713
10135 23:51:51.715746 00500000 ################################################################
10136 23:51:51.715927
10137 23:51:52.242238 00580000 ################################################################
10138 23:51:52.242378
10139 23:51:52.776032 00600000 ################################################################
10140 23:51:52.776197
10141 23:51:53.310387 00680000 ################################################################
10142 23:51:53.310563
10143 23:51:53.837375 00700000 ################################################################
10144 23:51:53.837510
10145 23:51:54.364620 00780000 ################################################################
10146 23:51:54.364785
10147 23:51:54.895537 00800000 ################################################################
10148 23:51:54.895680
10149 23:51:55.425500 00880000 ################################################################
10150 23:51:55.425637
10151 23:51:55.946528 00900000 ################################################################
10152 23:51:55.946665
10153 23:51:56.476662 00980000 ################################################################
10154 23:51:56.476830
10155 23:51:57.008192 00a00000 ################################################################
10156 23:51:57.008330
10157 23:51:57.532738 00a80000 ################################################################
10158 23:51:57.532876
10159 23:51:58.061439 00b00000 ################################################################
10160 23:51:58.061604
10161 23:51:58.580611 00b80000 ################################################################
10162 23:51:58.580758
10163 23:51:59.109698 00c00000 ################################################################
10164 23:51:59.109837
10165 23:51:59.639116 00c80000 ################################################################
10166 23:51:59.639250
10167 23:52:00.160812 00d00000 ################################################################
10168 23:52:00.160968
10169 23:52:00.686003 00d80000 ################################################################
10170 23:52:00.686140
10171 23:52:01.204784 00e00000 ################################################################
10172 23:52:01.204947
10173 23:52:01.737664 00e80000 ################################################################
10174 23:52:01.737803
10175 23:52:02.263632 00f00000 ################################################################
10176 23:52:02.263779
10177 23:52:02.800308 00f80000 ################################################################
10178 23:52:02.800451
10179 23:52:03.325660 01000000 ################################################################
10180 23:52:03.325799
10181 23:52:03.842207 01080000 ################################################################
10182 23:52:03.842392
10183 23:52:04.363286 01100000 ################################################################
10184 23:52:04.363423
10185 23:52:04.888936 01180000 ################################################################
10186 23:52:04.889104
10187 23:52:05.409145 01200000 ################################################################
10188 23:52:05.409281
10189 23:52:05.931460 01280000 ################################################################
10190 23:52:05.931623
10191 23:52:06.465755 01300000 ################################################################
10192 23:52:06.465886
10193 23:52:06.989581 01380000 ################################################################
10194 23:52:06.989742
10195 23:52:07.514445 01400000 ################################################################
10196 23:52:07.514600
10197 23:52:08.056587 01480000 ################################################################
10198 23:52:08.056730
10199 23:52:08.596714 01500000 ################################################################
10200 23:52:08.596848
10201 23:52:09.123214 01580000 ################################################################
10202 23:52:09.123348
10203 23:52:09.669912 01600000 ################################################################
10204 23:52:09.670044
10205 23:52:10.214601 01680000 ################################################################
10206 23:52:10.214742
10207 23:52:10.735379 01700000 ################################################################
10208 23:52:10.735515
10209 23:52:11.282459 01780000 ################################################################
10210 23:52:11.282590
10211 23:52:11.810076 01800000 ################################################################
10212 23:52:11.810211
10213 23:52:12.352852 01880000 ################################################################
10214 23:52:12.352996
10215 23:52:12.882361 01900000 ################################################################
10216 23:52:12.882493
10217 23:52:13.408645 01980000 ################################################################
10218 23:52:13.408784
10219 23:52:13.975232 01a00000 ################################################################
10220 23:52:13.975367
10221 23:52:14.617878 01a80000 ################################################################
10222 23:52:14.618457
10223 23:52:15.344927 01b00000 ################################################################
10224 23:52:15.345472
10225 23:52:16.056716 01b80000 ################################################################
10226 23:52:16.057267
10227 23:52:16.685934 01c00000 ################################################################
10228 23:52:16.686417
10229 23:52:17.379803 01c80000 ################################################################
10230 23:52:17.380373
10231 23:52:18.036607 01d00000 ################################################################
10232 23:52:18.037112
10233 23:52:18.734525 01d80000 ################################################################
10234 23:52:18.735005
10235 23:52:19.421252 01e00000 ################################################################
10236 23:52:19.421737
10237 23:52:20.073666 01e80000 ################################################################
10238 23:52:20.073800
10239 23:52:20.699934 01f00000 ################################################################
10240 23:52:20.700090
10241 23:52:21.343545 01f80000 ################################################################
10242 23:52:21.344035
10243 23:52:21.963952 02000000 ################################################################
10244 23:52:21.964100
10245 23:52:22.524864 02080000 ################################################################
10246 23:52:22.525039
10247 23:52:23.166068 02100000 ################################################################
10248 23:52:23.166633
10249 23:52:23.814755 02180000 ################################################################
10250 23:52:23.815407
10251 23:52:24.485087 02200000 ################################################################
10252 23:52:24.485218
10253 23:52:25.119450 02280000 ################################################################
10254 23:52:25.119942
10255 23:52:25.758691 02300000 ################################################################
10256 23:52:25.758827
10257 23:52:26.355450 02380000 ################################################################
10258 23:52:26.355656
10259 23:52:27.062129 02400000 ################################################################
10260 23:52:27.062774
10261 23:52:27.760285 02480000 ################################################################
10262 23:52:27.760861
10263 23:52:28.429278 02500000 ################################################################
10264 23:52:28.429741
10265 23:52:29.075906 02580000 ################################################################
10266 23:52:29.076398
10267 23:52:29.779831 02600000 ################################################################
10268 23:52:29.780408
10269 23:52:30.431381 02680000 ################################################################
10270 23:52:30.431522
10271 23:52:31.090525 02700000 ################################################################
10272 23:52:31.091088
10273 23:52:31.731487 02780000 ################################################################
10274 23:52:31.731668
10275 23:52:32.373413 02800000 ################################################################
10276 23:52:32.373919
10277 23:52:33.011392 02880000 ################################################################
10278 23:52:33.011926
10279 23:52:33.701234 02900000 ################################################################
10280 23:52:33.701748
10281 23:52:34.331582 02980000 ################################################################
10282 23:52:34.331726
10283 23:52:34.960693 02a00000 ################################################################
10284 23:52:34.960841
10285 23:52:35.580402 02a80000 ################################################################
10286 23:52:35.580541
10287 23:52:36.248940 02b00000 ################################################################
10288 23:52:36.249494
10289 23:52:36.939926 02b80000 ################################################################
10290 23:52:36.940432
10291 23:52:37.637598 02c00000 ################################################################
10292 23:52:37.638109
10293 23:52:38.308272 02c80000 ################################################################
10294 23:52:38.308797
10295 23:52:38.974481 02d00000 ################################################################
10296 23:52:38.974999
10297 23:52:39.690035 02d80000 ################################################################
10298 23:52:39.690545
10299 23:52:40.298390 02e00000 ################################################################
10300 23:52:40.298544
10301 23:52:40.949890 02e80000 ################################################################
10302 23:52:40.950382
10303 23:52:41.653755 02f00000 ################################################################
10304 23:52:41.654255
10305 23:52:42.323126 02f80000 ################################################################
10306 23:52:42.323289
10307 23:52:42.995987 03000000 ################################################################
10308 23:52:42.996501
10309 23:52:43.718103 03080000 ################################################################
10310 23:52:43.718637
10311 23:52:44.441667 03100000 ################################################################
10312 23:52:44.442236
10313 23:52:45.139740 03180000 ################################################################
10314 23:52:45.140248
10315 23:52:45.847069 03200000 ################################################################
10316 23:52:45.847580
10317 23:52:46.567909 03280000 ################################################################
10318 23:52:46.568427
10319 23:52:47.271854 03300000 ################################################################
10320 23:52:47.272362
10321 23:52:47.975915 03380000 ################################################################
10322 23:52:47.976429
10323 23:52:48.679187 03400000 ################################################################
10324 23:52:48.679710
10325 23:52:49.383788 03480000 ################################################################
10326 23:52:49.384328
10327 23:52:50.080569 03500000 ################################################################
10328 23:52:50.081100
10329 23:52:50.783773 03580000 ################################################################
10330 23:52:50.784293
10331 23:52:51.489189 03600000 ################################################################
10332 23:52:51.489869
10333 23:52:52.220713 03680000 ################################################################
10334 23:52:52.221358
10335 23:52:52.934853 03700000 ################################################################
10336 23:52:52.935484
10337 23:52:53.624000 03780000 ################################################################
10338 23:52:53.624523
10339 23:52:54.288401 03800000 ################################################################
10340 23:52:54.288907
10341 23:52:55.002772 03880000 ################################################################
10342 23:52:55.003273
10343 23:52:55.707966 03900000 ################################################################
10344 23:52:55.708541
10345 23:52:56.391039 03980000 ################################################################
10346 23:52:56.391554
10347 23:52:57.024436 03a00000 ################################################################
10348 23:52:57.024584
10349 23:52:57.706698 03a80000 ################################################################
10350 23:52:57.707235
10351 23:52:58.397956 03b00000 ################################################################
10352 23:52:58.398462
10353 23:52:59.071384 03b80000 ################################################################
10354 23:52:59.072075
10355 23:52:59.767232 03c00000 ################################################################
10356 23:52:59.767740
10357 23:53:00.471020 03c80000 ################################################################
10358 23:53:00.471544
10359 23:53:01.123289 03d00000 ################################################################
10360 23:53:01.123438
10361 23:53:01.721765 03d80000 ################################################################
10362 23:53:01.721914
10363 23:53:02.313423 03e00000 ################################################################
10364 23:53:02.313573
10365 23:53:02.889926 03e80000 ################################################################
10366 23:53:02.890084
10367 23:53:03.468419 03f00000 ################################################################
10368 23:53:03.468570
10369 23:53:04.041371 03f80000 ################################################################
10370 23:53:04.041507
10371 23:53:04.608145 04000000 ################################################################
10372 23:53:04.608294
10373 23:53:05.188461 04080000 ################################################################
10374 23:53:05.188607
10375 23:53:05.766294 04100000 ################################################################
10376 23:53:05.766440
10377 23:53:06.354125 04180000 ################################################################
10378 23:53:06.354270
10379 23:53:06.930671 04200000 ################################################################
10380 23:53:06.930810
10381 23:53:07.496812 04280000 ################################################################
10382 23:53:07.496966
10383 23:53:08.053610 04300000 ################################################################
10384 23:53:08.053752
10385 23:53:08.618780 04380000 ################################################################
10386 23:53:08.618962
10387 23:53:09.177998 04400000 ################################################################
10388 23:53:09.178143
10389 23:53:09.734663 04480000 ################################################################
10390 23:53:09.734821
10391 23:53:10.397343 04500000 ################################################################
10392 23:53:10.397486
10393 23:53:11.006892 04580000 ################################################################
10394 23:53:11.007053
10395 23:53:11.611517 04600000 ################################################################
10396 23:53:11.611692
10397 23:53:11.827561 04680000 ######################## done.
10398 23:53:11.827741
10399 23:53:11.830924 The bootfile was 74113886 bytes long.
10400 23:53:11.831002
10401 23:53:11.833924 Sending tftp read request... done.
10402 23:53:11.834036
10403 23:53:11.837513 Waiting for the transfer...
10404 23:53:11.837595
10405 23:53:11.837660 00000000 # done.
10406 23:53:11.837722
10407 23:53:11.843646 Command line loaded dynamically from TFTP file: 14084325/tftp-deploy-7j3mdvgy/kernel/cmdline
10408 23:53:11.847062
10409 23:53:11.857049 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10410 23:53:11.860666
10411 23:53:11.860746 Loading FIT.
10412 23:53:11.860810
10413 23:53:11.865920 Image ramdisk-1 has 61001105 bytes.
10414 23:53:11.866000
10415 23:53:11.867355 Image fdt-1 has 47258 bytes.
10416 23:53:11.867436
10417 23:53:11.867499 Image kernel-1 has 13063488 bytes.
10418 23:53:11.870503
10419 23:53:11.877387 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10420 23:53:11.877468
10421 23:53:11.894101 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10422 23:53:11.894189
10423 23:53:11.900551 Choosing best match conf-1 for compat google,spherion-rev2.
10424 23:53:11.905168
10425 23:53:11.909658 Connected to device vid:did:rid of 1ae0:0028:00
10426 23:53:11.917713
10427 23:53:11.921547 tpm_get_response: command 0x17b, return code 0x0
10428 23:53:11.921628
10429 23:53:11.924349 ec_init: CrosEC protocol v3 supported (256, 248)
10430 23:53:11.930653
10431 23:53:11.933150 tpm_cleanup: add release locality here.
10432 23:53:11.933231
10433 23:53:11.933293 Shutting down all USB controllers.
10434 23:53:11.936608
10435 23:53:11.936687 Removing current net device
10436 23:53:11.936751
10437 23:53:11.944463 Exiting depthcharge with code 4 at timestamp: 126644278
10438 23:53:11.944545
10439 23:53:11.946505 LZMA decompressing kernel-1 to 0x821a6718
10440 23:53:11.946586
10441 23:53:11.949742 LZMA decompressing kernel-1 to 0x40000000
10442 23:53:13.561316
10443 23:53:13.561464 jumping to kernel
10444 23:53:13.562004 end: 2.2.4 bootloader-commands (duration 00:01:39) [common]
10445 23:53:13.562144 start: 2.2.5 auto-login-action (timeout 00:02:46) [common]
10446 23:53:13.562217 Setting prompt string to ['Linux version [0-9]']
10447 23:53:13.562283 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10448 23:53:13.562348 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10449 23:53:13.642999
10450 23:53:13.646511 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10451 23:53:13.650259 start: 2.2.5.1 login-action (timeout 00:02:46) [common]
10452 23:53:13.650369 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10453 23:53:13.650440 Setting prompt string to []
10454 23:53:13.650515 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10455 23:53:13.650587 Using line separator: #'\n'#
10456 23:53:13.650645 No login prompt set.
10457 23:53:13.650703 Parsing kernel messages
10458 23:53:13.650757 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10459 23:53:13.650853 [login-action] Waiting for messages, (timeout 00:02:46)
10460 23:53:13.650916 Waiting using forced prompt support (timeout 00:01:23)
10461 23:53:13.670133 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10462 23:53:13.673676 [ 0.000000] random: crng init done
10463 23:53:13.679511 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10464 23:53:13.684809 [ 0.000000] efi: UEFI not found.
10465 23:53:13.689987 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10466 23:53:13.696818 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10467 23:53:13.705987 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10468 23:53:13.716309 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10469 23:53:13.722570 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10470 23:53:13.729187 [ 0.000000] printk: bootconsole [mtk8250] enabled
10471 23:53:13.735945 [ 0.000000] NUMA: No NUMA configuration found
10472 23:53:13.742811 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10473 23:53:13.746580 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10474 23:53:13.749465 [ 0.000000] Zone ranges:
10475 23:53:13.756121 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10476 23:53:13.759406 [ 0.000000] DMA32 empty
10477 23:53:13.766068 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10478 23:53:13.769081 [ 0.000000] Movable zone start for each node
10479 23:53:13.772260 [ 0.000000] Early memory node ranges
10480 23:53:13.779012 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10481 23:53:13.786034 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10482 23:53:13.792845 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10483 23:53:13.795665 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10484 23:53:13.802282 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10485 23:53:13.809148 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10486 23:53:13.867598 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10487 23:53:13.874842 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10488 23:53:13.881188 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10489 23:53:13.885063 [ 0.000000] psci: probing for conduit method from DT.
10490 23:53:13.891357 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10491 23:53:13.894571 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10492 23:53:13.901512 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10493 23:53:13.904324 [ 0.000000] psci: SMC Calling Convention v1.2
10494 23:53:13.911196 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10495 23:53:13.914403 [ 0.000000] Detected VIPT I-cache on CPU0
10496 23:53:13.921415 [ 0.000000] CPU features: detected: GIC system register CPU interface
10497 23:53:13.927992 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10498 23:53:13.934404 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10499 23:53:13.941358 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10500 23:53:13.947993 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10501 23:53:13.954337 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10502 23:53:13.961586 [ 0.000000] alternatives: applying boot alternatives
10503 23:53:13.964382 [ 0.000000] Fallback order for Node 0: 0
10504 23:53:13.970954 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10505 23:53:13.974233 [ 0.000000] Policy zone: Normal
10506 23:53:13.991376 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10507 23:53:14.000845 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10508 23:53:14.010945 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10509 23:53:14.020960 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10510 23:53:14.027362 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10511 23:53:14.030730 <6>[ 0.000000] software IO TLB: area num 8.
10512 23:53:14.087824 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10513 23:53:14.236839 <6>[ 0.000000] Memory: 7904620K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448148K reserved, 32768K cma-reserved)
10514 23:53:14.243824 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10515 23:53:14.250461 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10516 23:53:14.253563 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10517 23:53:14.260214 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10518 23:53:14.267061 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10519 23:53:14.269996 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10520 23:53:14.279787 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10521 23:53:14.286953 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10522 23:53:14.289720 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10523 23:53:14.297685 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10524 23:53:14.300638 <6>[ 0.000000] GICv3: 608 SPIs implemented
10525 23:53:14.308104 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10526 23:53:14.312011 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10527 23:53:14.314179 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10528 23:53:14.324331 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10529 23:53:14.333954 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10530 23:53:14.347098 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10531 23:53:14.354300 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10532 23:53:14.363496 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10533 23:53:14.376288 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10534 23:53:14.383756 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10535 23:53:14.389757 <6>[ 0.009177] Console: colour dummy device 80x25
10536 23:53:14.400286 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10537 23:53:14.404228 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10538 23:53:14.410838 <6>[ 0.029219] LSM: Security Framework initializing
10539 23:53:14.416892 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10540 23:53:14.426658 <6>[ 0.041969] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10541 23:53:14.432899 <6>[ 0.051398] cblist_init_generic: Setting adjustable number of callback queues.
10542 23:53:14.439489 <6>[ 0.058843] cblist_init_generic: Setting shift to 3 and lim to 1.
10543 23:53:14.449587 <6>[ 0.065222] cblist_init_generic: Setting adjustable number of callback queues.
10544 23:53:14.453493 <6>[ 0.072694] cblist_init_generic: Setting shift to 3 and lim to 1.
10545 23:53:14.459810 <6>[ 0.079095] rcu: Hierarchical SRCU implementation.
10546 23:53:14.466187 <6>[ 0.084111] rcu: Max phase no-delay instances is 1000.
10547 23:53:14.472806 <6>[ 0.091168] EFI services will not be available.
10548 23:53:14.476420 <6>[ 0.096126] smp: Bringing up secondary CPUs ...
10549 23:53:14.484916 <6>[ 0.101174] Detected VIPT I-cache on CPU1
10550 23:53:14.490923 <6>[ 0.101246] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10551 23:53:14.497325 <6>[ 0.101277] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10552 23:53:14.500529 <6>[ 0.101619] Detected VIPT I-cache on CPU2
10553 23:53:14.508130 <6>[ 0.101672] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10554 23:53:14.517774 <6>[ 0.101690] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10555 23:53:14.520517 <6>[ 0.101950] Detected VIPT I-cache on CPU3
10556 23:53:14.527158 <6>[ 0.102000] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10557 23:53:14.533928 <6>[ 0.102014] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10558 23:53:14.536848 <6>[ 0.102318] CPU features: detected: Spectre-v4
10559 23:53:14.543634 <6>[ 0.102325] CPU features: detected: Spectre-BHB
10560 23:53:14.547907 <6>[ 0.102329] Detected PIPT I-cache on CPU4
10561 23:53:14.553982 <6>[ 0.102387] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10562 23:53:14.560670 <6>[ 0.102404] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10563 23:53:14.566911 <6>[ 0.102693] Detected PIPT I-cache on CPU5
10564 23:53:14.573744 <6>[ 0.102754] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10565 23:53:14.580535 <6>[ 0.102770] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10566 23:53:14.583780 <6>[ 0.103048] Detected PIPT I-cache on CPU6
10567 23:53:14.590482 <6>[ 0.103114] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10568 23:53:14.597111 <6>[ 0.103130] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10569 23:53:14.603865 <6>[ 0.103426] Detected PIPT I-cache on CPU7
10570 23:53:14.610301 <6>[ 0.103490] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10571 23:53:14.617523 <6>[ 0.103507] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10572 23:53:14.620132 <6>[ 0.103554] smp: Brought up 1 node, 8 CPUs
10573 23:53:14.627279 <6>[ 0.245020] SMP: Total of 8 processors activated.
10574 23:53:14.630246 <6>[ 0.249941] CPU features: detected: 32-bit EL0 Support
10575 23:53:14.640175 <6>[ 0.255305] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10576 23:53:14.647479 <6>[ 0.264160] CPU features: detected: Common not Private translations
10577 23:53:14.650247 <6>[ 0.270635] CPU features: detected: CRC32 instructions
10578 23:53:14.656903 <6>[ 0.275987] CPU features: detected: RCpc load-acquire (LDAPR)
10579 23:53:14.663512 <6>[ 0.281947] CPU features: detected: LSE atomic instructions
10580 23:53:14.670163 <6>[ 0.287728] CPU features: detected: Privileged Access Never
10581 23:53:14.673446 <6>[ 0.293508] CPU features: detected: RAS Extension Support
10582 23:53:14.680314 <6>[ 0.299117] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10583 23:53:14.686760 <6>[ 0.306382] CPU: All CPU(s) started at EL2
10584 23:53:14.693450 <6>[ 0.310725] alternatives: applying system-wide alternatives
10585 23:53:14.702083 <6>[ 0.321572] devtmpfs: initialized
10586 23:53:14.714587 <6>[ 0.330562] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10587 23:53:14.724415 <6>[ 0.340518] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10588 23:53:14.730770 <6>[ 0.348537] pinctrl core: initialized pinctrl subsystem
10589 23:53:14.734185 <6>[ 0.355188] DMI not present or invalid.
10590 23:53:14.741690 <6>[ 0.359598] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10591 23:53:14.747592 <6>[ 0.366460] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10592 23:53:14.758317 <6>[ 0.374044] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10593 23:53:14.765257 <6>[ 0.382268] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10594 23:53:14.771497 <6>[ 0.390508] audit: initializing netlink subsys (disabled)
10595 23:53:14.781572 <5>[ 0.396197] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10596 23:53:14.784543 <6>[ 0.396873] thermal_sys: Registered thermal governor 'step_wise'
10597 23:53:14.791135 <6>[ 0.404163] thermal_sys: Registered thermal governor 'power_allocator'
10598 23:53:14.797831 <6>[ 0.410416] cpuidle: using governor menu
10599 23:53:14.801312 <6>[ 0.421374] NET: Registered PF_QIPCRTR protocol family
10600 23:53:14.807655 <6>[ 0.426850] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10601 23:53:14.814731 <6>[ 0.433954] ASID allocator initialised with 32768 entries
10602 23:53:14.822072 <6>[ 0.440531] Serial: AMBA PL011 UART driver
10603 23:53:14.829501 <4>[ 0.449255] Trying to register duplicate clock ID: 134
10604 23:53:14.888076 <6>[ 0.510705] KASLR enabled
10605 23:53:14.902804 <6>[ 0.518472] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10606 23:53:14.908824 <6>[ 0.525488] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10607 23:53:14.915994 <6>[ 0.531979] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10608 23:53:14.922857 <6>[ 0.538980] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10609 23:53:14.928723 <6>[ 0.545469] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10610 23:53:14.936259 <6>[ 0.552476] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10611 23:53:14.942529 <6>[ 0.558958] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10612 23:53:14.948520 <6>[ 0.565965] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10613 23:53:14.952221 <6>[ 0.573493] ACPI: Interpreter disabled.
10614 23:53:14.959996 <6>[ 0.579922] iommu: Default domain type: Translated
10615 23:53:14.966930 <6>[ 0.585035] iommu: DMA domain TLB invalidation policy: strict mode
10616 23:53:14.970918 <5>[ 0.591697] SCSI subsystem initialized
10617 23:53:14.977015 <6>[ 0.595861] usbcore: registered new interface driver usbfs
10618 23:53:14.983537 <6>[ 0.601596] usbcore: registered new interface driver hub
10619 23:53:14.988127 <6>[ 0.607149] usbcore: registered new device driver usb
10620 23:53:14.993417 <6>[ 0.613250] pps_core: LinuxPPS API ver. 1 registered
10621 23:53:15.003550 <6>[ 0.618444] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10622 23:53:15.008036 <6>[ 0.627790] PTP clock support registered
10623 23:53:15.010778 <6>[ 0.632031] EDAC MC: Ver: 3.0.0
10624 23:53:15.017394 <6>[ 0.637178] FPGA manager framework
10625 23:53:15.024327 <6>[ 0.640861] Advanced Linux Sound Architecture Driver Initialized.
10626 23:53:15.027202 <6>[ 0.647640] vgaarb: loaded
10627 23:53:15.034076 <6>[ 0.650790] clocksource: Switched to clocksource arch_sys_counter
10628 23:53:15.038974 <5>[ 0.657231] VFS: Disk quotas dquot_6.6.0
10629 23:53:15.044090 <6>[ 0.661413] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10630 23:53:15.047459 <6>[ 0.668598] pnp: PnP ACPI: disabled
10631 23:53:15.055729 <6>[ 0.675271] NET: Registered PF_INET protocol family
10632 23:53:15.065773 <6>[ 0.680867] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10633 23:53:15.076878 <6>[ 0.693177] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10634 23:53:15.086697 <6>[ 0.701996] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10635 23:53:15.093654 <6>[ 0.709969] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10636 23:53:15.100296 <6>[ 0.718670] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10637 23:53:15.112759 <6>[ 0.728428] TCP: Hash tables configured (established 65536 bind 65536)
10638 23:53:15.118731 <6>[ 0.735296] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10639 23:53:15.125364 <6>[ 0.742499] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10640 23:53:15.132123 <6>[ 0.750198] NET: Registered PF_UNIX/PF_LOCAL protocol family
10641 23:53:15.138303 <6>[ 0.756360] RPC: Registered named UNIX socket transport module.
10642 23:53:15.141902 <6>[ 0.762509] RPC: Registered udp transport module.
10643 23:53:15.148188 <6>[ 0.767443] RPC: Registered tcp transport module.
10644 23:53:15.155254 <6>[ 0.772375] RPC: Registered tcp NFSv4.1 backchannel transport module.
10645 23:53:15.158425 <6>[ 0.779041] PCI: CLS 0 bytes, default 64
10646 23:53:15.161453 <6>[ 0.783385] Unpacking initramfs...
10647 23:53:15.186615 <6>[ 0.802915] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10648 23:53:15.196223 <6>[ 0.811562] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10649 23:53:15.199748 <6>[ 0.820404] kvm [1]: IPA Size Limit: 40 bits
10650 23:53:15.206614 <6>[ 0.824934] kvm [1]: GICv3: no GICV resource entry
10651 23:53:15.210320 <6>[ 0.829956] kvm [1]: disabling GICv2 emulation
10652 23:53:15.216198 <6>[ 0.834645] kvm [1]: GIC system register CPU interface enabled
10653 23:53:15.219971 <6>[ 0.840803] kvm [1]: vgic interrupt IRQ18
10654 23:53:15.226340 <6>[ 0.845159] kvm [1]: VHE mode initialized successfully
10655 23:53:15.233356 <5>[ 0.851695] Initialise system trusted keyrings
10656 23:53:15.240111 <6>[ 0.856517] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10657 23:53:15.247747 <6>[ 0.866500] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10658 23:53:15.254285 <5>[ 0.872935] NFS: Registering the id_resolver key type
10659 23:53:15.256902 <5>[ 0.878239] Key type id_resolver registered
10660 23:53:15.263182 <5>[ 0.882651] Key type id_legacy registered
10661 23:53:15.271136 <6>[ 0.886931] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10662 23:53:15.276531 <6>[ 0.893856] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10663 23:53:15.283059 <6>[ 0.901549] 9p: Installing v9fs 9p2000 file system support
10664 23:53:15.319758 <5>[ 0.939286] Key type asymmetric registered
10665 23:53:15.323305 <5>[ 0.943615] Asymmetric key parser 'x509' registered
10666 23:53:15.333323 <6>[ 0.948769] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10667 23:53:15.336286 <6>[ 0.956405] io scheduler mq-deadline registered
10668 23:53:15.339385 <6>[ 0.961174] io scheduler kyber registered
10669 23:53:15.358232 <6>[ 0.978057] EINJ: ACPI disabled.
10670 23:53:15.391012 <4>[ 1.003961] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10671 23:53:15.403032 <4>[ 1.014604] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10672 23:53:15.415521 <6>[ 1.035377] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10673 23:53:15.423990 <6>[ 1.043336] printk: console [ttyS0] disabled
10674 23:53:15.451330 <6>[ 1.067960] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10675 23:53:15.458024 <6>[ 1.077430] printk: console [ttyS0] enabled
10676 23:53:15.461432 <6>[ 1.077430] printk: console [ttyS0] enabled
10677 23:53:15.468656 <6>[ 1.086326] printk: bootconsole [mtk8250] disabled
10678 23:53:15.473964 <6>[ 1.086326] printk: bootconsole [mtk8250] disabled
10679 23:53:15.478431 <6>[ 1.097324] SuperH (H)SCI(F) driver initialized
10680 23:53:15.481210 <6>[ 1.102596] msm_serial: driver initialized
10681 23:53:15.496003 <6>[ 1.111494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10682 23:53:15.505581 <6>[ 1.120040] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10683 23:53:15.511548 <6>[ 1.128582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10684 23:53:15.521602 <6>[ 1.137210] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10685 23:53:15.528717 <6>[ 1.145917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10686 23:53:15.538545 <6>[ 1.154631] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10687 23:53:15.549066 <6>[ 1.163172] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10688 23:53:15.554968 <6>[ 1.171970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10689 23:53:15.564542 <6>[ 1.180511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10690 23:53:15.576214 <6>[ 1.196036] loop: module loaded
10691 23:53:15.583852 <6>[ 1.202028] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10692 23:53:15.605663 <4>[ 1.225318] mtk-pmic-keys: Failed to locate of_node [id: -1]
10693 23:53:15.612207 <6>[ 1.232063] megasas: 07.719.03.00-rc1
10694 23:53:15.621762 <6>[ 1.241593] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10695 23:53:15.630340 <6>[ 1.250182] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10696 23:53:15.647707 <6>[ 1.266744] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10697 23:53:15.703771 <6>[ 1.316507] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10698 23:53:17.845889 <6>[ 3.465914] Freeing initrd memory: 59564K
10699 23:53:17.857670 <6>[ 3.477618] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10700 23:53:17.868674 <6>[ 3.488544] tun: Universal TUN/TAP device driver, 1.6
10701 23:53:17.871695 <6>[ 3.494590] thunder_xcv, ver 1.0
10702 23:53:17.875419 <6>[ 3.498093] thunder_bgx, ver 1.0
10703 23:53:17.878506 <6>[ 3.501591] nicpf, ver 1.0
10704 23:53:17.889393 <6>[ 3.505595] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10705 23:53:17.892157 <6>[ 3.513071] hns3: Copyright (c) 2017 Huawei Corporation.
10706 23:53:17.895655 <6>[ 3.518661] hclge is initializing
10707 23:53:17.902212 <6>[ 3.522240] e1000: Intel(R) PRO/1000 Network Driver
10708 23:53:17.909192 <6>[ 3.527370] e1000: Copyright (c) 1999-2006 Intel Corporation.
10709 23:53:17.912259 <6>[ 3.533382] e1000e: Intel(R) PRO/1000 Network Driver
10710 23:53:17.919421 <6>[ 3.538597] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10711 23:53:17.925578 <6>[ 3.544781] igb: Intel(R) Gigabit Ethernet Network Driver
10712 23:53:17.932059 <6>[ 3.550431] igb: Copyright (c) 2007-2014 Intel Corporation.
10713 23:53:17.938790 <6>[ 3.556267] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10714 23:53:17.945184 <6>[ 3.562785] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10715 23:53:17.948764 <6>[ 3.569246] sky2: driver version 1.30
10716 23:53:17.955303 <6>[ 3.574166] usbcore: registered new device driver r8152-cfgselector
10717 23:53:17.961830 <6>[ 3.580704] usbcore: registered new interface driver r8152
10718 23:53:17.965021 <6>[ 3.586523] VFIO - User Level meta-driver version: 0.3
10719 23:53:17.974671 <6>[ 3.594727] usbcore: registered new interface driver usb-storage
10720 23:53:17.981398 <6>[ 3.601178] usbcore: registered new device driver onboard-usb-hub
10721 23:53:17.990237 <6>[ 3.610289] mt6397-rtc mt6359-rtc: registered as rtc0
10722 23:53:18.000613 <6>[ 3.615752] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:53:18 UTC (1717026798)
10723 23:53:18.003677 <6>[ 3.625312] i2c_dev: i2c /dev entries driver
10724 23:53:18.020267 <6>[ 3.637088] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10725 23:53:18.027367 <4>[ 3.645809] cpu cpu0: supply cpu not found, using dummy regulator
10726 23:53:18.033757 <4>[ 3.652232] cpu cpu1: supply cpu not found, using dummy regulator
10727 23:53:18.040273 <4>[ 3.658641] cpu cpu2: supply cpu not found, using dummy regulator
10728 23:53:18.046623 <4>[ 3.665043] cpu cpu3: supply cpu not found, using dummy regulator
10729 23:53:18.053561 <4>[ 3.671435] cpu cpu4: supply cpu not found, using dummy regulator
10730 23:53:18.060415 <4>[ 3.677832] cpu cpu5: supply cpu not found, using dummy regulator
10731 23:53:18.066640 <4>[ 3.684227] cpu cpu6: supply cpu not found, using dummy regulator
10732 23:53:18.073250 <4>[ 3.690640] cpu cpu7: supply cpu not found, using dummy regulator
10733 23:53:18.092987 <6>[ 3.712294] cpu cpu0: EM: created perf domain
10734 23:53:18.095336 <6>[ 3.717205] cpu cpu4: EM: created perf domain
10735 23:53:18.103197 <6>[ 3.722797] sdhci: Secure Digital Host Controller Interface driver
10736 23:53:18.109196 <6>[ 3.729224] sdhci: Copyright(c) Pierre Ossman
10737 23:53:18.116107 <6>[ 3.734180] Synopsys Designware Multimedia Card Interface Driver
10738 23:53:18.122862 <6>[ 3.740812] sdhci-pltfm: SDHCI platform and OF driver helper
10739 23:53:18.126628 <6>[ 3.740953] mmc0: CQHCI version 5.10
10740 23:53:18.132698 <6>[ 3.750803] ledtrig-cpu: registered to indicate activity on CPUs
10741 23:53:18.139780 <6>[ 3.757702] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10742 23:53:18.146021 <6>[ 3.764750] usbcore: registered new interface driver usbhid
10743 23:53:18.149361 <6>[ 3.770572] usbhid: USB HID core driver
10744 23:53:18.156052 <6>[ 3.774771] spi_master spi0: will run message pump with realtime priority
10745 23:53:18.198552 <6>[ 3.811768] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10746 23:53:18.217132 <6>[ 3.826993] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10747 23:53:18.224215 <6>[ 3.841704] cros-ec-spi spi0.0: Chrome EC device registered
10748 23:53:18.227570 <6>[ 3.847823] mmc0: Command Queue Engine enabled
10749 23:53:18.233997 <6>[ 3.852576] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10750 23:53:18.240631 <6>[ 3.860275] mmcblk0: mmc0:0001 DA4128 116 GiB
10751 23:53:18.250693 <6>[ 3.870762] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10752 23:53:18.258170 <6>[ 3.878446] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10753 23:53:18.268380 <6>[ 3.882644] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10754 23:53:18.271426 <6>[ 3.884371] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10755 23:53:18.278620 <6>[ 3.894406] NET: Registered PF_PACKET protocol family
10756 23:53:18.284915 <6>[ 3.898975] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10757 23:53:18.288356 <6>[ 3.903578] 9pnet: Installing 9P2000 support
10758 23:53:18.295346 <5>[ 3.914584] Key type dns_resolver registered
10759 23:53:18.298245 <6>[ 3.919538] registered taskstats version 1
10760 23:53:18.305124 <5>[ 3.923923] Loading compiled-in X.509 certificates
10761 23:53:18.334958 <4>[ 3.948067] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10762 23:53:18.344860 <4>[ 3.958827] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10763 23:53:18.359452 <6>[ 3.979444] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10764 23:53:18.366369 <6>[ 3.986348] xhci-mtk 11200000.usb: xHCI Host Controller
10765 23:53:18.373204 <6>[ 3.991890] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10766 23:53:18.383449 <6>[ 3.999753] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10767 23:53:18.389899 <6>[ 4.009212] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10768 23:53:18.396270 <6>[ 4.015425] xhci-mtk 11200000.usb: xHCI Host Controller
10769 23:53:18.402900 <6>[ 4.020932] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10770 23:53:18.409483 <6>[ 4.028592] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10771 23:53:18.416848 <6>[ 4.036386] hub 1-0:1.0: USB hub found
10772 23:53:18.419463 <6>[ 4.040405] hub 1-0:1.0: 1 port detected
10773 23:53:18.426336 <6>[ 4.044690] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10774 23:53:18.433080 <6>[ 4.053392] hub 2-0:1.0: USB hub found
10775 23:53:18.437212 <6>[ 4.057414] hub 2-0:1.0: 1 port detected
10776 23:53:18.445014 <6>[ 4.064690] mtk-msdc 11f70000.mmc: Got CD GPIO
10777 23:53:18.461639 <6>[ 4.078098] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10778 23:53:18.468221 <6>[ 4.086131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10779 23:53:18.478036 <4>[ 4.094047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10780 23:53:18.487788 <6>[ 4.103586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10781 23:53:18.494381 <6>[ 4.111665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10782 23:53:18.501404 <6>[ 4.119680] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10783 23:53:18.511284 <6>[ 4.127602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10784 23:53:18.518473 <6>[ 4.135420] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10785 23:53:18.528194 <6>[ 4.143237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10786 23:53:18.537613 <6>[ 4.153667] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10787 23:53:18.544628 <6>[ 4.162024] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10788 23:53:18.554070 <6>[ 4.170373] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10789 23:53:18.561067 <6>[ 4.178711] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10790 23:53:18.571304 <6>[ 4.187049] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10791 23:53:18.578331 <6>[ 4.195387] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10792 23:53:18.587599 <6>[ 4.203724] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10793 23:53:18.594158 <6>[ 4.212063] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10794 23:53:18.604171 <6>[ 4.220401] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10795 23:53:18.611186 <6>[ 4.228739] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10796 23:53:18.620833 <6>[ 4.237085] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10797 23:53:18.627286 <6>[ 4.245423] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10798 23:53:18.637662 <6>[ 4.253761] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10799 23:53:18.644128 <6>[ 4.262099] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10800 23:53:18.653824 <6>[ 4.270438] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10801 23:53:18.660832 <6>[ 4.279191] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10802 23:53:18.667299 <6>[ 4.286347] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10803 23:53:18.673649 <6>[ 4.293117] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10804 23:53:18.680525 <6>[ 4.299884] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10805 23:53:18.687421 <6>[ 4.306828] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10806 23:53:18.697124 <6>[ 4.313682] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10807 23:53:18.707038 <6>[ 4.322827] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10808 23:53:18.716873 <6>[ 4.331946] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10809 23:53:18.727141 <6>[ 4.341240] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10810 23:53:18.733388 <6>[ 4.350707] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10811 23:53:18.743606 <6>[ 4.360178] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10812 23:53:18.753718 <6>[ 4.369298] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10813 23:53:18.763300 <6>[ 4.378765] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10814 23:53:18.773294 <6>[ 4.387883] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10815 23:53:18.783983 <6>[ 4.397177] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10816 23:53:18.793270 <6>[ 4.407338] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10817 23:53:18.803025 <6>[ 4.419142] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10818 23:53:18.846655 <6>[ 4.463043] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10819 23:53:19.000687 <6>[ 4.620590] hub 1-1:1.0: USB hub found
10820 23:53:19.003536 <6>[ 4.625098] hub 1-1:1.0: 4 ports detected
10821 23:53:19.013896 <6>[ 4.633819] hub 1-1:1.0: USB hub found
10822 23:53:19.017027 <6>[ 4.638196] hub 1-1:1.0: 4 ports detected
10823 23:53:19.126425 <6>[ 4.743175] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10824 23:53:19.152232 <6>[ 4.771825] hub 2-1:1.0: USB hub found
10825 23:53:19.154872 <6>[ 4.776245] hub 2-1:1.0: 3 ports detected
10826 23:53:19.163501 <6>[ 4.783331] hub 2-1:1.0: USB hub found
10827 23:53:19.166333 <6>[ 4.787782] hub 2-1:1.0: 3 ports detected
10828 23:53:19.342367 <6>[ 4.959167] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10829 23:53:19.474558 <6>[ 5.094430] hub 1-1.4:1.0: USB hub found
10830 23:53:19.481011 <6>[ 5.099059] hub 1-1.4:1.0: 2 ports detected
10831 23:53:19.486592 <6>[ 5.106729] hub 1-1.4:1.0: USB hub found
10832 23:53:19.489969 <6>[ 5.111265] hub 1-1.4:1.0: 2 ports detected
10833 23:53:19.553956 <6>[ 5.171104] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10834 23:53:19.662513 <6>[ 5.279482] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10835 23:53:19.694742 <4>[ 5.311584] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10836 23:53:19.704780 <4>[ 5.320678] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10837 23:53:19.739490 <6>[ 5.360027] r8152 2-1.3:1.0 eth0: v1.12.13
10838 23:53:19.790065 <6>[ 5.407114] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10839 23:53:19.982213 <6>[ 5.598932] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10840 23:53:21.410042 <6>[ 7.030590] r8152 2-1.3:1.0 eth0: carrier on
10841 23:53:23.746663 <5>[ 7.054912] Sending DHCP requests .., OK
10842 23:53:23.752952 <6>[ 9.371462] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10843 23:53:23.756530 <6>[ 9.379791] IP-Config: Complete:
10844 23:53:23.769676 <6>[ 9.383288] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10845 23:53:23.776214 <6>[ 9.393998] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10846 23:53:23.783060 <6>[ 9.402616] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10847 23:53:23.789450 <6>[ 9.402625] nameserver0=192.168.201.1
10848 23:53:23.792880 <6>[ 9.414829] clk: Disabling unused clocks
10849 23:53:23.796356 <6>[ 9.420248] ALSA device list:
10850 23:53:23.803093 <6>[ 9.423552] No soundcards found.
10851 23:53:23.811328 <6>[ 9.431368] Freeing unused kernel memory: 8512K
10852 23:53:23.813988 <6>[ 9.436399] Run /init as init process
10853 23:53:23.846709 <6>[ 9.467449] NET: Registered PF_INET6 protocol family
10854 23:53:23.853636 <6>[ 9.474257] Segment Routing with IPv6
10855 23:53:23.856855 <6>[ 9.478249] In-situ OAM (IOAM) with IPv6
10856 23:53:23.897715 <30>[ 9.492003] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10857 23:53:23.904729 <30>[ 9.525031] systemd[1]: Detected architecture arm64.
10858 23:53:23.904829
10859 23:53:23.907970 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10860 23:53:23.911357
10861 23:53:23.926689 <30>[ 9.547129] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10862 23:53:24.029598 <30>[ 9.647156] systemd[1]: Queued start job for default target graphical.target.
10863 23:53:24.067505 <30>[ 9.684860] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10864 23:53:24.074231 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10865 23:53:24.094345 <30>[ 9.711751] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10866 23:53:24.104322 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10867 23:53:24.123032 <30>[ 9.740650] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10868 23:53:24.132992 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10869 23:53:24.151236 <30>[ 9.768489] systemd[1]: Created slice user.slice - User and Session Slice.
10870 23:53:24.157299 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10871 23:53:24.181435 <30>[ 9.795793] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10872 23:53:24.191421 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10873 23:53:24.209283 <30>[ 9.823277] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10874 23:53:24.215918 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10875 23:53:24.243908 <30>[ 9.851647] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10876 23:53:24.254112 <30>[ 9.871633] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10877 23:53:24.261139 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10878 23:53:24.278264 <30>[ 9.895121] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10879 23:53:24.284616 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10880 23:53:24.301984 <30>[ 9.919141] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10881 23:53:24.311943 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10882 23:53:24.326913 <30>[ 9.947631] systemd[1]: Reached target paths.target - Path Units.
10883 23:53:24.336858 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10884 23:53:24.354285 <30>[ 9.971521] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10885 23:53:24.360904 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10886 23:53:24.374464 <30>[ 9.995069] systemd[1]: Reached target slices.target - Slice Units.
10887 23:53:24.384545 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10888 23:53:24.399068 <30>[ 10.019570] systemd[1]: Reached target swap.target - Swaps.
10889 23:53:24.405324 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10890 23:53:24.426324 <30>[ 10.043598] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10891 23:53:24.436529 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10892 23:53:24.454671 <30>[ 10.071950] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10893 23:53:24.464189 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10894 23:53:24.483221 <30>[ 10.100674] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10895 23:53:24.493522 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10896 23:53:24.510145 <30>[ 10.127773] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10897 23:53:24.520347 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10898 23:53:24.538665 <30>[ 10.155668] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10899 23:53:24.544881 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10900 23:53:24.562452 <30>[ 10.179710] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10901 23:53:24.572185 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10902 23:53:24.590587 <30>[ 10.207723] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10903 23:53:24.600492 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10904 23:53:24.650128 <30>[ 10.267147] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10905 23:53:24.656422 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10906 23:53:24.676000 <30>[ 10.293150] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10907 23:53:24.682384 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10908 23:53:24.704103 <30>[ 10.321934] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10909 23:53:24.711093 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10910 23:53:24.736611 <30>[ 10.347447] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10911 23:53:24.774294 <30>[ 10.391794] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10912 23:53:24.784106 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10913 23:53:24.807178 <30>[ 10.424442] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10914 23:53:24.813559 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10915 23:53:24.838740 <30>[ 10.456115] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10916 23:53:24.849001 Startin<6>[ 10.465590] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10917 23:53:24.855147 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10918 23:53:24.878990 <30>[ 10.496550] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10919 23:53:24.885825 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10920 23:53:24.908083 <30>[ 10.525663] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10921 23:53:24.914641 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10922 23:53:24.936471 <30>[ 10.554273] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10923 23:53:24.944002 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10924 23:53:24.969813 <30>[ 10.587279] systemd[1]: Starting systemd-journald.service - Journal Service...
10925 23:53:24.976903 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10926 23:53:25.000294 <30>[ 10.617912] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10927 23:53:25.006876 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10928 23:53:25.031531 <30>[ 10.645670] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10929 23:53:25.038171 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10930 23:53:25.061884 <30>[ 10.679493] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10931 23:53:25.071737 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10932 23:53:25.092951 <30>[ 10.710525] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10933 23:53:25.099834 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10934 23:53:25.122556 <30>[ 10.739956] systemd[1]: Started systemd-journald.service - Journal Service.
10935 23:53:25.129409 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10936 23:53:25.148643 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10937 23:53:25.166798 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10938 23:53:25.186511 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10939 23:53:25.207363 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10940 23:53:25.227349 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10941 23:53:25.247478 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10942 23:53:25.268221 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10943 23:53:25.288616 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10944 23:53:25.310559 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10945 23:53:25.328775 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10946 23:53:25.347386 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10947 23:53:25.368822 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10948 23:53:25.375109 See 'systemctl status systemd-remount-fs.service' for details.
10949 23:53:25.384795 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10950 23:53:25.404770 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10951 23:53:25.462276 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10952 23:53:25.482822 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10953 23:53:25.503874 <46>[ 11.121462] systemd-journald[195]: Received client request to flush runtime journal.
10954 23:53:25.510495 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10955 23:53:25.534748 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10956 23:53:25.557547 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10957 23:53:25.579919 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10958 23:53:25.599538 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10959 23:53:25.619037 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10960 23:53:25.639206 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10961 23:53:25.659086 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10962 23:53:25.710837 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10963 23:53:25.746030 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10964 23:53:25.762411 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10965 23:53:25.781666 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10966 23:53:25.826495 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10967 23:53:25.847038 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10968 23:53:25.869469 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10969 23:53:25.908435 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10970 23:53:25.931830 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10971 23:53:25.951700 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10972 23:53:26.005468 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10973 23:53:26.033085 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - N<46>[ 11.652397] systemd-journald[195]: Time jumped backwards, rotating.
10974 23:53:26.036320 etwork Time Synchronization.
10975 23:53:26.078734 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10976 23:53:26.175506 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10977 23:53:26.194446 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10978 23:53:26.214377 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10979 23:53:26.235416 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10980 23:53:26.255116 [[0;32m OK [<6>[ 11.873674] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10981 23:53:26.262354 0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10982 23:53:26.269693 <6>[ 11.890496] remoteproc remoteproc0: scp is available
10983 23:53:26.276680 <6>[ 11.895392] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10984 23:53:26.282801 <6>[ 11.897046] remoteproc remoteproc0: powering up scp
10985 23:53:26.292783 <6>[ 11.903517] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10986 23:53:26.299770 <6>[ 11.908635] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10987 23:53:26.309756 <6>[ 11.917400] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10988 23:53:26.312902 <6>[ 11.925242] Bluetooth: Core ver 2.22
10989 23:53:26.319609 <6>[ 11.925820] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10990 23:53:26.323089 <6>[ 11.925947] NET: Registered PF_BLUETOOTH protocol family
10991 23:53:26.332673 <3>[ 11.937313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10992 23:53:26.339737 <6>[ 11.938702] Bluetooth: HCI device and connection manager initialized
10993 23:53:26.345871 <3>[ 11.944617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10994 23:53:26.352361 <6>[ 11.950170] Bluetooth: HCI socket layer initialized
10995 23:53:26.359667 <3>[ 11.957877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10996 23:53:26.366385 <6>[ 11.964422] Bluetooth: L2CAP socket layer initialized
10997 23:53:26.369359 <6>[ 11.964462] Bluetooth: SCO socket layer initialized
10998 23:53:26.375606 <6>[ 11.969091] mc: Linux media interface: v0.10
10999 23:53:26.382596 <3>[ 11.974581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11000 23:53:26.388894 <4>[ 12.001541] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11001 23:53:26.398752 <6>[ 12.004767] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11002 23:53:26.405587 <3>[ 12.008932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11003 23:53:26.412262 <4>[ 12.019483] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11004 23:53:26.419078 <6>[ 12.019856] videodev: Linux video capture interface: v2.00
11005 23:53:26.429055 <3>[ 12.023746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11006 23:53:26.435512 <3>[ 12.023761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11007 23:53:26.445750 <3>[ 12.023770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11008 23:53:26.452584 <3>[ 12.023961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11009 23:53:26.459323 <3>[ 12.024050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11010 23:53:26.469165 <3>[ 12.024055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11011 23:53:26.475824 <3>[ 12.024060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11012 23:53:26.486071 <3>[ 12.024187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11013 23:53:26.492813 <3>[ 12.024192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11014 23:53:26.499772 <3>[ 12.024196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11015 23:53:26.509234 <3>[ 12.024199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11016 23:53:26.516102 <3>[ 12.024203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11017 23:53:26.526872 <3>[ 12.024227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11018 23:53:26.530492 <6>[ 12.060132] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11019 23:53:26.537401 <6>[ 12.062024] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11020 23:53:26.547537 <6>[ 12.062059] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11021 23:53:26.555054 <6>[ 12.062069] remoteproc remoteproc0: remote processor scp is now up
11022 23:53:26.558181 <6>[ 12.070051] pci_bus 0000:00: root bus resource [bus 00-ff]
11023 23:53:26.568179 <6>[ 12.070057] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11024 23:53:26.577950 <6>[ 12.070059] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11025 23:53:26.581727 <6>[ 12.070095] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11026 23:53:26.592290 <6>[ 12.095524] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11027 23:53:26.599037 <4>[ 12.097440] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11028 23:53:26.605336 <4>[ 12.097440] Fallback method does not support PEC.
11029 23:53:26.612239 <6>[ 12.102483] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11030 23:53:26.621842 <6>[ 12.103410] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11031 23:53:26.632064 <6>[ 12.103809] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11032 23:53:26.638682 <6>[ 12.112734] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11033 23:53:26.648623 <3>[ 12.115672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 23:53:26.652354 <6>[ 12.118688] pci 0000:00:00.0: supports D1 D2
11035 23:53:26.662327 <3>[ 12.157439] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11036 23:53:26.669024 <6>[ 12.157794] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11037 23:53:26.676354 <3>[ 12.158314] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11038 23:53:26.686901 <3>[ 12.181145] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11039 23:53:26.696852 <6>[ 12.186091] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11040 23:53:26.703525 <6>[ 12.186453] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11041 23:53:26.710998 <6>[ 12.186530] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11042 23:53:26.717536 <6>[ 12.186554] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11043 23:53:26.724026 <6>[ 12.186572] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11044 23:53:26.730523 <6>[ 12.186586] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11045 23:53:26.737384 <6>[ 12.186690] pci 0000:01:00.0: supports D1 D2
11046 23:53:26.744406 <6>[ 12.186691] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11047 23:53:26.751193 <6>[ 12.202925] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11048 23:53:26.757824 <3>[ 12.233031] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11049 23:53:26.768172 <6>[ 12.238319] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11050 23:53:26.775014 <6>[ 12.288950] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11051 23:53:26.778660 <6>[ 12.289479] usbcore: registered new interface driver btusb
11052 23:53:26.792040 <4>[ 12.290314] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11053 23:53:26.795320 <3>[ 12.290324] Bluetooth: hci0: Failed to load firmware file (-2)
11054 23:53:26.803011 <3>[ 12.290328] Bluetooth: hci0: Failed to set up firmware (-2)
11055 23:53:26.812518 <4>[ 12.290331] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11056 23:53:26.819348 <6>[ 12.294573] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11057 23:53:26.829886 <6>[ 12.294587] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11058 23:53:26.836593 <3>[ 12.302600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11059 23:53:26.847134 <3>[ 12.303420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11060 23:53:26.860493 <6>[ 12.304564] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11061 23:53:26.863599 <6>[ 12.304749] usbcore: registered new interface driver uvcvideo
11062 23:53:26.874034 <6>[ 12.312136] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11063 23:53:26.880236 <6>[ 12.312151] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11064 23:53:26.886961 <6>[ 12.312915] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11065 23:53:26.896828 <3>[ 12.316886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11066 23:53:26.903916 <3>[ 12.339121] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11067 23:53:26.910367 <6>[ 12.343423] pci 0000:00:00.0: PCI bridge to [bus 01]
11068 23:53:26.917402 <6>[ 12.343430] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11069 23:53:26.926906 <3>[ 12.371109] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11070 23:53:26.933585 <6>[ 12.376761] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11071 23:53:26.940447 [[0;32m OK [<6>[ 12.559994] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11072 23:53:26.946811 0m] Listening on<6>[ 12.568054] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11073 23:53:26.953823 [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11074 23:53:26.967378 <5>[ 12.584644] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11075 23:53:26.973760 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11076 23:53:26.995865 <5>[ 12.613650] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11077 23:53:27.002783 <5>[ 12.620703] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11078 23:53:27.012916 <4>[ 12.629148] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11079 23:53:27.016455 <6>[ 12.629161] cfg80211: failed to load regulatory.db
11080 23:53:27.026093 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11081 23:53:27.058353 <6>[ 12.675833] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11082 23:53:27.064818 <6>[ 12.683390] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11083 23:53:27.079214 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11084 23:53:27.085898 <6>[ 12.706935] mt7921e 0000:01:00.0: ASIC revision: 79610010
11085 23:53:27.106260 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11086 23:53:27.128303 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11087 23:53:27.146697 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11088 23:53:27.189994 <6>[ 12.807971] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11089 23:53:27.193846 <6>[ 12.807971]
11090 23:53:27.200593 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11091 23:53:27.252159 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11092 23:53:27.273574 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11093 23:53:27.290465 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11094 23:53:27.310410 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11095 23:53:27.350533 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11096 23:53:27.372367 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11097 23:53:27.390295 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11098 23:53:27.406347 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11099 23:53:27.426147 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11100 23:53:27.459459 <6>[ 13.077172] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11101 23:53:27.479373 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11102 23:53:27.503051 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11103 23:53:27.529512 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11104 23:53:27.604060 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11105 23:53:27.624171 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11106 23:53:27.648205 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11107 23:53:27.683615
11108 23:53:27.687095 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11109 23:53:27.687216
11110 23:53:27.690359 debian-bookworm-arm64 login: root (automatic login)
11111 23:53:27.690441
11112 23:53:27.705562 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11113 23:53:27.705683
11114 23:53:27.711575 The programs included with the Debian GNU/Linux system are free software;
11115 23:53:27.718213 the exact distribution terms for each program are described in the
11116 23:53:27.721699 individual files in /usr/share/doc/*/copyright.
11117 23:53:27.721826
11118 23:53:27.728062 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11119 23:53:27.731234 permitted by applicable law.
11120 23:53:27.731624 Matched prompt #10: / #
11122 23:53:27.731848 Setting prompt string to ['/ #']
11123 23:53:27.732000 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11125 23:53:27.732238 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11126 23:53:27.732323 start: 2.2.6 expect-shell-connection (timeout 00:02:32) [common]
11127 23:53:27.732397 Setting prompt string to ['/ #']
11128 23:53:27.732480 Forcing a shell prompt, looking for ['/ #']
11130 23:53:27.782677 / #
11131 23:53:27.782861 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11132 23:53:27.782967 Waiting using forced prompt support (timeout 00:02:30)
11133 23:53:27.788261
11134 23:53:27.788551 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11135 23:53:27.788645 start: 2.2.7 export-device-env (timeout 00:02:32) [common]
11136 23:53:27.788743 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11137 23:53:27.788828 end: 2.2 depthcharge-retry (duration 00:02:28) [common]
11138 23:53:27.788908 end: 2 depthcharge-action (duration 00:02:28) [common]
11139 23:53:27.789011 start: 3 lava-test-retry (timeout 00:07:07) [common]
11140 23:53:27.789099 start: 3.1 lava-test-shell (timeout 00:07:07) [common]
11141 23:53:27.789176 Using namespace: common
11143 23:53:27.889476 / # #
11144 23:53:27.889632 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11145 23:53:27.894736 #
11146 23:53:27.895038 Using /lava-14084325
11148 23:53:27.995427 / # export SHELL=/bin/sh
11149 23:53:28.000132 export SHELL=/bin/sh
11151 23:53:28.100714 / # . /lava-14084325/environment
11152 23:53:28.106160 . /lava-14084325/environment
11154 23:53:28.206688 / # /lava-14084325/bin/lava-test-runner /lava-14084325/0
11155 23:53:28.206844 Test shell timeout: 10s (minimum of the action and connection timeout)
11156 23:53:28.212220 /lava-14084325/bin/lava-test-runner /lava-14084325/0
11157 23:53:28.238528 + export TESTRUN_ID=0_igt-kms-me<8>[ 13.858656] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14084325_1.5.2.3.1>
11158 23:53:28.238846 Received signal: <STARTRUN> 0_igt-kms-mediatek 14084325_1.5.2.3.1
11159 23:53:28.238927 Starting test lava.0_igt-kms-mediatek (14084325_1.5.2.3.1)
11160 23:53:28.239015 Skipping test definition patterns.
11161 23:53:28.242039 diatek
11162 23:53:28.245538 + cd /lava-14084325/0/tests/0_igt-kms-mediatek
11163 23:53:28.245631 + cat uuid
11164 23:53:28.248799 + UUID=14084325_1.5.2.3.1
11165 23:53:28.248916 + set +x
11166 23:53:28.268090 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11167 23:53:28.276310 <8>[ 13.897175] <LAVA_SIGNAL_TESTSET START core_auth>
11168 23:53:28.276627 Received signal: <TESTSET> START core_auth
11169 23:53:28.276710 Starting test_set core_auth
11170 23:53:28.311775 <14>[ 13.932828] [IGT] core_auth: executing
11171 23:53:28.317994 IGT-Version: 1.2<14>[ 13.937549] [IGT] core_auth: starting subtest getclient-simple
11172 23:53:28.328327 8-ga44ebfe (aarc<14>[ 13.945107] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11173 23:53:28.332023 h64) (Linux: 6.1<14>[ 13.953379] [IGT] core_auth: exiting, ret=0
11174 23:53:28.335207 .91-cip21 aarch64)
11175 23:53:28.338219 Using IGT_SRANDOM=1717026808 for randomisation
11176 23:53:28.348308 Starting subtest: getclient-<8>[ 13.966554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11177 23:53:28.348604 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11179 23:53:28.355217 <6>[ 13.967192] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11180 23:53:28.355339 simple
11181 23:53:28.358494 Opened device: /dev/dri/card0
11182 23:53:28.362008 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11183 23:53:28.370074 <14>[ 13.991345] [IGT] core_auth: executing
11184 23:53:28.376551 IGT-Version: 1.2<14>[ 13.995777] [IGT] core_auth: starting subtest getclient-master-drop
11185 23:53:28.386875 8-ga44ebfe (aarc<14>[ 14.003884] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11186 23:53:28.393251 h64) (Linux: 6.1<14>[ 14.012576] [IGT] core_auth: exiting, ret=0
11187 23:53:28.393347 .91-cip21 aarch64)
11188 23:53:28.396654 Using IGT_SRANDOM=1717026808 for randomisation
11189 23:53:28.406714 Starting sub<8>[ 14.024239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11190 23:53:28.406999 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11192 23:53:28.410409 test: getclient-master-drop
11193 23:53:28.413807 Opened device: /dev/dri/card0
11194 23:53:28.416360 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11195 23:53:28.436515 <14>[ 14.057676] [IGT] core_auth: executing
11196 23:53:28.442834 IGT-Version: 1.2<14>[ 14.062455] [IGT] core_auth: starting subtest basic-auth
11197 23:53:28.449664 8-ga44ebfe (aarc<14>[ 14.069432] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11198 23:53:28.456575 h64) (Linux: 6.1<14>[ 14.077135] [IGT] core_auth: exiting, ret=0
11199 23:53:28.459705 .91-cip21 aarch64)
11200 23:53:28.463279 Using IGT_SRANDOM=1717026808 for randomisation
11201 23:53:28.469654 Opened devic<8>[ 14.089484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11202 23:53:28.469950 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11204 23:53:28.473090 e: /dev/dri/card0
11205 23:53:28.476299 Starting subtest: basic-auth
11206 23:53:28.479616 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11207 23:53:28.489093 <14>[ 14.110490] [IGT] core_auth: executing
11208 23:53:28.496013 IGT-Version: 1.2<14>[ 14.114995] [IGT] core_auth: starting subtest many-magics
11209 23:53:28.498987 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11210 23:53:28.509358 Using IGT_SRANDOM=1717026808<14>[ 14.128266] [IGT] core_auth: finished subtest many-magics, SUCCESS
11211 23:53:28.512520 <14>[ 14.135338] [IGT] core_auth: exiting, ret=0
11212 23:53:28.515866 for randomisation
11213 23:53:28.519212 Opened device: /dev/dri/card0
11214 23:53:28.526083 Starting subt<8>[ 14.145277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11215 23:53:28.526378 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11217 23:53:28.532294 est: many-magics<8>[ 14.153546] <LAVA_SIGNAL_TESTSET STOP>
11218 23:53:28.532402
11219 23:53:28.532649 Received signal: <TESTSET> STOP
11220 23:53:28.532729 Closing test_set core_auth
11221 23:53:28.535634 Reopening device failed after 1020 opens
11222 23:53:28.538992 [1mSubtest many-magics: SUCCESS (0.006s)[0m
11223 23:53:28.576365 <14>[ 14.197821] [IGT] core_getclient: executing
11224 23:53:28.583294 IGT-Version: 1.2<14>[ 14.202714] [IGT] core_getclient: exiting, ret=0
11225 23:53:28.586516 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11226 23:53:28.596267 Using IGT_SR<8>[ 14.214022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11227 23:53:28.596574 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11229 23:53:28.600112 ANDOM=1717026808 for randomisation
11230 23:53:28.600208 Opened device: /dev/dri/card0
11231 23:53:28.603282 SUCCESS (0.006s)
11232 23:53:28.642870 <14>[ 14.264081] [IGT] core_getstats: executing
11233 23:53:28.649808 IGT-Version: 1.2<14>[ 14.269143] [IGT] core_getstats: exiting, ret=0
11234 23:53:28.652677 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11235 23:53:28.662585 Using IGT_SRANDOM=1717026808<8>[ 14.280930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11236 23:53:28.662942 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11238 23:53:28.666117 for randomisation
11239 23:53:28.666232 Opened device: /dev/dri/card0
11240 23:53:28.669350 SUCCESS (0.006s)
11241 23:53:28.711689 <14>[ 14.332622] [IGT] core_getversion: executing
11242 23:53:28.717967 IGT-Version: 1.2<14>[ 14.337610] [IGT] core_getversion: exiting, ret=0
11243 23:53:28.725098 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11244 23:53:28.731569 Using IGT_SR<8>[ 14.349187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11245 23:53:28.731888 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11247 23:53:28.734745 ANDOM=1717026808 for randomisation
11248 23:53:28.734874 Opened device: /dev/dri/card0
11249 23:53:28.738431 SUCCESS (0.006s)
11250 23:53:28.763615 <14>[ 14.384731] [IGT] core_setmaster_vs_auth: executing
11251 23:53:28.770045 IGT-Version: 1.2<14>[ 14.390363] [IGT] core_setmaster_vs_auth: exiting, ret=0
11252 23:53:28.776668 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11253 23:53:28.783495 Using IGT_SR<8>[ 14.402332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11254 23:53:28.783809 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11256 23:53:28.786460 ANDOM=1717026808 for randomisation
11257 23:53:28.789859 Opened device: /dev/dri/card0
11258 23:53:28.793498 SUCCESS (0.007s)
11259 23:53:28.808432 <8>[ 14.428325] <LAVA_SIGNAL_TESTSET START drm_read>
11260 23:53:28.808780 Received signal: <TESTSET> START drm_read
11261 23:53:28.808888 Starting test_set drm_read
11262 23:53:28.828043 <14>[ 14.449189] [IGT] drm_read: executing
11263 23:53:28.834543 IGT-Version: 1.2<14>[ 14.453694] [IGT] drm_read: exiting, ret=77
11264 23:53:28.837997 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11265 23:53:28.844716 Using IGT_SR<8>[ 14.464620] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11266 23:53:28.845006 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11268 23:53:28.847984 ANDOM=1717026808 for randomisation
11269 23:53:28.851176 Opened device: /dev/dri/card0
11270 23:53:28.854682 No KMS driver or no outputs, pipes: 16, outputs: 0
11271 23:53:28.864348 [1mSubtest invalid-buffer: SKIP (0.000s)<14>[ 14.485632] [IGT] drm_read: executing
11272 23:53:28.864508 [0m
11273 23:53:28.871238 IGT-Version: 1.2<14>[ 14.490462] [IGT] drm_read: exiting, ret=77
11274 23:53:28.874678 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11275 23:53:28.880930 Using IGT_SR<8>[ 14.501645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11276 23:53:28.881250 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11278 23:53:28.884237 ANDOM=1717026808 for randomisation
11279 23:53:28.887536 Opened device: /dev/dri/card0
11280 23:53:28.894534 No KMS driver or no outputs, pipes: 16, outputs: 0
11281 23:53:28.900885 [1mSubtest fault-buffer: SKIP (0.000s)[<14>[ 14.522541] [IGT] drm_read: executing
11282 23:53:28.901010 0m
11283 23:53:28.907531 IGT-Version: 1.2<14>[ 14.527493] [IGT] drm_read: exiting, ret=77
11284 23:53:28.910714 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11285 23:53:28.921069 Using IGT_SRANDOM=1717026808<8>[ 14.539402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11286 23:53:28.921221 for randomisation
11287 23:53:28.921496 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11289 23:53:28.924724 Opened device: /dev/dri/card0
11290 23:53:28.930704 No KMS driver or no outputs, pipes: 16, outputs: 0
11291 23:53:28.934461 [1mSubtest empty-block: SKIP (0.000s)[0m
11292 23:53:28.937743 <14>[ 14.560505] [IGT] drm_read: executing
11293 23:53:28.944531 IGT-Version: 1.2<14>[ 14.564963] [IGT] drm_read: exiting, ret=77
11294 23:53:28.947771 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11295 23:53:28.957525 Using IGT_SRANDOM=1717026808<8>[ 14.576176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11296 23:53:28.957827 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11298 23:53:28.960773 for randomisation
11299 23:53:28.964450 Opened device: /dev/dri/card0
11300 23:53:28.967243 No KMS driver or no outputs, pipes: 16, outputs: 0
11301 23:53:28.970617 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11302 23:53:28.974079 <14>[ 14.598093] [IGT] drm_read: executing
11303 23:53:28.981204 IGT-Version: 1.2<14>[ 14.602716] [IGT] drm_read: exiting, ret=77
11304 23:53:28.987613 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11305 23:53:28.994290 Using IGT_SR<8>[ 14.613640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11306 23:53:28.994615 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11308 23:53:28.997720 ANDOM=1717026808 for randomisation
11309 23:53:29.000810 Opened device: /dev/dri/card0
11310 23:53:29.004720 No KMS driver or no outputs, pipes: 16, outputs: 0
11311 23:53:29.014295 [1mSubtest short-buffer-block: SKIP (0.0<14>[ 14.635154] [IGT] drm_read: executing
11312 23:53:29.014453 00s)[0m
11313 23:53:29.017993 <14>[ 14.639940] [IGT] drm_read: exiting, ret=77
11314 23:53:29.030989 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch6<8>[ 14.650221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11315 23:53:29.031128 4)
11316 23:53:29.031378 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11318 23:53:29.038290 Using IGT_SRANDOM=1717026809 for randomisation
11319 23:53:29.038414 Opened device: /dev/dri/card0
11320 23:53:29.044280 No KMS driver or no outputs, pipes: 16, outputs: 0
11321 23:53:29.047867 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11322 23:53:29.051537 <14>[ 14.673518] [IGT] drm_read: executing
11323 23:53:29.057513 IGT-Version: 1.2<14>[ 14.679144] [IGT] drm_read: exiting, ret=77
11324 23:53:29.064333 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11325 23:53:29.070749 Using IGT_SR<8>[ 14.689958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11326 23:53:29.071061 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11328 23:53:29.077769 ANDOM=1717026809 for randomisati<8>[ 14.699243] <LAVA_SIGNAL_TESTSET STOP>
11329 23:53:29.077900 on
11330 23:53:29.078171 Received signal: <TESTSET> STOP
11331 23:53:29.078241 Closing test_set drm_read
11332 23:53:29.081175 Opened device: /dev/dri/card0
11333 23:53:29.084493 No KMS driver or no outputs, pipes: 16, outputs: 0
11334 23:53:29.090898 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11335 23:53:29.109407 <8>[ 14.730850] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11336 23:53:29.109750 Received signal: <TESTSET> START kms_addfb_basic
11337 23:53:29.109863 Starting test_set kms_addfb_basic
11338 23:53:29.139713 <14>[ 14.760650] [IGT] kms_addfb_basic: executing
11339 23:53:29.152362 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch6<14>[ 14.770204] [IGT] kms_addfb_basic: starting subtest unused-handle
11340 23:53:29.152547 4)
11341 23:53:29.158938 Using IGT_SR<14>[ 14.777693] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11342 23:53:29.162453 ANDOM=1717026809 for randomisation
11343 23:53:29.165670 Opened device: /dev/dri/card0
11344 23:53:29.169096 Starting subtest: unused-handle
11345 23:53:29.176206 [1mSubtest <14>[ 14.795174] [IGT] kms_addfb_basic: exiting, ret=0
11346 23:53:29.179366 unused-handle: SUCCESS (0.000s)[0m
11347 23:53:29.189300 Test requirement not met in function igt_re<8>[ 14.806903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11348 23:53:29.189691 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11350 23:53:29.192999 quire_intel, file ../lib/drmtest.c:880:
11351 23:53:29.195857 Test requirement: is_intel_device(fd)
11352 23:53:29.205998 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 14.829010] [IGT] kms_addfb_basic: executing
11353 23:53:29.209078 0:
11354 23:53:29.212532 Test requirement: is_intel_device(fd)
11355 23:53:29.219379 No KMS driver or no o<14>[ 14.838228] [IGT] kms_addfb_basic: starting subtest unused-pitches
11356 23:53:29.229674 utputs, pipes: 1<14>[ 14.845979] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11357 23:53:29.229808 6, outputs: 0
11358 23:53:29.235854 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11359 23:53:29.242614 Using IGT_SRA<14>[ 14.862483] [IGT] kms_addfb_basic: exiting, ret=0
11360 23:53:29.245958 NDOM=1717026809 for randomisation
11361 23:53:29.246093 Opened device: /dev/dri/card0
11362 23:53:29.255840 Starting subte<8>[ 14.874085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11363 23:53:29.256172 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11365 23:53:29.259312 st: unused-pitches
11366 23:53:29.262675 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11367 23:53:29.268790 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11368 23:53:29.275588 Test requirement: is_i<14>[ 14.896577] [IGT] kms_addfb_basic: executing
11369 23:53:29.279318 ntel_device(fd)
11370 23:53:29.288582 Test requirement not met in function igt_requir<14>[ 14.906527] [IGT] kms_addfb_basic: starting subtest unused-offsets
11371 23:53:29.295679 e_intel, file ..<14>[ 14.914331] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11372 23:53:29.298650 /lib/drmtest.c:880:
11373 23:53:29.302176 Test requirement: is_intel_device(fd)
11374 23:53:29.309120 No KMS driver or no outputs, pipes: <14>[ 14.931032] [IGT] kms_addfb_basic: exiting, ret=0
11375 23:53:29.312522 16, outputs: 0
11376 23:53:29.325399 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch6<8>[ 14.942696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11377 23:53:29.325559 4)
11378 23:53:29.325807 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11380 23:53:29.328373 Using IGT_SRANDOM=1717026809 for randomisation
11381 23:53:29.331708 Opened device: /dev/dri/card0
11382 23:53:29.335182 Starting subtest: unused-offsets
11383 23:53:29.338440 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11384 23:53:29.345415 Test requ<14>[ 14.965227] [IGT] kms_addfb_basic: executing
11385 23:53:29.355206 irement not met in function igt_require_intel, file ../lib/drmte<14>[ 14.974990] [IGT] kms_addfb_basic: starting subtest unused-modifier
11386 23:53:29.358462 st.c:880:
11387 23:53:29.365248 Test <14>[ 14.982772] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11388 23:53:29.368441 requirement: is_intel_device(fd)
11389 23:53:29.378299 Test requirement not met in function igt_require_intel, file .<14>[ 14.999678] [IGT] kms_addfb_basic: exiting, ret=0
11390 23:53:29.381673 ./lib/drmtest.c:880:
11391 23:53:29.384970 Test requirement: is_intel_device(fd)
11392 23:53:29.391868 No KMS driver or no<8>[ 15.011034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11393 23:53:29.392184 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11395 23:53:29.394751 outputs, pipes: 16, outputs: 0
11396 23:53:29.401203 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11397 23:53:29.404772 Using IGT_SRANDOM=1717026809 for randomisation
11398 23:53:29.411373 Opened device: /dev/dri/car<14>[ 15.034101] [IGT] kms_addfb_basic: executing
11399 23:53:29.414677 d0
11400 23:53:29.414790 Starting subtest: unused-modifier
11401 23:53:29.425033 [1mSubtest unused-modifi<14>[ 15.043690] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11402 23:53:29.434775 er: SUCCESS (0.0<14>[ 15.051737] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11403 23:53:29.434921 00s)[0m
11404 23:53:29.441709 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11405 23:53:29.448095 Te<14>[ 15.068713] [IGT] kms_addfb_basic: exiting, ret=77
11406 23:53:29.451284 st requirement: is_intel_device(fd)
11407 23:53:29.461629 Test requirement not met in function igt_re<8>[ 15.080085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11408 23:53:29.461946 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11410 23:53:29.464845 quire_intel, file ../lib/drmtest.c:880:
11411 23:53:29.467892 Test requirement: is_intel_device(fd)
11412 23:53:29.474548 No KMS driver or no outputs, pipes: 16, outputs: 0
11413 23:53:29.481318 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 15.102875] [IGT] kms_addfb_basic: executing
11414 23:53:29.484700 6.1.91-cip21 aarch64)
11415 23:53:29.494700 Using IGT_SRANDOM=1717026809 for randomi<14>[ 15.113069] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11416 23:53:29.494860 sation
11417 23:53:29.504773 Opened d<14>[ 15.122157] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11418 23:53:29.508144 evice: /dev/dri/card0
11419 23:53:29.511976 Starting subtest: clobberred-modifier
11420 23:53:29.517953 Test requirement not met in functi<14>[ 15.139525] [IGT] kms_addfb_basic: exiting, ret=77
11421 23:53:29.521505 on igt_require_i915, file ../lib/drmtest.c:885:
11422 23:53:29.535041 Test requirement: is_i915_devic<8>[ 15.150979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11423 23:53:29.535175 e(fd)
11424 23:53:29.535429 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11426 23:53:29.538081 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11427 23:53:29.548114 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11428 23:53:29.554558 Test requirement: is_intel_device<14>[ 15.174521] [IGT] kms_addfb_basic: executing
11429 23:53:29.554721 (fd)
11430 23:53:29.564528 Test requirement not met in function igt_require_intel, fi<14>[ 15.184951] [IGT] kms_addfb_basic: starting subtest legacy-format
11431 23:53:29.568230 le ../lib/drmtest.c:880:
11432 23:53:29.571372 Test requirement: is_intel_device(fd)
11433 23:53:29.581239 No KMS driver o<14>[ 15.198336] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11434 23:53:29.584445 r no outputs, pipes: 16, outputs: 0
11435 23:53:29.594903 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 a<14>[ 15.214738] [IGT] kms_addfb_basic: exiting, ret=0
11436 23:53:29.595035 arch64)
11437 23:53:29.597681 Using IGT_SRANDOM=1717026809 for randomisation
11438 23:53:29.607678 Opened device: /dev/dri<8>[ 15.226197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11439 23:53:29.607803 /card0
11440 23:53:29.608046 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11442 23:53:29.611157 Starting subtest: invalid-smem-bo-on-discrete
11443 23:53:29.621254 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11444 23:53:29.627510 Test requirement: is_intel_device(fd)<14>[ 15.248350] [IGT] kms_addfb_basic: executing
11445 23:53:29.627634
11446 23:53:29.634258 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11447 23:53:29.641183 Test requirement n<14>[ 15.261047] [IGT] kms_addfb_basic: starting subtest no-handle
11448 23:53:29.647764 ot met in functi<14>[ 15.267574] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11449 23:53:29.654325 on igt_require_intel, file ../lib/drmtest.c:880:
11450 23:53:29.661145 Test requirement: is_intel_dev<14>[ 15.281575] [IGT] kms_addfb_basic: exiting, ret=0
11451 23:53:29.661275 ice(fd)
11452 23:53:29.674114 Test requirement not met in function igt_require_intel, file ../lib/drm<8>[ 15.294021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11453 23:53:29.674429 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11455 23:53:29.677744 test.c:880:
11456 23:53:29.680676 Test requirement: is_intel_device(fd)
11457 23:53:29.684469 No KMS driver or no outputs, pipes: 16, outputs: 0
11458 23:53:29.690859 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11459 23:53:29.694488 Usin<14>[ 15.316311] [IGT] kms_addfb_basic: executing
11460 23:53:29.697593 g IGT_SRANDOM=1717026809 for randomisation
11461 23:53:29.700784 Opened device: /dev/dri/card0
11462 23:53:29.707459 Start<14>[ 15.327994] [IGT] kms_addfb_basic: starting subtest basic
11463 23:53:29.713928 ing subtest: leg<14>[ 15.334156] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11464 23:53:29.717459 acy-format
11465 23:53:29.720948 Successfully fuzzed 10000 {bpp, depth} variations
11466 23:53:29.727383 [1mSubtest legac<14>[ 15.348037] [IGT] kms_addfb_basic: exiting, ret=0
11467 23:53:29.730838 y-format: SUCCESS (0.006s)[0m
11468 23:53:29.741241 Test requirement not met in function igt_require<8>[ 15.360097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11469 23:53:29.741551 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11471 23:53:29.744169 _intel, file ../lib/drmtest.c:880:
11472 23:53:29.747678 Test requirement: is_intel_device(fd)
11473 23:53:29.754288 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11474 23:53:29.760824 Test requirement:<14>[ 15.382314] [IGT] kms_addfb_basic: executing
11475 23:53:29.764138 is_intel_device(fd)
11476 23:53:29.768264 No KMS driver or no outputs, pipes: 16, outputs: 0
11477 23:53:29.774372 IGT-Ve<14>[ 15.394019] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11478 23:53:29.784413 rsion: 1.28-ga44<14>[ 15.400826] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11479 23:53:29.787637 ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11480 23:53:29.793830 Using IGT_SRANDOM=1717026809 for r<14>[ 15.415198] [IGT] kms_addfb_basic: exiting, ret=0
11481 23:53:29.797521 andomisation
11482 23:53:29.797645 Opened device: /dev/dri/card0
11483 23:53:29.800495 Starting subtest: no-handle
11484 23:53:29.807733 [1mSu<8>[ 15.426976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11485 23:53:29.808021 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11487 23:53:29.810736 btest no-handle: SUCCESS (0.000s)[0m
11488 23:53:29.820585 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11489 23:53:29.827559 Test requirement: is_intel_device(fd)<14>[ 15.448797] [IGT] kms_addfb_basic: executing
11490 23:53:29.827678
11491 23:53:29.840837 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 15.460232] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11492 23:53:29.840968 880:
11493 23:53:29.850518 Test requi<14>[ 15.467101] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11494 23:53:29.850642 rement: is_intel_device(fd)
11495 23:53:29.857014 No KMS driver or no outputs, pipes: 16, outputs: 0
11496 23:53:29.860642 <14>[ 15.481475] [IGT] kms_addfb_basic: exiting, ret=0
11497 23:53:29.860745
11498 23:53:29.867066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11499 23:53:29.873935 Using IGT_S<8>[ 15.494000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11500 23:53:29.874240 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11502 23:53:29.876926 RANDOM=1717026809 for randomisation
11503 23:53:29.880053 Opened device: /dev/dri/card0
11504 23:53:29.883336 Starting subtest: basic
11505 23:53:29.886834 [1mSubtest basic: SUCCESS (0.000s)[0m
11506 23:53:29.894122 Test requirement not met in function igt_r<14>[ 15.515952] [IGT] kms_addfb_basic: executing
11507 23:53:29.900467 equire_intel, file ../lib/drmtest.c:880:
11508 23:53:29.903560 Test requirement: is_intel_device(fd)
11509 23:53:29.910166 <14>[ 15.528051] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11510 23:53:29.910288
11511 23:53:29.916965 Test requiremen<14>[ 15.535168] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11512 23:53:29.924062 t not met in function igt_require_intel, file ../lib/drmtest.c:880:
11513 23:53:29.930061 Test requir<14>[ 15.549389] [IGT] kms_addfb_basic: exiting, ret=0
11514 23:53:29.930185 ement: is_intel_device(fd)
11515 23:53:29.936547 No KMS driver or no outputs, pipes: 16, outputs: 0
11516 23:53:29.943380 <8>[ 15.561439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11517 23:53:29.943683 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11519 23:53:29.950147 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11520 23:53:29.953668 Using IGT_SRANDOM=1717026809 for randomisation
11521 23:53:29.956656 Opened device: /dev/dri/card0
11522 23:53:29.963244 Starting subtest: bad-pitch-0<14>[ 15.583772] [IGT] kms_addfb_basic: executing
11523 23:53:29.963364
11524 23:53:29.966467 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11525 23:53:29.976845 Test requirement not met in fun<14>[ 15.596012] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11526 23:53:29.987172 ction igt_requir<14>[ 15.602982] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11527 23:53:29.987296 e_intel, file ../lib/drmtest.c:880:
11528 23:53:29.993518 Test requirement: is_intel_device(fd)
11529 23:53:29.996854 Test<14>[ 15.617369] [IGT] kms_addfb_basic: exiting, ret=0
11530 23:53:30.003357 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11531 23:53:30.010092 <8>[ 15.629895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11532 23:53:30.010411 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11534 23:53:30.013373 Test requirement: is_intel_device(fd)
11535 23:53:30.019808 No KMS driver or no outputs, pipes: 16, outputs: 0
11536 23:53:30.026782 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11537 23:53:30.029817 Using IGT_SRANDOM<14>[ 15.651648] [IGT] kms_addfb_basic: executing
11538 23:53:30.032995 =1717026809 for randomisation
11539 23:53:30.036499 Opened device: /dev/dri/card0
11540 23:53:30.043503 Starting subtest: <14>[ 15.664205] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11541 23:53:30.046684 bad-pitch-32
11542 23:53:30.053144 [<14>[ 15.671136] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11543 23:53:30.056340 1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11544 23:53:30.066709 Test requirement not met in functi<14>[ 15.685611] [IGT] kms_addfb_basic: exiting, ret=0
11545 23:53:30.069762 on igt_require_intel, file ../lib/drmtest.c:880:
11546 23:53:30.079648 Test requirement: is_intel_dev<8>[ 15.698087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11547 23:53:30.079792 ice(fd)
11548 23:53:30.080085 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11550 23:53:30.086681 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11551 23:53:30.089669 Test requirement: is_intel_device(fd)
11552 23:53:30.099703 No KMS driver or no outputs, pipes: 16, outp<14>[ 15.720369] [IGT] kms_addfb_basic: executing
11553 23:53:30.099830 uts: 0
11554 23:53:30.106533 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11555 23:53:30.113118 Usin<14>[ 15.732382] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11556 23:53:30.123215 g IGT_SRANDOM=17<14>[ 15.739347] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11557 23:53:30.123369 17026809 for randomisation
11558 23:53:30.126227 Opened device: /dev/dri/card0
11559 23:53:30.133396 Starting subtest: bad<14>[ 15.753818] [IGT] kms_addfb_basic: exiting, ret=0
11560 23:53:30.133519 -pitch-63
11561 23:53:30.139539 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11562 23:53:30.146369 Test requirement not <8>[ 15.766172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11563 23:53:30.146675 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11565 23:53:30.152883 met in function igt_require_intel, file ../lib/drmtest.c:880:
11566 23:53:30.156152 Test requirement: is_intel_device(fd)
11567 23:53:30.169118 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 15.788076] [IGT] kms_addfb_basic: executing
11568 23:53:30.169251 t.c:880:
11569 23:53:30.172496 Test requirement: is_intel_device(fd)
11570 23:53:30.182441 No KMS driver or no outputs, pi<14>[ 15.800862] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11571 23:53:30.189215 pes: 16, outputs<14>[ 15.807684] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11572 23:53:30.189339 : 0
11573 23:53:30.195739 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11574 23:53:30.202150 Using I<14>[ 15.822128] [IGT] kms_addfb_basic: exiting, ret=0
11575 23:53:30.205898 GT_SRANDOM=1717026809 for randomisation
11576 23:53:30.209428 Opened device: /dev/dri/card0
11577 23:53:30.215559 Starting<8>[ 15.834283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11578 23:53:30.215850 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11580 23:53:30.219100 subtest: bad-pitch-128
11581 23:53:30.222030 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11582 23:53:30.229089 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11583 23:53:30.232582 Test requirement: is_intel_device(fd)
11584 23:53:30.245436 Test requirement not met in function igt_require_intel, file ../lib/drmtest<14>[ 15.865483] [IGT] kms_addfb_basic: executing
11585 23:53:30.245572 .c:880:
11586 23:53:30.248530 Test requirement: is_intel_device(fd)
11587 23:53:30.258685 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 15.877927] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11588 23:53:30.258851 0
11589 23:53:30.268590 IGT-Version:<14>[ 15.885672] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11590 23:53:30.271779 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11591 23:53:30.278521 Using IGT_SRANDOM=171702<14>[ 15.900949] [IGT] kms_addfb_basic: exiting, ret=0
11592 23:53:30.281853 6810 for randomisation
11593 23:53:30.284954 Opened device: /dev/dri/card0
11594 23:53:30.295078 Starting subtest: bad-pit<8>[ 15.912437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11595 23:53:30.295208 ch-256
11596 23:53:30.295477 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11598 23:53:30.298565 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11599 23:53:30.304916 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11600 23:53:30.312049 Test requirement: i<14>[ 15.934295] [IGT] kms_addfb_basic: executing
11601 23:53:30.315148 s_intel_device(fd)
11602 23:53:30.321707 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11603 23:53:30.328790 Test req<14>[ 15.947964] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11604 23:53:30.338223 uirement: is_int<14>[ 15.956280] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11605 23:53:30.341659 el_device(fd)
11606 23:53:30.348525 No KMS driver or no outputs, pipes: 16, outputs: <14>[ 15.969659] [IGT] kms_addfb_basic: exiting, ret=0
11607 23:53:30.348676 0
11608 23:53:30.355270 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11609 23:53:30.365336 Using IGT<8>[ 15.982351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11610 23:53:30.365643 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11612 23:53:30.368763 _SRANDOM=1717026810 for randomisation
11613 23:53:30.372165 Opened device: /dev/dri/card0
11614 23:53:30.372344 Starting subtest: bad-pitch-1024
11615 23:53:30.378669 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11616 23:53:30.384813 Test requirement not m<14>[ 16.005387] [IGT] kms_addfb_basic: executing
11617 23:53:30.388296 et in function igt_require_intel, file ../lib/drmtest.c:880:
11618 23:53:30.392029 Test requirement: is_intel_device(fd)
11619 23:53:30.402059 Test requir<14>[ 16.019283] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11620 23:53:30.408494 ement not met in<14>[ 16.027290] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11621 23:53:30.418419 function igt_require_intel, file ../lib/drmtest<14>[ 16.040167] [IGT] kms_addfb_basic: exiting, ret=0
11622 23:53:30.418548 .c:880:
11623 23:53:30.421433 Test requirement: is_intel_device(fd)
11624 23:53:30.431478 No KMS driver or<8>[ 16.050586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11625 23:53:30.431787 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11627 23:53:30.435127 no outputs, pipes: 16, outputs: 0
11628 23:53:30.441505 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11629 23:53:30.444866 Using IGT_SRANDOM=1717026810 for randomisation
11630 23:53:30.448207 Opened device: /dev/dri/card0
11631 23:53:30.451508 Starting subtest: bad-pitch-999
11632 23:53:30.455168 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11633 23:53:30.461700 Test re<14>[ 16.081753] [IGT] kms_addfb_basic: executing
11634 23:53:30.468446 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11635 23:53:30.478092 Test requirement: is_intel_device(f<14>[ 16.096046] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11636 23:53:30.478227 d)
11637 23:53:30.484719 Test require<14>[ 16.103528] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11638 23:53:30.498093 ment not met in function igt_require_intel, file ../lib/drmtest.<14>[ 16.117118] [IGT] kms_addfb_basic: exiting, ret=0
11639 23:53:30.498297 c:880:
11640 23:53:30.501399 Test requirement: is_intel_device(fd)
11641 23:53:30.511085 No KMS driver or no outputs, pipe<8>[ 16.129078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11642 23:53:30.511391 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11644 23:53:30.514708 s: 16, outputs: 0
11645 23:53:30.517628 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11646 23:53:30.524583 Using IGT_SRANDOM=1717026810 for randomisation
11647 23:53:30.531086 Opened device: /dev/dri/c<14>[ 16.151663] [IGT] kms_addfb_basic: executing
11648 23:53:30.531228 ard0
11649 23:53:30.534149 Starting subtest: bad-pitch-65536
11650 23:53:30.537553 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11651 23:53:30.547531 Test requirement not<14>[ 16.165237] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11652 23:53:30.554231 met in function<14>[ 16.173107] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11653 23:53:30.561258 igt_require_intel, file ../lib/drmtest.c:880:
11654 23:53:30.564038 <14>[ 16.185943] [IGT] kms_addfb_basic: exiting, ret=0
11655 23:53:30.567414 Test requirement: is_intel_device(fd)
11656 23:53:30.577339 Test requirement not met in function igt_<8>[ 16.197247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11657 23:53:30.577663 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11659 23:53:30.584147 require_intel, file ../lib/drmtest.c:880:
11660 23:53:30.587565 Test requirement: is_intel_device(fd)
11661 23:53:30.590616 No KMS driver or no outputs, pipes: 16, outputs: 0
11662 23:53:30.597683 IGT-Version: 1.28-ga44ebfe (aarch64) (Linu<14>[ 16.220399] [IGT] kms_addfb_basic: executing
11663 23:53:30.600539 x: 6.1.91-cip21 aarch64)
11664 23:53:30.604289 Using IGT_SRANDOM=1717026810 for randomisation
11665 23:53:30.607113 Opened device: /dev/dri/card0
11666 23:53:30.617554 Starting subtest: inval<14>[ 16.235985] [IGT] kms_addfb_basic: starting subtest master-rmfb
11667 23:53:30.617686 id-get-prop-any
11668 23:53:30.623935 <14>[ 16.243062] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11669 23:53:30.624045
11670 23:53:30.634019 [1mSubtest invalid-get-prop-an<14>[ 16.253448] [IGT] kms_addfb_basic: exiting, ret=0
11671 23:53:30.634142 y: SUCCESS (0.000s)[0m
11672 23:53:30.647638 Test requirement not met in function igt_require_intel,<8>[ 16.265132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11673 23:53:30.647960 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11675 23:53:30.650419 file ../lib/drmtest.c:880:
11676 23:53:30.653745 Test requirement: is_intel_device(fd)
11677 23:53:30.660279 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11678 23:53:30.666884 Test requirement: is_int<14>[ 16.287277] [IGT] kms_addfb_basic: executing
11679 23:53:30.667009 el_device(fd)
11680 23:53:30.673620 No KMS driver or no outputs, pipes: 16, outputs: 0
11681 23:53:30.677007 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11682 23:53:30.687112 Using IGT<14>[ 16.305368] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11683 23:53:30.697224 _SRANDOM=1717026<14>[ 16.313246] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11684 23:53:30.703709 810 for randomis<14>[ 16.322939] [IGT] kms_addfb_basic: exiting, ret=0
11685 23:53:30.703840 ation
11686 23:53:30.707136 Opened device: /dev/dri/card0
11687 23:53:30.716679 Starting subtest: invalid-<8>[ 16.334363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11688 23:53:30.716817 get-prop
11689 23:53:30.717108 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11691 23:53:30.719927 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11692 23:53:30.730151 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11693 23:53:30.733927 Test requireme<14>[ 16.356211] [IGT] kms_addfb_basic: executing
11694 23:53:30.736791 nt: is_intel_device(fd)
11695 23:53:30.743304 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11696 23:53:30.753605 Test requirement: is_intel_device(f<14>[ 16.373592] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11697 23:53:30.753754 d)
11698 23:53:30.760140 No KMS driver or no outputs, pipes: 16, outputs: 0
11699 23:53:30.769968 IGT-Version: 1.28-ga44eb<14>[ 16.387362] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11700 23:53:30.773318 fe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11701 23:53:30.776785 Using IGT_SRANDOM=1717026810 for randomisation
11702 23:53:30.779776 Opened device: /dev/dri/card0
11703 23:53:30.783528 Starting subtest: invalid-set-prop-any
11704 23:53:30.786393 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11705 23:53:30.796587 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11706 23:53:30.799684 Test requirement: is_intel_device(fd)
11707 23:53:30.806432 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11708 23:53:30.810282 Test requirement: is_intel_device(fd)
11709 23:53:30.812919 No KMS driver or no outputs, pipes: 16, outputs: 0
11710 23:53:30.819596 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11711 23:53:30.823101 Using IGT_SRANDOM=1717026810 for randomisation
11712 23:53:30.826636 Opened device: /dev/dri/card0
11713 23:53:30.829659 Starting subtest: invalid-set-prop
11714 23:53:30.833230 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11715 23:53:30.842929 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11716 23:53:30.846294 Test requirement: is_intel_device(fd)
11717 23:53:30.852724 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11718 23:53:30.856081 Test requirement: is_intel_device(fd)
11719 23:53:30.859598 No KMS driver or no outputs, pipes: 16, outputs: 0
11720 23:53:30.865849 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11721 23:53:30.869341 Using IGT_SRANDOM=1717026810 for randomisation
11722 23:53:30.872634 Opened device: /dev/dri/card0
11723 23:53:30.876270 Starting subtest: master-rmfb
11724 23:53:30.879509 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11725 23:53:30.886135 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11726 23:53:30.889564 Test requirement: is_intel_device(fd)
11727 23:53:30.895754 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11728 23:53:30.902653 Test requirement: is_intel_device(fd)
11729 23:53:30.905863 No KMS driver or no outputs, pipes: 16, outputs: 0
11730 23:53:30.912646 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11731 23:53:30.915942 Using IGT_SRANDOM=1717026810 for randomisation
11732 23:53:30.919283 Opened device: /dev/dri/card0
11733 23:53:30.922843 Starting subtest: addfb25-modifier-no-flag
11734 23:53:30.925907 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11735 23:53:30.936017 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11736 23:53:30.939093 Test requirement: is_intel_device(fd)
11737 23:53:30.945769 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11738 23:53:30.948814 Test requirement: is_intel_device(fd)
11739 23:53:30.952341 No KMS driver or no outputs, pipes: 16, outputs: 0
11740 23:53:30.959036 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11741 23:53:30.962528 Using IGT_SRANDOM=1717026810 for randomisation
11742 23:53:30.965347 Opened device: /dev/dri/card0
11743 23:53:30.969221 Starting subtest: addfb25-bad-modifier
11744 23:53:30.979057 (kms_addfb_basic:441) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11745 23:53:30.998988 (kms_addfb_basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11746 23:53:31.002417 (kms_addfb_basic:441) CRITICAL: error: 0 != -1
11747 23:53:31.002562 Stack trace:
11748 23:53:31.005705 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11749 23:53:31.008867 #1 [<unknown>+0xcfd74358]
11750 23:53:31.011996 #2 [<unknown>+0xcfd75fbc]
11751 23:53:31.015346 #3 [<unknown>+0xcfd7156c]
11752 23:53:31.018711 #4 [__libc_init_first+0x80]
11753 23:53:31.018834 #5 [__libc_start_main+0x98]
11754 23:53:31.022373 #6 [<unknown>+0xcfd715b0]
11755 23:53:31.025364 Subtest addfb25-bad-modifier failed.
11756 23:53:31.029104 **** DEBUG ****
11757 23:53:31.035480 (kms_addfb_basic:441) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11758 23:53:31.045668 (kms_addfb_basic:441) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11759 23:53:31.062031 (kms_addfb_basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11760 23:53:31.068656 (kms_addfb_basic:441) CRITICAL: error: 0 != -1
11761 23:53:31.072154 (kms_addfb_basic:441) igt_core-INFO: Stack trace:
11762 23:53:31.078538 (kms_addfb_basic:441) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11763 23:53:31.085213 (kms_addfb_basic:441) igt_core-INFO: #1 [<unknown>+0xcfd74358]
11764 23:53:31.091780 (kms_addfb_basic:441) igt_core-INFO: #2 [<unknown>+0xcfd75fbc]
11765 23:53:31.094924 (kms_addfb_basic:441) igt_core-INFO: #3 [<unknown>+0xcfd7156c]
11766 23:53:31.101859 (kms_addfb_basic:441) igt_core-INFO: #4 [__libc_init_first+0x80]
11767 23:53:31.108185 (kms_addfb_<14>[ 16.729414] [IGT] kms_addfb_basic: exiting, ret=98
11768 23:53:31.115276 basic:441) igt_core-INFO: #5 [__libc_start_main+0x98]
11769 23:53:31.121888 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11771 23:53:31.125041 (kms_addfb_basic:441) i<8>[ 16.742054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11772 23:53:31.128346 gt_core-INFO: #6 [<unknown>+0xcfd715b0]
11773 23:53:31.128474 **** END ****
11774 23:53:31.131678 [1mSubtest addfb25-bad-modifier: FAIL (0.006s)[0m
11775 23:53:31.145236 Test requirement not met in function igt_require_intel, file ..<14>[ 16.764320] [IGT] kms_addfb_basic: executing
11776 23:53:31.145399 /lib/drmtest.c:880:
11777 23:53:31.148261 Test requirement: is_intel_device(fd)
11778 23:53:31.154817 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11779 23:53:31.161590 Test requirement<14>[ 16.782718] [IGT] kms_addfb_basic: exiting, ret=77
11780 23:53:31.165207 : is_intel_device(fd)
11781 23:53:31.178086 No KMS driver or no outputs, pipes: 16, o<8>[ 16.794532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11782 23:53:31.178257 utputs: 0
11783 23:53:31.178544 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11785 23:53:31.184867 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11786 23:53:31.188015 Using IGT_SRANDOM=1717026811 for randomisation
11787 23:53:31.191649 Opened device: /dev/dri/card0
11788 23:53:31.198282 Test requirement not met in functi<14>[ 16.819673] [IGT] kms_addfb_basic: executing
11789 23:53:31.201574 on igt_require_intel, file ../lib/drmtest.c:880:
11790 23:53:31.204708 Test requirement: is_intel_device(fd)
11791 23:53:31.210992 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11792 23:53:31.217770 Test re<14>[ 16.837367] [IGT] kms_addfb_basic: exiting, ret=77
11793 23:53:31.224709 quirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11794 23:53:31.231427 Tes<8>[ 16.849640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11795 23:53:31.231772 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11797 23:53:31.235266 t requirement: is_intel_device(fd)
11798 23:53:31.241018 No KMS driver or no outputs, pipes: 16, outputs: 0
11799 23:53:31.244201 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11800 23:53:31.251110 Usin<14>[ 16.872299] [IGT] kms_addfb_basic: executing
11801 23:53:31.254637 g IGT_SRANDOM=1717026811 for randomisation
11802 23:53:31.258020 Opened device: /dev/dri/card0
11803 23:53:31.264210 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11804 23:53:31.271205 T<14>[ 16.889895] [IGT] kms_addfb_basic: exiting, ret=77
11805 23:53:31.274156 est requirement: is_intel_device(fd)
11806 23:53:31.284556 [1mSubtest addfb25-x-tiled-legacy: SKIP (<8>[ 16.901932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11807 23:53:31.284893 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11809 23:53:31.287305 0.000s)[0m
11810 23:53:31.294262 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11811 23:53:31.297236 Test requirement: is_intel_device(fd)
11812 23:53:31.300621 No KMS driver or no outputs, pipes: 16, outputs: 0
11813 23:53:31.307264 IGT-<14>[ 16.928266] [IGT] kms_addfb_basic: executing
11814 23:53:31.314229 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11815 23:53:31.317028 Using IGT_SRANDOM=1717026811 for randomisation
11816 23:53:31.320995 Opened device: /dev/dri/card0
11817 23:53:31.323922 T<14>[ 16.946160] [IGT] kms_addfb_basic: exiting, ret=77
11818 23:53:31.337759 est requirement not met in function igt_require_intel, file ../l<8>[ 16.956862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11819 23:53:31.338069 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11821 23:53:31.340376 ib/drmtest.c:880:
11822 23:53:31.343950 Test requirement: is_intel_device(fd)
11823 23:53:31.347219 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11824 23:53:31.357168 Test requirement not met in function<14>[ 16.978412] [IGT] kms_addfb_basic: executing
11825 23:53:31.360632 igt_require_intel, file ../lib/drmtest.c:880:
11826 23:53:31.363653 Test requirement: is_intel_device(fd)
11827 23:53:31.367022 No KMS driver or no outputs, pipes: 16, outputs: 0
11828 23:53:31.377044 IGT-Version: 1.28-ga4<14>[ 16.996047] [IGT] kms_addfb_basic: exiting, ret=77
11829 23:53:31.380571 4ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11830 23:53:31.390348 Using IGT_SRANDOM<8>[ 17.007757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11831 23:53:31.390697 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11833 23:53:31.393368 =1717026811 for randomisation
11834 23:53:31.393485 Opened device: /dev/dri/card0
11835 23:53:31.403678 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11836 23:53:31.406536 Test requireme<14>[ 17.028968] [IGT] kms_addfb_basic: executing
11837 23:53:31.410356 nt: is_intel_device(fd)
11838 23:53:31.416428 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11839 23:53:31.420191 Test requirement: is_intel_device(fd)
11840 23:53:31.427155 [1mSubtest <14>[ 17.047222] [IGT] kms_addfb_basic: exiting, ret=77
11841 23:53:31.430312 basic-x-tiled-legacy: SKIP (0.000s)[0m
11842 23:53:31.440456 No KMS driver or no out<8>[ 17.058710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11843 23:53:31.440797 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11845 23:53:31.443125 puts, pipes: 16, outputs: 0
11846 23:53:31.450173 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11847 23:53:31.453199 Using IGT_SRANDOM=1717026811 for randomisation
11848 23:53:31.460265 Opened device: <14>[ 17.079475] [IGT] kms_addfb_basic: executing
11849 23:53:31.460399 /dev/dri/card0
11850 23:53:31.466581 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11851 23:53:31.469960 Test requirement: is_intel_device(fd)
11852 23:53:31.476419 Test requirement not <14>[ 17.097937] [IGT] kms_addfb_basic: exiting, ret=77
11853 23:53:31.482805 met in function igt_require_intel, file ../lib/drmtest.c:880:
11854 23:53:31.489706 T<8>[ 17.109905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11855 23:53:31.490043 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11857 23:53:31.493277 est requirement: is_intel_device(fd)
11858 23:53:31.499648 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11859 23:53:31.503216 No KMS driver or no outputs, pipes: 16, outputs: 0
11860 23:53:31.509741 IGT-Version:<14>[ 17.131277] [IGT] kms_addfb_basic: executing
11861 23:53:31.513077 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11862 23:53:31.519624 Using IGT_SRANDOM=1717026811 for randomisation
11863 23:53:31.523058 Opened device: /dev/dri/card0
11864 23:53:31.529896 Test requirement not met <14>[ 17.148915] [IGT] kms_addfb_basic: exiting, ret=77
11865 23:53:31.533374 in function igt_require_intel, file ../lib/drmtest.c:880:
11866 23:53:31.539531 Test <8>[ 17.160744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11867 23:53:31.539855 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11869 23:53:31.543018 requirement: is_intel_device(fd)
11870 23:53:31.549894 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11871 23:53:31.556241 Test requirement: is_intel_device(fd)
11872 23:53:31.562751 [1mSubtest tile-pitch-mismatch: SK<14>[ 17.183822] [IGT] kms_addfb_basic: executing
11873 23:53:31.562880 IP (0.000s)[0m
11874 23:53:31.569526 No KMS driver or no outputs, pipes: 16, outputs: 0
11875 23:53:31.572757 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11876 23:53:31.583190 Using IGT_SRANDOM=17170<14>[ 17.201531] [IGT] kms_addfb_basic: exiting, ret=77
11877 23:53:31.583348 26811 for randomisation
11878 23:53:31.586629 Opened device: /dev/dri/card0
11879 23:53:31.592671 Test req<8>[ 17.213495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11880 23:53:31.593021 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11882 23:53:31.599266 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11883 23:53:31.602507 Test requirement: is_intel_device(fd)
11884 23:53:31.613088 Test requirement not met in function igt_requ<14>[ 17.233277] [IGT] kms_addfb_basic: executing
11885 23:53:31.615727 ire_intel, file ../lib/drmtest.c:880:
11886 23:53:31.619282 Test requirement: is_intel_device(fd)
11887 23:53:31.622583 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11888 23:53:31.632530 No KMS driver or no outputs, <14>[ 17.251479] [IGT] kms_addfb_basic: exiting, ret=77
11889 23:53:31.632698 pipes: 16, outputs: 0
11890 23:53:31.645715 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21<8>[ 17.263423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11891 23:53:31.645883 aarch64)
11892 23:53:31.646167 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11894 23:53:31.648936 Using IGT_SRANDOM=1717026811 for randomisation
11895 23:53:31.652279 Opened device: /dev/dri/card0
11896 23:53:31.662352 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 17.285078] [IGT] kms_addfb_basic: executing
11897 23:53:31.665838 mtest.c:880:
11898 23:53:31.669256 Test requirement: is_intel_device(fd)
11899 23:53:31.675486 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11900 23:53:31.682483 Test requirement: is_in<14>[ 17.302591] [IGT] kms_addfb_basic: exiting, ret=77
11901 23:53:31.682639 tel_device(fd)
11902 23:53:31.695572 No KMS driver or no outputs, pipes: 16, outputs:<8>[ 17.314453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11903 23:53:31.695743 0
11904 23:53:31.696026 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11906 23:53:31.699109 [1mSubtest size-max: SKIP (0.000s)[0m
11907 23:53:31.705609 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11908 23:53:31.708941 Using IGT_SRANDOM=1717026811 for randomisation
11909 23:53:31.712541 <14>[ 17.335302] [IGT] kms_addfb_basic: executing
11910 23:53:31.712673
11911 23:53:31.715610 Opened device: /dev/dri/card0
11912 23:53:31.722067 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11913 23:53:31.725650 Test requirement: is_intel_device(fd)
11914 23:53:31.732158 Test <14>[ 17.352838] [IGT] kms_addfb_basic: exiting, ret=77
11915 23:53:31.745213 requirement not met in function igt_require_intel, file ../lib/d<8>[ 17.364795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11916 23:53:31.745383 rmtest.c:880:
11917 23:53:31.745669 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11919 23:53:31.748668 Test requirement: is_intel_device(fd)
11920 23:53:31.755468 No KMS driver or no outputs, pipes: 16, outputs: 0
11921 23:53:31.758791 [1mSubtest too-wide: SKIP (0.000s)[0m
11922 23:53:31.761938 IGT-Version: <14>[ 17.385193] [IGT] kms_addfb_basic: executing
11923 23:53:31.768693 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11924 23:53:31.771938 Using IGT_SRANDOM=1717026811 for randomisation
11925 23:53:31.775296 Opened device: /dev/dri/card0
11926 23:53:31.782137 Test requirement not met i<14>[ 17.402686] [IGT] kms_addfb_basic: exiting, ret=77
11927 23:53:31.788540 n function igt_require_intel, file ../lib/drmtest.c:880:
11928 23:53:31.794966 Test r<8>[ 17.414632] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11929 23:53:31.795307 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11931 23:53:31.798749 equirement: is_intel_device(fd)
11932 23:53:31.805249 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11933 23:53:31.808715 Test requirement: is_intel_device(fd)
11934 23:53:31.818346 No KMS driver or no outputs, pipes: <14>[ 17.439301] [IGT] kms_addfb_basic: executing
11935 23:53:31.818499 16, outputs: 0
11936 23:53:31.821652 [1mSubtest too-high: SKIP (0.000s)[0m
11937 23:53:31.828455 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11938 23:53:31.834991 Using IGT_SRANDOM=1717026811 for ra<14>[ 17.457071] [IGT] kms_addfb_basic: exiting, ret=77
11939 23:53:31.838694 ndomisation
11940 23:53:31.841935 Opened device: /dev/dri/card0
11941 23:53:31.848884 Test requirement not<8>[ 17.468818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11942 23:53:31.849217 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11944 23:53:31.855145 met in function igt_require_intel, file ../lib/drmtest.c:880:
11945 23:53:31.858320 Test requirement: is_intel_device(fd)
11946 23:53:31.868716 Test requirement not met in function igt_require_intel, f<14>[ 17.490041] [IGT] kms_addfb_basic: executing
11947 23:53:31.871642 ile ../lib/drmtest.c:880:
11948 23:53:31.875254 Test requirement: is_intel_device(fd)
11949 23:53:31.878867 No KMS driver or no outputs, pipes: 16, outputs: 0
11950 23:53:31.888399 [1mSubtest bo-too-small: SKIP (0.000s)[0<14>[ 17.507939] [IGT] kms_addfb_basic: exiting, ret=77
11951 23:53:31.888521 m
11952 23:53:31.901699 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aar<8>[ 17.519922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11953 23:53:31.901886 ch64)
11954 23:53:31.902191 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11956 23:53:31.905221 Using IGT_SRANDOM=1717026811 for randomisation
11957 23:53:31.908560 Opened device: /dev/dri/card0
11958 23:53:31.918105 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 17.541676] [IGT] kms_addfb_basic: executing
11959 23:53:31.921542 t.c:880:
11960 23:53:31.925152 Test requirement: is_intel_device(fd)
11961 23:53:31.931480 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11962 23:53:31.938195 Test requirement: is_intel_<14>[ 17.559368] [IGT] kms_addfb_basic: exiting, ret=77
11963 23:53:31.941923 device(fd)
11964 23:53:31.945335 No KMS driver or no outputs, pipes: 16, outputs: 0
11965 23:53:31.951681 <8>[ 17.570893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11966 23:53:31.952017 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11968 23:53:31.954808 [1mSubtest small-bo: SKIP (0.000s)[0m
11969 23:53:31.961500 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11970 23:53:31.968448 Using IGT_SRANDOM=1717026811 for randomisation
11971 23:53:31.971858 Ope<14>[ 17.592966] [IGT] kms_addfb_basic: executing
11972 23:53:31.974772 ned device: /dev/dri/card0
11973 23:53:31.981917 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11974 23:53:31.984852 Test requirement: is_intel_device(fd)
11975 23:53:31.991747 Test requ<14>[ 17.610857] [IGT] kms_addfb_basic: exiting, ret=77
11976 23:53:32.001829 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11978 23:53:32.005213 irement not met in function igt_require_intel, file ../lib/drmte<8>[ 17.622591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11979 23:53:32.005308 st.c:880:
11980 23:53:32.008251 Test <8>[ 17.631258] <LAVA_SIGNAL_TESTSET STOP>
11981 23:53:32.008513 Received signal: <TESTSET> STOP
11982 23:53:32.008613 Closing test_set kms_addfb_basic
11983 23:53:32.012005 requirement: is_intel_device(fd)
11984 23:53:32.014728 No KMS driver or no outputs, pipes: 16, outputs: 0
11985 23:53:32.021772 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11986 23:53:32.028465 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
11987 23:53:32.032147 Received signal: <TESTSET> START kms_atomic
11988 23:53:32.032249 Starting test_set kms_atomic
11989 23:53:32.034944 Using IGT_S<8>[ 17.653549] <LAVA_SIGNAL_TESTSET START kms_atomic>
11990 23:53:32.035033 RANDOM=1717026811 for randomisation
11991 23:53:32.038530 Opened device: /dev/dri/card0
11992 23:53:32.044942 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11993 23:53:32.051851 Test requirement: is_intel_device(fd)
11994 23:53:32.055024 T<14>[ 17.676398] [IGT] kms_atomic: executing
11995 23:53:32.061660 est requirement <14>[ 17.681442] [IGT] kms_atomic: exiting, ret=77
11996 23:53:32.074965 not met in function igt_require_intel, file ../lib/drmtest.c:880<8>[ 17.692553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11997 23:53:32.075100 :
11998 23:53:32.075342 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
12000 23:53:32.078182 Test requirement: is_intel_device(fd)
12001 23:53:32.082026 No KMS driver or no outputs, pipes: 16, outputs: 0
12002 23:53:32.088191 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
12003 23:53:32.091907 IGT-Version<14>[ 17.714112] [IGT] kms_atomic: executing
12004 23:53:32.098135 : 1.28-ga44ebfe <14>[ 17.719244] [IGT] kms_atomic: exiting, ret=77
12005 23:53:32.101367 (aarch64) (Linux: 6.1.91-cip21 aarch64)
12006 23:53:32.111289 Using IGT_SRANDOM=17170<8>[ 17.729970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
12007 23:53:32.111621 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
12009 23:53:32.114983 26811 for randomisation
12010 23:53:32.115083 Opened device: /dev/dri/card0
12011 23:53:32.124815 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12012 23:53:32.128344 Test requirement: is<14>[ 17.751576] [IGT] kms_atomic: executing
12013 23:53:32.134872 _intel_device(fd<14>[ 17.756563] [IGT] kms_atomic: exiting, ret=77
12014 23:53:32.134985 )
12015 23:53:32.151482 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c<8>[ 17.768516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
12016 23:53:32.151647 :880:
12017 23:53:32.151927 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12019 23:53:32.154630 Test requirement: is_intel_device(fd)
12020 23:53:32.161348 No KMS driver or no outputs, pipes: 16, outputs: 0
12021 23:53:32.164497 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
12022 23:53:32.171580 IGT-Version: 1.28-ga44ebfe (aarch64) (<14>[ 17.793508] [IGT] kms_atomic: executing
12023 23:53:32.177660 Linux: 6.1.91-ci<14>[ 17.799494] [IGT] kms_atomic: exiting, ret=77
12024 23:53:32.180683 p21 aarch64)
12025 23:53:32.184050 Using IGT_SRANDOM=1717026811 for randomisation
12026 23:53:32.190761 Op<8>[ 17.810559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
12027 23:53:32.191083 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12029 23:53:32.194481 ened device: /dev/dri/card0
12030 23:53:32.200931 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12031 23:53:32.204507 Test requirement: is_intel_device(fd)
12032 23:53:32.211113 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12033 23:53:32.220766 Test requirement: is_intel_device(fd<14>[ 17.841872] [IGT] kms_atomic: executing
12034 23:53:32.220921 )
12035 23:53:32.224412 No KMS driver<14>[ 17.847094] [IGT] kms_atomic: exiting, ret=77
12036 23:53:32.227490 or no outputs, pipes: 16, outputs: 0
12037 23:53:32.240962 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[<8>[ 17.859560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
12038 23:53:32.241121 0m
12039 23:53:32.241408 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12041 23:53:32.247671 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12042 23:53:32.250862 Using IGT_SRANDOM=1717026811 for randomisation
12043 23:53:32.254491 Opened device: /dev/dri/card0
12044 23:53:32.260760 Test requirement not met <14>[ 17.881703] [IGT] kms_atomic: executing
12045 23:53:32.267241 in function igt_<14>[ 17.887420] [IGT] kms_atomic: exiting, ret=77
12046 23:53:32.270841 require_intel, file ../lib/drmtest.c:880:
12047 23:53:32.280510 Test requirement: is_<8>[ 17.898448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12048 23:53:32.280702 intel_device(fd)
12049 23:53:32.281023 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12051 23:53:32.287254 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12052 23:53:32.290669 Test requirement: is_intel_device(fd)
12053 23:53:32.297535 No KMS driver or no outputs, pipes:<14>[ 17.920364] [IGT] kms_atomic: executing
12054 23:53:32.300868 16, outputs: 0
12055 23:53:32.304390 <14>[ 17.926176] [IGT] kms_atomic: exiting, ret=77
12056 23:53:32.304506
12057 23:53:32.310793 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12058 23:53:32.320875 IGT-Version: 1.28-ga44ebfe (aar<8>[ 17.937569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12059 23:53:32.321186 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12061 23:53:32.324141 ch64) (Linux: 6.1.91-cip21 aarch64)
12062 23:53:32.327093 Using IGT_SRANDOM=1717026812 for randomisation
12063 23:53:32.330685 Opened device: /dev/dri/card0
12064 23:53:32.337186 No KMS driver or no outputs, pipes: 16, outp<14>[ 17.959792] [IGT] kms_atomic: executing
12065 23:53:32.337302 uts: 0
12066 23:53:32.344195 [1mSubt<14>[ 17.965187] [IGT] kms_atomic: exiting, ret=77
12067 23:53:32.347491 est plane-overlay-legacy: SKIP (0.000s)[0m
12068 23:53:32.360938 IGT-Version: 1.28-ga44ebfe (aarch64<8>[ 17.977542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12069 23:53:32.361085 ) (Linux: 6.1.91-cip21 aarch64)
12070 23:53:32.361359 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12072 23:53:32.367285 Using IGT_SRANDOM=1717026812 for randomisation
12073 23:53:32.370739 Opened device: /dev/dri/card0
12074 23:53:32.374375 No KMS driver or no outputs, pipes: 16, outputs: 0
12075 23:53:32.377392 [1mSubtest <14>[ 18.000789] [IGT] kms_atomic: executing
12076 23:53:32.384210 plane-primary-le<14>[ 18.006002] [IGT] kms_atomic: exiting, ret=77
12077 23:53:32.387643 gacy: SKIP (0.000s)[0m
12078 23:53:32.397128 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 18.016915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12079 23:53:32.397440 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12081 23:53:32.400369 inux: 6.1.91-cip21 aarch64)
12082 23:53:32.403938 Using IGT_SRANDOM=1717026812 for randomisation
12083 23:53:32.407343 Opened device: /dev/dri/card0
12084 23:53:32.410607 No KMS driver or no outputs, pipes: 16, outputs: 0
12085 23:53:32.417340 <14>[ 18.038155] [IGT] kms_atomic: executing
12086 23:53:32.420785 [1mSubtest plan<14>[ 18.043386] [IGT] kms_atomic: exiting, ret=77
12087 23:53:32.427375 e-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12088 23:53:32.437374 IGT-Version: <8>[ 18.054438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12089 23:53:32.437686 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12091 23:53:32.440685 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12092 23:53:32.443653 Using IGT_SRANDOM=1717026812 for randomisation
12093 23:53:32.447125 Opened device: /dev/dri/card0
12094 23:53:32.453647 No KMS driver or no output<14>[ 18.076237] [IGT] kms_atomic: executing
12095 23:53:32.460769 s, pipes: 16, ou<14>[ 18.081381] [IGT] kms_atomic: exiting, ret=77
12096 23:53:32.460915 tputs: 0
12097 23:53:32.467035 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12098 23:53:32.474005 IGT-Version: 1.28<8>[ 18.092646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12099 23:53:32.474293 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12101 23:53:32.480384 -ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12102 23:53:32.483960 Using IGT_SRANDOM=1717026812 for randomisation
12103 23:53:32.486959 Opened device: /dev/dri/card0
12104 23:53:32.493669 No KMS driver or no outputs, pipes: 16, output<14>[ 18.115955] [IGT] kms_atomic: executing
12105 23:53:32.493774 s: 0
12106 23:53:32.500563 [1mSubtes<14>[ 18.121764] [IGT] kms_atomic: exiting, ret=77
12107 23:53:32.504001 t test-only: SKIP (0.000s)[0m
12108 23:53:32.513808 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 18.132850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12109 23:53:32.514122 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12111 23:53:32.520322 h64) (Linux: 6.1<8>[ 18.141915] <LAVA_SIGNAL_TESTSET STOP>
12112 23:53:32.520416 .91-cip21 aarch64)
12113 23:53:32.520652 Received signal: <TESTSET> STOP
12114 23:53:32.520716 Closing test_set kms_atomic
12115 23:53:32.523774 Using IGT_SRANDOM=1717026812 for randomisation
12116 23:53:32.527101 Opened device: /dev/dri/card0
12117 23:53:32.533629 No KMS driver or no outputs, pipes: 16, outputs: 0
12118 23:53:32.536686 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12119 23:53:32.543540 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12120 23:53:32.546688 Using IGT_SRANDOM=1717026812 for randomisation
12121 23:53:32.553580 O<8>[ 18.172873] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12122 23:53:32.553870 Received signal: <TESTSET> START kms_flip_event_leak
12123 23:53:32.553951 Starting test_set kms_flip_event_leak
12124 23:53:32.556830 pened device: /dev/dri/card0
12125 23:53:32.560199 No KMS driver or no outputs, pipes: 16, outputs: 0
12126 23:53:32.563177 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12127 23:53:32.570097 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12128 23:53:32.573547 Using IGT_SRANDOM=1717026812 for randomisation
12129 23:53:32.576405 Opened device: /dev/dri/card0
12130 23:53:32.583262 No KMS driver or no outputs, pipes: 16, outputs: 0
12131 23:53:32.587055 [<14>[ 18.208524] [IGT] kms_flip_event_leak: executing
12132 23:53:32.593435 1mSubtest plane-<14>[ 18.214623] [IGT] kms_flip_event_leak: exiting, ret=77
12133 23:53:32.597003 invalid-params-fence: SKIP (0.000s)[0m
12134 23:53:32.606503 IGT-Version: 1.28-ga44e<8>[ 18.226220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12135 23:53:32.606828 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12137 23:53:32.613371 bfe (aarch64) (Linux: 6.1.91-cip<8>[ 18.234496] <LAVA_SIGNAL_TESTSET STOP>
12138 23:53:32.613474 21 aarch64)
12139 23:53:32.613713 Received signal: <TESTSET> STOP
12140 23:53:32.613782 Closing test_set kms_flip_event_leak
12141 23:53:32.616347 Using IGT_SRANDOM=1717026812 for randomisation
12142 23:53:32.619749 Opened device: /dev/dri/card0
12143 23:53:32.626700 No KMS driver or no outputs, pipes: 16, outputs: 0
12144 23:53:32.630265 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12145 23:53:32.636689 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12146 23:53:32.639966 Using IGT_SRANDOM=1717026812 for randomisation
12147 23:53:32.646717 Opened d<8>[ 18.266448] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12148 23:53:32.646829 evice: /dev/dri/card0
12149 23:53:32.647114 Received signal: <TESTSET> START kms_prop_blob
12150 23:53:32.647187 Starting test_set kms_prop_blob
12151 23:53:32.653275 No KMS driver or no outputs, pipes: 16, outputs: 0
12152 23:53:32.656294 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12153 23:53:32.663353 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12154 23:53:32.666601 Using IGT_SRANDOM=1717026812 for randomisation
12155 23:53:32.669693 Opened device: /dev/dri/card0
12156 23:53:32.673175 No KMS driver or no outputs, pipes: 16, outputs: 0
12157 23:53:32.679787 [1m<14>[ 18.300458] [IGT] kms_prop_blob: executing
12158 23:53:32.686496 Subtest atomic-i<14>[ 18.306859] [IGT] kms_prop_blob: starting subtest basic
12159 23:53:32.692879 nvalid-params: S<14>[ 18.313332] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12160 23:53:32.699934 KIP (0.000s)[0m<14>[ 18.321147] [IGT] kms_prop_blob: exiting, ret=0
12161 23:53:32.700048
12162 23:53:32.706406 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12163 23:53:32.713205 Using IGT_<8>[ 18.334214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12164 23:53:32.713678 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12166 23:53:32.715948 SRANDOM=1717026812 for randomisation
12167 23:53:32.719485 Opened device: /dev/dri/card0
12168 23:53:32.722744 No KMS driver or no outputs, pipes: 16, outputs: 0
12169 23:53:32.729504 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
12170 23:53:32.733114 IGT<14>[ 18.354836] [IGT] kms_prop_blob: executing
12171 23:53:32.742668 -Version: 1.28-g<14>[ 18.360799] [IGT] kms_prop_blob: starting subtest blob-prop-core
12172 23:53:32.749804 a44ebfe (aarch64<14>[ 18.368316] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12173 23:53:32.756397 ) (Linux: 6.1.91<14>[ 18.376893] [IGT] kms_prop_blob: exiting, ret=0
12174 23:53:32.759690 -cip21 aarch64)
12175 23:53:32.762963 Using IGT_SRANDOM=1717026812 for randomisation
12176 23:53:32.769272 <8>[ 18.388602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12177 23:53:32.769389
12178 23:53:32.769658 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12180 23:53:32.772848 Opened device: /dev/dri/card0
12181 23:53:32.775892 No KMS driver or no outputs, pipes: 16, outputs: 0
12182 23:53:32.779295 [1mSubtest basic: SKIP (0.000s)[0m
12183 23:53:32.786208 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12184 23:53:32.789269 Us<14>[ 18.411227] [IGT] kms_prop_blob: executing
12185 23:53:32.798926 ing IGT_SRANDOM=<14>[ 18.417447] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12186 23:53:32.805965 1717026812 for r<14>[ 18.425301] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12187 23:53:32.809177 andomisation
12188 23:53:32.812631 Op<14>[ 18.434177] [IGT] kms_prop_blob: exiting, ret=0
12189 23:53:32.816030 ened device: /dev/dri/card0
12190 23:53:32.819693 Starting subtest: basic
12191 23:53:32.825492 [1mSubtes<8>[ 18.445640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12192 23:53:32.825804 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12194 23:53:32.828957 t basic: SUCCESS (0.000s)[0m
12195 23:53:32.836083 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12196 23:53:32.839045 Using IGT_SRANDOM=1717026812 for randomisation
12197 23:53:32.845630 Opened device<14>[ 18.467296] [IGT] kms_prop_blob: executing
12198 23:53:32.852858 : /dev/dri/card0<14>[ 18.472212] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12199 23:53:32.853045
12200 23:53:32.862164 Starting subte<14>[ 18.480163] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12201 23:53:32.869013 st: blob-prop-co<14>[ 18.489000] [IGT] kms_prop_blob: exiting, ret=0
12202 23:53:32.869178 re
12203 23:53:32.872115 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12204 23:53:32.882180 IGT-Versio<8>[ 18.500457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12205 23:53:32.882527 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12207 23:53:32.885175 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12208 23:53:32.891850 Using IGT_SRANDOM=1717026812 for randomisation
12209 23:53:32.891993 Opened device: /dev/dri/card0
12210 23:53:32.898574 Starting subtest: blob-<14>[ 18.521915] [IGT] kms_prop_blob: executing
12211 23:53:32.901772 prop-validate
12212 23:53:32.908319 <14>[ 18.527151] [IGT] kms_prop_blob: starting subtest blob-multiple
12213 23:53:32.914836 [1mSubtest blob-<14>[ 18.534545] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12214 23:53:32.921658 prop-validate: S<14>[ 18.542950] [IGT] kms_prop_blob: exiting, ret=0
12215 23:53:32.925158 UCCESS (0.000s)[0m
12216 23:53:32.935037 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<8>[ 18.554395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12217 23:53:32.935391 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12219 23:53:32.938070 : 6.1.91-cip21 aarch64)
12220 23:53:32.941616 Using IGT_SRANDOM=1717026812 for randomisation
12221 23:53:32.945087 Opened device: /dev/dri/card0
12222 23:53:32.948348 Starting subtest: blob-prop-lifetime
12223 23:53:32.955386 [1mSubtest blob-p<14>[ 18.574468] [IGT] kms_prop_blob: executing
12224 23:53:32.961716 rop-lifetime: SU<14>[ 18.580529] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12225 23:53:32.971030 CCESS (0.000s)[<14>[ 18.588570] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12226 23:53:32.971195 0m
12227 23:53:32.978277 IGT-Version:<14>[ 18.597668] [IGT] kms_prop_blob: exiting, ret=0
12228 23:53:32.981433 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12229 23:53:32.991311 Using IG<8>[ 18.609028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12230 23:53:32.991621 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12232 23:53:32.994257 T_SRANDOM=1717026812 for randomisation
12233 23:53:32.997861 Opened device: /dev/dri/card0
12234 23:53:33.000872 Starting subtest: blob-multiple
12235 23:53:33.004228 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12236 23:53:33.011099 IGT-Version: 1.28-ga44e<14>[ 18.631124] [IGT] kms_prop_blob: executing
12237 23:53:33.017484 bfe (aarch64) (L<14>[ 18.637217] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12238 23:53:33.027415 inux: 6.1.91-cip<14>[ 18.644922] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12239 23:53:33.027581 21 aarch64)
12240 23:53:33.033891 Usi<14>[ 18.653664] [IGT] kms_prop_blob: exiting, ret=0
12241 23:53:33.037440 ng IGT_SRANDOM=1717026812 for randomisation
12242 23:53:33.047826 Opened device: /dev<8>[ 18.664983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12243 23:53:33.047989 /dri/card0
12244 23:53:33.048275 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12246 23:53:33.050961 Starting subtest: invalid-get-prop-any
12247 23:53:33.053954 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12248 23:53:33.061366 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12249 23:53:33.067237 <14>[ 18.688052] [IGT] kms_prop_blob: executing
12250 23:53:33.073659 Using IGT_SRANDO<14>[ 18.692934] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12251 23:53:33.083756 M=1717026813 for<14>[ 18.700949] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12252 23:53:33.083930 randomisation
12253 23:53:33.090920 <14>[ 18.710060] [IGT] kms_prop_blob: exiting, ret=0
12254 23:53:33.093926 Opened device: /dev/dri/card0
12255 23:53:33.103818 Starting subtest: invalid-get-pro<8>[ 18.721671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12256 23:53:33.103979 p
12257 23:53:33.104263 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12259 23:53:33.107180 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12260 23:53:33.113729 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12261 23:53:33.120437 Using IGT_SRANDOM=1717026813 for rand<14>[ 18.743147] [IGT] kms_prop_blob: executing
12262 23:53:33.123676 omisation
12263 23:53:33.130010 Opene<14>[ 18.748211] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12264 23:53:33.136930 d device: /dev/d<14>[ 18.755926] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12265 23:53:33.140033 ri/card0
12266 23:53:33.143382 Starti<14>[ 18.764668] [IGT] kms_prop_blob: exiting, ret=0
12267 23:53:33.146942 ng subtest: invalid-set-prop-any
12268 23:53:33.156868 [1mSubtest invalid-set-prop-a<8>[ 18.776029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12269 23:53:33.157232 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12271 23:53:33.163485 ny: SUCCESS (0.0<8>[ 18.784981] <LAVA_SIGNAL_TESTSET STOP>
12272 23:53:33.163635 00s)[0m
12273 23:53:33.163914 Received signal: <TESTSET> STOP
12274 23:53:33.164022 Closing test_set kms_prop_blob
12275 23:53:33.170402 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12276 23:53:33.173470 Using IGT_SRANDOM=1717026813 for randomisation
12277 23:53:33.176573 Opened device: /dev/dri/card0
12278 23:53:33.179970 Starting subtest: invalid-set-prop
12279 23:53:33.182922 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12280 23:53:33.194424 <8>[ 18.816247] <LAVA_SIGNAL_TESTSET START kms_setmode>
12281 23:53:33.194766 Received signal: <TESTSET> START kms_setmode
12282 23:53:33.194877 Starting test_set kms_setmode
12283 23:53:33.228432 <14>[ 18.850283] [IGT] kms_setmode: executing
12284 23:53:33.235294 IGT-Version: 1.2<14>[ 18.855353] [IGT] kms_setmode: starting subtest basic
12285 23:53:33.241986 8-ga44ebfe (aarc<14>[ 18.861587] [IGT] kms_setmode: finished subtest basic, SKIP
12286 23:53:33.248524 h64) (Linux: 6.1<14>[ 18.868946] [IGT] kms_setmode: exiting, ret=77
12287 23:53:33.248646 .91-cip21 aarch64)
12288 23:53:33.255141 Using IGT_SRANDOM=1717026813 for randomisation
12289 23:53:33.261592 Opened devic<8>[ 18.881161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12290 23:53:33.261679 e: /dev/dri/card0
12291 23:53:33.261918 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12293 23:53:33.264914 Starting subtest: basic
12294 23:53:33.268020 No dynamic tests executed.
12295 23:53:33.271471 [1mSubtest basic: SKIP (0.000s)[0m
12296 23:53:33.280498 <14>[ 18.902512] [IGT] kms_setmode: executing
12297 23:53:33.287117 IGT-Version: 1.2<14>[ 18.907353] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12298 23:53:33.297653 8-ga44ebfe (aarc<14>[ 18.915548] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12299 23:53:33.304345 h64) (Linux: 6.1<14>[ 18.924481] [IGT] kms_setmode: exiting, ret=77
12300 23:53:33.304460 .91-cip21 aarch64)
12301 23:53:33.317417 Using IGT_SRANDOM=1717026813 for randomisati<8>[ 18.935050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12302 23:53:33.317505 on
12303 23:53:33.317742 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12305 23:53:33.320496 Opened device: /dev/dri/card0
12306 23:53:33.323885 Starting subtest: basic-clone-single-crtc
12307 23:53:33.327170 No dynamic tests executed.
12308 23:53:33.333572 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m<14>[ 18.957395] [IGT] kms_setmode: executing
12309 23:53:33.337242
12310 23:53:33.343577 IGT-Version: 1.2<14>[ 18.962731] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12311 23:53:33.353907 8-ga44ebfe (aarc<14>[ 18.971078] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12312 23:53:33.360463 h64) (Linux: 6.1<14>[ 18.980110] [IGT] kms_setmode: exiting, ret=77
12313 23:53:33.360605 .91-cip21 aarch64)
12314 23:53:33.373957 Using IGT_SRANDOM=1717026813 for randomisati<8>[ 18.990504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12315 23:53:33.374054 on
12316 23:53:33.374294 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12318 23:53:33.376895 Opened device: /dev/dri/card0
12319 23:53:33.380417 Starting subtest: invalid-clone-single-crtc
12320 23:53:33.383886 No dynamic tests executed.
12321 23:53:33.390602 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)<14>[ 19.012639] [IGT] kms_setmode: executing
12322 23:53:33.390720 [0m
12323 23:53:33.400779 <14>[ 19.018533] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12324 23:53:33.407331 IGT-Version: 1.2<14>[ 19.026183] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12325 23:53:33.413834 8-ga44ebfe (aarc<14>[ 19.035523] [IGT] kms_setmode: exiting, ret=77
12326 23:53:33.417328 h64) (Linux: 6.1.91-cip21 aarch64)
12327 23:53:33.427057 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12329 23:53:33.430502 Using IGT_SRANDOM=1717026813<8>[ 19.046710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12330 23:53:33.430584 for randomisation
12331 23:53:33.433787 Opened device: /dev/dri/card0
12332 23:53:33.437368 Starting subtest: invalid-clone-exclusive-crtc
12333 23:53:33.440349 No dynamic tests executed.
12334 23:53:33.443804 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12335 23:53:33.450360 <14>[ 19.072041] [IGT] kms_setmode: executing
12336 23:53:33.457105 IGT-Version: 1.2<14>[ 19.076774] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12337 23:53:33.467428 8-ga44ebfe (aarc<14>[ 19.084667] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12338 23:53:33.473833 h64) (Linux: 6.1<14>[ 19.093424] [IGT] kms_setmode: exiting, ret=77
12339 23:53:33.473964 .91-cip21 aarch64)
12340 23:53:33.486807 Using IGT_SRANDOM=1717026813 for randomisati<8>[ 19.104586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12341 23:53:33.486950 on
12342 23:53:33.487226 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12344 23:53:33.490101 Opened device: /dev/dri/card0
12345 23:53:33.493647 Starting subtest: clone-exclusive-crtc
12346 23:53:33.493759 No dynamic tests executed.
12347 23:53:33.500103 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12348 23:53:33.503587 <14>[ 19.126005] [IGT] kms_setmode: executing
12349 23:53:33.513562 IGT-Version: 1.2<14>[ 19.131091] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12350 23:53:33.523584 8-ga44ebfe (aarc<14>[ 19.140061] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12351 23:53:33.530154 h64) (Linux: 6.1<14>[ 19.149949] [IGT] kms_setmode: exiting, ret=77
12352 23:53:33.530318 .91-cip21 aarch64)
12353 23:53:33.543735 Using IGT_SRANDOM=1717026813 for randomisati<8>[ 19.161239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12354 23:53:33.543860 on
12355 23:53:33.544138 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12357 23:53:33.549996 Opened device: /dev/dri/card<8>[ 19.171970] <LAVA_SIGNAL_TESTSET STOP>
12358 23:53:33.550109 0
12359 23:53:33.550380 Received signal: <TESTSET> STOP
12360 23:53:33.550479 Closing test_set kms_setmode
12361 23:53:33.557092 Starting subtest: invalid-clone-single-crtc-stealing
12362 23:53:33.557203 No dynamic tests executed.
12363 23:53:33.563652 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12364 23:53:33.583142 <8>[ 19.204902] <LAVA_SIGNAL_TESTSET START kms_vblank>
12365 23:53:33.583470 Received signal: <TESTSET> START kms_vblank
12366 23:53:33.583576 Starting test_set kms_vblank
12367 23:53:33.616589 <14>[ 19.238561] [IGT] kms_vblank: executing
12368 23:53:33.623171 IGT-Version: 1.2<14>[ 19.243640] [IGT] kms_vblank: exiting, ret=77
12369 23:53:33.626825 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12370 23:53:33.636685 Using IGT_SRANDOM=1717026813 for randomisati<8>[ 19.256612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12371 23:53:33.636803 on
12372 23:53:33.637077 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12374 23:53:33.639727 Opened device: /dev/dri/card0
12375 23:53:33.643205 No KMS driver or no outputs, pipes: 16, outputs: 0
12376 23:53:33.649722 [1mSubtest invalid: SKIP (0.000s)[0m
12377 23:53:33.660149 <14>[ 19.281994] [IGT] kms_vblank: executing
12378 23:53:33.666770 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 19.288064] [IGT] kms_vblank: exiting, ret=77
12379 23:53:33.670566 h64) (Linux: 6.1.91-cip21 aarch64)
12380 23:53:33.675104 Using IGT_SRANDOM=1717026813 for randomisation
12381 23:53:33.676735 Opened device: /dev/dri/card0
12382 23:53:33.683197 No KMS driver<8>[ 19.304672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12383 23:53:33.683542 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12385 23:53:33.686568 or no outputs, pipes: 16, outputs: 0
12386 23:53:33.693355 [1mSubtest crtc-id: SKIP (0.000s)[0m
12387 23:53:33.714159 <14>[ 19.336303] [IGT] kms_vblank: executing
12388 23:53:33.721910 IGT-Version: 1.2<14>[ 19.341248] [IGT] kms_vblank: exiting, ret=77
12389 23:53:33.724289 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12390 23:53:33.734573 Using IGT_SRANDOM=1717026813 for randomisati<8>[ 19.354032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12391 23:53:33.734673 on
12392 23:53:33.734929 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12394 23:53:33.737474 Opened device: /dev/dri/card0
12395 23:53:33.744157 No KMS driver or no outputs, pipes: 16, outputs: 0
12396 23:53:33.747483 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12397 23:53:33.755145 <14>[ 19.376851] [IGT] kms_vblank: executing
12398 23:53:33.761498 IGT-Version: 1.2<14>[ 19.381481] [IGT] kms_vblank: exiting, ret=77
12399 23:53:33.765078 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12400 23:53:33.774909 Using IGT_SRANDOM=1717026813<8>[ 19.393053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12401 23:53:33.775045 for randomisation
12402 23:53:33.775327 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12404 23:53:33.777879 Opened device: /dev/dri/card0
12405 23:53:33.785114 No KMS driver or no outputs, pipes: 16, outputs: 0
12406 23:53:33.787899 [1mSubtest query-idle: SKIP (0.000s)[0m
12407 23:53:33.791482 <14>[ 19.415222] [IGT] kms_vblank: executing
12408 23:53:33.798001 IGT-Version: 1.2<14>[ 19.419857] [IGT] kms_vblank: exiting, ret=77
12409 23:53:33.804581 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12410 23:53:33.811222 Using IGT_SR<8>[ 19.430918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12411 23:53:33.811531 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12413 23:53:33.814453 ANDOM=1717026813 for randomisation
12414 23:53:33.818039 Opened device: /dev/dri/card0
12415 23:53:33.821160 No KMS driver or no outputs, pipes: 16, outputs: 0
12416 23:53:33.831386 [1mSubtest query-idle-hang: SKIP (0.000s<14>[ 19.451721] [IGT] kms_vblank: executing
12417 23:53:33.831508 )[0m
12418 23:53:33.834845 <14>[ 19.457112] [IGT] kms_vblank: exiting, ret=77
12419 23:53:33.841186 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12420 23:53:33.847737 Using IGT_SR<8>[ 19.468219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12421 23:53:33.848011 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12423 23:53:33.851179 ANDOM=1717026813 for randomisation
12424 23:53:33.854830 Opened device: /dev/dri/card0
12425 23:53:33.858212 No KMS driver or no outputs, pipes: 16, outputs: 0
12426 23:53:33.867696 [1mSubtest query-forked: SKIP (0.000s)[<14>[ 19.489681] [IGT] kms_vblank: executing
12427 23:53:33.867830 0m
12428 23:53:33.874788 IGT-Version: 1.2<14>[ 19.494492] [IGT] kms_vblank: exiting, ret=77
12429 23:53:33.878069 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12430 23:53:33.881094 Using IGT_SRANDOM=1717026813 for randomisation
12431 23:53:33.891130 Opened devic<8>[ 19.509186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12432 23:53:33.891264 e: /dev/dri/card0
12433 23:53:33.891536 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12435 23:53:33.898146 No KMS driver or no outputs, pipes: 16, outputs: 0
12436 23:53:33.901237 [1mSubtest query-forked-hang: SKIP (0.000s)[0m
12437 23:53:33.918923 <14>[ 19.541133] [IGT] kms_vblank: executing
12438 23:53:33.925751 IGT-Version: 1.2<14>[ 19.546057] [IGT] kms_vblank: exiting, ret=77
12439 23:53:33.929233 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12440 23:53:33.939002 Using IGT_SRANDOM=1717026813<8>[ 19.557678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12441 23:53:33.939142 for randomisation
12442 23:53:33.939420 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12444 23:53:33.942344 Opened device: /dev/dri/card0
12445 23:53:33.948965 No KMS driver or no outputs, pipes: 16, outputs: 0
12446 23:53:33.952267 [1mSubtest query-busy: SKIP (0.000s)[0m
12447 23:53:33.966671 <14>[ 19.588566] [IGT] kms_vblank: executing
12448 23:53:33.973213 IGT-Version: 1.2<14>[ 19.593499] [IGT] kms_vblank: exiting, ret=77
12449 23:53:33.976878 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12450 23:53:33.986344 Using IGT_SRANDOM=1717026813<8>[ 19.605807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12451 23:53:33.986674 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12453 23:53:33.989906 for randomisation
12454 23:53:33.989989 Opened device: /dev/dri/card0
12455 23:53:33.996454 No KMS driver or no outputs, pipes: 16, outputs: 0
12456 23:53:33.999831 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12457 23:53:34.007049 <14>[ 19.629008] [IGT] kms_vblank: executing
12458 23:53:34.013560 IGT-Version: 1.2<14>[ 19.633764] [IGT] kms_vblank: exiting, ret=77
12459 23:53:34.016959 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12460 23:53:34.026907 Using IGT_SRANDOM=1717026814<8>[ 19.645864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12461 23:53:34.027198 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12463 23:53:34.030365 for randomisation
12464 23:53:34.030450 Opened device: /dev/dri/card0
12465 23:53:34.037091 No KMS driver or no outputs, pipes: 16, outputs: 0
12466 23:53:34.040105 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12467 23:53:34.054849 <14>[ 19.676992] [IGT] kms_vblank: executing
12468 23:53:34.061656 IGT-Version: 1.2<14>[ 19.681984] [IGT] kms_vblank: exiting, ret=77
12469 23:53:34.064955 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12470 23:53:34.074765 Using IGT_SRANDOM=1717026814<8>[ 19.693640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12471 23:53:34.075068 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12473 23:53:34.078423 for randomisation
12474 23:53:34.078512 Opened device: /dev/dri/card0
12475 23:53:34.084831 No KMS driver or no outputs, pipes: 16, outputs: 0
12476 23:53:34.088807 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[0m
12477 23:53:34.103380 <14>[ 19.725486] [IGT] kms_vblank: executing
12478 23:53:34.110391 IGT-Version: 1.2<14>[ 19.730493] [IGT] kms_vblank: exiting, ret=77
12479 23:53:34.113861 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12480 23:53:34.123925 Using IGT_SRANDOM=1717026814<8>[ 19.741802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12481 23:53:34.124046 for randomisation
12482 23:53:34.124296 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12484 23:53:34.126767 Opened device: /dev/dri/card0
12485 23:53:34.130239 No KMS driver or no outputs, pipes: 16, outputs: 0
12486 23:53:34.137281 [1mSubtest wait-idle: SKIP (0.000s)[0m
12487 23:53:34.140164 <14>[ 19.764063] [IGT] kms_vblank: executing
12488 23:53:34.146627 IGT-Version: 1.2<14>[ 19.768696] [IGT] kms_vblank: exiting, ret=77
12489 23:53:34.153352 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12490 23:53:34.163728 Using IGT_SRANDOM=1717026814 for randomisati<8>[ 19.781856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12491 23:53:34.163902 on
12492 23:53:34.164185 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12494 23:53:34.166609 Opened device: /dev/dri/card0
12495 23:53:34.169984 No KMS driver or no outputs, pipes: 16, outputs: 0
12496 23:53:34.173569 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12497 23:53:34.181959 <14>[ 19.803868] [IGT] kms_vblank: executing
12498 23:53:34.188335 IGT-Version: 1.2<14>[ 19.808487] [IGT] kms_vblank: exiting, ret=77
12499 23:53:34.191848 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12500 23:53:34.201745 Using IGT_SRANDOM=1717026814 for randomisati<8>[ 19.821790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12501 23:53:34.201900 on
12502 23:53:34.202176 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12504 23:53:34.205002 Opened device: /dev/dri/card0
12505 23:53:34.211865 No KMS driver or no outputs, pipes: 16, outputs: 0
12506 23:53:34.215144 [1mSubtest wait-forked: SKIP (0.000s)[0m
12507 23:53:34.218676 <14>[ 19.842738] [IGT] kms_vblank: executing
12508 23:53:34.225075 IGT-Version: 1.2<14>[ 19.847400] [IGT] kms_vblank: exiting, ret=77
12509 23:53:34.232123 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12510 23:53:34.241802 Using IGT_SRANDOM=1717026814 for randomisati<8>[ 19.860705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12511 23:53:34.241956 on
12512 23:53:34.242217 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12514 23:53:34.244792 Opened device: /dev/dri/card0
12515 23:53:34.248400 No KMS driver or no outputs, pipes: 16, outputs: 0
12516 23:53:34.255028 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12517 23:53:34.269870 <14>[ 19.891738] [IGT] kms_vblank: executing
12518 23:53:34.276574 IGT-Version: 1.2<14>[ 19.896759] [IGT] kms_vblank: exiting, ret=77
12519 23:53:34.279925 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12520 23:53:34.289517 Using IGT_SRANDOM=1717026814<8>[ 19.908339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12521 23:53:34.289634 for randomisation
12522 23:53:34.289883 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12524 23:53:34.293214 Opened device: /dev/dri/card0
12525 23:53:34.299691 No KMS driver or no outputs, pipes: 16, outputs: 0
12526 23:53:34.303148 [1mSubtest wait-busy: SKIP (0.000s)[0m
12527 23:53:34.317019 <14>[ 19.939034] [IGT] kms_vblank: executing
12528 23:53:34.323842 IGT-Version: 1.2<14>[ 19.944034] [IGT] kms_vblank: exiting, ret=77
12529 23:53:34.327181 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12530 23:53:34.337111 Using IGT_SRANDOM=1717026814 for randomisati<8>[ 19.957142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12531 23:53:34.337224 on
12532 23:53:34.337475 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12534 23:53:34.340513 Opened device: /dev/dri/card0
12535 23:53:34.347227 No KMS driver or no outputs, pipes: 16, outputs: 0
12536 23:53:34.349995 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12537 23:53:34.358101 <14>[ 19.980047] [IGT] kms_vblank: executing
12538 23:53:34.365163 IGT-Version: 1.2<14>[ 19.984699] [IGT] kms_vblank: exiting, ret=77
12539 23:53:34.368224 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12540 23:53:34.378447 Using IGT_SRANDOM=1717026814 for randomisati<8>[ 19.997966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12541 23:53:34.378564 on
12542 23:53:34.378809 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12544 23:53:34.381457 Opened device: /dev/dri/card0
12545 23:53:34.388640 No KMS driver or no outputs, pipes: 16, outputs: 0
12546 23:53:34.391314 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12547 23:53:34.398200 <14>[ 20.020300] [IGT] kms_vblank: executing
12548 23:53:34.404773 IGT-Version: 1.2<14>[ 20.024931] [IGT] kms_vblank: exiting, ret=77
12549 23:53:34.408168 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12550 23:53:34.418186 Using IGT_SRANDOM=1717026814<8>[ 20.037080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12551 23:53:34.418480 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12553 23:53:34.421527 for randomisation
12554 23:53:34.421612 Opened device: /dev/dri/card0
12555 23:53:34.428340 No KMS driver or no outputs, pipes: 16, outputs: 0
12556 23:53:34.431246 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12557 23:53:34.446432 <14>[ 20.068632] [IGT] kms_vblank: executing
12558 23:53:34.453185 IGT-Version: 1.2<14>[ 20.073584] [IGT] kms_vblank: exiting, ret=77
12559 23:53:34.456963 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12560 23:53:34.466236 Using IGT_SRANDOM=1717026814<8>[ 20.085606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12561 23:53:34.466531 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12563 23:53:34.470107 for randomisation
12564 23:53:34.470199 Opened device: /dev/dri/card0
12565 23:53:34.476543 No KMS driver or no outputs, pipes: 16, outputs: 0
12566 23:53:34.479596 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12567 23:53:34.486537 <14>[ 20.108355] [IGT] kms_vblank: executing
12568 23:53:34.493329 IGT-Version: 1.2<14>[ 20.112998] [IGT] kms_vblank: exiting, ret=77
12569 23:53:34.496337 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12570 23:53:34.506355 Using IGT_SRANDOM=1717026814<8>[ 20.125601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12571 23:53:34.506646 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12573 23:53:34.509654 for randomisation
12574 23:53:34.512589 Opened device: /dev/dri/card0
12575 23:53:34.516116 No KMS driver or no outputs, pipes: 16, outputs: 0
12576 23:53:34.519762 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12577 23:53:34.526273 <14>[ 20.148060] [IGT] kms_vblank: executing
12578 23:53:34.532637 IGT-Version: 1.2<14>[ 20.152693] [IGT] kms_vblank: exiting, ret=77
12579 23:53:34.535722 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12580 23:53:34.545781 Using IGT_SRANDOM=1717026814<8>[ 20.164036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12581 23:53:34.546086 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12583 23:53:34.549329 for randomisation
12584 23:53:34.552575 Opened device: /dev/dri/card0
12585 23:53:34.556038 No KMS driver or no outputs, pipes: 16, outputs: 0
12586 23:53:34.559022 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12587 23:53:34.575000 <14>[ 20.196468] [IGT] kms_vblank: executing
12588 23:53:34.580881 IGT-Version: 1.2<14>[ 20.201413] [IGT] kms_vblank: exiting, ret=77
12589 23:53:34.584448 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12590 23:53:34.594699 Using IGT_SRANDOM=1717026814<8>[ 20.212718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12591 23:53:34.595023 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12593 23:53:34.597720 for randomisation
12594 23:53:34.601426 Opened device: /dev/dri/card0
12595 23:53:34.604311 No KMS driver or no outputs, pipes: 16, outputs: 0
12596 23:53:34.611268 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12597 23:53:34.623053 <14>[ 20.245195] [IGT] kms_vblank: executing
12598 23:53:34.630113 IGT-Version: 1.2<14>[ 20.250174] [IGT] kms_vblank: exiting, ret=77
12599 23:53:34.633006 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12600 23:53:34.636617 Using IGT_SRANDOM=1717026814 for randomisation
12601 23:53:34.646495 Opened devic<8>[ 20.265129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12602 23:53:34.646786 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12604 23:53:34.649748 e: /dev/dri/card0
12605 23:53:34.653086 No KMS driver or no outputs, pipes: 16, outputs: 0
12606 23:53:34.656238 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12607 23:53:34.665997 <14>[ 20.287988] [IGT] kms_vblank: executing
12608 23:53:34.672915 IGT-Version: 1.2<14>[ 20.292614] [IGT] kms_vblank: exiting, ret=77
12609 23:53:34.676205 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12610 23:53:34.685809 Using IGT_SRANDOM=1717026814 for randomisati<8>[ 20.305905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12611 23:53:34.686096 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12613 23:53:34.689146 on
12614 23:53:34.689227 Opened device: /dev/dri/card0
12615 23:53:34.696396 No KMS driver or no outputs, pipes: 16, outputs: 0
12616 23:53:34.699304 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12617 23:53:34.715597 <14>[ 20.337947] [IGT] kms_vblank: executing
12618 23:53:34.722520 IGT-Version: 1.2<14>[ 20.342984] [IGT] kms_vblank: exiting, ret=77
12619 23:53:34.725898 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12620 23:53:34.735936 Using IGT_SRANDOM=1717026814<8>[ 20.354327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12621 23:53:34.736261 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12623 23:53:34.739351 for randomisation
12624 23:53:34.742485 Opened device: /dev/dri/card0
12625 23:53:34.745865 No KMS driver or no outputs, pipes: 16, outputs: 0
12626 23:53:34.752344 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12627 23:53:34.755866 <14>[ 20.378014] [IGT] kms_vblank: executing
12628 23:53:34.762309 IGT-Version: 1.2<14>[ 20.382861] [IGT] kms_vblank: exiting, ret=77
12629 23:53:34.765717 8-ga44ebfe (aarch64) (Linux: 6.1.91-cip21 aarch64)
12630 23:53:34.775455 Using IGT_SRANDOM=1717026814<8>[ 20.394968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12631 23:53:34.775781 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12633 23:53:34.778737 for randomisation
12634 23:53:34.782329 Opened devic<8>[ 20.405468] <LAVA_SIGNAL_TESTSET STOP>
12635 23:53:34.782614 Received signal: <TESTSET> STOP
12636 23:53:34.782687 Closing test_set kms_vblank
12637 23:53:34.791951 e: /dev/dri/card<8>[ 20.411688] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14084325_1.5.2.3.1>
12638 23:53:34.792087 0
12639 23:53:34.792351 Received signal: <ENDRUN> 0_igt-kms-mediatek 14084325_1.5.2.3.1
12640 23:53:34.792432 Ending use of test pattern.
12641 23:53:34.792494 Ending test lava.0_igt-kms-mediatek (14084325_1.5.2.3.1), duration 6.55
12643 23:53:34.795470 No KMS driver or no outputs, pipes: 16, outputs: 0
12644 23:53:34.802244 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12645 23:53:34.802377 + set +x
12646 23:53:34.805823 <LAVA_TEST_RUNNER EXIT>
12647 23:53:34.806110 ok: lava_test_shell seems to have completed
12648 23:53:34.807644 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12649 23:53:34.807795 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12650 23:53:34.807886 end: 3 lava-test-retry (duration 00:00:07) [common]
12651 23:53:34.807973 start: 4 finalize (timeout 00:07:00) [common]
12652 23:53:34.808066 start: 4.1 power-off (timeout 00:00:30) [common]
12653 23:53:34.808220 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
12654 23:53:34.886096 >> Command sent successfully.
12655 23:53:34.888564 Returned 0 in 0 seconds
12656 23:53:34.988998 end: 4.1 power-off (duration 00:00:00) [common]
12658 23:53:34.989424 start: 4.2 read-feedback (timeout 00:07:00) [common]
12659 23:53:34.989743 Listened to connection for namespace 'common' for up to 1s
12660 23:53:35.990660 Finalising connection for namespace 'common'
12661 23:53:35.990824 Disconnecting from shell: Finalise
12662 23:53:35.990903 / #
12663 23:53:36.091195 end: 4.2 read-feedback (duration 00:00:01) [common]
12664 23:53:36.091364 end: 4 finalize (duration 00:00:01) [common]
12665 23:53:36.091481 Cleaning after the job
12666 23:53:36.091591 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/ramdisk
12667 23:53:36.098361 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/kernel
12668 23:53:36.114143 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/dtb
12669 23:53:36.114372 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084325/tftp-deploy-7j3mdvgy/modules
12670 23:53:36.120004 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084325
12671 23:53:36.235381 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084325
12672 23:53:36.235547 Job finished correctly