Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 23:49:54.625939 lava-dispatcher, installed at version: 2024.03
2 23:49:54.626135 start: 0 validate
3 23:49:54.626275 Start time: 2024-05-29 23:49:54.626266+00:00 (UTC)
4 23:49:54.626389 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:49:54.626514 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:49:54.894221 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:49:54.894395 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:49:55.162057 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:49:55.162233 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:49:55.429168 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:49:55.429384 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:49:55.959479 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:49:55.959662 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:49:56.219699 validate duration: 1.59
16 23:49:56.220070 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:49:56.220221 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:49:56.220338 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:49:56.220497 Not decompressing ramdisk as can be used compressed.
20 23:49:56.220612 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:49:56.220713 saving as /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/ramdisk/initrd.cpio.gz
22 23:49:56.220807 total size: 5628169 (5 MB)
23 23:49:56.222086 progress 0 % (0 MB)
24 23:49:56.223814 progress 5 % (0 MB)
25 23:49:56.225562 progress 10 % (0 MB)
26 23:49:56.227013 progress 15 % (0 MB)
27 23:49:56.228691 progress 20 % (1 MB)
28 23:49:56.230206 progress 25 % (1 MB)
29 23:49:56.231839 progress 30 % (1 MB)
30 23:49:56.233511 progress 35 % (1 MB)
31 23:49:56.234934 progress 40 % (2 MB)
32 23:49:56.236571 progress 45 % (2 MB)
33 23:49:56.238033 progress 50 % (2 MB)
34 23:49:56.239619 progress 55 % (2 MB)
35 23:49:56.241345 progress 60 % (3 MB)
36 23:49:56.242790 progress 65 % (3 MB)
37 23:49:56.244481 progress 70 % (3 MB)
38 23:49:56.246066 progress 75 % (4 MB)
39 23:49:56.247679 progress 80 % (4 MB)
40 23:49:56.249153 progress 85 % (4 MB)
41 23:49:56.250838 progress 90 % (4 MB)
42 23:49:56.252477 progress 95 % (5 MB)
43 23:49:56.254018 progress 100 % (5 MB)
44 23:49:56.254237 5 MB downloaded in 0.03 s (160.56 MB/s)
45 23:49:56.254393 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:49:56.254649 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:49:56.254739 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:49:56.254833 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:49:56.254996 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:49:56.255066 saving as /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/kernel/Image
52 23:49:56.255126 total size: 54682112 (52 MB)
53 23:49:56.255225 No compression specified
54 23:49:56.256877 progress 0 % (0 MB)
55 23:49:56.272007 progress 5 % (2 MB)
56 23:49:56.286707 progress 10 % (5 MB)
57 23:49:56.300627 progress 15 % (7 MB)
58 23:49:56.314268 progress 20 % (10 MB)
59 23:49:56.328067 progress 25 % (13 MB)
60 23:49:56.341756 progress 30 % (15 MB)
61 23:49:56.355679 progress 35 % (18 MB)
62 23:49:56.369603 progress 40 % (20 MB)
63 23:49:56.383386 progress 45 % (23 MB)
64 23:49:56.397469 progress 50 % (26 MB)
65 23:49:56.411210 progress 55 % (28 MB)
66 23:49:56.424960 progress 60 % (31 MB)
67 23:49:56.438510 progress 65 % (33 MB)
68 23:49:56.454015 progress 70 % (36 MB)
69 23:49:56.468182 progress 75 % (39 MB)
70 23:49:56.483050 progress 80 % (41 MB)
71 23:49:56.497394 progress 85 % (44 MB)
72 23:49:56.511386 progress 90 % (46 MB)
73 23:49:56.525308 progress 95 % (49 MB)
74 23:49:56.538893 progress 100 % (52 MB)
75 23:49:56.539128 52 MB downloaded in 0.28 s (183.62 MB/s)
76 23:49:56.539277 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:49:56.539513 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:49:56.539599 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:49:56.539682 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:49:56.539812 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:49:56.539887 saving as /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/dtb/mt8192-asurada-spherion-r0.dtb
83 23:49:56.539948 total size: 47258 (0 MB)
84 23:49:56.540008 No compression specified
85 23:49:56.541116 progress 69 % (0 MB)
86 23:49:56.541429 progress 100 % (0 MB)
87 23:49:56.541583 0 MB downloaded in 0.00 s (27.59 MB/s)
88 23:49:56.541702 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:49:56.541928 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:49:56.542031 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:49:56.542140 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:49:56.542266 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:49:56.542333 saving as /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/nfsrootfs/full.rootfs.tar
95 23:49:56.542398 total size: 120894716 (115 MB)
96 23:49:56.542464 Using unxz to decompress xz
97 23:49:56.546675 progress 0 % (0 MB)
98 23:49:56.893970 progress 5 % (5 MB)
99 23:49:57.251874 progress 10 % (11 MB)
100 23:49:57.601952 progress 15 % (17 MB)
101 23:49:57.930780 progress 20 % (23 MB)
102 23:49:58.224449 progress 25 % (28 MB)
103 23:49:58.586381 progress 30 % (34 MB)
104 23:49:58.929393 progress 35 % (40 MB)
105 23:49:59.094744 progress 40 % (46 MB)
106 23:49:59.271764 progress 45 % (51 MB)
107 23:49:59.581176 progress 50 % (57 MB)
108 23:49:59.956099 progress 55 % (63 MB)
109 23:50:00.300238 progress 60 % (69 MB)
110 23:50:00.641874 progress 65 % (74 MB)
111 23:50:00.986201 progress 70 % (80 MB)
112 23:50:01.346225 progress 75 % (86 MB)
113 23:50:01.689349 progress 80 % (92 MB)
114 23:50:02.033066 progress 85 % (98 MB)
115 23:50:02.395949 progress 90 % (103 MB)
116 23:50:02.732225 progress 95 % (109 MB)
117 23:50:03.092683 progress 100 % (115 MB)
118 23:50:03.098146 115 MB downloaded in 6.56 s (17.59 MB/s)
119 23:50:03.098440 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:50:03.098711 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:50:03.098803 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:50:03.098889 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:50:03.099048 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:50:03.099171 saving as /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/modules/modules.tar
126 23:50:03.099232 total size: 8601444 (8 MB)
127 23:50:03.099297 Using unxz to decompress xz
128 23:50:03.103457 progress 0 % (0 MB)
129 23:50:03.123814 progress 5 % (0 MB)
130 23:50:03.148822 progress 10 % (0 MB)
131 23:50:03.174872 progress 15 % (1 MB)
132 23:50:03.200100 progress 20 % (1 MB)
133 23:50:03.226180 progress 25 % (2 MB)
134 23:50:03.251548 progress 30 % (2 MB)
135 23:50:03.275345 progress 35 % (2 MB)
136 23:50:03.300080 progress 40 % (3 MB)
137 23:50:03.327067 progress 45 % (3 MB)
138 23:50:03.351682 progress 50 % (4 MB)
139 23:50:03.376984 progress 55 % (4 MB)
140 23:50:03.402031 progress 60 % (4 MB)
141 23:50:03.426264 progress 65 % (5 MB)
142 23:50:03.452989 progress 70 % (5 MB)
143 23:50:03.478549 progress 75 % (6 MB)
144 23:50:03.502546 progress 80 % (6 MB)
145 23:50:03.528448 progress 85 % (7 MB)
146 23:50:03.552509 progress 90 % (7 MB)
147 23:50:03.582271 progress 95 % (7 MB)
148 23:50:03.610548 progress 100 % (8 MB)
149 23:50:03.616091 8 MB downloaded in 0.52 s (15.87 MB/s)
150 23:50:03.616432 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:50:03.616858 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:50:03.616997 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 23:50:03.617138 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 23:50:07.972232 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7
156 23:50:07.972441 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:50:07.972540 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:50:07.972714 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx
159 23:50:07.972842 makedir: /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin
160 23:50:07.972941 makedir: /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/tests
161 23:50:07.973039 makedir: /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/results
162 23:50:07.973138 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-add-keys
163 23:50:07.973461 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-add-sources
164 23:50:07.973647 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-background-process-start
165 23:50:07.973808 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-background-process-stop
166 23:50:07.973936 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-common-functions
167 23:50:07.974059 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-echo-ipv4
168 23:50:07.974183 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-install-packages
169 23:50:07.974306 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-installed-packages
170 23:50:07.974428 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-os-build
171 23:50:07.974552 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-probe-channel
172 23:50:07.974675 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-probe-ip
173 23:50:07.974798 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-target-ip
174 23:50:07.974920 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-target-mac
175 23:50:07.975041 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-target-storage
176 23:50:07.975165 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-case
177 23:50:07.975287 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-event
178 23:50:07.975412 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-feedback
179 23:50:07.975535 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-raise
180 23:50:07.975656 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-reference
181 23:50:07.975778 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-runner
182 23:50:07.975899 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-set
183 23:50:07.976023 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-test-shell
184 23:50:07.976147 Updating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-add-keys (debian)
185 23:50:07.976298 Updating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-add-sources (debian)
186 23:50:07.976438 Updating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-install-packages (debian)
187 23:50:07.976576 Updating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-installed-packages (debian)
188 23:50:07.976713 Updating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/bin/lava-os-build (debian)
189 23:50:07.976830 Creating /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/environment
190 23:50:07.976930 LAVA metadata
191 23:50:07.976999 - LAVA_JOB_ID=14084322
192 23:50:07.977061 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:50:07.977161 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:50:07.977226 skipped lava-vland-overlay
195 23:50:07.977344 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:50:07.977422 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:50:07.977482 skipped lava-multinode-overlay
198 23:50:07.977552 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:50:07.977627 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:50:07.977699 Loading test definitions
201 23:50:07.977785 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:50:07.977854 Using /lava-14084322 at stage 0
203 23:50:07.978130 uuid=14084322_1.6.2.3.1 testdef=None
204 23:50:07.978216 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:50:07.978300 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:50:07.978746 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:50:07.978964 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:50:07.979507 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:50:07.979734 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:50:07.980258 runner path: /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/0/tests/0_timesync-off test_uuid 14084322_1.6.2.3.1
213 23:50:07.980414 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:50:07.980639 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:50:07.980711 Using /lava-14084322 at stage 0
217 23:50:07.980806 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:50:07.980891 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/0/tests/1_kselftest-alsa'
219 23:50:11.077482 Running '/usr/bin/git checkout kernelci.org
220 23:50:11.155359 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 23:50:11.156118 uuid=14084322_1.6.2.3.5 testdef=None
222 23:50:11.156282 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:50:11.156527 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 23:50:11.157268 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:50:11.157539 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 23:50:11.158537 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:50:11.158821 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 23:50:11.159847 runner path: /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/0/tests/1_kselftest-alsa test_uuid 14084322_1.6.2.3.5
232 23:50:11.159941 BOARD='mt8192-asurada-spherion-r0'
233 23:50:11.160006 BRANCH='cip-gitlab'
234 23:50:11.160064 SKIPFILE='/dev/null'
235 23:50:11.160121 SKIP_INSTALL='True'
236 23:50:11.160176 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:50:11.160232 TST_CASENAME=''
238 23:50:11.160286 TST_CMDFILES='alsa'
239 23:50:11.160430 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:50:11.160636 Creating lava-test-runner.conf files
242 23:50:11.160700 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084322/lava-overlay-qavxtbmx/lava-14084322/0 for stage 0
243 23:50:11.160793 - 0_timesync-off
244 23:50:11.160864 - 1_kselftest-alsa
245 23:50:11.160957 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:50:11.161045 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 23:50:18.615006 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:50:18.615167 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 23:50:18.615262 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:50:18.615363 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:50:18.615452 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 23:50:18.778660 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:50:18.779060 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:50:18.779172 extracting modules file /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7
255 23:50:18.985556 extracting modules file /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084322/extract-overlay-ramdisk-denei09v/ramdisk
256 23:50:19.196740 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:50:19.196907 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 23:50:19.196998 [common] Applying overlay to NFS
259 23:50:19.197069 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084322/compress-overlay-25oz8z9z/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7
260 23:50:20.108959 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:50:20.109133 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 23:50:20.109229 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:50:20.109371 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 23:50:20.109459 Building ramdisk /var/lib/lava/dispatcher/tmp/14084322/extract-overlay-ramdisk-denei09v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084322/extract-overlay-ramdisk-denei09v/ramdisk
265 23:50:20.447738 >> 130335 blocks
266 23:50:22.495081 rename /var/lib/lava/dispatcher/tmp/14084322/extract-overlay-ramdisk-denei09v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/ramdisk/ramdisk.cpio.gz
267 23:50:22.495573 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:50:22.495751 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 23:50:22.495898 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 23:50:22.496044 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/kernel/Image']
271 23:50:35.586755 Returned 0 in 13 seconds
272 23:50:35.687665 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/kernel/image.itb
273 23:50:36.094780 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:50:36.095288 output: Created: Thu May 30 00:50:36 2024
275 23:50:36.095423 output: Image 0 (kernel-1)
276 23:50:36.095548 output: Description:
277 23:50:36.095671 output: Created: Thu May 30 00:50:36 2024
278 23:50:36.095787 output: Type: Kernel Image
279 23:50:36.095906 output: Compression: lzma compressed
280 23:50:36.096025 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
281 23:50:36.096144 output: Architecture: AArch64
282 23:50:36.096273 output: OS: Linux
283 23:50:36.096394 output: Load Address: 0x00000000
284 23:50:36.096515 output: Entry Point: 0x00000000
285 23:50:36.096637 output: Hash algo: crc32
286 23:50:36.096756 output: Hash value: 907bf91d
287 23:50:36.096878 output: Image 1 (fdt-1)
288 23:50:36.096997 output: Description: mt8192-asurada-spherion-r0
289 23:50:36.097114 output: Created: Thu May 30 00:50:36 2024
290 23:50:36.097233 output: Type: Flat Device Tree
291 23:50:36.097358 output: Compression: uncompressed
292 23:50:36.097475 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:50:36.097596 output: Architecture: AArch64
294 23:50:36.097711 output: Hash algo: crc32
295 23:50:36.097825 output: Hash value: 0f8e4d2e
296 23:50:36.097943 output: Image 2 (ramdisk-1)
297 23:50:36.098057 output: Description: unavailable
298 23:50:36.098179 output: Created: Thu May 30 00:50:36 2024
299 23:50:36.098300 output: Type: RAMDisk Image
300 23:50:36.098416 output: Compression: Unknown Compression
301 23:50:36.098531 output: Data Size: 18718904 Bytes = 18280.18 KiB = 17.85 MiB
302 23:50:36.098645 output: Architecture: AArch64
303 23:50:36.098760 output: OS: Linux
304 23:50:36.098873 output: Load Address: unavailable
305 23:50:36.098987 output: Entry Point: unavailable
306 23:50:36.099098 output: Hash algo: crc32
307 23:50:36.099214 output: Hash value: 978e6a59
308 23:50:36.099329 output: Default Configuration: 'conf-1'
309 23:50:36.099442 output: Configuration 0 (conf-1)
310 23:50:36.099562 output: Description: mt8192-asurada-spherion-r0
311 23:50:36.099676 output: Kernel: kernel-1
312 23:50:36.099792 output: Init Ramdisk: ramdisk-1
313 23:50:36.099908 output: FDT: fdt-1
314 23:50:36.100022 output: Loadables: kernel-1
315 23:50:36.100138 output:
316 23:50:36.100450 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:50:36.100627 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:50:36.100805 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 23:50:36.100971 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:50:36.101116 No LXC device requested
321 23:50:36.101308 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:50:36.101473 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:50:36.101627 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:50:36.101764 Checking files for TFTP limit of 4294967296 bytes.
325 23:50:36.102617 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:50:36.102795 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:50:36.102956 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:50:36.103173 substitutions:
329 23:50:36.103304 - {DTB}: 14084322/tftp-deploy-lr3_8_9e/dtb/mt8192-asurada-spherion-r0.dtb
330 23:50:36.103435 - {INITRD}: 14084322/tftp-deploy-lr3_8_9e/ramdisk/ramdisk.cpio.gz
331 23:50:36.103555 - {KERNEL}: 14084322/tftp-deploy-lr3_8_9e/kernel/Image
332 23:50:36.103674 - {LAVA_MAC}: None
333 23:50:36.103791 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7
334 23:50:36.103909 - {NFS_SERVER_IP}: 192.168.201.1
335 23:50:36.104032 - {PRESEED_CONFIG}: None
336 23:50:36.104152 - {PRESEED_LOCAL}: None
337 23:50:36.104269 - {RAMDISK}: 14084322/tftp-deploy-lr3_8_9e/ramdisk/ramdisk.cpio.gz
338 23:50:36.104386 - {ROOT_PART}: None
339 23:50:36.104501 - {ROOT}: None
340 23:50:36.104617 - {SERVER_IP}: 192.168.201.1
341 23:50:36.104732 - {TEE}: None
342 23:50:36.104847 Parsed boot commands:
343 23:50:36.104958 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:50:36.105273 Parsed boot commands: tftpboot 192.168.201.1 14084322/tftp-deploy-lr3_8_9e/kernel/image.itb 14084322/tftp-deploy-lr3_8_9e/kernel/cmdline
345 23:50:36.105440 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:50:36.105599 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:50:36.105765 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:50:36.105927 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:50:36.106065 Not connected, no need to disconnect.
350 23:50:36.106207 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:50:36.106368 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:50:36.106503 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 23:50:36.111197 Setting prompt string to ['lava-test: # ']
354 23:50:36.111616 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:50:36.111779 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:50:36.111948 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:50:36.112101 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:50:36.112389 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 23:50:50.087793 Returned 0 in 13 seconds
360 23:50:50.188475 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 23:50:50.188819 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 23:50:50.188922 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 23:50:50.189011 Setting prompt string to 'Starting depthcharge on Spherion...'
365 23:50:50.189083 Changing prompt to 'Starting depthcharge on Spherion...'
366 23:50:50.189151 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 23:50:50.189596 [Enter `^Ec?' for help]
368 23:50:50.189678
369 23:50:50.189746
370 23:50:50.189812 F0: 102B 0000
371 23:50:50.189878
372 23:50:50.189941 F3: 1001 0000 [0200]
373 23:50:50.190036
374 23:50:50.190106 F3: 1001 0000
375 23:50:50.190204
376 23:50:50.190306 F7: 102D 0000
377 23:50:50.190366
378 23:50:50.190422 F1: 0000 0000
379 23:50:50.190478
380 23:50:50.190533 V0: 0000 0000 [0001]
381 23:50:50.190588
382 23:50:50.190643 00: 0007 8000
383 23:50:50.190701
384 23:50:50.190756 01: 0000 0000
385 23:50:50.190813
386 23:50:50.190868 BP: 0C00 0209 [0000]
387 23:50:50.190922
388 23:50:50.190977 G0: 1182 0000
389 23:50:50.191031
390 23:50:50.191085 EC: 0000 0021 [4000]
391 23:50:50.191139
392 23:50:50.191194 S7: 0000 0000 [0000]
393 23:50:50.191248
394 23:50:50.191302 CC: 0000 0000 [0001]
395 23:50:50.191356
396 23:50:50.191410 T0: 0000 0040 [010F]
397 23:50:50.191466
398 23:50:50.191520 Jump to BL
399 23:50:50.191573
400 23:50:50.191627
401 23:50:50.191682
402 23:50:50.191736 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 23:50:50.191794 ARM64: Exception handlers installed.
404 23:50:50.191850 ARM64: Testing exception
405 23:50:50.191905 ARM64: Done test exception
406 23:50:50.191959 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 23:50:50.192015 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 23:50:50.192072 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 23:50:50.192128 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 23:50:50.192183 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 23:50:50.192239 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 23:50:50.192294 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 23:50:50.192350 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 23:50:50.192405 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 23:50:50.192461 WDT: Last reset was cold boot
416 23:50:50.192515 SPI1(PAD0) initialized at 2873684 Hz
417 23:50:50.192570 SPI5(PAD0) initialized at 992727 Hz
418 23:50:50.192625 VBOOT: Loading verstage.
419 23:50:50.192680 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 23:50:50.192735 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 23:50:50.192791 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 23:50:50.192846 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 23:50:50.192902 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 23:50:50.192958 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 23:50:50.193013 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 23:50:50.193068
427 23:50:50.193123
428 23:50:50.193181 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 23:50:50.193237 ARM64: Exception handlers installed.
430 23:50:50.193343 ARM64: Testing exception
431 23:50:50.193402 ARM64: Done test exception
432 23:50:50.193458 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 23:50:50.193515 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 23:50:50.193571 Probing TPM: . done!
435 23:50:50.193626 TPM ready after 0 ms
436 23:50:50.193682 Connected to device vid:did:rid of 1ae0:0028:00
437 23:50:50.193737 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 23:50:50.193794 Initialized TPM device CR50 revision 0
439 23:50:50.193849 tlcl_send_startup: Startup return code is 0
440 23:50:50.193904 TPM: setup succeeded
441 23:50:50.193959 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 23:50:50.194015 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 23:50:50.194070 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 23:50:50.194126 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:50:50.194184 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 23:50:50.194241 in-header: 03 07 00 00 08 00 00 00
447 23:50:50.194296 in-data: aa e4 47 04 13 02 00 00
448 23:50:50.194351 Chrome EC: UHEPI supported
449 23:50:50.194407 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 23:50:50.194463 in-header: 03 a9 00 00 08 00 00 00
451 23:50:50.194518 in-data: 84 60 60 08 00 00 00 00
452 23:50:50.194573 Phase 1
453 23:50:50.194627 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 23:50:50.194683 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 23:50:50.194739 VB2:vb2_check_recovery() Recovery was requested manually
456 23:50:50.194794 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 23:50:50.194850 Recovery requested (1009000e)
458 23:50:50.194905 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:50:50.194961 tlcl_extend: response is 0
460 23:50:50.195015 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:50:50.195071 tlcl_extend: response is 0
462 23:50:50.195126 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:50:50.195181 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 23:50:50.195237 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:50:50.195293
466 23:50:50.195347
467 23:50:50.195402 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:50:50.195458 ARM64: Exception handlers installed.
469 23:50:50.195513 ARM64: Testing exception
470 23:50:50.195567 ARM64: Done test exception
471 23:50:50.195622 pmic_efuse_setting: Set efuses in 11 msecs
472 23:50:50.195676 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:50:50.195731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:50:50.195787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:50:50.196036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:50:50.196142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:50:50.196281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:50:50.196391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:50:50.196500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:50:50.196596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:50:50.196686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:50:50.196772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:50:50.196858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:50:50.196969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:50:50.197074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:50:50.197167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:50:50.197254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:50:50.197383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:50:50.197475 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:50:50.197581 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:50:50.197673 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:50:50.197759 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:50:50.197844 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:50:50.197964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:50:50.198050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:50:50.198136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:50:50.198299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:50:50.198387 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:50:50.198474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:50:50.198560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:50:50.198645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:50:50.198731 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:50:50.198816 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:50:50.198902 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:50:50.198988 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:50:50.199073 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:50:50.199158 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:50:50.199243 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:50:50.199329 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:50:50.199413 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:50:50.199499 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:50:50.199584 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:50:50.199669 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:50:50.199754 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:50:50.199839 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:50:50.199923 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:50:50.200008 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:50:50.200093 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:50:50.200177 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:50:50.200262 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:50:50.200347 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:50:50.200432 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:50:50.200517 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:50:50.200602 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 23:50:50.200689 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:50:50.200774 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:50:50.200861 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:50:50.200947 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:50:50.201032 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:50:50.201117 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:50:50.201202 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:50:50.201336 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x1
533 23:50:50.201409 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:50:50.201465 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 23:50:50.201521 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:50:50.201577 [RTC]rtc_get_frequency_meter,154: input=15, output=853
537 23:50:50.201633 [RTC]rtc_get_frequency_meter,154: input=7, output=725
538 23:50:50.201688 [RTC]rtc_get_frequency_meter,154: input=11, output=789
539 23:50:50.201743 [RTC]rtc_get_frequency_meter,154: input=13, output=821
540 23:50:50.201798 [RTC]rtc_get_frequency_meter,154: input=12, output=806
541 23:50:50.201853 [RTC]rtc_get_frequency_meter,154: input=11, output=789
542 23:50:50.201908 [RTC]rtc_get_frequency_meter,154: input=12, output=806
543 23:50:50.201963 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 23:50:50.202019 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 23:50:50.202263 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:50:50.202394 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 23:50:50.202451 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:50:50.202507 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 23:50:50.202563 ADC[4]: Raw value=904064 ID=7
550 23:50:50.202618 ADC[3]: Raw value=213916 ID=1
551 23:50:50.202673 RAM Code: 0x71
552 23:50:50.202728 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:50:50.202784 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:50:50.202839 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 23:50:50.202927 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 23:50:50.203013 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:50:50.203069 in-header: 03 07 00 00 08 00 00 00
558 23:50:50.203124 in-data: aa e4 47 04 13 02 00 00
559 23:50:50.203178 Chrome EC: UHEPI supported
560 23:50:50.203233 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:50:50.203289 in-header: 03 a9 00 00 08 00 00 00
562 23:50:50.203344 in-data: 84 60 60 08 00 00 00 00
563 23:50:50.203398 MRC: failed to locate region type 0.
564 23:50:50.203453 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:50:50.203508 DRAM-K: Running full calibration
566 23:50:50.203564 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 23:50:50.203619 header.status = 0x0
568 23:50:50.203694 header.version = 0x6 (expected: 0x6)
569 23:50:50.203759 header.size = 0xd00 (expected: 0xd00)
570 23:50:50.203827 header.flags = 0x0
571 23:50:50.203882 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:50:50.203938 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 23:50:50.203994 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:50:50.204050 dram_init: ddr_geometry: 2
575 23:50:50.204132 [EMI] MDL number = 2
576 23:50:50.204235 [EMI] Get MDL freq = 0
577 23:50:50.204291 dram_init: ddr_type: 0
578 23:50:50.204360 is_discrete_lpddr4: 1
579 23:50:50.204428 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:50:50.204482
581 23:50:50.204537
582 23:50:50.204591 [Bian_co] ETT version 0.0.0.1
583 23:50:50.204646 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 23:50:50.204701
585 23:50:50.204756 dramc_set_vcore_voltage set vcore to 650000
586 23:50:50.204811 Read voltage for 800, 4
587 23:50:50.204866 Vio18 = 0
588 23:50:50.204920 Vcore = 650000
589 23:50:50.204974 Vdram = 0
590 23:50:50.205028 Vddq = 0
591 23:50:50.205083 Vmddr = 0
592 23:50:50.205137 dram_init: config_dvfs: 1
593 23:50:50.205192 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:50:50.205269 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:50:50.205339 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 23:50:50.205394 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 23:50:50.205450 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 23:50:50.205504 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 23:50:50.205559 MEM_TYPE=3, freq_sel=18
600 23:50:50.205613 sv_algorithm_assistance_LP4_1600
601 23:50:50.205668 ============ PULL DRAM RESETB DOWN ============
602 23:50:50.205726 ========== PULL DRAM RESETB DOWN end =========
603 23:50:50.205783 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:50:50.205837 ===================================
605 23:50:50.205892 LPDDR4 DRAM CONFIGURATION
606 23:50:50.205946 ===================================
607 23:50:50.206001 EX_ROW_EN[0] = 0x0
608 23:50:50.206056 EX_ROW_EN[1] = 0x0
609 23:50:50.206110 LP4Y_EN = 0x0
610 23:50:50.206183 WORK_FSP = 0x0
611 23:50:50.206277 WL = 0x2
612 23:50:50.206380 RL = 0x2
613 23:50:50.206435 BL = 0x2
614 23:50:50.206489 RPST = 0x0
615 23:50:50.206544 RD_PRE = 0x0
616 23:50:50.206599 WR_PRE = 0x1
617 23:50:50.206653 WR_PST = 0x0
618 23:50:50.206707 DBI_WR = 0x0
619 23:50:50.206761 DBI_RD = 0x0
620 23:50:50.206815 OTF = 0x1
621 23:50:50.206870 ===================================
622 23:50:50.206925 ===================================
623 23:50:50.206980 ANA top config
624 23:50:50.207048 ===================================
625 23:50:50.207107 DLL_ASYNC_EN = 0
626 23:50:50.207162 ALL_SLAVE_EN = 1
627 23:50:50.207217 NEW_RANK_MODE = 1
628 23:50:50.207273 DLL_IDLE_MODE = 1
629 23:50:50.207327 LP45_APHY_COMB_EN = 1
630 23:50:50.207382 TX_ODT_DIS = 1
631 23:50:50.207437 NEW_8X_MODE = 1
632 23:50:50.207492 ===================================
633 23:50:50.207547 ===================================
634 23:50:50.207602 data_rate = 1600
635 23:50:50.207656 CKR = 1
636 23:50:50.207711 DQ_P2S_RATIO = 8
637 23:50:50.207766 ===================================
638 23:50:50.207821 CA_P2S_RATIO = 8
639 23:50:50.207875 DQ_CA_OPEN = 0
640 23:50:50.207929 DQ_SEMI_OPEN = 0
641 23:50:50.207984 CA_SEMI_OPEN = 0
642 23:50:50.208039 CA_FULL_RATE = 0
643 23:50:50.208094 DQ_CKDIV4_EN = 1
644 23:50:50.208176 CA_CKDIV4_EN = 1
645 23:50:50.208245 CA_PREDIV_EN = 0
646 23:50:50.208301 PH8_DLY = 0
647 23:50:50.208384 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:50:50.208454 DQ_AAMCK_DIV = 4
649 23:50:50.208511 CA_AAMCK_DIV = 4
650 23:50:50.208567 CA_ADMCK_DIV = 4
651 23:50:50.208621 DQ_TRACK_CA_EN = 0
652 23:50:50.208675 CA_PICK = 800
653 23:50:50.208733 CA_MCKIO = 800
654 23:50:50.208787 MCKIO_SEMI = 0
655 23:50:50.208841 PLL_FREQ = 3068
656 23:50:50.208896 DQ_UI_PI_RATIO = 32
657 23:50:50.208954 CA_UI_PI_RATIO = 0
658 23:50:50.209012 ===================================
659 23:50:50.209070 ===================================
660 23:50:50.209126 memory_type:LPDDR4
661 23:50:50.209181 GP_NUM : 10
662 23:50:50.209235 SRAM_EN : 1
663 23:50:50.209324 MD32_EN : 0
664 23:50:50.209379 ===================================
665 23:50:50.209642 [ANA_INIT] >>>>>>>>>>>>>>
666 23:50:50.209703 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:50:50.209762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:50:50.209850 ===================================
669 23:50:50.209906 data_rate = 1600,PCW = 0X7600
670 23:50:50.209975 ===================================
671 23:50:50.210087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:50:50.210171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:50:50.210228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:50:50.210298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:50:50.210382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:50:50.210437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:50:50.210492 [ANA_INIT] flow start
678 23:50:50.210562 [ANA_INIT] PLL >>>>>>>>
679 23:50:50.210617 [ANA_INIT] PLL <<<<<<<<
680 23:50:50.210672 [ANA_INIT] MIDPI >>>>>>>>
681 23:50:50.210728 [ANA_INIT] MIDPI <<<<<<<<
682 23:50:50.210797 [ANA_INIT] DLL >>>>>>>>
683 23:50:50.210865 [ANA_INIT] flow end
684 23:50:50.210920 ============ LP4 DIFF to SE enter ============
685 23:50:50.210977 ============ LP4 DIFF to SE exit ============
686 23:50:50.211033 [ANA_INIT] <<<<<<<<<<<<<
687 23:50:50.211089 [Flow] Enable top DCM control >>>>>
688 23:50:50.211145 [Flow] Enable top DCM control <<<<<
689 23:50:50.211201 Enable DLL master slave shuffle
690 23:50:50.211257 ==============================================================
691 23:50:50.211313 Gating Mode config
692 23:50:50.211369 ==============================================================
693 23:50:50.211425 Config description:
694 23:50:50.211480 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:50:50.211537 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:50:50.211593 SELPH_MODE 0: By rank 1: By Phase
697 23:50:50.211649 ==============================================================
698 23:50:50.211705 GAT_TRACK_EN = 1
699 23:50:50.211761 RX_GATING_MODE = 2
700 23:50:50.211816 RX_GATING_TRACK_MODE = 2
701 23:50:50.211872 SELPH_MODE = 1
702 23:50:50.211927 PICG_EARLY_EN = 1
703 23:50:50.211983 VALID_LAT_VALUE = 1
704 23:50:50.212038 ==============================================================
705 23:50:50.212094 Enter into Gating configuration >>>>
706 23:50:50.212150 Exit from Gating configuration <<<<
707 23:50:50.212227 Enter into DVFS_PRE_config >>>>>
708 23:50:50.212337 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:50:50.212405 Exit from DVFS_PRE_config <<<<<
710 23:50:50.212462 Enter into PICG configuration >>>>
711 23:50:50.212545 Exit from PICG configuration <<<<
712 23:50:50.212601 [RX_INPUT] configuration >>>>>
713 23:50:50.212656 [RX_INPUT] configuration <<<<<
714 23:50:50.212726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:50:50.212823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:50:50.212878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:50:50.212934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:50:50.213016 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:50:50.213071 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:50:50.213126 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:50:50.213181 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:50:50.213250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:50:50.213335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:50:50.213390 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:50:50.213460 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:50:50.213529 ===================================
727 23:50:50.213584 LPDDR4 DRAM CONFIGURATION
728 23:50:50.213639 ===================================
729 23:50:50.213693 EX_ROW_EN[0] = 0x0
730 23:50:50.213748 EX_ROW_EN[1] = 0x0
731 23:50:50.213802 LP4Y_EN = 0x0
732 23:50:50.213856 WORK_FSP = 0x0
733 23:50:50.213911 WL = 0x2
734 23:50:50.213964 RL = 0x2
735 23:50:50.214018 BL = 0x2
736 23:50:50.214071 RPST = 0x0
737 23:50:50.214125 RD_PRE = 0x0
738 23:50:50.214194 WR_PRE = 0x1
739 23:50:50.214290 WR_PST = 0x0
740 23:50:50.214344 DBI_WR = 0x0
741 23:50:50.214398 DBI_RD = 0x0
742 23:50:50.214452 OTF = 0x1
743 23:50:50.214507 ===================================
744 23:50:50.214562 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:50:50.214616 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:50:50.214687 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:50:50.214774 ===================================
748 23:50:50.214844 LPDDR4 DRAM CONFIGURATION
749 23:50:50.214897 ===================================
750 23:50:50.214951 EX_ROW_EN[0] = 0x10
751 23:50:50.215006 EX_ROW_EN[1] = 0x0
752 23:50:50.215059 LP4Y_EN = 0x0
753 23:50:50.215113 WORK_FSP = 0x0
754 23:50:50.215167 WL = 0x2
755 23:50:50.215221 RL = 0x2
756 23:50:50.215274 BL = 0x2
757 23:50:50.215328 RPST = 0x0
758 23:50:50.215381 RD_PRE = 0x0
759 23:50:50.215435 WR_PRE = 0x1
760 23:50:50.215488 WR_PST = 0x0
761 23:50:50.215542 DBI_WR = 0x0
762 23:50:50.215596 DBI_RD = 0x0
763 23:50:50.215650 OTF = 0x1
764 23:50:50.215705 ===================================
765 23:50:50.215760 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:50:50.215814 nWR fixed to 40
767 23:50:50.215879 [ModeRegInit_LP4] CH0 RK0
768 23:50:50.215934 [ModeRegInit_LP4] CH0 RK1
769 23:50:50.215989 [ModeRegInit_LP4] CH1 RK0
770 23:50:50.216042 [ModeRegInit_LP4] CH1 RK1
771 23:50:50.216097 match AC timing 13
772 23:50:50.216151 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 23:50:50.216399 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:50:50.216460 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:50:50.216516 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:50:50.216572 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:50:50.216655 [EMI DOE] emi_dcm 0
778 23:50:50.216710 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:50:50.216764 ==
780 23:50:50.216819 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:50:50.216874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:50:50.216929 ==
783 23:50:50.216983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:50:50.217039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:50:50.217094 [CA 0] Center 38 (7~69) winsize 63
786 23:50:50.217149 [CA 1] Center 37 (7~68) winsize 62
787 23:50:50.217203 [CA 2] Center 35 (5~65) winsize 61
788 23:50:50.217279 [CA 3] Center 35 (4~66) winsize 63
789 23:50:50.217349 [CA 4] Center 33 (3~64) winsize 62
790 23:50:50.217403 [CA 5] Center 33 (3~64) winsize 62
791 23:50:50.217458
792 23:50:50.217512 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:50:50.217567
794 23:50:50.217621 [CATrainingPosCal] consider 1 rank data
795 23:50:50.217675 u2DelayCellTimex100 = 270/100 ps
796 23:50:50.217729 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
797 23:50:50.217784 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:50:50.217839 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
799 23:50:50.217893 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
800 23:50:50.217947 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 23:50:50.218002 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:50:50.218056
803 23:50:50.218110 CA PerBit enable=1, Macro0, CA PI delay=33
804 23:50:50.218164
805 23:50:50.218219 [CBTSetCACLKResult] CA Dly = 33
806 23:50:50.218273 CS Dly: 5 (0~36)
807 23:50:50.218328 ==
808 23:50:50.218382 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:50:50.218437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:50:50.218492 ==
811 23:50:50.218547 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:50:50.218602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:50:50.218657 [CA 0] Center 38 (7~69) winsize 63
814 23:50:50.218711 [CA 1] Center 37 (7~68) winsize 62
815 23:50:50.218765 [CA 2] Center 35 (4~66) winsize 63
816 23:50:50.218819 [CA 3] Center 35 (4~66) winsize 63
817 23:50:50.218873 [CA 4] Center 34 (3~65) winsize 63
818 23:50:50.218928 [CA 5] Center 33 (3~64) winsize 62
819 23:50:50.218982
820 23:50:50.219036 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 23:50:50.219090
822 23:50:50.219145 [CATrainingPosCal] consider 2 rank data
823 23:50:50.219199 u2DelayCellTimex100 = 270/100 ps
824 23:50:50.219253 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
825 23:50:50.219309 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:50:50.219363 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
827 23:50:50.219417 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
828 23:50:50.219472 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 23:50:50.219526 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:50:50.219581
831 23:50:50.219635 CA PerBit enable=1, Macro0, CA PI delay=33
832 23:50:50.219690
833 23:50:50.219744 [CBTSetCACLKResult] CA Dly = 33
834 23:50:50.219831 CS Dly: 6 (0~38)
835 23:50:50.219885
836 23:50:50.219939 ----->DramcWriteLeveling(PI) begin...
837 23:50:50.219997 ==
838 23:50:50.220051 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:50:50.220105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 23:50:50.220160 ==
841 23:50:50.220214 Write leveling (Byte 0): 30 => 30
842 23:50:50.220268 Write leveling (Byte 1): 28 => 28
843 23:50:50.220321 DramcWriteLeveling(PI) end<-----
844 23:50:50.220375
845 23:50:50.220428 ==
846 23:50:50.220482 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:50:50.220550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 23:50:50.220620 ==
849 23:50:50.220676 [Gating] SW mode calibration
850 23:50:50.220731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:50:50.220786 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:50:50.220842 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 23:50:50.220897 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 23:50:50.220952 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 23:50:50.221007 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:50:50.221062 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:50:50.221117 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:50:50.221172 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:50:50.221227 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:50:50.221324 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:50:50.221380 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:50:50.221435 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:50:50.221490 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:50:50.221544 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:50:50.221598 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:50:50.221653 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:50:50.221708 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:50:50.221762 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 23:50:50.221816 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
870 23:50:50.221870 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 23:50:50.221925 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 23:50:50.221979 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:50:50.222034 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:50:50.222088 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:50:50.222143 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:50:50.222197 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:50:50.222252 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:50:50.222307 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
879 23:50:50.222361 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
880 23:50:50.222416 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:50:50.222662 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:50:50.222741 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:50:50.222810 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:50:50.222866 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:50:50.222923 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
886 23:50:50.223007 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
887 23:50:50.223062 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
888 23:50:50.223117 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:50:50.223235 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:50:50.223290 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:50:50.223345 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:50:50.223429 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:50:50.223483 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
894 23:50:50.223537 0 11 8 | B1->B0 | 2d2d 4444 | 1 1 | (0 0) (0 0)
895 23:50:50.223592 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
896 23:50:50.223702 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:50:50.223771 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:50:50.223826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:50:50.223882 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:50:50.223938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:50:50.223994 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 23:50:50.224049 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 23:50:50.224105 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:50:50.224161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:50:50.224217 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:50:50.224273 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:50:50.224329 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:50:50.224384 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:50:50.224440 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:50:50.224495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:50:50.224551 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:50:50.224610 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:50:50.224666 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:50:50.224722 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:50:50.224780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:50:50.224862 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:50:50.224929 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 23:50:50.224984 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 23:50:50.225037 Total UI for P1: 0, mck2ui 16
920 23:50:50.225106 best dqsien dly found for B0: ( 0, 14, 4)
921 23:50:50.225162 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
922 23:50:50.225217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:50:50.225283 Total UI for P1: 0, mck2ui 16
924 23:50:50.225367 best dqsien dly found for B1: ( 0, 14, 10)
925 23:50:50.225422 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 23:50:50.225478 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 23:50:50.225534
928 23:50:50.225590 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 23:50:50.225645 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 23:50:50.225701 [Gating] SW calibration Done
931 23:50:50.225757 ==
932 23:50:50.225813 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:50:50.225882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:50:50.225937 ==
935 23:50:50.225991 RX Vref Scan: 0
936 23:50:50.226059
937 23:50:50.226155 RX Vref 0 -> 0, step: 1
938 23:50:50.226256
939 23:50:50.226313 RX Delay -130 -> 252, step: 16
940 23:50:50.226397 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:50:50.226452 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 23:50:50.226507 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:50:50.226562 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:50:50.226646 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 23:50:50.226701 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 23:50:50.226755 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:50:50.226810 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 23:50:50.226865 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 23:50:50.226919 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 23:50:50.226973 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 23:50:50.227027 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 23:50:50.227081 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 23:50:50.227136 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 23:50:50.227189 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:50:50.227243 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 23:50:50.227298 ==
957 23:50:50.227353 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:50:50.227407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:50:50.227462 ==
960 23:50:50.227516 DQS Delay:
961 23:50:50.227570 DQS0 = 0, DQS1 = 0
962 23:50:50.227624 DQM Delay:
963 23:50:50.227679 DQM0 = 88, DQM1 = 75
964 23:50:50.227733 DQ Delay:
965 23:50:50.227809 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 23:50:50.227878 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 23:50:50.227932 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
968 23:50:50.227986 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 23:50:50.228040
970 23:50:50.228108
971 23:50:50.228175 ==
972 23:50:50.228230 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:50:50.228284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:50:50.228352 ==
975 23:50:50.228420
976 23:50:50.228474
977 23:50:50.228528 TX Vref Scan disable
978 23:50:50.228582 == TX Byte 0 ==
979 23:50:50.228636 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 23:50:50.228691 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 23:50:50.228745 == TX Byte 1 ==
982 23:50:50.228800 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 23:50:50.228854 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 23:50:50.228909 ==
985 23:50:50.228963 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:50:50.229017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:50:50.229072 ==
988 23:50:50.229314 TX Vref=22, minBit 1, minWin=27, winSum=437
989 23:50:50.229454 TX Vref=24, minBit 0, minWin=27, winSum=439
990 23:50:50.229540 TX Vref=26, minBit 1, minWin=27, winSum=446
991 23:50:50.229610 TX Vref=28, minBit 1, minWin=27, winSum=451
992 23:50:50.229673 TX Vref=30, minBit 1, minWin=27, winSum=450
993 23:50:50.229729 TX Vref=32, minBit 1, minWin=27, winSum=450
994 23:50:50.229784 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
995 23:50:50.229868
996 23:50:50.229950 Final TX Range 1 Vref 28
997 23:50:50.230005
998 23:50:50.230073 ==
999 23:50:50.230129 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:50:50.230197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:50:50.230261 ==
1002 23:50:50.230331
1003 23:50:50.230428
1004 23:50:50.230482 TX Vref Scan disable
1005 23:50:50.230537 == TX Byte 0 ==
1006 23:50:50.230620 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 23:50:50.230675 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 23:50:50.230730 == TX Byte 1 ==
1009 23:50:50.230784 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 23:50:50.230867 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 23:50:50.230950
1012 23:50:50.231005 [DATLAT]
1013 23:50:50.231074 Freq=800, CH0 RK0
1014 23:50:50.231144
1015 23:50:50.231198 DATLAT Default: 0xa
1016 23:50:50.231253 0, 0xFFFF, sum = 0
1017 23:50:50.231324 1, 0xFFFF, sum = 0
1018 23:50:50.231409 2, 0xFFFF, sum = 0
1019 23:50:50.231466 3, 0xFFFF, sum = 0
1020 23:50:50.231523 4, 0xFFFF, sum = 0
1021 23:50:50.231579 5, 0xFFFF, sum = 0
1022 23:50:50.231636 6, 0xFFFF, sum = 0
1023 23:50:50.231693 7, 0xFFFF, sum = 0
1024 23:50:50.231750 8, 0xFFFF, sum = 0
1025 23:50:50.231813 9, 0x0, sum = 1
1026 23:50:50.231875 10, 0x0, sum = 2
1027 23:50:50.231932 11, 0x0, sum = 3
1028 23:50:50.231989 12, 0x0, sum = 4
1029 23:50:50.232045 best_step = 10
1030 23:50:50.232100
1031 23:50:50.232155 ==
1032 23:50:50.232211 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:50:50.232266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:50:50.232321 ==
1035 23:50:50.232417 RX Vref Scan: 1
1036 23:50:50.232470
1037 23:50:50.232538 Set Vref Range= 32 -> 127
1038 23:50:50.232606
1039 23:50:50.232660 RX Vref 32 -> 127, step: 1
1040 23:50:50.232714
1041 23:50:50.232789 RX Delay -111 -> 252, step: 8
1042 23:50:50.232845
1043 23:50:50.232900 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:50:50.232968 [Byte1]: 32
1045 23:50:50.233022
1046 23:50:50.233076 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:50:50.233130 [Byte1]: 33
1048 23:50:50.233184
1049 23:50:50.233251 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:50:50.233337 [Byte1]: 34
1051 23:50:50.233392
1052 23:50:50.233448 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:50:50.233502 [Byte1]: 35
1054 23:50:50.233555
1055 23:50:50.233609 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:50:50.233663 [Byte1]: 36
1057 23:50:50.233716
1058 23:50:50.233769 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:50:50.233823 [Byte1]: 37
1060 23:50:50.233877
1061 23:50:50.233930 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:50:50.233984 [Byte1]: 38
1063 23:50:50.234036
1064 23:50:50.234139 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:50:50.234194 [Byte1]: 39
1066 23:50:50.234247
1067 23:50:50.234300 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:50:50.234354 [Byte1]: 40
1069 23:50:50.234408
1070 23:50:50.234461 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:50:50.234515 [Byte1]: 41
1072 23:50:50.234568
1073 23:50:50.234621 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:50:50.234675 [Byte1]: 42
1075 23:50:50.234728
1076 23:50:50.234781 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:50:50.234835 [Byte1]: 43
1078 23:50:50.234889
1079 23:50:50.234942 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:50:50.234996 [Byte1]: 44
1081 23:50:50.235050
1082 23:50:50.235104 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:50:50.235158 [Byte1]: 45
1084 23:50:50.235212
1085 23:50:50.235265 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:50:50.235318 [Byte1]: 46
1087 23:50:50.235371
1088 23:50:50.235425 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:50:50.235478 [Byte1]: 47
1090 23:50:50.235531
1091 23:50:50.235584 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:50:50.235638 [Byte1]: 48
1093 23:50:50.235691
1094 23:50:50.235744 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:50:50.235797 [Byte1]: 49
1096 23:50:50.235851
1097 23:50:50.235904 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:50:50.235958 [Byte1]: 50
1099 23:50:50.236012
1100 23:50:50.236065 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:50:50.236118 [Byte1]: 51
1102 23:50:50.236171
1103 23:50:50.236224 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:50:50.236278 [Byte1]: 52
1105 23:50:50.236331
1106 23:50:50.236384 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:50:50.236438 [Byte1]: 53
1108 23:50:50.236491
1109 23:50:50.236545 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:50:50.236598 [Byte1]: 54
1111 23:50:50.236652
1112 23:50:50.236706 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:50:50.236759 [Byte1]: 55
1114 23:50:50.236813
1115 23:50:50.236866 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:50:50.236919 [Byte1]: 56
1117 23:50:50.236973
1118 23:50:50.237026 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:50:50.237080 [Byte1]: 57
1120 23:50:50.237133
1121 23:50:50.237186 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:50:50.237240 [Byte1]: 58
1123 23:50:50.237330
1124 23:50:50.237384 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:50:50.237438 [Byte1]: 59
1126 23:50:50.237491
1127 23:50:50.237545 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:50:50.237598 [Byte1]: 60
1129 23:50:50.237652
1130 23:50:50.237705 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:50:50.237759 [Byte1]: 61
1132 23:50:50.237813
1133 23:50:50.237866 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:50:50.237920 [Byte1]: 62
1135 23:50:50.237974
1136 23:50:50.238026 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:50:50.238080 [Byte1]: 63
1138 23:50:50.238134
1139 23:50:50.238187 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:50:50.238241 [Byte1]: 64
1141 23:50:50.238294
1142 23:50:50.238347 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:50:50.238401 [Byte1]: 65
1144 23:50:50.238454
1145 23:50:50.238507 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:50:50.238560 [Byte1]: 66
1147 23:50:50.238613
1148 23:50:50.238666 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:50:50.238719 [Byte1]: 67
1150 23:50:50.238773
1151 23:50:50.238826 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:50:50.238880 [Byte1]: 68
1153 23:50:50.238933
1154 23:50:50.238987 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:50:50.239041 [Byte1]: 69
1156 23:50:50.239094
1157 23:50:50.239342 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:50:50.239406 [Byte1]: 70
1159 23:50:50.239461
1160 23:50:50.239515 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:50:50.239568 [Byte1]: 71
1162 23:50:50.239622
1163 23:50:50.239676 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:50:50.239730 [Byte1]: 72
1165 23:50:50.239783
1166 23:50:50.239837 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:50:50.239920 [Byte1]: 73
1168 23:50:50.239974
1169 23:50:50.240027 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:50:50.240105 [Byte1]: 74
1171 23:50:50.240200
1172 23:50:50.240259 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:50:50.240315 [Byte1]: 75
1174 23:50:50.240370
1175 23:50:50.240424 Final RX Vref Byte 0 = 58 to rank0
1176 23:50:50.240479 Final RX Vref Byte 1 = 60 to rank0
1177 23:50:50.240534 Final RX Vref Byte 0 = 58 to rank1
1178 23:50:50.240588 Final RX Vref Byte 1 = 60 to rank1==
1179 23:50:50.240642 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 23:50:50.240697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 23:50:50.240751 ==
1182 23:50:50.240805 DQS Delay:
1183 23:50:50.240858 DQS0 = 0, DQS1 = 0
1184 23:50:50.240912 DQM Delay:
1185 23:50:50.240965 DQM0 = 88, DQM1 = 76
1186 23:50:50.241019 DQ Delay:
1187 23:50:50.241073 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1188 23:50:50.241127 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1189 23:50:50.241181 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1190 23:50:50.241235 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1191 23:50:50.241333
1192 23:50:50.241388
1193 23:50:50.241442 [DQSOSCAuto] RK0, (LSB)MR18= 0x342d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1194 23:50:50.241498 CH0 RK0: MR19=606, MR18=342D
1195 23:50:50.241553 CH0_RK0: MR19=0x606, MR18=0x342D, DQSOSC=396, MR23=63, INC=94, DEC=62
1196 23:50:50.241607
1197 23:50:50.241661 ----->DramcWriteLeveling(PI) begin...
1198 23:50:50.241716 ==
1199 23:50:50.241770 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 23:50:50.241825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 23:50:50.241879 ==
1202 23:50:50.241933 Write leveling (Byte 0): 30 => 30
1203 23:50:50.241987 Write leveling (Byte 1): 27 => 27
1204 23:50:50.242041 DramcWriteLeveling(PI) end<-----
1205 23:50:50.242095
1206 23:50:50.242148 ==
1207 23:50:50.242202 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:50:50.242256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 23:50:50.242311 ==
1210 23:50:50.242364 [Gating] SW mode calibration
1211 23:50:50.242417 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 23:50:50.242473 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 23:50:50.242526 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 23:50:50.242581 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1215 23:50:50.242635 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1216 23:50:50.242689 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:50:50.242743 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:50:50.242797 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:50:50.242851 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:50:50.242905 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:50:50.242975 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:50:50.243030 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:50:50.243084 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:50:50.243138 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:50:50.243191 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:50:50.243244 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:50:50.243299 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:50:50.243353 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:50:50.243407 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:50:50.243461 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:50:50.243514 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1232 23:50:50.243568 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:50:50.243622 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:50:50.243676 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:50:50.243729 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:50:50.243783 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:50:50.243836 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:50:50.243890 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:50:50.243944 0 9 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
1240 23:50:50.244014 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1241 23:50:50.244083 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 23:50:50.244136 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 23:50:50.244190 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 23:50:50.244243 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 23:50:50.244297 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1246 23:50:50.244351 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1247 23:50:50.244405 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1248 23:50:50.244459 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1249 23:50:50.244513 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:50:50.244567 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:50:50.244621 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:50:50.244675 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:50:50.244729 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:50:50.244783 0 11 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
1255 23:50:50.244837 0 11 8 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
1256 23:50:50.244890 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 23:50:50.244944 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:50:50.244998 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 23:50:50.245052 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:50:50.245106 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 23:50:50.245353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 23:50:50.245442 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 23:50:50.245514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:50:50.245569 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1265 23:50:50.245625 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:50:50.245680 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:50:50.245735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:50:50.245790 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:50:50.245845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:50:50.245900 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:50:50.245954 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:50:50.246010 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:50:50.246065 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:50:50.246120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:50:50.246175 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:50:50.246242 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:50:50.246295 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:50:50.246350 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 23:50:50.246417 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1280 23:50:50.246485 Total UI for P1: 0, mck2ui 16
1281 23:50:50.246542 best dqsien dly found for B0: ( 0, 14, 4)
1282 23:50:50.246596 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 23:50:50.246651 Total UI for P1: 0, mck2ui 16
1284 23:50:50.246705 best dqsien dly found for B1: ( 0, 14, 6)
1285 23:50:50.246760 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1286 23:50:50.246813 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1287 23:50:50.246868
1288 23:50:50.246921 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1289 23:50:50.246975 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1290 23:50:50.247029 [Gating] SW calibration Done
1291 23:50:50.247082 ==
1292 23:50:50.247136 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 23:50:50.247189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 23:50:50.247243 ==
1295 23:50:50.247325 RX Vref Scan: 0
1296 23:50:50.247379
1297 23:50:50.247432 RX Vref 0 -> 0, step: 1
1298 23:50:50.247486
1299 23:50:50.247540 RX Delay -130 -> 252, step: 16
1300 23:50:50.247593 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1301 23:50:50.247647 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1302 23:50:50.247701 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1303 23:50:50.247755 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1304 23:50:50.247809 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1305 23:50:50.247863 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1306 23:50:50.247916 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1307 23:50:50.247969 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1308 23:50:50.248023 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1309 23:50:50.248076 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1310 23:50:50.248130 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1311 23:50:50.248183 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1312 23:50:50.248237 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1313 23:50:50.248290 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1314 23:50:50.248344 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1315 23:50:50.248397 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1316 23:50:50.248451 ==
1317 23:50:50.248504 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 23:50:50.248558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 23:50:50.248613 ==
1320 23:50:50.248666 DQS Delay:
1321 23:50:50.248720 DQS0 = 0, DQS1 = 0
1322 23:50:50.248774 DQM Delay:
1323 23:50:50.248827 DQM0 = 85, DQM1 = 76
1324 23:50:50.248881 DQ Delay:
1325 23:50:50.248934 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1326 23:50:50.248987 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1327 23:50:50.249041 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1328 23:50:50.249095 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1329 23:50:50.249149
1330 23:50:50.249221
1331 23:50:50.249353 ==
1332 23:50:50.249412 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 23:50:50.249467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 23:50:50.249522 ==
1335 23:50:50.249577
1336 23:50:50.249631
1337 23:50:50.249684 TX Vref Scan disable
1338 23:50:50.249739 == TX Byte 0 ==
1339 23:50:50.249793 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1340 23:50:50.249848 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1341 23:50:50.249902 == TX Byte 1 ==
1342 23:50:50.249956 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1343 23:50:50.250010 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1344 23:50:50.250064 ==
1345 23:50:50.250146 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 23:50:50.250200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 23:50:50.250255 ==
1348 23:50:50.250309 TX Vref=22, minBit 0, minWin=27, winSum=438
1349 23:50:50.250364 TX Vref=24, minBit 1, minWin=27, winSum=444
1350 23:50:50.250418 TX Vref=26, minBit 2, minWin=27, winSum=447
1351 23:50:50.250473 TX Vref=28, minBit 6, minWin=27, winSum=448
1352 23:50:50.250527 TX Vref=30, minBit 1, minWin=27, winSum=448
1353 23:50:50.250581 TX Vref=32, minBit 7, minWin=27, winSum=449
1354 23:50:50.250635 [TxChooseVref] Worse bit 7, Min win 27, Win sum 449, Final Vref 32
1355 23:50:50.250690
1356 23:50:50.250744 Final TX Range 1 Vref 32
1357 23:50:50.250798
1358 23:50:50.250851 ==
1359 23:50:50.250905 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 23:50:50.250959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 23:50:50.251012 ==
1362 23:50:50.251066
1363 23:50:50.251118
1364 23:50:50.251171 TX Vref Scan disable
1365 23:50:50.251224 == TX Byte 0 ==
1366 23:50:50.251277 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1367 23:50:50.251330 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1368 23:50:50.251384 == TX Byte 1 ==
1369 23:50:50.251438 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1370 23:50:50.251492 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1371 23:50:50.251544
1372 23:50:50.251597 [DATLAT]
1373 23:50:50.251650 Freq=800, CH0 RK1
1374 23:50:50.251703
1375 23:50:50.251756 DATLAT Default: 0xa
1376 23:50:50.251809 0, 0xFFFF, sum = 0
1377 23:50:50.251864 1, 0xFFFF, sum = 0
1378 23:50:50.251918 2, 0xFFFF, sum = 0
1379 23:50:50.251973 3, 0xFFFF, sum = 0
1380 23:50:50.252041 4, 0xFFFF, sum = 0
1381 23:50:50.252106 5, 0xFFFF, sum = 0
1382 23:50:50.252162 6, 0xFFFF, sum = 0
1383 23:50:50.252216 7, 0xFFFF, sum = 0
1384 23:50:50.252270 8, 0xFFFF, sum = 0
1385 23:50:50.252325 9, 0x0, sum = 1
1386 23:50:50.252379 10, 0x0, sum = 2
1387 23:50:50.252434 11, 0x0, sum = 3
1388 23:50:50.252489 12, 0x0, sum = 4
1389 23:50:50.252543 best_step = 10
1390 23:50:50.252596
1391 23:50:50.252649 ==
1392 23:50:50.252896 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 23:50:50.252956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 23:50:50.253011 ==
1395 23:50:50.253066 RX Vref Scan: 0
1396 23:50:50.253119
1397 23:50:50.253172 RX Vref 0 -> 0, step: 1
1398 23:50:50.253225
1399 23:50:50.253317 RX Delay -95 -> 252, step: 8
1400 23:50:50.253372 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1401 23:50:50.253425 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1402 23:50:50.253479 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1403 23:50:50.253531 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1404 23:50:50.253585 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1405 23:50:50.253639 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1406 23:50:50.253693 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1407 23:50:50.253746 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1408 23:50:50.253799 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1409 23:50:50.253852 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1410 23:50:50.253906 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1411 23:50:50.253959 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1412 23:50:50.254012 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1413 23:50:50.254064 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1414 23:50:50.254118 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1415 23:50:50.254170 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1416 23:50:50.254223 ==
1417 23:50:50.254277 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 23:50:50.254330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 23:50:50.254384 ==
1420 23:50:50.254436 DQS Delay:
1421 23:50:50.254490 DQS0 = 0, DQS1 = 0
1422 23:50:50.254543 DQM Delay:
1423 23:50:50.254595 DQM0 = 86, DQM1 = 76
1424 23:50:50.254648 DQ Delay:
1425 23:50:50.254701 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1426 23:50:50.254754 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1427 23:50:50.254807 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1428 23:50:50.254860 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1429 23:50:50.254913
1430 23:50:50.254966
1431 23:50:50.255019 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1432 23:50:50.255073 CH0 RK1: MR19=606, MR18=2F2D
1433 23:50:50.255126 CH0_RK1: MR19=0x606, MR18=0x2F2D, DQSOSC=397, MR23=63, INC=93, DEC=62
1434 23:50:50.255179 [RxdqsGatingPostProcess] freq 800
1435 23:50:50.255233 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 23:50:50.255286 Pre-setting of DQS Precalculation
1437 23:50:50.255339 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1438 23:50:50.255392 ==
1439 23:50:50.255445 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 23:50:50.255498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 23:50:50.255551 ==
1442 23:50:50.255604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 23:50:50.255659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 23:50:50.255712 [CA 0] Center 37 (6~68) winsize 63
1445 23:50:50.255766 [CA 1] Center 37 (6~68) winsize 63
1446 23:50:50.255818 [CA 2] Center 35 (4~66) winsize 63
1447 23:50:50.255871 [CA 3] Center 34 (4~65) winsize 62
1448 23:50:50.255924 [CA 4] Center 35 (4~66) winsize 63
1449 23:50:50.255977 [CA 5] Center 34 (4~65) winsize 62
1450 23:50:50.256029
1451 23:50:50.256081 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1452 23:50:50.256134
1453 23:50:50.256186 [CATrainingPosCal] consider 1 rank data
1454 23:50:50.256239 u2DelayCellTimex100 = 270/100 ps
1455 23:50:50.256359 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1456 23:50:50.256412 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1457 23:50:50.256465 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1458 23:50:50.256517 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 23:50:50.256570 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1460 23:50:50.256623 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 23:50:50.256676
1462 23:50:50.256728 CA PerBit enable=1, Macro0, CA PI delay=34
1463 23:50:50.256781
1464 23:50:50.256833 [CBTSetCACLKResult] CA Dly = 34
1465 23:50:50.256917 CS Dly: 4 (0~35)
1466 23:50:50.256969 ==
1467 23:50:50.257022 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 23:50:50.257074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 23:50:50.257128 ==
1470 23:50:50.257180 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 23:50:50.257233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 23:50:50.257325 [CA 0] Center 36 (6~67) winsize 62
1473 23:50:50.257379 [CA 1] Center 36 (6~67) winsize 62
1474 23:50:50.257432 [CA 2] Center 35 (4~66) winsize 63
1475 23:50:50.257485 [CA 3] Center 34 (4~65) winsize 62
1476 23:50:50.257538 [CA 4] Center 34 (4~65) winsize 62
1477 23:50:50.257591 [CA 5] Center 34 (4~65) winsize 62
1478 23:50:50.257644
1479 23:50:50.257698 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1480 23:50:50.257751
1481 23:50:50.257804 [CATrainingPosCal] consider 2 rank data
1482 23:50:50.257859 u2DelayCellTimex100 = 270/100 ps
1483 23:50:50.257912 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 23:50:50.257965 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 23:50:50.258018 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1486 23:50:50.258133 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 23:50:50.258227 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 23:50:50.258349 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 23:50:50.258418
1490 23:50:50.258472 CA PerBit enable=1, Macro0, CA PI delay=34
1491 23:50:50.258526
1492 23:50:50.258580 [CBTSetCACLKResult] CA Dly = 34
1493 23:50:50.258633 CS Dly: 5 (0~37)
1494 23:50:50.258687
1495 23:50:50.258743 ----->DramcWriteLeveling(PI) begin...
1496 23:50:50.258797 ==
1497 23:50:50.258851 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 23:50:50.258904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 23:50:50.258958 ==
1500 23:50:50.259011 Write leveling (Byte 0): 24 => 24
1501 23:50:50.259065 Write leveling (Byte 1): 30 => 30
1502 23:50:50.259118 DramcWriteLeveling(PI) end<-----
1503 23:50:50.259171
1504 23:50:50.259252 ==
1505 23:50:50.259305 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 23:50:50.259358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 23:50:50.259412 ==
1508 23:50:50.259465 [Gating] SW mode calibration
1509 23:50:50.259518 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 23:50:50.259573 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 23:50:50.259626 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1512 23:50:50.259679 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:50:50.259733 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:50:50.259981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:50:50.260040 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:50:50.260097 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:50:50.260152 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:50:50.260205 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:50:50.260259 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:50:50.260313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:50:50.260367 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:50:50.260420 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:50:50.260473 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:50:50.260526 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:50:50.260580 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:50:50.260633 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:50:50.260686 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1528 23:50:50.260740 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1529 23:50:50.260793 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:50:50.260846 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:50:50.260899 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:50:50.260952 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:50:50.261005 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:50:50.261058 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:50:50.261112 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:50:50.261164 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1537 23:50:50.261217 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1538 23:50:50.261308 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 23:50:50.261363 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 23:50:50.261417 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 23:50:50.261470 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 23:50:50.261523 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 23:50:50.261609 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 23:50:50.261663 0 10 4 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
1545 23:50:50.261716 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1546 23:50:50.261769 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:50:50.261822 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:50:50.261876 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:50:50.261928 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:50:50.261982 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:50:50.262034 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:50:50.262088 0 11 4 | B1->B0 | 2424 2525 | 1 0 | (0 0) (0 0)
1553 23:50:50.262165 0 11 8 | B1->B0 | 3a3a 4242 | 1 0 | (0 0) (0 0)
1554 23:50:50.262234 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 23:50:50.262287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:50:50.262340 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 23:50:50.262393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 23:50:50.262446 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 23:50:50.262499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:50:50.262553 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1561 23:50:50.262606 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1562 23:50:50.262659 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:50:50.262713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:50:50.262766 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:50:50.262818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:50:50.262871 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:50:50.262923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:50:50.262977 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:50:50.263029 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:50:50.263082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:50:50.263135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:50:50.263188 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:50:50.263241 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:50:50.263294 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:50:50.263347 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:50:50.263400 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1577 23:50:50.263453 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 23:50:50.263505 Total UI for P1: 0, mck2ui 16
1579 23:50:50.263558 best dqsien dly found for B0: ( 0, 14, 4)
1580 23:50:50.263612 Total UI for P1: 0, mck2ui 16
1581 23:50:50.263665 best dqsien dly found for B1: ( 0, 14, 4)
1582 23:50:50.263719 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1583 23:50:50.263772 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1584 23:50:50.263825
1585 23:50:50.263878 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1586 23:50:50.263932 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1587 23:50:50.263985 [Gating] SW calibration Done
1588 23:50:50.264039 ==
1589 23:50:50.264092 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 23:50:50.264146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 23:50:50.264199 ==
1592 23:50:50.264252 RX Vref Scan: 0
1593 23:50:50.264305
1594 23:50:50.264358 RX Vref 0 -> 0, step: 1
1595 23:50:50.264411
1596 23:50:50.264463 RX Delay -130 -> 252, step: 16
1597 23:50:50.264516 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1598 23:50:50.264570 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1599 23:50:50.264623 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1600 23:50:50.264676 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1601 23:50:50.264730 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1602 23:50:50.264782 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1603 23:50:50.265030 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1604 23:50:50.265121 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1605 23:50:50.265176 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1606 23:50:50.265229 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1607 23:50:50.265329 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1608 23:50:50.265384 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1609 23:50:50.265438 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1610 23:50:50.265491 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1611 23:50:50.265544 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1612 23:50:50.265597 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1613 23:50:50.265650 ==
1614 23:50:50.265704 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 23:50:50.265758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 23:50:50.265812 ==
1617 23:50:50.265865 DQS Delay:
1618 23:50:50.265919 DQS0 = 0, DQS1 = 0
1619 23:50:50.265972 DQM Delay:
1620 23:50:50.266025 DQM0 = 88, DQM1 = 82
1621 23:50:50.266078 DQ Delay:
1622 23:50:50.266131 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1623 23:50:50.266184 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1624 23:50:50.266237 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1625 23:50:50.266290 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1626 23:50:50.266344
1627 23:50:50.266396
1628 23:50:50.266450 ==
1629 23:50:50.266505 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 23:50:50.266558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 23:50:50.266612 ==
1632 23:50:50.266666
1633 23:50:50.266719
1634 23:50:50.266771 TX Vref Scan disable
1635 23:50:50.266825 == TX Byte 0 ==
1636 23:50:50.266879 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1637 23:50:50.266932 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1638 23:50:50.266986 == TX Byte 1 ==
1639 23:50:50.267039 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1640 23:50:50.267093 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1641 23:50:50.267146 ==
1642 23:50:50.267200 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 23:50:50.267253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 23:50:50.267307 ==
1645 23:50:50.267360 TX Vref=22, minBit 6, minWin=26, winSum=440
1646 23:50:50.267413 TX Vref=24, minBit 0, minWin=27, winSum=443
1647 23:50:50.267467 TX Vref=26, minBit 1, minWin=27, winSum=448
1648 23:50:50.267521 TX Vref=28, minBit 1, minWin=27, winSum=449
1649 23:50:50.267575 TX Vref=30, minBit 2, minWin=27, winSum=453
1650 23:50:50.267628 TX Vref=32, minBit 1, minWin=27, winSum=451
1651 23:50:50.267682 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
1652 23:50:50.267735
1653 23:50:50.267788 Final TX Range 1 Vref 30
1654 23:50:50.267841
1655 23:50:50.267894 ==
1656 23:50:50.267947 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 23:50:50.268000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 23:50:50.268054 ==
1659 23:50:50.268107
1660 23:50:50.268160
1661 23:50:50.268212 TX Vref Scan disable
1662 23:50:50.268265 == TX Byte 0 ==
1663 23:50:50.268317 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1664 23:50:50.268371 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1665 23:50:50.268424 == TX Byte 1 ==
1666 23:50:50.268477 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1667 23:50:50.268530 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1668 23:50:50.268583
1669 23:50:50.268637 [DATLAT]
1670 23:50:50.268689 Freq=800, CH1 RK0
1671 23:50:50.268742
1672 23:50:50.268795 DATLAT Default: 0xa
1673 23:50:50.268849 0, 0xFFFF, sum = 0
1674 23:50:50.268903 1, 0xFFFF, sum = 0
1675 23:50:50.268958 2, 0xFFFF, sum = 0
1676 23:50:50.269012 3, 0xFFFF, sum = 0
1677 23:50:50.269066 4, 0xFFFF, sum = 0
1678 23:50:50.269120 5, 0xFFFF, sum = 0
1679 23:50:50.269174 6, 0xFFFF, sum = 0
1680 23:50:50.269228 7, 0xFFFF, sum = 0
1681 23:50:50.269325 8, 0xFFFF, sum = 0
1682 23:50:50.269409 9, 0x0, sum = 1
1683 23:50:50.269463 10, 0x0, sum = 2
1684 23:50:50.269517 11, 0x0, sum = 3
1685 23:50:50.269572 12, 0x0, sum = 4
1686 23:50:50.269625 best_step = 10
1687 23:50:50.269678
1688 23:50:50.269731 ==
1689 23:50:50.269785 Dram Type= 6, Freq= 0, CH_1, rank 0
1690 23:50:50.269838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1691 23:50:50.269892 ==
1692 23:50:50.269946 RX Vref Scan: 1
1693 23:50:50.269999
1694 23:50:50.270051 Set Vref Range= 32 -> 127
1695 23:50:50.270104
1696 23:50:50.270156 RX Vref 32 -> 127, step: 1
1697 23:50:50.270209
1698 23:50:50.270262 RX Delay -79 -> 252, step: 8
1699 23:50:50.270315
1700 23:50:50.270368 Set Vref, RX VrefLevel [Byte0]: 32
1701 23:50:50.270421 [Byte1]: 32
1702 23:50:50.270474
1703 23:50:50.270527 Set Vref, RX VrefLevel [Byte0]: 33
1704 23:50:50.270580 [Byte1]: 33
1705 23:50:50.270633
1706 23:50:50.270686 Set Vref, RX VrefLevel [Byte0]: 34
1707 23:50:50.270739 [Byte1]: 34
1708 23:50:50.270792
1709 23:50:50.270844 Set Vref, RX VrefLevel [Byte0]: 35
1710 23:50:50.270897 [Byte1]: 35
1711 23:50:50.270950
1712 23:50:50.271002 Set Vref, RX VrefLevel [Byte0]: 36
1713 23:50:50.271055 [Byte1]: 36
1714 23:50:50.271109
1715 23:50:50.271162 Set Vref, RX VrefLevel [Byte0]: 37
1716 23:50:50.271215 [Byte1]: 37
1717 23:50:50.271269
1718 23:50:50.271321 Set Vref, RX VrefLevel [Byte0]: 38
1719 23:50:50.271374 [Byte1]: 38
1720 23:50:50.271428
1721 23:50:50.271481 Set Vref, RX VrefLevel [Byte0]: 39
1722 23:50:50.271533 [Byte1]: 39
1723 23:50:50.271586
1724 23:50:50.271639 Set Vref, RX VrefLevel [Byte0]: 40
1725 23:50:50.271692 [Byte1]: 40
1726 23:50:50.271745
1727 23:50:50.271798 Set Vref, RX VrefLevel [Byte0]: 41
1728 23:50:50.271850 [Byte1]: 41
1729 23:50:50.271904
1730 23:50:50.271956 Set Vref, RX VrefLevel [Byte0]: 42
1731 23:50:50.272009 [Byte1]: 42
1732 23:50:50.272061
1733 23:50:50.272114 Set Vref, RX VrefLevel [Byte0]: 43
1734 23:50:50.272167 [Byte1]: 43
1735 23:50:50.272219
1736 23:50:50.272271 Set Vref, RX VrefLevel [Byte0]: 44
1737 23:50:50.272324 [Byte1]: 44
1738 23:50:50.272376
1739 23:50:50.272429 Set Vref, RX VrefLevel [Byte0]: 45
1740 23:50:50.272481 [Byte1]: 45
1741 23:50:50.272534
1742 23:50:50.272586 Set Vref, RX VrefLevel [Byte0]: 46
1743 23:50:50.272639 [Byte1]: 46
1744 23:50:50.272692
1745 23:50:50.272744 Set Vref, RX VrefLevel [Byte0]: 47
1746 23:50:50.272797 [Byte1]: 47
1747 23:50:50.272849
1748 23:50:50.272902 Set Vref, RX VrefLevel [Byte0]: 48
1749 23:50:50.272954 [Byte1]: 48
1750 23:50:50.273008
1751 23:50:50.273060 Set Vref, RX VrefLevel [Byte0]: 49
1752 23:50:50.273113 [Byte1]: 49
1753 23:50:50.273165
1754 23:50:50.273217 Set Vref, RX VrefLevel [Byte0]: 50
1755 23:50:50.273308 [Byte1]: 50
1756 23:50:50.273364
1757 23:50:50.273417 Set Vref, RX VrefLevel [Byte0]: 51
1758 23:50:50.273469 [Byte1]: 51
1759 23:50:50.273523
1760 23:50:50.273576 Set Vref, RX VrefLevel [Byte0]: 52
1761 23:50:50.273629 [Byte1]: 52
1762 23:50:50.273681
1763 23:50:50.273734 Set Vref, RX VrefLevel [Byte0]: 53
1764 23:50:50.273977 [Byte1]: 53
1765 23:50:50.274059
1766 23:50:50.274126 Set Vref, RX VrefLevel [Byte0]: 54
1767 23:50:50.274180 [Byte1]: 54
1768 23:50:50.274234
1769 23:50:50.274288 Set Vref, RX VrefLevel [Byte0]: 55
1770 23:50:50.274369 [Byte1]: 55
1771 23:50:50.274422
1772 23:50:50.274475 Set Vref, RX VrefLevel [Byte0]: 56
1773 23:50:50.274528 [Byte1]: 56
1774 23:50:50.274580
1775 23:50:50.274660 Set Vref, RX VrefLevel [Byte0]: 57
1776 23:50:50.274713 [Byte1]: 57
1777 23:50:50.274766
1778 23:50:50.274819 Set Vref, RX VrefLevel [Byte0]: 58
1779 23:50:50.274872 [Byte1]: 58
1780 23:50:50.274954
1781 23:50:50.275019 Set Vref, RX VrefLevel [Byte0]: 59
1782 23:50:50.275074 [Byte1]: 59
1783 23:50:50.275127
1784 23:50:50.275180 Set Vref, RX VrefLevel [Byte0]: 60
1785 23:50:50.275233 [Byte1]: 60
1786 23:50:50.275285
1787 23:50:50.275338 Set Vref, RX VrefLevel [Byte0]: 61
1788 23:50:50.275391 [Byte1]: 61
1789 23:50:50.275444
1790 23:50:50.275497 Set Vref, RX VrefLevel [Byte0]: 62
1791 23:50:50.275550 [Byte1]: 62
1792 23:50:50.275603
1793 23:50:50.275656 Set Vref, RX VrefLevel [Byte0]: 63
1794 23:50:50.275709 [Byte1]: 63
1795 23:50:50.275762
1796 23:50:50.275815 Set Vref, RX VrefLevel [Byte0]: 64
1797 23:50:50.275868 [Byte1]: 64
1798 23:50:50.275922
1799 23:50:50.275976 Set Vref, RX VrefLevel [Byte0]: 65
1800 23:50:50.276029 [Byte1]: 65
1801 23:50:50.276081
1802 23:50:50.276134 Set Vref, RX VrefLevel [Byte0]: 66
1803 23:50:50.276187 [Byte1]: 66
1804 23:50:50.276239
1805 23:50:50.276293 Set Vref, RX VrefLevel [Byte0]: 67
1806 23:50:50.276345 [Byte1]: 67
1807 23:50:50.276398
1808 23:50:50.276451 Set Vref, RX VrefLevel [Byte0]: 68
1809 23:50:50.276504 [Byte1]: 68
1810 23:50:50.276557
1811 23:50:50.276610 Set Vref, RX VrefLevel [Byte0]: 69
1812 23:50:50.276663 [Byte1]: 69
1813 23:50:50.276716
1814 23:50:50.276769 Set Vref, RX VrefLevel [Byte0]: 70
1815 23:50:50.276822 [Byte1]: 70
1816 23:50:50.276876
1817 23:50:50.276928 Set Vref, RX VrefLevel [Byte0]: 71
1818 23:50:50.276982 [Byte1]: 71
1819 23:50:50.277035
1820 23:50:50.277088 Set Vref, RX VrefLevel [Byte0]: 72
1821 23:50:50.277142 [Byte1]: 72
1822 23:50:50.277195
1823 23:50:50.277248 Set Vref, RX VrefLevel [Byte0]: 73
1824 23:50:50.277343 [Byte1]: 73
1825 23:50:50.277397
1826 23:50:50.277449 Set Vref, RX VrefLevel [Byte0]: 74
1827 23:50:50.277502 [Byte1]: 74
1828 23:50:50.277556
1829 23:50:50.277609 Set Vref, RX VrefLevel [Byte0]: 75
1830 23:50:50.277662 [Byte1]: 75
1831 23:50:50.277714
1832 23:50:50.277767 Final RX Vref Byte 0 = 55 to rank0
1833 23:50:50.277821 Final RX Vref Byte 1 = 55 to rank0
1834 23:50:50.277875 Final RX Vref Byte 0 = 55 to rank1
1835 23:50:50.277928 Final RX Vref Byte 1 = 55 to rank1==
1836 23:50:50.277982 Dram Type= 6, Freq= 0, CH_1, rank 0
1837 23:50:50.278035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1838 23:50:50.278089 ==
1839 23:50:50.278142 DQS Delay:
1840 23:50:50.278196 DQS0 = 0, DQS1 = 0
1841 23:50:50.278249 DQM Delay:
1842 23:50:50.278302 DQM0 = 86, DQM1 = 80
1843 23:50:50.278355 DQ Delay:
1844 23:50:50.278408 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1845 23:50:50.278461 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =84
1846 23:50:50.278514 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1847 23:50:50.278567 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1848 23:50:50.278620
1849 23:50:50.278673
1850 23:50:50.278725 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d30, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1851 23:50:50.278780 CH1 RK0: MR19=606, MR18=1D30
1852 23:50:50.278833 CH1_RK0: MR19=0x606, MR18=0x1D30, DQSOSC=397, MR23=63, INC=93, DEC=62
1853 23:50:50.278887
1854 23:50:50.278940 ----->DramcWriteLeveling(PI) begin...
1855 23:50:50.278995 ==
1856 23:50:50.279047 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 23:50:50.279101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 23:50:50.279155 ==
1859 23:50:50.279207 Write leveling (Byte 0): 25 => 25
1860 23:50:50.279260 Write leveling (Byte 1): 29 => 29
1861 23:50:50.279314 DramcWriteLeveling(PI) end<-----
1862 23:50:50.279367
1863 23:50:50.279419 ==
1864 23:50:50.279472 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 23:50:50.279525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 23:50:50.279579 ==
1867 23:50:50.279632 [Gating] SW mode calibration
1868 23:50:50.279685 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1869 23:50:50.279739 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1870 23:50:50.279793 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1871 23:50:50.279847 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1872 23:50:50.279901 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1873 23:50:50.279954 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:50:50.280007 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:50:50.280061 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:50:50.280114 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:50:50.280167 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:50:50.280220 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:50:50.280275 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:50:50.280328 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:50:50.280382 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:50:50.280435 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:50:50.280488 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:50:50.280541 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:50:50.280595 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:50:50.280647 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:50:50.280701 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1888 23:50:50.280753 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:50:50.280807 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:50:50.280860 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:50:50.280913 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:50:50.280966 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:50:50.281212 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:50:50.281313 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:50:50.281406 0 9 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1896 23:50:50.281460 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1897 23:50:50.281513 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 23:50:50.281567 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:50:50.281634 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 23:50:50.281702 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 23:50:50.281755 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 23:50:50.281808 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1903 23:50:50.281862 0 10 4 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
1904 23:50:50.281915 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:50:50.281969 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:50:50.282022 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:50:50.282075 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:50:50.282128 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:50:50.282182 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:50:50.282235 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:50:50.282288 0 11 4 | B1->B0 | 2525 3939 | 0 1 | (0 0) (0 0)
1912 23:50:50.282343 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1913 23:50:50.282396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:50:50.282449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:50:50.282502 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:50:50.282556 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 23:50:50.282609 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 23:50:50.282662 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1919 23:50:50.282715 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:50:50.282769 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:50:50.282822 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:50:50.282875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:50:50.282929 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:50:50.282982 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:50:50.283036 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:50:50.283088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:50:50.283141 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:50:50.283195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:50:50.283248 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:50:50.283301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:50:50.283354 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:50:50.283408 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:50:50.283461 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:50:50.283514 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1935 23:50:50.283567 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1936 23:50:50.283620 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1937 23:50:50.283673 Total UI for P1: 0, mck2ui 16
1938 23:50:50.283726 best dqsien dly found for B0: ( 0, 14, 2)
1939 23:50:50.283780 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 23:50:50.283833 Total UI for P1: 0, mck2ui 16
1941 23:50:50.283887 best dqsien dly found for B1: ( 0, 14, 6)
1942 23:50:50.283940 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1943 23:50:50.283993 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1944 23:50:50.284047
1945 23:50:50.284100 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1946 23:50:50.284153 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1947 23:50:50.284207 [Gating] SW calibration Done
1948 23:50:50.284260 ==
1949 23:50:50.284313 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:50:50.284367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:50:50.284420 ==
1952 23:50:50.284473 RX Vref Scan: 0
1953 23:50:50.284526
1954 23:50:50.284578 RX Vref 0 -> 0, step: 1
1955 23:50:50.284631
1956 23:50:50.284684 RX Delay -130 -> 252, step: 16
1957 23:50:50.284737 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1958 23:50:50.284791 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1959 23:50:50.284845 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1960 23:50:50.284898 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1961 23:50:50.284951 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1962 23:50:50.285005 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1963 23:50:50.285058 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1964 23:50:50.285111 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1965 23:50:50.285164 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1966 23:50:50.285217 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1967 23:50:50.285308 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1968 23:50:50.285362 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1969 23:50:50.285415 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1970 23:50:50.285469 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1971 23:50:50.285522 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1972 23:50:50.285576 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1973 23:50:50.285629 ==
1974 23:50:50.285683 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 23:50:50.285736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 23:50:50.285790 ==
1977 23:50:50.285843 DQS Delay:
1978 23:50:50.285895 DQS0 = 0, DQS1 = 0
1979 23:50:50.285948 DQM Delay:
1980 23:50:50.286001 DQM0 = 85, DQM1 = 81
1981 23:50:50.286054 DQ Delay:
1982 23:50:50.286107 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1983 23:50:50.286160 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1984 23:50:50.286213 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1985 23:50:50.417156 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1986 23:50:50.417290
1987 23:50:50.417372
1988 23:50:50.417433 ==
1989 23:50:50.417493 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 23:50:50.417551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 23:50:50.417608 ==
1992 23:50:50.417664
1993 23:50:50.417719
1994 23:50:50.417773 TX Vref Scan disable
1995 23:50:50.417828 == TX Byte 0 ==
1996 23:50:50.417881 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1997 23:50:50.417937 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1998 23:50:50.417991 == TX Byte 1 ==
1999 23:50:50.418247 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2000 23:50:50.418345 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2001 23:50:50.418400 ==
2002 23:50:50.418455 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 23:50:50.418510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 23:50:50.418564 ==
2005 23:50:50.418618 TX Vref=22, minBit 1, minWin=26, winSum=442
2006 23:50:50.418673 TX Vref=24, minBit 1, minWin=26, winSum=445
2007 23:50:50.418727 TX Vref=26, minBit 2, minWin=27, winSum=449
2008 23:50:50.418781 TX Vref=28, minBit 2, minWin=27, winSum=453
2009 23:50:50.418835 TX Vref=30, minBit 2, minWin=27, winSum=454
2010 23:50:50.418889 TX Vref=32, minBit 2, minWin=27, winSum=453
2011 23:50:50.418942 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 30
2012 23:50:50.418997
2013 23:50:50.419050 Final TX Range 1 Vref 30
2014 23:50:50.419103
2015 23:50:50.419156 ==
2016 23:50:50.419209 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 23:50:50.419263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 23:50:50.419317 ==
2019 23:50:50.419371
2020 23:50:50.419424
2021 23:50:50.419477 TX Vref Scan disable
2022 23:50:50.419531 == TX Byte 0 ==
2023 23:50:50.419584 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2024 23:50:50.419638 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2025 23:50:50.419691 == TX Byte 1 ==
2026 23:50:50.419744 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2027 23:50:50.419798 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2028 23:50:50.419852
2029 23:50:50.419904 [DATLAT]
2030 23:50:50.419957 Freq=800, CH1 RK1
2031 23:50:50.420010
2032 23:50:50.420064 DATLAT Default: 0xa
2033 23:50:50.420117 0, 0xFFFF, sum = 0
2034 23:50:50.420172 1, 0xFFFF, sum = 0
2035 23:50:50.420226 2, 0xFFFF, sum = 0
2036 23:50:50.420281 3, 0xFFFF, sum = 0
2037 23:50:50.420335 4, 0xFFFF, sum = 0
2038 23:50:50.420390 5, 0xFFFF, sum = 0
2039 23:50:50.420444 6, 0xFFFF, sum = 0
2040 23:50:50.420498 7, 0xFFFF, sum = 0
2041 23:50:50.420552 8, 0xFFFF, sum = 0
2042 23:50:50.420606 9, 0x0, sum = 1
2043 23:50:50.420660 10, 0x0, sum = 2
2044 23:50:50.420714 11, 0x0, sum = 3
2045 23:50:50.420768 12, 0x0, sum = 4
2046 23:50:50.420822 best_step = 10
2047 23:50:50.420875
2048 23:50:50.420928 ==
2049 23:50:50.420981 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 23:50:50.421035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 23:50:50.421088 ==
2052 23:50:50.421141 RX Vref Scan: 0
2053 23:50:50.421208
2054 23:50:50.421269 RX Vref 0 -> 0, step: 1
2055 23:50:50.421337
2056 23:50:50.421390 RX Delay -95 -> 252, step: 8
2057 23:50:50.421443 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
2058 23:50:50.421498 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2059 23:50:50.421551 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2060 23:50:50.421604 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2061 23:50:50.421658 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2062 23:50:50.421711 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2063 23:50:50.421765 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2064 23:50:50.421817 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2065 23:50:50.421871 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2066 23:50:50.421924 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2067 23:50:50.421978 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2068 23:50:50.422031 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2069 23:50:50.422085 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2070 23:50:50.422138 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2071 23:50:50.422192 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2072 23:50:50.422245 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2073 23:50:50.422298 ==
2074 23:50:50.422351 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 23:50:50.422434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 23:50:50.422488 ==
2077 23:50:50.422542 DQS Delay:
2078 23:50:50.422595 DQS0 = 0, DQS1 = 0
2079 23:50:50.422649 DQM Delay:
2080 23:50:50.422702 DQM0 = 87, DQM1 = 83
2081 23:50:50.422754 DQ Delay:
2082 23:50:50.422808 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2083 23:50:50.422862 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2084 23:50:50.422915 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =76
2085 23:50:50.422969 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =88
2086 23:50:50.423022
2087 23:50:50.423076
2088 23:50:50.423129 [DQSOSCAuto] RK1, (LSB)MR18= 0x233f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 401 ps
2089 23:50:50.423184 CH1 RK1: MR19=606, MR18=233F
2090 23:50:50.423252 CH1_RK1: MR19=0x606, MR18=0x233F, DQSOSC=393, MR23=63, INC=95, DEC=63
2091 23:50:50.423320 [RxdqsGatingPostProcess] freq 800
2092 23:50:50.423373 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 23:50:50.423427 Pre-setting of DQS Precalculation
2094 23:50:50.423480 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 23:50:50.423548 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 23:50:50.423616 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 23:50:50.423671
2098 23:50:50.423724
2099 23:50:50.423777 [Calibration Summary] 1600 Mbps
2100 23:50:50.423831 CH 0, Rank 0
2101 23:50:50.423885 SW Impedance : PASS
2102 23:50:50.423938 DUTY Scan : NO K
2103 23:50:50.423991 ZQ Calibration : PASS
2104 23:50:50.424044 Jitter Meter : NO K
2105 23:50:50.424098 CBT Training : PASS
2106 23:50:50.424151 Write leveling : PASS
2107 23:50:50.424204 RX DQS gating : PASS
2108 23:50:50.424257 RX DQ/DQS(RDDQC) : PASS
2109 23:50:50.424311 TX DQ/DQS : PASS
2110 23:50:50.424365 RX DATLAT : PASS
2111 23:50:50.424440 RX DQ/DQS(Engine): PASS
2112 23:50:50.424507 TX OE : NO K
2113 23:50:50.424561 All Pass.
2114 23:50:50.424615
2115 23:50:50.424668 CH 0, Rank 1
2116 23:50:50.424721 SW Impedance : PASS
2117 23:50:50.424775 DUTY Scan : NO K
2118 23:50:50.424828 ZQ Calibration : PASS
2119 23:50:50.424881 Jitter Meter : NO K
2120 23:50:50.424934 CBT Training : PASS
2121 23:50:50.424987 Write leveling : PASS
2122 23:50:50.425040 RX DQS gating : PASS
2123 23:50:50.425092 RX DQ/DQS(RDDQC) : PASS
2124 23:50:50.425145 TX DQ/DQS : PASS
2125 23:50:50.425200 RX DATLAT : PASS
2126 23:50:50.425253 RX DQ/DQS(Engine): PASS
2127 23:50:50.425348 TX OE : NO K
2128 23:50:50.425403 All Pass.
2129 23:50:50.425457
2130 23:50:50.425510 CH 1, Rank 0
2131 23:50:50.425563 SW Impedance : PASS
2132 23:50:50.425617 DUTY Scan : NO K
2133 23:50:50.425671 ZQ Calibration : PASS
2134 23:50:50.425724 Jitter Meter : NO K
2135 23:50:50.425777 CBT Training : PASS
2136 23:50:50.425831 Write leveling : PASS
2137 23:50:50.425884 RX DQS gating : PASS
2138 23:50:50.425938 RX DQ/DQS(RDDQC) : PASS
2139 23:50:50.425991 TX DQ/DQS : PASS
2140 23:50:50.426045 RX DATLAT : PASS
2141 23:50:50.426098 RX DQ/DQS(Engine): PASS
2142 23:50:50.426151 TX OE : NO K
2143 23:50:50.426204 All Pass.
2144 23:50:50.426257
2145 23:50:50.426310 CH 1, Rank 1
2146 23:50:50.426363 SW Impedance : PASS
2147 23:50:50.426658 DUTY Scan : NO K
2148 23:50:50.426765 ZQ Calibration : PASS
2149 23:50:50.426834 Jitter Meter : NO K
2150 23:50:50.426888 CBT Training : PASS
2151 23:50:50.426942 Write leveling : PASS
2152 23:50:50.426996 RX DQS gating : PASS
2153 23:50:50.427050 RX DQ/DQS(RDDQC) : PASS
2154 23:50:50.427104 TX DQ/DQS : PASS
2155 23:50:50.427175 RX DATLAT : PASS
2156 23:50:50.427230 RX DQ/DQS(Engine): PASS
2157 23:50:50.427285 TX OE : NO K
2158 23:50:50.427340 All Pass.
2159 23:50:50.427395
2160 23:50:50.427450 DramC Write-DBI off
2161 23:50:50.427505 PER_BANK_REFRESH: Hybrid Mode
2162 23:50:50.427559 TX_TRACKING: ON
2163 23:50:50.427615 [GetDramInforAfterCalByMRR] Vendor 6.
2164 23:50:50.427670 [GetDramInforAfterCalByMRR] Revision 606.
2165 23:50:50.427726 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 23:50:50.427781 MR0 0x3b3b
2167 23:50:50.427835 MR8 0x5151
2168 23:50:50.427891 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 23:50:50.427946
2170 23:50:50.428000 MR0 0x3b3b
2171 23:50:50.428054 MR8 0x5151
2172 23:50:50.428109 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 23:50:50.428164
2174 23:50:50.428218 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 23:50:50.428274 [FAST_K] Save calibration result to emmc
2176 23:50:50.428328 [FAST_K] Save calibration result to emmc
2177 23:50:50.428383 dram_init: config_dvfs: 1
2178 23:50:50.428439 dramc_set_vcore_voltage set vcore to 662500
2179 23:50:50.428494 Read voltage for 1200, 2
2180 23:50:50.428549 Vio18 = 0
2181 23:50:50.428603 Vcore = 662500
2182 23:50:50.428658 Vdram = 0
2183 23:50:50.428713 Vddq = 0
2184 23:50:50.428767 Vmddr = 0
2185 23:50:50.428822 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 23:50:50.428877 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 23:50:50.428933 MEM_TYPE=3, freq_sel=15
2188 23:50:50.428988 sv_algorithm_assistance_LP4_1600
2189 23:50:50.429043 ============ PULL DRAM RESETB DOWN ============
2190 23:50:50.429099 ========== PULL DRAM RESETB DOWN end =========
2191 23:50:50.429154 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 23:50:50.429209 ===================================
2193 23:50:50.429272 LPDDR4 DRAM CONFIGURATION
2194 23:50:50.429342 ===================================
2195 23:50:50.429409 EX_ROW_EN[0] = 0x0
2196 23:50:50.429478 EX_ROW_EN[1] = 0x0
2197 23:50:50.429531 LP4Y_EN = 0x0
2198 23:50:50.429585 WORK_FSP = 0x0
2199 23:50:50.429639 WL = 0x4
2200 23:50:50.429706 RL = 0x4
2201 23:50:50.429774 BL = 0x2
2202 23:50:50.429828 RPST = 0x0
2203 23:50:50.429881 RD_PRE = 0x0
2204 23:50:50.429935 WR_PRE = 0x1
2205 23:50:50.430002 WR_PST = 0x0
2206 23:50:50.430068 DBI_WR = 0x0
2207 23:50:50.430121 DBI_RD = 0x0
2208 23:50:50.430175 OTF = 0x1
2209 23:50:50.430229 ===================================
2210 23:50:50.430297 ===================================
2211 23:50:50.430365 ANA top config
2212 23:50:50.430450 ===================================
2213 23:50:50.430504 DLL_ASYNC_EN = 0
2214 23:50:50.430557 ALL_SLAVE_EN = 0
2215 23:50:50.430611 NEW_RANK_MODE = 1
2216 23:50:50.430665 DLL_IDLE_MODE = 1
2217 23:50:50.430719 LP45_APHY_COMB_EN = 1
2218 23:50:50.430772 TX_ODT_DIS = 1
2219 23:50:50.430826 NEW_8X_MODE = 1
2220 23:50:50.430903 ===================================
2221 23:50:50.430971 ===================================
2222 23:50:50.431025 data_rate = 2400
2223 23:50:50.431078 CKR = 1
2224 23:50:50.431132 DQ_P2S_RATIO = 8
2225 23:50:50.431186 ===================================
2226 23:50:50.431239 CA_P2S_RATIO = 8
2227 23:50:50.431293 DQ_CA_OPEN = 0
2228 23:50:50.431346 DQ_SEMI_OPEN = 0
2229 23:50:50.431400 CA_SEMI_OPEN = 0
2230 23:50:50.431453 CA_FULL_RATE = 0
2231 23:50:50.431506 DQ_CKDIV4_EN = 0
2232 23:50:50.431560 CA_CKDIV4_EN = 0
2233 23:50:50.431613 CA_PREDIV_EN = 0
2234 23:50:50.431666 PH8_DLY = 17
2235 23:50:50.431720 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 23:50:50.431773 DQ_AAMCK_DIV = 4
2237 23:50:50.431827 CA_AAMCK_DIV = 4
2238 23:50:50.431880 CA_ADMCK_DIV = 4
2239 23:50:50.431934 DQ_TRACK_CA_EN = 0
2240 23:50:50.431987 CA_PICK = 1200
2241 23:50:50.432040 CA_MCKIO = 1200
2242 23:50:50.432094 MCKIO_SEMI = 0
2243 23:50:50.432147 PLL_FREQ = 2366
2244 23:50:50.432200 DQ_UI_PI_RATIO = 32
2245 23:50:50.432254 CA_UI_PI_RATIO = 0
2246 23:50:50.432307 ===================================
2247 23:50:50.432360 ===================================
2248 23:50:50.432430 memory_type:LPDDR4
2249 23:50:50.432497 GP_NUM : 10
2250 23:50:50.432551 SRAM_EN : 1
2251 23:50:50.432605 MD32_EN : 0
2252 23:50:50.432659 ===================================
2253 23:50:50.432713 [ANA_INIT] >>>>>>>>>>>>>>
2254 23:50:50.432767 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 23:50:50.432821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 23:50:50.432875 ===================================
2257 23:50:50.432929 data_rate = 2400,PCW = 0X5b00
2258 23:50:50.432983 ===================================
2259 23:50:50.433037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 23:50:50.433091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 23:50:50.433145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 23:50:50.433200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 23:50:50.433253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 23:50:50.433343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 23:50:50.433397 [ANA_INIT] flow start
2266 23:50:50.433451 [ANA_INIT] PLL >>>>>>>>
2267 23:50:50.433505 [ANA_INIT] PLL <<<<<<<<
2268 23:50:50.433559 [ANA_INIT] MIDPI >>>>>>>>
2269 23:50:50.433612 [ANA_INIT] MIDPI <<<<<<<<
2270 23:50:50.433665 [ANA_INIT] DLL >>>>>>>>
2271 23:50:50.433719 [ANA_INIT] DLL <<<<<<<<
2272 23:50:50.433772 [ANA_INIT] flow end
2273 23:50:50.433826 ============ LP4 DIFF to SE enter ============
2274 23:50:50.433880 ============ LP4 DIFF to SE exit ============
2275 23:50:50.433935 [ANA_INIT] <<<<<<<<<<<<<
2276 23:50:50.433988 [Flow] Enable top DCM control >>>>>
2277 23:50:50.434069 [Flow] Enable top DCM control <<<<<
2278 23:50:50.434153 Enable DLL master slave shuffle
2279 23:50:50.434414 ==============================================================
2280 23:50:50.434488 Gating Mode config
2281 23:50:50.434543 ==============================================================
2282 23:50:50.434598 Config description:
2283 23:50:50.434652 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 23:50:50.434707 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 23:50:50.434761 SELPH_MODE 0: By rank 1: By Phase
2286 23:50:50.434830 ==============================================================
2287 23:50:50.434898 GAT_TRACK_EN = 1
2288 23:50:50.434980 RX_GATING_MODE = 2
2289 23:50:50.435033 RX_GATING_TRACK_MODE = 2
2290 23:50:50.435087 SELPH_MODE = 1
2291 23:50:50.435140 PICG_EARLY_EN = 1
2292 23:50:50.435194 VALID_LAT_VALUE = 1
2293 23:50:50.435247 ==============================================================
2294 23:50:50.435301 Enter into Gating configuration >>>>
2295 23:50:50.435355 Exit from Gating configuration <<<<
2296 23:50:50.435408 Enter into DVFS_PRE_config >>>>>
2297 23:50:50.435463 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 23:50:50.435518 Exit from DVFS_PRE_config <<<<<
2299 23:50:50.435572 Enter into PICG configuration >>>>
2300 23:50:50.435626 Exit from PICG configuration <<<<
2301 23:50:50.435680 [RX_INPUT] configuration >>>>>
2302 23:50:50.435734 [RX_INPUT] configuration <<<<<
2303 23:50:50.435788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 23:50:50.435842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 23:50:50.435897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 23:50:50.435951 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 23:50:50.436005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 23:50:50.436059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 23:50:50.436114 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 23:50:50.436167 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 23:50:50.436221 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 23:50:50.436275 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 23:50:50.436329 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 23:50:50.436399 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 23:50:50.436467 ===================================
2316 23:50:50.436521 LPDDR4 DRAM CONFIGURATION
2317 23:50:50.436575 ===================================
2318 23:50:50.436629 EX_ROW_EN[0] = 0x0
2319 23:50:50.436682 EX_ROW_EN[1] = 0x0
2320 23:50:50.436735 LP4Y_EN = 0x0
2321 23:50:50.436789 WORK_FSP = 0x0
2322 23:50:50.436842 WL = 0x4
2323 23:50:50.436895 RL = 0x4
2324 23:50:50.436948 BL = 0x2
2325 23:50:50.437001 RPST = 0x0
2326 23:50:50.437054 RD_PRE = 0x0
2327 23:50:50.437107 WR_PRE = 0x1
2328 23:50:50.437161 WR_PST = 0x0
2329 23:50:50.437214 DBI_WR = 0x0
2330 23:50:50.437290 DBI_RD = 0x0
2331 23:50:50.437371 OTF = 0x1
2332 23:50:50.437439 ===================================
2333 23:50:50.437493 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 23:50:50.437547 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 23:50:50.437601 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 23:50:50.437655 ===================================
2337 23:50:50.437710 LPDDR4 DRAM CONFIGURATION
2338 23:50:50.437764 ===================================
2339 23:50:50.437817 EX_ROW_EN[0] = 0x10
2340 23:50:50.437871 EX_ROW_EN[1] = 0x0
2341 23:50:50.437925 LP4Y_EN = 0x0
2342 23:50:50.437978 WORK_FSP = 0x0
2343 23:50:50.438031 WL = 0x4
2344 23:50:50.438084 RL = 0x4
2345 23:50:50.438138 BL = 0x2
2346 23:50:50.438191 RPST = 0x0
2347 23:50:50.438245 RD_PRE = 0x0
2348 23:50:50.438298 WR_PRE = 0x1
2349 23:50:50.438351 WR_PST = 0x0
2350 23:50:50.438441 DBI_WR = 0x0
2351 23:50:50.438496 DBI_RD = 0x0
2352 23:50:50.438549 OTF = 0x1
2353 23:50:50.438603 ===================================
2354 23:50:50.438658 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 23:50:50.438713 ==
2356 23:50:50.438767 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 23:50:50.438821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 23:50:50.438876 ==
2359 23:50:50.438948 [Duty_Offset_Calibration]
2360 23:50:50.439016 B0:2 B1:0 CA:4
2361 23:50:50.439068
2362 23:50:50.439122 [DutyScan_Calibration_Flow] k_type=0
2363 23:50:50.439175
2364 23:50:50.439227 ==CLK 0==
2365 23:50:50.439280 Final CLK duty delay cell = -4
2366 23:50:50.439334 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2367 23:50:50.439387 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2368 23:50:50.439440 [-4] AVG Duty = 4937%(X100)
2369 23:50:50.439494
2370 23:50:50.439546 CH0 CLK Duty spec in!! Max-Min= 187%
2371 23:50:50.439599 [DutyScan_Calibration_Flow] ====Done====
2372 23:50:50.439653
2373 23:50:50.439705 [DutyScan_Calibration_Flow] k_type=1
2374 23:50:50.439758
2375 23:50:50.439850 ==DQS 0 ==
2376 23:50:50.439904 Final DQS duty delay cell = 0
2377 23:50:50.439957 [0] MAX Duty = 5156%(X100), DQS PI = 18
2378 23:50:50.440011 [0] MIN Duty = 5093%(X100), DQS PI = 0
2379 23:50:50.440064 [0] AVG Duty = 5124%(X100)
2380 23:50:50.440117
2381 23:50:50.440170 ==DQS 1 ==
2382 23:50:50.440224 Final DQS duty delay cell = 0
2383 23:50:50.440277 [0] MAX Duty = 5093%(X100), DQS PI = 4
2384 23:50:50.440330 [0] MIN Duty = 4969%(X100), DQS PI = 14
2385 23:50:50.440414 [0] AVG Duty = 5031%(X100)
2386 23:50:50.440478
2387 23:50:50.440531 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2388 23:50:50.440585
2389 23:50:50.440638 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2390 23:50:50.440691 [DutyScan_Calibration_Flow] ====Done====
2391 23:50:50.440773
2392 23:50:50.440826 [DutyScan_Calibration_Flow] k_type=3
2393 23:50:50.440879
2394 23:50:50.440932 ==DQM 0 ==
2395 23:50:50.440986 Final DQM duty delay cell = 0
2396 23:50:50.441038 [0] MAX Duty = 5125%(X100), DQS PI = 20
2397 23:50:50.441093 [0] MIN Duty = 4844%(X100), DQS PI = 50
2398 23:50:50.441146 [0] AVG Duty = 4984%(X100)
2399 23:50:50.441199
2400 23:50:50.441252 ==DQM 1 ==
2401 23:50:50.441345 Final DQM duty delay cell = 0
2402 23:50:50.441400 [0] MAX Duty = 4969%(X100), DQS PI = 2
2403 23:50:50.441648 [0] MIN Duty = 4875%(X100), DQS PI = 14
2404 23:50:50.441755 [0] AVG Duty = 4922%(X100)
2405 23:50:50.441824
2406 23:50:50.441877 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2407 23:50:50.441932
2408 23:50:50.441984 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2409 23:50:50.442038 [DutyScan_Calibration_Flow] ====Done====
2410 23:50:50.442092
2411 23:50:50.442145 [DutyScan_Calibration_Flow] k_type=2
2412 23:50:50.442199
2413 23:50:50.442252 ==DQ 0 ==
2414 23:50:50.442306 Final DQ duty delay cell = 0
2415 23:50:50.442361 [0] MAX Duty = 5125%(X100), DQS PI = 18
2416 23:50:50.442465 [0] MIN Duty = 5000%(X100), DQS PI = 8
2417 23:50:50.442520 [0] AVG Duty = 5062%(X100)
2418 23:50:50.442575
2419 23:50:50.442629 ==DQ 1 ==
2420 23:50:50.442683 Final DQ duty delay cell = 0
2421 23:50:50.442737 [0] MAX Duty = 5125%(X100), DQS PI = 4
2422 23:50:50.442791 [0] MIN Duty = 4938%(X100), DQS PI = 14
2423 23:50:50.442844 [0] AVG Duty = 5031%(X100)
2424 23:50:50.442898
2425 23:50:50.442951 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2426 23:50:50.443005
2427 23:50:50.443059 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2428 23:50:50.443112 [DutyScan_Calibration_Flow] ====Done====
2429 23:50:50.443166 ==
2430 23:50:50.443219 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 23:50:50.443273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 23:50:50.443327 ==
2433 23:50:50.443381 [Duty_Offset_Calibration]
2434 23:50:50.443433 B0:0 B1:-1 CA:3
2435 23:50:50.443486
2436 23:50:50.443539 [DutyScan_Calibration_Flow] k_type=0
2437 23:50:50.443592
2438 23:50:50.443645 ==CLK 0==
2439 23:50:50.443698 Final CLK duty delay cell = -4
2440 23:50:50.443753 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2441 23:50:50.443821 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2442 23:50:50.443876 [-4] AVG Duty = 4938%(X100)
2443 23:50:50.443944
2444 23:50:50.443996 CH1 CLK Duty spec in!! Max-Min= 124%
2445 23:50:50.444065 [DutyScan_Calibration_Flow] ====Done====
2446 23:50:50.444119
2447 23:50:50.444187 [DutyScan_Calibration_Flow] k_type=1
2448 23:50:50.444240
2449 23:50:50.444292 ==DQS 0 ==
2450 23:50:50.444361 Final DQS duty delay cell = 0
2451 23:50:50.444452 [0] MAX Duty = 5156%(X100), DQS PI = 18
2452 23:50:50.444566 [0] MIN Duty = 4907%(X100), DQS PI = 38
2453 23:50:50.444650 [0] AVG Duty = 5031%(X100)
2454 23:50:50.444717
2455 23:50:50.444770 ==DQS 1 ==
2456 23:50:50.444839 Final DQS duty delay cell = 0
2457 23:50:50.444907 [0] MAX Duty = 5156%(X100), DQS PI = 8
2458 23:50:50.444976 [0] MIN Duty = 5000%(X100), DQS PI = 26
2459 23:50:50.445043 [0] AVG Duty = 5078%(X100)
2460 23:50:50.445096
2461 23:50:50.445165 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2462 23:50:50.445220
2463 23:50:50.445298 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2464 23:50:50.445353 [DutyScan_Calibration_Flow] ====Done====
2465 23:50:50.445407
2466 23:50:50.445460 [DutyScan_Calibration_Flow] k_type=3
2467 23:50:50.445536
2468 23:50:50.445603 ==DQM 0 ==
2469 23:50:50.445657 Final DQM duty delay cell = 0
2470 23:50:50.445710 [0] MAX Duty = 5031%(X100), DQS PI = 28
2471 23:50:50.445794 [0] MIN Duty = 4813%(X100), DQS PI = 38
2472 23:50:50.445847 [0] AVG Duty = 4922%(X100)
2473 23:50:50.445921
2474 23:50:50.445987 ==DQM 1 ==
2475 23:50:50.446040 Final DQM duty delay cell = 0
2476 23:50:50.446093 [0] MAX Duty = 5000%(X100), DQS PI = 34
2477 23:50:50.446146 [0] MIN Duty = 4844%(X100), DQS PI = 0
2478 23:50:50.446214 [0] AVG Duty = 4922%(X100)
2479 23:50:50.446281
2480 23:50:50.446334 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2481 23:50:50.446387
2482 23:50:50.446439 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2483 23:50:50.446506 [DutyScan_Calibration_Flow] ====Done====
2484 23:50:50.446573
2485 23:50:50.446627 [DutyScan_Calibration_Flow] k_type=2
2486 23:50:50.446679
2487 23:50:50.446732 ==DQ 0 ==
2488 23:50:50.446800 Final DQ duty delay cell = -4
2489 23:50:50.446867 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2490 23:50:50.446922 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2491 23:50:50.446975 [-4] AVG Duty = 4937%(X100)
2492 23:50:50.447029
2493 23:50:50.447109 ==DQ 1 ==
2494 23:50:50.447162 Final DQ duty delay cell = 0
2495 23:50:50.447216 [0] MAX Duty = 5031%(X100), DQS PI = 34
2496 23:50:50.447269 [0] MIN Duty = 4844%(X100), DQS PI = 0
2497 23:50:50.447379 [0] AVG Duty = 4937%(X100)
2498 23:50:50.447432
2499 23:50:50.447485 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2500 23:50:50.447538
2501 23:50:50.447591 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2502 23:50:50.447644 [DutyScan_Calibration_Flow] ====Done====
2503 23:50:50.447698 nWR fixed to 30
2504 23:50:50.447751 [ModeRegInit_LP4] CH0 RK0
2505 23:50:50.447805 [ModeRegInit_LP4] CH0 RK1
2506 23:50:50.447858 [ModeRegInit_LP4] CH1 RK0
2507 23:50:50.447911 [ModeRegInit_LP4] CH1 RK1
2508 23:50:50.447964 match AC timing 7
2509 23:50:50.448018 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 23:50:50.448072 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 23:50:50.448126 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 23:50:50.448179 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 23:50:50.448233 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 23:50:50.448287 ==
2515 23:50:50.448340 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 23:50:50.448393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:50:50.448470 ==
2518 23:50:50.448563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 23:50:50.448624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 23:50:50.448680 [CA 0] Center 39 (9~70) winsize 62
2521 23:50:50.448735 [CA 1] Center 38 (8~69) winsize 62
2522 23:50:50.448803 [CA 2] Center 35 (5~66) winsize 62
2523 23:50:50.448901 [CA 3] Center 35 (5~66) winsize 62
2524 23:50:50.448982 [CA 4] Center 33 (3~64) winsize 62
2525 23:50:50.449036 [CA 5] Center 33 (3~64) winsize 62
2526 23:50:50.449090
2527 23:50:50.449143 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 23:50:50.449196
2529 23:50:50.449249 [CATrainingPosCal] consider 1 rank data
2530 23:50:50.449371 u2DelayCellTimex100 = 270/100 ps
2531 23:50:50.449455 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2532 23:50:50.449544 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2533 23:50:50.449642 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 23:50:50.449701 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 23:50:50.449755 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2536 23:50:50.449810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2537 23:50:50.449864
2538 23:50:50.449918 CA PerBit enable=1, Macro0, CA PI delay=33
2539 23:50:50.449972
2540 23:50:50.450026 [CBTSetCACLKResult] CA Dly = 33
2541 23:50:50.450080 CS Dly: 7 (0~38)
2542 23:50:50.450133 ==
2543 23:50:50.450187 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 23:50:50.450241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 23:50:50.450295 ==
2546 23:50:50.450348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 23:50:50.450403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2548 23:50:50.450518 [CA 0] Center 39 (9~70) winsize 62
2549 23:50:50.450593 [CA 1] Center 39 (9~70) winsize 62
2550 23:50:50.450841 [CA 2] Center 35 (5~66) winsize 62
2551 23:50:50.450901 [CA 3] Center 35 (5~66) winsize 62
2552 23:50:50.450956 [CA 4] Center 34 (4~65) winsize 62
2553 23:50:50.451010 [CA 5] Center 33 (3~64) winsize 62
2554 23:50:50.451063
2555 23:50:50.451117 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2556 23:50:50.451171
2557 23:50:50.451225 [CATrainingPosCal] consider 2 rank data
2558 23:50:50.451278 u2DelayCellTimex100 = 270/100 ps
2559 23:50:50.451332 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2560 23:50:50.451386 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2561 23:50:50.451440 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 23:50:50.451493 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 23:50:50.451547 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2564 23:50:50.451600 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2565 23:50:50.451653
2566 23:50:50.451705 CA PerBit enable=1, Macro0, CA PI delay=33
2567 23:50:50.451759
2568 23:50:50.451812 [CBTSetCACLKResult] CA Dly = 33
2569 23:50:50.451867 CS Dly: 8 (0~41)
2570 23:50:50.451920
2571 23:50:50.451973 ----->DramcWriteLeveling(PI) begin...
2572 23:50:50.452028 ==
2573 23:50:50.452081 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 23:50:50.452135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 23:50:50.452189 ==
2576 23:50:50.452243 Write leveling (Byte 0): 32 => 32
2577 23:50:50.452297 Write leveling (Byte 1): 26 => 26
2578 23:50:50.452350 DramcWriteLeveling(PI) end<-----
2579 23:50:50.452403
2580 23:50:50.452457 ==
2581 23:50:50.452510 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 23:50:50.452564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 23:50:50.452617 ==
2584 23:50:50.452670 [Gating] SW mode calibration
2585 23:50:50.452723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 23:50:50.452777 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 23:50:50.452830 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2588 23:50:50.452884 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2589 23:50:50.452937 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:50:50.452991 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 23:50:50.453045 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 23:50:50.453125 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 23:50:50.453193 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 23:50:50.453248 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2595 23:50:50.453326 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2596 23:50:50.453379 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:50:50.453432 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:50:50.453486 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 23:50:50.453539 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 23:50:50.453593 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 23:50:50.453646 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2602 23:50:50.453699 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2603 23:50:50.453752 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2604 23:50:50.453806 1 1 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2605 23:50:50.453859 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:50:50.453914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:50:50.453968 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 23:50:50.454021 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 23:50:50.454074 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2610 23:50:50.454128 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 23:50:50.454181 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 23:50:50.454234 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 23:50:50.454287 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:50:50.454346 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:50:50.454409 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:50:50.454500 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:50:50.454556 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:50:50.454611 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:50:50.454665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:50:50.454719 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:50:50.454772 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:50:50.454826 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:50:50.454879 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:50:50.454932 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:50:50.454985 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2626 23:50:50.455038 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 23:50:50.455091 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 23:50:50.455145 Total UI for P1: 0, mck2ui 16
2629 23:50:50.455199 best dqsien dly found for B0: ( 1, 3, 26)
2630 23:50:50.455253 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 23:50:50.455306 Total UI for P1: 0, mck2ui 16
2632 23:50:50.455360 best dqsien dly found for B1: ( 1, 4, 0)
2633 23:50:50.455414 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2634 23:50:50.455467 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 23:50:50.455520
2636 23:50:50.455573 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2637 23:50:50.455626 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 23:50:50.455679 [Gating] SW calibration Done
2639 23:50:50.455732 ==
2640 23:50:50.455785 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 23:50:50.455844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 23:50:50.455898 ==
2643 23:50:50.455951 RX Vref Scan: 0
2644 23:50:50.456004
2645 23:50:50.456057 RX Vref 0 -> 0, step: 1
2646 23:50:50.456110
2647 23:50:50.456162 RX Delay -40 -> 252, step: 8
2648 23:50:50.456215 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2649 23:50:50.456269 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2650 23:50:50.456322 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2651 23:50:50.456375 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2652 23:50:50.456428 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2653 23:50:50.456526 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2654 23:50:50.456771 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2655 23:50:50.456876 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2656 23:50:50.456931 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2657 23:50:50.456987 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2658 23:50:50.457042 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2659 23:50:50.457097 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2660 23:50:50.457152 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2661 23:50:50.457207 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2662 23:50:50.457271 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2663 23:50:50.457328 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2664 23:50:50.457383 ==
2665 23:50:50.457437 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 23:50:50.457492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 23:50:50.457547 ==
2668 23:50:50.457602 DQS Delay:
2669 23:50:50.457657 DQS0 = 0, DQS1 = 0
2670 23:50:50.457711 DQM Delay:
2671 23:50:50.457765 DQM0 = 117, DQM1 = 107
2672 23:50:50.457820 DQ Delay:
2673 23:50:50.457875 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2674 23:50:50.457929 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =119
2675 23:50:50.457983 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2676 23:50:50.458037 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =115
2677 23:50:50.458091
2678 23:50:50.458145
2679 23:50:50.458199 ==
2680 23:50:50.458254 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 23:50:50.458309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 23:50:50.458364 ==
2683 23:50:50.458418
2684 23:50:50.458472
2685 23:50:50.458525 TX Vref Scan disable
2686 23:50:50.458579 == TX Byte 0 ==
2687 23:50:50.458633 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2688 23:50:50.458689 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2689 23:50:50.458743 == TX Byte 1 ==
2690 23:50:50.458797 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2691 23:50:50.458851 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2692 23:50:50.458906 ==
2693 23:50:50.458960 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 23:50:50.459014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 23:50:50.459070 ==
2696 23:50:50.459124 TX Vref=22, minBit 1, minWin=25, winSum=411
2697 23:50:50.459179 TX Vref=24, minBit 4, minWin=25, winSum=414
2698 23:50:50.459234 TX Vref=26, minBit 14, minWin=25, winSum=425
2699 23:50:50.459289 TX Vref=28, minBit 1, minWin=25, winSum=427
2700 23:50:50.459344 TX Vref=30, minBit 5, minWin=26, winSum=430
2701 23:50:50.459399 TX Vref=32, minBit 5, minWin=26, winSum=429
2702 23:50:50.459454 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 30
2703 23:50:50.459509
2704 23:50:50.459563 Final TX Range 1 Vref 30
2705 23:50:50.459618
2706 23:50:50.459671 ==
2707 23:50:50.459725 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 23:50:50.459780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 23:50:50.459834 ==
2710 23:50:50.459888
2711 23:50:50.459942
2712 23:50:50.459996 TX Vref Scan disable
2713 23:50:50.460050 == TX Byte 0 ==
2714 23:50:50.460104 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2715 23:50:50.460158 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2716 23:50:50.460212 == TX Byte 1 ==
2717 23:50:50.460266 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2718 23:50:50.460320 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2719 23:50:50.460373
2720 23:50:50.460427 [DATLAT]
2721 23:50:50.460481 Freq=1200, CH0 RK0
2722 23:50:50.460536
2723 23:50:50.460590 DATLAT Default: 0xd
2724 23:50:50.460643 0, 0xFFFF, sum = 0
2725 23:50:50.460699 1, 0xFFFF, sum = 0
2726 23:50:50.460754 2, 0xFFFF, sum = 0
2727 23:50:50.460810 3, 0xFFFF, sum = 0
2728 23:50:50.460864 4, 0xFFFF, sum = 0
2729 23:50:50.460920 5, 0xFFFF, sum = 0
2730 23:50:50.460975 6, 0xFFFF, sum = 0
2731 23:50:50.461030 7, 0xFFFF, sum = 0
2732 23:50:50.461085 8, 0xFFFF, sum = 0
2733 23:50:50.461140 9, 0xFFFF, sum = 0
2734 23:50:50.461195 10, 0xFFFF, sum = 0
2735 23:50:50.461251 11, 0xFFFF, sum = 0
2736 23:50:50.461329 12, 0x0, sum = 1
2737 23:50:50.461384 13, 0x0, sum = 2
2738 23:50:50.461438 14, 0x0, sum = 3
2739 23:50:50.461492 15, 0x0, sum = 4
2740 23:50:50.461547 best_step = 13
2741 23:50:50.461600
2742 23:50:50.461652 ==
2743 23:50:50.461705 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 23:50:50.461758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 23:50:50.461812 ==
2746 23:50:50.461865 RX Vref Scan: 1
2747 23:50:50.461918
2748 23:50:50.461970 Set Vref Range= 32 -> 127
2749 23:50:50.462024
2750 23:50:50.462077 RX Vref 32 -> 127, step: 1
2751 23:50:50.462130
2752 23:50:50.462182 RX Delay -21 -> 252, step: 4
2753 23:50:50.462235
2754 23:50:50.462288 Set Vref, RX VrefLevel [Byte0]: 32
2755 23:50:50.462341 [Byte1]: 32
2756 23:50:50.462394
2757 23:50:50.462478 Set Vref, RX VrefLevel [Byte0]: 33
2758 23:50:50.462530 [Byte1]: 33
2759 23:50:50.462583
2760 23:50:50.462636 Set Vref, RX VrefLevel [Byte0]: 34
2761 23:50:50.462688 [Byte1]: 34
2762 23:50:50.462741
2763 23:50:50.462793 Set Vref, RX VrefLevel [Byte0]: 35
2764 23:50:50.462846 [Byte1]: 35
2765 23:50:50.462898
2766 23:50:50.462951 Set Vref, RX VrefLevel [Byte0]: 36
2767 23:50:50.463005 [Byte1]: 36
2768 23:50:50.463058
2769 23:50:50.463111 Set Vref, RX VrefLevel [Byte0]: 37
2770 23:50:50.463164 [Byte1]: 37
2771 23:50:50.463217
2772 23:50:50.463270 Set Vref, RX VrefLevel [Byte0]: 38
2773 23:50:50.463323 [Byte1]: 38
2774 23:50:50.463375
2775 23:50:50.463428 Set Vref, RX VrefLevel [Byte0]: 39
2776 23:50:50.463480 [Byte1]: 39
2777 23:50:50.463533
2778 23:50:50.463586 Set Vref, RX VrefLevel [Byte0]: 40
2779 23:50:50.463639 [Byte1]: 40
2780 23:50:50.463692
2781 23:50:50.463745 Set Vref, RX VrefLevel [Byte0]: 41
2782 23:50:50.463798 [Byte1]: 41
2783 23:50:50.463851
2784 23:50:50.463904 Set Vref, RX VrefLevel [Byte0]: 42
2785 23:50:50.463957 [Byte1]: 42
2786 23:50:50.464009
2787 23:50:50.464062 Set Vref, RX VrefLevel [Byte0]: 43
2788 23:50:50.464115 [Byte1]: 43
2789 23:50:50.464168
2790 23:50:50.464220 Set Vref, RX VrefLevel [Byte0]: 44
2791 23:50:50.464273 [Byte1]: 44
2792 23:50:50.464326
2793 23:50:50.464379 Set Vref, RX VrefLevel [Byte0]: 45
2794 23:50:50.464449 [Byte1]: 45
2795 23:50:50.464515
2796 23:50:50.464566 Set Vref, RX VrefLevel [Byte0]: 46
2797 23:50:50.464619 [Byte1]: 46
2798 23:50:50.464671
2799 23:50:50.464724 Set Vref, RX VrefLevel [Byte0]: 47
2800 23:50:50.464776 [Byte1]: 47
2801 23:50:50.464829
2802 23:50:50.464881 Set Vref, RX VrefLevel [Byte0]: 48
2803 23:50:50.464934 [Byte1]: 48
2804 23:50:50.464987
2805 23:50:50.465039 Set Vref, RX VrefLevel [Byte0]: 49
2806 23:50:50.465092 [Byte1]: 49
2807 23:50:50.465145
2808 23:50:50.465198 Set Vref, RX VrefLevel [Byte0]: 50
2809 23:50:50.465251 [Byte1]: 50
2810 23:50:50.465345
2811 23:50:50.465398 Set Vref, RX VrefLevel [Byte0]: 51
2812 23:50:50.465452 [Byte1]: 51
2813 23:50:50.465505
2814 23:50:50.465558 Set Vref, RX VrefLevel [Byte0]: 52
2815 23:50:50.465810 [Byte1]: 52
2816 23:50:50.465872
2817 23:50:50.465942 Set Vref, RX VrefLevel [Byte0]: 53
2818 23:50:50.466010 [Byte1]: 53
2819 23:50:50.466063
2820 23:50:50.466117 Set Vref, RX VrefLevel [Byte0]: 54
2821 23:50:50.466169 [Byte1]: 54
2822 23:50:50.466239
2823 23:50:50.466324 Set Vref, RX VrefLevel [Byte0]: 55
2824 23:50:50.466392 [Byte1]: 55
2825 23:50:50.466469
2826 23:50:50.466535 Set Vref, RX VrefLevel [Byte0]: 56
2827 23:50:50.466589 [Byte1]: 56
2828 23:50:50.466641
2829 23:50:50.466695 Set Vref, RX VrefLevel [Byte0]: 57
2830 23:50:50.466748 [Byte1]: 57
2831 23:50:50.466801
2832 23:50:50.466854 Set Vref, RX VrefLevel [Byte0]: 58
2833 23:50:50.466907 [Byte1]: 58
2834 23:50:50.466960
2835 23:50:50.467012 Set Vref, RX VrefLevel [Byte0]: 59
2836 23:50:50.467066 [Byte1]: 59
2837 23:50:50.467119
2838 23:50:50.467172 Set Vref, RX VrefLevel [Byte0]: 60
2839 23:50:50.467225 [Byte1]: 60
2840 23:50:50.467278
2841 23:50:50.467331 Set Vref, RX VrefLevel [Byte0]: 61
2842 23:50:50.467384 [Byte1]: 61
2843 23:50:50.467437
2844 23:50:50.467489 Set Vref, RX VrefLevel [Byte0]: 62
2845 23:50:50.467542 [Byte1]: 62
2846 23:50:50.467595
2847 23:50:50.467648 Set Vref, RX VrefLevel [Byte0]: 63
2848 23:50:50.467701 [Byte1]: 63
2849 23:50:50.467754
2850 23:50:50.467807 Set Vref, RX VrefLevel [Byte0]: 64
2851 23:50:50.467860 [Byte1]: 64
2852 23:50:50.467914
2853 23:50:50.467967 Set Vref, RX VrefLevel [Byte0]: 65
2854 23:50:50.468020 [Byte1]: 65
2855 23:50:50.468073
2856 23:50:50.468125 Set Vref, RX VrefLevel [Byte0]: 66
2857 23:50:50.468179 [Byte1]: 66
2858 23:50:50.468232
2859 23:50:50.468285 Set Vref, RX VrefLevel [Byte0]: 67
2860 23:50:50.468338 [Byte1]: 67
2861 23:50:50.468390
2862 23:50:50.468443 Set Vref, RX VrefLevel [Byte0]: 68
2863 23:50:50.468496 [Byte1]: 68
2864 23:50:50.468548
2865 23:50:50.468601 Final RX Vref Byte 0 = 53 to rank0
2866 23:50:50.468655 Final RX Vref Byte 1 = 47 to rank0
2867 23:50:50.468709 Final RX Vref Byte 0 = 53 to rank1
2868 23:50:50.468762 Final RX Vref Byte 1 = 47 to rank1==
2869 23:50:50.468816 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 23:50:50.468869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 23:50:50.468923 ==
2872 23:50:50.468976 DQS Delay:
2873 23:50:50.469029 DQS0 = 0, DQS1 = 0
2874 23:50:50.469081 DQM Delay:
2875 23:50:50.469135 DQM0 = 117, DQM1 = 102
2876 23:50:50.469188 DQ Delay:
2877 23:50:50.469241 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2878 23:50:50.469342 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2879 23:50:50.469396 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2880 23:50:50.469451 DQ12 =110, DQ13 =108, DQ14 =112, DQ15 =110
2881 23:50:50.469504
2882 23:50:50.469557
2883 23:50:50.469610 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2884 23:50:50.469664 CH0 RK0: MR19=403, MR18=4FF
2885 23:50:50.469717 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2886 23:50:50.469771
2887 23:50:50.469824 ----->DramcWriteLeveling(PI) begin...
2888 23:50:50.469879 ==
2889 23:50:50.469932 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 23:50:50.469986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 23:50:50.470040 ==
2892 23:50:50.470094 Write leveling (Byte 0): 33 => 33
2893 23:50:50.470147 Write leveling (Byte 1): 26 => 26
2894 23:50:50.470200 DramcWriteLeveling(PI) end<-----
2895 23:50:50.470254
2896 23:50:50.470306 ==
2897 23:50:50.470359 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 23:50:50.470436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 23:50:50.470520 ==
2900 23:50:50.470614 [Gating] SW mode calibration
2901 23:50:50.470674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 23:50:50.470729 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 23:50:50.470784 0 15 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
2904 23:50:50.470838 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 23:50:50.470892 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 23:50:50.470946 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 23:50:50.470999 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 23:50:50.471053 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 23:50:50.471107 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2910 23:50:50.471161 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
2911 23:50:50.471214 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2912 23:50:50.471268 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 23:50:50.471322 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 23:50:50.471376 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 23:50:50.471430 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 23:50:50.471483 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 23:50:50.471537 1 0 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
2918 23:50:50.471591 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2919 23:50:50.471644 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2920 23:50:50.471698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 23:50:50.471751 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 23:50:50.471805 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 23:50:50.471858 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 23:50:50.471911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:50:50.471965 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2926 23:50:50.472018 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2927 23:50:50.472072 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2928 23:50:50.472125 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:50:50.472179 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:50:50.472232 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:50:50.472285 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:50:50.472338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:50:50.472391 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:50:50.472445 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:50:50.472688 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:50:50.472762 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:50:50.472818 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:50:50.472874 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:50:50.472928 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:50:50.472984 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:50:50.473039 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2942 23:50:50.473094 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2943 23:50:50.473149 Total UI for P1: 0, mck2ui 16
2944 23:50:50.473204 best dqsien dly found for B0: ( 1, 3, 24)
2945 23:50:50.473269 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2946 23:50:50.473339 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 23:50:50.473393 Total UI for P1: 0, mck2ui 16
2948 23:50:50.473447 best dqsien dly found for B1: ( 1, 4, 0)
2949 23:50:50.473501 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2950 23:50:50.473554 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2951 23:50:50.473608
2952 23:50:50.473661 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2953 23:50:50.473714 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2954 23:50:50.473767 [Gating] SW calibration Done
2955 23:50:50.473821 ==
2956 23:50:50.473873 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:50:50.473927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:50:50.473981 ==
2959 23:50:50.474034 RX Vref Scan: 0
2960 23:50:50.474087
2961 23:50:50.474140 RX Vref 0 -> 0, step: 1
2962 23:50:50.474193
2963 23:50:50.474245 RX Delay -40 -> 252, step: 8
2964 23:50:50.474299 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2965 23:50:50.474353 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2966 23:50:50.474406 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2967 23:50:50.474528 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2968 23:50:50.474598 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2969 23:50:50.474651 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2970 23:50:50.474705 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 23:50:50.474758 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2972 23:50:50.474811 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2973 23:50:50.474864 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2974 23:50:50.474917 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2975 23:50:50.474971 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2976 23:50:50.475024 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2977 23:50:50.475077 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2978 23:50:50.475130 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2979 23:50:50.475184 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2980 23:50:50.475245 ==
2981 23:50:50.475300 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 23:50:50.475354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 23:50:50.475408 ==
2984 23:50:50.475461 DQS Delay:
2985 23:50:50.475514 DQS0 = 0, DQS1 = 0
2986 23:50:50.475566 DQM Delay:
2987 23:50:50.475619 DQM0 = 115, DQM1 = 106
2988 23:50:50.475673 DQ Delay:
2989 23:50:50.475726 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2990 23:50:50.475780 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2991 23:50:50.475833 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2992 23:50:50.475886 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2993 23:50:50.475939
2994 23:50:50.475991
2995 23:50:50.476044 ==
2996 23:50:50.476097 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 23:50:50.476150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 23:50:50.476204 ==
2999 23:50:50.476257
3000 23:50:50.476309
3001 23:50:50.476362 TX Vref Scan disable
3002 23:50:50.476415 == TX Byte 0 ==
3003 23:50:50.476468 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3004 23:50:50.592350 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3005 23:50:50.592461 == TX Byte 1 ==
3006 23:50:50.592527 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3007 23:50:50.592646 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3008 23:50:50.592740 ==
3009 23:50:50.592803 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 23:50:50.592879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 23:50:50.592949 ==
3012 23:50:50.593006 TX Vref=22, minBit 4, minWin=25, winSum=416
3013 23:50:50.593062 TX Vref=24, minBit 10, minWin=25, winSum=420
3014 23:50:50.593117 TX Vref=26, minBit 13, minWin=25, winSum=428
3015 23:50:50.593172 TX Vref=28, minBit 10, minWin=26, winSum=428
3016 23:50:50.593227 TX Vref=30, minBit 10, minWin=26, winSum=429
3017 23:50:50.593321 TX Vref=32, minBit 5, minWin=26, winSum=427
3018 23:50:50.593376 [TxChooseVref] Worse bit 10, Min win 26, Win sum 429, Final Vref 30
3019 23:50:50.593431
3020 23:50:50.593486 Final TX Range 1 Vref 30
3021 23:50:50.593540
3022 23:50:50.593594 ==
3023 23:50:50.593647 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 23:50:50.593702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 23:50:50.593756 ==
3026 23:50:50.593810
3027 23:50:50.593863
3028 23:50:50.593916 TX Vref Scan disable
3029 23:50:50.593970 == TX Byte 0 ==
3030 23:50:50.594024 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3031 23:50:50.594078 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3032 23:50:50.594160 == TX Byte 1 ==
3033 23:50:50.594213 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3034 23:50:50.594267 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3035 23:50:50.594320
3036 23:50:50.594373 [DATLAT]
3037 23:50:50.594426 Freq=1200, CH0 RK1
3038 23:50:50.594480
3039 23:50:50.594533 DATLAT Default: 0xd
3040 23:50:50.594586 0, 0xFFFF, sum = 0
3041 23:50:50.594642 1, 0xFFFF, sum = 0
3042 23:50:50.594697 2, 0xFFFF, sum = 0
3043 23:50:50.594751 3, 0xFFFF, sum = 0
3044 23:50:50.594804 4, 0xFFFF, sum = 0
3045 23:50:50.594858 5, 0xFFFF, sum = 0
3046 23:50:50.594912 6, 0xFFFF, sum = 0
3047 23:50:50.594966 7, 0xFFFF, sum = 0
3048 23:50:50.595020 8, 0xFFFF, sum = 0
3049 23:50:50.595074 9, 0xFFFF, sum = 0
3050 23:50:50.595128 10, 0xFFFF, sum = 0
3051 23:50:50.595183 11, 0xFFFF, sum = 0
3052 23:50:50.595237 12, 0x0, sum = 1
3053 23:50:50.595291 13, 0x0, sum = 2
3054 23:50:50.595373 14, 0x0, sum = 3
3055 23:50:50.595426 15, 0x0, sum = 4
3056 23:50:50.595481 best_step = 13
3057 23:50:50.595533
3058 23:50:50.595586 ==
3059 23:50:50.595639 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 23:50:50.595692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 23:50:50.595745 ==
3062 23:50:50.595799 RX Vref Scan: 0
3063 23:50:50.595852
3064 23:50:50.595905 RX Vref 0 -> 0, step: 1
3065 23:50:50.595958
3066 23:50:50.596010 RX Delay -21 -> 252, step: 4
3067 23:50:50.596064 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3068 23:50:50.596116 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3069 23:50:50.596169 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3070 23:50:50.596222 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3071 23:50:50.596275 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3072 23:50:50.596328 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3073 23:50:50.596580 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3074 23:50:50.596640 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3075 23:50:50.596694 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3076 23:50:50.596748 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3077 23:50:50.596802 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3078 23:50:50.596855 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3079 23:50:50.596909 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3080 23:50:50.596963 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3081 23:50:50.597017 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3082 23:50:50.597070 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3083 23:50:50.597124 ==
3084 23:50:50.597177 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 23:50:50.597231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 23:50:50.597322 ==
3087 23:50:50.597376 DQS Delay:
3088 23:50:50.597429 DQS0 = 0, DQS1 = 0
3089 23:50:50.597483 DQM Delay:
3090 23:50:50.597536 DQM0 = 116, DQM1 = 104
3091 23:50:50.597589 DQ Delay:
3092 23:50:50.597642 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3093 23:50:50.597696 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3094 23:50:50.597749 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =98
3095 23:50:50.597803 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3096 23:50:50.597856
3097 23:50:50.597909
3098 23:50:50.597962 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3099 23:50:50.598017 CH0 RK1: MR19=303, MR18=FFFD
3100 23:50:50.598071 CH0_RK1: MR19=0x303, MR18=0xFFFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3101 23:50:50.598125 [RxdqsGatingPostProcess] freq 1200
3102 23:50:50.598178 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 23:50:50.598232 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 23:50:50.598286 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 23:50:50.598339 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 23:50:50.598392 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 23:50:50.598480 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 23:50:50.598534 best DQS1 dly(2T, 0.5T) = (0, 12)
3109 23:50:50.598587 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 23:50:50.598641 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3111 23:50:50.598694 Pre-setting of DQS Precalculation
3112 23:50:50.598775 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 23:50:50.598829 ==
3114 23:50:50.598882 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 23:50:50.598936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 23:50:50.598990 ==
3117 23:50:50.599043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 23:50:50.599097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 23:50:50.599151 [CA 0] Center 38 (8~68) winsize 61
3120 23:50:50.599205 [CA 1] Center 37 (7~68) winsize 62
3121 23:50:50.599259 [CA 2] Center 35 (6~65) winsize 60
3122 23:50:50.599312 [CA 3] Center 34 (4~64) winsize 61
3123 23:50:50.599365 [CA 4] Center 34 (4~64) winsize 61
3124 23:50:50.599419 [CA 5] Center 33 (3~63) winsize 61
3125 23:50:50.599472
3126 23:50:50.599525 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3127 23:50:50.599579
3128 23:50:50.599632 [CATrainingPosCal] consider 1 rank data
3129 23:50:50.599686 u2DelayCellTimex100 = 270/100 ps
3130 23:50:50.599739 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 23:50:50.599793 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 23:50:50.599847 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3133 23:50:50.599900 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 23:50:50.599954 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 23:50:50.600008 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 23:50:50.600061
3137 23:50:50.600114 CA PerBit enable=1, Macro0, CA PI delay=33
3138 23:50:50.600168
3139 23:50:50.600220 [CBTSetCACLKResult] CA Dly = 33
3140 23:50:50.600274 CS Dly: 5 (0~36)
3141 23:50:50.600327 ==
3142 23:50:50.600381 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 23:50:50.600434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 23:50:50.600488 ==
3145 23:50:50.600542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 23:50:50.600596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3147 23:50:50.600650 [CA 0] Center 37 (7~68) winsize 62
3148 23:50:50.600703 [CA 1] Center 38 (8~68) winsize 61
3149 23:50:50.600757 [CA 2] Center 35 (5~65) winsize 61
3150 23:50:50.600811 [CA 3] Center 33 (3~64) winsize 62
3151 23:50:50.600865 [CA 4] Center 34 (4~64) winsize 61
3152 23:50:50.600918 [CA 5] Center 33 (3~63) winsize 61
3153 23:50:50.600972
3154 23:50:50.601025 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3155 23:50:50.601078
3156 23:50:50.601131 [CATrainingPosCal] consider 2 rank data
3157 23:50:50.601185 u2DelayCellTimex100 = 270/100 ps
3158 23:50:50.601240 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 23:50:50.601331 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3160 23:50:50.601385 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3161 23:50:50.601439 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 23:50:50.601508 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 23:50:50.601575 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3164 23:50:50.601629
3165 23:50:50.601682 CA PerBit enable=1, Macro0, CA PI delay=33
3166 23:50:50.601736
3167 23:50:50.601789 [CBTSetCACLKResult] CA Dly = 33
3168 23:50:50.601843 CS Dly: 6 (0~38)
3169 23:50:50.601896
3170 23:50:50.601950 ----->DramcWriteLeveling(PI) begin...
3171 23:50:50.602005 ==
3172 23:50:50.602059 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 23:50:50.602113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 23:50:50.602167 ==
3175 23:50:50.602235 Write leveling (Byte 0): 25 => 25
3176 23:50:50.602331 Write leveling (Byte 1): 28 => 28
3177 23:50:50.602385 DramcWriteLeveling(PI) end<-----
3178 23:50:50.602438
3179 23:50:50.602491 ==
3180 23:50:50.602544 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 23:50:50.602598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 23:50:50.602652 ==
3183 23:50:50.602706 [Gating] SW mode calibration
3184 23:50:50.602760 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 23:50:50.602815 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 23:50:50.602869 0 15 0 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
3187 23:50:50.602923 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 23:50:50.602977 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 23:50:50.603031 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 23:50:50.603086 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 23:50:50.603338 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 23:50:50.603459 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
3193 23:50:50.603514 0 15 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
3194 23:50:50.603568 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 23:50:50.603623 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 23:50:50.603676 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 23:50:50.603731 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 23:50:50.603784 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 23:50:50.603839 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 23:50:50.603892 1 0 24 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
3201 23:50:50.603946 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3202 23:50:50.604001 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 23:50:50.604055 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 23:50:50.604110 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 23:50:50.604164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 23:50:50.604217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 23:50:50.604272 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 23:50:50.604326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 23:50:50.604380 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 23:50:50.604434 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:50:50.604488 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:50:50.604543 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:50:50.604596 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:50:50.604650 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:50:50.604704 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:50:50.604757 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:50:50.604811 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:50:50.604865 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:50:50.604936 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:50:50.605004 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:50:50.605057 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:50:50.605111 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:50:50.605165 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:50:50.605218 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3225 23:50:50.605293 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3226 23:50:50.605362 Total UI for P1: 0, mck2ui 16
3227 23:50:50.605416 best dqsien dly found for B0: ( 1, 3, 24)
3228 23:50:50.605471 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 23:50:50.605525 Total UI for P1: 0, mck2ui 16
3230 23:50:50.605579 best dqsien dly found for B1: ( 1, 3, 28)
3231 23:50:50.605632 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3232 23:50:50.605686 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3233 23:50:50.605739
3234 23:50:50.605792 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3235 23:50:50.605845 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3236 23:50:50.605898 [Gating] SW calibration Done
3237 23:50:50.605952 ==
3238 23:50:50.606005 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:50:50.606060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:50:50.606114 ==
3241 23:50:50.606168 RX Vref Scan: 0
3242 23:50:50.606221
3243 23:50:50.606290 RX Vref 0 -> 0, step: 1
3244 23:50:50.606357
3245 23:50:50.606438 RX Delay -40 -> 252, step: 8
3246 23:50:50.606492 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3247 23:50:50.606546 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3248 23:50:50.606600 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3249 23:50:50.606654 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3250 23:50:50.606708 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3251 23:50:50.606762 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3252 23:50:50.606816 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3253 23:50:50.606869 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3254 23:50:50.606923 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3255 23:50:50.606976 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3256 23:50:50.607030 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3257 23:50:50.607083 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3258 23:50:50.607136 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 23:50:50.607190 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3260 23:50:50.607244 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3261 23:50:50.607297 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3262 23:50:50.607350 ==
3263 23:50:50.607404 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 23:50:50.607458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 23:50:50.607512 ==
3266 23:50:50.607565 DQS Delay:
3267 23:50:50.607619 DQS0 = 0, DQS1 = 0
3268 23:50:50.607672 DQM Delay:
3269 23:50:50.607726 DQM0 = 115, DQM1 = 112
3270 23:50:50.607779 DQ Delay:
3271 23:50:50.607833 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3272 23:50:50.607886 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3273 23:50:50.607940 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3274 23:50:50.607993 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3275 23:50:50.608046
3276 23:50:50.608099
3277 23:50:50.608152 ==
3278 23:50:50.608205 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 23:50:50.608259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 23:50:50.608314 ==
3281 23:50:50.608367
3282 23:50:50.608420
3283 23:50:50.608472 TX Vref Scan disable
3284 23:50:50.608555 == TX Byte 0 ==
3285 23:50:50.608608 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3286 23:50:50.608662 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3287 23:50:50.608716 == TX Byte 1 ==
3288 23:50:50.608770 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 23:50:50.608824 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 23:50:50.608878 ==
3291 23:50:50.608931 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 23:50:50.608984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 23:50:50.609039 ==
3294 23:50:50.609092 TX Vref=22, minBit 8, minWin=25, winSum=418
3295 23:50:50.609147 TX Vref=24, minBit 9, minWin=25, winSum=420
3296 23:50:50.609200 TX Vref=26, minBit 9, minWin=25, winSum=422
3297 23:50:50.609255 TX Vref=28, minBit 2, minWin=26, winSum=425
3298 23:50:50.609355 TX Vref=30, minBit 2, minWin=26, winSum=429
3299 23:50:50.609599 TX Vref=32, minBit 9, minWin=25, winSum=426
3300 23:50:50.609659 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3301 23:50:50.609715
3302 23:50:50.609768 Final TX Range 1 Vref 30
3303 23:50:50.609823
3304 23:50:50.609876 ==
3305 23:50:50.609930 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 23:50:50.609984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 23:50:50.610037 ==
3308 23:50:50.610120
3309 23:50:50.610233
3310 23:50:50.610286 TX Vref Scan disable
3311 23:50:50.610340 == TX Byte 0 ==
3312 23:50:50.610393 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3313 23:50:50.610447 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3314 23:50:50.610501 == TX Byte 1 ==
3315 23:50:50.610555 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3316 23:50:50.610608 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3317 23:50:50.610662
3318 23:50:50.610715 [DATLAT]
3319 23:50:50.610768 Freq=1200, CH1 RK0
3320 23:50:50.610821
3321 23:50:50.610875 DATLAT Default: 0xd
3322 23:50:50.610928 0, 0xFFFF, sum = 0
3323 23:50:50.610984 1, 0xFFFF, sum = 0
3324 23:50:50.611039 2, 0xFFFF, sum = 0
3325 23:50:50.611093 3, 0xFFFF, sum = 0
3326 23:50:50.611148 4, 0xFFFF, sum = 0
3327 23:50:50.611203 5, 0xFFFF, sum = 0
3328 23:50:50.611257 6, 0xFFFF, sum = 0
3329 23:50:50.611311 7, 0xFFFF, sum = 0
3330 23:50:50.611367 8, 0xFFFF, sum = 0
3331 23:50:50.611421 9, 0xFFFF, sum = 0
3332 23:50:50.611476 10, 0xFFFF, sum = 0
3333 23:50:50.611530 11, 0xFFFF, sum = 0
3334 23:50:50.611585 12, 0x0, sum = 1
3335 23:50:50.611640 13, 0x0, sum = 2
3336 23:50:50.611723 14, 0x0, sum = 3
3337 23:50:50.611778 15, 0x0, sum = 4
3338 23:50:50.611833 best_step = 13
3339 23:50:50.611887
3340 23:50:50.611939 ==
3341 23:50:50.611993 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 23:50:50.612046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 23:50:50.612100 ==
3344 23:50:50.612153 RX Vref Scan: 1
3345 23:50:50.612206
3346 23:50:50.612259 Set Vref Range= 32 -> 127
3347 23:50:50.612313
3348 23:50:50.612366 RX Vref 32 -> 127, step: 1
3349 23:50:50.612419
3350 23:50:50.612473 RX Delay -13 -> 252, step: 4
3351 23:50:50.612526
3352 23:50:50.612579 Set Vref, RX VrefLevel [Byte0]: 32
3353 23:50:50.612633 [Byte1]: 32
3354 23:50:50.612686
3355 23:50:50.612740 Set Vref, RX VrefLevel [Byte0]: 33
3356 23:50:50.612793 [Byte1]: 33
3357 23:50:50.612846
3358 23:50:50.612900 Set Vref, RX VrefLevel [Byte0]: 34
3359 23:50:50.612954 [Byte1]: 34
3360 23:50:50.613007
3361 23:50:50.613060 Set Vref, RX VrefLevel [Byte0]: 35
3362 23:50:50.613114 [Byte1]: 35
3363 23:50:50.613167
3364 23:50:50.613219 Set Vref, RX VrefLevel [Byte0]: 36
3365 23:50:50.613299 [Byte1]: 36
3366 23:50:50.613367
3367 23:50:50.613420 Set Vref, RX VrefLevel [Byte0]: 37
3368 23:50:50.613475 [Byte1]: 37
3369 23:50:50.613528
3370 23:50:50.613580 Set Vref, RX VrefLevel [Byte0]: 38
3371 23:50:50.613633 [Byte1]: 38
3372 23:50:50.613687
3373 23:50:50.613740 Set Vref, RX VrefLevel [Byte0]: 39
3374 23:50:50.613823 [Byte1]: 39
3375 23:50:50.613922
3376 23:50:50.613989 Set Vref, RX VrefLevel [Byte0]: 40
3377 23:50:50.614042 [Byte1]: 40
3378 23:50:50.614096
3379 23:50:50.614148 Set Vref, RX VrefLevel [Byte0]: 41
3380 23:50:50.614201 [Byte1]: 41
3381 23:50:50.614254
3382 23:50:50.614307 Set Vref, RX VrefLevel [Byte0]: 42
3383 23:50:50.614360 [Byte1]: 42
3384 23:50:50.614413
3385 23:50:50.614466 Set Vref, RX VrefLevel [Byte0]: 43
3386 23:50:50.614518 [Byte1]: 43
3387 23:50:50.614571
3388 23:50:50.614624 Set Vref, RX VrefLevel [Byte0]: 44
3389 23:50:50.614677 [Byte1]: 44
3390 23:50:50.614730
3391 23:50:50.614782 Set Vref, RX VrefLevel [Byte0]: 45
3392 23:50:50.614835 [Byte1]: 45
3393 23:50:50.614888
3394 23:50:50.614940 Set Vref, RX VrefLevel [Byte0]: 46
3395 23:50:50.614993 [Byte1]: 46
3396 23:50:50.615046
3397 23:50:50.615099 Set Vref, RX VrefLevel [Byte0]: 47
3398 23:50:50.615152 [Byte1]: 47
3399 23:50:50.615205
3400 23:50:50.615258 Set Vref, RX VrefLevel [Byte0]: 48
3401 23:50:50.615311 [Byte1]: 48
3402 23:50:50.615364
3403 23:50:50.615417 Set Vref, RX VrefLevel [Byte0]: 49
3404 23:50:50.615487 [Byte1]: 49
3405 23:50:50.615554
3406 23:50:50.615607 Set Vref, RX VrefLevel [Byte0]: 50
3407 23:50:50.615660 [Byte1]: 50
3408 23:50:50.615714
3409 23:50:50.615767 Set Vref, RX VrefLevel [Byte0]: 51
3410 23:50:50.615820 [Byte1]: 51
3411 23:50:50.615873
3412 23:50:50.615927 Set Vref, RX VrefLevel [Byte0]: 52
3413 23:50:50.615980 [Byte1]: 52
3414 23:50:50.616033
3415 23:50:50.616086 Set Vref, RX VrefLevel [Byte0]: 53
3416 23:50:50.616139 [Byte1]: 53
3417 23:50:50.616192
3418 23:50:50.616245 Set Vref, RX VrefLevel [Byte0]: 54
3419 23:50:50.616298 [Byte1]: 54
3420 23:50:50.616351
3421 23:50:50.616403 Set Vref, RX VrefLevel [Byte0]: 55
3422 23:50:50.616456 [Byte1]: 55
3423 23:50:50.616509
3424 23:50:50.616562 Set Vref, RX VrefLevel [Byte0]: 56
3425 23:50:50.616615 [Byte1]: 56
3426 23:50:50.616668
3427 23:50:50.616720 Set Vref, RX VrefLevel [Byte0]: 57
3428 23:50:50.616773 [Byte1]: 57
3429 23:50:50.616826
3430 23:50:50.616879 Set Vref, RX VrefLevel [Byte0]: 58
3431 23:50:50.616933 [Byte1]: 58
3432 23:50:50.616986
3433 23:50:50.617039 Set Vref, RX VrefLevel [Byte0]: 59
3434 23:50:50.617092 [Byte1]: 59
3435 23:50:50.617146
3436 23:50:50.617198 Set Vref, RX VrefLevel [Byte0]: 60
3437 23:50:50.617251 [Byte1]: 60
3438 23:50:50.617353
3439 23:50:50.617406 Set Vref, RX VrefLevel [Byte0]: 61
3440 23:50:50.617460 [Byte1]: 61
3441 23:50:50.617513
3442 23:50:50.617566 Set Vref, RX VrefLevel [Byte0]: 62
3443 23:50:50.617619 [Byte1]: 62
3444 23:50:50.617671
3445 23:50:50.617724 Set Vref, RX VrefLevel [Byte0]: 63
3446 23:50:50.617779 [Byte1]: 63
3447 23:50:50.617832
3448 23:50:50.617885 Set Vref, RX VrefLevel [Byte0]: 64
3449 23:50:50.617938 [Byte1]: 64
3450 23:50:50.617991
3451 23:50:50.618044 Set Vref, RX VrefLevel [Byte0]: 65
3452 23:50:50.618097 [Byte1]: 65
3453 23:50:50.618180
3454 23:50:50.618249 Final RX Vref Byte 0 = 53 to rank0
3455 23:50:50.618316 Final RX Vref Byte 1 = 49 to rank0
3456 23:50:50.618370 Final RX Vref Byte 0 = 53 to rank1
3457 23:50:50.618423 Final RX Vref Byte 1 = 49 to rank1==
3458 23:50:50.618477 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 23:50:50.618530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 23:50:50.618584 ==
3461 23:50:50.618653 DQS Delay:
3462 23:50:50.618720 DQS0 = 0, DQS1 = 0
3463 23:50:50.618773 DQM Delay:
3464 23:50:50.618826 DQM0 = 114, DQM1 = 112
3465 23:50:50.618879 DQ Delay:
3466 23:50:50.618932 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3467 23:50:50.618985 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3468 23:50:50.619038 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
3469 23:50:50.619284 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3470 23:50:50.619343
3471 23:50:50.619397
3472 23:50:50.619450 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3473 23:50:50.619504 CH1 RK0: MR19=304, MR18=F400
3474 23:50:50.619558 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3475 23:50:50.619612
3476 23:50:50.619666 ----->DramcWriteLeveling(PI) begin...
3477 23:50:50.619721 ==
3478 23:50:50.619774 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 23:50:50.619828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 23:50:50.619882 ==
3481 23:50:50.619936 Write leveling (Byte 0): 25 => 25
3482 23:50:50.619990 Write leveling (Byte 1): 27 => 27
3483 23:50:50.620043 DramcWriteLeveling(PI) end<-----
3484 23:50:50.620096
3485 23:50:50.620149 ==
3486 23:50:50.620202 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 23:50:50.620256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 23:50:50.620310 ==
3489 23:50:50.620364 [Gating] SW mode calibration
3490 23:50:50.620418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 23:50:50.620471 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 23:50:50.620526 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 23:50:50.620580 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 23:50:50.620633 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 23:50:50.620687 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 23:50:50.620741 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 23:50:50.620795 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3498 23:50:50.620848 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
3499 23:50:50.620902 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
3500 23:50:50.620955 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 23:50:50.621008 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 23:50:50.621062 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 23:50:50.621115 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 23:50:50.621169 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 23:50:50.621222 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
3506 23:50:50.621302 1 0 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3507 23:50:50.621371 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3508 23:50:50.621424 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 23:50:50.621478 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 23:50:50.621531 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 23:50:50.621584 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 23:50:50.621681 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 23:50:50.621764 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:50:50.621832 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 23:50:50.621885 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3516 23:50:50.621938 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:50:50.621991 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:50:50.622076 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:50:50.622161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:50:50.622214 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:50:50.622269 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:50:50.622322 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:50:50.622376 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:50:50.622429 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:50:50.622482 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:50:50.622535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:50:50.622588 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:50:50.622642 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:50:50.622695 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:50:50.622748 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3531 23:50:50.622802 Total UI for P1: 0, mck2ui 16
3532 23:50:50.622855 best dqsien dly found for B0: ( 1, 3, 22)
3533 23:50:50.622909 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3534 23:50:50.622963 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3535 23:50:50.623016 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 23:50:50.623069 Total UI for P1: 0, mck2ui 16
3537 23:50:50.623122 best dqsien dly found for B1: ( 1, 3, 28)
3538 23:50:50.623176 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3539 23:50:50.623229 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3540 23:50:50.623283
3541 23:50:50.623335 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3542 23:50:50.623389 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3543 23:50:50.623443 [Gating] SW calibration Done
3544 23:50:50.623496 ==
3545 23:50:50.623550 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 23:50:50.623603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 23:50:50.623657 ==
3548 23:50:50.623709 RX Vref Scan: 0
3549 23:50:50.623763
3550 23:50:50.623815 RX Vref 0 -> 0, step: 1
3551 23:50:50.623869
3552 23:50:50.623922 RX Delay -40 -> 252, step: 8
3553 23:50:50.623975 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3554 23:50:50.624029 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3555 23:50:50.624082 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3556 23:50:50.624135 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3557 23:50:50.624188 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3558 23:50:50.624242 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3559 23:50:50.624296 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3560 23:50:50.624349 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3561 23:50:50.624402 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3562 23:50:50.624455 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3563 23:50:50.624508 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3564 23:50:50.624562 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3565 23:50:50.624615 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3566 23:50:50.624729 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3567 23:50:50.624783 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3568 23:50:50.625026 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3569 23:50:50.625085 ==
3570 23:50:50.625140 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 23:50:50.625193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 23:50:50.625248 ==
3573 23:50:50.625347 DQS Delay:
3574 23:50:50.625400 DQS0 = 0, DQS1 = 0
3575 23:50:50.625454 DQM Delay:
3576 23:50:50.625507 DQM0 = 116, DQM1 = 111
3577 23:50:50.625561 DQ Delay:
3578 23:50:50.625614 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3579 23:50:50.625667 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =119
3580 23:50:50.625721 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3581 23:50:50.625774 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3582 23:50:50.625844
3583 23:50:50.625909
3584 23:50:50.626022 ==
3585 23:50:50.626076 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 23:50:50.626129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 23:50:50.626183 ==
3588 23:50:50.626235
3589 23:50:50.626288
3590 23:50:50.626341 TX Vref Scan disable
3591 23:50:50.626394 == TX Byte 0 ==
3592 23:50:50.626447 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3593 23:50:50.626500 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3594 23:50:50.626553 == TX Byte 1 ==
3595 23:50:50.626606 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3596 23:50:50.626659 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3597 23:50:50.626712 ==
3598 23:50:50.626767 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 23:50:50.626839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 23:50:50.626895 ==
3601 23:50:50.626949 TX Vref=22, minBit 9, minWin=24, winSum=415
3602 23:50:50.627003 TX Vref=24, minBit 9, minWin=24, winSum=421
3603 23:50:50.627057 TX Vref=26, minBit 2, minWin=25, winSum=423
3604 23:50:50.627111 TX Vref=28, minBit 9, minWin=25, winSum=425
3605 23:50:50.627164 TX Vref=30, minBit 9, minWin=25, winSum=428
3606 23:50:50.627218 TX Vref=32, minBit 9, minWin=25, winSum=431
3607 23:50:50.627272 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 32
3608 23:50:50.627326
3609 23:50:50.627379 Final TX Range 1 Vref 32
3610 23:50:50.627433
3611 23:50:50.627486 ==
3612 23:50:50.627539 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 23:50:50.627591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 23:50:50.627644 ==
3615 23:50:50.627698
3616 23:50:50.627750
3617 23:50:50.627803 TX Vref Scan disable
3618 23:50:50.627857 == TX Byte 0 ==
3619 23:50:50.627910 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3620 23:50:50.627965 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3621 23:50:50.628019 == TX Byte 1 ==
3622 23:50:50.628072 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 23:50:50.628141 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 23:50:50.628225
3625 23:50:50.628292 [DATLAT]
3626 23:50:50.628345 Freq=1200, CH1 RK1
3627 23:50:50.628399
3628 23:50:50.628452 DATLAT Default: 0xd
3629 23:50:50.628504 0, 0xFFFF, sum = 0
3630 23:50:50.628559 1, 0xFFFF, sum = 0
3631 23:50:50.628613 2, 0xFFFF, sum = 0
3632 23:50:50.628667 3, 0xFFFF, sum = 0
3633 23:50:50.628721 4, 0xFFFF, sum = 0
3634 23:50:50.628775 5, 0xFFFF, sum = 0
3635 23:50:50.628829 6, 0xFFFF, sum = 0
3636 23:50:50.628883 7, 0xFFFF, sum = 0
3637 23:50:50.628937 8, 0xFFFF, sum = 0
3638 23:50:50.628991 9, 0xFFFF, sum = 0
3639 23:50:50.629045 10, 0xFFFF, sum = 0
3640 23:50:50.629101 11, 0xFFFF, sum = 0
3641 23:50:50.629155 12, 0x0, sum = 1
3642 23:50:50.629210 13, 0x0, sum = 2
3643 23:50:50.629301 14, 0x0, sum = 3
3644 23:50:50.629357 15, 0x0, sum = 4
3645 23:50:50.629411 best_step = 13
3646 23:50:50.629463
3647 23:50:50.629516 ==
3648 23:50:50.629569 Dram Type= 6, Freq= 0, CH_1, rank 1
3649 23:50:50.629622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3650 23:50:50.629677 ==
3651 23:50:50.629730 RX Vref Scan: 0
3652 23:50:50.629782
3653 23:50:50.629835 RX Vref 0 -> 0, step: 1
3654 23:50:50.629888
3655 23:50:50.629940 RX Delay -13 -> 252, step: 4
3656 23:50:50.629993 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3657 23:50:50.630046 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3658 23:50:50.630099 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3659 23:50:50.630153 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3660 23:50:50.630206 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3661 23:50:50.630259 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3662 23:50:50.630312 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3663 23:50:50.630365 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3664 23:50:50.630418 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3665 23:50:50.630471 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3666 23:50:50.630524 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3667 23:50:50.630578 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3668 23:50:50.630631 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3669 23:50:50.630684 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3670 23:50:50.630737 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3671 23:50:50.630790 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3672 23:50:50.630843 ==
3673 23:50:50.630896 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 23:50:50.630949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 23:50:50.631003 ==
3676 23:50:50.631056 DQS Delay:
3677 23:50:50.631108 DQS0 = 0, DQS1 = 0
3678 23:50:50.631162 DQM Delay:
3679 23:50:50.631215 DQM0 = 115, DQM1 = 112
3680 23:50:50.631268 DQ Delay:
3681 23:50:50.631322 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3682 23:50:50.631376 DQ4 =116, DQ5 =124, DQ6 =120, DQ7 =112
3683 23:50:50.631429 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3684 23:50:50.631482 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3685 23:50:50.631536
3686 23:50:50.631588
3687 23:50:50.631642 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3688 23:50:50.631697 CH1 RK1: MR19=304, MR18=F709
3689 23:50:50.631750 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3690 23:50:50.631804 [RxdqsGatingPostProcess] freq 1200
3691 23:50:50.631857 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3692 23:50:50.631911 best DQS0 dly(2T, 0.5T) = (0, 11)
3693 23:50:50.631965 best DQS1 dly(2T, 0.5T) = (0, 11)
3694 23:50:50.632017 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3695 23:50:50.632070 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3696 23:50:50.632123 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 23:50:50.632176 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 23:50:50.632229 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 23:50:50.632282 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 23:50:50.632335 Pre-setting of DQS Precalculation
3701 23:50:50.632388 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3702 23:50:50.632442 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3703 23:50:50.632495 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3704 23:50:50.632549
3705 23:50:50.632602
3706 23:50:50.632654 [Calibration Summary] 2400 Mbps
3707 23:50:50.632707 CH 0, Rank 0
3708 23:50:50.632950 SW Impedance : PASS
3709 23:50:50.633009 DUTY Scan : NO K
3710 23:50:50.633063 ZQ Calibration : PASS
3711 23:50:50.633116 Jitter Meter : NO K
3712 23:50:50.633170 CBT Training : PASS
3713 23:50:50.633222 Write leveling : PASS
3714 23:50:50.633298 RX DQS gating : PASS
3715 23:50:50.633365 RX DQ/DQS(RDDQC) : PASS
3716 23:50:50.633418 TX DQ/DQS : PASS
3717 23:50:50.633472 RX DATLAT : PASS
3718 23:50:50.633525 RX DQ/DQS(Engine): PASS
3719 23:50:50.633578 TX OE : NO K
3720 23:50:50.633632 All Pass.
3721 23:50:50.633685
3722 23:50:50.633738 CH 0, Rank 1
3723 23:50:50.633791 SW Impedance : PASS
3724 23:50:50.633844 DUTY Scan : NO K
3725 23:50:50.633897 ZQ Calibration : PASS
3726 23:50:50.633949 Jitter Meter : NO K
3727 23:50:50.634003 CBT Training : PASS
3728 23:50:50.634055 Write leveling : PASS
3729 23:50:50.634108 RX DQS gating : PASS
3730 23:50:50.634161 RX DQ/DQS(RDDQC) : PASS
3731 23:50:50.634213 TX DQ/DQS : PASS
3732 23:50:50.634266 RX DATLAT : PASS
3733 23:50:50.634319 RX DQ/DQS(Engine): PASS
3734 23:50:50.634371 TX OE : NO K
3735 23:50:50.634425 All Pass.
3736 23:50:50.634478
3737 23:50:50.634531 CH 1, Rank 0
3738 23:50:50.634583 SW Impedance : PASS
3739 23:50:50.634637 DUTY Scan : NO K
3740 23:50:50.634689 ZQ Calibration : PASS
3741 23:50:50.634742 Jitter Meter : NO K
3742 23:50:50.634794 CBT Training : PASS
3743 23:50:50.634846 Write leveling : PASS
3744 23:50:50.634899 RX DQS gating : PASS
3745 23:50:50.634953 RX DQ/DQS(RDDQC) : PASS
3746 23:50:50.635005 TX DQ/DQS : PASS
3747 23:50:50.635058 RX DATLAT : PASS
3748 23:50:50.635111 RX DQ/DQS(Engine): PASS
3749 23:50:50.635164 TX OE : NO K
3750 23:50:50.635218 All Pass.
3751 23:50:50.635270
3752 23:50:50.635324 CH 1, Rank 1
3753 23:50:50.635376 SW Impedance : PASS
3754 23:50:50.635430 DUTY Scan : NO K
3755 23:50:50.635482 ZQ Calibration : PASS
3756 23:50:50.635535 Jitter Meter : NO K
3757 23:50:50.635588 CBT Training : PASS
3758 23:50:50.635641 Write leveling : PASS
3759 23:50:50.635694 RX DQS gating : PASS
3760 23:50:50.635747 RX DQ/DQS(RDDQC) : PASS
3761 23:50:50.635800 TX DQ/DQS : PASS
3762 23:50:50.635853 RX DATLAT : PASS
3763 23:50:50.635906 RX DQ/DQS(Engine): PASS
3764 23:50:50.635959 TX OE : NO K
3765 23:50:50.636013 All Pass.
3766 23:50:50.636066
3767 23:50:50.636119 DramC Write-DBI off
3768 23:50:50.636172 PER_BANK_REFRESH: Hybrid Mode
3769 23:50:50.636224 TX_TRACKING: ON
3770 23:50:50.636278 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3771 23:50:50.636332 [FAST_K] Save calibration result to emmc
3772 23:50:50.636386 dramc_set_vcore_voltage set vcore to 650000
3773 23:50:50.636438 Read voltage for 600, 5
3774 23:50:50.636491 Vio18 = 0
3775 23:50:50.636544 Vcore = 650000
3776 23:50:50.636596 Vdram = 0
3777 23:50:50.636648 Vddq = 0
3778 23:50:50.636700 Vmddr = 0
3779 23:50:50.636753 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3780 23:50:50.636807 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3781 23:50:50.636860 MEM_TYPE=3, freq_sel=19
3782 23:50:50.636912 sv_algorithm_assistance_LP4_1600
3783 23:50:50.636965 ============ PULL DRAM RESETB DOWN ============
3784 23:50:50.637018 ========== PULL DRAM RESETB DOWN end =========
3785 23:50:50.637072 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3786 23:50:50.637125 ===================================
3787 23:50:50.637179 LPDDR4 DRAM CONFIGURATION
3788 23:50:50.637232 ===================================
3789 23:50:50.637330 EX_ROW_EN[0] = 0x0
3790 23:50:50.637384 EX_ROW_EN[1] = 0x0
3791 23:50:50.637437 LP4Y_EN = 0x0
3792 23:50:50.637491 WORK_FSP = 0x0
3793 23:50:50.637543 WL = 0x2
3794 23:50:50.637596 RL = 0x2
3795 23:50:50.637649 BL = 0x2
3796 23:50:50.637701 RPST = 0x0
3797 23:50:50.637754 RD_PRE = 0x0
3798 23:50:50.637807 WR_PRE = 0x1
3799 23:50:50.637860 WR_PST = 0x0
3800 23:50:50.637929 DBI_WR = 0x0
3801 23:50:50.637995 DBI_RD = 0x0
3802 23:50:50.638048 OTF = 0x1
3803 23:50:50.638101 ===================================
3804 23:50:50.638154 ===================================
3805 23:50:50.638209 ANA top config
3806 23:50:50.638262 ===================================
3807 23:50:50.638316 DLL_ASYNC_EN = 0
3808 23:50:50.638369 ALL_SLAVE_EN = 1
3809 23:50:50.638422 NEW_RANK_MODE = 1
3810 23:50:50.638476 DLL_IDLE_MODE = 1
3811 23:50:50.638530 LP45_APHY_COMB_EN = 1
3812 23:50:50.638583 TX_ODT_DIS = 1
3813 23:50:50.638636 NEW_8X_MODE = 1
3814 23:50:50.638690 ===================================
3815 23:50:50.638744 ===================================
3816 23:50:50.638798 data_rate = 1200
3817 23:50:50.638851 CKR = 1
3818 23:50:50.638904 DQ_P2S_RATIO = 8
3819 23:50:50.638957 ===================================
3820 23:50:50.639011 CA_P2S_RATIO = 8
3821 23:50:50.639063 DQ_CA_OPEN = 0
3822 23:50:50.639116 DQ_SEMI_OPEN = 0
3823 23:50:50.639168 CA_SEMI_OPEN = 0
3824 23:50:50.639221 CA_FULL_RATE = 0
3825 23:50:50.639274 DQ_CKDIV4_EN = 1
3826 23:50:50.639326 CA_CKDIV4_EN = 1
3827 23:50:50.639380 CA_PREDIV_EN = 0
3828 23:50:50.639433 PH8_DLY = 0
3829 23:50:50.639486 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3830 23:50:50.639539 DQ_AAMCK_DIV = 4
3831 23:50:50.639592 CA_AAMCK_DIV = 4
3832 23:50:50.639644 CA_ADMCK_DIV = 4
3833 23:50:50.639698 DQ_TRACK_CA_EN = 0
3834 23:50:50.639750 CA_PICK = 600
3835 23:50:50.639803 CA_MCKIO = 600
3836 23:50:50.639857 MCKIO_SEMI = 0
3837 23:50:50.639910 PLL_FREQ = 2288
3838 23:50:50.639963 DQ_UI_PI_RATIO = 32
3839 23:50:50.640017 CA_UI_PI_RATIO = 0
3840 23:50:50.640070 ===================================
3841 23:50:50.640123 ===================================
3842 23:50:50.640176 memory_type:LPDDR4
3843 23:50:50.640229 GP_NUM : 10
3844 23:50:50.640283 SRAM_EN : 1
3845 23:50:50.640336 MD32_EN : 0
3846 23:50:50.640390 ===================================
3847 23:50:50.640442 [ANA_INIT] >>>>>>>>>>>>>>
3848 23:50:50.640495 <<<<<< [CONFIGURE PHASE]: ANA_TX
3849 23:50:50.640549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3850 23:50:50.640602 ===================================
3851 23:50:50.640667 data_rate = 1200,PCW = 0X5800
3852 23:50:50.640723 ===================================
3853 23:50:50.641028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3854 23:50:50.647862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 23:50:50.654702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3856 23:50:50.657785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3857 23:50:50.660943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3858 23:50:50.664622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3859 23:50:50.667495 [ANA_INIT] flow start
3860 23:50:50.667577 [ANA_INIT] PLL >>>>>>>>
3861 23:50:50.670683 [ANA_INIT] PLL <<<<<<<<
3862 23:50:50.674629 [ANA_INIT] MIDPI >>>>>>>>
3863 23:50:50.677411 [ANA_INIT] MIDPI <<<<<<<<
3864 23:50:50.677492 [ANA_INIT] DLL >>>>>>>>
3865 23:50:50.680867 [ANA_INIT] flow end
3866 23:50:50.684212 ============ LP4 DIFF to SE enter ============
3867 23:50:50.687518 ============ LP4 DIFF to SE exit ============
3868 23:50:50.690941 [ANA_INIT] <<<<<<<<<<<<<
3869 23:50:50.694134 [Flow] Enable top DCM control >>>>>
3870 23:50:50.697824 [Flow] Enable top DCM control <<<<<
3871 23:50:50.700681 Enable DLL master slave shuffle
3872 23:50:50.707319 ==============================================================
3873 23:50:50.707401 Gating Mode config
3874 23:50:50.713710 ==============================================================
3875 23:50:50.713793 Config description:
3876 23:50:50.723650 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3877 23:50:50.730301 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3878 23:50:50.737071 SELPH_MODE 0: By rank 1: By Phase
3879 23:50:50.740247 ==============================================================
3880 23:50:50.743554 GAT_TRACK_EN = 1
3881 23:50:50.746698 RX_GATING_MODE = 2
3882 23:50:50.750203 RX_GATING_TRACK_MODE = 2
3883 23:50:50.753445 SELPH_MODE = 1
3884 23:50:50.756659 PICG_EARLY_EN = 1
3885 23:50:50.759832 VALID_LAT_VALUE = 1
3886 23:50:50.767382 ==============================================================
3887 23:50:50.769947 Enter into Gating configuration >>>>
3888 23:50:50.773550 Exit from Gating configuration <<<<
3889 23:50:50.776835 Enter into DVFS_PRE_config >>>>>
3890 23:50:50.786167 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3891 23:50:50.789750 Exit from DVFS_PRE_config <<<<<
3892 23:50:50.792682 Enter into PICG configuration >>>>
3893 23:50:50.796175 Exit from PICG configuration <<<<
3894 23:50:50.799357 [RX_INPUT] configuration >>>>>
3895 23:50:50.799439 [RX_INPUT] configuration <<<<<
3896 23:50:50.805830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3897 23:50:50.812426 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3898 23:50:50.819452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 23:50:50.822473 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 23:50:50.829034 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3901 23:50:50.835697 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3902 23:50:50.838898 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3903 23:50:50.842336 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3904 23:50:50.848887 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3905 23:50:50.852296 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3906 23:50:50.855718 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3907 23:50:50.862146 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3908 23:50:50.865361 ===================================
3909 23:50:50.865444 LPDDR4 DRAM CONFIGURATION
3910 23:50:50.869025 ===================================
3911 23:50:50.872055 EX_ROW_EN[0] = 0x0
3912 23:50:50.875123 EX_ROW_EN[1] = 0x0
3913 23:50:50.875205 LP4Y_EN = 0x0
3914 23:50:50.879495 WORK_FSP = 0x0
3915 23:50:50.879576 WL = 0x2
3916 23:50:50.882292 RL = 0x2
3917 23:50:50.882374 BL = 0x2
3918 23:50:50.885526 RPST = 0x0
3919 23:50:50.885608 RD_PRE = 0x0
3920 23:50:50.888937 WR_PRE = 0x1
3921 23:50:50.889019 WR_PST = 0x0
3922 23:50:50.891910 DBI_WR = 0x0
3923 23:50:50.891991 DBI_RD = 0x0
3924 23:50:50.895028 OTF = 0x1
3925 23:50:50.898379 ===================================
3926 23:50:50.901558 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3927 23:50:50.905773 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3928 23:50:50.911899 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3929 23:50:50.914894 ===================================
3930 23:50:50.914977 LPDDR4 DRAM CONFIGURATION
3931 23:50:50.918080 ===================================
3932 23:50:50.921536 EX_ROW_EN[0] = 0x10
3933 23:50:50.924950 EX_ROW_EN[1] = 0x0
3934 23:50:50.925048 LP4Y_EN = 0x0
3935 23:50:50.928254 WORK_FSP = 0x0
3936 23:50:50.928336 WL = 0x2
3937 23:50:50.931575 RL = 0x2
3938 23:50:50.931657 BL = 0x2
3939 23:50:50.934717 RPST = 0x0
3940 23:50:50.934800 RD_PRE = 0x0
3941 23:50:50.937535 WR_PRE = 0x1
3942 23:50:50.937618 WR_PST = 0x0
3943 23:50:50.941253 DBI_WR = 0x0
3944 23:50:50.941358 DBI_RD = 0x0
3945 23:50:50.944730 OTF = 0x1
3946 23:50:50.947825 ===================================
3947 23:50:50.954253 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3948 23:50:50.957392 nWR fixed to 30
3949 23:50:50.961084 [ModeRegInit_LP4] CH0 RK0
3950 23:50:50.961183 [ModeRegInit_LP4] CH0 RK1
3951 23:50:50.964072 [ModeRegInit_LP4] CH1 RK0
3952 23:50:50.967805 [ModeRegInit_LP4] CH1 RK1
3953 23:50:50.967888 match AC timing 17
3954 23:50:50.974117 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3955 23:50:50.977816 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3956 23:50:50.980689 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3957 23:50:50.987607 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3958 23:50:50.990632 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3959 23:50:50.990715 ==
3960 23:50:50.994297 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 23:50:50.997482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 23:50:50.997566 ==
3963 23:50:51.004136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 23:50:51.010701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3965 23:50:51.014003 [CA 0] Center 36 (6~67) winsize 62
3966 23:50:51.017506 [CA 1] Center 36 (5~67) winsize 63
3967 23:50:51.020272 [CA 2] Center 34 (3~65) winsize 63
3968 23:50:51.023851 [CA 3] Center 34 (3~65) winsize 63
3969 23:50:51.026747 [CA 4] Center 33 (3~64) winsize 62
3970 23:50:51.030135 [CA 5] Center 33 (3~64) winsize 62
3971 23:50:51.030218
3972 23:50:51.033619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3973 23:50:51.033702
3974 23:50:51.036934 [CATrainingPosCal] consider 1 rank data
3975 23:50:51.040106 u2DelayCellTimex100 = 270/100 ps
3976 23:50:51.043476 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3977 23:50:51.046608 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3978 23:50:51.050417 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3979 23:50:51.053406 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3980 23:50:51.060555 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 23:50:51.063438 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 23:50:51.063545
3983 23:50:51.066415 CA PerBit enable=1, Macro0, CA PI delay=33
3984 23:50:51.066518
3985 23:50:51.070016 [CBTSetCACLKResult] CA Dly = 33
3986 23:50:51.070097 CS Dly: 6 (0~37)
3987 23:50:51.070166 ==
3988 23:50:51.073687 Dram Type= 6, Freq= 0, CH_0, rank 1
3989 23:50:51.079888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 23:50:51.079985 ==
3991 23:50:51.083168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3992 23:50:51.089739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3993 23:50:51.092694 [CA 0] Center 36 (6~67) winsize 62
3994 23:50:51.095989 [CA 1] Center 36 (6~67) winsize 62
3995 23:50:51.099622 [CA 2] Center 34 (4~65) winsize 62
3996 23:50:51.102995 [CA 3] Center 34 (3~65) winsize 63
3997 23:50:51.106035 [CA 4] Center 34 (3~65) winsize 63
3998 23:50:51.109361 [CA 5] Center 33 (3~64) winsize 62
3999 23:50:51.109444
4000 23:50:51.112730 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4001 23:50:51.112813
4002 23:50:51.116041 [CATrainingPosCal] consider 2 rank data
4003 23:50:51.119447 u2DelayCellTimex100 = 270/100 ps
4004 23:50:51.122581 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4005 23:50:51.129826 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4006 23:50:51.132821 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 23:50:51.135498 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4008 23:50:51.138890 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 23:50:51.142319 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4010 23:50:51.142402
4011 23:50:51.145646 CA PerBit enable=1, Macro0, CA PI delay=33
4012 23:50:51.145729
4013 23:50:51.148863 [CBTSetCACLKResult] CA Dly = 33
4014 23:50:51.152505 CS Dly: 6 (0~37)
4015 23:50:51.152587
4016 23:50:51.155489 ----->DramcWriteLeveling(PI) begin...
4017 23:50:51.155573 ==
4018 23:50:51.159077 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 23:50:51.161953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 23:50:51.162037 ==
4021 23:50:51.165185 Write leveling (Byte 0): 33 => 33
4022 23:50:51.168685 Write leveling (Byte 1): 30 => 30
4023 23:50:51.171995 DramcWriteLeveling(PI) end<-----
4024 23:50:51.172077
4025 23:50:51.172143 ==
4026 23:50:51.175217 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 23:50:51.178176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 23:50:51.178259 ==
4029 23:50:51.181956 [Gating] SW mode calibration
4030 23:50:51.188258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4031 23:50:51.194835 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4032 23:50:51.198355 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 23:50:51.204574 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 23:50:51.208306 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 23:50:51.211298 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4036 23:50:51.217758 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
4037 23:50:51.221166 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 23:50:51.224814 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 23:50:51.231036 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 23:50:51.234691 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 23:50:51.238040 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 23:50:51.244205 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 23:50:51.247396 0 10 12 | B1->B0 | 2828 3131 | 0 1 | (0 0) (0 0)
4044 23:50:51.251058 0 10 16 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
4045 23:50:51.254174 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 23:50:51.261187 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 23:50:51.264342 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 23:50:51.267449 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 23:50:51.274823 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:50:51.277429 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:50:51.281481 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:50:51.287714 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4053 23:50:51.291183 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:50:51.294650 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:50:51.300825 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:50:51.303614 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:50:51.307515 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:50:51.314264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:50:51.317410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:50:51.320862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:50:51.326721 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:50:51.329957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:50:51.333456 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:50:51.340086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:50:51.343304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:50:51.346813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:50:51.353027 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4068 23:50:51.356511 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4069 23:50:51.359997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:50:51.363139 Total UI for P1: 0, mck2ui 16
4071 23:50:51.366716 best dqsien dly found for B0: ( 0, 13, 14)
4072 23:50:51.369861 Total UI for P1: 0, mck2ui 16
4073 23:50:51.373211 best dqsien dly found for B1: ( 0, 13, 16)
4074 23:50:51.376281 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4075 23:50:51.383353 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4076 23:50:51.383435
4077 23:50:51.386938 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4078 23:50:51.389713 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4079 23:50:51.393073 [Gating] SW calibration Done
4080 23:50:51.393159 ==
4081 23:50:51.396520 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 23:50:51.399752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 23:50:51.399857 ==
4084 23:50:51.399950 RX Vref Scan: 0
4085 23:50:51.402966
4086 23:50:51.403065 RX Vref 0 -> 0, step: 1
4087 23:50:51.403155
4088 23:50:51.406308 RX Delay -230 -> 252, step: 16
4089 23:50:51.409168 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4090 23:50:51.416234 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4091 23:50:51.419459 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4092 23:50:51.422834 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4093 23:50:51.426142 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4094 23:50:51.433203 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4095 23:50:51.435665 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4096 23:50:51.439083 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4097 23:50:51.442732 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4098 23:50:51.446577 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4099 23:50:51.452398 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4100 23:50:51.455616 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4101 23:50:51.458973 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4102 23:50:51.462414 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4103 23:50:51.468929 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4104 23:50:51.472276 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4105 23:50:51.472362 ==
4106 23:50:51.475677 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 23:50:51.478671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 23:50:51.478757 ==
4109 23:50:51.481701 DQS Delay:
4110 23:50:51.481786 DQS0 = 0, DQS1 = 0
4111 23:50:51.484990 DQM Delay:
4112 23:50:51.485075 DQM0 = 40, DQM1 = 33
4113 23:50:51.485177 DQ Delay:
4114 23:50:51.488482 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4115 23:50:51.491591 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4116 23:50:51.495177 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4117 23:50:51.498462 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4118 23:50:51.498547
4119 23:50:51.498634
4120 23:50:51.502585 ==
4121 23:50:51.504847 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 23:50:51.508113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 23:50:51.508200 ==
4124 23:50:51.508285
4125 23:50:51.508365
4126 23:50:51.511426 TX Vref Scan disable
4127 23:50:51.511511 == TX Byte 0 ==
4128 23:50:51.518333 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4129 23:50:51.521449 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4130 23:50:51.521535 == TX Byte 1 ==
4131 23:50:51.527903 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4132 23:50:51.531367 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4133 23:50:51.531453 ==
4134 23:50:51.534538 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:50:51.538399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:50:51.538507 ==
4137 23:50:51.538601
4138 23:50:51.538689
4139 23:50:51.541191 TX Vref Scan disable
4140 23:50:51.544549 == TX Byte 0 ==
4141 23:50:51.547583 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4142 23:50:51.551102 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4143 23:50:51.554135 == TX Byte 1 ==
4144 23:50:51.557642 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4145 23:50:51.560897 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4146 23:50:51.564102
4147 23:50:51.564181 [DATLAT]
4148 23:50:51.564272 Freq=600, CH0 RK0
4149 23:50:51.564361
4150 23:50:51.567498 DATLAT Default: 0x9
4151 23:50:51.567571 0, 0xFFFF, sum = 0
4152 23:50:51.570725 1, 0xFFFF, sum = 0
4153 23:50:51.570795 2, 0xFFFF, sum = 0
4154 23:50:51.574357 3, 0xFFFF, sum = 0
4155 23:50:51.577435 4, 0xFFFF, sum = 0
4156 23:50:51.577509 5, 0xFFFF, sum = 0
4157 23:50:51.580868 6, 0xFFFF, sum = 0
4158 23:50:51.580941 7, 0xFFFF, sum = 0
4159 23:50:51.583863 8, 0x0, sum = 1
4160 23:50:51.583956 9, 0x0, sum = 2
4161 23:50:51.584019 10, 0x0, sum = 3
4162 23:50:51.587429 11, 0x0, sum = 4
4163 23:50:51.587502 best_step = 9
4164 23:50:51.587562
4165 23:50:51.590992 ==
4166 23:50:51.591064 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 23:50:51.597152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 23:50:51.597253 ==
4169 23:50:51.597381 RX Vref Scan: 1
4170 23:50:51.597447
4171 23:50:51.600298 RX Vref 0 -> 0, step: 1
4172 23:50:51.600371
4173 23:50:51.603813 RX Delay -195 -> 252, step: 8
4174 23:50:51.603887
4175 23:50:51.607525 Set Vref, RX VrefLevel [Byte0]: 53
4176 23:50:51.610282 [Byte1]: 47
4177 23:50:51.610355
4178 23:50:51.613662 Final RX Vref Byte 0 = 53 to rank0
4179 23:50:51.616768 Final RX Vref Byte 1 = 47 to rank0
4180 23:50:51.620803 Final RX Vref Byte 0 = 53 to rank1
4181 23:50:51.623737 Final RX Vref Byte 1 = 47 to rank1==
4182 23:50:51.626569 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 23:50:51.629987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 23:50:51.633491 ==
4185 23:50:51.633590 DQS Delay:
4186 23:50:51.633679 DQS0 = 0, DQS1 = 0
4187 23:50:51.636594 DQM Delay:
4188 23:50:51.636672 DQM0 = 41, DQM1 = 34
4189 23:50:51.640183 DQ Delay:
4190 23:50:51.643161 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4191 23:50:51.643259 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4192 23:50:51.646466 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4193 23:50:51.653516 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4194 23:50:51.653603
4195 23:50:51.653690
4196 23:50:51.659568 [DQSOSCAuto] RK0, (LSB)MR18= 0x5047, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4197 23:50:51.663119 CH0 RK0: MR19=808, MR18=5047
4198 23:50:51.669315 CH0_RK0: MR19=0x808, MR18=0x5047, DQSOSC=394, MR23=63, INC=168, DEC=112
4199 23:50:51.669402
4200 23:50:51.673106 ----->DramcWriteLeveling(PI) begin...
4201 23:50:51.673193 ==
4202 23:50:51.676094 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 23:50:51.679617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 23:50:51.679703 ==
4205 23:50:51.682770 Write leveling (Byte 0): 34 => 34
4206 23:50:51.686501 Write leveling (Byte 1): 31 => 31
4207 23:50:51.689074 DramcWriteLeveling(PI) end<-----
4208 23:50:51.689159
4209 23:50:51.689284 ==
4210 23:50:51.692494 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 23:50:51.695865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 23:50:51.695952 ==
4213 23:50:51.698884 [Gating] SW mode calibration
4214 23:50:51.705927 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4215 23:50:51.712801 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4216 23:50:51.715698 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 23:50:51.722271 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 23:50:51.725203 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 23:50:51.729578 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
4220 23:50:51.735243 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4221 23:50:51.738446 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 23:50:51.741827 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:50:51.748655 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 23:50:51.752211 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:50:51.754876 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 23:50:51.761446 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4227 23:50:51.765437 0 10 12 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
4228 23:50:51.768379 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
4229 23:50:51.775351 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 23:50:51.778586 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 23:50:51.781642 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 23:50:51.787963 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:50:51.791411 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:50:51.794728 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:50:51.801404 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4236 23:50:51.805212 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:50:51.807641 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:50:51.814880 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:50:51.817878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:50:51.821148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:50:51.827432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:50:51.830882 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:50:51.834055 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:50:51.840894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:50:51.843974 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:50:51.847213 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:50:51.854071 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:50:51.857475 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:50:51.860366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:50:51.866983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:50:51.870190 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4252 23:50:51.873686 Total UI for P1: 0, mck2ui 16
4253 23:50:51.877078 best dqsien dly found for B0: ( 0, 13, 10)
4254 23:50:51.880003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 23:50:51.883559 Total UI for P1: 0, mck2ui 16
4256 23:50:51.886758 best dqsien dly found for B1: ( 0, 13, 12)
4257 23:50:51.890465 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4258 23:50:51.896789 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4259 23:50:51.896891
4260 23:50:51.899743 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4261 23:50:51.903256 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4262 23:50:51.906903 [Gating] SW calibration Done
4263 23:50:51.906999 ==
4264 23:50:51.910195 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 23:50:51.912931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 23:50:51.912999 ==
4267 23:50:51.916586 RX Vref Scan: 0
4268 23:50:51.916680
4269 23:50:51.916770 RX Vref 0 -> 0, step: 1
4270 23:50:51.916856
4271 23:50:51.919782 RX Delay -230 -> 252, step: 16
4272 23:50:51.923549 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4273 23:50:51.930308 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4274 23:50:51.933172 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4275 23:50:51.936217 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4276 23:50:51.939634 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4277 23:50:51.945746 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4278 23:50:51.949648 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4279 23:50:51.952717 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4280 23:50:51.955987 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4281 23:50:51.962582 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4282 23:50:51.965499 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4283 23:50:51.969545 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4284 23:50:51.972304 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4285 23:50:51.978652 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4286 23:50:51.981909 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4287 23:50:51.985370 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4288 23:50:51.985451 ==
4289 23:50:51.989036 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 23:50:51.991625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 23:50:51.995286 ==
4292 23:50:51.995388 DQS Delay:
4293 23:50:51.995479 DQS0 = 0, DQS1 = 0
4294 23:50:51.998724 DQM Delay:
4295 23:50:51.998825 DQM0 = 40, DQM1 = 30
4296 23:50:52.001966 DQ Delay:
4297 23:50:52.002041 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4298 23:50:52.005252 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4299 23:50:52.008600 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4300 23:50:52.012196 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4301 23:50:52.012282
4302 23:50:52.015120
4303 23:50:52.015205 ==
4304 23:50:52.018183 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 23:50:52.022196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 23:50:52.022282 ==
4307 23:50:52.022367
4308 23:50:52.022449
4309 23:50:52.024851 TX Vref Scan disable
4310 23:50:52.024926 == TX Byte 0 ==
4311 23:50:52.032013 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4312 23:50:52.034917 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4313 23:50:52.035002 == TX Byte 1 ==
4314 23:50:52.041382 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4315 23:50:52.044671 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4316 23:50:52.044757 ==
4317 23:50:52.048117 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 23:50:52.050938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 23:50:52.051026 ==
4320 23:50:52.051112
4321 23:50:52.054253
4322 23:50:52.054338 TX Vref Scan disable
4323 23:50:52.057861 == TX Byte 0 ==
4324 23:50:52.061104 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4325 23:50:52.067708 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4326 23:50:52.067794 == TX Byte 1 ==
4327 23:50:52.070757 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4328 23:50:52.077827 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4329 23:50:52.077935
4330 23:50:52.078033 [DATLAT]
4331 23:50:52.078121 Freq=600, CH0 RK1
4332 23:50:52.078216
4333 23:50:52.081309 DATLAT Default: 0x9
4334 23:50:52.084252 0, 0xFFFF, sum = 0
4335 23:50:52.084358 1, 0xFFFF, sum = 0
4336 23:50:52.087679 2, 0xFFFF, sum = 0
4337 23:50:52.087765 3, 0xFFFF, sum = 0
4338 23:50:52.090906 4, 0xFFFF, sum = 0
4339 23:50:52.090993 5, 0xFFFF, sum = 0
4340 23:50:52.094452 6, 0xFFFF, sum = 0
4341 23:50:52.094539 7, 0xFFFF, sum = 0
4342 23:50:52.097790 8, 0x0, sum = 1
4343 23:50:52.097877 9, 0x0, sum = 2
4344 23:50:52.100965 10, 0x0, sum = 3
4345 23:50:52.101078 11, 0x0, sum = 4
4346 23:50:52.101184 best_step = 9
4347 23:50:52.101320
4348 23:50:52.103790 ==
4349 23:50:52.107357 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 23:50:52.110364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 23:50:52.110450 ==
4352 23:50:52.110537 RX Vref Scan: 0
4353 23:50:52.110618
4354 23:50:52.113779 RX Vref 0 -> 0, step: 1
4355 23:50:52.113864
4356 23:50:52.117021 RX Delay -195 -> 252, step: 8
4357 23:50:52.123664 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4358 23:50:52.126994 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4359 23:50:52.130290 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4360 23:50:52.133715 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4361 23:50:52.140192 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4362 23:50:52.143555 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4363 23:50:52.146655 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4364 23:50:52.149813 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4365 23:50:52.153244 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4366 23:50:52.160363 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4367 23:50:52.163112 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4368 23:50:52.166295 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4369 23:50:52.169941 iDelay=197, Bit 12, Center 36 (-115 ~ 188) 304
4370 23:50:52.176401 iDelay=197, Bit 13, Center 36 (-115 ~ 188) 304
4371 23:50:52.180421 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4372 23:50:52.182921 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4373 23:50:52.183004 ==
4374 23:50:52.186142 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 23:50:52.189390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 23:50:52.192820 ==
4377 23:50:52.192902 DQS Delay:
4378 23:50:52.192966 DQS0 = 0, DQS1 = 0
4379 23:50:52.196658 DQM Delay:
4380 23:50:52.196739 DQM0 = 40, DQM1 = 32
4381 23:50:52.199839 DQ Delay:
4382 23:50:52.202440 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4383 23:50:52.206086 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4384 23:50:52.206168 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4385 23:50:52.212685 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4386 23:50:52.212768
4387 23:50:52.212832
4388 23:50:52.219138 [DQSOSCAuto] RK1, (LSB)MR18= 0x4440, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4389 23:50:52.222623 CH0 RK1: MR19=808, MR18=4440
4390 23:50:52.229009 CH0_RK1: MR19=0x808, MR18=0x4440, DQSOSC=396, MR23=63, INC=167, DEC=111
4391 23:50:52.232594 [RxdqsGatingPostProcess] freq 600
4392 23:50:52.235384 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4393 23:50:52.238920 Pre-setting of DQS Precalculation
4394 23:50:52.245306 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4395 23:50:52.245388 ==
4396 23:50:52.248758 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 23:50:52.252291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 23:50:52.252374 ==
4399 23:50:52.258706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 23:50:52.265245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4401 23:50:52.268146 [CA 0] Center 35 (5~66) winsize 62
4402 23:50:52.271502 [CA 1] Center 35 (5~66) winsize 62
4403 23:50:52.275065 [CA 2] Center 35 (5~65) winsize 61
4404 23:50:52.278134 [CA 3] Center 34 (3~65) winsize 63
4405 23:50:52.281500 [CA 4] Center 34 (4~65) winsize 62
4406 23:50:52.284946 [CA 5] Center 34 (3~65) winsize 63
4407 23:50:52.285028
4408 23:50:52.289129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4409 23:50:52.289237
4410 23:50:52.291474 [CATrainingPosCal] consider 1 rank data
4411 23:50:52.295134 u2DelayCellTimex100 = 270/100 ps
4412 23:50:52.298487 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4413 23:50:52.301278 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4414 23:50:52.304753 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4415 23:50:52.308213 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4416 23:50:52.311184 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4417 23:50:52.314535 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4418 23:50:52.314621
4419 23:50:52.320975 CA PerBit enable=1, Macro0, CA PI delay=34
4420 23:50:52.321061
4421 23:50:52.324327 [CBTSetCACLKResult] CA Dly = 34
4422 23:50:52.324413 CS Dly: 3 (0~34)
4423 23:50:52.324498 ==
4424 23:50:52.327741 Dram Type= 6, Freq= 0, CH_1, rank 1
4425 23:50:52.331093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 23:50:52.331179 ==
4427 23:50:52.337800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4428 23:50:52.344515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4429 23:50:52.347796 [CA 0] Center 35 (5~66) winsize 62
4430 23:50:52.351060 [CA 1] Center 36 (6~66) winsize 61
4431 23:50:52.354289 [CA 2] Center 34 (4~65) winsize 62
4432 23:50:52.357379 [CA 3] Center 34 (3~65) winsize 63
4433 23:50:52.361115 [CA 4] Center 34 (3~65) winsize 63
4434 23:50:52.364180 [CA 5] Center 33 (3~64) winsize 62
4435 23:50:52.364265
4436 23:50:52.367090 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4437 23:50:52.367175
4438 23:50:52.370524 [CATrainingPosCal] consider 2 rank data
4439 23:50:52.373685 u2DelayCellTimex100 = 270/100 ps
4440 23:50:52.376923 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4441 23:50:52.380302 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4442 23:50:52.386711 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4443 23:50:52.390162 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4444 23:50:52.394392 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4445 23:50:52.396802 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4446 23:50:52.396888
4447 23:50:52.400027 CA PerBit enable=1, Macro0, CA PI delay=33
4448 23:50:52.400113
4449 23:50:52.403516 [CBTSetCACLKResult] CA Dly = 33
4450 23:50:52.403602 CS Dly: 4 (0~36)
4451 23:50:52.403688
4452 23:50:52.406512 ----->DramcWriteLeveling(PI) begin...
4453 23:50:52.410329 ==
4454 23:50:52.413153 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 23:50:52.416585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 23:50:52.416671 ==
4457 23:50:52.420040 Write leveling (Byte 0): 29 => 29
4458 23:50:52.423211 Write leveling (Byte 1): 28 => 28
4459 23:50:52.426494 DramcWriteLeveling(PI) end<-----
4460 23:50:52.426579
4461 23:50:52.426664 ==
4462 23:50:52.429855 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 23:50:52.433175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 23:50:52.433322 ==
4465 23:50:52.436262 [Gating] SW mode calibration
4466 23:50:52.443225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4467 23:50:52.449392 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4468 23:50:52.452491 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 23:50:52.455821 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 23:50:52.462452 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 23:50:52.465912 0 9 12 | B1->B0 | 2f2f 2f2f | 0 1 | (0 1) (1 0)
4472 23:50:52.469501 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 23:50:52.476159 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 23:50:52.478965 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 23:50:52.482595 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 23:50:52.489013 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 23:50:52.492277 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 23:50:52.495827 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4479 23:50:52.502372 0 10 12 | B1->B0 | 3333 3737 | 0 1 | (0 0) (0 0)
4480 23:50:52.505531 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 23:50:52.508832 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 23:50:52.515382 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 23:50:52.518885 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:50:52.522433 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:50:52.528436 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:50:52.531984 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:50:52.535250 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:50:52.542132 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:50:52.545387 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:50:52.548280 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:50:52.555146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:50:52.559052 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:50:52.561360 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:50:52.567868 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:50:52.571294 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:50:52.574574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:50:52.581238 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:50:52.585063 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:50:52.587869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:50:52.594722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:50:52.597693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:50:52.601282 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:50:52.607437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4504 23:50:52.607522 Total UI for P1: 0, mck2ui 16
4505 23:50:52.614297 best dqsien dly found for B0: ( 0, 13, 10)
4506 23:50:52.617808 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 23:50:52.621401 Total UI for P1: 0, mck2ui 16
4508 23:50:52.624199 best dqsien dly found for B1: ( 0, 13, 14)
4509 23:50:52.627334 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4510 23:50:52.630924 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4511 23:50:52.631030
4512 23:50:52.634296 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4513 23:50:52.637223 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4514 23:50:52.641145 [Gating] SW calibration Done
4515 23:50:52.641228 ==
4516 23:50:52.644007 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 23:50:52.650901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 23:50:52.650984 ==
4519 23:50:52.651050 RX Vref Scan: 0
4520 23:50:52.651111
4521 23:50:52.654233 RX Vref 0 -> 0, step: 1
4522 23:50:52.654315
4523 23:50:52.657146 RX Delay -230 -> 252, step: 16
4524 23:50:52.660735 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4525 23:50:52.663490 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4526 23:50:52.667029 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4527 23:50:52.673560 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4528 23:50:52.677220 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4529 23:50:52.679849 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4530 23:50:52.683241 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4531 23:50:52.690126 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4532 23:50:52.693290 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4533 23:50:52.696496 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4534 23:50:52.699903 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4535 23:50:52.706337 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4536 23:50:52.709445 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4537 23:50:52.713197 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4538 23:50:52.715983 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4539 23:50:52.722967 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4540 23:50:52.723049 ==
4541 23:50:52.726224 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 23:50:52.729571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 23:50:52.729654 ==
4544 23:50:52.729718 DQS Delay:
4545 23:50:52.732812 DQS0 = 0, DQS1 = 0
4546 23:50:52.732893 DQM Delay:
4547 23:50:52.736824 DQM0 = 44, DQM1 = 39
4548 23:50:52.736905 DQ Delay:
4549 23:50:52.739120 DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =41
4550 23:50:52.743095 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4551 23:50:52.745745 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4552 23:50:52.749092 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4553 23:50:52.749178
4554 23:50:52.749244
4555 23:50:52.749345 ==
4556 23:50:52.752620 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 23:50:52.755705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 23:50:52.759198 ==
4559 23:50:52.759280
4560 23:50:52.759345
4561 23:50:52.759404 TX Vref Scan disable
4562 23:50:52.762573 == TX Byte 0 ==
4563 23:50:52.765765 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4564 23:50:52.769231 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4565 23:50:52.771867 == TX Byte 1 ==
4566 23:50:52.775820 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4567 23:50:52.782396 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4568 23:50:52.782480 ==
4569 23:50:52.785081 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 23:50:52.789055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 23:50:52.789138 ==
4572 23:50:52.789203
4573 23:50:52.789283
4574 23:50:52.791715 TX Vref Scan disable
4575 23:50:52.795392 == TX Byte 0 ==
4576 23:50:52.799102 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4577 23:50:52.801770 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4578 23:50:52.805428 == TX Byte 1 ==
4579 23:50:52.808132 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 23:50:52.811971 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 23:50:52.812054
4582 23:50:52.812118 [DATLAT]
4583 23:50:52.815301 Freq=600, CH1 RK0
4584 23:50:52.815383
4585 23:50:52.818465 DATLAT Default: 0x9
4586 23:50:52.818547 0, 0xFFFF, sum = 0
4587 23:50:52.821576 1, 0xFFFF, sum = 0
4588 23:50:52.821660 2, 0xFFFF, sum = 0
4589 23:50:52.824863 3, 0xFFFF, sum = 0
4590 23:50:52.824947 4, 0xFFFF, sum = 0
4591 23:50:52.827899 5, 0xFFFF, sum = 0
4592 23:50:52.827983 6, 0xFFFF, sum = 0
4593 23:50:52.831335 7, 0xFFFF, sum = 0
4594 23:50:52.831419 8, 0x0, sum = 1
4595 23:50:52.834686 9, 0x0, sum = 2
4596 23:50:52.834769 10, 0x0, sum = 3
4597 23:50:52.838464 11, 0x0, sum = 4
4598 23:50:52.838548 best_step = 9
4599 23:50:52.838613
4600 23:50:52.838672 ==
4601 23:50:52.841205 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 23:50:52.844740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 23:50:52.844823 ==
4604 23:50:52.847736 RX Vref Scan: 1
4605 23:50:52.847818
4606 23:50:52.851307 RX Vref 0 -> 0, step: 1
4607 23:50:52.851390
4608 23:50:52.851455 RX Delay -179 -> 252, step: 8
4609 23:50:52.854209
4610 23:50:52.854290 Set Vref, RX VrefLevel [Byte0]: 53
4611 23:50:52.857795 [Byte1]: 49
4612 23:50:52.862781
4613 23:50:52.862863 Final RX Vref Byte 0 = 53 to rank0
4614 23:50:52.865747 Final RX Vref Byte 1 = 49 to rank0
4615 23:50:52.869019 Final RX Vref Byte 0 = 53 to rank1
4616 23:50:52.872566 Final RX Vref Byte 1 = 49 to rank1==
4617 23:50:52.875693 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 23:50:52.882153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 23:50:52.882236 ==
4620 23:50:52.882302 DQS Delay:
4621 23:50:52.885520 DQS0 = 0, DQS1 = 0
4622 23:50:52.885602 DQM Delay:
4623 23:50:52.885668 DQM0 = 42, DQM1 = 33
4624 23:50:52.888977 DQ Delay:
4625 23:50:52.892273 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4626 23:50:52.895393 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4627 23:50:52.898816 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4628 23:50:52.902047 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4629 23:50:52.902130
4630 23:50:52.902195
4631 23:50:52.908818 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4632 23:50:52.911866 CH1 RK0: MR19=808, MR18=2C46
4633 23:50:52.918678 CH1_RK0: MR19=0x808, MR18=0x2C46, DQSOSC=396, MR23=63, INC=167, DEC=111
4634 23:50:52.918761
4635 23:50:52.922132 ----->DramcWriteLeveling(PI) begin...
4636 23:50:52.922216 ==
4637 23:50:52.924913 Dram Type= 6, Freq= 0, CH_1, rank 1
4638 23:50:52.928536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 23:50:52.928619 ==
4640 23:50:52.931740 Write leveling (Byte 0): 29 => 29
4641 23:50:52.934991 Write leveling (Byte 1): 31 => 31
4642 23:50:52.939058 DramcWriteLeveling(PI) end<-----
4643 23:50:52.939140
4644 23:50:52.939205 ==
4645 23:50:52.941848 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 23:50:52.945044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 23:50:52.948086 ==
4648 23:50:52.948168 [Gating] SW mode calibration
4649 23:50:52.957854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4650 23:50:52.961323 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4651 23:50:52.964854 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 23:50:52.971044 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 23:50:52.975000 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 23:50:52.978040 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (1 0)
4655 23:50:52.984667 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 23:50:52.988219 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 23:50:52.990968 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 23:50:52.997711 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 23:50:53.001173 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 23:50:53.004212 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 23:50:53.011007 0 10 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4662 23:50:53.014238 0 10 12 | B1->B0 | 3131 4141 | 1 0 | (0 0) (0 0)
4663 23:50:53.017519 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 23:50:53.023996 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 23:50:53.027585 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 23:50:53.030681 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 23:50:53.037115 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 23:50:53.040611 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:50:53.043452 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:50:53.050325 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4671 23:50:53.054203 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:50:53.057610 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:50:53.063537 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:50:53.067176 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:50:53.069853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:50:53.077001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:50:53.081644 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:50:53.083560 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:50:53.089827 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:50:53.093655 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:50:53.096521 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:50:53.103280 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:50:53.106186 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:50:53.109182 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:50:53.116385 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:50:53.119483 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4687 23:50:53.122433 Total UI for P1: 0, mck2ui 16
4688 23:50:53.125946 best dqsien dly found for B0: ( 0, 13, 10)
4689 23:50:53.129023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 23:50:53.132499 Total UI for P1: 0, mck2ui 16
4691 23:50:53.136487 best dqsien dly found for B1: ( 0, 13, 12)
4692 23:50:53.139363 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4693 23:50:53.145628 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4694 23:50:53.145721
4695 23:50:53.148989 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4696 23:50:53.152095 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4697 23:50:53.156336 [Gating] SW calibration Done
4698 23:50:53.156420 ==
4699 23:50:53.159093 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 23:50:53.161756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 23:50:53.161840 ==
4702 23:50:53.165414 RX Vref Scan: 0
4703 23:50:53.165498
4704 23:50:53.165591 RX Vref 0 -> 0, step: 1
4705 23:50:53.165680
4706 23:50:53.168553 RX Delay -230 -> 252, step: 16
4707 23:50:53.175520 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4708 23:50:53.178737 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4709 23:50:53.181896 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4710 23:50:53.184903 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4711 23:50:53.188121 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4712 23:50:53.194961 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4713 23:50:53.198103 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4714 23:50:53.201625 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4715 23:50:53.205159 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4716 23:50:53.211430 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4717 23:50:53.214887 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4718 23:50:53.217874 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4719 23:50:53.221189 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4720 23:50:53.228161 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4721 23:50:53.232043 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4722 23:50:53.234432 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4723 23:50:53.234515 ==
4724 23:50:53.238006 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 23:50:53.241008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 23:50:53.244469 ==
4727 23:50:53.244555 DQS Delay:
4728 23:50:53.244642 DQS0 = 0, DQS1 = 0
4729 23:50:53.247568 DQM Delay:
4730 23:50:53.247653 DQM0 = 42, DQM1 = 38
4731 23:50:53.251408 DQ Delay:
4732 23:50:53.254297 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4733 23:50:53.254383 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4734 23:50:53.257838 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4735 23:50:53.260889 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4736 23:50:53.263904
4737 23:50:53.263989
4738 23:50:53.264077 ==
4739 23:50:53.267445 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 23:50:53.270868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 23:50:53.270954 ==
4742 23:50:53.271041
4743 23:50:53.271121
4744 23:50:53.274460 TX Vref Scan disable
4745 23:50:53.274546 == TX Byte 0 ==
4746 23:50:53.280769 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4747 23:50:53.283952 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4748 23:50:53.284039 == TX Byte 1 ==
4749 23:50:53.290704 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4750 23:50:53.293988 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4751 23:50:53.294074 ==
4752 23:50:53.297631 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 23:50:53.301093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 23:50:53.301179 ==
4755 23:50:53.301309
4756 23:50:53.303730
4757 23:50:53.303815 TX Vref Scan disable
4758 23:50:53.307484 == TX Byte 0 ==
4759 23:50:53.310541 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4760 23:50:53.316890 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4761 23:50:53.316976 == TX Byte 1 ==
4762 23:50:53.320303 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4763 23:50:53.326782 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4764 23:50:53.326868
4765 23:50:53.326954 [DATLAT]
4766 23:50:53.327034 Freq=600, CH1 RK1
4767 23:50:53.327114
4768 23:50:53.330234 DATLAT Default: 0x9
4769 23:50:53.330319 0, 0xFFFF, sum = 0
4770 23:50:53.333593 1, 0xFFFF, sum = 0
4771 23:50:53.336875 2, 0xFFFF, sum = 0
4772 23:50:53.336960 3, 0xFFFF, sum = 0
4773 23:50:53.340001 4, 0xFFFF, sum = 0
4774 23:50:53.340086 5, 0xFFFF, sum = 0
4775 23:50:53.343770 6, 0xFFFF, sum = 0
4776 23:50:53.343853 7, 0xFFFF, sum = 0
4777 23:50:53.346838 8, 0x0, sum = 1
4778 23:50:53.346922 9, 0x0, sum = 2
4779 23:50:53.350017 10, 0x0, sum = 3
4780 23:50:53.350102 11, 0x0, sum = 4
4781 23:50:53.350168 best_step = 9
4782 23:50:53.350230
4783 23:50:53.352955 ==
4784 23:50:53.356682 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 23:50:53.359580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 23:50:53.359663 ==
4787 23:50:53.359730 RX Vref Scan: 0
4788 23:50:53.359790
4789 23:50:53.363028 RX Vref 0 -> 0, step: 1
4790 23:50:53.363112
4791 23:50:53.366331 RX Delay -179 -> 252, step: 8
4792 23:50:53.372723 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4793 23:50:53.376193 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4794 23:50:53.379978 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4795 23:50:53.382843 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4796 23:50:53.389643 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4797 23:50:53.392866 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4798 23:50:53.396653 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4799 23:50:53.399412 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4800 23:50:53.402470 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4801 23:50:53.409188 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4802 23:50:53.412518 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4803 23:50:53.415847 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4804 23:50:53.419250 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4805 23:50:53.426241 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4806 23:50:53.429166 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4807 23:50:53.432227 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4808 23:50:53.432311 ==
4809 23:50:53.435615 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 23:50:53.441943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 23:50:53.442027 ==
4812 23:50:53.442093 DQS Delay:
4813 23:50:53.442154 DQS0 = 0, DQS1 = 0
4814 23:50:53.445686 DQM Delay:
4815 23:50:53.445768 DQM0 = 37, DQM1 = 34
4816 23:50:53.448530 DQ Delay:
4817 23:50:53.452481 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4818 23:50:53.455156 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4819 23:50:53.458722 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4820 23:50:53.461883 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4821 23:50:53.461966
4822 23:50:53.462031
4823 23:50:53.468369 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4824 23:50:53.471606 CH1 RK1: MR19=808, MR18=3C60
4825 23:50:53.478735 CH1_RK1: MR19=0x808, MR18=0x3C60, DQSOSC=391, MR23=63, INC=171, DEC=114
4826 23:50:53.481934 [RxdqsGatingPostProcess] freq 600
4827 23:50:53.484827 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4828 23:50:53.488037 Pre-setting of DQS Precalculation
4829 23:50:53.494861 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4830 23:50:53.501805 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4831 23:50:53.507839 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4832 23:50:53.507922
4833 23:50:53.507988
4834 23:50:53.511161 [Calibration Summary] 1200 Mbps
4835 23:50:53.511244 CH 0, Rank 0
4836 23:50:53.514255 SW Impedance : PASS
4837 23:50:53.517714 DUTY Scan : NO K
4838 23:50:53.517797 ZQ Calibration : PASS
4839 23:50:53.521083 Jitter Meter : NO K
4840 23:50:53.524268 CBT Training : PASS
4841 23:50:53.524351 Write leveling : PASS
4842 23:50:53.528031 RX DQS gating : PASS
4843 23:50:53.531231 RX DQ/DQS(RDDQC) : PASS
4844 23:50:53.531313 TX DQ/DQS : PASS
4845 23:50:53.534043 RX DATLAT : PASS
4846 23:50:53.537384 RX DQ/DQS(Engine): PASS
4847 23:50:53.537467 TX OE : NO K
4848 23:50:53.541067 All Pass.
4849 23:50:53.541149
4850 23:50:53.541215 CH 0, Rank 1
4851 23:50:53.544118 SW Impedance : PASS
4852 23:50:53.544200 DUTY Scan : NO K
4853 23:50:53.547413 ZQ Calibration : PASS
4854 23:50:53.550696 Jitter Meter : NO K
4855 23:50:53.550779 CBT Training : PASS
4856 23:50:53.553966 Write leveling : PASS
4857 23:50:53.557109 RX DQS gating : PASS
4858 23:50:53.557237 RX DQ/DQS(RDDQC) : PASS
4859 23:50:53.560587 TX DQ/DQS : PASS
4860 23:50:53.564032 RX DATLAT : PASS
4861 23:50:53.564115 RX DQ/DQS(Engine): PASS
4862 23:50:53.567195 TX OE : NO K
4863 23:50:53.567277 All Pass.
4864 23:50:53.567344
4865 23:50:53.570653 CH 1, Rank 0
4866 23:50:53.570735 SW Impedance : PASS
4867 23:50:53.573587 DUTY Scan : NO K
4868 23:50:53.577102 ZQ Calibration : PASS
4869 23:50:53.577184 Jitter Meter : NO K
4870 23:50:53.580240 CBT Training : PASS
4871 23:50:53.583726 Write leveling : PASS
4872 23:50:53.583809 RX DQS gating : PASS
4873 23:50:53.587062 RX DQ/DQS(RDDQC) : PASS
4874 23:50:53.590494 TX DQ/DQS : PASS
4875 23:50:53.590577 RX DATLAT : PASS
4876 23:50:53.593445 RX DQ/DQS(Engine): PASS
4877 23:50:53.593528 TX OE : NO K
4878 23:50:53.596704 All Pass.
4879 23:50:53.596787
4880 23:50:53.596853 CH 1, Rank 1
4881 23:50:53.600139 SW Impedance : PASS
4882 23:50:53.600222 DUTY Scan : NO K
4883 23:50:53.603458 ZQ Calibration : PASS
4884 23:50:53.607082 Jitter Meter : NO K
4885 23:50:53.607164 CBT Training : PASS
4886 23:50:53.610052 Write leveling : PASS
4887 23:50:53.613208 RX DQS gating : PASS
4888 23:50:53.613341 RX DQ/DQS(RDDQC) : PASS
4889 23:50:53.616501 TX DQ/DQS : PASS
4890 23:50:53.620125 RX DATLAT : PASS
4891 23:50:53.620234 RX DQ/DQS(Engine): PASS
4892 23:50:53.623378 TX OE : NO K
4893 23:50:53.623462 All Pass.
4894 23:50:53.623526
4895 23:50:53.626510 DramC Write-DBI off
4896 23:50:53.629916 PER_BANK_REFRESH: Hybrid Mode
4897 23:50:53.629999 TX_TRACKING: ON
4898 23:50:53.639658 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4899 23:50:53.643307 [FAST_K] Save calibration result to emmc
4900 23:50:53.646160 dramc_set_vcore_voltage set vcore to 662500
4901 23:50:53.649679 Read voltage for 933, 3
4902 23:50:53.649762 Vio18 = 0
4903 23:50:53.649828 Vcore = 662500
4904 23:50:53.653200 Vdram = 0
4905 23:50:53.653320 Vddq = 0
4906 23:50:53.653386 Vmddr = 0
4907 23:50:53.659332 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4908 23:50:53.662808 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4909 23:50:53.666557 MEM_TYPE=3, freq_sel=17
4910 23:50:53.670108 sv_algorithm_assistance_LP4_1600
4911 23:50:53.672949 ============ PULL DRAM RESETB DOWN ============
4912 23:50:53.676173 ========== PULL DRAM RESETB DOWN end =========
4913 23:50:53.682646 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4914 23:50:53.685965 ===================================
4915 23:50:53.689089 LPDDR4 DRAM CONFIGURATION
4916 23:50:53.692262 ===================================
4917 23:50:53.692345 EX_ROW_EN[0] = 0x0
4918 23:50:53.695915 EX_ROW_EN[1] = 0x0
4919 23:50:53.695998 LP4Y_EN = 0x0
4920 23:50:53.698961 WORK_FSP = 0x0
4921 23:50:53.699070 WL = 0x3
4922 23:50:53.702793 RL = 0x3
4923 23:50:53.702875 BL = 0x2
4924 23:50:53.705916 RPST = 0x0
4925 23:50:53.705999 RD_PRE = 0x0
4926 23:50:53.709475 WR_PRE = 0x1
4927 23:50:53.712173 WR_PST = 0x0
4928 23:50:53.712256 DBI_WR = 0x0
4929 23:50:53.715404 DBI_RD = 0x0
4930 23:50:53.715487 OTF = 0x1
4931 23:50:53.718655 ===================================
4932 23:50:53.722081 ===================================
4933 23:50:53.725276 ANA top config
4934 23:50:53.729108 ===================================
4935 23:50:53.729232 DLL_ASYNC_EN = 0
4936 23:50:53.732172 ALL_SLAVE_EN = 1
4937 23:50:53.735033 NEW_RANK_MODE = 1
4938 23:50:53.738881 DLL_IDLE_MODE = 1
4939 23:50:53.738968 LP45_APHY_COMB_EN = 1
4940 23:50:53.741709 TX_ODT_DIS = 1
4941 23:50:53.744980 NEW_8X_MODE = 1
4942 23:50:53.748410 ===================================
4943 23:50:53.751782 ===================================
4944 23:50:53.755492 data_rate = 1866
4945 23:50:53.758364 CKR = 1
4946 23:50:53.761547 DQ_P2S_RATIO = 8
4947 23:50:53.764639 ===================================
4948 23:50:53.764743 CA_P2S_RATIO = 8
4949 23:50:53.768159 DQ_CA_OPEN = 0
4950 23:50:53.771266 DQ_SEMI_OPEN = 0
4951 23:50:53.775218 CA_SEMI_OPEN = 0
4952 23:50:53.778049 CA_FULL_RATE = 0
4953 23:50:53.781064 DQ_CKDIV4_EN = 1
4954 23:50:53.781174 CA_CKDIV4_EN = 1
4955 23:50:53.784377 CA_PREDIV_EN = 0
4956 23:50:53.787678 PH8_DLY = 0
4957 23:50:53.791558 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4958 23:50:53.794534 DQ_AAMCK_DIV = 4
4959 23:50:53.797676 CA_AAMCK_DIV = 4
4960 23:50:53.800920 CA_ADMCK_DIV = 4
4961 23:50:53.801003 DQ_TRACK_CA_EN = 0
4962 23:50:53.804238 CA_PICK = 933
4963 23:50:53.808071 CA_MCKIO = 933
4964 23:50:53.811265 MCKIO_SEMI = 0
4965 23:50:53.813987 PLL_FREQ = 3732
4966 23:50:53.817827 DQ_UI_PI_RATIO = 32
4967 23:50:53.820714 CA_UI_PI_RATIO = 0
4968 23:50:53.824225 ===================================
4969 23:50:53.827074 ===================================
4970 23:50:53.827157 memory_type:LPDDR4
4971 23:50:53.830852 GP_NUM : 10
4972 23:50:53.833579 SRAM_EN : 1
4973 23:50:53.833661 MD32_EN : 0
4974 23:50:53.837206 ===================================
4975 23:50:53.840703 [ANA_INIT] >>>>>>>>>>>>>>
4976 23:50:53.843537 <<<<<< [CONFIGURE PHASE]: ANA_TX
4977 23:50:53.847076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4978 23:50:53.850294 ===================================
4979 23:50:53.853520 data_rate = 1866,PCW = 0X8f00
4980 23:50:53.856615 ===================================
4981 23:50:53.860259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4982 23:50:53.863133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 23:50:53.870184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 23:50:53.873055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4985 23:50:53.879560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4986 23:50:53.883209 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4987 23:50:53.883292 [ANA_INIT] flow start
4988 23:50:53.886457 [ANA_INIT] PLL >>>>>>>>
4989 23:50:53.889668 [ANA_INIT] PLL <<<<<<<<
4990 23:50:53.889751 [ANA_INIT] MIDPI >>>>>>>>
4991 23:50:53.893175 [ANA_INIT] MIDPI <<<<<<<<
4992 23:50:53.896244 [ANA_INIT] DLL >>>>>>>>
4993 23:50:53.896326 [ANA_INIT] flow end
4994 23:50:53.903024 ============ LP4 DIFF to SE enter ============
4995 23:50:53.906410 ============ LP4 DIFF to SE exit ============
4996 23:50:53.909192 [ANA_INIT] <<<<<<<<<<<<<
4997 23:50:53.912522 [Flow] Enable top DCM control >>>>>
4998 23:50:53.916057 [Flow] Enable top DCM control <<<<<
4999 23:50:53.916140 Enable DLL master slave shuffle
5000 23:50:53.922706 ==============================================================
5001 23:50:53.926048 Gating Mode config
5002 23:50:53.928834 ==============================================================
5003 23:50:53.932423 Config description:
5004 23:50:53.942555 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5005 23:50:53.949487 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5006 23:50:53.951940 SELPH_MODE 0: By rank 1: By Phase
5007 23:50:53.958647 ==============================================================
5008 23:50:53.961856 GAT_TRACK_EN = 1
5009 23:50:53.965605 RX_GATING_MODE = 2
5010 23:50:53.969040 RX_GATING_TRACK_MODE = 2
5011 23:50:53.971799 SELPH_MODE = 1
5012 23:50:53.971882 PICG_EARLY_EN = 1
5013 23:50:53.975482 VALID_LAT_VALUE = 1
5014 23:50:53.981630 ==============================================================
5015 23:50:53.985006 Enter into Gating configuration >>>>
5016 23:50:53.988694 Exit from Gating configuration <<<<
5017 23:50:53.991965 Enter into DVFS_PRE_config >>>>>
5018 23:50:54.001816 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5019 23:50:54.005001 Exit from DVFS_PRE_config <<<<<
5020 23:50:54.008621 Enter into PICG configuration >>>>
5021 23:50:54.011551 Exit from PICG configuration <<<<
5022 23:50:54.014720 [RX_INPUT] configuration >>>>>
5023 23:50:54.017978 [RX_INPUT] configuration <<<<<
5024 23:50:54.025039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5025 23:50:54.028236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5026 23:50:54.034416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 23:50:54.041248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 23:50:54.048237 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 23:50:54.054251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 23:50:54.057883 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5031 23:50:54.060837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5032 23:50:54.064633 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5033 23:50:54.071012 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5034 23:50:54.074063 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5035 23:50:54.077181 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 23:50:54.080662 ===================================
5037 23:50:54.084128 LPDDR4 DRAM CONFIGURATION
5038 23:50:54.087141 ===================================
5039 23:50:54.090634 EX_ROW_EN[0] = 0x0
5040 23:50:54.090716 EX_ROW_EN[1] = 0x0
5041 23:50:54.093696 LP4Y_EN = 0x0
5042 23:50:54.093805 WORK_FSP = 0x0
5043 23:50:54.097674 WL = 0x3
5044 23:50:54.097757 RL = 0x3
5045 23:50:54.100174 BL = 0x2
5046 23:50:54.100283 RPST = 0x0
5047 23:50:54.103438 RD_PRE = 0x0
5048 23:50:54.103521 WR_PRE = 0x1
5049 23:50:54.106714 WR_PST = 0x0
5050 23:50:54.106796 DBI_WR = 0x0
5051 23:50:54.110162 DBI_RD = 0x0
5052 23:50:54.110245 OTF = 0x1
5053 23:50:54.113234 ===================================
5054 23:50:54.120375 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5055 23:50:54.123184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5056 23:50:54.126640 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5057 23:50:54.129934 ===================================
5058 23:50:54.133129 LPDDR4 DRAM CONFIGURATION
5059 23:50:54.136455 ===================================
5060 23:50:54.139896 EX_ROW_EN[0] = 0x10
5061 23:50:54.139979 EX_ROW_EN[1] = 0x0
5062 23:50:54.143074 LP4Y_EN = 0x0
5063 23:50:54.143158 WORK_FSP = 0x0
5064 23:50:54.146350 WL = 0x3
5065 23:50:54.146433 RL = 0x3
5066 23:50:54.149473 BL = 0x2
5067 23:50:54.149556 RPST = 0x0
5068 23:50:54.152767 RD_PRE = 0x0
5069 23:50:54.152850 WR_PRE = 0x1
5070 23:50:54.156397 WR_PST = 0x0
5071 23:50:54.156479 DBI_WR = 0x0
5072 23:50:54.159422 DBI_RD = 0x0
5073 23:50:54.162781 OTF = 0x1
5074 23:50:54.165868 ===================================
5075 23:50:54.169439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5076 23:50:54.174534 nWR fixed to 30
5077 23:50:54.178221 [ModeRegInit_LP4] CH0 RK0
5078 23:50:54.178303 [ModeRegInit_LP4] CH0 RK1
5079 23:50:54.181177 [ModeRegInit_LP4] CH1 RK0
5080 23:50:54.184262 [ModeRegInit_LP4] CH1 RK1
5081 23:50:54.184344 match AC timing 9
5082 23:50:54.191310 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5083 23:50:54.194440 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5084 23:50:54.197733 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5085 23:50:54.203944 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5086 23:50:54.207580 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5087 23:50:54.207663 ==
5088 23:50:54.210665 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 23:50:54.214057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 23:50:54.214140 ==
5091 23:50:54.220405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 23:50:54.227207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5093 23:50:54.230996 [CA 0] Center 37 (7~68) winsize 62
5094 23:50:54.233883 [CA 1] Center 37 (7~68) winsize 62
5095 23:50:54.236847 [CA 2] Center 34 (4~65) winsize 62
5096 23:50:54.240593 [CA 3] Center 34 (4~65) winsize 62
5097 23:50:54.243809 [CA 4] Center 32 (2~63) winsize 62
5098 23:50:54.247263 [CA 5] Center 33 (3~63) winsize 61
5099 23:50:54.247345
5100 23:50:54.250483 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5101 23:50:54.250566
5102 23:50:54.253882 [CATrainingPosCal] consider 1 rank data
5103 23:50:54.257372 u2DelayCellTimex100 = 270/100 ps
5104 23:50:54.260392 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5105 23:50:54.263434 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5106 23:50:54.266647 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5107 23:50:54.273643 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5108 23:50:54.276449 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5109 23:50:54.279886 CA5 delay=33 (3~63),Diff = 1 PI (6 cell)
5110 23:50:54.279969
5111 23:50:54.283058 CA PerBit enable=1, Macro0, CA PI delay=32
5112 23:50:54.283141
5113 23:50:54.286461 [CBTSetCACLKResult] CA Dly = 32
5114 23:50:54.286544 CS Dly: 5 (0~36)
5115 23:50:54.286610 ==
5116 23:50:54.289964 Dram Type= 6, Freq= 0, CH_0, rank 1
5117 23:50:54.296501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 23:50:54.296584 ==
5119 23:50:54.299772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 23:50:54.306068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5121 23:50:54.309667 [CA 0] Center 38 (8~68) winsize 61
5122 23:50:54.312823 [CA 1] Center 37 (7~68) winsize 62
5123 23:50:54.316084 [CA 2] Center 34 (4~65) winsize 62
5124 23:50:54.319887 [CA 3] Center 34 (4~65) winsize 62
5125 23:50:54.323426 [CA 4] Center 33 (3~64) winsize 62
5126 23:50:54.325886 [CA 5] Center 32 (2~63) winsize 62
5127 23:50:54.325969
5128 23:50:54.329264 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5129 23:50:54.329361
5130 23:50:54.332865 [CATrainingPosCal] consider 2 rank data
5131 23:50:54.336297 u2DelayCellTimex100 = 270/100 ps
5132 23:50:54.339182 CA0 delay=38 (8~68),Diff = 5 PI (31 cell)
5133 23:50:54.346109 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5134 23:50:54.349345 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5135 23:50:54.352732 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5136 23:50:54.355919 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5137 23:50:54.359247 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5138 23:50:54.359331
5139 23:50:54.362896 CA PerBit enable=1, Macro0, CA PI delay=33
5140 23:50:54.362978
5141 23:50:54.365453 [CBTSetCACLKResult] CA Dly = 33
5142 23:50:54.369219 CS Dly: 6 (0~39)
5143 23:50:54.369350
5144 23:50:54.372662 ----->DramcWriteLeveling(PI) begin...
5145 23:50:54.372747 ==
5146 23:50:54.375739 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 23:50:54.379178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 23:50:54.379261 ==
5149 23:50:54.382357 Write leveling (Byte 0): 31 => 31
5150 23:50:54.385448 Write leveling (Byte 1): 29 => 29
5151 23:50:54.388619 DramcWriteLeveling(PI) end<-----
5152 23:50:54.388702
5153 23:50:54.388766 ==
5154 23:50:54.392126 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 23:50:54.395137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 23:50:54.395220 ==
5157 23:50:54.398612 [Gating] SW mode calibration
5158 23:50:54.405090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5159 23:50:54.411702 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5160 23:50:54.415285 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5161 23:50:54.421675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:50:54.424665 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 23:50:54.428555 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 23:50:54.434924 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 23:50:54.438025 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 23:50:54.441701 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5167 23:50:54.447700 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
5168 23:50:54.451605 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5169 23:50:54.454997 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:50:54.461005 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 23:50:54.464100 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 23:50:54.467733 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 23:50:54.474241 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 23:50:54.477719 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5175 23:50:54.480952 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
5176 23:50:54.487902 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5177 23:50:54.490827 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:50:54.494238 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 23:50:54.500602 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:50:54.503556 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 23:50:54.507192 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 23:50:54.514114 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 23:50:54.517824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5184 23:50:54.520323 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5185 23:50:54.527412 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:50:54.530385 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:50:54.533750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:50:54.540453 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:50:54.543728 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:50:54.546794 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:50:54.553912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:50:54.556915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:50:54.560350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:50:54.567261 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:50:54.569941 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:50:54.573300 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:50:54.580204 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:50:54.583573 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:50:54.586670 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 23:50:54.593094 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5201 23:50:54.593671 Total UI for P1: 0, mck2ui 16
5202 23:50:54.599582 best dqsien dly found for B0: ( 1, 2, 28)
5203 23:50:54.603123 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 23:50:54.606400 Total UI for P1: 0, mck2ui 16
5205 23:50:54.609764 best dqsien dly found for B1: ( 1, 3, 0)
5206 23:50:54.613519 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5207 23:50:54.616137 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5208 23:50:54.616565
5209 23:50:54.619287 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5210 23:50:54.622492 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5211 23:50:54.625952 [Gating] SW calibration Done
5212 23:50:54.626380 ==
5213 23:50:54.629519 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 23:50:54.632713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 23:50:54.635760 ==
5216 23:50:54.636185 RX Vref Scan: 0
5217 23:50:54.636525
5218 23:50:54.639456 RX Vref 0 -> 0, step: 1
5219 23:50:54.639883
5220 23:50:54.642630 RX Delay -80 -> 252, step: 8
5221 23:50:54.645849 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5222 23:50:54.648984 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5223 23:50:54.652273 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5224 23:50:54.655635 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5225 23:50:54.658789 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5226 23:50:54.665219 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5227 23:50:54.669624 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5228 23:50:54.671841 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5229 23:50:54.675532 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5230 23:50:54.678422 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5231 23:50:54.685091 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5232 23:50:54.688538 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5233 23:50:54.691676 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5234 23:50:54.695002 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5235 23:50:54.698896 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5236 23:50:54.704835 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5237 23:50:54.705306 ==
5238 23:50:54.708253 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 23:50:54.711605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 23:50:54.712052 ==
5241 23:50:54.712501 DQS Delay:
5242 23:50:54.714666 DQS0 = 0, DQS1 = 0
5243 23:50:54.715105 DQM Delay:
5244 23:50:54.718074 DQM0 = 100, DQM1 = 88
5245 23:50:54.718515 DQ Delay:
5246 23:50:54.721330 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5247 23:50:54.724377 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5248 23:50:54.727728 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5249 23:50:54.731013 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5250 23:50:54.731456
5251 23:50:54.731899
5252 23:50:54.732313 ==
5253 23:50:54.734680 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 23:50:54.740842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 23:50:54.741315 ==
5256 23:50:54.741762
5257 23:50:54.742194
5258 23:50:54.742599 TX Vref Scan disable
5259 23:50:54.744694 == TX Byte 0 ==
5260 23:50:54.747918 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5261 23:50:54.754016 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5262 23:50:54.754459 == TX Byte 1 ==
5263 23:50:54.757321 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5264 23:50:54.763959 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5265 23:50:54.764402 ==
5266 23:50:54.767357 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 23:50:54.770860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 23:50:54.771304 ==
5269 23:50:54.771747
5270 23:50:54.772164
5271 23:50:54.774578 TX Vref Scan disable
5272 23:50:54.777528 == TX Byte 0 ==
5273 23:50:54.780368 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5274 23:50:54.783737 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5275 23:50:54.787041 == TX Byte 1 ==
5276 23:50:54.790110 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5277 23:50:54.793675 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5278 23:50:54.794157
5279 23:50:54.794598 [DATLAT]
5280 23:50:54.796702 Freq=933, CH0 RK0
5281 23:50:54.797144
5282 23:50:54.799955 DATLAT Default: 0xd
5283 23:50:54.800396 0, 0xFFFF, sum = 0
5284 23:50:54.803398 1, 0xFFFF, sum = 0
5285 23:50:54.803845 2, 0xFFFF, sum = 0
5286 23:50:54.806614 3, 0xFFFF, sum = 0
5287 23:50:54.807060 4, 0xFFFF, sum = 0
5288 23:50:54.810002 5, 0xFFFF, sum = 0
5289 23:50:54.810450 6, 0xFFFF, sum = 0
5290 23:50:54.813014 7, 0xFFFF, sum = 0
5291 23:50:54.813517 8, 0xFFFF, sum = 0
5292 23:50:54.816396 9, 0xFFFF, sum = 0
5293 23:50:54.816841 10, 0x0, sum = 1
5294 23:50:54.820020 11, 0x0, sum = 2
5295 23:50:54.820464 12, 0x0, sum = 3
5296 23:50:54.823315 13, 0x0, sum = 4
5297 23:50:54.823763 best_step = 11
5298 23:50:54.824204
5299 23:50:54.824621 ==
5300 23:50:54.826536 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 23:50:54.829697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 23:50:54.833236 ==
5303 23:50:54.833712 RX Vref Scan: 1
5304 23:50:54.834155
5305 23:50:54.836507 RX Vref 0 -> 0, step: 1
5306 23:50:54.836948
5307 23:50:54.840277 RX Delay -61 -> 252, step: 4
5308 23:50:54.840715
5309 23:50:54.843090 Set Vref, RX VrefLevel [Byte0]: 53
5310 23:50:54.846462 [Byte1]: 47
5311 23:50:54.846900
5312 23:50:54.849717 Final RX Vref Byte 0 = 53 to rank0
5313 23:50:54.852799 Final RX Vref Byte 1 = 47 to rank0
5314 23:50:54.855977 Final RX Vref Byte 0 = 53 to rank1
5315 23:50:54.859257 Final RX Vref Byte 1 = 47 to rank1==
5316 23:50:54.862901 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 23:50:54.866103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 23:50:54.866560 ==
5319 23:50:54.869137 DQS Delay:
5320 23:50:54.869627 DQS0 = 0, DQS1 = 0
5321 23:50:54.870072 DQM Delay:
5322 23:50:54.872741 DQM0 = 98, DQM1 = 87
5323 23:50:54.873352 DQ Delay:
5324 23:50:54.876066 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5325 23:50:54.879235 DQ4 =98, DQ5 =90, DQ6 =108, DQ7 =106
5326 23:50:54.882317 DQ8 =80, DQ9 =74, DQ10 =86, DQ11 =82
5327 23:50:54.885849 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =96
5328 23:50:54.886276
5329 23:50:54.886609
5330 23:50:54.895800 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f19, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5331 23:50:54.898992 CH0 RK0: MR19=505, MR18=1F19
5332 23:50:54.902799 CH0_RK0: MR19=0x505, MR18=0x1F19, DQSOSC=412, MR23=63, INC=63, DEC=42
5333 23:50:54.905600
5334 23:50:54.908968 ----->DramcWriteLeveling(PI) begin...
5335 23:50:54.909440 ==
5336 23:50:54.912252 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 23:50:54.915529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 23:50:54.915957 ==
5339 23:50:54.918986 Write leveling (Byte 0): 29 => 29
5340 23:50:54.922175 Write leveling (Byte 1): 29 => 29
5341 23:50:54.925660 DramcWriteLeveling(PI) end<-----
5342 23:50:54.926085
5343 23:50:54.926419 ==
5344 23:50:54.928748 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 23:50:54.932774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 23:50:54.933207 ==
5347 23:50:54.935605 [Gating] SW mode calibration
5348 23:50:54.942220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5349 23:50:54.948332 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5350 23:50:54.952496 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5351 23:50:54.955433 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 23:50:54.961472 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 23:50:54.965044 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:50:54.968019 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:50:54.975057 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 23:50:54.978097 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5357 23:50:54.981995 0 14 28 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (1 0)
5358 23:50:54.988146 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5359 23:50:54.991465 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:50:54.995394 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:50:55.001243 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:50:55.004261 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 23:50:55.007879 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 23:50:55.014677 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5365 23:50:55.017642 0 15 28 | B1->B0 | 2828 4444 | 1 0 | (0 0) (0 0)
5366 23:50:55.021216 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5367 23:50:55.027657 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:50:55.030580 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:50:55.033998 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:50:55.040572 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:50:55.044063 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:50:55.047824 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:50:55.054237 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5374 23:50:55.057478 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5375 23:50:55.060410 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:50:55.067033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:50:55.070484 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:50:55.074037 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:50:55.080290 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:50:55.083910 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:50:55.086942 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:50:55.093800 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:50:55.096967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:50:55.099952 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:50:55.106558 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:50:55.109997 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:50:55.113488 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:50:55.119865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5389 23:50:55.122931 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5390 23:50:55.126457 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 23:50:55.129399 Total UI for P1: 0, mck2ui 16
5392 23:50:55.133228 best dqsien dly found for B0: ( 1, 2, 26)
5393 23:50:55.136064 Total UI for P1: 0, mck2ui 16
5394 23:50:55.140592 best dqsien dly found for B1: ( 1, 2, 28)
5395 23:50:55.142786 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5396 23:50:55.145791 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5397 23:50:55.149104
5398 23:50:55.152552 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5399 23:50:55.156003 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5400 23:50:55.159108 [Gating] SW calibration Done
5401 23:50:55.159546 ==
5402 23:50:55.162615 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 23:50:55.165646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 23:50:55.166071 ==
5405 23:50:55.168845 RX Vref Scan: 0
5406 23:50:55.169306
5407 23:50:55.169675 RX Vref 0 -> 0, step: 1
5408 23:50:55.169991
5409 23:50:55.172354 RX Delay -80 -> 252, step: 8
5410 23:50:55.175472 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5411 23:50:55.178632 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5412 23:50:55.185305 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5413 23:50:55.188518 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5414 23:50:55.191918 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5415 23:50:55.195274 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5416 23:50:55.198681 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5417 23:50:55.201866 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5418 23:50:55.208867 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5419 23:50:55.212124 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5420 23:50:55.215331 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5421 23:50:55.219114 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5422 23:50:55.221878 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5423 23:50:55.229172 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5424 23:50:55.231467 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5425 23:50:55.234826 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5426 23:50:55.235254 ==
5427 23:50:55.238373 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 23:50:55.241842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 23:50:55.242272 ==
5430 23:50:55.244898 DQS Delay:
5431 23:50:55.245367 DQS0 = 0, DQS1 = 0
5432 23:50:55.248059 DQM Delay:
5433 23:50:55.248483 DQM0 = 97, DQM1 = 89
5434 23:50:55.248818 DQ Delay:
5435 23:50:55.251382 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5436 23:50:55.255308 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5437 23:50:55.258174 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5438 23:50:55.261366 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5439 23:50:55.261794
5440 23:50:55.262128
5441 23:50:55.264900 ==
5442 23:50:55.268540 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 23:50:55.271113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 23:50:55.271553 ==
5445 23:50:55.271995
5446 23:50:55.272411
5447 23:50:55.274226 TX Vref Scan disable
5448 23:50:55.274664 == TX Byte 0 ==
5449 23:50:55.281087 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5450 23:50:55.284088 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5451 23:50:55.284531 == TX Byte 1 ==
5452 23:50:55.291590 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5453 23:50:55.294046 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5454 23:50:55.294487 ==
5455 23:50:55.297449 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 23:50:55.300812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 23:50:55.301282 ==
5458 23:50:55.301737
5459 23:50:55.302151
5460 23:50:55.303801 TX Vref Scan disable
5461 23:50:55.306837 == TX Byte 0 ==
5462 23:50:55.310527 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5463 23:50:55.313623 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5464 23:50:55.317041 == TX Byte 1 ==
5465 23:50:55.320171 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5466 23:50:55.323924 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5467 23:50:55.324363
5468 23:50:55.326858 [DATLAT]
5469 23:50:55.327297 Freq=933, CH0 RK1
5470 23:50:55.327743
5471 23:50:55.330273 DATLAT Default: 0xb
5472 23:50:55.330711 0, 0xFFFF, sum = 0
5473 23:50:55.333595 1, 0xFFFF, sum = 0
5474 23:50:55.334041 2, 0xFFFF, sum = 0
5475 23:50:55.336555 3, 0xFFFF, sum = 0
5476 23:50:55.337025 4, 0xFFFF, sum = 0
5477 23:50:55.340367 5, 0xFFFF, sum = 0
5478 23:50:55.340814 6, 0xFFFF, sum = 0
5479 23:50:55.343778 7, 0xFFFF, sum = 0
5480 23:50:55.347022 8, 0xFFFF, sum = 0
5481 23:50:55.347467 9, 0xFFFF, sum = 0
5482 23:50:55.349632 10, 0x0, sum = 1
5483 23:50:55.350077 11, 0x0, sum = 2
5484 23:50:55.350528 12, 0x0, sum = 3
5485 23:50:55.353300 13, 0x0, sum = 4
5486 23:50:55.353749 best_step = 11
5487 23:50:55.354185
5488 23:50:55.356244 ==
5489 23:50:55.356687 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 23:50:55.362945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 23:50:55.363383 ==
5492 23:50:55.363828 RX Vref Scan: 0
5493 23:50:55.364243
5494 23:50:55.366417 RX Vref 0 -> 0, step: 1
5495 23:50:55.366852
5496 23:50:55.369432 RX Delay -53 -> 252, step: 4
5497 23:50:55.372844 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5498 23:50:55.379537 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5499 23:50:55.382958 iDelay=195, Bit 2, Center 94 (7 ~ 182) 176
5500 23:50:55.385886 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5501 23:50:55.389342 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5502 23:50:55.392392 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5503 23:50:55.395768 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5504 23:50:55.403003 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5505 23:50:55.406032 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5506 23:50:55.408840 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5507 23:50:55.412518 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5508 23:50:55.418893 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5509 23:50:55.422156 iDelay=195, Bit 12, Center 92 (7 ~ 178) 172
5510 23:50:55.425242 iDelay=195, Bit 13, Center 90 (3 ~ 178) 176
5511 23:50:55.429126 iDelay=195, Bit 14, Center 96 (7 ~ 186) 180
5512 23:50:55.432040 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5513 23:50:55.432465 ==
5514 23:50:55.436014 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 23:50:55.442120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 23:50:55.442548 ==
5517 23:50:55.442887 DQS Delay:
5518 23:50:55.443201 DQS0 = 0, DQS1 = 0
5519 23:50:55.445640 DQM Delay:
5520 23:50:55.446063 DQM0 = 97, DQM1 = 87
5521 23:50:55.448748 DQ Delay:
5522 23:50:55.452105 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5523 23:50:55.454964 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5524 23:50:55.458576 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5525 23:50:55.461590 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =94
5526 23:50:55.462015
5527 23:50:55.462347
5528 23:50:55.468513 [DQSOSCAuto] RK1, (LSB)MR18= 0x1715, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5529 23:50:55.471993 CH0 RK1: MR19=505, MR18=1715
5530 23:50:55.478291 CH0_RK1: MR19=0x505, MR18=0x1715, DQSOSC=414, MR23=63, INC=63, DEC=42
5531 23:50:55.481623 [RxdqsGatingPostProcess] freq 933
5532 23:50:55.484930 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5533 23:50:55.487780 best DQS0 dly(2T, 0.5T) = (0, 10)
5534 23:50:55.491980 best DQS1 dly(2T, 0.5T) = (0, 11)
5535 23:50:55.495238 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5536 23:50:55.497968 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5537 23:50:55.501208 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 23:50:55.504479 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 23:50:55.507880 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 23:50:55.511076 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 23:50:55.514980 Pre-setting of DQS Precalculation
5542 23:50:55.518231 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5543 23:50:55.521415 ==
5544 23:50:55.524723 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 23:50:55.527616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 23:50:55.528045 ==
5547 23:50:55.531779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 23:50:55.537767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 23:50:55.541199 [CA 0] Center 36 (6~67) winsize 62
5550 23:50:55.544781 [CA 1] Center 36 (5~67) winsize 63
5551 23:50:55.548354 [CA 2] Center 34 (4~65) winsize 62
5552 23:50:55.551091 [CA 3] Center 33 (3~64) winsize 62
5553 23:50:55.554724 [CA 4] Center 34 (4~65) winsize 62
5554 23:50:55.558290 [CA 5] Center 33 (3~64) winsize 62
5555 23:50:55.558715
5556 23:50:55.561076 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 23:50:55.561556
5558 23:50:55.564843 [CATrainingPosCal] consider 1 rank data
5559 23:50:55.567736 u2DelayCellTimex100 = 270/100 ps
5560 23:50:55.571036 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 23:50:55.577504 CA1 delay=36 (5~67),Diff = 3 PI (18 cell)
5562 23:50:55.580869 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 23:50:55.584418 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 23:50:55.587769 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 23:50:55.590663 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 23:50:55.591091
5567 23:50:55.593884 CA PerBit enable=1, Macro0, CA PI delay=33
5568 23:50:55.594310
5569 23:50:55.598665 [CBTSetCACLKResult] CA Dly = 33
5570 23:50:55.600594 CS Dly: 5 (0~36)
5571 23:50:55.601046 ==
5572 23:50:55.603988 Dram Type= 6, Freq= 0, CH_1, rank 1
5573 23:50:55.607575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 23:50:55.608006 ==
5575 23:50:55.613768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 23:50:55.618673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5577 23:50:55.621072 [CA 0] Center 36 (6~67) winsize 62
5578 23:50:55.624612 [CA 1] Center 36 (6~67) winsize 62
5579 23:50:55.627664 [CA 2] Center 34 (4~64) winsize 61
5580 23:50:55.631253 [CA 3] Center 33 (3~64) winsize 62
5581 23:50:55.634427 [CA 4] Center 33 (3~64) winsize 62
5582 23:50:55.638214 [CA 5] Center 33 (3~64) winsize 62
5583 23:50:55.638640
5584 23:50:55.640700 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5585 23:50:55.641123
5586 23:50:55.644324 [CATrainingPosCal] consider 2 rank data
5587 23:50:55.647593 u2DelayCellTimex100 = 270/100 ps
5588 23:50:55.650871 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 23:50:55.657223 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 23:50:55.660586 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 23:50:55.663880 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 23:50:55.667229 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5593 23:50:55.670840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5594 23:50:55.670950
5595 23:50:55.673629 CA PerBit enable=1, Macro0, CA PI delay=33
5596 23:50:55.673712
5597 23:50:55.676713 [CBTSetCACLKResult] CA Dly = 33
5598 23:50:55.680075 CS Dly: 6 (0~38)
5599 23:50:55.680159
5600 23:50:55.683340 ----->DramcWriteLeveling(PI) begin...
5601 23:50:55.683424 ==
5602 23:50:55.687148 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 23:50:55.690088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 23:50:55.690172 ==
5605 23:50:55.693342 Write leveling (Byte 0): 24 => 24
5606 23:50:55.696503 Write leveling (Byte 1): 26 => 26
5607 23:50:55.700455 DramcWriteLeveling(PI) end<-----
5608 23:50:55.700537
5609 23:50:55.700603 ==
5610 23:50:55.702862 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 23:50:55.706753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 23:50:55.706836 ==
5613 23:50:55.709914 [Gating] SW mode calibration
5614 23:50:55.716602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5615 23:50:55.722790 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5616 23:50:55.726804 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 23:50:55.733054 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 23:50:55.736050 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 23:50:55.739360 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 23:50:55.742839 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 23:50:55.749599 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 23:50:55.752740 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5623 23:50:55.755993 0 14 28 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
5624 23:50:55.762594 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 23:50:55.765793 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 23:50:55.769063 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 23:50:55.776012 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 23:50:55.779053 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 23:50:55.782541 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 23:50:55.789188 0 15 24 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
5631 23:50:55.792086 0 15 28 | B1->B0 | 3737 3f3f | 0 0 | (0 0) (0 0)
5632 23:50:55.795590 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 23:50:55.802285 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 23:50:55.805384 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 23:50:55.809108 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:50:55.815084 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 23:50:55.818435 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 23:50:55.825582 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 23:50:55.828148 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 23:50:55.831668 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:50:55.838121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:50:55.841473 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:50:55.844821 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:50:55.851700 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:50:55.854851 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:50:55.858045 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:50:55.864844 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:50:55.867999 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:50:55.870946 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:50:55.878129 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:50:55.881190 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:50:55.884307 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:50:55.890911 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:50:55.893870 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5655 23:50:55.897215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5656 23:50:55.900831 Total UI for P1: 0, mck2ui 16
5657 23:50:55.904099 best dqsien dly found for B1: ( 1, 2, 24)
5658 23:50:55.910492 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5659 23:50:55.910574 Total UI for P1: 0, mck2ui 16
5660 23:50:55.914204 best dqsien dly found for B0: ( 1, 2, 26)
5661 23:50:55.920498 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5662 23:50:55.923937 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5663 23:50:55.924019
5664 23:50:55.927736 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5665 23:50:55.930520 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5666 23:50:55.933539 [Gating] SW calibration Done
5667 23:50:55.933621 ==
5668 23:50:55.936988 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 23:50:55.940607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 23:50:55.940690 ==
5671 23:50:55.943694 RX Vref Scan: 0
5672 23:50:55.943776
5673 23:50:55.943840 RX Vref 0 -> 0, step: 1
5674 23:50:55.943901
5675 23:50:55.946813 RX Delay -80 -> 252, step: 8
5676 23:50:55.950030 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5677 23:50:55.957126 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5678 23:50:55.960437 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5679 23:50:55.963258 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5680 23:50:55.966696 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5681 23:50:55.970021 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5682 23:50:55.973087 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5683 23:50:55.980045 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5684 23:50:55.983088 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5685 23:50:55.986486 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5686 23:50:55.989977 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5687 23:50:55.992826 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5688 23:50:55.996303 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5689 23:50:56.003120 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5690 23:50:56.006372 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5691 23:50:56.009858 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5692 23:50:56.009940 ==
5693 23:50:56.013031 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 23:50:56.016268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 23:50:56.016354 ==
5696 23:50:56.019499 DQS Delay:
5697 23:50:56.019581 DQS0 = 0, DQS1 = 0
5698 23:50:56.022635 DQM Delay:
5699 23:50:56.022716 DQM0 = 99, DQM1 = 95
5700 23:50:56.026373 DQ Delay:
5701 23:50:56.026455 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5702 23:50:56.029997 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5703 23:50:56.032645 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5704 23:50:56.039265 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5705 23:50:56.039347
5706 23:50:56.039413
5707 23:50:56.039472 ==
5708 23:50:56.043046 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 23:50:56.045566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 23:50:56.045649 ==
5711 23:50:56.045725
5712 23:50:56.045787
5713 23:50:56.049407 TX Vref Scan disable
5714 23:50:56.049489 == TX Byte 0 ==
5715 23:50:56.055536 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5716 23:50:56.058800 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5717 23:50:56.061839 == TX Byte 1 ==
5718 23:50:56.066428 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 23:50:56.069110 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 23:50:56.069193 ==
5721 23:50:56.072230 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 23:50:56.075142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 23:50:56.075225 ==
5724 23:50:56.079041
5725 23:50:56.079122
5726 23:50:56.079187 TX Vref Scan disable
5727 23:50:56.082243 == TX Byte 0 ==
5728 23:50:56.085551 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5729 23:50:56.091901 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5730 23:50:56.091984 == TX Byte 1 ==
5731 23:50:56.095132 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 23:50:56.103189 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 23:50:56.103272
5734 23:50:56.103337 [DATLAT]
5735 23:50:56.103397 Freq=933, CH1 RK0
5736 23:50:56.103456
5737 23:50:56.104833 DATLAT Default: 0xd
5738 23:50:56.104915 0, 0xFFFF, sum = 0
5739 23:50:56.108109 1, 0xFFFF, sum = 0
5740 23:50:56.111659 2, 0xFFFF, sum = 0
5741 23:50:56.111743 3, 0xFFFF, sum = 0
5742 23:50:56.114812 4, 0xFFFF, sum = 0
5743 23:50:56.114896 5, 0xFFFF, sum = 0
5744 23:50:56.118041 6, 0xFFFF, sum = 0
5745 23:50:56.118124 7, 0xFFFF, sum = 0
5746 23:50:56.121874 8, 0xFFFF, sum = 0
5747 23:50:56.121958 9, 0xFFFF, sum = 0
5748 23:50:56.124551 10, 0x0, sum = 1
5749 23:50:56.124635 11, 0x0, sum = 2
5750 23:50:56.127818 12, 0x0, sum = 3
5751 23:50:56.127901 13, 0x0, sum = 4
5752 23:50:56.131989 best_step = 11
5753 23:50:56.132071
5754 23:50:56.132135 ==
5755 23:50:56.134853 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 23:50:56.137869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 23:50:56.137953 ==
5758 23:50:56.138018 RX Vref Scan: 1
5759 23:50:56.140953
5760 23:50:56.141034 RX Vref 0 -> 0, step: 1
5761 23:50:56.141100
5762 23:50:56.144315 RX Delay -53 -> 252, step: 4
5763 23:50:56.144397
5764 23:50:56.147589 Set Vref, RX VrefLevel [Byte0]: 53
5765 23:50:56.150876 [Byte1]: 49
5766 23:50:56.154666
5767 23:50:56.154750 Final RX Vref Byte 0 = 53 to rank0
5768 23:50:56.157646 Final RX Vref Byte 1 = 49 to rank0
5769 23:50:56.161158 Final RX Vref Byte 0 = 53 to rank1
5770 23:50:56.164617 Final RX Vref Byte 1 = 49 to rank1==
5771 23:50:56.167897 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 23:50:56.174236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 23:50:56.174319 ==
5774 23:50:56.174385 DQS Delay:
5775 23:50:56.178294 DQS0 = 0, DQS1 = 0
5776 23:50:56.178376 DQM Delay:
5777 23:50:56.178441 DQM0 = 98, DQM1 = 94
5778 23:50:56.181118 DQ Delay:
5779 23:50:56.184255 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5780 23:50:56.187260 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5781 23:50:56.190859 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5782 23:50:56.194688 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5783 23:50:56.194770
5784 23:50:56.194834
5785 23:50:56.200788 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
5786 23:50:56.204319 CH1 RK0: MR19=505, MR18=D1D
5787 23:50:56.210502 CH1_RK0: MR19=0x505, MR18=0xD1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5788 23:50:56.210585
5789 23:50:56.213815 ----->DramcWriteLeveling(PI) begin...
5790 23:50:56.213900 ==
5791 23:50:56.217168 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 23:50:56.220439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 23:50:56.220554 ==
5794 23:50:56.223781 Write leveling (Byte 0): 27 => 27
5795 23:50:56.226819 Write leveling (Byte 1): 26 => 26
5796 23:50:56.230455 DramcWriteLeveling(PI) end<-----
5797 23:50:56.230531
5798 23:50:56.230594 ==
5799 23:50:56.233595 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 23:50:56.240468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 23:50:56.240547 ==
5802 23:50:56.240616 [Gating] SW mode calibration
5803 23:50:56.250056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5804 23:50:56.253192 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5805 23:50:56.260415 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 23:50:56.262856 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 23:50:56.266253 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 23:50:56.272734 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 23:50:56.276569 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 23:50:56.280024 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 23:50:56.286016 0 14 24 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (1 0)
5812 23:50:56.289420 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5813 23:50:56.292685 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 23:50:56.299462 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 23:50:56.303059 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 23:50:56.305996 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 23:50:56.312774 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 23:50:56.316268 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 23:50:56.319039 0 15 24 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
5820 23:50:56.325905 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5821 23:50:56.329984 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 23:50:56.332131 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 23:50:56.339217 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 23:50:56.342958 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 23:50:56.345710 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 23:50:56.352249 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 23:50:56.355619 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5828 23:50:56.359022 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:50:56.365775 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:50:56.368927 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:50:56.371924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:50:56.378961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:50:56.381553 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:50:56.384638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:50:56.391502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:50:56.394695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:50:56.397959 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:50:56.404884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:50:56.407823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:50:56.411264 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:50:56.418224 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:50:56.421170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:50:56.424738 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5844 23:50:56.431224 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 23:50:56.431406 Total UI for P1: 0, mck2ui 16
5846 23:50:56.437849 best dqsien dly found for B0: ( 1, 2, 24)
5847 23:50:56.438062 Total UI for P1: 0, mck2ui 16
5848 23:50:56.441650 best dqsien dly found for B1: ( 1, 2, 24)
5849 23:50:56.447686 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5850 23:50:56.451903 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5851 23:50:56.452309
5852 23:50:56.454237 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5853 23:50:56.457752 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5854 23:50:56.461204 [Gating] SW calibration Done
5855 23:50:56.461688 ==
5856 23:50:56.464325 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 23:50:56.467738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 23:50:56.468172 ==
5859 23:50:56.471132 RX Vref Scan: 0
5860 23:50:56.471559
5861 23:50:56.471897 RX Vref 0 -> 0, step: 1
5862 23:50:56.472253
5863 23:50:56.474227 RX Delay -80 -> 252, step: 8
5864 23:50:56.477665 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5865 23:50:56.484524 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5866 23:50:56.487214 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5867 23:50:56.490758 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5868 23:50:56.494048 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5869 23:50:56.497143 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5870 23:50:56.500953 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5871 23:50:56.507927 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5872 23:50:56.510952 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5873 23:50:56.513639 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5874 23:50:56.517217 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5875 23:50:56.520259 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5876 23:50:56.526896 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5877 23:50:56.530064 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5878 23:50:56.533899 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5879 23:50:56.536932 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5880 23:50:56.537404 ==
5881 23:50:56.540327 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 23:50:56.543346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 23:50:56.547106 ==
5884 23:50:56.547533 DQS Delay:
5885 23:50:56.547870 DQS0 = 0, DQS1 = 0
5886 23:50:56.549975 DQM Delay:
5887 23:50:56.550398 DQM0 = 97, DQM1 = 94
5888 23:50:56.553385 DQ Delay:
5889 23:50:56.556176 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5890 23:50:56.559824 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5891 23:50:56.563259 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5892 23:50:56.566460 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5893 23:50:56.566890
5894 23:50:56.567226
5895 23:50:56.567538 ==
5896 23:50:56.569879 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 23:50:56.573048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 23:50:56.573554 ==
5899 23:50:56.573999
5900 23:50:56.574414
5901 23:50:56.576133 TX Vref Scan disable
5902 23:50:56.579521 == TX Byte 0 ==
5903 23:50:56.583375 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 23:50:56.586398 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 23:50:56.590197 == TX Byte 1 ==
5906 23:50:56.592952 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5907 23:50:56.596349 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5908 23:50:56.596801 ==
5909 23:50:56.599212 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 23:50:56.603066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 23:50:56.606486 ==
5912 23:50:56.606915
5913 23:50:56.607251
5914 23:50:56.607561 TX Vref Scan disable
5915 23:50:56.609701 == TX Byte 0 ==
5916 23:50:56.613396 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5917 23:50:56.619792 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5918 23:50:56.620221 == TX Byte 1 ==
5919 23:50:56.622803 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5920 23:50:56.629354 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5921 23:50:56.629785
5922 23:50:56.630122 [DATLAT]
5923 23:50:56.630435 Freq=933, CH1 RK1
5924 23:50:56.630741
5925 23:50:56.632491 DATLAT Default: 0xb
5926 23:50:56.635782 0, 0xFFFF, sum = 0
5927 23:50:56.636260 1, 0xFFFF, sum = 0
5928 23:50:56.639528 2, 0xFFFF, sum = 0
5929 23:50:56.639963 3, 0xFFFF, sum = 0
5930 23:50:56.642446 4, 0xFFFF, sum = 0
5931 23:50:56.642879 5, 0xFFFF, sum = 0
5932 23:50:56.645880 6, 0xFFFF, sum = 0
5933 23:50:56.646315 7, 0xFFFF, sum = 0
5934 23:50:56.649235 8, 0xFFFF, sum = 0
5935 23:50:56.649714 9, 0xFFFF, sum = 0
5936 23:50:56.652535 10, 0x0, sum = 1
5937 23:50:56.652968 11, 0x0, sum = 2
5938 23:50:56.655693 12, 0x0, sum = 3
5939 23:50:56.656124 13, 0x0, sum = 4
5940 23:50:56.658956 best_step = 11
5941 23:50:56.659382
5942 23:50:56.659733 ==
5943 23:50:56.662579 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 23:50:56.666167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 23:50:56.666599 ==
5946 23:50:56.666938 RX Vref Scan: 0
5947 23:50:56.667254
5948 23:50:56.668988 RX Vref 0 -> 0, step: 1
5949 23:50:56.669464
5950 23:50:56.672406 RX Delay -53 -> 252, step: 4
5951 23:50:56.679346 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5952 23:50:56.682096 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5953 23:50:56.685403 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5954 23:50:56.688849 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5955 23:50:56.692475 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5956 23:50:56.695307 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5957 23:50:56.701588 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5958 23:50:56.705196 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5959 23:50:56.708259 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5960 23:50:56.711524 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5961 23:50:56.714880 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5962 23:50:56.721309 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5963 23:50:56.724850 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5964 23:50:56.728045 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5965 23:50:56.731225 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5966 23:50:56.734903 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5967 23:50:56.737833 ==
5968 23:50:56.738259 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 23:50:56.745298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 23:50:56.745744 ==
5971 23:50:56.746083 DQS Delay:
5972 23:50:56.747980 DQS0 = 0, DQS1 = 0
5973 23:50:56.748404 DQM Delay:
5974 23:50:56.751391 DQM0 = 97, DQM1 = 92
5975 23:50:56.751818 DQ Delay:
5976 23:50:56.755185 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5977 23:50:56.757975 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =96
5978 23:50:56.761150 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
5979 23:50:56.764687 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5980 23:50:56.765112
5981 23:50:56.765499
5982 23:50:56.771287 [DQSOSCAuto] RK1, (LSB)MR18= 0xf26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5983 23:50:56.774057 CH1 RK1: MR19=505, MR18=F26
5984 23:50:56.780528 CH1_RK1: MR19=0x505, MR18=0xF26, DQSOSC=409, MR23=63, INC=64, DEC=43
5985 23:50:56.784045 [RxdqsGatingPostProcess] freq 933
5986 23:50:56.790903 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 23:50:56.794018 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 23:50:56.797398 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 23:50:56.800265 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 23:50:56.803473 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 23:50:56.803627 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 23:50:56.807600 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 23:50:56.810517 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 23:50:56.813679 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 23:50:56.817056 Pre-setting of DQS Precalculation
5996 23:50:56.823209 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 23:50:56.829935 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 23:50:56.838172 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 23:50:56.838602
6000 23:50:56.838878
6001 23:50:56.840308 [Calibration Summary] 1866 Mbps
6002 23:50:56.842989 CH 0, Rank 0
6003 23:50:56.843377 SW Impedance : PASS
6004 23:50:56.846940 DUTY Scan : NO K
6005 23:50:56.847470 ZQ Calibration : PASS
6006 23:50:56.849837 Jitter Meter : NO K
6007 23:50:56.852908 CBT Training : PASS
6008 23:50:56.853375 Write leveling : PASS
6009 23:50:56.856734 RX DQS gating : PASS
6010 23:50:56.859746 RX DQ/DQS(RDDQC) : PASS
6011 23:50:56.860285 TX DQ/DQS : PASS
6012 23:50:56.862942 RX DATLAT : PASS
6013 23:50:56.866693 RX DQ/DQS(Engine): PASS
6014 23:50:56.867229 TX OE : NO K
6015 23:50:56.870215 All Pass.
6016 23:50:56.870638
6017 23:50:56.870971 CH 0, Rank 1
6018 23:50:56.872765 SW Impedance : PASS
6019 23:50:56.873188 DUTY Scan : NO K
6020 23:50:56.877029 ZQ Calibration : PASS
6021 23:50:56.879992 Jitter Meter : NO K
6022 23:50:56.880420 CBT Training : PASS
6023 23:50:56.883358 Write leveling : PASS
6024 23:50:56.886112 RX DQS gating : PASS
6025 23:50:56.886554 RX DQ/DQS(RDDQC) : PASS
6026 23:50:56.889667 TX DQ/DQS : PASS
6027 23:50:56.893017 RX DATLAT : PASS
6028 23:50:56.893491 RX DQ/DQS(Engine): PASS
6029 23:50:56.896005 TX OE : NO K
6030 23:50:56.896557 All Pass.
6031 23:50:56.896904
6032 23:50:56.899702 CH 1, Rank 0
6033 23:50:56.900251 SW Impedance : PASS
6034 23:50:56.902745 DUTY Scan : NO K
6035 23:50:56.906254 ZQ Calibration : PASS
6036 23:50:56.906680 Jitter Meter : NO K
6037 23:50:56.909428 CBT Training : PASS
6038 23:50:56.912639 Write leveling : PASS
6039 23:50:56.913166 RX DQS gating : PASS
6040 23:50:56.915610 RX DQ/DQS(RDDQC) : PASS
6041 23:50:56.919320 TX DQ/DQS : PASS
6042 23:50:56.919840 RX DATLAT : PASS
6043 23:50:56.922177 RX DQ/DQS(Engine): PASS
6044 23:50:56.925971 TX OE : NO K
6045 23:50:56.926507 All Pass.
6046 23:50:56.926855
6047 23:50:56.927171 CH 1, Rank 1
6048 23:50:56.929220 SW Impedance : PASS
6049 23:50:56.932100 DUTY Scan : NO K
6050 23:50:56.932530 ZQ Calibration : PASS
6051 23:50:56.935210 Jitter Meter : NO K
6052 23:50:56.935634 CBT Training : PASS
6053 23:50:56.939015 Write leveling : PASS
6054 23:50:56.942029 RX DQS gating : PASS
6055 23:50:56.942548 RX DQ/DQS(RDDQC) : PASS
6056 23:50:56.945786 TX DQ/DQS : PASS
6057 23:50:56.948987 RX DATLAT : PASS
6058 23:50:56.949445 RX DQ/DQS(Engine): PASS
6059 23:50:56.951907 TX OE : NO K
6060 23:50:56.952430 All Pass.
6061 23:50:56.952790
6062 23:50:56.955481 DramC Write-DBI off
6063 23:50:56.958893 PER_BANK_REFRESH: Hybrid Mode
6064 23:50:56.959414 TX_TRACKING: ON
6065 23:50:56.968526 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 23:50:56.971862 [FAST_K] Save calibration result to emmc
6067 23:50:56.974619 dramc_set_vcore_voltage set vcore to 650000
6068 23:50:56.978095 Read voltage for 400, 6
6069 23:50:56.978523 Vio18 = 0
6070 23:50:56.981376 Vcore = 650000
6071 23:50:56.981804 Vdram = 0
6072 23:50:56.982147 Vddq = 0
6073 23:50:56.982466 Vmddr = 0
6074 23:50:56.988409 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 23:50:56.994525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 23:50:56.995092 MEM_TYPE=3, freq_sel=20
6077 23:50:56.998167 sv_algorithm_assistance_LP4_800
6078 23:50:57.001092 ============ PULL DRAM RESETB DOWN ============
6079 23:50:57.007914 ========== PULL DRAM RESETB DOWN end =========
6080 23:50:57.010993 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 23:50:57.014560 ===================================
6082 23:50:57.017627 LPDDR4 DRAM CONFIGURATION
6083 23:50:57.021729 ===================================
6084 23:50:57.022300 EX_ROW_EN[0] = 0x0
6085 23:50:57.024669 EX_ROW_EN[1] = 0x0
6086 23:50:57.025235 LP4Y_EN = 0x0
6087 23:50:57.027394 WORK_FSP = 0x0
6088 23:50:57.030886 WL = 0x2
6089 23:50:57.031355 RL = 0x2
6090 23:50:57.034581 BL = 0x2
6091 23:50:57.035162 RPST = 0x0
6092 23:50:57.038009 RD_PRE = 0x0
6093 23:50:57.038581 WR_PRE = 0x1
6094 23:50:57.041888 WR_PST = 0x0
6095 23:50:57.042464 DBI_WR = 0x0
6096 23:50:57.044959 DBI_RD = 0x0
6097 23:50:57.045584 OTF = 0x1
6098 23:50:57.047665 ===================================
6099 23:50:57.050942 ===================================
6100 23:50:57.053996 ANA top config
6101 23:50:57.057860 ===================================
6102 23:50:57.058335 DLL_ASYNC_EN = 0
6103 23:50:57.060609 ALL_SLAVE_EN = 1
6104 23:50:57.064201 NEW_RANK_MODE = 1
6105 23:50:57.067518 DLL_IDLE_MODE = 1
6106 23:50:57.068128 LP45_APHY_COMB_EN = 1
6107 23:50:57.070422 TX_ODT_DIS = 1
6108 23:50:57.074482 NEW_8X_MODE = 1
6109 23:50:57.077378 ===================================
6110 23:50:57.080817 ===================================
6111 23:50:57.084132 data_rate = 800
6112 23:50:57.087346 CKR = 1
6113 23:50:57.090695 DQ_P2S_RATIO = 4
6114 23:50:57.093875 ===================================
6115 23:50:57.094440 CA_P2S_RATIO = 4
6116 23:50:57.097478 DQ_CA_OPEN = 0
6117 23:50:57.100525 DQ_SEMI_OPEN = 1
6118 23:50:57.103659 CA_SEMI_OPEN = 1
6119 23:50:57.107061 CA_FULL_RATE = 0
6120 23:50:57.110109 DQ_CKDIV4_EN = 0
6121 23:50:57.110683 CA_CKDIV4_EN = 1
6122 23:50:57.114203 CA_PREDIV_EN = 0
6123 23:50:57.116914 PH8_DLY = 0
6124 23:50:57.120846 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 23:50:57.123730 DQ_AAMCK_DIV = 0
6126 23:50:57.127185 CA_AAMCK_DIV = 0
6127 23:50:57.127760 CA_ADMCK_DIV = 4
6128 23:50:57.129894 DQ_TRACK_CA_EN = 0
6129 23:50:57.133321 CA_PICK = 800
6130 23:50:57.136795 CA_MCKIO = 400
6131 23:50:57.139888 MCKIO_SEMI = 400
6132 23:50:57.143322 PLL_FREQ = 3016
6133 23:50:57.146676 DQ_UI_PI_RATIO = 32
6134 23:50:57.150127 CA_UI_PI_RATIO = 32
6135 23:50:57.153106 ===================================
6136 23:50:57.156143 ===================================
6137 23:50:57.156621 memory_type:LPDDR4
6138 23:50:57.159940 GP_NUM : 10
6139 23:50:57.163101 SRAM_EN : 1
6140 23:50:57.163574 MD32_EN : 0
6141 23:50:57.166112 ===================================
6142 23:50:57.169549 [ANA_INIT] >>>>>>>>>>>>>>
6143 23:50:57.172996 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 23:50:57.176605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 23:50:57.179731 ===================================
6146 23:50:57.182767 data_rate = 800,PCW = 0X7400
6147 23:50:57.185819 ===================================
6148 23:50:57.189502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 23:50:57.193250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 23:50:57.206061 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 23:50:57.209302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 23:50:57.212434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 23:50:57.215903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 23:50:57.219357 [ANA_INIT] flow start
6155 23:50:57.222517 [ANA_INIT] PLL >>>>>>>>
6156 23:50:57.222987 [ANA_INIT] PLL <<<<<<<<
6157 23:50:57.225747 [ANA_INIT] MIDPI >>>>>>>>
6158 23:50:57.229088 [ANA_INIT] MIDPI <<<<<<<<
6159 23:50:57.229746 [ANA_INIT] DLL >>>>>>>>
6160 23:50:57.232516 [ANA_INIT] flow end
6161 23:50:57.235429 ============ LP4 DIFF to SE enter ============
6162 23:50:57.242304 ============ LP4 DIFF to SE exit ============
6163 23:50:57.242867 [ANA_INIT] <<<<<<<<<<<<<
6164 23:50:57.245376 [Flow] Enable top DCM control >>>>>
6165 23:50:57.248642 [Flow] Enable top DCM control <<<<<
6166 23:50:57.252014 Enable DLL master slave shuffle
6167 23:50:57.258792 ==============================================================
6168 23:50:57.259360 Gating Mode config
6169 23:50:57.265027 ==============================================================
6170 23:50:57.268247 Config description:
6171 23:50:57.278853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 23:50:57.285491 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 23:50:57.288342 SELPH_MODE 0: By rank 1: By Phase
6174 23:50:57.294757 ==============================================================
6175 23:50:57.298205 GAT_TRACK_EN = 0
6176 23:50:57.301558 RX_GATING_MODE = 2
6177 23:50:57.302137 RX_GATING_TRACK_MODE = 2
6178 23:50:57.304532 SELPH_MODE = 1
6179 23:50:57.308091 PICG_EARLY_EN = 1
6180 23:50:57.310756 VALID_LAT_VALUE = 1
6181 23:50:57.317768 ==============================================================
6182 23:50:57.321773 Enter into Gating configuration >>>>
6183 23:50:57.324157 Exit from Gating configuration <<<<
6184 23:50:57.327772 Enter into DVFS_PRE_config >>>>>
6185 23:50:57.337600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 23:50:57.340941 Exit from DVFS_PRE_config <<<<<
6187 23:50:57.344104 Enter into PICG configuration >>>>
6188 23:50:57.347692 Exit from PICG configuration <<<<
6189 23:50:57.350547 [RX_INPUT] configuration >>>>>
6190 23:50:57.353816 [RX_INPUT] configuration <<<<<
6191 23:50:57.357023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 23:50:57.363843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 23:50:57.370558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 23:50:57.377042 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 23:50:57.383894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 23:50:57.390143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 23:50:57.393297 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 23:50:57.396585 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 23:50:57.400085 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 23:50:57.406863 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 23:50:57.409877 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 23:50:57.414017 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 23:50:57.416713 ===================================
6204 23:50:57.419965 LPDDR4 DRAM CONFIGURATION
6205 23:50:57.423246 ===================================
6206 23:50:57.423692 EX_ROW_EN[0] = 0x0
6207 23:50:57.426251 EX_ROW_EN[1] = 0x0
6208 23:50:57.426698 LP4Y_EN = 0x0
6209 23:50:57.429301 WORK_FSP = 0x0
6210 23:50:57.432692 WL = 0x2
6211 23:50:57.433359 RL = 0x2
6212 23:50:57.436163 BL = 0x2
6213 23:50:57.436687 RPST = 0x0
6214 23:50:57.439187 RD_PRE = 0x0
6215 23:50:57.439626 WR_PRE = 0x1
6216 23:50:57.442658 WR_PST = 0x0
6217 23:50:57.443098 DBI_WR = 0x0
6218 23:50:57.445925 DBI_RD = 0x0
6219 23:50:57.446406 OTF = 0x1
6220 23:50:57.449067 ===================================
6221 23:50:57.452810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 23:50:57.458903 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 23:50:57.462377 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 23:50:57.465578 ===================================
6225 23:50:57.469249 LPDDR4 DRAM CONFIGURATION
6226 23:50:57.472145 ===================================
6227 23:50:57.472643 EX_ROW_EN[0] = 0x10
6228 23:50:57.475898 EX_ROW_EN[1] = 0x0
6229 23:50:57.478588 LP4Y_EN = 0x0
6230 23:50:57.479036 WORK_FSP = 0x0
6231 23:50:57.481928 WL = 0x2
6232 23:50:57.482370 RL = 0x2
6233 23:50:57.485778 BL = 0x2
6234 23:50:57.486217 RPST = 0x0
6235 23:50:57.488798 RD_PRE = 0x0
6236 23:50:57.489239 WR_PRE = 0x1
6237 23:50:57.492532 WR_PST = 0x0
6238 23:50:57.493064 DBI_WR = 0x0
6239 23:50:57.495433 DBI_RD = 0x0
6240 23:50:57.495872 OTF = 0x1
6241 23:50:57.498797 ===================================
6242 23:50:57.505303 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 23:50:57.509836 nWR fixed to 30
6244 23:50:57.513142 [ModeRegInit_LP4] CH0 RK0
6245 23:50:57.513628 [ModeRegInit_LP4] CH0 RK1
6246 23:50:57.516492 [ModeRegInit_LP4] CH1 RK0
6247 23:50:57.520132 [ModeRegInit_LP4] CH1 RK1
6248 23:50:57.520668 match AC timing 19
6249 23:50:57.526329 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 23:50:57.530215 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 23:50:57.532622 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 23:50:57.539748 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 23:50:57.542487 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 23:50:57.542919 ==
6255 23:50:57.546128 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 23:50:57.549514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 23:50:57.550050 ==
6258 23:50:57.555925 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 23:50:57.562337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6260 23:50:57.565599 [CA 0] Center 36 (8~64) winsize 57
6261 23:50:57.568822 [CA 1] Center 36 (8~64) winsize 57
6262 23:50:57.572502 [CA 2] Center 36 (8~64) winsize 57
6263 23:50:57.575405 [CA 3] Center 36 (8~64) winsize 57
6264 23:50:57.579087 [CA 4] Center 36 (8~64) winsize 57
6265 23:50:57.579518 [CA 5] Center 36 (8~64) winsize 57
6266 23:50:57.582047
6267 23:50:57.586157 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6268 23:50:57.586693
6269 23:50:57.588814 [CATrainingPosCal] consider 1 rank data
6270 23:50:57.592651 u2DelayCellTimex100 = 270/100 ps
6271 23:50:57.595435 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:50:57.599268 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:50:57.602481 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:50:57.605552 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:50:57.608941 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:50:57.612116 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:50:57.612693
6278 23:50:57.615455 CA PerBit enable=1, Macro0, CA PI delay=36
6279 23:50:57.616033
6280 23:50:57.618474 [CBTSetCACLKResult] CA Dly = 36
6281 23:50:57.621844 CS Dly: 1 (0~32)
6282 23:50:57.622328 ==
6283 23:50:57.625352 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 23:50:57.628574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 23:50:57.629113 ==
6286 23:50:57.635049 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 23:50:57.641555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6288 23:50:57.645132 [CA 0] Center 36 (8~64) winsize 57
6289 23:50:57.648915 [CA 1] Center 36 (8~64) winsize 57
6290 23:50:57.649498 [CA 2] Center 36 (8~64) winsize 57
6291 23:50:57.651551 [CA 3] Center 36 (8~64) winsize 57
6292 23:50:57.654862 [CA 4] Center 36 (8~64) winsize 57
6293 23:50:57.657968 [CA 5] Center 36 (8~64) winsize 57
6294 23:50:57.658410
6295 23:50:57.661716 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6296 23:50:57.665884
6297 23:50:57.668167 [CATrainingPosCal] consider 2 rank data
6298 23:50:57.668782 u2DelayCellTimex100 = 270/100 ps
6299 23:50:57.674869 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:50:57.678206 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:50:57.681436 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:50:57.685206 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 23:50:57.688308 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 23:50:57.691329 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 23:50:57.691866
6306 23:50:57.694974 CA PerBit enable=1, Macro0, CA PI delay=36
6307 23:50:57.695517
6308 23:50:57.697708 [CBTSetCACLKResult] CA Dly = 36
6309 23:50:57.701740 CS Dly: 1 (0~32)
6310 23:50:57.702259
6311 23:50:57.704571 ----->DramcWriteLeveling(PI) begin...
6312 23:50:57.705101 ==
6313 23:50:57.707823 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 23:50:57.711699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 23:50:57.712228 ==
6316 23:50:57.714462 Write leveling (Byte 0): 40 => 8
6317 23:50:57.717889 Write leveling (Byte 1): 40 => 8
6318 23:50:57.721346 DramcWriteLeveling(PI) end<-----
6319 23:50:57.721870
6320 23:50:57.722207 ==
6321 23:50:57.725324 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 23:50:57.727619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 23:50:57.728143 ==
6324 23:50:57.730923 [Gating] SW mode calibration
6325 23:50:57.737366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 23:50:57.744371 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 23:50:57.748244 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 23:50:57.753695 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 23:50:57.757147 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 23:50:57.761249 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 23:50:57.764088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 23:50:57.771005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 23:50:57.774145 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 23:50:57.777075 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 23:50:57.783420 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 23:50:57.786602 Total UI for P1: 0, mck2ui 16
6337 23:50:57.790176 best dqsien dly found for B0: ( 0, 14, 24)
6338 23:50:57.793296 Total UI for P1: 0, mck2ui 16
6339 23:50:57.797161 best dqsien dly found for B1: ( 0, 14, 24)
6340 23:50:57.800485 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 23:50:57.803234 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 23:50:57.803712
6343 23:50:57.806460 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 23:50:57.809795 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 23:50:57.813414 [Gating] SW calibration Done
6346 23:50:57.813969 ==
6347 23:50:57.816893 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 23:50:57.820866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 23:50:57.823452 ==
6350 23:50:57.823971 RX Vref Scan: 0
6351 23:50:57.824313
6352 23:50:57.827141 RX Vref 0 -> 0, step: 1
6353 23:50:57.827664
6354 23:50:57.829690 RX Delay -410 -> 252, step: 16
6355 23:50:57.833223 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6356 23:50:57.836826 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6357 23:50:57.840371 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6358 23:50:57.846420 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6359 23:50:57.849686 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6360 23:50:57.853051 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6361 23:50:57.856269 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6362 23:50:57.863124 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6363 23:50:57.866119 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6364 23:50:57.869462 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6365 23:50:57.872434 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6366 23:50:57.878962 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6367 23:50:57.882666 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6368 23:50:57.885893 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6369 23:50:57.893651 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6370 23:50:57.895223 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6371 23:50:57.895649 ==
6372 23:50:57.899145 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 23:50:57.902005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 23:50:57.902437 ==
6375 23:50:57.905314 DQS Delay:
6376 23:50:57.905849 DQS0 = 35, DQS1 = 51
6377 23:50:57.909174 DQM Delay:
6378 23:50:57.909654 DQM0 = 4, DQM1 = 11
6379 23:50:57.909992 DQ Delay:
6380 23:50:57.912191 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6381 23:50:57.916654 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6382 23:50:57.918750 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6383 23:50:57.921827 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6384 23:50:57.922252
6385 23:50:57.922588
6386 23:50:57.922900 ==
6387 23:50:57.924673 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 23:50:57.931794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 23:50:57.932220 ==
6390 23:50:57.932567
6391 23:50:57.932880
6392 23:50:57.933175 TX Vref Scan disable
6393 23:50:57.934898 == TX Byte 0 ==
6394 23:50:57.938066 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 23:50:57.942091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 23:50:57.945167 == TX Byte 1 ==
6397 23:50:57.948166 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 23:50:57.952126 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 23:50:57.952645 ==
6400 23:50:57.954820 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 23:50:57.961321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 23:50:57.961861 ==
6403 23:50:57.962202
6404 23:50:57.962518
6405 23:50:57.964145 TX Vref Scan disable
6406 23:50:57.964568 == TX Byte 0 ==
6407 23:50:57.967930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 23:50:57.974749 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 23:50:57.975327 == TX Byte 1 ==
6410 23:50:57.977694 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 23:50:57.984099 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 23:50:57.984527
6413 23:50:57.984862 [DATLAT]
6414 23:50:57.985173 Freq=400, CH0 RK0
6415 23:50:57.985529
6416 23:50:57.987562 DATLAT Default: 0xf
6417 23:50:57.988078 0, 0xFFFF, sum = 0
6418 23:50:57.991201 1, 0xFFFF, sum = 0
6419 23:50:57.994523 2, 0xFFFF, sum = 0
6420 23:50:57.995049 3, 0xFFFF, sum = 0
6421 23:50:57.997853 4, 0xFFFF, sum = 0
6422 23:50:57.998380 5, 0xFFFF, sum = 0
6423 23:50:58.000784 6, 0xFFFF, sum = 0
6424 23:50:58.001354 7, 0xFFFF, sum = 0
6425 23:50:58.004164 8, 0xFFFF, sum = 0
6426 23:50:58.004690 9, 0xFFFF, sum = 0
6427 23:50:58.007407 10, 0xFFFF, sum = 0
6428 23:50:58.007839 11, 0xFFFF, sum = 0
6429 23:50:58.010627 12, 0xFFFF, sum = 0
6430 23:50:58.011154 13, 0x0, sum = 1
6431 23:50:58.013727 14, 0x0, sum = 2
6432 23:50:58.014258 15, 0x0, sum = 3
6433 23:50:58.016846 16, 0x0, sum = 4
6434 23:50:58.017310 best_step = 14
6435 23:50:58.017657
6436 23:50:58.017970 ==
6437 23:50:58.020560 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 23:50:58.027473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 23:50:58.028004 ==
6440 23:50:58.028345 RX Vref Scan: 1
6441 23:50:58.028657
6442 23:50:58.030447 RX Vref 0 -> 0, step: 1
6443 23:50:58.030869
6444 23:50:58.033225 RX Delay -343 -> 252, step: 8
6445 23:50:58.033706
6446 23:50:58.037457 Set Vref, RX VrefLevel [Byte0]: 53
6447 23:50:58.039928 [Byte1]: 47
6448 23:50:58.040353
6449 23:50:58.043675 Final RX Vref Byte 0 = 53 to rank0
6450 23:50:58.046817 Final RX Vref Byte 1 = 47 to rank0
6451 23:50:58.049976 Final RX Vref Byte 0 = 53 to rank1
6452 23:50:58.053308 Final RX Vref Byte 1 = 47 to rank1==
6453 23:50:58.056422 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 23:50:58.061321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 23:50:58.063568 ==
6456 23:50:58.063994 DQS Delay:
6457 23:50:58.064333 DQS0 = 40, DQS1 = 56
6458 23:50:58.066572 DQM Delay:
6459 23:50:58.066994 DQM0 = 7, DQM1 = 13
6460 23:50:58.070258 DQ Delay:
6461 23:50:58.070779 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =0
6462 23:50:58.073402 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6463 23:50:58.076381 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6464 23:50:58.079287 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6465 23:50:58.079716
6466 23:50:58.080051
6467 23:50:58.089530 [DQSOSCAuto] RK0, (LSB)MR18= 0x9589, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6468 23:50:58.092808 CH0 RK0: MR19=C0C, MR18=9589
6469 23:50:58.099831 CH0_RK0: MR19=0xC0C, MR18=0x9589, DQSOSC=391, MR23=63, INC=386, DEC=257
6470 23:50:58.100358 ==
6471 23:50:58.103366 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 23:50:58.105960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 23:50:58.106494 ==
6474 23:50:58.109484 [Gating] SW mode calibration
6475 23:50:58.115981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 23:50:58.122342 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 23:50:58.126112 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 23:50:58.129108 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 23:50:58.135619 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 23:50:58.139241 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 23:50:58.142193 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 23:50:58.149393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 23:50:58.151751 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 23:50:58.155387 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 23:50:58.162150 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 23:50:58.162680 Total UI for P1: 0, mck2ui 16
6487 23:50:58.165538 best dqsien dly found for B0: ( 0, 14, 24)
6488 23:50:58.168649 Total UI for P1: 0, mck2ui 16
6489 23:50:58.171892 best dqsien dly found for B1: ( 0, 14, 24)
6490 23:50:58.178288 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 23:50:58.181799 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 23:50:58.182226
6493 23:50:58.185598 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 23:50:58.188758 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 23:50:58.191563 [Gating] SW calibration Done
6496 23:50:58.192087 ==
6497 23:50:58.194725 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 23:50:58.198196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 23:50:58.198699 ==
6500 23:50:58.201392 RX Vref Scan: 0
6501 23:50:58.201914
6502 23:50:58.202255 RX Vref 0 -> 0, step: 1
6503 23:50:58.202575
6504 23:50:58.205193 RX Delay -410 -> 252, step: 16
6505 23:50:58.212264 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6506 23:50:58.214346 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6507 23:50:58.217919 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6508 23:50:58.221386 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6509 23:50:58.228041 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6510 23:50:58.231195 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6511 23:50:58.234666 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6512 23:50:58.237851 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6513 23:50:58.244256 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6514 23:50:58.248032 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6515 23:50:58.251308 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6516 23:50:58.254610 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6517 23:50:58.260953 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6518 23:50:58.264707 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6519 23:50:58.267456 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6520 23:50:58.274428 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6521 23:50:58.274982 ==
6522 23:50:58.277132 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 23:50:58.280756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 23:50:58.281233 ==
6525 23:50:58.281659 DQS Delay:
6526 23:50:58.284095 DQS0 = 35, DQS1 = 59
6527 23:50:58.284516 DQM Delay:
6528 23:50:58.287737 DQM0 = 5, DQM1 = 17
6529 23:50:58.288165 DQ Delay:
6530 23:50:58.290693 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6531 23:50:58.293479 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6532 23:50:58.296971 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6533 23:50:58.300861 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6534 23:50:58.301434
6535 23:50:58.301781
6536 23:50:58.302095 ==
6537 23:50:58.304084 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 23:50:58.306607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 23:50:58.307038 ==
6540 23:50:58.307463
6541 23:50:58.307787
6542 23:50:58.309873 TX Vref Scan disable
6543 23:50:58.310301 == TX Byte 0 ==
6544 23:50:58.316770 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 23:50:58.320362 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 23:50:58.320891 == TX Byte 1 ==
6547 23:50:58.326972 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6548 23:50:58.329814 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6549 23:50:58.330283 ==
6550 23:50:58.333288 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 23:50:58.336558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 23:50:58.337029 ==
6553 23:50:58.337417
6554 23:50:58.340164
6555 23:50:58.340738 TX Vref Scan disable
6556 23:50:58.342843 == TX Byte 0 ==
6557 23:50:58.346473 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6558 23:50:58.349751 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6559 23:50:58.353118 == TX Byte 1 ==
6560 23:50:58.356232 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6561 23:50:58.359676 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6562 23:50:58.360198
6563 23:50:58.360534 [DATLAT]
6564 23:50:58.363199 Freq=400, CH0 RK1
6565 23:50:58.363720
6566 23:50:58.366856 DATLAT Default: 0xe
6567 23:50:58.367380 0, 0xFFFF, sum = 0
6568 23:50:58.369011 1, 0xFFFF, sum = 0
6569 23:50:58.369472 2, 0xFFFF, sum = 0
6570 23:50:58.372457 3, 0xFFFF, sum = 0
6571 23:50:58.372881 4, 0xFFFF, sum = 0
6572 23:50:58.375803 5, 0xFFFF, sum = 0
6573 23:50:58.376362 6, 0xFFFF, sum = 0
6574 23:50:58.380315 7, 0xFFFF, sum = 0
6575 23:50:58.380858 8, 0xFFFF, sum = 0
6576 23:50:58.382543 9, 0xFFFF, sum = 0
6577 23:50:58.383070 10, 0xFFFF, sum = 0
6578 23:50:58.385401 11, 0xFFFF, sum = 0
6579 23:50:58.385830 12, 0xFFFF, sum = 0
6580 23:50:58.389135 13, 0x0, sum = 1
6581 23:50:58.389708 14, 0x0, sum = 2
6582 23:50:58.392405 15, 0x0, sum = 3
6583 23:50:58.392928 16, 0x0, sum = 4
6584 23:50:58.395789 best_step = 14
6585 23:50:58.396312
6586 23:50:58.396653 ==
6587 23:50:58.398914 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 23:50:58.401955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 23:50:58.402382 ==
6590 23:50:58.405816 RX Vref Scan: 0
6591 23:50:58.406327
6592 23:50:58.406663 RX Vref 0 -> 0, step: 1
6593 23:50:58.406976
6594 23:50:58.409073 RX Delay -359 -> 252, step: 8
6595 23:50:58.416835 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6596 23:50:58.420730 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6597 23:50:58.424090 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6598 23:50:58.430081 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6599 23:50:58.433115 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6600 23:50:58.436862 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6601 23:50:58.440586 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6602 23:50:58.446098 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6603 23:50:58.449640 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6604 23:50:58.453254 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6605 23:50:58.456170 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6606 23:50:58.463168 iDelay=209, Bit 11, Center -52 (-287 ~ 184) 472
6607 23:50:58.465957 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6608 23:50:58.469489 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6609 23:50:58.476315 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6610 23:50:58.479682 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6611 23:50:58.480205 ==
6612 23:50:58.482495 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 23:50:58.485740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 23:50:58.486173 ==
6615 23:50:58.489495 DQS Delay:
6616 23:50:58.490014 DQS0 = 44, DQS1 = 60
6617 23:50:58.490356 DQM Delay:
6618 23:50:58.492640 DQM0 = 9, DQM1 = 15
6619 23:50:58.493066 DQ Delay:
6620 23:50:58.495913 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6621 23:50:58.499403 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6622 23:50:58.502364 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6623 23:50:58.505379 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6624 23:50:58.505932
6625 23:50:58.506306
6626 23:50:58.515462 [DQSOSCAuto] RK1, (LSB)MR18= 0x8981, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6627 23:50:58.516025 CH0 RK1: MR19=C0C, MR18=8981
6628 23:50:58.522273 CH0_RK1: MR19=0xC0C, MR18=0x8981, DQSOSC=392, MR23=63, INC=384, DEC=256
6629 23:50:58.525239 [RxdqsGatingPostProcess] freq 400
6630 23:50:58.531802 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 23:50:58.534832 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 23:50:58.538033 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 23:50:58.541559 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 23:50:58.545233 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 23:50:58.548191 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 23:50:58.551689 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 23:50:58.554984 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 23:50:58.557921 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 23:50:58.558343 Pre-setting of DQS Precalculation
6640 23:50:58.564516 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 23:50:58.564943 ==
6642 23:50:58.567830 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 23:50:58.571394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 23:50:58.571914 ==
6645 23:50:58.578286 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 23:50:58.584707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6647 23:50:58.588173 [CA 0] Center 36 (8~64) winsize 57
6648 23:50:58.591142 [CA 1] Center 36 (8~64) winsize 57
6649 23:50:58.594009 [CA 2] Center 36 (8~64) winsize 57
6650 23:50:58.597321 [CA 3] Center 36 (8~64) winsize 57
6651 23:50:58.600987 [CA 4] Center 36 (8~64) winsize 57
6652 23:50:58.601535 [CA 5] Center 36 (8~64) winsize 57
6653 23:50:58.603892
6654 23:50:58.608066 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6655 23:50:58.608488
6656 23:50:58.610577 [CATrainingPosCal] consider 1 rank data
6657 23:50:58.614060 u2DelayCellTimex100 = 270/100 ps
6658 23:50:58.617485 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:50:58.620868 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:50:58.623934 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:50:58.627632 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:50:58.630966 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:50:58.633700 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:50:58.634124
6665 23:50:58.637366 CA PerBit enable=1, Macro0, CA PI delay=36
6666 23:50:58.640636
6667 23:50:58.641119 [CBTSetCACLKResult] CA Dly = 36
6668 23:50:58.644151 CS Dly: 1 (0~32)
6669 23:50:58.644576 ==
6670 23:50:58.647237 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 23:50:58.650528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 23:50:58.650961 ==
6673 23:50:58.656966 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 23:50:58.663973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6675 23:50:58.666608 [CA 0] Center 36 (8~64) winsize 57
6676 23:50:58.669897 [CA 1] Center 36 (8~64) winsize 57
6677 23:50:58.673739 [CA 2] Center 36 (8~64) winsize 57
6678 23:50:58.674440 [CA 3] Center 36 (8~64) winsize 57
6679 23:50:58.676865 [CA 4] Center 36 (8~64) winsize 57
6680 23:50:58.680485 [CA 5] Center 36 (8~64) winsize 57
6681 23:50:58.681007
6682 23:50:58.686966 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6683 23:50:58.687487
6684 23:50:58.690104 [CATrainingPosCal] consider 2 rank data
6685 23:50:58.693630 u2DelayCellTimex100 = 270/100 ps
6686 23:50:58.697046 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:50:58.700553 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:50:58.704436 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:50:58.706578 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 23:50:58.709834 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 23:50:58.713428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 23:50:58.713986
6693 23:50:58.717162 CA PerBit enable=1, Macro0, CA PI delay=36
6694 23:50:58.717780
6695 23:50:58.719951 [CBTSetCACLKResult] CA Dly = 36
6696 23:50:58.722803 CS Dly: 1 (0~32)
6697 23:50:58.723298
6698 23:50:58.726683 ----->DramcWriteLeveling(PI) begin...
6699 23:50:58.727254 ==
6700 23:50:58.730143 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 23:50:58.733404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 23:50:58.733967 ==
6703 23:50:58.736517 Write leveling (Byte 0): 40 => 8
6704 23:50:58.739725 Write leveling (Byte 1): 40 => 8
6705 23:50:58.742676 DramcWriteLeveling(PI) end<-----
6706 23:50:58.743150
6707 23:50:58.743519 ==
6708 23:50:58.746215 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 23:50:58.749288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 23:50:58.749714 ==
6711 23:50:58.753053 [Gating] SW mode calibration
6712 23:50:58.759321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 23:50:58.765878 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 23:50:58.769320 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 23:50:58.776246 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 23:50:58.780207 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 23:50:58.783293 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 23:50:58.789204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 23:50:58.792608 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 23:50:58.795898 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 23:50:58.802021 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 23:50:58.805810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 23:50:58.810321 Total UI for P1: 0, mck2ui 16
6724 23:50:58.811781 best dqsien dly found for B0: ( 0, 14, 24)
6725 23:50:58.815420 Total UI for P1: 0, mck2ui 16
6726 23:50:58.819310 best dqsien dly found for B1: ( 0, 14, 24)
6727 23:50:58.822321 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 23:50:58.825587 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 23:50:58.826197
6730 23:50:58.828462 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 23:50:58.831528 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 23:50:58.834833 [Gating] SW calibration Done
6733 23:50:58.835404 ==
6734 23:50:58.838664 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 23:50:58.841480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 23:50:58.844989 ==
6737 23:50:58.845534 RX Vref Scan: 0
6738 23:50:58.845872
6739 23:50:58.848730 RX Vref 0 -> 0, step: 1
6740 23:50:58.849144
6741 23:50:58.852595 RX Delay -410 -> 252, step: 16
6742 23:50:58.854417 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6743 23:50:58.857934 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6744 23:50:58.861786 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6745 23:50:58.868542 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6746 23:50:58.871580 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6747 23:50:58.874949 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6748 23:50:58.881775 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6749 23:50:58.884369 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6750 23:50:58.887852 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6751 23:50:58.891294 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6752 23:50:58.897502 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6753 23:50:58.900615 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6754 23:50:58.904130 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6755 23:50:58.907504 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6756 23:50:58.913719 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6757 23:50:58.917746 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6758 23:50:58.918309 ==
6759 23:50:58.920712 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 23:50:58.924063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 23:50:58.924627 ==
6762 23:50:58.928222 DQS Delay:
6763 23:50:58.928781 DQS0 = 35, DQS1 = 51
6764 23:50:58.930670 DQM Delay:
6765 23:50:58.931130 DQM0 = 6, DQM1 = 13
6766 23:50:58.931496 DQ Delay:
6767 23:50:58.934214 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6768 23:50:58.937111 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6769 23:50:58.940490 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6770 23:50:58.943479 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6771 23:50:58.943898
6772 23:50:58.944224
6773 23:50:58.944531 ==
6774 23:50:58.947119 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 23:50:58.953332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 23:50:58.953755 ==
6777 23:50:58.954087
6778 23:50:58.954395
6779 23:50:58.954686 TX Vref Scan disable
6780 23:50:58.957176 == TX Byte 0 ==
6781 23:50:58.960616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 23:50:58.963560 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 23:50:58.967172 == TX Byte 1 ==
6784 23:50:58.969863 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 23:50:58.973082 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 23:50:58.977086 ==
6787 23:50:58.977573 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 23:50:58.983116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 23:50:58.983814 ==
6790 23:50:58.984179
6791 23:50:58.984488
6792 23:50:58.986379 TX Vref Scan disable
6793 23:50:58.986799 == TX Byte 0 ==
6794 23:50:58.990008 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 23:50:58.996358 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 23:50:58.996877 == TX Byte 1 ==
6797 23:50:58.999643 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 23:50:59.006128 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 23:50:59.006569
6800 23:50:59.006901 [DATLAT]
6801 23:50:59.007210 Freq=400, CH1 RK0
6802 23:50:59.007697
6803 23:50:59.009524 DATLAT Default: 0xf
6804 23:50:59.009944 0, 0xFFFF, sum = 0
6805 23:50:59.013204 1, 0xFFFF, sum = 0
6806 23:50:59.016142 2, 0xFFFF, sum = 0
6807 23:50:59.016564 3, 0xFFFF, sum = 0
6808 23:50:59.020014 4, 0xFFFF, sum = 0
6809 23:50:59.020540 5, 0xFFFF, sum = 0
6810 23:50:59.022410 6, 0xFFFF, sum = 0
6811 23:50:59.022836 7, 0xFFFF, sum = 0
6812 23:50:59.025994 8, 0xFFFF, sum = 0
6813 23:50:59.026419 9, 0xFFFF, sum = 0
6814 23:50:59.029765 10, 0xFFFF, sum = 0
6815 23:50:59.030295 11, 0xFFFF, sum = 0
6816 23:50:59.032303 12, 0xFFFF, sum = 0
6817 23:50:59.032833 13, 0x0, sum = 1
6818 23:50:59.035678 14, 0x0, sum = 2
6819 23:50:59.036206 15, 0x0, sum = 3
6820 23:50:59.038796 16, 0x0, sum = 4
6821 23:50:59.039224 best_step = 14
6822 23:50:59.039553
6823 23:50:59.039858 ==
6824 23:50:59.042212 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 23:50:59.049435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 23:50:59.049974 ==
6827 23:50:59.050323 RX Vref Scan: 1
6828 23:50:59.050642
6829 23:50:59.052364 RX Vref 0 -> 0, step: 1
6830 23:50:59.052791
6831 23:50:59.055608 RX Delay -343 -> 252, step: 8
6832 23:50:59.056038
6833 23:50:59.058978 Set Vref, RX VrefLevel [Byte0]: 53
6834 23:50:59.062087 [Byte1]: 49
6835 23:50:59.062604
6836 23:50:59.065422 Final RX Vref Byte 0 = 53 to rank0
6837 23:50:59.068613 Final RX Vref Byte 1 = 49 to rank0
6838 23:50:59.071992 Final RX Vref Byte 0 = 53 to rank1
6839 23:50:59.074995 Final RX Vref Byte 1 = 49 to rank1==
6840 23:50:59.078236 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 23:50:59.082115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 23:50:59.085224 ==
6843 23:50:59.085826 DQS Delay:
6844 23:50:59.086313 DQS0 = 44, DQS1 = 52
6845 23:50:59.088001 DQM Delay:
6846 23:50:59.088535 DQM0 = 12, DQM1 = 11
6847 23:50:59.091438 DQ Delay:
6848 23:50:59.095282 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6849 23:50:59.095699 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6850 23:50:59.098241 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6851 23:50:59.101417 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6852 23:50:59.101837
6853 23:50:59.102165
6854 23:50:59.111716 [DQSOSCAuto] RK0, (LSB)MR18= 0x749a, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6855 23:50:59.114844 CH1 RK0: MR19=C0C, MR18=749A
6856 23:50:59.121212 CH1_RK0: MR19=0xC0C, MR18=0x749A, DQSOSC=390, MR23=63, INC=388, DEC=258
6857 23:50:59.121718 ==
6858 23:50:59.124539 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 23:50:59.128003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 23:50:59.128502 ==
6861 23:50:59.131347 [Gating] SW mode calibration
6862 23:50:59.137793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 23:50:59.144006 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 23:50:59.147225 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 23:50:59.150738 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 23:50:59.157309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 23:50:59.160995 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 23:50:59.164125 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 23:50:59.170289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 23:50:59.174256 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 23:50:59.176892 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 23:50:59.183302 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 23:50:59.183862 Total UI for P1: 0, mck2ui 16
6874 23:50:59.190460 best dqsien dly found for B0: ( 0, 14, 24)
6875 23:50:59.190787 Total UI for P1: 0, mck2ui 16
6876 23:50:59.196568 best dqsien dly found for B1: ( 0, 14, 24)
6877 23:50:59.200019 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 23:50:59.202948 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 23:50:59.203182
6880 23:50:59.206299 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 23:50:59.209619 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 23:50:59.213589 [Gating] SW calibration Done
6883 23:50:59.213815 ==
6884 23:50:59.216760 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 23:50:59.219879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 23:50:59.220150 ==
6887 23:50:59.222999 RX Vref Scan: 0
6888 23:50:59.223224
6889 23:50:59.223390 RX Vref 0 -> 0, step: 1
6890 23:50:59.226267
6891 23:50:59.226499 RX Delay -410 -> 252, step: 16
6892 23:50:59.233173 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6893 23:50:59.236143 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6894 23:50:59.239619 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6895 23:50:59.242886 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6896 23:50:59.249335 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6897 23:50:59.252715 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6898 23:50:59.256101 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6899 23:50:59.259420 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6900 23:50:59.266023 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6901 23:50:59.269349 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6902 23:50:59.272341 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6903 23:50:59.278970 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6904 23:50:59.282363 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6905 23:50:59.285825 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6906 23:50:59.289441 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6907 23:50:59.295979 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6908 23:50:59.296348 ==
6909 23:50:59.299274 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 23:50:59.301913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 23:50:59.302208 ==
6912 23:50:59.302427 DQS Delay:
6913 23:50:59.305285 DQS0 = 43, DQS1 = 51
6914 23:50:59.305564 DQM Delay:
6915 23:50:59.308331 DQM0 = 10, DQM1 = 13
6916 23:50:59.308605 DQ Delay:
6917 23:50:59.311900 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6918 23:50:59.315600 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6919 23:50:59.318299 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6920 23:50:59.321969 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6921 23:50:59.322260
6922 23:50:59.322493
6923 23:50:59.322720 ==
6924 23:50:59.325203 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 23:50:59.328666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 23:50:59.328942 ==
6927 23:50:59.331894
6928 23:50:59.332257
6929 23:50:59.332573 TX Vref Scan disable
6930 23:50:59.334872 == TX Byte 0 ==
6931 23:50:59.338210 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 23:50:59.341501 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 23:50:59.344605 == TX Byte 1 ==
6934 23:50:59.348322 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6935 23:50:59.351569 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6936 23:50:59.351844 ==
6937 23:50:59.354690 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 23:50:59.358669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 23:50:59.361682 ==
6940 23:50:59.361966
6941 23:50:59.362283
6942 23:50:59.362626 TX Vref Scan disable
6943 23:50:59.364787 == TX Byte 0 ==
6944 23:50:59.367913 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 23:50:59.371646 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 23:50:59.374368 == TX Byte 1 ==
6947 23:50:59.378276 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 23:50:59.381246 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 23:50:59.381522
6950 23:50:59.384727 [DATLAT]
6951 23:50:59.384965 Freq=400, CH1 RK1
6952 23:50:59.385170
6953 23:50:59.387797 DATLAT Default: 0xe
6954 23:50:59.388030 0, 0xFFFF, sum = 0
6955 23:50:59.391097 1, 0xFFFF, sum = 0
6956 23:50:59.391335 2, 0xFFFF, sum = 0
6957 23:50:59.395204 3, 0xFFFF, sum = 0
6958 23:50:59.395571 4, 0xFFFF, sum = 0
6959 23:50:59.397723 5, 0xFFFF, sum = 0
6960 23:50:59.398005 6, 0xFFFF, sum = 0
6961 23:50:59.401356 7, 0xFFFF, sum = 0
6962 23:50:59.401735 8, 0xFFFF, sum = 0
6963 23:50:59.404155 9, 0xFFFF, sum = 0
6964 23:50:59.404440 10, 0xFFFF, sum = 0
6965 23:50:59.407522 11, 0xFFFF, sum = 0
6966 23:50:59.411722 12, 0xFFFF, sum = 0
6967 23:50:59.412000 13, 0x0, sum = 1
6968 23:50:59.412225 14, 0x0, sum = 2
6969 23:50:59.413778 15, 0x0, sum = 3
6970 23:50:59.414055 16, 0x0, sum = 4
6971 23:50:59.417126 best_step = 14
6972 23:50:59.417463
6973 23:50:59.417682 ==
6974 23:50:59.420601 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 23:50:59.424203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 23:50:59.424562 ==
6977 23:50:59.427559 RX Vref Scan: 0
6978 23:50:59.428085
6979 23:50:59.428418 RX Vref 0 -> 0, step: 1
6980 23:50:59.430944
6981 23:50:59.431359 RX Delay -343 -> 252, step: 8
6982 23:50:59.439116 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6983 23:50:59.442530 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6984 23:50:59.446296 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6985 23:50:59.449098 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6986 23:50:59.455875 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6987 23:50:59.458641 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6988 23:50:59.462420 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6989 23:50:59.465647 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6990 23:50:59.472138 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6991 23:50:59.475244 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6992 23:50:59.479070 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6993 23:50:59.485227 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6994 23:50:59.488852 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6995 23:50:59.492552 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6996 23:50:59.495379 iDelay=217, Bit 14, Center -40 (-279 ~ 200) 480
6997 23:50:59.502155 iDelay=217, Bit 15, Center -32 (-271 ~ 208) 480
6998 23:50:59.502487 ==
6999 23:50:59.505200 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 23:50:59.508064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 23:50:59.508367 ==
7002 23:50:59.508573 DQS Delay:
7003 23:50:59.511577 DQS0 = 44, DQS1 = 56
7004 23:50:59.511901 DQM Delay:
7005 23:50:59.514746 DQM0 = 9, DQM1 = 14
7006 23:50:59.515049 DQ Delay:
7007 23:50:59.518217 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7008 23:50:59.522178 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
7009 23:50:59.524752 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7010 23:50:59.527987 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
7011 23:50:59.528288
7012 23:50:59.528554
7013 23:50:59.535316 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cb3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7014 23:50:59.537709 CH1 RK1: MR19=C0C, MR18=7CB3
7015 23:50:59.544748 CH1_RK1: MR19=0xC0C, MR18=0x7CB3, DQSOSC=387, MR23=63, INC=394, DEC=262
7016 23:50:59.548055 [RxdqsGatingPostProcess] freq 400
7017 23:50:59.554587 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 23:50:59.558524 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 23:50:59.560933 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 23:50:59.564298 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 23:50:59.568131 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 23:50:59.568592 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 23:50:59.571420 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 23:50:59.574578 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 23:50:59.577731 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 23:50:59.580919 Pre-setting of DQS Precalculation
7027 23:50:59.587454 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 23:50:59.594373 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 23:50:59.600217 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 23:50:59.600639
7031 23:50:59.600967
7032 23:50:59.604096 [Calibration Summary] 800 Mbps
7033 23:50:59.607656 CH 0, Rank 0
7034 23:50:59.608242 SW Impedance : PASS
7035 23:50:59.610564 DUTY Scan : NO K
7036 23:50:59.611129 ZQ Calibration : PASS
7037 23:50:59.613997 Jitter Meter : NO K
7038 23:50:59.617343 CBT Training : PASS
7039 23:50:59.617813 Write leveling : PASS
7040 23:50:59.620194 RX DQS gating : PASS
7041 23:50:59.623565 RX DQ/DQS(RDDQC) : PASS
7042 23:50:59.624083 TX DQ/DQS : PASS
7043 23:50:59.626648 RX DATLAT : PASS
7044 23:50:59.630337 RX DQ/DQS(Engine): PASS
7045 23:50:59.630757 TX OE : NO K
7046 23:50:59.633785 All Pass.
7047 23:50:59.634218
7048 23:50:59.634628 CH 0, Rank 1
7049 23:50:59.636794 SW Impedance : PASS
7050 23:50:59.637319 DUTY Scan : NO K
7051 23:50:59.640462 ZQ Calibration : PASS
7052 23:50:59.643594 Jitter Meter : NO K
7053 23:50:59.644039 CBT Training : PASS
7054 23:50:59.646765 Write leveling : NO K
7055 23:50:59.649786 RX DQS gating : PASS
7056 23:50:59.650087 RX DQ/DQS(RDDQC) : PASS
7057 23:50:59.653035 TX DQ/DQS : PASS
7058 23:50:59.656492 RX DATLAT : PASS
7059 23:50:59.656757 RX DQ/DQS(Engine): PASS
7060 23:50:59.659577 TX OE : NO K
7061 23:50:59.659767 All Pass.
7062 23:50:59.659914
7063 23:50:59.663455 CH 1, Rank 0
7064 23:50:59.663642 SW Impedance : PASS
7065 23:50:59.666116 DUTY Scan : NO K
7066 23:50:59.670005 ZQ Calibration : PASS
7067 23:50:59.670187 Jitter Meter : NO K
7068 23:50:59.672917 CBT Training : PASS
7069 23:50:59.676115 Write leveling : PASS
7070 23:50:59.676320 RX DQS gating : PASS
7071 23:50:59.679115 RX DQ/DQS(RDDQC) : PASS
7072 23:50:59.682576 TX DQ/DQS : PASS
7073 23:50:59.682760 RX DATLAT : PASS
7074 23:50:59.686311 RX DQ/DQS(Engine): PASS
7075 23:50:59.686506 TX OE : NO K
7076 23:50:59.689020 All Pass.
7077 23:50:59.689203
7078 23:50:59.689372 CH 1, Rank 1
7079 23:50:59.692399 SW Impedance : PASS
7080 23:50:59.695610 DUTY Scan : NO K
7081 23:50:59.695793 ZQ Calibration : PASS
7082 23:50:59.699081 Jitter Meter : NO K
7083 23:50:59.699265 CBT Training : PASS
7084 23:50:59.702112 Write leveling : NO K
7085 23:50:59.705841 RX DQS gating : PASS
7086 23:50:59.706025 RX DQ/DQS(RDDQC) : PASS
7087 23:50:59.708800 TX DQ/DQS : PASS
7088 23:50:59.712003 RX DATLAT : PASS
7089 23:50:59.712187 RX DQ/DQS(Engine): PASS
7090 23:50:59.715573 TX OE : NO K
7091 23:50:59.715756 All Pass.
7092 23:50:59.715902
7093 23:50:59.718813 DramC Write-DBI off
7094 23:50:59.722183 PER_BANK_REFRESH: Hybrid Mode
7095 23:50:59.722376 TX_TRACKING: ON
7096 23:50:59.731983 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 23:50:59.735590 [FAST_K] Save calibration result to emmc
7098 23:50:59.738797 dramc_set_vcore_voltage set vcore to 725000
7099 23:50:59.741919 Read voltage for 1600, 0
7100 23:50:59.742103 Vio18 = 0
7101 23:50:59.744867 Vcore = 725000
7102 23:50:59.745107 Vdram = 0
7103 23:50:59.745323 Vddq = 0
7104 23:50:59.745466 Vmddr = 0
7105 23:50:59.751528 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 23:50:59.758037 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 23:50:59.758254 MEM_TYPE=3, freq_sel=13
7108 23:50:59.761314 sv_algorithm_assistance_LP4_3733
7109 23:50:59.764779 ============ PULL DRAM RESETB DOWN ============
7110 23:50:59.771444 ========== PULL DRAM RESETB DOWN end =========
7111 23:50:59.774871 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 23:50:59.778045 ===================================
7113 23:50:59.781174 LPDDR4 DRAM CONFIGURATION
7114 23:50:59.784764 ===================================
7115 23:50:59.784980 EX_ROW_EN[0] = 0x0
7116 23:50:59.788095 EX_ROW_EN[1] = 0x0
7117 23:50:59.790962 LP4Y_EN = 0x0
7118 23:50:59.791179 WORK_FSP = 0x1
7119 23:50:59.794389 WL = 0x5
7120 23:50:59.794603 RL = 0x5
7121 23:50:59.797988 BL = 0x2
7122 23:50:59.798243 RPST = 0x0
7123 23:50:59.801681 RD_PRE = 0x0
7124 23:50:59.801897 WR_PRE = 0x1
7125 23:50:59.804739 WR_PST = 0x1
7126 23:50:59.804970 DBI_WR = 0x0
7127 23:50:59.808164 DBI_RD = 0x0
7128 23:50:59.808379 OTF = 0x1
7129 23:50:59.811186 ===================================
7130 23:50:59.814155 ===================================
7131 23:50:59.818047 ANA top config
7132 23:50:59.821414 ===================================
7133 23:50:59.821630 DLL_ASYNC_EN = 0
7134 23:50:59.824730 ALL_SLAVE_EN = 0
7135 23:50:59.827312 NEW_RANK_MODE = 1
7136 23:50:59.831220 DLL_IDLE_MODE = 1
7137 23:50:59.834589 LP45_APHY_COMB_EN = 1
7138 23:50:59.834805 TX_ODT_DIS = 0
7139 23:50:59.837557 NEW_8X_MODE = 1
7140 23:50:59.840848 ===================================
7141 23:50:59.844258 ===================================
7142 23:50:59.847815 data_rate = 3200
7143 23:50:59.850678 CKR = 1
7144 23:50:59.854021 DQ_P2S_RATIO = 8
7145 23:50:59.857206 ===================================
7146 23:50:59.860581 CA_P2S_RATIO = 8
7147 23:50:59.860795 DQ_CA_OPEN = 0
7148 23:50:59.864081 DQ_SEMI_OPEN = 0
7149 23:50:59.866859 CA_SEMI_OPEN = 0
7150 23:50:59.871142 CA_FULL_RATE = 0
7151 23:50:59.873404 DQ_CKDIV4_EN = 0
7152 23:50:59.877278 CA_CKDIV4_EN = 0
7153 23:50:59.877482 CA_PREDIV_EN = 0
7154 23:50:59.880595 PH8_DLY = 12
7155 23:50:59.883678 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 23:50:59.886971 DQ_AAMCK_DIV = 4
7157 23:50:59.889962 CA_AAMCK_DIV = 4
7158 23:50:59.893052 CA_ADMCK_DIV = 4
7159 23:50:59.893289 DQ_TRACK_CA_EN = 0
7160 23:50:59.896486 CA_PICK = 1600
7161 23:50:59.899748 CA_MCKIO = 1600
7162 23:50:59.903498 MCKIO_SEMI = 0
7163 23:50:59.906461 PLL_FREQ = 3068
7164 23:50:59.910253 DQ_UI_PI_RATIO = 32
7165 23:50:59.912830 CA_UI_PI_RATIO = 0
7166 23:50:59.916906 ===================================
7167 23:50:59.919929 ===================================
7168 23:50:59.920148 memory_type:LPDDR4
7169 23:50:59.923300 GP_NUM : 10
7170 23:50:59.926230 SRAM_EN : 1
7171 23:50:59.926446 MD32_EN : 0
7172 23:50:59.929527 ===================================
7173 23:50:59.933039 [ANA_INIT] >>>>>>>>>>>>>>
7174 23:50:59.936013 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 23:50:59.939228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 23:50:59.942944 ===================================
7177 23:50:59.945825 data_rate = 3200,PCW = 0X7600
7178 23:50:59.949201 ===================================
7179 23:50:59.952896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 23:50:59.956072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 23:50:59.962941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 23:50:59.969172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 23:50:59.972342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 23:50:59.975526 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 23:50:59.975614 [ANA_INIT] flow start
7186 23:50:59.979604 [ANA_INIT] PLL >>>>>>>>
7187 23:50:59.982761 [ANA_INIT] PLL <<<<<<<<
7188 23:50:59.982873 [ANA_INIT] MIDPI >>>>>>>>
7189 23:50:59.985711 [ANA_INIT] MIDPI <<<<<<<<
7190 23:50:59.989740 [ANA_INIT] DLL >>>>>>>>
7191 23:50:59.989863 [ANA_INIT] DLL <<<<<<<<
7192 23:50:59.992277 [ANA_INIT] flow end
7193 23:50:59.995407 ============ LP4 DIFF to SE enter ============
7194 23:51:00.002253 ============ LP4 DIFF to SE exit ============
7195 23:51:00.002484 [ANA_INIT] <<<<<<<<<<<<<
7196 23:51:00.005696 [Flow] Enable top DCM control >>>>>
7197 23:51:00.008499 [Flow] Enable top DCM control <<<<<
7198 23:51:00.012444 Enable DLL master slave shuffle
7199 23:51:00.019020 ==============================================================
7200 23:51:00.019152 Gating Mode config
7201 23:51:00.025158 ==============================================================
7202 23:51:00.028678 Config description:
7203 23:51:00.038373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 23:51:00.044987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 23:51:00.048020 SELPH_MODE 0: By rank 1: By Phase
7206 23:51:00.054839 ==============================================================
7207 23:51:00.057937 GAT_TRACK_EN = 1
7208 23:51:00.061227 RX_GATING_MODE = 2
7209 23:51:00.061345 RX_GATING_TRACK_MODE = 2
7210 23:51:00.064575 SELPH_MODE = 1
7211 23:51:00.068178 PICG_EARLY_EN = 1
7212 23:51:00.071301 VALID_LAT_VALUE = 1
7213 23:51:00.078577 ==============================================================
7214 23:51:00.081533 Enter into Gating configuration >>>>
7215 23:51:00.084401 Exit from Gating configuration <<<<
7216 23:51:00.087599 Enter into DVFS_PRE_config >>>>>
7217 23:51:00.097302 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 23:51:00.100804 Exit from DVFS_PRE_config <<<<<
7219 23:51:00.104457 Enter into PICG configuration >>>>
7220 23:51:00.107892 Exit from PICG configuration <<<<
7221 23:51:00.110758 [RX_INPUT] configuration >>>>>
7222 23:51:00.113870 [RX_INPUT] configuration <<<<<
7223 23:51:00.117408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 23:51:00.124000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 23:51:00.130401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 23:51:00.136838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 23:51:00.144699 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 23:51:00.146967 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 23:51:00.153505 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 23:51:00.157225 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 23:51:00.160227 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 23:51:00.163177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 23:51:00.169891 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 23:51:00.173274 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 23:51:00.176719 ===================================
7236 23:51:00.179800 LPDDR4 DRAM CONFIGURATION
7237 23:51:00.183561 ===================================
7238 23:51:00.183715 EX_ROW_EN[0] = 0x0
7239 23:51:00.186323 EX_ROW_EN[1] = 0x0
7240 23:51:00.186488 LP4Y_EN = 0x0
7241 23:51:00.189822 WORK_FSP = 0x1
7242 23:51:00.189958 WL = 0x5
7243 23:51:00.193231 RL = 0x5
7244 23:51:00.196729 BL = 0x2
7245 23:51:00.196865 RPST = 0x0
7246 23:51:00.199831 RD_PRE = 0x0
7247 23:51:00.199982 WR_PRE = 0x1
7248 23:51:00.202940 WR_PST = 0x1
7249 23:51:00.203075 DBI_WR = 0x0
7250 23:51:00.206036 DBI_RD = 0x0
7251 23:51:00.206183 OTF = 0x1
7252 23:51:00.209648 ===================================
7253 23:51:00.212956 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 23:51:00.219553 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 23:51:00.222566 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 23:51:00.225861 ===================================
7257 23:51:00.229148 LPDDR4 DRAM CONFIGURATION
7258 23:51:00.232849 ===================================
7259 23:51:00.233119 EX_ROW_EN[0] = 0x10
7260 23:51:00.236118 EX_ROW_EN[1] = 0x0
7261 23:51:00.238823 LP4Y_EN = 0x0
7262 23:51:00.239136 WORK_FSP = 0x1
7263 23:51:00.242120 WL = 0x5
7264 23:51:00.242362 RL = 0x5
7265 23:51:00.246041 BL = 0x2
7266 23:51:00.246283 RPST = 0x0
7267 23:51:00.248907 RD_PRE = 0x0
7268 23:51:00.249148 WR_PRE = 0x1
7269 23:51:00.253416 WR_PST = 0x1
7270 23:51:00.253658 DBI_WR = 0x0
7271 23:51:00.255265 DBI_RD = 0x0
7272 23:51:00.255506 OTF = 0x1
7273 23:51:00.259040 ===================================
7274 23:51:00.265245 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 23:51:00.265512 ==
7276 23:51:00.268312 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 23:51:00.271908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 23:51:00.275209 ==
7279 23:51:00.275324 [Duty_Offset_Calibration]
7280 23:51:00.278833 B0:2 B1:0 CA:4
7281 23:51:00.278914
7282 23:51:00.281832 [DutyScan_Calibration_Flow] k_type=0
7283 23:51:00.289953
7284 23:51:00.290035 ==CLK 0==
7285 23:51:00.293491 Final CLK duty delay cell = -4
7286 23:51:00.296504 [-4] MAX Duty = 5031%(X100), DQS PI = 34
7287 23:51:00.299928 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7288 23:51:00.303114 [-4] AVG Duty = 4922%(X100)
7289 23:51:00.303196
7290 23:51:00.306339 CH0 CLK Duty spec in!! Max-Min= 218%
7291 23:51:00.309816 [DutyScan_Calibration_Flow] ====Done====
7292 23:51:00.309898
7293 23:51:00.312859 [DutyScan_Calibration_Flow] k_type=1
7294 23:51:00.330046
7295 23:51:00.330134 ==DQS 0 ==
7296 23:51:00.333300 Final DQS duty delay cell = 0
7297 23:51:00.337039 [0] MAX Duty = 5218%(X100), DQS PI = 38
7298 23:51:00.339746 [0] MIN Duty = 5093%(X100), DQS PI = 10
7299 23:51:00.343204 [0] AVG Duty = 5155%(X100)
7300 23:51:00.343337
7301 23:51:00.343463 ==DQS 1 ==
7302 23:51:00.347109 Final DQS duty delay cell = 0
7303 23:51:00.350357 [0] MAX Duty = 5187%(X100), DQS PI = 2
7304 23:51:00.353192 [0] MIN Duty = 4969%(X100), DQS PI = 10
7305 23:51:00.356615 [0] AVG Duty = 5078%(X100)
7306 23:51:00.356727
7307 23:51:00.359912 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7308 23:51:00.360034
7309 23:51:00.362901 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7310 23:51:00.366090 [DutyScan_Calibration_Flow] ====Done====
7311 23:51:00.366226
7312 23:51:00.369616 [DutyScan_Calibration_Flow] k_type=3
7313 23:51:00.387608
7314 23:51:00.387690 ==DQM 0 ==
7315 23:51:00.390953 Final DQM duty delay cell = 0
7316 23:51:00.393804 [0] MAX Duty = 5124%(X100), DQS PI = 22
7317 23:51:00.397150 [0] MIN Duty = 4844%(X100), DQS PI = 56
7318 23:51:00.400730 [0] AVG Duty = 4984%(X100)
7319 23:51:00.400812
7320 23:51:00.400877 ==DQM 1 ==
7321 23:51:00.403841 Final DQM duty delay cell = 0
7322 23:51:00.407084 [0] MAX Duty = 5000%(X100), DQS PI = 2
7323 23:51:00.410019 [0] MIN Duty = 4844%(X100), DQS PI = 14
7324 23:51:00.413697 [0] AVG Duty = 4922%(X100)
7325 23:51:00.413770
7326 23:51:00.417194 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7327 23:51:00.417292
7328 23:51:00.419843 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7329 23:51:00.423117 [DutyScan_Calibration_Flow] ====Done====
7330 23:51:00.423206
7331 23:51:00.426386 [DutyScan_Calibration_Flow] k_type=2
7332 23:51:00.444542
7333 23:51:00.444719 ==DQ 0 ==
7334 23:51:00.448093 Final DQ duty delay cell = 0
7335 23:51:00.451271 [0] MAX Duty = 5124%(X100), DQS PI = 20
7336 23:51:00.454596 [0] MIN Duty = 4938%(X100), DQS PI = 12
7337 23:51:00.454797 [0] AVG Duty = 5031%(X100)
7338 23:51:00.457788
7339 23:51:00.457929 ==DQ 1 ==
7340 23:51:00.461216 Final DQ duty delay cell = 0
7341 23:51:00.464518 [0] MAX Duty = 5187%(X100), DQS PI = 2
7342 23:51:00.467500 [0] MIN Duty = 4938%(X100), DQS PI = 12
7343 23:51:00.467676 [0] AVG Duty = 5062%(X100)
7344 23:51:00.470804
7345 23:51:00.474217 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7346 23:51:00.474421
7347 23:51:00.477673 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7348 23:51:00.481215 [DutyScan_Calibration_Flow] ====Done====
7349 23:51:00.481478 ==
7350 23:51:00.484370 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 23:51:00.488424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 23:51:00.488960 ==
7353 23:51:00.490865 [Duty_Offset_Calibration]
7354 23:51:00.491288 B0:0 B1:-1 CA:3
7355 23:51:00.491622
7356 23:51:00.494285 [DutyScan_Calibration_Flow] k_type=0
7357 23:51:00.504612
7358 23:51:00.505162 ==CLK 0==
7359 23:51:00.507643 Final CLK duty delay cell = -4
7360 23:51:00.510823 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7361 23:51:00.514174 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7362 23:51:00.517405 [-4] AVG Duty = 4922%(X100)
7363 23:51:00.517834
7364 23:51:00.520627 CH1 CLK Duty spec in!! Max-Min= 156%
7365 23:51:00.524310 [DutyScan_Calibration_Flow] ====Done====
7366 23:51:00.524725
7367 23:51:00.527288 [DutyScan_Calibration_Flow] k_type=1
7368 23:51:00.543640
7369 23:51:00.544130 ==DQS 0 ==
7370 23:51:00.547171 Final DQS duty delay cell = 0
7371 23:51:00.550325 [0] MAX Duty = 5250%(X100), DQS PI = 28
7372 23:51:00.553323 [0] MIN Duty = 4907%(X100), DQS PI = 56
7373 23:51:00.556458 [0] AVG Duty = 5078%(X100)
7374 23:51:00.556886
7375 23:51:00.557423 ==DQS 1 ==
7376 23:51:00.559987 Final DQS duty delay cell = -4
7377 23:51:00.562999 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7378 23:51:00.566301 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7379 23:51:00.570045 [-4] AVG Duty = 4906%(X100)
7380 23:51:00.570460
7381 23:51:00.573120 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7382 23:51:00.573772
7383 23:51:00.576409 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7384 23:51:00.579847 [DutyScan_Calibration_Flow] ====Done====
7385 23:51:00.580450
7386 23:51:00.582837 [DutyScan_Calibration_Flow] k_type=3
7387 23:51:00.600295
7388 23:51:00.600761 ==DQM 0 ==
7389 23:51:00.603884 Final DQM duty delay cell = 0
7390 23:51:00.607281 [0] MAX Duty = 5062%(X100), DQS PI = 30
7391 23:51:00.610331 [0] MIN Duty = 4750%(X100), DQS PI = 40
7392 23:51:00.614085 [0] AVG Duty = 4906%(X100)
7393 23:51:00.614495
7394 23:51:00.614819 ==DQM 1 ==
7395 23:51:00.616946 Final DQM duty delay cell = 0
7396 23:51:00.620272 [0] MAX Duty = 5000%(X100), DQS PI = 30
7397 23:51:00.623484 [0] MIN Duty = 4813%(X100), DQS PI = 60
7398 23:51:00.627189 [0] AVG Duty = 4906%(X100)
7399 23:51:00.627601
7400 23:51:00.630556 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7401 23:51:00.630973
7402 23:51:00.633894 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7403 23:51:00.637088 [DutyScan_Calibration_Flow] ====Done====
7404 23:51:00.637547
7405 23:51:00.640059 [DutyScan_Calibration_Flow] k_type=2
7406 23:51:00.657092
7407 23:51:00.657549 ==DQ 0 ==
7408 23:51:00.659861 Final DQ duty delay cell = -4
7409 23:51:00.663204 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7410 23:51:00.667127 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7411 23:51:00.669935 [-4] AVG Duty = 4891%(X100)
7412 23:51:00.670389
7413 23:51:00.670723 ==DQ 1 ==
7414 23:51:00.672995 Final DQ duty delay cell = 0
7415 23:51:00.676228 [0] MAX Duty = 5062%(X100), DQS PI = 32
7416 23:51:00.679952 [0] MIN Duty = 4875%(X100), DQS PI = 0
7417 23:51:00.682913 [0] AVG Duty = 4968%(X100)
7418 23:51:00.683328
7419 23:51:00.686719 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7420 23:51:00.687140
7421 23:51:00.689870 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7422 23:51:00.692697 [DutyScan_Calibration_Flow] ====Done====
7423 23:51:00.696183 nWR fixed to 30
7424 23:51:00.700244 [ModeRegInit_LP4] CH0 RK0
7425 23:51:00.700756 [ModeRegInit_LP4] CH0 RK1
7426 23:51:00.703074 [ModeRegInit_LP4] CH1 RK0
7427 23:51:00.705869 [ModeRegInit_LP4] CH1 RK1
7428 23:51:00.706296 match AC timing 5
7429 23:51:00.712659 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 23:51:00.716860 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 23:51:00.719604 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 23:51:00.725985 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 23:51:00.729412 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 23:51:00.732351 [MiockJmeterHQA]
7435 23:51:00.732907
7436 23:51:00.735830 [DramcMiockJmeter] u1RxGatingPI = 0
7437 23:51:00.736360 0 : 4255, 4027
7438 23:51:00.736781 4 : 4253, 4027
7439 23:51:00.738976 8 : 4252, 4027
7440 23:51:00.739403 12 : 4365, 4140
7441 23:51:00.742405 16 : 4253, 4026
7442 23:51:00.743072 20 : 4252, 4027
7443 23:51:00.745779 24 : 4252, 4027
7444 23:51:00.746207 28 : 4363, 4137
7445 23:51:00.748858 32 : 4252, 4027
7446 23:51:00.749430 36 : 4363, 4137
7447 23:51:00.749782 40 : 4253, 4027
7448 23:51:00.751920 44 : 4252, 4027
7449 23:51:00.752348 48 : 4250, 4026
7450 23:51:00.755690 52 : 4255, 4030
7451 23:51:00.756225 56 : 4252, 4029
7452 23:51:00.758723 60 : 4250, 4027
7453 23:51:00.759152 64 : 4363, 4140
7454 23:51:00.762031 68 : 4250, 4026
7455 23:51:00.762564 72 : 4252, 4030
7456 23:51:00.762909 76 : 4250, 4027
7457 23:51:00.765357 80 : 4361, 4137
7458 23:51:00.765888 84 : 4250, 4026
7459 23:51:00.768661 88 : 4360, 4137
7460 23:51:00.769092 92 : 4250, 4027
7461 23:51:00.772182 96 : 4250, 2768
7462 23:51:00.772612 100 : 4250, 0
7463 23:51:00.772952 104 : 4250, 0
7464 23:51:00.775363 108 : 4250, 0
7465 23:51:00.775898 112 : 4361, 0
7466 23:51:00.778971 116 : 4250, 0
7467 23:51:00.779401 120 : 4250, 0
7468 23:51:00.779745 124 : 4250, 0
7469 23:51:00.782833 128 : 4360, 0
7470 23:51:00.783496 132 : 4360, 0
7471 23:51:00.785008 136 : 4250, 0
7472 23:51:00.785474 140 : 4250, 0
7473 23:51:00.785823 144 : 4250, 0
7474 23:51:00.788098 148 : 4252, 0
7475 23:51:00.788527 152 : 4250, 0
7476 23:51:00.791508 156 : 4250, 0
7477 23:51:00.791939 160 : 4252, 0
7478 23:51:00.792280 164 : 4361, 0
7479 23:51:00.795385 168 : 4250, 0
7480 23:51:00.795921 172 : 4250, 0
7481 23:51:00.798390 176 : 4250, 0
7482 23:51:00.798824 180 : 4360, 0
7483 23:51:00.799162 184 : 4361, 0
7484 23:51:00.801738 188 : 4250, 0
7485 23:51:00.802275 192 : 4250, 0
7486 23:51:00.802620 196 : 4250, 0
7487 23:51:00.805121 200 : 4250, 0
7488 23:51:00.805855 204 : 4250, 0
7489 23:51:00.808312 208 : 4250, 0
7490 23:51:00.808896 212 : 4252, 0
7491 23:51:00.809507 216 : 4361, 0
7492 23:51:00.811681 220 : 4250, 515
7493 23:51:00.812225 224 : 4250, 4016
7494 23:51:00.814611 228 : 4250, 4027
7495 23:51:00.815075 232 : 4253, 4029
7496 23:51:00.817960 236 : 4361, 4137
7497 23:51:00.818565 240 : 4361, 4137
7498 23:51:00.821305 244 : 4250, 4027
7499 23:51:00.821897 248 : 4363, 4140
7500 23:51:00.824618 252 : 4361, 4137
7501 23:51:00.825150 256 : 4250, 4026
7502 23:51:00.828397 260 : 4250, 4027
7503 23:51:00.828922 264 : 4252, 4030
7504 23:51:00.831256 268 : 4250, 4026
7505 23:51:00.831792 272 : 4250, 4027
7506 23:51:00.834696 276 : 4250, 4027
7507 23:51:00.835233 280 : 4250, 4027
7508 23:51:00.835628 284 : 4250, 4026
7509 23:51:00.837377 288 : 4361, 4137
7510 23:51:00.837811 292 : 4361, 4137
7511 23:51:00.841650 296 : 4250, 4026
7512 23:51:00.842185 300 : 4363, 4140
7513 23:51:00.844372 304 : 4361, 4137
7514 23:51:00.844907 308 : 4250, 4026
7515 23:51:00.847595 312 : 4250, 4027
7516 23:51:00.848120 316 : 4252, 4030
7517 23:51:00.850781 320 : 4250, 4026
7518 23:51:00.851212 324 : 4250, 4027
7519 23:51:00.854368 328 : 4250, 4027
7520 23:51:00.854798 332 : 4252, 3909
7521 23:51:00.858004 336 : 4250, 1472
7522 23:51:00.858540
7523 23:51:00.858878 MIOCK jitter meter ch=0
7524 23:51:00.859196
7525 23:51:00.860770 1T = (336-100) = 236 dly cells
7526 23:51:00.867380 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7527 23:51:00.867914 ==
7528 23:51:00.870697 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 23:51:00.873617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 23:51:00.874046 ==
7531 23:51:00.880532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 23:51:00.883593 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 23:51:00.887065 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 23:51:00.893379 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 23:51:00.903696 [CA 0] Center 43 (13~73) winsize 61
7536 23:51:00.906754 [CA 1] Center 42 (12~73) winsize 62
7537 23:51:00.909780 [CA 2] Center 37 (8~67) winsize 60
7538 23:51:00.913102 [CA 3] Center 37 (8~67) winsize 60
7539 23:51:00.917189 [CA 4] Center 36 (6~66) winsize 61
7540 23:51:00.919904 [CA 5] Center 35 (5~66) winsize 62
7541 23:51:00.920451
7542 23:51:00.923691 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 23:51:00.924120
7544 23:51:00.930216 [CATrainingPosCal] consider 1 rank data
7545 23:51:00.930645 u2DelayCellTimex100 = 275/100 ps
7546 23:51:00.936221 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7547 23:51:00.939355 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7548 23:51:00.943095 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7549 23:51:00.946591 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7550 23:51:00.949394 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7551 23:51:00.952829 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7552 23:51:00.953254
7553 23:51:00.956210 CA PerBit enable=1, Macro0, CA PI delay=35
7554 23:51:00.956691
7555 23:51:00.959583 [CBTSetCACLKResult] CA Dly = 35
7556 23:51:00.962947 CS Dly: 10 (0~41)
7557 23:51:00.966249 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 23:51:00.969500 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 23:51:00.970105 ==
7560 23:51:00.972886 Dram Type= 6, Freq= 0, CH_0, rank 1
7561 23:51:00.980197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 23:51:00.980775 ==
7563 23:51:00.982165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 23:51:00.988955 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 23:51:00.991906 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 23:51:00.998376 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 23:51:01.006688 [CA 0] Center 44 (14~75) winsize 62
7568 23:51:01.010085 [CA 1] Center 44 (14~74) winsize 61
7569 23:51:01.013019 [CA 2] Center 39 (10~69) winsize 60
7570 23:51:01.016507 [CA 3] Center 39 (10~68) winsize 59
7571 23:51:01.019634 [CA 4] Center 37 (7~67) winsize 61
7572 23:51:01.023204 [CA 5] Center 36 (6~66) winsize 61
7573 23:51:01.023342
7574 23:51:01.026922 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 23:51:01.027091
7576 23:51:01.032832 [CATrainingPosCal] consider 2 rank data
7577 23:51:01.032997 u2DelayCellTimex100 = 275/100 ps
7578 23:51:01.039369 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7579 23:51:01.043230 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7580 23:51:01.046159 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7581 23:51:01.049278 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7582 23:51:01.052444 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7583 23:51:01.055797 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7584 23:51:01.055923
7585 23:51:01.059229 CA PerBit enable=1, Macro0, CA PI delay=36
7586 23:51:01.059357
7587 23:51:01.062313 [CBTSetCACLKResult] CA Dly = 36
7588 23:51:01.065798 CS Dly: 11 (0~44)
7589 23:51:01.069203 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 23:51:01.072451 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 23:51:01.072564
7592 23:51:01.075642 ----->DramcWriteLeveling(PI) begin...
7593 23:51:01.078850 ==
7594 23:51:01.078933 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 23:51:01.085285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 23:51:01.085384 ==
7597 23:51:01.088664 Write leveling (Byte 0): 37 => 37
7598 23:51:01.092145 Write leveling (Byte 1): 25 => 25
7599 23:51:01.095398 DramcWriteLeveling(PI) end<-----
7600 23:51:01.095518
7601 23:51:01.095622 ==
7602 23:51:01.098714 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 23:51:01.101900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 23:51:01.102031 ==
7605 23:51:01.105105 [Gating] SW mode calibration
7606 23:51:01.111858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7607 23:51:01.118414 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7608 23:51:01.122269 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 23:51:01.125386 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 23:51:01.131853 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7611 23:51:01.134749 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7612 23:51:01.138208 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7613 23:51:01.144592 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
7614 23:51:01.148020 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 23:51:01.151078 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 23:51:01.158217 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 23:51:01.161096 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 23:51:01.164320 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7619 23:51:01.171086 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 1)
7620 23:51:01.174348 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7621 23:51:01.177639 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
7622 23:51:01.184533 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7623 23:51:01.187486 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 23:51:01.191283 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 23:51:01.197660 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 23:51:01.201527 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7627 23:51:01.204459 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7628 23:51:01.210948 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7629 23:51:01.214323 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7630 23:51:01.217417 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 23:51:01.224450 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 23:51:01.228168 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 23:51:01.231128 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 23:51:01.236847 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 23:51:01.240417 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 23:51:01.243838 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7637 23:51:01.250369 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7638 23:51:01.253607 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 23:51:01.257213 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:51:01.264026 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:51:01.266831 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:51:01.269884 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:51:01.276700 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:51:01.279846 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:51:01.283236 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:51:01.289890 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:51:01.292748 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:51:01.296235 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:51:01.302562 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7650 23:51:01.305634 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 23:51:01.309110 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 23:51:01.316618 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7653 23:51:01.316704 Total UI for P1: 0, mck2ui 16
7654 23:51:01.322681 best dqsien dly found for B0: ( 1, 9, 8)
7655 23:51:01.325720 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7656 23:51:01.329159 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7657 23:51:01.335492 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 23:51:01.335575 Total UI for P1: 0, mck2ui 16
7659 23:51:01.342370 best dqsien dly found for B1: ( 1, 9, 24)
7660 23:51:01.345707 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7661 23:51:01.348912 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7662 23:51:01.349019
7663 23:51:01.352112 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7664 23:51:01.355242 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7665 23:51:01.358242 [Gating] SW calibration Done
7666 23:51:01.358334 ==
7667 23:51:01.361852 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 23:51:01.365195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 23:51:01.365345 ==
7670 23:51:01.368519 RX Vref Scan: 0
7671 23:51:01.368609
7672 23:51:01.371555 RX Vref 0 -> 0, step: 1
7673 23:51:01.371627
7674 23:51:01.371688 RX Delay 0 -> 252, step: 8
7675 23:51:01.378355 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7676 23:51:01.381595 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7677 23:51:01.385524 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7678 23:51:01.388968 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7679 23:51:01.391708 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7680 23:51:01.398330 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7681 23:51:01.401233 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7682 23:51:01.404645 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7683 23:51:01.407891 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7684 23:51:01.411235 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7685 23:51:01.417941 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7686 23:51:01.421190 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7687 23:51:01.424829 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7688 23:51:01.428017 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7689 23:51:01.431218 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7690 23:51:01.438680 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7691 23:51:01.439179 ==
7692 23:51:01.441296 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 23:51:01.445417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 23:51:01.445933 ==
7695 23:51:01.446271 DQS Delay:
7696 23:51:01.448752 DQS0 = 0, DQS1 = 0
7697 23:51:01.449330 DQM Delay:
7698 23:51:01.451425 DQM0 = 131, DQM1 = 126
7699 23:51:01.451843 DQ Delay:
7700 23:51:01.455179 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7701 23:51:01.457895 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7702 23:51:01.461042 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7703 23:51:01.464822 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7704 23:51:01.467433
7705 23:51:01.467990
7706 23:51:01.468478 ==
7707 23:51:01.470916 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 23:51:01.474578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 23:51:01.475005 ==
7710 23:51:01.475342
7711 23:51:01.475652
7712 23:51:01.477821 TX Vref Scan disable
7713 23:51:01.478240 == TX Byte 0 ==
7714 23:51:01.484054 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7715 23:51:01.487522 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7716 23:51:01.487988 == TX Byte 1 ==
7717 23:51:01.494233 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7718 23:51:01.497430 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7719 23:51:01.497853 ==
7720 23:51:01.500607 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 23:51:01.503958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 23:51:01.504385 ==
7723 23:51:01.520645
7724 23:51:01.524532 TX Vref early break, caculate TX vref
7725 23:51:01.527261 TX Vref=16, minBit 8, minWin=21, winSum=370
7726 23:51:01.530983 TX Vref=18, minBit 8, minWin=22, winSum=376
7727 23:51:01.533432 TX Vref=20, minBit 1, minWin=24, winSum=390
7728 23:51:01.536842 TX Vref=22, minBit 4, minWin=24, winSum=400
7729 23:51:01.539697 TX Vref=24, minBit 10, minWin=24, winSum=407
7730 23:51:01.547236 TX Vref=26, minBit 4, minWin=25, winSum=417
7731 23:51:01.550005 TX Vref=28, minBit 4, minWin=25, winSum=418
7732 23:51:01.553385 TX Vref=30, minBit 1, minWin=25, winSum=416
7733 23:51:01.556885 TX Vref=32, minBit 0, minWin=25, winSum=406
7734 23:51:01.560127 TX Vref=34, minBit 1, minWin=24, winSum=397
7735 23:51:01.567152 TX Vref=36, minBit 0, minWin=23, winSum=383
7736 23:51:01.570299 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
7737 23:51:01.570756
7738 23:51:01.573314 Final TX Range 0 Vref 28
7739 23:51:01.573884
7740 23:51:01.574231 ==
7741 23:51:01.576761 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 23:51:01.579853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 23:51:01.582855 ==
7744 23:51:01.583276
7745 23:51:01.583609
7746 23:51:01.583917 TX Vref Scan disable
7747 23:51:01.589803 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7748 23:51:01.590224 == TX Byte 0 ==
7749 23:51:01.593643 u2DelayCellOfst[0]=14 cells (4 PI)
7750 23:51:01.596992 u2DelayCellOfst[1]=17 cells (5 PI)
7751 23:51:01.599588 u2DelayCellOfst[2]=14 cells (4 PI)
7752 23:51:01.603598 u2DelayCellOfst[3]=14 cells (4 PI)
7753 23:51:01.606037 u2DelayCellOfst[4]=10 cells (3 PI)
7754 23:51:01.609915 u2DelayCellOfst[5]=0 cells (0 PI)
7755 23:51:01.612926 u2DelayCellOfst[6]=21 cells (6 PI)
7756 23:51:01.616658 u2DelayCellOfst[7]=17 cells (5 PI)
7757 23:51:01.620139 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7758 23:51:01.622901 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7759 23:51:01.626055 == TX Byte 1 ==
7760 23:51:01.629631 u2DelayCellOfst[8]=0 cells (0 PI)
7761 23:51:01.632821 u2DelayCellOfst[9]=0 cells (0 PI)
7762 23:51:01.636141 u2DelayCellOfst[10]=3 cells (1 PI)
7763 23:51:01.639388 u2DelayCellOfst[11]=0 cells (0 PI)
7764 23:51:01.642607 u2DelayCellOfst[12]=7 cells (2 PI)
7765 23:51:01.645900 u2DelayCellOfst[13]=7 cells (2 PI)
7766 23:51:01.649729 u2DelayCellOfst[14]=14 cells (4 PI)
7767 23:51:01.652272 u2DelayCellOfst[15]=10 cells (3 PI)
7768 23:51:01.655434 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7769 23:51:01.658855 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7770 23:51:01.662343 DramC Write-DBI on
7771 23:51:01.662869 ==
7772 23:51:01.665164 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 23:51:01.668624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 23:51:01.669153 ==
7775 23:51:01.669535
7776 23:51:01.669854
7777 23:51:01.671722 TX Vref Scan disable
7778 23:51:01.675157 == TX Byte 0 ==
7779 23:51:01.678913 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7780 23:51:01.679375 == TX Byte 1 ==
7781 23:51:01.685291 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7782 23:51:01.685721 DramC Write-DBI off
7783 23:51:01.686058
7784 23:51:01.688368 [DATLAT]
7785 23:51:01.688791 Freq=1600, CH0 RK0
7786 23:51:01.689130
7787 23:51:01.691764 DATLAT Default: 0xf
7788 23:51:01.692185 0, 0xFFFF, sum = 0
7789 23:51:01.694763 1, 0xFFFF, sum = 0
7790 23:51:01.695192 2, 0xFFFF, sum = 0
7791 23:51:01.698062 3, 0xFFFF, sum = 0
7792 23:51:01.698492 4, 0xFFFF, sum = 0
7793 23:51:01.701445 5, 0xFFFF, sum = 0
7794 23:51:01.701874 6, 0xFFFF, sum = 0
7795 23:51:01.705210 7, 0xFFFF, sum = 0
7796 23:51:01.705666 8, 0xFFFF, sum = 0
7797 23:51:01.708705 9, 0xFFFF, sum = 0
7798 23:51:01.709134 10, 0xFFFF, sum = 0
7799 23:51:01.711697 11, 0xFFFF, sum = 0
7800 23:51:01.714969 12, 0xFFFF, sum = 0
7801 23:51:01.715400 13, 0xFFFF, sum = 0
7802 23:51:01.719071 14, 0x0, sum = 1
7803 23:51:01.719606 15, 0x0, sum = 2
7804 23:51:01.719949 16, 0x0, sum = 3
7805 23:51:01.722288 17, 0x0, sum = 4
7806 23:51:01.722809 best_step = 15
7807 23:51:01.723150
7808 23:51:01.725356 ==
7809 23:51:01.725788 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 23:51:01.731463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 23:51:01.731995 ==
7812 23:51:01.732336 RX Vref Scan: 1
7813 23:51:01.732648
7814 23:51:01.734445 Set Vref Range= 24 -> 127
7815 23:51:01.734868
7816 23:51:01.738153 RX Vref 24 -> 127, step: 1
7817 23:51:01.738577
7818 23:51:01.741319 RX Delay 11 -> 252, step: 4
7819 23:51:01.741743
7820 23:51:01.744263 Set Vref, RX VrefLevel [Byte0]: 24
7821 23:51:01.748221 [Byte1]: 24
7822 23:51:01.748748
7823 23:51:01.751231 Set Vref, RX VrefLevel [Byte0]: 25
7824 23:51:01.754962 [Byte1]: 25
7825 23:51:01.755488
7826 23:51:01.758110 Set Vref, RX VrefLevel [Byte0]: 26
7827 23:51:01.760590 [Byte1]: 26
7828 23:51:01.764742
7829 23:51:01.765305 Set Vref, RX VrefLevel [Byte0]: 27
7830 23:51:01.767479 [Byte1]: 27
7831 23:51:01.772163
7832 23:51:01.772686 Set Vref, RX VrefLevel [Byte0]: 28
7833 23:51:01.775353 [Byte1]: 28
7834 23:51:01.779460
7835 23:51:01.779881 Set Vref, RX VrefLevel [Byte0]: 29
7836 23:51:01.782851 [Byte1]: 29
7837 23:51:01.787551
7838 23:51:01.787968 Set Vref, RX VrefLevel [Byte0]: 30
7839 23:51:01.790267 [Byte1]: 30
7840 23:51:01.794657
7841 23:51:01.795074 Set Vref, RX VrefLevel [Byte0]: 31
7842 23:51:01.798459 [Byte1]: 31
7843 23:51:01.802829
7844 23:51:01.803354 Set Vref, RX VrefLevel [Byte0]: 32
7845 23:51:01.805784 [Byte1]: 32
7846 23:51:01.810304
7847 23:51:01.810770 Set Vref, RX VrefLevel [Byte0]: 33
7848 23:51:01.813949 [Byte1]: 33
7849 23:51:01.817631
7850 23:51:01.818050 Set Vref, RX VrefLevel [Byte0]: 34
7851 23:51:01.821413 [Byte1]: 34
7852 23:51:01.825677
7853 23:51:01.826246 Set Vref, RX VrefLevel [Byte0]: 35
7854 23:51:01.829329 [Byte1]: 35
7855 23:51:01.832977
7856 23:51:01.833627 Set Vref, RX VrefLevel [Byte0]: 36
7857 23:51:01.836343 [Byte1]: 36
7858 23:51:01.841129
7859 23:51:01.841776 Set Vref, RX VrefLevel [Byte0]: 37
7860 23:51:01.843841 [Byte1]: 37
7861 23:51:01.847974
7862 23:51:01.848475 Set Vref, RX VrefLevel [Byte0]: 38
7863 23:51:01.851510 [Byte1]: 38
7864 23:51:01.856177
7865 23:51:01.856741 Set Vref, RX VrefLevel [Byte0]: 39
7866 23:51:01.859643 [Byte1]: 39
7867 23:51:01.863694
7868 23:51:01.864185 Set Vref, RX VrefLevel [Byte0]: 40
7869 23:51:01.866790 [Byte1]: 40
7870 23:51:01.871153
7871 23:51:01.871665 Set Vref, RX VrefLevel [Byte0]: 41
7872 23:51:01.874204 [Byte1]: 41
7873 23:51:01.878823
7874 23:51:01.879395 Set Vref, RX VrefLevel [Byte0]: 42
7875 23:51:01.882058 [Byte1]: 42
7876 23:51:01.886413
7877 23:51:01.886971 Set Vref, RX VrefLevel [Byte0]: 43
7878 23:51:01.889474 [Byte1]: 43
7879 23:51:01.894439
7880 23:51:01.894997 Set Vref, RX VrefLevel [Byte0]: 44
7881 23:51:01.897078 [Byte1]: 44
7882 23:51:01.902036
7883 23:51:01.902607 Set Vref, RX VrefLevel [Byte0]: 45
7884 23:51:01.904845 [Byte1]: 45
7885 23:51:01.909225
7886 23:51:01.912350 Set Vref, RX VrefLevel [Byte0]: 46
7887 23:51:01.915609 [Byte1]: 46
7888 23:51:01.916071
7889 23:51:01.918898 Set Vref, RX VrefLevel [Byte0]: 47
7890 23:51:01.922190 [Byte1]: 47
7891 23:51:01.922771
7892 23:51:01.925546 Set Vref, RX VrefLevel [Byte0]: 48
7893 23:51:01.928693 [Byte1]: 48
7894 23:51:01.931862
7895 23:51:01.932339 Set Vref, RX VrefLevel [Byte0]: 49
7896 23:51:01.935488 [Byte1]: 49
7897 23:51:01.939185
7898 23:51:01.939782 Set Vref, RX VrefLevel [Byte0]: 50
7899 23:51:01.942638 [Byte1]: 50
7900 23:51:01.947218
7901 23:51:01.947635 Set Vref, RX VrefLevel [Byte0]: 51
7902 23:51:01.950083 [Byte1]: 51
7903 23:51:01.954771
7904 23:51:01.955189 Set Vref, RX VrefLevel [Byte0]: 52
7905 23:51:01.958663 [Byte1]: 52
7906 23:51:01.962954
7907 23:51:01.963483 Set Vref, RX VrefLevel [Byte0]: 53
7908 23:51:01.965977 [Byte1]: 53
7909 23:51:01.970171
7910 23:51:01.970699 Set Vref, RX VrefLevel [Byte0]: 54
7911 23:51:01.973442 [Byte1]: 54
7912 23:51:01.977918
7913 23:51:01.978468 Set Vref, RX VrefLevel [Byte0]: 55
7914 23:51:01.981686 [Byte1]: 55
7915 23:51:01.985676
7916 23:51:01.986371 Set Vref, RX VrefLevel [Byte0]: 56
7917 23:51:01.988133 [Byte1]: 56
7918 23:51:01.992993
7919 23:51:01.993508 Set Vref, RX VrefLevel [Byte0]: 57
7920 23:51:01.995926 [Byte1]: 57
7921 23:51:02.000830
7922 23:51:02.001251 Set Vref, RX VrefLevel [Byte0]: 58
7923 23:51:02.003408 [Byte1]: 58
7924 23:51:02.008273
7925 23:51:02.008828 Set Vref, RX VrefLevel [Byte0]: 59
7926 23:51:02.011770 [Byte1]: 59
7927 23:51:02.015741
7928 23:51:02.016232 Set Vref, RX VrefLevel [Byte0]: 60
7929 23:51:02.018621 [Byte1]: 60
7930 23:51:02.022886
7931 23:51:02.023303 Set Vref, RX VrefLevel [Byte0]: 61
7932 23:51:02.026474 [Byte1]: 61
7933 23:51:02.030768
7934 23:51:02.031187 Set Vref, RX VrefLevel [Byte0]: 62
7935 23:51:02.033844 [Byte1]: 62
7936 23:51:02.038398
7937 23:51:02.038826 Set Vref, RX VrefLevel [Byte0]: 63
7938 23:51:02.042115 [Byte1]: 63
7939 23:51:02.045837
7940 23:51:02.046360 Set Vref, RX VrefLevel [Byte0]: 64
7941 23:51:02.049382 [Byte1]: 64
7942 23:51:02.053692
7943 23:51:02.054364 Set Vref, RX VrefLevel [Byte0]: 65
7944 23:51:02.056908 [Byte1]: 65
7945 23:51:02.061126
7946 23:51:02.061653 Set Vref, RX VrefLevel [Byte0]: 66
7947 23:51:02.064192 [Byte1]: 66
7948 23:51:02.069054
7949 23:51:02.069606 Set Vref, RX VrefLevel [Byte0]: 67
7950 23:51:02.072094 [Byte1]: 67
7951 23:51:02.076076
7952 23:51:02.076378 Set Vref, RX VrefLevel [Byte0]: 68
7953 23:51:02.079444 [Byte1]: 68
7954 23:51:02.083709
7955 23:51:02.084007 Set Vref, RX VrefLevel [Byte0]: 69
7956 23:51:02.087060 [Byte1]: 69
7957 23:51:02.091789
7958 23:51:02.092111 Set Vref, RX VrefLevel [Byte0]: 70
7959 23:51:02.094721 [Byte1]: 70
7960 23:51:02.099151
7961 23:51:02.099379 Set Vref, RX VrefLevel [Byte0]: 71
7962 23:51:02.102261 [Byte1]: 71
7963 23:51:02.106381
7964 23:51:02.106607 Set Vref, RX VrefLevel [Byte0]: 72
7965 23:51:02.110189 [Byte1]: 72
7966 23:51:02.114695
7967 23:51:02.114923 Set Vref, RX VrefLevel [Byte0]: 73
7968 23:51:02.117623 [Byte1]: 73
7969 23:51:02.121834
7970 23:51:02.122048 Set Vref, RX VrefLevel [Byte0]: 74
7971 23:51:02.125023 [Byte1]: 74
7972 23:51:02.129218
7973 23:51:02.129350 Final RX Vref Byte 0 = 57 to rank0
7974 23:51:02.132384 Final RX Vref Byte 1 = 56 to rank0
7975 23:51:02.135697 Final RX Vref Byte 0 = 57 to rank1
7976 23:51:02.138977 Final RX Vref Byte 1 = 56 to rank1==
7977 23:51:02.142524 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 23:51:02.149055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 23:51:02.149160 ==
7980 23:51:02.149251 DQS Delay:
7981 23:51:02.153207 DQS0 = 0, DQS1 = 0
7982 23:51:02.153354 DQM Delay:
7983 23:51:02.153458 DQM0 = 128, DQM1 = 124
7984 23:51:02.156081 DQ Delay:
7985 23:51:02.158982 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7986 23:51:02.162212 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7987 23:51:02.166033 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7988 23:51:02.169071 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7989 23:51:02.169144
7990 23:51:02.169206
7991 23:51:02.169293
7992 23:51:02.172298 [DramC_TX_OE_Calibration] TA2
7993 23:51:02.175458 Original DQ_B0 (3 6) =30, OEN = 27
7994 23:51:02.178749 Original DQ_B1 (3 6) =30, OEN = 27
7995 23:51:02.182177 24, 0x0, End_B0=24 End_B1=24
7996 23:51:02.182251 25, 0x0, End_B0=25 End_B1=25
7997 23:51:02.185771 26, 0x0, End_B0=26 End_B1=26
7998 23:51:02.188972 27, 0x0, End_B0=27 End_B1=27
7999 23:51:02.191993 28, 0x0, End_B0=28 End_B1=28
8000 23:51:02.195664 29, 0x0, End_B0=29 End_B1=29
8001 23:51:02.195749 30, 0x0, End_B0=30 End_B1=30
8002 23:51:02.198722 31, 0x4141, End_B0=30 End_B1=30
8003 23:51:02.202107 Byte0 end_step=30 best_step=27
8004 23:51:02.205412 Byte1 end_step=30 best_step=27
8005 23:51:02.208901 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 23:51:02.212233 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 23:51:02.212332
8008 23:51:02.212402
8009 23:51:02.218301 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
8010 23:51:02.221801 CH0 RK0: MR19=303, MR18=1A17
8011 23:51:02.228599 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
8012 23:51:02.228696
8013 23:51:02.232309 ----->DramcWriteLeveling(PI) begin...
8014 23:51:02.232406 ==
8015 23:51:02.235102 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 23:51:02.239532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 23:51:02.239628 ==
8018 23:51:02.241607 Write leveling (Byte 0): 34 => 34
8019 23:51:02.245192 Write leveling (Byte 1): 25 => 25
8020 23:51:02.248408 DramcWriteLeveling(PI) end<-----
8021 23:51:02.248511
8022 23:51:02.248592 ==
8023 23:51:02.251513 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:51:02.255060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 23:51:02.258210 ==
8026 23:51:02.258391 [Gating] SW mode calibration
8027 23:51:02.267990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 23:51:02.271520 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 23:51:02.274746 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 23:51:02.281073 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 23:51:02.284897 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8032 23:51:02.287933 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8033 23:51:02.294640 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8034 23:51:02.297802 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8035 23:51:02.301897 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 23:51:02.307936 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 23:51:02.310925 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 23:51:02.314241 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8039 23:51:02.320635 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8040 23:51:02.324060 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8041 23:51:02.327356 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8042 23:51:02.333750 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8043 23:51:02.337240 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 23:51:02.340526 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 23:51:02.347365 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 23:51:02.350518 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 23:51:02.353752 1 6 8 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
8048 23:51:02.360496 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8049 23:51:02.364020 1 6 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8050 23:51:02.366649 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8051 23:51:02.373255 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 23:51:02.376330 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 23:51:02.380433 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 23:51:02.386177 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8055 23:51:02.389388 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 23:51:02.393054 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8057 23:51:02.399350 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 23:51:02.402712 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8059 23:51:02.406489 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:51:02.412703 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:51:02.415810 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:51:02.422250 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:51:02.425713 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:51:02.429133 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 23:51:02.435473 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:51:02.438929 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 23:51:02.441941 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:51:02.448344 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:51:02.452223 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:51:02.455811 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 23:51:02.463035 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8072 23:51:02.465459 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8073 23:51:02.468557 Total UI for P1: 0, mck2ui 16
8074 23:51:02.471859 best dqsien dly found for B0: ( 1, 9, 6)
8075 23:51:02.475633 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 23:51:02.481468 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8077 23:51:02.484919 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 23:51:02.487979 Total UI for P1: 0, mck2ui 16
8079 23:51:02.491389 best dqsien dly found for B1: ( 1, 9, 18)
8080 23:51:02.494711 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8081 23:51:02.498134 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8082 23:51:02.498249
8083 23:51:02.501485 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8084 23:51:02.504556 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8085 23:51:02.508063 [Gating] SW calibration Done
8086 23:51:02.508147 ==
8087 23:51:02.511346 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 23:51:02.514602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 23:51:02.518130 ==
8090 23:51:02.518228 RX Vref Scan: 0
8091 23:51:02.518305
8092 23:51:02.521113 RX Vref 0 -> 0, step: 1
8093 23:51:02.521297
8094 23:51:02.521396 RX Delay 0 -> 252, step: 8
8095 23:51:02.528131 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8096 23:51:02.531354 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8097 23:51:02.534589 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8098 23:51:02.538167 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8099 23:51:02.544523 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8100 23:51:02.547965 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8101 23:51:02.550960 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8102 23:51:02.554161 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8103 23:51:02.557628 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8104 23:51:02.564175 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8105 23:51:02.567572 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8106 23:51:02.571035 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8107 23:51:02.574074 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8108 23:51:02.577503 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8109 23:51:02.584365 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8110 23:51:02.587769 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8111 23:51:02.588297 ==
8112 23:51:02.591004 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 23:51:02.594523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 23:51:02.595118 ==
8115 23:51:02.597711 DQS Delay:
8116 23:51:02.598134 DQS0 = 0, DQS1 = 0
8117 23:51:02.600525 DQM Delay:
8118 23:51:02.600947 DQM0 = 132, DQM1 = 127
8119 23:51:02.601329 DQ Delay:
8120 23:51:02.603654 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8121 23:51:02.610798 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8122 23:51:02.614361 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8123 23:51:02.617041 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8124 23:51:02.617509
8125 23:51:02.617849
8126 23:51:02.618164 ==
8127 23:51:02.620546 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 23:51:02.623516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 23:51:02.623945 ==
8130 23:51:02.624280
8131 23:51:02.624590
8132 23:51:02.626844 TX Vref Scan disable
8133 23:51:02.630416 == TX Byte 0 ==
8134 23:51:02.633394 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8135 23:51:02.636453 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8136 23:51:02.639965 == TX Byte 1 ==
8137 23:51:02.643059 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8138 23:51:02.646831 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8139 23:51:02.647258 ==
8140 23:51:02.649986 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 23:51:02.656904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 23:51:02.657473 ==
8143 23:51:02.670788
8144 23:51:02.673957 TX Vref early break, caculate TX vref
8145 23:51:02.676717 TX Vref=16, minBit 1, minWin=23, winSum=380
8146 23:51:02.680026 TX Vref=18, minBit 1, minWin=24, winSum=389
8147 23:51:02.683282 TX Vref=20, minBit 2, minWin=24, winSum=395
8148 23:51:02.687008 TX Vref=22, minBit 0, minWin=25, winSum=403
8149 23:51:02.690699 TX Vref=24, minBit 1, minWin=25, winSum=409
8150 23:51:02.696810 TX Vref=26, minBit 3, minWin=25, winSum=415
8151 23:51:02.699511 TX Vref=28, minBit 1, minWin=25, winSum=415
8152 23:51:02.703320 TX Vref=30, minBit 2, minWin=25, winSum=412
8153 23:51:02.706467 TX Vref=32, minBit 1, minWin=24, winSum=400
8154 23:51:02.709733 TX Vref=34, minBit 1, minWin=24, winSum=394
8155 23:51:02.716292 TX Vref=36, minBit 5, minWin=23, winSum=384
8156 23:51:02.719399 [TxChooseVref] Worse bit 3, Min win 25, Win sum 415, Final Vref 26
8157 23:51:02.719828
8158 23:51:02.722847 Final TX Range 0 Vref 26
8159 23:51:02.723272
8160 23:51:02.723607 ==
8161 23:51:02.725822 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 23:51:02.729477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 23:51:02.732675 ==
8164 23:51:02.733134
8165 23:51:02.733528
8166 23:51:02.733924 TX Vref Scan disable
8167 23:51:02.739242 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8168 23:51:02.739668 == TX Byte 0 ==
8169 23:51:02.742955 u2DelayCellOfst[0]=14 cells (4 PI)
8170 23:51:02.746266 u2DelayCellOfst[1]=17 cells (5 PI)
8171 23:51:02.749591 u2DelayCellOfst[2]=10 cells (3 PI)
8172 23:51:02.752744 u2DelayCellOfst[3]=10 cells (3 PI)
8173 23:51:02.756392 u2DelayCellOfst[4]=10 cells (3 PI)
8174 23:51:02.759626 u2DelayCellOfst[5]=0 cells (0 PI)
8175 23:51:02.762646 u2DelayCellOfst[6]=17 cells (5 PI)
8176 23:51:02.766049 u2DelayCellOfst[7]=17 cells (5 PI)
8177 23:51:02.769836 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8178 23:51:02.772743 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8179 23:51:02.776241 == TX Byte 1 ==
8180 23:51:02.779221 u2DelayCellOfst[8]=0 cells (0 PI)
8181 23:51:02.782519 u2DelayCellOfst[9]=0 cells (0 PI)
8182 23:51:02.785595 u2DelayCellOfst[10]=3 cells (1 PI)
8183 23:51:02.789035 u2DelayCellOfst[11]=0 cells (0 PI)
8184 23:51:02.792360 u2DelayCellOfst[12]=7 cells (2 PI)
8185 23:51:02.792786 u2DelayCellOfst[13]=7 cells (2 PI)
8186 23:51:02.795726 u2DelayCellOfst[14]=14 cells (4 PI)
8187 23:51:02.798670 u2DelayCellOfst[15]=10 cells (3 PI)
8188 23:51:02.805934 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8189 23:51:02.808730 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8190 23:51:02.812126 DramC Write-DBI on
8191 23:51:02.812649 ==
8192 23:51:02.815736 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 23:51:02.818598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 23:51:02.819028 ==
8195 23:51:02.819364
8196 23:51:02.819679
8197 23:51:02.822118 TX Vref Scan disable
8198 23:51:02.822642 == TX Byte 0 ==
8199 23:51:02.828486 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8200 23:51:02.829012 == TX Byte 1 ==
8201 23:51:02.832208 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8202 23:51:02.835084 DramC Write-DBI off
8203 23:51:02.835512
8204 23:51:02.835893 [DATLAT]
8205 23:51:02.838271 Freq=1600, CH0 RK1
8206 23:51:02.838891
8207 23:51:02.839319 DATLAT Default: 0xf
8208 23:51:02.841530 0, 0xFFFF, sum = 0
8209 23:51:02.842122 1, 0xFFFF, sum = 0
8210 23:51:02.844840 2, 0xFFFF, sum = 0
8211 23:51:02.848089 3, 0xFFFF, sum = 0
8212 23:51:02.848606 4, 0xFFFF, sum = 0
8213 23:51:02.851772 5, 0xFFFF, sum = 0
8214 23:51:02.852208 6, 0xFFFF, sum = 0
8215 23:51:02.854820 7, 0xFFFF, sum = 0
8216 23:51:02.855254 8, 0xFFFF, sum = 0
8217 23:51:02.858390 9, 0xFFFF, sum = 0
8218 23:51:02.858826 10, 0xFFFF, sum = 0
8219 23:51:02.861195 11, 0xFFFF, sum = 0
8220 23:51:02.861667 12, 0xFFFF, sum = 0
8221 23:51:02.864999 13, 0xFFFF, sum = 0
8222 23:51:02.865474 14, 0x0, sum = 1
8223 23:51:02.868283 15, 0x0, sum = 2
8224 23:51:02.868760 16, 0x0, sum = 3
8225 23:51:02.872047 17, 0x0, sum = 4
8226 23:51:02.872483 best_step = 15
8227 23:51:02.872820
8228 23:51:02.873132 ==
8229 23:51:02.874916 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 23:51:02.881533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 23:51:02.881961 ==
8232 23:51:02.882299 RX Vref Scan: 0
8233 23:51:02.882617
8234 23:51:02.885394 RX Vref 0 -> 0, step: 1
8235 23:51:02.885914
8236 23:51:02.887845 RX Delay 11 -> 252, step: 4
8237 23:51:02.891446 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8238 23:51:02.895163 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8239 23:51:02.897708 iDelay=187, Bit 2, Center 122 (71 ~ 174) 104
8240 23:51:02.904209 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8241 23:51:02.908163 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8242 23:51:02.911043 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8243 23:51:02.914125 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8244 23:51:02.920799 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8245 23:51:02.923857 iDelay=187, Bit 8, Center 112 (59 ~ 166) 108
8246 23:51:02.927501 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8247 23:51:02.930358 iDelay=187, Bit 10, Center 126 (75 ~ 178) 104
8248 23:51:02.933552 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8249 23:51:02.941309 iDelay=187, Bit 12, Center 128 (75 ~ 182) 108
8250 23:51:02.943575 iDelay=187, Bit 13, Center 128 (79 ~ 178) 100
8251 23:51:02.947558 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8252 23:51:02.950014 iDelay=187, Bit 15, Center 130 (79 ~ 182) 104
8253 23:51:02.950489 ==
8254 23:51:02.953951 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 23:51:02.960661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 23:51:02.961345 ==
8257 23:51:02.961863 DQS Delay:
8258 23:51:02.963295 DQS0 = 0, DQS1 = 0
8259 23:51:02.963763 DQM Delay:
8260 23:51:02.966680 DQM0 = 128, DQM1 = 123
8261 23:51:02.967149 DQ Delay:
8262 23:51:02.970188 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8263 23:51:02.973354 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
8264 23:51:02.976553 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =118
8265 23:51:02.979462 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8266 23:51:02.979935
8267 23:51:02.980306
8268 23:51:02.980649
8269 23:51:02.983441 [DramC_TX_OE_Calibration] TA2
8270 23:51:02.986173 Original DQ_B0 (3 6) =30, OEN = 27
8271 23:51:02.989844 Original DQ_B1 (3 6) =30, OEN = 27
8272 23:51:02.992959 24, 0x0, End_B0=24 End_B1=24
8273 23:51:02.996396 25, 0x0, End_B0=25 End_B1=25
8274 23:51:02.996834 26, 0x0, End_B0=26 End_B1=26
8275 23:51:02.999275 27, 0x0, End_B0=27 End_B1=27
8276 23:51:03.002657 28, 0x0, End_B0=28 End_B1=28
8277 23:51:03.006612 29, 0x0, End_B0=29 End_B1=29
8278 23:51:03.009249 30, 0x0, End_B0=30 End_B1=30
8279 23:51:03.009730 31, 0x4141, End_B0=30 End_B1=30
8280 23:51:03.013375 Byte0 end_step=30 best_step=27
8281 23:51:03.016078 Byte1 end_step=30 best_step=27
8282 23:51:03.019434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8283 23:51:03.023221 Byte1 TX OE(2T, 0.5T) = (3, 3)
8284 23:51:03.023746
8285 23:51:03.024087
8286 23:51:03.029377 [DQSOSCAuto] RK1, (LSB)MR18= 0x1716, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
8287 23:51:03.032565 CH0 RK1: MR19=303, MR18=1716
8288 23:51:03.038836 CH0_RK1: MR19=0x303, MR18=0x1716, DQSOSC=398, MR23=63, INC=23, DEC=15
8289 23:51:03.042763 [RxdqsGatingPostProcess] freq 1600
8290 23:51:03.048898 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8291 23:51:03.052132 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 23:51:03.052655 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 23:51:03.055873 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 23:51:03.058938 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 23:51:03.062165 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 23:51:03.065654 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 23:51:03.068841 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 23:51:03.072895 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 23:51:03.075281 Pre-setting of DQS Precalculation
8300 23:51:03.078403 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8301 23:51:03.082110 ==
8302 23:51:03.085359 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 23:51:03.088519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 23:51:03.089050 ==
8305 23:51:03.095294 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 23:51:03.098177 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 23:51:03.101440 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 23:51:03.108270 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 23:51:03.116641 [CA 0] Center 42 (12~72) winsize 61
8310 23:51:03.119985 [CA 1] Center 42 (12~72) winsize 61
8311 23:51:03.123221 [CA 2] Center 38 (9~67) winsize 59
8312 23:51:03.126708 [CA 3] Center 37 (8~66) winsize 59
8313 23:51:03.130382 [CA 4] Center 37 (7~68) winsize 62
8314 23:51:03.133316 [CA 5] Center 36 (7~66) winsize 60
8315 23:51:03.133796
8316 23:51:03.136970 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8317 23:51:03.137601
8318 23:51:03.143019 [CATrainingPosCal] consider 1 rank data
8319 23:51:03.143583 u2DelayCellTimex100 = 275/100 ps
8320 23:51:03.149735 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8321 23:51:03.152502 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8322 23:51:03.156326 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8323 23:51:03.159723 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8324 23:51:03.162893 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8325 23:51:03.165837 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 23:51:03.166329
8327 23:51:03.169741 CA PerBit enable=1, Macro0, CA PI delay=36
8328 23:51:03.170175
8329 23:51:03.172403 [CBTSetCACLKResult] CA Dly = 36
8330 23:51:03.176322 CS Dly: 8 (0~39)
8331 23:51:03.179530 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 23:51:03.182740 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 23:51:03.183173 ==
8334 23:51:03.185727 Dram Type= 6, Freq= 0, CH_1, rank 1
8335 23:51:03.192627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 23:51:03.193179 ==
8337 23:51:03.196071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 23:51:03.202157 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 23:51:03.205624 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 23:51:03.212241 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 23:51:03.219963 [CA 0] Center 41 (11~71) winsize 61
8342 23:51:03.223030 [CA 1] Center 41 (12~71) winsize 60
8343 23:51:03.226486 [CA 2] Center 37 (8~67) winsize 60
8344 23:51:03.229617 [CA 3] Center 36 (7~65) winsize 59
8345 23:51:03.232583 [CA 4] Center 37 (7~67) winsize 61
8346 23:51:03.236183 [CA 5] Center 36 (7~66) winsize 60
8347 23:51:03.236615
8348 23:51:03.239557 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8349 23:51:03.239991
8350 23:51:03.246075 [CATrainingPosCal] consider 2 rank data
8351 23:51:03.246605 u2DelayCellTimex100 = 275/100 ps
8352 23:51:03.253106 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8353 23:51:03.256018 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8354 23:51:03.259281 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8355 23:51:03.262764 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8356 23:51:03.265865 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8357 23:51:03.268910 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 23:51:03.269410
8359 23:51:03.272162 CA PerBit enable=1, Macro0, CA PI delay=36
8360 23:51:03.272596
8361 23:51:03.275424 [CBTSetCACLKResult] CA Dly = 36
8362 23:51:03.278887 CS Dly: 9 (0~42)
8363 23:51:03.282180 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 23:51:03.285550 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 23:51:03.286048
8366 23:51:03.288661 ----->DramcWriteLeveling(PI) begin...
8367 23:51:03.289156 ==
8368 23:51:03.291859 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 23:51:03.298819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 23:51:03.299136 ==
8371 23:51:03.301668 Write leveling (Byte 0): 24 => 24
8372 23:51:03.305458 Write leveling (Byte 1): 27 => 27
8373 23:51:03.308534 DramcWriteLeveling(PI) end<-----
8374 23:51:03.308847
8375 23:51:03.309032 ==
8376 23:51:03.311934 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 23:51:03.314675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 23:51:03.314904 ==
8379 23:51:03.318117 [Gating] SW mode calibration
8380 23:51:03.324706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8381 23:51:03.331542 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8382 23:51:03.335052 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 23:51:03.338400 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 23:51:03.344550 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 23:51:03.347855 1 4 12 | B1->B0 | 2322 3333 | 1 0 | (0 0) (0 0)
8386 23:51:03.351192 1 4 16 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8387 23:51:03.354592 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 23:51:03.361774 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 23:51:03.364730 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 23:51:03.368432 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 23:51:03.374728 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8392 23:51:03.378421 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8393 23:51:03.381351 1 5 12 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (1 0)
8394 23:51:03.387875 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8395 23:51:03.390995 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 23:51:03.394444 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:51:03.400959 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 23:51:03.404543 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 23:51:03.407503 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 23:51:03.413782 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8401 23:51:03.417207 1 6 12 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8402 23:51:03.423754 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 23:51:03.427346 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 23:51:03.430282 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 23:51:03.437561 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:51:03.440782 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 23:51:03.444030 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 23:51:03.446908 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 23:51:03.453137 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8410 23:51:03.456742 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8411 23:51:03.463419 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:51:03.467185 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:51:03.470021 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:51:03.476546 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:51:03.480128 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:51:03.483051 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:51:03.489764 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:51:03.492608 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:51:03.496745 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:51:03.502658 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:51:03.506225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:51:03.509320 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:51:03.515819 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:51:03.519736 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8425 23:51:03.522348 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8426 23:51:03.529613 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8427 23:51:03.530146 Total UI for P1: 0, mck2ui 16
8428 23:51:03.536088 best dqsien dly found for B0: ( 1, 9, 10)
8429 23:51:03.539009 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 23:51:03.542397 Total UI for P1: 0, mck2ui 16
8431 23:51:03.545613 best dqsien dly found for B1: ( 1, 9, 16)
8432 23:51:03.549118 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8433 23:51:03.552911 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8434 23:51:03.553482
8435 23:51:03.555855 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8436 23:51:03.558721 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8437 23:51:03.562354 [Gating] SW calibration Done
8438 23:51:03.562877 ==
8439 23:51:03.565541 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 23:51:03.569229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 23:51:03.572452 ==
8442 23:51:03.572883 RX Vref Scan: 0
8443 23:51:03.573223
8444 23:51:03.575568 RX Vref 0 -> 0, step: 1
8445 23:51:03.576087
8446 23:51:03.576429 RX Delay 0 -> 252, step: 8
8447 23:51:03.582379 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8448 23:51:03.586636 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8449 23:51:03.588640 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8450 23:51:03.592323 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8451 23:51:03.595078 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8452 23:51:03.602150 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8453 23:51:03.605167 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8454 23:51:03.609002 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8455 23:51:03.612552 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8456 23:51:03.615676 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8457 23:51:03.621803 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8458 23:51:03.625025 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8459 23:51:03.629052 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8460 23:51:03.631386 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8461 23:51:03.638343 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8462 23:51:03.642440 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8463 23:51:03.643063 ==
8464 23:51:03.645033 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 23:51:03.648283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 23:51:03.648880 ==
8467 23:51:03.651156 DQS Delay:
8468 23:51:03.651808 DQS0 = 0, DQS1 = 0
8469 23:51:03.652297 DQM Delay:
8470 23:51:03.654086 DQM0 = 134, DQM1 = 131
8471 23:51:03.654564 DQ Delay:
8472 23:51:03.657725 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8473 23:51:03.661078 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8474 23:51:03.667660 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8475 23:51:03.670718 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8476 23:51:03.671142
8477 23:51:03.671479
8478 23:51:03.671790 ==
8479 23:51:03.674484 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 23:51:03.677544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 23:51:03.677972 ==
8482 23:51:03.678308
8483 23:51:03.678615
8484 23:51:03.680831 TX Vref Scan disable
8485 23:51:03.684098 == TX Byte 0 ==
8486 23:51:03.687474 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8487 23:51:03.691038 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8488 23:51:03.694033 == TX Byte 1 ==
8489 23:51:03.697229 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8490 23:51:03.700879 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8491 23:51:03.701463 ==
8492 23:51:03.704023 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 23:51:03.710946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 23:51:03.711487 ==
8495 23:51:03.723517
8496 23:51:03.726147 TX Vref early break, caculate TX vref
8497 23:51:03.729669 TX Vref=16, minBit 8, minWin=21, winSum=364
8498 23:51:03.733012 TX Vref=18, minBit 9, minWin=22, winSum=378
8499 23:51:03.736178 TX Vref=20, minBit 8, minWin=23, winSum=389
8500 23:51:03.739568 TX Vref=22, minBit 8, minWin=23, winSum=396
8501 23:51:03.742736 TX Vref=24, minBit 8, minWin=24, winSum=407
8502 23:51:03.749124 TX Vref=26, minBit 8, minWin=24, winSum=412
8503 23:51:03.752576 TX Vref=28, minBit 0, minWin=25, winSum=418
8504 23:51:03.755790 TX Vref=30, minBit 0, minWin=25, winSum=416
8505 23:51:03.759303 TX Vref=32, minBit 0, minWin=24, winSum=402
8506 23:51:03.762855 TX Vref=34, minBit 0, minWin=24, winSum=397
8507 23:51:03.766001 TX Vref=36, minBit 0, minWin=23, winSum=382
8508 23:51:03.772507 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8509 23:51:03.773045
8510 23:51:03.775820 Final TX Range 0 Vref 28
8511 23:51:03.776351
8512 23:51:03.776802 ==
8513 23:51:03.779050 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 23:51:03.782515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 23:51:03.783069 ==
8516 23:51:03.785897
8517 23:51:03.786437
8518 23:51:03.786881 TX Vref Scan disable
8519 23:51:03.792450 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8520 23:51:03.792999 == TX Byte 0 ==
8521 23:51:03.795597 u2DelayCellOfst[0]=17 cells (5 PI)
8522 23:51:03.798749 u2DelayCellOfst[1]=10 cells (3 PI)
8523 23:51:03.802082 u2DelayCellOfst[2]=0 cells (0 PI)
8524 23:51:03.805840 u2DelayCellOfst[3]=7 cells (2 PI)
8525 23:51:03.809096 u2DelayCellOfst[4]=10 cells (3 PI)
8526 23:51:03.811963 u2DelayCellOfst[5]=17 cells (5 PI)
8527 23:51:03.816095 u2DelayCellOfst[6]=17 cells (5 PI)
8528 23:51:03.818270 u2DelayCellOfst[7]=7 cells (2 PI)
8529 23:51:03.821728 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8530 23:51:03.824956 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8531 23:51:03.828835 == TX Byte 1 ==
8532 23:51:03.831434 u2DelayCellOfst[8]=0 cells (0 PI)
8533 23:51:03.835197 u2DelayCellOfst[9]=3 cells (1 PI)
8534 23:51:03.838315 u2DelayCellOfst[10]=10 cells (3 PI)
8535 23:51:03.841379 u2DelayCellOfst[11]=7 cells (2 PI)
8536 23:51:03.845228 u2DelayCellOfst[12]=17 cells (5 PI)
8537 23:51:03.847840 u2DelayCellOfst[13]=17 cells (5 PI)
8538 23:51:03.851436 u2DelayCellOfst[14]=17 cells (5 PI)
8539 23:51:03.854831 u2DelayCellOfst[15]=17 cells (5 PI)
8540 23:51:03.857918 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8541 23:51:03.861693 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8542 23:51:03.864797 DramC Write-DBI on
8543 23:51:03.865224 ==
8544 23:51:03.867988 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 23:51:03.870902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 23:51:03.871342 ==
8547 23:51:03.871776
8548 23:51:03.872184
8549 23:51:03.874106 TX Vref Scan disable
8550 23:51:03.874536 == TX Byte 0 ==
8551 23:51:03.881324 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8552 23:51:03.881870 == TX Byte 1 ==
8553 23:51:03.887718 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8554 23:51:03.888258 DramC Write-DBI off
8555 23:51:03.888702
8556 23:51:03.889111 [DATLAT]
8557 23:51:03.890949 Freq=1600, CH1 RK0
8558 23:51:03.891383
8559 23:51:03.894468 DATLAT Default: 0xf
8560 23:51:03.895007 0, 0xFFFF, sum = 0
8561 23:51:03.897652 1, 0xFFFF, sum = 0
8562 23:51:03.898202 2, 0xFFFF, sum = 0
8563 23:51:03.900831 3, 0xFFFF, sum = 0
8564 23:51:03.901420 4, 0xFFFF, sum = 0
8565 23:51:03.903972 5, 0xFFFF, sum = 0
8566 23:51:03.904419 6, 0xFFFF, sum = 0
8567 23:51:03.907490 7, 0xFFFF, sum = 0
8568 23:51:03.908011 8, 0xFFFF, sum = 0
8569 23:51:03.910543 9, 0xFFFF, sum = 0
8570 23:51:03.910968 10, 0xFFFF, sum = 0
8571 23:51:03.914088 11, 0xFFFF, sum = 0
8572 23:51:03.914512 12, 0xFFFF, sum = 0
8573 23:51:03.917007 13, 0xFFFF, sum = 0
8574 23:51:03.917472 14, 0x0, sum = 1
8575 23:51:03.920818 15, 0x0, sum = 2
8576 23:51:03.921393 16, 0x0, sum = 3
8577 23:51:03.923786 17, 0x0, sum = 4
8578 23:51:03.924319 best_step = 15
8579 23:51:03.924656
8580 23:51:03.924964 ==
8581 23:51:03.927328 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 23:51:03.933712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 23:51:03.934135 ==
8584 23:51:03.934468 RX Vref Scan: 1
8585 23:51:03.934775
8586 23:51:03.937231 Set Vref Range= 24 -> 127
8587 23:51:03.937724
8588 23:51:03.940399 RX Vref 24 -> 127, step: 1
8589 23:51:03.940832
8590 23:51:03.943360 RX Delay 19 -> 252, step: 4
8591 23:51:03.943794
8592 23:51:03.946509 Set Vref, RX VrefLevel [Byte0]: 24
8593 23:51:03.950032 [Byte1]: 24
8594 23:51:03.950465
8595 23:51:03.953227 Set Vref, RX VrefLevel [Byte0]: 25
8596 23:51:03.956191 [Byte1]: 25
8597 23:51:03.956623
8598 23:51:03.959438 Set Vref, RX VrefLevel [Byte0]: 26
8599 23:51:03.963085 [Byte1]: 26
8600 23:51:03.966283
8601 23:51:03.966709 Set Vref, RX VrefLevel [Byte0]: 27
8602 23:51:03.969352 [Byte1]: 27
8603 23:51:03.973860
8604 23:51:03.974285 Set Vref, RX VrefLevel [Byte0]: 28
8605 23:51:03.977420 [Byte1]: 28
8606 23:51:03.981523
8607 23:51:03.981946 Set Vref, RX VrefLevel [Byte0]: 29
8608 23:51:03.984545 [Byte1]: 29
8609 23:51:03.989902
8610 23:51:03.990434 Set Vref, RX VrefLevel [Byte0]: 30
8611 23:51:03.992437 [Byte1]: 30
8612 23:51:03.996574
8613 23:51:03.997002 Set Vref, RX VrefLevel [Byte0]: 31
8614 23:51:04.000204 [Byte1]: 31
8615 23:51:04.004707
8616 23:51:04.005132 Set Vref, RX VrefLevel [Byte0]: 32
8617 23:51:04.008154 [Byte1]: 32
8618 23:51:04.011778
8619 23:51:04.012201 Set Vref, RX VrefLevel [Byte0]: 33
8620 23:51:04.015069 [Byte1]: 33
8621 23:51:04.019208
8622 23:51:04.019631 Set Vref, RX VrefLevel [Byte0]: 34
8623 23:51:04.022944 [Byte1]: 34
8624 23:51:04.026975
8625 23:51:04.027504 Set Vref, RX VrefLevel [Byte0]: 35
8626 23:51:04.031151 [Byte1]: 35
8627 23:51:04.034863
8628 23:51:04.035424 Set Vref, RX VrefLevel [Byte0]: 36
8629 23:51:04.038045 [Byte1]: 36
8630 23:51:04.042162
8631 23:51:04.042621 Set Vref, RX VrefLevel [Byte0]: 37
8632 23:51:04.045553 [Byte1]: 37
8633 23:51:04.049714
8634 23:51:04.050130 Set Vref, RX VrefLevel [Byte0]: 38
8635 23:51:04.053198 [Byte1]: 38
8636 23:51:04.057722
8637 23:51:04.058149 Set Vref, RX VrefLevel [Byte0]: 39
8638 23:51:04.060448 [Byte1]: 39
8639 23:51:04.065065
8640 23:51:04.065629 Set Vref, RX VrefLevel [Byte0]: 40
8641 23:51:04.068527 [Byte1]: 40
8642 23:51:04.072290
8643 23:51:04.072705 Set Vref, RX VrefLevel [Byte0]: 41
8644 23:51:04.075650 [Byte1]: 41
8645 23:51:04.079866
8646 23:51:04.080406 Set Vref, RX VrefLevel [Byte0]: 42
8647 23:51:04.082989 [Byte1]: 42
8648 23:51:04.087588
8649 23:51:04.088103 Set Vref, RX VrefLevel [Byte0]: 43
8650 23:51:04.090522 [Byte1]: 43
8651 23:51:04.095331
8652 23:51:04.095745 Set Vref, RX VrefLevel [Byte0]: 44
8653 23:51:04.098282 [Byte1]: 44
8654 23:51:04.103174
8655 23:51:04.103700 Set Vref, RX VrefLevel [Byte0]: 45
8656 23:51:04.106038 [Byte1]: 45
8657 23:51:04.110116
8658 23:51:04.110656 Set Vref, RX VrefLevel [Byte0]: 46
8659 23:51:04.113377 [Byte1]: 46
8660 23:51:04.117640
8661 23:51:04.118054 Set Vref, RX VrefLevel [Byte0]: 47
8662 23:51:04.120931 [Byte1]: 47
8663 23:51:04.125419
8664 23:51:04.125919 Set Vref, RX VrefLevel [Byte0]: 48
8665 23:51:04.128912 [Byte1]: 48
8666 23:51:04.133013
8667 23:51:04.133633 Set Vref, RX VrefLevel [Byte0]: 49
8668 23:51:04.136112 [Byte1]: 49
8669 23:51:04.141346
8670 23:51:04.141852 Set Vref, RX VrefLevel [Byte0]: 50
8671 23:51:04.143467 [Byte1]: 50
8672 23:51:04.147968
8673 23:51:04.148385 Set Vref, RX VrefLevel [Byte0]: 51
8674 23:51:04.151986 [Byte1]: 51
8675 23:51:04.155807
8676 23:51:04.156223 Set Vref, RX VrefLevel [Byte0]: 52
8677 23:51:04.159683 [Byte1]: 52
8678 23:51:04.163385
8679 23:51:04.163932 Set Vref, RX VrefLevel [Byte0]: 53
8680 23:51:04.166995 [Byte1]: 53
8681 23:51:04.170825
8682 23:51:04.171302 Set Vref, RX VrefLevel [Byte0]: 54
8683 23:51:04.174859 [Byte1]: 54
8684 23:51:04.178418
8685 23:51:04.178946 Set Vref, RX VrefLevel [Byte0]: 55
8686 23:51:04.181616 [Byte1]: 55
8687 23:51:04.186009
8688 23:51:04.186424 Set Vref, RX VrefLevel [Byte0]: 56
8689 23:51:04.189280 [Byte1]: 56
8690 23:51:04.193502
8691 23:51:04.193918 Set Vref, RX VrefLevel [Byte0]: 57
8692 23:51:04.196628 [Byte1]: 57
8693 23:51:04.201658
8694 23:51:04.202180 Set Vref, RX VrefLevel [Byte0]: 58
8695 23:51:04.204359 [Byte1]: 58
8696 23:51:04.208947
8697 23:51:04.209397 Set Vref, RX VrefLevel [Byte0]: 59
8698 23:51:04.212698 [Byte1]: 59
8699 23:51:04.216446
8700 23:51:04.216863 Set Vref, RX VrefLevel [Byte0]: 60
8701 23:51:04.219323 [Byte1]: 60
8702 23:51:04.223652
8703 23:51:04.224068 Set Vref, RX VrefLevel [Byte0]: 61
8704 23:51:04.227287 [Byte1]: 61
8705 23:51:04.231848
8706 23:51:04.232271 Set Vref, RX VrefLevel [Byte0]: 62
8707 23:51:04.234917 [Byte1]: 62
8708 23:51:04.238820
8709 23:51:04.239295 Set Vref, RX VrefLevel [Byte0]: 63
8710 23:51:04.242740 [Byte1]: 63
8711 23:51:04.246527
8712 23:51:04.246950 Set Vref, RX VrefLevel [Byte0]: 64
8713 23:51:04.249793 [Byte1]: 64
8714 23:51:04.254337
8715 23:51:04.254763 Set Vref, RX VrefLevel [Byte0]: 65
8716 23:51:04.257484 [Byte1]: 65
8717 23:51:04.262530
8718 23:51:04.263061 Set Vref, RX VrefLevel [Byte0]: 66
8719 23:51:04.265431 [Byte1]: 66
8720 23:51:04.269372
8721 23:51:04.269794 Set Vref, RX VrefLevel [Byte0]: 67
8722 23:51:04.273082 [Byte1]: 67
8723 23:51:04.277096
8724 23:51:04.277669 Set Vref, RX VrefLevel [Byte0]: 68
8725 23:51:04.280498 [Byte1]: 68
8726 23:51:04.285438
8727 23:51:04.286010 Set Vref, RX VrefLevel [Byte0]: 69
8728 23:51:04.287642 [Byte1]: 69
8729 23:51:04.292277
8730 23:51:04.292739 Set Vref, RX VrefLevel [Byte0]: 70
8731 23:51:04.295681 [Byte1]: 70
8732 23:51:04.300180
8733 23:51:04.300597 Final RX Vref Byte 0 = 56 to rank0
8734 23:51:04.302750 Final RX Vref Byte 1 = 54 to rank0
8735 23:51:04.305909 Final RX Vref Byte 0 = 56 to rank1
8736 23:51:04.309546 Final RX Vref Byte 1 = 54 to rank1==
8737 23:51:04.312970 Dram Type= 6, Freq= 0, CH_1, rank 0
8738 23:51:04.319694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 23:51:04.320242 ==
8740 23:51:04.320587 DQS Delay:
8741 23:51:04.322364 DQS0 = 0, DQS1 = 0
8742 23:51:04.322814 DQM Delay:
8743 23:51:04.323143 DQM0 = 133, DQM1 = 130
8744 23:51:04.325864 DQ Delay:
8745 23:51:04.329230 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =132
8746 23:51:04.332576 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =128
8747 23:51:04.336167 DQ8 =114, DQ9 =118, DQ10 =132, DQ11 =124
8748 23:51:04.339716 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8749 23:51:04.340239
8750 23:51:04.340576
8751 23:51:04.340880
8752 23:51:04.342725 [DramC_TX_OE_Calibration] TA2
8753 23:51:04.345614 Original DQ_B0 (3 6) =30, OEN = 27
8754 23:51:04.348929 Original DQ_B1 (3 6) =30, OEN = 27
8755 23:51:04.352804 24, 0x0, End_B0=24 End_B1=24
8756 23:51:04.355649 25, 0x0, End_B0=25 End_B1=25
8757 23:51:04.356179 26, 0x0, End_B0=26 End_B1=26
8758 23:51:04.359276 27, 0x0, End_B0=27 End_B1=27
8759 23:51:04.363406 28, 0x0, End_B0=28 End_B1=28
8760 23:51:04.365132 29, 0x0, End_B0=29 End_B1=29
8761 23:51:04.365581 30, 0x0, End_B0=30 End_B1=30
8762 23:51:04.369416 31, 0x4545, End_B0=30 End_B1=30
8763 23:51:04.372079 Byte0 end_step=30 best_step=27
8764 23:51:04.375640 Byte1 end_step=30 best_step=27
8765 23:51:04.378727 Byte0 TX OE(2T, 0.5T) = (3, 3)
8766 23:51:04.383201 Byte1 TX OE(2T, 0.5T) = (3, 3)
8767 23:51:04.383719
8768 23:51:04.384055
8769 23:51:04.388445 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8770 23:51:04.392492 CH1 RK0: MR19=303, MR18=D17
8771 23:51:04.398501 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8772 23:51:04.398919
8773 23:51:04.401623 ----->DramcWriteLeveling(PI) begin...
8774 23:51:04.402045 ==
8775 23:51:04.405167 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 23:51:04.408353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 23:51:04.408772 ==
8778 23:51:04.411575 Write leveling (Byte 0): 25 => 25
8779 23:51:04.415285 Write leveling (Byte 1): 26 => 26
8780 23:51:04.417860 DramcWriteLeveling(PI) end<-----
8781 23:51:04.418284
8782 23:51:04.418618 ==
8783 23:51:04.421343 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 23:51:04.424959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 23:51:04.428414 ==
8786 23:51:04.428947 [Gating] SW mode calibration
8787 23:51:04.438759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8788 23:51:04.441384 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8789 23:51:04.444873 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 23:51:04.450891 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8791 23:51:04.454159 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8792 23:51:04.458240 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8793 23:51:04.464767 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 23:51:04.467976 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 23:51:04.471027 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 23:51:04.477618 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 23:51:04.481368 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 23:51:04.484185 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8799 23:51:04.490620 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8800 23:51:04.494078 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
8801 23:51:04.497516 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 23:51:04.504957 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 23:51:04.506858 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 23:51:04.510628 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 23:51:04.516870 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 23:51:04.520298 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 23:51:04.523130 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8808 23:51:04.530015 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8809 23:51:04.532918 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 23:51:04.536342 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 23:51:04.542685 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 23:51:04.546199 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 23:51:04.552974 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 23:51:04.556163 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 23:51:04.559500 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8816 23:51:04.565857 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8817 23:51:04.570040 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8818 23:51:04.572540 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:51:04.580054 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:51:04.582402 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:51:04.585927 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:51:04.592579 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:51:04.595621 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:51:04.599333 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:51:04.605418 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:51:04.608938 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:51:04.613097 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:51:04.618665 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:51:04.622035 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:51:04.625550 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8831 23:51:04.632233 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8832 23:51:04.635293 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8833 23:51:04.638589 Total UI for P1: 0, mck2ui 16
8834 23:51:04.641786 best dqsien dly found for B0: ( 1, 9, 6)
8835 23:51:04.645142 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 23:51:04.648503 Total UI for P1: 0, mck2ui 16
8837 23:51:04.651605 best dqsien dly found for B1: ( 1, 9, 12)
8838 23:51:04.654879 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8839 23:51:04.658776 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8840 23:51:04.659198
8841 23:51:04.661479 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8842 23:51:04.668765 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8843 23:51:04.669320 [Gating] SW calibration Done
8844 23:51:04.672003 ==
8845 23:51:04.672742 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 23:51:04.678901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 23:51:04.679472 ==
8848 23:51:04.680108 RX Vref Scan: 0
8849 23:51:04.680580
8850 23:51:04.681252 RX Vref 0 -> 0, step: 1
8851 23:51:04.681648
8852 23:51:04.685165 RX Delay 0 -> 252, step: 8
8853 23:51:04.688330 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8854 23:51:04.691329 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8855 23:51:04.694654 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8856 23:51:04.701810 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8857 23:51:04.704988 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8858 23:51:04.708003 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8859 23:51:04.711202 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8860 23:51:04.714173 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8861 23:51:04.721039 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8862 23:51:04.724211 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8863 23:51:04.727664 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8864 23:51:04.730825 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8865 23:51:04.737153 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8866 23:51:04.740836 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8867 23:51:04.743867 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8868 23:51:04.747100 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8869 23:51:04.747570 ==
8870 23:51:04.750902 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 23:51:04.757359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 23:51:04.757787 ==
8873 23:51:04.758121 DQS Delay:
8874 23:51:04.758444 DQS0 = 0, DQS1 = 0
8875 23:51:04.760779 DQM Delay:
8876 23:51:04.761350 DQM0 = 136, DQM1 = 130
8877 23:51:04.764068 DQ Delay:
8878 23:51:04.767191 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =131
8879 23:51:04.770296 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8880 23:51:04.774045 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8881 23:51:04.777095 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8882 23:51:04.777677
8883 23:51:04.778015
8884 23:51:04.778324 ==
8885 23:51:04.780823 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 23:51:04.784001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 23:51:04.787077 ==
8888 23:51:04.787625
8889 23:51:04.788038
8890 23:51:04.788362 TX Vref Scan disable
8891 23:51:04.790415 == TX Byte 0 ==
8892 23:51:04.793557 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8893 23:51:04.796928 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8894 23:51:04.799607 == TX Byte 1 ==
8895 23:51:04.803599 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8896 23:51:04.809589 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 23:51:04.810103 ==
8898 23:51:04.813354 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 23:51:04.816283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 23:51:04.816710 ==
8901 23:51:04.829646
8902 23:51:04.833683 TX Vref early break, caculate TX vref
8903 23:51:04.836146 TX Vref=16, minBit 9, minWin=22, winSum=377
8904 23:51:04.839760 TX Vref=18, minBit 9, minWin=22, winSum=386
8905 23:51:04.842972 TX Vref=20, minBit 9, minWin=22, winSum=393
8906 23:51:04.846128 TX Vref=22, minBit 9, minWin=24, winSum=401
8907 23:51:04.849331 TX Vref=24, minBit 9, minWin=24, winSum=409
8908 23:51:04.856067 TX Vref=26, minBit 9, minWin=24, winSum=415
8909 23:51:04.859032 TX Vref=28, minBit 3, minWin=25, winSum=418
8910 23:51:04.862392 TX Vref=30, minBit 8, minWin=24, winSum=417
8911 23:51:04.865810 TX Vref=32, minBit 9, minWin=24, winSum=415
8912 23:51:04.868842 TX Vref=34, minBit 0, minWin=24, winSum=403
8913 23:51:04.875791 TX Vref=36, minBit 8, minWin=23, winSum=392
8914 23:51:04.879128 [TxChooseVref] Worse bit 3, Min win 25, Win sum 418, Final Vref 28
8915 23:51:04.879657
8916 23:51:04.882248 Final TX Range 0 Vref 28
8917 23:51:04.882670
8918 23:51:04.883002 ==
8919 23:51:04.885324 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 23:51:04.888818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 23:51:04.893232 ==
8922 23:51:04.893777
8923 23:51:04.894106
8924 23:51:04.894415 TX Vref Scan disable
8925 23:51:04.898538 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8926 23:51:04.898961 == TX Byte 0 ==
8927 23:51:04.901909 u2DelayCellOfst[0]=14 cells (4 PI)
8928 23:51:04.905864 u2DelayCellOfst[1]=10 cells (3 PI)
8929 23:51:04.908455 u2DelayCellOfst[2]=0 cells (0 PI)
8930 23:51:04.912284 u2DelayCellOfst[3]=7 cells (2 PI)
8931 23:51:04.915585 u2DelayCellOfst[4]=7 cells (2 PI)
8932 23:51:04.918900 u2DelayCellOfst[5]=17 cells (5 PI)
8933 23:51:04.921965 u2DelayCellOfst[6]=17 cells (5 PI)
8934 23:51:04.925176 u2DelayCellOfst[7]=3 cells (1 PI)
8935 23:51:04.928923 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8936 23:51:04.931985 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8937 23:51:04.935195 == TX Byte 1 ==
8938 23:51:04.938575 u2DelayCellOfst[8]=0 cells (0 PI)
8939 23:51:04.941912 u2DelayCellOfst[9]=7 cells (2 PI)
8940 23:51:04.945164 u2DelayCellOfst[10]=14 cells (4 PI)
8941 23:51:04.948236 u2DelayCellOfst[11]=7 cells (2 PI)
8942 23:51:04.951718 u2DelayCellOfst[12]=17 cells (5 PI)
8943 23:51:04.954575 u2DelayCellOfst[13]=21 cells (6 PI)
8944 23:51:04.958653 u2DelayCellOfst[14]=21 cells (6 PI)
8945 23:51:04.959241 u2DelayCellOfst[15]=21 cells (6 PI)
8946 23:51:04.964925 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8947 23:51:04.968218 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8948 23:51:04.971641 DramC Write-DBI on
8949 23:51:04.972109 ==
8950 23:51:04.974331 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 23:51:04.978398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 23:51:04.978921 ==
8953 23:51:04.979258
8954 23:51:04.979567
8955 23:51:04.981356 TX Vref Scan disable
8956 23:51:04.981868 == TX Byte 0 ==
8957 23:51:04.988109 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8958 23:51:04.988640 == TX Byte 1 ==
8959 23:51:04.991011 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8960 23:51:04.994384 DramC Write-DBI off
8961 23:51:04.994907
8962 23:51:04.995283 [DATLAT]
8963 23:51:04.997878 Freq=1600, CH1 RK1
8964 23:51:04.998299
8965 23:51:04.998628 DATLAT Default: 0xf
8966 23:51:05.001162 0, 0xFFFF, sum = 0
8967 23:51:05.001622 1, 0xFFFF, sum = 0
8968 23:51:05.004912 2, 0xFFFF, sum = 0
8969 23:51:05.007525 3, 0xFFFF, sum = 0
8970 23:51:05.008044 4, 0xFFFF, sum = 0
8971 23:51:05.010604 5, 0xFFFF, sum = 0
8972 23:51:05.011069 6, 0xFFFF, sum = 0
8973 23:51:05.014716 7, 0xFFFF, sum = 0
8974 23:51:05.015244 8, 0xFFFF, sum = 0
8975 23:51:05.017438 9, 0xFFFF, sum = 0
8976 23:51:05.017867 10, 0xFFFF, sum = 0
8977 23:51:05.020545 11, 0xFFFF, sum = 0
8978 23:51:05.020973 12, 0xFFFF, sum = 0
8979 23:51:05.024141 13, 0xFFFF, sum = 0
8980 23:51:05.024666 14, 0x0, sum = 1
8981 23:51:05.027560 15, 0x0, sum = 2
8982 23:51:05.028084 16, 0x0, sum = 3
8983 23:51:05.030953 17, 0x0, sum = 4
8984 23:51:05.031473 best_step = 15
8985 23:51:05.031806
8986 23:51:05.032116 ==
8987 23:51:05.033983 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 23:51:05.040695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 23:51:05.041320 ==
8990 23:51:05.041830 RX Vref Scan: 0
8991 23:51:05.042169
8992 23:51:05.043862 RX Vref 0 -> 0, step: 1
8993 23:51:05.044281
8994 23:51:05.047127 RX Delay 11 -> 252, step: 4
8995 23:51:05.050647 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8996 23:51:05.053705 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8997 23:51:05.060372 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8998 23:51:05.063601 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8999 23:51:05.067396 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
9000 23:51:05.070317 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9001 23:51:05.073548 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9002 23:51:05.080235 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
9003 23:51:05.083416 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9004 23:51:05.086335 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
9005 23:51:05.090036 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9006 23:51:05.093443 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9007 23:51:05.100082 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9008 23:51:05.103202 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9009 23:51:05.106377 iDelay=195, Bit 14, Center 132 (83 ~ 182) 100
9010 23:51:05.109998 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9011 23:51:05.110481 ==
9012 23:51:05.113065 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 23:51:05.120026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 23:51:05.120622 ==
9015 23:51:05.120999 DQS Delay:
9016 23:51:05.122804 DQS0 = 0, DQS1 = 0
9017 23:51:05.123269 DQM Delay:
9018 23:51:05.125700 DQM0 = 133, DQM1 = 127
9019 23:51:05.126125 DQ Delay:
9020 23:51:05.129647 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9021 23:51:05.132802 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
9022 23:51:05.136037 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
9023 23:51:05.139933 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =140
9024 23:51:05.140509
9025 23:51:05.140926
9026 23:51:05.141336
9027 23:51:05.142172 [DramC_TX_OE_Calibration] TA2
9028 23:51:05.145990 Original DQ_B0 (3 6) =30, OEN = 27
9029 23:51:05.149622 Original DQ_B1 (3 6) =30, OEN = 27
9030 23:51:05.152538 24, 0x0, End_B0=24 End_B1=24
9031 23:51:05.156346 25, 0x0, End_B0=25 End_B1=25
9032 23:51:05.156910 26, 0x0, End_B0=26 End_B1=26
9033 23:51:05.159475 27, 0x0, End_B0=27 End_B1=27
9034 23:51:05.162510 28, 0x0, End_B0=28 End_B1=28
9035 23:51:05.165598 29, 0x0, End_B0=29 End_B1=29
9036 23:51:05.166073 30, 0x0, End_B0=30 End_B1=30
9037 23:51:05.168879 31, 0x4545, End_B0=30 End_B1=30
9038 23:51:05.172989 Byte0 end_step=30 best_step=27
9039 23:51:05.175841 Byte1 end_step=30 best_step=27
9040 23:51:05.178922 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 23:51:05.181699 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 23:51:05.182169
9043 23:51:05.182536
9044 23:51:05.188124 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9045 23:51:05.192114 CH1 RK1: MR19=303, MR18=E1D
9046 23:51:05.198283 CH1_RK1: MR19=0x303, MR18=0xE1D, DQSOSC=395, MR23=63, INC=23, DEC=15
9047 23:51:05.202322 [RxdqsGatingPostProcess] freq 1600
9048 23:51:05.208214 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 23:51:05.208738 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 23:51:05.211603 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 23:51:05.214658 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 23:51:05.218782 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 23:51:05.221568 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 23:51:05.225122 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 23:51:05.228424 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 23:51:05.231697 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 23:51:05.234595 Pre-setting of DQS Precalculation
9058 23:51:05.237787 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 23:51:05.248306 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 23:51:05.254840 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 23:51:05.255388
9062 23:51:05.255755
9063 23:51:05.257817 [Calibration Summary] 3200 Mbps
9064 23:51:05.258283 CH 0, Rank 0
9065 23:51:05.260716 SW Impedance : PASS
9066 23:51:05.261234 DUTY Scan : NO K
9067 23:51:05.264028 ZQ Calibration : PASS
9068 23:51:05.267336 Jitter Meter : NO K
9069 23:51:05.267757 CBT Training : PASS
9070 23:51:05.270981 Write leveling : PASS
9071 23:51:05.274217 RX DQS gating : PASS
9072 23:51:05.274733 RX DQ/DQS(RDDQC) : PASS
9073 23:51:05.277716 TX DQ/DQS : PASS
9074 23:51:05.281651 RX DATLAT : PASS
9075 23:51:05.282204 RX DQ/DQS(Engine): PASS
9076 23:51:05.284569 TX OE : PASS
9077 23:51:05.285130 All Pass.
9078 23:51:05.285557
9079 23:51:05.287845 CH 0, Rank 1
9080 23:51:05.288405 SW Impedance : PASS
9081 23:51:05.290938 DUTY Scan : NO K
9082 23:51:05.294027 ZQ Calibration : PASS
9083 23:51:05.294587 Jitter Meter : NO K
9084 23:51:05.297782 CBT Training : PASS
9085 23:51:05.301434 Write leveling : PASS
9086 23:51:05.301988 RX DQS gating : PASS
9087 23:51:05.303810 RX DQ/DQS(RDDQC) : PASS
9088 23:51:05.308414 TX DQ/DQS : PASS
9089 23:51:05.308993 RX DATLAT : PASS
9090 23:51:05.310599 RX DQ/DQS(Engine): PASS
9091 23:51:05.311075 TX OE : PASS
9092 23:51:05.313839 All Pass.
9093 23:51:05.314301
9094 23:51:05.314667 CH 1, Rank 0
9095 23:51:05.317124 SW Impedance : PASS
9096 23:51:05.317586 DUTY Scan : NO K
9097 23:51:05.320696 ZQ Calibration : PASS
9098 23:51:05.323577 Jitter Meter : NO K
9099 23:51:05.323996 CBT Training : PASS
9100 23:51:05.326917 Write leveling : PASS
9101 23:51:05.330591 RX DQS gating : PASS
9102 23:51:05.331157 RX DQ/DQS(RDDQC) : PASS
9103 23:51:05.333331 TX DQ/DQS : PASS
9104 23:51:05.337113 RX DATLAT : PASS
9105 23:51:05.337691 RX DQ/DQS(Engine): PASS
9106 23:51:05.340302 TX OE : PASS
9107 23:51:05.340727 All Pass.
9108 23:51:05.341253
9109 23:51:05.343495 CH 1, Rank 1
9110 23:51:05.343917 SW Impedance : PASS
9111 23:51:05.346823 DUTY Scan : NO K
9112 23:51:05.350488 ZQ Calibration : PASS
9113 23:51:05.350945 Jitter Meter : NO K
9114 23:51:05.353481 CBT Training : PASS
9115 23:51:05.357809 Write leveling : PASS
9116 23:51:05.358337 RX DQS gating : PASS
9117 23:51:05.359969 RX DQ/DQS(RDDQC) : PASS
9118 23:51:05.363112 TX DQ/DQS : PASS
9119 23:51:05.363541 RX DATLAT : PASS
9120 23:51:05.366867 RX DQ/DQS(Engine): PASS
9121 23:51:05.369924 TX OE : PASS
9122 23:51:05.370450 All Pass.
9123 23:51:05.370791
9124 23:51:05.371107 DramC Write-DBI on
9125 23:51:05.373743 PER_BANK_REFRESH: Hybrid Mode
9126 23:51:05.376945 TX_TRACKING: ON
9127 23:51:05.383404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 23:51:05.393406 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 23:51:05.399669 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 23:51:05.402990 [FAST_K] Save calibration result to emmc
9131 23:51:05.406546 sync common calibartion params.
9132 23:51:05.409857 sync cbt_mode0:1, 1:1
9133 23:51:05.410417 dram_init: ddr_geometry: 2
9134 23:51:05.412370 dram_init: ddr_geometry: 2
9135 23:51:05.415878 dram_init: ddr_geometry: 2
9136 23:51:05.419481 0:dram_rank_size:100000000
9137 23:51:05.419958 1:dram_rank_size:100000000
9138 23:51:05.425638 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 23:51:05.429199 DFS_SHUFFLE_HW_MODE: ON
9140 23:51:05.432237 dramc_set_vcore_voltage set vcore to 725000
9141 23:51:05.435811 Read voltage for 1600, 0
9142 23:51:05.436379 Vio18 = 0
9143 23:51:05.436752 Vcore = 725000
9144 23:51:05.438720 Vdram = 0
9145 23:51:05.439246 Vddq = 0
9146 23:51:05.439630 Vmddr = 0
9147 23:51:05.442421 switch to 3200 Mbps bootup
9148 23:51:05.442979 [DramcRunTimeConfig]
9149 23:51:05.445696 PHYPLL
9150 23:51:05.446230 DPM_CONTROL_AFTERK: ON
9151 23:51:05.448596 PER_BANK_REFRESH: ON
9152 23:51:05.451931 REFRESH_OVERHEAD_REDUCTION: ON
9153 23:51:05.452357 CMD_PICG_NEW_MODE: OFF
9154 23:51:05.454986 XRTWTW_NEW_MODE: ON
9155 23:51:05.455470 XRTRTR_NEW_MODE: ON
9156 23:51:05.458708 TX_TRACKING: ON
9157 23:51:05.459134 RDSEL_TRACKING: OFF
9158 23:51:05.461802 DQS Precalculation for DVFS: ON
9159 23:51:05.464871 RX_TRACKING: OFF
9160 23:51:05.465339 HW_GATING DBG: ON
9161 23:51:05.468607 ZQCS_ENABLE_LP4: ON
9162 23:51:05.469135 RX_PICG_NEW_MODE: ON
9163 23:51:05.471824 TX_PICG_NEW_MODE: ON
9164 23:51:05.475492 ENABLE_RX_DCM_DPHY: ON
9165 23:51:05.476036 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 23:51:05.478768 DUMMY_READ_FOR_TRACKING: OFF
9167 23:51:05.481831 !!! SPM_CONTROL_AFTERK: OFF
9168 23:51:05.485205 !!! SPM could not control APHY
9169 23:51:05.485771 IMPEDANCE_TRACKING: ON
9170 23:51:05.487991 TEMP_SENSOR: ON
9171 23:51:05.488413 HW_SAVE_FOR_SR: OFF
9172 23:51:05.492369 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 23:51:05.495646 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 23:51:05.498565 Read ODT Tracking: ON
9175 23:51:05.501997 Refresh Rate DeBounce: ON
9176 23:51:05.502422 DFS_NO_QUEUE_FLUSH: ON
9177 23:51:05.505000 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 23:51:05.507960 ENABLE_DFS_RUNTIME_MRW: OFF
9179 23:51:05.512010 DDR_RESERVE_NEW_MODE: ON
9180 23:51:05.512552 MR_CBT_SWITCH_FREQ: ON
9181 23:51:05.515047 =========================
9182 23:51:05.534588 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 23:51:05.537438 dram_init: ddr_geometry: 2
9184 23:51:05.555714 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 23:51:05.558863 dram_init: dram init end (result: 0)
9186 23:51:05.565122 DRAM-K: Full calibration passed in 24432 msecs
9187 23:51:05.568342 MRC: failed to locate region type 0.
9188 23:51:05.568795 DRAM rank0 size:0x100000000,
9189 23:51:05.571525 DRAM rank1 size=0x100000000
9190 23:51:05.581610 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 23:51:05.588578 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 23:51:05.595220 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 23:51:05.605143 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 23:51:05.605787 DRAM rank0 size:0x100000000,
9195 23:51:05.608732 DRAM rank1 size=0x100000000
9196 23:51:05.609342 CBMEM:
9197 23:51:05.611725 IMD: root @ 0xfffff000 254 entries.
9198 23:51:05.614748 IMD: root @ 0xffffec00 62 entries.
9199 23:51:05.618289 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 23:51:05.625091 WARNING: RO_VPD is uninitialized or empty.
9201 23:51:05.628700 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 23:51:05.635950 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 23:51:05.648674 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9204 23:51:05.659746 BS: romstage times (exec / console): total (unknown) / 23961 ms
9205 23:51:05.660319
9206 23:51:05.660695
9207 23:51:05.669747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 23:51:05.673742 ARM64: Exception handlers installed.
9209 23:51:05.676828 ARM64: Testing exception
9210 23:51:05.679744 ARM64: Done test exception
9211 23:51:05.680307 Enumerating buses...
9212 23:51:05.683399 Show all devs... Before device enumeration.
9213 23:51:05.686434 Root Device: enabled 1
9214 23:51:05.689719 CPU_CLUSTER: 0: enabled 1
9215 23:51:05.690187 CPU: 00: enabled 1
9216 23:51:05.692519 Compare with tree...
9217 23:51:05.692998 Root Device: enabled 1
9218 23:51:05.696183 CPU_CLUSTER: 0: enabled 1
9219 23:51:05.699334 CPU: 00: enabled 1
9220 23:51:05.699802 Root Device scanning...
9221 23:51:05.702429 scan_static_bus for Root Device
9222 23:51:05.705930 CPU_CLUSTER: 0 enabled
9223 23:51:05.709524 scan_static_bus for Root Device done
9224 23:51:05.712619 scan_bus: bus Root Device finished in 8 msecs
9225 23:51:05.713050 done
9226 23:51:05.719169 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 23:51:05.722884 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 23:51:05.728849 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 23:51:05.732182 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 23:51:05.735836 Allocating resources...
9231 23:51:05.738714 Reading resources...
9232 23:51:05.742057 Root Device read_resources bus 0 link: 0
9233 23:51:05.745739 DRAM rank0 size:0x100000000,
9234 23:51:05.746162 DRAM rank1 size=0x100000000
9235 23:51:05.752573 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 23:51:05.752998 CPU: 00 missing read_resources
9237 23:51:05.758261 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 23:51:05.761504 Root Device read_resources bus 0 link: 0 done
9239 23:51:05.765086 Done reading resources.
9240 23:51:05.769072 Show resources in subtree (Root Device)...After reading.
9241 23:51:05.771485 Root Device child on link 0 CPU_CLUSTER: 0
9242 23:51:05.775321 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 23:51:05.785387 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 23:51:05.785928 CPU: 00
9245 23:51:05.790960 Root Device assign_resources, bus 0 link: 0
9246 23:51:05.794550 CPU_CLUSTER: 0 missing set_resources
9247 23:51:05.797931 Root Device assign_resources, bus 0 link: 0 done
9248 23:51:05.801377 Done setting resources.
9249 23:51:05.804357 Show resources in subtree (Root Device)...After assigning values.
9250 23:51:05.808003 Root Device child on link 0 CPU_CLUSTER: 0
9251 23:51:05.814241 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 23:51:05.820918 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 23:51:05.824463 CPU: 00
9254 23:51:05.824886 Done allocating resources.
9255 23:51:05.830672 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 23:51:05.831096 Enabling resources...
9257 23:51:05.834343 done.
9258 23:51:05.837160 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 23:51:05.840802 Initializing devices...
9260 23:51:05.841226 Root Device init
9261 23:51:05.844071 init hardware done!
9262 23:51:05.844599 0x00000018: ctrlr->caps
9263 23:51:05.847644 52.000 MHz: ctrlr->f_max
9264 23:51:05.850520 0.400 MHz: ctrlr->f_min
9265 23:51:05.853798 0x40ff8080: ctrlr->voltages
9266 23:51:05.854258 sclk: 390625
9267 23:51:05.854594 Bus Width = 1
9268 23:51:05.857144 sclk: 390625
9269 23:51:05.857716 Bus Width = 1
9270 23:51:05.860572 Early init status = 3
9271 23:51:05.863813 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 23:51:05.867164 in-header: 03 fc 00 00 01 00 00 00
9273 23:51:05.872883 in-data: 00
9274 23:51:05.873881 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 23:51:05.878419 in-header: 03 fd 00 00 00 00 00 00
9276 23:51:05.881828 in-data:
9277 23:51:05.885250 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 23:51:05.888806 in-header: 03 fc 00 00 01 00 00 00
9279 23:51:05.892128 in-data: 00
9280 23:51:05.895403 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 23:51:05.899963 in-header: 03 fd 00 00 00 00 00 00
9282 23:51:05.903457 in-data:
9283 23:51:05.906529 [SSUSB] Setting up USB HOST controller...
9284 23:51:05.910229 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 23:51:05.913650 [SSUSB] phy power-on done.
9286 23:51:05.917403 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 23:51:05.923589 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 23:51:05.926634 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 23:51:05.933621 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 23:51:05.940004 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 23:51:05.946412 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 23:51:05.953045 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 23:51:05.959715 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 23:51:05.962652 SPM: binary array size = 0x9dc
9295 23:51:05.966706 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 23:51:05.973469 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 23:51:05.979423 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 23:51:05.986488 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 23:51:05.988942 configure_display: Starting display init
9300 23:51:06.024224 anx7625_power_on_init: Init interface.
9301 23:51:06.026731 anx7625_disable_pd_protocol: Disabled PD feature.
9302 23:51:06.030232 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 23:51:06.058105 anx7625_start_dp_work: Secure OCM version=00
9304 23:51:06.061040 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 23:51:06.075939 sp_tx_get_edid_block: EDID Block = 1
9306 23:51:06.178696 Extracted contents:
9307 23:51:06.182097 header: 00 ff ff ff ff ff ff 00
9308 23:51:06.185084 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 23:51:06.188840 version: 01 04
9310 23:51:06.191782 basic params: 95 1f 11 78 0a
9311 23:51:06.195360 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 23:51:06.198683 established: 00 00 00
9313 23:51:06.204578 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 23:51:06.211593 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 23:51:06.214381 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 23:51:06.221024 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 23:51:06.228212 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 23:51:06.231594 extensions: 00
9319 23:51:06.232146 checksum: fb
9320 23:51:06.232515
9321 23:51:06.237437 Manufacturer: IVO Model 57d Serial Number 0
9322 23:51:06.238134 Made week 0 of 2020
9323 23:51:06.241013 EDID version: 1.4
9324 23:51:06.241639 Digital display
9325 23:51:06.244242 6 bits per primary color channel
9326 23:51:06.247530 DisplayPort interface
9327 23:51:06.247996 Maximum image size: 31 cm x 17 cm
9328 23:51:06.251267 Gamma: 220%
9329 23:51:06.251820 Check DPMS levels
9330 23:51:06.257555 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 23:51:06.260760 First detailed timing is preferred timing
9332 23:51:06.264440 Established timings supported:
9333 23:51:06.264967 Standard timings supported:
9334 23:51:06.267346 Detailed timings
9335 23:51:06.271027 Hex of detail: 383680a07038204018303c0035ae10000019
9336 23:51:06.277287 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 23:51:06.280545 0780 0798 07c8 0820 hborder 0
9338 23:51:06.283780 0438 043b 0447 0458 vborder 0
9339 23:51:06.286965 -hsync -vsync
9340 23:51:06.287390 Did detailed timing
9341 23:51:06.294205 Hex of detail: 000000000000000000000000000000000000
9342 23:51:06.296882 Manufacturer-specified data, tag 0
9343 23:51:06.300636 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 23:51:06.303680 ASCII string: InfoVision
9345 23:51:06.306679 Hex of detail: 000000fe00523134304e574635205248200a
9346 23:51:06.310519 ASCII string: R140NWF5 RH
9347 23:51:06.311199 Checksum
9348 23:51:06.313653 Checksum: 0xfb (valid)
9349 23:51:06.316939 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 23:51:06.320518 DSI data_rate: 832800000 bps
9351 23:51:06.326829 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 23:51:06.329925 anx7625_parse_edid: pixelclock(138800).
9353 23:51:06.333406 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 23:51:06.337749 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 23:51:06.339763 anx7625_dsi_config: config dsi.
9356 23:51:06.346159 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 23:51:06.360955 anx7625_dsi_config: success to config DSI
9358 23:51:06.364106 anx7625_dp_start: MIPI phy setup OK.
9359 23:51:06.367325 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 23:51:06.370143 mtk_ddp_mode_set invalid vrefresh 60
9361 23:51:06.373769 main_disp_path_setup
9362 23:51:06.374192 ovl_layer_smi_id_en
9363 23:51:06.377007 ovl_layer_smi_id_en
9364 23:51:06.377459 ccorr_config
9365 23:51:06.377794 aal_config
9366 23:51:06.380592 gamma_config
9367 23:51:06.381011 postmask_config
9368 23:51:06.383608 dither_config
9369 23:51:06.386846 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 23:51:06.393970 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 23:51:06.396920 Root Device init finished in 551 msecs
9372 23:51:06.400164 CPU_CLUSTER: 0 init
9373 23:51:06.406847 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 23:51:06.413621 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 23:51:06.414151 APU_MBOX 0x190000b0 = 0x10001
9376 23:51:06.416767 APU_MBOX 0x190001b0 = 0x10001
9377 23:51:06.419925 APU_MBOX 0x190005b0 = 0x10001
9378 23:51:06.423672 APU_MBOX 0x190006b0 = 0x10001
9379 23:51:06.429614 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 23:51:06.440005 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9381 23:51:06.452406 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 23:51:06.458422 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 23:51:06.470456 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9384 23:51:06.479070 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 23:51:06.482715 CPU_CLUSTER: 0 init finished in 81 msecs
9386 23:51:06.485909 Devices initialized
9387 23:51:06.489599 Show all devs... After init.
9388 23:51:06.490167 Root Device: enabled 1
9389 23:51:06.492653 CPU_CLUSTER: 0: enabled 1
9390 23:51:06.496195 CPU: 00: enabled 1
9391 23:51:06.498948 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9392 23:51:06.502678 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 23:51:06.505552 ELOG: NV offset 0x57f000 size 0x1000
9394 23:51:06.512652 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9395 23:51:06.518856 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 23:51:06.522005 ELOG: Event(17) added with size 13 at 2024-05-29 23:51:06 UTC
9397 23:51:06.528855 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 23:51:06.532544 in-header: 03 db 00 00 2c 00 00 00
9399 23:51:06.542209 in-data: 62 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 23:51:06.548480 ELOG: Event(A1) added with size 10 at 2024-05-29 23:51:06 UTC
9401 23:51:06.554721 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9402 23:51:06.562202 ELOG: Event(A0) added with size 9 at 2024-05-29 23:51:06 UTC
9403 23:51:06.565385 elog_add_boot_reason: Logged dev mode boot
9404 23:51:06.571483 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9405 23:51:06.572044 Finalize devices...
9406 23:51:06.575428 Devices finalized
9407 23:51:06.578229 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 23:51:06.581430 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9409 23:51:06.585153 in-header: 03 07 00 00 08 00 00 00
9410 23:51:06.588070 in-data: aa e4 47 04 13 02 00 00
9411 23:51:06.591438 Chrome EC: UHEPI supported
9412 23:51:06.598274 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9413 23:51:06.601232 in-header: 03 a9 00 00 08 00 00 00
9414 23:51:06.604659 in-data: 84 60 60 08 00 00 00 00
9415 23:51:06.611268 ELOG: Event(91) added with size 10 at 2024-05-29 23:51:06 UTC
9416 23:51:06.615123 Chrome EC: clear events_b mask to 0x0000000020004000
9417 23:51:06.621074 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9418 23:51:06.625707 in-header: 03 fd 00 00 00 00 00 00
9419 23:51:06.629278 in-data:
9420 23:51:06.631735 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9421 23:51:06.635412 Writing coreboot table at 0xffe64000
9422 23:51:06.641673 0. 000000000010a000-0000000000113fff: RAMSTAGE
9423 23:51:06.646041 1. 0000000040000000-00000000400fffff: RAM
9424 23:51:06.648261 2. 0000000040100000-000000004032afff: RAMSTAGE
9425 23:51:06.651332 3. 000000004032b000-00000000545fffff: RAM
9426 23:51:06.654918 4. 0000000054600000-000000005465ffff: BL31
9427 23:51:06.661039 5. 0000000054660000-00000000ffe63fff: RAM
9428 23:51:06.664696 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9429 23:51:06.668020 7. 0000000100000000-000000023fffffff: RAM
9430 23:51:06.671696 Passing 5 GPIOs to payload:
9431 23:51:06.674774 NAME | PORT | POLARITY | VALUE
9432 23:51:06.681839 EC in RW | 0x000000aa | low | undefined
9433 23:51:06.684923 EC interrupt | 0x00000005 | low | undefined
9434 23:51:06.690715 TPM interrupt | 0x000000ab | high | undefined
9435 23:51:06.694183 SD card detect | 0x00000011 | high | undefined
9436 23:51:06.700691 speaker enable | 0x00000093 | high | undefined
9437 23:51:06.704108 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9438 23:51:06.707909 in-header: 03 f9 00 00 02 00 00 00
9439 23:51:06.708490 in-data: 02 00
9440 23:51:06.710452 ADC[4]: Raw value=901847 ID=7
9441 23:51:06.713957 ADC[3]: Raw value=213916 ID=1
9442 23:51:06.714530 RAM Code: 0x71
9443 23:51:06.717575 ADC[6]: Raw value=74630 ID=0
9444 23:51:06.720891 ADC[5]: Raw value=213546 ID=1
9445 23:51:06.721525 SKU Code: 0x1
9446 23:51:06.727360 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 21b
9447 23:51:06.730750 coreboot table: 964 bytes.
9448 23:51:06.733987 IMD ROOT 0. 0xfffff000 0x00001000
9449 23:51:06.737189 IMD SMALL 1. 0xffffe000 0x00001000
9450 23:51:06.740411 RO MCACHE 2. 0xffffc000 0x00001104
9451 23:51:06.743912 CONSOLE 3. 0xfff7c000 0x00080000
9452 23:51:06.747025 FMAP 4. 0xfff7b000 0x00000452
9453 23:51:06.750102 TIME STAMP 5. 0xfff7a000 0x00000910
9454 23:51:06.753340 VBOOT WORK 6. 0xfff66000 0x00014000
9455 23:51:06.756764 RAMOOPS 7. 0xffe66000 0x00100000
9456 23:51:06.760198 COREBOOT 8. 0xffe64000 0x00002000
9457 23:51:06.760667 IMD small region:
9458 23:51:06.763066 IMD ROOT 0. 0xffffec00 0x00000400
9459 23:51:06.766198 VPD 1. 0xffffeb80 0x0000006c
9460 23:51:06.769687 MMC STATUS 2. 0xffffeb60 0x00000004
9461 23:51:06.776702 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9462 23:51:06.783648 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9463 23:51:06.822181 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9464 23:51:06.825736 Checking segment from ROM address 0x40100000
9465 23:51:06.832054 Checking segment from ROM address 0x4010001c
9466 23:51:06.835946 Loading segment from ROM address 0x40100000
9467 23:51:06.836519 code (compression=0)
9468 23:51:06.845244 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9469 23:51:06.851463 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9470 23:51:06.854741 it's not compressed!
9471 23:51:06.858075 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9472 23:51:06.864519 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9473 23:51:06.882734 Loading segment from ROM address 0x4010001c
9474 23:51:06.883171 Entry Point 0x80000000
9475 23:51:06.885547 Loaded segments
9476 23:51:06.888970 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9477 23:51:06.895737 Jumping to boot code at 0x80000000(0xffe64000)
9478 23:51:06.902469 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9479 23:51:06.908614 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9480 23:51:06.917659 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9481 23:51:06.920053 Checking segment from ROM address 0x40100000
9482 23:51:06.923597 Checking segment from ROM address 0x4010001c
9483 23:51:06.929825 Loading segment from ROM address 0x40100000
9484 23:51:06.930251 code (compression=1)
9485 23:51:06.937123 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9486 23:51:06.946446 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9487 23:51:06.946967 using LZMA
9488 23:51:06.955456 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9489 23:51:06.962004 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9490 23:51:06.964751 Loading segment from ROM address 0x4010001c
9491 23:51:06.968520 Entry Point 0x54601000
9492 23:51:06.968945 Loaded segments
9493 23:51:06.971467 NOTICE: MT8192 bl31_setup
9494 23:51:06.979149 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9495 23:51:06.982003 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9496 23:51:06.985234 WARNING: region 0:
9497 23:51:06.989246 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 23:51:06.989716 WARNING: region 1:
9499 23:51:06.995347 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9500 23:51:06.998482 WARNING: region 2:
9501 23:51:07.001891 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9502 23:51:07.005079 WARNING: region 3:
9503 23:51:07.011663 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 23:51:07.012189 WARNING: region 4:
9505 23:51:07.018849 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 23:51:07.019419 WARNING: region 5:
9507 23:51:07.021397 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 23:51:07.025088 WARNING: region 6:
9509 23:51:07.028655 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 23:51:07.031510 WARNING: region 7:
9511 23:51:07.034871 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 23:51:07.041565 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9513 23:51:07.044797 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9514 23:51:07.051188 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9515 23:51:07.054753 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9516 23:51:07.057908 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9517 23:51:07.064160 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9518 23:51:07.067831 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9519 23:51:07.070873 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9520 23:51:07.078027 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9521 23:51:07.080781 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9522 23:51:07.087282 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9523 23:51:07.091124 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9524 23:51:07.094429 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9525 23:51:07.101019 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9526 23:51:07.104181 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9527 23:51:07.110504 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9528 23:51:07.113721 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9529 23:51:07.116941 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9530 23:51:07.123566 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9531 23:51:07.126818 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9532 23:51:07.133517 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9533 23:51:07.136896 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9534 23:51:07.140449 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9535 23:51:07.146993 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9536 23:51:07.150068 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9537 23:51:07.156970 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9538 23:51:07.159743 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9539 23:51:07.163536 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9540 23:51:07.169932 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9541 23:51:07.173500 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9542 23:51:07.179636 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9543 23:51:07.183182 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9544 23:51:07.186013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9545 23:51:07.192937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9546 23:51:07.195902 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9547 23:51:07.200019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9548 23:51:07.202712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9549 23:51:07.208996 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9550 23:51:07.212576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9551 23:51:07.215895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9552 23:51:07.219373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9553 23:51:07.226200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9554 23:51:07.229587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9555 23:51:07.232628 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9556 23:51:07.236003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9557 23:51:07.243162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9558 23:51:07.246020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9559 23:51:07.249078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9560 23:51:07.255523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9561 23:51:07.259065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9562 23:51:07.265361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9563 23:51:07.268643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9564 23:51:07.272525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9565 23:51:07.278936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9566 23:51:07.282075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9567 23:51:07.288959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9568 23:51:07.292656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9569 23:51:07.298841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9570 23:51:07.301822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9571 23:51:07.308559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9572 23:51:07.311471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9573 23:51:07.315861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9574 23:51:07.321731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9575 23:51:07.324764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9576 23:51:07.331540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9577 23:51:07.334786 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9578 23:51:07.341290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9579 23:51:07.345049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9580 23:51:07.351400 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9581 23:51:07.353960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9582 23:51:07.360636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9583 23:51:07.364541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9584 23:51:07.367851 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9585 23:51:07.374502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9586 23:51:07.377878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9587 23:51:07.384187 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9588 23:51:07.387729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9589 23:51:07.394760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9590 23:51:07.397452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9591 23:51:07.404011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9592 23:51:07.407311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9593 23:51:07.410368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9594 23:51:07.417027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9595 23:51:07.420524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9596 23:51:07.426727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9597 23:51:07.430044 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9598 23:51:07.437717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9599 23:51:07.439935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9600 23:51:07.446729 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9601 23:51:07.450222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9602 23:51:07.453790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9603 23:51:07.459989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9604 23:51:07.463125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9605 23:51:07.469846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9606 23:51:07.473338 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9607 23:51:07.479794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9608 23:51:07.483154 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9609 23:51:07.486599 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9610 23:51:07.492986 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9611 23:51:07.496425 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9612 23:51:07.499724 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9613 23:51:07.505937 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9614 23:51:07.509314 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9615 23:51:07.512503 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9616 23:51:07.519030 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9617 23:51:07.522878 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9618 23:51:07.529306 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9619 23:51:07.532703 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9620 23:51:07.536141 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9621 23:51:07.542502 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9622 23:51:07.545831 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9623 23:51:07.552695 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9624 23:51:07.555350 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9625 23:51:07.558997 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9626 23:51:07.565386 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9627 23:51:07.569056 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9628 23:51:07.571825 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9629 23:51:07.579133 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9630 23:51:07.581879 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9631 23:51:07.585439 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9632 23:51:07.592100 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9633 23:51:07.594950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9634 23:51:07.598349 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9635 23:51:07.601970 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9636 23:51:07.608959 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9637 23:51:07.611702 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9638 23:51:07.618462 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9639 23:51:07.621712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9640 23:51:07.625361 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9641 23:51:07.631956 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9642 23:51:07.634711 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9643 23:51:07.641745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9644 23:51:07.644491 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9645 23:51:07.648248 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9646 23:51:07.654299 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9647 23:51:07.658054 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9648 23:51:07.664575 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9649 23:51:07.667963 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9650 23:51:07.670626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9651 23:51:07.677419 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9652 23:51:07.681143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9653 23:51:07.687459 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9654 23:51:07.690954 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9655 23:51:07.696963 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9656 23:51:07.700319 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9657 23:51:07.705124 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9658 23:51:07.710942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9659 23:51:07.715789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9660 23:51:07.720266 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9661 23:51:07.723445 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9662 23:51:07.726494 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9663 23:51:07.733624 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9664 23:51:07.736392 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9665 23:51:07.743770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9666 23:51:07.746063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9667 23:51:07.749823 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9668 23:51:07.756567 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9669 23:51:07.759866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9670 23:51:07.766397 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9671 23:51:07.769492 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9672 23:51:07.772793 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9673 23:51:07.779320 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9674 23:51:07.782915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9675 23:51:07.789458 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9676 23:51:07.792450 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9677 23:51:07.795587 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9678 23:51:07.802567 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9679 23:51:07.806180 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9680 23:51:07.812462 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9681 23:51:07.815763 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9682 23:51:07.818626 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9683 23:51:07.825307 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9684 23:51:07.828699 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9685 23:51:07.835235 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9686 23:51:07.838200 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9687 23:51:07.841563 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9688 23:51:07.848920 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9689 23:51:07.852172 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9690 23:51:07.858134 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9691 23:51:07.861562 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9692 23:51:07.864854 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9693 23:51:07.871400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9694 23:51:07.874752 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9695 23:51:07.881137 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9696 23:51:07.884447 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9697 23:51:07.891629 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9698 23:51:07.894510 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9699 23:51:07.897689 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9700 23:51:07.904487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9701 23:51:07.908044 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9702 23:51:07.914568 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9703 23:51:07.917840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9704 23:51:07.920932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9705 23:51:07.927722 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9706 23:51:07.931422 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9707 23:51:07.937559 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9708 23:51:07.940934 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9709 23:51:07.947532 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9710 23:51:07.950378 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9711 23:51:07.953767 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9712 23:51:07.960285 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9713 23:51:07.963620 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9714 23:51:07.970786 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9715 23:51:07.973622 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9716 23:51:07.980362 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9717 23:51:07.983634 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9718 23:51:07.986525 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9719 23:51:07.993241 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9720 23:51:07.997537 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9721 23:51:08.003668 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9722 23:51:08.006784 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9723 23:51:08.013249 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9724 23:51:08.016073 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9725 23:51:08.019582 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9726 23:51:08.026747 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9727 23:51:08.030131 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9728 23:51:08.036577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9729 23:51:08.040105 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9730 23:51:08.046104 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9731 23:51:08.049568 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9732 23:51:08.052700 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9733 23:51:08.059526 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9734 23:51:08.062370 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9735 23:51:08.069344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9736 23:51:08.072215 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9737 23:51:08.079341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9738 23:51:08.082328 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9739 23:51:08.085882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9740 23:51:08.092358 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9741 23:51:08.095722 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9742 23:51:08.099202 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9743 23:51:08.102464 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9744 23:51:08.108889 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9745 23:51:08.112355 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9746 23:51:08.115046 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9747 23:51:08.121775 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9748 23:51:08.124892 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9749 23:51:08.131636 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9750 23:51:08.134858 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9751 23:51:08.138255 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9752 23:51:08.145012 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9753 23:51:08.148845 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9754 23:51:08.151113 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9755 23:51:08.157896 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9756 23:51:08.161320 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9757 23:51:08.164428 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9758 23:51:08.171276 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9759 23:51:08.174534 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9760 23:51:08.181929 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9761 23:51:08.184823 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9762 23:51:08.188038 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9763 23:51:08.194229 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9764 23:51:08.197223 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9765 23:51:08.200520 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9766 23:51:08.207089 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9767 23:51:08.210923 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9768 23:51:08.217156 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9769 23:51:08.220649 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9770 23:51:08.223779 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9771 23:51:08.230279 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9772 23:51:08.233388 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9773 23:51:08.240121 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9774 23:51:08.243553 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9775 23:51:08.247050 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9776 23:51:08.253580 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9777 23:51:08.256776 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9778 23:51:08.259852 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9779 23:51:08.266759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9780 23:51:08.269825 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9781 23:51:08.272944 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9782 23:51:08.279671 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9783 23:51:08.282649 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9784 23:51:08.286374 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9785 23:51:08.289339 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9786 23:51:08.296745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9787 23:51:08.299453 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9788 23:51:08.302450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9789 23:51:08.305989 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9790 23:51:08.312298 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9791 23:51:08.315835 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9792 23:51:08.319529 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9793 23:51:08.322747 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9794 23:51:08.328867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9795 23:51:08.332327 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9796 23:51:08.338722 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9797 23:51:08.342183 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9798 23:51:08.348811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9799 23:51:08.351832 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9800 23:51:08.358606 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9801 23:51:08.362407 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9802 23:51:08.365089 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9803 23:51:08.372064 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9804 23:51:08.374809 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9805 23:51:08.382029 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9806 23:51:08.385166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9807 23:51:08.391638 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9808 23:51:08.394941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9809 23:51:08.397957 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9810 23:51:08.404697 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9811 23:51:08.407636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9812 23:51:08.414567 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9813 23:51:08.417395 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9814 23:51:08.420941 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9815 23:51:08.427742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9816 23:51:08.430816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9817 23:51:08.437598 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9818 23:51:08.441104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9819 23:51:08.444080 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9820 23:51:08.451467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9821 23:51:08.454374 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9822 23:51:08.460663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9823 23:51:08.464297 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9824 23:51:08.470680 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9825 23:51:08.473819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9826 23:51:08.476851 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9827 23:51:08.483575 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9828 23:51:08.487270 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9829 23:51:08.493871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9830 23:51:08.497155 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9831 23:51:08.503943 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9832 23:51:08.506785 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9833 23:51:08.510371 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9834 23:51:08.516716 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9835 23:51:08.519992 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9836 23:51:08.526575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9837 23:51:08.530175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9838 23:51:08.536304 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9839 23:51:08.539429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9840 23:51:08.544224 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9841 23:51:08.549654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9842 23:51:08.553064 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9843 23:51:08.559594 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9844 23:51:08.562724 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9845 23:51:08.565639 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9846 23:51:08.572891 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9847 23:51:08.576579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9848 23:51:08.582481 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9849 23:51:08.585946 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9850 23:51:08.589414 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9851 23:51:08.595752 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9852 23:51:08.599276 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9853 23:51:08.605893 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9854 23:51:08.608662 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9855 23:51:08.615227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9856 23:51:08.619580 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9857 23:51:08.621999 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9858 23:51:08.628679 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9859 23:51:08.631743 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9860 23:51:08.638838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9861 23:51:08.641924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9862 23:51:08.648591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9863 23:51:08.651408 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9864 23:51:08.655022 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9865 23:51:08.661442 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9866 23:51:08.664933 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9867 23:51:08.671456 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9868 23:51:08.674481 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9869 23:51:08.681091 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9870 23:51:08.684546 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9871 23:51:08.690826 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9872 23:51:08.694549 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9873 23:51:08.697523 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9874 23:51:08.704141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9875 23:51:08.707763 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9876 23:51:08.715028 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9877 23:51:08.717513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9878 23:51:08.724622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9879 23:51:08.727006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9880 23:51:08.734109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9881 23:51:08.737199 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9882 23:51:08.740888 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9883 23:51:08.747614 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9884 23:51:08.750241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9885 23:51:08.756579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9886 23:51:08.760893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9887 23:51:08.767241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9888 23:51:08.769926 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9889 23:51:08.773536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9890 23:51:08.779425 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9891 23:51:08.782945 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9892 23:51:08.789748 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9893 23:51:08.792946 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9894 23:51:08.799743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9895 23:51:08.802890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9896 23:51:08.809420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9897 23:51:08.812852 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9898 23:51:08.816144 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9899 23:51:08.823108 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9900 23:51:08.825696 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9901 23:51:08.832930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9902 23:51:08.836198 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9903 23:51:08.842610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9904 23:51:08.845980 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9905 23:51:08.852382 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9906 23:51:08.855856 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9907 23:51:08.862385 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9908 23:51:08.865692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9909 23:51:08.869248 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9910 23:51:08.876132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9911 23:51:08.879144 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9912 23:51:08.885152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9913 23:51:08.888377 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9914 23:51:08.891876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9915 23:51:08.898314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9916 23:51:08.901799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9917 23:51:08.908586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9918 23:51:08.911666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9919 23:51:08.918407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9920 23:51:08.921332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9921 23:51:08.928226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9922 23:51:08.931385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9923 23:51:08.937942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9924 23:51:08.941093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9925 23:51:08.948381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9926 23:51:08.951399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9927 23:51:08.957375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9928 23:51:08.961371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9929 23:51:08.967304 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9930 23:51:08.971033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9931 23:51:08.977530 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9932 23:51:08.981100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9933 23:51:08.987168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9934 23:51:08.990750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9935 23:51:08.997310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9936 23:51:09.001104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9937 23:51:09.007133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9938 23:51:09.010164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9939 23:51:09.017064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9940 23:51:09.020539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9941 23:51:09.026718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9942 23:51:09.033187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9943 23:51:09.037000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9944 23:51:09.043687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9945 23:51:09.046594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9946 23:51:09.049773 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9947 23:51:09.053177 INFO: [APUAPC] vio 0
9948 23:51:09.056219 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9949 23:51:09.063477 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9950 23:51:09.067284 INFO: [APUAPC] D0_APC_0: 0x400510
9951 23:51:09.069759 INFO: [APUAPC] D0_APC_1: 0x0
9952 23:51:09.073253 INFO: [APUAPC] D0_APC_2: 0x1540
9953 23:51:09.073854 INFO: [APUAPC] D0_APC_3: 0x0
9954 23:51:09.076521 INFO: [APUAPC] D1_APC_0: 0xffffffff
9955 23:51:09.082992 INFO: [APUAPC] D1_APC_1: 0xffffffff
9956 23:51:09.086044 INFO: [APUAPC] D1_APC_2: 0x3fffff
9957 23:51:09.086511 INFO: [APUAPC] D1_APC_3: 0x0
9958 23:51:09.089394 INFO: [APUAPC] D2_APC_0: 0xffffffff
9959 23:51:09.093201 INFO: [APUAPC] D2_APC_1: 0xffffffff
9960 23:51:09.096191 INFO: [APUAPC] D2_APC_2: 0x3fffff
9961 23:51:09.099437 INFO: [APUAPC] D2_APC_3: 0x0
9962 23:51:09.103037 INFO: [APUAPC] D3_APC_0: 0xffffffff
9963 23:51:09.105821 INFO: [APUAPC] D3_APC_1: 0xffffffff
9964 23:51:09.109514 INFO: [APUAPC] D3_APC_2: 0x3fffff
9965 23:51:09.113230 INFO: [APUAPC] D3_APC_3: 0x0
9966 23:51:09.115955 INFO: [APUAPC] D4_APC_0: 0xffffffff
9967 23:51:09.119562 INFO: [APUAPC] D4_APC_1: 0xffffffff
9968 23:51:09.122876 INFO: [APUAPC] D4_APC_2: 0x3fffff
9969 23:51:09.125982 INFO: [APUAPC] D4_APC_3: 0x0
9970 23:51:09.129670 INFO: [APUAPC] D5_APC_0: 0xffffffff
9971 23:51:09.132597 INFO: [APUAPC] D5_APC_1: 0xffffffff
9972 23:51:09.135826 INFO: [APUAPC] D5_APC_2: 0x3fffff
9973 23:51:09.139199 INFO: [APUAPC] D5_APC_3: 0x0
9974 23:51:09.142047 INFO: [APUAPC] D6_APC_0: 0xffffffff
9975 23:51:09.145431 INFO: [APUAPC] D6_APC_1: 0xffffffff
9976 23:51:09.148896 INFO: [APUAPC] D6_APC_2: 0x3fffff
9977 23:51:09.151858 INFO: [APUAPC] D6_APC_3: 0x0
9978 23:51:09.155349 INFO: [APUAPC] D7_APC_0: 0xffffffff
9979 23:51:09.158334 INFO: [APUAPC] D7_APC_1: 0xffffffff
9980 23:51:09.162406 INFO: [APUAPC] D7_APC_2: 0x3fffff
9981 23:51:09.165187 INFO: [APUAPC] D7_APC_3: 0x0
9982 23:51:09.168573 INFO: [APUAPC] D8_APC_0: 0xffffffff
9983 23:51:09.172040 INFO: [APUAPC] D8_APC_1: 0xffffffff
9984 23:51:09.174999 INFO: [APUAPC] D8_APC_2: 0x3fffff
9985 23:51:09.178944 INFO: [APUAPC] D8_APC_3: 0x0
9986 23:51:09.181925 INFO: [APUAPC] D9_APC_0: 0xffffffff
9987 23:51:09.184796 INFO: [APUAPC] D9_APC_1: 0xffffffff
9988 23:51:09.188329 INFO: [APUAPC] D9_APC_2: 0x3fffff
9989 23:51:09.191230 INFO: [APUAPC] D9_APC_3: 0x0
9990 23:51:09.195327 INFO: [APUAPC] D10_APC_0: 0xffffffff
9991 23:51:09.198459 INFO: [APUAPC] D10_APC_1: 0xffffffff
9992 23:51:09.201921 INFO: [APUAPC] D10_APC_2: 0x3fffff
9993 23:51:09.204846 INFO: [APUAPC] D10_APC_3: 0x0
9994 23:51:09.208255 INFO: [APUAPC] D11_APC_0: 0xffffffff
9995 23:51:09.211394 INFO: [APUAPC] D11_APC_1: 0xffffffff
9996 23:51:09.214957 INFO: [APUAPC] D11_APC_2: 0x3fffff
9997 23:51:09.218230 INFO: [APUAPC] D11_APC_3: 0x0
9998 23:51:09.221229 INFO: [APUAPC] D12_APC_0: 0xffffffff
9999 23:51:09.224874 INFO: [APUAPC] D12_APC_1: 0xffffffff
10000 23:51:09.227930 INFO: [APUAPC] D12_APC_2: 0x3fffff
10001 23:51:09.231242 INFO: [APUAPC] D12_APC_3: 0x0
10002 23:51:09.234760 INFO: [APUAPC] D13_APC_0: 0xffffffff
10003 23:51:09.238179 INFO: [APUAPC] D13_APC_1: 0xffffffff
10004 23:51:09.241219 INFO: [APUAPC] D13_APC_2: 0x3fffff
10005 23:51:09.244829 INFO: [APUAPC] D13_APC_3: 0x0
10006 23:51:09.247795 INFO: [APUAPC] D14_APC_0: 0xffffffff
10007 23:51:09.251757 INFO: [APUAPC] D14_APC_1: 0xffffffff
10008 23:51:09.254050 INFO: [APUAPC] D14_APC_2: 0x3fffff
10009 23:51:09.257297 INFO: [APUAPC] D14_APC_3: 0x0
10010 23:51:09.260763 INFO: [APUAPC] D15_APC_0: 0xffffffff
10011 23:51:09.264277 INFO: [APUAPC] D15_APC_1: 0xffffffff
10012 23:51:09.268405 INFO: [APUAPC] D15_APC_2: 0x3fffff
10013 23:51:09.270617 INFO: [APUAPC] D15_APC_3: 0x0
10014 23:51:09.273801 INFO: [APUAPC] APC_CON: 0x4
10015 23:51:09.277164 INFO: [NOCDAPC] D0_APC_0: 0x0
10016 23:51:09.280447 INFO: [NOCDAPC] D0_APC_1: 0x0
10017 23:51:09.283733 INFO: [NOCDAPC] D1_APC_0: 0x0
10018 23:51:09.286725 INFO: [NOCDAPC] D1_APC_1: 0xfff
10019 23:51:09.289778 INFO: [NOCDAPC] D2_APC_0: 0x0
10020 23:51:09.293305 INFO: [NOCDAPC] D2_APC_1: 0xfff
10021 23:51:09.296692 INFO: [NOCDAPC] D3_APC_0: 0x0
10022 23:51:09.297120 INFO: [NOCDAPC] D3_APC_1: 0xfff
10023 23:51:09.300650 INFO: [NOCDAPC] D4_APC_0: 0x0
10024 23:51:09.303223 INFO: [NOCDAPC] D4_APC_1: 0xfff
10025 23:51:09.306407 INFO: [NOCDAPC] D5_APC_0: 0x0
10026 23:51:09.309799 INFO: [NOCDAPC] D5_APC_1: 0xfff
10027 23:51:09.313386 INFO: [NOCDAPC] D6_APC_0: 0x0
10028 23:51:09.316246 INFO: [NOCDAPC] D6_APC_1: 0xfff
10029 23:51:09.319604 INFO: [NOCDAPC] D7_APC_0: 0x0
10030 23:51:09.322839 INFO: [NOCDAPC] D7_APC_1: 0xfff
10031 23:51:09.326358 INFO: [NOCDAPC] D8_APC_0: 0x0
10032 23:51:09.329560 INFO: [NOCDAPC] D8_APC_1: 0xfff
10033 23:51:09.333053 INFO: [NOCDAPC] D9_APC_0: 0x0
10034 23:51:09.333513 INFO: [NOCDAPC] D9_APC_1: 0xfff
10035 23:51:09.336460 INFO: [NOCDAPC] D10_APC_0: 0x0
10036 23:51:09.339326 INFO: [NOCDAPC] D10_APC_1: 0xfff
10037 23:51:09.343192 INFO: [NOCDAPC] D11_APC_0: 0x0
10038 23:51:09.346416 INFO: [NOCDAPC] D11_APC_1: 0xfff
10039 23:51:09.349080 INFO: [NOCDAPC] D12_APC_0: 0x0
10040 23:51:09.352893 INFO: [NOCDAPC] D12_APC_1: 0xfff
10041 23:51:09.355713 INFO: [NOCDAPC] D13_APC_0: 0x0
10042 23:51:09.359084 INFO: [NOCDAPC] D13_APC_1: 0xfff
10043 23:51:09.362967 INFO: [NOCDAPC] D14_APC_0: 0x0
10044 23:51:09.366285 INFO: [NOCDAPC] D14_APC_1: 0xfff
10045 23:51:09.369359 INFO: [NOCDAPC] D15_APC_0: 0x0
10046 23:51:09.372759 INFO: [NOCDAPC] D15_APC_1: 0xfff
10047 23:51:09.375731 INFO: [NOCDAPC] APC_CON: 0x4
10048 23:51:09.379009 INFO: [APUAPC] set_apusys_apc done
10049 23:51:09.382775 INFO: [DEVAPC] devapc_init done
10050 23:51:09.385234 INFO: GICv3 without legacy support detected.
10051 23:51:09.388861 INFO: ARM GICv3 driver initialized in EL3
10052 23:51:09.392185 INFO: Maximum SPI INTID supported: 639
10053 23:51:09.395430 INFO: BL31: Initializing runtime services
10054 23:51:09.402096 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10055 23:51:09.405337 INFO: SPM: enable CPC mode
10056 23:51:09.411777 INFO: mcdi ready for mcusys-off-idle and system suspend
10057 23:51:09.414844 INFO: BL31: Preparing for EL3 exit to normal world
10058 23:51:09.418226 INFO: Entry point address = 0x80000000
10059 23:51:09.421596 INFO: SPSR = 0x8
10060 23:51:09.426655
10061 23:51:09.427080
10062 23:51:09.427414
10063 23:51:09.429990 Starting depthcharge on Spherion...
10064 23:51:09.430420
10065 23:51:09.430755 Wipe memory regions:
10066 23:51:09.431072
10067 23:51:09.433493 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10068 23:51:09.434027 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10069 23:51:09.434452 Setting prompt string to ['asurada:']
10070 23:51:09.434866 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10071 23:51:09.435529 [0x00000040000000, 0x00000054600000)
10072 23:51:09.555052
10073 23:51:09.555254 [0x00000054660000, 0x00000080000000)
10074 23:51:09.816351
10075 23:51:09.816916 [0x000000821a7280, 0x000000ffe64000)
10076 23:51:10.561356
10077 23:51:10.562049 [0x00000100000000, 0x00000240000000)
10078 23:51:12.451516
10079 23:51:12.454743 Initializing XHCI USB controller at 0x11200000.
10080 23:51:13.493239
10081 23:51:13.495981 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10082 23:51:13.496444
10083 23:51:13.496815
10084 23:51:13.497613 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 23:51:13.598736 asurada: tftpboot 192.168.201.1 14084322/tftp-deploy-lr3_8_9e/kernel/image.itb 14084322/tftp-deploy-lr3_8_9e/kernel/cmdline
10087 23:51:13.599266 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 23:51:13.599661 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10089 23:51:13.604118 tftpboot 192.168.201.1 14084322/tftp-deploy-lr3_8_9e/kernel/image.ittp-deploy-lr3_8_9e/kernel/cmdline
10090 23:51:13.604551
10091 23:51:13.604893 Waiting for link
10092 23:51:13.762550
10093 23:51:13.763164 R8152: Initializing
10094 23:51:13.763520
10095 23:51:13.766217 Version 6 (ocp_data = 5c30)
10096 23:51:13.766642
10097 23:51:13.768905 R8152: Done initializing
10098 23:51:13.769381
10099 23:51:13.769730 Adding net device
10100 23:51:15.735203
10101 23:51:15.735774 done.
10102 23:51:15.736152
10103 23:51:15.736500 MAC: 00:24:32:30:7c:7b
10104 23:51:15.737050
10105 23:51:15.737931 Sending DHCP discover... done.
10106 23:51:15.738341
10107 23:51:15.741958 Waiting for reply... done.
10108 23:51:15.742445
10109 23:51:15.744697 Sending DHCP request... done.
10110 23:51:15.745140
10111 23:51:15.750875 Waiting for reply... done.
10112 23:51:15.751306
10113 23:51:15.751668 My ip is 192.168.201.14
10114 23:51:15.751986
10115 23:51:15.754317 The DHCP server ip is 192.168.201.1
10116 23:51:15.754838
10117 23:51:15.760439 TFTP server IP predefined by user: 192.168.201.1
10118 23:51:15.760948
10119 23:51:15.767146 Bootfile predefined by user: 14084322/tftp-deploy-lr3_8_9e/kernel/image.itb
10120 23:51:15.767607
10121 23:51:15.770052 Sending tftp read request... done.
10122 23:51:15.770481
10123 23:51:15.776597 Waiting for the transfer...
10124 23:51:15.777186
10125 23:51:16.390186 00000000 ################################################################
10126 23:51:16.390319
10127 23:51:16.953522 00080000 ################################################################
10128 23:51:16.953687
10129 23:51:17.509086 00100000 ################################################################
10130 23:51:17.509250
10131 23:51:18.062375 00180000 ################################################################
10132 23:51:18.062527
10133 23:51:18.641385 00200000 ################################################################
10134 23:51:18.641550
10135 23:51:19.203903 00280000 ################################################################
10136 23:51:19.204066
10137 23:51:19.772288 00300000 ################################################################
10138 23:51:19.772447
10139 23:51:20.336842 00380000 ################################################################
10140 23:51:20.336992
10141 23:51:20.886049 00400000 ################################################################
10142 23:51:20.886189
10143 23:51:21.430106 00480000 ################################################################
10144 23:51:21.430248
10145 23:51:21.973985 00500000 ################################################################
10146 23:51:21.974147
10147 23:51:22.509950 00580000 ################################################################
10148 23:51:22.510102
10149 23:51:23.057911 00600000 ################################################################
10150 23:51:23.058057
10151 23:51:23.609911 00680000 ################################################################
10152 23:51:23.610058
10153 23:51:24.172358 00700000 ################################################################
10154 23:51:24.172496
10155 23:51:24.739944 00780000 ################################################################
10156 23:51:24.740097
10157 23:51:25.289403 00800000 ################################################################
10158 23:51:25.289549
10159 23:51:25.822673 00880000 ################################################################
10160 23:51:25.822823
10161 23:51:26.362384 00900000 ################################################################
10162 23:51:26.362537
10163 23:51:26.887646 00980000 ################################################################
10164 23:51:26.887799
10165 23:51:27.408653 00a00000 ################################################################
10166 23:51:27.408801
10167 23:51:27.933007 00a80000 ################################################################
10168 23:51:27.933162
10169 23:51:28.459592 00b00000 ################################################################
10170 23:51:28.459743
10171 23:51:28.998434 00b80000 ################################################################
10172 23:51:28.998612
10173 23:51:29.519663 00c00000 ################################################################
10174 23:51:29.519815
10175 23:51:30.062184 00c80000 ################################################################
10176 23:51:30.062340
10177 23:51:30.591045 00d00000 ################################################################
10178 23:51:30.591203
10179 23:51:31.131597 00d80000 ################################################################
10180 23:51:31.131749
10181 23:51:31.678248 00e00000 ################################################################
10182 23:51:31.678391
10183 23:51:32.206268 00e80000 ################################################################
10184 23:51:32.206418
10185 23:51:32.764175 00f00000 ################################################################
10186 23:51:32.764312
10187 23:51:33.308786 00f80000 ################################################################
10188 23:51:33.308926
10189 23:51:33.869733 01000000 ################################################################
10190 23:51:33.869907
10191 23:51:34.437855 01080000 ################################################################
10192 23:51:34.438012
10193 23:51:35.002111 01100000 ################################################################
10194 23:51:35.002273
10195 23:51:35.605148 01180000 ################################################################
10196 23:51:35.605345
10197 23:51:36.175626 01200000 ################################################################
10198 23:51:36.175784
10199 23:51:36.774082 01280000 ################################################################
10200 23:51:36.774243
10201 23:51:37.350610 01300000 ################################################################
10202 23:51:37.350771
10203 23:51:37.944039 01380000 ################################################################
10204 23:51:37.944200
10205 23:51:38.528391 01400000 ################################################################
10206 23:51:38.528555
10207 23:51:39.124191 01480000 ################################################################
10208 23:51:39.124353
10209 23:51:39.714494 01500000 ################################################################
10210 23:51:39.714657
10211 23:51:40.308149 01580000 ################################################################
10212 23:51:40.308308
10213 23:51:40.900606 01600000 ################################################################
10214 23:51:40.900762
10215 23:51:41.490134 01680000 ################################################################
10216 23:51:41.490293
10217 23:51:42.082165 01700000 ################################################################
10218 23:51:42.082322
10219 23:51:42.660278 01780000 ################################################################
10220 23:51:42.660436
10221 23:51:43.246934 01800000 ################################################################
10222 23:51:43.247091
10223 23:51:43.833754 01880000 ################################################################
10224 23:51:43.833907
10225 23:51:44.419983 01900000 ################################################################
10226 23:51:44.420138
10227 23:51:44.996403 01980000 ################################################################
10228 23:51:44.996562
10229 23:51:45.562225 01a00000 ################################################################
10230 23:51:45.562376
10231 23:51:46.119565 01a80000 ################################################################
10232 23:51:46.119703
10233 23:51:46.682344 01b00000 ################################################################
10234 23:51:46.682495
10235 23:51:47.261911 01b80000 ################################################################
10236 23:51:47.262063
10237 23:51:47.857413 01c00000 ################################################################
10238 23:51:47.857572
10239 23:51:48.442244 01c80000 ################################################################
10240 23:51:48.442387
10241 23:51:48.992505 01d00000 ################################################################
10242 23:51:48.992656
10243 23:51:49.614401 01d80000 ################################################################
10244 23:51:49.614540
10245 23:51:50.039772 01e00000 ############################################## done.
10246 23:51:50.040280
10247 23:51:50.043265 The bootfile was 31831682 bytes long.
10248 23:51:50.043825
10249 23:51:50.046393 Sending tftp read request... done.
10250 23:51:50.047027
10251 23:51:50.050179 Waiting for the transfer...
10252 23:51:50.050606
10253 23:51:50.050943 00000000 # done.
10254 23:51:50.051269
10255 23:51:50.057647 Command line loaded dynamically from TFTP file: 14084322/tftp-deploy-lr3_8_9e/kernel/cmdline
10256 23:51:50.058077
10257 23:51:50.079919 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10258 23:51:50.080365
10259 23:51:50.080706 Loading FIT.
10260 23:51:50.083224
10261 23:51:50.083696 Image ramdisk-1 has 18718904 bytes.
10262 23:51:50.086777
10263 23:51:50.087198 Image fdt-1 has 47258 bytes.
10264 23:51:50.087535
10265 23:51:50.090006 Image kernel-1 has 13063488 bytes.
10266 23:51:50.090429
10267 23:51:50.099700 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 23:51:50.100137
10269 23:51:50.116581 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 23:51:50.117074
10271 23:51:50.123252 Choosing best match conf-1 for compat google,spherion-rev2.
10272 23:51:50.126958
10273 23:51:50.131485 Connected to device vid:did:rid of 1ae0:0028:00
10274 23:51:50.139522
10275 23:51:50.143021 tpm_get_response: command 0x17b, return code 0x0
10276 23:51:50.143466
10277 23:51:50.145800 ec_init: CrosEC protocol v3 supported (256, 248)
10278 23:51:50.149672
10279 23:51:50.153119 tpm_cleanup: add release locality here.
10280 23:51:50.153594
10281 23:51:50.153963 Shutting down all USB controllers.
10282 23:51:50.156354
10283 23:51:50.156777 Removing current net device
10284 23:51:50.157138
10285 23:51:50.162891 Exiting depthcharge with code 4 at timestamp: 69981553
10286 23:51:50.163314
10287 23:51:50.166637 LZMA decompressing kernel-1 to 0x821a6718
10288 23:51:50.167061
10289 23:51:50.169565 LZMA decompressing kernel-1 to 0x40000000
10290 23:51:51.780176
10291 23:51:51.780691 jumping to kernel
10292 23:51:51.782413 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10293 23:51:51.782920 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10294 23:51:51.783325 Setting prompt string to ['Linux version [0-9]']
10295 23:51:51.783702 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 23:51:51.784074 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 23:51:51.863247
10298 23:51:51.865912 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 23:51:51.869712 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10300 23:51:51.870242 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 23:51:51.870629 Setting prompt string to []
10302 23:51:51.871019 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10303 23:51:51.871451 Using line separator: #'\n'#
10304 23:51:51.871764 No login prompt set.
10305 23:51:51.872095 Parsing kernel messages
10306 23:51:51.872448 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10307 23:51:51.873044 [login-action] Waiting for messages, (timeout 00:03:44)
10308 23:51:51.873470 Waiting using forced prompt support (timeout 00:01:52)
10309 23:51:51.889127 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10310 23:51:51.892986 [ 0.000000] random: crng init done
10311 23:51:51.899350 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 23:51:51.902568 [ 0.000000] efi: UEFI not found.
10313 23:51:51.909075 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 23:51:51.915577 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 23:51:51.925614 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 23:51:51.935848 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 23:51:51.942334 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 23:51:51.948702 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 23:51:51.955549 [ 0.000000] NUMA: No NUMA configuration found
10320 23:51:51.962121 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 23:51:51.965623 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10322 23:51:51.968586 [ 0.000000] Zone ranges:
10323 23:51:51.975333 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 23:51:51.978443 [ 0.000000] DMA32 empty
10325 23:51:51.985831 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 23:51:51.989093 [ 0.000000] Movable zone start for each node
10327 23:51:51.991716 [ 0.000000] Early memory node ranges
10328 23:51:51.998485 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 23:51:52.004966 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 23:51:52.011964 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 23:51:52.018356 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 23:51:52.025185 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 23:51:52.031497 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 23:51:52.087758 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 23:51:52.093876 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 23:51:52.100822 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 23:51:52.104474 [ 0.000000] psci: probing for conduit method from DT.
10338 23:51:52.110645 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 23:51:52.114466 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 23:51:52.121027 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 23:51:52.124646 [ 0.000000] psci: SMC Calling Convention v1.2
10342 23:51:52.130822 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10343 23:51:52.134456 [ 0.000000] Detected VIPT I-cache on CPU0
10344 23:51:52.140456 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 23:51:52.147413 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 23:51:52.154236 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 23:51:52.160619 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 23:51:52.167516 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 23:51:52.177495 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 23:51:52.180229 [ 0.000000] alternatives: applying boot alternatives
10351 23:51:52.186954 [ 0.000000] Fallback order for Node 0: 0
10352 23:51:52.193582 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 23:51:52.196642 [ 0.000000] Policy zone: Normal
10354 23:51:52.220540 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10355 23:51:52.230400 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 23:51:52.241108 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 23:51:52.250705 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 23:51:52.257446 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 23:51:52.260977 <6>[ 0.000000] software IO TLB: area num 8.
10360 23:51:52.317318 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 23:51:52.467127 <6>[ 0.000000] Memory: 7945908K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406860K reserved, 32768K cma-reserved)
10362 23:51:52.474111 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 23:51:52.480664 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 23:51:52.483840 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 23:51:52.490674 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 23:51:52.497056 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 23:51:52.500206 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 23:51:52.510189 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 23:51:52.516980 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 23:51:52.524083 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 23:51:52.530225 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 23:51:52.533836 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 23:51:52.536710 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 23:51:52.542805 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 23:51:52.546056 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 23:51:52.552866 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 23:51:52.566117 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 23:51:52.575775 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 23:51:52.586303 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 23:51:52.593163 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 23:51:52.606480 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 23:51:52.613026 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 23:51:52.620178 <6>[ 0.009180] Console: colour dummy device 80x25
10384 23:51:52.630473 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 23:51:52.636418 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10386 23:51:52.639993 <6>[ 0.029241] LSM: Security Framework initializing
10387 23:51:52.646353 <6>[ 0.034180] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 23:51:52.656647 <6>[ 0.041995] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 23:51:52.663021 <6>[ 0.051415] cblist_init_generic: Setting adjustable number of callback queues.
10390 23:51:52.670329 <6>[ 0.058859] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 23:51:52.679989 <6>[ 0.065198] cblist_init_generic: Setting adjustable number of callback queues.
10392 23:51:52.683215 <6>[ 0.072670] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 23:51:52.689936 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10394 23:51:52.696503 <6>[ 0.084127] rcu: Max phase no-delay instances is 1000.
10395 23:51:52.703261 <6>[ 0.091160] EFI services will not be available.
10396 23:51:52.706238 <6>[ 0.096145] smp: Bringing up secondary CPUs ...
10397 23:51:52.714161 <6>[ 0.101191] Detected VIPT I-cache on CPU1
10398 23:51:52.720557 <6>[ 0.101263] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10399 23:51:52.727310 <6>[ 0.101292] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10400 23:51:52.730863 <6>[ 0.101624] Detected VIPT I-cache on CPU2
10401 23:51:52.737696 <6>[ 0.101674] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10402 23:51:52.743972 <6>[ 0.101691] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10403 23:51:52.750725 <6>[ 0.101947] Detected VIPT I-cache on CPU3
10404 23:51:52.757644 <6>[ 0.101994] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10405 23:51:52.763892 <6>[ 0.102008] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10406 23:51:52.767703 <6>[ 0.102311] CPU features: detected: Spectre-v4
10407 23:51:52.774541 <6>[ 0.102318] CPU features: detected: Spectre-BHB
10408 23:51:52.778162 <6>[ 0.102323] Detected PIPT I-cache on CPU4
10409 23:51:52.784317 <6>[ 0.102379] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10410 23:51:52.791151 <6>[ 0.102395] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10411 23:51:52.797832 <6>[ 0.102689] Detected PIPT I-cache on CPU5
10412 23:51:52.804575 <6>[ 0.102752] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10413 23:51:52.810773 <6>[ 0.102768] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10414 23:51:52.814044 <6>[ 0.103050] Detected PIPT I-cache on CPU6
10415 23:51:52.820796 <6>[ 0.103114] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10416 23:51:52.827653 <6>[ 0.103130] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10417 23:51:52.834126 <6>[ 0.103426] Detected PIPT I-cache on CPU7
10418 23:51:52.840522 <6>[ 0.103490] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10419 23:51:52.847042 <6>[ 0.103506] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10420 23:51:52.850666 <6>[ 0.103552] smp: Brought up 1 node, 8 CPUs
10421 23:51:52.857100 <6>[ 0.244881] SMP: Total of 8 processors activated.
10422 23:51:52.860219 <6>[ 0.249802] CPU features: detected: 32-bit EL0 Support
10423 23:51:52.870181 <6>[ 0.255199] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10424 23:51:52.876817 <6>[ 0.264054] CPU features: detected: Common not Private translations
10425 23:51:52.880168 <6>[ 0.270570] CPU features: detected: CRC32 instructions
10426 23:51:52.886695 <6>[ 0.275921] CPU features: detected: RCpc load-acquire (LDAPR)
10427 23:51:52.893183 <6>[ 0.281881] CPU features: detected: LSE atomic instructions
10428 23:51:52.899806 <6>[ 0.287662] CPU features: detected: Privileged Access Never
10429 23:51:52.903216 <6>[ 0.293442] CPU features: detected: RAS Extension Support
10430 23:51:52.913211 <6>[ 0.299051] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10431 23:51:52.916561 <6>[ 0.306271] CPU: All CPU(s) started at EL2
10432 23:51:52.923346 <6>[ 0.310614] alternatives: applying system-wide alternatives
10433 23:51:52.932395 <6>[ 0.321506] devtmpfs: initialized
10434 23:51:52.947472 <6>[ 0.330392] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10435 23:51:52.954686 <6>[ 0.340353] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10436 23:51:52.960927 <6>[ 0.348365] pinctrl core: initialized pinctrl subsystem
10437 23:51:52.964381 <6>[ 0.355013] DMI not present or invalid.
10438 23:51:52.971101 <6>[ 0.359419] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10439 23:51:52.980867 <6>[ 0.366218] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10440 23:51:52.987967 <6>[ 0.373805] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10441 23:51:52.997935 <6>[ 0.382022] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10442 23:51:53.001233 <6>[ 0.390263] audit: initializing netlink subsys (disabled)
10443 23:51:53.011061 <5>[ 0.395958] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10444 23:51:53.018022 <6>[ 0.396656] thermal_sys: Registered thermal governor 'step_wise'
10445 23:51:53.024158 <6>[ 0.403925] thermal_sys: Registered thermal governor 'power_allocator'
10446 23:51:53.027478 <6>[ 0.410179] cpuidle: using governor menu
10447 23:51:53.030907 <6>[ 0.421135] NET: Registered PF_QIPCRTR protocol family
10448 23:51:53.040781 <6>[ 0.426623] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10449 23:51:53.044253 <6>[ 0.433723] ASID allocator initialised with 32768 entries
10450 23:51:53.051025 <6>[ 0.440294] Serial: AMBA PL011 UART driver
10451 23:51:53.060393 <4>[ 0.449064] Trying to register duplicate clock ID: 134
10452 23:51:53.118203 <6>[ 0.510606] KASLR enabled
10453 23:51:53.132691 <6>[ 0.518342] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 23:51:53.139211 <6>[ 0.525358] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 23:51:53.145903 <6>[ 0.531848] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 23:51:53.152699 <6>[ 0.538851] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 23:51:53.159048 <6>[ 0.545338] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 23:51:53.165811 <6>[ 0.552343] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 23:51:53.172998 <6>[ 0.558832] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 23:51:53.178917 <6>[ 0.565834] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 23:51:53.182213 <6>[ 0.573354] ACPI: Interpreter disabled.
10462 23:51:53.190493 <6>[ 0.579782] iommu: Default domain type: Translated
10463 23:51:53.197366 <6>[ 0.584888] iommu: DMA domain TLB invalidation policy: strict mode
10464 23:51:53.200844 <5>[ 0.591544] SCSI subsystem initialized
10465 23:51:53.206955 <6>[ 0.595714] usbcore: registered new interface driver usbfs
10466 23:51:53.213913 <6>[ 0.601448] usbcore: registered new interface driver hub
10467 23:51:53.217424 <6>[ 0.606998] usbcore: registered new device driver usb
10468 23:51:53.224305 <6>[ 0.613092] pps_core: LinuxPPS API ver. 1 registered
10469 23:51:53.233845 <6>[ 0.618283] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10470 23:51:53.237335 <6>[ 0.627628] PTP clock support registered
10471 23:51:53.240500 <6>[ 0.631869] EDAC MC: Ver: 3.0.0
10472 23:51:53.248044 <6>[ 0.637022] FPGA manager framework
10473 23:51:53.254748 <6>[ 0.640707] Advanced Linux Sound Architecture Driver Initialized.
10474 23:51:53.257952 <6>[ 0.647481] vgaarb: loaded
10475 23:51:53.264946 <6>[ 0.650638] clocksource: Switched to clocksource arch_sys_counter
10476 23:51:53.267967 <5>[ 0.657083] VFS: Disk quotas dquot_6.6.0
10477 23:51:53.274105 <6>[ 0.661267] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10478 23:51:53.277444 <6>[ 0.668454] pnp: PnP ACPI: disabled
10479 23:51:53.285882 <6>[ 0.675121] NET: Registered PF_INET protocol family
10480 23:51:53.295410 <6>[ 0.680719] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10481 23:51:53.307249 <6>[ 0.693053] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10482 23:51:53.317546 <6>[ 0.701872] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10483 23:51:53.323915 <6>[ 0.709845] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10484 23:51:53.333675 <6>[ 0.718542] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10485 23:51:53.340271 <6>[ 0.728297] TCP: Hash tables configured (established 65536 bind 65536)
10486 23:51:53.346476 <6>[ 0.735161] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 23:51:53.356344 <6>[ 0.742359] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 23:51:53.363649 <6>[ 0.750058] NET: Registered PF_UNIX/PF_LOCAL protocol family
10489 23:51:53.369704 <6>[ 0.756215] RPC: Registered named UNIX socket transport module.
10490 23:51:53.373102 <6>[ 0.762369] RPC: Registered udp transport module.
10491 23:51:53.379718 <6>[ 0.767301] RPC: Registered tcp transport module.
10492 23:51:53.386476 <6>[ 0.772231] RPC: Registered tcp NFSv4.1 backchannel transport module.
10493 23:51:53.389795 <6>[ 0.778897] PCI: CLS 0 bytes, default 64
10494 23:51:53.392920 <6>[ 0.783221] Unpacking initramfs...
10495 23:51:53.409336 <6>[ 0.795196] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10496 23:51:53.419192 <6>[ 0.803863] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10497 23:51:53.422523 <6>[ 0.812710] kvm [1]: IPA Size Limit: 40 bits
10498 23:51:53.429335 <6>[ 0.817240] kvm [1]: GICv3: no GICV resource entry
10499 23:51:53.432751 <6>[ 0.822260] kvm [1]: disabling GICv2 emulation
10500 23:51:53.439390 <6>[ 0.826945] kvm [1]: GIC system register CPU interface enabled
10501 23:51:53.442329 <6>[ 0.833101] kvm [1]: vgic interrupt IRQ18
10502 23:51:53.449322 <6>[ 0.837453] kvm [1]: VHE mode initialized successfully
10503 23:51:53.455401 <5>[ 0.843987] Initialise system trusted keyrings
10504 23:51:53.462243 <6>[ 0.848806] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10505 23:51:53.469496 <6>[ 0.858896] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10506 23:51:53.476890 <5>[ 0.865301] NFS: Registering the id_resolver key type
10507 23:51:53.480034 <5>[ 0.870601] Key type id_resolver registered
10508 23:51:53.486347 <5>[ 0.875012] Key type id_legacy registered
10509 23:51:53.492985 <6>[ 0.879292] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10510 23:51:53.499579 <6>[ 0.886208] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10511 23:51:53.506059 <6>[ 0.893927] 9p: Installing v9fs 9p2000 file system support
10512 23:51:53.543048 <5>[ 0.931815] Key type asymmetric registered
10513 23:51:53.545819 <5>[ 0.936147] Asymmetric key parser 'x509' registered
10514 23:51:53.556255 <6>[ 0.941290] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10515 23:51:53.559996 <6>[ 0.948906] io scheduler mq-deadline registered
10516 23:51:53.562380 <6>[ 0.953686] io scheduler kyber registered
10517 23:51:53.581363 <6>[ 0.970704] EINJ: ACPI disabled.
10518 23:51:53.614276 <4>[ 0.996572] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 23:51:53.624071 <4>[ 1.007206] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 23:51:53.639425 <6>[ 1.027990] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10521 23:51:53.646616 <6>[ 1.035957] printk: console [ttyS0] disabled
10522 23:51:53.675061 <6>[ 1.060586] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10523 23:51:53.681302 <6>[ 1.070052] printk: console [ttyS0] enabled
10524 23:51:53.684645 <6>[ 1.070052] printk: console [ttyS0] enabled
10525 23:51:53.691444 <6>[ 1.078947] printk: bootconsole [mtk8250] disabled
10526 23:51:53.694856 <6>[ 1.078947] printk: bootconsole [mtk8250] disabled
10527 23:51:53.701341 <6>[ 1.090016] SuperH (H)SCI(F) driver initialized
10528 23:51:53.704900 <6>[ 1.095290] msm_serial: driver initialized
10529 23:51:53.718561 <6>[ 1.104173] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10530 23:51:53.728594 <6>[ 1.112720] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10531 23:51:53.734950 <6>[ 1.121264] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10532 23:51:53.745093 <6>[ 1.129891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10533 23:51:53.754763 <6>[ 1.138597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10534 23:51:53.761252 <6>[ 1.147314] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10535 23:51:53.771362 <6>[ 1.155861] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10536 23:51:53.778291 <6>[ 1.164657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10537 23:51:53.787773 <6>[ 1.173198] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10538 23:51:53.799628 <6>[ 1.188618] loop: module loaded
10539 23:51:53.806171 <6>[ 1.194474] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10540 23:51:53.828540 <4>[ 1.217843] mtk-pmic-keys: Failed to locate of_node [id: -1]
10541 23:51:53.835608 <6>[ 1.224643] megasas: 07.719.03.00-rc1
10542 23:51:53.845035 <6>[ 1.234277] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10543 23:51:53.856829 <6>[ 1.246028] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10544 23:51:53.873730 <6>[ 1.262521] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10545 23:51:53.929666 <6>[ 1.312350] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10546 23:51:54.187224 <6>[ 1.576143] Freeing initrd memory: 18276K
10547 23:51:54.198389 <6>[ 1.587843] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10548 23:51:54.209429 <6>[ 1.598702] tun: Universal TUN/TAP device driver, 1.6
10549 23:51:54.212929 <6>[ 1.604758] thunder_xcv, ver 1.0
10550 23:51:54.216573 <6>[ 1.608264] thunder_bgx, ver 1.0
10551 23:51:54.219331 <6>[ 1.611762] nicpf, ver 1.0
10552 23:51:54.229952 <6>[ 1.615765] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10553 23:51:54.233211 <6>[ 1.623241] hns3: Copyright (c) 2017 Huawei Corporation.
10554 23:51:54.239634 <6>[ 1.628827] hclge is initializing
10555 23:51:54.243154 <6>[ 1.632407] e1000: Intel(R) PRO/1000 Network Driver
10556 23:51:54.250187 <6>[ 1.637536] e1000: Copyright (c) 1999-2006 Intel Corporation.
10557 23:51:54.253364 <6>[ 1.643550] e1000e: Intel(R) PRO/1000 Network Driver
10558 23:51:54.260247 <6>[ 1.648765] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10559 23:51:54.267104 <6>[ 1.654949] igb: Intel(R) Gigabit Ethernet Network Driver
10560 23:51:54.273145 <6>[ 1.660599] igb: Copyright (c) 2007-2014 Intel Corporation.
10561 23:51:54.279710 <6>[ 1.666435] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 23:51:54.286203 <6>[ 1.672953] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 23:51:54.289765 <6>[ 1.679416] sky2: driver version 1.30
10564 23:51:54.296271 <6>[ 1.684334] usbcore: registered new device driver r8152-cfgselector
10565 23:51:54.303017 <6>[ 1.690872] usbcore: registered new interface driver r8152
10566 23:51:54.309357 <6>[ 1.696682] VFIO - User Level meta-driver version: 0.3
10567 23:51:54.316306 <6>[ 1.704899] usbcore: registered new interface driver usb-storage
10568 23:51:54.322368 <6>[ 1.711343] usbcore: registered new device driver onboard-usb-hub
10569 23:51:54.331630 <6>[ 1.720456] mt6397-rtc mt6359-rtc: registered as rtc0
10570 23:51:54.341297 <6>[ 1.725917] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:51:54 UTC (1717026714)
10571 23:51:54.344733 <6>[ 1.735475] i2c_dev: i2c /dev entries driver
10572 23:51:54.361781 <6>[ 1.747170] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10573 23:51:54.367786 <4>[ 1.755891] cpu cpu0: supply cpu not found, using dummy regulator
10574 23:51:54.375062 <4>[ 1.762314] cpu cpu1: supply cpu not found, using dummy regulator
10575 23:51:54.381889 <4>[ 1.768717] cpu cpu2: supply cpu not found, using dummy regulator
10576 23:51:54.387840 <4>[ 1.775118] cpu cpu3: supply cpu not found, using dummy regulator
10577 23:51:54.394305 <4>[ 1.781530] cpu cpu4: supply cpu not found, using dummy regulator
10578 23:51:54.401043 <4>[ 1.787934] cpu cpu5: supply cpu not found, using dummy regulator
10579 23:51:54.407773 <4>[ 1.794328] cpu cpu6: supply cpu not found, using dummy regulator
10580 23:51:54.414252 <4>[ 1.800721] cpu cpu7: supply cpu not found, using dummy regulator
10581 23:51:54.431734 <6>[ 1.821352] cpu cpu0: EM: created perf domain
10582 23:51:54.435140 <6>[ 1.826293] cpu cpu4: EM: created perf domain
10583 23:51:54.442738 <6>[ 1.831878] sdhci: Secure Digital Host Controller Interface driver
10584 23:51:54.448705 <6>[ 1.838312] sdhci: Copyright(c) Pierre Ossman
10585 23:51:54.455579 <6>[ 1.843266] Synopsys Designware Multimedia Card Interface Driver
10586 23:51:54.462301 <6>[ 1.849900] sdhci-pltfm: SDHCI platform and OF driver helper
10587 23:51:54.465946 <6>[ 1.850004] mmc0: CQHCI version 5.10
10588 23:51:54.472927 <6>[ 1.859978] ledtrig-cpu: registered to indicate activity on CPUs
10589 23:51:54.478841 <6>[ 1.867055] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10590 23:51:54.485716 <6>[ 1.874110] usbcore: registered new interface driver usbhid
10591 23:51:54.488722 <6>[ 1.879931] usbhid: USB HID core driver
10592 23:51:54.495697 <6>[ 1.884122] spi_master spi0: will run message pump with realtime priority
10593 23:51:54.540452 <6>[ 1.923553] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10594 23:51:54.560129 <6>[ 1.939349] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10595 23:51:54.563738 <6>[ 1.952932] mmc0: Command Queue Engine enabled
10596 23:51:54.570749 <6>[ 1.957700] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 23:51:54.577072 <6>[ 1.964633] cros-ec-spi spi0.0: Chrome EC device registered
10598 23:51:54.580076 <6>[ 1.964942] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 23:51:54.592574 <6>[ 1.981603] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 23:51:54.599579 <6>[ 1.988974] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10601 23:51:54.606615 <6>[ 1.994951] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10602 23:51:54.616553 <6>[ 1.999474] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10603 23:51:54.622628 <6>[ 2.000838] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10604 23:51:54.625992 <6>[ 2.010771] NET: Registered PF_PACKET protocol family
10605 23:51:54.632904 <6>[ 2.021395] 9pnet: Installing 9P2000 support
10606 23:51:54.636142 <5>[ 2.025958] Key type dns_resolver registered
10607 23:51:54.639948 <6>[ 2.030927] registered taskstats version 1
10608 23:51:54.645947 <5>[ 2.035312] Loading compiled-in X.509 certificates
10609 23:51:54.675629 <4>[ 2.057560] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 23:51:54.684935 <4>[ 2.068285] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 23:51:54.700166 <6>[ 2.089027] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10612 23:51:54.706549 <6>[ 2.095844] xhci-mtk 11200000.usb: xHCI Host Controller
10613 23:51:54.713450 <6>[ 2.101344] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10614 23:51:54.723026 <6>[ 2.109180] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10615 23:51:54.730063 <6>[ 2.118623] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10616 23:51:54.736948 <6>[ 2.124716] xhci-mtk 11200000.usb: xHCI Host Controller
10617 23:51:54.743196 <6>[ 2.130195] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10618 23:51:54.750006 <6>[ 2.137845] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10619 23:51:54.756580 <6>[ 2.145489] hub 1-0:1.0: USB hub found
10620 23:51:54.760117 <6>[ 2.149503] hub 1-0:1.0: 1 port detected
10621 23:51:54.766574 <6>[ 2.153784] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10622 23:51:54.773210 <6>[ 2.162319] hub 2-0:1.0: USB hub found
10623 23:51:54.776492 <6>[ 2.166327] hub 2-0:1.0: 1 port detected
10624 23:51:54.784517 <6>[ 2.173542] mtk-msdc 11f70000.mmc: Got CD GPIO
10625 23:51:54.802260 <6>[ 2.188119] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10626 23:51:54.808805 <6>[ 2.196247] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10627 23:51:54.818783 <4>[ 2.204175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10628 23:51:54.828537 <6>[ 2.213769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10629 23:51:54.835402 <6>[ 2.221854] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10630 23:51:54.841805 <6>[ 2.229884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10631 23:51:54.852144 <6>[ 2.237798] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10632 23:51:54.859069 <6>[ 2.245630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10633 23:51:54.868556 <6>[ 2.253452] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10634 23:51:54.878544 <6>[ 2.263853] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10635 23:51:54.885427 <6>[ 2.272214] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10636 23:51:54.895250 <6>[ 2.280578] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10637 23:51:54.901413 <6>[ 2.288917] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10638 23:51:54.911505 <6>[ 2.297266] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10639 23:51:54.921391 <6>[ 2.305604] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10640 23:51:54.928310 <6>[ 2.313953] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10641 23:51:54.937626 <6>[ 2.322292] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10642 23:51:54.944331 <6>[ 2.330642] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10643 23:51:54.954460 <6>[ 2.338981] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10644 23:51:54.960698 <6>[ 2.347319] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10645 23:51:54.970550 <6>[ 2.355662] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10646 23:51:54.977647 <6>[ 2.364000] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10647 23:51:54.986865 <6>[ 2.372338] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10648 23:51:54.993737 <6>[ 2.380676] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10649 23:51:54.999918 <6>[ 2.389420] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10650 23:51:55.007117 <6>[ 2.396597] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10651 23:51:55.013749 <6>[ 2.403366] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10652 23:51:55.023884 <6>[ 2.410134] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10653 23:51:55.030616 <6>[ 2.417057] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10654 23:51:55.036904 <6>[ 2.423905] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10655 23:51:55.046922 <6>[ 2.433043] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10656 23:51:55.056681 <6>[ 2.442188] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10657 23:51:55.066751 <6>[ 2.451488] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10658 23:51:55.076535 <6>[ 2.460957] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10659 23:51:55.086516 <6>[ 2.470423] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10660 23:51:55.092989 <6>[ 2.479543] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10661 23:51:55.103212 <6>[ 2.489009] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10662 23:51:55.113166 <6>[ 2.498128] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10663 23:51:55.123090 <6>[ 2.507424] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10664 23:51:55.133262 <6>[ 2.517585] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10665 23:51:55.142752 <6>[ 2.529116] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10666 23:51:55.149594 <6>[ 2.538734] Trying to probe devices needed for running init ...
10667 23:51:55.164653 <6>[ 2.551004] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10668 23:51:55.193071 <6>[ 2.582508] hub 2-1:1.0: USB hub found
10669 23:51:55.196234 <6>[ 2.586992] hub 2-1:1.0: 3 ports detected
10670 23:51:55.204814 <6>[ 2.594222] hub 2-1:1.0: USB hub found
10671 23:51:55.208434 <6>[ 2.598577] hub 2-1:1.0: 3 ports detected
10672 23:51:55.316714 <6>[ 2.702849] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10673 23:51:55.475371 <6>[ 2.864491] hub 1-1:1.0: USB hub found
10674 23:51:55.478473 <6>[ 2.868959] hub 1-1:1.0: 4 ports detected
10675 23:51:55.487632 <6>[ 2.876674] hub 1-1:1.0: USB hub found
10676 23:51:55.490707 <6>[ 2.881171] hub 1-1:1.0: 4 ports detected
10677 23:51:55.556734 <6>[ 2.943023] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10678 23:51:55.665181 <6>[ 3.051326] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10679 23:51:55.697264 <4>[ 3.083502] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10680 23:51:55.706825 <4>[ 3.092577] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10681 23:51:55.741638 <6>[ 3.131544] r8152 2-1.3:1.0 eth0: v1.12.13
10682 23:51:55.820961 <6>[ 3.206923] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10683 23:51:55.953217 <6>[ 3.342928] hub 1-1.4:1.0: USB hub found
10684 23:51:55.956890 <6>[ 3.347602] hub 1-1.4:1.0: 2 ports detected
10685 23:51:55.966977 <6>[ 3.356318] hub 1-1.4:1.0: USB hub found
10686 23:51:55.970219 <6>[ 3.360924] hub 1-1.4:1.0: 2 ports detected
10687 23:51:56.268418 <6>[ 3.654970] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10688 23:51:56.460917 <6>[ 3.846974] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10689 23:51:57.334579 <6>[ 4.723924] r8152 2-1.3:1.0 eth0: carrier on
10690 23:52:00.380777 <5>[ 4.754764] Sending DHCP requests .., OK
10691 23:52:00.387269 <6>[ 7.775306] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10692 23:52:00.390733 <6>[ 7.783629] IP-Config: Complete:
10693 23:52:00.403758 <6>[ 7.787126] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10694 23:52:00.410702 <6>[ 7.797833] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10695 23:52:00.420264 <6>[ 7.806451] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10696 23:52:00.423649 <6>[ 7.806461] nameserver0=192.168.201.1
10697 23:52:00.427287 <6>[ 7.818663] clk: Disabling unused clocks
10698 23:52:00.430615 <6>[ 7.824151] ALSA device list:
10699 23:52:00.437414 <6>[ 7.827424] No soundcards found.
10700 23:52:00.445148 <6>[ 7.834976] Freeing unused kernel memory: 8512K
10701 23:52:00.447974 <6>[ 7.839918] Run /init as init process
10702 23:52:00.457931 Loading, please wait...
10703 23:52:00.487825 Starting systemd-udevd version 252.22-1~deb12u1
10704 23:52:00.759075 <6>[ 8.145781] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10705 23:52:00.768798 <6>[ 8.158292] remoteproc remoteproc0: scp is available
10706 23:52:00.774781 <6>[ 8.163652] remoteproc remoteproc0: powering up scp
10707 23:52:00.781777 <6>[ 8.168790] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10708 23:52:00.788144 <6>[ 8.177319] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10709 23:52:00.810168 <3>[ 8.196797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 23:52:00.816919 <6>[ 8.199607] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10711 23:52:00.826716 <3>[ 8.204965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 23:52:00.833523 <6>[ 8.212542] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10713 23:52:00.843407 <3>[ 8.220592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:52:00.850393 <4>[ 8.225634] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10715 23:52:00.859954 <6>[ 8.229353] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10716 23:52:00.872646 <4>[ 8.259221] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10717 23:52:00.880019 <3>[ 8.259492] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 23:52:00.885671 <6>[ 8.268149] mc: Linux media interface: v0.10
10719 23:52:00.892321 <3>[ 8.274771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 23:52:00.899626 <3>[ 8.274781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 23:52:00.908997 <3>[ 8.274790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:52:00.915648 <3>[ 8.274795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 23:52:00.925678 <3>[ 8.274878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 23:52:00.932073 <3>[ 8.274934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 23:52:00.942483 <3>[ 8.274939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 23:52:00.948611 <3>[ 8.274942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 23:52:00.958579 <3>[ 8.274995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 23:52:00.965317 <6>[ 8.308485] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10729 23:52:00.971616 <6>[ 8.308540] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10730 23:52:00.978235 <6>[ 8.308548] remoteproc remoteproc0: remote processor scp is now up
10731 23:52:00.988822 <3>[ 8.311805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 23:52:00.995497 <3>[ 8.311811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 23:52:01.004648 <3>[ 8.311817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 23:52:01.011935 <6>[ 8.387006] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10735 23:52:01.018134 <3>[ 8.390363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 23:52:01.024890 <6>[ 8.392466] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10737 23:52:01.031502 <6>[ 8.392475] pci_bus 0000:00: root bus resource [bus 00-ff]
10738 23:52:01.038237 <6>[ 8.392479] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10739 23:52:01.048135 <6>[ 8.392482] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10740 23:52:01.054737 <6>[ 8.392514] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10741 23:52:01.061335 <6>[ 8.392529] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10742 23:52:01.068429 <6>[ 8.392599] pci 0000:00:00.0: supports D1 D2
10743 23:52:01.074840 <6>[ 8.392601] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10744 23:52:01.084812 <6>[ 8.392848] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10745 23:52:01.087821 <6>[ 8.393704] videodev: Linux video capture interface: v2.00
10746 23:52:01.098118 <6>[ 8.396133] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10747 23:52:01.104811 <6>[ 8.396576] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10748 23:52:01.111838 <6>[ 8.396610] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10749 23:52:01.118076 <6>[ 8.396633] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10750 23:52:01.124731 <6>[ 8.396648] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10751 23:52:01.131518 <6>[ 8.396768] pci 0000:01:00.0: supports D1 D2
10752 23:52:01.138061 <6>[ 8.396771] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10753 23:52:01.144817 <6>[ 8.406750] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10754 23:52:01.151182 <6>[ 8.407442] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10755 23:52:01.161515 <6>[ 8.409246] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10756 23:52:01.170892 <4>[ 8.412843] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10757 23:52:01.174616 <4>[ 8.412843] Fallback method does not support PEC.
10758 23:52:01.181432 <3>[ 8.414178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 23:52:01.190834 <6>[ 8.421051] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10760 23:52:01.200908 <3>[ 8.428333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10761 23:52:01.207319 <6>[ 8.434413] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10762 23:52:01.217482 <6>[ 8.460329] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10763 23:52:01.227482 <6>[ 8.462175] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10764 23:52:01.234167 <6>[ 8.469593] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10765 23:52:01.244028 <6>[ 8.478333] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10766 23:52:01.250189 <6>[ 8.478346] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10767 23:52:01.260680 <3>[ 8.487746] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10768 23:52:01.263394 <6>[ 8.492348] pci 0000:00:00.0: PCI bridge to [bus 01]
10769 23:52:01.273984 <6>[ 8.492354] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10770 23:52:01.277160 <6>[ 8.514091] Bluetooth: Core ver 2.22
10771 23:52:01.283988 <6>[ 8.521235] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10772 23:52:01.290097 <6>[ 8.525622] NET: Registered PF_BLUETOOTH protocol family
10773 23:52:01.293368 <6>[ 8.533002] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10774 23:52:01.300208 <6>[ 8.539289] Bluetooth: HCI device and connection manager initialized
10775 23:52:01.306523 <6>[ 8.539306] Bluetooth: HCI socket layer initialized
10776 23:52:01.313282 <6>[ 8.540785] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10777 23:52:01.326290 <6>[ 8.541975] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10778 23:52:01.332938 <6>[ 8.542148] usbcore: registered new interface driver uvcvideo
10779 23:52:01.336508 <6>[ 8.547926] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10780 23:52:01.343014 <6>[ 8.555819] Bluetooth: L2CAP socket layer initialized
10781 23:52:01.349486 <6>[ 8.555829] Bluetooth: SCO socket layer initialized
10782 23:52:01.355937 <5>[ 8.589251] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10783 23:52:01.362618 <6>[ 8.595742] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10784 23:52:01.368940 <5>[ 8.619967] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10785 23:52:01.376289 <6>[ 8.655308] usbcore: registered new interface driver btusb
10786 23:52:01.382156 <5>[ 8.660237] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10787 23:52:01.395372 <4>[ 8.660313] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10788 23:52:01.398555 <3>[ 8.660323] Bluetooth: hci0: Failed to load firmware file (-2)
10789 23:52:01.405643 <3>[ 8.660327] Bluetooth: hci0: Failed to set up firmware (-2)
10790 23:52:01.415466 <4>[ 8.660331] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10791 23:52:01.425498 <4>[ 8.811358] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10792 23:52:01.431613 <6>[ 8.820244] cfg80211: failed to load regulatory.db
10793 23:52:01.470386 <6>[ 8.856973] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10794 23:52:01.477696 <6>[ 8.864482] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10795 23:52:01.501223 <6>[ 8.891197] mt7921e 0000:01:00.0: ASIC revision: 79610010
10796 23:52:01.603802 <6>[ 8.990256] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10797 23:52:01.607552 <6>[ 8.990256]
10798 23:52:01.610704 Begin: Loading essential drivers ... done.
10799 23:52:01.614049 Begin: Running /scripts/init-premount ... done.
10800 23:52:01.620552 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10801 23:52:01.630251 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10802 23:52:01.633554 Device /sys/class/net/eth0 found
10803 23:52:01.633988 done.
10804 23:52:01.640275 Begin: Waiting up to 180 secs for any network device to become available ... done.
10805 23:52:01.684879 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10806 23:52:01.693600 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10807 23:52:01.700186 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10808 23:52:01.707258 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10809 23:52:01.713415 host : mt8192-asurada-spherion-r0-cbg-2
10810 23:52:01.720203 domain : lava-rack
10811 23:52:01.723070 rootserver: 192.168.201.1 rootpath:
10812 23:52:01.726217 filename :
10813 23:52:01.873641 <6>[ 9.260944] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10814 23:52:01.883232 done.
10815 23:52:01.892268 Begin: Running /scripts/nfs-bottom ... done.
10816 23:52:01.910428 Begin: Running /scripts/init-bottom ... done.
10817 23:52:03.257187 <6>[ 10.647720] NET: Registered PF_INET6 protocol family
10818 23:52:03.265424 <6>[ 10.655378] Segment Routing with IPv6
10819 23:52:03.267976 <6>[ 10.659360] In-situ OAM (IOAM) with IPv6
10820 23:52:03.446977 <30>[ 10.810819] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10821 23:52:03.453175 <30>[ 10.843946] systemd[1]: Detected architecture arm64.
10822 23:52:03.462799
10823 23:52:03.465979 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10824 23:52:03.466063
10825 23:52:03.495093 <30>[ 10.884797] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10826 23:52:04.589191 <30>[ 11.976233] systemd[1]: Queued start job for default target graphical.target.
10827 23:52:04.629093 <30>[ 12.016173] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10828 23:52:04.635078 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10829 23:52:04.661247 <30>[ 12.048743] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10830 23:52:04.671195 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10831 23:52:04.689132 <30>[ 12.076702] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10832 23:52:04.698960 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10833 23:52:04.717011 <30>[ 12.104303] systemd[1]: Created slice user.slice - User and Session Slice.
10834 23:52:04.723524 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10835 23:52:04.747675 <30>[ 12.131758] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10836 23:52:04.757419 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10837 23:52:04.775608 <30>[ 12.159192] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10838 23:52:04.781657 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10839 23:52:04.810584 <30>[ 12.187602] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10840 23:52:04.820521 <30>[ 12.207533] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10841 23:52:04.826830 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10842 23:52:04.843399 <30>[ 12.230926] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10843 23:52:04.850430 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10844 23:52:04.867524 <30>[ 12.254990] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10845 23:52:04.877243 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10846 23:52:04.892283 <30>[ 12.283027] systemd[1]: Reached target paths.target - Path Units.
10847 23:52:04.901916 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10848 23:52:04.920094 <30>[ 12.306943] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10849 23:52:04.926070 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10850 23:52:04.940290 <30>[ 12.330924] systemd[1]: Reached target slices.target - Slice Units.
10851 23:52:04.950572 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10852 23:52:04.965007 <30>[ 12.355422] systemd[1]: Reached target swap.target - Swaps.
10853 23:52:04.971498 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10854 23:52:04.992155 <30>[ 12.379444] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10855 23:52:05.001722 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10856 23:52:05.020117 <30>[ 12.407401] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10857 23:52:05.029876 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10858 23:52:05.051463 <30>[ 12.438611] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10859 23:52:05.061224 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10860 23:52:05.076833 <30>[ 12.464428] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10861 23:52:05.086644 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10862 23:52:05.104885 <30>[ 12.491671] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10863 23:52:05.110573 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10864 23:52:05.128807 <30>[ 12.516499] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10865 23:52:05.139246 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10866 23:52:05.158707 <30>[ 12.545970] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10867 23:52:05.168256 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10868 23:52:05.183853 <30>[ 12.571405] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10869 23:52:05.194057 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10870 23:52:05.236062 <30>[ 12.623383] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10871 23:52:05.242592 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10872 23:52:05.263228 <30>[ 12.650668] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10873 23:52:05.269655 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10874 23:52:05.290801 <30>[ 12.678301] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10875 23:52:05.297241 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10876 23:52:05.322926 <30>[ 12.703900] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10877 23:52:05.339307 <30>[ 12.725801] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10878 23:52:05.349097 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10879 23:52:05.368974 <30>[ 12.756422] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10880 23:52:05.378612 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10881 23:52:05.401152 <30>[ 12.788834] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10882 23:52:05.408044 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10883 23:52:05.435533 <30>[ 12.822829] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10884 23:52:05.445641 Startin<6>[ 12.831832] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10885 23:52:05.451656 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10886 23:52:05.477065 <30>[ 12.864701] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10887 23:52:05.487315 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10888 23:52:05.509549 <30>[ 12.896834] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10889 23:52:05.516054 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10890 23:52:05.555120 <6>[ 12.945938] fuse: init (API version 7.37)
10891 23:52:05.568586 <30>[ 12.956029] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10892 23:52:05.575097 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10893 23:52:05.601776 <30>[ 12.988607] systemd[1]: Starting systemd-journald.service - Journal Service...
10894 23:52:05.607748 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10895 23:52:05.656388 <30>[ 13.043760] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10896 23:52:05.662780 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10897 23:52:05.693589 <30>[ 13.077873] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10898 23:52:05.700595 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10899 23:52:05.724777 <30>[ 13.112390] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10900 23:52:05.734775 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10901 23:52:05.753998 <3>[ 13.141190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 23:52:05.763557 <30>[ 13.142330] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10903 23:52:05.770595 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10904 23:52:05.785602 <3>[ 13.172895] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 23:52:05.800514 <30>[ 13.188073] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10906 23:52:05.807015 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10907 23:52:05.826616 <3>[ 13.213977] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 23:52:05.836394 <30>[ 13.223549] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10909 23:52:05.842786 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10910 23:52:05.856365 <3>[ 13.243809] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 23:52:05.866089 <30>[ 13.253536] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10912 23:52:05.873319 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10913 23:52:05.886264 <3>[ 13.273356] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 23:52:05.896367 <30>[ 13.283764] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10915 23:52:05.906270 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10916 23:52:05.924341 <30>[ 13.311695] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10917 23:52:05.934090 <30>[ 13.319770] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10918 23:52:05.944556 [[0;32m OK [<3>[ 13.328977] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 23:52:05.950438 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10920 23:52:05.969022 <30>[ 13.355796] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10921 23:52:05.975470 <3>[ 13.360226] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 23:52:05.985295 <30>[ 13.363380] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10923 23:52:05.991955 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10924 23:52:06.007789 <3>[ 13.395154] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 23:52:06.018351 <30>[ 13.406054] systemd[1]: modprobe@drm.service: Deactivated successfully.
10926 23:52:06.025551 <30>[ 13.414399] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10927 23:52:06.035607 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10928 23:52:06.052707 <30>[ 13.439828] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10929 23:52:06.059452 <30>[ 13.447712] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10930 23:52:06.066227 <4>[ 13.448286] power_supply_show_property: 1 callbacks suppressed
10931 23:52:06.075967 <3>[ 13.448300] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 23:52:06.085865 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10933 23:52:06.101585 <30>[ 13.491779] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10934 23:52:06.111978 <3>[ 13.496006] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 23:52:06.118382 <30>[ 13.499401] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10936 23:52:06.128228 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10937 23:52:06.143459 <3>[ 13.531181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 23:52:06.153446 <30>[ 13.540985] systemd[1]: modprobe@loop.service: Deactivated successfully.
10939 23:52:06.160514 <30>[ 13.548280] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10940 23:52:06.177021 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Mo<3>[ 13.563219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 23:52:06.190876 <4>[ 13.572142] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10942 23:52:06.201075 <3>[ 13.581282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 23:52:06.208029 <3>[ 13.587776] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10944 23:52:06.210662 dule loop.
10945 23:52:06.228561 <30>[ 13.616057] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10946 23:52:06.245442 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Ker<3>[ 13.629914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 23:52:06.245532 nel Modules.
10948 23:52:06.268530 <30>[ 13.651826] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10949 23:52:06.278687 [[0;32m OK [0m] Finished [0<3>[ 13.665431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 23:52:06.284690 ;1;39msystemd-network-g…rk units from Kernel command line.
10951 23:52:06.304286 <30>[ 13.691421] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10952 23:52:06.317699 <3>[ 13.705449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 23:52:06.328027 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10954 23:52:06.348065 <30>[ 13.735409] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10955 23:52:06.358207 <3>[ 13.738774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 23:52:06.365014 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10957 23:52:06.388597 <30>[ 13.776362] systemd[1]: Reached target network-pre.target - Preparation for Network.
10958 23:52:06.398947 <3>[ 13.776502] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 23:52:06.405141 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10960 23:52:06.455523 <30>[ 13.843108] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10961 23:52:06.462532 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10962 23:52:06.490086 <30>[ 13.877613] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10963 23:52:06.499927 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10964 23:52:06.522542 <30>[ 13.907104] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10965 23:52:06.540057 <30>[ 13.920807] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10966 23:52:06.583860 <30>[ 13.971659] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10967 23:52:06.590880 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10968 23:52:06.617510 <30>[ 14.001682] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10969 23:52:06.629552 <30>[ 14.017377] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10970 23:52:06.636472 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10971 23:52:06.662211 <30>[ 14.049699] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10972 23:52:06.668916 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10973 23:52:06.699117 <30>[ 14.086610] systemd[1]: Started systemd-journald.service - Journal Service.
10974 23:52:06.705277 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10975 23:52:06.728858 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10976 23:52:06.748364 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10977 23:52:06.772838 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10978 23:52:06.793156 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10979 23:52:06.813086 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10980 23:52:06.860463 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10981 23:52:06.884316 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10982 23:52:06.924242 <46>[ 14.312204] systemd-journald[310]: Received client request to flush runtime journal.
10983 23:52:07.705254 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10984 23:52:07.724250 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10985 23:52:07.743502 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10986 23:52:08.048266 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10987 23:52:08.332321 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10988 23:52:08.358173 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10989 23:52:08.504273 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10990 23:52:08.579639 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10991 23:52:08.652046 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10992 23:52:08.928709 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10993 23:52:08.940458 <6>[ 16.331423] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10994 23:52:08.989294 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10995 23:52:09.099153 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10996 23:52:09.117300 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10997 23:52:09.181103 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10998 23:52:09.206742 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10999 23:52:09.227873 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11000 23:52:09.249591 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11001 23:52:09.281406 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11002 23:52:09.348044 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11003 23:52:09.371089 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11004 23:52:09.388064 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11005 23:52:09.423346 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11006 23:52:09.532332 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11007 23:52:09.551487 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11008 23:52:09.567294 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11009 23:52:09.582947 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11010 23:52:09.608907 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11011 23:52:09.625805 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11012 23:52:09.643469 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11013 23:52:09.662245 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11014 23:52:09.682443 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11015 23:52:09.699055 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11016 23:52:09.717008 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11017 23:52:09.735417 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11018 23:52:09.751288 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11019 23:52:09.792230 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11020 23:52:09.828617 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11021 23:52:09.919892 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11022 23:52:09.936579 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11023 23:52:10.106905 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11024 23:52:10.168144 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11025 23:52:10.213729 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11026 23:52:10.233323 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11027 23:52:10.256357 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11028 23:52:10.290663 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11029 23:52:10.311249 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11030 23:52:10.329768 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11031 23:52:10.347904 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11032 23:52:10.404999 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11033 23:52:10.450935 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11034 23:52:10.533045
11035 23:52:10.536274 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11036 23:52:10.536365
11037 23:52:10.539390 debian-bookworm-arm64 login: root (automatic login)
11038 23:52:10.539473
11039 23:52:10.853069 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11040 23:52:10.853213
11041 23:52:10.859768 The programs included with the Debian GNU/Linux system are free software;
11042 23:52:10.866217 the exact distribution terms for each program are described in the
11043 23:52:10.869377 individual files in /usr/share/doc/*/copyright.
11044 23:52:10.869462
11045 23:52:10.876074 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11046 23:52:10.880076 permitted by applicable law.
11047 23:52:12.004279 Matched prompt #10: / #
11049 23:52:12.004569 Setting prompt string to ['/ #']
11050 23:52:12.004663 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11052 23:52:12.004862 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11053 23:52:12.004951 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11054 23:52:12.005023 Setting prompt string to ['/ #']
11055 23:52:12.005085 Forcing a shell prompt, looking for ['/ #']
11057 23:52:12.055300 / #
11058 23:52:12.055404 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11059 23:52:12.055477 Waiting using forced prompt support (timeout 00:02:30)
11060 23:52:12.060235
11061 23:52:12.060505 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11062 23:52:12.060600 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11064 23:52:12.160941 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7'
11065 23:52:12.166170 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084322/extract-nfsrootfs-tgcbstq7'
11067 23:52:12.266689 / # export NFS_SERVER_IP='192.168.201.1'
11068 23:52:12.271719 export NFS_SERVER_IP='192.168.201.1'
11069 23:52:12.272005 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11070 23:52:12.272115 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11071 23:52:12.272218 end: 2 depthcharge-action (duration 00:01:36) [common]
11072 23:52:12.272309 start: 3 lava-test-retry (timeout 00:07:44) [common]
11073 23:52:12.272413 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
11074 23:52:12.272521 Using namespace: common
11076 23:52:12.372861 / # #
11077 23:52:12.373000 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11078 23:52:12.378088 #
11079 23:52:12.378354 Using /lava-14084322
11081 23:52:12.478680 / # export SHELL=/bin/bash
11082 23:52:12.483683 export SHELL=/bin/bash
11084 23:52:12.584205 / # . /lava-14084322/environment
11085 23:52:12.589061 . /lava-14084322/environment
11087 23:52:12.695593 / # /lava-14084322/bin/lava-test-runner /lava-14084322/0
11088 23:52:12.695732 Test shell timeout: 10s (minimum of the action and connection timeout)
11089 23:52:12.701620 /lava-14084322/bin/lava-test-runner /lava-14084322/0
11090 23:52:12.990884 + export TESTRUN_ID=0_timesync-off
11091 23:52:12.994565 + TESTRUN_ID=0_timesync-off
11092 23:52:12.997799 + cd /lava-14084322/0/tests/0_timesync-off
11093 23:52:13.000867 ++ cat uuid
11094 23:52:13.005859 + UUID=14084322_1.6.2.3.1
11095 23:52:13.005942 + set +x
11096 23:52:13.011514 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14084322_1.6.2.3.1>
11097 23:52:13.011779 Received signal: <STARTRUN> 0_timesync-off 14084322_1.6.2.3.1
11098 23:52:13.011855 Starting test lava.0_timesync-off (14084322_1.6.2.3.1)
11099 23:52:13.011942 Skipping test definition patterns.
11100 23:52:13.015084 + systemctl stop systemd-timesyncd
11101 23:52:13.098174 + set +x
11102 23:52:13.101375 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14084322_1.6.2.3.1>
11103 23:52:13.101655 Received signal: <ENDRUN> 0_timesync-off 14084322_1.6.2.3.1
11104 23:52:13.101764 Ending use of test pattern.
11105 23:52:13.101854 Ending test lava.0_timesync-off (14084322_1.6.2.3.1), duration 0.09
11107 23:52:13.187361 + export TESTRUN_ID=1_kselftest-alsa
11108 23:52:13.190856 + TESTRUN_ID=1_kselftest-alsa
11109 23:52:13.197920 + cd /lava-14084322/0/tests/1_kselftest-alsa
11110 23:52:13.198004 ++ cat uuid
11111 23:52:13.204556 + UUID=14084322_1.6.2.3.5
11112 23:52:13.204641 + set +x
11113 23:52:13.211318 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14084322_1.6.2.3.5>
11114 23:52:13.211577 Received signal: <STARTRUN> 1_kselftest-alsa 14084322_1.6.2.3.5
11115 23:52:13.211648 Starting test lava.1_kselftest-alsa (14084322_1.6.2.3.5)
11116 23:52:13.211729 Skipping test definition patterns.
11117 23:52:13.214232 + cd ./automated/linux/kselftest/
11118 23:52:13.244373 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11119 23:52:13.289940 INFO: install_deps skipped
11120 23:52:13.807070 --2024-05-29 23:52:13-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11121 23:52:13.813444 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11122 23:52:13.947710 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11123 23:52:14.077722 HTTP request sent, awaiting response... 200 OK
11124 23:52:14.080667 Length: 1642292 (1.6M) [application/octet-stream]
11125 23:52:14.085109 Saving to: 'kselftest_armhf.tar.gz'
11126 23:52:14.085196
11127 23:52:14.085289
11128 23:52:14.336888 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11129 23:52:14.595836 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11130 23:52:15.032700 kselftest_armhf.tar 13%[=> ] 217.50K 420KB/s
11131 23:52:15.113894 kselftest_armhf.tar 49%[========> ] 793.02K 831KB/s
11132 23:52:15.120268 kselftest_armhf.tar 100%[===================>] 1.57M 1.51MB/s in 1.0s
11133 23:52:15.120357
11134 23:52:15.265551 2024-05-29 23:52:15 (1.51 MB/s) - 'kselftest_armhf.tar.gz' saved [1642292/1642292]
11135 23:52:15.265700
11136 23:52:19.915474 skiplist:
11137 23:52:19.918806 ========================================
11138 23:52:19.921800 ========================================
11139 23:52:19.978739 alsa:mixer-test
11140 23:52:20.004463 ============== Tests to run ===============
11141 23:52:20.007686 alsa:mixer-test
11142 23:52:20.011028 ===========End Tests to run ===============
11143 23:52:20.017046 shardfile-alsa pass
11144 23:52:20.135256 <12>[ 27.527801] kselftest: Running tests in alsa
11145 23:52:20.145559 TAP version 13
11146 23:52:20.160833 1..1
11147 23:52:20.177522 # selftests: alsa: mixer-test
11148 23:52:20.642478 # TAP version 13
11149 23:52:20.642647 # 1..0
11150 23:52:20.648876 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11151 23:52:20.652152 ok 1 selftests: alsa: mixer-test
11152 23:52:22.159054 alsa_mixer-test pass
11153 23:52:22.236379 + ../../utils/send-to-lava.sh ./output/result.txt
11154 23:52:22.322710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11155 23:52:22.323045 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11157 23:52:22.382927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11158 23:52:22.383067 + set +x
11159 23:52:22.383349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11161 23:52:22.389438 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14084322_1.6.2.3.5>
11162 23:52:22.389768 Received signal: <ENDRUN> 1_kselftest-alsa 14084322_1.6.2.3.5
11163 23:52:22.389879 Ending use of test pattern.
11164 23:52:22.389970 Ending test lava.1_kselftest-alsa (14084322_1.6.2.3.5), duration 9.18
11166 23:52:22.392836 <LAVA_TEST_RUNNER EXIT>
11167 23:52:22.393109 ok: lava_test_shell seems to have completed
11168 23:52:22.393248 alsa_mixer-test: pass
shardfile-alsa: pass
11169 23:52:22.393414 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11170 23:52:22.393529 end: 3 lava-test-retry (duration 00:00:10) [common]
11171 23:52:22.393631 start: 4 finalize (timeout 00:07:34) [common]
11172 23:52:22.393720 start: 4.1 power-off (timeout 00:00:30) [common]
11173 23:52:22.393972 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11174 23:52:22.603774 >> Command sent successfully.
11175 23:52:22.613917 Returned 0 in 0 seconds
11176 23:52:22.714972 end: 4.1 power-off (duration 00:00:00) [common]
11178 23:52:22.715411 start: 4.2 read-feedback (timeout 00:07:34) [common]
11179 23:52:22.715708 Listened to connection for namespace 'common' for up to 1s
11180 23:52:23.716629 Finalising connection for namespace 'common'
11181 23:52:23.716829 Disconnecting from shell: Finalise
11182 23:52:23.716934 / #
11183 23:52:23.817248 end: 4.2 read-feedback (duration 00:00:01) [common]
11184 23:52:23.817487 end: 4 finalize (duration 00:00:01) [common]
11185 23:52:23.817635 Cleaning after the job
11186 23:52:23.817770 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/ramdisk
11187 23:52:23.820010 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/kernel
11188 23:52:23.831163 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/dtb
11189 23:52:23.831377 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/nfsrootfs
11190 23:52:23.896773 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084322/tftp-deploy-lr3_8_9e/modules
11191 23:52:23.902566 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084322
11192 23:52:24.463065 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084322
11193 23:52:24.463244 Job finished correctly