Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 23:55:54.656478 lava-dispatcher, installed at version: 2024.03
2 23:55:54.656678 start: 0 validate
3 23:55:54.656817 Start time: 2024-05-29 23:55:54.656810+00:00 (UTC)
4 23:55:54.656942 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:55:54.657069 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:55:54.917374 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:55:54.917540 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:55:55.184657 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:55:55.185422 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:55:55.448029 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:55:55.448647 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:55:55.719617 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:55:55.720404 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:55:55.990680 validate duration: 1.33
16 23:55:55.991916 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:55:55.992437 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:55:55.992883 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:55:55.993473 Not decompressing ramdisk as can be used compressed.
20 23:55:55.993914 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:55:55.994250 saving as /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/ramdisk/initrd.cpio.gz
22 23:55:55.994576 total size: 5628169 (5 MB)
23 23:55:55.999405 progress 0 % (0 MB)
24 23:55:56.007704 progress 5 % (0 MB)
25 23:55:56.015242 progress 10 % (0 MB)
26 23:55:56.020087 progress 15 % (0 MB)
27 23:55:56.024298 progress 20 % (1 MB)
28 23:55:56.027418 progress 25 % (1 MB)
29 23:55:56.030579 progress 30 % (1 MB)
30 23:55:56.033436 progress 35 % (1 MB)
31 23:55:56.035707 progress 40 % (2 MB)
32 23:55:56.038160 progress 45 % (2 MB)
33 23:55:56.040186 progress 50 % (2 MB)
34 23:55:56.042291 progress 55 % (2 MB)
35 23:55:56.044411 progress 60 % (3 MB)
36 23:55:56.046156 progress 65 % (3 MB)
37 23:55:56.048077 progress 70 % (3 MB)
38 23:55:56.049715 progress 75 % (4 MB)
39 23:55:56.051395 progress 80 % (4 MB)
40 23:55:56.052898 progress 85 % (4 MB)
41 23:55:56.054605 progress 90 % (4 MB)
42 23:55:56.056140 progress 95 % (5 MB)
43 23:55:56.057544 progress 100 % (5 MB)
44 23:55:56.057752 5 MB downloaded in 0.06 s (84.94 MB/s)
45 23:55:56.057904 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:55:56.058147 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:55:56.058239 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:55:56.058325 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:55:56.058458 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:55:56.058527 saving as /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/kernel/Image
52 23:55:56.058587 total size: 54682112 (52 MB)
53 23:55:56.058650 No compression specified
54 23:55:56.059782 progress 0 % (0 MB)
55 23:55:56.073500 progress 5 % (2 MB)
56 23:55:56.087076 progress 10 % (5 MB)
57 23:55:56.100825 progress 15 % (7 MB)
58 23:55:56.114509 progress 20 % (10 MB)
59 23:55:56.128337 progress 25 % (13 MB)
60 23:55:56.142048 progress 30 % (15 MB)
61 23:55:56.155817 progress 35 % (18 MB)
62 23:55:56.169615 progress 40 % (20 MB)
63 23:55:56.183319 progress 45 % (23 MB)
64 23:55:56.197063 progress 50 % (26 MB)
65 23:55:56.210774 progress 55 % (28 MB)
66 23:55:56.224546 progress 60 % (31 MB)
67 23:55:56.238290 progress 65 % (33 MB)
68 23:55:56.252151 progress 70 % (36 MB)
69 23:55:56.265871 progress 75 % (39 MB)
70 23:55:56.279794 progress 80 % (41 MB)
71 23:55:56.293569 progress 85 % (44 MB)
72 23:55:56.307210 progress 90 % (46 MB)
73 23:55:56.320865 progress 95 % (49 MB)
74 23:55:56.334331 progress 100 % (52 MB)
75 23:55:56.334557 52 MB downloaded in 0.28 s (188.97 MB/s)
76 23:55:56.334705 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:55:56.334939 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:55:56.335024 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:55:56.335108 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:55:56.335242 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:55:56.335316 saving as /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/dtb/mt8192-asurada-spherion-r0.dtb
83 23:55:56.335377 total size: 47258 (0 MB)
84 23:55:56.335438 No compression specified
85 23:55:56.336560 progress 69 % (0 MB)
86 23:55:56.336853 progress 100 % (0 MB)
87 23:55:56.337006 0 MB downloaded in 0.00 s (27.71 MB/s)
88 23:55:56.337125 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:55:56.337387 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:55:56.337472 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:55:56.337552 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:55:56.337661 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:55:56.337727 saving as /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/nfsrootfs/full.rootfs.tar
95 23:55:56.337786 total size: 120894716 (115 MB)
96 23:55:56.337846 Using unxz to decompress xz
97 23:55:56.341771 progress 0 % (0 MB)
98 23:55:56.690083 progress 5 % (5 MB)
99 23:55:57.042739 progress 10 % (11 MB)
100 23:55:57.392660 progress 15 % (17 MB)
101 23:55:57.727741 progress 20 % (23 MB)
102 23:55:58.027453 progress 25 % (28 MB)
103 23:55:58.404835 progress 30 % (34 MB)
104 23:55:58.757408 progress 35 % (40 MB)
105 23:55:58.924319 progress 40 % (46 MB)
106 23:55:59.101840 progress 45 % (51 MB)
107 23:55:59.420900 progress 50 % (57 MB)
108 23:55:59.810994 progress 55 % (63 MB)
109 23:56:00.154089 progress 60 % (69 MB)
110 23:56:00.502706 progress 65 % (74 MB)
111 23:56:00.857245 progress 70 % (80 MB)
112 23:56:01.211829 progress 75 % (86 MB)
113 23:56:01.553647 progress 80 % (92 MB)
114 23:56:01.889829 progress 85 % (98 MB)
115 23:56:02.243287 progress 90 % (103 MB)
116 23:56:02.568970 progress 95 % (109 MB)
117 23:56:02.925263 progress 100 % (115 MB)
118 23:56:02.930627 115 MB downloaded in 6.59 s (17.49 MB/s)
119 23:56:02.930886 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:56:02.931154 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:56:02.931245 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:56:02.931332 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:56:02.931479 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:56:02.931549 saving as /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/modules/modules.tar
126 23:56:02.931610 total size: 8601444 (8 MB)
127 23:56:02.931673 Using unxz to decompress xz
128 23:56:02.935758 progress 0 % (0 MB)
129 23:56:02.955277 progress 5 % (0 MB)
130 23:56:02.979269 progress 10 % (0 MB)
131 23:56:03.004356 progress 15 % (1 MB)
132 23:56:03.028854 progress 20 % (1 MB)
133 23:56:03.054263 progress 25 % (2 MB)
134 23:56:03.078794 progress 30 % (2 MB)
135 23:56:03.101758 progress 35 % (2 MB)
136 23:56:03.125911 progress 40 % (3 MB)
137 23:56:03.152205 progress 45 % (3 MB)
138 23:56:03.175989 progress 50 % (4 MB)
139 23:56:03.200237 progress 55 % (4 MB)
140 23:56:03.224290 progress 60 % (4 MB)
141 23:56:03.247851 progress 65 % (5 MB)
142 23:56:03.274017 progress 70 % (5 MB)
143 23:56:03.298667 progress 75 % (6 MB)
144 23:56:03.321844 progress 80 % (6 MB)
145 23:56:03.347060 progress 85 % (7 MB)
146 23:56:03.370445 progress 90 % (7 MB)
147 23:56:03.399241 progress 95 % (7 MB)
148 23:56:03.426899 progress 100 % (8 MB)
149 23:56:03.432223 8 MB downloaded in 0.50 s (16.39 MB/s)
150 23:56:03.432489 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:56:03.432755 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:56:03.432850 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 23:56:03.432944 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 23:56:06.915090 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n
156 23:56:06.915278 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 23:56:06.915380 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 23:56:06.915550 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714
159 23:56:06.915677 makedir: /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin
160 23:56:06.915776 makedir: /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/tests
161 23:56:06.915872 makedir: /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/results
162 23:56:06.915971 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-add-keys
163 23:56:06.916110 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-add-sources
164 23:56:06.916237 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-background-process-start
165 23:56:06.916364 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-background-process-stop
166 23:56:06.916488 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-common-functions
167 23:56:06.916610 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-echo-ipv4
168 23:56:06.916733 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-install-packages
169 23:56:06.916855 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-installed-packages
170 23:56:06.916978 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-os-build
171 23:56:06.917101 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-probe-channel
172 23:56:06.917223 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-probe-ip
173 23:56:06.917389 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-target-ip
174 23:56:06.917511 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-target-mac
175 23:56:06.917633 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-target-storage
176 23:56:06.917756 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-case
177 23:56:06.917879 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-event
178 23:56:06.918001 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-feedback
179 23:56:06.918122 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-raise
180 23:56:06.918242 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-reference
181 23:56:06.918379 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-runner
182 23:56:06.918501 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-set
183 23:56:06.918624 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-test-shell
184 23:56:06.918758 Updating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-add-keys (debian)
185 23:56:06.918906 Updating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-add-sources (debian)
186 23:56:06.919041 Updating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-install-packages (debian)
187 23:56:06.919175 Updating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-installed-packages (debian)
188 23:56:06.919308 Updating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/bin/lava-os-build (debian)
189 23:56:06.919425 Creating /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/environment
190 23:56:06.919520 LAVA metadata
191 23:56:06.919586 - LAVA_JOB_ID=14084381
192 23:56:06.919648 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:56:06.919747 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 23:56:06.919812 skipped lava-vland-overlay
195 23:56:06.919885 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:56:06.919962 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 23:56:06.920020 skipped lava-multinode-overlay
198 23:56:06.920090 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:56:06.920164 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 23:56:06.920249 Loading test definitions
201 23:56:06.920335 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 23:56:06.920405 Using /lava-14084381 at stage 0
203 23:56:06.920713 uuid=14084381_1.6.2.3.1 testdef=None
204 23:56:06.920800 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:56:06.920884 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 23:56:06.921372 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:56:06.921588 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 23:56:06.922146 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:56:06.922369 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 23:56:06.922891 runner path: /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/0/tests/0_timesync-off test_uuid 14084381_1.6.2.3.1
213 23:56:06.923049 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:56:06.923271 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 23:56:06.923342 Using /lava-14084381 at stage 0
217 23:56:06.923437 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:56:06.923521 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/0/tests/1_kselftest-arm64'
219 23:56:08.963112 Running '/usr/bin/git checkout kernelci.org
220 23:56:09.108499 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 23:56:09.109231 uuid=14084381_1.6.2.3.5 testdef=None
222 23:56:09.109456 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 23:56:09.109697 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 23:56:09.110489 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:56:09.110716 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 23:56:09.111799 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:56:09.112037 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 23:56:09.112940 runner path: /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/0/tests/1_kselftest-arm64 test_uuid 14084381_1.6.2.3.5
232 23:56:09.113032 BOARD='mt8192-asurada-spherion-r0'
233 23:56:09.113096 BRANCH='cip-gitlab'
234 23:56:09.113154 SKIPFILE='/dev/null'
235 23:56:09.113211 SKIP_INSTALL='True'
236 23:56:09.113270 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:56:09.113387 TST_CASENAME=''
238 23:56:09.113442 TST_CMDFILES='arm64'
239 23:56:09.113580 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:56:09.113783 Creating lava-test-runner.conf files
242 23:56:09.113846 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084381/lava-overlay-kggmc714/lava-14084381/0 for stage 0
243 23:56:09.113938 - 0_timesync-off
244 23:56:09.114004 - 1_kselftest-arm64
245 23:56:09.114096 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 23:56:09.114197 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 23:56:16.633405 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:56:16.633563 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 23:56:16.633657 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:56:16.633757 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:56:16.633851 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 23:56:16.801961 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:56:16.802344 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 23:56:16.802459 extracting modules file /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n
255 23:56:17.023729 extracting modules file /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084381/extract-overlay-ramdisk-h2gubb2i/ramdisk
256 23:56:17.250190 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:56:17.250357 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 23:56:17.250453 [common] Applying overlay to NFS
259 23:56:17.250525 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084381/compress-overlay-urv3avge/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n
260 23:56:18.197112 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:56:18.197296 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 23:56:18.197413 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:56:18.197509 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 23:56:18.197592 Building ramdisk /var/lib/lava/dispatcher/tmp/14084381/extract-overlay-ramdisk-h2gubb2i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084381/extract-overlay-ramdisk-h2gubb2i/ramdisk
265 23:56:18.546014 >> 130335 blocks
266 23:56:20.583455 rename /var/lib/lava/dispatcher/tmp/14084381/extract-overlay-ramdisk-h2gubb2i/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/ramdisk/ramdisk.cpio.gz
267 23:56:20.583935 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:56:20.584110 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 23:56:20.584248 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 23:56:20.584410 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/kernel/Image']
271 23:56:33.691076 Returned 0 in 13 seconds
272 23:56:33.792061 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/kernel/image.itb
273 23:56:34.149635 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:56:34.150013 output: Created: Thu May 30 00:56:34 2024
275 23:56:34.150090 output: Image 0 (kernel-1)
276 23:56:34.150159 output: Description:
277 23:56:34.150224 output: Created: Thu May 30 00:56:34 2024
278 23:56:34.150288 output: Type: Kernel Image
279 23:56:34.150351 output: Compression: lzma compressed
280 23:56:34.150411 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
281 23:56:34.150470 output: Architecture: AArch64
282 23:56:34.150528 output: OS: Linux
283 23:56:34.150584 output: Load Address: 0x00000000
284 23:56:34.150639 output: Entry Point: 0x00000000
285 23:56:34.150692 output: Hash algo: crc32
286 23:56:34.150746 output: Hash value: 907bf91d
287 23:56:34.150801 output: Image 1 (fdt-1)
288 23:56:34.150854 output: Description: mt8192-asurada-spherion-r0
289 23:56:34.150909 output: Created: Thu May 30 00:56:34 2024
290 23:56:34.150965 output: Type: Flat Device Tree
291 23:56:34.151018 output: Compression: uncompressed
292 23:56:34.151071 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:56:34.151124 output: Architecture: AArch64
294 23:56:34.151177 output: Hash algo: crc32
295 23:56:34.151229 output: Hash value: 0f8e4d2e
296 23:56:34.151282 output: Image 2 (ramdisk-1)
297 23:56:34.151334 output: Description: unavailable
298 23:56:34.151386 output: Created: Thu May 30 00:56:34 2024
299 23:56:34.151439 output: Type: RAMDisk Image
300 23:56:34.151492 output: Compression: Unknown Compression
301 23:56:34.151545 output: Data Size: 18719830 Bytes = 18281.08 KiB = 17.85 MiB
302 23:56:34.151598 output: Architecture: AArch64
303 23:56:34.151650 output: OS: Linux
304 23:56:34.151703 output: Load Address: unavailable
305 23:56:34.151755 output: Entry Point: unavailable
306 23:56:34.151807 output: Hash algo: crc32
307 23:56:34.151859 output: Hash value: 6e02b7b3
308 23:56:34.151917 output: Default Configuration: 'conf-1'
309 23:56:34.151970 output: Configuration 0 (conf-1)
310 23:56:34.152023 output: Description: mt8192-asurada-spherion-r0
311 23:56:34.152076 output: Kernel: kernel-1
312 23:56:34.152129 output: Init Ramdisk: ramdisk-1
313 23:56:34.152182 output: FDT: fdt-1
314 23:56:34.152235 output: Loadables: kernel-1
315 23:56:34.152288 output:
316 23:56:34.152517 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:56:34.152626 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:56:34.152740 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:56:34.152834 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 23:56:34.152910 No LXC device requested
321 23:56:34.152988 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:56:34.153075 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 23:56:34.153153 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:56:34.153222 Checking files for TFTP limit of 4294967296 bytes.
325 23:56:34.153771 end: 1 tftp-deploy (duration 00:00:38) [common]
326 23:56:34.153881 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:56:34.153979 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:56:34.154105 substitutions:
329 23:56:34.154173 - {DTB}: 14084381/tftp-deploy-y63n22rm/dtb/mt8192-asurada-spherion-r0.dtb
330 23:56:34.154238 - {INITRD}: 14084381/tftp-deploy-y63n22rm/ramdisk/ramdisk.cpio.gz
331 23:56:34.154296 - {KERNEL}: 14084381/tftp-deploy-y63n22rm/kernel/Image
332 23:56:34.154354 - {LAVA_MAC}: None
333 23:56:34.154409 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n
334 23:56:34.154465 - {NFS_SERVER_IP}: 192.168.201.1
335 23:56:34.154519 - {PRESEED_CONFIG}: None
336 23:56:34.154573 - {PRESEED_LOCAL}: None
337 23:56:34.154626 - {RAMDISK}: 14084381/tftp-deploy-y63n22rm/ramdisk/ramdisk.cpio.gz
338 23:56:34.154681 - {ROOT_PART}: None
339 23:56:34.154733 - {ROOT}: None
340 23:56:34.154786 - {SERVER_IP}: 192.168.201.1
341 23:56:34.154839 - {TEE}: None
342 23:56:34.154893 Parsed boot commands:
343 23:56:34.154945 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:56:34.155124 Parsed boot commands: tftpboot 192.168.201.1 14084381/tftp-deploy-y63n22rm/kernel/image.itb 14084381/tftp-deploy-y63n22rm/kernel/cmdline
345 23:56:34.155211 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:56:34.155298 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:56:34.155388 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:56:34.155473 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:56:34.155544 Not connected, no need to disconnect.
350 23:56:34.155616 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:56:34.155699 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:56:34.155767 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 23:56:34.159458 Setting prompt string to ['lava-test: # ']
354 23:56:34.159864 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:56:34.159978 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:56:34.160078 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:56:34.160170 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:56:34.160352 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 23:56:48.270642 Returned 0 in 14 seconds
360 23:56:48.371675 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 23:56:48.373044 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 23:56:48.373606 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 23:56:48.374053 Setting prompt string to 'Starting depthcharge on Spherion...'
365 23:56:48.374444 Changing prompt to 'Starting depthcharge on Spherion...'
366 23:56:48.374793 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 23:56:48.376705 [Enter `^Ec?' for help]
368 23:56:48.377135
369 23:56:48.377547
370 23:56:48.377880 F0: 102B 0000
371 23:56:48.378199
372 23:56:48.378493 F3: 1001 0000 [0200]
373 23:56:48.378799
374 23:56:48.379105 F3: 1001 0000
375 23:56:48.379447
376 23:56:48.379733 F7: 102D 0000
377 23:56:48.380016
378 23:56:48.380294 F1: 0000 0000
379 23:56:48.380574
380 23:56:48.380849 V0: 0000 0000 [0001]
381 23:56:48.381127
382 23:56:48.381460 00: 0007 8000
383 23:56:48.381808
384 23:56:48.382097 01: 0000 0000
385 23:56:48.382383
386 23:56:48.382661 BP: 0C00 0209 [0000]
387 23:56:48.382938
388 23:56:48.383235 G0: 1182 0000
389 23:56:48.383519
390 23:56:48.383794 EC: 0000 0021 [4000]
391 23:56:48.384096
392 23:56:48.384405 S7: 0000 0000 [0000]
393 23:56:48.384728
394 23:56:48.385004 CC: 0000 0000 [0001]
395 23:56:48.385340
396 23:56:48.385652 T0: 0000 0040 [010F]
397 23:56:48.385957
398 23:56:48.386237 Jump to BL
399 23:56:48.386511
400 23:56:48.386784
401 23:56:48.387104
402 23:56:48.387418 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 23:56:48.387734 ARM64: Exception handlers installed.
404 23:56:48.388019 ARM64: Testing exception
405 23:56:48.388297 ARM64: Done test exception
406 23:56:48.388598 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 23:56:48.388879 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 23:56:48.389195 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 23:56:48.389580 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 23:56:48.389880 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 23:56:48.390161 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 23:56:48.390440 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 23:56:48.390722 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 23:56:48.391000 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 23:56:48.391280 WDT: Last reset was cold boot
416 23:56:48.391558 SPI1(PAD0) initialized at 2873684 Hz
417 23:56:48.391835 SPI5(PAD0) initialized at 992727 Hz
418 23:56:48.392232 VBOOT: Loading verstage.
419 23:56:48.392576 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 23:56:48.392863 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 23:56:48.393145 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 23:56:48.393458 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 23:56:48.393739 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 23:56:48.394017 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 23:56:48.394298 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 23:56:48.394684
427 23:56:48.394969
428 23:56:48.395242 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 23:56:48.395523 ARM64: Exception handlers installed.
430 23:56:48.395800 ARM64: Testing exception
431 23:56:48.396076 ARM64: Done test exception
432 23:56:48.396350 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 23:56:48.396628 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 23:56:48.396907 Probing TPM: . done!
435 23:56:48.397177 TPM ready after 0 ms
436 23:56:48.397616 Connected to device vid:did:rid of 1ae0:0028:00
437 23:56:48.397910 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 23:56:48.398192 Initialized TPM device CR50 revision 0
439 23:56:48.398466 tlcl_send_startup: Startup return code is 0
440 23:56:48.398744 TPM: setup succeeded
441 23:56:48.399021 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 23:56:48.399298 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 23:56:48.399630 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 23:56:48.399929 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:56:48.400154 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 23:56:48.400353 in-header: 03 07 00 00 08 00 00 00
447 23:56:48.400552 in-data: aa e4 47 04 13 02 00 00
448 23:56:48.400750 Chrome EC: UHEPI supported
449 23:56:48.400948 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 23:56:48.401146 in-header: 03 a9 00 00 08 00 00 00
451 23:56:48.401374 in-data: 84 60 60 08 00 00 00 00
452 23:56:48.401576 Phase 1
453 23:56:48.401772 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 23:56:48.401971 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 23:56:48.402172 VB2:vb2_check_recovery() Recovery was requested manually
456 23:56:48.402370 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 23:56:48.402569 Recovery requested (1009000e)
458 23:56:48.402767 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:56:48.402967 tlcl_extend: response is 0
460 23:56:48.403166 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:56:48.403364 tlcl_extend: response is 0
462 23:56:48.403562 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:56:48.403761 read SPI 0x210d4 0x2173b: 15141 us, 9049 KB/s, 72.392 Mbps
464 23:56:48.403959 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:56:48.404155
466 23:56:48.404348
467 23:56:48.404544 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:56:48.404744 ARM64: Exception handlers installed.
469 23:56:48.404940 ARM64: Testing exception
470 23:56:48.405117 ARM64: Done test exception
471 23:56:48.405283 pmic_efuse_setting: Set efuses in 11 msecs
472 23:56:48.405437 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:56:48.405589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:56:48.405831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:56:48.406315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:56:48.406488 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:56:48.406643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:56:48.406795 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:56:48.406945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:56:48.407094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:56:48.407242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:56:48.407391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:56:48.407541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:56:48.407689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:56:48.407837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:56:48.407985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:56:48.408134 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:56:48.408285 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:56:48.408433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:56:48.408581 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:56:48.408730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:56:48.408878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:56:48.409027 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:56:48.409177 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:56:48.409364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:56:48.409515 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:56:48.409665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:56:48.409815 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:56:48.409964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:56:48.410098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:56:48.410217 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:56:48.410336 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:56:48.410455 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:56:48.410574 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:56:48.410694 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:56:48.410813 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:56:48.410932 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:56:48.411050 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:56:48.411170 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:56:48.411290 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:56:48.411408 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:56:48.411527 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:56:48.411646 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:56:48.411765 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:56:48.411885 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:56:48.412004 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:56:48.412123 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:56:48.412241 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:56:48.412360 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:56:48.412478 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:56:48.412596 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:56:48.412714 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:56:48.412833 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:56:48.412951 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 23:56:48.413071 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:56:48.413190 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:56:48.413329 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:56:48.413453 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:56:48.413574 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:56:48.413693 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:56:48.413812 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:56:48.413932 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x1
533 23:56:48.414050 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:56:48.414170 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 23:56:48.414289 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:56:48.414408 [RTC]rtc_get_frequency_meter,154: input=15, output=852
537 23:56:48.414526 [RTC]rtc_get_frequency_meter,154: input=7, output=725
538 23:56:48.414645 [RTC]rtc_get_frequency_meter,154: input=11, output=788
539 23:56:48.414763 [RTC]rtc_get_frequency_meter,154: input=13, output=821
540 23:56:48.414881 [RTC]rtc_get_frequency_meter,154: input=12, output=805
541 23:56:48.415047 [RTC]rtc_get_frequency_meter,154: input=11, output=789
542 23:56:48.415152 [RTC]rtc_get_frequency_meter,154: input=12, output=805
543 23:56:48.415254 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 23:56:48.415354 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 23:56:48.415672 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:56:48.415783 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 23:56:48.415884 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:56:48.415984 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 23:56:48.416084 ADC[4]: Raw value=902955 ID=7
550 23:56:48.416184 ADC[3]: Raw value=213916 ID=1
551 23:56:48.416283 RAM Code: 0x71
552 23:56:48.416383 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:56:48.416484 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:56:48.416585 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 23:56:48.416685 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 23:56:48.416786 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:56:48.416886 in-header: 03 07 00 00 08 00 00 00
558 23:56:48.416987 in-data: aa e4 47 04 13 02 00 00
559 23:56:48.417086 Chrome EC: UHEPI supported
560 23:56:48.417186 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:56:48.417304 in-header: 03 a9 00 00 08 00 00 00
562 23:56:48.417407 in-data: 84 60 60 08 00 00 00 00
563 23:56:48.417506 MRC: failed to locate region type 0.
564 23:56:48.417606 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:56:48.417706 DRAM-K: Running full calibration
566 23:56:48.417804 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 23:56:48.417904 header.status = 0x0
568 23:56:48.418003 header.version = 0x6 (expected: 0x6)
569 23:56:48.418102 header.size = 0xd00 (expected: 0xd00)
570 23:56:48.418201 header.flags = 0x0
571 23:56:48.418300 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:56:48.418400 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
573 23:56:48.418500 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:56:48.418600 dram_init: ddr_geometry: 2
575 23:56:48.418699 [EMI] MDL number = 2
576 23:56:48.418798 [EMI] Get MDL freq = 0
577 23:56:48.418897 dram_init: ddr_type: 0
578 23:56:48.418996 is_discrete_lpddr4: 1
579 23:56:48.419096 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:56:48.419198
581 23:56:48.419297
582 23:56:48.419394 [Bian_co] ETT version 0.0.0.1
583 23:56:48.419493 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 23:56:48.419592
585 23:56:48.419689 dramc_set_vcore_voltage set vcore to 650000
586 23:56:48.419788 Read voltage for 800, 4
587 23:56:48.419887 Vio18 = 0
588 23:56:48.419993 Vcore = 650000
589 23:56:48.420076 Vdram = 0
590 23:56:48.420161 Vddq = 0
591 23:56:48.420244 Vmddr = 0
592 23:56:48.420328 dram_init: config_dvfs: 1
593 23:56:48.420413 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:56:48.420499 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:56:48.420585 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 23:56:48.420670 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 23:56:48.420755 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 23:56:48.420840 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 23:56:48.420925 MEM_TYPE=3, freq_sel=18
600 23:56:48.421010 sv_algorithm_assistance_LP4_1600
601 23:56:48.421094 ============ PULL DRAM RESETB DOWN ============
602 23:56:48.421184 ========== PULL DRAM RESETB DOWN end =========
603 23:56:48.421280 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:56:48.421369 ===================================
605 23:56:48.421454 LPDDR4 DRAM CONFIGURATION
606 23:56:48.421539 ===================================
607 23:56:48.421624 EX_ROW_EN[0] = 0x0
608 23:56:48.421710 EX_ROW_EN[1] = 0x0
609 23:56:48.421794 LP4Y_EN = 0x0
610 23:56:48.421879 WORK_FSP = 0x0
611 23:56:48.421964 WL = 0x2
612 23:56:48.422047 RL = 0x2
613 23:56:48.422132 BL = 0x2
614 23:56:48.422217 RPST = 0x0
615 23:56:48.422302 RD_PRE = 0x0
616 23:56:48.422386 WR_PRE = 0x1
617 23:56:48.422470 WR_PST = 0x0
618 23:56:48.422554 DBI_WR = 0x0
619 23:56:48.422638 DBI_RD = 0x0
620 23:56:48.422721 OTF = 0x1
621 23:56:48.422806 ===================================
622 23:56:48.422891 ===================================
623 23:56:48.422976 ANA top config
624 23:56:48.423060 ===================================
625 23:56:48.423145 DLL_ASYNC_EN = 0
626 23:56:48.423230 ALL_SLAVE_EN = 1
627 23:56:48.423314 NEW_RANK_MODE = 1
628 23:56:48.423399 DLL_IDLE_MODE = 1
629 23:56:48.423484 LP45_APHY_COMB_EN = 1
630 23:56:48.423568 TX_ODT_DIS = 1
631 23:56:48.423653 NEW_8X_MODE = 1
632 23:56:48.423737 ===================================
633 23:56:48.423822 ===================================
634 23:56:48.423961 data_rate = 1600
635 23:56:48.424083 CKR = 1
636 23:56:48.424172 DQ_P2S_RATIO = 8
637 23:56:48.424257 ===================================
638 23:56:48.424343 CA_P2S_RATIO = 8
639 23:56:48.424427 DQ_CA_OPEN = 0
640 23:56:48.424512 DQ_SEMI_OPEN = 0
641 23:56:48.424596 CA_SEMI_OPEN = 0
642 23:56:48.424679 CA_FULL_RATE = 0
643 23:56:48.424764 DQ_CKDIV4_EN = 1
644 23:56:48.424848 CA_CKDIV4_EN = 1
645 23:56:48.424932 CA_PREDIV_EN = 0
646 23:56:48.425023 PH8_DLY = 0
647 23:56:48.425097 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:56:48.425171 DQ_AAMCK_DIV = 4
649 23:56:48.425245 CA_AAMCK_DIV = 4
650 23:56:48.425337 CA_ADMCK_DIV = 4
651 23:56:48.425412 DQ_TRACK_CA_EN = 0
652 23:56:48.425486 CA_PICK = 800
653 23:56:48.425560 CA_MCKIO = 800
654 23:56:48.425634 MCKIO_SEMI = 0
655 23:56:48.425708 PLL_FREQ = 3068
656 23:56:48.425782 DQ_UI_PI_RATIO = 32
657 23:56:48.425856 CA_UI_PI_RATIO = 0
658 23:56:48.425929 ===================================
659 23:56:48.426004 ===================================
660 23:56:48.426079 memory_type:LPDDR4
661 23:56:48.426153 GP_NUM : 10
662 23:56:48.426227 SRAM_EN : 1
663 23:56:48.426301 MD32_EN : 0
664 23:56:48.426374 ===================================
665 23:56:48.426683 [ANA_INIT] >>>>>>>>>>>>>>
666 23:56:48.426766 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:56:48.426845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:56:48.426920 ===================================
669 23:56:48.426995 data_rate = 1600,PCW = 0X7600
670 23:56:48.427069 ===================================
671 23:56:48.427144 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:56:48.427218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:56:48.427293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:56:48.427367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:56:48.427442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:56:48.427516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:56:48.427590 [ANA_INIT] flow start
678 23:56:48.427664 [ANA_INIT] PLL >>>>>>>>
679 23:56:48.427738 [ANA_INIT] PLL <<<<<<<<
680 23:56:48.427812 [ANA_INIT] MIDPI >>>>>>>>
681 23:56:48.427885 [ANA_INIT] MIDPI <<<<<<<<
682 23:56:48.427960 [ANA_INIT] DLL >>>>>>>>
683 23:56:48.428033 [ANA_INIT] flow end
684 23:56:48.428107 ============ LP4 DIFF to SE enter ============
685 23:56:48.428182 ============ LP4 DIFF to SE exit ============
686 23:56:48.428258 [ANA_INIT] <<<<<<<<<<<<<
687 23:56:48.428332 [Flow] Enable top DCM control >>>>>
688 23:56:48.428407 [Flow] Enable top DCM control <<<<<
689 23:56:48.428481 Enable DLL master slave shuffle
690 23:56:48.428554 ==============================================================
691 23:56:48.428629 Gating Mode config
692 23:56:48.428703 ==============================================================
693 23:56:48.428778 Config description:
694 23:56:48.428853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:56:48.428928 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:56:48.429003 SELPH_MODE 0: By rank 1: By Phase
697 23:56:48.429078 ==============================================================
698 23:56:48.429152 GAT_TRACK_EN = 1
699 23:56:48.429226 RX_GATING_MODE = 2
700 23:56:48.429312 RX_GATING_TRACK_MODE = 2
701 23:56:48.429387 SELPH_MODE = 1
702 23:56:48.429461 PICG_EARLY_EN = 1
703 23:56:48.429536 VALID_LAT_VALUE = 1
704 23:56:48.429610 ==============================================================
705 23:56:48.429685 Enter into Gating configuration >>>>
706 23:56:48.429758 Exit from Gating configuration <<<<
707 23:56:48.429831 Enter into DVFS_PRE_config >>>>>
708 23:56:48.429919 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:56:48.430016 Exit from DVFS_PRE_config <<<<<
710 23:56:48.430082 Enter into PICG configuration >>>>
711 23:56:48.430148 Exit from PICG configuration <<<<
712 23:56:48.430215 [RX_INPUT] configuration >>>>>
713 23:56:48.430281 [RX_INPUT] configuration <<<<<
714 23:56:48.430347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:56:48.430414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:56:48.430480 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:56:48.430548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:56:48.430614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:56:48.430681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:56:48.430747 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:56:48.430813 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:56:48.430879 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:56:48.430946 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:56:48.431012 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:56:48.431078 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:56:48.431144 ===================================
727 23:56:48.431209 LPDDR4 DRAM CONFIGURATION
728 23:56:48.431275 ===================================
729 23:56:48.431340 EX_ROW_EN[0] = 0x0
730 23:56:48.431406 EX_ROW_EN[1] = 0x0
731 23:56:48.431471 LP4Y_EN = 0x0
732 23:56:48.431536 WORK_FSP = 0x0
733 23:56:48.431601 WL = 0x2
734 23:56:48.431667 RL = 0x2
735 23:56:48.431732 BL = 0x2
736 23:56:48.431797 RPST = 0x0
737 23:56:48.431863 RD_PRE = 0x0
738 23:56:48.431928 WR_PRE = 0x1
739 23:56:48.431993 WR_PST = 0x0
740 23:56:48.432069 DBI_WR = 0x0
741 23:56:48.432121 DBI_RD = 0x0
742 23:56:48.432173 OTF = 0x1
743 23:56:48.432226 ===================================
744 23:56:48.432279 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:56:48.432332 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:56:48.432385 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:56:48.432438 ===================================
748 23:56:48.432491 LPDDR4 DRAM CONFIGURATION
749 23:56:48.432544 ===================================
750 23:56:48.432597 EX_ROW_EN[0] = 0x10
751 23:56:48.432650 EX_ROW_EN[1] = 0x0
752 23:56:48.432702 LP4Y_EN = 0x0
753 23:56:48.432754 WORK_FSP = 0x0
754 23:56:48.432807 WL = 0x2
755 23:56:48.432859 RL = 0x2
756 23:56:48.432911 BL = 0x2
757 23:56:48.432964 RPST = 0x0
758 23:56:48.433016 RD_PRE = 0x0
759 23:56:48.433069 WR_PRE = 0x1
760 23:56:48.433121 WR_PST = 0x0
761 23:56:48.433174 DBI_WR = 0x0
762 23:56:48.433226 DBI_RD = 0x0
763 23:56:48.433321 OTF = 0x1
764 23:56:48.433374 ===================================
765 23:56:48.433428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:56:48.433481 nWR fixed to 40
767 23:56:48.433535 [ModeRegInit_LP4] CH0 RK0
768 23:56:48.433588 [ModeRegInit_LP4] CH0 RK1
769 23:56:48.433640 [ModeRegInit_LP4] CH1 RK0
770 23:56:48.433693 [ModeRegInit_LP4] CH1 RK1
771 23:56:48.433745 match AC timing 13
772 23:56:48.433797 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 23:56:48.434047 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:56:48.434113 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:56:48.434170 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:56:48.434225 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:56:48.434280 [EMI DOE] emi_dcm 0
778 23:56:48.434334 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:56:48.434435 ==
780 23:56:48.434503 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:56:48.434557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:56:48.434610 ==
783 23:56:48.434681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:56:48.434748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:56:48.434802 [CA 0] Center 37 (7~68) winsize 62
786 23:56:48.434855 [CA 1] Center 37 (6~68) winsize 63
787 23:56:48.434908 [CA 2] Center 34 (4~65) winsize 62
788 23:56:48.434961 [CA 3] Center 34 (4~65) winsize 62
789 23:56:48.435013 [CA 4] Center 33 (3~64) winsize 62
790 23:56:48.435066 [CA 5] Center 33 (3~64) winsize 62
791 23:56:48.435118
792 23:56:48.435171 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 23:56:48.435223
794 23:56:48.435276 [CATrainingPosCal] consider 1 rank data
795 23:56:48.435329 u2DelayCellTimex100 = 270/100 ps
796 23:56:48.435382 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 23:56:48.435452 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 23:56:48.435518 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 23:56:48.435571 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:56:48.435625 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 23:56:48.435677 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:56:48.435749
803 23:56:48.435837 CA PerBit enable=1, Macro0, CA PI delay=33
804 23:56:48.435942
805 23:56:48.436045 [CBTSetCACLKResult] CA Dly = 33
806 23:56:48.436140 CS Dly: 5 (0~36)
807 23:56:48.436229 ==
808 23:56:48.436315 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:56:48.436399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:56:48.436483 ==
811 23:56:48.436566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:56:48.436649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:56:48.436732 [CA 0] Center 38 (7~69) winsize 63
814 23:56:48.436815 [CA 1] Center 37 (7~68) winsize 62
815 23:56:48.436897 [CA 2] Center 35 (4~66) winsize 63
816 23:56:48.436979 [CA 3] Center 34 (4~65) winsize 62
817 23:56:48.437060 [CA 4] Center 34 (3~65) winsize 63
818 23:56:48.437141 [CA 5] Center 33 (3~64) winsize 62
819 23:56:48.437222
820 23:56:48.437330 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 23:56:48.437416
822 23:56:48.437511 [CATrainingPosCal] consider 2 rank data
823 23:56:48.437593 u2DelayCellTimex100 = 270/100 ps
824 23:56:48.437675 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 23:56:48.437757 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:56:48.437838 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 23:56:48.437965 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:56:48.438086 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 23:56:48.438198 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:56:48.438278
831 23:56:48.438358 CA PerBit enable=1, Macro0, CA PI delay=33
832 23:56:48.438438
833 23:56:48.438518 [CBTSetCACLKResult] CA Dly = 33
834 23:56:48.438620 CS Dly: 6 (0~38)
835 23:56:48.438714
836 23:56:48.438794 ----->DramcWriteLeveling(PI) begin...
837 23:56:48.438878 ==
838 23:56:48.438959 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:56:48.439040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 23:56:48.439136 ==
841 23:56:48.439231 Write leveling (Byte 0): 31 => 31
842 23:56:48.439311 Write leveling (Byte 1): 27 => 27
843 23:56:48.439390 DramcWriteLeveling(PI) end<-----
844 23:56:48.439468
845 23:56:48.439545 ==
846 23:56:48.439624 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:56:48.439704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 23:56:48.439785 ==
849 23:56:48.439866 [Gating] SW mode calibration
850 23:56:48.439952 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:56:48.440048 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:56:48.440146 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 23:56:48.440245 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:56:48.440372 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 23:56:48.440468 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:56:48.440573 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:56:48.440663 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:56:48.440726 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:56:48.440785 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:56:48.440842 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:56:48.440898 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:56:48.440953 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:56:48.441007 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:56:48.441062 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:56:48.441116 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:56:48.441188 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:56:48.441243 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:56:48.441321 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 23:56:48.441376 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
870 23:56:48.441430 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 23:56:48.441483 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
872 23:56:48.441536 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:56:48.441589 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:56:48.441642 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:56:48.441696 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:56:48.441748 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:56:48.441801 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:56:48.441855 0 9 8 | B1->B0 | 2323 2f2f | 1 1 | (1 1) (1 1)
879 23:56:48.441908 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
880 23:56:48.441961 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:56:48.442208 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:56:48.442269 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:56:48.442363 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:56:48.442417 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:56:48.442470 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
886 23:56:48.442524 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
887 23:56:48.442576 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
888 23:56:48.442630 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:56:48.442683 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:56:48.442736 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:56:48.442788 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:56:48.442841 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:56:48.442894 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
894 23:56:48.442947 0 11 8 | B1->B0 | 2b2b 4242 | 0 0 | (1 1) (0 0)
895 23:56:48.443000 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
896 23:56:48.443053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:56:48.443105 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:56:48.443158 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:56:48.443210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:56:48.443263 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:56:48.443316 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:56:48.443369 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 23:56:48.443422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:56:48.443475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:56:48.443528 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:56:48.443580 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:56:48.443633 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:56:48.443686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:56:48.443738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:56:48.443791 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:56:48.443844 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:56:48.443900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:56:48.443953 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:56:48.444005 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:56:48.444058 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:56:48.444110 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
917 23:56:48.444164 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:56:48.444216 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 23:56:48.444269 Total UI for P1: 0, mck2ui 16
920 23:56:48.444322 best dqsien dly found for B0: ( 0, 14, 6)
921 23:56:48.444375 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 23:56:48.444428 Total UI for P1: 0, mck2ui 16
923 23:56:48.444482 best dqsien dly found for B1: ( 0, 14, 8)
924 23:56:48.444535 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 23:56:48.444588 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 23:56:48.444641
927 23:56:48.444694 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 23:56:48.444747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:56:48.444800 [Gating] SW calibration Done
930 23:56:48.444853 ==
931 23:56:48.444906 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:56:48.444958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:56:48.445012 ==
934 23:56:48.445064 RX Vref Scan: 0
935 23:56:48.445117
936 23:56:48.445170 RX Vref 0 -> 0, step: 1
937 23:56:48.445222
938 23:56:48.445300 RX Delay -130 -> 252, step: 16
939 23:56:48.445369 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 23:56:48.445422 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 23:56:48.445477 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
942 23:56:48.445530 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 23:56:48.445582 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 23:56:48.445635 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 23:56:48.445687 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 23:56:48.445739 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
947 23:56:48.445793 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 23:56:48.445845 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
949 23:56:48.445898 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
950 23:56:48.445951 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 23:56:48.446003 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
952 23:56:48.446056 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
953 23:56:48.446109 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 23:56:48.446162 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 23:56:48.446215 ==
956 23:56:48.446268 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:56:48.446320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:56:48.446373 ==
959 23:56:48.446425 DQS Delay:
960 23:56:48.446478 DQS0 = 0, DQS1 = 0
961 23:56:48.446529 DQM Delay:
962 23:56:48.446582 DQM0 = 91, DQM1 = 76
963 23:56:48.446634 DQ Delay:
964 23:56:48.446687 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
965 23:56:48.446740 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
966 23:56:48.446792 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
967 23:56:48.446845 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
968 23:56:48.446898
969 23:56:48.446950
970 23:56:48.447002 ==
971 23:56:48.447054 Dram Type= 6, Freq= 0, CH_0, rank 0
972 23:56:48.447107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 23:56:48.447160 ==
974 23:56:48.447212
975 23:56:48.447264
976 23:56:48.447316 TX Vref Scan disable
977 23:56:48.447369 == TX Byte 0 ==
978 23:56:48.447422 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
979 23:56:48.447476 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
980 23:56:48.447529 == TX Byte 1 ==
981 23:56:48.447582 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
982 23:56:48.447634 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
983 23:56:48.447688 ==
984 23:56:48.447740 Dram Type= 6, Freq= 0, CH_0, rank 0
985 23:56:48.447793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 23:56:48.447846 ==
987 23:56:48.447900 TX Vref=22, minBit 1, minWin=27, winSum=440
988 23:56:48.447953 TX Vref=24, minBit 2, minWin=27, winSum=442
989 23:56:48.448198 TX Vref=26, minBit 3, minWin=27, winSum=446
990 23:56:48.448257 TX Vref=28, minBit 1, minWin=27, winSum=448
991 23:56:48.448311 TX Vref=30, minBit 1, minWin=27, winSum=448
992 23:56:48.448364 TX Vref=32, minBit 1, minWin=27, winSum=447
993 23:56:48.448417 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 28
994 23:56:48.448470
995 23:56:48.448524 Final TX Range 1 Vref 28
996 23:56:48.448576
997 23:56:48.448629 ==
998 23:56:48.448682 Dram Type= 6, Freq= 0, CH_0, rank 0
999 23:56:48.448735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 23:56:48.448788 ==
1001 23:56:48.448840
1002 23:56:48.448892
1003 23:56:48.448945 TX Vref Scan disable
1004 23:56:48.448998 == TX Byte 0 ==
1005 23:56:48.449051 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1006 23:56:48.449104 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1007 23:56:48.449157 == TX Byte 1 ==
1008 23:56:48.449210 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1009 23:56:48.449288 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1010 23:56:48.449356
1011 23:56:48.449410 [DATLAT]
1012 23:56:48.449464 Freq=800, CH0 RK0
1013 23:56:48.449517
1014 23:56:48.449570 DATLAT Default: 0xa
1015 23:56:48.449622 0, 0xFFFF, sum = 0
1016 23:56:48.449677 1, 0xFFFF, sum = 0
1017 23:56:48.449731 2, 0xFFFF, sum = 0
1018 23:56:48.449784 3, 0xFFFF, sum = 0
1019 23:56:48.449855 4, 0xFFFF, sum = 0
1020 23:56:48.449913 5, 0xFFFF, sum = 0
1021 23:56:48.449967 6, 0xFFFF, sum = 0
1022 23:56:48.450021 7, 0xFFFF, sum = 0
1023 23:56:48.450075 8, 0xFFFF, sum = 0
1024 23:56:48.450129 9, 0x0, sum = 1
1025 23:56:48.450190 10, 0x0, sum = 2
1026 23:56:48.450251 11, 0x0, sum = 3
1027 23:56:48.450306 12, 0x0, sum = 4
1028 23:56:48.450360 best_step = 10
1029 23:56:48.450413
1030 23:56:48.450465 ==
1031 23:56:48.450517 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 23:56:48.450572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 23:56:48.450626 ==
1034 23:56:48.450679 RX Vref Scan: 1
1035 23:56:48.450731
1036 23:56:48.450783 Set Vref Range= 32 -> 127
1037 23:56:48.450836
1038 23:56:48.450888 RX Vref 32 -> 127, step: 1
1039 23:56:48.450941
1040 23:56:48.450992 RX Delay -111 -> 252, step: 8
1041 23:56:48.451044
1042 23:56:48.451096 Set Vref, RX VrefLevel [Byte0]: 32
1043 23:56:48.451149 [Byte1]: 32
1044 23:56:48.451201
1045 23:56:48.451253 Set Vref, RX VrefLevel [Byte0]: 33
1046 23:56:48.451306 [Byte1]: 33
1047 23:56:48.451358
1048 23:56:48.451410 Set Vref, RX VrefLevel [Byte0]: 34
1049 23:56:48.451462 [Byte1]: 34
1050 23:56:48.451515
1051 23:56:48.451568 Set Vref, RX VrefLevel [Byte0]: 35
1052 23:56:48.451620 [Byte1]: 35
1053 23:56:48.451672
1054 23:56:48.451724 Set Vref, RX VrefLevel [Byte0]: 36
1055 23:56:48.451777 [Byte1]: 36
1056 23:56:48.451830
1057 23:56:48.451882 Set Vref, RX VrefLevel [Byte0]: 37
1058 23:56:48.451934 [Byte1]: 37
1059 23:56:48.451986
1060 23:56:48.452038 Set Vref, RX VrefLevel [Byte0]: 38
1061 23:56:48.452089 [Byte1]: 38
1062 23:56:48.452141
1063 23:56:48.452193 Set Vref, RX VrefLevel [Byte0]: 39
1064 23:56:48.452246 [Byte1]: 39
1065 23:56:48.452298
1066 23:56:48.452350 Set Vref, RX VrefLevel [Byte0]: 40
1067 23:56:48.452402 [Byte1]: 40
1068 23:56:48.452454
1069 23:56:48.452506 Set Vref, RX VrefLevel [Byte0]: 41
1070 23:56:48.452558 [Byte1]: 41
1071 23:56:48.452610
1072 23:56:48.452661 Set Vref, RX VrefLevel [Byte0]: 42
1073 23:56:48.452714 [Byte1]: 42
1074 23:56:48.452766
1075 23:56:48.452818 Set Vref, RX VrefLevel [Byte0]: 43
1076 23:56:48.452870 [Byte1]: 43
1077 23:56:48.452922
1078 23:56:48.452974 Set Vref, RX VrefLevel [Byte0]: 44
1079 23:56:48.453026 [Byte1]: 44
1080 23:56:48.453078
1081 23:56:48.453130 Set Vref, RX VrefLevel [Byte0]: 45
1082 23:56:48.453182 [Byte1]: 45
1083 23:56:48.453234
1084 23:56:48.453326 Set Vref, RX VrefLevel [Byte0]: 46
1085 23:56:48.453379 [Byte1]: 46
1086 23:56:48.453432
1087 23:56:48.453484 Set Vref, RX VrefLevel [Byte0]: 47
1088 23:56:48.453536 [Byte1]: 47
1089 23:56:48.453588
1090 23:56:48.453640 Set Vref, RX VrefLevel [Byte0]: 48
1091 23:56:48.453692 [Byte1]: 48
1092 23:56:48.453744
1093 23:56:48.453795 Set Vref, RX VrefLevel [Byte0]: 49
1094 23:56:48.453847 [Byte1]: 49
1095 23:56:48.453899
1096 23:56:48.453951 Set Vref, RX VrefLevel [Byte0]: 50
1097 23:56:48.454003 [Byte1]: 50
1098 23:56:48.454056
1099 23:56:48.454107 Set Vref, RX VrefLevel [Byte0]: 51
1100 23:56:48.454159 [Byte1]: 51
1101 23:56:48.454211
1102 23:56:48.454264 Set Vref, RX VrefLevel [Byte0]: 52
1103 23:56:48.454317 [Byte1]: 52
1104 23:56:48.454369
1105 23:56:48.454421 Set Vref, RX VrefLevel [Byte0]: 53
1106 23:56:48.454473 [Byte1]: 53
1107 23:56:48.454525
1108 23:56:48.454577 Set Vref, RX VrefLevel [Byte0]: 54
1109 23:56:48.454629 [Byte1]: 54
1110 23:56:48.454680
1111 23:56:48.454732 Set Vref, RX VrefLevel [Byte0]: 55
1112 23:56:48.454784 [Byte1]: 55
1113 23:56:48.454835
1114 23:56:48.454886 Set Vref, RX VrefLevel [Byte0]: 56
1115 23:56:48.454938 [Byte1]: 56
1116 23:56:48.454990
1117 23:56:48.455041 Set Vref, RX VrefLevel [Byte0]: 57
1118 23:56:48.455093 [Byte1]: 57
1119 23:56:48.455145
1120 23:56:48.455197 Set Vref, RX VrefLevel [Byte0]: 58
1121 23:56:48.455249 [Byte1]: 58
1122 23:56:48.455301
1123 23:56:48.455353 Set Vref, RX VrefLevel [Byte0]: 59
1124 23:56:48.455406 [Byte1]: 59
1125 23:56:48.455458
1126 23:56:48.455510 Set Vref, RX VrefLevel [Byte0]: 60
1127 23:56:48.455562 [Byte1]: 60
1128 23:56:48.455615
1129 23:56:48.455667 Set Vref, RX VrefLevel [Byte0]: 61
1130 23:56:48.455718 [Byte1]: 61
1131 23:56:48.455770
1132 23:56:48.455822 Set Vref, RX VrefLevel [Byte0]: 62
1133 23:56:48.455875 [Byte1]: 62
1134 23:56:48.455926
1135 23:56:48.455978 Set Vref, RX VrefLevel [Byte0]: 63
1136 23:56:48.456030 [Byte1]: 63
1137 23:56:48.456082
1138 23:56:48.456134 Set Vref, RX VrefLevel [Byte0]: 64
1139 23:56:48.456187 [Byte1]: 64
1140 23:56:48.456239
1141 23:56:48.456291 Set Vref, RX VrefLevel [Byte0]: 65
1142 23:56:48.456343 [Byte1]: 65
1143 23:56:48.456395
1144 23:56:48.456447 Set Vref, RX VrefLevel [Byte0]: 66
1145 23:56:48.456499 [Byte1]: 66
1146 23:56:48.456552
1147 23:56:48.456604 Set Vref, RX VrefLevel [Byte0]: 67
1148 23:56:48.456657 [Byte1]: 67
1149 23:56:48.456709
1150 23:56:48.456761 Set Vref, RX VrefLevel [Byte0]: 68
1151 23:56:48.456814 [Byte1]: 68
1152 23:56:48.456866
1153 23:56:48.456918 Set Vref, RX VrefLevel [Byte0]: 69
1154 23:56:48.456969 [Byte1]: 69
1155 23:56:48.457022
1156 23:56:48.457074 Set Vref, RX VrefLevel [Byte0]: 70
1157 23:56:48.457328 [Byte1]: 70
1158 23:56:48.457388
1159 23:56:48.457441 Set Vref, RX VrefLevel [Byte0]: 71
1160 23:56:48.457494 [Byte1]: 71
1161 23:56:48.457546
1162 23:56:48.457599 Set Vref, RX VrefLevel [Byte0]: 72
1163 23:56:48.457668 [Byte1]: 72
1164 23:56:48.457735
1165 23:56:48.457787 Set Vref, RX VrefLevel [Byte0]: 73
1166 23:56:48.457869 [Byte1]: 73
1167 23:56:48.457921
1168 23:56:48.457973 Set Vref, RX VrefLevel [Byte0]: 74
1169 23:56:48.458025 [Byte1]: 74
1170 23:56:48.458091
1171 23:56:48.458147 Set Vref, RX VrefLevel [Byte0]: 75
1172 23:56:48.458200 [Byte1]: 75
1173 23:56:48.458252
1174 23:56:48.458305 Final RX Vref Byte 0 = 54 to rank0
1175 23:56:48.458358 Final RX Vref Byte 1 = 59 to rank0
1176 23:56:48.458427 Final RX Vref Byte 0 = 54 to rank1
1177 23:56:48.458494 Final RX Vref Byte 1 = 59 to rank1==
1178 23:56:48.458547 Dram Type= 6, Freq= 0, CH_0, rank 0
1179 23:56:48.458600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1180 23:56:48.458653 ==
1181 23:56:48.458705 DQS Delay:
1182 23:56:48.458757 DQS0 = 0, DQS1 = 0
1183 23:56:48.458810 DQM Delay:
1184 23:56:48.458862 DQM0 = 88, DQM1 = 76
1185 23:56:48.458915 DQ Delay:
1186 23:56:48.458967 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1187 23:56:48.459020 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1188 23:56:48.459073 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1189 23:56:48.459125 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1190 23:56:48.459177
1191 23:56:48.459229
1192 23:56:48.459281 [DQSOSCAuto] RK0, (LSB)MR18= 0x362f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
1193 23:56:48.459335 CH0 RK0: MR19=606, MR18=362F
1194 23:56:48.459387 CH0_RK0: MR19=0x606, MR18=0x362F, DQSOSC=396, MR23=63, INC=94, DEC=62
1195 23:56:48.459440
1196 23:56:48.459493 ----->DramcWriteLeveling(PI) begin...
1197 23:56:48.459546 ==
1198 23:56:48.459599 Dram Type= 6, Freq= 0, CH_0, rank 1
1199 23:56:48.459651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1200 23:56:48.459704 ==
1201 23:56:48.459757 Write leveling (Byte 0): 29 => 29
1202 23:56:48.459810 Write leveling (Byte 1): 28 => 28
1203 23:56:48.459862 DramcWriteLeveling(PI) end<-----
1204 23:56:48.459915
1205 23:56:48.459966 ==
1206 23:56:48.460019 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 23:56:48.460071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 23:56:48.460124 ==
1209 23:56:48.460177 [Gating] SW mode calibration
1210 23:56:48.460230 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1211 23:56:48.460282 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1212 23:56:48.460335 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1213 23:56:48.460388 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1214 23:56:48.460440 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1215 23:56:48.460492 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:56:48.460545 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:56:48.460598 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:56:48.460650 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:56:48.460702 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:56:48.460754 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:56:48.460807 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:56:48.460859 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:56:48.460912 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:56:48.460964 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:56:48.461016 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:56:48.461069 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:56:48.461121 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:56:48.461173 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1229 23:56:48.461226 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1230 23:56:48.461321 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:56:48.461375 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1232 23:56:48.461427 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:56:48.461480 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:56:48.461532 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:56:48.461585 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:56:48.461637 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:56:48.461690 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1238 23:56:48.461742 0 9 8 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
1239 23:56:48.461794 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 23:56:48.461846 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 23:56:48.461898 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 23:56:48.461951 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 23:56:48.462003 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 23:56:48.462055 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 23:56:48.462110 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
1246 23:56:48.462163 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
1247 23:56:48.462215 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1248 23:56:48.462268 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:56:48.462320 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:56:48.462373 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:56:48.462426 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:56:48.462478 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:56:48.462531 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1254 23:56:48.462583 0 11 8 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
1255 23:56:48.462636 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 23:56:48.462688 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 23:56:48.462740 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:56:48.462793 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 23:56:48.462845 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:56:48.462896 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 23:56:48.463142 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1262 23:56:48.463204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1263 23:56:48.463257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:56:48.463327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:56:48.463393 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:56:48.463446 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:56:48.463498 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:56:48.463551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:56:48.463604 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:56:48.463656 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:56:48.463708 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:56:48.463760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:56:48.463813 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:56:48.463865 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:56:48.463917 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:56:48.463970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:56:48.464022 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1278 23:56:48.464075 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1279 23:56:48.464127 Total UI for P1: 0, mck2ui 16
1280 23:56:48.464180 best dqsien dly found for B0: ( 0, 14, 4)
1281 23:56:48.464233 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 23:56:48.464286 Total UI for P1: 0, mck2ui 16
1283 23:56:48.464338 best dqsien dly found for B1: ( 0, 14, 8)
1284 23:56:48.464391 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1285 23:56:48.464468 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1286 23:56:48.464535
1287 23:56:48.464587 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1288 23:56:48.464640 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1289 23:56:48.464692 [Gating] SW calibration Done
1290 23:56:48.464744 ==
1291 23:56:48.464796 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 23:56:48.464849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 23:56:48.464902 ==
1294 23:56:48.464954 RX Vref Scan: 0
1295 23:56:48.465007
1296 23:56:48.465059 RX Vref 0 -> 0, step: 1
1297 23:56:48.465110
1298 23:56:48.465162 RX Delay -130 -> 252, step: 16
1299 23:56:48.465214 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1300 23:56:48.465288 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1301 23:56:48.465356 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1302 23:56:48.465409 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1303 23:56:48.465462 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1304 23:56:48.465514 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1305 23:56:48.465566 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1306 23:56:48.465619 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1307 23:56:48.465672 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1308 23:56:48.465724 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1309 23:56:48.465777 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1310 23:56:48.465829 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1311 23:56:48.465882 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1312 23:56:48.465934 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1313 23:56:48.465986 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1314 23:56:48.466038 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1315 23:56:48.466091 ==
1316 23:56:48.466144 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 23:56:48.466196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 23:56:48.466248 ==
1319 23:56:48.466301 DQS Delay:
1320 23:56:48.466352 DQS0 = 0, DQS1 = 0
1321 23:56:48.466405 DQM Delay:
1322 23:56:48.466457 DQM0 = 86, DQM1 = 77
1323 23:56:48.466509 DQ Delay:
1324 23:56:48.466561 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1325 23:56:48.466613 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1326 23:56:48.466666 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1327 23:56:48.466718 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1328 23:56:48.466771
1329 23:56:48.466823
1330 23:56:48.466874 ==
1331 23:56:48.466926 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 23:56:48.466979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 23:56:48.467032 ==
1334 23:56:48.467084
1335 23:56:48.467160
1336 23:56:48.467226 TX Vref Scan disable
1337 23:56:48.467278 == TX Byte 0 ==
1338 23:56:48.467331 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1339 23:56:48.467384 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1340 23:56:48.467436 == TX Byte 1 ==
1341 23:56:48.467489 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1342 23:56:48.467542 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1343 23:56:48.467617 ==
1344 23:56:48.467682 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 23:56:48.467735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 23:56:48.467788 ==
1347 23:56:48.467841 TX Vref=22, minBit 0, minWin=27, winSum=440
1348 23:56:48.467893 TX Vref=24, minBit 3, minWin=27, winSum=445
1349 23:56:48.467945 TX Vref=26, minBit 0, minWin=27, winSum=447
1350 23:56:48.467998 TX Vref=28, minBit 2, minWin=27, winSum=448
1351 23:56:48.468051 TX Vref=30, minBit 1, minWin=27, winSum=448
1352 23:56:48.468103 TX Vref=32, minBit 6, minWin=27, winSum=449
1353 23:56:48.468173 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 32
1354 23:56:48.468255
1355 23:56:48.468322 Final TX Range 1 Vref 32
1356 23:56:48.468374
1357 23:56:48.468426 ==
1358 23:56:48.468478 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 23:56:48.468530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 23:56:48.468582 ==
1361 23:56:48.468634
1362 23:56:48.468686
1363 23:56:48.468737 TX Vref Scan disable
1364 23:56:48.468789 == TX Byte 0 ==
1365 23:56:48.468841 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1366 23:56:48.468893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1367 23:56:48.468946 == TX Byte 1 ==
1368 23:56:48.468997 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1369 23:56:48.469048 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1370 23:56:48.469101
1371 23:56:48.469169 [DATLAT]
1372 23:56:48.469221 Freq=800, CH0 RK1
1373 23:56:48.469294
1374 23:56:48.469346 DATLAT Default: 0xa
1375 23:56:48.469398 0, 0xFFFF, sum = 0
1376 23:56:48.469452 1, 0xFFFF, sum = 0
1377 23:56:48.469504 2, 0xFFFF, sum = 0
1378 23:56:48.469556 3, 0xFFFF, sum = 0
1379 23:56:48.469609 4, 0xFFFF, sum = 0
1380 23:56:48.469661 5, 0xFFFF, sum = 0
1381 23:56:48.469714 6, 0xFFFF, sum = 0
1382 23:56:48.469765 7, 0xFFFF, sum = 0
1383 23:56:48.469818 8, 0xFFFF, sum = 0
1384 23:56:48.469870 9, 0x0, sum = 1
1385 23:56:48.469923 10, 0x0, sum = 2
1386 23:56:48.469976 11, 0x0, sum = 3
1387 23:56:48.470029 12, 0x0, sum = 4
1388 23:56:48.470082 best_step = 10
1389 23:56:48.470134
1390 23:56:48.470186 ==
1391 23:56:48.470238 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 23:56:48.470483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 23:56:48.470542 ==
1394 23:56:48.470596 RX Vref Scan: 0
1395 23:56:48.470648
1396 23:56:48.470700 RX Vref 0 -> 0, step: 1
1397 23:56:48.470751
1398 23:56:48.470803 RX Delay -95 -> 252, step: 8
1399 23:56:48.470855 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1400 23:56:48.470907 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1401 23:56:48.470959 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1402 23:56:48.471010 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1403 23:56:48.471062 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1404 23:56:48.471114 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1405 23:56:48.471168 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1406 23:56:48.471220 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1407 23:56:48.471272 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1408 23:56:48.471323 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1409 23:56:48.471375 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1410 23:56:48.471426 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1411 23:56:48.471477 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1412 23:56:48.471529 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1413 23:56:48.471581 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1414 23:56:48.471632 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1415 23:56:48.471705 ==
1416 23:56:48.471771 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 23:56:48.471822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 23:56:48.471874 ==
1419 23:56:48.471926 DQS Delay:
1420 23:56:48.471977 DQS0 = 0, DQS1 = 0
1421 23:56:48.472029 DQM Delay:
1422 23:56:48.472081 DQM0 = 86, DQM1 = 76
1423 23:56:48.472132 DQ Delay:
1424 23:56:48.472183 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1425 23:56:48.472235 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1426 23:56:48.472286 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1427 23:56:48.472338 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =80
1428 23:56:48.472390
1429 23:56:48.472441
1430 23:56:48.472492 [DQSOSCAuto] RK1, (LSB)MR18= 0x2823, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1431 23:56:48.472545 CH0 RK1: MR19=606, MR18=2823
1432 23:56:48.472597 CH0_RK1: MR19=0x606, MR18=0x2823, DQSOSC=399, MR23=63, INC=92, DEC=61
1433 23:56:48.472649 [RxdqsGatingPostProcess] freq 800
1434 23:56:48.472701 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 23:56:48.472754 Pre-setting of DQS Precalculation
1436 23:56:48.472806 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 23:56:48.472858 ==
1438 23:56:48.472910 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 23:56:48.472961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 23:56:48.473013 ==
1441 23:56:48.473065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 23:56:48.473117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 23:56:48.473169 [CA 0] Center 37 (6~68) winsize 63
1444 23:56:48.473222 [CA 1] Center 37 (6~68) winsize 63
1445 23:56:48.473309 [CA 2] Center 35 (5~65) winsize 61
1446 23:56:48.473362 [CA 3] Center 34 (4~65) winsize 62
1447 23:56:48.473414 [CA 4] Center 34 (4~65) winsize 62
1448 23:56:48.473465 [CA 5] Center 34 (3~65) winsize 63
1449 23:56:48.473516
1450 23:56:48.473567 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1451 23:56:48.473619
1452 23:56:48.473670 [CATrainingPosCal] consider 1 rank data
1453 23:56:48.473721 u2DelayCellTimex100 = 270/100 ps
1454 23:56:48.473773 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1455 23:56:48.473824 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1456 23:56:48.473876 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1457 23:56:48.473928 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 23:56:48.473980 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 23:56:48.474032 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1460 23:56:48.474084
1461 23:56:48.474135 CA PerBit enable=1, Macro0, CA PI delay=34
1462 23:56:48.474186
1463 23:56:48.474237 [CBTSetCACLKResult] CA Dly = 34
1464 23:56:48.474289 CS Dly: 4 (0~35)
1465 23:56:48.474340 ==
1466 23:56:48.474392 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 23:56:48.474444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 23:56:48.474496 ==
1469 23:56:48.474548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 23:56:48.474600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 23:56:48.474652 [CA 0] Center 37 (6~68) winsize 63
1472 23:56:48.474703 [CA 1] Center 36 (6~67) winsize 62
1473 23:56:48.474754 [CA 2] Center 34 (4~65) winsize 62
1474 23:56:48.474805 [CA 3] Center 34 (3~65) winsize 63
1475 23:56:48.474857 [CA 4] Center 34 (3~65) winsize 63
1476 23:56:48.474908 [CA 5] Center 34 (3~65) winsize 63
1477 23:56:48.474959
1478 23:56:48.475010 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1479 23:56:48.475061
1480 23:56:48.475113 [CATrainingPosCal] consider 2 rank data
1481 23:56:48.475164 u2DelayCellTimex100 = 270/100 ps
1482 23:56:48.475216 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1483 23:56:48.475268 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 23:56:48.475320 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1485 23:56:48.475370 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 23:56:48.475422 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 23:56:48.475473 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1488 23:56:48.475525
1489 23:56:48.475576 CA PerBit enable=1, Macro0, CA PI delay=34
1490 23:56:48.475628
1491 23:56:48.475679 [CBTSetCACLKResult] CA Dly = 34
1492 23:56:48.475730 CS Dly: 5 (0~37)
1493 23:56:48.475828
1494 23:56:48.475893 ----->DramcWriteLeveling(PI) begin...
1495 23:56:48.475946 ==
1496 23:56:48.475998 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 23:56:48.476050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 23:56:48.476102 ==
1499 23:56:48.476182 Write leveling (Byte 0): 26 => 26
1500 23:56:48.476234 Write leveling (Byte 1): 26 => 26
1501 23:56:48.476286 DramcWriteLeveling(PI) end<-----
1502 23:56:48.476337
1503 23:56:48.476389 ==
1504 23:56:48.476439 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 23:56:48.476491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 23:56:48.476544 ==
1507 23:56:48.476595 [Gating] SW mode calibration
1508 23:56:48.476647 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 23:56:48.476699 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 23:56:48.476751 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 23:56:48.476804 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1512 23:56:48.476892 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1513 23:56:48.476944 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:56:48.477188 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:56:48.477246 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:56:48.477341 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:56:48.477409 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:56:48.477475 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:56:48.477527 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:56:48.477579 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:56:48.477632 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:56:48.477684 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:56:48.477735 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:56:48.477787 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:56:48.477839 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:56:48.477891 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1527 23:56:48.477942 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1528 23:56:48.477994 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1529 23:56:48.478046 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:56:48.478098 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:56:48.478149 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:56:48.478201 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:56:48.478252 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:56:48.478304 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:56:48.478356 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1536 23:56:48.478407 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1537 23:56:48.478459 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 23:56:48.478510 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 23:56:48.478561 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 23:56:48.478613 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 23:56:48.478664 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 23:56:48.478716 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 23:56:48.478768 0 10 4 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (0 0)
1544 23:56:48.478819 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1545 23:56:48.478871 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:56:48.478923 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:56:48.478975 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:56:48.479027 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:56:48.479078 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:56:48.479129 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:56:48.479181 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1552 23:56:48.479233 0 11 8 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
1553 23:56:48.479285 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 23:56:48.479337 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 23:56:48.479389 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:56:48.479441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 23:56:48.479493 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 23:56:48.479544 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 23:56:48.479596 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1560 23:56:48.479648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 23:56:48.479700 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:56:48.479751 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:56:48.479803 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:56:48.479855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:56:48.479906 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:56:48.479958 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:56:48.480024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:56:48.480089 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:56:48.480140 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:56:48.480215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:56:48.480268 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:56:48.480333 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:56:48.480402 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:56:48.480467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:56:48.480519 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1576 23:56:48.480571 Total UI for P1: 0, mck2ui 16
1577 23:56:48.480624 best dqsien dly found for B0: ( 0, 14, 2)
1578 23:56:48.480676 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1579 23:56:48.480728 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 23:56:48.480779 Total UI for P1: 0, mck2ui 16
1581 23:56:48.480832 best dqsien dly found for B1: ( 0, 14, 6)
1582 23:56:48.480884 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1583 23:56:48.480935 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1584 23:56:48.480987
1585 23:56:48.481039 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1586 23:56:48.481114 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1587 23:56:48.481166 [Gating] SW calibration Done
1588 23:56:48.481220 ==
1589 23:56:48.481295 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 23:56:48.481349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 23:56:48.481401 ==
1592 23:56:48.481453 RX Vref Scan: 0
1593 23:56:48.481505
1594 23:56:48.481570 RX Vref 0 -> 0, step: 1
1595 23:56:48.481650
1596 23:56:48.481744 RX Delay -130 -> 252, step: 16
1597 23:56:48.481795 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1598 23:56:48.481847 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1599 23:56:48.481899 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1600 23:56:48.481950 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1601 23:56:48.482001 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1602 23:56:48.482053 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1603 23:56:48.482296 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1604 23:56:48.482358 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1605 23:56:48.482429 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1606 23:56:48.482496 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1607 23:56:48.482547 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1608 23:56:48.482599 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1609 23:56:48.482651 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1610 23:56:48.482703 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1611 23:56:48.482755 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1612 23:56:48.482807 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1613 23:56:48.482859 ==
1614 23:56:48.482911 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 23:56:48.482963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 23:56:48.483015 ==
1617 23:56:48.483067 DQS Delay:
1618 23:56:48.483118 DQS0 = 0, DQS1 = 0
1619 23:56:48.483211 DQM Delay:
1620 23:56:48.483262 DQM0 = 87, DQM1 = 83
1621 23:56:48.483314 DQ Delay:
1622 23:56:48.483365 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1623 23:56:48.483417 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1624 23:56:48.483469 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1625 23:56:48.483520 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1626 23:56:48.483572
1627 23:56:48.483623
1628 23:56:48.483676 ==
1629 23:56:48.483727 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 23:56:48.483779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 23:56:48.483831 ==
1632 23:56:48.483883
1633 23:56:48.483934
1634 23:56:48.483985 TX Vref Scan disable
1635 23:56:48.484037 == TX Byte 0 ==
1636 23:56:48.484089 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1637 23:56:48.484142 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1638 23:56:48.484194 == TX Byte 1 ==
1639 23:56:48.484246 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1640 23:56:48.484298 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1641 23:56:48.484350 ==
1642 23:56:48.484401 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 23:56:48.484453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 23:56:48.484505 ==
1645 23:56:48.484556 TX Vref=22, minBit 1, minWin=27, winSum=442
1646 23:56:48.484609 TX Vref=24, minBit 2, minWin=27, winSum=448
1647 23:56:48.484661 TX Vref=26, minBit 6, minWin=27, winSum=454
1648 23:56:48.484714 TX Vref=28, minBit 6, minWin=27, winSum=456
1649 23:56:48.484765 TX Vref=30, minBit 6, minWin=27, winSum=456
1650 23:56:48.484817 TX Vref=32, minBit 6, minWin=27, winSum=456
1651 23:56:48.484869 [TxChooseVref] Worse bit 6, Min win 27, Win sum 456, Final Vref 28
1652 23:56:48.484921
1653 23:56:48.484973 Final TX Range 1 Vref 28
1654 23:56:48.485024
1655 23:56:48.485075 ==
1656 23:56:48.485128 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 23:56:48.485179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 23:56:48.485231 ==
1659 23:56:48.485324
1660 23:56:48.485376
1661 23:56:48.485427 TX Vref Scan disable
1662 23:56:48.485479 == TX Byte 0 ==
1663 23:56:48.485531 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1664 23:56:48.485583 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1665 23:56:48.485635 == TX Byte 1 ==
1666 23:56:48.485687 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1667 23:56:48.485739 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1668 23:56:48.485791
1669 23:56:48.485842 [DATLAT]
1670 23:56:48.485894 Freq=800, CH1 RK0
1671 23:56:48.485945
1672 23:56:48.485996 DATLAT Default: 0xa
1673 23:56:48.486047 0, 0xFFFF, sum = 0
1674 23:56:48.486100 1, 0xFFFF, sum = 0
1675 23:56:48.486153 2, 0xFFFF, sum = 0
1676 23:56:48.486206 3, 0xFFFF, sum = 0
1677 23:56:48.486258 4, 0xFFFF, sum = 0
1678 23:56:48.486311 5, 0xFFFF, sum = 0
1679 23:56:48.486363 6, 0xFFFF, sum = 0
1680 23:56:48.486415 7, 0xFFFF, sum = 0
1681 23:56:48.486467 8, 0xFFFF, sum = 0
1682 23:56:48.486520 9, 0x0, sum = 1
1683 23:56:48.486573 10, 0x0, sum = 2
1684 23:56:48.486625 11, 0x0, sum = 3
1685 23:56:48.486678 12, 0x0, sum = 4
1686 23:56:48.486730 best_step = 10
1687 23:56:48.486781
1688 23:56:48.486832 ==
1689 23:56:48.486884 Dram Type= 6, Freq= 0, CH_1, rank 0
1690 23:56:48.486936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1691 23:56:48.486988 ==
1692 23:56:48.487039 RX Vref Scan: 1
1693 23:56:48.487090
1694 23:56:48.487142 Set Vref Range= 32 -> 127
1695 23:56:48.487194
1696 23:56:48.487245 RX Vref 32 -> 127, step: 1
1697 23:56:48.487297
1698 23:56:48.487348 RX Delay -95 -> 252, step: 8
1699 23:56:48.487399
1700 23:56:48.487451 Set Vref, RX VrefLevel [Byte0]: 32
1701 23:56:48.487502 [Byte1]: 32
1702 23:56:48.487554
1703 23:56:48.487605 Set Vref, RX VrefLevel [Byte0]: 33
1704 23:56:48.487657 [Byte1]: 33
1705 23:56:48.487710
1706 23:56:48.487761 Set Vref, RX VrefLevel [Byte0]: 34
1707 23:56:48.487813 [Byte1]: 34
1708 23:56:48.487865
1709 23:56:48.487916 Set Vref, RX VrefLevel [Byte0]: 35
1710 23:56:48.487967 [Byte1]: 35
1711 23:56:48.488019
1712 23:56:48.488071 Set Vref, RX VrefLevel [Byte0]: 36
1713 23:56:48.488122 [Byte1]: 36
1714 23:56:48.488173
1715 23:56:48.488225 Set Vref, RX VrefLevel [Byte0]: 37
1716 23:56:48.488277 [Byte1]: 37
1717 23:56:48.488329
1718 23:56:48.488380 Set Vref, RX VrefLevel [Byte0]: 38
1719 23:56:48.488457 [Byte1]: 38
1720 23:56:48.488524
1721 23:56:48.488575 Set Vref, RX VrefLevel [Byte0]: 39
1722 23:56:48.488627 [Byte1]: 39
1723 23:56:48.488678
1724 23:56:48.488729 Set Vref, RX VrefLevel [Byte0]: 40
1725 23:56:48.488781 [Byte1]: 40
1726 23:56:48.488833
1727 23:56:48.488884 Set Vref, RX VrefLevel [Byte0]: 41
1728 23:56:48.488935 [Byte1]: 41
1729 23:56:48.488987
1730 23:56:48.489038 Set Vref, RX VrefLevel [Byte0]: 42
1731 23:56:48.489090 [Byte1]: 42
1732 23:56:48.489141
1733 23:56:48.489192 Set Vref, RX VrefLevel [Byte0]: 43
1734 23:56:48.489243 [Byte1]: 43
1735 23:56:48.489328
1736 23:56:48.489379 Set Vref, RX VrefLevel [Byte0]: 44
1737 23:56:48.489430 [Byte1]: 44
1738 23:56:48.489482
1739 23:56:48.489533 Set Vref, RX VrefLevel [Byte0]: 45
1740 23:56:48.489585 [Byte1]: 45
1741 23:56:48.489636
1742 23:56:48.489688 Set Vref, RX VrefLevel [Byte0]: 46
1743 23:56:48.489739 [Byte1]: 46
1744 23:56:48.489790
1745 23:56:48.489841 Set Vref, RX VrefLevel [Byte0]: 47
1746 23:56:48.489892 [Byte1]: 47
1747 23:56:48.489944
1748 23:56:48.489995 Set Vref, RX VrefLevel [Byte0]: 48
1749 23:56:48.490046 [Byte1]: 48
1750 23:56:48.490098
1751 23:56:48.490149 Set Vref, RX VrefLevel [Byte0]: 49
1752 23:56:48.490199 [Byte1]: 49
1753 23:56:48.490250
1754 23:56:48.490301 Set Vref, RX VrefLevel [Byte0]: 50
1755 23:56:48.490353 [Byte1]: 50
1756 23:56:48.490405
1757 23:56:48.490456 Set Vref, RX VrefLevel [Byte0]: 51
1758 23:56:48.490508 [Byte1]: 51
1759 23:56:48.490559
1760 23:56:48.490610 Set Vref, RX VrefLevel [Byte0]: 52
1761 23:56:48.490662 [Byte1]: 52
1762 23:56:48.490714
1763 23:56:48.490765 Set Vref, RX VrefLevel [Byte0]: 53
1764 23:56:48.491011 [Byte1]: 53
1765 23:56:48.491070
1766 23:56:48.491123 Set Vref, RX VrefLevel [Byte0]: 54
1767 23:56:48.491175 [Byte1]: 54
1768 23:56:48.491227
1769 23:56:48.491279 Set Vref, RX VrefLevel [Byte0]: 55
1770 23:56:48.491331 [Byte1]: 55
1771 23:56:48.491382
1772 23:56:48.491434 Set Vref, RX VrefLevel [Byte0]: 56
1773 23:56:48.491486 [Byte1]: 56
1774 23:56:48.491537
1775 23:56:48.491588 Set Vref, RX VrefLevel [Byte0]: 57
1776 23:56:48.491640 [Byte1]: 57
1777 23:56:48.491692
1778 23:56:48.491743 Set Vref, RX VrefLevel [Byte0]: 58
1779 23:56:48.491795 [Byte1]: 58
1780 23:56:48.491846
1781 23:56:48.491898 Set Vref, RX VrefLevel [Byte0]: 59
1782 23:56:48.491950 [Byte1]: 59
1783 23:56:48.492001
1784 23:56:48.492053 Set Vref, RX VrefLevel [Byte0]: 60
1785 23:56:48.492104 [Byte1]: 60
1786 23:56:48.492156
1787 23:56:48.492207 Set Vref, RX VrefLevel [Byte0]: 61
1788 23:56:48.492259 [Byte1]: 61
1789 23:56:48.492310
1790 23:56:48.492362 Set Vref, RX VrefLevel [Byte0]: 62
1791 23:56:48.492426 [Byte1]: 62
1792 23:56:48.492482
1793 23:56:48.492534 Set Vref, RX VrefLevel [Byte0]: 63
1794 23:56:48.492586 [Byte1]: 63
1795 23:56:48.492638
1796 23:56:48.492689 Set Vref, RX VrefLevel [Byte0]: 64
1797 23:56:48.492741 [Byte1]: 64
1798 23:56:48.492794
1799 23:56:48.492846 Set Vref, RX VrefLevel [Byte0]: 65
1800 23:56:48.492898 [Byte1]: 65
1801 23:56:48.492949
1802 23:56:48.493001 Set Vref, RX VrefLevel [Byte0]: 66
1803 23:56:48.493053 [Byte1]: 66
1804 23:56:48.493105
1805 23:56:48.493156 Set Vref, RX VrefLevel [Byte0]: 67
1806 23:56:48.493208 [Byte1]: 67
1807 23:56:48.493267
1808 23:56:48.493349 Set Vref, RX VrefLevel [Byte0]: 68
1809 23:56:48.493400 [Byte1]: 68
1810 23:56:48.493452
1811 23:56:48.493504 Set Vref, RX VrefLevel [Byte0]: 69
1812 23:56:48.493556 [Byte1]: 69
1813 23:56:48.493608
1814 23:56:48.493659 Set Vref, RX VrefLevel [Byte0]: 70
1815 23:56:48.493711 [Byte1]: 70
1816 23:56:48.493762
1817 23:56:48.493814 Set Vref, RX VrefLevel [Byte0]: 71
1818 23:56:48.493866 [Byte1]: 71
1819 23:56:48.493917
1820 23:56:48.493968 Set Vref, RX VrefLevel [Byte0]: 72
1821 23:56:48.494019 [Byte1]: 72
1822 23:56:48.494070
1823 23:56:48.494122 Set Vref, RX VrefLevel [Byte0]: 73
1824 23:56:48.494174 [Byte1]: 73
1825 23:56:48.494226
1826 23:56:48.494277 Set Vref, RX VrefLevel [Byte0]: 74
1827 23:56:48.494328 [Byte1]: 74
1828 23:56:48.494380
1829 23:56:48.494431 Set Vref, RX VrefLevel [Byte0]: 75
1830 23:56:48.494482 [Byte1]: 75
1831 23:56:48.494544
1832 23:56:48.494599 Set Vref, RX VrefLevel [Byte0]: 76
1833 23:56:48.494651 [Byte1]: 76
1834 23:56:48.494703
1835 23:56:48.494753 Final RX Vref Byte 0 = 54 to rank0
1836 23:56:48.494806 Final RX Vref Byte 1 = 57 to rank0
1837 23:56:48.494857 Final RX Vref Byte 0 = 54 to rank1
1838 23:56:48.494910 Final RX Vref Byte 1 = 57 to rank1==
1839 23:56:48.494961 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 23:56:48.495014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 23:56:48.495068 ==
1842 23:56:48.495119 DQS Delay:
1843 23:56:48.495171 DQS0 = 0, DQS1 = 0
1844 23:56:48.495223 DQM Delay:
1845 23:56:48.495274 DQM0 = 84, DQM1 = 79
1846 23:56:48.495326 DQ Delay:
1847 23:56:48.495378 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1848 23:56:48.495429 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1849 23:56:48.495481 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =72
1850 23:56:48.495533 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =84
1851 23:56:48.495585
1852 23:56:48.495636
1853 23:56:48.495687 [DQSOSCAuto] RK0, (LSB)MR18= 0x192d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1854 23:56:48.495740 CH1 RK0: MR19=606, MR18=192D
1855 23:56:48.495792 CH1_RK0: MR19=0x606, MR18=0x192D, DQSOSC=398, MR23=63, INC=93, DEC=62
1856 23:56:48.495844
1857 23:56:48.495895 ----->DramcWriteLeveling(PI) begin...
1858 23:56:48.495949 ==
1859 23:56:48.496000 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 23:56:48.496052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 23:56:48.496104 ==
1862 23:56:48.496155 Write leveling (Byte 0): 26 => 26
1863 23:56:48.496207 Write leveling (Byte 1): 28 => 28
1864 23:56:48.496259 DramcWriteLeveling(PI) end<-----
1865 23:56:48.496310
1866 23:56:48.496361 ==
1867 23:56:48.496413 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 23:56:48.496465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 23:56:48.496517 ==
1870 23:56:48.496569 [Gating] SW mode calibration
1871 23:56:48.496621 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 23:56:48.496673 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 23:56:48.496725 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1874 23:56:48.496777 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1875 23:56:48.496829 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:56:48.496881 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:56:48.496933 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:56:48.496985 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:56:48.497037 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:56:48.497089 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:56:48.497141 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:56:48.497193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:56:48.497245 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:56:48.497330 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:56:48.497383 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:56:48.497434 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:56:48.497485 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:56:48.497538 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:56:48.497589 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1890 23:56:48.497641 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1891 23:56:48.497692 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:56:48.497744 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:56:48.497796 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:56:48.497847 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:56:48.498087 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:56:48.498146 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:56:48.498200 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:56:48.498252 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1899 23:56:48.498305 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1900 23:56:48.498357 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 23:56:48.498409 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 23:56:48.498461 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 23:56:48.498513 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 23:56:48.498565 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 23:56:48.498616 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1906 23:56:48.498668 0 10 4 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
1907 23:56:48.498721 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1908 23:56:48.498773 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:56:48.498825 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:56:48.498876 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:56:48.498928 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:56:48.498981 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 23:56:48.499097 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1914 23:56:48.499162 0 11 4 | B1->B0 | 2626 3a3a | 0 1 | (0 0) (0 0)
1915 23:56:48.499239 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1916 23:56:48.499304 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 23:56:48.499356 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 23:56:48.499408 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 23:56:48.499460 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 23:56:48.499511 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 23:56:48.499563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1922 23:56:48.499615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1923 23:56:48.499666 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:56:48.499718 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:56:48.499770 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:56:48.499821 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:56:48.499872 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:56:48.499924 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:56:48.499976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:56:48.500027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:56:48.500079 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:56:48.500130 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:56:48.500182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:56:48.500233 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 23:56:48.500285 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 23:56:48.500337 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 23:56:48.500388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1938 23:56:48.500439 Total UI for P1: 0, mck2ui 16
1939 23:56:48.500492 best dqsien dly found for B0: ( 0, 13, 30)
1940 23:56:48.500544 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1941 23:56:48.500596 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1942 23:56:48.500648 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 23:56:48.500699 Total UI for P1: 0, mck2ui 16
1944 23:56:48.500751 best dqsien dly found for B1: ( 0, 14, 6)
1945 23:56:48.500803 best DQS0 dly(MCK, UI, PI) = (0, 13, 30)
1946 23:56:48.500856 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1947 23:56:48.500908
1948 23:56:48.500959 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 30)
1949 23:56:48.501011 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1950 23:56:48.501062 [Gating] SW calibration Done
1951 23:56:48.501114 ==
1952 23:56:48.501165 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 23:56:48.501217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 23:56:48.501290 ==
1955 23:56:48.501356 RX Vref Scan: 0
1956 23:56:48.501407
1957 23:56:48.501459 RX Vref 0 -> 0, step: 1
1958 23:56:48.501511
1959 23:56:48.501562 RX Delay -130 -> 252, step: 16
1960 23:56:48.501613 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1961 23:56:48.501665 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1962 23:56:48.501717 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1963 23:56:48.501769 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1964 23:56:48.501821 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1965 23:56:48.501872 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1966 23:56:48.501924 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1967 23:56:48.501976 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1968 23:56:48.502027 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1969 23:56:48.502078 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1970 23:56:48.502130 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1971 23:56:48.502181 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1972 23:56:48.502233 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1973 23:56:48.502284 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1974 23:56:48.502336 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1975 23:56:48.502387 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1976 23:56:48.502439 ==
1977 23:56:48.502490 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 23:56:48.502542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 23:56:48.502594 ==
1980 23:56:48.502646 DQS Delay:
1981 23:56:48.502697 DQS0 = 0, DQS1 = 0
1982 23:56:48.502748 DQM Delay:
1983 23:56:48.502800 DQM0 = 84, DQM1 = 80
1984 23:56:48.502851 DQ Delay:
1985 23:56:48.502902 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1986 23:56:48.780605 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1987 23:56:48.781087 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1988 23:56:48.781462 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1989 23:56:48.781770
1990 23:56:48.782062
1991 23:56:48.782348 ==
1992 23:56:48.782631 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:56:48.782912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:56:48.783195 ==
1995 23:56:48.783469
1996 23:56:48.783740
1997 23:56:48.784009 TX Vref Scan disable
1998 23:56:48.784284 == TX Byte 0 ==
1999 23:56:48.784557 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2000 23:56:48.785299 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2001 23:56:48.785629 == TX Byte 1 ==
2002 23:56:48.785915 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2003 23:56:48.786196 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2004 23:56:48.786470 ==
2005 23:56:48.786743 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 23:56:48.787015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 23:56:48.787292 ==
2008 23:56:48.787563 TX Vref=22, minBit 4, minWin=27, winSum=450
2009 23:56:48.787833 TX Vref=24, minBit 1, minWin=27, winSum=450
2010 23:56:48.788100 TX Vref=26, minBit 0, minWin=28, winSum=455
2011 23:56:48.788370 TX Vref=28, minBit 0, minWin=28, winSum=458
2012 23:56:48.788640 TX Vref=30, minBit 5, minWin=27, winSum=456
2013 23:56:48.788906 TX Vref=32, minBit 4, minWin=27, winSum=455
2014 23:56:48.789235 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
2015 23:56:48.789648
2016 23:56:48.790038 Final TX Range 1 Vref 28
2017 23:56:48.790414
2018 23:56:48.790698 ==
2019 23:56:48.790973 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 23:56:48.791248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 23:56:48.791528 ==
2022 23:56:48.791799
2023 23:56:48.792068
2024 23:56:48.792332 TX Vref Scan disable
2025 23:56:48.792604 == TX Byte 0 ==
2026 23:56:48.792875 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2027 23:56:48.793238 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2028 23:56:48.793559 == TX Byte 1 ==
2029 23:56:48.793836 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2030 23:56:48.794110 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2031 23:56:48.794380
2032 23:56:48.794646 [DATLAT]
2033 23:56:48.794932 Freq=800, CH1 RK1
2034 23:56:48.795272
2035 23:56:48.795595 DATLAT Default: 0xa
2036 23:56:48.795867 0, 0xFFFF, sum = 0
2037 23:56:48.796143 1, 0xFFFF, sum = 0
2038 23:56:48.796420 2, 0xFFFF, sum = 0
2039 23:56:48.796696 3, 0xFFFF, sum = 0
2040 23:56:48.796971 4, 0xFFFF, sum = 0
2041 23:56:48.797248 5, 0xFFFF, sum = 0
2042 23:56:48.797546 6, 0xFFFF, sum = 0
2043 23:56:48.797824 7, 0xFFFF, sum = 0
2044 23:56:48.798096 8, 0xFFFF, sum = 0
2045 23:56:48.798370 9, 0x0, sum = 1
2046 23:56:48.798641 10, 0x0, sum = 2
2047 23:56:48.798917 11, 0x0, sum = 3
2048 23:56:48.799189 12, 0x0, sum = 4
2049 23:56:48.799465 best_step = 10
2050 23:56:48.799734
2051 23:56:48.800004 ==
2052 23:56:48.800273 Dram Type= 6, Freq= 0, CH_1, rank 1
2053 23:56:48.800546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2054 23:56:48.800889 ==
2055 23:56:48.801173 RX Vref Scan: 0
2056 23:56:48.801486
2057 23:56:48.801759 RX Vref 0 -> 0, step: 1
2058 23:56:48.802027
2059 23:56:48.802295 RX Delay -95 -> 252, step: 8
2060 23:56:48.802563 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2061 23:56:48.802834 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2062 23:56:48.803105 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2063 23:56:48.803376 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2064 23:56:48.803644 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2065 23:56:48.803915 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2066 23:56:48.804187 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2067 23:56:48.804453 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2068 23:56:48.804720 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2069 23:56:48.804986 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2070 23:56:48.805252 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2071 23:56:48.805544 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2072 23:56:48.805812 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2073 23:56:48.806163 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2074 23:56:48.806440 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2075 23:56:48.806709 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2076 23:56:48.806979 ==
2077 23:56:48.807245 Dram Type= 6, Freq= 0, CH_1, rank 1
2078 23:56:48.807542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2079 23:56:48.807812 ==
2080 23:56:48.808081 DQS Delay:
2081 23:56:48.808368 DQS0 = 0, DQS1 = 0
2082 23:56:48.808641 DQM Delay:
2083 23:56:48.808910 DQM0 = 86, DQM1 = 81
2084 23:56:48.809202 DQ Delay:
2085 23:56:48.809541 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2086 23:56:48.809817 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2087 23:56:48.810092 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2088 23:56:48.810289 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2089 23:56:48.810483
2090 23:56:48.810674
2091 23:56:48.810899 [DQSOSCAuto] RK1, (LSB)MR18= 0x203c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2092 23:56:48.811119 CH1 RK1: MR19=606, MR18=203C
2093 23:56:48.811314 CH1_RK1: MR19=0x606, MR18=0x203C, DQSOSC=394, MR23=63, INC=95, DEC=63
2094 23:56:48.811507 [RxdqsGatingPostProcess] freq 800
2095 23:56:48.811700 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2096 23:56:48.811895 Pre-setting of DQS Precalculation
2097 23:56:48.812087 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2098 23:56:48.812285 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2099 23:56:48.812482 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2100 23:56:48.812676
2101 23:56:48.812868
2102 23:56:48.813059 [Calibration Summary] 1600 Mbps
2103 23:56:48.813252 CH 0, Rank 0
2104 23:56:48.813481 SW Impedance : PASS
2105 23:56:48.813677 DUTY Scan : NO K
2106 23:56:48.813869 ZQ Calibration : PASS
2107 23:56:48.814063 Jitter Meter : NO K
2108 23:56:48.814255 CBT Training : PASS
2109 23:56:48.814448 Write leveling : PASS
2110 23:56:48.814640 RX DQS gating : PASS
2111 23:56:48.814832 RX DQ/DQS(RDDQC) : PASS
2112 23:56:48.815023 TX DQ/DQS : PASS
2113 23:56:48.815169 RX DATLAT : PASS
2114 23:56:48.815314 RX DQ/DQS(Engine): PASS
2115 23:56:48.815459 TX OE : NO K
2116 23:56:48.815605 All Pass.
2117 23:56:48.815750
2118 23:56:48.815939 CH 0, Rank 1
2119 23:56:48.816088 SW Impedance : PASS
2120 23:56:48.816235 DUTY Scan : NO K
2121 23:56:48.816402 ZQ Calibration : PASS
2122 23:56:48.816564 Jitter Meter : NO K
2123 23:56:48.816711 CBT Training : PASS
2124 23:56:48.816856 Write leveling : PASS
2125 23:56:48.817001 RX DQS gating : PASS
2126 23:56:48.817147 RX DQ/DQS(RDDQC) : PASS
2127 23:56:48.817305 TX DQ/DQS : PASS
2128 23:56:48.817453 RX DATLAT : PASS
2129 23:56:48.817598 RX DQ/DQS(Engine): PASS
2130 23:56:48.817742 TX OE : NO K
2131 23:56:48.817889 All Pass.
2132 23:56:48.818034
2133 23:56:48.818179 CH 1, Rank 0
2134 23:56:48.818323 SW Impedance : PASS
2135 23:56:48.818469 DUTY Scan : NO K
2136 23:56:48.818612 ZQ Calibration : PASS
2137 23:56:48.818756 Jitter Meter : NO K
2138 23:56:48.818901 CBT Training : PASS
2139 23:56:48.819046 Write leveling : PASS
2140 23:56:48.819190 RX DQS gating : PASS
2141 23:56:48.819335 RX DQ/DQS(RDDQC) : PASS
2142 23:56:48.819480 TX DQ/DQS : PASS
2143 23:56:48.819625 RX DATLAT : PASS
2144 23:56:48.819770 RX DQ/DQS(Engine): PASS
2145 23:56:48.820167 TX OE : NO K
2146 23:56:48.820302 All Pass.
2147 23:56:48.820421
2148 23:56:48.820538 CH 1, Rank 1
2149 23:56:48.820655 SW Impedance : PASS
2150 23:56:48.820774 DUTY Scan : NO K
2151 23:56:48.820891 ZQ Calibration : PASS
2152 23:56:48.821007 Jitter Meter : NO K
2153 23:56:48.821124 CBT Training : PASS
2154 23:56:48.821326 Write leveling : PASS
2155 23:56:48.821465 RX DQS gating : PASS
2156 23:56:48.821586 RX DQ/DQS(RDDQC) : PASS
2157 23:56:48.821703 TX DQ/DQS : PASS
2158 23:56:48.821821 RX DATLAT : PASS
2159 23:56:48.821939 RX DQ/DQS(Engine): PASS
2160 23:56:48.822055 TX OE : NO K
2161 23:56:48.822171 All Pass.
2162 23:56:48.822289
2163 23:56:48.822406 DramC Write-DBI off
2164 23:56:48.822524 PER_BANK_REFRESH: Hybrid Mode
2165 23:56:48.822642 TX_TRACKING: ON
2166 23:56:48.822761 [GetDramInforAfterCalByMRR] Vendor 6.
2167 23:56:48.822879 [GetDramInforAfterCalByMRR] Revision 606.
2168 23:56:48.822996 [GetDramInforAfterCalByMRR] Revision 2 0.
2169 23:56:48.823113 MR0 0x3b3b
2170 23:56:48.823230 MR8 0x5151
2171 23:56:48.823345 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2172 23:56:48.823463
2173 23:56:48.823601 MR0 0x3b3b
2174 23:56:48.823775 MR8 0x5151
2175 23:56:48.823966 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 23:56:48.824093
2177 23:56:48.824214 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2178 23:56:48.824336 [FAST_K] Save calibration result to emmc
2179 23:56:48.824455 [FAST_K] Save calibration result to emmc
2180 23:56:48.824572 dram_init: config_dvfs: 1
2181 23:56:48.824692 dramc_set_vcore_voltage set vcore to 662500
2182 23:56:48.824811 Read voltage for 1200, 2
2183 23:56:48.824929 Vio18 = 0
2184 23:56:48.825050 Vcore = 662500
2185 23:56:48.825186 Vdram = 0
2186 23:56:48.825363 Vddq = 0
2187 23:56:48.825467 Vmddr = 0
2188 23:56:48.825566 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2189 23:56:48.825668 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2190 23:56:48.825769 MEM_TYPE=3, freq_sel=15
2191 23:56:48.825866 sv_algorithm_assistance_LP4_1600
2192 23:56:48.825966 ============ PULL DRAM RESETB DOWN ============
2193 23:56:48.826066 ========== PULL DRAM RESETB DOWN end =========
2194 23:56:48.826165 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2195 23:56:48.826265 ===================================
2196 23:56:48.826398 LPDDR4 DRAM CONFIGURATION
2197 23:56:48.826500 ===================================
2198 23:56:48.826601 EX_ROW_EN[0] = 0x0
2199 23:56:48.826698 EX_ROW_EN[1] = 0x0
2200 23:56:48.826795 LP4Y_EN = 0x0
2201 23:56:48.826932 WORK_FSP = 0x0
2202 23:56:48.827034 WL = 0x4
2203 23:56:48.827131 RL = 0x4
2204 23:56:48.827229 BL = 0x2
2205 23:56:48.827327 RPST = 0x0
2206 23:56:48.827424 RD_PRE = 0x0
2207 23:56:48.827522 WR_PRE = 0x1
2208 23:56:48.827618 WR_PST = 0x0
2209 23:56:48.827716 DBI_WR = 0x0
2210 23:56:48.827818 DBI_RD = 0x0
2211 23:56:48.827914 OTF = 0x1
2212 23:56:48.828012 ===================================
2213 23:56:48.828111 ===================================
2214 23:56:48.828210 ANA top config
2215 23:56:48.828307 ===================================
2216 23:56:48.828405 DLL_ASYNC_EN = 0
2217 23:56:48.828503 ALL_SLAVE_EN = 0
2218 23:56:48.828600 NEW_RANK_MODE = 1
2219 23:56:48.828698 DLL_IDLE_MODE = 1
2220 23:56:48.828794 LP45_APHY_COMB_EN = 1
2221 23:56:48.828890 TX_ODT_DIS = 1
2222 23:56:48.828987 NEW_8X_MODE = 1
2223 23:56:48.829085 ===================================
2224 23:56:48.829184 ===================================
2225 23:56:48.829296 data_rate = 2400
2226 23:56:48.829397 CKR = 1
2227 23:56:48.829495 DQ_P2S_RATIO = 8
2228 23:56:48.829593 ===================================
2229 23:56:48.829692 CA_P2S_RATIO = 8
2230 23:56:48.829789 DQ_CA_OPEN = 0
2231 23:56:48.829886 DQ_SEMI_OPEN = 0
2232 23:56:48.829983 CA_SEMI_OPEN = 0
2233 23:56:48.830084 CA_FULL_RATE = 0
2234 23:56:48.830167 DQ_CKDIV4_EN = 0
2235 23:56:48.830282 CA_CKDIV4_EN = 0
2236 23:56:48.830370 CA_PREDIV_EN = 0
2237 23:56:48.830455 PH8_DLY = 17
2238 23:56:48.830579 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2239 23:56:48.830669 DQ_AAMCK_DIV = 4
2240 23:56:48.830754 CA_AAMCK_DIV = 4
2241 23:56:48.830871 CA_ADMCK_DIV = 4
2242 23:56:48.830967 DQ_TRACK_CA_EN = 0
2243 23:56:48.831075 CA_PICK = 1200
2244 23:56:48.831162 CA_MCKIO = 1200
2245 23:56:48.831247 MCKIO_SEMI = 0
2246 23:56:48.831332 PLL_FREQ = 2366
2247 23:56:48.831416 DQ_UI_PI_RATIO = 32
2248 23:56:48.831501 CA_UI_PI_RATIO = 0
2249 23:56:48.831585 ===================================
2250 23:56:48.831683 ===================================
2251 23:56:48.831778 memory_type:LPDDR4
2252 23:56:48.831863 GP_NUM : 10
2253 23:56:48.831948 SRAM_EN : 1
2254 23:56:48.832032 MD32_EN : 0
2255 23:56:48.832115 ===================================
2256 23:56:48.832200 [ANA_INIT] >>>>>>>>>>>>>>
2257 23:56:48.832284 <<<<<< [CONFIGURE PHASE]: ANA_TX
2258 23:56:48.832370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2259 23:56:48.832454 ===================================
2260 23:56:48.832537 data_rate = 2400,PCW = 0X5b00
2261 23:56:48.832622 ===================================
2262 23:56:48.832706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2263 23:56:48.832790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 23:56:48.832874 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 23:56:48.832960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2266 23:56:48.833044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2267 23:56:48.833128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2268 23:56:48.833212 [ANA_INIT] flow start
2269 23:56:48.833324 [ANA_INIT] PLL >>>>>>>>
2270 23:56:48.833413 [ANA_INIT] PLL <<<<<<<<
2271 23:56:48.833497 [ANA_INIT] MIDPI >>>>>>>>
2272 23:56:48.833581 [ANA_INIT] MIDPI <<<<<<<<
2273 23:56:48.833665 [ANA_INIT] DLL >>>>>>>>
2274 23:56:48.833749 [ANA_INIT] DLL <<<<<<<<
2275 23:56:48.833834 [ANA_INIT] flow end
2276 23:56:48.833918 ============ LP4 DIFF to SE enter ============
2277 23:56:48.834004 ============ LP4 DIFF to SE exit ============
2278 23:56:48.834089 [ANA_INIT] <<<<<<<<<<<<<
2279 23:56:48.834173 [Flow] Enable top DCM control >>>>>
2280 23:56:48.834256 [Flow] Enable top DCM control <<<<<
2281 23:56:48.834562 Enable DLL master slave shuffle
2282 23:56:48.834656 ==============================================================
2283 23:56:48.834742 Gating Mode config
2284 23:56:48.834827 ==============================================================
2285 23:56:48.834912 Config description:
2286 23:56:48.835002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2287 23:56:48.835082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2288 23:56:48.835157 SELPH_MODE 0: By rank 1: By Phase
2289 23:56:48.835232 ==============================================================
2290 23:56:48.835306 GAT_TRACK_EN = 1
2291 23:56:48.835379 RX_GATING_MODE = 2
2292 23:56:48.835452 RX_GATING_TRACK_MODE = 2
2293 23:56:48.835525 SELPH_MODE = 1
2294 23:56:48.835598 PICG_EARLY_EN = 1
2295 23:56:48.835672 VALID_LAT_VALUE = 1
2296 23:56:48.835746 ==============================================================
2297 23:56:48.835820 Enter into Gating configuration >>>>
2298 23:56:48.835894 Exit from Gating configuration <<<<
2299 23:56:48.835966 Enter into DVFS_PRE_config >>>>>
2300 23:56:48.836040 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2301 23:56:48.836115 Exit from DVFS_PRE_config <<<<<
2302 23:56:48.836188 Enter into PICG configuration >>>>
2303 23:56:48.836263 Exit from PICG configuration <<<<
2304 23:56:48.836335 [RX_INPUT] configuration >>>>>
2305 23:56:48.836409 [RX_INPUT] configuration <<<<<
2306 23:56:48.836483 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2307 23:56:48.836576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2308 23:56:48.836654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 23:56:48.836729 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 23:56:48.836803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 23:56:48.836877 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 23:56:48.836950 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2313 23:56:48.837024 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2314 23:56:48.837098 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2315 23:56:48.837172 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2316 23:56:48.837245 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2317 23:56:48.837332 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 23:56:48.837406 ===================================
2319 23:56:48.837481 LPDDR4 DRAM CONFIGURATION
2320 23:56:48.837554 ===================================
2321 23:56:48.837628 EX_ROW_EN[0] = 0x0
2322 23:56:48.837702 EX_ROW_EN[1] = 0x0
2323 23:56:48.837775 LP4Y_EN = 0x0
2324 23:56:48.837848 WORK_FSP = 0x0
2325 23:56:48.837921 WL = 0x4
2326 23:56:48.837994 RL = 0x4
2327 23:56:48.838067 BL = 0x2
2328 23:56:48.838140 RPST = 0x0
2329 23:56:48.838212 RD_PRE = 0x0
2330 23:56:48.838285 WR_PRE = 0x1
2331 23:56:48.838358 WR_PST = 0x0
2332 23:56:48.838431 DBI_WR = 0x0
2333 23:56:48.838503 DBI_RD = 0x0
2334 23:56:48.838575 OTF = 0x1
2335 23:56:48.838648 ===================================
2336 23:56:48.838722 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2337 23:56:48.838796 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2338 23:56:48.838870 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2339 23:56:48.838944 ===================================
2340 23:56:48.839016 LPDDR4 DRAM CONFIGURATION
2341 23:56:48.839090 ===================================
2342 23:56:48.839163 EX_ROW_EN[0] = 0x10
2343 23:56:48.839236 EX_ROW_EN[1] = 0x0
2344 23:56:48.839309 LP4Y_EN = 0x0
2345 23:56:48.839382 WORK_FSP = 0x0
2346 23:56:48.839454 WL = 0x4
2347 23:56:48.839527 RL = 0x4
2348 23:56:48.839599 BL = 0x2
2349 23:56:48.839672 RPST = 0x0
2350 23:56:48.839744 RD_PRE = 0x0
2351 23:56:48.839817 WR_PRE = 0x1
2352 23:56:48.839890 WR_PST = 0x0
2353 23:56:48.839963 DBI_WR = 0x0
2354 23:56:48.840042 DBI_RD = 0x0
2355 23:56:48.840106 OTF = 0x1
2356 23:56:48.840171 ===================================
2357 23:56:48.840237 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2358 23:56:48.840303 ==
2359 23:56:48.840368 Dram Type= 6, Freq= 0, CH_0, rank 0
2360 23:56:48.840434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 23:56:48.840500 ==
2362 23:56:48.840565 [Duty_Offset_Calibration]
2363 23:56:48.840629 B0:2 B1:0 CA:4
2364 23:56:48.840694
2365 23:56:48.840758 [DutyScan_Calibration_Flow] k_type=0
2366 23:56:48.840823
2367 23:56:48.840887 ==CLK 0==
2368 23:56:48.840951 Final CLK duty delay cell = -4
2369 23:56:48.841016 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2370 23:56:48.841081 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2371 23:56:48.841146 [-4] AVG Duty = 4953%(X100)
2372 23:56:48.841210
2373 23:56:48.841285 CH0 CLK Duty spec in!! Max-Min= 218%
2374 23:56:48.841352 [DutyScan_Calibration_Flow] ====Done====
2375 23:56:48.841418
2376 23:56:48.841482 [DutyScan_Calibration_Flow] k_type=1
2377 23:56:48.841546
2378 23:56:48.841611 ==DQS 0 ==
2379 23:56:48.841675 Final DQS duty delay cell = 0
2380 23:56:48.841740 [0] MAX Duty = 5156%(X100), DQS PI = 18
2381 23:56:48.841805 [0] MIN Duty = 5093%(X100), DQS PI = 0
2382 23:56:48.841870 [0] AVG Duty = 5124%(X100)
2383 23:56:48.841935
2384 23:56:48.841999 ==DQS 1 ==
2385 23:56:48.842063 Final DQS duty delay cell = 0
2386 23:56:48.842141 [0] MAX Duty = 5125%(X100), DQS PI = 52
2387 23:56:48.842210 [0] MIN Duty = 4969%(X100), DQS PI = 14
2388 23:56:48.842276 [0] AVG Duty = 5047%(X100)
2389 23:56:48.842341
2390 23:56:48.842405 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2391 23:56:48.842470
2392 23:56:48.842534 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2393 23:56:48.842599 [DutyScan_Calibration_Flow] ====Done====
2394 23:56:48.842664
2395 23:56:48.842728 [DutyScan_Calibration_Flow] k_type=3
2396 23:56:48.842793
2397 23:56:48.842857 ==DQM 0 ==
2398 23:56:48.842921 Final DQM duty delay cell = 0
2399 23:56:48.842987 [0] MAX Duty = 5093%(X100), DQS PI = 20
2400 23:56:48.843052 [0] MIN Duty = 4844%(X100), DQS PI = 52
2401 23:56:48.843117 [0] AVG Duty = 4968%(X100)
2402 23:56:48.843181
2403 23:56:48.843245 ==DQM 1 ==
2404 23:56:48.843312 Final DQM duty delay cell = 0
2405 23:56:48.843579 [0] MAX Duty = 4969%(X100), DQS PI = 0
2406 23:56:48.843653 [0] MIN Duty = 4875%(X100), DQS PI = 20
2407 23:56:48.843720 [0] AVG Duty = 4922%(X100)
2408 23:56:48.843786
2409 23:56:48.843852 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2410 23:56:48.843917
2411 23:56:48.843982 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2412 23:56:48.844047 [DutyScan_Calibration_Flow] ====Done====
2413 23:56:48.844112
2414 23:56:48.844176 [DutyScan_Calibration_Flow] k_type=2
2415 23:56:48.844241
2416 23:56:48.844306 ==DQ 0 ==
2417 23:56:48.844372 Final DQ duty delay cell = 0
2418 23:56:48.844438 [0] MAX Duty = 5156%(X100), DQS PI = 18
2419 23:56:48.844502 [0] MIN Duty = 5000%(X100), DQS PI = 6
2420 23:56:48.844567 [0] AVG Duty = 5078%(X100)
2421 23:56:48.844632
2422 23:56:48.844697 ==DQ 1 ==
2423 23:56:48.844761 Final DQ duty delay cell = 0
2424 23:56:48.844826 [0] MAX Duty = 5125%(X100), DQS PI = 4
2425 23:56:48.844891 [0] MIN Duty = 4938%(X100), DQS PI = 16
2426 23:56:48.844970 [0] AVG Duty = 5031%(X100)
2427 23:56:48.845028
2428 23:56:48.845086 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2429 23:56:48.845145
2430 23:56:48.845203 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2431 23:56:48.845268 [DutyScan_Calibration_Flow] ====Done====
2432 23:56:48.845330 ==
2433 23:56:48.845388 Dram Type= 6, Freq= 0, CH_1, rank 0
2434 23:56:48.845447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2435 23:56:48.845506 ==
2436 23:56:48.845565 [Duty_Offset_Calibration]
2437 23:56:48.845623 B0:0 B1:-1 CA:3
2438 23:56:48.845682
2439 23:56:48.845740 [DutyScan_Calibration_Flow] k_type=0
2440 23:56:48.845798
2441 23:56:48.845856 ==CLK 0==
2442 23:56:48.845916 Final CLK duty delay cell = -4
2443 23:56:48.845975 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2444 23:56:48.846034 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2445 23:56:48.846093 [-4] AVG Duty = 4938%(X100)
2446 23:56:48.846152
2447 23:56:48.846212 CH1 CLK Duty spec in!! Max-Min= 124%
2448 23:56:48.846271 [DutyScan_Calibration_Flow] ====Done====
2449 23:56:48.846329
2450 23:56:48.846387 [DutyScan_Calibration_Flow] k_type=1
2451 23:56:48.846445
2452 23:56:48.846503 ==DQS 0 ==
2453 23:56:48.846562 Final DQS duty delay cell = 0
2454 23:56:48.846621 [0] MAX Duty = 5156%(X100), DQS PI = 30
2455 23:56:48.846679 [0] MIN Duty = 4907%(X100), DQS PI = 38
2456 23:56:48.846738 [0] AVG Duty = 5031%(X100)
2457 23:56:48.846796
2458 23:56:48.846854 ==DQS 1 ==
2459 23:56:48.846912 Final DQS duty delay cell = 0
2460 23:56:48.846971 [0] MAX Duty = 5156%(X100), DQS PI = 8
2461 23:56:48.847030 [0] MIN Duty = 5031%(X100), DQS PI = 2
2462 23:56:48.847100 [0] AVG Duty = 5093%(X100)
2463 23:56:48.847162
2464 23:56:48.847220 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2465 23:56:48.847279
2466 23:56:48.847337 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2467 23:56:48.847395 [DutyScan_Calibration_Flow] ====Done====
2468 23:56:48.847453
2469 23:56:48.847511 [DutyScan_Calibration_Flow] k_type=3
2470 23:56:48.847569
2471 23:56:48.847627 ==DQM 0 ==
2472 23:56:48.847686 Final DQM duty delay cell = 0
2473 23:56:48.847745 [0] MAX Duty = 5031%(X100), DQS PI = 28
2474 23:56:48.847804 [0] MIN Duty = 4782%(X100), DQS PI = 38
2475 23:56:48.847862 [0] AVG Duty = 4906%(X100)
2476 23:56:48.847920
2477 23:56:48.847978 ==DQM 1 ==
2478 23:56:48.848036 Final DQM duty delay cell = 4
2479 23:56:48.848094 [4] MAX Duty = 5187%(X100), DQS PI = 32
2480 23:56:48.848152 [4] MIN Duty = 5062%(X100), DQS PI = 2
2481 23:56:48.848210 [4] AVG Duty = 5124%(X100)
2482 23:56:48.848268
2483 23:56:48.848326 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2484 23:56:48.848385
2485 23:56:48.848442 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2486 23:56:48.848501 [DutyScan_Calibration_Flow] ====Done====
2487 23:56:48.848560
2488 23:56:48.848617 [DutyScan_Calibration_Flow] k_type=2
2489 23:56:48.848675
2490 23:56:48.848734 ==DQ 0 ==
2491 23:56:48.848793 Final DQ duty delay cell = -4
2492 23:56:48.848852 [-4] MAX Duty = 5000%(X100), DQS PI = 30
2493 23:56:48.848910 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2494 23:56:48.848968 [-4] AVG Duty = 4922%(X100)
2495 23:56:48.849026
2496 23:56:48.849084 ==DQ 1 ==
2497 23:56:48.849142 Final DQ duty delay cell = 0
2498 23:56:48.849200 [0] MAX Duty = 5031%(X100), DQS PI = 32
2499 23:56:48.849264 [0] MIN Duty = 4844%(X100), DQS PI = 0
2500 23:56:48.849324 [0] AVG Duty = 4937%(X100)
2501 23:56:48.849383
2502 23:56:48.849440 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2503 23:56:48.849499
2504 23:56:48.849557 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2505 23:56:48.849615 [DutyScan_Calibration_Flow] ====Done====
2506 23:56:48.849674 nWR fixed to 30
2507 23:56:48.849733 [ModeRegInit_LP4] CH0 RK0
2508 23:56:48.849790 [ModeRegInit_LP4] CH0 RK1
2509 23:56:48.849848 [ModeRegInit_LP4] CH1 RK0
2510 23:56:48.849906 [ModeRegInit_LP4] CH1 RK1
2511 23:56:48.849964 match AC timing 7
2512 23:56:48.850031 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2513 23:56:48.850086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2514 23:56:48.850139 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2515 23:56:48.850193 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2516 23:56:48.850247 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2517 23:56:48.850300 ==
2518 23:56:48.850353 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 23:56:48.850406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 23:56:48.850460 ==
2521 23:56:48.850530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 23:56:48.850588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 23:56:48.850642 [CA 0] Center 39 (9~70) winsize 62
2524 23:56:48.850696 [CA 1] Center 39 (9~69) winsize 61
2525 23:56:48.850750 [CA 2] Center 35 (5~66) winsize 62
2526 23:56:48.850803 [CA 3] Center 35 (5~66) winsize 62
2527 23:56:48.850857 [CA 4] Center 33 (3~64) winsize 62
2528 23:56:48.850910 [CA 5] Center 33 (3~63) winsize 61
2529 23:56:48.850964
2530 23:56:48.851018 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2531 23:56:48.851072
2532 23:56:48.851125 [CATrainingPosCal] consider 1 rank data
2533 23:56:48.851178 u2DelayCellTimex100 = 270/100 ps
2534 23:56:48.851231 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2535 23:56:48.851285 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2536 23:56:48.851338 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2537 23:56:48.851392 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 23:56:48.851445 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2539 23:56:48.851498 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2540 23:56:48.851551
2541 23:56:48.851604 CA PerBit enable=1, Macro0, CA PI delay=33
2542 23:56:48.851657
2543 23:56:48.851709 [CBTSetCACLKResult] CA Dly = 33
2544 23:56:48.851762 CS Dly: 7 (0~38)
2545 23:56:48.851815 ==
2546 23:56:48.851868 Dram Type= 6, Freq= 0, CH_0, rank 1
2547 23:56:48.851921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2548 23:56:48.851974 ==
2549 23:56:48.852028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2550 23:56:48.852082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2551 23:56:48.852336 [CA 0] Center 39 (9~70) winsize 62
2552 23:56:48.852401 [CA 1] Center 39 (9~70) winsize 62
2553 23:56:48.852456 [CA 2] Center 35 (5~66) winsize 62
2554 23:56:48.852529 [CA 3] Center 35 (5~66) winsize 62
2555 23:56:48.852585 [CA 4] Center 34 (4~65) winsize 62
2556 23:56:48.852639 [CA 5] Center 33 (3~64) winsize 62
2557 23:56:48.852693
2558 23:56:48.852746 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2559 23:56:48.852800
2560 23:56:48.852853 [CATrainingPosCal] consider 2 rank data
2561 23:56:48.852907 u2DelayCellTimex100 = 270/100 ps
2562 23:56:48.852960 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2563 23:56:48.853014 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2564 23:56:48.853068 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2565 23:56:48.853121 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2566 23:56:48.853175 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2567 23:56:48.853228 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2568 23:56:48.853289
2569 23:56:48.853343 CA PerBit enable=1, Macro0, CA PI delay=33
2570 23:56:48.853398
2571 23:56:48.853451 [CBTSetCACLKResult] CA Dly = 33
2572 23:56:48.853504 CS Dly: 8 (0~41)
2573 23:56:48.853557
2574 23:56:48.853610 ----->DramcWriteLeveling(PI) begin...
2575 23:56:48.853665 ==
2576 23:56:48.853718 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 23:56:48.853771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 23:56:48.853825 ==
2579 23:56:48.853878 Write leveling (Byte 0): 32 => 32
2580 23:56:48.853932 Write leveling (Byte 1): 26 => 26
2581 23:56:48.853985 DramcWriteLeveling(PI) end<-----
2582 23:56:48.854038
2583 23:56:48.854091 ==
2584 23:56:48.854144 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 23:56:48.854197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 23:56:48.854251 ==
2587 23:56:48.854304 [Gating] SW mode calibration
2588 23:56:48.854357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2589 23:56:48.854412 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2590 23:56:48.854465 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2591 23:56:48.854518 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2592 23:56:48.854571 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 23:56:48.854624 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 23:56:48.854677 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 23:56:48.854729 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 23:56:48.854782 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
2597 23:56:48.854835 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2598 23:56:48.854888 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2599 23:56:48.854954 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 23:56:48.855006 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 23:56:48.855058 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 23:56:48.855110 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 23:56:48.855162 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 23:56:48.855214 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
2605 23:56:48.855266 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2606 23:56:48.855318 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
2607 23:56:48.855370 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 23:56:48.855422 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 23:56:48.855474 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 23:56:48.855526 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 23:56:48.855577 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 23:56:48.855629 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 23:56:48.855681 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2614 23:56:48.855733 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2615 23:56:48.855784 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:56:48.855836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:56:48.855888 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:56:48.855941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:56:48.855992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:56:48.856043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:56:48.856095 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:56:48.856147 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:56:48.856199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:56:48.856251 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:56:48.856303 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:56:48.856354 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 23:56:48.856407 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 23:56:48.856458 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2629 23:56:48.856510 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2630 23:56:48.856562 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2631 23:56:48.856614 Total UI for P1: 0, mck2ui 16
2632 23:56:48.856667 best dqsien dly found for B0: ( 1, 3, 26)
2633 23:56:48.856720 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 23:56:48.856773 Total UI for P1: 0, mck2ui 16
2635 23:56:48.856825 best dqsien dly found for B1: ( 1, 4, 0)
2636 23:56:48.856877 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2637 23:56:48.856929 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2638 23:56:48.856981
2639 23:56:48.857033 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2640 23:56:48.857085 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2641 23:56:48.857137 [Gating] SW calibration Done
2642 23:56:48.857190 ==
2643 23:56:48.857242 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 23:56:48.857338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 23:56:48.857391 ==
2646 23:56:48.857444 RX Vref Scan: 0
2647 23:56:48.857496
2648 23:56:48.857547 RX Vref 0 -> 0, step: 1
2649 23:56:48.857599
2650 23:56:48.857650 RX Delay -40 -> 252, step: 8
2651 23:56:48.857702 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2652 23:56:48.857772 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2653 23:56:48.857827 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2654 23:56:48.857879 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2655 23:56:48.857932 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2656 23:56:48.858175 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2657 23:56:48.858233 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2658 23:56:48.858287 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2659 23:56:48.858340 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2660 23:56:48.858393 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2661 23:56:48.858445 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2662 23:56:48.858498 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2663 23:56:48.858550 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2664 23:56:48.858620 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
2665 23:56:48.858674 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2666 23:56:48.858727 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2667 23:56:48.858779 ==
2668 23:56:48.858832 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 23:56:48.858884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 23:56:48.858937 ==
2671 23:56:48.858989 DQS Delay:
2672 23:56:48.859041 DQS0 = 0, DQS1 = 0
2673 23:56:48.859093 DQM Delay:
2674 23:56:48.859145 DQM0 = 117, DQM1 = 108
2675 23:56:48.859198 DQ Delay:
2676 23:56:48.859250 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2677 23:56:48.859303 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2678 23:56:48.859356 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2679 23:56:48.859408 DQ12 =119, DQ13 =115, DQ14 =119, DQ15 =115
2680 23:56:48.859460
2681 23:56:48.859512
2682 23:56:48.859564 ==
2683 23:56:48.859617 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 23:56:48.859669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 23:56:48.859722 ==
2686 23:56:48.859773
2687 23:56:48.859824
2688 23:56:48.859876 TX Vref Scan disable
2689 23:56:48.859928 == TX Byte 0 ==
2690 23:56:48.859979 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2691 23:56:48.860032 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2692 23:56:48.860084 == TX Byte 1 ==
2693 23:56:48.860136 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2694 23:56:48.860189 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2695 23:56:48.860241 ==
2696 23:56:48.860294 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 23:56:48.860346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 23:56:48.860399 ==
2699 23:56:48.860450 TX Vref=22, minBit 4, minWin=25, winSum=413
2700 23:56:48.860503 TX Vref=24, minBit 10, minWin=25, winSum=418
2701 23:56:48.860556 TX Vref=26, minBit 10, minWin=25, winSum=422
2702 23:56:48.860608 TX Vref=28, minBit 4, minWin=26, winSum=430
2703 23:56:48.860661 TX Vref=30, minBit 4, minWin=26, winSum=434
2704 23:56:48.860713 TX Vref=32, minBit 5, minWin=26, winSum=432
2705 23:56:48.860766 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 30
2706 23:56:48.860819
2707 23:56:48.860871 Final TX Range 1 Vref 30
2708 23:56:48.860924
2709 23:56:48.860975 ==
2710 23:56:48.861027 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 23:56:48.861080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 23:56:48.861133 ==
2713 23:56:48.861185
2714 23:56:48.861236
2715 23:56:48.861326 TX Vref Scan disable
2716 23:56:48.861380 == TX Byte 0 ==
2717 23:56:48.861432 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2718 23:56:48.861484 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2719 23:56:48.861536 == TX Byte 1 ==
2720 23:56:48.861588 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2721 23:56:48.861640 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2722 23:56:48.861692
2723 23:56:48.861745 [DATLAT]
2724 23:56:48.861797 Freq=1200, CH0 RK0
2725 23:56:48.861849
2726 23:56:48.861901 DATLAT Default: 0xd
2727 23:56:48.861953 0, 0xFFFF, sum = 0
2728 23:56:48.862007 1, 0xFFFF, sum = 0
2729 23:56:48.862060 2, 0xFFFF, sum = 0
2730 23:56:48.862112 3, 0xFFFF, sum = 0
2731 23:56:48.862166 4, 0xFFFF, sum = 0
2732 23:56:48.862219 5, 0xFFFF, sum = 0
2733 23:56:48.862271 6, 0xFFFF, sum = 0
2734 23:56:48.862324 7, 0xFFFF, sum = 0
2735 23:56:48.862377 8, 0xFFFF, sum = 0
2736 23:56:48.862430 9, 0xFFFF, sum = 0
2737 23:56:48.862483 10, 0xFFFF, sum = 0
2738 23:56:48.862536 11, 0xFFFF, sum = 0
2739 23:56:48.862589 12, 0x0, sum = 1
2740 23:56:48.862642 13, 0x0, sum = 2
2741 23:56:48.862694 14, 0x0, sum = 3
2742 23:56:48.862746 15, 0x0, sum = 4
2743 23:56:48.862799 best_step = 13
2744 23:56:48.862850
2745 23:56:48.862902 ==
2746 23:56:48.862954 Dram Type= 6, Freq= 0, CH_0, rank 0
2747 23:56:48.863007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2748 23:56:48.863059 ==
2749 23:56:48.863111 RX Vref Scan: 1
2750 23:56:48.863163
2751 23:56:48.863214 Set Vref Range= 32 -> 127
2752 23:56:48.863266
2753 23:56:48.863325 RX Vref 32 -> 127, step: 1
2754 23:56:48.863384
2755 23:56:48.863436 RX Delay -21 -> 252, step: 4
2756 23:56:48.863489
2757 23:56:48.863541 Set Vref, RX VrefLevel [Byte0]: 32
2758 23:56:48.863593 [Byte1]: 32
2759 23:56:48.863646
2760 23:56:48.863698 Set Vref, RX VrefLevel [Byte0]: 33
2761 23:56:48.863750 [Byte1]: 33
2762 23:56:48.863802
2763 23:56:48.863855 Set Vref, RX VrefLevel [Byte0]: 34
2764 23:56:48.863907 [Byte1]: 34
2765 23:56:48.863959
2766 23:56:48.864011 Set Vref, RX VrefLevel [Byte0]: 35
2767 23:56:48.864063 [Byte1]: 35
2768 23:56:48.864116
2769 23:56:48.864168 Set Vref, RX VrefLevel [Byte0]: 36
2770 23:56:48.864220 [Byte1]: 36
2771 23:56:48.864271
2772 23:56:48.864323 Set Vref, RX VrefLevel [Byte0]: 37
2773 23:56:48.864375 [Byte1]: 37
2774 23:56:48.864427
2775 23:56:48.864479 Set Vref, RX VrefLevel [Byte0]: 38
2776 23:56:48.864531 [Byte1]: 38
2777 23:56:48.864583
2778 23:56:48.864635 Set Vref, RX VrefLevel [Byte0]: 39
2779 23:56:48.864687 [Byte1]: 39
2780 23:56:48.864738
2781 23:56:48.864790 Set Vref, RX VrefLevel [Byte0]: 40
2782 23:56:48.864842 [Byte1]: 40
2783 23:56:48.864894
2784 23:56:48.864945 Set Vref, RX VrefLevel [Byte0]: 41
2785 23:56:48.864997 [Byte1]: 41
2786 23:56:48.865049
2787 23:56:48.865101 Set Vref, RX VrefLevel [Byte0]: 42
2788 23:56:48.865153 [Byte1]: 42
2789 23:56:48.865204
2790 23:56:48.865260 Set Vref, RX VrefLevel [Byte0]: 43
2791 23:56:48.865350 [Byte1]: 43
2792 23:56:48.865402
2793 23:56:48.865454 Set Vref, RX VrefLevel [Byte0]: 44
2794 23:56:48.865506 [Byte1]: 44
2795 23:56:48.865558
2796 23:56:48.865610 Set Vref, RX VrefLevel [Byte0]: 45
2797 23:56:48.865662 [Byte1]: 45
2798 23:56:48.865714
2799 23:56:48.865766 Set Vref, RX VrefLevel [Byte0]: 46
2800 23:56:48.865818 [Byte1]: 46
2801 23:56:48.865870
2802 23:56:48.865921 Set Vref, RX VrefLevel [Byte0]: 47
2803 23:56:48.865973 [Byte1]: 47
2804 23:56:48.866025
2805 23:56:48.866077 Set Vref, RX VrefLevel [Byte0]: 48
2806 23:56:48.866128 [Byte1]: 48
2807 23:56:48.866180
2808 23:56:48.866232 Set Vref, RX VrefLevel [Byte0]: 49
2809 23:56:48.866284 [Byte1]: 49
2810 23:56:48.866336
2811 23:56:48.866388 Set Vref, RX VrefLevel [Byte0]: 50
2812 23:56:48.866440 [Byte1]: 50
2813 23:56:48.866492
2814 23:56:48.866544 Set Vref, RX VrefLevel [Byte0]: 51
2815 23:56:48.866785 [Byte1]: 51
2816 23:56:48.866844
2817 23:56:48.866897 Set Vref, RX VrefLevel [Byte0]: 52
2818 23:56:48.866949 [Byte1]: 52
2819 23:56:48.867001
2820 23:56:48.867053 Set Vref, RX VrefLevel [Byte0]: 53
2821 23:56:48.867105 [Byte1]: 53
2822 23:56:48.867158
2823 23:56:48.867209 Set Vref, RX VrefLevel [Byte0]: 54
2824 23:56:48.867261 [Byte1]: 54
2825 23:56:48.867312
2826 23:56:48.867364 Set Vref, RX VrefLevel [Byte0]: 55
2827 23:56:48.867416 [Byte1]: 55
2828 23:56:48.867468
2829 23:56:48.867520 Set Vref, RX VrefLevel [Byte0]: 56
2830 23:56:48.867571 [Byte1]: 56
2831 23:56:48.867623
2832 23:56:48.867674 Set Vref, RX VrefLevel [Byte0]: 57
2833 23:56:48.867726 [Byte1]: 57
2834 23:56:48.867778
2835 23:56:48.867830 Set Vref, RX VrefLevel [Byte0]: 58
2836 23:56:48.867882 [Byte1]: 58
2837 23:56:48.867933
2838 23:56:48.867985 Set Vref, RX VrefLevel [Byte0]: 59
2839 23:56:48.868037 [Byte1]: 59
2840 23:56:48.868088
2841 23:56:48.868140 Set Vref, RX VrefLevel [Byte0]: 60
2842 23:56:48.868192 [Byte1]: 60
2843 23:56:48.868244
2844 23:56:48.868296 Set Vref, RX VrefLevel [Byte0]: 61
2845 23:56:48.868348 [Byte1]: 61
2846 23:56:48.868420
2847 23:56:48.868474 Set Vref, RX VrefLevel [Byte0]: 62
2848 23:56:48.868527 [Byte1]: 62
2849 23:56:48.868579
2850 23:56:48.868631 Set Vref, RX VrefLevel [Byte0]: 63
2851 23:56:48.868683 [Byte1]: 63
2852 23:56:48.868736
2853 23:56:48.868789 Set Vref, RX VrefLevel [Byte0]: 64
2854 23:56:48.868841 [Byte1]: 64
2855 23:56:48.868893
2856 23:56:48.868946 Set Vref, RX VrefLevel [Byte0]: 65
2857 23:56:48.868998 [Byte1]: 65
2858 23:56:48.869050
2859 23:56:48.869101 Set Vref, RX VrefLevel [Byte0]: 66
2860 23:56:48.869153 [Byte1]: 66
2861 23:56:48.869205
2862 23:56:48.869261 Set Vref, RX VrefLevel [Byte0]: 67
2863 23:56:48.869349 [Byte1]: 67
2864 23:56:48.869401
2865 23:56:48.869453 Set Vref, RX VrefLevel [Byte0]: 68
2866 23:56:48.869505 [Byte1]: 68
2867 23:56:48.869557
2868 23:56:48.869609 Set Vref, RX VrefLevel [Byte0]: 69
2869 23:56:48.869661 [Byte1]: 69
2870 23:56:48.869713
2871 23:56:48.869765 Final RX Vref Byte 0 = 54 to rank0
2872 23:56:48.869817 Final RX Vref Byte 1 = 59 to rank0
2873 23:56:48.869869 Final RX Vref Byte 0 = 54 to rank1
2874 23:56:48.869922 Final RX Vref Byte 1 = 59 to rank1==
2875 23:56:48.869974 Dram Type= 6, Freq= 0, CH_0, rank 0
2876 23:56:48.870028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 23:56:48.870080 ==
2878 23:56:48.870133 DQS Delay:
2879 23:56:48.870184 DQS0 = 0, DQS1 = 0
2880 23:56:48.870236 DQM Delay:
2881 23:56:48.870288 DQM0 = 117, DQM1 = 105
2882 23:56:48.870340 DQ Delay:
2883 23:56:48.870393 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2884 23:56:48.870444 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2885 23:56:48.870497 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2886 23:56:48.870549 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2887 23:56:48.870602
2888 23:56:48.870653
2889 23:56:48.870705 [DQSOSCAuto] RK0, (LSB)MR18= 0x601, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2890 23:56:48.870758 CH0 RK0: MR19=404, MR18=601
2891 23:56:48.870811 CH0_RK0: MR19=0x404, MR18=0x601, DQSOSC=407, MR23=63, INC=39, DEC=26
2892 23:56:48.870863
2893 23:56:48.870916 ----->DramcWriteLeveling(PI) begin...
2894 23:56:48.870970 ==
2895 23:56:48.871022 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 23:56:48.871074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 23:56:48.871127 ==
2898 23:56:48.871179 Write leveling (Byte 0): 32 => 32
2899 23:56:48.871231 Write leveling (Byte 1): 26 => 26
2900 23:56:48.871284 DramcWriteLeveling(PI) end<-----
2901 23:56:48.871335
2902 23:56:48.871387 ==
2903 23:56:48.871439 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 23:56:48.871491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 23:56:48.871544 ==
2906 23:56:48.871596 [Gating] SW mode calibration
2907 23:56:48.871649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2908 23:56:48.871702 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2909 23:56:48.871755 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2910 23:56:48.871807 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2911 23:56:48.871860 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 23:56:48.871912 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 23:56:48.871964 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 23:56:48.872017 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 23:56:48.872069 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2916 23:56:48.872121 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2917 23:56:48.872173 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2918 23:56:48.872226 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 23:56:48.872278 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 23:56:48.872330 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 23:56:48.872383 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 23:56:48.872435 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 23:56:48.872487 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2924 23:56:48.872539 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2925 23:56:48.872591 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
2926 23:56:48.872643 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 23:56:48.872696 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 23:56:48.872748 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 23:56:48.872800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 23:56:48.872852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 23:56:48.872904 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2932 23:56:48.872956 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2933 23:56:48.873008 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2934 23:56:48.873060 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:56:48.873113 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:56:48.873165 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:56:48.873217 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:56:48.873512 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:56:48.873578 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:56:48.873632 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:56:48.873685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:56:48.873767 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:56:48.873819 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:56:48.873872 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:56:48.873924 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:56:48.873977 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2947 23:56:48.874029 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2948 23:56:48.874081 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2949 23:56:48.874133 Total UI for P1: 0, mck2ui 16
2950 23:56:48.874186 best dqsien dly found for B0: ( 1, 3, 22)
2951 23:56:48.874239 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2952 23:56:48.874291 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 23:56:48.874359 Total UI for P1: 0, mck2ui 16
2954 23:56:48.874425 best dqsien dly found for B1: ( 1, 4, 0)
2955 23:56:48.874478 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2956 23:56:48.874530 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2957 23:56:48.874582
2958 23:56:48.874634 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2959 23:56:48.874686 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2960 23:56:48.874738 [Gating] SW calibration Done
2961 23:56:48.874791 ==
2962 23:56:48.874843 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 23:56:48.874895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 23:56:48.874949 ==
2965 23:56:48.875030 RX Vref Scan: 0
2966 23:56:48.875082
2967 23:56:48.875134 RX Vref 0 -> 0, step: 1
2968 23:56:48.875187
2969 23:56:48.875238 RX Delay -40 -> 252, step: 8
2970 23:56:48.875289 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2971 23:56:48.875341 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2972 23:56:48.875394 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2973 23:56:48.875446 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2974 23:56:48.875498 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2975 23:56:48.875550 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2976 23:56:48.875620 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2977 23:56:48.875685 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2978 23:56:48.875738 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2979 23:56:48.875789 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2980 23:56:48.875841 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2981 23:56:48.875894 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2982 23:56:48.875946 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2983 23:56:48.875998 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2984 23:56:48.876050 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2985 23:56:48.876102 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2986 23:56:48.876155 ==
2987 23:56:48.876223 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 23:56:48.876289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 23:56:48.876342 ==
2990 23:56:48.876394 DQS Delay:
2991 23:56:48.876446 DQS0 = 0, DQS1 = 0
2992 23:56:48.876497 DQM Delay:
2993 23:56:48.876549 DQM0 = 115, DQM1 = 109
2994 23:56:48.876601 DQ Delay:
2995 23:56:48.876653 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2996 23:56:48.876705 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2997 23:56:48.876758 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2998 23:56:48.876810 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2999 23:56:48.876892
3000 23:56:48.876943
3001 23:56:48.876994 ==
3002 23:56:48.877046 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 23:56:48.877098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 23:56:49.023222 ==
3005 23:56:49.023711
3006 23:56:49.024234
3007 23:56:49.024576 TX Vref Scan disable
3008 23:56:49.024888 == TX Byte 0 ==
3009 23:56:49.025242 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3010 23:56:49.025597 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3011 23:56:49.025912 == TX Byte 1 ==
3012 23:56:49.026435 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3013 23:56:49.026759 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3014 23:56:49.027106 ==
3015 23:56:49.027401 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 23:56:49.027687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 23:56:49.027974 ==
3018 23:56:49.028257 TX Vref=22, minBit 2, minWin=25, winSum=415
3019 23:56:49.028541 TX Vref=24, minBit 12, minWin=25, winSum=422
3020 23:56:49.028823 TX Vref=26, minBit 2, minWin=26, winSum=425
3021 23:56:49.029104 TX Vref=28, minBit 5, minWin=26, winSum=429
3022 23:56:49.029427 TX Vref=30, minBit 2, minWin=26, winSum=425
3023 23:56:49.029726 TX Vref=32, minBit 3, minWin=26, winSum=425
3024 23:56:49.030007 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 28
3025 23:56:49.030288
3026 23:56:49.030568 Final TX Range 1 Vref 28
3027 23:56:49.030845
3028 23:56:49.031119 ==
3029 23:56:49.031392 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 23:56:49.031670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 23:56:49.031948 ==
3032 23:56:49.032222
3033 23:56:49.032493
3034 23:56:49.032764 TX Vref Scan disable
3035 23:56:49.033042 == TX Byte 0 ==
3036 23:56:49.033343 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3037 23:56:49.033628 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3038 23:56:49.033904 == TX Byte 1 ==
3039 23:56:49.034179 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3040 23:56:49.034451 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3041 23:56:49.034728
3042 23:56:49.034999 [DATLAT]
3043 23:56:49.035272 Freq=1200, CH0 RK1
3044 23:56:49.035548
3045 23:56:49.035820 DATLAT Default: 0xd
3046 23:56:49.036140 0, 0xFFFF, sum = 0
3047 23:56:49.036427 1, 0xFFFF, sum = 0
3048 23:56:49.036706 2, 0xFFFF, sum = 0
3049 23:56:49.036982 3, 0xFFFF, sum = 0
3050 23:56:49.037281 4, 0xFFFF, sum = 0
3051 23:56:49.037583 5, 0xFFFF, sum = 0
3052 23:56:49.037860 6, 0xFFFF, sum = 0
3053 23:56:49.038137 7, 0xFFFF, sum = 0
3054 23:56:49.038410 8, 0xFFFF, sum = 0
3055 23:56:49.038690 9, 0xFFFF, sum = 0
3056 23:56:49.038969 10, 0xFFFF, sum = 0
3057 23:56:49.039249 11, 0xFFFF, sum = 0
3058 23:56:49.039524 12, 0x0, sum = 1
3059 23:56:49.039801 13, 0x0, sum = 2
3060 23:56:49.040077 14, 0x0, sum = 3
3061 23:56:49.040357 15, 0x0, sum = 4
3062 23:56:49.040634 best_step = 13
3063 23:56:49.040910
3064 23:56:49.041181 ==
3065 23:56:49.041498 Dram Type= 6, Freq= 0, CH_0, rank 1
3066 23:56:49.041775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 23:56:49.042052 ==
3068 23:56:49.042321 RX Vref Scan: 0
3069 23:56:49.042591
3070 23:56:49.042860 RX Vref 0 -> 0, step: 1
3071 23:56:49.043131
3072 23:56:49.043403 RX Delay -21 -> 252, step: 4
3073 23:56:49.043759 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3074 23:56:49.044042 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3075 23:56:49.044319 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3076 23:56:49.044977 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3077 23:56:49.045327 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3078 23:56:49.045621 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3079 23:56:49.045898 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3080 23:56:49.046309 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3081 23:56:49.046758 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3082 23:56:49.047057 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3083 23:56:49.047341 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3084 23:56:49.047620 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3085 23:56:49.047903 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3086 23:56:49.048180 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3087 23:56:49.048458 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3088 23:56:49.048735 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3089 23:56:49.049008 ==
3090 23:56:49.049300 Dram Type= 6, Freq= 0, CH_0, rank 1
3091 23:56:49.049579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 23:56:49.049857 ==
3093 23:56:49.050112 DQS Delay:
3094 23:56:49.050307 DQS0 = 0, DQS1 = 0
3095 23:56:49.050503 DQM Delay:
3096 23:56:49.050699 DQM0 = 115, DQM1 = 106
3097 23:56:49.050896 DQ Delay:
3098 23:56:49.051092 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3099 23:56:49.051287 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3100 23:56:49.051481 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3101 23:56:49.051676 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3102 23:56:49.051871
3103 23:56:49.052066
3104 23:56:49.052259 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3105 23:56:49.052460 CH0 RK1: MR19=303, MR18=FFFC
3106 23:56:49.052658 CH0_RK1: MR19=0x303, MR18=0xFFFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3107 23:56:49.052856 [RxdqsGatingPostProcess] freq 1200
3108 23:56:49.053054 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3109 23:56:49.053249 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 23:56:49.053462 best DQS1 dly(2T, 0.5T) = (0, 12)
3111 23:56:49.053656 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 23:56:49.053853 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3113 23:56:49.054051 best DQS0 dly(2T, 0.5T) = (0, 11)
3114 23:56:49.054249 best DQS1 dly(2T, 0.5T) = (0, 12)
3115 23:56:49.054447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3116 23:56:49.054645 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3117 23:56:49.054844 Pre-setting of DQS Precalculation
3118 23:56:49.055042 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3119 23:56:49.055192 ==
3120 23:56:49.055341 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 23:56:49.055489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 23:56:49.055638 ==
3123 23:56:49.055786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3124 23:56:49.055936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3125 23:56:49.056084 [CA 0] Center 38 (8~68) winsize 61
3126 23:56:49.056235 [CA 1] Center 37 (7~68) winsize 62
3127 23:56:49.056383 [CA 2] Center 35 (5~65) winsize 61
3128 23:56:49.056532 [CA 3] Center 34 (4~64) winsize 61
3129 23:56:49.056678 [CA 4] Center 34 (4~65) winsize 62
3130 23:56:49.056825 [CA 5] Center 33 (3~64) winsize 62
3131 23:56:49.056973
3132 23:56:49.057122 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3133 23:56:49.057278
3134 23:56:49.057428 [CATrainingPosCal] consider 1 rank data
3135 23:56:49.057578 u2DelayCellTimex100 = 270/100 ps
3136 23:56:49.057727 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3137 23:56:49.057877 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3138 23:56:49.058026 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3139 23:56:49.058175 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 23:56:49.058324 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3141 23:56:49.058473 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 23:56:49.058622
3143 23:56:49.058770 CA PerBit enable=1, Macro0, CA PI delay=33
3144 23:56:49.058917
3145 23:56:49.059066 [CBTSetCACLKResult] CA Dly = 33
3146 23:56:49.059213 CS Dly: 5 (0~36)
3147 23:56:49.059360 ==
3148 23:56:49.059509 Dram Type= 6, Freq= 0, CH_1, rank 1
3149 23:56:49.059658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3150 23:56:49.059806 ==
3151 23:56:49.059953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3152 23:56:49.060089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3153 23:56:49.060209 [CA 0] Center 37 (7~68) winsize 62
3154 23:56:49.060327 [CA 1] Center 38 (8~68) winsize 61
3155 23:56:49.060446 [CA 2] Center 35 (5~65) winsize 61
3156 23:56:49.060566 [CA 3] Center 33 (3~64) winsize 62
3157 23:56:49.060683 [CA 4] Center 34 (4~64) winsize 61
3158 23:56:49.060801 [CA 5] Center 33 (3~63) winsize 61
3159 23:56:49.060918
3160 23:56:49.061037 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3161 23:56:49.061156
3162 23:56:49.061283 [CATrainingPosCal] consider 2 rank data
3163 23:56:49.061404 u2DelayCellTimex100 = 270/100 ps
3164 23:56:49.061524 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3165 23:56:49.061644 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3166 23:56:49.061765 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3167 23:56:49.061885 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3168 23:56:49.062004 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 23:56:49.062124 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3170 23:56:49.062242
3171 23:56:49.062360 CA PerBit enable=1, Macro0, CA PI delay=33
3172 23:56:49.062479
3173 23:56:49.062597 [CBTSetCACLKResult] CA Dly = 33
3174 23:56:49.062715 CS Dly: 6 (0~39)
3175 23:56:49.062833
3176 23:56:49.062951 ----->DramcWriteLeveling(PI) begin...
3177 23:56:49.063074 ==
3178 23:56:49.063194 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 23:56:49.063313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 23:56:49.063432 ==
3181 23:56:49.063551 Write leveling (Byte 0): 24 => 24
3182 23:56:49.063671 Write leveling (Byte 1): 28 => 28
3183 23:56:49.063790 DramcWriteLeveling(PI) end<-----
3184 23:56:49.063908
3185 23:56:49.064026 ==
3186 23:56:49.064145 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 23:56:49.064264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 23:56:49.064384 ==
3189 23:56:49.064503 [Gating] SW mode calibration
3190 23:56:49.064621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3191 23:56:49.064741 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3192 23:56:49.064860 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
3193 23:56:49.064980 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 23:56:49.065093 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 23:56:49.065432 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 23:56:49.065544 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 23:56:49.065646 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 23:56:49.065747 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3199 23:56:49.065847 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3200 23:56:49.065946 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 23:56:49.066047 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 23:56:49.066146 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 23:56:49.066245 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 23:56:49.066346 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 23:56:49.066447 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 23:56:49.066549 1 0 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 1)
3207 23:56:49.066648 1 0 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3208 23:56:49.066748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 23:56:49.066848 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 23:56:49.066947 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 23:56:49.067046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 23:56:49.067145 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 23:56:49.067245 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 23:56:49.067344 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 23:56:49.067443 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3216 23:56:49.067544 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:56:49.067643 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:56:49.067742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:56:49.067840 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:56:49.067938 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:56:49.068038 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:56:49.068137 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:56:49.068237 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:56:49.068336 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:56:49.068435 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:56:49.068535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:56:49.068634 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:56:49.068733 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:56:49.068832 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:56:49.068931 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3231 23:56:49.069030 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3232 23:56:49.069129 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 23:56:49.069228 Total UI for P1: 0, mck2ui 16
3234 23:56:49.069341 best dqsien dly found for B0: ( 1, 3, 26)
3235 23:56:49.069441 Total UI for P1: 0, mck2ui 16
3236 23:56:49.069541 best dqsien dly found for B1: ( 1, 3, 26)
3237 23:56:49.069641 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3238 23:56:49.069740 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3239 23:56:49.069839
3240 23:56:49.069936 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3241 23:56:49.070038 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3242 23:56:49.070123 [Gating] SW calibration Done
3243 23:56:49.070208 ==
3244 23:56:49.070293 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 23:56:49.070378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 23:56:49.070465 ==
3247 23:56:49.070550 RX Vref Scan: 0
3248 23:56:49.070633
3249 23:56:49.070718 RX Vref 0 -> 0, step: 1
3250 23:56:49.070802
3251 23:56:49.070886 RX Delay -40 -> 252, step: 8
3252 23:56:49.070971 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3253 23:56:49.071056 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3254 23:56:49.071142 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3255 23:56:49.071227 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3256 23:56:49.071312 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3257 23:56:49.071396 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3258 23:56:49.071483 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3259 23:56:49.071568 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3260 23:56:49.071652 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3261 23:56:49.071737 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3262 23:56:49.071822 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3263 23:56:49.071907 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3264 23:56:49.071991 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3265 23:56:49.072076 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3266 23:56:49.072161 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3267 23:56:49.072246 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3268 23:56:49.072331 ==
3269 23:56:49.072416 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 23:56:49.072501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 23:56:49.072586 ==
3272 23:56:49.072672 DQS Delay:
3273 23:56:49.072756 DQS0 = 0, DQS1 = 0
3274 23:56:49.072841 DQM Delay:
3275 23:56:49.072926 DQM0 = 114, DQM1 = 113
3276 23:56:49.073010 DQ Delay:
3277 23:56:49.073094 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =115
3278 23:56:49.073178 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3279 23:56:49.073268 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3280 23:56:49.073354 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3281 23:56:49.073438
3282 23:56:49.073522
3283 23:56:49.073606 ==
3284 23:56:49.073691 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 23:56:49.073776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 23:56:49.073864 ==
3287 23:56:49.073949
3288 23:56:49.074033
3289 23:56:49.074116 TX Vref Scan disable
3290 23:56:49.074201 == TX Byte 0 ==
3291 23:56:49.074285 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3292 23:56:49.074372 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3293 23:56:49.074457 == TX Byte 1 ==
3294 23:56:49.074543 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3295 23:56:49.074628 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3296 23:56:49.074713 ==
3297 23:56:49.074799 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 23:56:49.074885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 23:56:49.074980 ==
3300 23:56:49.075054 TX Vref=22, minBit 1, minWin=25, winSum=411
3301 23:56:49.075130 TX Vref=24, minBit 3, minWin=25, winSum=418
3302 23:56:49.075413 TX Vref=26, minBit 9, minWin=25, winSum=422
3303 23:56:49.075497 TX Vref=28, minBit 3, minWin=25, winSum=425
3304 23:56:49.075573 TX Vref=30, minBit 9, minWin=25, winSum=427
3305 23:56:49.075649 TX Vref=32, minBit 8, minWin=25, winSum=430
3306 23:56:49.075725 [TxChooseVref] Worse bit 8, Min win 25, Win sum 430, Final Vref 32
3307 23:56:49.075800
3308 23:56:49.075874 Final TX Range 1 Vref 32
3309 23:56:49.075950
3310 23:56:49.076023 ==
3311 23:56:49.076097 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 23:56:49.076173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 23:56:49.076248 ==
3314 23:56:49.076323
3315 23:56:49.076396
3316 23:56:49.076471 TX Vref Scan disable
3317 23:56:49.076565 == TX Byte 0 ==
3318 23:56:49.076643 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3319 23:56:49.076718 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3320 23:56:49.076793 == TX Byte 1 ==
3321 23:56:49.076868 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3322 23:56:49.076944 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3323 23:56:49.077019
3324 23:56:49.077093 [DATLAT]
3325 23:56:49.077168 Freq=1200, CH1 RK0
3326 23:56:49.077243
3327 23:56:49.077331 DATLAT Default: 0xd
3328 23:56:49.077406 0, 0xFFFF, sum = 0
3329 23:56:49.077484 1, 0xFFFF, sum = 0
3330 23:56:49.077559 2, 0xFFFF, sum = 0
3331 23:56:49.077634 3, 0xFFFF, sum = 0
3332 23:56:49.077710 4, 0xFFFF, sum = 0
3333 23:56:49.077787 5, 0xFFFF, sum = 0
3334 23:56:49.077863 6, 0xFFFF, sum = 0
3335 23:56:49.077939 7, 0xFFFF, sum = 0
3336 23:56:49.078016 8, 0xFFFF, sum = 0
3337 23:56:49.078092 9, 0xFFFF, sum = 0
3338 23:56:49.078167 10, 0xFFFF, sum = 0
3339 23:56:49.078243 11, 0xFFFF, sum = 0
3340 23:56:49.078318 12, 0x0, sum = 1
3341 23:56:49.078394 13, 0x0, sum = 2
3342 23:56:49.078469 14, 0x0, sum = 3
3343 23:56:49.078544 15, 0x0, sum = 4
3344 23:56:49.078620 best_step = 13
3345 23:56:49.078694
3346 23:56:49.078769 ==
3347 23:56:49.078843 Dram Type= 6, Freq= 0, CH_1, rank 0
3348 23:56:49.078919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3349 23:56:49.078994 ==
3350 23:56:49.079069 RX Vref Scan: 1
3351 23:56:49.079143
3352 23:56:49.079218 Set Vref Range= 32 -> 127
3353 23:56:49.079294
3354 23:56:49.079368 RX Vref 32 -> 127, step: 1
3355 23:56:49.079443
3356 23:56:49.079517 RX Delay -13 -> 252, step: 4
3357 23:56:49.079592
3358 23:56:49.079666 Set Vref, RX VrefLevel [Byte0]: 32
3359 23:56:49.079742 [Byte1]: 32
3360 23:56:49.079816
3361 23:56:49.079890 Set Vref, RX VrefLevel [Byte0]: 33
3362 23:56:49.079965 [Byte1]: 33
3363 23:56:49.080045
3364 23:56:49.080110 Set Vref, RX VrefLevel [Byte0]: 34
3365 23:56:49.080176 [Byte1]: 34
3366 23:56:49.080242
3367 23:56:49.080307 Set Vref, RX VrefLevel [Byte0]: 35
3368 23:56:49.080373 [Byte1]: 35
3369 23:56:49.080439
3370 23:56:49.080504 Set Vref, RX VrefLevel [Byte0]: 36
3371 23:56:49.080570 [Byte1]: 36
3372 23:56:49.080635
3373 23:56:49.080700 Set Vref, RX VrefLevel [Byte0]: 37
3374 23:56:49.080766 [Byte1]: 37
3375 23:56:49.080832
3376 23:56:49.080897 Set Vref, RX VrefLevel [Byte0]: 38
3377 23:56:49.080962 [Byte1]: 38
3378 23:56:49.081029
3379 23:56:49.081094 Set Vref, RX VrefLevel [Byte0]: 39
3380 23:56:49.081160 [Byte1]: 39
3381 23:56:49.081225
3382 23:56:49.081301 Set Vref, RX VrefLevel [Byte0]: 40
3383 23:56:49.081368 [Byte1]: 40
3384 23:56:49.081434
3385 23:56:49.081500 Set Vref, RX VrefLevel [Byte0]: 41
3386 23:56:49.081565 [Byte1]: 41
3387 23:56:49.081630
3388 23:56:49.081696 Set Vref, RX VrefLevel [Byte0]: 42
3389 23:56:49.081761 [Byte1]: 42
3390 23:56:49.081826
3391 23:56:49.081892 Set Vref, RX VrefLevel [Byte0]: 43
3392 23:56:49.081958 [Byte1]: 43
3393 23:56:49.082024
3394 23:56:49.082089 Set Vref, RX VrefLevel [Byte0]: 44
3395 23:56:49.082155 [Byte1]: 44
3396 23:56:49.082221
3397 23:56:49.082286 Set Vref, RX VrefLevel [Byte0]: 45
3398 23:56:49.082352 [Byte1]: 45
3399 23:56:49.082418
3400 23:56:49.082483 Set Vref, RX VrefLevel [Byte0]: 46
3401 23:56:49.082548 [Byte1]: 46
3402 23:56:49.082614
3403 23:56:49.082679 Set Vref, RX VrefLevel [Byte0]: 47
3404 23:56:49.082748 [Byte1]: 47
3405 23:56:49.082814
3406 23:56:49.082880 Set Vref, RX VrefLevel [Byte0]: 48
3407 23:56:49.082945 [Byte1]: 48
3408 23:56:49.083011
3409 23:56:49.083076 Set Vref, RX VrefLevel [Byte0]: 49
3410 23:56:49.083141 [Byte1]: 49
3411 23:56:49.083206
3412 23:56:49.083271 Set Vref, RX VrefLevel [Byte0]: 50
3413 23:56:49.083337 [Byte1]: 50
3414 23:56:49.083403
3415 23:56:49.083468 Set Vref, RX VrefLevel [Byte0]: 51
3416 23:56:49.083533 [Byte1]: 51
3417 23:56:49.083599
3418 23:56:49.083665 Set Vref, RX VrefLevel [Byte0]: 52
3419 23:56:49.083743 [Byte1]: 52
3420 23:56:49.083812
3421 23:56:49.083877 Set Vref, RX VrefLevel [Byte0]: 53
3422 23:56:49.083944 [Byte1]: 53
3423 23:56:49.084009
3424 23:56:49.084075 Set Vref, RX VrefLevel [Byte0]: 54
3425 23:56:49.084141 [Byte1]: 54
3426 23:56:49.084207
3427 23:56:49.084273 Set Vref, RX VrefLevel [Byte0]: 55
3428 23:56:49.084338 [Byte1]: 55
3429 23:56:49.084403
3430 23:56:49.084469 Set Vref, RX VrefLevel [Byte0]: 56
3431 23:56:49.084535 [Byte1]: 56
3432 23:56:49.084601
3433 23:56:49.084666 Set Vref, RX VrefLevel [Byte0]: 57
3434 23:56:49.084731 [Byte1]: 57
3435 23:56:49.084797
3436 23:56:49.084863 Set Vref, RX VrefLevel [Byte0]: 58
3437 23:56:49.084928 [Byte1]: 58
3438 23:56:49.085002
3439 23:56:49.085061 Set Vref, RX VrefLevel [Byte0]: 59
3440 23:56:49.085119 [Byte1]: 59
3441 23:56:49.085178
3442 23:56:49.085236 Set Vref, RX VrefLevel [Byte0]: 60
3443 23:56:49.085301 [Byte1]: 60
3444 23:56:49.085360
3445 23:56:49.085419 Set Vref, RX VrefLevel [Byte0]: 61
3446 23:56:49.085479 [Byte1]: 61
3447 23:56:49.085539
3448 23:56:49.085598 Set Vref, RX VrefLevel [Byte0]: 62
3449 23:56:49.085657 [Byte1]: 62
3450 23:56:49.085717
3451 23:56:49.085775 Set Vref, RX VrefLevel [Byte0]: 63
3452 23:56:49.085834 [Byte1]: 63
3453 23:56:49.085894
3454 23:56:49.085952 Set Vref, RX VrefLevel [Byte0]: 64
3455 23:56:49.086011 [Byte1]: 64
3456 23:56:49.086070
3457 23:56:49.086129 Set Vref, RX VrefLevel [Byte0]: 65
3458 23:56:49.086189 [Byte1]: 65
3459 23:56:49.086248
3460 23:56:49.086306 Final RX Vref Byte 0 = 53 to rank0
3461 23:56:49.086367 Final RX Vref Byte 1 = 52 to rank0
3462 23:56:49.086426 Final RX Vref Byte 0 = 53 to rank1
3463 23:56:49.086486 Final RX Vref Byte 1 = 52 to rank1==
3464 23:56:49.086545 Dram Type= 6, Freq= 0, CH_1, rank 0
3465 23:56:49.086605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 23:56:49.086664 ==
3467 23:56:49.086723 DQS Delay:
3468 23:56:49.086782 DQS0 = 0, DQS1 = 0
3469 23:56:49.086841 DQM Delay:
3470 23:56:49.086900 DQM0 = 114, DQM1 = 113
3471 23:56:49.087160 DQ Delay:
3472 23:56:49.087227 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3473 23:56:49.087288 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3474 23:56:49.087347 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3475 23:56:49.087407 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3476 23:56:49.087466
3477 23:56:49.087526
3478 23:56:49.087585 [DQSOSCAuto] RK0, (LSB)MR18= 0xf603, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 414 ps
3479 23:56:49.087649 CH1 RK0: MR19=304, MR18=F603
3480 23:56:49.087709 CH1_RK0: MR19=0x304, MR18=0xF603, DQSOSC=408, MR23=63, INC=39, DEC=26
3481 23:56:49.087768
3482 23:56:49.087827 ----->DramcWriteLeveling(PI) begin...
3483 23:56:49.087888 ==
3484 23:56:49.087947 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 23:56:49.088007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 23:56:49.088067 ==
3487 23:56:49.088127 Write leveling (Byte 0): 27 => 27
3488 23:56:49.088186 Write leveling (Byte 1): 30 => 30
3489 23:56:49.088245 DramcWriteLeveling(PI) end<-----
3490 23:56:49.088304
3491 23:56:49.088363 ==
3492 23:56:49.088422 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 23:56:49.088481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 23:56:49.088541 ==
3495 23:56:49.088601 [Gating] SW mode calibration
3496 23:56:49.088660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3497 23:56:49.088720 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3498 23:56:49.088779 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3499 23:56:49.088839 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 23:56:49.088899 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 23:56:49.088958 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 23:56:49.089018 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 23:56:49.089077 0 15 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3504 23:56:49.089137 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
3505 23:56:49.089195 0 15 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3506 23:56:49.089254 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 23:56:49.089321 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 23:56:49.089381 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 23:56:49.089440 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 23:56:49.089499 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 23:56:49.089559 1 0 20 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3512 23:56:49.089619 1 0 24 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
3513 23:56:49.089677 1 0 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3514 23:56:49.089736 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 23:56:49.089796 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 23:56:49.089855 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 23:56:49.089914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 23:56:49.089985 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 23:56:49.090038 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3520 23:56:49.090092 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3521 23:56:49.090145 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3522 23:56:49.090200 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:56:49.090255 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:56:49.090308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:56:49.090362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:56:49.090416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:56:49.090470 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:56:49.090524 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:56:49.090578 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:56:49.090632 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:56:49.090686 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:56:49.090740 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:56:49.090794 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:56:49.090848 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:56:49.090902 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:56:49.090956 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3537 23:56:49.091009 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3538 23:56:49.091063 Total UI for P1: 0, mck2ui 16
3539 23:56:49.091118 best dqsien dly found for B0: ( 1, 3, 24)
3540 23:56:49.091172 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 23:56:49.091226 Total UI for P1: 0, mck2ui 16
3542 23:56:49.091280 best dqsien dly found for B1: ( 1, 3, 28)
3543 23:56:49.091333 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3544 23:56:49.091387 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3545 23:56:49.091440
3546 23:56:49.091493 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3547 23:56:49.091547 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3548 23:56:49.091601 [Gating] SW calibration Done
3549 23:56:49.091655 ==
3550 23:56:49.091708 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 23:56:49.091762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 23:56:49.091816 ==
3553 23:56:49.091869 RX Vref Scan: 0
3554 23:56:49.091923
3555 23:56:49.091976 RX Vref 0 -> 0, step: 1
3556 23:56:49.092029
3557 23:56:49.092082 RX Delay -40 -> 252, step: 8
3558 23:56:49.092136 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3559 23:56:49.092191 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3560 23:56:49.092245 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3561 23:56:49.092299 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3562 23:56:49.092353 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3563 23:56:49.092406 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3564 23:56:49.092460 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3565 23:56:49.092514 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3566 23:56:49.092567 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3567 23:56:49.092621 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3568 23:56:49.092675 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3569 23:56:49.092729 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3570 23:56:49.092783 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3571 23:56:49.093030 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3572 23:56:49.093091 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3573 23:56:49.093145 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3574 23:56:49.093200 ==
3575 23:56:49.093254 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 23:56:49.093320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 23:56:49.093375 ==
3578 23:56:49.093429 DQS Delay:
3579 23:56:49.093482 DQS0 = 0, DQS1 = 0
3580 23:56:49.093555 DQM Delay:
3581 23:56:49.093612 DQM0 = 115, DQM1 = 112
3582 23:56:49.093666 DQ Delay:
3583 23:56:49.093720 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3584 23:56:49.093774 DQ4 =119, DQ5 =127, DQ6 =119, DQ7 =111
3585 23:56:49.093828 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3586 23:56:49.093882 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3587 23:56:49.093936
3588 23:56:49.093990
3589 23:56:49.094044 ==
3590 23:56:49.094100 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 23:56:49.094155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 23:56:49.094209 ==
3593 23:56:49.094263
3594 23:56:49.094316
3595 23:56:49.094370 TX Vref Scan disable
3596 23:56:49.094424 == TX Byte 0 ==
3597 23:56:49.094479 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3598 23:56:49.094534 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3599 23:56:49.094589 == TX Byte 1 ==
3600 23:56:49.094643 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3601 23:56:49.094697 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3602 23:56:49.094751 ==
3603 23:56:49.094805 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 23:56:49.094859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 23:56:49.094914 ==
3606 23:56:49.094981 TX Vref=22, minBit 1, minWin=25, winSum=420
3607 23:56:49.095034 TX Vref=24, minBit 1, minWin=26, winSum=427
3608 23:56:49.095086 TX Vref=26, minBit 1, minWin=26, winSum=429
3609 23:56:49.095139 TX Vref=28, minBit 1, minWin=26, winSum=433
3610 23:56:49.095192 TX Vref=30, minBit 1, minWin=26, winSum=430
3611 23:56:49.095244 TX Vref=32, minBit 1, minWin=26, winSum=430
3612 23:56:49.095297 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3613 23:56:49.095349
3614 23:56:49.095402 Final TX Range 1 Vref 28
3615 23:56:49.095454
3616 23:56:49.095507 ==
3617 23:56:49.095558 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 23:56:49.095611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 23:56:49.095664 ==
3620 23:56:49.095717
3621 23:56:49.095769
3622 23:56:49.095821 TX Vref Scan disable
3623 23:56:49.095874 == TX Byte 0 ==
3624 23:56:49.095926 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3625 23:56:49.095979 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3626 23:56:49.096032 == TX Byte 1 ==
3627 23:56:49.096085 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3628 23:56:49.096137 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3629 23:56:49.096190
3630 23:56:49.096241 [DATLAT]
3631 23:56:49.096293 Freq=1200, CH1 RK1
3632 23:56:49.096346
3633 23:56:49.096398 DATLAT Default: 0xd
3634 23:56:49.096451 0, 0xFFFF, sum = 0
3635 23:56:49.096505 1, 0xFFFF, sum = 0
3636 23:56:49.096559 2, 0xFFFF, sum = 0
3637 23:56:49.096612 3, 0xFFFF, sum = 0
3638 23:56:49.096666 4, 0xFFFF, sum = 0
3639 23:56:49.096719 5, 0xFFFF, sum = 0
3640 23:56:49.096773 6, 0xFFFF, sum = 0
3641 23:56:49.096827 7, 0xFFFF, sum = 0
3642 23:56:49.096881 8, 0xFFFF, sum = 0
3643 23:56:49.096934 9, 0xFFFF, sum = 0
3644 23:56:49.096987 10, 0xFFFF, sum = 0
3645 23:56:49.097041 11, 0xFFFF, sum = 0
3646 23:56:49.097094 12, 0x0, sum = 1
3647 23:56:49.097147 13, 0x0, sum = 2
3648 23:56:49.097200 14, 0x0, sum = 3
3649 23:56:49.097280 15, 0x0, sum = 4
3650 23:56:49.097348 best_step = 13
3651 23:56:49.097400
3652 23:56:49.097452 ==
3653 23:56:49.097505 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 23:56:49.097557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 23:56:49.097611 ==
3656 23:56:49.097664 RX Vref Scan: 0
3657 23:56:49.097716
3658 23:56:49.097768 RX Vref 0 -> 0, step: 1
3659 23:56:49.097821
3660 23:56:49.097873 RX Delay -13 -> 252, step: 4
3661 23:56:49.097926 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3662 23:56:49.097980 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3663 23:56:49.098032 iDelay=191, Bit 2, Center 106 (39 ~ 174) 136
3664 23:56:49.098085 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3665 23:56:49.098138 iDelay=191, Bit 4, Center 114 (43 ~ 186) 144
3666 23:56:49.098191 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3667 23:56:49.098243 iDelay=191, Bit 6, Center 120 (51 ~ 190) 140
3668 23:56:49.098296 iDelay=191, Bit 7, Center 112 (43 ~ 182) 140
3669 23:56:49.098348 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3670 23:56:49.098401 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3671 23:56:49.098453 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3672 23:56:49.098507 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3673 23:56:49.098559 iDelay=191, Bit 12, Center 118 (55 ~ 182) 128
3674 23:56:49.098612 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3675 23:56:49.098664 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3676 23:56:49.098717 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3677 23:56:49.098769 ==
3678 23:56:49.098821 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 23:56:49.098873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 23:56:49.098926 ==
3681 23:56:49.098978 DQS Delay:
3682 23:56:49.099032 DQS0 = 0, DQS1 = 0
3683 23:56:49.099084 DQM Delay:
3684 23:56:49.099137 DQM0 = 114, DQM1 = 111
3685 23:56:49.099189 DQ Delay:
3686 23:56:49.099242 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3687 23:56:49.099294 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =112
3688 23:56:49.099347 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3689 23:56:49.099400 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3690 23:56:49.099453
3691 23:56:49.099505
3692 23:56:49.099557 [DQSOSCAuto] RK1, (LSB)MR18= 0xf80a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3693 23:56:49.099611 CH1 RK1: MR19=304, MR18=F80A
3694 23:56:49.099664 CH1_RK1: MR19=0x304, MR18=0xF80A, DQSOSC=406, MR23=63, INC=39, DEC=26
3695 23:56:49.099718 [RxdqsGatingPostProcess] freq 1200
3696 23:56:49.099771 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3697 23:56:49.099824 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 23:56:49.099877 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 23:56:49.099961 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 23:56:49.100013 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 23:56:49.100066 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 23:56:49.100119 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 23:56:49.100171 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 23:56:49.100224 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 23:56:49.100276 Pre-setting of DQS Precalculation
3706 23:56:49.100328 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3707 23:56:49.100381 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3708 23:56:49.100632 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3709 23:56:49.100696
3710 23:56:49.100749
3711 23:56:49.100801 [Calibration Summary] 2400 Mbps
3712 23:56:49.100854 CH 0, Rank 0
3713 23:56:49.100907 SW Impedance : PASS
3714 23:56:49.100960 DUTY Scan : NO K
3715 23:56:49.101013 ZQ Calibration : PASS
3716 23:56:49.101065 Jitter Meter : NO K
3717 23:56:49.101118 CBT Training : PASS
3718 23:56:49.101171 Write leveling : PASS
3719 23:56:49.101224 RX DQS gating : PASS
3720 23:56:49.101310 RX DQ/DQS(RDDQC) : PASS
3721 23:56:49.101363 TX DQ/DQS : PASS
3722 23:56:49.101416 RX DATLAT : PASS
3723 23:56:49.101469 RX DQ/DQS(Engine): PASS
3724 23:56:49.101521 TX OE : NO K
3725 23:56:49.101573 All Pass.
3726 23:56:49.101626
3727 23:56:49.101678 CH 0, Rank 1
3728 23:56:49.101731 SW Impedance : PASS
3729 23:56:49.101783 DUTY Scan : NO K
3730 23:56:49.101835 ZQ Calibration : PASS
3731 23:56:49.101888 Jitter Meter : NO K
3732 23:56:49.101941 CBT Training : PASS
3733 23:56:49.101993 Write leveling : PASS
3734 23:56:49.102046 RX DQS gating : PASS
3735 23:56:49.102098 RX DQ/DQS(RDDQC) : PASS
3736 23:56:49.102151 TX DQ/DQS : PASS
3737 23:56:49.102204 RX DATLAT : PASS
3738 23:56:49.102256 RX DQ/DQS(Engine): PASS
3739 23:56:49.102308 TX OE : NO K
3740 23:56:49.102361 All Pass.
3741 23:56:49.102414
3742 23:56:49.102466 CH 1, Rank 0
3743 23:56:49.102518 SW Impedance : PASS
3744 23:56:49.102570 DUTY Scan : NO K
3745 23:56:49.102623 ZQ Calibration : PASS
3746 23:56:49.102675 Jitter Meter : NO K
3747 23:56:49.102727 CBT Training : PASS
3748 23:56:49.102780 Write leveling : PASS
3749 23:56:49.102832 RX DQS gating : PASS
3750 23:56:49.102886 RX DQ/DQS(RDDQC) : PASS
3751 23:56:49.102938 TX DQ/DQS : PASS
3752 23:56:49.102990 RX DATLAT : PASS
3753 23:56:49.103043 RX DQ/DQS(Engine): PASS
3754 23:56:49.103096 TX OE : NO K
3755 23:56:49.103149 All Pass.
3756 23:56:49.103202
3757 23:56:49.103254 CH 1, Rank 1
3758 23:56:49.103306 SW Impedance : PASS
3759 23:56:49.103359 DUTY Scan : NO K
3760 23:56:49.103411 ZQ Calibration : PASS
3761 23:56:49.103464 Jitter Meter : NO K
3762 23:56:49.103517 CBT Training : PASS
3763 23:56:49.103570 Write leveling : PASS
3764 23:56:49.103622 RX DQS gating : PASS
3765 23:56:49.103676 RX DQ/DQS(RDDQC) : PASS
3766 23:56:49.103729 TX DQ/DQS : PASS
3767 23:56:49.103781 RX DATLAT : PASS
3768 23:56:49.103834 RX DQ/DQS(Engine): PASS
3769 23:56:49.103886 TX OE : NO K
3770 23:56:49.103939 All Pass.
3771 23:56:49.103991
3772 23:56:49.104043 DramC Write-DBI off
3773 23:56:49.104096 PER_BANK_REFRESH: Hybrid Mode
3774 23:56:49.104149 TX_TRACKING: ON
3775 23:56:49.104202 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3776 23:56:49.104257 [FAST_K] Save calibration result to emmc
3777 23:56:49.104309 dramc_set_vcore_voltage set vcore to 650000
3778 23:56:49.104362 Read voltage for 600, 5
3779 23:56:49.104415 Vio18 = 0
3780 23:56:49.104467 Vcore = 650000
3781 23:56:49.104519 Vdram = 0
3782 23:56:49.104572 Vddq = 0
3783 23:56:49.104624 Vmddr = 0
3784 23:56:49.104676 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3785 23:56:49.104729 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3786 23:56:49.104782 MEM_TYPE=3, freq_sel=19
3787 23:56:49.104834 sv_algorithm_assistance_LP4_1600
3788 23:56:49.104887 ============ PULL DRAM RESETB DOWN ============
3789 23:56:49.104940 ========== PULL DRAM RESETB DOWN end =========
3790 23:56:49.104993 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3791 23:56:49.105045 ===================================
3792 23:56:49.105098 LPDDR4 DRAM CONFIGURATION
3793 23:56:49.105151 ===================================
3794 23:56:49.105202 EX_ROW_EN[0] = 0x0
3795 23:56:49.105259 EX_ROW_EN[1] = 0x0
3796 23:56:49.105351 LP4Y_EN = 0x0
3797 23:56:49.105404 WORK_FSP = 0x0
3798 23:56:49.105457 WL = 0x2
3799 23:56:49.105509 RL = 0x2
3800 23:56:49.105562 BL = 0x2
3801 23:56:49.105615 RPST = 0x0
3802 23:56:49.105667 RD_PRE = 0x0
3803 23:56:49.105719 WR_PRE = 0x1
3804 23:56:49.105771 WR_PST = 0x0
3805 23:56:49.105823 DBI_WR = 0x0
3806 23:56:49.105876 DBI_RD = 0x0
3807 23:56:49.105928 OTF = 0x1
3808 23:56:49.105981 ===================================
3809 23:56:49.106034 ===================================
3810 23:56:49.106087 ANA top config
3811 23:56:49.106139 ===================================
3812 23:56:49.106191 DLL_ASYNC_EN = 0
3813 23:56:49.106244 ALL_SLAVE_EN = 1
3814 23:56:49.106296 NEW_RANK_MODE = 1
3815 23:56:49.106349 DLL_IDLE_MODE = 1
3816 23:56:49.106401 LP45_APHY_COMB_EN = 1
3817 23:56:49.106453 TX_ODT_DIS = 1
3818 23:56:49.106506 NEW_8X_MODE = 1
3819 23:56:49.106559 ===================================
3820 23:56:49.106612 ===================================
3821 23:56:49.106665 data_rate = 1200
3822 23:56:49.106718 CKR = 1
3823 23:56:49.106770 DQ_P2S_RATIO = 8
3824 23:56:49.106822 ===================================
3825 23:56:49.106874 CA_P2S_RATIO = 8
3826 23:56:49.106929 DQ_CA_OPEN = 0
3827 23:56:49.107000 DQ_SEMI_OPEN = 0
3828 23:56:49.107054 CA_SEMI_OPEN = 0
3829 23:56:49.107106 CA_FULL_RATE = 0
3830 23:56:49.107159 DQ_CKDIV4_EN = 1
3831 23:56:49.107212 CA_CKDIV4_EN = 1
3832 23:56:49.107264 CA_PREDIV_EN = 0
3833 23:56:49.107317 PH8_DLY = 0
3834 23:56:49.107369 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3835 23:56:49.107422 DQ_AAMCK_DIV = 4
3836 23:56:49.107474 CA_AAMCK_DIV = 4
3837 23:56:49.107526 CA_ADMCK_DIV = 4
3838 23:56:49.107579 DQ_TRACK_CA_EN = 0
3839 23:56:49.107631 CA_PICK = 600
3840 23:56:49.107683 CA_MCKIO = 600
3841 23:56:49.107735 MCKIO_SEMI = 0
3842 23:56:49.107788 PLL_FREQ = 2288
3843 23:56:49.107840 DQ_UI_PI_RATIO = 32
3844 23:56:49.107892 CA_UI_PI_RATIO = 0
3845 23:56:49.107945 ===================================
3846 23:56:49.107998 ===================================
3847 23:56:49.108052 memory_type:LPDDR4
3848 23:56:49.108105 GP_NUM : 10
3849 23:56:49.108158 SRAM_EN : 1
3850 23:56:49.108210 MD32_EN : 0
3851 23:56:49.108263 ===================================
3852 23:56:49.108316 [ANA_INIT] >>>>>>>>>>>>>>
3853 23:56:49.108369 <<<<<< [CONFIGURE PHASE]: ANA_TX
3854 23:56:49.108421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3855 23:56:49.108474 ===================================
3856 23:56:49.108527 data_rate = 1200,PCW = 0X5800
3857 23:56:49.108579 ===================================
3858 23:56:49.108822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3859 23:56:49.108882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 23:56:49.108936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 23:56:49.108989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3862 23:56:49.109042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3863 23:56:49.109095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3864 23:56:49.109148 [ANA_INIT] flow start
3865 23:56:49.109202 [ANA_INIT] PLL >>>>>>>>
3866 23:56:49.109255 [ANA_INIT] PLL <<<<<<<<
3867 23:56:49.109352 [ANA_INIT] MIDPI >>>>>>>>
3868 23:56:49.109404 [ANA_INIT] MIDPI <<<<<<<<
3869 23:56:49.109457 [ANA_INIT] DLL >>>>>>>>
3870 23:56:49.109509 [ANA_INIT] flow end
3871 23:56:49.109561 ============ LP4 DIFF to SE enter ============
3872 23:56:49.109615 ============ LP4 DIFF to SE exit ============
3873 23:56:49.109668 [ANA_INIT] <<<<<<<<<<<<<
3874 23:56:49.109721 [Flow] Enable top DCM control >>>>>
3875 23:56:49.109774 [Flow] Enable top DCM control <<<<<
3876 23:56:49.109827 Enable DLL master slave shuffle
3877 23:56:49.109880 ==============================================================
3878 23:56:49.109933 Gating Mode config
3879 23:56:49.109985 ==============================================================
3880 23:56:49.110038 Config description:
3881 23:56:49.110091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3882 23:56:49.110145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3883 23:56:49.110199 SELPH_MODE 0: By rank 1: By Phase
3884 23:56:49.110253 ==============================================================
3885 23:56:49.110307 GAT_TRACK_EN = 1
3886 23:56:49.110359 RX_GATING_MODE = 2
3887 23:56:49.110412 RX_GATING_TRACK_MODE = 2
3888 23:56:49.110465 SELPH_MODE = 1
3889 23:56:49.110518 PICG_EARLY_EN = 1
3890 23:56:49.110570 VALID_LAT_VALUE = 1
3891 23:56:49.110623 ==============================================================
3892 23:56:49.110676 Enter into Gating configuration >>>>
3893 23:56:49.110729 Exit from Gating configuration <<<<
3894 23:56:49.110781 Enter into DVFS_PRE_config >>>>>
3895 23:56:49.110834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3896 23:56:49.110889 Exit from DVFS_PRE_config <<<<<
3897 23:56:49.110942 Enter into PICG configuration >>>>
3898 23:56:49.110995 Exit from PICG configuration <<<<
3899 23:56:49.111047 [RX_INPUT] configuration >>>>>
3900 23:56:49.111099 [RX_INPUT] configuration <<<<<
3901 23:56:49.111151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3902 23:56:49.111205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3903 23:56:49.111257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 23:56:49.111310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 23:56:49.111363 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 23:56:49.111416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 23:56:49.111469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3908 23:56:49.111522 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3909 23:56:49.111574 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3910 23:56:49.111627 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3911 23:56:49.111680 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3912 23:56:49.111733 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 23:56:49.111786 ===================================
3914 23:56:49.111839 LPDDR4 DRAM CONFIGURATION
3915 23:56:49.111891 ===================================
3916 23:56:49.111944 EX_ROW_EN[0] = 0x0
3917 23:56:49.111998 EX_ROW_EN[1] = 0x0
3918 23:56:49.112051 LP4Y_EN = 0x0
3919 23:56:49.112103 WORK_FSP = 0x0
3920 23:56:49.112155 WL = 0x2
3921 23:56:49.112208 RL = 0x2
3922 23:56:49.112260 BL = 0x2
3923 23:56:49.112312 RPST = 0x0
3924 23:56:49.112364 RD_PRE = 0x0
3925 23:56:49.112416 WR_PRE = 0x1
3926 23:56:49.112469 WR_PST = 0x0
3927 23:56:49.112521 DBI_WR = 0x0
3928 23:56:49.112572 DBI_RD = 0x0
3929 23:56:49.112624 OTF = 0x1
3930 23:56:49.112677 ===================================
3931 23:56:49.112730 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3932 23:56:49.112784 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3933 23:56:49.112837 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 23:56:49.112890 ===================================
3935 23:56:49.112943 LPDDR4 DRAM CONFIGURATION
3936 23:56:49.112996 ===================================
3937 23:56:49.113049 EX_ROW_EN[0] = 0x10
3938 23:56:49.113101 EX_ROW_EN[1] = 0x0
3939 23:56:49.113153 LP4Y_EN = 0x0
3940 23:56:49.113206 WORK_FSP = 0x0
3941 23:56:49.113267 WL = 0x2
3942 23:56:49.113353 RL = 0x2
3943 23:56:49.113405 BL = 0x2
3944 23:56:49.113457 RPST = 0x0
3945 23:56:49.113509 RD_PRE = 0x0
3946 23:56:49.113561 WR_PRE = 0x1
3947 23:56:49.113613 WR_PST = 0x0
3948 23:56:49.113665 DBI_WR = 0x0
3949 23:56:49.113717 DBI_RD = 0x0
3950 23:56:49.113769 OTF = 0x1
3951 23:56:49.113822 ===================================
3952 23:56:49.113888 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3953 23:56:49.113944 nWR fixed to 30
3954 23:56:49.117202 [ModeRegInit_LP4] CH0 RK0
3955 23:56:49.117471 [ModeRegInit_LP4] CH0 RK1
3956 23:56:49.120220 [ModeRegInit_LP4] CH1 RK0
3957 23:56:49.123594 [ModeRegInit_LP4] CH1 RK1
3958 23:56:49.123833 match AC timing 17
3959 23:56:49.130767 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3960 23:56:49.133603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3961 23:56:49.136520 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3962 23:56:49.143317 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3963 23:56:49.146572 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3964 23:56:49.146765 ==
3965 23:56:49.150038 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 23:56:49.153552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 23:56:49.153634 ==
3968 23:56:49.159664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 23:56:49.166446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3970 23:56:49.169654 [CA 0] Center 36 (6~67) winsize 62
3971 23:56:49.173233 [CA 1] Center 36 (6~67) winsize 62
3972 23:56:49.176389 [CA 2] Center 34 (3~65) winsize 63
3973 23:56:49.179903 [CA 3] Center 34 (4~65) winsize 62
3974 23:56:49.183269 [CA 4] Center 33 (3~64) winsize 62
3975 23:56:49.186776 [CA 5] Center 33 (2~64) winsize 63
3976 23:56:49.187268
3977 23:56:49.189551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3978 23:56:49.189971
3979 23:56:49.193186 [CATrainingPosCal] consider 1 rank data
3980 23:56:49.196542 u2DelayCellTimex100 = 270/100 ps
3981 23:56:49.199984 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3982 23:56:49.203183 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3983 23:56:49.206352 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3984 23:56:49.212733 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3985 23:56:49.216191 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 23:56:49.219282 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3987 23:56:49.219703
3988 23:56:49.223124 CA PerBit enable=1, Macro0, CA PI delay=33
3989 23:56:49.223543
3990 23:56:49.226607 [CBTSetCACLKResult] CA Dly = 33
3991 23:56:49.227255 CS Dly: 5 (0~36)
3992 23:56:49.227645 ==
3993 23:56:49.229428 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 23:56:49.236091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 23:56:49.236510 ==
3996 23:56:49.239191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 23:56:49.245784 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3998 23:56:49.249305 [CA 0] Center 36 (6~67) winsize 62
3999 23:56:49.252383 [CA 1] Center 36 (6~67) winsize 62
4000 23:56:49.256371 [CA 2] Center 34 (4~65) winsize 62
4001 23:56:49.259063 [CA 3] Center 34 (4~65) winsize 62
4002 23:56:49.262315 [CA 4] Center 33 (3~64) winsize 62
4003 23:56:49.265636 [CA 5] Center 33 (3~64) winsize 62
4004 23:56:49.266057
4005 23:56:49.269171 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4006 23:56:49.269644
4007 23:56:49.272419 [CATrainingPosCal] consider 2 rank data
4008 23:56:49.275446 u2DelayCellTimex100 = 270/100 ps
4009 23:56:49.278882 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4010 23:56:49.285315 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4011 23:56:49.288780 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4012 23:56:49.291949 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4013 23:56:49.295383 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4014 23:56:49.298702 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4015 23:56:49.298931
4016 23:56:49.301770 CA PerBit enable=1, Macro0, CA PI delay=33
4017 23:56:49.302000
4018 23:56:49.305041 [CBTSetCACLKResult] CA Dly = 33
4019 23:56:49.308457 CS Dly: 6 (0~38)
4020 23:56:49.308734
4021 23:56:49.311896 ----->DramcWriteLeveling(PI) begin...
4022 23:56:49.312264 ==
4023 23:56:49.315510 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 23:56:49.318378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 23:56:49.318810 ==
4026 23:56:49.321953 Write leveling (Byte 0): 32 => 32
4027 23:56:49.325097 Write leveling (Byte 1): 28 => 28
4028 23:56:49.328922 DramcWriteLeveling(PI) end<-----
4029 23:56:49.329383
4030 23:56:49.329726 ==
4031 23:56:49.332005 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 23:56:49.335113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 23:56:49.335550 ==
4034 23:56:49.338541 [Gating] SW mode calibration
4035 23:56:49.345109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4036 23:56:49.351537 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4037 23:56:49.355057 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 23:56:49.358568 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 23:56:49.364732 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 23:56:49.368297 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4041 23:56:49.371503 0 9 16 | B1->B0 | 2525 2727 | 0 0 | (1 1) (0 0)
4042 23:56:49.377999 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 23:56:49.381738 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 23:56:49.384418 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 23:56:49.391106 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 23:56:49.394213 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 23:56:49.398020 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 23:56:49.404236 0 10 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4049 23:56:49.407609 0 10 16 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
4050 23:56:49.410848 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:56:49.417561 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:56:49.421129 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 23:56:49.424047 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 23:56:49.431157 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 23:56:49.433706 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 23:56:49.437242 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 23:56:49.443949 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4058 23:56:49.447024 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:56:49.450407 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:56:49.457123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:56:49.460149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:56:49.463489 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:56:49.470088 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:56:49.473695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:56:49.476881 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:56:49.483647 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:56:49.486588 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:56:49.489894 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:56:49.496799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:56:49.499618 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:56:49.503460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:56:49.509956 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4073 23:56:49.513193 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4074 23:56:49.517143 Total UI for P1: 0, mck2ui 16
4075 23:56:49.519879 best dqsien dly found for B0: ( 0, 13, 12)
4076 23:56:49.523146 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 23:56:49.526525 Total UI for P1: 0, mck2ui 16
4078 23:56:49.529570 best dqsien dly found for B1: ( 0, 13, 18)
4079 23:56:49.533218 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4080 23:56:49.539393 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4081 23:56:49.539797
4082 23:56:49.542510 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4083 23:56:49.545768 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4084 23:56:49.549371 [Gating] SW calibration Done
4085 23:56:49.549453 ==
4086 23:56:49.551989 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 23:56:49.555687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 23:56:49.555769 ==
4089 23:56:49.559056 RX Vref Scan: 0
4090 23:56:49.559137
4091 23:56:49.559202 RX Vref 0 -> 0, step: 1
4092 23:56:49.559262
4093 23:56:49.561834 RX Delay -230 -> 252, step: 16
4094 23:56:49.565753 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4095 23:56:49.572404 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4096 23:56:49.575437 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4097 23:56:49.578853 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4098 23:56:49.582508 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4099 23:56:49.588846 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4100 23:56:49.591871 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4101 23:56:49.595158 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4102 23:56:49.598504 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4103 23:56:49.605066 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4104 23:56:49.608557 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4105 23:56:49.611527 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4106 23:56:49.615026 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4107 23:56:49.621466 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4108 23:56:49.625069 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4109 23:56:49.628267 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4110 23:56:49.628908 ==
4111 23:56:49.631771 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 23:56:49.634869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 23:56:49.637782 ==
4114 23:56:49.638151 DQS Delay:
4115 23:56:49.638510 DQS0 = 0, DQS1 = 0
4116 23:56:49.641600 DQM Delay:
4117 23:56:49.642050 DQM0 = 40, DQM1 = 32
4118 23:56:49.644322 DQ Delay:
4119 23:56:49.644825 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4120 23:56:49.647652 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4121 23:56:49.651300 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4122 23:56:49.654276 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4123 23:56:49.658122
4124 23:56:49.658677
4125 23:56:49.659113 ==
4126 23:56:49.660989 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 23:56:49.664247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 23:56:49.664788 ==
4129 23:56:49.665223
4130 23:56:49.665686
4131 23:56:49.667570 TX Vref Scan disable
4132 23:56:49.668000 == TX Byte 0 ==
4133 23:56:49.674146 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4134 23:56:49.677421 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4135 23:56:49.677855 == TX Byte 1 ==
4136 23:56:49.684205 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4137 23:56:49.687349 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4138 23:56:49.688065 ==
4139 23:56:49.690731 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 23:56:49.693608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 23:56:49.694154 ==
4142 23:56:49.694673
4143 23:56:49.696858
4144 23:56:49.697218 TX Vref Scan disable
4145 23:56:49.700386 == TX Byte 0 ==
4146 23:56:49.703623 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4147 23:56:49.710558 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4148 23:56:49.710759 == TX Byte 1 ==
4149 23:56:49.713616 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4150 23:56:49.720145 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4151 23:56:49.720286
4152 23:56:49.720371 [DATLAT]
4153 23:56:49.720447 Freq=600, CH0 RK0
4154 23:56:49.720520
4155 23:56:49.723838 DATLAT Default: 0x9
4156 23:56:49.723997 0, 0xFFFF, sum = 0
4157 23:56:49.727045 1, 0xFFFF, sum = 0
4158 23:56:49.730086 2, 0xFFFF, sum = 0
4159 23:56:49.730223 3, 0xFFFF, sum = 0
4160 23:56:49.733417 4, 0xFFFF, sum = 0
4161 23:56:49.733554 5, 0xFFFF, sum = 0
4162 23:56:49.736411 6, 0xFFFF, sum = 0
4163 23:56:49.736510 7, 0xFFFF, sum = 0
4164 23:56:49.739926 8, 0x0, sum = 1
4165 23:56:49.740076 9, 0x0, sum = 2
4166 23:56:49.743145 10, 0x0, sum = 3
4167 23:56:49.743299 11, 0x0, sum = 4
4168 23:56:49.743470 best_step = 9
4169 23:56:49.743615
4170 23:56:49.746370 ==
4171 23:56:49.746503 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 23:56:49.753029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 23:56:49.753163 ==
4174 23:56:49.753286 RX Vref Scan: 1
4175 23:56:49.753365
4176 23:56:49.756111 RX Vref 0 -> 0, step: 1
4177 23:56:49.756244
4178 23:56:49.759331 RX Delay -195 -> 252, step: 8
4179 23:56:49.759465
4180 23:56:49.763367 Set Vref, RX VrefLevel [Byte0]: 54
4181 23:56:49.766263 [Byte1]: 59
4182 23:56:49.766405
4183 23:56:49.770010 Final RX Vref Byte 0 = 54 to rank0
4184 23:56:49.773024 Final RX Vref Byte 1 = 59 to rank0
4185 23:56:49.776634 Final RX Vref Byte 0 = 54 to rank1
4186 23:56:49.780162 Final RX Vref Byte 1 = 59 to rank1==
4187 23:56:49.782636 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 23:56:49.789470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 23:56:49.789580 ==
4190 23:56:49.789662 DQS Delay:
4191 23:56:49.789737 DQS0 = 0, DQS1 = 0
4192 23:56:49.792552 DQM Delay:
4193 23:56:49.792653 DQM0 = 40, DQM1 = 32
4194 23:56:49.796128 DQ Delay:
4195 23:56:49.799441 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4196 23:56:49.802366 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4197 23:56:49.805927 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4198 23:56:49.808840 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4199 23:56:49.808935
4200 23:56:49.809017
4201 23:56:49.815879 [DQSOSCAuto] RK0, (LSB)MR18= 0x5249, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4202 23:56:49.818992 CH0 RK0: MR19=808, MR18=5249
4203 23:56:49.825408 CH0_RK0: MR19=0x808, MR18=0x5249, DQSOSC=394, MR23=63, INC=168, DEC=112
4204 23:56:49.825513
4205 23:56:49.829114 ----->DramcWriteLeveling(PI) begin...
4206 23:56:49.829293 ==
4207 23:56:49.832449 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 23:56:49.835299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 23:56:49.835415 ==
4210 23:56:49.839216 Write leveling (Byte 0): 32 => 32
4211 23:56:49.841895 Write leveling (Byte 1): 29 => 29
4212 23:56:49.845513 DramcWriteLeveling(PI) end<-----
4213 23:56:49.845647
4214 23:56:49.845759 ==
4215 23:56:49.848693 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 23:56:49.851773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 23:56:49.855034 ==
4218 23:56:49.855210 [Gating] SW mode calibration
4219 23:56:49.865704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4220 23:56:49.868632 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4221 23:56:49.871765 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 23:56:49.878326 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 23:56:49.881720 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 23:56:49.884883 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4225 23:56:49.891172 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
4226 23:56:49.894644 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 23:56:49.897706 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 23:56:49.904421 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 23:56:49.907780 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 23:56:49.910931 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 23:56:49.917806 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 23:56:49.921236 0 10 12 | B1->B0 | 2727 3232 | 0 1 | (0 0) (1 1)
4233 23:56:49.924109 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4234 23:56:49.930785 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:56:49.934098 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:56:49.937813 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:56:49.944817 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 23:56:49.947894 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 23:56:49.950839 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 23:56:49.957135 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 23:56:49.960910 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:56:49.963893 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:56:49.970845 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:56:49.973838 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:56:49.977748 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:56:49.983989 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:56:49.986983 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:56:49.990325 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:56:49.996933 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:56:49.999767 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:56:50.003749 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:56:50.010174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:56:50.013467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:56:50.019548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:56:50.023331 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4256 23:56:50.026340 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4257 23:56:50.029669 Total UI for P1: 0, mck2ui 16
4258 23:56:50.033251 best dqsien dly found for B0: ( 0, 13, 8)
4259 23:56:50.036275 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4260 23:56:50.042826 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 23:56:50.046331 Total UI for P1: 0, mck2ui 16
4262 23:56:50.049382 best dqsien dly found for B1: ( 0, 13, 16)
4263 23:56:50.052795 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4264 23:56:50.056324 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4265 23:56:50.056749
4266 23:56:50.059865 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4267 23:56:50.062602 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4268 23:56:50.065675 [Gating] SW calibration Done
4269 23:56:50.066098 ==
4270 23:56:50.069138 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 23:56:50.072860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 23:56:50.073325 ==
4273 23:56:50.075517 RX Vref Scan: 0
4274 23:56:50.075934
4275 23:56:50.079021 RX Vref 0 -> 0, step: 1
4276 23:56:50.079444
4277 23:56:50.082139 RX Delay -230 -> 252, step: 16
4278 23:56:50.086000 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4279 23:56:50.088862 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4280 23:56:50.092150 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4281 23:56:50.098496 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4282 23:56:50.101906 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4283 23:56:50.105244 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4284 23:56:50.108560 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4285 23:56:50.111660 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4286 23:56:50.118768 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4287 23:56:50.121894 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4288 23:56:50.125089 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4289 23:56:50.128205 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4290 23:56:50.134816 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4291 23:56:50.138342 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4292 23:56:50.141835 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4293 23:56:50.145025 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4294 23:56:50.148334 ==
4295 23:56:50.151537 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 23:56:50.154789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 23:56:50.155239 ==
4298 23:56:50.155580 DQS Delay:
4299 23:56:50.157883 DQS0 = 0, DQS1 = 0
4300 23:56:50.158306 DQM Delay:
4301 23:56:50.162030 DQM0 = 43, DQM1 = 34
4302 23:56:50.162453 DQ Delay:
4303 23:56:50.164473 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4304 23:56:50.168048 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4305 23:56:50.171359 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4306 23:56:50.174882 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4307 23:56:50.175320
4308 23:56:50.175655
4309 23:56:50.176009 ==
4310 23:56:50.178001 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 23:56:50.180781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 23:56:50.181418 ==
4313 23:56:50.181769
4314 23:56:50.182088
4315 23:56:50.185205 TX Vref Scan disable
4316 23:56:50.187899 == TX Byte 0 ==
4317 23:56:50.191215 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4318 23:56:50.194491 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4319 23:56:50.197627 == TX Byte 1 ==
4320 23:56:50.200944 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4321 23:56:50.204570 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4322 23:56:50.204997 ==
4323 23:56:50.208052 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 23:56:50.213747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 23:56:50.214189 ==
4326 23:56:50.214522
4327 23:56:50.214832
4328 23:56:50.215129 TX Vref Scan disable
4329 23:56:50.219276 == TX Byte 0 ==
4330 23:56:50.221913 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4331 23:56:50.228242 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4332 23:56:50.228693 == TX Byte 1 ==
4333 23:56:50.231605 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4334 23:56:50.238107 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4335 23:56:50.238535
4336 23:56:50.238866 [DATLAT]
4337 23:56:50.239169 Freq=600, CH0 RK1
4338 23:56:50.239467
4339 23:56:50.241481 DATLAT Default: 0x9
4340 23:56:50.244795 0, 0xFFFF, sum = 0
4341 23:56:50.245223 1, 0xFFFF, sum = 0
4342 23:56:50.248185 2, 0xFFFF, sum = 0
4343 23:56:50.248611 3, 0xFFFF, sum = 0
4344 23:56:50.251850 4, 0xFFFF, sum = 0
4345 23:56:50.252277 5, 0xFFFF, sum = 0
4346 23:56:50.254834 6, 0xFFFF, sum = 0
4347 23:56:50.255262 7, 0xFFFF, sum = 0
4348 23:56:50.258239 8, 0x0, sum = 1
4349 23:56:50.258666 9, 0x0, sum = 2
4350 23:56:50.262069 10, 0x0, sum = 3
4351 23:56:50.262495 11, 0x0, sum = 4
4352 23:56:50.262836 best_step = 9
4353 23:56:50.263145
4354 23:56:50.264897 ==
4355 23:56:50.268334 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 23:56:50.271925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 23:56:50.272349 ==
4358 23:56:50.272682 RX Vref Scan: 0
4359 23:56:50.272993
4360 23:56:50.274485 RX Vref 0 -> 0, step: 1
4361 23:56:50.274906
4362 23:56:50.277861 RX Delay -179 -> 252, step: 8
4363 23:56:50.284203 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4364 23:56:50.287543 iDelay=197, Bit 1, Center 40 (-115 ~ 196) 312
4365 23:56:50.290927 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4366 23:56:50.294281 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4367 23:56:50.297496 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4368 23:56:50.304180 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4369 23:56:50.307460 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4370 23:56:50.310774 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4371 23:56:50.314299 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4372 23:56:50.320638 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4373 23:56:50.324050 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4374 23:56:50.327549 iDelay=197, Bit 11, Center 24 (-131 ~ 180) 312
4375 23:56:50.330410 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4376 23:56:50.337391 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4377 23:56:50.340664 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4378 23:56:50.343948 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4379 23:56:50.344390 ==
4380 23:56:50.347322 Dram Type= 6, Freq= 0, CH_0, rank 1
4381 23:56:50.350309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 23:56:50.353783 ==
4383 23:56:50.354238 DQS Delay:
4384 23:56:50.354572 DQS0 = 0, DQS1 = 0
4385 23:56:50.356818 DQM Delay:
4386 23:56:50.357237 DQM0 = 39, DQM1 = 32
4387 23:56:50.359998 DQ Delay:
4388 23:56:50.360079 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4389 23:56:50.363198 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4390 23:56:50.366991 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4391 23:56:50.370117 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4392 23:56:50.373430
4393 23:56:50.373579
4394 23:56:50.379912 [DQSOSCAuto] RK1, (LSB)MR18= 0x4540, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4395 23:56:50.383350 CH0 RK1: MR19=808, MR18=4540
4396 23:56:50.389491 CH0_RK1: MR19=0x808, MR18=0x4540, DQSOSC=396, MR23=63, INC=167, DEC=111
4397 23:56:50.392664 [RxdqsGatingPostProcess] freq 600
4398 23:56:50.396101 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4399 23:56:50.399750 Pre-setting of DQS Precalculation
4400 23:56:50.406713 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4401 23:56:50.406915 ==
4402 23:56:50.409422 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 23:56:50.412999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 23:56:50.413241 ==
4405 23:56:50.419072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4406 23:56:50.422465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4407 23:56:50.427606 [CA 0] Center 35 (5~66) winsize 62
4408 23:56:50.430443 [CA 1] Center 35 (5~66) winsize 62
4409 23:56:50.433810 [CA 2] Center 34 (4~65) winsize 62
4410 23:56:50.437374 [CA 3] Center 34 (4~65) winsize 62
4411 23:56:50.440839 [CA 4] Center 34 (4~65) winsize 62
4412 23:56:50.443456 [CA 5] Center 34 (3~65) winsize 63
4413 23:56:50.443538
4414 23:56:50.447558 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4415 23:56:50.447640
4416 23:56:50.450765 [CATrainingPosCal] consider 1 rank data
4417 23:56:50.454216 u2DelayCellTimex100 = 270/100 ps
4418 23:56:50.456991 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4419 23:56:50.463845 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4420 23:56:50.466687 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 23:56:50.470307 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4422 23:56:50.474347 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 23:56:50.476942 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4424 23:56:50.477393
4425 23:56:50.480063 CA PerBit enable=1, Macro0, CA PI delay=34
4426 23:56:50.480490
4427 23:56:50.483389 [CBTSetCACLKResult] CA Dly = 34
4428 23:56:50.483824 CS Dly: 4 (0~35)
4429 23:56:50.486670 ==
4430 23:56:50.490355 Dram Type= 6, Freq= 0, CH_1, rank 1
4431 23:56:50.493309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 23:56:50.493740 ==
4433 23:56:50.500080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4434 23:56:50.503027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4435 23:56:50.507200 [CA 0] Center 35 (5~66) winsize 62
4436 23:56:50.510217 [CA 1] Center 35 (5~66) winsize 62
4437 23:56:50.513673 [CA 2] Center 34 (4~65) winsize 62
4438 23:56:50.516720 [CA 3] Center 34 (3~65) winsize 63
4439 23:56:50.520246 [CA 4] Center 34 (4~65) winsize 62
4440 23:56:50.523361 [CA 5] Center 34 (3~65) winsize 63
4441 23:56:50.523473
4442 23:56:50.526811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4443 23:56:50.526884
4444 23:56:50.530069 [CATrainingPosCal] consider 2 rank data
4445 23:56:50.533458 u2DelayCellTimex100 = 270/100 ps
4446 23:56:50.537219 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4447 23:56:50.543255 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4448 23:56:50.546659 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 23:56:50.549656 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4450 23:56:50.553220 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4451 23:56:50.556527 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4452 23:56:50.556606
4453 23:56:50.559623 CA PerBit enable=1, Macro0, CA PI delay=34
4454 23:56:50.559692
4455 23:56:50.563628 [CBTSetCACLKResult] CA Dly = 34
4456 23:56:50.563717 CS Dly: 5 (0~37)
4457 23:56:50.566184
4458 23:56:50.569675 ----->DramcWriteLeveling(PI) begin...
4459 23:56:50.569773 ==
4460 23:56:50.572741 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 23:56:50.576388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 23:56:50.576491 ==
4463 23:56:50.579925 Write leveling (Byte 0): 28 => 28
4464 23:56:50.582794 Write leveling (Byte 1): 31 => 31
4465 23:56:50.586581 DramcWriteLeveling(PI) end<-----
4466 23:56:50.586726
4467 23:56:50.586826 ==
4468 23:56:50.589395 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 23:56:50.592673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 23:56:50.592793 ==
4471 23:56:50.596179 [Gating] SW mode calibration
4472 23:56:50.602775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4473 23:56:50.609612 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4474 23:56:50.613055 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 23:56:50.616069 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 23:56:50.622805 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 23:56:50.625939 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (1 1)
4478 23:56:50.629107 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 23:56:50.635549 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 23:56:50.638738 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 23:56:50.642164 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 23:56:50.649221 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 23:56:50.652426 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 23:56:50.655725 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4485 23:56:50.662041 0 10 12 | B1->B0 | 3131 3535 | 0 0 | (1 1) (0 0)
4486 23:56:50.665386 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:56:50.668630 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 23:56:50.675378 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 23:56:50.678655 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 23:56:50.681788 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 23:56:50.689039 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 23:56:50.692242 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 23:56:50.696130 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4494 23:56:50.702578 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:56:50.705702 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:56:50.708873 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:56:50.715229 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:56:50.718504 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:56:50.721739 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:56:50.728669 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:56:50.732034 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:56:50.734704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:56:50.741541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:56:50.744859 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:56:50.748172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:56:50.754601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:56:50.757968 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:56:50.761362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:56:50.768222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 23:56:50.768639 Total UI for P1: 0, mck2ui 16
4511 23:56:50.774743 best dqsien dly found for B0: ( 0, 13, 10)
4512 23:56:50.775159 Total UI for P1: 0, mck2ui 16
4513 23:56:50.780644 best dqsien dly found for B1: ( 0, 13, 10)
4514 23:56:50.784545 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4515 23:56:50.787468 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4516 23:56:50.787902
4517 23:56:50.791471 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4518 23:56:50.794480 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4519 23:56:50.797855 [Gating] SW calibration Done
4520 23:56:50.798284 ==
4521 23:56:50.800883 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 23:56:50.804282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 23:56:50.804714 ==
4524 23:56:50.807249 RX Vref Scan: 0
4525 23:56:50.807674
4526 23:56:50.810624 RX Vref 0 -> 0, step: 1
4527 23:56:50.811050
4528 23:56:50.811477 RX Delay -230 -> 252, step: 16
4529 23:56:50.817614 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4530 23:56:50.820448 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4531 23:56:50.823673 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4532 23:56:50.827133 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4533 23:56:50.833981 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4534 23:56:50.837685 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4535 23:56:50.840708 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4536 23:56:50.843771 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4537 23:56:50.847420 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4538 23:56:50.853668 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4539 23:56:50.857130 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4540 23:56:50.859909 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4541 23:56:50.863557 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4542 23:56:50.869889 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4543 23:56:50.873535 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4544 23:56:50.877103 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4545 23:56:50.877609 ==
4546 23:56:50.880053 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 23:56:50.886554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 23:56:50.886980 ==
4549 23:56:50.887318 DQS Delay:
4550 23:56:50.889928 DQS0 = 0, DQS1 = 0
4551 23:56:50.890349 DQM Delay:
4552 23:56:50.890689 DQM0 = 41, DQM1 = 38
4553 23:56:50.893077 DQ Delay:
4554 23:56:50.896790 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4555 23:56:50.899358 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4556 23:56:50.902533 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4557 23:56:50.906032 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4558 23:56:50.906546
4559 23:56:50.906887
4560 23:56:50.907193 ==
4561 23:56:50.909536 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 23:56:50.913128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 23:56:50.913611 ==
4564 23:56:50.913948
4565 23:56:50.914260
4566 23:56:50.916899 TX Vref Scan disable
4567 23:56:50.919937 == TX Byte 0 ==
4568 23:56:50.922478 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4569 23:56:50.925802 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4570 23:56:50.929180 == TX Byte 1 ==
4571 23:56:50.932821 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4572 23:56:50.936022 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4573 23:56:50.936448 ==
4574 23:56:50.939082 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 23:56:50.942804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 23:56:50.945398 ==
4577 23:56:50.945820
4578 23:56:50.946154
4579 23:56:50.946465 TX Vref Scan disable
4580 23:56:50.950015 == TX Byte 0 ==
4581 23:56:50.953144 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4582 23:56:50.959400 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4583 23:56:50.959834 == TX Byte 1 ==
4584 23:56:50.962811 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4585 23:56:50.969382 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4586 23:56:50.969810
4587 23:56:50.970145 [DATLAT]
4588 23:56:50.970542 Freq=600, CH1 RK0
4589 23:56:50.970912
4590 23:56:50.972485 DATLAT Default: 0x9
4591 23:56:50.975729 0, 0xFFFF, sum = 0
4592 23:56:50.976177 1, 0xFFFF, sum = 0
4593 23:56:50.979682 2, 0xFFFF, sum = 0
4594 23:56:50.980108 3, 0xFFFF, sum = 0
4595 23:56:50.982651 4, 0xFFFF, sum = 0
4596 23:56:50.983078 5, 0xFFFF, sum = 0
4597 23:56:50.986432 6, 0xFFFF, sum = 0
4598 23:56:50.986923 7, 0xFFFF, sum = 0
4599 23:56:50.989419 8, 0x0, sum = 1
4600 23:56:50.989849 9, 0x0, sum = 2
4601 23:56:50.992935 10, 0x0, sum = 3
4602 23:56:50.993402 11, 0x0, sum = 4
4603 23:56:50.993750 best_step = 9
4604 23:56:50.994065
4605 23:56:50.995946 ==
4606 23:56:50.999071 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 23:56:51.002745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 23:56:51.003163 ==
4609 23:56:51.003491 RX Vref Scan: 1
4610 23:56:51.003798
4611 23:56:51.005855 RX Vref 0 -> 0, step: 1
4612 23:56:51.006304
4613 23:56:51.008999 RX Delay -179 -> 252, step: 8
4614 23:56:51.009523
4615 23:56:51.012440 Set Vref, RX VrefLevel [Byte0]: 53
4616 23:56:51.015409 [Byte1]: 52
4617 23:56:51.015825
4618 23:56:51.019419 Final RX Vref Byte 0 = 53 to rank0
4619 23:56:51.022150 Final RX Vref Byte 1 = 52 to rank0
4620 23:56:51.025528 Final RX Vref Byte 0 = 53 to rank1
4621 23:56:51.028990 Final RX Vref Byte 1 = 52 to rank1==
4622 23:56:51.031990 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 23:56:51.035257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 23:56:51.038719 ==
4625 23:56:51.039261 DQS Delay:
4626 23:56:51.039616 DQS0 = 0, DQS1 = 0
4627 23:56:51.042252 DQM Delay:
4628 23:56:51.042662 DQM0 = 41, DQM1 = 33
4629 23:56:51.045228 DQ Delay:
4630 23:56:51.048730 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4631 23:56:51.051812 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4632 23:56:51.055661 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4633 23:56:51.057904 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4634 23:56:51.058294
4635 23:56:51.058631
4636 23:56:51.064907 [DQSOSCAuto] RK0, (LSB)MR18= 0x344d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4637 23:56:51.067960 CH1 RK0: MR19=808, MR18=344D
4638 23:56:51.074799 CH1_RK0: MR19=0x808, MR18=0x344D, DQSOSC=395, MR23=63, INC=168, DEC=112
4639 23:56:51.075244
4640 23:56:51.077808 ----->DramcWriteLeveling(PI) begin...
4641 23:56:51.078226 ==
4642 23:56:51.081517 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 23:56:51.084932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 23:56:51.085388 ==
4645 23:56:51.087946 Write leveling (Byte 0): 29 => 29
4646 23:56:51.091575 Write leveling (Byte 1): 30 => 30
4647 23:56:51.094484 DramcWriteLeveling(PI) end<-----
4648 23:56:51.094899
4649 23:56:51.095227 ==
4650 23:56:51.097886 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 23:56:51.101038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 23:56:51.104965 ==
4653 23:56:51.105433 [Gating] SW mode calibration
4654 23:56:51.114116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4655 23:56:51.117615 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4656 23:56:51.120918 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 23:56:51.127524 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 23:56:51.131037 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 23:56:51.134031 0 9 12 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
4660 23:56:51.140510 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 23:56:51.143627 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 23:56:51.146952 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 23:56:51.153722 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 23:56:51.157342 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 23:56:51.160828 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 23:56:51.166861 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 23:56:51.170215 0 10 12 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
4668 23:56:51.173791 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:56:51.180566 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:56:51.184139 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 23:56:51.187255 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 23:56:51.193627 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 23:56:51.196845 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 23:56:51.199953 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 23:56:51.206778 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4676 23:56:51.210524 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:56:51.213234 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:56:51.219733 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:56:51.223197 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:56:51.226557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:56:51.233620 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:56:51.236126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:56:51.239975 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:56:51.246480 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:56:51.249539 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:56:51.252944 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:56:51.259259 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:56:51.263005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:56:51.266127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:56:51.273452 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:56:51.276034 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 23:56:51.279078 Total UI for P1: 0, mck2ui 16
4693 23:56:51.282647 best dqsien dly found for B0: ( 0, 13, 10)
4694 23:56:51.285389 Total UI for P1: 0, mck2ui 16
4695 23:56:51.288903 best dqsien dly found for B1: ( 0, 13, 10)
4696 23:56:51.292101 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4697 23:56:51.295802 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4698 23:56:51.296230
4699 23:56:51.299404 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4700 23:56:51.305976 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 23:56:51.306405 [Gating] SW calibration Done
4702 23:56:51.306843 ==
4703 23:56:51.308436 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 23:56:51.315132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 23:56:51.315644 ==
4706 23:56:51.316085 RX Vref Scan: 0
4707 23:56:51.316491
4708 23:56:51.318487 RX Vref 0 -> 0, step: 1
4709 23:56:51.318915
4710 23:56:51.322585 RX Delay -230 -> 252, step: 16
4711 23:56:51.325083 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4712 23:56:51.329001 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4713 23:56:51.335047 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4714 23:56:51.338123 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4715 23:56:51.341823 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4716 23:56:51.344856 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4717 23:56:51.348377 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4718 23:56:51.354833 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4719 23:56:51.358534 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4720 23:56:51.361824 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4721 23:56:51.364713 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4722 23:56:51.371196 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4723 23:56:51.374240 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4724 23:56:51.377672 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4725 23:56:51.381127 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4726 23:56:51.387658 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4727 23:56:51.388096 ==
4728 23:56:51.391302 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 23:56:51.394106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 23:56:51.394524 ==
4731 23:56:51.394852 DQS Delay:
4732 23:56:51.397316 DQS0 = 0, DQS1 = 0
4733 23:56:51.397791 DQM Delay:
4734 23:56:51.400585 DQM0 = 39, DQM1 = 39
4735 23:56:51.401017 DQ Delay:
4736 23:56:51.404052 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4737 23:56:51.407284 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4738 23:56:51.410561 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4739 23:56:51.414114 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4740 23:56:51.414558
4741 23:56:51.414994
4742 23:56:51.415404 ==
4743 23:56:51.417516 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 23:56:51.420815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 23:56:51.423678 ==
4746 23:56:51.424107
4747 23:56:51.424641
4748 23:56:51.425052 TX Vref Scan disable
4749 23:56:51.427570 == TX Byte 0 ==
4750 23:56:51.430872 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4751 23:56:51.437168 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4752 23:56:51.437660 == TX Byte 1 ==
4753 23:56:51.440103 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4754 23:56:51.447075 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4755 23:56:51.447505 ==
4756 23:56:51.450382 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 23:56:51.453247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 23:56:51.453719 ==
4759 23:56:51.454148
4760 23:56:51.454552
4761 23:56:51.457030 TX Vref Scan disable
4762 23:56:51.460180 == TX Byte 0 ==
4763 23:56:51.463485 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4764 23:56:51.466380 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4765 23:56:51.470191 == TX Byte 1 ==
4766 23:56:51.473424 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4767 23:56:51.476488 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4768 23:56:51.476917
4769 23:56:51.479678 [DATLAT]
4770 23:56:51.480106 Freq=600, CH1 RK1
4771 23:56:51.480537
4772 23:56:51.483070 DATLAT Default: 0x9
4773 23:56:51.483498 0, 0xFFFF, sum = 0
4774 23:56:51.486283 1, 0xFFFF, sum = 0
4775 23:56:51.486799 2, 0xFFFF, sum = 0
4776 23:56:51.490037 3, 0xFFFF, sum = 0
4777 23:56:51.490472 4, 0xFFFF, sum = 0
4778 23:56:51.493595 5, 0xFFFF, sum = 0
4779 23:56:51.494032 6, 0xFFFF, sum = 0
4780 23:56:51.496397 7, 0xFFFF, sum = 0
4781 23:56:51.496842 8, 0x0, sum = 1
4782 23:56:51.499579 9, 0x0, sum = 2
4783 23:56:51.500044 10, 0x0, sum = 3
4784 23:56:51.502819 11, 0x0, sum = 4
4785 23:56:51.503254 best_step = 9
4786 23:56:51.503689
4787 23:56:51.504097 ==
4788 23:56:51.506109 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 23:56:51.509741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 23:56:51.510173 ==
4791 23:56:51.512367 RX Vref Scan: 0
4792 23:56:51.512795
4793 23:56:51.516064 RX Vref 0 -> 0, step: 1
4794 23:56:51.516491
4795 23:56:51.519105 RX Delay -179 -> 252, step: 8
4796 23:56:51.522489 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4797 23:56:51.525798 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4798 23:56:51.532488 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4799 23:56:51.535653 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4800 23:56:51.539008 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4801 23:56:51.542467 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4802 23:56:51.548809 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4803 23:56:51.552386 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4804 23:56:51.555202 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4805 23:56:51.558599 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4806 23:56:51.561891 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4807 23:56:51.568612 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4808 23:56:51.572295 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4809 23:56:51.575457 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4810 23:56:51.578471 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4811 23:56:51.585103 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4812 23:56:51.585567 ==
4813 23:56:51.588337 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 23:56:51.591974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 23:56:51.592359 ==
4816 23:56:51.592701 DQS Delay:
4817 23:56:51.595061 DQS0 = 0, DQS1 = 0
4818 23:56:51.595471 DQM Delay:
4819 23:56:51.598651 DQM0 = 37, DQM1 = 35
4820 23:56:51.599078 DQ Delay:
4821 23:56:51.601867 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4822 23:56:51.605193 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4823 23:56:51.608709 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4824 23:56:51.611962 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4825 23:56:51.612376
4826 23:56:51.612703
4827 23:56:51.621746 [DQSOSCAuto] RK1, (LSB)MR18= 0x385c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4828 23:56:51.622266 CH1 RK1: MR19=808, MR18=385C
4829 23:56:51.628405 CH1_RK1: MR19=0x808, MR18=0x385C, DQSOSC=392, MR23=63, INC=170, DEC=113
4830 23:56:51.631865 [RxdqsGatingPostProcess] freq 600
4831 23:56:51.638592 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 23:56:51.641185 Pre-setting of DQS Precalculation
4833 23:56:51.645119 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 23:56:51.651534 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 23:56:51.660974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 23:56:51.661452
4837 23:56:51.661925
4838 23:56:51.664496 [Calibration Summary] 1200 Mbps
4839 23:56:51.664917 CH 0, Rank 0
4840 23:56:51.667650 SW Impedance : PASS
4841 23:56:51.668070 DUTY Scan : NO K
4842 23:56:51.670904 ZQ Calibration : PASS
4843 23:56:51.674504 Jitter Meter : NO K
4844 23:56:51.674924 CBT Training : PASS
4845 23:56:51.677388 Write leveling : PASS
4846 23:56:51.680708 RX DQS gating : PASS
4847 23:56:51.681135 RX DQ/DQS(RDDQC) : PASS
4848 23:56:51.684113 TX DQ/DQS : PASS
4849 23:56:51.687936 RX DATLAT : PASS
4850 23:56:51.688366 RX DQ/DQS(Engine): PASS
4851 23:56:51.690775 TX OE : NO K
4852 23:56:51.691204 All Pass.
4853 23:56:51.691635
4854 23:56:51.694022 CH 0, Rank 1
4855 23:56:51.694450 SW Impedance : PASS
4856 23:56:51.697338 DUTY Scan : NO K
4857 23:56:51.700868 ZQ Calibration : PASS
4858 23:56:51.701323 Jitter Meter : NO K
4859 23:56:51.704122 CBT Training : PASS
4860 23:56:51.704549 Write leveling : PASS
4861 23:56:51.706953 RX DQS gating : PASS
4862 23:56:51.710655 RX DQ/DQS(RDDQC) : PASS
4863 23:56:51.711089 TX DQ/DQS : PASS
4864 23:56:51.714053 RX DATLAT : PASS
4865 23:56:51.717346 RX DQ/DQS(Engine): PASS
4866 23:56:51.717761 TX OE : NO K
4867 23:56:51.720244 All Pass.
4868 23:56:51.720656
4869 23:56:51.720982 CH 1, Rank 0
4870 23:56:51.723508 SW Impedance : PASS
4871 23:56:51.724092 DUTY Scan : NO K
4872 23:56:51.726937 ZQ Calibration : PASS
4873 23:56:51.730160 Jitter Meter : NO K
4874 23:56:51.730594 CBT Training : PASS
4875 23:56:51.733388 Write leveling : PASS
4876 23:56:51.736921 RX DQS gating : PASS
4877 23:56:51.737396 RX DQ/DQS(RDDQC) : PASS
4878 23:56:51.740060 TX DQ/DQS : PASS
4879 23:56:51.743543 RX DATLAT : PASS
4880 23:56:51.743977 RX DQ/DQS(Engine): PASS
4881 23:56:51.746418 TX OE : NO K
4882 23:56:51.746852 All Pass.
4883 23:56:51.747289
4884 23:56:51.750041 CH 1, Rank 1
4885 23:56:51.750472 SW Impedance : PASS
4886 23:56:51.753034 DUTY Scan : NO K
4887 23:56:51.756584 ZQ Calibration : PASS
4888 23:56:51.757018 Jitter Meter : NO K
4889 23:56:51.759670 CBT Training : PASS
4890 23:56:51.763102 Write leveling : PASS
4891 23:56:51.763514 RX DQS gating : PASS
4892 23:56:51.766491 RX DQ/DQS(RDDQC) : PASS
4893 23:56:51.769327 TX DQ/DQS : PASS
4894 23:56:51.769875 RX DATLAT : PASS
4895 23:56:51.773128 RX DQ/DQS(Engine): PASS
4896 23:56:51.776239 TX OE : NO K
4897 23:56:51.776668 All Pass.
4898 23:56:51.777096
4899 23:56:51.777561 DramC Write-DBI off
4900 23:56:51.779740 PER_BANK_REFRESH: Hybrid Mode
4901 23:56:51.782932 TX_TRACKING: ON
4902 23:56:51.789542 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 23:56:51.792828 [FAST_K] Save calibration result to emmc
4904 23:56:51.799662 dramc_set_vcore_voltage set vcore to 662500
4905 23:56:51.800108 Read voltage for 933, 3
4906 23:56:51.802615 Vio18 = 0
4907 23:56:51.803044 Vcore = 662500
4908 23:56:51.803561 Vdram = 0
4909 23:56:51.805730 Vddq = 0
4910 23:56:51.806202 Vmddr = 0
4911 23:56:51.808943 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 23:56:51.815860 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 23:56:51.819015 MEM_TYPE=3, freq_sel=17
4914 23:56:51.822713 sv_algorithm_assistance_LP4_1600
4915 23:56:51.825824 ============ PULL DRAM RESETB DOWN ============
4916 23:56:51.828806 ========== PULL DRAM RESETB DOWN end =========
4917 23:56:51.835020 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 23:56:51.838192 ===================================
4919 23:56:51.838279 LPDDR4 DRAM CONFIGURATION
4920 23:56:51.842082 ===================================
4921 23:56:51.845176 EX_ROW_EN[0] = 0x0
4922 23:56:51.845264 EX_ROW_EN[1] = 0x0
4923 23:56:51.848604 LP4Y_EN = 0x0
4924 23:56:51.848685 WORK_FSP = 0x0
4925 23:56:51.851589 WL = 0x3
4926 23:56:51.854813 RL = 0x3
4927 23:56:51.854899 BL = 0x2
4928 23:56:51.858095 RPST = 0x0
4929 23:56:51.858188 RD_PRE = 0x0
4930 23:56:51.862036 WR_PRE = 0x1
4931 23:56:51.862138 WR_PST = 0x0
4932 23:56:51.864650 DBI_WR = 0x0
4933 23:56:51.864751 DBI_RD = 0x0
4934 23:56:51.868300 OTF = 0x1
4935 23:56:51.871564 ===================================
4936 23:56:51.874988 ===================================
4937 23:56:51.875447 ANA top config
4938 23:56:51.878546 ===================================
4939 23:56:51.881536 DLL_ASYNC_EN = 0
4940 23:56:51.885097 ALL_SLAVE_EN = 1
4941 23:56:51.885587 NEW_RANK_MODE = 1
4942 23:56:51.888854 DLL_IDLE_MODE = 1
4943 23:56:51.891525 LP45_APHY_COMB_EN = 1
4944 23:56:51.894793 TX_ODT_DIS = 1
4945 23:56:51.898255 NEW_8X_MODE = 1
4946 23:56:51.901042 ===================================
4947 23:56:51.904322 ===================================
4948 23:56:51.907867 data_rate = 1866
4949 23:56:51.908298 CKR = 1
4950 23:56:51.911001 DQ_P2S_RATIO = 8
4951 23:56:51.914174 ===================================
4952 23:56:51.917654 CA_P2S_RATIO = 8
4953 23:56:51.920672 DQ_CA_OPEN = 0
4954 23:56:51.924300 DQ_SEMI_OPEN = 0
4955 23:56:51.927662 CA_SEMI_OPEN = 0
4956 23:56:51.928085 CA_FULL_RATE = 0
4957 23:56:51.930759 DQ_CKDIV4_EN = 1
4958 23:56:51.934175 CA_CKDIV4_EN = 1
4959 23:56:51.937160 CA_PREDIV_EN = 0
4960 23:56:51.940603 PH8_DLY = 0
4961 23:56:51.943738 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 23:56:51.944202 DQ_AAMCK_DIV = 4
4963 23:56:51.947491 CA_AAMCK_DIV = 4
4964 23:56:51.950730 CA_ADMCK_DIV = 4
4965 23:56:51.954009 DQ_TRACK_CA_EN = 0
4966 23:56:51.957175 CA_PICK = 933
4967 23:56:51.960574 CA_MCKIO = 933
4968 23:56:51.963979 MCKIO_SEMI = 0
4969 23:56:51.964433 PLL_FREQ = 3732
4970 23:56:51.967168 DQ_UI_PI_RATIO = 32
4971 23:56:51.970405 CA_UI_PI_RATIO = 0
4972 23:56:51.974267 ===================================
4973 23:56:51.977171 ===================================
4974 23:56:51.980156 memory_type:LPDDR4
4975 23:56:51.983470 GP_NUM : 10
4976 23:56:51.983928 SRAM_EN : 1
4977 23:56:51.987031 MD32_EN : 0
4978 23:56:51.990636 ===================================
4979 23:56:51.991118 [ANA_INIT] >>>>>>>>>>>>>>
4980 23:56:51.993499 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 23:56:51.996824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 23:56:52.000674 ===================================
4983 23:56:52.003551 data_rate = 1866,PCW = 0X8f00
4984 23:56:52.006745 ===================================
4985 23:56:52.010168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 23:56:52.016509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 23:56:52.023104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 23:56:52.026308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 23:56:52.030062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 23:56:52.033055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 23:56:52.036061 [ANA_INIT] flow start
4992 23:56:52.036495 [ANA_INIT] PLL >>>>>>>>
4993 23:56:52.039537 [ANA_INIT] PLL <<<<<<<<
4994 23:56:52.043197 [ANA_INIT] MIDPI >>>>>>>>
4995 23:56:52.045939 [ANA_INIT] MIDPI <<<<<<<<
4996 23:56:52.046431 [ANA_INIT] DLL >>>>>>>>
4997 23:56:52.049699 [ANA_INIT] flow end
4998 23:56:52.052506 ============ LP4 DIFF to SE enter ============
4999 23:56:52.055776 ============ LP4 DIFF to SE exit ============
5000 23:56:52.059459 [ANA_INIT] <<<<<<<<<<<<<
5001 23:56:52.062689 [Flow] Enable top DCM control >>>>>
5002 23:56:52.066103 [Flow] Enable top DCM control <<<<<
5003 23:56:52.069516 Enable DLL master slave shuffle
5004 23:56:52.075880 ==============================================================
5005 23:56:52.076304 Gating Mode config
5006 23:56:52.082304 ==============================================================
5007 23:56:52.082758 Config description:
5008 23:56:52.092245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 23:56:52.098806 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 23:56:52.105316 SELPH_MODE 0: By rank 1: By Phase
5011 23:56:52.108757 ==============================================================
5012 23:56:52.111895 GAT_TRACK_EN = 1
5013 23:56:52.115130 RX_GATING_MODE = 2
5014 23:56:52.118318 RX_GATING_TRACK_MODE = 2
5015 23:56:52.121760 SELPH_MODE = 1
5016 23:56:52.126317 PICG_EARLY_EN = 1
5017 23:56:52.129097 VALID_LAT_VALUE = 1
5018 23:56:52.134972 ==============================================================
5019 23:56:52.138388 Enter into Gating configuration >>>>
5020 23:56:52.141840 Exit from Gating configuration <<<<
5021 23:56:52.144773 Enter into DVFS_PRE_config >>>>>
5022 23:56:52.154929 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 23:56:52.158152 Exit from DVFS_PRE_config <<<<<
5024 23:56:52.161358 Enter into PICG configuration >>>>
5025 23:56:52.164587 Exit from PICG configuration <<<<
5026 23:56:52.168043 [RX_INPUT] configuration >>>>>
5027 23:56:52.170979 [RX_INPUT] configuration <<<<<
5028 23:56:52.174896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 23:56:52.181461 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 23:56:52.187963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 23:56:52.190826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 23:56:52.197728 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 23:56:52.204192 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 23:56:52.207272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 23:56:52.214131 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 23:56:52.216913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 23:56:52.220512 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 23:56:52.223640 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 23:56:52.230737 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 23:56:52.233685 ===================================
5041 23:56:52.237423 LPDDR4 DRAM CONFIGURATION
5042 23:56:52.240194 ===================================
5043 23:56:52.240652 EX_ROW_EN[0] = 0x0
5044 23:56:52.243130 EX_ROW_EN[1] = 0x0
5045 23:56:52.243541 LP4Y_EN = 0x0
5046 23:56:52.246621 WORK_FSP = 0x0
5047 23:56:52.247033 WL = 0x3
5048 23:56:52.249743 RL = 0x3
5049 23:56:52.250154 BL = 0x2
5050 23:56:52.253177 RPST = 0x0
5051 23:56:52.253630 RD_PRE = 0x0
5052 23:56:52.256408 WR_PRE = 0x1
5053 23:56:52.256826 WR_PST = 0x0
5054 23:56:52.259839 DBI_WR = 0x0
5055 23:56:52.263547 DBI_RD = 0x0
5056 23:56:52.263963 OTF = 0x1
5057 23:56:52.266525 ===================================
5058 23:56:52.269777 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 23:56:52.272891 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 23:56:52.279549 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 23:56:52.282824 ===================================
5062 23:56:52.286299 LPDDR4 DRAM CONFIGURATION
5063 23:56:52.289673 ===================================
5064 23:56:52.290096 EX_ROW_EN[0] = 0x10
5065 23:56:52.292958 EX_ROW_EN[1] = 0x0
5066 23:56:52.293419 LP4Y_EN = 0x0
5067 23:56:52.296652 WORK_FSP = 0x0
5068 23:56:52.297240 WL = 0x3
5069 23:56:52.300091 RL = 0x3
5070 23:56:52.300513 BL = 0x2
5071 23:56:52.302921 RPST = 0x0
5072 23:56:52.303343 RD_PRE = 0x0
5073 23:56:52.306006 WR_PRE = 0x1
5074 23:56:52.309143 WR_PST = 0x0
5075 23:56:52.309608 DBI_WR = 0x0
5076 23:56:52.312304 DBI_RD = 0x0
5077 23:56:52.312786 OTF = 0x1
5078 23:56:52.315973 ===================================
5079 23:56:52.322678 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 23:56:52.326024 nWR fixed to 30
5081 23:56:52.329488 [ModeRegInit_LP4] CH0 RK0
5082 23:56:52.329902 [ModeRegInit_LP4] CH0 RK1
5083 23:56:52.332968 [ModeRegInit_LP4] CH1 RK0
5084 23:56:52.336201 [ModeRegInit_LP4] CH1 RK1
5085 23:56:52.336621 match AC timing 9
5086 23:56:52.342917 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 23:56:52.346322 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 23:56:52.349231 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 23:56:52.355509 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 23:56:52.359191 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 23:56:52.359613 ==
5092 23:56:52.362249 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 23:56:52.365527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 23:56:52.366028 ==
5095 23:56:52.372335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 23:56:52.379001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5097 23:56:52.382285 [CA 0] Center 37 (7~68) winsize 62
5098 23:56:52.385466 [CA 1] Center 37 (7~68) winsize 62
5099 23:56:52.388696 [CA 2] Center 34 (4~65) winsize 62
5100 23:56:52.391812 [CA 3] Center 34 (4~65) winsize 62
5101 23:56:52.395218 [CA 4] Center 33 (3~64) winsize 62
5102 23:56:52.398768 [CA 5] Center 32 (2~63) winsize 62
5103 23:56:52.399188
5104 23:56:52.402279 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5105 23:56:52.402690
5106 23:56:52.405325 [CATrainingPosCal] consider 1 rank data
5107 23:56:52.408417 u2DelayCellTimex100 = 270/100 ps
5108 23:56:52.411663 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5109 23:56:52.414883 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5110 23:56:52.418527 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5111 23:56:52.425000 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5112 23:56:52.428751 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5113 23:56:52.432191 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5114 23:56:52.432693
5115 23:56:52.434621 CA PerBit enable=1, Macro0, CA PI delay=32
5116 23:56:52.435031
5117 23:56:52.438205 [CBTSetCACLKResult] CA Dly = 32
5118 23:56:52.438618 CS Dly: 6 (0~37)
5119 23:56:52.438944 ==
5120 23:56:52.441975 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 23:56:52.448191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 23:56:52.448610 ==
5123 23:56:52.451072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 23:56:52.457696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5125 23:56:52.461378 [CA 0] Center 37 (7~68) winsize 62
5126 23:56:52.464527 [CA 1] Center 37 (7~68) winsize 62
5127 23:56:52.467740 [CA 2] Center 34 (4~65) winsize 62
5128 23:56:52.471369 [CA 3] Center 34 (4~65) winsize 62
5129 23:56:52.474152 [CA 4] Center 33 (3~64) winsize 62
5130 23:56:52.477983 [CA 5] Center 32 (2~63) winsize 62
5131 23:56:52.478404
5132 23:56:52.480996 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5133 23:56:52.481530
5134 23:56:52.484477 [CATrainingPosCal] consider 2 rank data
5135 23:56:52.487755 u2DelayCellTimex100 = 270/100 ps
5136 23:56:52.491074 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5137 23:56:52.497691 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5138 23:56:52.501119 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5139 23:56:52.504267 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5140 23:56:52.507554 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5141 23:56:52.510963 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5142 23:56:52.511505
5143 23:56:52.514018 CA PerBit enable=1, Macro0, CA PI delay=32
5144 23:56:52.514431
5145 23:56:52.516967 [CBTSetCACLKResult] CA Dly = 32
5146 23:56:52.520227 CS Dly: 7 (0~39)
5147 23:56:52.520763
5148 23:56:52.523984 ----->DramcWriteLeveling(PI) begin...
5149 23:56:52.524537 ==
5150 23:56:52.526526 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 23:56:52.530078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 23:56:52.530503 ==
5153 23:56:52.533848 Write leveling (Byte 0): 33 => 33
5154 23:56:52.537059 Write leveling (Byte 1): 28 => 28
5155 23:56:52.540000 DramcWriteLeveling(PI) end<-----
5156 23:56:52.540419
5157 23:56:52.540752 ==
5158 23:56:52.543333 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 23:56:52.546505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 23:56:52.546927 ==
5161 23:56:52.550235 [Gating] SW mode calibration
5162 23:56:52.556866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 23:56:52.563050 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 23:56:52.566212 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5165 23:56:52.573092 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5166 23:56:52.576335 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 23:56:52.579765 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 23:56:52.586365 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 23:56:52.589741 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 23:56:52.592630 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5171 23:56:52.599210 0 14 28 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
5172 23:56:52.602780 0 15 0 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
5173 23:56:52.605977 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5174 23:56:52.613492 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 23:56:52.615553 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 23:56:52.619085 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 23:56:52.625822 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 23:56:52.628972 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
5179 23:56:52.632201 0 15 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5180 23:56:52.638604 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5181 23:56:52.642282 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 23:56:52.645944 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 23:56:52.651980 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 23:56:52.655287 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 23:56:52.658560 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 23:56:52.665687 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 23:56:52.668627 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5188 23:56:52.671668 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5189 23:56:52.678115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:56:52.682022 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:56:52.685146 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:56:52.691774 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:56:52.695049 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:56:52.698574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:56:52.705019 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:56:52.708810 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:56:52.711840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:56:52.717854 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:56:52.721253 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:56:52.724467 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:56:52.731240 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:56:52.734483 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:56:52.737730 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 23:56:52.740982 Total UI for P1: 0, mck2ui 16
5205 23:56:52.744761 best dqsien dly found for B0: ( 1, 2, 26)
5206 23:56:52.751020 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5207 23:56:52.754527 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 23:56:52.757460 Total UI for P1: 0, mck2ui 16
5209 23:56:52.761018 best dqsien dly found for B1: ( 1, 3, 2)
5210 23:56:52.764277 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5211 23:56:52.767457 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5212 23:56:52.767878
5213 23:56:52.771330 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5214 23:56:52.774111 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5215 23:56:52.777351 [Gating] SW calibration Done
5216 23:56:52.777772 ==
5217 23:56:52.780931 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 23:56:52.784303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 23:56:52.787386 ==
5220 23:56:52.787796 RX Vref Scan: 0
5221 23:56:52.788120
5222 23:56:52.790820 RX Vref 0 -> 0, step: 1
5223 23:56:52.791231
5224 23:56:52.793950 RX Delay -80 -> 252, step: 8
5225 23:56:52.797320 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5226 23:56:52.800394 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5227 23:56:52.804130 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5228 23:56:52.807056 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5229 23:56:52.810249 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5230 23:56:52.817529 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5231 23:56:52.820177 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5232 23:56:52.823943 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5233 23:56:52.827071 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5234 23:56:52.830110 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5235 23:56:52.833657 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5236 23:56:52.840289 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5237 23:56:52.843605 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5238 23:56:52.846818 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5239 23:56:52.850186 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5240 23:56:52.853419 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5241 23:56:52.853852 ==
5242 23:56:52.856741 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 23:56:52.863117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 23:56:52.863556 ==
5245 23:56:52.864096 DQS Delay:
5246 23:56:52.866579 DQS0 = 0, DQS1 = 0
5247 23:56:52.867009 DQM Delay:
5248 23:56:52.867445 DQM0 = 99, DQM1 = 88
5249 23:56:52.869972 DQ Delay:
5250 23:56:52.873663 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5251 23:56:52.876566 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5252 23:56:52.879753 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5253 23:56:52.882976 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5254 23:56:52.883433
5255 23:56:52.883888
5256 23:56:52.884297 ==
5257 23:56:52.886927 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 23:56:52.889655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 23:56:52.890095 ==
5260 23:56:52.890525
5261 23:56:52.890931
5262 23:56:52.893169 TX Vref Scan disable
5263 23:56:52.896406 == TX Byte 0 ==
5264 23:56:52.900202 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5265 23:56:52.902885 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5266 23:56:52.906206 == TX Byte 1 ==
5267 23:56:52.910035 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5268 23:56:52.912803 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5269 23:56:52.913437 ==
5270 23:56:52.916034 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 23:56:52.922833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 23:56:52.923252 ==
5273 23:56:52.923581
5274 23:56:52.923890
5275 23:56:52.924252 TX Vref Scan disable
5276 23:56:52.926958 == TX Byte 0 ==
5277 23:56:52.930651 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5278 23:56:52.936289 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5279 23:56:52.936710 == TX Byte 1 ==
5280 23:56:52.939720 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5281 23:56:52.946309 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5282 23:56:52.946730
5283 23:56:52.947062 [DATLAT]
5284 23:56:52.947460 Freq=933, CH0 RK0
5285 23:56:52.948002
5286 23:56:52.949909 DATLAT Default: 0xd
5287 23:56:52.953383 0, 0xFFFF, sum = 0
5288 23:56:52.953852 1, 0xFFFF, sum = 0
5289 23:56:52.956329 2, 0xFFFF, sum = 0
5290 23:56:52.956751 3, 0xFFFF, sum = 0
5291 23:56:52.959600 4, 0xFFFF, sum = 0
5292 23:56:52.960086 5, 0xFFFF, sum = 0
5293 23:56:52.963495 6, 0xFFFF, sum = 0
5294 23:56:52.963920 7, 0xFFFF, sum = 0
5295 23:56:52.966273 8, 0xFFFF, sum = 0
5296 23:56:52.966698 9, 0xFFFF, sum = 0
5297 23:56:52.969755 10, 0x0, sum = 1
5298 23:56:52.970181 11, 0x0, sum = 2
5299 23:56:52.973104 12, 0x0, sum = 3
5300 23:56:52.973596 13, 0x0, sum = 4
5301 23:56:52.976430 best_step = 11
5302 23:56:52.976897
5303 23:56:52.977422 ==
5304 23:56:52.979537 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 23:56:52.982858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 23:56:52.983290 ==
5307 23:56:52.983730 RX Vref Scan: 1
5308 23:56:52.986269
5309 23:56:52.986839 RX Vref 0 -> 0, step: 1
5310 23:56:52.987329
5311 23:56:52.989298 RX Delay -61 -> 252, step: 4
5312 23:56:52.989925
5313 23:56:52.992677 Set Vref, RX VrefLevel [Byte0]: 54
5314 23:56:52.995860 [Byte1]: 59
5315 23:56:52.999434
5316 23:56:52.999852 Final RX Vref Byte 0 = 54 to rank0
5317 23:56:53.002615 Final RX Vref Byte 1 = 59 to rank0
5318 23:56:53.006179 Final RX Vref Byte 0 = 54 to rank1
5319 23:56:53.009435 Final RX Vref Byte 1 = 59 to rank1==
5320 23:56:53.012478 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 23:56:53.018928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 23:56:53.019360 ==
5323 23:56:53.019794 DQS Delay:
5324 23:56:53.022133 DQS0 = 0, DQS1 = 0
5325 23:56:53.022556 DQM Delay:
5326 23:56:53.022990 DQM0 = 98, DQM1 = 88
5327 23:56:53.025910 DQ Delay:
5328 23:56:53.028625 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =94
5329 23:56:53.032342 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =106
5330 23:56:53.035382 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5331 23:56:53.038538 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =94
5332 23:56:53.038986
5333 23:56:53.039503
5334 23:56:53.045669 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5335 23:56:53.048747 CH0 RK0: MR19=505, MR18=1A14
5336 23:56:53.055104 CH0_RK0: MR19=0x505, MR18=0x1A14, DQSOSC=413, MR23=63, INC=63, DEC=42
5337 23:56:53.055533
5338 23:56:53.058217 ----->DramcWriteLeveling(PI) begin...
5339 23:56:53.058712 ==
5340 23:56:53.061700 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 23:56:53.064692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 23:56:53.068398 ==
5343 23:56:53.068931 Write leveling (Byte 0): 32 => 32
5344 23:56:53.071589 Write leveling (Byte 1): 26 => 26
5345 23:56:53.074641 DramcWriteLeveling(PI) end<-----
5346 23:56:53.075073
5347 23:56:53.075590 ==
5348 23:56:53.078002 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 23:56:53.084457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 23:56:53.084890 ==
5351 23:56:53.088422 [Gating] SW mode calibration
5352 23:56:53.094866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 23:56:53.097223 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 23:56:53.104189 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5355 23:56:53.107204 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 23:56:53.110671 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 23:56:53.117635 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 23:56:53.120597 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 23:56:53.123766 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 23:56:53.130710 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5361 23:56:53.133504 0 14 28 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 0)
5362 23:56:53.136571 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5363 23:56:53.143715 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 23:56:53.146697 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 23:56:53.149849 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 23:56:53.156765 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 23:56:53.160574 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 23:56:53.163845 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5369 23:56:53.170033 0 15 28 | B1->B0 | 2727 4040 | 1 0 | (0 0) (0 0)
5370 23:56:53.173020 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5371 23:56:53.175960 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:56:53.182900 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:56:53.186510 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 23:56:53.189632 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 23:56:53.196351 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 23:56:53.199563 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5377 23:56:53.203098 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 23:56:53.209552 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:56:53.212661 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:56:53.215777 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:56:53.222528 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:56:53.225850 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:56:53.228837 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:56:53.235604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:56:53.239410 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:56:53.242458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:56:53.249224 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:56:53.252322 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:56:53.255536 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:56:53.262443 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:56:53.265390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:56:53.268983 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:56:53.275377 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5394 23:56:53.278359 Total UI for P1: 0, mck2ui 16
5395 23:56:53.282257 best dqsien dly found for B0: ( 1, 2, 26)
5396 23:56:53.285059 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5397 23:56:53.288502 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 23:56:53.291642 Total UI for P1: 0, mck2ui 16
5399 23:56:53.295087 best dqsien dly found for B1: ( 1, 2, 30)
5400 23:56:53.298089 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5401 23:56:53.304710 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5402 23:56:53.305326
5403 23:56:53.308870 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5404 23:56:53.311922 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5405 23:56:53.314709 [Gating] SW calibration Done
5406 23:56:53.315264 ==
5407 23:56:53.318315 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 23:56:53.320910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 23:56:53.321473 ==
5410 23:56:53.324903 RX Vref Scan: 0
5411 23:56:53.325476
5412 23:56:53.325845 RX Vref 0 -> 0, step: 1
5413 23:56:53.326176
5414 23:56:53.327923 RX Delay -80 -> 252, step: 8
5415 23:56:53.331143 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5416 23:56:53.337535 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5417 23:56:53.341110 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5418 23:56:53.344037 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5419 23:56:53.347375 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5420 23:56:53.351237 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5421 23:56:53.354371 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5422 23:56:53.360861 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5423 23:56:53.364057 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5424 23:56:53.367098 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5425 23:56:53.370454 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5426 23:56:53.374299 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5427 23:56:53.377017 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5428 23:56:53.383845 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5429 23:56:53.387120 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5430 23:56:53.390152 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5431 23:56:53.390540 ==
5432 23:56:53.393549 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 23:56:53.397039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 23:56:53.397482 ==
5435 23:56:53.400481 DQS Delay:
5436 23:56:53.400991 DQS0 = 0, DQS1 = 0
5437 23:56:53.403671 DQM Delay:
5438 23:56:53.404075 DQM0 = 97, DQM1 = 90
5439 23:56:53.404400 DQ Delay:
5440 23:56:53.407084 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5441 23:56:53.410242 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5442 23:56:53.413746 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5443 23:56:53.416990 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5444 23:56:53.417427
5445 23:56:53.417850
5446 23:56:53.420223 ==
5447 23:56:53.423871 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 23:56:53.426862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 23:56:53.427344 ==
5450 23:56:53.427674
5451 23:56:53.427975
5452 23:56:53.430072 TX Vref Scan disable
5453 23:56:53.430482 == TX Byte 0 ==
5454 23:56:53.436318 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5455 23:56:53.439489 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5456 23:56:53.439900 == TX Byte 1 ==
5457 23:56:53.446305 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5458 23:56:53.449633 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5459 23:56:53.450051 ==
5460 23:56:53.452665 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 23:56:53.456254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 23:56:53.456671 ==
5463 23:56:53.456999
5464 23:56:53.457349
5465 23:56:53.459471 TX Vref Scan disable
5466 23:56:53.462525 == TX Byte 0 ==
5467 23:56:53.466303 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5468 23:56:53.469454 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5469 23:56:53.473331 == TX Byte 1 ==
5470 23:56:53.475916 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5471 23:56:53.478996 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5472 23:56:53.479497
5473 23:56:53.482611 [DATLAT]
5474 23:56:53.483023 Freq=933, CH0 RK1
5475 23:56:53.483350
5476 23:56:53.485554 DATLAT Default: 0xb
5477 23:56:53.485969 0, 0xFFFF, sum = 0
5478 23:56:53.489088 1, 0xFFFF, sum = 0
5479 23:56:53.489568 2, 0xFFFF, sum = 0
5480 23:56:53.492955 3, 0xFFFF, sum = 0
5481 23:56:53.493440 4, 0xFFFF, sum = 0
5482 23:56:53.495886 5, 0xFFFF, sum = 0
5483 23:56:53.496313 6, 0xFFFF, sum = 0
5484 23:56:53.498903 7, 0xFFFF, sum = 0
5485 23:56:53.502265 8, 0xFFFF, sum = 0
5486 23:56:53.502687 9, 0xFFFF, sum = 0
5487 23:56:53.505390 10, 0x0, sum = 1
5488 23:56:53.505811 11, 0x0, sum = 2
5489 23:56:53.506148 12, 0x0, sum = 3
5490 23:56:53.508745 13, 0x0, sum = 4
5491 23:56:53.509177 best_step = 11
5492 23:56:53.509691
5493 23:56:53.512216 ==
5494 23:56:53.512638 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 23:56:53.518451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 23:56:53.518879 ==
5497 23:56:53.519309 RX Vref Scan: 0
5498 23:56:53.519711
5499 23:56:53.522038 RX Vref 0 -> 0, step: 1
5500 23:56:53.522461
5501 23:56:53.525617 RX Delay -53 -> 252, step: 4
5502 23:56:53.528537 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5503 23:56:53.535107 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5504 23:56:53.538672 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5505 23:56:53.541844 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5506 23:56:53.544922 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5507 23:56:53.548320 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5508 23:56:53.551653 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5509 23:56:53.558471 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5510 23:56:53.561603 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5511 23:56:53.564582 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5512 23:56:53.568450 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5513 23:56:53.571507 iDelay=195, Bit 11, Center 86 (-1 ~ 174) 176
5514 23:56:53.578179 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5515 23:56:53.581649 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5516 23:56:53.584292 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5517 23:56:53.587886 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5518 23:56:53.588304 ==
5519 23:56:53.590864 Dram Type= 6, Freq= 0, CH_0, rank 1
5520 23:56:53.597340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 23:56:53.597759 ==
5522 23:56:53.598093 DQS Delay:
5523 23:56:53.601186 DQS0 = 0, DQS1 = 0
5524 23:56:53.601641 DQM Delay:
5525 23:56:53.601968 DQM0 = 96, DQM1 = 89
5526 23:56:53.604017 DQ Delay:
5527 23:56:53.607651 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =94
5528 23:56:53.610613 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5529 23:56:53.614372 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =86
5530 23:56:53.617331 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5531 23:56:53.617749
5532 23:56:53.618076
5533 23:56:53.624006 [DQSOSCAuto] RK1, (LSB)MR18= 0x1512, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5534 23:56:53.627078 CH0 RK1: MR19=505, MR18=1512
5535 23:56:53.633408 CH0_RK1: MR19=0x505, MR18=0x1512, DQSOSC=415, MR23=63, INC=62, DEC=41
5536 23:56:53.636835 [RxdqsGatingPostProcess] freq 933
5537 23:56:53.643848 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5538 23:56:53.646972 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 23:56:53.647392 best DQS1 dly(2T, 0.5T) = (0, 11)
5540 23:56:53.650330 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 23:56:53.653379 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5542 23:56:53.656856 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 23:56:53.660263 best DQS1 dly(2T, 0.5T) = (0, 10)
5544 23:56:53.663360 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 23:56:53.666881 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5546 23:56:53.669912 Pre-setting of DQS Precalculation
5547 23:56:53.676114 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5548 23:56:53.676196 ==
5549 23:56:53.679525 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 23:56:53.682970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 23:56:53.683133 ==
5552 23:56:53.689149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 23:56:53.692598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 23:56:53.697207 [CA 0] Center 36 (6~67) winsize 62
5555 23:56:53.700478 [CA 1] Center 36 (6~67) winsize 62
5556 23:56:53.703510 [CA 2] Center 34 (4~65) winsize 62
5557 23:56:53.706807 [CA 3] Center 33 (3~64) winsize 62
5558 23:56:53.710389 [CA 4] Center 34 (4~65) winsize 62
5559 23:56:53.713747 [CA 5] Center 33 (3~64) winsize 62
5560 23:56:53.713832
5561 23:56:53.716566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 23:56:53.716661
5563 23:56:53.720319 [CATrainingPosCal] consider 1 rank data
5564 23:56:53.723239 u2DelayCellTimex100 = 270/100 ps
5565 23:56:53.726771 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 23:56:53.733860 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 23:56:53.736930 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 23:56:53.739635 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 23:56:53.743381 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 23:56:53.746885 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 23:56:53.747043
5572 23:56:53.749587 CA PerBit enable=1, Macro0, CA PI delay=33
5573 23:56:53.749759
5574 23:56:53.752788 [CBTSetCACLKResult] CA Dly = 33
5575 23:56:53.756705 CS Dly: 5 (0~36)
5576 23:56:53.756945 ==
5577 23:56:53.760067 Dram Type= 6, Freq= 0, CH_1, rank 1
5578 23:56:53.763632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 23:56:53.763941 ==
5580 23:56:53.769648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 23:56:53.773345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5582 23:56:53.777174 [CA 0] Center 36 (6~67) winsize 62
5583 23:56:53.780541 [CA 1] Center 36 (6~67) winsize 62
5584 23:56:53.784088 [CA 2] Center 34 (4~65) winsize 62
5585 23:56:53.787170 [CA 3] Center 33 (3~64) winsize 62
5586 23:56:53.790750 [CA 4] Center 33 (3~64) winsize 62
5587 23:56:53.794015 [CA 5] Center 33 (3~64) winsize 62
5588 23:56:53.794482
5589 23:56:53.797281 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5590 23:56:53.797787
5591 23:56:53.800191 [CATrainingPosCal] consider 2 rank data
5592 23:56:53.803703 u2DelayCellTimex100 = 270/100 ps
5593 23:56:53.807303 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5594 23:56:53.814025 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5595 23:56:53.817316 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5596 23:56:53.820354 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5597 23:56:53.823556 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5598 23:56:53.826704 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 23:56:53.827121
5600 23:56:53.829911 CA PerBit enable=1, Macro0, CA PI delay=33
5601 23:56:53.830321
5602 23:56:53.833004 [CBTSetCACLKResult] CA Dly = 33
5603 23:56:53.836280 CS Dly: 6 (0~38)
5604 23:56:53.836685
5605 23:56:53.839648 ----->DramcWriteLeveling(PI) begin...
5606 23:56:53.840065 ==
5607 23:56:53.842682 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 23:56:53.845954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 23:56:53.846367 ==
5610 23:56:53.849341 Write leveling (Byte 0): 27 => 27
5611 23:56:53.852873 Write leveling (Byte 1): 27 => 27
5612 23:56:53.857224 DramcWriteLeveling(PI) end<-----
5613 23:56:53.857759
5614 23:56:53.858095 ==
5615 23:56:53.859292 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 23:56:53.862513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 23:56:53.862929 ==
5618 23:56:53.866062 [Gating] SW mode calibration
5619 23:56:53.872274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5620 23:56:53.879138 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5621 23:56:53.882635 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 23:56:53.889250 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 23:56:53.892180 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 23:56:53.895777 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 23:56:53.901859 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 23:56:53.905164 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 23:56:53.909012 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5628 23:56:53.914953 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
5629 23:56:53.918417 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 23:56:53.922261 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 23:56:53.928379 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 23:56:53.931465 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 23:56:53.935124 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 23:56:53.941215 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 23:56:53.944551 0 15 24 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)
5636 23:56:53.948060 0 15 28 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
5637 23:56:53.955004 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 23:56:53.958191 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 23:56:53.961084 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 23:56:53.968027 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 23:56:53.970831 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 23:56:53.974009 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 23:56:53.980525 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 23:56:53.983836 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5645 23:56:53.987376 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:56:53.994621 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:56:53.997010 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:56:54.000442 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:56:54.007161 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:56:54.010547 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:56:54.013457 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:56:54.020004 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:56:54.023456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:56:54.026695 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:56:54.032921 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:56:54.036328 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:56:54.040182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:56:54.046364 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:56:54.049788 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5660 23:56:54.052676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5661 23:56:54.056047 Total UI for P1: 0, mck2ui 16
5662 23:56:54.060051 best dqsien dly found for B0: ( 1, 2, 24)
5663 23:56:54.066210 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 23:56:54.066290 Total UI for P1: 0, mck2ui 16
5665 23:56:54.072791 best dqsien dly found for B1: ( 1, 2, 26)
5666 23:56:54.075915 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5667 23:56:54.079379 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5668 23:56:54.079464
5669 23:56:54.082322 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5670 23:56:54.086053 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5671 23:56:54.088932 [Gating] SW calibration Done
5672 23:56:54.089031 ==
5673 23:56:54.092618 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 23:56:54.095751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 23:56:54.095872 ==
5676 23:56:54.098796 RX Vref Scan: 0
5677 23:56:54.098916
5678 23:56:54.102119 RX Vref 0 -> 0, step: 1
5679 23:56:54.102253
5680 23:56:54.102358 RX Delay -80 -> 252, step: 8
5681 23:56:54.108770 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5682 23:56:54.112414 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5683 23:56:54.115718 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5684 23:56:54.119707 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5685 23:56:54.122019 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5686 23:56:54.125478 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5687 23:56:54.131825 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5688 23:56:54.135410 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5689 23:56:54.139164 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5690 23:56:54.142342 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5691 23:56:54.145453 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5692 23:56:54.152028 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5693 23:56:54.155287 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5694 23:56:54.158647 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5695 23:56:54.161927 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5696 23:56:54.164644 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5697 23:56:54.168265 ==
5698 23:56:54.168676 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 23:56:54.175400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 23:56:54.175818 ==
5701 23:56:54.176143 DQS Delay:
5702 23:56:54.178600 DQS0 = 0, DQS1 = 0
5703 23:56:54.179015 DQM Delay:
5704 23:56:54.181525 DQM0 = 99, DQM1 = 96
5705 23:56:54.181934 DQ Delay:
5706 23:56:54.184674 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5707 23:56:54.188092 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5708 23:56:54.191426 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5709 23:56:54.194807 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5710 23:56:54.195217
5711 23:56:54.195540
5712 23:56:54.195839 ==
5713 23:56:54.197942 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 23:56:54.201121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 23:56:54.201574 ==
5716 23:56:54.205293
5717 23:56:54.205705
5718 23:56:54.206027 TX Vref Scan disable
5719 23:56:54.208297 == TX Byte 0 ==
5720 23:56:54.211211 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5721 23:56:54.214516 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5722 23:56:54.217688 == TX Byte 1 ==
5723 23:56:54.221340 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5724 23:56:54.224228 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5725 23:56:54.224638 ==
5726 23:56:54.228232 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 23:56:54.233930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 23:56:54.234340 ==
5729 23:56:54.234663
5730 23:56:54.234964
5731 23:56:54.237216 TX Vref Scan disable
5732 23:56:54.237679 == TX Byte 0 ==
5733 23:56:54.244073 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5734 23:56:54.247062 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5735 23:56:54.247651 == TX Byte 1 ==
5736 23:56:54.253596 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5737 23:56:54.257336 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5738 23:56:54.257751
5739 23:56:54.258079 [DATLAT]
5740 23:56:54.260076 Freq=933, CH1 RK0
5741 23:56:54.260490
5742 23:56:54.260819 DATLAT Default: 0xd
5743 23:56:54.263421 0, 0xFFFF, sum = 0
5744 23:56:54.263844 1, 0xFFFF, sum = 0
5745 23:56:54.266999 2, 0xFFFF, sum = 0
5746 23:56:54.267532 3, 0xFFFF, sum = 0
5747 23:56:54.270211 4, 0xFFFF, sum = 0
5748 23:56:54.273375 5, 0xFFFF, sum = 0
5749 23:56:54.273791 6, 0xFFFF, sum = 0
5750 23:56:54.276641 7, 0xFFFF, sum = 0
5751 23:56:54.277060 8, 0xFFFF, sum = 0
5752 23:56:54.279982 9, 0xFFFF, sum = 0
5753 23:56:54.280403 10, 0x0, sum = 1
5754 23:56:54.283363 11, 0x0, sum = 2
5755 23:56:54.283781 12, 0x0, sum = 3
5756 23:56:54.286697 13, 0x0, sum = 4
5757 23:56:54.287115 best_step = 11
5758 23:56:54.287440
5759 23:56:54.287751 ==
5760 23:56:54.290630 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 23:56:54.293143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 23:56:54.293653 ==
5763 23:56:54.296309 RX Vref Scan: 1
5764 23:56:54.296720
5765 23:56:54.299766 RX Vref 0 -> 0, step: 1
5766 23:56:54.300179
5767 23:56:54.300505 RX Delay -53 -> 252, step: 4
5768 23:56:54.300811
5769 23:56:54.303286 Set Vref, RX VrefLevel [Byte0]: 53
5770 23:56:54.306837 [Byte1]: 52
5771 23:56:54.310807
5772 23:56:54.311240 Final RX Vref Byte 0 = 53 to rank0
5773 23:56:54.314275 Final RX Vref Byte 1 = 52 to rank0
5774 23:56:54.318165 Final RX Vref Byte 0 = 53 to rank1
5775 23:56:54.320715 Final RX Vref Byte 1 = 52 to rank1==
5776 23:56:54.324163 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 23:56:54.330518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 23:56:54.330938 ==
5779 23:56:54.331271 DQS Delay:
5780 23:56:54.334081 DQS0 = 0, DQS1 = 0
5781 23:56:54.334494 DQM Delay:
5782 23:56:54.334822 DQM0 = 98, DQM1 = 94
5783 23:56:54.337310 DQ Delay:
5784 23:56:54.340475 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5785 23:56:54.344222 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5786 23:56:54.347096 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5787 23:56:54.350559 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5788 23:56:54.351002
5789 23:56:54.351333
5790 23:56:54.357132 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5791 23:56:54.360391 CH1 RK0: MR19=505, MR18=B1B
5792 23:56:54.366925 CH1_RK0: MR19=0x505, MR18=0xB1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5793 23:56:54.367374
5794 23:56:54.370191 ----->DramcWriteLeveling(PI) begin...
5795 23:56:54.370614 ==
5796 23:56:54.373533 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 23:56:54.376782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:56:54.377194 ==
5799 23:56:54.380410 Write leveling (Byte 0): 26 => 26
5800 23:56:54.383339 Write leveling (Byte 1): 28 => 28
5801 23:56:54.387058 DramcWriteLeveling(PI) end<-----
5802 23:56:54.387492
5803 23:56:54.387826 ==
5804 23:56:54.390531 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 23:56:54.396947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 23:56:54.397418 ==
5807 23:56:54.397760 [Gating] SW mode calibration
5808 23:56:54.406482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 23:56:54.409613 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 23:56:54.416314 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 23:56:54.419863 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 23:56:54.423086 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 23:56:54.429645 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 23:56:54.433246 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 23:56:54.436099 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 23:56:54.442746 0 14 24 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 0)
5817 23:56:54.445923 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5818 23:56:54.449441 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5819 23:56:54.455958 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 23:56:54.459437 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 23:56:54.462553 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 23:56:54.469051 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 23:56:54.472661 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 23:56:54.475663 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
5825 23:56:54.482439 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5826 23:56:54.485408 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 23:56:54.488758 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 23:56:54.495857 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 23:56:54.498706 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 23:56:54.501942 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 23:56:54.509062 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 23:56:54.511693 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 23:56:54.515124 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5834 23:56:54.522068 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5835 23:56:54.525045 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:56:54.528115 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:56:54.534974 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:56:54.538271 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:56:54.541691 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:56:54.548000 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:56:54.551778 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:56:54.554518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:56:54.561609 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 23:56:54.564739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:56:54.567653 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:56:54.574601 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:56:54.577934 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:56:54.580599 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5849 23:56:54.587170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5850 23:56:54.590572 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5851 23:56:54.594111 Total UI for P1: 0, mck2ui 16
5852 23:56:54.597071 best dqsien dly found for B0: ( 1, 2, 26)
5853 23:56:54.600584 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 23:56:54.603993 Total UI for P1: 0, mck2ui 16
5855 23:56:54.607181 best dqsien dly found for B1: ( 1, 2, 30)
5856 23:56:54.610621 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5857 23:56:54.613766 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5858 23:56:54.614195
5859 23:56:54.620225 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5860 23:56:54.623794 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5861 23:56:54.624255 [Gating] SW calibration Done
5862 23:56:54.626697 ==
5863 23:56:54.630295 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 23:56:54.633531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 23:56:54.634133 ==
5866 23:56:54.634487 RX Vref Scan: 0
5867 23:56:54.634801
5868 23:56:54.636877 RX Vref 0 -> 0, step: 1
5869 23:56:54.637330
5870 23:56:54.639985 RX Delay -80 -> 252, step: 8
5871 23:56:54.643521 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5872 23:56:54.646994 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5873 23:56:54.653379 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5874 23:56:54.657054 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5875 23:56:54.659588 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5876 23:56:54.663008 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5877 23:56:54.666541 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5878 23:56:54.669532 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5879 23:56:54.676321 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5880 23:56:54.679820 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5881 23:56:54.682708 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5882 23:56:54.686070 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5883 23:56:54.689767 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5884 23:56:54.696097 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5885 23:56:54.699380 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5886 23:56:54.702444 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5887 23:56:54.702983 ==
5888 23:56:54.705921 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 23:56:54.709480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 23:56:54.710072 ==
5891 23:56:54.712586 DQS Delay:
5892 23:56:54.713144 DQS0 = 0, DQS1 = 0
5893 23:56:54.715669 DQM Delay:
5894 23:56:54.716074 DQM0 = 97, DQM1 = 94
5895 23:56:54.716398 DQ Delay:
5896 23:56:54.718959 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5897 23:56:54.722120 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5898 23:56:54.726337 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5899 23:56:54.728825 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5900 23:56:54.732073
5901 23:56:54.732517
5902 23:56:54.732863 ==
5903 23:56:54.735596 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 23:56:54.738892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 23:56:54.739406 ==
5906 23:56:54.739779
5907 23:56:54.740084
5908 23:56:54.742610 TX Vref Scan disable
5909 23:56:54.743070 == TX Byte 0 ==
5910 23:56:54.749120 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5911 23:56:54.752125 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5912 23:56:54.752793 == TX Byte 1 ==
5913 23:56:54.759034 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5914 23:56:54.762140 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5915 23:56:54.762593 ==
5916 23:56:54.765052 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 23:56:54.768713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 23:56:54.769150 ==
5919 23:56:54.769568
5920 23:56:54.769959
5921 23:56:54.771537 TX Vref Scan disable
5922 23:56:54.775015 == TX Byte 0 ==
5923 23:56:54.778196 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5924 23:56:54.781695 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5925 23:56:54.784822 == TX Byte 1 ==
5926 23:56:54.788019 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5927 23:56:54.791531 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5928 23:56:54.795650
5929 23:56:54.796218 [DATLAT]
5930 23:56:54.796618 Freq=933, CH1 RK1
5931 23:56:54.796932
5932 23:56:54.798141 DATLAT Default: 0xb
5933 23:56:54.798550 0, 0xFFFF, sum = 0
5934 23:56:54.801495 1, 0xFFFF, sum = 0
5935 23:56:54.801993 2, 0xFFFF, sum = 0
5936 23:56:54.804387 3, 0xFFFF, sum = 0
5937 23:56:54.804875 4, 0xFFFF, sum = 0
5938 23:56:54.808205 5, 0xFFFF, sum = 0
5939 23:56:54.811069 6, 0xFFFF, sum = 0
5940 23:56:54.811512 7, 0xFFFF, sum = 0
5941 23:56:54.814499 8, 0xFFFF, sum = 0
5942 23:56:54.814924 9, 0xFFFF, sum = 0
5943 23:56:54.817603 10, 0x0, sum = 1
5944 23:56:54.818136 11, 0x0, sum = 2
5945 23:56:54.818482 12, 0x0, sum = 3
5946 23:56:54.821151 13, 0x0, sum = 4
5947 23:56:54.821613 best_step = 11
5948 23:56:54.821943
5949 23:56:54.824484 ==
5950 23:56:54.824898 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 23:56:54.830789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 23:56:54.831405 ==
5953 23:56:54.831953 RX Vref Scan: 0
5954 23:56:54.832492
5955 23:56:54.834512 RX Vref 0 -> 0, step: 1
5956 23:56:54.834994
5957 23:56:54.838345 RX Delay -53 -> 252, step: 4
5958 23:56:54.841546 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5959 23:56:54.847707 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5960 23:56:54.851090 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5961 23:56:54.854168 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5962 23:56:54.858260 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5963 23:56:54.861290 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5964 23:56:54.867487 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5965 23:56:54.870743 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5966 23:56:54.873923 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5967 23:56:54.877144 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5968 23:56:54.880305 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5969 23:56:54.883868 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5970 23:56:54.890215 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5971 23:56:54.893722 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5972 23:56:54.897239 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5973 23:56:54.900221 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5974 23:56:54.900645 ==
5975 23:56:54.903639 Dram Type= 6, Freq= 0, CH_1, rank 1
5976 23:56:54.910116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5977 23:56:54.910533 ==
5978 23:56:54.910858 DQS Delay:
5979 23:56:54.913200 DQS0 = 0, DQS1 = 0
5980 23:56:54.913640 DQM Delay:
5981 23:56:54.913968 DQM0 = 97, DQM1 = 92
5982 23:56:54.916503 DQ Delay:
5983 23:56:54.920100 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =92
5984 23:56:54.923119 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5985 23:56:54.926643 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =86
5986 23:56:54.929626 DQ12 =100, DQ13 =98, DQ14 =96, DQ15 =100
5987 23:56:54.929723
5988 23:56:54.929794
5989 23:56:54.936018 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5990 23:56:54.939358 CH1 RK1: MR19=505, MR18=B22
5991 23:56:54.945688 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5992 23:56:54.949244 [RxdqsGatingPostProcess] freq 933
5993 23:56:54.955762 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5994 23:56:54.955914 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 23:56:54.959123 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 23:56:54.962194 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 23:56:54.965474 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 23:56:54.968918 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 23:56:54.973017 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 23:56:54.976370 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 23:56:54.979317 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 23:56:54.982650 Pre-setting of DQS Precalculation
6003 23:56:54.989253 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6004 23:56:54.995493 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6005 23:56:55.002084 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6006 23:56:55.002455
6007 23:56:55.002768
6008 23:56:55.005852 [Calibration Summary] 1866 Mbps
6009 23:56:55.006210 CH 0, Rank 0
6010 23:56:55.009407 SW Impedance : PASS
6011 23:56:55.012392 DUTY Scan : NO K
6012 23:56:55.012910 ZQ Calibration : PASS
6013 23:56:55.015233 Jitter Meter : NO K
6014 23:56:55.018891 CBT Training : PASS
6015 23:56:55.019317 Write leveling : PASS
6016 23:56:55.021937 RX DQS gating : PASS
6017 23:56:55.025242 RX DQ/DQS(RDDQC) : PASS
6018 23:56:55.025721 TX DQ/DQS : PASS
6019 23:56:55.029016 RX DATLAT : PASS
6020 23:56:55.029472 RX DQ/DQS(Engine): PASS
6021 23:56:55.032008 TX OE : NO K
6022 23:56:55.032442 All Pass.
6023 23:56:55.032772
6024 23:56:55.035188 CH 0, Rank 1
6025 23:56:55.038202 SW Impedance : PASS
6026 23:56:55.038619 DUTY Scan : NO K
6027 23:56:55.041763 ZQ Calibration : PASS
6028 23:56:55.042177 Jitter Meter : NO K
6029 23:56:55.044838 CBT Training : PASS
6030 23:56:55.048614 Write leveling : PASS
6031 23:56:55.049041 RX DQS gating : PASS
6032 23:56:55.051389 RX DQ/DQS(RDDQC) : PASS
6033 23:56:55.054970 TX DQ/DQS : PASS
6034 23:56:55.055473 RX DATLAT : PASS
6035 23:56:55.058407 RX DQ/DQS(Engine): PASS
6036 23:56:55.061585 TX OE : NO K
6037 23:56:55.062010 All Pass.
6038 23:56:55.062408
6039 23:56:55.062715 CH 1, Rank 0
6040 23:56:55.064702 SW Impedance : PASS
6041 23:56:55.067943 DUTY Scan : NO K
6042 23:56:55.068377 ZQ Calibration : PASS
6043 23:56:55.071668 Jitter Meter : NO K
6044 23:56:55.074919 CBT Training : PASS
6045 23:56:55.075512 Write leveling : PASS
6046 23:56:55.078210 RX DQS gating : PASS
6047 23:56:55.081356 RX DQ/DQS(RDDQC) : PASS
6048 23:56:55.081788 TX DQ/DQS : PASS
6049 23:56:55.084566 RX DATLAT : PASS
6050 23:56:55.087517 RX DQ/DQS(Engine): PASS
6051 23:56:55.087959 TX OE : NO K
6052 23:56:55.091056 All Pass.
6053 23:56:55.091424
6054 23:56:55.091736 CH 1, Rank 1
6055 23:56:55.094359 SW Impedance : PASS
6056 23:56:55.094714 DUTY Scan : NO K
6057 23:56:55.097549 ZQ Calibration : PASS
6058 23:56:55.101123 Jitter Meter : NO K
6059 23:56:55.101549 CBT Training : PASS
6060 23:56:55.104639 Write leveling : PASS
6061 23:56:55.108088 RX DQS gating : PASS
6062 23:56:55.108444 RX DQ/DQS(RDDQC) : PASS
6063 23:56:55.110879 TX DQ/DQS : PASS
6064 23:56:55.111386 RX DATLAT : PASS
6065 23:56:55.114496 RX DQ/DQS(Engine): PASS
6066 23:56:55.118078 TX OE : NO K
6067 23:56:55.118519 All Pass.
6068 23:56:55.118877
6069 23:56:55.120474 DramC Write-DBI off
6070 23:56:55.124162 PER_BANK_REFRESH: Hybrid Mode
6071 23:56:55.124611 TX_TRACKING: ON
6072 23:56:55.134104 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6073 23:56:55.136936 [FAST_K] Save calibration result to emmc
6074 23:56:55.140445 dramc_set_vcore_voltage set vcore to 650000
6075 23:56:55.143536 Read voltage for 400, 6
6076 23:56:55.144055 Vio18 = 0
6077 23:56:55.144389 Vcore = 650000
6078 23:56:55.146757 Vdram = 0
6079 23:56:55.147243 Vddq = 0
6080 23:56:55.147609 Vmddr = 0
6081 23:56:55.153535 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6082 23:56:55.156966 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6083 23:56:55.160317 MEM_TYPE=3, freq_sel=20
6084 23:56:55.163643 sv_algorithm_assistance_LP4_800
6085 23:56:55.166504 ============ PULL DRAM RESETB DOWN ============
6086 23:56:55.169931 ========== PULL DRAM RESETB DOWN end =========
6087 23:56:55.177155 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6088 23:56:55.180477 ===================================
6089 23:56:55.183344 LPDDR4 DRAM CONFIGURATION
6090 23:56:55.186540 ===================================
6091 23:56:55.187023 EX_ROW_EN[0] = 0x0
6092 23:56:55.189743 EX_ROW_EN[1] = 0x0
6093 23:56:55.190339 LP4Y_EN = 0x0
6094 23:56:55.193373 WORK_FSP = 0x0
6095 23:56:55.193823 WL = 0x2
6096 23:56:55.196166 RL = 0x2
6097 23:56:55.196621 BL = 0x2
6098 23:56:55.199808 RPST = 0x0
6099 23:56:55.200244 RD_PRE = 0x0
6100 23:56:55.203258 WR_PRE = 0x1
6101 23:56:55.203773 WR_PST = 0x0
6102 23:56:55.206362 DBI_WR = 0x0
6103 23:56:55.209811 DBI_RD = 0x0
6104 23:56:55.210219 OTF = 0x1
6105 23:56:55.212784 ===================================
6106 23:56:55.215974 ===================================
6107 23:56:55.216386 ANA top config
6108 23:56:55.219467 ===================================
6109 23:56:55.223403 DLL_ASYNC_EN = 0
6110 23:56:55.226244 ALL_SLAVE_EN = 1
6111 23:56:55.229612 NEW_RANK_MODE = 1
6112 23:56:55.232702 DLL_IDLE_MODE = 1
6113 23:56:55.233161 LP45_APHY_COMB_EN = 1
6114 23:56:55.235680 TX_ODT_DIS = 1
6115 23:56:55.238948 NEW_8X_MODE = 1
6116 23:56:55.242514 ===================================
6117 23:56:55.246137 ===================================
6118 23:56:55.249624 data_rate = 800
6119 23:56:55.252707 CKR = 1
6120 23:56:55.253181 DQ_P2S_RATIO = 4
6121 23:56:55.255450 ===================================
6122 23:56:55.258848 CA_P2S_RATIO = 4
6123 23:56:55.262593 DQ_CA_OPEN = 0
6124 23:56:55.265528 DQ_SEMI_OPEN = 1
6125 23:56:55.268815 CA_SEMI_OPEN = 1
6126 23:56:55.271934 CA_FULL_RATE = 0
6127 23:56:55.272542 DQ_CKDIV4_EN = 0
6128 23:56:55.275478 CA_CKDIV4_EN = 1
6129 23:56:55.278700 CA_PREDIV_EN = 0
6130 23:56:55.282148 PH8_DLY = 0
6131 23:56:55.285680 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6132 23:56:55.288745 DQ_AAMCK_DIV = 0
6133 23:56:55.291584 CA_AAMCK_DIV = 0
6134 23:56:55.292025 CA_ADMCK_DIV = 4
6135 23:56:55.295142 DQ_TRACK_CA_EN = 0
6136 23:56:55.298987 CA_PICK = 800
6137 23:56:55.301981 CA_MCKIO = 400
6138 23:56:55.304917 MCKIO_SEMI = 400
6139 23:56:55.308365 PLL_FREQ = 3016
6140 23:56:55.311326 DQ_UI_PI_RATIO = 32
6141 23:56:55.314976 CA_UI_PI_RATIO = 32
6142 23:56:55.318212 ===================================
6143 23:56:55.321358 ===================================
6144 23:56:55.321808 memory_type:LPDDR4
6145 23:56:55.324392 GP_NUM : 10
6146 23:56:55.327811 SRAM_EN : 1
6147 23:56:55.328237 MD32_EN : 0
6148 23:56:55.331168 ===================================
6149 23:56:55.334431 [ANA_INIT] >>>>>>>>>>>>>>
6150 23:56:55.338357 <<<<<< [CONFIGURE PHASE]: ANA_TX
6151 23:56:55.341339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6152 23:56:55.344559 ===================================
6153 23:56:55.347842 data_rate = 800,PCW = 0X7400
6154 23:56:55.351353 ===================================
6155 23:56:55.354551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6156 23:56:55.357616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 23:56:55.370336 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 23:56:55.374740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6159 23:56:55.377110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6160 23:56:55.380481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6161 23:56:55.384336 [ANA_INIT] flow start
6162 23:56:55.387076 [ANA_INIT] PLL >>>>>>>>
6163 23:56:55.387506 [ANA_INIT] PLL <<<<<<<<
6164 23:56:55.391262 [ANA_INIT] MIDPI >>>>>>>>
6165 23:56:55.393931 [ANA_INIT] MIDPI <<<<<<<<
6166 23:56:55.394344 [ANA_INIT] DLL >>>>>>>>
6167 23:56:55.397414 [ANA_INIT] flow end
6168 23:56:55.400687 ============ LP4 DIFF to SE enter ============
6169 23:56:55.403680 ============ LP4 DIFF to SE exit ============
6170 23:56:55.407401 [ANA_INIT] <<<<<<<<<<<<<
6171 23:56:55.410641 [Flow] Enable top DCM control >>>>>
6172 23:56:55.413324 [Flow] Enable top DCM control <<<<<
6173 23:56:55.417119 Enable DLL master slave shuffle
6174 23:56:55.423422 ==============================================================
6175 23:56:55.423928 Gating Mode config
6176 23:56:55.429825 ==============================================================
6177 23:56:55.433114 Config description:
6178 23:56:55.440077 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6179 23:56:55.446461 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6180 23:56:55.452828 SELPH_MODE 0: By rank 1: By Phase
6181 23:56:55.460263 ==============================================================
6182 23:56:55.462858 GAT_TRACK_EN = 0
6183 23:56:55.463290 RX_GATING_MODE = 2
6184 23:56:55.466088 RX_GATING_TRACK_MODE = 2
6185 23:56:55.469527 SELPH_MODE = 1
6186 23:56:55.472560 PICG_EARLY_EN = 1
6187 23:56:55.475957 VALID_LAT_VALUE = 1
6188 23:56:55.482489 ==============================================================
6189 23:56:55.485887 Enter into Gating configuration >>>>
6190 23:56:55.489677 Exit from Gating configuration <<<<
6191 23:56:55.492398 Enter into DVFS_PRE_config >>>>>
6192 23:56:55.502346 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6193 23:56:55.505744 Exit from DVFS_PRE_config <<<<<
6194 23:56:55.509333 Enter into PICG configuration >>>>
6195 23:56:55.512105 Exit from PICG configuration <<<<
6196 23:56:55.515404 [RX_INPUT] configuration >>>>>
6197 23:56:55.518918 [RX_INPUT] configuration <<<<<
6198 23:56:55.521970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6199 23:56:55.528660 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6200 23:56:55.535267 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 23:56:55.542038 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 23:56:55.548309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 23:56:55.551570 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 23:56:55.558111 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6205 23:56:55.561541 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6206 23:56:55.564969 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6207 23:56:55.568421 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6208 23:56:55.575177 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6209 23:56:55.578505 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6210 23:56:55.581142 ===================================
6211 23:56:55.584580 LPDDR4 DRAM CONFIGURATION
6212 23:56:55.587645 ===================================
6213 23:56:55.588082 EX_ROW_EN[0] = 0x0
6214 23:56:55.591537 EX_ROW_EN[1] = 0x0
6215 23:56:55.591969 LP4Y_EN = 0x0
6216 23:56:55.594838 WORK_FSP = 0x0
6217 23:56:55.595271 WL = 0x2
6218 23:56:55.598120 RL = 0x2
6219 23:56:55.601138 BL = 0x2
6220 23:56:55.601637 RPST = 0x0
6221 23:56:55.604761 RD_PRE = 0x0
6222 23:56:55.605190 WR_PRE = 0x1
6223 23:56:55.607390 WR_PST = 0x0
6224 23:56:55.607820 DBI_WR = 0x0
6225 23:56:55.610847 DBI_RD = 0x0
6226 23:56:55.611278 OTF = 0x1
6227 23:56:55.614323 ===================================
6228 23:56:55.618109 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6229 23:56:55.624267 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6230 23:56:55.627798 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 23:56:55.630983 ===================================
6232 23:56:55.634266 LPDDR4 DRAM CONFIGURATION
6233 23:56:55.637751 ===================================
6234 23:56:55.638184 EX_ROW_EN[0] = 0x10
6235 23:56:55.640634 EX_ROW_EN[1] = 0x0
6236 23:56:55.641067 LP4Y_EN = 0x0
6237 23:56:55.643871 WORK_FSP = 0x0
6238 23:56:55.644303 WL = 0x2
6239 23:56:55.647151 RL = 0x2
6240 23:56:55.651015 BL = 0x2
6241 23:56:55.651444 RPST = 0x0
6242 23:56:55.653921 RD_PRE = 0x0
6243 23:56:55.654354 WR_PRE = 0x1
6244 23:56:55.657811 WR_PST = 0x0
6245 23:56:55.658240 DBI_WR = 0x0
6246 23:56:55.660925 DBI_RD = 0x0
6247 23:56:55.661471 OTF = 0x1
6248 23:56:55.663670 ===================================
6249 23:56:55.670670 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6250 23:56:55.674240 nWR fixed to 30
6251 23:56:55.677979 [ModeRegInit_LP4] CH0 RK0
6252 23:56:55.678413 [ModeRegInit_LP4] CH0 RK1
6253 23:56:55.681087 [ModeRegInit_LP4] CH1 RK0
6254 23:56:55.684674 [ModeRegInit_LP4] CH1 RK1
6255 23:56:55.685104 match AC timing 19
6256 23:56:55.690759 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6257 23:56:55.694011 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6258 23:56:55.697317 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6259 23:56:55.703941 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6260 23:56:55.706749 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6261 23:56:55.706834 ==
6262 23:56:55.710343 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 23:56:55.713532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 23:56:55.713616 ==
6265 23:56:55.720420 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6266 23:56:55.727094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6267 23:56:55.730022 [CA 0] Center 36 (8~64) winsize 57
6268 23:56:55.733550 [CA 1] Center 36 (8~64) winsize 57
6269 23:56:55.737410 [CA 2] Center 36 (8~64) winsize 57
6270 23:56:55.740206 [CA 3] Center 36 (8~64) winsize 57
6271 23:56:55.743799 [CA 4] Center 36 (8~64) winsize 57
6272 23:56:55.743885 [CA 5] Center 36 (8~64) winsize 57
6273 23:56:55.747006
6274 23:56:55.750008 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6275 23:56:55.750165
6276 23:56:55.753509 [CATrainingPosCal] consider 1 rank data
6277 23:56:55.756848 u2DelayCellTimex100 = 270/100 ps
6278 23:56:55.760085 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 23:56:55.763067 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 23:56:55.766777 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 23:56:55.769710 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 23:56:55.773234 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 23:56:55.776664 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 23:56:55.776841
6285 23:56:55.779990 CA PerBit enable=1, Macro0, CA PI delay=36
6286 23:56:55.780174
6287 23:56:55.783110 [CBTSetCACLKResult] CA Dly = 36
6288 23:56:55.786452 CS Dly: 1 (0~32)
6289 23:56:55.786639 ==
6290 23:56:55.789934 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 23:56:55.793190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 23:56:55.793343 ==
6293 23:56:55.799594 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6294 23:56:55.806141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6295 23:56:55.809568 [CA 0] Center 36 (8~64) winsize 57
6296 23:56:55.812720 [CA 1] Center 36 (8~64) winsize 57
6297 23:56:55.815993 [CA 2] Center 36 (8~64) winsize 57
6298 23:56:55.816298 [CA 3] Center 36 (8~64) winsize 57
6299 23:56:55.819687 [CA 4] Center 36 (8~64) winsize 57
6300 23:56:55.822818 [CA 5] Center 36 (8~64) winsize 57
6301 23:56:55.823286
6302 23:56:55.829737 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6303 23:56:55.830188
6304 23:56:55.832706 [CATrainingPosCal] consider 2 rank data
6305 23:56:55.836112 u2DelayCellTimex100 = 270/100 ps
6306 23:56:55.839319 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 23:56:55.842853 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 23:56:55.846666 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 23:56:55.849190 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 23:56:55.852567 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 23:56:55.855833 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 23:56:55.856261
6313 23:56:55.859062 CA PerBit enable=1, Macro0, CA PI delay=36
6314 23:56:55.859472
6315 23:56:55.862846 [CBTSetCACLKResult] CA Dly = 36
6316 23:56:55.865542 CS Dly: 1 (0~32)
6317 23:56:55.865954
6318 23:56:55.869338 ----->DramcWriteLeveling(PI) begin...
6319 23:56:55.869782 ==
6320 23:56:55.872423 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 23:56:55.875694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 23:56:55.876110 ==
6323 23:56:55.878803 Write leveling (Byte 0): 40 => 8
6324 23:56:55.882394 Write leveling (Byte 1): 40 => 8
6325 23:56:55.885418 DramcWriteLeveling(PI) end<-----
6326 23:56:55.885790
6327 23:56:55.886183 ==
6328 23:56:55.888997 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 23:56:55.892970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 23:56:55.893434 ==
6331 23:56:55.895702 [Gating] SW mode calibration
6332 23:56:55.902128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6333 23:56:55.907962 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6334 23:56:55.911035 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 23:56:55.917540 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 23:56:55.920777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 23:56:55.924154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 23:56:55.930928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 23:56:55.934700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 23:56:55.937517 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 23:56:55.943887 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 23:56:55.947283 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 23:56:55.951126 Total UI for P1: 0, mck2ui 16
6344 23:56:55.954147 best dqsien dly found for B0: ( 0, 14, 24)
6345 23:56:55.957638 Total UI for P1: 0, mck2ui 16
6346 23:56:55.960778 best dqsien dly found for B1: ( 0, 14, 24)
6347 23:56:55.963853 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6348 23:56:55.967517 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6349 23:56:55.967664
6350 23:56:55.970564 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 23:56:55.974579 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 23:56:55.977065 [Gating] SW calibration Done
6353 23:56:55.977394 ==
6354 23:56:55.980622 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 23:56:55.987561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 23:56:55.987816 ==
6357 23:56:55.988004 RX Vref Scan: 0
6358 23:56:55.988177
6359 23:56:55.990526 RX Vref 0 -> 0, step: 1
6360 23:56:55.990818
6361 23:56:55.993845 RX Delay -410 -> 252, step: 16
6362 23:56:55.997397 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6363 23:56:56.000497 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6364 23:56:56.006779 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6365 23:56:56.010693 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6366 23:56:56.013511 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6367 23:56:56.016349 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6368 23:56:56.023001 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6369 23:56:56.026200 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6370 23:56:56.029421 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6371 23:56:56.032777 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6372 23:56:56.039769 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6373 23:56:56.042738 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6374 23:56:56.046752 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6375 23:56:56.053003 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6376 23:56:56.055949 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6377 23:56:56.060033 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6378 23:56:56.060119 ==
6379 23:56:56.063041 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 23:56:56.066252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 23:56:56.066333 ==
6382 23:56:56.069214 DQS Delay:
6383 23:56:56.069353 DQS0 = 35, DQS1 = 51
6384 23:56:56.072638 DQM Delay:
6385 23:56:56.072710 DQM0 = 6, DQM1 = 10
6386 23:56:56.075743 DQ Delay:
6387 23:56:56.075840 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6388 23:56:56.079204 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6389 23:56:56.082371 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6390 23:56:56.086190 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6391 23:56:56.086258
6392 23:56:56.086317
6393 23:56:56.086373 ==
6394 23:56:56.089169 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 23:56:56.095789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 23:56:56.095870 ==
6397 23:56:56.095934
6398 23:56:56.095991
6399 23:56:56.096047 TX Vref Scan disable
6400 23:56:56.099195 == TX Byte 0 ==
6401 23:56:56.102469 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 23:56:56.105336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 23:56:56.108834 == TX Byte 1 ==
6404 23:56:56.111979 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 23:56:56.115145 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 23:56:56.118663 ==
6407 23:56:56.118732 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 23:56:56.125141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 23:56:56.125255 ==
6410 23:56:56.125343
6411 23:56:56.125406
6412 23:56:56.128885 TX Vref Scan disable
6413 23:56:56.128971 == TX Byte 0 ==
6414 23:56:56.132137 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 23:56:56.138456 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 23:56:56.138537 == TX Byte 1 ==
6417 23:56:56.141947 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 23:56:56.148732 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 23:56:56.149320
6420 23:56:56.149817 [DATLAT]
6421 23:56:56.150263 Freq=400, CH0 RK0
6422 23:56:56.150643
6423 23:56:56.152010 DATLAT Default: 0xf
6424 23:56:56.155076 0, 0xFFFF, sum = 0
6425 23:56:56.155539 1, 0xFFFF, sum = 0
6426 23:56:56.158242 2, 0xFFFF, sum = 0
6427 23:56:56.158658 3, 0xFFFF, sum = 0
6428 23:56:56.161650 4, 0xFFFF, sum = 0
6429 23:56:56.162083 5, 0xFFFF, sum = 0
6430 23:56:56.164820 6, 0xFFFF, sum = 0
6431 23:56:56.165231 7, 0xFFFF, sum = 0
6432 23:56:56.169058 8, 0xFFFF, sum = 0
6433 23:56:56.169511 9, 0xFFFF, sum = 0
6434 23:56:56.171371 10, 0xFFFF, sum = 0
6435 23:56:56.171812 11, 0xFFFF, sum = 0
6436 23:56:56.175356 12, 0xFFFF, sum = 0
6437 23:56:56.175800 13, 0x0, sum = 1
6438 23:56:56.178442 14, 0x0, sum = 2
6439 23:56:56.178884 15, 0x0, sum = 3
6440 23:56:56.181818 16, 0x0, sum = 4
6441 23:56:56.182262 best_step = 14
6442 23:56:56.182587
6443 23:56:56.182959 ==
6444 23:56:56.184689 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 23:56:56.191429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 23:56:56.191927 ==
6447 23:56:56.192268 RX Vref Scan: 1
6448 23:56:56.192614
6449 23:56:56.194988 RX Vref 0 -> 0, step: 1
6450 23:56:56.195354
6451 23:56:56.197781 RX Delay -343 -> 252, step: 8
6452 23:56:56.198178
6453 23:56:56.201225 Set Vref, RX VrefLevel [Byte0]: 54
6454 23:56:56.204568 [Byte1]: 59
6455 23:56:56.205108
6456 23:56:56.207912 Final RX Vref Byte 0 = 54 to rank0
6457 23:56:56.210865 Final RX Vref Byte 1 = 59 to rank0
6458 23:56:56.214518 Final RX Vref Byte 0 = 54 to rank1
6459 23:56:56.217482 Final RX Vref Byte 1 = 59 to rank1==
6460 23:56:56.221486 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 23:56:56.227664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 23:56:56.228192 ==
6463 23:56:56.228564 DQS Delay:
6464 23:56:56.231219 DQS0 = 44, DQS1 = 60
6465 23:56:56.231628 DQM Delay:
6466 23:56:56.232030 DQM0 = 10, DQM1 = 16
6467 23:56:56.234061 DQ Delay:
6468 23:56:56.237319 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6469 23:56:56.240449 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6470 23:56:56.240973 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6471 23:56:56.244149 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6472 23:56:56.247244
6473 23:56:56.247703
6474 23:56:56.253743 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b8e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6475 23:56:56.256762 CH0 RK0: MR19=C0C, MR18=9B8E
6476 23:56:56.263756 CH0_RK0: MR19=0xC0C, MR18=0x9B8E, DQSOSC=390, MR23=63, INC=388, DEC=258
6477 23:56:56.264171 ==
6478 23:56:56.266791 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 23:56:56.270501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 23:56:56.270916 ==
6481 23:56:56.273444 [Gating] SW mode calibration
6482 23:56:56.280273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6483 23:56:56.286894 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6484 23:56:56.290114 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 23:56:56.293934 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 23:56:56.299665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 23:56:56.303078 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 23:56:56.306135 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 23:56:56.312910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 23:56:56.316718 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 23:56:56.319655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 23:56:56.325995 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 23:56:56.329202 Total UI for P1: 0, mck2ui 16
6494 23:56:56.332655 best dqsien dly found for B0: ( 0, 14, 24)
6495 23:56:56.336213 Total UI for P1: 0, mck2ui 16
6496 23:56:56.339166 best dqsien dly found for B1: ( 0, 14, 24)
6497 23:56:56.343123 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6498 23:56:56.345844 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6499 23:56:56.346256
6500 23:56:56.349417 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 23:56:56.352367 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 23:56:56.355726 [Gating] SW calibration Done
6503 23:56:56.356277 ==
6504 23:56:56.358943 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 23:56:56.362367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 23:56:56.362890 ==
6507 23:56:56.365516 RX Vref Scan: 0
6508 23:56:56.366091
6509 23:56:56.369202 RX Vref 0 -> 0, step: 1
6510 23:56:56.369658
6511 23:56:56.369982 RX Delay -410 -> 252, step: 16
6512 23:56:56.375800 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6513 23:56:56.379348 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6514 23:56:56.382357 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6515 23:56:56.389172 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6516 23:56:56.392366 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6517 23:56:56.395979 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6518 23:56:56.398845 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6519 23:56:56.405401 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6520 23:56:56.408970 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6521 23:56:56.412420 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6522 23:56:56.415354 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6523 23:56:56.421668 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6524 23:56:56.425423 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6525 23:56:56.428429 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6526 23:56:56.431608 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6527 23:56:56.438526 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6528 23:56:56.438934 ==
6529 23:56:56.441752 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 23:56:56.444832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 23:56:56.445504 ==
6532 23:56:56.446055 DQS Delay:
6533 23:56:56.449563 DQS0 = 35, DQS1 = 59
6534 23:56:56.450027 DQM Delay:
6535 23:56:56.451669 DQM0 = 6, DQM1 = 17
6536 23:56:56.452045 DQ Delay:
6537 23:56:56.455342 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6538 23:56:56.458018 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6539 23:56:56.461325 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6540 23:56:56.464657 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6541 23:56:56.465094
6542 23:56:56.465556
6543 23:56:56.465944 ==
6544 23:56:56.467929 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 23:56:56.471044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 23:56:56.471627 ==
6547 23:56:56.474324
6548 23:56:56.474727
6549 23:56:56.475053 TX Vref Scan disable
6550 23:56:56.477773 == TX Byte 0 ==
6551 23:56:56.480830 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6552 23:56:56.484176 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6553 23:56:56.487352 == TX Byte 1 ==
6554 23:56:56.490858 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6555 23:56:56.494185 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6556 23:56:56.494641 ==
6557 23:56:56.497636 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 23:56:56.503838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 23:56:56.504302 ==
6560 23:56:56.504666
6561 23:56:56.504999
6562 23:56:56.505458 TX Vref Scan disable
6563 23:56:56.507241 == TX Byte 0 ==
6564 23:56:56.510569 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6565 23:56:56.513599 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6566 23:56:56.516753 == TX Byte 1 ==
6567 23:56:56.520498 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6568 23:56:56.523619 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6569 23:56:56.524107
6570 23:56:56.526844 [DATLAT]
6571 23:56:56.527310 Freq=400, CH0 RK1
6572 23:56:56.527676
6573 23:56:56.530134 DATLAT Default: 0xe
6574 23:56:56.530657 0, 0xFFFF, sum = 0
6575 23:56:56.533309 1, 0xFFFF, sum = 0
6576 23:56:56.533677 2, 0xFFFF, sum = 0
6577 23:56:56.536864 3, 0xFFFF, sum = 0
6578 23:56:56.537379 4, 0xFFFF, sum = 0
6579 23:56:56.540161 5, 0xFFFF, sum = 0
6580 23:56:56.540830 6, 0xFFFF, sum = 0
6581 23:56:56.543415 7, 0xFFFF, sum = 0
6582 23:56:56.546792 8, 0xFFFF, sum = 0
6583 23:56:56.547209 9, 0xFFFF, sum = 0
6584 23:56:56.550026 10, 0xFFFF, sum = 0
6585 23:56:56.550578 11, 0xFFFF, sum = 0
6586 23:56:56.553190 12, 0xFFFF, sum = 0
6587 23:56:56.553701 13, 0x0, sum = 1
6588 23:56:56.556906 14, 0x0, sum = 2
6589 23:56:56.557404 15, 0x0, sum = 3
6590 23:56:56.559797 16, 0x0, sum = 4
6591 23:56:56.560176 best_step = 14
6592 23:56:56.560514
6593 23:56:56.560892 ==
6594 23:56:56.563236 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 23:56:56.566491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 23:56:56.567130 ==
6597 23:56:56.569459 RX Vref Scan: 0
6598 23:56:56.569875
6599 23:56:56.573528 RX Vref 0 -> 0, step: 1
6600 23:56:56.574012
6601 23:56:56.574394 RX Delay -359 -> 252, step: 8
6602 23:56:56.581858 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6603 23:56:56.584911 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6604 23:56:56.588432 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6605 23:56:56.594786 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6606 23:56:56.597969 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6607 23:56:56.601698 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6608 23:56:56.604772 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6609 23:56:56.611698 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6610 23:56:56.615191 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6611 23:56:56.618147 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6612 23:56:56.621501 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6613 23:56:56.628136 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6614 23:56:56.631054 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6615 23:56:56.635166 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6616 23:56:56.637861 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6617 23:56:56.644630 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6618 23:56:56.645089 ==
6619 23:56:56.647371 Dram Type= 6, Freq= 0, CH_0, rank 1
6620 23:56:56.651535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 23:56:56.651946 ==
6622 23:56:56.652346 DQS Delay:
6623 23:56:56.654329 DQS0 = 44, DQS1 = 60
6624 23:56:56.654736 DQM Delay:
6625 23:56:56.657362 DQM0 = 9, DQM1 = 15
6626 23:56:56.657807 DQ Delay:
6627 23:56:56.661212 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6628 23:56:56.664380 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6629 23:56:56.667813 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6630 23:56:56.671160 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6631 23:56:56.671640
6632 23:56:56.672223
6633 23:56:56.680924 [DQSOSCAuto] RK1, (LSB)MR18= 0x857e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6634 23:56:56.681588 CH0 RK1: MR19=C0C, MR18=857E
6635 23:56:56.687433 CH0_RK1: MR19=0xC0C, MR18=0x857E, DQSOSC=393, MR23=63, INC=382, DEC=254
6636 23:56:56.690061 [RxdqsGatingPostProcess] freq 400
6637 23:56:56.696622 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6638 23:56:56.700083 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 23:56:56.703675 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 23:56:56.706727 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 23:56:56.710476 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 23:56:56.713338 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 23:56:56.713754 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 23:56:56.717170 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 23:56:56.719782 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 23:56:56.723407 Pre-setting of DQS Precalculation
6647 23:56:56.729702 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6648 23:56:56.730164 ==
6649 23:56:56.733332 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 23:56:56.736692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 23:56:56.737397 ==
6652 23:56:56.743328 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6653 23:56:56.749875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6654 23:56:56.753141 [CA 0] Center 36 (8~64) winsize 57
6655 23:56:56.756101 [CA 1] Center 36 (8~64) winsize 57
6656 23:56:56.760035 [CA 2] Center 36 (8~64) winsize 57
6657 23:56:56.760451 [CA 3] Center 36 (8~64) winsize 57
6658 23:56:56.763181 [CA 4] Center 36 (8~64) winsize 57
6659 23:56:56.766209 [CA 5] Center 36 (8~64) winsize 57
6660 23:56:56.766678
6661 23:56:56.772782 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6662 23:56:56.773230
6663 23:56:56.776196 [CATrainingPosCal] consider 1 rank data
6664 23:56:56.779518 u2DelayCellTimex100 = 270/100 ps
6665 23:56:56.782529 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 23:56:56.786018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 23:56:56.789245 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 23:56:56.792754 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 23:56:56.796220 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 23:56:56.799314 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 23:56:56.799792
6672 23:56:56.802813 CA PerBit enable=1, Macro0, CA PI delay=36
6673 23:56:56.803248
6674 23:56:56.805588 [CBTSetCACLKResult] CA Dly = 36
6675 23:56:56.809071 CS Dly: 1 (0~32)
6676 23:56:56.809688 ==
6677 23:56:56.812185 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 23:56:56.815807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 23:56:56.816225 ==
6680 23:56:56.822116 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6681 23:56:56.828553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6682 23:56:56.832496 [CA 0] Center 36 (8~64) winsize 57
6683 23:56:56.835373 [CA 1] Center 36 (8~64) winsize 57
6684 23:56:56.835832 [CA 2] Center 36 (8~64) winsize 57
6685 23:56:56.839051 [CA 3] Center 36 (8~64) winsize 57
6686 23:56:56.842313 [CA 4] Center 36 (8~64) winsize 57
6687 23:56:56.845373 [CA 5] Center 36 (8~64) winsize 57
6688 23:56:56.845957
6689 23:56:56.848699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6690 23:56:56.849112
6691 23:56:56.855619 [CATrainingPosCal] consider 2 rank data
6692 23:56:56.856041 u2DelayCellTimex100 = 270/100 ps
6693 23:56:56.861775 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 23:56:56.864916 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 23:56:56.868238 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 23:56:56.871404 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 23:56:56.875286 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 23:56:56.877885 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 23:56:56.878188
6700 23:56:56.881019 CA PerBit enable=1, Macro0, CA PI delay=36
6701 23:56:56.881584
6702 23:56:56.884447 [CBTSetCACLKResult] CA Dly = 36
6703 23:56:56.887900 CS Dly: 1 (0~32)
6704 23:56:56.888219
6705 23:56:56.891171 ----->DramcWriteLeveling(PI) begin...
6706 23:56:56.891471 ==
6707 23:56:56.894406 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 23:56:56.897588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 23:56:56.897891 ==
6710 23:56:56.901290 Write leveling (Byte 0): 40 => 8
6711 23:56:56.905623 Write leveling (Byte 1): 40 => 8
6712 23:56:56.908098 DramcWriteLeveling(PI) end<-----
6713 23:56:56.908394
6714 23:56:56.908627 ==
6715 23:56:56.910949 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 23:56:56.914236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 23:56:56.914532 ==
6718 23:56:56.918236 [Gating] SW mode calibration
6719 23:56:56.923849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6720 23:56:56.930879 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6721 23:56:56.934093 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 23:56:56.940740 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 23:56:56.944073 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 23:56:56.947736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 23:56:56.954096 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 23:56:56.957421 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 23:56:56.960589 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 23:56:56.966893 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 23:56:56.970954 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 23:56:56.973898 Total UI for P1: 0, mck2ui 16
6731 23:56:56.976995 best dqsien dly found for B0: ( 0, 14, 24)
6732 23:56:56.980350 Total UI for P1: 0, mck2ui 16
6733 23:56:56.983137 best dqsien dly found for B1: ( 0, 14, 24)
6734 23:56:56.986707 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6735 23:56:56.990484 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6736 23:56:56.990900
6737 23:56:56.993147 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 23:56:56.996728 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 23:56:56.999878 [Gating] SW calibration Done
6740 23:56:57.000291 ==
6741 23:56:57.003262 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 23:56:57.006783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 23:56:57.009917 ==
6744 23:56:57.010376 RX Vref Scan: 0
6745 23:56:57.010729
6746 23:56:57.013643 RX Vref 0 -> 0, step: 1
6747 23:56:57.014022
6748 23:56:57.016166 RX Delay -410 -> 252, step: 16
6749 23:56:57.019650 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6750 23:56:57.022775 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6751 23:56:57.029368 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6752 23:56:57.032456 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6753 23:56:57.036018 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6754 23:56:57.039409 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6755 23:56:57.045815 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6756 23:56:57.049238 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6757 23:56:57.052274 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6758 23:56:57.055545 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6759 23:56:57.062193 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6760 23:56:57.065814 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6761 23:56:57.068913 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6762 23:56:57.072019 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6763 23:56:57.078531 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6764 23:56:57.082013 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6765 23:56:57.082421 ==
6766 23:56:57.085319 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 23:56:57.088799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 23:56:57.089223 ==
6769 23:56:57.092087 DQS Delay:
6770 23:56:57.092488 DQS0 = 35, DQS1 = 51
6771 23:56:57.095243 DQM Delay:
6772 23:56:57.095629 DQM0 = 6, DQM1 = 14
6773 23:56:57.095962 DQ Delay:
6774 23:56:57.098783 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6775 23:56:57.102140 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6776 23:56:57.105302 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6777 23:56:57.108492 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6778 23:56:57.108898
6779 23:56:57.109241
6780 23:56:57.109580 ==
6781 23:56:57.111944 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 23:56:57.118308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 23:56:57.118774 ==
6784 23:56:57.119104
6785 23:56:57.119484
6786 23:56:57.119779 TX Vref Scan disable
6787 23:56:57.121800 == TX Byte 0 ==
6788 23:56:57.124671 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 23:56:57.131353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 23:56:57.131826 == TX Byte 1 ==
6791 23:56:57.134522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 23:56:57.141311 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 23:56:57.141760 ==
6794 23:56:57.144640 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 23:56:57.147729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 23:56:57.148166 ==
6797 23:56:57.148481
6798 23:56:57.148803
6799 23:56:57.151081 TX Vref Scan disable
6800 23:56:57.151572 == TX Byte 0 ==
6801 23:56:57.154658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 23:56:57.161527 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 23:56:57.162213 == TX Byte 1 ==
6804 23:56:57.164084 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 23:56:57.170973 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 23:56:57.171359
6807 23:56:57.171679 [DATLAT]
6808 23:56:57.172026 Freq=400, CH1 RK0
6809 23:56:57.173890
6810 23:56:57.174287 DATLAT Default: 0xf
6811 23:56:57.177093 0, 0xFFFF, sum = 0
6812 23:56:57.177550 1, 0xFFFF, sum = 0
6813 23:56:57.180929 2, 0xFFFF, sum = 0
6814 23:56:57.181321 3, 0xFFFF, sum = 0
6815 23:56:57.184185 4, 0xFFFF, sum = 0
6816 23:56:57.184631 5, 0xFFFF, sum = 0
6817 23:56:57.187422 6, 0xFFFF, sum = 0
6818 23:56:57.188015 7, 0xFFFF, sum = 0
6819 23:56:57.190466 8, 0xFFFF, sum = 0
6820 23:56:57.190883 9, 0xFFFF, sum = 0
6821 23:56:57.194123 10, 0xFFFF, sum = 0
6822 23:56:57.194545 11, 0xFFFF, sum = 0
6823 23:56:57.197137 12, 0xFFFF, sum = 0
6824 23:56:57.197594 13, 0x0, sum = 1
6825 23:56:57.200833 14, 0x0, sum = 2
6826 23:56:57.201248 15, 0x0, sum = 3
6827 23:56:57.204065 16, 0x0, sum = 4
6828 23:56:57.204632 best_step = 14
6829 23:56:57.205226
6830 23:56:57.205613 ==
6831 23:56:57.207235 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 23:56:57.213718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 23:56:57.214228 ==
6834 23:56:57.214555 RX Vref Scan: 1
6835 23:56:57.214962
6836 23:56:57.216965 RX Vref 0 -> 0, step: 1
6837 23:56:57.217482
6838 23:56:57.220278 RX Delay -343 -> 252, step: 8
6839 23:56:57.220713
6840 23:56:57.224235 Set Vref, RX VrefLevel [Byte0]: 53
6841 23:56:57.226548 [Byte1]: 52
6842 23:56:57.230346
6843 23:56:57.230759 Final RX Vref Byte 0 = 53 to rank0
6844 23:56:57.233759 Final RX Vref Byte 1 = 52 to rank0
6845 23:56:57.236671 Final RX Vref Byte 0 = 53 to rank1
6846 23:56:57.240294 Final RX Vref Byte 1 = 52 to rank1==
6847 23:56:57.243822 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 23:56:57.250453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 23:56:57.250871 ==
6850 23:56:57.251335 DQS Delay:
6851 23:56:57.253298 DQS0 = 44, DQS1 = 56
6852 23:56:57.253715 DQM Delay:
6853 23:56:57.254048 DQM0 = 10, DQM1 = 14
6854 23:56:57.256396 DQ Delay:
6855 23:56:57.259688 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6856 23:56:57.260168 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6857 23:56:57.263006 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6858 23:56:57.266559 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6859 23:56:57.269735
6860 23:56:57.270147
6861 23:56:57.276378 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e95, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6862 23:56:57.279514 CH1 RK0: MR19=C0C, MR18=6E95
6863 23:56:57.286449 CH1_RK0: MR19=0xC0C, MR18=0x6E95, DQSOSC=391, MR23=63, INC=386, DEC=257
6864 23:56:57.287006 ==
6865 23:56:57.289439 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 23:56:57.292685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 23:56:57.293153 ==
6868 23:56:57.295938 [Gating] SW mode calibration
6869 23:56:57.302850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6870 23:56:57.309172 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6871 23:56:57.312142 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 23:56:57.315436 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 23:56:57.322115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 23:56:57.325345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 23:56:57.328568 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 23:56:57.335692 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 23:56:57.338532 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 23:56:57.342046 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 23:56:57.348314 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 23:56:57.351619 Total UI for P1: 0, mck2ui 16
6881 23:56:57.355099 best dqsien dly found for B0: ( 0, 14, 24)
6882 23:56:57.358180 Total UI for P1: 0, mck2ui 16
6883 23:56:57.361797 best dqsien dly found for B1: ( 0, 14, 24)
6884 23:56:57.364972 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6885 23:56:57.368280 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6886 23:56:57.368715
6887 23:56:57.371298 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 23:56:57.374910 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 23:56:57.378139 [Gating] SW calibration Done
6890 23:56:57.378560 ==
6891 23:56:57.381456 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 23:56:57.385200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 23:56:57.385660 ==
6894 23:56:57.388272 RX Vref Scan: 0
6895 23:56:57.388689
6896 23:56:57.391383 RX Vref 0 -> 0, step: 1
6897 23:56:57.391802
6898 23:56:57.392179 RX Delay -410 -> 252, step: 16
6899 23:56:57.398602 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6900 23:56:57.401440 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6901 23:56:57.404758 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6902 23:56:57.411334 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6903 23:56:57.414470 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6904 23:56:57.418377 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6905 23:56:57.420873 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6906 23:56:57.427857 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6907 23:56:57.430849 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6908 23:56:57.434069 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6909 23:56:57.437492 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6910 23:56:57.444076 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6911 23:56:57.447326 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6912 23:56:57.451192 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6913 23:56:57.458195 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6914 23:56:57.460677 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6915 23:56:57.461310 ==
6916 23:56:57.463810 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 23:56:57.467281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 23:56:57.467702 ==
6919 23:56:57.470236 DQS Delay:
6920 23:56:57.470651 DQS0 = 43, DQS1 = 51
6921 23:56:57.470981 DQM Delay:
6922 23:56:57.473564 DQM0 = 8, DQM1 = 14
6923 23:56:57.473983 DQ Delay:
6924 23:56:57.476835 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6925 23:56:57.480434 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6926 23:56:57.483191 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6927 23:56:57.486765 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6928 23:56:57.487337
6929 23:56:57.487877
6930 23:56:57.488353 ==
6931 23:56:57.490444 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 23:56:57.493251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 23:56:57.497080 ==
6934 23:56:57.497540
6935 23:56:57.497873
6936 23:56:57.498191 TX Vref Scan disable
6937 23:56:57.499805 == TX Byte 0 ==
6938 23:56:57.503284 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6939 23:56:57.507335 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6940 23:56:57.509844 == TX Byte 1 ==
6941 23:56:57.513113 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6942 23:56:57.516483 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6943 23:56:57.516929 ==
6944 23:56:57.519717 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 23:56:57.526187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 23:56:57.526610 ==
6947 23:56:57.526944
6948 23:56:57.527250
6949 23:56:57.527544 TX Vref Scan disable
6950 23:56:57.529595 == TX Byte 0 ==
6951 23:56:57.533323 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6952 23:56:57.536592 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6953 23:56:57.539366 == TX Byte 1 ==
6954 23:56:57.543017 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6955 23:56:57.546661 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6956 23:56:57.547260
6957 23:56:57.549591 [DATLAT]
6958 23:56:57.550157 Freq=400, CH1 RK1
6959 23:56:57.550510
6960 23:56:57.553458 DATLAT Default: 0xe
6961 23:56:57.553871 0, 0xFFFF, sum = 0
6962 23:56:57.556182 1, 0xFFFF, sum = 0
6963 23:56:57.556603 2, 0xFFFF, sum = 0
6964 23:56:57.559335 3, 0xFFFF, sum = 0
6965 23:56:57.559754 4, 0xFFFF, sum = 0
6966 23:56:57.562411 5, 0xFFFF, sum = 0
6967 23:56:57.562834 6, 0xFFFF, sum = 0
6968 23:56:57.565788 7, 0xFFFF, sum = 0
6969 23:56:57.566242 8, 0xFFFF, sum = 0
6970 23:56:57.569211 9, 0xFFFF, sum = 0
6971 23:56:57.572084 10, 0xFFFF, sum = 0
6972 23:56:57.572569 11, 0xFFFF, sum = 0
6973 23:56:57.575984 12, 0xFFFF, sum = 0
6974 23:56:57.576424 13, 0x0, sum = 1
6975 23:56:57.579367 14, 0x0, sum = 2
6976 23:56:57.579971 15, 0x0, sum = 3
6977 23:56:57.582240 16, 0x0, sum = 4
6978 23:56:57.582657 best_step = 14
6979 23:56:57.583086
6980 23:56:57.583439 ==
6981 23:56:57.585392 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 23:56:57.588607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 23:56:57.589025 ==
6984 23:56:57.592111 RX Vref Scan: 0
6985 23:56:57.592564
6986 23:56:57.595659 RX Vref 0 -> 0, step: 1
6987 23:56:57.596121
6988 23:56:57.596452 RX Delay -343 -> 252, step: 8
6989 23:56:57.604262 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6990 23:56:57.606969 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6991 23:56:57.610304 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6992 23:56:57.613747 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6993 23:56:57.620625 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6994 23:56:57.623581 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6995 23:56:57.626961 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6996 23:56:57.633494 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6997 23:56:57.636525 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6998 23:56:57.640181 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6999 23:56:57.643297 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
7000 23:56:57.649778 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
7001 23:56:57.653059 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
7002 23:56:57.656279 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
7003 23:56:57.659786 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
7004 23:56:57.666625 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
7005 23:56:57.667214 ==
7006 23:56:57.669743 Dram Type= 6, Freq= 0, CH_1, rank 1
7007 23:56:57.673821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7008 23:56:57.674235 ==
7009 23:56:57.674567 DQS Delay:
7010 23:56:57.676660 DQS0 = 48, DQS1 = 52
7011 23:56:57.677071 DQM Delay:
7012 23:56:57.679355 DQM0 = 11, DQM1 = 10
7013 23:56:57.679436 DQ Delay:
7014 23:56:57.682711 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7015 23:56:57.686016 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7016 23:56:57.689578 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7017 23:56:57.692543 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7018 23:56:57.692623
7019 23:56:57.692686
7020 23:56:57.703249 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cb4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7021 23:56:57.703331 CH1 RK1: MR19=C0C, MR18=7CB4
7022 23:56:57.709227 CH1_RK1: MR19=0xC0C, MR18=0x7CB4, DQSOSC=387, MR23=63, INC=394, DEC=262
7023 23:56:57.712531 [RxdqsGatingPostProcess] freq 400
7024 23:56:57.719589 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7025 23:56:57.722902 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 23:56:57.725694 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 23:56:57.729015 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 23:56:57.732417 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 23:56:57.735737 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 23:56:57.735818 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 23:56:57.739541 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 23:56:57.742643 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 23:56:57.746274 Pre-setting of DQS Precalculation
7034 23:56:57.752207 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7035 23:56:57.758893 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7036 23:56:57.765148 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7037 23:56:57.765230
7038 23:56:57.765336
7039 23:56:57.769001 [Calibration Summary] 800 Mbps
7040 23:56:57.771915 CH 0, Rank 0
7041 23:56:57.771995 SW Impedance : PASS
7042 23:56:57.775738 DUTY Scan : NO K
7043 23:56:57.779032 ZQ Calibration : PASS
7044 23:56:57.779470 Jitter Meter : NO K
7045 23:56:57.782691 CBT Training : PASS
7046 23:56:57.783169 Write leveling : PASS
7047 23:56:57.786539 RX DQS gating : PASS
7048 23:56:57.788761 RX DQ/DQS(RDDQC) : PASS
7049 23:56:57.789186 TX DQ/DQS : PASS
7050 23:56:57.791905 RX DATLAT : PASS
7051 23:56:57.795243 RX DQ/DQS(Engine): PASS
7052 23:56:57.795664 TX OE : NO K
7053 23:56:57.798541 All Pass.
7054 23:56:57.799012
7055 23:56:57.799348 CH 0, Rank 1
7056 23:56:57.802079 SW Impedance : PASS
7057 23:56:57.802500 DUTY Scan : NO K
7058 23:56:57.805090 ZQ Calibration : PASS
7059 23:56:57.808680 Jitter Meter : NO K
7060 23:56:57.809098 CBT Training : PASS
7061 23:56:57.811939 Write leveling : NO K
7062 23:56:57.815130 RX DQS gating : PASS
7063 23:56:57.815550 RX DQ/DQS(RDDQC) : PASS
7064 23:56:57.818375 TX DQ/DQS : PASS
7065 23:56:57.821460 RX DATLAT : PASS
7066 23:56:57.822057 RX DQ/DQS(Engine): PASS
7067 23:56:57.824758 TX OE : NO K
7068 23:56:57.825211 All Pass.
7069 23:56:57.825677
7070 23:56:57.828651 CH 1, Rank 0
7071 23:56:57.829064 SW Impedance : PASS
7072 23:56:57.832064 DUTY Scan : NO K
7073 23:56:57.834981 ZQ Calibration : PASS
7074 23:56:57.835062 Jitter Meter : NO K
7075 23:56:57.837540 CBT Training : PASS
7076 23:56:57.841614 Write leveling : PASS
7077 23:56:57.841704 RX DQS gating : PASS
7078 23:56:57.844334 RX DQ/DQS(RDDQC) : PASS
7079 23:56:57.847272 TX DQ/DQS : PASS
7080 23:56:57.847360 RX DATLAT : PASS
7081 23:56:57.850839 RX DQ/DQS(Engine): PASS
7082 23:56:57.854216 TX OE : NO K
7083 23:56:57.854371 All Pass.
7084 23:56:57.854468
7085 23:56:57.854543 CH 1, Rank 1
7086 23:56:57.857623 SW Impedance : PASS
7087 23:56:57.860877 DUTY Scan : NO K
7088 23:56:57.861034 ZQ Calibration : PASS
7089 23:56:57.864152 Jitter Meter : NO K
7090 23:56:57.868034 CBT Training : PASS
7091 23:56:57.868521 Write leveling : NO K
7092 23:56:57.871205 RX DQS gating : PASS
7093 23:56:57.871623 RX DQ/DQS(RDDQC) : PASS
7094 23:56:57.874363 TX DQ/DQS : PASS
7095 23:56:57.877721 RX DATLAT : PASS
7096 23:56:57.878145 RX DQ/DQS(Engine): PASS
7097 23:56:57.880811 TX OE : NO K
7098 23:56:57.881230 All Pass.
7099 23:56:57.881611
7100 23:56:57.884513 DramC Write-DBI off
7101 23:56:57.887779 PER_BANK_REFRESH: Hybrid Mode
7102 23:56:57.888198 TX_TRACKING: ON
7103 23:56:57.897874 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7104 23:56:57.901126 [FAST_K] Save calibration result to emmc
7105 23:56:57.904223 dramc_set_vcore_voltage set vcore to 725000
7106 23:56:57.907907 Read voltage for 1600, 0
7107 23:56:57.908330 Vio18 = 0
7108 23:56:57.910790 Vcore = 725000
7109 23:56:57.911257 Vdram = 0
7110 23:56:57.911600 Vddq = 0
7111 23:56:57.912008 Vmddr = 0
7112 23:56:57.918107 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7113 23:56:57.923815 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7114 23:56:57.924332 MEM_TYPE=3, freq_sel=13
7115 23:56:57.927523 sv_algorithm_assistance_LP4_3733
7116 23:56:57.930494 ============ PULL DRAM RESETB DOWN ============
7117 23:56:57.937070 ========== PULL DRAM RESETB DOWN end =========
7118 23:56:57.940575 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7119 23:56:57.943660 ===================================
7120 23:56:57.946767 LPDDR4 DRAM CONFIGURATION
7121 23:56:57.950201 ===================================
7122 23:56:57.950629 EX_ROW_EN[0] = 0x0
7123 23:56:57.953912 EX_ROW_EN[1] = 0x0
7124 23:56:57.954457 LP4Y_EN = 0x0
7125 23:56:57.956863 WORK_FSP = 0x1
7126 23:56:57.959953 WL = 0x5
7127 23:56:57.960371 RL = 0x5
7128 23:56:57.963466 BL = 0x2
7129 23:56:57.963882 RPST = 0x0
7130 23:56:57.967061 RD_PRE = 0x0
7131 23:56:57.967479 WR_PRE = 0x1
7132 23:56:57.969827 WR_PST = 0x1
7133 23:56:57.970244 DBI_WR = 0x0
7134 23:56:57.973602 DBI_RD = 0x0
7135 23:56:57.974096 OTF = 0x1
7136 23:56:57.976873 ===================================
7137 23:56:57.980223 ===================================
7138 23:56:57.983286 ANA top config
7139 23:56:57.986349 ===================================
7140 23:56:57.986769 DLL_ASYNC_EN = 0
7141 23:56:57.989880 ALL_SLAVE_EN = 0
7142 23:56:57.992957 NEW_RANK_MODE = 1
7143 23:56:57.996207 DLL_IDLE_MODE = 1
7144 23:56:57.999591 LP45_APHY_COMB_EN = 1
7145 23:56:58.000014 TX_ODT_DIS = 0
7146 23:56:58.002681 NEW_8X_MODE = 1
7147 23:56:58.006237 ===================================
7148 23:56:58.009652 ===================================
7149 23:56:58.013121 data_rate = 3200
7150 23:56:58.015984 CKR = 1
7151 23:56:58.019791 DQ_P2S_RATIO = 8
7152 23:56:58.022986 ===================================
7153 23:56:58.026080 CA_P2S_RATIO = 8
7154 23:56:58.026504 DQ_CA_OPEN = 0
7155 23:56:58.029308 DQ_SEMI_OPEN = 0
7156 23:56:58.032495 CA_SEMI_OPEN = 0
7157 23:56:58.035997 CA_FULL_RATE = 0
7158 23:56:58.039323 DQ_CKDIV4_EN = 0
7159 23:56:58.042428 CA_CKDIV4_EN = 0
7160 23:56:58.042845 CA_PREDIV_EN = 0
7161 23:56:58.045661 PH8_DLY = 12
7162 23:56:58.049245 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7163 23:56:58.052188 DQ_AAMCK_DIV = 4
7164 23:56:58.055587 CA_AAMCK_DIV = 4
7165 23:56:58.059100 CA_ADMCK_DIV = 4
7166 23:56:58.059520 DQ_TRACK_CA_EN = 0
7167 23:56:58.062015 CA_PICK = 1600
7168 23:56:58.065718 CA_MCKIO = 1600
7169 23:56:58.068529 MCKIO_SEMI = 0
7170 23:56:58.072014 PLL_FREQ = 3068
7171 23:56:58.075161 DQ_UI_PI_RATIO = 32
7172 23:56:58.078910 CA_UI_PI_RATIO = 0
7173 23:56:58.081758 ===================================
7174 23:56:58.085710 ===================================
7175 23:56:58.086135 memory_type:LPDDR4
7176 23:56:58.088233 GP_NUM : 10
7177 23:56:58.092186 SRAM_EN : 1
7178 23:56:58.092605 MD32_EN : 0
7179 23:56:58.094943 ===================================
7180 23:56:58.098134 [ANA_INIT] >>>>>>>>>>>>>>
7181 23:56:58.101820 <<<<<< [CONFIGURE PHASE]: ANA_TX
7182 23:56:58.105068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7183 23:56:58.108203 ===================================
7184 23:56:58.111418 data_rate = 3200,PCW = 0X7600
7185 23:56:58.114695 ===================================
7186 23:56:58.117872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7187 23:56:58.124629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 23:56:58.127928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 23:56:58.134337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7190 23:56:58.137977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7191 23:56:58.141089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7192 23:56:58.141566 [ANA_INIT] flow start
7193 23:56:58.144566 [ANA_INIT] PLL >>>>>>>>
7194 23:56:58.147962 [ANA_INIT] PLL <<<<<<<<
7195 23:56:58.148382 [ANA_INIT] MIDPI >>>>>>>>
7196 23:56:58.151057 [ANA_INIT] MIDPI <<<<<<<<
7197 23:56:58.154479 [ANA_INIT] DLL >>>>>>>>
7198 23:56:58.157291 [ANA_INIT] DLL <<<<<<<<
7199 23:56:58.157714 [ANA_INIT] flow end
7200 23:56:58.161141 ============ LP4 DIFF to SE enter ============
7201 23:56:58.168035 ============ LP4 DIFF to SE exit ============
7202 23:56:58.168477 [ANA_INIT] <<<<<<<<<<<<<
7203 23:56:58.170885 [Flow] Enable top DCM control >>>>>
7204 23:56:58.173713 [Flow] Enable top DCM control <<<<<
7205 23:56:58.177406 Enable DLL master slave shuffle
7206 23:56:58.184028 ==============================================================
7207 23:56:58.184490 Gating Mode config
7208 23:56:58.190499 ==============================================================
7209 23:56:58.193758 Config description:
7210 23:56:58.203116 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7211 23:56:58.209996 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7212 23:56:58.213688 SELPH_MODE 0: By rank 1: By Phase
7213 23:56:58.219872 ==============================================================
7214 23:56:58.223188 GAT_TRACK_EN = 1
7215 23:56:58.226448 RX_GATING_MODE = 2
7216 23:56:58.229679 RX_GATING_TRACK_MODE = 2
7217 23:56:58.230096 SELPH_MODE = 1
7218 23:56:58.233236 PICG_EARLY_EN = 1
7219 23:56:58.236233 VALID_LAT_VALUE = 1
7220 23:56:58.243060 ==============================================================
7221 23:56:58.246551 Enter into Gating configuration >>>>
7222 23:56:58.250250 Exit from Gating configuration <<<<
7223 23:56:58.253100 Enter into DVFS_PRE_config >>>>>
7224 23:56:58.262671 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7225 23:56:58.266319 Exit from DVFS_PRE_config <<<<<
7226 23:56:58.269502 Enter into PICG configuration >>>>
7227 23:56:58.272796 Exit from PICG configuration <<<<
7228 23:56:58.276212 [RX_INPUT] configuration >>>>>
7229 23:56:58.279305 [RX_INPUT] configuration <<<<<
7230 23:56:58.282388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7231 23:56:58.289135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7232 23:56:58.296372 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 23:56:58.302803 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 23:56:58.308894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 23:56:58.312201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 23:56:58.319169 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7237 23:56:58.321970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7238 23:56:58.325426 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7239 23:56:58.328944 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7240 23:56:58.335328 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7241 23:56:58.338224 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7242 23:56:58.341774 ===================================
7243 23:56:58.344852 LPDDR4 DRAM CONFIGURATION
7244 23:56:58.348402 ===================================
7245 23:56:58.348818 EX_ROW_EN[0] = 0x0
7246 23:56:58.352161 EX_ROW_EN[1] = 0x0
7247 23:56:58.355157 LP4Y_EN = 0x0
7248 23:56:58.355573 WORK_FSP = 0x1
7249 23:56:58.358164 WL = 0x5
7250 23:56:58.358579 RL = 0x5
7251 23:56:58.361317 BL = 0x2
7252 23:56:58.361862 RPST = 0x0
7253 23:56:58.364967 RD_PRE = 0x0
7254 23:56:58.365419 WR_PRE = 0x1
7255 23:56:58.368327 WR_PST = 0x1
7256 23:56:58.368742 DBI_WR = 0x0
7257 23:56:58.371194 DBI_RD = 0x0
7258 23:56:58.371605 OTF = 0x1
7259 23:56:58.374541 ===================================
7260 23:56:58.378203 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7261 23:56:58.384275 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7262 23:56:58.387709 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 23:56:58.391211 ===================================
7264 23:56:58.394520 LPDDR4 DRAM CONFIGURATION
7265 23:56:58.397548 ===================================
7266 23:56:58.397970 EX_ROW_EN[0] = 0x10
7267 23:56:58.401524 EX_ROW_EN[1] = 0x0
7268 23:56:58.404386 LP4Y_EN = 0x0
7269 23:56:58.404837 WORK_FSP = 0x1
7270 23:56:58.407612 WL = 0x5
7271 23:56:58.408028 RL = 0x5
7272 23:56:58.410895 BL = 0x2
7273 23:56:58.411309 RPST = 0x0
7274 23:56:58.414500 RD_PRE = 0x0
7275 23:56:58.414911 WR_PRE = 0x1
7276 23:56:58.417296 WR_PST = 0x1
7277 23:56:58.417769 DBI_WR = 0x0
7278 23:56:58.420546 DBI_RD = 0x0
7279 23:56:58.420962 OTF = 0x1
7280 23:56:58.423917 ===================================
7281 23:56:58.431115 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7282 23:56:58.431645 ==
7283 23:56:58.433505 Dram Type= 6, Freq= 0, CH_0, rank 0
7284 23:56:58.440532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 23:56:58.440945 ==
7286 23:56:58.441338 [Duty_Offset_Calibration]
7287 23:56:58.443852 B0:2 B1:0 CA:4
7288 23:56:58.444266
7289 23:56:58.446759 [DutyScan_Calibration_Flow] k_type=0
7290 23:56:58.455818
7291 23:56:58.456262 ==CLK 0==
7292 23:56:58.458728 Final CLK duty delay cell = -4
7293 23:56:58.462144 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7294 23:56:58.465122 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7295 23:56:58.468513 [-4] AVG Duty = 4922%(X100)
7296 23:56:58.468927
7297 23:56:58.472139 CH0 CLK Duty spec in!! Max-Min= 218%
7298 23:56:58.475669 [DutyScan_Calibration_Flow] ====Done====
7299 23:56:58.476086
7300 23:56:58.478766 [DutyScan_Calibration_Flow] k_type=1
7301 23:56:58.495850
7302 23:56:58.496357 ==DQS 0 ==
7303 23:56:58.498877 Final DQS duty delay cell = 0
7304 23:56:58.502606 [0] MAX Duty = 5218%(X100), DQS PI = 36
7305 23:56:58.505367 [0] MIN Duty = 5062%(X100), DQS PI = 12
7306 23:56:58.508980 [0] AVG Duty = 5140%(X100)
7307 23:56:58.509434
7308 23:56:58.509769 ==DQS 1 ==
7309 23:56:58.512364 Final DQS duty delay cell = 0
7310 23:56:58.515634 [0] MAX Duty = 5156%(X100), DQS PI = 2
7311 23:56:58.518596 [0] MIN Duty = 4969%(X100), DQS PI = 12
7312 23:56:58.521924 [0] AVG Duty = 5062%(X100)
7313 23:56:58.522407
7314 23:56:58.525583 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7315 23:56:58.526001
7316 23:56:58.528471 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7317 23:56:58.532050 [DutyScan_Calibration_Flow] ====Done====
7318 23:56:58.532462
7319 23:56:58.535209 [DutyScan_Calibration_Flow] k_type=3
7320 23:56:58.552693
7321 23:56:58.553120 ==DQM 0 ==
7322 23:56:58.555957 Final DQM duty delay cell = 0
7323 23:56:58.560118 [0] MAX Duty = 5124%(X100), DQS PI = 22
7324 23:56:58.562690 [0] MIN Duty = 4875%(X100), DQS PI = 54
7325 23:56:58.565627 [0] AVG Duty = 4999%(X100)
7326 23:56:58.565708
7327 23:56:58.565773 ==DQM 1 ==
7328 23:56:58.569217 Final DQM duty delay cell = 0
7329 23:56:58.572156 [0] MAX Duty = 5000%(X100), DQS PI = 2
7330 23:56:58.575388 [0] MIN Duty = 4844%(X100), DQS PI = 14
7331 23:56:58.578977 [0] AVG Duty = 4922%(X100)
7332 23:56:58.579149
7333 23:56:58.582779 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7334 23:56:58.583218
7335 23:56:58.585838 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7336 23:56:58.589611 [DutyScan_Calibration_Flow] ====Done====
7337 23:56:58.590033
7338 23:56:58.592822 [DutyScan_Calibration_Flow] k_type=2
7339 23:56:58.609984
7340 23:56:58.610545 ==DQ 0 ==
7341 23:56:58.613818 Final DQ duty delay cell = 0
7342 23:56:58.616638 [0] MAX Duty = 5124%(X100), DQS PI = 22
7343 23:56:58.619981 [0] MIN Duty = 4938%(X100), DQS PI = 12
7344 23:56:58.620560 [0] AVG Duty = 5031%(X100)
7345 23:56:58.623123
7346 23:56:58.623537 ==DQ 1 ==
7347 23:56:58.626360 Final DQ duty delay cell = 0
7348 23:56:58.629804 [0] MAX Duty = 5187%(X100), DQS PI = 2
7349 23:56:58.632776 [0] MIN Duty = 4938%(X100), DQS PI = 12
7350 23:56:58.633192 [0] AVG Duty = 5062%(X100)
7351 23:56:58.636064
7352 23:56:58.639545 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7353 23:56:58.639962
7354 23:56:58.642711 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7355 23:56:58.646065 [DutyScan_Calibration_Flow] ====Done====
7356 23:56:58.646490 ==
7357 23:56:58.649507 Dram Type= 6, Freq= 0, CH_1, rank 0
7358 23:56:58.652933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7359 23:56:58.653393 ==
7360 23:56:58.656549 [Duty_Offset_Calibration]
7361 23:56:58.656958 B0:0 B1:-1 CA:3
7362 23:56:58.657376
7363 23:56:58.659352 [DutyScan_Calibration_Flow] k_type=0
7364 23:56:58.669235
7365 23:56:58.669682 ==CLK 0==
7366 23:56:58.672662 Final CLK duty delay cell = -4
7367 23:56:58.675589 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7368 23:56:58.678942 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7369 23:56:58.682948 [-4] AVG Duty = 4922%(X100)
7370 23:56:58.683243
7371 23:56:58.686310 CH1 CLK Duty spec in!! Max-Min= 156%
7372 23:56:58.689181 [DutyScan_Calibration_Flow] ====Done====
7373 23:56:58.689533
7374 23:56:58.692605 [DutyScan_Calibration_Flow] k_type=1
7375 23:56:58.708192
7376 23:56:58.708485 ==DQS 0 ==
7377 23:56:58.711990 Final DQS duty delay cell = 0
7378 23:56:58.715724 [0] MAX Duty = 5250%(X100), DQS PI = 30
7379 23:56:58.719186 [0] MIN Duty = 4907%(X100), DQS PI = 40
7380 23:56:58.722155 [0] AVG Duty = 5078%(X100)
7381 23:56:58.722575
7382 23:56:58.722898 ==DQS 1 ==
7383 23:56:58.725197 Final DQS duty delay cell = -4
7384 23:56:58.728597 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7385 23:56:58.731890 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7386 23:56:58.735137 [-4] AVG Duty = 4906%(X100)
7387 23:56:58.735545
7388 23:56:58.738569 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7389 23:56:58.738987
7390 23:56:58.741958 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7391 23:56:58.745351 [DutyScan_Calibration_Flow] ====Done====
7392 23:56:58.745771
7393 23:56:58.748797 [DutyScan_Calibration_Flow] k_type=3
7394 23:56:58.766388
7395 23:56:58.766799 ==DQM 0 ==
7396 23:56:58.769145 Final DQM duty delay cell = 0
7397 23:56:58.772197 [0] MAX Duty = 5031%(X100), DQS PI = 30
7398 23:56:58.775409 [0] MIN Duty = 4782%(X100), DQS PI = 38
7399 23:56:58.778966 [0] AVG Duty = 4906%(X100)
7400 23:56:58.779382
7401 23:56:58.779707 ==DQM 1 ==
7402 23:56:58.782236 Final DQM duty delay cell = 0
7403 23:56:58.785585 [0] MAX Duty = 5000%(X100), DQS PI = 32
7404 23:56:58.788671 [0] MIN Duty = 4813%(X100), DQS PI = 60
7405 23:56:58.792376 [0] AVG Duty = 4906%(X100)
7406 23:56:58.792793
7407 23:56:58.795526 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7408 23:56:58.795997
7409 23:56:58.798922 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7410 23:56:58.802046 [DutyScan_Calibration_Flow] ====Done====
7411 23:56:58.802462
7412 23:56:58.805394 [DutyScan_Calibration_Flow] k_type=2
7413 23:56:58.821943
7414 23:56:58.822445 ==DQ 0 ==
7415 23:56:58.825321 Final DQ duty delay cell = -4
7416 23:56:58.828238 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7417 23:56:58.832152 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7418 23:56:58.834908 [-4] AVG Duty = 4891%(X100)
7419 23:56:58.835361
7420 23:56:58.835689 ==DQ 1 ==
7421 23:56:58.838028 Final DQ duty delay cell = 0
7422 23:56:58.842268 [0] MAX Duty = 5031%(X100), DQS PI = 32
7423 23:56:58.844799 [0] MIN Duty = 4844%(X100), DQS PI = 60
7424 23:56:58.847842 [0] AVG Duty = 4937%(X100)
7425 23:56:58.848384
7426 23:56:58.851051 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7427 23:56:58.851504
7428 23:56:58.855427 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7429 23:56:58.858250 [DutyScan_Calibration_Flow] ====Done====
7430 23:56:58.861121 nWR fixed to 30
7431 23:56:58.864334 [ModeRegInit_LP4] CH0 RK0
7432 23:56:58.864750 [ModeRegInit_LP4] CH0 RK1
7433 23:56:58.867821 [ModeRegInit_LP4] CH1 RK0
7434 23:56:58.871527 [ModeRegInit_LP4] CH1 RK1
7435 23:56:58.871956 match AC timing 5
7436 23:56:58.877838 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7437 23:56:58.881281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7438 23:56:58.884201 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7439 23:56:58.890893 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7440 23:56:58.894138 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7441 23:56:58.897234 [MiockJmeterHQA]
7442 23:56:58.897716
7443 23:56:58.900770 [DramcMiockJmeter] u1RxGatingPI = 0
7444 23:56:58.901194 0 : 4254, 4029
7445 23:56:58.901578 4 : 4252, 4027
7446 23:56:58.904092 8 : 4252, 4026
7447 23:56:58.904511 12 : 4252, 4027
7448 23:56:58.907615 16 : 4253, 4026
7449 23:56:58.908038 20 : 4252, 4027
7450 23:56:58.910319 24 : 4252, 4026
7451 23:56:58.910744 28 : 4253, 4026
7452 23:56:58.913996 32 : 4252, 4027
7453 23:56:58.914423 36 : 4366, 4139
7454 23:56:58.914757 40 : 4366, 4140
7455 23:56:58.917696 44 : 4252, 4027
7456 23:56:58.918120 48 : 4255, 4029
7457 23:56:58.921044 52 : 4360, 4138
7458 23:56:58.921521 56 : 4250, 4027
7459 23:56:58.923989 60 : 4363, 4140
7460 23:56:58.924415 64 : 4250, 4027
7461 23:56:58.927293 68 : 4250, 4027
7462 23:56:58.927781 72 : 4250, 4027
7463 23:56:58.928127 76 : 4252, 4029
7464 23:56:58.930225 80 : 4360, 4138
7465 23:56:58.930650 84 : 4250, 4027
7466 23:56:58.933368 88 : 4361, 4137
7467 23:56:58.933798 92 : 4363, 4140
7468 23:56:58.937357 96 : 4250, 2434
7469 23:56:58.937831 100 : 4253, 0
7470 23:56:58.938237 104 : 4252, 0
7471 23:56:58.939995 108 : 4252, 0
7472 23:56:58.940420 112 : 4253, 0
7473 23:56:58.943653 116 : 4252, 0
7474 23:56:58.944079 120 : 4361, 0
7475 23:56:58.944430 124 : 4365, 0
7476 23:56:58.947256 128 : 4363, 0
7477 23:56:58.947695 132 : 4250, 0
7478 23:56:58.949956 136 : 4250, 0
7479 23:56:58.950382 140 : 4363, 0
7480 23:56:58.950718 144 : 4250, 0
7481 23:56:58.953365 148 : 4250, 0
7482 23:56:58.953829 152 : 4365, 0
7483 23:56:58.956529 156 : 4250, 0
7484 23:56:58.956952 160 : 4360, 0
7485 23:56:58.957322 164 : 4250, 0
7486 23:56:58.960551 168 : 4250, 0
7487 23:56:58.960975 172 : 4362, 0
7488 23:56:58.963330 176 : 4361, 0
7489 23:56:58.963756 180 : 4250, 0
7490 23:56:58.964198 184 : 4250, 0
7491 23:56:58.966633 188 : 4360, 0
7492 23:56:58.967056 192 : 4363, 0
7493 23:56:58.967397 196 : 4250, 0
7494 23:56:58.969855 200 : 4250, 0
7495 23:56:58.970282 204 : 4255, 0
7496 23:56:58.972982 208 : 4253, 0
7497 23:56:58.973517 212 : 4250, 0
7498 23:56:58.973865 216 : 4250, 0
7499 23:56:58.976601 220 : 4252, 738
7500 23:56:58.977114 224 : 4360, 4132
7501 23:56:58.980108 228 : 4250, 4027
7502 23:56:58.980581 232 : 4250, 4026
7503 23:56:58.982820 236 : 4250, 4026
7504 23:56:58.983267 240 : 4250, 4026
7505 23:56:58.986103 244 : 4250, 4026
7506 23:56:58.986526 248 : 4249, 4027
7507 23:56:58.989904 252 : 4250, 4026
7508 23:56:58.990396 256 : 4250, 4026
7509 23:56:58.992930 260 : 4363, 4140
7510 23:56:58.993524 264 : 4250, 4027
7511 23:56:58.996597 268 : 4250, 4026
7512 23:56:58.997021 272 : 4250, 4027
7513 23:56:58.997404 276 : 4363, 4139
7514 23:56:58.999487 280 : 4360, 4138
7515 23:56:58.999914 284 : 4250, 4027
7516 23:56:59.002889 288 : 4250, 4026
7517 23:56:59.003315 292 : 4250, 4027
7518 23:56:59.005565 296 : 4250, 4027
7519 23:56:59.006007 300 : 4250, 4027
7520 23:56:59.009526 304 : 4252, 4029
7521 23:56:59.010001 308 : 4250, 4026
7522 23:56:59.012097 312 : 4363, 4139
7523 23:56:59.012180 316 : 4250, 4027
7524 23:56:59.015358 320 : 4249, 4027
7525 23:56:59.015441 324 : 4250, 4027
7526 23:56:59.018481 328 : 4363, 4140
7527 23:56:59.018563 332 : 4360, 3951
7528 23:56:59.022182 336 : 4249, 1143
7529 23:56:59.022267
7530 23:56:59.022330 MIOCK jitter meter ch=0
7531 23:56:59.022390
7532 23:56:59.025460 1T = (336-100) = 236 dly cells
7533 23:56:59.031987 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7534 23:56:59.032069 ==
7535 23:56:59.034848 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 23:56:59.038849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 23:56:59.038932 ==
7538 23:56:59.045360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 23:56:59.049089 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 23:56:59.055929 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 23:56:59.058600 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 23:56:59.068482 [CA 0] Center 44 (14~74) winsize 61
7543 23:56:59.072242 [CA 1] Center 43 (13~74) winsize 62
7544 23:56:59.075588 [CA 2] Center 39 (10~68) winsize 59
7545 23:56:59.078201 [CA 3] Center 38 (9~68) winsize 60
7546 23:56:59.081552 [CA 4] Center 36 (7~66) winsize 60
7547 23:56:59.085165 [CA 5] Center 36 (6~66) winsize 61
7548 23:56:59.085720
7549 23:56:59.088616 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 23:56:59.089036
7551 23:56:59.095045 [CATrainingPosCal] consider 1 rank data
7552 23:56:59.095469 u2DelayCellTimex100 = 275/100 ps
7553 23:56:59.101525 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7554 23:56:59.104806 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7555 23:56:59.108026 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7556 23:56:59.111738 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7557 23:56:59.115344 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7558 23:56:59.118053 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7559 23:56:59.118474
7560 23:56:59.121051 CA PerBit enable=1, Macro0, CA PI delay=36
7561 23:56:59.121516
7562 23:56:59.124485 [CBTSetCACLKResult] CA Dly = 36
7563 23:56:59.128251 CS Dly: 10 (0~41)
7564 23:56:59.131143 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 23:56:59.134561 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 23:56:59.134981 ==
7567 23:56:59.137466 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 23:56:59.144053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 23:56:59.144477 ==
7570 23:56:59.147592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 23:56:59.154171 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 23:56:59.157248 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 23:56:59.163920 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 23:56:59.172563 [CA 0] Center 44 (14~75) winsize 62
7575 23:56:59.175291 [CA 1] Center 44 (14~74) winsize 61
7576 23:56:59.178780 [CA 2] Center 39 (10~69) winsize 60
7577 23:56:59.182111 [CA 3] Center 39 (10~68) winsize 59
7578 23:56:59.185542 [CA 4] Center 37 (7~67) winsize 61
7579 23:56:59.188533 [CA 5] Center 36 (7~66) winsize 60
7580 23:56:59.188951
7581 23:56:59.192130 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 23:56:59.192548
7583 23:56:59.198680 [CATrainingPosCal] consider 2 rank data
7584 23:56:59.199099 u2DelayCellTimex100 = 275/100 ps
7585 23:56:59.205146 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7586 23:56:59.208339 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7587 23:56:59.211568 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7588 23:56:59.215462 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7589 23:56:59.218536 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7590 23:56:59.221565 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7591 23:56:59.221984
7592 23:56:59.225030 CA PerBit enable=1, Macro0, CA PI delay=36
7593 23:56:59.225570
7594 23:56:59.228844 [CBTSetCACLKResult] CA Dly = 36
7595 23:56:59.231264 CS Dly: 11 (0~43)
7596 23:56:59.234978 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 23:56:59.238285 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 23:56:59.238703
7599 23:56:59.245366 ----->DramcWriteLeveling(PI) begin...
7600 23:56:59.245793 ==
7601 23:56:59.247930 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 23:56:59.251352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 23:56:59.251824 ==
7604 23:56:59.255040 Write leveling (Byte 0): 36 => 36
7605 23:56:59.257732 Write leveling (Byte 1): 25 => 25
7606 23:56:59.261552 DramcWriteLeveling(PI) end<-----
7607 23:56:59.261972
7608 23:56:59.262299 ==
7609 23:56:59.264548 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 23:56:59.267652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 23:56:59.268161 ==
7612 23:56:59.270910 [Gating] SW mode calibration
7613 23:56:59.277863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 23:56:59.284159 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 23:56:59.287395 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 23:56:59.290722 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 23:56:59.298141 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7618 23:56:59.300516 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7619 23:56:59.304645 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7620 23:56:59.310888 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7621 23:56:59.314431 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 23:56:59.317172 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 23:56:59.324182 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 23:56:59.326996 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 23:56:59.330174 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
7626 23:56:59.336952 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7627 23:56:59.340040 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7628 23:56:59.343961 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7629 23:56:59.349817 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7630 23:56:59.353684 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 23:56:59.356725 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 23:56:59.363065 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 23:56:59.366824 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7634 23:56:59.369975 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7635 23:56:59.376410 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7636 23:56:59.379688 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7637 23:56:59.383459 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 23:56:59.389685 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 23:56:59.392951 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 23:56:59.396347 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 23:56:59.402800 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 23:56:59.406095 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 23:56:59.409393 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7644 23:56:59.416067 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7645 23:56:59.419150 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 23:56:59.422250 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:56:59.429391 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:56:59.432529 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:56:59.435986 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:56:59.442272 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:56:59.445875 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:56:59.448710 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:56:59.455241 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 23:56:59.458944 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 23:56:59.462015 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 23:56:59.468640 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 23:56:59.471687 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 23:56:59.475086 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7659 23:56:59.478475 Total UI for P1: 0, mck2ui 16
7660 23:56:59.482093 best dqsien dly found for B0: ( 1, 9, 8)
7661 23:56:59.489564 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7662 23:56:59.491711 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7663 23:56:59.495129 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 23:56:59.499155 Total UI for P1: 0, mck2ui 16
7665 23:56:59.501564 best dqsien dly found for B1: ( 1, 9, 22)
7666 23:56:59.505340 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7667 23:56:59.508174 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7668 23:56:59.508594
7669 23:56:59.514698 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7670 23:56:59.517878 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7671 23:56:59.521138 [Gating] SW calibration Done
7672 23:56:59.521584 ==
7673 23:56:59.524509 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 23:56:59.527920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 23:56:59.528351 ==
7676 23:56:59.528689 RX Vref Scan: 0
7677 23:56:59.530889
7678 23:56:59.531304 RX Vref 0 -> 0, step: 1
7679 23:56:59.531636
7680 23:56:59.534399 RX Delay 0 -> 252, step: 8
7681 23:56:59.537907 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7682 23:56:59.541342 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7683 23:56:59.547368 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7684 23:56:59.551146 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7685 23:56:59.554177 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7686 23:56:59.557194 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7687 23:56:59.560959 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7688 23:56:59.567201 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7689 23:56:59.570627 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7690 23:56:59.574059 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7691 23:56:59.577145 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7692 23:56:59.583871 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7693 23:56:59.587103 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7694 23:56:59.589962 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7695 23:56:59.594307 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7696 23:56:59.596721 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7697 23:56:59.600308 ==
7698 23:56:59.603465 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 23:56:59.606902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 23:56:59.607324 ==
7701 23:56:59.607654 DQS Delay:
7702 23:56:59.609977 DQS0 = 0, DQS1 = 0
7703 23:56:59.610396 DQM Delay:
7704 23:56:59.613366 DQM0 = 131, DQM1 = 127
7705 23:56:59.613785 DQ Delay:
7706 23:56:59.616372 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7707 23:56:59.619794 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7708 23:56:59.623106 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7709 23:56:59.626686 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7710 23:56:59.627108
7711 23:56:59.627437
7712 23:56:59.627896 ==
7713 23:56:59.629987 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 23:56:59.636416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 23:56:59.636836 ==
7716 23:56:59.637171
7717 23:56:59.637519
7718 23:56:59.639838 TX Vref Scan disable
7719 23:56:59.640257 == TX Byte 0 ==
7720 23:56:59.642604 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7721 23:56:59.649479 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7722 23:56:59.650115 == TX Byte 1 ==
7723 23:56:59.655856 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7724 23:56:59.659086 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7725 23:56:59.659633 ==
7726 23:56:59.662654 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 23:56:59.665986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 23:56:59.666406 ==
7729 23:56:59.681891
7730 23:56:59.684614 TX Vref early break, caculate TX vref
7731 23:56:59.688179 TX Vref=16, minBit 3, minWin=22, winSum=367
7732 23:56:59.691390 TX Vref=18, minBit 8, minWin=22, winSum=379
7733 23:56:59.695110 TX Vref=20, minBit 1, minWin=24, winSum=389
7734 23:56:59.698138 TX Vref=22, minBit 1, minWin=23, winSum=397
7735 23:56:59.701174 TX Vref=24, minBit 0, minWin=25, winSum=409
7736 23:56:59.707763 TX Vref=26, minBit 1, minWin=25, winSum=412
7737 23:56:59.710971 TX Vref=28, minBit 1, minWin=25, winSum=414
7738 23:56:59.714033 TX Vref=30, minBit 1, minWin=25, winSum=412
7739 23:56:59.717747 TX Vref=32, minBit 4, minWin=24, winSum=404
7740 23:56:59.721046 TX Vref=34, minBit 1, minWin=24, winSum=396
7741 23:56:59.727158 TX Vref=36, minBit 2, minWin=23, winSum=383
7742 23:56:59.730336 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
7743 23:56:59.730430
7744 23:56:59.733773 Final TX Range 0 Vref 28
7745 23:56:59.733866
7746 23:56:59.733940 ==
7747 23:56:59.736773 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 23:56:59.740725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 23:56:59.743438 ==
7750 23:56:59.743549
7751 23:56:59.743635
7752 23:56:59.743716 TX Vref Scan disable
7753 23:56:59.750501 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7754 23:56:59.750622 == TX Byte 0 ==
7755 23:56:59.753512 u2DelayCellOfst[0]=17 cells (5 PI)
7756 23:56:59.756975 u2DelayCellOfst[1]=17 cells (5 PI)
7757 23:56:59.760246 u2DelayCellOfst[2]=10 cells (3 PI)
7758 23:56:59.763688 u2DelayCellOfst[3]=14 cells (4 PI)
7759 23:56:59.766886 u2DelayCellOfst[4]=10 cells (3 PI)
7760 23:56:59.769989 u2DelayCellOfst[5]=0 cells (0 PI)
7761 23:56:59.774010 u2DelayCellOfst[6]=21 cells (6 PI)
7762 23:56:59.776860 u2DelayCellOfst[7]=17 cells (5 PI)
7763 23:56:59.780005 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7764 23:56:59.783732 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7765 23:56:59.786930 == TX Byte 1 ==
7766 23:56:59.790161 u2DelayCellOfst[8]=0 cells (0 PI)
7767 23:56:59.793509 u2DelayCellOfst[9]=0 cells (0 PI)
7768 23:56:59.796841 u2DelayCellOfst[10]=7 cells (2 PI)
7769 23:56:59.800650 u2DelayCellOfst[11]=0 cells (0 PI)
7770 23:56:59.803820 u2DelayCellOfst[12]=7 cells (2 PI)
7771 23:56:59.807628 u2DelayCellOfst[13]=7 cells (2 PI)
7772 23:56:59.810156 u2DelayCellOfst[14]=14 cells (4 PI)
7773 23:56:59.810713 u2DelayCellOfst[15]=7 cells (2 PI)
7774 23:56:59.816404 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7775 23:56:59.819767 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7776 23:56:59.823199 DramC Write-DBI on
7777 23:56:59.823680 ==
7778 23:56:59.826891 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 23:56:59.830211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 23:56:59.830629 ==
7781 23:56:59.831055
7782 23:56:59.831416
7783 23:56:59.833084 TX Vref Scan disable
7784 23:56:59.833618 == TX Byte 0 ==
7785 23:56:59.839628 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7786 23:56:59.840134 == TX Byte 1 ==
7787 23:56:59.846019 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7788 23:56:59.846436 DramC Write-DBI off
7789 23:56:59.846838
7790 23:56:59.847154 [DATLAT]
7791 23:56:59.849347 Freq=1600, CH0 RK0
7792 23:56:59.849969
7793 23:56:59.853020 DATLAT Default: 0xf
7794 23:56:59.853467 0, 0xFFFF, sum = 0
7795 23:56:59.856107 1, 0xFFFF, sum = 0
7796 23:56:59.856526 2, 0xFFFF, sum = 0
7797 23:56:59.859085 3, 0xFFFF, sum = 0
7798 23:56:59.859506 4, 0xFFFF, sum = 0
7799 23:56:59.862854 5, 0xFFFF, sum = 0
7800 23:56:59.863275 6, 0xFFFF, sum = 0
7801 23:56:59.866030 7, 0xFFFF, sum = 0
7802 23:56:59.866450 8, 0xFFFF, sum = 0
7803 23:56:59.868951 9, 0xFFFF, sum = 0
7804 23:56:59.869407 10, 0xFFFF, sum = 0
7805 23:56:59.872575 11, 0xFFFF, sum = 0
7806 23:56:59.872994 12, 0xFFFF, sum = 0
7807 23:56:59.875564 13, 0xFFFF, sum = 0
7808 23:56:59.875981 14, 0x0, sum = 1
7809 23:56:59.879448 15, 0x0, sum = 2
7810 23:56:59.879868 16, 0x0, sum = 3
7811 23:56:59.882058 17, 0x0, sum = 4
7812 23:56:59.882478 best_step = 15
7813 23:56:59.882809
7814 23:56:59.883114 ==
7815 23:56:59.885901 Dram Type= 6, Freq= 0, CH_0, rank 0
7816 23:56:59.892352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7817 23:56:59.892770 ==
7818 23:56:59.893101 RX Vref Scan: 1
7819 23:56:59.893465
7820 23:56:59.895986 Set Vref Range= 24 -> 127
7821 23:56:59.896398
7822 23:56:59.899148 RX Vref 24 -> 127, step: 1
7823 23:56:59.899564
7824 23:56:59.902003 RX Delay 11 -> 252, step: 4
7825 23:56:59.902467
7826 23:56:59.905620 Set Vref, RX VrefLevel [Byte0]: 24
7827 23:56:59.908452 [Byte1]: 24
7828 23:56:59.908870
7829 23:56:59.912089 Set Vref, RX VrefLevel [Byte0]: 25
7830 23:56:59.915363 [Byte1]: 25
7831 23:56:59.915777
7832 23:56:59.919088 Set Vref, RX VrefLevel [Byte0]: 26
7833 23:56:59.921703 [Byte1]: 26
7834 23:56:59.925167
7835 23:56:59.925638 Set Vref, RX VrefLevel [Byte0]: 27
7836 23:56:59.928494 [Byte1]: 27
7837 23:56:59.932839
7838 23:56:59.933249 Set Vref, RX VrefLevel [Byte0]: 28
7839 23:56:59.936255 [Byte1]: 28
7840 23:56:59.940251
7841 23:56:59.940663 Set Vref, RX VrefLevel [Byte0]: 29
7842 23:56:59.943783 [Byte1]: 29
7843 23:56:59.948287
7844 23:56:59.948700 Set Vref, RX VrefLevel [Byte0]: 30
7845 23:56:59.951103 [Byte1]: 30
7846 23:56:59.955536
7847 23:56:59.955949 Set Vref, RX VrefLevel [Byte0]: 31
7848 23:56:59.959035 [Byte1]: 31
7849 23:56:59.963524
7850 23:56:59.963937 Set Vref, RX VrefLevel [Byte0]: 32
7851 23:56:59.966429 [Byte1]: 32
7852 23:56:59.970782
7853 23:56:59.971208 Set Vref, RX VrefLevel [Byte0]: 33
7854 23:56:59.975112 [Byte1]: 33
7855 23:56:59.978396
7856 23:56:59.978807 Set Vref, RX VrefLevel [Byte0]: 34
7857 23:56:59.981806 [Byte1]: 34
7858 23:56:59.986389
7859 23:56:59.986879 Set Vref, RX VrefLevel [Byte0]: 35
7860 23:56:59.989776 [Byte1]: 35
7861 23:56:59.993623
7862 23:56:59.994036 Set Vref, RX VrefLevel [Byte0]: 36
7863 23:56:59.996826 [Byte1]: 36
7864 23:57:00.001843
7865 23:57:00.002362 Set Vref, RX VrefLevel [Byte0]: 37
7866 23:57:00.004432 [Byte1]: 37
7867 23:57:00.008834
7868 23:57:00.009248 Set Vref, RX VrefLevel [Byte0]: 38
7869 23:57:00.012435 [Byte1]: 38
7870 23:57:00.016252
7871 23:57:00.016667 Set Vref, RX VrefLevel [Byte0]: 39
7872 23:57:00.019695 [Byte1]: 39
7873 23:57:00.023884
7874 23:57:00.024302 Set Vref, RX VrefLevel [Byte0]: 40
7875 23:57:00.028236 [Byte1]: 40
7876 23:57:00.031557
7877 23:57:00.032020 Set Vref, RX VrefLevel [Byte0]: 41
7878 23:57:00.035127 [Byte1]: 41
7879 23:57:00.039524
7880 23:57:00.039942 Set Vref, RX VrefLevel [Byte0]: 42
7881 23:57:00.042581 [Byte1]: 42
7882 23:57:00.046689
7883 23:57:00.050154 Set Vref, RX VrefLevel [Byte0]: 43
7884 23:57:00.053188 [Byte1]: 43
7885 23:57:00.053648
7886 23:57:00.056431 Set Vref, RX VrefLevel [Byte0]: 44
7887 23:57:00.059682 [Byte1]: 44
7888 23:57:00.060099
7889 23:57:00.062912 Set Vref, RX VrefLevel [Byte0]: 45
7890 23:57:00.066418 [Byte1]: 45
7891 23:57:00.069967
7892 23:57:00.070384 Set Vref, RX VrefLevel [Byte0]: 46
7893 23:57:00.072986 [Byte1]: 46
7894 23:57:00.078423
7895 23:57:00.078873 Set Vref, RX VrefLevel [Byte0]: 47
7896 23:57:00.080556 [Byte1]: 47
7897 23:57:00.085001
7898 23:57:00.085469 Set Vref, RX VrefLevel [Byte0]: 48
7899 23:57:00.088353 [Byte1]: 48
7900 23:57:00.092380
7901 23:57:00.092798 Set Vref, RX VrefLevel [Byte0]: 49
7902 23:57:00.095808 [Byte1]: 49
7903 23:57:00.100277
7904 23:57:00.100690 Set Vref, RX VrefLevel [Byte0]: 50
7905 23:57:00.103590 [Byte1]: 50
7906 23:57:00.108273
7907 23:57:00.108690 Set Vref, RX VrefLevel [Byte0]: 51
7908 23:57:00.111779 [Byte1]: 51
7909 23:57:00.115696
7910 23:57:00.116274 Set Vref, RX VrefLevel [Byte0]: 52
7911 23:57:00.119006 [Byte1]: 52
7912 23:57:00.123152
7913 23:57:00.123616 Set Vref, RX VrefLevel [Byte0]: 53
7914 23:57:00.126878 [Byte1]: 53
7915 23:57:00.130452
7916 23:57:00.130936 Set Vref, RX VrefLevel [Byte0]: 54
7917 23:57:00.134263 [Byte1]: 54
7918 23:57:00.138226
7919 23:57:00.138650 Set Vref, RX VrefLevel [Byte0]: 55
7920 23:57:00.141910 [Byte1]: 55
7921 23:57:00.145676
7922 23:57:00.146088 Set Vref, RX VrefLevel [Byte0]: 56
7923 23:57:00.149521 [Byte1]: 56
7924 23:57:00.153368
7925 23:57:00.153814 Set Vref, RX VrefLevel [Byte0]: 57
7926 23:57:00.157060 [Byte1]: 57
7927 23:57:00.161480
7928 23:57:00.161889 Set Vref, RX VrefLevel [Byte0]: 58
7929 23:57:00.164259 [Byte1]: 58
7930 23:57:00.169083
7931 23:57:00.169535 Set Vref, RX VrefLevel [Byte0]: 59
7932 23:57:00.172610 [Byte1]: 59
7933 23:57:00.176221
7934 23:57:00.176711 Set Vref, RX VrefLevel [Byte0]: 60
7935 23:57:00.179520 [Byte1]: 60
7936 23:57:00.183750
7937 23:57:00.184202 Set Vref, RX VrefLevel [Byte0]: 61
7938 23:57:00.187746 [Byte1]: 61
7939 23:57:00.191909
7940 23:57:00.192320 Set Vref, RX VrefLevel [Byte0]: 62
7941 23:57:00.195405 [Byte1]: 62
7942 23:57:00.199272
7943 23:57:00.199692 Set Vref, RX VrefLevel [Byte0]: 63
7944 23:57:00.202772 [Byte1]: 63
7945 23:57:00.206884
7946 23:57:00.207375 Set Vref, RX VrefLevel [Byte0]: 64
7947 23:57:00.210135 [Byte1]: 64
7948 23:57:00.214271
7949 23:57:00.214681 Set Vref, RX VrefLevel [Byte0]: 65
7950 23:57:00.217967 [Byte1]: 65
7951 23:57:00.222227
7952 23:57:00.222667 Set Vref, RX VrefLevel [Byte0]: 66
7953 23:57:00.225761 [Byte1]: 66
7954 23:57:00.229494
7955 23:57:00.229951 Set Vref, RX VrefLevel [Byte0]: 67
7956 23:57:00.232713 [Byte1]: 67
7957 23:57:00.237718
7958 23:57:00.238126 Set Vref, RX VrefLevel [Byte0]: 68
7959 23:57:00.240493 [Byte1]: 68
7960 23:57:00.244756
7961 23:57:00.245226 Set Vref, RX VrefLevel [Byte0]: 69
7962 23:57:00.248133 [Byte1]: 69
7963 23:57:00.252310
7964 23:57:00.252743 Set Vref, RX VrefLevel [Byte0]: 70
7965 23:57:00.255718 [Byte1]: 70
7966 23:57:00.260040
7967 23:57:00.260450 Set Vref, RX VrefLevel [Byte0]: 71
7968 23:57:00.263710 [Byte1]: 71
7969 23:57:00.267629
7970 23:57:00.268103 Set Vref, RX VrefLevel [Byte0]: 72
7971 23:57:00.271223 [Byte1]: 72
7972 23:57:00.275249
7973 23:57:00.275730 Set Vref, RX VrefLevel [Byte0]: 73
7974 23:57:00.278562 [Byte1]: 73
7975 23:57:00.283297
7976 23:57:00.283716 Set Vref, RX VrefLevel [Byte0]: 74
7977 23:57:00.286052 [Byte1]: 74
7978 23:57:00.291209
7979 23:57:00.291647 Set Vref, RX VrefLevel [Byte0]: 75
7980 23:57:00.293809 [Byte1]: 75
7981 23:57:00.298645
7982 23:57:00.299064 Set Vref, RX VrefLevel [Byte0]: 76
7983 23:57:00.301601 [Byte1]: 76
7984 23:57:00.306026
7985 23:57:00.306453 Final RX Vref Byte 0 = 56 to rank0
7986 23:57:00.308878 Final RX Vref Byte 1 = 60 to rank0
7987 23:57:00.312562 Final RX Vref Byte 0 = 56 to rank1
7988 23:57:00.315531 Final RX Vref Byte 1 = 60 to rank1==
7989 23:57:00.318740 Dram Type= 6, Freq= 0, CH_0, rank 0
7990 23:57:00.325243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 23:57:00.325734 ==
7992 23:57:00.326172 DQS Delay:
7993 23:57:00.328953 DQS0 = 0, DQS1 = 0
7994 23:57:00.329419 DQM Delay:
7995 23:57:00.329857 DQM0 = 129, DQM1 = 123
7996 23:57:00.331939 DQ Delay:
7997 23:57:00.335532 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7998 23:57:00.338620 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
7999 23:57:00.342210 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
8000 23:57:00.345364 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =130
8001 23:57:00.345797
8002 23:57:00.346232
8003 23:57:00.346644
8004 23:57:00.348557 [DramC_TX_OE_Calibration] TA2
8005 23:57:00.351658 Original DQ_B0 (3 6) =30, OEN = 27
8006 23:57:00.355060 Original DQ_B1 (3 6) =30, OEN = 27
8007 23:57:00.358478 24, 0x0, End_B0=24 End_B1=24
8008 23:57:00.361767 25, 0x0, End_B0=25 End_B1=25
8009 23:57:00.362210 26, 0x0, End_B0=26 End_B1=26
8010 23:57:00.365133 27, 0x0, End_B0=27 End_B1=27
8011 23:57:00.368512 28, 0x0, End_B0=28 End_B1=28
8012 23:57:00.371724 29, 0x0, End_B0=29 End_B1=29
8013 23:57:00.372213 30, 0x0, End_B0=30 End_B1=30
8014 23:57:00.374996 31, 0x4141, End_B0=30 End_B1=30
8015 23:57:00.378062 Byte0 end_step=30 best_step=27
8016 23:57:00.381668 Byte1 end_step=30 best_step=27
8017 23:57:00.384612 Byte0 TX OE(2T, 0.5T) = (3, 3)
8018 23:57:00.388492 Byte1 TX OE(2T, 0.5T) = (3, 3)
8019 23:57:00.388936
8020 23:57:00.389311
8021 23:57:00.394531 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
8022 23:57:00.397738 CH0 RK0: MR19=303, MR18=1A17
8023 23:57:00.404312 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
8024 23:57:00.404775
8025 23:57:00.407800 ----->DramcWriteLeveling(PI) begin...
8026 23:57:00.408361 ==
8027 23:57:00.411334 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 23:57:00.414157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 23:57:00.414605 ==
8030 23:57:00.417593 Write leveling (Byte 0): 35 => 35
8031 23:57:00.420768 Write leveling (Byte 1): 26 => 26
8032 23:57:00.424208 DramcWriteLeveling(PI) end<-----
8033 23:57:00.424617
8034 23:57:00.425184 ==
8035 23:57:00.427342 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 23:57:00.434410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 23:57:00.434857 ==
8038 23:57:00.435298 [Gating] SW mode calibration
8039 23:57:00.443656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8040 23:57:00.446910 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8041 23:57:00.453582 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 23:57:00.457106 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 23:57:00.460430 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
8044 23:57:00.466806 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8045 23:57:00.469974 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8046 23:57:00.473843 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 23:57:00.480099 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 23:57:00.483534 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 23:57:00.486891 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 23:57:00.493433 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8051 23:57:00.496689 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8052 23:57:00.499806 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8053 23:57:00.506690 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8054 23:57:00.509719 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8055 23:57:00.513403 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 23:57:00.519425 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 23:57:00.522994 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 23:57:00.526487 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8059 23:57:00.533592 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8060 23:57:00.536014 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8061 23:57:00.539087 1 6 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8062 23:57:00.545581 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 23:57:00.549198 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 23:57:00.552476 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 23:57:00.559276 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 23:57:00.562491 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 23:57:00.565429 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8068 23:57:00.572647 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8069 23:57:00.575842 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8070 23:57:00.578464 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8071 23:57:00.585357 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:57:00.588693 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:57:00.592118 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:57:00.598722 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:57:00.602228 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:57:00.605049 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:57:00.611534 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:57:00.615045 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:57:00.618232 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 23:57:00.624886 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 23:57:00.628354 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 23:57:00.631240 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8083 23:57:00.637879 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8084 23:57:00.641224 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8085 23:57:00.644639 Total UI for P1: 0, mck2ui 16
8086 23:57:00.648272 best dqsien dly found for B0: ( 1, 9, 6)
8087 23:57:00.651360 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8088 23:57:00.658394 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 23:57:00.658814 Total UI for P1: 0, mck2ui 16
8090 23:57:00.664505 best dqsien dly found for B1: ( 1, 9, 16)
8091 23:57:00.667722 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8092 23:57:00.671250 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8093 23:57:00.671673
8094 23:57:00.675015 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8095 23:57:00.677636 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8096 23:57:00.681105 [Gating] SW calibration Done
8097 23:57:00.681748 ==
8098 23:57:00.684252 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 23:57:00.687665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 23:57:00.688086 ==
8101 23:57:00.691208 RX Vref Scan: 0
8102 23:57:00.691808
8103 23:57:00.692368 RX Vref 0 -> 0, step: 1
8104 23:57:00.692755
8105 23:57:00.694280 RX Delay 0 -> 252, step: 8
8106 23:57:00.697390 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8107 23:57:00.704138 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8108 23:57:00.707870 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8109 23:57:00.710979 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8110 23:57:00.714190 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8111 23:57:00.717089 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8112 23:57:00.723868 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8113 23:57:00.727130 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8114 23:57:00.730427 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8115 23:57:00.733563 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
8116 23:57:00.737001 iDelay=192, Bit 10, Center 131 (72 ~ 191) 120
8117 23:57:00.744079 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8118 23:57:00.747148 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
8119 23:57:00.750380 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8120 23:57:00.753663 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8121 23:57:00.760271 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8122 23:57:00.760692 ==
8123 23:57:00.763409 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 23:57:00.766769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 23:57:00.767279 ==
8126 23:57:00.767618 DQS Delay:
8127 23:57:00.770141 DQS0 = 0, DQS1 = 0
8128 23:57:00.770555 DQM Delay:
8129 23:57:00.773709 DQM0 = 131, DQM1 = 128
8130 23:57:00.774126 DQ Delay:
8131 23:57:00.776367 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8132 23:57:00.780041 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8133 23:57:00.783207 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8134 23:57:00.786687 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8135 23:57:00.787107
8136 23:57:00.790153
8137 23:57:00.790567 ==
8138 23:57:00.793359 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 23:57:00.796091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 23:57:00.796512 ==
8141 23:57:00.796842
8142 23:57:00.797150
8143 23:57:00.800231 TX Vref Scan disable
8144 23:57:00.800646 == TX Byte 0 ==
8145 23:57:00.806490 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8146 23:57:00.809254 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8147 23:57:00.809705 == TX Byte 1 ==
8148 23:57:00.816087 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8149 23:57:00.819391 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8150 23:57:00.819811 ==
8151 23:57:00.823175 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 23:57:00.826374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 23:57:00.826799 ==
8154 23:57:00.840554
8155 23:57:00.843951 TX Vref early break, caculate TX vref
8156 23:57:00.847496 TX Vref=16, minBit 1, minWin=23, winSum=380
8157 23:57:00.850193 TX Vref=18, minBit 8, minWin=23, winSum=387
8158 23:57:00.853613 TX Vref=20, minBit 2, minWin=24, winSum=398
8159 23:57:00.856803 TX Vref=22, minBit 4, minWin=24, winSum=403
8160 23:57:00.860465 TX Vref=24, minBit 1, minWin=25, winSum=409
8161 23:57:00.867080 TX Vref=26, minBit 4, minWin=25, winSum=418
8162 23:57:00.869837 TX Vref=28, minBit 0, minWin=26, winSum=423
8163 23:57:00.873525 TX Vref=30, minBit 1, minWin=25, winSum=410
8164 23:57:00.876801 TX Vref=32, minBit 1, minWin=24, winSum=402
8165 23:57:00.880188 TX Vref=34, minBit 1, minWin=24, winSum=400
8166 23:57:00.886623 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
8167 23:57:00.887051
8168 23:57:00.889568 Final TX Range 0 Vref 28
8169 23:57:00.889987
8170 23:57:00.890317 ==
8171 23:57:00.893036 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 23:57:00.896313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 23:57:00.896737 ==
8174 23:57:00.897072
8175 23:57:00.900221
8176 23:57:00.900637 TX Vref Scan disable
8177 23:57:00.906072 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8178 23:57:00.906504 == TX Byte 0 ==
8179 23:57:00.909839 u2DelayCellOfst[0]=14 cells (4 PI)
8180 23:57:00.912916 u2DelayCellOfst[1]=14 cells (4 PI)
8181 23:57:00.916419 u2DelayCellOfst[2]=10 cells (3 PI)
8182 23:57:00.919327 u2DelayCellOfst[3]=14 cells (4 PI)
8183 23:57:00.923084 u2DelayCellOfst[4]=10 cells (3 PI)
8184 23:57:00.926162 u2DelayCellOfst[5]=0 cells (0 PI)
8185 23:57:00.929658 u2DelayCellOfst[6]=17 cells (5 PI)
8186 23:57:00.932374 u2DelayCellOfst[7]=17 cells (5 PI)
8187 23:57:00.936516 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8188 23:57:00.939765 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8189 23:57:00.942179 == TX Byte 1 ==
8190 23:57:00.945741 u2DelayCellOfst[8]=0 cells (0 PI)
8191 23:57:00.949343 u2DelayCellOfst[9]=0 cells (0 PI)
8192 23:57:00.952627 u2DelayCellOfst[10]=3 cells (1 PI)
8193 23:57:00.955617 u2DelayCellOfst[11]=3 cells (1 PI)
8194 23:57:00.958885 u2DelayCellOfst[12]=7 cells (2 PI)
8195 23:57:00.959295 u2DelayCellOfst[13]=7 cells (2 PI)
8196 23:57:00.962431 u2DelayCellOfst[14]=14 cells (4 PI)
8197 23:57:00.965709 u2DelayCellOfst[15]=10 cells (3 PI)
8198 23:57:00.972012 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8199 23:57:00.975427 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8200 23:57:00.978393 DramC Write-DBI on
8201 23:57:00.978804 ==
8202 23:57:00.981710 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 23:57:00.984776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 23:57:00.984861 ==
8205 23:57:00.984929
8206 23:57:00.984991
8207 23:57:00.988487 TX Vref Scan disable
8208 23:57:00.988900 == TX Byte 0 ==
8209 23:57:00.994997 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8210 23:57:00.995418 == TX Byte 1 ==
8211 23:57:00.998208 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8212 23:57:01.001837 DramC Write-DBI off
8213 23:57:01.002248
8214 23:57:01.002648 [DATLAT]
8215 23:57:01.005138 Freq=1600, CH0 RK1
8216 23:57:01.005580
8217 23:57:01.005907 DATLAT Default: 0xf
8218 23:57:01.008196 0, 0xFFFF, sum = 0
8219 23:57:01.012145 1, 0xFFFF, sum = 0
8220 23:57:01.012579 2, 0xFFFF, sum = 0
8221 23:57:01.015212 3, 0xFFFF, sum = 0
8222 23:57:01.015715 4, 0xFFFF, sum = 0
8223 23:57:01.018083 5, 0xFFFF, sum = 0
8224 23:57:01.018533 6, 0xFFFF, sum = 0
8225 23:57:01.021627 7, 0xFFFF, sum = 0
8226 23:57:01.022044 8, 0xFFFF, sum = 0
8227 23:57:01.024504 9, 0xFFFF, sum = 0
8228 23:57:01.024942 10, 0xFFFF, sum = 0
8229 23:57:01.027727 11, 0xFFFF, sum = 0
8230 23:57:01.028175 12, 0xFFFF, sum = 0
8231 23:57:01.032149 13, 0xFFFF, sum = 0
8232 23:57:01.032595 14, 0x0, sum = 1
8233 23:57:01.034558 15, 0x0, sum = 2
8234 23:57:01.034973 16, 0x0, sum = 3
8235 23:57:01.037804 17, 0x0, sum = 4
8236 23:57:01.038241 best_step = 15
8237 23:57:01.038591
8238 23:57:01.038911 ==
8239 23:57:01.041228 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 23:57:01.047622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 23:57:01.048198 ==
8242 23:57:01.048541 RX Vref Scan: 0
8243 23:57:01.048885
8244 23:57:01.051380 RX Vref 0 -> 0, step: 1
8245 23:57:01.051789
8246 23:57:01.054187 RX Delay 19 -> 252, step: 4
8247 23:57:01.057497 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8248 23:57:01.061222 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8249 23:57:01.067697 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8250 23:57:01.070986 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8251 23:57:01.073808 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8252 23:57:01.077511 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8253 23:57:01.080691 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8254 23:57:01.083705 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8255 23:57:01.090522 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8256 23:57:01.093574 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8257 23:57:01.097454 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8258 23:57:01.100410 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8259 23:57:01.106841 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8260 23:57:01.110438 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8261 23:57:01.113496 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8262 23:57:01.117367 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8263 23:57:01.117830 ==
8264 23:57:01.119964 Dram Type= 6, Freq= 0, CH_0, rank 1
8265 23:57:01.126571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 23:57:01.127000 ==
8267 23:57:01.127333 DQS Delay:
8268 23:57:01.130307 DQS0 = 0, DQS1 = 0
8269 23:57:01.130719 DQM Delay:
8270 23:57:01.131045 DQM0 = 128, DQM1 = 123
8271 23:57:01.133162 DQ Delay:
8272 23:57:01.136721 DQ0 =126, DQ1 =132, DQ2 =122, DQ3 =126
8273 23:57:01.140144 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
8274 23:57:01.143389 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8275 23:57:01.146655 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8276 23:57:01.147211
8277 23:57:01.147681
8278 23:57:01.148022
8279 23:57:01.149624 [DramC_TX_OE_Calibration] TA2
8280 23:57:01.153190 Original DQ_B0 (3 6) =30, OEN = 27
8281 23:57:01.156425 Original DQ_B1 (3 6) =30, OEN = 27
8282 23:57:01.159495 24, 0x0, End_B0=24 End_B1=24
8283 23:57:01.162920 25, 0x0, End_B0=25 End_B1=25
8284 23:57:01.163336 26, 0x0, End_B0=26 End_B1=26
8285 23:57:01.166424 27, 0x0, End_B0=27 End_B1=27
8286 23:57:01.169406 28, 0x0, End_B0=28 End_B1=28
8287 23:57:01.172848 29, 0x0, End_B0=29 End_B1=29
8288 23:57:01.173322 30, 0x0, End_B0=30 End_B1=30
8289 23:57:01.176434 31, 0x4141, End_B0=30 End_B1=30
8290 23:57:01.179435 Byte0 end_step=30 best_step=27
8291 23:57:01.183296 Byte1 end_step=30 best_step=27
8292 23:57:01.186085 Byte0 TX OE(2T, 0.5T) = (3, 3)
8293 23:57:01.189793 Byte1 TX OE(2T, 0.5T) = (3, 3)
8294 23:57:01.190204
8295 23:57:01.190527
8296 23:57:01.196426 [DQSOSCAuto] RK1, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8297 23:57:01.199483 CH0 RK1: MR19=303, MR18=1312
8298 23:57:01.205890 CH0_RK1: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8299 23:57:01.208862 [RxdqsGatingPostProcess] freq 1600
8300 23:57:01.215977 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8301 23:57:01.216395 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 23:57:01.218953 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 23:57:01.222209 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 23:57:01.225539 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 23:57:01.228519 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 23:57:01.232051 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 23:57:01.235520 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 23:57:01.238752 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 23:57:01.241503 Pre-setting of DQS Precalculation
8310 23:57:01.245254 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8311 23:57:01.248246 ==
8312 23:57:01.251316 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 23:57:01.254706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 23:57:01.255143 ==
8315 23:57:01.261353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 23:57:01.264865 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 23:57:01.268225 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 23:57:01.274709 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 23:57:01.282834 [CA 0] Center 42 (12~72) winsize 61
8320 23:57:01.286724 [CA 1] Center 42 (12~72) winsize 61
8321 23:57:01.289550 [CA 2] Center 38 (9~67) winsize 59
8322 23:57:01.293172 [CA 3] Center 37 (8~66) winsize 59
8323 23:57:01.296030 [CA 4] Center 38 (8~68) winsize 61
8324 23:57:01.299634 [CA 5] Center 36 (7~66) winsize 60
8325 23:57:01.300155
8326 23:57:01.303271 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 23:57:01.303685
8328 23:57:01.309516 [CATrainingPosCal] consider 1 rank data
8329 23:57:01.309927 u2DelayCellTimex100 = 275/100 ps
8330 23:57:01.315683 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8331 23:57:01.319136 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8332 23:57:01.322726 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8333 23:57:01.325737 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8334 23:57:01.329123 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8335 23:57:01.332891 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8336 23:57:01.333353
8337 23:57:01.335658 CA PerBit enable=1, Macro0, CA PI delay=36
8338 23:57:01.336073
8339 23:57:01.339485 [CBTSetCACLKResult] CA Dly = 36
8340 23:57:01.342250 CS Dly: 8 (0~39)
8341 23:57:01.345416 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 23:57:01.348903 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 23:57:01.349359 ==
8344 23:57:01.353385 Dram Type= 6, Freq= 0, CH_1, rank 1
8345 23:57:01.359000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 23:57:01.359424 ==
8347 23:57:01.362310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 23:57:01.368694 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 23:57:01.372276 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 23:57:01.378294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 23:57:01.386369 [CA 0] Center 41 (11~72) winsize 62
8352 23:57:01.390076 [CA 1] Center 42 (13~72) winsize 60
8353 23:57:01.392864 [CA 2] Center 38 (9~68) winsize 60
8354 23:57:01.396485 [CA 3] Center 37 (8~66) winsize 59
8355 23:57:01.399128 [CA 4] Center 38 (8~68) winsize 61
8356 23:57:01.402470 [CA 5] Center 37 (8~67) winsize 60
8357 23:57:01.402884
8358 23:57:01.406286 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8359 23:57:01.406697
8360 23:57:01.412240 [CATrainingPosCal] consider 2 rank data
8361 23:57:01.412672 u2DelayCellTimex100 = 275/100 ps
8362 23:57:01.419227 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8363 23:57:01.422546 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8364 23:57:01.425686 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8365 23:57:01.429212 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8366 23:57:01.432979 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8367 23:57:01.435636 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8368 23:57:01.436043
8369 23:57:01.439171 CA PerBit enable=1, Macro0, CA PI delay=37
8370 23:57:01.439578
8371 23:57:01.442306 [CBTSetCACLKResult] CA Dly = 37
8372 23:57:01.445855 CS Dly: 9 (0~42)
8373 23:57:01.448513 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 23:57:01.452036 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 23:57:01.452444
8376 23:57:01.455586 ----->DramcWriteLeveling(PI) begin...
8377 23:57:01.455999 ==
8378 23:57:01.458664 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 23:57:01.465397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 23:57:01.465811 ==
8381 23:57:01.468588 Write leveling (Byte 0): 26 => 26
8382 23:57:01.471750 Write leveling (Byte 1): 27 => 27
8383 23:57:01.472171 DramcWriteLeveling(PI) end<-----
8384 23:57:01.475426
8385 23:57:01.475829 ==
8386 23:57:01.478650 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 23:57:01.481638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 23:57:01.482046 ==
8389 23:57:01.485158 [Gating] SW mode calibration
8390 23:57:01.492236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8391 23:57:01.494950 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8392 23:57:01.501822 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 23:57:01.504823 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 23:57:01.508485 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 23:57:01.514631 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8396 23:57:01.517985 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8397 23:57:01.521160 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 23:57:01.527640 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 23:57:01.531113 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 23:57:01.534381 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 23:57:01.540831 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 23:57:01.544571 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8403 23:57:01.547782 1 5 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
8404 23:57:01.554455 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 23:57:01.558110 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 23:57:01.561212 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 23:57:01.567919 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 23:57:01.570576 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 23:57:01.574204 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 23:57:01.580592 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8411 23:57:01.584143 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8412 23:57:01.587569 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 23:57:01.593878 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 23:57:01.597078 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 23:57:01.600238 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 23:57:01.607631 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 23:57:01.610408 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 23:57:01.613520 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 23:57:01.620238 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8420 23:57:01.623124 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8421 23:57:01.626564 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:57:01.633749 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:57:01.636592 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:57:01.643288 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:57:01.646348 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:57:01.649974 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:57:01.656543 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:57:01.659445 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:57:01.663174 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:57:01.669510 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:57:01.672765 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 23:57:01.675937 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 23:57:01.682443 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 23:57:01.685858 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8435 23:57:01.688917 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8436 23:57:01.696270 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8437 23:57:01.696708 Total UI for P1: 0, mck2ui 16
8438 23:57:01.702480 best dqsien dly found for B0: ( 1, 9, 10)
8439 23:57:01.705646 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 23:57:01.708577 Total UI for P1: 0, mck2ui 16
8441 23:57:01.712442 best dqsien dly found for B1: ( 1, 9, 14)
8442 23:57:01.715068 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8443 23:57:01.718570 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8444 23:57:01.718989
8445 23:57:01.722644 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8446 23:57:01.725508 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8447 23:57:01.728521 [Gating] SW calibration Done
8448 23:57:01.728813 ==
8449 23:57:01.731501 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 23:57:01.738371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 23:57:01.738557 ==
8452 23:57:01.738698 RX Vref Scan: 0
8453 23:57:01.738830
8454 23:57:01.741137 RX Vref 0 -> 0, step: 1
8455 23:57:01.741310
8456 23:57:01.744700 RX Delay 0 -> 252, step: 8
8457 23:57:01.747838 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8458 23:57:01.751286 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8459 23:57:01.754359 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8460 23:57:01.757906 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8461 23:57:01.764432 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8462 23:57:01.767582 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8463 23:57:01.770929 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8464 23:57:01.774390 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8465 23:57:01.777908 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8466 23:57:01.784623 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8467 23:57:01.787421 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8468 23:57:01.790775 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8469 23:57:01.794181 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8470 23:57:01.800602 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8471 23:57:01.803778 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8472 23:57:01.807665 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8473 23:57:01.807795 ==
8474 23:57:01.810656 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 23:57:01.813823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 23:57:01.814038 ==
8477 23:57:01.817422 DQS Delay:
8478 23:57:01.817585 DQS0 = 0, DQS1 = 0
8479 23:57:01.820311 DQM Delay:
8480 23:57:01.820474 DQM0 = 135, DQM1 = 131
8481 23:57:01.823562 DQ Delay:
8482 23:57:01.826880 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8483 23:57:01.830052 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8484 23:57:01.833843 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8485 23:57:01.837018 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8486 23:57:01.837492
8487 23:57:01.837782
8488 23:57:01.838042 ==
8489 23:57:01.840182 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 23:57:01.843637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 23:57:01.844055 ==
8492 23:57:01.844401
8493 23:57:01.846630
8494 23:57:01.847042 TX Vref Scan disable
8495 23:57:01.849986 == TX Byte 0 ==
8496 23:57:01.853645 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8497 23:57:01.857552 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8498 23:57:01.860298 == TX Byte 1 ==
8499 23:57:01.863187 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8500 23:57:01.866568 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8501 23:57:01.866985 ==
8502 23:57:01.869956 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 23:57:01.877051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 23:57:01.877565 ==
8505 23:57:01.887888
8506 23:57:01.891166 TX Vref early break, caculate TX vref
8507 23:57:01.894680 TX Vref=16, minBit 8, minWin=21, winSum=369
8508 23:57:01.898372 TX Vref=18, minBit 8, minWin=21, winSum=377
8509 23:57:01.901053 TX Vref=20, minBit 1, minWin=23, winSum=385
8510 23:57:01.904689 TX Vref=22, minBit 3, minWin=23, winSum=394
8511 23:57:01.907927 TX Vref=24, minBit 8, minWin=24, winSum=407
8512 23:57:01.914557 TX Vref=26, minBit 1, minWin=25, winSum=413
8513 23:57:01.917749 TX Vref=28, minBit 11, minWin=25, winSum=417
8514 23:57:01.921040 TX Vref=30, minBit 0, minWin=25, winSum=412
8515 23:57:01.924192 TX Vref=32, minBit 9, minWin=24, winSum=401
8516 23:57:01.927698 TX Vref=34, minBit 0, minWin=24, winSum=395
8517 23:57:01.933943 [TxChooseVref] Worse bit 11, Min win 25, Win sum 417, Final Vref 28
8518 23:57:01.934361
8519 23:57:01.937220 Final TX Range 0 Vref 28
8520 23:57:01.937701
8521 23:57:01.938030 ==
8522 23:57:01.940718 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 23:57:01.943963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 23:57:01.944383 ==
8525 23:57:01.944715
8526 23:57:01.947614
8527 23:57:01.948026 TX Vref Scan disable
8528 23:57:01.954231 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8529 23:57:01.954648 == TX Byte 0 ==
8530 23:57:01.956916 u2DelayCellOfst[0]=14 cells (4 PI)
8531 23:57:01.960556 u2DelayCellOfst[1]=10 cells (3 PI)
8532 23:57:01.964034 u2DelayCellOfst[2]=0 cells (0 PI)
8533 23:57:01.967529 u2DelayCellOfst[3]=7 cells (2 PI)
8534 23:57:01.970538 u2DelayCellOfst[4]=7 cells (2 PI)
8535 23:57:01.973687 u2DelayCellOfst[5]=17 cells (5 PI)
8536 23:57:01.977012 u2DelayCellOfst[6]=14 cells (4 PI)
8537 23:57:01.980270 u2DelayCellOfst[7]=7 cells (2 PI)
8538 23:57:01.983450 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8539 23:57:01.986700 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8540 23:57:01.990641 == TX Byte 1 ==
8541 23:57:01.993618 u2DelayCellOfst[8]=0 cells (0 PI)
8542 23:57:01.996826 u2DelayCellOfst[9]=7 cells (2 PI)
8543 23:57:02.000039 u2DelayCellOfst[10]=14 cells (4 PI)
8544 23:57:02.003497 u2DelayCellOfst[11]=7 cells (2 PI)
8545 23:57:02.004045 u2DelayCellOfst[12]=14 cells (4 PI)
8546 23:57:02.006557 u2DelayCellOfst[13]=14 cells (4 PI)
8547 23:57:02.010188 u2DelayCellOfst[14]=17 cells (5 PI)
8548 23:57:02.013574 u2DelayCellOfst[15]=17 cells (5 PI)
8549 23:57:02.019622 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8550 23:57:02.023310 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8551 23:57:02.023880 DramC Write-DBI on
8552 23:57:02.026419 ==
8553 23:57:02.029771 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 23:57:02.032654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 23:57:02.033070 ==
8556 23:57:02.033441
8557 23:57:02.033749
8558 23:57:02.036166 TX Vref Scan disable
8559 23:57:02.036584 == TX Byte 0 ==
8560 23:57:02.043110 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8561 23:57:02.043528 == TX Byte 1 ==
8562 23:57:02.046519 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8563 23:57:02.049646 DramC Write-DBI off
8564 23:57:02.050057
8565 23:57:02.050383 [DATLAT]
8566 23:57:02.052631 Freq=1600, CH1 RK0
8567 23:57:02.053098
8568 23:57:02.053468 DATLAT Default: 0xf
8569 23:57:02.056373 0, 0xFFFF, sum = 0
8570 23:57:02.056898 1, 0xFFFF, sum = 0
8571 23:57:02.059142 2, 0xFFFF, sum = 0
8572 23:57:02.059565 3, 0xFFFF, sum = 0
8573 23:57:02.062444 4, 0xFFFF, sum = 0
8574 23:57:02.066044 5, 0xFFFF, sum = 0
8575 23:57:02.066464 6, 0xFFFF, sum = 0
8576 23:57:02.069204 7, 0xFFFF, sum = 0
8577 23:57:02.069672 8, 0xFFFF, sum = 0
8578 23:57:02.072286 9, 0xFFFF, sum = 0
8579 23:57:02.072708 10, 0xFFFF, sum = 0
8580 23:57:02.075763 11, 0xFFFF, sum = 0
8581 23:57:02.076184 12, 0xFFFF, sum = 0
8582 23:57:02.079083 13, 0xFFFF, sum = 0
8583 23:57:02.079518 14, 0x0, sum = 1
8584 23:57:02.082274 15, 0x0, sum = 2
8585 23:57:02.082698 16, 0x0, sum = 3
8586 23:57:02.085650 17, 0x0, sum = 4
8587 23:57:02.086071 best_step = 15
8588 23:57:02.086396
8589 23:57:02.086698 ==
8590 23:57:02.089540 Dram Type= 6, Freq= 0, CH_1, rank 0
8591 23:57:02.095982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8592 23:57:02.096497 ==
8593 23:57:02.096827 RX Vref Scan: 1
8594 23:57:02.097132
8595 23:57:02.098948 Set Vref Range= 24 -> 127
8596 23:57:02.099363
8597 23:57:02.101745 RX Vref 24 -> 127, step: 1
8598 23:57:02.102160
8599 23:57:02.102490 RX Delay 19 -> 252, step: 4
8600 23:57:02.102801
8601 23:57:02.105203 Set Vref, RX VrefLevel [Byte0]: 24
8602 23:57:02.108593 [Byte1]: 24
8603 23:57:02.112620
8604 23:57:02.113035 Set Vref, RX VrefLevel [Byte0]: 25
8605 23:57:02.115716 [Byte1]: 25
8606 23:57:02.120262
8607 23:57:02.120677 Set Vref, RX VrefLevel [Byte0]: 26
8608 23:57:02.123557 [Byte1]: 26
8609 23:57:02.127917
8610 23:57:02.128343 Set Vref, RX VrefLevel [Byte0]: 27
8611 23:57:02.130845 [Byte1]: 27
8612 23:57:02.135121
8613 23:57:02.135536 Set Vref, RX VrefLevel [Byte0]: 28
8614 23:57:02.138391 [Byte1]: 28
8615 23:57:02.142857
8616 23:57:02.143272 Set Vref, RX VrefLevel [Byte0]: 29
8617 23:57:02.146429 [Byte1]: 29
8618 23:57:02.150466
8619 23:57:02.150881 Set Vref, RX VrefLevel [Byte0]: 30
8620 23:57:02.154078 [Byte1]: 30
8621 23:57:02.158637
8622 23:57:02.159050 Set Vref, RX VrefLevel [Byte0]: 31
8623 23:57:02.161666 [Byte1]: 31
8624 23:57:02.165816
8625 23:57:02.166231 Set Vref, RX VrefLevel [Byte0]: 32
8626 23:57:02.168945 [Byte1]: 32
8627 23:57:02.173708
8628 23:57:02.174347 Set Vref, RX VrefLevel [Byte0]: 33
8629 23:57:02.177150 [Byte1]: 33
8630 23:57:02.180876
8631 23:57:02.181333 Set Vref, RX VrefLevel [Byte0]: 34
8632 23:57:02.183911 [Byte1]: 34
8633 23:57:02.188925
8634 23:57:02.189365 Set Vref, RX VrefLevel [Byte0]: 35
8635 23:57:02.191446 [Byte1]: 35
8636 23:57:02.196403
8637 23:57:02.196819 Set Vref, RX VrefLevel [Byte0]: 36
8638 23:57:02.199201 [Byte1]: 36
8639 23:57:02.203961
8640 23:57:02.204460 Set Vref, RX VrefLevel [Byte0]: 37
8641 23:57:02.206905 [Byte1]: 37
8642 23:57:02.211084
8643 23:57:02.211604 Set Vref, RX VrefLevel [Byte0]: 38
8644 23:57:02.214897 [Byte1]: 38
8645 23:57:02.219031
8646 23:57:02.219539 Set Vref, RX VrefLevel [Byte0]: 39
8647 23:57:02.222234 [Byte1]: 39
8648 23:57:02.226380
8649 23:57:02.227024 Set Vref, RX VrefLevel [Byte0]: 40
8650 23:57:02.230019 [Byte1]: 40
8651 23:57:02.233856
8652 23:57:02.234315 Set Vref, RX VrefLevel [Byte0]: 41
8653 23:57:02.236912 [Byte1]: 41
8654 23:57:02.241885
8655 23:57:02.242438 Set Vref, RX VrefLevel [Byte0]: 42
8656 23:57:02.245218 [Byte1]: 42
8657 23:57:02.249127
8658 23:57:02.249584 Set Vref, RX VrefLevel [Byte0]: 43
8659 23:57:02.252168 [Byte1]: 43
8660 23:57:02.256976
8661 23:57:02.257646 Set Vref, RX VrefLevel [Byte0]: 44
8662 23:57:02.259637 [Byte1]: 44
8663 23:57:02.264259
8664 23:57:02.264771 Set Vref, RX VrefLevel [Byte0]: 45
8665 23:57:02.267387 [Byte1]: 45
8666 23:57:02.271601
8667 23:57:02.272015 Set Vref, RX VrefLevel [Byte0]: 46
8668 23:57:02.274717 [Byte1]: 46
8669 23:57:02.279465
8670 23:57:02.279878 Set Vref, RX VrefLevel [Byte0]: 47
8671 23:57:02.282695 [Byte1]: 47
8672 23:57:02.286627
8673 23:57:02.287039 Set Vref, RX VrefLevel [Byte0]: 48
8674 23:57:02.290310 [Byte1]: 48
8675 23:57:02.294456
8676 23:57:02.294906 Set Vref, RX VrefLevel [Byte0]: 49
8677 23:57:02.297525 [Byte1]: 49
8678 23:57:02.301934
8679 23:57:02.302447 Set Vref, RX VrefLevel [Byte0]: 50
8680 23:57:02.305366 [Byte1]: 50
8681 23:57:02.309884
8682 23:57:02.310402 Set Vref, RX VrefLevel [Byte0]: 51
8683 23:57:02.313044 [Byte1]: 51
8684 23:57:02.316933
8685 23:57:02.317389 Set Vref, RX VrefLevel [Byte0]: 52
8686 23:57:02.321118 [Byte1]: 52
8687 23:57:02.324797
8688 23:57:02.325288 Set Vref, RX VrefLevel [Byte0]: 53
8689 23:57:02.328666 [Byte1]: 53
8690 23:57:02.333093
8691 23:57:02.333540 Set Vref, RX VrefLevel [Byte0]: 54
8692 23:57:02.335524 [Byte1]: 54
8693 23:57:02.340244
8694 23:57:02.340753 Set Vref, RX VrefLevel [Byte0]: 55
8695 23:57:02.343126 [Byte1]: 55
8696 23:57:02.347543
8697 23:57:02.347960 Set Vref, RX VrefLevel [Byte0]: 56
8698 23:57:02.350466 [Byte1]: 56
8699 23:57:02.355138
8700 23:57:02.355638 Set Vref, RX VrefLevel [Byte0]: 57
8701 23:57:02.357975 [Byte1]: 57
8702 23:57:02.362282
8703 23:57:02.362695 Set Vref, RX VrefLevel [Byte0]: 58
8704 23:57:02.366647 [Byte1]: 58
8705 23:57:02.369990
8706 23:57:02.370522 Set Vref, RX VrefLevel [Byte0]: 59
8707 23:57:02.373452 [Byte1]: 59
8708 23:57:02.377775
8709 23:57:02.378189 Set Vref, RX VrefLevel [Byte0]: 60
8710 23:57:02.380998 [Byte1]: 60
8711 23:57:02.385659
8712 23:57:02.386106 Set Vref, RX VrefLevel [Byte0]: 61
8713 23:57:02.388257 [Byte1]: 61
8714 23:57:02.393255
8715 23:57:02.393707 Set Vref, RX VrefLevel [Byte0]: 62
8716 23:57:02.396080 [Byte1]: 62
8717 23:57:02.400622
8718 23:57:02.401201 Set Vref, RX VrefLevel [Byte0]: 63
8719 23:57:02.403683 [Byte1]: 63
8720 23:57:02.408356
8721 23:57:02.408874 Set Vref, RX VrefLevel [Byte0]: 64
8722 23:57:02.411604 [Byte1]: 64
8723 23:57:02.415516
8724 23:57:02.415936 Set Vref, RX VrefLevel [Byte0]: 65
8725 23:57:02.418654 [Byte1]: 65
8726 23:57:02.423675
8727 23:57:02.424087 Set Vref, RX VrefLevel [Byte0]: 66
8728 23:57:02.426676 [Byte1]: 66
8729 23:57:02.430987
8730 23:57:02.431496 Set Vref, RX VrefLevel [Byte0]: 67
8731 23:57:02.434056 [Byte1]: 67
8732 23:57:02.438366
8733 23:57:02.438886 Set Vref, RX VrefLevel [Byte0]: 68
8734 23:57:02.441352 [Byte1]: 68
8735 23:57:02.445862
8736 23:57:02.446603 Set Vref, RX VrefLevel [Byte0]: 69
8737 23:57:02.448952 [Byte1]: 69
8738 23:57:02.453431
8739 23:57:02.453959 Final RX Vref Byte 0 = 55 to rank0
8740 23:57:02.456788 Final RX Vref Byte 1 = 61 to rank0
8741 23:57:02.459922 Final RX Vref Byte 0 = 55 to rank1
8742 23:57:02.463355 Final RX Vref Byte 1 = 61 to rank1==
8743 23:57:02.466882 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 23:57:02.473131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 23:57:02.473602 ==
8746 23:57:02.473936 DQS Delay:
8747 23:57:02.474243 DQS0 = 0, DQS1 = 0
8748 23:57:02.477122 DQM Delay:
8749 23:57:02.477755 DQM0 = 132, DQM1 = 130
8750 23:57:02.480501 DQ Delay:
8751 23:57:02.483287 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8752 23:57:02.486274 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =126
8753 23:57:02.489507 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8754 23:57:02.493208 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8755 23:57:02.493664
8756 23:57:02.494021
8757 23:57:02.494533
8758 23:57:02.496190 [DramC_TX_OE_Calibration] TA2
8759 23:57:02.499267 Original DQ_B0 (3 6) =30, OEN = 27
8760 23:57:02.503116 Original DQ_B1 (3 6) =30, OEN = 27
8761 23:57:02.506249 24, 0x0, End_B0=24 End_B1=24
8762 23:57:02.509329 25, 0x0, End_B0=25 End_B1=25
8763 23:57:02.509756 26, 0x0, End_B0=26 End_B1=26
8764 23:57:02.513243 27, 0x0, End_B0=27 End_B1=27
8765 23:57:02.516170 28, 0x0, End_B0=28 End_B1=28
8766 23:57:02.519805 29, 0x0, End_B0=29 End_B1=29
8767 23:57:02.520442 30, 0x0, End_B0=30 End_B1=30
8768 23:57:02.522724 31, 0x4141, End_B0=30 End_B1=30
8769 23:57:02.526005 Byte0 end_step=30 best_step=27
8770 23:57:02.529329 Byte1 end_step=30 best_step=27
8771 23:57:02.533019 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 23:57:02.535844 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 23:57:02.536260
8774 23:57:02.536587
8775 23:57:02.542610 [DQSOSCAuto] RK0, (LSB)MR18= 0xe17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 402 ps
8776 23:57:02.545543 CH1 RK0: MR19=303, MR18=E17
8777 23:57:02.552145 CH1_RK0: MR19=0x303, MR18=0xE17, DQSOSC=398, MR23=63, INC=23, DEC=15
8778 23:57:02.552799
8779 23:57:02.555250 ----->DramcWriteLeveling(PI) begin...
8780 23:57:02.555765 ==
8781 23:57:02.559095 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 23:57:02.561833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 23:57:02.562254 ==
8784 23:57:02.565176 Write leveling (Byte 0): 26 => 26
8785 23:57:02.568441 Write leveling (Byte 1): 26 => 26
8786 23:57:02.571844 DramcWriteLeveling(PI) end<-----
8787 23:57:02.572269
8788 23:57:02.572643 ==
8789 23:57:02.575095 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 23:57:02.578565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 23:57:02.581987 ==
8792 23:57:02.582429 [Gating] SW mode calibration
8793 23:57:02.591769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 23:57:02.594883 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 23:57:02.598091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:57:02.604965 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:57:02.608438 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8798 23:57:02.611779 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8799 23:57:02.618556 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8800 23:57:02.621511 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 23:57:02.624676 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 23:57:02.631479 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 23:57:02.634345 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 23:57:02.637720 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
8805 23:57:02.644388 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8806 23:57:02.647969 1 5 12 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8807 23:57:02.650952 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8808 23:57:02.657687 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 23:57:02.660865 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 23:57:02.663949 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 23:57:02.671106 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 23:57:02.674243 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8813 23:57:02.677330 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8814 23:57:02.683738 1 6 12 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8815 23:57:02.687103 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:57:02.690568 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:57:02.696775 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 23:57:02.700039 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 23:57:02.703356 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 23:57:02.710575 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8821 23:57:02.713574 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8822 23:57:02.717020 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8823 23:57:02.723059 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8824 23:57:02.726569 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:57:02.729995 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:57:02.736461 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:57:02.739952 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:57:02.742966 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:57:02.749895 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:57:02.753232 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:57:02.756739 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:57:02.762955 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:57:02.766404 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:57:02.769485 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:57:02.775879 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:57:02.779531 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8837 23:57:02.782799 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8838 23:57:02.789174 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8839 23:57:02.792312 Total UI for P1: 0, mck2ui 16
8840 23:57:02.795835 best dqsien dly found for B0: ( 1, 9, 6)
8841 23:57:02.798952 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 23:57:02.802323 Total UI for P1: 0, mck2ui 16
8843 23:57:02.805510 best dqsien dly found for B1: ( 1, 9, 12)
8844 23:57:02.809082 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8845 23:57:02.812211 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8846 23:57:02.812742
8847 23:57:02.815542 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8848 23:57:02.822239 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8849 23:57:02.822658 [Gating] SW calibration Done
8850 23:57:02.822987 ==
8851 23:57:02.825471 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 23:57:02.831689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 23:57:02.832261 ==
8854 23:57:02.832748 RX Vref Scan: 0
8855 23:57:02.833214
8856 23:57:02.835134 RX Vref 0 -> 0, step: 1
8857 23:57:02.835546
8858 23:57:02.838704 RX Delay 0 -> 252, step: 8
8859 23:57:02.841917 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8860 23:57:02.845096 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8861 23:57:02.848337 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8862 23:57:02.855129 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8863 23:57:02.858248 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8864 23:57:02.861533 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8865 23:57:02.865373 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8866 23:57:02.868446 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8867 23:57:02.874773 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8868 23:57:02.878298 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8869 23:57:02.882142 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8870 23:57:02.884852 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8871 23:57:02.891672 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8872 23:57:02.894394 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8873 23:57:02.898026 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8874 23:57:02.901144 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8875 23:57:02.901594 ==
8876 23:57:02.904263 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 23:57:02.910880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 23:57:02.911301 ==
8879 23:57:02.911715 DQS Delay:
8880 23:57:02.914995 DQS0 = 0, DQS1 = 0
8881 23:57:02.915405 DQM Delay:
8882 23:57:02.915729 DQM0 = 136, DQM1 = 129
8883 23:57:02.917318 DQ Delay:
8884 23:57:02.921094 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8885 23:57:02.924073 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8886 23:57:02.927572 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8887 23:57:02.930425 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8888 23:57:02.930843
8889 23:57:02.931169
8890 23:57:02.931472 ==
8891 23:57:02.935140 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 23:57:02.937459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 23:57:02.940614 ==
8894 23:57:02.941026
8895 23:57:02.941397
8896 23:57:02.941714 TX Vref Scan disable
8897 23:57:02.943661 == TX Byte 0 ==
8898 23:57:02.947063 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8899 23:57:02.950713 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 23:57:02.953951 == TX Byte 1 ==
8901 23:57:02.957035 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8902 23:57:02.960233 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8903 23:57:02.963394 ==
8904 23:57:02.967168 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 23:57:02.970603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 23:57:02.971029 ==
8907 23:57:02.983958
8908 23:57:02.986509 TX Vref early break, caculate TX vref
8909 23:57:02.989673 TX Vref=16, minBit 9, minWin=21, winSum=375
8910 23:57:02.993179 TX Vref=18, minBit 9, minWin=22, winSum=385
8911 23:57:02.996450 TX Vref=20, minBit 9, minWin=22, winSum=392
8912 23:57:02.999984 TX Vref=22, minBit 9, minWin=23, winSum=400
8913 23:57:03.003493 TX Vref=24, minBit 9, minWin=23, winSum=406
8914 23:57:03.009214 TX Vref=26, minBit 9, minWin=23, winSum=413
8915 23:57:03.012959 TX Vref=28, minBit 9, minWin=25, winSum=419
8916 23:57:03.016144 TX Vref=30, minBit 3, minWin=25, winSum=418
8917 23:57:03.019236 TX Vref=32, minBit 9, minWin=24, winSum=411
8918 23:57:03.022543 TX Vref=34, minBit 8, minWin=24, winSum=404
8919 23:57:03.029364 TX Vref=36, minBit 8, minWin=23, winSum=393
8920 23:57:03.032153 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8921 23:57:03.032571
8922 23:57:03.035414 Final TX Range 0 Vref 28
8923 23:57:03.035829
8924 23:57:03.036153 ==
8925 23:57:03.038873 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 23:57:03.045167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 23:57:03.045772 ==
8928 23:57:03.046132
8929 23:57:03.046443
8930 23:57:03.046741 TX Vref Scan disable
8931 23:57:03.052458 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8932 23:57:03.052875 == TX Byte 0 ==
8933 23:57:03.056022 u2DelayCellOfst[0]=14 cells (4 PI)
8934 23:57:03.058891 u2DelayCellOfst[1]=10 cells (3 PI)
8935 23:57:03.062380 u2DelayCellOfst[2]=0 cells (0 PI)
8936 23:57:03.065856 u2DelayCellOfst[3]=3 cells (1 PI)
8937 23:57:03.069233 u2DelayCellOfst[4]=7 cells (2 PI)
8938 23:57:03.072333 u2DelayCellOfst[5]=14 cells (4 PI)
8939 23:57:03.075608 u2DelayCellOfst[6]=14 cells (4 PI)
8940 23:57:03.079381 u2DelayCellOfst[7]=3 cells (1 PI)
8941 23:57:03.082025 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8942 23:57:03.085859 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8943 23:57:03.088524 == TX Byte 1 ==
8944 23:57:03.092071 u2DelayCellOfst[8]=0 cells (0 PI)
8945 23:57:03.095378 u2DelayCellOfst[9]=3 cells (1 PI)
8946 23:57:03.098420 u2DelayCellOfst[10]=10 cells (3 PI)
8947 23:57:03.102318 u2DelayCellOfst[11]=3 cells (1 PI)
8948 23:57:03.105106 u2DelayCellOfst[12]=14 cells (4 PI)
8949 23:57:03.108498 u2DelayCellOfst[13]=14 cells (4 PI)
8950 23:57:03.111895 u2DelayCellOfst[14]=17 cells (5 PI)
8951 23:57:03.112403 u2DelayCellOfst[15]=14 cells (4 PI)
8952 23:57:03.118603 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8953 23:57:03.121676 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8954 23:57:03.125351 DramC Write-DBI on
8955 23:57:03.125782 ==
8956 23:57:03.128321 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 23:57:03.132038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 23:57:03.132559 ==
8959 23:57:03.132893
8960 23:57:03.133198
8961 23:57:03.134515 TX Vref Scan disable
8962 23:57:03.134945 == TX Byte 0 ==
8963 23:57:03.141222 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8964 23:57:03.141667 == TX Byte 1 ==
8965 23:57:03.147853 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8966 23:57:03.148357 DramC Write-DBI off
8967 23:57:03.148692
8968 23:57:03.149000 [DATLAT]
8969 23:57:03.151040 Freq=1600, CH1 RK1
8970 23:57:03.151456
8971 23:57:03.154494 DATLAT Default: 0xf
8972 23:57:03.154908 0, 0xFFFF, sum = 0
8973 23:57:03.157950 1, 0xFFFF, sum = 0
8974 23:57:03.158371 2, 0xFFFF, sum = 0
8975 23:57:03.161435 3, 0xFFFF, sum = 0
8976 23:57:03.161951 4, 0xFFFF, sum = 0
8977 23:57:03.164359 5, 0xFFFF, sum = 0
8978 23:57:03.164781 6, 0xFFFF, sum = 0
8979 23:57:03.168213 7, 0xFFFF, sum = 0
8980 23:57:03.168736 8, 0xFFFF, sum = 0
8981 23:57:03.170963 9, 0xFFFF, sum = 0
8982 23:57:03.171488 10, 0xFFFF, sum = 0
8983 23:57:03.174258 11, 0xFFFF, sum = 0
8984 23:57:03.174678 12, 0xFFFF, sum = 0
8985 23:57:03.177491 13, 0xFFFF, sum = 0
8986 23:57:03.177912 14, 0x0, sum = 1
8987 23:57:03.181219 15, 0x0, sum = 2
8988 23:57:03.181701 16, 0x0, sum = 3
8989 23:57:03.184082 17, 0x0, sum = 4
8990 23:57:03.184499 best_step = 15
8991 23:57:03.184826
8992 23:57:03.185134 ==
8993 23:57:03.187354 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 23:57:03.194419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 23:57:03.194839 ==
8996 23:57:03.195172 RX Vref Scan: 0
8997 23:57:03.195480
8998 23:57:03.197512 RX Vref 0 -> 0, step: 1
8999 23:57:03.197929
9000 23:57:03.200289 RX Delay 11 -> 252, step: 4
9001 23:57:03.203902 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
9002 23:57:03.207009 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9003 23:57:03.213705 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9004 23:57:03.217032 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
9005 23:57:03.221141 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
9006 23:57:03.223736 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9007 23:57:03.226577 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9008 23:57:03.233622 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9009 23:57:03.236684 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9010 23:57:03.239573 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9011 23:57:03.243184 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9012 23:57:03.246416 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9013 23:57:03.253395 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9014 23:57:03.256132 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9015 23:57:03.259702 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9016 23:57:03.262835 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9017 23:57:03.265960 ==
9018 23:57:03.269193 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 23:57:03.272871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 23:57:03.273444 ==
9021 23:57:03.273786 DQS Delay:
9022 23:57:03.276205 DQS0 = 0, DQS1 = 0
9023 23:57:03.276747 DQM Delay:
9024 23:57:03.279329 DQM0 = 132, DQM1 = 127
9025 23:57:03.279739 DQ Delay:
9026 23:57:03.282573 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9027 23:57:03.286235 DQ4 =132, DQ5 =144, DQ6 =140, DQ7 =128
9028 23:57:03.288856 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9029 23:57:03.292533 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
9030 23:57:03.292951
9031 23:57:03.293316
9032 23:57:03.293643
9033 23:57:03.295487 [DramC_TX_OE_Calibration] TA2
9034 23:57:03.299134 Original DQ_B0 (3 6) =30, OEN = 27
9035 23:57:03.302316 Original DQ_B1 (3 6) =30, OEN = 27
9036 23:57:03.305764 24, 0x0, End_B0=24 End_B1=24
9037 23:57:03.308949 25, 0x0, End_B0=25 End_B1=25
9038 23:57:03.311757 26, 0x0, End_B0=26 End_B1=26
9039 23:57:03.312181 27, 0x0, End_B0=27 End_B1=27
9040 23:57:03.315432 28, 0x0, End_B0=28 End_B1=28
9041 23:57:03.318411 29, 0x0, End_B0=29 End_B1=29
9042 23:57:03.322049 30, 0x0, End_B0=30 End_B1=30
9043 23:57:03.325018 31, 0x4141, End_B0=30 End_B1=30
9044 23:57:03.325471 Byte0 end_step=30 best_step=27
9045 23:57:03.328450 Byte1 end_step=30 best_step=27
9046 23:57:03.331834 Byte0 TX OE(2T, 0.5T) = (3, 3)
9047 23:57:03.334851 Byte1 TX OE(2T, 0.5T) = (3, 3)
9048 23:57:03.335267
9049 23:57:03.335596
9050 23:57:03.345435 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9051 23:57:03.345986 CH1 RK1: MR19=303, MR18=F1D
9052 23:57:03.351142 CH1_RK1: MR19=0x303, MR18=0xF1D, DQSOSC=395, MR23=63, INC=23, DEC=15
9053 23:57:03.354391 [RxdqsGatingPostProcess] freq 1600
9054 23:57:03.361784 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9055 23:57:03.364687 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 23:57:03.368094 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 23:57:03.371247 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 23:57:03.374569 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 23:57:03.375036 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 23:57:03.377832 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 23:57:03.380856 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 23:57:03.384337 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 23:57:03.387450 Pre-setting of DQS Precalculation
9064 23:57:03.394026 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9065 23:57:03.400348 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9066 23:57:03.407144 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 23:57:03.407709
9068 23:57:03.408214
9069 23:57:03.410733 [Calibration Summary] 3200 Mbps
9070 23:57:03.411154 CH 0, Rank 0
9071 23:57:03.414200 SW Impedance : PASS
9072 23:57:03.417454 DUTY Scan : NO K
9073 23:57:03.417876 ZQ Calibration : PASS
9074 23:57:03.420480 Jitter Meter : NO K
9075 23:57:03.423730 CBT Training : PASS
9076 23:57:03.424146 Write leveling : PASS
9077 23:57:03.427412 RX DQS gating : PASS
9078 23:57:03.431043 RX DQ/DQS(RDDQC) : PASS
9079 23:57:03.431562 TX DQ/DQS : PASS
9080 23:57:03.434403 RX DATLAT : PASS
9081 23:57:03.437102 RX DQ/DQS(Engine): PASS
9082 23:57:03.437549 TX OE : PASS
9083 23:57:03.440619 All Pass.
9084 23:57:03.441031
9085 23:57:03.441385 CH 0, Rank 1
9086 23:57:03.443458 SW Impedance : PASS
9087 23:57:03.443978 DUTY Scan : NO K
9088 23:57:03.447274 ZQ Calibration : PASS
9089 23:57:03.449989 Jitter Meter : NO K
9090 23:57:03.450416 CBT Training : PASS
9091 23:57:03.453251 Write leveling : PASS
9092 23:57:03.457125 RX DQS gating : PASS
9093 23:57:03.457706 RX DQ/DQS(RDDQC) : PASS
9094 23:57:03.460314 TX DQ/DQS : PASS
9095 23:57:03.460862 RX DATLAT : PASS
9096 23:57:03.463819 RX DQ/DQS(Engine): PASS
9097 23:57:03.466527 TX OE : PASS
9098 23:57:03.466989 All Pass.
9099 23:57:03.467354
9100 23:57:03.467693 CH 1, Rank 0
9101 23:57:03.469876 SW Impedance : PASS
9102 23:57:03.473242 DUTY Scan : NO K
9103 23:57:03.473792 ZQ Calibration : PASS
9104 23:57:03.476673 Jitter Meter : NO K
9105 23:57:03.479960 CBT Training : PASS
9106 23:57:03.480373 Write leveling : PASS
9107 23:57:03.483070 RX DQS gating : PASS
9108 23:57:03.486807 RX DQ/DQS(RDDQC) : PASS
9109 23:57:03.487350 TX DQ/DQS : PASS
9110 23:57:03.489977 RX DATLAT : PASS
9111 23:57:03.492874 RX DQ/DQS(Engine): PASS
9112 23:57:03.493320 TX OE : PASS
9113 23:57:03.496688 All Pass.
9114 23:57:03.497227
9115 23:57:03.497639 CH 1, Rank 1
9116 23:57:03.499548 SW Impedance : PASS
9117 23:57:03.499969 DUTY Scan : NO K
9118 23:57:03.503170 ZQ Calibration : PASS
9119 23:57:03.506163 Jitter Meter : NO K
9120 23:57:03.506585 CBT Training : PASS
9121 23:57:03.509514 Write leveling : PASS
9122 23:57:03.512478 RX DQS gating : PASS
9123 23:57:03.512895 RX DQ/DQS(RDDQC) : PASS
9124 23:57:03.516018 TX DQ/DQS : PASS
9125 23:57:03.519041 RX DATLAT : PASS
9126 23:57:03.519455 RX DQ/DQS(Engine): PASS
9127 23:57:03.522647 TX OE : PASS
9128 23:57:03.523058 All Pass.
9129 23:57:03.523383
9130 23:57:03.525720 DramC Write-DBI on
9131 23:57:03.529542 PER_BANK_REFRESH: Hybrid Mode
9132 23:57:03.529959 TX_TRACKING: ON
9133 23:57:03.539445 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9134 23:57:03.545462 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9135 23:57:03.552669 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9136 23:57:03.556072 [FAST_K] Save calibration result to emmc
9137 23:57:03.559337 sync common calibartion params.
9138 23:57:03.562836 sync cbt_mode0:1, 1:1
9139 23:57:03.565581 dram_init: ddr_geometry: 2
9140 23:57:03.566040 dram_init: ddr_geometry: 2
9141 23:57:03.569173 dram_init: ddr_geometry: 2
9142 23:57:03.572784 0:dram_rank_size:100000000
9143 23:57:03.575920 1:dram_rank_size:100000000
9144 23:57:03.578760 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9145 23:57:03.582029 DFS_SHUFFLE_HW_MODE: ON
9146 23:57:03.585357 dramc_set_vcore_voltage set vcore to 725000
9147 23:57:03.588530 Read voltage for 1600, 0
9148 23:57:03.588989 Vio18 = 0
9149 23:57:03.589387 Vcore = 725000
9150 23:57:03.591943 Vdram = 0
9151 23:57:03.592396 Vddq = 0
9152 23:57:03.592757 Vmddr = 0
9153 23:57:03.595225 switch to 3200 Mbps bootup
9154 23:57:03.598296 [DramcRunTimeConfig]
9155 23:57:03.598785 PHYPLL
9156 23:57:03.599150 DPM_CONTROL_AFTERK: ON
9157 23:57:03.601673 PER_BANK_REFRESH: ON
9158 23:57:03.604864 REFRESH_OVERHEAD_REDUCTION: ON
9159 23:57:03.608398 CMD_PICG_NEW_MODE: OFF
9160 23:57:03.608927 XRTWTW_NEW_MODE: ON
9161 23:57:03.611947 XRTRTR_NEW_MODE: ON
9162 23:57:03.612365 TX_TRACKING: ON
9163 23:57:03.614471 RDSEL_TRACKING: OFF
9164 23:57:03.614885 DQS Precalculation for DVFS: ON
9165 23:57:03.617792 RX_TRACKING: OFF
9166 23:57:03.618209 HW_GATING DBG: ON
9167 23:57:03.621244 ZQCS_ENABLE_LP4: ON
9168 23:57:03.624974 RX_PICG_NEW_MODE: ON
9169 23:57:03.625430 TX_PICG_NEW_MODE: ON
9170 23:57:03.627862 ENABLE_RX_DCM_DPHY: ON
9171 23:57:03.631136 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9172 23:57:03.634239 DUMMY_READ_FOR_TRACKING: OFF
9173 23:57:03.634685 !!! SPM_CONTROL_AFTERK: OFF
9174 23:57:03.637606 !!! SPM could not control APHY
9175 23:57:03.640859 IMPEDANCE_TRACKING: ON
9176 23:57:03.641296 TEMP_SENSOR: ON
9177 23:57:03.644715 HW_SAVE_FOR_SR: OFF
9178 23:57:03.647946 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9179 23:57:03.650808 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9180 23:57:03.651233 Read ODT Tracking: ON
9181 23:57:03.654039 Refresh Rate DeBounce: ON
9182 23:57:03.657360 DFS_NO_QUEUE_FLUSH: ON
9183 23:57:03.661035 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9184 23:57:03.661618 ENABLE_DFS_RUNTIME_MRW: OFF
9185 23:57:03.664370 DDR_RESERVE_NEW_MODE: ON
9186 23:57:03.667503 MR_CBT_SWITCH_FREQ: ON
9187 23:57:03.667922 =========================
9188 23:57:03.687562 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9189 23:57:03.691015 dram_init: ddr_geometry: 2
9190 23:57:03.709138 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9191 23:57:03.712435 dram_init: dram init end (result: 0)
9192 23:57:03.719087 DRAM-K: Full calibration passed in 24442 msecs
9193 23:57:03.722482 MRC: failed to locate region type 0.
9194 23:57:03.722905 DRAM rank0 size:0x100000000,
9195 23:57:03.725902 DRAM rank1 size=0x100000000
9196 23:57:03.735590 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9197 23:57:03.742089 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9198 23:57:03.748420 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9199 23:57:03.759114 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9200 23:57:03.759635 DRAM rank0 size:0x100000000,
9201 23:57:03.761761 DRAM rank1 size=0x100000000
9202 23:57:03.762178 CBMEM:
9203 23:57:03.765789 IMD: root @ 0xfffff000 254 entries.
9204 23:57:03.768640 IMD: root @ 0xffffec00 62 entries.
9205 23:57:03.775554 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9206 23:57:03.778643 WARNING: RO_VPD is uninitialized or empty.
9207 23:57:03.781584 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9208 23:57:03.789190 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9209 23:57:03.801910 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9210 23:57:03.813617 BS: romstage times (exec / console): total (unknown) / 23967 ms
9211 23:57:03.813988
9212 23:57:03.814230
9213 23:57:03.822837 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9214 23:57:03.826479 ARM64: Exception handlers installed.
9215 23:57:03.829968 ARM64: Testing exception
9216 23:57:03.832925 ARM64: Done test exception
9217 23:57:03.833056 Enumerating buses...
9218 23:57:03.836110 Show all devs... Before device enumeration.
9219 23:57:03.839462 Root Device: enabled 1
9220 23:57:03.842641 CPU_CLUSTER: 0: enabled 1
9221 23:57:03.842743 CPU: 00: enabled 1
9222 23:57:03.845897 Compare with tree...
9223 23:57:03.846006 Root Device: enabled 1
9224 23:57:03.849415 CPU_CLUSTER: 0: enabled 1
9225 23:57:03.853058 CPU: 00: enabled 1
9226 23:57:03.853143 Root Device scanning...
9227 23:57:03.856266 scan_static_bus for Root Device
9228 23:57:03.859100 CPU_CLUSTER: 0 enabled
9229 23:57:03.862757 scan_static_bus for Root Device done
9230 23:57:03.865947 scan_bus: bus Root Device finished in 8 msecs
9231 23:57:03.866029 done
9232 23:57:03.872346 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9233 23:57:03.876002 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9234 23:57:03.882209 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9235 23:57:03.888947 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9236 23:57:03.889045 Allocating resources...
9237 23:57:03.891850 Reading resources...
9238 23:57:03.895186 Root Device read_resources bus 0 link: 0
9239 23:57:03.899572 DRAM rank0 size:0x100000000,
9240 23:57:03.899659 DRAM rank1 size=0x100000000
9241 23:57:03.904893 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9242 23:57:03.904979 CPU: 00 missing read_resources
9243 23:57:03.911562 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9244 23:57:03.915112 Root Device read_resources bus 0 link: 0 done
9245 23:57:03.918116 Done reading resources.
9246 23:57:03.921368 Show resources in subtree (Root Device)...After reading.
9247 23:57:03.924786 Root Device child on link 0 CPU_CLUSTER: 0
9248 23:57:03.928008 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 23:57:03.938075 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 23:57:03.938168 CPU: 00
9251 23:57:03.944581 Root Device assign_resources, bus 0 link: 0
9252 23:57:03.947850 CPU_CLUSTER: 0 missing set_resources
9253 23:57:03.950982 Root Device assign_resources, bus 0 link: 0 done
9254 23:57:03.954415 Done setting resources.
9255 23:57:03.957412 Show resources in subtree (Root Device)...After assigning values.
9256 23:57:03.964414 Root Device child on link 0 CPU_CLUSTER: 0
9257 23:57:03.967255 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 23:57:03.974019 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 23:57:03.977164 CPU: 00
9260 23:57:03.977295 Done allocating resources.
9261 23:57:03.984787 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9262 23:57:03.987112 Enabling resources...
9263 23:57:03.987195 done.
9264 23:57:03.990252 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9265 23:57:03.993756 Initializing devices...
9266 23:57:03.993837 Root Device init
9267 23:57:03.997863 init hardware done!
9268 23:57:04.000484 0x00000018: ctrlr->caps
9269 23:57:04.000568 52.000 MHz: ctrlr->f_max
9270 23:57:04.003691 0.400 MHz: ctrlr->f_min
9271 23:57:04.007284 0x40ff8080: ctrlr->voltages
9272 23:57:04.007367 sclk: 390625
9273 23:57:04.007432 Bus Width = 1
9274 23:57:04.010988 sclk: 390625
9275 23:57:04.011069 Bus Width = 1
9276 23:57:04.013601 Early init status = 3
9277 23:57:04.016777 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9278 23:57:04.020575 in-header: 03 fc 00 00 01 00 00 00
9279 23:57:04.024497 in-data: 00
9280 23:57:04.027533 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9281 23:57:04.031966 in-header: 03 fd 00 00 00 00 00 00
9282 23:57:04.035911 in-data:
9283 23:57:04.038407 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9284 23:57:04.041977 in-header: 03 fc 00 00 01 00 00 00
9285 23:57:04.045212 in-data: 00
9286 23:57:04.048162 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9287 23:57:04.053136 in-header: 03 fd 00 00 00 00 00 00
9288 23:57:04.056145 in-data:
9289 23:57:04.059423 [SSUSB] Setting up USB HOST controller...
9290 23:57:04.063230 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9291 23:57:04.066595 [SSUSB] phy power-on done.
9292 23:57:04.069684 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9293 23:57:04.076259 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9294 23:57:04.079384 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9295 23:57:04.086020 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9296 23:57:04.093202 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9297 23:57:04.099617 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9298 23:57:04.105964 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9299 23:57:04.112509 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9300 23:57:04.115701 SPM: binary array size = 0x9dc
9301 23:57:04.119473 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9302 23:57:04.126579 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9303 23:57:04.132758 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9304 23:57:04.138930 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9305 23:57:04.142261 configure_display: Starting display init
9306 23:57:04.176665 anx7625_power_on_init: Init interface.
9307 23:57:04.180435 anx7625_disable_pd_protocol: Disabled PD feature.
9308 23:57:04.183265 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9309 23:57:04.210937 anx7625_start_dp_work: Secure OCM version=00
9310 23:57:04.213836 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9311 23:57:04.228762 sp_tx_get_edid_block: EDID Block = 1
9312 23:57:04.331359 Extracted contents:
9313 23:57:04.335171 header: 00 ff ff ff ff ff ff 00
9314 23:57:04.338668 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9315 23:57:04.341226 version: 01 04
9316 23:57:04.344492 basic params: 95 1f 11 78 0a
9317 23:57:04.348150 chroma info: 76 90 94 55 54 90 27 21 50 54
9318 23:57:04.351424 established: 00 00 00
9319 23:57:04.357832 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9320 23:57:04.361549 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9321 23:57:04.368640 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9322 23:57:04.374538 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9323 23:57:04.381008 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9324 23:57:04.384355 extensions: 00
9325 23:57:04.384438 checksum: fb
9326 23:57:04.384503
9327 23:57:04.387526 Manufacturer: IVO Model 57d Serial Number 0
9328 23:57:04.391192 Made week 0 of 2020
9329 23:57:04.394091 EDID version: 1.4
9330 23:57:04.394173 Digital display
9331 23:57:04.397234 6 bits per primary color channel
9332 23:57:04.397357 DisplayPort interface
9333 23:57:04.400419 Maximum image size: 31 cm x 17 cm
9334 23:57:04.404648 Gamma: 220%
9335 23:57:04.404729 Check DPMS levels
9336 23:57:04.410359 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9337 23:57:04.413699 First detailed timing is preferred timing
9338 23:57:04.416997 Established timings supported:
9339 23:57:04.417079 Standard timings supported:
9340 23:57:04.420421 Detailed timings
9341 23:57:04.423439 Hex of detail: 383680a07038204018303c0035ae10000019
9342 23:57:04.430158 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9343 23:57:04.434173 0780 0798 07c8 0820 hborder 0
9344 23:57:04.436543 0438 043b 0447 0458 vborder 0
9345 23:57:04.440566 -hsync -vsync
9346 23:57:04.440648 Did detailed timing
9347 23:57:04.446593 Hex of detail: 000000000000000000000000000000000000
9348 23:57:04.450332 Manufacturer-specified data, tag 0
9349 23:57:04.453377 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9350 23:57:04.456369 ASCII string: InfoVision
9351 23:57:04.459835 Hex of detail: 000000fe00523134304e574635205248200a
9352 23:57:04.463676 ASCII string: R140NWF5 RH
9353 23:57:04.463760 Checksum
9354 23:57:04.466437 Checksum: 0xfb (valid)
9355 23:57:04.470090 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9356 23:57:04.473524 DSI data_rate: 832800000 bps
9357 23:57:04.480193 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9358 23:57:04.483145 anx7625_parse_edid: pixelclock(138800).
9359 23:57:04.486498 hactive(1920), hsync(48), hfp(24), hbp(88)
9360 23:57:04.489989 vactive(1080), vsync(12), vfp(3), vbp(17)
9361 23:57:04.492732 anx7625_dsi_config: config dsi.
9362 23:57:04.499583 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9363 23:57:04.513497 anx7625_dsi_config: success to config DSI
9364 23:57:04.516608 anx7625_dp_start: MIPI phy setup OK.
9365 23:57:04.520036 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9366 23:57:04.523150 mtk_ddp_mode_set invalid vrefresh 60
9367 23:57:04.526600 main_disp_path_setup
9368 23:57:04.526739 ovl_layer_smi_id_en
9369 23:57:04.530132 ovl_layer_smi_id_en
9370 23:57:04.530344 ccorr_config
9371 23:57:04.530454 aal_config
9372 23:57:04.533855 gamma_config
9373 23:57:04.534027 postmask_config
9374 23:57:04.536301 dither_config
9375 23:57:04.540073 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9376 23:57:04.546660 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9377 23:57:04.550345 Root Device init finished in 551 msecs
9378 23:57:04.553214 CPU_CLUSTER: 0 init
9379 23:57:04.559860 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9380 23:57:04.566178 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9381 23:57:04.566378 APU_MBOX 0x190000b0 = 0x10001
9382 23:57:04.569486 APU_MBOX 0x190001b0 = 0x10001
9383 23:57:04.573173 APU_MBOX 0x190005b0 = 0x10001
9384 23:57:04.576370 APU_MBOX 0x190006b0 = 0x10001
9385 23:57:04.582576 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9386 23:57:04.592768 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9387 23:57:04.605323 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9388 23:57:04.611585 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9389 23:57:04.623320 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9390 23:57:04.632616 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9391 23:57:04.635922 CPU_CLUSTER: 0 init finished in 81 msecs
9392 23:57:04.639279 Devices initialized
9393 23:57:04.642235 Show all devs... After init.
9394 23:57:04.642417 Root Device: enabled 1
9395 23:57:04.645946 CPU_CLUSTER: 0: enabled 1
9396 23:57:04.649173 CPU: 00: enabled 1
9397 23:57:04.652856 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9398 23:57:04.655456 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9399 23:57:04.659230 ELOG: NV offset 0x57f000 size 0x1000
9400 23:57:04.665988 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9401 23:57:04.672972 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9402 23:57:04.676229 ELOG: Event(17) added with size 13 at 2024-05-29 23:57:04 UTC
9403 23:57:04.682023 out: cmd=0x121: 03 db 21 01 00 00 00 00
9404 23:57:04.685736 in-header: 03 e1 00 00 2c 00 00 00
9405 23:57:04.695765 in-data: 5c 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9406 23:57:04.702486 ELOG: Event(A1) added with size 10 at 2024-05-29 23:57:04 UTC
9407 23:57:04.708980 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9408 23:57:04.715757 ELOG: Event(A0) added with size 9 at 2024-05-29 23:57:04 UTC
9409 23:57:04.719323 elog_add_boot_reason: Logged dev mode boot
9410 23:57:04.725327 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9411 23:57:04.725749 Finalize devices...
9412 23:57:04.728802 Devices finalized
9413 23:57:04.732209 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9414 23:57:04.736136 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9415 23:57:04.738761 in-header: 03 07 00 00 08 00 00 00
9416 23:57:04.742024 in-data: aa e4 47 04 13 02 00 00
9417 23:57:04.744939 Chrome EC: UHEPI supported
9418 23:57:04.751733 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9419 23:57:04.754922 in-header: 03 a9 00 00 08 00 00 00
9420 23:57:04.758275 in-data: 84 60 60 08 00 00 00 00
9421 23:57:04.765607 ELOG: Event(91) added with size 10 at 2024-05-29 23:57:04 UTC
9422 23:57:04.768660 Chrome EC: clear events_b mask to 0x0000000020004000
9423 23:57:04.775087 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9424 23:57:04.778947 in-header: 03 fd 00 00 00 00 00 00
9425 23:57:04.779465 in-data:
9426 23:57:04.785690 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9427 23:57:04.788705 Writing coreboot table at 0xffe64000
9428 23:57:04.792315 0. 000000000010a000-0000000000113fff: RAMSTAGE
9429 23:57:04.795258 1. 0000000040000000-00000000400fffff: RAM
9430 23:57:04.801671 2. 0000000040100000-000000004032afff: RAMSTAGE
9431 23:57:04.805512 3. 000000004032b000-00000000545fffff: RAM
9432 23:57:04.809168 4. 0000000054600000-000000005465ffff: BL31
9433 23:57:04.811449 5. 0000000054660000-00000000ffe63fff: RAM
9434 23:57:04.818853 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9435 23:57:04.821370 7. 0000000100000000-000000023fffffff: RAM
9436 23:57:04.824862 Passing 5 GPIOs to payload:
9437 23:57:04.827972 NAME | PORT | POLARITY | VALUE
9438 23:57:04.834625 EC in RW | 0x000000aa | low | undefined
9439 23:57:04.838100 EC interrupt | 0x00000005 | low | undefined
9440 23:57:04.841455 TPM interrupt | 0x000000ab | high | undefined
9441 23:57:04.848209 SD card detect | 0x00000011 | high | undefined
9442 23:57:04.851404 speaker enable | 0x00000093 | high | undefined
9443 23:57:04.854604 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9444 23:57:04.858116 in-header: 03 f9 00 00 02 00 00 00
9445 23:57:04.861249 in-data: 02 00
9446 23:57:04.864497 ADC[4]: Raw value=901847 ID=7
9447 23:57:04.864917 ADC[3]: Raw value=213546 ID=1
9448 23:57:04.867941 RAM Code: 0x71
9449 23:57:04.871782 ADC[6]: Raw value=75000 ID=0
9450 23:57:04.872303 ADC[5]: Raw value=213916 ID=1
9451 23:57:04.874431 SKU Code: 0x1
9452 23:57:04.880855 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bd9a
9453 23:57:04.881310 coreboot table: 964 bytes.
9454 23:57:04.884379 IMD ROOT 0. 0xfffff000 0x00001000
9455 23:57:04.887758 IMD SMALL 1. 0xffffe000 0x00001000
9456 23:57:04.890409 RO MCACHE 2. 0xffffc000 0x00001104
9457 23:57:04.894587 CONSOLE 3. 0xfff7c000 0x00080000
9458 23:57:04.897439 FMAP 4. 0xfff7b000 0x00000452
9459 23:57:04.900443 TIME STAMP 5. 0xfff7a000 0x00000910
9460 23:57:04.904094 VBOOT WORK 6. 0xfff66000 0x00014000
9461 23:57:04.907909 RAMOOPS 7. 0xffe66000 0x00100000
9462 23:57:04.910709 COREBOOT 8. 0xffe64000 0x00002000
9463 23:57:04.913958 IMD small region:
9464 23:57:04.917922 IMD ROOT 0. 0xffffec00 0x00000400
9465 23:57:04.921442 VPD 1. 0xffffeb80 0x0000006c
9466 23:57:04.924605 MMC STATUS 2. 0xffffeb60 0x00000004
9467 23:57:04.926799 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9468 23:57:04.933822 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9469 23:57:04.974988 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9470 23:57:04.978843 Checking segment from ROM address 0x40100000
9471 23:57:04.981906 Checking segment from ROM address 0x4010001c
9472 23:57:04.988400 Loading segment from ROM address 0x40100000
9473 23:57:04.988824 code (compression=0)
9474 23:57:04.998060 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9475 23:57:05.004873 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9476 23:57:05.005568 it's not compressed!
9477 23:57:05.011338 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9478 23:57:05.017898 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9479 23:57:05.035567 Loading segment from ROM address 0x4010001c
9480 23:57:05.036092 Entry Point 0x80000000
9481 23:57:05.038831 Loaded segments
9482 23:57:05.042155 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9483 23:57:05.049153 Jumping to boot code at 0x80000000(0xffe64000)
9484 23:57:05.055665 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9485 23:57:05.062578 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9486 23:57:05.069735 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9487 23:57:05.073451 Checking segment from ROM address 0x40100000
9488 23:57:05.076697 Checking segment from ROM address 0x4010001c
9489 23:57:05.083187 Loading segment from ROM address 0x40100000
9490 23:57:05.083619 code (compression=1)
9491 23:57:05.090237 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9492 23:57:05.099151 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9493 23:57:05.099576 using LZMA
9494 23:57:05.108528 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9495 23:57:05.114772 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9496 23:57:05.118314 Loading segment from ROM address 0x4010001c
9497 23:57:05.121884 Entry Point 0x54601000
9498 23:57:05.122300 Loaded segments
9499 23:57:05.125224 NOTICE: MT8192 bl31_setup
9500 23:57:05.132015 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9501 23:57:05.135448 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9502 23:57:05.138579 WARNING: region 0:
9503 23:57:05.141952 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 23:57:05.142433 WARNING: region 1:
9505 23:57:05.148569 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9506 23:57:05.152064 WARNING: region 2:
9507 23:57:05.155516 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9508 23:57:05.158153 WARNING: region 3:
9509 23:57:05.164942 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 23:57:05.165509 WARNING: region 4:
9511 23:57:05.172465 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9512 23:57:05.173008 WARNING: region 5:
9513 23:57:05.175279 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 23:57:05.178857 WARNING: region 6:
9515 23:57:05.181328 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 23:57:05.184934 WARNING: region 7:
9517 23:57:05.188806 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 23:57:05.194520 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9519 23:57:05.198000 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9520 23:57:05.204612 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9521 23:57:05.207404 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9522 23:57:05.210973 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9523 23:57:05.217685 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9524 23:57:05.220958 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9525 23:57:05.227577 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9526 23:57:05.230658 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9527 23:57:05.234476 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9528 23:57:05.240715 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9529 23:57:05.243763 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9530 23:57:05.246906 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9531 23:57:05.253718 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9532 23:57:05.256749 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9533 23:57:05.263968 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9534 23:57:05.267021 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9535 23:57:05.270233 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9536 23:57:05.276977 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9537 23:57:05.280065 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9538 23:57:05.286246 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9539 23:57:05.289575 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9540 23:57:05.293739 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9541 23:57:05.299840 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9542 23:57:05.303345 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9543 23:57:05.309551 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9544 23:57:05.312683 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9545 23:57:05.316108 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9546 23:57:05.323108 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9547 23:57:05.326115 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9548 23:57:05.333015 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9549 23:57:05.336389 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9550 23:57:05.339672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9551 23:57:05.345835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9552 23:57:05.349798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9553 23:57:05.352396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9554 23:57:05.355455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9555 23:57:05.362268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9556 23:57:05.365647 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9557 23:57:05.368959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9558 23:57:05.372318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9559 23:57:05.378974 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9560 23:57:05.382115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9561 23:57:05.385981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9562 23:57:05.389151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9563 23:57:05.395106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9564 23:57:05.398529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9565 23:57:05.402265 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9566 23:57:05.408281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9567 23:57:05.412447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9568 23:57:05.418104 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9569 23:57:05.421455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9570 23:57:05.428738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9571 23:57:05.431546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9572 23:57:05.435406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9573 23:57:05.441243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9574 23:57:05.444620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9575 23:57:05.451302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9576 23:57:05.454627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9577 23:57:05.461161 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9578 23:57:05.464742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9579 23:57:05.470875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9580 23:57:05.474648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9581 23:57:05.481019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9582 23:57:05.484568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9583 23:57:05.487691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9584 23:57:05.494653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9585 23:57:05.497044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9586 23:57:05.504226 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9587 23:57:05.507328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9588 23:57:05.513590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9589 23:57:05.517014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9590 23:57:05.520217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9591 23:57:05.526678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9592 23:57:05.530271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9593 23:57:05.536694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9594 23:57:05.539837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9595 23:57:05.546321 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9596 23:57:05.550120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9597 23:57:05.556640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9598 23:57:05.559638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9599 23:57:05.566551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9600 23:57:05.569916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9601 23:57:05.573227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9602 23:57:05.579861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9603 23:57:05.583684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9604 23:57:05.590101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9605 23:57:05.593235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9606 23:57:05.599737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9607 23:57:05.602608 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9608 23:57:05.610195 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9609 23:57:05.613565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9610 23:57:05.616365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9611 23:57:05.622521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9612 23:57:05.626695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9613 23:57:05.632620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9614 23:57:05.636429 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9615 23:57:05.639111 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9616 23:57:05.645603 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9617 23:57:05.649179 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9618 23:57:05.652547 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9619 23:57:05.658844 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9620 23:57:05.662723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9621 23:57:05.665821 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9622 23:57:05.672373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9623 23:57:05.675510 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9624 23:57:05.681825 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9625 23:57:05.685152 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9626 23:57:05.688985 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9627 23:57:05.695229 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9628 23:57:05.698692 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9629 23:57:05.705132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9630 23:57:05.708320 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9631 23:57:05.714878 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9632 23:57:05.717867 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9633 23:57:05.721619 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9634 23:57:05.724488 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9635 23:57:05.731257 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9636 23:57:05.734471 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9637 23:57:05.741385 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9638 23:57:05.744747 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9639 23:57:05.747868 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9640 23:57:05.751265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9641 23:57:05.757553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9642 23:57:05.760907 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9643 23:57:05.764606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9644 23:57:05.771388 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9645 23:57:05.775029 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9646 23:57:05.781644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9647 23:57:05.784027 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9648 23:57:05.787386 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9649 23:57:05.793961 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9650 23:57:05.797155 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9651 23:57:05.805016 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9652 23:57:05.807366 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9653 23:57:05.810604 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9654 23:57:05.817586 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9655 23:57:05.820694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9656 23:57:05.827435 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9657 23:57:05.830267 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9658 23:57:05.833766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9659 23:57:05.840861 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9660 23:57:05.843364 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9661 23:57:05.850164 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9662 23:57:05.853439 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9663 23:57:05.856923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9664 23:57:05.863611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9665 23:57:05.867083 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9666 23:57:05.873938 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9667 23:57:05.876319 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9668 23:57:05.880122 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9669 23:57:05.886793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9670 23:57:05.889721 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9671 23:57:05.892867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9672 23:57:05.899718 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9673 23:57:05.902956 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9674 23:57:05.909865 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9675 23:57:05.912812 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9676 23:57:05.916237 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9677 23:57:05.923793 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9678 23:57:05.926538 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9679 23:57:05.932472 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9680 23:57:05.936510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9681 23:57:05.942483 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9682 23:57:05.945959 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9683 23:57:05.948836 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9684 23:57:05.955922 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9685 23:57:05.959144 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9686 23:57:05.965633 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9687 23:57:05.968594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9688 23:57:05.972247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9689 23:57:05.979219 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9690 23:57:05.981860 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9691 23:57:05.988743 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9692 23:57:05.992499 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9693 23:57:05.994884 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9694 23:57:06.002085 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9695 23:57:06.004991 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9696 23:57:06.011365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9697 23:57:06.015314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9698 23:57:06.018493 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9699 23:57:06.024846 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9700 23:57:06.028369 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9701 23:57:06.034644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9702 23:57:06.038671 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9703 23:57:06.041379 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9704 23:57:06.047870 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9705 23:57:06.051616 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9706 23:57:06.058020 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9707 23:57:06.061326 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9708 23:57:06.068431 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9709 23:57:06.070848 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9710 23:57:06.074775 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9711 23:57:06.081244 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9712 23:57:06.084125 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9713 23:57:06.090520 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9714 23:57:06.094460 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9715 23:57:06.101192 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9716 23:57:06.103805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9717 23:57:06.107099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9718 23:57:06.113863 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9719 23:57:06.117210 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9720 23:57:06.123811 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9721 23:57:06.126899 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9722 23:57:06.130247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9723 23:57:06.136706 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9724 23:57:06.139924 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9725 23:57:06.146635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9726 23:57:06.150162 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9727 23:57:06.157018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9728 23:57:06.159677 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9729 23:57:06.163361 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9730 23:57:06.170235 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9731 23:57:06.173628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9732 23:57:06.179845 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9733 23:57:06.182808 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9734 23:57:06.189781 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9735 23:57:06.193226 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9736 23:57:06.196546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9737 23:57:06.202421 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9738 23:57:06.206055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9739 23:57:06.213126 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9740 23:57:06.217195 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9741 23:57:06.222640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9742 23:57:06.226319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9743 23:57:06.229131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9744 23:57:06.235915 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9745 23:57:06.239039 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9746 23:57:06.245213 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9747 23:57:06.249425 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9748 23:57:06.252039 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9749 23:57:06.255340 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9750 23:57:06.262092 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9751 23:57:06.265576 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9752 23:57:06.268559 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9753 23:57:06.275502 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9754 23:57:06.278650 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9755 23:57:06.281649 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9756 23:57:06.288031 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9757 23:57:06.291771 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9758 23:57:06.298109 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9759 23:57:06.301328 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9760 23:57:06.305131 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9761 23:57:06.311609 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9762 23:57:06.314449 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9763 23:57:06.318102 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9764 23:57:06.324641 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9765 23:57:06.328300 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9766 23:57:06.334052 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9767 23:57:06.337427 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9768 23:57:06.341070 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9769 23:57:06.347886 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9770 23:57:06.350729 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9771 23:57:06.353772 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9772 23:57:06.360742 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9773 23:57:06.364024 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9774 23:57:06.370781 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9775 23:57:06.374029 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9776 23:57:06.376951 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9777 23:57:06.384008 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9778 23:57:06.386838 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9779 23:57:06.393243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9780 23:57:06.397182 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9781 23:57:06.400227 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9782 23:57:06.406833 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9783 23:57:06.409980 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9784 23:57:06.413398 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9785 23:57:06.419622 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9786 23:57:06.423309 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9787 23:57:06.427145 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9788 23:57:06.429630 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9789 23:57:06.436262 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9790 23:57:06.439826 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9791 23:57:06.443019 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9792 23:57:06.446824 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9793 23:57:06.453524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9794 23:57:06.456406 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9795 23:57:06.459593 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9796 23:57:06.466538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9797 23:57:06.468931 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9798 23:57:06.472351 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9799 23:57:06.475642 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9800 23:57:06.482649 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9801 23:57:06.485795 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9802 23:57:06.492088 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9803 23:57:06.495919 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9804 23:57:06.502114 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9805 23:57:06.505564 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9806 23:57:06.509316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9807 23:57:06.515561 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9808 23:57:06.518630 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9809 23:57:06.525405 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9810 23:57:06.528294 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9811 23:57:06.535081 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9812 23:57:06.538348 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9813 23:57:06.541286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9814 23:57:06.548196 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9815 23:57:06.551715 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9816 23:57:06.558156 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9817 23:57:06.561148 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9818 23:57:06.565052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9819 23:57:06.571342 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9820 23:57:06.574504 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9821 23:57:06.581436 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9822 23:57:06.584752 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9823 23:57:06.590901 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9824 23:57:06.594285 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9825 23:57:06.597885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9826 23:57:06.604044 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9827 23:57:06.607575 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9828 23:57:06.614150 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9829 23:57:06.617718 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9830 23:57:06.624211 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9831 23:57:06.628006 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9832 23:57:06.630485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9833 23:57:06.637024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9834 23:57:06.640642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9835 23:57:06.647676 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9836 23:57:06.650064 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9837 23:57:06.656538 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9838 23:57:06.660718 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9839 23:57:06.663444 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9840 23:57:06.670601 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9841 23:57:06.673332 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9842 23:57:06.679886 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9843 23:57:06.683755 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9844 23:57:06.686274 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9845 23:57:06.693239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9846 23:57:06.696669 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9847 23:57:06.702803 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9848 23:57:06.706188 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9849 23:57:06.709942 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9850 23:57:06.715960 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9851 23:57:06.719279 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9852 23:57:06.726263 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9853 23:57:06.729395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9854 23:57:06.735671 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9855 23:57:06.739417 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9856 23:57:06.742243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9857 23:57:06.749222 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9858 23:57:06.752254 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9859 23:57:06.758678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9860 23:57:06.762545 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9861 23:57:06.768928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9862 23:57:06.772368 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9863 23:57:06.775718 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9864 23:57:06.782188 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9865 23:57:06.785375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9866 23:57:06.792856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9867 23:57:06.795098 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9868 23:57:06.798852 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9869 23:57:06.805309 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9870 23:57:06.808824 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9871 23:57:06.814720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9872 23:57:06.818075 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9873 23:57:06.825043 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9874 23:57:06.828207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9875 23:57:06.831093 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9876 23:57:06.838017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9877 23:57:06.841196 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9878 23:57:06.847918 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9879 23:57:06.851271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9880 23:57:06.858053 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9881 23:57:06.861036 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9882 23:57:06.867637 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9883 23:57:06.871169 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9884 23:57:06.877489 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9885 23:57:06.881054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9886 23:57:06.883883 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9887 23:57:06.890440 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9888 23:57:06.893890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9889 23:57:06.900453 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9890 23:57:06.903989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9891 23:57:06.910370 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9892 23:57:06.913778 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9893 23:57:06.920509 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9894 23:57:06.924510 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9895 23:57:06.926795 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9896 23:57:06.933195 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9897 23:57:06.936940 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9898 23:57:06.943098 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9899 23:57:06.946591 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9900 23:57:06.953279 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9901 23:57:06.956619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9902 23:57:06.963016 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9903 23:57:06.966613 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9904 23:57:06.969657 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9905 23:57:06.976397 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9906 23:57:06.979808 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9907 23:57:06.986015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9908 23:57:06.989148 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9909 23:57:06.995871 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9910 23:57:06.999016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9911 23:57:07.006489 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9912 23:57:07.009671 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9913 23:57:07.012336 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9914 23:57:07.019213 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9915 23:57:07.023019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9916 23:57:07.028731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9917 23:57:07.032138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9918 23:57:07.039010 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9919 23:57:07.042002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9920 23:57:07.045130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9921 23:57:07.052101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9922 23:57:07.055412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9923 23:57:07.061643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9924 23:57:07.065537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9925 23:57:07.072310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9926 23:57:07.074992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9927 23:57:07.082382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9928 23:57:07.084878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9929 23:57:07.091872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9930 23:57:07.095228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9931 23:57:07.101066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9932 23:57:07.104473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9933 23:57:07.111048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9934 23:57:07.114576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9935 23:57:07.120754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9936 23:57:07.124768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9937 23:57:07.130493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9938 23:57:07.134462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9939 23:57:07.141074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9940 23:57:07.144200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9941 23:57:07.150692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9942 23:57:07.154058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9943 23:57:07.161691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9944 23:57:07.164215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9945 23:57:07.170620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9946 23:57:07.173842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9947 23:57:07.180580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9948 23:57:07.183849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9949 23:57:07.189761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9950 23:57:07.193622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9951 23:57:07.199704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9952 23:57:07.203645 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9953 23:57:07.206547 INFO: [APUAPC] vio 0
9954 23:57:07.209938 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9955 23:57:07.216065 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9956 23:57:07.219403 INFO: [APUAPC] D0_APC_0: 0x400510
9957 23:57:07.222972 INFO: [APUAPC] D0_APC_1: 0x0
9958 23:57:07.226557 INFO: [APUAPC] D0_APC_2: 0x1540
9959 23:57:07.226975 INFO: [APUAPC] D0_APC_3: 0x0
9960 23:57:07.233209 INFO: [APUAPC] D1_APC_0: 0xffffffff
9961 23:57:07.236681 INFO: [APUAPC] D1_APC_1: 0xffffffff
9962 23:57:07.239541 INFO: [APUAPC] D1_APC_2: 0x3fffff
9963 23:57:07.240049 INFO: [APUAPC] D1_APC_3: 0x0
9964 23:57:07.242527 INFO: [APUAPC] D2_APC_0: 0xffffffff
9965 23:57:07.249405 INFO: [APUAPC] D2_APC_1: 0xffffffff
9966 23:57:07.252267 INFO: [APUAPC] D2_APC_2: 0x3fffff
9967 23:57:07.252685 INFO: [APUAPC] D2_APC_3: 0x0
9968 23:57:07.255877 INFO: [APUAPC] D3_APC_0: 0xffffffff
9969 23:57:07.259274 INFO: [APUAPC] D3_APC_1: 0xffffffff
9970 23:57:07.262921 INFO: [APUAPC] D3_APC_2: 0x3fffff
9971 23:57:07.265625 INFO: [APUAPC] D3_APC_3: 0x0
9972 23:57:07.269165 INFO: [APUAPC] D4_APC_0: 0xffffffff
9973 23:57:07.272531 INFO: [APUAPC] D4_APC_1: 0xffffffff
9974 23:57:07.275680 INFO: [APUAPC] D4_APC_2: 0x3fffff
9975 23:57:07.279042 INFO: [APUAPC] D4_APC_3: 0x0
9976 23:57:07.282245 INFO: [APUAPC] D5_APC_0: 0xffffffff
9977 23:57:07.285607 INFO: [APUAPC] D5_APC_1: 0xffffffff
9978 23:57:07.289478 INFO: [APUAPC] D5_APC_2: 0x3fffff
9979 23:57:07.292400 INFO: [APUAPC] D5_APC_3: 0x0
9980 23:57:07.295364 INFO: [APUAPC] D6_APC_0: 0xffffffff
9981 23:57:07.298819 INFO: [APUAPC] D6_APC_1: 0xffffffff
9982 23:57:07.302327 INFO: [APUAPC] D6_APC_2: 0x3fffff
9983 23:57:07.305111 INFO: [APUAPC] D6_APC_3: 0x0
9984 23:57:07.308511 INFO: [APUAPC] D7_APC_0: 0xffffffff
9985 23:57:07.311929 INFO: [APUAPC] D7_APC_1: 0xffffffff
9986 23:57:07.315022 INFO: [APUAPC] D7_APC_2: 0x3fffff
9987 23:57:07.319133 INFO: [APUAPC] D7_APC_3: 0x0
9988 23:57:07.322334 INFO: [APUAPC] D8_APC_0: 0xffffffff
9989 23:57:07.325117 INFO: [APUAPC] D8_APC_1: 0xffffffff
9990 23:57:07.328500 INFO: [APUAPC] D8_APC_2: 0x3fffff
9991 23:57:07.331542 INFO: [APUAPC] D8_APC_3: 0x0
9992 23:57:07.335250 INFO: [APUAPC] D9_APC_0: 0xffffffff
9993 23:57:07.337974 INFO: [APUAPC] D9_APC_1: 0xffffffff
9994 23:57:07.341617 INFO: [APUAPC] D9_APC_2: 0x3fffff
9995 23:57:07.344880 INFO: [APUAPC] D9_APC_3: 0x0
9996 23:57:07.348136 INFO: [APUAPC] D10_APC_0: 0xffffffff
9997 23:57:07.351951 INFO: [APUAPC] D10_APC_1: 0xffffffff
9998 23:57:07.354975 INFO: [APUAPC] D10_APC_2: 0x3fffff
9999 23:57:07.357861 INFO: [APUAPC] D10_APC_3: 0x0
10000 23:57:07.361641 INFO: [APUAPC] D11_APC_0: 0xffffffff
10001 23:57:07.365416 INFO: [APUAPC] D11_APC_1: 0xffffffff
10002 23:57:07.368074 INFO: [APUAPC] D11_APC_2: 0x3fffff
10003 23:57:07.371402 INFO: [APUAPC] D11_APC_3: 0x0
10004 23:57:07.374904 INFO: [APUAPC] D12_APC_0: 0xffffffff
10005 23:57:07.378170 INFO: [APUAPC] D12_APC_1: 0xffffffff
10006 23:57:07.381280 INFO: [APUAPC] D12_APC_2: 0x3fffff
10007 23:57:07.384440 INFO: [APUAPC] D12_APC_3: 0x0
10008 23:57:07.387607 INFO: [APUAPC] D13_APC_0: 0xffffffff
10009 23:57:07.391045 INFO: [APUAPC] D13_APC_1: 0xffffffff
10010 23:57:07.394467 INFO: [APUAPC] D13_APC_2: 0x3fffff
10011 23:57:07.397374 INFO: [APUAPC] D13_APC_3: 0x0
10012 23:57:07.400697 INFO: [APUAPC] D14_APC_0: 0xffffffff
10013 23:57:07.404101 INFO: [APUAPC] D14_APC_1: 0xffffffff
10014 23:57:07.407432 INFO: [APUAPC] D14_APC_2: 0x3fffff
10015 23:57:07.410227 INFO: [APUAPC] D14_APC_3: 0x0
10016 23:57:07.413978 INFO: [APUAPC] D15_APC_0: 0xffffffff
10017 23:57:07.417848 INFO: [APUAPC] D15_APC_1: 0xffffffff
10018 23:57:07.420518 INFO: [APUAPC] D15_APC_2: 0x3fffff
10019 23:57:07.423859 INFO: [APUAPC] D15_APC_3: 0x0
10020 23:57:07.426894 INFO: [APUAPC] APC_CON: 0x4
10021 23:57:07.430327 INFO: [NOCDAPC] D0_APC_0: 0x0
10022 23:57:07.433992 INFO: [NOCDAPC] D0_APC_1: 0x0
10023 23:57:07.437120 INFO: [NOCDAPC] D1_APC_0: 0x0
10024 23:57:07.440671 INFO: [NOCDAPC] D1_APC_1: 0xfff
10025 23:57:07.443548 INFO: [NOCDAPC] D2_APC_0: 0x0
10026 23:57:07.446805 INFO: [NOCDAPC] D2_APC_1: 0xfff
10027 23:57:07.450198 INFO: [NOCDAPC] D3_APC_0: 0x0
10028 23:57:07.453336 INFO: [NOCDAPC] D3_APC_1: 0xfff
10029 23:57:07.453895 INFO: [NOCDAPC] D4_APC_0: 0x0
10030 23:57:07.456493 INFO: [NOCDAPC] D4_APC_1: 0xfff
10031 23:57:07.459838 INFO: [NOCDAPC] D5_APC_0: 0x0
10032 23:57:07.462895 INFO: [NOCDAPC] D5_APC_1: 0xfff
10033 23:57:07.466050 INFO: [NOCDAPC] D6_APC_0: 0x0
10034 23:57:07.469613 INFO: [NOCDAPC] D6_APC_1: 0xfff
10035 23:57:07.472936 INFO: [NOCDAPC] D7_APC_0: 0x0
10036 23:57:07.476317 INFO: [NOCDAPC] D7_APC_1: 0xfff
10037 23:57:07.479652 INFO: [NOCDAPC] D8_APC_0: 0x0
10038 23:57:07.482987 INFO: [NOCDAPC] D8_APC_1: 0xfff
10039 23:57:07.485944 INFO: [NOCDAPC] D9_APC_0: 0x0
10040 23:57:07.489177 INFO: [NOCDAPC] D9_APC_1: 0xfff
10041 23:57:07.489834 INFO: [NOCDAPC] D10_APC_0: 0x0
10042 23:57:07.493440 INFO: [NOCDAPC] D10_APC_1: 0xfff
10043 23:57:07.496014 INFO: [NOCDAPC] D11_APC_0: 0x0
10044 23:57:07.499238 INFO: [NOCDAPC] D11_APC_1: 0xfff
10045 23:57:07.502773 INFO: [NOCDAPC] D12_APC_0: 0x0
10046 23:57:07.506306 INFO: [NOCDAPC] D12_APC_1: 0xfff
10047 23:57:07.508989 INFO: [NOCDAPC] D13_APC_0: 0x0
10048 23:57:07.512286 INFO: [NOCDAPC] D13_APC_1: 0xfff
10049 23:57:07.515823 INFO: [NOCDAPC] D14_APC_0: 0x0
10050 23:57:07.519800 INFO: [NOCDAPC] D14_APC_1: 0xfff
10051 23:57:07.522278 INFO: [NOCDAPC] D15_APC_0: 0x0
10052 23:57:07.525308 INFO: [NOCDAPC] D15_APC_1: 0xfff
10053 23:57:07.529036 INFO: [NOCDAPC] APC_CON: 0x4
10054 23:57:07.532347 INFO: [APUAPC] set_apusys_apc done
10055 23:57:07.535776 INFO: [DEVAPC] devapc_init done
10056 23:57:07.538556 INFO: GICv3 without legacy support detected.
10057 23:57:07.542380 INFO: ARM GICv3 driver initialized in EL3
10058 23:57:07.545620 INFO: Maximum SPI INTID supported: 639
10059 23:57:07.548417 INFO: BL31: Initializing runtime services
10060 23:57:07.555545 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10061 23:57:07.558525 INFO: SPM: enable CPC mode
10062 23:57:07.565384 INFO: mcdi ready for mcusys-off-idle and system suspend
10063 23:57:07.568422 INFO: BL31: Preparing for EL3 exit to normal world
10064 23:57:07.571977 INFO: Entry point address = 0x80000000
10065 23:57:07.574855 INFO: SPSR = 0x8
10066 23:57:07.580161
10067 23:57:07.580674
10068 23:57:07.581003
10069 23:57:07.583844 Starting depthcharge on Spherion...
10070 23:57:07.584550
10071 23:57:07.585102 Wipe memory regions:
10072 23:57:07.585499
10073 23:57:07.587767 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10074 23:57:07.588254 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10075 23:57:07.588671 Setting prompt string to ['asurada:']
10076 23:57:07.589149 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10077 23:57:07.590155 [0x00000040000000, 0x00000054600000)
10078 23:57:07.709323
10079 23:57:07.709836 [0x00000054660000, 0x00000080000000)
10080 23:57:07.969818
10081 23:57:07.970479 [0x000000821a7280, 0x000000ffe64000)
10082 23:57:08.715035
10083 23:57:08.715640 [0x00000100000000, 0x00000240000000)
10084 23:57:10.605087
10085 23:57:10.608224 Initializing XHCI USB controller at 0x11200000.
10086 23:57:11.646166
10087 23:57:11.649205 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10088 23:57:11.649720
10089 23:57:11.650086
10090 23:57:11.650933 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 23:57:11.752151 asurada: tftpboot 192.168.201.1 14084381/tftp-deploy-y63n22rm/kernel/image.itb 14084381/tftp-deploy-y63n22rm/kernel/cmdline
10093 23:57:11.752796 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 23:57:11.753221 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10095 23:57:11.757626 tftpboot 192.168.201.1 14084381/tftp-deploy-y63n22rm/kernel/image.ittp-deploy-y63n22rm/kernel/cmdline
10096 23:57:11.758102
10097 23:57:11.758467 Waiting for link
10098 23:57:11.916468
10099 23:57:11.917027 R8152: Initializing
10100 23:57:11.917419
10101 23:57:11.919020 Version 6 (ocp_data = 5c30)
10102 23:57:11.919485
10103 23:57:11.922758 R8152: Done initializing
10104 23:57:11.923316
10105 23:57:11.923687 Adding net device
10106 23:57:13.887277
10107 23:57:13.887793 done.
10108 23:57:13.888128
10109 23:57:13.888442 MAC: 00:24:32:30:7c:7b
10110 23:57:13.888743
10111 23:57:13.890403 Sending DHCP discover... done.
10112 23:57:13.890829
10113 23:57:17.063453 Waiting for reply... done.
10114 23:57:17.064148
10115 23:57:17.064533 Sending DHCP request... done.
10116 23:57:17.066263
10117 23:57:17.066721 Waiting for reply... done.
10118 23:57:17.067083
10119 23:57:17.069780 My ip is 192.168.201.14
10120 23:57:17.070241
10121 23:57:17.072985 The DHCP server ip is 192.168.201.1
10122 23:57:17.073451
10123 23:57:17.076932 TFTP server IP predefined by user: 192.168.201.1
10124 23:57:17.077396
10125 23:57:17.082804 Bootfile predefined by user: 14084381/tftp-deploy-y63n22rm/kernel/image.itb
10126 23:57:17.083227
10127 23:57:17.086654 Sending tftp read request... done.
10128 23:57:17.087074
10129 23:57:17.094408 Waiting for the transfer...
10130 23:57:17.094920
10131 23:57:17.748498 00000000 ################################################################
10132 23:57:17.749021
10133 23:57:18.406507 00080000 ################################################################
10134 23:57:18.407013
10135 23:57:19.065358 00100000 ################################################################
10136 23:57:19.065880
10137 23:57:19.748211 00180000 ################################################################
10138 23:57:19.748740
10139 23:57:20.401098 00200000 ################################################################
10140 23:57:20.401672
10141 23:57:21.080275 00280000 ################################################################
10142 23:57:21.080792
10143 23:57:21.742063 00300000 ################################################################
10144 23:57:21.742604
10145 23:57:22.412541 00380000 ################################################################
10146 23:57:22.413135
10147 23:57:23.079822 00400000 ################################################################
10148 23:57:23.080521
10149 23:57:23.756771 00480000 ################################################################
10150 23:57:23.757316
10151 23:57:24.427570 00500000 ################################################################
10152 23:57:24.428072
10153 23:57:25.075096 00580000 ################################################################
10154 23:57:25.075608
10155 23:57:25.748039 00600000 ################################################################
10156 23:57:25.748543
10157 23:57:26.413998 00680000 ################################################################
10158 23:57:26.414516
10159 23:57:27.056129 00700000 ################################################################
10160 23:57:27.056657
10161 23:57:27.726990 00780000 ################################################################
10162 23:57:27.727510
10163 23:57:28.397972 00800000 ################################################################
10164 23:57:28.398522
10165 23:57:29.064538 00880000 ################################################################
10166 23:57:29.065080
10167 23:57:29.742100 00900000 ################################################################
10168 23:57:29.742662
10169 23:57:30.417371 00980000 ################################################################
10170 23:57:30.417884
10171 23:57:31.087037 00a00000 ################################################################
10172 23:57:31.087557
10173 23:57:31.767217 00a80000 ################################################################
10174 23:57:31.767725
10175 23:57:32.438885 00b00000 ################################################################
10176 23:57:32.439524
10177 23:57:33.114770 00b80000 ################################################################
10178 23:57:33.115276
10179 23:57:33.782619 00c00000 ################################################################
10180 23:57:33.783162
10181 23:57:34.440622 00c80000 ################################################################
10182 23:57:34.441140
10183 23:57:35.119066 00d00000 ################################################################
10184 23:57:35.119742
10185 23:57:35.803403 00d80000 ################################################################
10186 23:57:35.803941
10187 23:57:36.474607 00e00000 ################################################################
10188 23:57:36.475118
10189 23:57:37.153571 00e80000 ################################################################
10190 23:57:37.154069
10191 23:57:37.828780 00f00000 ################################################################
10192 23:57:37.829320
10193 23:57:38.496934 00f80000 ################################################################
10194 23:57:38.497469
10195 23:57:39.149367 01000000 ################################################################
10196 23:57:39.149881
10197 23:57:39.826680 01080000 ################################################################
10198 23:57:39.827196
10199 23:57:40.503550 01100000 ################################################################
10200 23:57:40.504065
10201 23:57:41.167063 01180000 ################################################################
10202 23:57:41.167561
10203 23:57:41.820107 01200000 ################################################################
10204 23:57:41.820614
10205 23:57:42.485149 01280000 ################################################################
10206 23:57:42.485698
10207 23:57:43.176262 01300000 ################################################################
10208 23:57:43.176941
10209 23:57:43.846857 01380000 ################################################################
10210 23:57:43.847377
10211 23:57:44.530522 01400000 ################################################################
10212 23:57:44.531077
10213 23:57:45.205946 01480000 ################################################################
10214 23:57:45.206481
10215 23:57:45.879911 01500000 ################################################################
10216 23:57:45.880504
10217 23:57:46.556745 01580000 ################################################################
10218 23:57:46.557472
10219 23:57:47.241984 01600000 ################################################################
10220 23:57:47.242513
10221 23:57:47.922097 01680000 ################################################################
10222 23:57:47.922672
10223 23:57:48.604695 01700000 ################################################################
10224 23:57:48.605249
10225 23:57:49.287432 01780000 ################################################################
10226 23:57:49.288011
10227 23:57:49.967726 01800000 ################################################################
10228 23:57:49.968270
10229 23:57:50.653380 01880000 ################################################################
10230 23:57:50.653926
10231 23:57:51.321617 01900000 ################################################################
10232 23:57:51.322154
10233 23:57:51.962587 01980000 ################################################################
10234 23:57:51.962737
10235 23:57:52.613223 01a00000 ################################################################
10236 23:57:52.613810
10237 23:57:53.281636 01a80000 ################################################################
10238 23:57:53.282157
10239 23:57:53.950666 01b00000 ################################################################
10240 23:57:53.951199
10241 23:57:54.618975 01b80000 ################################################################
10242 23:57:54.619556
10243 23:57:55.288109 01c00000 ################################################################
10244 23:57:55.288605
10245 23:57:55.950290 01c80000 ################################################################
10246 23:57:55.950867
10247 23:57:56.628798 01d00000 ################################################################
10248 23:57:56.629353
10249 23:57:57.299585 01d80000 ################################################################
10250 23:57:57.300088
10251 23:57:57.770873 01e00000 ############################################## done.
10252 23:57:57.771385
10253 23:57:57.773852 The bootfile was 31832610 bytes long.
10254 23:57:57.774419
10255 23:57:57.777403 Sending tftp read request... done.
10256 23:57:57.777827
10257 23:57:57.781605 Waiting for the transfer...
10258 23:57:57.782027
10259 23:57:57.782357 00000000 # done.
10260 23:57:57.782679
10261 23:57:57.788278 Command line loaded dynamically from TFTP file: 14084381/tftp-deploy-y63n22rm/kernel/cmdline
10262 23:57:57.788703
10263 23:57:57.810937 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10264 23:57:57.811469
10265 23:57:57.811803 Loading FIT.
10266 23:57:57.815093
10267 23:57:57.815513 Image ramdisk-1 has 18719830 bytes.
10268 23:57:57.815845
10269 23:57:57.818268 Image fdt-1 has 47258 bytes.
10270 23:57:57.818688
10271 23:57:57.821056 Image kernel-1 has 13063488 bytes.
10272 23:57:57.821559
10273 23:57:57.831668 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10274 23:57:57.832197
10275 23:57:57.848355 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10276 23:57:57.848895
10277 23:57:57.854341 Choosing best match conf-1 for compat google,spherion-rev2.
10278 23:57:57.854756
10279 23:57:57.862331 Connected to device vid:did:rid of 1ae0:0028:00
10280 23:57:57.870627
10281 23:57:57.873722 tpm_get_response: command 0x17b, return code 0x0
10282 23:57:57.874272
10283 23:57:57.880555 ec_init: CrosEC protocol v3 supported (256, 248)
10284 23:57:57.881065
10285 23:57:57.884498 tpm_cleanup: add release locality here.
10286 23:57:57.884914
10287 23:57:57.887182 Shutting down all USB controllers.
10288 23:57:57.887767
10289 23:57:57.890736 Removing current net device
10290 23:57:57.891243
10291 23:57:57.893748 Exiting depthcharge with code 4 at timestamp: 79571754
10292 23:57:57.894263
10293 23:57:57.900307 LZMA decompressing kernel-1 to 0x821a6718
10294 23:57:57.901017
10295 23:57:57.904248 LZMA decompressing kernel-1 to 0x40000000
10296 23:57:59.513469
10297 23:57:59.514009 jumping to kernel
10298 23:57:59.515809 end: 2.2.4 bootloader-commands (duration 00:00:52) [common]
10299 23:57:59.516339 start: 2.2.5 auto-login-action (timeout 00:03:35) [common]
10300 23:57:59.516774 Setting prompt string to ['Linux version [0-9]']
10301 23:57:59.517154 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10302 23:57:59.517577 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10303 23:57:59.595833
10304 23:57:59.599252 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10305 23:57:59.602404 start: 2.2.5.1 login-action (timeout 00:03:35) [common]
10306 23:57:59.602965 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10307 23:57:59.603361 Setting prompt string to []
10308 23:57:59.603769 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10309 23:57:59.604170 Using line separator: #'\n'#
10310 23:57:59.604504 No login prompt set.
10311 23:57:59.604831 Parsing kernel messages
10312 23:57:59.605140 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10313 23:57:59.605739 [login-action] Waiting for messages, (timeout 00:03:35)
10314 23:57:59.606105 Waiting using forced prompt support (timeout 00:01:47)
10315 23:57:59.621753 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10316 23:57:59.625180 [ 0.000000] random: crng init done
10317 23:57:59.632246 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10318 23:57:59.635765 [ 0.000000] efi: UEFI not found.
10319 23:57:59.641692 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10320 23:57:59.648633 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10321 23:57:59.658184 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10322 23:57:59.668479 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10323 23:57:59.675546 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10324 23:57:59.681889 [ 0.000000] printk: bootconsole [mtk8250] enabled
10325 23:57:59.688134 [ 0.000000] NUMA: No NUMA configuration found
10326 23:57:59.694440 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10327 23:57:59.698031 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10328 23:57:59.701911 [ 0.000000] Zone ranges:
10329 23:57:59.707971 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10330 23:57:59.710928 [ 0.000000] DMA32 empty
10331 23:57:59.717941 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10332 23:57:59.721371 [ 0.000000] Movable zone start for each node
10333 23:57:59.724496 [ 0.000000] Early memory node ranges
10334 23:57:59.731234 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10335 23:57:59.737812 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10336 23:57:59.744312 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10337 23:57:59.751214 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10338 23:57:59.757966 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10339 23:57:59.764512 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10340 23:57:59.819995 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10341 23:57:59.827237 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10342 23:57:59.833584 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10343 23:57:59.836429 [ 0.000000] psci: probing for conduit method from DT.
10344 23:57:59.843659 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10345 23:57:59.846399 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10346 23:57:59.852921 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10347 23:57:59.856874 [ 0.000000] psci: SMC Calling Convention v1.2
10348 23:57:59.863251 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10349 23:57:59.866334 [ 0.000000] Detected VIPT I-cache on CPU0
10350 23:57:59.873147 [ 0.000000] CPU features: detected: GIC system register CPU interface
10351 23:57:59.879789 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10352 23:57:59.887178 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10353 23:57:59.893475 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10354 23:57:59.903058 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10355 23:57:59.909718 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10356 23:57:59.912975 [ 0.000000] alternatives: applying boot alternatives
10357 23:57:59.919155 [ 0.000000] Fallback order for Node 0: 0
10358 23:57:59.926227 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10359 23:57:59.929700 [ 0.000000] Policy zone: Normal
10360 23:57:59.952778 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10361 23:57:59.962685 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10362 23:57:59.973498 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10363 23:57:59.984123 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10364 23:57:59.990173 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10365 23:57:59.993623 <6>[ 0.000000] software IO TLB: area num 8.
10366 23:58:00.049922 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10367 23:58:00.199339 <6>[ 0.000000] Memory: 7945908K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406860K reserved, 32768K cma-reserved)
10368 23:58:00.205312 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10369 23:58:00.212165 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10370 23:58:00.216211 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10371 23:58:00.221763 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10372 23:58:00.228997 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10373 23:58:00.232332 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10374 23:58:00.241728 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10375 23:58:00.248522 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10376 23:58:00.254938 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10377 23:58:00.261385 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10378 23:58:00.265601 <6>[ 0.000000] GICv3: 608 SPIs implemented
10379 23:58:00.268479 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10380 23:58:00.275565 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10381 23:58:00.278260 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10382 23:58:00.285484 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10383 23:58:00.298403 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10384 23:58:00.311618 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10385 23:58:00.317997 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10386 23:58:00.325911 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10387 23:58:00.338994 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10388 23:58:00.345622 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10389 23:58:00.352643 <6>[ 0.009177] Console: colour dummy device 80x25
10390 23:58:00.362153 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10391 23:58:00.369025 <6>[ 0.024375] pid_max: default: 32768 minimum: 301
10392 23:58:00.371657 <6>[ 0.029246] LSM: Security Framework initializing
10393 23:58:00.378322 <6>[ 0.034184] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10394 23:58:00.388877 <6>[ 0.042047] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 23:58:00.398538 <6>[ 0.051458] cblist_init_generic: Setting adjustable number of callback queues.
10396 23:58:00.401752 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10397 23:58:00.411756 <6>[ 0.065291] cblist_init_generic: Setting adjustable number of callback queues.
10398 23:58:00.418033 <6>[ 0.072718] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 23:58:00.421557 <6>[ 0.079156] rcu: Hierarchical SRCU implementation.
10400 23:58:00.429093 <6>[ 0.084172] rcu: Max phase no-delay instances is 1000.
10401 23:58:00.434578 <6>[ 0.091206] EFI services will not be available.
10402 23:58:00.438198 <6>[ 0.096164] smp: Bringing up secondary CPUs ...
10403 23:58:00.446504 <6>[ 0.101212] Detected VIPT I-cache on CPU1
10404 23:58:00.453023 <6>[ 0.101283] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10405 23:58:00.459953 <6>[ 0.101313] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10406 23:58:00.463842 <6>[ 0.101651] Detected VIPT I-cache on CPU2
10407 23:58:00.469457 <6>[ 0.101704] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10408 23:58:00.479647 <6>[ 0.101722] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10409 23:58:00.483186 <6>[ 0.101979] Detected VIPT I-cache on CPU3
10410 23:58:00.489606 <6>[ 0.102027] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10411 23:58:00.496517 <6>[ 0.102041] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10412 23:58:00.499715 <6>[ 0.102346] CPU features: detected: Spectre-v4
10413 23:58:00.506585 <6>[ 0.102352] CPU features: detected: Spectre-BHB
10414 23:58:00.509567 <6>[ 0.102357] Detected PIPT I-cache on CPU4
10415 23:58:00.515916 <6>[ 0.102415] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10416 23:58:00.522315 <6>[ 0.102431] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10417 23:58:00.529241 <6>[ 0.102723] Detected PIPT I-cache on CPU5
10418 23:58:00.535605 <6>[ 0.102785] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10419 23:58:00.542511 <6>[ 0.102801] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10420 23:58:00.545593 <6>[ 0.103079] Detected PIPT I-cache on CPU6
10421 23:58:00.552214 <6>[ 0.103143] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10422 23:58:00.558904 <6>[ 0.103159] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10423 23:58:00.565676 <6>[ 0.103460] Detected PIPT I-cache on CPU7
10424 23:58:00.571999 <6>[ 0.103525] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10425 23:58:00.579125 <6>[ 0.103541] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10426 23:58:00.582853 <6>[ 0.103586] smp: Brought up 1 node, 8 CPUs
10427 23:58:00.588729 <6>[ 0.244988] SMP: Total of 8 processors activated.
10428 23:58:00.592393 <6>[ 0.249939] CPU features: detected: 32-bit EL0 Support
10429 23:58:00.601650 <6>[ 0.255334] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10430 23:58:00.608941 <6>[ 0.264135] CPU features: detected: Common not Private translations
10431 23:58:00.615346 <6>[ 0.270611] CPU features: detected: CRC32 instructions
10432 23:58:00.618591 <6>[ 0.275963] CPU features: detected: RCpc load-acquire (LDAPR)
10433 23:58:00.625338 <6>[ 0.281960] CPU features: detected: LSE atomic instructions
10434 23:58:00.631960 <6>[ 0.287741] CPU features: detected: Privileged Access Never
10435 23:58:00.638595 <6>[ 0.293521] CPU features: detected: RAS Extension Support
10436 23:58:00.645758 <6>[ 0.299130] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10437 23:58:00.647987 <6>[ 0.306352] CPU: All CPU(s) started at EL2
10438 23:58:00.655027 <6>[ 0.310695] alternatives: applying system-wide alternatives
10439 23:58:00.664102 <6>[ 0.321536] devtmpfs: initialized
10440 23:58:00.677020 <6>[ 0.330395] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10441 23:58:00.686846 <6>[ 0.340356] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10442 23:58:00.693730 <6>[ 0.348365] pinctrl core: initialized pinctrl subsystem
10443 23:58:00.696581 <6>[ 0.355011] DMI not present or invalid.
10444 23:58:00.702873 <6>[ 0.359418] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10445 23:58:00.712993 <6>[ 0.366285] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10446 23:58:00.719934 <6>[ 0.373869] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10447 23:58:00.729506 <6>[ 0.382087] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10448 23:58:00.733342 <6>[ 0.390328] audit: initializing netlink subsys (disabled)
10449 23:58:00.743413 <5>[ 0.396020] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10450 23:58:00.750338 <6>[ 0.396724] thermal_sys: Registered thermal governor 'step_wise'
10451 23:58:00.755916 <6>[ 0.403985] thermal_sys: Registered thermal governor 'power_allocator'
10452 23:58:00.759882 <6>[ 0.410240] cpuidle: using governor menu
10453 23:58:00.765784 <6>[ 0.421203] NET: Registered PF_QIPCRTR protocol family
10454 23:58:00.772683 <6>[ 0.426693] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10455 23:58:00.776070 <6>[ 0.433798] ASID allocator initialised with 32768 entries
10456 23:58:00.783112 <6>[ 0.440336] Serial: AMBA PL011 UART driver
10457 23:58:00.792918 <4>[ 0.449086] Trying to register duplicate clock ID: 134
10458 23:58:00.850224 <6>[ 0.510481] KASLR enabled
10459 23:58:00.864192 <6>[ 0.518296] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10460 23:58:00.870787 <6>[ 0.525311] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10461 23:58:00.877970 <6>[ 0.531800] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10462 23:58:00.884287 <6>[ 0.538806] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10463 23:58:00.891261 <6>[ 0.545292] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10464 23:58:00.897626 <6>[ 0.552296] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10465 23:58:00.904234 <6>[ 0.558784] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10466 23:58:00.910980 <6>[ 0.565788] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10467 23:58:00.914321 <6>[ 0.573322] ACPI: Interpreter disabled.
10468 23:58:00.922307 <6>[ 0.579748] iommu: Default domain type: Translated
10469 23:58:00.929547 <6>[ 0.584859] iommu: DMA domain TLB invalidation policy: strict mode
10470 23:58:00.932199 <5>[ 0.591521] SCSI subsystem initialized
10471 23:58:00.939220 <6>[ 0.595688] usbcore: registered new interface driver usbfs
10472 23:58:00.945553 <6>[ 0.601419] usbcore: registered new interface driver hub
10473 23:58:00.948840 <6>[ 0.606970] usbcore: registered new device driver usb
10474 23:58:00.955985 <6>[ 0.613062] pps_core: LinuxPPS API ver. 1 registered
10475 23:58:00.965955 <6>[ 0.618254] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10476 23:58:00.969285 <6>[ 0.627600] PTP clock support registered
10477 23:58:00.972454 <6>[ 0.631842] EDAC MC: Ver: 3.0.0
10478 23:58:00.979869 <6>[ 0.636987] FPGA manager framework
10479 23:58:00.987048 <6>[ 0.640667] Advanced Linux Sound Architecture Driver Initialized.
10480 23:58:00.990165 <6>[ 0.647439] vgaarb: loaded
10481 23:58:00.996115 <6>[ 0.650624] clocksource: Switched to clocksource arch_sys_counter
10482 23:58:00.999635 <5>[ 0.657073] VFS: Disk quotas dquot_6.6.0
10483 23:58:01.005997 <6>[ 0.661255] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10484 23:58:01.009418 <6>[ 0.668448] pnp: PnP ACPI: disabled
10485 23:58:01.017859 <6>[ 0.675069] NET: Registered PF_INET protocol family
10486 23:58:01.027656 <6>[ 0.680665] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10487 23:58:01.039147 <6>[ 0.692980] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10488 23:58:01.049178 <6>[ 0.701794] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10489 23:58:01.055631 <6>[ 0.709765] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10490 23:58:01.065594 <6>[ 0.718465] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10491 23:58:01.071825 <6>[ 0.728227] TCP: Hash tables configured (established 65536 bind 65536)
10492 23:58:01.078307 <6>[ 0.735091] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 23:58:01.088578 <6>[ 0.742288] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 23:58:01.094993 <6>[ 0.749987] NET: Registered PF_UNIX/PF_LOCAL protocol family
10495 23:58:01.101409 <6>[ 0.756146] RPC: Registered named UNIX socket transport module.
10496 23:58:01.105149 <6>[ 0.762298] RPC: Registered udp transport module.
10497 23:58:01.111073 <6>[ 0.767232] RPC: Registered tcp transport module.
10498 23:58:01.118358 <6>[ 0.772167] RPC: Registered tcp NFSv4.1 backchannel transport module.
10499 23:58:01.121233 <6>[ 0.778834] PCI: CLS 0 bytes, default 64
10500 23:58:01.124713 <6>[ 0.783172] Unpacking initramfs...
10501 23:58:01.148558 <6>[ 0.802739] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10502 23:58:01.158486 <6>[ 0.811381] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10503 23:58:01.162783 <6>[ 0.820224] kvm [1]: IPA Size Limit: 40 bits
10504 23:58:01.169152 <6>[ 0.824753] kvm [1]: GICv3: no GICV resource entry
10505 23:58:01.171762 <6>[ 0.829773] kvm [1]: disabling GICv2 emulation
10506 23:58:01.178228 <6>[ 0.834463] kvm [1]: GIC system register CPU interface enabled
10507 23:58:01.181609 <6>[ 0.840619] kvm [1]: vgic interrupt IRQ18
10508 23:58:01.188722 <6>[ 0.844980] kvm [1]: VHE mode initialized successfully
10509 23:58:01.194763 <5>[ 0.851481] Initialise system trusted keyrings
10510 23:58:01.201324 <6>[ 0.856308] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10511 23:58:01.209111 <6>[ 0.866334] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10512 23:58:01.215947 <5>[ 0.872717] NFS: Registering the id_resolver key type
10513 23:58:01.218757 <5>[ 0.878018] Key type id_resolver registered
10514 23:58:01.225810 <5>[ 0.882433] Key type id_legacy registered
10515 23:58:01.232006 <6>[ 0.886713] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10516 23:58:01.238958 <6>[ 0.893631] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10517 23:58:01.245194 <6>[ 0.901331] 9p: Installing v9fs 9p2000 file system support
10518 23:58:01.282106 <5>[ 0.939235] Key type asymmetric registered
10519 23:58:01.285217 <5>[ 0.943565] Asymmetric key parser 'x509' registered
10520 23:58:01.295403 <6>[ 0.948697] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10521 23:58:01.299063 <6>[ 0.956309] io scheduler mq-deadline registered
10522 23:58:01.301848 <6>[ 0.961084] io scheduler kyber registered
10523 23:58:01.320728 <6>[ 0.977847] EINJ: ACPI disabled.
10524 23:58:01.352857 <4>[ 1.003838] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 23:58:01.363280 <4>[ 1.014454] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 23:58:01.378042 <6>[ 1.035032] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10527 23:58:01.386123 <6>[ 1.042959] printk: console [ttyS0] disabled
10528 23:58:01.413630 <6>[ 1.067583] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10529 23:58:01.420457 <6>[ 1.077054] printk: console [ttyS0] enabled
10530 23:58:01.423724 <6>[ 1.077054] printk: console [ttyS0] enabled
10531 23:58:01.430076 <6>[ 1.085949] printk: bootconsole [mtk8250] disabled
10532 23:58:01.433200 <6>[ 1.085949] printk: bootconsole [mtk8250] disabled
10533 23:58:01.440258 <6>[ 1.096968] SuperH (H)SCI(F) driver initialized
10534 23:58:01.442978 <6>[ 1.102236] msm_serial: driver initialized
10535 23:58:01.457343 <6>[ 1.111121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10536 23:58:01.467321 <6>[ 1.119667] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10537 23:58:01.473656 <6>[ 1.128211] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10538 23:58:01.484250 <6>[ 1.136837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10539 23:58:01.493824 <6>[ 1.145543] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10540 23:58:01.500434 <6>[ 1.154263] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10541 23:58:01.510155 <6>[ 1.162803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10542 23:58:01.516894 <6>[ 1.171598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10543 23:58:01.526118 <6>[ 1.180141] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10544 23:58:01.538712 <6>[ 1.195601] loop: module loaded
10545 23:58:01.544875 <6>[ 1.201456] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10546 23:58:01.567774 <4>[ 1.224617] mtk-pmic-keys: Failed to locate of_node [id: -1]
10547 23:58:01.574277 <6>[ 1.231449] megasas: 07.719.03.00-rc1
10548 23:58:01.584198 <6>[ 1.240979] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10549 23:58:01.596563 <6>[ 1.254002] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10550 23:58:01.613801 <6>[ 1.270580] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10551 23:58:01.669254 <6>[ 1.319920] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10552 23:58:01.914844 <6>[ 1.572070] Freeing initrd memory: 18276K
10553 23:58:01.926365 <6>[ 1.583746] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10554 23:58:01.937735 <6>[ 1.594641] tun: Universal TUN/TAP device driver, 1.6
10555 23:58:01.940690 <6>[ 1.600691] thunder_xcv, ver 1.0
10556 23:58:01.944367 <6>[ 1.604196] thunder_bgx, ver 1.0
10557 23:58:01.947851 <6>[ 1.607692] nicpf, ver 1.0
10558 23:58:01.957919 <6>[ 1.611694] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10559 23:58:01.961041 <6>[ 1.619170] hns3: Copyright (c) 2017 Huawei Corporation.
10560 23:58:01.967462 <6>[ 1.624759] hclge is initializing
10561 23:58:01.971250 <6>[ 1.628339] e1000: Intel(R) PRO/1000 Network Driver
10562 23:58:01.977667 <6>[ 1.633468] e1000: Copyright (c) 1999-2006 Intel Corporation.
10563 23:58:01.980917 <6>[ 1.639479] e1000e: Intel(R) PRO/1000 Network Driver
10564 23:58:01.987834 <6>[ 1.644694] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10565 23:58:01.994078 <6>[ 1.650879] igb: Intel(R) Gigabit Ethernet Network Driver
10566 23:58:02.001182 <6>[ 1.656529] igb: Copyright (c) 2007-2014 Intel Corporation.
10567 23:58:02.007516 <6>[ 1.662365] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10568 23:58:02.013842 <6>[ 1.668883] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10569 23:58:02.017623 <6>[ 1.675343] sky2: driver version 1.30
10570 23:58:02.023849 <6>[ 1.680261] usbcore: registered new device driver r8152-cfgselector
10571 23:58:02.031402 <6>[ 1.686796] usbcore: registered new interface driver r8152
10572 23:58:02.038015 <6>[ 1.692603] VFIO - User Level meta-driver version: 0.3
10573 23:58:02.044183 <6>[ 1.700826] usbcore: registered new interface driver usb-storage
10574 23:58:02.050387 <6>[ 1.707269] usbcore: registered new device driver onboard-usb-hub
10575 23:58:02.059253 <6>[ 1.716380] mt6397-rtc mt6359-rtc: registered as rtc0
10576 23:58:02.069036 <6>[ 1.721840] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:58:02 UTC (1717027082)
10577 23:58:02.073408 <6>[ 1.731403] i2c_dev: i2c /dev entries driver
10578 23:58:02.089547 <6>[ 1.743136] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10579 23:58:02.096231 <4>[ 1.751861] cpu cpu0: supply cpu not found, using dummy regulator
10580 23:58:02.102019 <4>[ 1.758285] cpu cpu1: supply cpu not found, using dummy regulator
10581 23:58:02.109247 <4>[ 1.764686] cpu cpu2: supply cpu not found, using dummy regulator
10582 23:58:02.115284 <4>[ 1.771110] cpu cpu3: supply cpu not found, using dummy regulator
10583 23:58:02.122001 <4>[ 1.777507] cpu cpu4: supply cpu not found, using dummy regulator
10584 23:58:02.129018 <4>[ 1.783907] cpu cpu5: supply cpu not found, using dummy regulator
10585 23:58:02.135083 <4>[ 1.790303] cpu cpu6: supply cpu not found, using dummy regulator
10586 23:58:02.141871 <4>[ 1.796694] cpu cpu7: supply cpu not found, using dummy regulator
10587 23:58:02.160298 <6>[ 1.817355] cpu cpu0: EM: created perf domain
10588 23:58:02.163313 <6>[ 1.822292] cpu cpu4: EM: created perf domain
10589 23:58:02.170503 <6>[ 1.827873] sdhci: Secure Digital Host Controller Interface driver
10590 23:58:02.176963 <6>[ 1.834306] sdhci: Copyright(c) Pierre Ossman
10591 23:58:02.183923 <6>[ 1.839259] Synopsys Designware Multimedia Card Interface Driver
10592 23:58:02.187888 <6>[ 1.845874] mmc0: CQHCI version 5.10
10593 23:58:02.193645 <6>[ 1.845887] sdhci-pltfm: SDHCI platform and OF driver helper
10594 23:58:02.200767 <6>[ 1.856662] ledtrig-cpu: registered to indicate activity on CPUs
10595 23:58:02.206962 <6>[ 1.863825] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10596 23:58:02.213374 <6>[ 1.870884] usbcore: registered new interface driver usbhid
10597 23:58:02.217353 <6>[ 1.876705] usbhid: USB HID core driver
10598 23:58:02.227277 <6>[ 1.880870] spi_master spi0: will run message pump with realtime priority
10599 23:58:02.272496 <6>[ 1.923412] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10600 23:58:02.292034 <6>[ 1.938649] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10601 23:58:02.294908 <6>[ 1.952241] mmc0: Command Queue Engine enabled
10602 23:58:02.302176 <6>[ 1.953800] cros-ec-spi spi0.0: Chrome EC device registered
10603 23:58:02.305555 <6>[ 1.956982] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10604 23:58:02.312988 <6>[ 1.970290] mmcblk0: mmc0:0001 DA4128 116 GiB
10605 23:58:02.322661 <6>[ 1.974740] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10606 23:58:02.329575 <6>[ 1.982751] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10607 23:58:02.333195 <6>[ 1.985374] NET: Registered PF_PACKET protocol family
10608 23:58:02.339407 <6>[ 1.991482] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10609 23:58:02.342895 <6>[ 1.995588] 9pnet: Installing 9P2000 support
10610 23:58:02.349982 <6>[ 2.001378] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10611 23:58:02.353386 <5>[ 2.005280] Key type dns_resolver registered
10612 23:58:02.359101 <6>[ 2.011234] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10613 23:58:02.362784 <6>[ 2.015322] registered taskstats version 1
10614 23:58:02.369353 <5>[ 2.025912] Loading compiled-in X.509 certificates
10615 23:58:02.396542 <4>[ 2.047134] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10616 23:58:02.406361 <4>[ 2.057855] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10617 23:58:02.420498 <6>[ 2.077842] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10618 23:58:02.427052 <6>[ 2.084657] xhci-mtk 11200000.usb: xHCI Host Controller
10619 23:58:02.437084 <6>[ 2.090163] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10620 23:58:02.443757 <6>[ 2.098012] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10621 23:58:02.449986 <6>[ 2.107441] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10622 23:58:02.456587 <6>[ 2.113632] xhci-mtk 11200000.usb: xHCI Host Controller
10623 23:58:02.463295 <6>[ 2.119136] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10624 23:58:02.473206 <6>[ 2.126805] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10625 23:58:02.476569 <6>[ 2.134731] hub 1-0:1.0: USB hub found
10626 23:58:02.480236 <6>[ 2.138759] hub 1-0:1.0: 1 port detected
10627 23:58:02.490521 <6>[ 2.143062] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10628 23:58:02.493133 <6>[ 2.151854] hub 2-0:1.0: USB hub found
10629 23:58:02.496595 <6>[ 2.155878] hub 2-0:1.0: 1 port detected
10630 23:58:02.506325 <6>[ 2.163714] mtk-msdc 11f70000.mmc: Got CD GPIO
10631 23:58:02.524089 <6>[ 2.178061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10632 23:58:02.530769 <6>[ 2.186087] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10633 23:58:02.540601 <4>[ 2.194042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10634 23:58:02.550613 <6>[ 2.203602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10635 23:58:02.556758 <6>[ 2.211682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10636 23:58:02.563406 <6>[ 2.219700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10637 23:58:02.573722 <6>[ 2.227616] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10638 23:58:02.581188 <6>[ 2.235437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10639 23:58:02.590981 <6>[ 2.243254] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10640 23:58:02.600149 <6>[ 2.253656] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10641 23:58:02.607312 <6>[ 2.262013] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10642 23:58:02.616818 <6>[ 2.270363] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10643 23:58:02.623168 <6>[ 2.278702] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10644 23:58:02.633519 <6>[ 2.287040] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10645 23:58:02.639906 <6>[ 2.295378] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10646 23:58:02.649795 <6>[ 2.303716] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10647 23:58:02.656391 <6>[ 2.312054] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10648 23:58:02.666304 <6>[ 2.320392] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10649 23:58:02.676380 <6>[ 2.328730] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10650 23:58:02.683139 <6>[ 2.337068] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10651 23:58:02.693402 <6>[ 2.345409] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10652 23:58:02.699934 <6>[ 2.353746] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10653 23:58:02.709227 <6>[ 2.362084] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10654 23:58:02.715938 <6>[ 2.370422] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10655 23:58:02.722474 <6>[ 2.379160] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10656 23:58:02.728901 <6>[ 2.386323] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10657 23:58:02.735372 <6>[ 2.393096] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10658 23:58:02.745816 <6>[ 2.399864] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10659 23:58:02.752251 <6>[ 2.406803] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10660 23:58:02.759178 <6>[ 2.413674] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10661 23:58:02.768893 <6>[ 2.422803] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10662 23:58:02.778866 <6>[ 2.431922] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10663 23:58:02.788966 <6>[ 2.441216] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10664 23:58:02.798985 <6>[ 2.450686] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10665 23:58:02.809182 <6>[ 2.460153] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10666 23:58:02.815282 <6>[ 2.469273] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10667 23:58:02.824954 <6>[ 2.478744] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10668 23:58:02.835178 <6>[ 2.487863] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10669 23:58:02.844936 <6>[ 2.497158] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10670 23:58:02.854252 <6>[ 2.507319] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10671 23:58:02.864623 <6>[ 2.518858] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10672 23:58:02.871216 <6>[ 2.528518] Trying to probe devices needed for running init ...
10673 23:58:02.912883 <6>[ 2.566892] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10674 23:58:03.067808 <6>[ 2.724788] hub 1-1:1.0: USB hub found
10675 23:58:03.070842 <6>[ 2.729314] hub 1-1:1.0: 4 ports detected
10676 23:58:03.080307 <6>[ 2.737889] hub 1-1:1.0: USB hub found
10677 23:58:03.083723 <6>[ 2.742239] hub 1-1:1.0: 4 ports detected
10678 23:58:03.193210 <6>[ 2.847184] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10679 23:58:03.219343 <6>[ 2.875836] hub 2-1:1.0: USB hub found
10680 23:58:03.221421 <6>[ 2.880276] hub 2-1:1.0: 3 ports detected
10681 23:58:03.230864 <6>[ 2.887783] hub 2-1:1.0: USB hub found
10682 23:58:03.233618 <6>[ 2.892234] hub 2-1:1.0: 3 ports detected
10683 23:58:03.408444 <6>[ 3.062944] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 23:58:03.542205 <6>[ 3.198804] hub 1-1.4:1.0: USB hub found
10685 23:58:03.544378 <6>[ 3.203467] hub 1-1.4:1.0: 2 ports detected
10686 23:58:03.553925 <6>[ 3.211149] hub 1-1.4:1.0: USB hub found
10687 23:58:03.556933 <6>[ 3.215745] hub 1-1.4:1.0: 2 ports detected
10688 23:58:03.621010 <6>[ 3.275068] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10689 23:58:03.729455 <6>[ 3.383568] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 23:58:03.765823 <4>[ 3.420010] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10691 23:58:03.776291 <4>[ 3.429125] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10692 23:58:03.811543 <6>[ 3.468515] r8152 2-1.3:1.0 eth0: v1.12.13
10693 23:58:03.852648 <6>[ 3.506942] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10694 23:58:04.044551 <6>[ 3.698878] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10695 23:58:05.439046 <6>[ 5.096638] r8152 2-1.3:1.0 eth0: carrier on
10696 23:58:08.429193 <5>[ 5.126713] Sending DHCP requests .., OK
10697 23:58:08.435398 <6>[ 8.091075] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10698 23:58:08.439129 <6>[ 8.099370] IP-Config: Complete:
10699 23:58:08.452711 <6>[ 8.102870] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10700 23:58:08.458334 <6>[ 8.113591] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10701 23:58:08.468319 <6>[ 8.122211] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10702 23:58:08.471373 <6>[ 8.122221] nameserver0=192.168.201.1
10703 23:58:08.474531 <6>[ 8.134379] clk: Disabling unused clocks
10704 23:58:08.478662 <6>[ 8.139881] ALSA device list:
10705 23:58:08.485134 <6>[ 8.143149] No soundcards found.
10706 23:58:08.492520 <6>[ 8.150395] Freeing unused kernel memory: 8512K
10707 23:58:08.495738 <6>[ 8.155362] Run /init as init process
10708 23:58:08.505705 Loading, please wait...
10709 23:58:08.533420 Starting systemd-udevd version 252.22-1~deb12u1
10710 23:58:08.786807 <6>[ 8.441560] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10711 23:58:08.793906 <6>[ 8.447439] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10712 23:58:08.803520 <6>[ 8.449389] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10713 23:58:08.810547 <6>[ 8.465594] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10714 23:58:08.816504 <6>[ 8.469557] remoteproc remoteproc0: scp is available
10715 23:58:08.823817 <6>[ 8.479888] remoteproc remoteproc0: powering up scp
10716 23:58:08.829661 <6>[ 8.485040] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10717 23:58:08.839966 <3>[ 8.485885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 23:58:08.843148 <6>[ 8.486251] mc: Linux media interface: v0.10
10719 23:58:08.849889 <6>[ 8.489443] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10720 23:58:08.856465 <6>[ 8.493666] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10721 23:58:08.863513 <3>[ 8.502448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:58:08.870335 <4>[ 8.505514] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10723 23:58:08.880560 <4>[ 8.506396] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10724 23:58:08.887139 <4>[ 8.513144] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10725 23:58:08.893818 <4>[ 8.513144] Fallback method does not support PEC.
10726 23:58:08.901090 <3>[ 8.513840] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 23:58:08.910209 <3>[ 8.513926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 23:58:08.917404 <3>[ 8.513931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 23:58:08.924070 <3>[ 8.513934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 23:58:08.933707 <3>[ 8.513939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 23:58:08.940114 <3>[ 8.513942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 23:58:08.950380 <3>[ 8.513973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 23:58:08.954194 <6>[ 8.529219] videodev: Linux video capture interface: v2.00
10734 23:58:08.963766 <3>[ 8.535066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 23:58:08.973869 <3>[ 8.543308] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10736 23:58:08.980621 <3>[ 8.555977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 23:58:08.987248 <3>[ 8.555990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 23:58:08.997140 <3>[ 8.556063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 23:58:09.007464 <3>[ 8.584804] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 23:58:09.013366 <3>[ 8.588336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 23:58:09.019748 <3>[ 8.588340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 23:58:09.030145 <3>[ 8.588344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 23:58:09.036847 <6>[ 8.604061] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10744 23:58:09.043024 <3>[ 8.604496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 23:58:09.053012 <6>[ 8.607418] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10746 23:58:09.063354 <6>[ 8.607799] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10747 23:58:09.069983 <6>[ 8.612582] pci_bus 0000:00: root bus resource [bus 00-ff]
10748 23:58:09.076159 <3>[ 8.618331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 23:58:09.085881 <6>[ 8.626391] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10750 23:58:09.096575 <6>[ 8.626395] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10751 23:58:09.098944 <6>[ 8.626423] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10752 23:58:09.109123 <6>[ 8.631219] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10753 23:58:09.115434 <6>[ 8.632000] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10754 23:58:09.125671 <6>[ 8.659447] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10755 23:58:09.128603 <6>[ 8.660022] Bluetooth: Core ver 2.22
10756 23:58:09.135438 <6>[ 8.660075] NET: Registered PF_BLUETOOTH protocol family
10757 23:58:09.142361 <6>[ 8.660078] Bluetooth: HCI device and connection manager initialized
10758 23:58:09.145138 <6>[ 8.660095] Bluetooth: HCI socket layer initialized
10759 23:58:09.151579 <6>[ 8.660102] Bluetooth: L2CAP socket layer initialized
10760 23:58:09.158034 <6>[ 8.660111] Bluetooth: SCO socket layer initialized
10761 23:58:09.164437 <6>[ 8.668229] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10762 23:58:09.171085 <6>[ 8.668751] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10763 23:58:09.177897 <6>[ 8.668842] pci 0000:00:00.0: supports D1 D2
10764 23:58:09.185689 <6>[ 8.668847] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10765 23:58:09.191018 <6>[ 8.669772] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10766 23:58:09.197563 <6>[ 8.669851] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10767 23:58:09.204584 <6>[ 8.669876] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10768 23:58:09.214064 <6>[ 8.669892] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10769 23:58:09.220921 <6>[ 8.669907] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10770 23:58:09.223999 <6>[ 8.670012] pci 0000:01:00.0: supports D1 D2
10771 23:58:09.231097 <6>[ 8.670013] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10772 23:58:09.241178 <6>[ 8.682687] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10773 23:58:09.247255 <6>[ 8.684386] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10774 23:58:09.254087 <6>[ 8.684432] remoteproc remoteproc0: remote processor scp is now up
10775 23:58:09.260341 <6>[ 8.692477] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10776 23:58:09.270758 <6>[ 8.694013] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10777 23:58:09.280606 <6>[ 8.695425] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10778 23:58:09.287394 <6>[ 8.695696] usbcore: registered new interface driver uvcvideo
10779 23:58:09.293601 <6>[ 8.727402] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10780 23:58:09.300363 <6>[ 8.727455] usbcore: registered new interface driver btusb
10781 23:58:09.309738 <4>[ 8.728817] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10782 23:58:09.316557 <3>[ 8.728836] Bluetooth: hci0: Failed to load firmware file (-2)
10783 23:58:09.323548 <3>[ 8.728843] Bluetooth: hci0: Failed to set up firmware (-2)
10784 23:58:09.332940 <4>[ 8.728850] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10785 23:58:09.339631 <6>[ 8.732476] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10786 23:58:09.350176 <6>[ 9.003517] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10787 23:58:09.356216 <6>[ 9.011523] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10788 23:58:09.362482 <6>[ 9.019526] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10789 23:58:09.369288 <6>[ 9.027526] pci 0000:00:00.0: PCI bridge to [bus 01]
10790 23:58:09.375867 <6>[ 9.032742] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10791 23:58:09.382744 <6>[ 9.040869] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10792 23:58:09.389828 <6>[ 9.047698] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10793 23:58:09.396274 <6>[ 9.054043] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10794 23:58:09.417897 <5>[ 9.072635] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10795 23:58:09.442825 <5>[ 9.097535] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10796 23:58:09.449120 <5>[ 9.104959] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10797 23:58:09.459598 <4>[ 9.113414] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10798 23:58:09.465993 <6>[ 9.122324] cfg80211: failed to load regulatory.db
10799 23:58:09.508461 <6>[ 9.163061] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10800 23:58:09.515283 <6>[ 9.170576] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10801 23:58:09.539025 <6>[ 9.197287] mt7921e 0000:01:00.0: ASIC revision: 79610010
10802 23:58:09.645396 <6>[ 9.300024] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10803 23:58:09.648411 <6>[ 9.300024]
10804 23:58:09.661554 Begin: Loading essential drivers ... done.
10805 23:58:09.664678 Begin: Running /scripts/init-premount ... done.
10806 23:58:09.671850 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10807 23:58:09.681792 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10808 23:58:09.684490 Device /sys/class/net/eth0 found
10809 23:58:09.684912 done.
10810 23:58:09.691078 Begin: Waiting up to 180 secs for any network device to become available ... done.
10811 23:58:09.732307 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10812 23:58:09.741100 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10813 23:58:09.747575 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10814 23:58:09.753841 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10815 23:58:09.760354 host : mt8192-asurada-spherion-r0-cbg-2
10816 23:58:09.767227 domain : lava-rack
10817 23:58:09.770679 rootserver: 192.168.201.1 rootpath:
10818 23:58:09.773461 filename :
10819 23:58:09.915284 <6>[ 9.570518] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10820 23:58:09.933699 done.
10821 23:58:09.940149 Begin: Running /scripts/nfs-bottom ... done.
10822 23:58:09.955989 Begin: Running /scripts/init-bottom ... done.
10823 23:58:11.334048 <6>[ 10.992452] NET: Registered PF_INET6 protocol family
10824 23:58:11.340644 <6>[ 10.999268] Segment Routing with IPv6
10825 23:58:11.344194 <6>[ 11.003214] In-situ OAM (IOAM) with IPv6
10826 23:58:11.525857 <30>[ 11.157932] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10827 23:58:11.532481 <30>[ 11.191055] systemd[1]: Detected architecture arm64.
10828 23:58:11.543724
10829 23:58:11.547256 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10830 23:58:11.547795
10831 23:58:11.571042 <30>[ 11.229712] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10832 23:58:12.800682 <30>[ 12.455834] systemd[1]: Queued start job for default target graphical.target.
10833 23:58:12.844356 <30>[ 12.499515] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10834 23:58:12.850774 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10835 23:58:12.869171 <30>[ 12.524426] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10836 23:58:12.879612 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10837 23:58:12.897197 <30>[ 12.552418] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10838 23:58:12.906992 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10839 23:58:12.924855 <30>[ 12.580119] systemd[1]: Created slice user.slice - User and Session Slice.
10840 23:58:12.931158 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10841 23:58:12.951140 <30>[ 12.603139] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10842 23:58:12.957827 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10843 23:58:12.978922 <30>[ 12.631061] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10844 23:58:12.985672 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10845 23:58:13.013936 <30>[ 12.659488] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10846 23:58:13.024290 <30>[ 12.679369] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10847 23:58:13.030401 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10848 23:58:13.048334 <30>[ 12.703237] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10849 23:58:13.057902 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10850 23:58:13.072055 <30>[ 12.726943] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10851 23:58:13.081920 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10852 23:58:13.096883 <30>[ 12.755404] systemd[1]: Reached target paths.target - Path Units.
10853 23:58:13.106720 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10854 23:58:13.124648 <30>[ 12.779208] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10855 23:58:13.130391 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10856 23:58:13.144412 <30>[ 12.802842] systemd[1]: Reached target slices.target - Slice Units.
10857 23:58:13.155006 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10858 23:58:13.168357 <30>[ 12.826906] systemd[1]: Reached target swap.target - Swaps.
10859 23:58:13.174629 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10860 23:58:13.192563 <30>[ 12.846954] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10861 23:58:13.201853 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10862 23:58:13.221129 <30>[ 12.875660] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10863 23:58:13.230542 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10864 23:58:13.251236 <30>[ 12.905734] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10865 23:58:13.260301 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10866 23:58:13.277042 <30>[ 12.932392] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10867 23:58:13.287035 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10868 23:58:13.304882 <30>[ 12.959409] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10869 23:58:13.311218 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10870 23:58:13.329406 <30>[ 12.984478] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10871 23:58:13.338811 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10872 23:58:13.359381 <30>[ 13.014170] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10873 23:58:13.368939 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10874 23:58:13.384097 <30>[ 13.039275] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10875 23:58:13.394070 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10876 23:58:13.435374 <30>[ 13.090953] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10877 23:58:13.442605 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10878 23:58:13.464478 <30>[ 13.119538] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10879 23:58:13.470774 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10880 23:58:13.496465 <30>[ 13.151735] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10881 23:58:13.502976 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10882 23:58:13.531745 <30>[ 13.179485] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10883 23:58:13.572256 <30>[ 13.227543] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10884 23:58:13.581778 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10885 23:58:13.604924 <30>[ 13.260472] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10886 23:58:13.612018 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10887 23:58:13.652514 <30>[ 13.307638] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10888 23:58:13.662301 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10889 23:58:13.685696 <30>[ 13.340869] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10890 23:58:13.691773 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10891 23:58:13.702251 <6>[ 13.357886] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10892 23:58:13.717035 <30>[ 13.372108] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10893 23:58:13.726492 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10894 23:58:13.748624 <30>[ 13.404345] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10895 23:58:13.755864 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10896 23:58:13.795764 <6>[ 13.454106] fuse: init (API version 7.37)
10897 23:58:13.820195 <30>[ 13.475852] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10898 23:58:13.826763 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10899 23:58:13.857034 <30>[ 13.512395] systemd[1]: Starting systemd-journald.service - Journal Service...
10900 23:58:13.863285 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10901 23:58:13.889007 <30>[ 13.544421] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10902 23:58:13.895907 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10903 23:58:13.925436 <30>[ 13.576911] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10904 23:58:13.931073 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10905 23:58:13.957566 <30>[ 13.613059] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10906 23:58:13.968084 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10907 23:58:13.987852 <30>[ 13.643457] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10908 23:58:13.997670 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10909 23:58:14.020708 <30>[ 13.676150] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10910 23:58:14.027350 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10911 23:58:14.048934 <30>[ 13.703818] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10912 23:58:14.059016 [[0;32m OK [0m] Mounted [0;<3>[ 13.714400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 23:58:14.066298 1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10914 23:58:14.084278 <30>[ 13.739274] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10915 23:58:14.090973 <3>[ 13.744469] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 23:58:14.100756 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10917 23:58:14.120180 <30>[ 13.775910] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10918 23:58:14.131693 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10919 23:58:14.138679 <3>[ 13.793921] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 23:58:14.153243 <30>[ 13.808208] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10921 23:58:14.160068 <30>[ 13.816392] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10922 23:58:14.176700 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 13.829416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 23:58:14.180534 Load Kernel Module configfs.
10924 23:58:14.197670 <30>[ 13.851931] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10925 23:58:14.203831 <30>[ 13.860007] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10926 23:58:14.213740 <3>[ 13.864642] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 23:58:14.220203 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10928 23:58:14.238773 <30>[ 13.896585] systemd[1]: modprobe@drm.service: Deactivated successfully.
10929 23:58:14.248177 <3>[ 13.899950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 23:58:14.254763 <30>[ 13.904690] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10931 23:58:14.265331 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10932 23:58:14.281008 <3>[ 13.935761] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 23:58:14.292249 <30>[ 13.946744] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10934 23:58:14.302049 <30>[ 13.955357] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10935 23:58:14.315087 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 13.968398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 23:58:14.318172 fi_psto…m - Load Kernel Module efi_pstore.
10937 23:58:14.335413 <30>[ 13.993428] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10938 23:58:14.346304 <30>[ 14.001484] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10939 23:58:14.356242 <3>[ 14.002608] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 23:58:14.362383 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10941 23:58:14.386016 <3>[ 14.041317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 23:58:14.392847 <30>[ 14.041510] systemd[1]: modprobe@loop.service: Deactivated successfully.
10943 23:58:14.403382 <30>[ 14.058387] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10944 23:58:14.409875 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10945 23:58:14.433829 <30>[ 14.089090] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10946 23:58:14.440910 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10947 23:58:14.463089 <4>[ 14.111459] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10948 23:58:14.469329 <3>[ 14.127122] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10949 23:58:14.482498 <30>[ 14.127923] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10950 23:58:14.489062 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10951 23:58:14.509541 <30>[ 14.164953] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10952 23:58:14.519593 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10953 23:58:14.536553 <30>[ 14.191550] systemd[1]: Started systemd-journald.service - Journal Service.
10954 23:58:14.542605 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10955 23:58:14.568313 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10956 23:58:14.590161 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10957 23:58:14.636784 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10958 23:58:14.655772 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10959 23:58:14.682168 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10960 23:58:14.707509 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10961 23:58:14.733348 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10962 23:58:14.765684 Starting [0;1;39msystemd-sysusers.…rvice[0m - Creat<46>[ 14.419591] systemd-journald[303]: Received client request to flush runtime journal.
10963 23:58:14.766144 e System Users...
10964 23:58:14.823653 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10965 23:58:14.840244 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10966 23:58:14.861638 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10967 23:58:14.881549 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10968 23:58:15.880982 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10969 23:58:15.933211 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10970 23:58:16.186923 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10971 23:58:16.318908 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10972 23:58:16.340295 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10973 23:58:16.363732 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10974 23:58:16.428313 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10975 23:58:16.453714 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10976 23:58:16.696845 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10977 23:58:16.765363 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10978 23:58:16.809584 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10979 23:58:17.128631 <6>[ 16.787435] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10980 23:58:17.174264 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10981 23:58:17.227678 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10982 23:58:17.318758 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10983 23:58:17.336097 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10984 23:58:17.363655 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10985 23:58:17.380430 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10986 23:58:17.399656 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10987 23:58:17.431690 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10988 23:58:17.492152 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10989 23:58:17.527705 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10990 23:58:17.547794 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10991 23:58:17.568684 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10992 23:58:17.611568 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10993 23:58:17.706361 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10994 23:58:17.724183 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10995 23:58:17.740433 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10996 23:58:17.755440 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10997 23:58:17.784942 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10998 23:58:17.811361 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10999 23:58:17.831346 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11000 23:58:17.855784 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11001 23:58:17.879962 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11002 23:58:17.895408 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11003 23:58:17.913797 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11004 23:58:17.931279 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11005 23:58:17.947622 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11006 23:58:18.000781 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11007 23:58:18.080370 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11008 23:58:18.164546 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11009 23:58:18.190264 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11010 23:58:18.357965 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11011 23:58:18.412225 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11012 23:58:18.438171 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11013 23:58:18.459865 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11014 23:58:18.485536 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11015 23:58:18.511210 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11016 23:58:18.540339 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11017 23:58:18.561936 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11018 23:58:18.579687 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11019 23:58:18.633282 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11020 23:58:18.684137 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11021 23:58:18.793982
11022 23:58:18.796446 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11023 23:58:18.796935
11024 23:58:18.799797 debian-bookworm-arm64 login: root (automatic login)
11025 23:58:18.800215
11026 23:58:19.148130 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11027 23:58:19.148637
11028 23:58:19.154497 The programs included with the Debian GNU/Linux system are free software;
11029 23:58:19.161594 the exact distribution terms for each program are described in the
11030 23:58:19.164284 individual files in /usr/share/doc/*/copyright.
11031 23:58:19.164699
11032 23:58:19.171461 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11033 23:58:19.174553 permitted by applicable law.
11034 23:58:20.401824 Matched prompt #10: / #
11036 23:58:20.402977 Setting prompt string to ['/ #']
11037 23:58:20.403406 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11039 23:58:20.404408 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11040 23:58:20.404841 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11041 23:58:20.405175 Setting prompt string to ['/ #']
11042 23:58:20.405552 Forcing a shell prompt, looking for ['/ #']
11044 23:58:20.456369 / #
11045 23:58:20.456999 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11046 23:58:20.457466 Waiting using forced prompt support (timeout 00:02:30)
11047 23:58:20.463141
11048 23:58:20.464088 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11049 23:58:20.464603 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11051 23:58:20.565853 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n'
11052 23:58:20.572015 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084381/extract-nfsrootfs-p3qf5f0n'
11054 23:58:20.673550 / # export NFS_SERVER_IP='192.168.201.1'
11055 23:58:20.679888 export NFS_SERVER_IP='192.168.201.1'
11056 23:58:20.680720 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11057 23:58:20.681319 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11058 23:58:20.682059 end: 2 depthcharge-action (duration 00:01:47) [common]
11059 23:58:20.682602 start: 3 lava-test-retry (timeout 00:07:35) [common]
11060 23:58:20.683097 start: 3.1 lava-test-shell (timeout 00:07:35) [common]
11061 23:58:20.683512 Using namespace: common
11063 23:58:20.784645 / # #
11064 23:58:20.785318 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11065 23:58:20.791381 #
11066 23:58:20.792150 Using /lava-14084381
11068 23:58:20.893360 / # export SHELL=/bin/bash
11069 23:58:20.899613 export SHELL=/bin/bash
11071 23:58:21.001211 / # . /lava-14084381/environment
11072 23:58:21.008729 . /lava-14084381/environment
11074 23:58:21.117551 / # /lava-14084381/bin/lava-test-runner /lava-14084381/0
11075 23:58:21.118172 Test shell timeout: 10s (minimum of the action and connection timeout)
11076 23:58:21.124317 /lava-14084381/bin/lava-test-runner /lava-14084381/0
11077 23:58:21.460941 + export TESTRUN_ID=0_timesync-off
11078 23:58:21.464443 + TESTRUN_ID=0_timesync-off
11079 23:58:21.467893 + cd /lava-14084381/0/tests/0_timesync-off
11080 23:58:21.471069 ++ cat uuid
11081 23:58:21.478943 + UUID=14084381_1.6.2.3.1
11082 23:58:21.479361 + set +x
11083 23:58:21.485481 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14084381_1.6.2.3.1>
11084 23:58:21.486171 Received signal: <STARTRUN> 0_timesync-off 14084381_1.6.2.3.1
11085 23:58:21.486543 Starting test lava.0_timesync-off (14084381_1.6.2.3.1)
11086 23:58:21.486952 Skipping test definition patterns.
11087 23:58:21.488413 + systemctl stop systemd-timesyncd
11088 23:58:21.556781 + set +x
11089 23:58:21.560624 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14084381_1.6.2.3.1>
11090 23:58:21.561349 Received signal: <ENDRUN> 0_timesync-off 14084381_1.6.2.3.1
11091 23:58:21.561762 Ending use of test pattern.
11092 23:58:21.562075 Ending test lava.0_timesync-off (14084381_1.6.2.3.1), duration 0.08
11094 23:58:21.668147 + export TESTRUN_ID=1_kselftest-arm64
11095 23:58:21.668772 + TESTRUN_ID=1_kselftest-arm64
11096 23:58:21.674690 + cd /lava-14084381/0/tests/1_kselftest-arm64
11097 23:58:21.675120 ++ cat uuid
11098 23:58:21.685571 + UUID=14084381_1.6.2.3.5
11099 23:58:21.685994 + set +x
11100 23:58:21.691458 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14084381_1.6.2.3.5>
11101 23:58:21.692369 Received signal: <STARTRUN> 1_kselftest-arm64 14084381_1.6.2.3.5
11102 23:58:21.692729 Starting test lava.1_kselftest-arm64 (14084381_1.6.2.3.5)
11103 23:58:21.693121 Skipping test definition patterns.
11104 23:58:21.694652 + cd ./automated/linux/kselftest/
11105 23:58:21.724330 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11106 23:58:21.783275 INFO: install_deps skipped
11107 23:58:22.311266 --2024-05-29 23:58:22-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11108 23:58:22.327018 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11109 23:58:22.457514 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11110 23:58:22.586477 HTTP request sent, awaiting response... 200 OK
11111 23:58:22.589908 Length: 1642292 (1.6M) [application/octet-stream]
11112 23:58:22.592797 Saving to: 'kselftest_armhf.tar.gz'
11113 23:58:22.593407
11114 23:58:22.593791
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11119 23:58:23.631137 kselftest_armhf.tar 100%[===================>] 1.57M 1.51MB/s in 1.0s
11120 23:58:23.631620
11121 23:58:23.775833 2024-05-29 23:58:24 (1.51 MB/s) - 'kselftest_armhf.tar.gz' saved [1642292/1642292]
11122 23:58:23.775992
11123 23:58:29.458346 skiplist:
11124 23:58:29.461632 ========================================
11125 23:58:29.465022 ========================================
11126 23:58:29.528675 arm64:tags_test
11127 23:58:29.532277 arm64:run_tags_test.sh
11128 23:58:29.532707 arm64:fake_sigreturn_bad_magic
11129 23:58:29.535303 arm64:fake_sigreturn_bad_size
11130 23:58:29.538596 arm64:fake_sigreturn_bad_size_for_magic0
11131 23:58:29.541766 arm64:fake_sigreturn_duplicated_fpsimd
11132 23:58:29.545187 arm64:fake_sigreturn_misaligned_sp
11133 23:58:29.548419 arm64:fake_sigreturn_missing_fpsimd
11134 23:58:29.551763 arm64:fake_sigreturn_sme_change_vl
11135 23:58:29.555734 arm64:fake_sigreturn_sve_change_vl
11136 23:58:29.558122 arm64:mangle_pstate_invalid_compat_toggle
11137 23:58:29.561824 arm64:mangle_pstate_invalid_daif_bits
11138 23:58:29.564563 arm64:mangle_pstate_invalid_mode_el1h
11139 23:58:29.568032 arm64:mangle_pstate_invalid_mode_el1t
11140 23:58:29.571790 arm64:mangle_pstate_invalid_mode_el2h
11141 23:58:29.574511 arm64:mangle_pstate_invalid_mode_el2t
11142 23:58:29.578193 arm64:mangle_pstate_invalid_mode_el3h
11143 23:58:29.581158 arm64:mangle_pstate_invalid_mode_el3t
11144 23:58:29.585103 arm64:sme_trap_no_sm
11145 23:58:29.587827 arm64:sme_trap_non_streaming
11146 23:58:29.588357 arm64:sme_trap_za
11147 23:58:29.591014 arm64:sme_vl
11148 23:58:29.591538 arm64:ssve_regs
11149 23:58:29.594752 arm64:sve_regs
11150 23:58:29.595168 arm64:sve_vl
11151 23:58:29.595513 arm64:za_no_regs
11152 23:58:29.597488 arm64:za_regs
11153 23:58:29.597915 arm64:pac
11154 23:58:29.601100 arm64:fp-stress
11155 23:58:29.601560 arm64:sve-ptrace
11156 23:58:29.604719 arm64:sve-probe-vls
11157 23:58:29.605135 arm64:vec-syscfg
11158 23:58:29.605559 arm64:za-fork
11159 23:58:29.607833 arm64:za-ptrace
11160 23:58:29.611008 arm64:check_buffer_fill
11161 23:58:29.611424 arm64:check_child_memory
11162 23:58:29.614552 arm64:check_gcr_el1_cswitch
11163 23:58:29.617735 arm64:check_ksm_options
11164 23:58:29.618149 arm64:check_mmap_options
11165 23:58:29.621419 arm64:check_prctl
11166 23:58:29.624293 arm64:check_tags_inclusion
11167 23:58:29.624710 arm64:check_user_mem
11168 23:58:29.627606 arm64:btitest
11169 23:58:29.628091 arm64:nobtitest
11170 23:58:29.628428 arm64:hwcap
11171 23:58:29.630577 arm64:ptrace
11172 23:58:29.630998 arm64:syscall-abi
11173 23:58:29.633918 arm64:tpidr2
11174 23:58:29.637651 ============== Tests to run ===============
11175 23:58:29.638073 arm64:tags_test
11176 23:58:29.640728 arm64:run_tags_test.sh
11177 23:58:29.644088 arm64:fake_sigreturn_bad_magic
11178 23:58:29.647496 arm64:fake_sigreturn_bad_size
11179 23:58:29.650815 arm64:fake_sigreturn_bad_size_for_magic0
11180 23:58:29.654237 arm64:fake_sigreturn_duplicated_fpsimd
11181 23:58:29.657047 arm64:fake_sigreturn_misaligned_sp
11182 23:58:29.660500 arm64:fake_sigreturn_missing_fpsimd
11183 23:58:29.663580 arm64:fake_sigreturn_sme_change_vl
11184 23:58:29.663998 arm64:fake_sigreturn_sve_change_vl
11185 23:58:29.670170 arm64:mangle_pstate_invalid_compat_toggle
11186 23:58:29.673747 arm64:mangle_pstate_invalid_daif_bits
11187 23:58:29.677217 arm64:mangle_pstate_invalid_mode_el1h
11188 23:58:29.680308 arm64:mangle_pstate_invalid_mode_el1t
11189 23:58:29.683520 arm64:mangle_pstate_invalid_mode_el2h
11190 23:58:29.686806 arm64:mangle_pstate_invalid_mode_el2t
11191 23:58:29.690050 arm64:mangle_pstate_invalid_mode_el3h
11192 23:58:29.693762 arm64:mangle_pstate_invalid_mode_el3t
11193 23:58:29.694179 arm64:sme_trap_no_sm
11194 23:58:29.696776 arm64:sme_trap_non_streaming
11195 23:58:29.699952 arm64:sme_trap_za
11196 23:58:29.700368 arm64:sme_vl
11197 23:58:29.700696 arm64:ssve_regs
11198 23:58:29.703689 arm64:sve_regs
11199 23:58:29.704107 arm64:sve_vl
11200 23:58:29.706857 arm64:za_no_regs
11201 23:58:29.707299 arm64:za_regs
11202 23:58:29.707659 arm64:pac
11203 23:58:29.709809 arm64:fp-stress
11204 23:58:29.710225 arm64:sve-ptrace
11205 23:58:29.713184 arm64:sve-probe-vls
11206 23:58:29.713665 arm64:vec-syscfg
11207 23:58:29.716506 arm64:za-fork
11208 23:58:29.716925 arm64:za-ptrace
11209 23:58:29.719878 arm64:check_buffer_fill
11210 23:58:29.723185 arm64:check_child_memory
11211 23:58:29.723763 arm64:check_gcr_el1_cswitch
11212 23:58:29.726424 arm64:check_ksm_options
11213 23:58:29.731372 arm64:check_mmap_options
11214 23:58:29.731788 arm64:check_prctl
11215 23:58:29.733018 arm64:check_tags_inclusion
11216 23:58:29.733511 arm64:check_user_mem
11217 23:58:29.736674 arm64:btitest
11218 23:58:29.737086 arm64:nobtitest
11219 23:58:29.739409 arm64:hwcap
11220 23:58:29.739995 arm64:ptrace
11221 23:58:29.743026 arm64:syscall-abi
11222 23:58:29.743442 arm64:tpidr2
11223 23:58:29.746002 ===========End Tests to run ===============
11224 23:58:29.749975 shardfile-arm64 pass
11225 23:58:30.055104 <12>[ 29.715701] kselftest: Running tests in arm64
11226 23:58:30.067705 TAP version 13
11227 23:58:30.084798 1..48
11228 23:58:30.107103 # selftests: arm64: tags_test
11229 23:58:30.596871 ok 1 selftests: arm64: tags_test
11230 23:58:30.615427 # selftests: arm64: run_tags_test.sh
11231 23:58:30.672262 # --------------------
11232 23:58:30.674815 # running tags test
11233 23:58:30.675237 # --------------------
11234 23:58:30.678027 # [PASS]
11235 23:58:30.681311 ok 2 selftests: arm64: run_tags_test.sh
11236 23:58:30.699417 # selftests: arm64: fake_sigreturn_bad_magic
11237 23:58:30.782556 # Registered handlers for all signals.
11238 23:58:30.783061 # Detected MINSTKSIGSZ:4720
11239 23:58:30.786250 # Testcase initialized.
11240 23:58:30.789855 # uc context validated.
11241 23:58:30.792863 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11242 23:58:30.796264 # Handled SIG_COPYCTX
11243 23:58:30.796683 # Available space:3568
11244 23:58:30.802338 # Using badly built context - ERR: BAD MAGIC !
11245 23:58:30.808943 # SIG_OK -- SP:0xFFFFE46779E0 si_addr@:0xffffe46779e0 si_code:2 token@:0xffffe4676780 offset:-4704
11246 23:58:30.812519 # ==>> completed. PASS(1)
11247 23:58:30.818924 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11248 23:58:30.825562 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE4676780
11249 23:58:30.832531 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11250 23:58:30.836029 # selftests: arm64: fake_sigreturn_bad_size
11251 23:58:30.884079 # Registered handlers for all signals.
11252 23:58:30.884587 # Detected MINSTKSIGSZ:4720
11253 23:58:30.887152 # Testcase initialized.
11254 23:58:30.890515 # uc context validated.
11255 23:58:30.893961 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11256 23:58:30.897113 # Handled SIG_COPYCTX
11257 23:58:30.897582 # Available space:3568
11258 23:58:30.900514 # uc context validated.
11259 23:58:30.907449 # Using badly built context - ERR: Bad size for esr_context
11260 23:58:30.913254 # SIG_OK -- SP:0xFFFFDCF058D0 si_addr@:0xffffdcf058d0 si_code:2 token@:0xffffdcf04670 offset:-4704
11261 23:58:30.916910 # ==>> completed. PASS(1)
11262 23:58:30.923336 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11263 23:58:30.930420 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDCF04670
11264 23:58:30.933958 ok 4 selftests: arm64: fake_sigreturn_bad_size
11265 23:58:30.940008 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11266 23:58:30.985438 # Registered handlers for all signals.
11267 23:58:30.985961 # Detected MINSTKSIGSZ:4720
11268 23:58:30.989021 # Testcase initialized.
11269 23:58:30.991764 # uc context validated.
11270 23:58:30.996193 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11271 23:58:30.999362 # Handled SIG_COPYCTX
11272 23:58:30.999779 # Available space:3568
11273 23:58:31.004988 # Using badly built context - ERR: Bad size for terminator
11274 23:58:31.014921 # SIG_OK -- SP:0xFFFFCA094190 si_addr@:0xffffca094190 si_code:2 token@:0xffffca092f30 offset:-4704
11275 23:58:31.015349 # ==>> completed. PASS(1)
11276 23:58:31.025459 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11277 23:58:31.032046 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCA092F30
11278 23:58:31.034713 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11279 23:58:31.041745 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11280 23:58:31.086143 # Registered handlers for all signals.
11281 23:58:31.086658 # Detected MINSTKSIGSZ:4720
11282 23:58:31.088455 # Testcase initialized.
11283 23:58:31.091992 # uc context validated.
11284 23:58:31.095551 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11285 23:58:31.098184 # Handled SIG_COPYCTX
11286 23:58:31.098599 # Available space:3568
11287 23:58:31.105325 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11288 23:58:31.115089 # SIG_OK -- SP:0xFFFFE19B6600 si_addr@:0xffffe19b6600 si_code:2 token@:0xffffe19b53a0 offset:-4704
11289 23:58:31.115547 # ==>> completed. PASS(1)
11290 23:58:31.124587 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11291 23:58:31.131443 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE19B53A0
11292 23:58:31.134977 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11293 23:58:31.137884 # selftests: arm64: fake_sigreturn_misaligned_sp
11294 23:58:31.170832 # Registered handlers for all signals.
11295 23:58:31.171336 # Detected MINSTKSIGSZ:4720
11296 23:58:31.173511 # Testcase initialized.
11297 23:58:31.176923 # uc context validated.
11298 23:58:31.180364 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11299 23:58:31.183641 # Handled SIG_COPYCTX
11300 23:58:31.189731 # SIG_OK -- SP:0xFFFFFCA331B3 si_addr@:0xfffffca331b3 si_code:2 token@:0xfffffca331b3 offset:0
11301 23:58:31.193288 # ==>> completed. PASS(1)
11302 23:58:31.199560 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11303 23:58:31.206513 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFCA331B3
11304 23:58:31.212752 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11305 23:58:31.216572 # selftests: arm64: fake_sigreturn_missing_fpsimd
11306 23:58:31.264739 # Registered handlers for all signals.
11307 23:58:31.265328 # Detected MINSTKSIGSZ:4720
11308 23:58:31.267893 # Testcase initialized.
11309 23:58:31.271368 # uc context validated.
11310 23:58:31.274594 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11311 23:58:31.277462 # Handled SIG_COPYCTX
11312 23:58:31.281157 # Mangling template header. Spare space:4096
11313 23:58:31.284240 # Using badly built context - ERR: Missing FPSIMD
11314 23:58:31.294631 # SIG_OK -- SP:0xFFFFC5158080 si_addr@:0xffffc5158080 si_code:2 token@:0xffffc5156e20 offset:-4704
11315 23:58:31.297547 # ==>> completed. PASS(1)
11316 23:58:31.304100 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11317 23:58:31.310680 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC5156E20
11318 23:58:31.314737 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11319 23:58:31.320774 # selftests: arm64: fake_sigreturn_sme_change_vl
11320 23:58:31.347638 # Registered handlers for all signals.
11321 23:58:31.348189 # Detected MINSTKSIGSZ:4720
11322 23:58:31.350294 # ==>> completed. SKIP.
11323 23:58:31.357042 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11324 23:58:31.359836 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11325 23:58:31.370573 # selftests: arm64: fake_sigreturn_sve_change_vl
11326 23:58:31.450483 # Registered handlers for all signals.
11327 23:58:31.451038 # Detected MINSTKSIGSZ:4720
11328 23:58:31.453836 # ==>> completed. SKIP.
11329 23:58:31.460339 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11330 23:58:31.463705 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11331 23:58:31.475340 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11332 23:58:31.544447 # Registered handlers for all signals.
11333 23:58:31.544999 # Detected MINSTKSIGSZ:4720
11334 23:58:31.547376 # Testcase initialized.
11335 23:58:31.550704 # uc context validated.
11336 23:58:31.551138 # Handled SIG_TRIG
11337 23:58:31.560538 # SIG_OK -- SP:0xFFFFC6200AF0 si_addr@:0xffffc6200af0 si_code:2 token@:(nil) offset:-281474005732080
11338 23:58:31.564048 # ==>> completed. PASS(1)
11339 23:58:31.570556 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11340 23:58:31.577186 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11341 23:58:31.580307 # selftests: arm64: mangle_pstate_invalid_daif_bits
11342 23:58:31.632364 # Registered handlers for all signals.
11343 23:58:31.632868 # Detected MINSTKSIGSZ:4720
11344 23:58:31.635073 # Testcase initialized.
11345 23:58:31.638910 # uc context validated.
11346 23:58:31.639332 # Handled SIG_TRIG
11347 23:58:31.648780 # SIG_OK -- SP:0xFFFFD515BC80 si_addr@:0xffffd515bc80 si_code:2 token@:(nil) offset:-281474256714880
11348 23:58:31.651702 # ==>> completed. PASS(1)
11349 23:58:31.658715 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11350 23:58:31.662027 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11351 23:58:31.668189 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11352 23:58:31.731801 # Registered handlers for all signals.
11353 23:58:31.732493 # Detected MINSTKSIGSZ:4720
11354 23:58:31.735185 # Testcase initialized.
11355 23:58:31.738722 # uc context validated.
11356 23:58:31.739143 # Handled SIG_TRIG
11357 23:58:31.748522 # SIG_OK -- SP:0xFFFFF3CCC060 si_addr@:0xfffff3ccc060 si_code:2 token@:(nil) offset:-281474772025440
11358 23:58:31.751337 # ==>> completed. PASS(1)
11359 23:58:31.758130 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11360 23:58:31.761373 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11361 23:58:31.768416 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11362 23:58:31.831091 # Registered handlers for all signals.
11363 23:58:31.831592 # Detected MINSTKSIGSZ:4720
11364 23:58:31.834222 # Testcase initialized.
11365 23:58:31.837564 # uc context validated.
11366 23:58:31.838023 # Handled SIG_TRIG
11367 23:58:31.847550 # SIG_OK -- SP:0xFFFFEBEB5570 si_addr@:0xffffebeb5570 si_code:2 token@:(nil) offset:-281474639811952
11368 23:58:31.851289 # ==>> completed. PASS(1)
11369 23:58:31.857629 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11370 23:58:31.860729 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11371 23:58:31.867248 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11372 23:58:31.933889 # Registered handlers for all signals.
11373 23:58:31.934430 # Detected MINSTKSIGSZ:4720
11374 23:58:31.936988 # Testcase initialized.
11375 23:58:31.940728 # uc context validated.
11376 23:58:31.941138 # Handled SIG_TRIG
11377 23:58:31.950088 # SIG_OK -- SP:0xFFFFF293CC00 si_addr@:0xfffff293cc00 si_code:2 token@:(nil) offset:-281474751515648
11378 23:58:31.953545 # ==>> completed. PASS(1)
11379 23:58:31.960405 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11380 23:58:31.963364 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11381 23:58:31.970221 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11382 23:58:32.026141 # Registered handlers for all signals.
11383 23:58:32.026619 # Detected MINSTKSIGSZ:4720
11384 23:58:32.029611 # Testcase initialized.
11385 23:58:32.032833 # uc context validated.
11386 23:58:32.033458 # Handled SIG_TRIG
11387 23:58:32.043087 # SIG_OK -- SP:0xFFFFD56D8AC0 si_addr@:0xffffd56d8ac0 si_code:2 token@:(nil) offset:-281474262469312
11388 23:58:32.045757 # ==>> completed. PASS(1)
11389 23:58:32.052639 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11390 23:58:32.055839 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11391 23:58:32.062541 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11392 23:58:32.130073 # Registered handlers for all signals.
11393 23:58:32.130584 # Detected MINSTKSIGSZ:4720
11394 23:58:32.132785 # Testcase initialized.
11395 23:58:32.135751 # uc context validated.
11396 23:58:32.136281 # Handled SIG_TRIG
11397 23:58:32.146363 # SIG_OK -- SP:0xFFFFC8FCD110 si_addr@:0xffffc8fcd110 si_code:2 token@:(nil) offset:-281474053755152
11398 23:58:32.149313 # ==>> completed. PASS(1)
11399 23:58:32.155824 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11400 23:58:32.159326 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11401 23:58:32.166074 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11402 23:58:32.216756 # Registered handlers for all signals.
11403 23:58:32.217199 # Detected MINSTKSIGSZ:4720
11404 23:58:32.219692 # Testcase initialized.
11405 23:58:32.223043 # uc context validated.
11406 23:58:32.223473 # Handled SIG_TRIG
11407 23:58:32.232449 # SIG_OK -- SP:0xFFFFC32AD7A0 si_addr@:0xffffc32ad7a0 si_code:2 token@:(nil) offset:-281473956108192
11408 23:58:32.235648 # ==>> completed. PASS(1)
11409 23:58:32.242478 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11410 23:58:32.246303 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11411 23:58:32.249005 # selftests: arm64: sme_trap_no_sm
11412 23:58:32.301731 # Registered handlers for all signals.
11413 23:58:32.302396 # Detected MINSTKSIGSZ:4720
11414 23:58:32.305076 # ==>> completed. SKIP.
11415 23:58:32.314707 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11416 23:58:32.317930 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11417 23:58:32.321535 # selftests: arm64: sme_trap_non_streaming
11418 23:58:32.399522 # Registered handlers for all signals.
11419 23:58:32.400077 # Detected MINSTKSIGSZ:4720
11420 23:58:32.402741 # ==>> completed. SKIP.
11421 23:58:32.412579 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11422 23:58:32.418982 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11423 23:58:32.422669 # selftests: arm64: sme_trap_za
11424 23:58:32.496706 # Registered handlers for all signals.
11425 23:58:32.497294 # Detected MINSTKSIGSZ:4720
11426 23:58:32.499643 # Testcase initialized.
11427 23:58:32.509239 # SIG_OK -- SP:0xFFFFFC7F3750 si_addr@:0xaaaadc182510 si_code:1 token@:(nil) offset:-187650813732112
11428 23:58:32.509704 # ==>> completed. PASS(1)
11429 23:58:32.519344 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11430 23:58:32.522603 ok 21 selftests: arm64: sme_trap_za
11431 23:58:32.523031 # selftests: arm64: sme_vl
11432 23:58:32.596002 # Registered handlers for all signals.
11433 23:58:32.596538 # Detected MINSTKSIGSZ:4720
11434 23:58:32.599130 # ==>> completed. SKIP.
11435 23:58:32.605193 # # SME VL :: Check that we get the right SME VL reported
11436 23:58:32.608338 ok 22 selftests: arm64: sme_vl # SKIP
11437 23:58:32.616743 # selftests: arm64: ssve_regs
11438 23:58:32.698381 # Registered handlers for all signals.
11439 23:58:32.698922 # Detected MINSTKSIGSZ:4720
11440 23:58:32.702177 # ==>> completed. SKIP.
11441 23:58:32.708448 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11442 23:58:32.714749 ok 23 selftests: arm64: ssve_regs # SKIP
11443 23:58:32.724748 # selftests: arm64: sve_regs
11444 23:58:32.795922 # Registered handlers for all signals.
11445 23:58:32.796432 # Detected MINSTKSIGSZ:4720
11446 23:58:32.799237 # ==>> completed. SKIP.
11447 23:58:32.805843 # # SVE registers :: Check that we get the right SVE registers reported
11448 23:58:32.808809 ok 24 selftests: arm64: sve_regs # SKIP
11449 23:58:32.822039 # selftests: arm64: sve_vl
11450 23:58:32.884324 # Registered handlers for all signals.
11451 23:58:32.884896 # Detected MINSTKSIGSZ:4720
11452 23:58:32.887582 # ==>> completed. SKIP.
11453 23:58:32.893898 # # SVE VL :: Check that we get the right SVE VL reported
11454 23:58:32.897329 ok 25 selftests: arm64: sve_vl # SKIP
11455 23:58:32.904565 # selftests: arm64: za_no_regs
11456 23:58:32.979896 # Registered handlers for all signals.
11457 23:58:32.980444 # Detected MINSTKSIGSZ:4720
11458 23:58:32.982533 # ==>> completed. SKIP.
11459 23:58:32.989424 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11460 23:58:32.992591 ok 26 selftests: arm64: za_no_regs # SKIP
11461 23:58:33.000664 # selftests: arm64: za_regs
11462 23:58:33.069799 # Registered handlers for all signals.
11463 23:58:33.070348 # Detected MINSTKSIGSZ:4720
11464 23:58:33.072802 # ==>> completed. SKIP.
11465 23:58:33.079622 # # ZA register :: Check that we get the right ZA registers reported
11466 23:58:33.082388 ok 27 selftests: arm64: za_regs # SKIP
11467 23:58:33.089130 # selftests: arm64: pac
11468 23:58:33.152650 # TAP version 13
11469 23:58:33.153222 # 1..7
11470 23:58:33.155874 # # Starting 7 tests from 1 test cases.
11471 23:58:33.160171 # # RUN global.corrupt_pac ...
11472 23:58:33.162856 # # SKIP PAUTH not enabled
11473 23:58:33.166664 # # OK global.corrupt_pac
11474 23:58:33.169133 # ok 1 # SKIP PAUTH not enabled
11475 23:58:33.175841 # # RUN global.pac_instructions_not_nop ...
11476 23:58:33.178875 # # SKIP PAUTH not enabled
11477 23:58:33.182291 # # OK global.pac_instructions_not_nop
11478 23:58:33.185949 # ok 2 # SKIP PAUTH not enabled
11479 23:58:33.191957 # # RUN global.pac_instructions_not_nop_generic ...
11480 23:58:33.195477 # # SKIP Generic PAUTH not enabled
11481 23:58:33.198675 # # OK global.pac_instructions_not_nop_generic
11482 23:58:33.205459 # ok 3 # SKIP Generic PAUTH not enabled
11483 23:58:33.208530 # # RUN global.single_thread_different_keys ...
11484 23:58:33.212145 # # SKIP PAUTH not enabled
11485 23:58:33.218401 # # OK global.single_thread_different_keys
11486 23:58:33.218832 # ok 4 # SKIP PAUTH not enabled
11487 23:58:33.225309 # # RUN global.exec_changed_keys ...
11488 23:58:33.228371 # # SKIP PAUTH not enabled
11489 23:58:33.232094 # # OK global.exec_changed_keys
11490 23:58:33.234767 # ok 5 # SKIP PAUTH not enabled
11491 23:58:33.238789 # # RUN global.context_switch_keep_keys ...
11492 23:58:33.241792 # # SKIP PAUTH not enabled
11493 23:58:33.248043 # # OK global.context_switch_keep_keys
11494 23:58:33.248490 # ok 6 # SKIP PAUTH not enabled
11495 23:58:33.255584 # # RUN global.context_switch_keep_keys_generic ...
11496 23:58:33.258037 # # SKIP Generic PAUTH not enabled
11497 23:58:33.264796 # # OK global.context_switch_keep_keys_generic
11498 23:58:33.268566 # ok 7 # SKIP Generic PAUTH not enabled
11499 23:58:33.271423 # # PASSED: 7 / 7 tests passed.
11500 23:58:33.274989 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11501 23:58:33.278995 ok 28 selftests: arm64: pac
11502 23:58:33.281135 # selftests: arm64: fp-stress
11503 23:58:40.353625 <6>[ 40.018710] vpu: disabling
11504 23:58:40.356777 <6>[ 40.021760] vproc2: disabling
11505 23:58:40.360328 <6>[ 40.025034] vproc1: disabling
11506 23:58:40.364115 <6>[ 40.028303] vaud18: disabling
11507 23:58:40.370137 <6>[ 40.031733] vsram_others: disabling
11508 23:58:40.373651 <6>[ 40.035624] va09: disabling
11509 23:58:40.377630 <6>[ 40.038741] vsram_md: disabling
11510 23:58:40.380316 <6>[ 40.042241] Vgpu: disabling
11511 23:58:43.231711 # TAP version 13
11512 23:58:43.232271 # 1..16
11513 23:58:43.235105 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11514 23:58:43.238154 # # Will run for 10s
11515 23:58:43.238608 # # Started FPSIMD-0-0
11516 23:58:43.242215 # # Started FPSIMD-0-1
11517 23:58:43.245068 # # Started FPSIMD-1-0
11518 23:58:43.245576 # # Started FPSIMD-1-1
11519 23:58:43.248311 # # Started FPSIMD-2-0
11520 23:58:43.248722 # # Started FPSIMD-2-1
11521 23:58:43.251697 # # Started FPSIMD-3-0
11522 23:58:43.255068 # # Started FPSIMD-3-1
11523 23:58:43.255481 # # Started FPSIMD-4-0
11524 23:58:43.257984 # # Started FPSIMD-4-1
11525 23:58:43.261703 # # Started FPSIMD-5-0
11526 23:58:43.262115 # # Started FPSIMD-5-1
11527 23:58:43.264967 # # Started FPSIMD-6-0
11528 23:58:43.267877 # # Started FPSIMD-6-1
11529 23:58:43.268287 # # Started FPSIMD-7-0
11530 23:58:43.271123 # # Started FPSIMD-7-1
11531 23:58:43.275009 # # FPSIMD-0-1: Vector length: 128 bits
11532 23:58:43.278189 # # FPSIMD-0-1: PID: 1166
11533 23:58:43.281081 # # FPSIMD-0-0: Vector length: 128 bits
11534 23:58:43.281578 # # FPSIMD-0-0: PID: 1165
11535 23:58:43.284704 # # FPSIMD-2-0: Vector length: 128 bits
11536 23:58:43.288055 # # FPSIMD-2-0: PID: 1169
11537 23:58:43.291379 # # FPSIMD-1-1: Vector length: 128 bits
11538 23:58:43.295203 # # FPSIMD-1-1: PID: 1168
11539 23:58:43.297831 # # FPSIMD-1-0: Vector length: 128 bits
11540 23:58:43.301146 # # FPSIMD-1-0: PID: 1167
11541 23:58:43.304416 # # FPSIMD-2-1: Vector length: 128 bits
11542 23:58:43.308122 # # FPSIMD-2-1: PID: 1170
11543 23:58:43.311035 # # FPSIMD-4-0: Vector length: 128 bits
11544 23:58:43.311546 # # FPSIMD-4-0: PID: 1173
11545 23:58:43.314078 # # FPSIMD-6-1: Vector length: 128 bits
11546 23:58:43.317345 # # FPSIMD-6-1: PID: 1178
11547 23:58:43.320610 # # FPSIMD-5-1: Vector length: 128 bits
11548 23:58:43.324949 # # FPSIMD-5-1: PID: 1176
11549 23:58:43.327191 # # FPSIMD-7-1: Vector length: 128 bits
11550 23:58:43.330584 # # FPSIMD-7-1: PID: 1180
11551 23:58:43.334432 # # FPSIMD-3-1: Vector length: 128 bits
11552 23:58:43.334844 # # FPSIMD-3-1: PID: 1172
11553 23:58:43.341110 # # FPSIMD-7-0: Vector length: 128 bits
11554 23:58:43.341618 # # FPSIMD-7-0: PID: 1179
11555 23:58:43.344302 # # FPSIMD-5-0: Vector length: 128 bits
11556 23:58:43.347438 # # FPSIMD-5-0: PID: 1175
11557 23:58:43.350343 # # FPSIMD-4-1: Vector length: 128 bits
11558 23:58:43.353556 # # FPSIMD-4-1: PID: 1174
11559 23:58:43.357159 # # FPSIMD-6-0: Vector length: 128 bits
11560 23:58:43.360515 # # FPSIMD-6-0: PID: 1177
11561 23:58:43.363658 # # FPSIMD-3-0: Vector length: 128 bits
11562 23:58:43.364076 # # FPSIMD-3-0: PID: 1171
11563 23:58:43.366958 # # Finishing up...
11564 23:58:43.373366 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1457455, signals=10
11565 23:58:43.380057 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1391843, signals=10
11566 23:58:43.390008 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1405269, signals=10
11567 23:58:43.396647 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1052500, signals=10
11568 23:58:43.403458 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=946621, signals=10
11569 23:58:43.409732 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1557283, signals=10
11570 23:58:43.416627 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1436737, signals=10
11571 23:58:43.419586 # ok 1 FPSIMD-0-0
11572 23:58:43.420004 # ok 2 FPSIMD-0-1
11573 23:58:43.423157 # ok 3 FPSIMD-1-0
11574 23:58:43.423575 # ok 4 FPSIMD-1-1
11575 23:58:43.426693 # ok 5 FPSIMD-2-0
11576 23:58:43.427133 # ok 6 FPSIMD-2-1
11577 23:58:43.429497 # ok 7 FPSIMD-3-0
11578 23:58:43.429913 # ok 8 FPSIMD-3-1
11579 23:58:43.432899 # ok 9 FPSIMD-4-0
11580 23:58:43.433461 # ok 10 FPSIMD-4-1
11581 23:58:43.436367 # ok 11 FPSIMD-5-0
11582 23:58:43.436788 # ok 12 FPSIMD-5-1
11583 23:58:43.439541 # ok 13 FPSIMD-6-0
11584 23:58:43.440012 # ok 14 FPSIMD-6-1
11585 23:58:43.442812 # ok 15 FPSIMD-7-0
11586 23:58:43.443223 # ok 16 FPSIMD-7-1
11587 23:58:43.452488 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=856235, signals=9
11588 23:58:43.459700 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1074568, signals=10
11589 23:58:43.465750 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=833465, signals=10
11590 23:58:43.472241 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1214347, signals=9
11591 23:58:43.478952 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1157225, signals=10
11592 23:58:43.485339 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1201770, signals=10
11593 23:58:43.495700 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1651555, signals=10
11594 23:58:43.502076 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=823188, signals=10
11595 23:58:43.508512 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1313071, signals=9
11596 23:58:43.512024 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11597 23:58:43.515072 ok 29 selftests: arm64: fp-stress
11598 23:58:43.518883 # selftests: arm64: sve-ptrace
11599 23:58:43.521760 # TAP version 13
11600 23:58:43.522169 # 1..4104
11601 23:58:43.525072 # ok 2 # SKIP SVE not available
11602 23:58:43.528614 # # Planned tests != run tests (4104 != 1)
11603 23:58:43.535246 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11604 23:58:43.538761 ok 30 selftests: arm64: sve-ptrace # SKIP
11605 23:58:43.541708 # selftests: arm64: sve-probe-vls
11606 23:58:43.542198 # TAP version 13
11607 23:58:43.542555 # 1..2
11608 23:58:43.544682 # ok 2 # SKIP SVE not available
11609 23:58:43.548646 # # Planned tests != run tests (2 != 1)
11610 23:58:43.554631 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11611 23:58:43.558177 ok 31 selftests: arm64: sve-probe-vls # SKIP
11612 23:58:43.561291 # selftests: arm64: vec-syscfg
11613 23:58:43.561714 # TAP version 13
11614 23:58:43.564465 # 1..20
11615 23:58:43.564877 # ok 1 # SKIP SVE not supported
11616 23:58:43.567834 # ok 2 # SKIP SVE not supported
11617 23:58:43.571378 # ok 3 # SKIP SVE not supported
11618 23:58:43.574546 # ok 4 # SKIP SVE not supported
11619 23:58:43.577757 # ok 5 # SKIP SVE not supported
11620 23:58:43.581424 # ok 6 # SKIP SVE not supported
11621 23:58:43.584296 # ok 7 # SKIP SVE not supported
11622 23:58:43.584712 # ok 8 # SKIP SVE not supported
11623 23:58:43.587722 # ok 9 # SKIP SVE not supported
11624 23:58:43.591320 # ok 10 # SKIP SVE not supported
11625 23:58:43.594569 # ok 11 # SKIP SME not supported
11626 23:58:43.597856 # ok 12 # SKIP SME not supported
11627 23:58:43.600913 # ok 13 # SKIP SME not supported
11628 23:58:43.604561 # ok 14 # SKIP SME not supported
11629 23:58:43.607522 # ok 15 # SKIP SME not supported
11630 23:58:43.611085 # ok 16 # SKIP SME not supported
11631 23:58:43.611502 # ok 17 # SKIP SME not supported
11632 23:58:43.614842 # ok 18 # SKIP SME not supported
11633 23:58:43.617482 # ok 19 # SKIP SME not supported
11634 23:58:43.620627 # ok 20 # SKIP SME not supported
11635 23:58:43.627291 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11636 23:58:43.631107 ok 32 selftests: arm64: vec-syscfg
11637 23:58:43.631545 # selftests: arm64: za-fork
11638 23:58:43.633992 # TAP version 13
11639 23:58:43.634405 # 1..1
11640 23:58:43.634751 # # PID: 1257
11641 23:58:43.637248 # # SME support not present
11642 23:58:43.640795 # ok 0 skipped
11643 23:58:43.643744 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11644 23:58:43.647155 ok 33 selftests: arm64: za-fork
11645 23:58:43.650187 # selftests: arm64: za-ptrace
11646 23:58:43.698854 # TAP version 13
11647 23:58:43.699381 # 1..1
11648 23:58:43.701705 # ok 2 # SKIP SME not available
11649 23:58:43.709145 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11650 23:58:43.711315 ok 34 selftests: arm64: za-ptrace # SKIP
11651 23:58:43.725172 # selftests: arm64: check_buffer_fill
11652 23:58:43.809541 # # SKIP: MTE features unavailable
11653 23:58:43.816897 ok 35 selftests: arm64: check_buffer_fill # SKIP
11654 23:58:43.835673 # selftests: arm64: check_child_memory
11655 23:58:43.904109 # # SKIP: MTE features unavailable
11656 23:58:43.911482 ok 36 selftests: arm64: check_child_memory # SKIP
11657 23:58:43.932285 # selftests: arm64: check_gcr_el1_cswitch
11658 23:58:43.991581 # # SKIP: MTE features unavailable
11659 23:58:43.998325 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11660 23:58:44.016912 # selftests: arm64: check_ksm_options
11661 23:58:44.069415 # # SKIP: MTE features unavailable
11662 23:58:44.076321 ok 38 selftests: arm64: check_ksm_options # SKIP
11663 23:58:44.096929 # selftests: arm64: check_mmap_options
11664 23:58:44.159823 # # SKIP: MTE features unavailable
11665 23:58:44.168637 ok 39 selftests: arm64: check_mmap_options # SKIP
11666 23:58:44.185748 # selftests: arm64: check_prctl
11667 23:58:44.257952 # TAP version 13
11668 23:58:44.258573 # 1..5
11669 23:58:44.261191 # ok 1 check_basic_read
11670 23:58:44.261821 # ok 2 NONE
11671 23:58:44.264637 # ok 3 # SKIP SYNC
11672 23:58:44.265216 # ok 4 # SKIP ASYNC
11673 23:58:44.268684 # ok 5 # SKIP SYNC+ASYNC
11674 23:58:44.271478 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11675 23:58:44.275552 ok 40 selftests: arm64: check_prctl
11676 23:58:44.288387 # selftests: arm64: check_tags_inclusion
11677 23:58:44.355357 # # SKIP: MTE features unavailable
11678 23:58:44.363142 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11679 23:58:44.379299 # selftests: arm64: check_user_mem
11680 23:58:44.445900 # # SKIP: MTE features unavailable
11681 23:58:44.453330 ok 42 selftests: arm64: check_user_mem # SKIP
11682 23:58:44.467739 # selftests: arm64: btitest
11683 23:58:44.532566 # TAP version 13
11684 23:58:44.533114 # 1..18
11685 23:58:44.535679 # # HWCAP_PACA not present
11686 23:58:44.538716 # # HWCAP2_BTI not present
11687 23:58:44.539131 # # Test binary built for BTI
11688 23:58:44.545834 # ok 1 nohint_func/call_using_br_x0 # SKIP
11689 23:58:44.548823 # ok 1 nohint_func/call_using_br_x16 # SKIP
11690 23:58:44.552437 # ok 1 nohint_func/call_using_blr # SKIP
11691 23:58:44.555519 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11692 23:58:44.558754 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11693 23:58:44.565242 # ok 1 bti_none_func/call_using_blr # SKIP
11694 23:58:44.568390 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11695 23:58:44.572481 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11696 23:58:44.574958 # ok 1 bti_c_func/call_using_blr # SKIP
11697 23:58:44.578633 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11698 23:58:44.581935 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11699 23:58:44.585917 # ok 1 bti_j_func/call_using_blr # SKIP
11700 23:58:44.588187 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11701 23:58:44.595170 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11702 23:58:44.598417 # ok 1 bti_jc_func/call_using_blr # SKIP
11703 23:58:44.601852 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11704 23:58:44.605635 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11705 23:58:44.608186 # ok 1 paciasp_func/call_using_blr # SKIP
11706 23:58:44.615461 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11707 23:58:44.618144 # # WARNING - EXPECTED TEST COUNT WRONG
11708 23:58:44.621998 ok 43 selftests: arm64: btitest
11709 23:58:44.624910 # selftests: arm64: nobtitest
11710 23:58:44.625373 # TAP version 13
11711 23:58:44.625712 # 1..18
11712 23:58:44.629289 # # HWCAP_PACA not present
11713 23:58:44.631280 # # HWCAP2_BTI not present
11714 23:58:44.634909 # # Test binary not built for BTI
11715 23:58:44.638213 # ok 1 nohint_func/call_using_br_x0 # SKIP
11716 23:58:44.641140 # ok 1 nohint_func/call_using_br_x16 # SKIP
11717 23:58:44.644398 # ok 1 nohint_func/call_using_blr # SKIP
11718 23:58:44.649023 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11719 23:58:44.654663 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11720 23:58:44.657896 # ok 1 bti_none_func/call_using_blr # SKIP
11721 23:58:44.660812 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11722 23:58:44.664651 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11723 23:58:44.667593 # ok 1 bti_c_func/call_using_blr # SKIP
11724 23:58:44.670899 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11725 23:58:44.673986 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11726 23:58:44.677197 # ok 1 bti_j_func/call_using_blr # SKIP
11727 23:58:44.684139 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11728 23:58:44.687521 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11729 23:58:44.690800 # ok 1 bti_jc_func/call_using_blr # SKIP
11730 23:58:44.693948 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11731 23:58:44.697250 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11732 23:58:44.700851 # ok 1 paciasp_func/call_using_blr # SKIP
11733 23:58:44.707411 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11734 23:58:44.710390 # # WARNING - EXPECTED TEST COUNT WRONG
11735 23:58:44.714060 ok 44 selftests: arm64: nobtitest
11736 23:58:44.717012 # selftests: arm64: hwcap
11737 23:58:44.717614 # TAP version 13
11738 23:58:44.717966 # 1..28
11739 23:58:44.720456 # ok 1 cpuinfo_match_RNG
11740 23:58:44.723575 # # SIGILL reported for RNG
11741 23:58:44.726989 # ok 2 # SKIP sigill_RNG
11742 23:58:44.727405 # ok 3 cpuinfo_match_SME
11743 23:58:44.730582 # ok 4 sigill_SME
11744 23:58:44.730999 # ok 5 cpuinfo_match_SVE
11745 23:58:44.733320 # ok 6 sigill_SVE
11746 23:58:44.736696 # ok 7 cpuinfo_match_SVE 2
11747 23:58:44.737109 # # SIGILL reported for SVE 2
11748 23:58:44.740073 # ok 8 # SKIP sigill_SVE 2
11749 23:58:44.743555 # ok 9 cpuinfo_match_SVE AES
11750 23:58:44.746911 # # SIGILL reported for SVE AES
11751 23:58:44.750194 # ok 10 # SKIP sigill_SVE AES
11752 23:58:44.753659 # ok 11 cpuinfo_match_SVE2 PMULL
11753 23:58:44.754078 # # SIGILL reported for SVE2 PMULL
11754 23:58:44.757172 # ok 12 # SKIP sigill_SVE2 PMULL
11755 23:58:44.759891 # ok 13 cpuinfo_match_SVE2 BITPERM
11756 23:58:44.763427 # # SIGILL reported for SVE2 BITPERM
11757 23:58:44.767066 # ok 14 # SKIP sigill_SVE2 BITPERM
11758 23:58:44.770676 # ok 15 cpuinfo_match_SVE2 SHA3
11759 23:58:44.773431 # # SIGILL reported for SVE2 SHA3
11760 23:58:44.776475 # ok 16 # SKIP sigill_SVE2 SHA3
11761 23:58:44.780342 # ok 17 cpuinfo_match_SVE2 SM4
11762 23:58:44.783384 # # SIGILL reported for SVE2 SM4
11763 23:58:44.783803 # ok 18 # SKIP sigill_SVE2 SM4
11764 23:58:44.786394 # ok 19 cpuinfo_match_SVE2 I8MM
11765 23:58:44.789983 # # SIGILL reported for SVE2 I8MM
11766 23:58:44.792961 # ok 20 # SKIP sigill_SVE2 I8MM
11767 23:58:44.797010 # ok 21 cpuinfo_match_SVE2 F32MM
11768 23:58:44.799904 # # SIGILL reported for SVE2 F32MM
11769 23:58:44.803588 # ok 22 # SKIP sigill_SVE2 F32MM
11770 23:58:44.806619 # ok 23 cpuinfo_match_SVE2 F64MM
11771 23:58:44.809716 # # SIGILL reported for SVE2 F64MM
11772 23:58:44.812965 # ok 24 # SKIP sigill_SVE2 F64MM
11773 23:58:44.813509 # ok 25 cpuinfo_match_SVE2 BF16
11774 23:58:44.816404 # # SIGILL reported for SVE2 BF16
11775 23:58:44.819574 # ok 26 # SKIP sigill_SVE2 BF16
11776 23:58:44.822770 # ok 27 cpuinfo_match_SVE2 EBF16
11777 23:58:44.826326 # ok 28 # SKIP sigill_SVE2 EBF16
11778 23:58:44.833493 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11779 23:58:44.833913 ok 45 selftests: arm64: hwcap
11780 23:58:44.836001 # selftests: arm64: ptrace
11781 23:58:44.840330 # TAP version 13
11782 23:58:44.840758 # 1..7
11783 23:58:44.842687 # # Parent is 1499, child is 1500
11784 23:58:44.843101 # ok 1 read_tpidr_one
11785 23:58:44.845773 # ok 2 write_tpidr_one
11786 23:58:44.849929 # ok 3 verify_tpidr_one
11787 23:58:44.850465 # ok 4 count_tpidrs
11788 23:58:44.852496 # ok 5 tpidr2_write
11789 23:58:44.852909 # ok 6 tpidr2_read
11790 23:58:44.855860 # ok 7 write_tpidr_only
11791 23:58:44.862432 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11792 23:58:44.862935 ok 46 selftests: arm64: ptrace
11793 23:58:44.866330 # selftests: arm64: syscall-abi
11794 23:58:44.868602 # TAP version 13
11795 23:58:44.869015 # 1..2
11796 23:58:44.872156 # ok 1 getpid() FPSIMD
11797 23:58:44.872678 # ok 2 sched_yield() FPSIMD
11798 23:58:44.879108 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11799 23:58:44.881993 ok 47 selftests: arm64: syscall-abi
11800 23:58:44.886809 # selftests: arm64: tpidr2
11801 23:58:44.964252 # TAP version 13
11802 23:58:44.964786 # 1..5
11803 23:58:44.967395 # # PID: 1536
11804 23:58:44.967944 # # SME support not present
11805 23:58:44.970579 # ok 0 skipped, TPIDR2 not supported
11806 23:58:44.973720 # ok 1 skipped, TPIDR2 not supported
11807 23:58:44.976958 # ok 2 skipped, TPIDR2 not supported
11808 23:58:44.980262 # ok 3 skipped, TPIDR2 not supported
11809 23:58:44.983587 # ok 4 skipped, TPIDR2 not supported
11810 23:58:44.990558 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11811 23:58:44.993398 ok 48 selftests: arm64: tpidr2
11812 23:58:46.579357 arm64_tags_test pass
11813 23:58:46.582531 arm64_run_tags_test_sh pass
11814 23:58:46.586291 arm64_fake_sigreturn_bad_magic pass
11815 23:58:46.588956 arm64_fake_sigreturn_bad_size pass
11816 23:58:46.592523 arm64_fake_sigreturn_bad_size_for_magic0 pass
11817 23:58:46.596158 arm64_fake_sigreturn_duplicated_fpsimd pass
11818 23:58:46.598640 arm64_fake_sigreturn_misaligned_sp pass
11819 23:58:46.602114 arm64_fake_sigreturn_missing_fpsimd pass
11820 23:58:46.605666 arm64_fake_sigreturn_sme_change_vl skip
11821 23:58:46.612621 arm64_fake_sigreturn_sve_change_vl skip
11822 23:58:46.615698 arm64_mangle_pstate_invalid_compat_toggle pass
11823 23:58:46.618782 arm64_mangle_pstate_invalid_daif_bits pass
11824 23:58:46.622119 arm64_mangle_pstate_invalid_mode_el1h pass
11825 23:58:46.625164 arm64_mangle_pstate_invalid_mode_el1t pass
11826 23:58:46.628584 arm64_mangle_pstate_invalid_mode_el2h pass
11827 23:58:46.635278 arm64_mangle_pstate_invalid_mode_el2t pass
11828 23:58:46.638692 arm64_mangle_pstate_invalid_mode_el3h pass
11829 23:58:46.641767 arm64_mangle_pstate_invalid_mode_el3t pass
11830 23:58:46.645155 arm64_sme_trap_no_sm skip
11831 23:58:46.645600 arm64_sme_trap_non_streaming skip
11832 23:58:46.648290 arm64_sme_trap_za pass
11833 23:58:46.651883 arm64_sme_vl skip
11834 23:58:46.652298 arm64_ssve_regs skip
11835 23:58:46.654790 arm64_sve_regs skip
11836 23:58:46.655362 arm64_sve_vl skip
11837 23:58:46.658839 arm64_za_no_regs skip
11838 23:58:46.659256 arm64_za_regs skip
11839 23:58:46.661366 arm64_pac_PAUTH_not_enabled skip
11840 23:58:46.664585 arm64_pac_PAUTH_not_enabled_dup2 skip
11841 23:58:46.668137 arm64_pac_Generic_PAUTH_not_enabled skip
11842 23:58:46.671168 arm64_pac_PAUTH_not_enabled_dup3 skip
11843 23:58:46.675333 arm64_pac_PAUTH_not_enabled_dup4 skip
11844 23:58:46.681637 arm64_pac_PAUTH_not_enabled_dup5 skip
11845 23:58:46.685284 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11846 23:58:46.685721 arm64_pac pass
11847 23:58:46.687788 arm64_fp-stress_FPSIMD-0-0 pass
11848 23:58:46.691251 arm64_fp-stress_FPSIMD-0-1 pass
11849 23:58:46.694368 arm64_fp-stress_FPSIMD-1-0 pass
11850 23:58:46.697551 arm64_fp-stress_FPSIMD-1-1 pass
11851 23:58:46.700946 arm64_fp-stress_FPSIMD-2-0 pass
11852 23:58:46.701415 arm64_fp-stress_FPSIMD-2-1 pass
11853 23:58:46.704940 arm64_fp-stress_FPSIMD-3-0 pass
11854 23:58:46.708412 arm64_fp-stress_FPSIMD-3-1 pass
11855 23:58:46.711183 arm64_fp-stress_FPSIMD-4-0 pass
11856 23:58:46.714453 arm64_fp-stress_FPSIMD-4-1 pass
11857 23:58:46.718105 arm64_fp-stress_FPSIMD-5-0 pass
11858 23:58:46.721382 arm64_fp-stress_FPSIMD-5-1 pass
11859 23:58:46.721800 arm64_fp-stress_FPSIMD-6-0 pass
11860 23:58:46.724434 arm64_fp-stress_FPSIMD-6-1 pass
11861 23:58:46.727897 arm64_fp-stress_FPSIMD-7-0 pass
11862 23:58:46.730707 arm64_fp-stress_FPSIMD-7-1 pass
11863 23:58:46.734337 arm64_fp-stress pass
11864 23:58:46.737394 arm64_sve-ptrace_SVE_not_available skip
11865 23:58:46.737812 arm64_sve-ptrace skip
11866 23:58:46.744029 arm64_sve-probe-vls_SVE_not_available skip
11867 23:58:46.744552 arm64_sve-probe-vls skip
11868 23:58:46.747102 arm64_vec-syscfg_SVE_not_supported skip
11869 23:58:46.750573 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11870 23:58:46.757565 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11871 23:58:46.760755 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11872 23:58:46.763416 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11873 23:58:46.767818 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11874 23:58:46.773817 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11875 23:58:46.776820 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11876 23:58:46.780949 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11877 23:58:46.783291 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11878 23:58:46.786879 arm64_vec-syscfg_SME_not_supported skip
11879 23:58:46.793126 arm64_vec-syscfg_SME_not_supported_dup2 skip
11880 23:58:46.796913 arm64_vec-syscfg_SME_not_supported_dup3 skip
11881 23:58:46.800013 arm64_vec-syscfg_SME_not_supported_dup4 skip
11882 23:58:46.803156 arm64_vec-syscfg_SME_not_supported_dup5 skip
11883 23:58:46.806803 arm64_vec-syscfg_SME_not_supported_dup6 skip
11884 23:58:46.812919 arm64_vec-syscfg_SME_not_supported_dup7 skip
11885 23:58:46.816518 arm64_vec-syscfg_SME_not_supported_dup8 skip
11886 23:58:46.819708 arm64_vec-syscfg_SME_not_supported_dup9 skip
11887 23:58:46.823262 arm64_vec-syscfg_SME_not_supported_dup10 skip
11888 23:58:46.826690 arm64_vec-syscfg pass
11889 23:58:46.829523 arm64_za-fork_skipped pass
11890 23:58:46.829938 arm64_za-fork pass
11891 23:58:46.833114 arm64_za-ptrace_SME_not_available skip
11892 23:58:46.836047 arm64_za-ptrace skip
11893 23:58:46.838979 arm64_check_buffer_fill skip
11894 23:58:46.839393 arm64_check_child_memory skip
11895 23:58:46.842967 arm64_check_gcr_el1_cswitch skip
11896 23:58:46.846144 arm64_check_ksm_options skip
11897 23:58:46.848902 arm64_check_mmap_options skip
11898 23:58:46.852442 arm64_check_prctl_check_basic_read pass
11899 23:58:46.855430 arm64_check_prctl_NONE pass
11900 23:58:46.858682 arm64_check_prctl_SYNC skip
11901 23:58:46.859094 arm64_check_prctl_ASYNC skip
11902 23:58:46.862004 arm64_check_prctl_SYNC_ASYNC skip
11903 23:58:46.865987 arm64_check_prctl pass
11904 23:58:46.869004 arm64_check_tags_inclusion skip
11905 23:58:46.869549 arm64_check_user_mem skip
11906 23:58:46.875569 arm64_btitest_nohint_func_call_using_br_x0 skip
11907 23:58:46.879219 arm64_btitest_nohint_func_call_using_br_x16 skip
11908 23:58:46.881974 arm64_btitest_nohint_func_call_using_blr skip
11909 23:58:46.888954 arm64_btitest_bti_none_func_call_using_br_x0 skip
11910 23:58:46.892226 arm64_btitest_bti_none_func_call_using_br_x16 skip
11911 23:58:46.895434 arm64_btitest_bti_none_func_call_using_blr skip
11912 23:58:46.901600 arm64_btitest_bti_c_func_call_using_br_x0 skip
11913 23:58:46.904910 arm64_btitest_bti_c_func_call_using_br_x16 skip
11914 23:58:46.908085 arm64_btitest_bti_c_func_call_using_blr skip
11915 23:58:46.911773 arm64_btitest_bti_j_func_call_using_br_x0 skip
11916 23:58:46.918425 arm64_btitest_bti_j_func_call_using_br_x16 skip
11917 23:58:46.921466 arm64_btitest_bti_j_func_call_using_blr skip
11918 23:58:46.924982 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11919 23:58:46.927902 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11920 23:58:46.934453 arm64_btitest_bti_jc_func_call_using_blr skip
11921 23:58:46.937979 arm64_btitest_paciasp_func_call_using_br_x0 skip
11922 23:58:46.941127 arm64_btitest_paciasp_func_call_using_br_x16 skip
11923 23:58:46.948166 arm64_btitest_paciasp_func_call_using_blr skip
11924 23:58:46.948586 arm64_btitest pass
11925 23:58:46.954477 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11926 23:58:46.958432 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11927 23:58:46.960820 arm64_nobtitest_nohint_func_call_using_blr skip
11928 23:58:46.967356 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11929 23:58:46.970749 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11930 23:58:46.974152 arm64_nobtitest_bti_none_func_call_using_blr skip
11931 23:58:46.980932 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11932 23:58:46.983961 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11933 23:58:46.988019 arm64_nobtitest_bti_c_func_call_using_blr skip
11934 23:58:46.994036 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11935 23:58:46.997060 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11936 23:58:47.000732 arm64_nobtitest_bti_j_func_call_using_blr skip
11937 23:58:47.007078 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11938 23:58:47.010198 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11939 23:58:47.013391 arm64_nobtitest_bti_jc_func_call_using_blr skip
11940 23:58:47.020488 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11941 23:58:47.023422 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11942 23:58:47.026611 arm64_nobtitest_paciasp_func_call_using_blr skip
11943 23:58:47.029876 arm64_nobtitest pass
11944 23:58:47.033176 arm64_hwcap_cpuinfo_match_RNG pass
11945 23:58:47.036713 arm64_hwcap_sigill_RNG skip
11946 23:58:47.040017 arm64_hwcap_cpuinfo_match_SME pass
11947 23:58:47.040433 arm64_hwcap_sigill_SME pass
11948 23:58:47.043080 arm64_hwcap_cpuinfo_match_SVE pass
11949 23:58:47.046430 arm64_hwcap_sigill_SVE pass
11950 23:58:47.050366 arm64_hwcap_cpuinfo_match_SVE_2 pass
11951 23:58:47.053126 arm64_hwcap_sigill_SVE_2 skip
11952 23:58:47.056274 arm64_hwcap_cpuinfo_match_SVE_AES pass
11953 23:58:47.059411 arm64_hwcap_sigill_SVE_AES skip
11954 23:58:47.063025 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11955 23:58:47.066514 arm64_hwcap_sigill_SVE2_PMULL skip
11956 23:58:47.069636 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11957 23:58:47.073221 arm64_hwcap_sigill_SVE2_BITPERM skip
11958 23:58:47.075930 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11959 23:58:47.079456 arm64_hwcap_sigill_SVE2_SHA3 skip
11960 23:58:47.082609 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11961 23:58:47.085851 arm64_hwcap_sigill_SVE2_SM4 skip
11962 23:58:47.088938 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11963 23:58:47.093222 arm64_hwcap_sigill_SVE2_I8MM skip
11964 23:58:47.095515 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11965 23:58:47.098912 arm64_hwcap_sigill_SVE2_F32MM skip
11966 23:58:47.102378 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11967 23:58:47.105962 arm64_hwcap_sigill_SVE2_F64MM skip
11968 23:58:47.108925 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11969 23:58:47.112037 arm64_hwcap_sigill_SVE2_BF16 skip
11970 23:58:47.115275 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11971 23:58:47.118557 arm64_hwcap_sigill_SVE2_EBF16 skip
11972 23:58:47.122174 arm64_hwcap pass
11973 23:58:47.125282 arm64_ptrace_read_tpidr_one pass
11974 23:58:47.128623 arm64_ptrace_write_tpidr_one pass
11975 23:58:47.132128 arm64_ptrace_verify_tpidr_one pass
11976 23:58:47.132554 arm64_ptrace_count_tpidrs pass
11977 23:58:47.135161 arm64_ptrace_tpidr2_write pass
11978 23:58:47.139093 arm64_ptrace_tpidr2_read pass
11979 23:58:47.141995 arm64_ptrace_write_tpidr_only pass
11980 23:58:47.145101 arm64_ptrace pass
11981 23:58:47.148817 arm64_syscall-abi_getpid_FPSIMD pass
11982 23:58:47.152090 arm64_syscall-abi_sched_yield_FPSIMD pass
11983 23:58:47.152506 arm64_syscall-abi pass
11984 23:58:47.158837 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11985 23:58:47.161779 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11986 23:58:47.165854 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11987 23:58:47.171645 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11988 23:58:47.175088 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11989 23:58:47.178770 arm64_tpidr2 pass
11990 23:58:47.181846 + ../../utils/send-to-lava.sh ./output/result.txt
11991 23:58:47.188059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11992 23:58:47.188821 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11994 23:58:47.191457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11995 23:58:47.192204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11997 23:58:47.197714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11998 23:58:47.198578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12000 23:58:47.205488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12002 23:58:47.207706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12003 23:58:47.276778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12004 23:58:47.277706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12006 23:58:47.343991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12007 23:58:47.344702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12009 23:58:47.408238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12010 23:58:47.409176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12012 23:58:47.474933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12013 23:58:47.475663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12015 23:58:47.541070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12016 23:58:47.541872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12018 23:58:47.611673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12019 23:58:47.612454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12021 23:58:47.681748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12022 23:58:47.682436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12024 23:58:47.749018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12025 23:58:47.749767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12027 23:58:47.817917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12028 23:58:47.818746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12030 23:58:47.887533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12031 23:58:47.888251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12033 23:58:47.958633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12034 23:58:47.959328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12036 23:58:48.026032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12037 23:58:48.026795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12039 23:58:48.095926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12040 23:58:48.096692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12042 23:58:48.162186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12043 23:58:48.163009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12045 23:58:48.230260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12046 23:58:48.230947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12048 23:58:48.289543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12049 23:58:48.290257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12051 23:58:48.354268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12053 23:58:48.357006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12054 23:58:48.419030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12055 23:58:48.419732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12057 23:58:48.479063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12058 23:58:48.480022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12060 23:58:48.542494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12061 23:58:48.543435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12063 23:58:48.607903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12064 23:58:48.608630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12066 23:58:48.675437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12067 23:58:48.676197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12069 23:58:48.743041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12070 23:58:48.743749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12072 23:58:48.811383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12073 23:58:48.812117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12075 23:58:48.878078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12077 23:58:48.881585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12078 23:58:48.944077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12079 23:58:48.944759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12081 23:58:49.011035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12082 23:58:49.011787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12084 23:58:49.076986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12085 23:58:49.077833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12087 23:58:49.143833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12088 23:58:49.144524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12090 23:58:49.211116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12091 23:58:49.211803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12093 23:58:49.278991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12094 23:58:49.279676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12096 23:58:49.342954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12097 23:58:49.343706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12099 23:58:49.408978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12100 23:58:49.409806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12102 23:58:49.477234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12103 23:58:49.478043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12105 23:58:49.544945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12106 23:58:49.545808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12108 23:58:49.612097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12109 23:58:49.612811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12111 23:58:49.679749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12112 23:58:49.680564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12114 23:58:49.748460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12116 23:58:49.751317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12117 23:58:49.816790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12118 23:58:49.817498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12120 23:58:49.881676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12121 23:58:49.882459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12123 23:58:49.944990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12124 23:58:49.945739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12126 23:58:50.009803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12127 23:58:50.010520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12129 23:58:50.075813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12130 23:58:50.076672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12132 23:58:50.138134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12133 23:58:50.138855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12135 23:58:50.202909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12136 23:58:50.203601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12138 23:58:50.274341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12139 23:58:50.275045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12141 23:58:50.341110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12142 23:58:50.341874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12144 23:58:50.413789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12145 23:58:50.414522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12147 23:58:50.480599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12148 23:58:50.481404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12150 23:58:50.547422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12151 23:58:50.548144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12153 23:58:50.610441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12154 23:58:50.611158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12156 23:58:50.678802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12157 23:58:50.679523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12159 23:58:50.738512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12160 23:58:50.739361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12162 23:58:50.807655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12163 23:58:50.808443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12165 23:58:50.876305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12166 23:58:50.877072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12168 23:58:50.938047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12169 23:58:50.938770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12171 23:58:51.003506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12172 23:58:51.004247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12174 23:58:51.068426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12175 23:58:51.069221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12177 23:58:51.131452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12178 23:58:51.132212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12180 23:58:51.193592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12181 23:58:51.194299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12183 23:58:51.260098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12184 23:58:51.260808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12186 23:58:51.326804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12187 23:58:51.327510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12189 23:58:51.392600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12190 23:58:51.393353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12192 23:58:51.456098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12193 23:58:51.456829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12195 23:58:51.520464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12196 23:58:51.521156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12198 23:58:51.585704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12199 23:58:51.586583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12201 23:58:51.652373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12202 23:58:51.653078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12204 23:58:51.718331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12205 23:58:51.719085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12207 23:58:51.786564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12208 23:58:51.787353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12210 23:58:51.856472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12211 23:58:51.857220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12213 23:58:51.923076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12214 23:58:51.923929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12216 23:58:51.992292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12217 23:58:51.992992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12219 23:58:52.057021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12220 23:58:52.057747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12222 23:58:52.120990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12223 23:58:52.121734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12225 23:58:52.188987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12226 23:58:52.189849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12228 23:58:52.259902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12229 23:58:52.260778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12231 23:58:52.331038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12232 23:58:52.331778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12234 23:58:52.394532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12235 23:58:52.395225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12237 23:58:52.460016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12238 23:58:52.460727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12240 23:58:52.528412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12241 23:58:52.529171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12243 23:58:52.602745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12245 23:58:52.605776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12246 23:58:52.673303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12247 23:58:52.674025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12249 23:58:52.744488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12250 23:58:52.745198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12252 23:58:52.815994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12253 23:58:52.816696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12255 23:58:52.877200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12256 23:58:52.877991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12258 23:58:52.940366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12259 23:58:52.941070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12261 23:58:53.007654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12262 23:58:53.008499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12264 23:58:53.076262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12266 23:58:53.079147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12267 23:58:53.143681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12268 23:58:53.144384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12270 23:58:53.208396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12271 23:58:53.209117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12273 23:58:53.275875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12274 23:58:53.276591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12276 23:58:53.342647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12277 23:58:53.343348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12279 23:58:53.409657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12280 23:58:53.410401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12282 23:58:53.479155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12283 23:58:53.479853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12285 23:58:53.546684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12286 23:58:53.547552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12288 23:58:53.613483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12289 23:58:53.614185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12291 23:58:53.675398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12292 23:58:53.676103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12294 23:58:53.742916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12295 23:58:53.743650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12297 23:58:53.809781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12298 23:58:53.810536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12300 23:58:53.876868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12301 23:58:53.877593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12303 23:58:53.942549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12304 23:58:53.943241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12306 23:58:54.008474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12307 23:58:54.009163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12309 23:58:54.075672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12310 23:58:54.076355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12312 23:58:54.145919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12313 23:58:54.146612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12315 23:58:54.211398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12316 23:58:54.212197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12318 23:58:54.278973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12319 23:58:54.279798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12321 23:58:54.345590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12322 23:58:54.346319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12324 23:58:54.411573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12325 23:58:54.412273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12327 23:58:54.478563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12328 23:58:54.479268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12330 23:58:54.543013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12331 23:58:54.543733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12333 23:58:54.608862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12334 23:58:54.609586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12336 23:58:54.674666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12337 23:58:54.675347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12339 23:58:54.740095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12340 23:58:54.740832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12342 23:58:54.805949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12343 23:58:54.806670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12345 23:58:54.871133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12346 23:58:54.871844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12348 23:58:54.938536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12349 23:58:54.939251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12351 23:58:55.004770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12352 23:58:55.005565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12354 23:58:55.072478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12355 23:58:55.073194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12357 23:58:55.137366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12358 23:58:55.138103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12360 23:58:55.204281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12361 23:58:55.205019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12363 23:58:55.272309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12364 23:58:55.273048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12366 23:58:55.338406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12367 23:58:55.339118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12369 23:58:55.404060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12370 23:58:55.404746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12372 23:58:55.467648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12373 23:58:55.468337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12375 23:58:55.534683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12376 23:58:55.535393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12378 23:58:55.600624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12379 23:58:55.601412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12381 23:58:55.670812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12382 23:58:55.671576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12384 23:58:55.738636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12385 23:58:55.739399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12387 23:58:55.799854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12388 23:58:55.800556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12390 23:58:55.867287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12391 23:58:55.867995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12393 23:58:55.931821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12394 23:58:55.932530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12396 23:58:56.002024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12397 23:58:56.002787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12399 23:58:56.064825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12400 23:58:56.065638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12402 23:58:56.136136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12403 23:58:56.136992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12405 23:58:56.197397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12406 23:58:56.198144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12408 23:58:56.266803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12409 23:58:56.267574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12411 23:58:56.329962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12412 23:58:56.330811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12414 23:58:56.403270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12415 23:58:56.404039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12417 23:58:56.473660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12418 23:58:56.474414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12420 23:58:56.548498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12421 23:58:56.549362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12423 23:58:56.620721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12424 23:58:56.621495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12426 23:58:56.690942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12427 23:58:56.691658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12429 23:58:56.757869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12430 23:58:56.758625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12432 23:58:56.828265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12433 23:58:56.829024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12435 23:58:56.891835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12437 23:58:56.894748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12438 23:58:56.960434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12439 23:58:56.961178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12441 23:58:57.020379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12443 23:58:57.023151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12444 23:58:57.091658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12445 23:58:57.092418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12447 23:58:57.157192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12449 23:58:57.160043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12450 23:58:57.228609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12451 23:58:57.229342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12453 23:58:57.298952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12454 23:58:57.299724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12456 23:58:57.366798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12457 23:58:57.367632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12459 23:58:57.429428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12460 23:58:57.430170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12462 23:58:57.492651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12463 23:58:57.493402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12465 23:58:57.552873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12467 23:58:57.555891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12468 23:58:57.619219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12469 23:58:57.619904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12471 23:58:57.687650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12472 23:58:57.688427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12474 23:58:57.754443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12475 23:58:57.755137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12477 23:58:57.821200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12479 23:58:57.824361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12480 23:58:57.885054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12482 23:58:57.887268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12483 23:58:57.953312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12484 23:58:57.954010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12486 23:58:58.018193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12487 23:58:58.018887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12489 23:58:58.083061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12490 23:58:58.083738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12492 23:58:58.151712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12493 23:58:58.152404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12495 23:58:58.221777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12496 23:58:58.222680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12498 23:58:58.295188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12499 23:58:58.295961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12501 23:58:58.366211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12502 23:58:58.366915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12504 23:58:58.431933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12505 23:58:58.432701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12507 23:58:58.494744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12508 23:58:58.495440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12510 23:58:58.565173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12511 23:58:58.566079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12513 23:58:58.631502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12514 23:58:58.632228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12516 23:58:58.698120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12517 23:58:58.698870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12519 23:58:58.764524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12520 23:58:58.765248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12522 23:58:58.829941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12523 23:58:58.830645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12525 23:58:58.890962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12526 23:58:58.891520 + set +x
12527 23:58:58.892125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12529 23:58:58.897427 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14084381_1.6.2.3.5>
12530 23:58:58.898193 Received signal: <ENDRUN> 1_kselftest-arm64 14084381_1.6.2.3.5
12531 23:58:58.898557 Ending use of test pattern.
12532 23:58:58.898867 Ending test lava.1_kselftest-arm64 (14084381_1.6.2.3.5), duration 37.21
12534 23:58:58.900705 <LAVA_TEST_RUNNER EXIT>
12535 23:58:58.901377 ok: lava_test_shell seems to have completed
12536 23:58:58.906924 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12537 23:58:58.907685 end: 3.1 lava-test-shell (duration 00:00:38) [common]
12538 23:58:58.908113 end: 3 lava-test-retry (duration 00:00:38) [common]
12539 23:58:58.908649 start: 4 finalize (timeout 00:06:57) [common]
12540 23:58:58.909249 start: 4.1 power-off (timeout 00:00:30) [common]
12541 23:58:58.910031 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
12542 23:58:59.162995 >> Command sent successfully.
12543 23:58:59.172923 Returned 0 in 0 seconds
12544 23:58:59.274334 end: 4.1 power-off (duration 00:00:00) [common]
12546 23:58:59.275928 start: 4.2 read-feedback (timeout 00:06:57) [common]
12547 23:58:59.277421 Listened to connection for namespace 'common' for up to 1s
12548 23:59:00.277722 Finalising connection for namespace 'common'
12549 23:59:00.278462 Disconnecting from shell: Finalise
12550 23:59:00.278924 / #
12551 23:59:00.379942 end: 4.2 read-feedback (duration 00:00:01) [common]
12552 23:59:00.380729 end: 4 finalize (duration 00:00:01) [common]
12553 23:59:00.381397 Cleaning after the job
12554 23:59:00.381949 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/ramdisk
12555 23:59:00.392023 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/kernel
12556 23:59:00.426228 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/dtb
12557 23:59:00.426586 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/nfsrootfs
12558 23:59:00.496010 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084381/tftp-deploy-y63n22rm/modules
12559 23:59:00.501555 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084381
12560 23:59:01.059842 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084381
12561 23:59:01.060042 Job finished correctly