Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:48:53.286105 lava-dispatcher, installed at version: 2024.03
2 23:48:53.286331 start: 0 validate
3 23:48:53.286468 Start time: 2024-05-29 23:48:53.286461+00:00 (UTC)
4 23:48:53.286601 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:48:53.286735 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:48:53.546751 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:48:53.546932 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:48:53.806201 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:48:53.806360 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:48:54.071916 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:48:54.072107 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:48:54.600251 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:48:54.600437 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:48:54.861117 validate duration: 1.57
16 23:48:54.861455 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:48:54.861561 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:48:54.861646 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:48:54.861771 Not decompressing ramdisk as can be used compressed.
20 23:48:54.861854 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:48:54.861923 saving as /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/ramdisk/initrd.cpio.gz
22 23:48:54.861989 total size: 5628169 (5 MB)
23 23:48:54.863095 progress 0 % (0 MB)
24 23:48:54.864763 progress 5 % (0 MB)
25 23:48:54.866376 progress 10 % (0 MB)
26 23:48:54.867854 progress 15 % (0 MB)
27 23:48:54.869474 progress 20 % (1 MB)
28 23:48:54.870895 progress 25 % (1 MB)
29 23:48:54.872508 progress 30 % (1 MB)
30 23:48:54.874088 progress 35 % (1 MB)
31 23:48:54.875467 progress 40 % (2 MB)
32 23:48:54.877061 progress 45 % (2 MB)
33 23:48:54.878429 progress 50 % (2 MB)
34 23:48:54.879955 progress 55 % (2 MB)
35 23:48:54.881531 progress 60 % (3 MB)
36 23:48:54.882897 progress 65 % (3 MB)
37 23:48:54.884434 progress 70 % (3 MB)
38 23:48:54.885835 progress 75 % (4 MB)
39 23:48:54.887357 progress 80 % (4 MB)
40 23:48:54.888762 progress 85 % (4 MB)
41 23:48:54.890296 progress 90 % (4 MB)
42 23:48:54.891817 progress 95 % (5 MB)
43 23:48:54.893248 progress 100 % (5 MB)
44 23:48:54.893590 5 MB downloaded in 0.03 s (169.86 MB/s)
45 23:48:54.893786 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:48:54.894158 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:48:54.894247 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:48:54.894333 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:48:54.894468 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:48:54.894539 saving as /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/kernel/Image
52 23:48:54.894601 total size: 54682112 (52 MB)
53 23:48:54.894664 No compression specified
54 23:48:54.895823 progress 0 % (0 MB)
55 23:48:54.909789 progress 5 % (2 MB)
56 23:48:54.923597 progress 10 % (5 MB)
57 23:48:54.937601 progress 15 % (7 MB)
58 23:48:54.951409 progress 20 % (10 MB)
59 23:48:54.965487 progress 25 % (13 MB)
60 23:48:54.979380 progress 30 % (15 MB)
61 23:48:54.993500 progress 35 % (18 MB)
62 23:48:55.007213 progress 40 % (20 MB)
63 23:48:55.021000 progress 45 % (23 MB)
64 23:48:55.034871 progress 50 % (26 MB)
65 23:48:55.048742 progress 55 % (28 MB)
66 23:48:55.062725 progress 60 % (31 MB)
67 23:48:55.076634 progress 65 % (33 MB)
68 23:48:55.090666 progress 70 % (36 MB)
69 23:48:55.104547 progress 75 % (39 MB)
70 23:48:55.118420 progress 80 % (41 MB)
71 23:48:55.132156 progress 85 % (44 MB)
72 23:48:55.145800 progress 90 % (46 MB)
73 23:48:55.159693 progress 95 % (49 MB)
74 23:48:55.173268 progress 100 % (52 MB)
75 23:48:55.173533 52 MB downloaded in 0.28 s (186.96 MB/s)
76 23:48:55.173690 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:48:55.173929 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:48:55.174015 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:48:55.174100 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:48:55.174238 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:48:55.174313 saving as /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/dtb/mt8192-asurada-spherion-r0.dtb
83 23:48:55.174374 total size: 47258 (0 MB)
84 23:48:55.174435 No compression specified
85 23:48:55.175605 progress 69 % (0 MB)
86 23:48:55.175905 progress 100 % (0 MB)
87 23:48:55.176063 0 MB downloaded in 0.00 s (26.73 MB/s)
88 23:48:55.176185 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:48:55.176407 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:48:55.176493 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:48:55.176602 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:48:55.176728 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:48:55.176797 saving as /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/nfsrootfs/full.rootfs.tar
95 23:48:55.176858 total size: 120894716 (115 MB)
96 23:48:55.176920 Using unxz to decompress xz
97 23:48:55.181079 progress 0 % (0 MB)
98 23:48:55.523641 progress 5 % (5 MB)
99 23:48:55.877309 progress 10 % (11 MB)
100 23:48:56.224390 progress 15 % (17 MB)
101 23:48:56.548076 progress 20 % (23 MB)
102 23:48:56.841196 progress 25 % (28 MB)
103 23:48:57.208894 progress 30 % (34 MB)
104 23:48:57.543682 progress 35 % (40 MB)
105 23:48:57.707390 progress 40 % (46 MB)
106 23:48:57.884595 progress 45 % (51 MB)
107 23:48:58.195232 progress 50 % (57 MB)
108 23:48:58.566102 progress 55 % (63 MB)
109 23:48:58.910027 progress 60 % (69 MB)
110 23:48:59.255065 progress 65 % (74 MB)
111 23:48:59.593974 progress 70 % (80 MB)
112 23:48:59.944846 progress 75 % (86 MB)
113 23:49:00.285405 progress 80 % (92 MB)
114 23:49:00.617414 progress 85 % (98 MB)
115 23:49:00.965952 progress 90 % (103 MB)
116 23:49:01.305625 progress 95 % (109 MB)
117 23:49:01.673240 progress 100 % (115 MB)
118 23:49:01.678684 115 MB downloaded in 6.50 s (17.73 MB/s)
119 23:49:01.678944 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:49:01.679207 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:49:01.679299 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:49:01.679384 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:49:01.679532 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:49:01.679603 saving as /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/modules/modules.tar
126 23:49:01.679664 total size: 8601444 (8 MB)
127 23:49:01.679728 Using unxz to decompress xz
128 23:49:01.684027 progress 0 % (0 MB)
129 23:49:01.705368 progress 5 % (0 MB)
130 23:49:01.730614 progress 10 % (0 MB)
131 23:49:01.756931 progress 15 % (1 MB)
132 23:49:01.783501 progress 20 % (1 MB)
133 23:49:01.811032 progress 25 % (2 MB)
134 23:49:01.837658 progress 30 % (2 MB)
135 23:49:01.863074 progress 35 % (2 MB)
136 23:49:01.889293 progress 40 % (3 MB)
137 23:49:01.917720 progress 45 % (3 MB)
138 23:49:01.942641 progress 50 % (4 MB)
139 23:49:01.969187 progress 55 % (4 MB)
140 23:49:01.994765 progress 60 % (4 MB)
141 23:49:02.019108 progress 65 % (5 MB)
142 23:49:02.046676 progress 70 % (5 MB)
143 23:49:02.072304 progress 75 % (6 MB)
144 23:49:02.097724 progress 80 % (6 MB)
145 23:49:02.125525 progress 85 % (7 MB)
146 23:49:02.150887 progress 90 % (7 MB)
147 23:49:02.182983 progress 95 % (7 MB)
148 23:49:02.213184 progress 100 % (8 MB)
149 23:49:02.218925 8 MB downloaded in 0.54 s (15.21 MB/s)
150 23:49:02.219178 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:49:02.219440 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:49:02.219534 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 23:49:02.219631 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 23:49:05.670833 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte
156 23:49:05.671043 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 23:49:05.671191 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 23:49:05.671420 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u
159 23:49:05.671604 makedir: /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin
160 23:49:05.671747 makedir: /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/tests
161 23:49:05.671885 makedir: /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/results
162 23:49:05.672027 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-add-keys
163 23:49:05.672250 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-add-sources
164 23:49:05.672437 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-background-process-start
165 23:49:05.672654 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-background-process-stop
166 23:49:05.672784 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-common-functions
167 23:49:05.672909 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-echo-ipv4
168 23:49:05.673041 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-install-packages
169 23:49:05.673162 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-installed-packages
170 23:49:05.673282 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-os-build
171 23:49:05.673405 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-probe-channel
172 23:49:05.673525 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-probe-ip
173 23:49:05.673645 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-target-ip
174 23:49:05.673764 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-target-mac
175 23:49:05.673883 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-target-storage
176 23:49:05.674004 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-case
177 23:49:05.674125 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-event
178 23:49:05.674244 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-feedback
179 23:49:05.674362 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-raise
180 23:49:05.674481 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-reference
181 23:49:05.674600 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-runner
182 23:49:05.674718 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-set
183 23:49:05.674840 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-test-shell
184 23:49:05.674964 Updating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-add-keys (debian)
185 23:49:05.675111 Updating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-add-sources (debian)
186 23:49:05.675244 Updating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-install-packages (debian)
187 23:49:05.675376 Updating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-installed-packages (debian)
188 23:49:05.675506 Updating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/bin/lava-os-build (debian)
189 23:49:05.675621 Creating /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/environment
190 23:49:05.675712 LAVA metadata
191 23:49:05.675774 - LAVA_JOB_ID=14084321
192 23:49:05.675836 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:49:05.675943 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 23:49:05.676008 skipped lava-vland-overlay
195 23:49:05.676079 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:49:05.676155 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 23:49:05.676213 skipped lava-multinode-overlay
198 23:49:05.676280 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:49:05.676365 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 23:49:05.676436 Loading test definitions
201 23:49:05.676520 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 23:49:05.676735 Using /lava-14084321 at stage 0
203 23:49:05.677013 uuid=14084321_1.6.2.3.1 testdef=None
204 23:49:05.677099 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:49:05.677180 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 23:49:05.677620 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:49:05.677836 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 23:49:05.678362 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:49:05.678585 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 23:49:05.679120 runner path: /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/0/tests/0_timesync-off test_uuid 14084321_1.6.2.3.1
213 23:49:05.679325 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:49:05.679547 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 23:49:05.679618 Using /lava-14084321 at stage 0
217 23:49:05.679712 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:49:05.679796 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/0/tests/1_kselftest-dt'
219 23:49:07.667913 Running '/usr/bin/git checkout kernelci.org
220 23:49:07.815422 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 23:49:07.816193 uuid=14084321_1.6.2.3.5 testdef=None
222 23:49:07.816357 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 23:49:07.816738 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 23:49:07.817487 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:49:07.817725 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 23:49:07.818876 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:49:07.819279 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 23:49:07.820747 runner path: /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/0/tests/1_kselftest-dt test_uuid 14084321_1.6.2.3.5
232 23:49:07.820838 BOARD='mt8192-asurada-spherion-r0'
233 23:49:07.820903 BRANCH='cip-gitlab'
234 23:49:07.820971 SKIPFILE='/dev/null'
235 23:49:07.821059 SKIP_INSTALL='True'
236 23:49:07.821144 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:49:07.821233 TST_CASENAME=''
238 23:49:07.821319 TST_CMDFILES='dt'
239 23:49:07.821484 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:49:07.821698 Creating lava-test-runner.conf files
242 23:49:07.821762 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084321/lava-overlay-pj2gl26u/lava-14084321/0 for stage 0
243 23:49:07.821857 - 0_timesync-off
244 23:49:07.821926 - 1_kselftest-dt
245 23:49:07.822024 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 23:49:07.822112 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 23:49:15.489599 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:49:15.489756 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 23:49:15.489856 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:49:15.489959 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:49:15.490051 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 23:49:15.657559 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:49:15.657933 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 23:49:15.658047 extracting modules file /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte
255 23:49:15.923836 extracting modules file /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084321/extract-overlay-ramdisk-imao_6ga/ramdisk
256 23:49:16.158775 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 23:49:16.158966 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 23:49:16.159064 [common] Applying overlay to NFS
259 23:49:16.159134 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084321/compress-overlay-xbmru4dd/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte
260 23:49:17.098859 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:49:17.099034 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 23:49:17.099131 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:49:17.099225 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 23:49:17.099309 Building ramdisk /var/lib/lava/dispatcher/tmp/14084321/extract-overlay-ramdisk-imao_6ga/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084321/extract-overlay-ramdisk-imao_6ga/ramdisk
265 23:49:17.444875 >> 130335 blocks
266 23:49:19.493856 rename /var/lib/lava/dispatcher/tmp/14084321/extract-overlay-ramdisk-imao_6ga/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/ramdisk/ramdisk.cpio.gz
267 23:49:19.494305 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:49:19.494429 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 23:49:19.494532 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 23:49:19.494634 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/kernel/Image']
271 23:49:32.692295 Returned 0 in 13 seconds
272 23:49:32.793278 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/kernel/image.itb
273 23:49:33.182303 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:49:33.182672 output: Created: Thu May 30 00:49:33 2024
275 23:49:33.182746 output: Image 0 (kernel-1)
276 23:49:33.182813 output: Description:
277 23:49:33.182882 output: Created: Thu May 30 00:49:33 2024
278 23:49:33.182946 output: Type: Kernel Image
279 23:49:33.183007 output: Compression: lzma compressed
280 23:49:33.183068 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
281 23:49:33.183128 output: Architecture: AArch64
282 23:49:33.183214 output: OS: Linux
283 23:49:33.183274 output: Load Address: 0x00000000
284 23:49:33.183335 output: Entry Point: 0x00000000
285 23:49:33.183398 output: Hash algo: crc32
286 23:49:33.183457 output: Hash value: 907bf91d
287 23:49:33.183513 output: Image 1 (fdt-1)
288 23:49:33.183568 output: Description: mt8192-asurada-spherion-r0
289 23:49:33.183622 output: Created: Thu May 30 00:49:33 2024
290 23:49:33.183676 output: Type: Flat Device Tree
291 23:49:33.183732 output: Compression: uncompressed
292 23:49:33.183785 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:49:33.183839 output: Architecture: AArch64
294 23:49:33.183894 output: Hash algo: crc32
295 23:49:33.183948 output: Hash value: 0f8e4d2e
296 23:49:33.184001 output: Image 2 (ramdisk-1)
297 23:49:33.184054 output: Description: unavailable
298 23:49:33.184107 output: Created: Thu May 30 00:49:33 2024
299 23:49:33.184160 output: Type: RAMDisk Image
300 23:49:33.184213 output: Compression: Unknown Compression
301 23:49:33.184266 output: Data Size: 18728275 Bytes = 18289.33 KiB = 17.86 MiB
302 23:49:33.184319 output: Architecture: AArch64
303 23:49:33.184373 output: OS: Linux
304 23:49:33.184430 output: Load Address: unavailable
305 23:49:33.184514 output: Entry Point: unavailable
306 23:49:33.184615 output: Hash algo: crc32
307 23:49:33.184683 output: Hash value: 7cb6843c
308 23:49:33.184737 output: Default Configuration: 'conf-1'
309 23:49:33.184791 output: Configuration 0 (conf-1)
310 23:49:33.184843 output: Description: mt8192-asurada-spherion-r0
311 23:49:33.184897 output: Kernel: kernel-1
312 23:49:33.184952 output: Init Ramdisk: ramdisk-1
313 23:49:33.185006 output: FDT: fdt-1
314 23:49:33.185058 output: Loadables: kernel-1
315 23:49:33.185111 output:
316 23:49:33.185313 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:49:33.185414 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:49:33.185521 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:49:33.185614 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 23:49:33.185693 No LXC device requested
321 23:49:33.185772 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:49:33.185857 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 23:49:33.185935 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:49:33.186006 Checking files for TFTP limit of 4294967296 bytes.
325 23:49:33.186508 end: 1 tftp-deploy (duration 00:00:38) [common]
326 23:49:33.186617 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:49:33.186709 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:49:33.186833 substitutions:
329 23:49:33.186900 - {DTB}: 14084321/tftp-deploy-8g3zsbyk/dtb/mt8192-asurada-spherion-r0.dtb
330 23:49:33.186965 - {INITRD}: 14084321/tftp-deploy-8g3zsbyk/ramdisk/ramdisk.cpio.gz
331 23:49:33.187023 - {KERNEL}: 14084321/tftp-deploy-8g3zsbyk/kernel/Image
332 23:49:33.187084 - {LAVA_MAC}: None
333 23:49:33.187141 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte
334 23:49:33.187228 - {NFS_SERVER_IP}: 192.168.201.1
335 23:49:33.187289 - {PRESEED_CONFIG}: None
336 23:49:33.187349 - {PRESEED_LOCAL}: None
337 23:49:33.187424 - {RAMDISK}: 14084321/tftp-deploy-8g3zsbyk/ramdisk/ramdisk.cpio.gz
338 23:49:33.187482 - {ROOT_PART}: None
339 23:49:33.187571 - {ROOT}: None
340 23:49:33.187633 - {SERVER_IP}: 192.168.201.1
341 23:49:33.187689 - {TEE}: None
342 23:49:33.187744 Parsed boot commands:
343 23:49:33.187798 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:49:33.187976 Parsed boot commands: tftpboot 192.168.201.1 14084321/tftp-deploy-8g3zsbyk/kernel/image.itb 14084321/tftp-deploy-8g3zsbyk/kernel/cmdline
345 23:49:33.188065 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:49:33.188151 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:49:33.188241 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:49:33.188329 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:49:33.188401 Not connected, no need to disconnect.
350 23:49:33.188475 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:49:33.188555 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:49:33.188671 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 23:49:33.192377 Setting prompt string to ['lava-test: # ']
354 23:49:33.192783 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:49:33.192895 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:49:33.192996 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:49:33.193086 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:49:33.193285 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
359 23:49:38.337401 >> Command sent successfully.
360 23:49:38.347811 Returned 0 in 5 seconds
361 23:49:38.449048 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:49:38.451176 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:49:38.452015 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:49:38.452507 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:49:38.453069 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:49:38.453722 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:49:38.456484 [Enter `^Ec?' for help]
369 23:49:38.613977
370 23:49:38.614530
371 23:49:38.614931 F0: 102B 0000
372 23:49:38.615265
373 23:49:38.615662 F3: 1001 0000 [0200]
374 23:49:38.617356
375 23:49:38.617828 F3: 1001 0000
376 23:49:38.618180
377 23:49:38.618526 F7: 102D 0000
378 23:49:38.618918
379 23:49:38.620455 F1: 0000 0000
380 23:49:38.621035
381 23:49:38.621383 V0: 0000 0000 [0001]
382 23:49:38.621806
383 23:49:38.623785 00: 0007 8000
384 23:49:38.624264
385 23:49:38.624784 01: 0000 0000
386 23:49:38.625148
387 23:49:38.627538 BP: 0C00 0209 [0000]
388 23:49:38.628055
389 23:49:38.628457 G0: 1182 0000
390 23:49:38.628941
391 23:49:38.631256 EC: 0000 0021 [4000]
392 23:49:38.631701
393 23:49:38.632045 S7: 0000 0000 [0000]
394 23:49:38.632394
395 23:49:38.634728 CC: 0000 0000 [0001]
396 23:49:38.635179
397 23:49:38.635523 T0: 0000 0040 [010F]
398 23:49:38.635863
399 23:49:38.636168 Jump to BL
400 23:49:38.636509
401 23:49:38.661079
402 23:49:38.661669
403 23:49:38.668184 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 23:49:38.671320 ARM64: Exception handlers installed.
405 23:49:38.674795 ARM64: Testing exception
406 23:49:38.677901 ARM64: Done test exception
407 23:49:38.684847 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 23:49:38.695664 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 23:49:38.701668 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 23:49:38.711751 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 23:49:38.718430 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 23:49:38.728644 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 23:49:38.739373 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 23:49:38.745894 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 23:49:38.764183 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 23:49:38.767161 WDT: Last reset was cold boot
417 23:49:38.770454 SPI1(PAD0) initialized at 2873684 Hz
418 23:49:38.773778 SPI5(PAD0) initialized at 992727 Hz
419 23:49:38.777286 VBOOT: Loading verstage.
420 23:49:38.784300 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 23:49:38.787027 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 23:49:38.790634 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 23:49:38.793932 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 23:49:38.801487 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 23:49:38.807812 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 23:49:38.818875 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
427 23:49:38.819309
428 23:49:38.819659
429 23:49:38.828923 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 23:49:38.832017 ARM64: Exception handlers installed.
431 23:49:38.835190 ARM64: Testing exception
432 23:49:38.835620 ARM64: Done test exception
433 23:49:38.842121 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 23:49:38.845443 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 23:49:38.860005 Probing TPM: . done!
436 23:49:38.860440 TPM ready after 0 ms
437 23:49:38.866668 Connected to device vid:did:rid of 1ae0:0028:00
438 23:49:38.873085 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 23:49:38.913512 Initialized TPM device CR50 revision 0
440 23:49:38.924902 tlcl_send_startup: Startup return code is 0
441 23:49:38.925106 TPM: setup succeeded
442 23:49:38.936321 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 23:49:38.944960 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 23:49:38.957986 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 23:49:38.966153 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 23:49:38.969488 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 23:49:38.973319 in-header: 03 07 00 00 08 00 00 00
448 23:49:38.976713 in-data: aa e4 47 04 13 02 00 00
449 23:49:38.980570 Chrome EC: UHEPI supported
450 23:49:38.987879 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 23:49:38.991830 in-header: 03 9d 00 00 08 00 00 00
452 23:49:38.995386 in-data: 10 20 20 08 00 00 00 00
453 23:49:38.995473 Phase 1
454 23:49:38.999628 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 23:49:39.006845 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 23:49:39.010295 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 23:49:39.013581 Recovery requested (1009000e)
458 23:49:39.017064 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:49:39.026495 tlcl_extend: response is 0
460 23:49:39.036281 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:49:39.040133 tlcl_extend: response is 0
462 23:49:39.047055 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:49:39.068042 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
464 23:49:39.075647 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:49:39.075766
466 23:49:39.075834
467 23:49:39.083226 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:49:39.086893 ARM64: Exception handlers installed.
469 23:49:39.090704 ARM64: Testing exception
470 23:49:39.090778 ARM64: Done test exception
471 23:49:39.113460 pmic_efuse_setting: Set efuses in 11 msecs
472 23:49:39.116752 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:49:39.120427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:49:39.127862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:49:39.131554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:49:39.135186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:49:39.143043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:49:39.145846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:49:39.149557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:49:39.157067 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:49:39.160467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:49:39.163660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:49:39.170225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:49:39.173851 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:49:39.180458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:49:39.184038 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:49:39.190270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:49:39.197029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:49:39.203671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:49:39.207387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:49:39.213810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:49:39.220744 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:49:39.224739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:49:39.232334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:49:39.235321 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:49:39.242268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:49:39.245892 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:49:39.252824 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:49:39.256177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:49:39.263543 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:49:39.266976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:49:39.270352 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:49:39.276815 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:49:39.280899 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:49:39.288840 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:49:39.292165 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:49:39.295690 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:49:39.303067 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:49:39.306551 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:49:39.313128 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:49:39.316756 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:49:39.319651 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:49:39.326275 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:49:39.330065 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:49:39.333086 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:49:39.340099 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:49:39.343042 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:49:39.346588 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:49:39.349977 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:49:39.356436 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:49:39.359859 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:49:39.362965 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:49:39.366675 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:49:39.376723 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 23:49:39.383077 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:49:39.390180 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:49:39.396787 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:49:39.406516 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:49:39.410099 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:49:39.413069 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:49:39.420159 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:49:39.426610 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x23
533 23:49:39.433600 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:49:39.437037 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
535 23:49:39.439978 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:49:39.450575 [RTC]rtc_get_frequency_meter,154: input=15, output=793
537 23:49:39.453827 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
538 23:49:39.460836 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
539 23:49:39.463955 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
540 23:49:39.467512 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
541 23:49:39.470418 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
542 23:49:39.473953 ADC[4]: Raw value=897780 ID=7
543 23:49:39.477370 ADC[3]: Raw value=213440 ID=1
544 23:49:39.477840 RAM Code: 0x71
545 23:49:39.484265 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
546 23:49:39.487414 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
547 23:49:39.497053 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
548 23:49:39.504671 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
549 23:49:39.507520 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
550 23:49:39.517033 in-header: 03 07 00 00 08 00 00 00
551 23:49:39.520547 in-data: aa e4 47 04 13 02 00 00
552 23:49:39.524175 Chrome EC: UHEPI supported
553 23:49:39.531742 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
554 23:49:39.534742 in-header: 03 95 00 00 08 00 00 00
555 23:49:39.539057 in-data: 18 20 20 08 00 00 00 00
556 23:49:39.542398 MRC: failed to locate region type 0.
557 23:49:39.546469 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
558 23:49:39.549900 DRAM-K: Running full calibration
559 23:49:39.557224 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
560 23:49:39.557313 header.status = 0x0
561 23:49:39.560817 header.version = 0x6 (expected: 0x6)
562 23:49:39.564548 header.size = 0xd00 (expected: 0xd00)
563 23:49:39.568521 header.flags = 0x0
564 23:49:39.571404 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
565 23:49:39.591208 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
566 23:49:39.599067 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
567 23:49:39.599224 dram_init: ddr_geometry: 2
568 23:49:39.602866 [EMI] MDL number = 2
569 23:49:39.606020 [EMI] Get MDL freq = 0
570 23:49:39.606196 dram_init: ddr_type: 0
571 23:49:39.609619 is_discrete_lpddr4: 1
572 23:49:39.612910 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
573 23:49:39.613114
574 23:49:39.613290
575 23:49:39.616135 [Bian_co] ETT version 0.0.0.1
576 23:49:39.619500 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
577 23:49:39.619811
578 23:49:39.623200 dramc_set_vcore_voltage set vcore to 650000
579 23:49:39.626772 Read voltage for 800, 4
580 23:49:39.627204 Vio18 = 0
581 23:49:39.627574 Vcore = 650000
582 23:49:39.630847 Vdram = 0
583 23:49:39.631276 Vddq = 0
584 23:49:39.631613 Vmddr = 0
585 23:49:39.634484 dram_init: config_dvfs: 1
586 23:49:39.638600 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
587 23:49:39.645420 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
588 23:49:39.648202 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
589 23:49:39.651588 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
590 23:49:39.655483 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
591 23:49:39.658141 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
592 23:49:39.661921 MEM_TYPE=3, freq_sel=18
593 23:49:39.665227 sv_algorithm_assistance_LP4_1600
594 23:49:39.668143 ============ PULL DRAM RESETB DOWN ============
595 23:49:39.671981 ========== PULL DRAM RESETB DOWN end =========
596 23:49:39.678331 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
597 23:49:39.681466 ===================================
598 23:49:39.681938 LPDDR4 DRAM CONFIGURATION
599 23:49:39.685284 ===================================
600 23:49:39.688271 EX_ROW_EN[0] = 0x0
601 23:49:39.688891 EX_ROW_EN[1] = 0x0
602 23:49:39.691647 LP4Y_EN = 0x0
603 23:49:39.692079 WORK_FSP = 0x0
604 23:49:39.695155 WL = 0x2
605 23:49:39.698518 RL = 0x2
606 23:49:39.698950 BL = 0x2
607 23:49:39.701533 RPST = 0x0
608 23:49:39.701962 RD_PRE = 0x0
609 23:49:39.704985 WR_PRE = 0x1
610 23:49:39.705409 WR_PST = 0x0
611 23:49:39.708537 DBI_WR = 0x0
612 23:49:39.708988 DBI_RD = 0x0
613 23:49:39.711554 OTF = 0x1
614 23:49:39.715454 ===================================
615 23:49:39.718584 ===================================
616 23:49:39.719011 ANA top config
617 23:49:39.722200 ===================================
618 23:49:39.725350 DLL_ASYNC_EN = 0
619 23:49:39.728397 ALL_SLAVE_EN = 1
620 23:49:39.728865 NEW_RANK_MODE = 1
621 23:49:39.731913 DLL_IDLE_MODE = 1
622 23:49:39.735287 LP45_APHY_COMB_EN = 1
623 23:49:39.738585 TX_ODT_DIS = 1
624 23:49:39.739012 NEW_8X_MODE = 1
625 23:49:39.742001 ===================================
626 23:49:39.745421 ===================================
627 23:49:39.748964 data_rate = 1600
628 23:49:39.751793 CKR = 1
629 23:49:39.755079 DQ_P2S_RATIO = 8
630 23:49:39.758699 ===================================
631 23:49:39.761704 CA_P2S_RATIO = 8
632 23:49:39.765249 DQ_CA_OPEN = 0
633 23:49:39.765704 DQ_SEMI_OPEN = 0
634 23:49:39.768888 CA_SEMI_OPEN = 0
635 23:49:39.771738 CA_FULL_RATE = 0
636 23:49:39.775178 DQ_CKDIV4_EN = 1
637 23:49:39.778692 CA_CKDIV4_EN = 1
638 23:49:39.781659 CA_PREDIV_EN = 0
639 23:49:39.782081 PH8_DLY = 0
640 23:49:39.785222 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
641 23:49:39.788497 DQ_AAMCK_DIV = 4
642 23:49:39.791986 CA_AAMCK_DIV = 4
643 23:49:39.794938 CA_ADMCK_DIV = 4
644 23:49:39.795362 DQ_TRACK_CA_EN = 0
645 23:49:39.798702 CA_PICK = 800
646 23:49:39.801786 CA_MCKIO = 800
647 23:49:39.805260 MCKIO_SEMI = 0
648 23:49:39.808553 PLL_FREQ = 3068
649 23:49:39.812163 DQ_UI_PI_RATIO = 32
650 23:49:39.815293 CA_UI_PI_RATIO = 0
651 23:49:39.818976 ===================================
652 23:49:39.821774 ===================================
653 23:49:39.822199 memory_type:LPDDR4
654 23:49:39.825274 GP_NUM : 10
655 23:49:39.828738 SRAM_EN : 1
656 23:49:39.829162 MD32_EN : 0
657 23:49:39.831694 ===================================
658 23:49:39.835089 [ANA_INIT] >>>>>>>>>>>>>>
659 23:49:39.838559 <<<<<< [CONFIGURE PHASE]: ANA_TX
660 23:49:39.842319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
661 23:49:39.845403 ===================================
662 23:49:39.848909 data_rate = 1600,PCW = 0X7600
663 23:49:39.851740 ===================================
664 23:49:39.855576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
665 23:49:39.858916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
666 23:49:39.864964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 23:49:39.869040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
668 23:49:39.872344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
669 23:49:39.875970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
670 23:49:39.880086 [ANA_INIT] flow start
671 23:49:39.880510 [ANA_INIT] PLL >>>>>>>>
672 23:49:39.883540 [ANA_INIT] PLL <<<<<<<<
673 23:49:39.886990 [ANA_INIT] MIDPI >>>>>>>>
674 23:49:39.887418 [ANA_INIT] MIDPI <<<<<<<<
675 23:49:39.891385 [ANA_INIT] DLL >>>>>>>>
676 23:49:39.891810 [ANA_INIT] flow end
677 23:49:39.894817 ============ LP4 DIFF to SE enter ============
678 23:49:39.902061 ============ LP4 DIFF to SE exit ============
679 23:49:39.902492 [ANA_INIT] <<<<<<<<<<<<<
680 23:49:39.905818 [Flow] Enable top DCM control >>>>>
681 23:49:39.909867 [Flow] Enable top DCM control <<<<<
682 23:49:39.913124 Enable DLL master slave shuffle
683 23:49:39.916718 ==============================================================
684 23:49:39.920216 Gating Mode config
685 23:49:39.923703 ==============================================================
686 23:49:39.926707 Config description:
687 23:49:39.936971 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
688 23:49:39.943758 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
689 23:49:39.946742 SELPH_MODE 0: By rank 1: By Phase
690 23:49:39.953404 ==============================================================
691 23:49:39.956820 GAT_TRACK_EN = 1
692 23:49:39.960429 RX_GATING_MODE = 2
693 23:49:39.963635 RX_GATING_TRACK_MODE = 2
694 23:49:39.966898 SELPH_MODE = 1
695 23:49:39.967360 PICG_EARLY_EN = 1
696 23:49:39.970422 VALID_LAT_VALUE = 1
697 23:49:39.977005 ==============================================================
698 23:49:39.980001 Enter into Gating configuration >>>>
699 23:49:39.983550 Exit from Gating configuration <<<<
700 23:49:39.987117 Enter into DVFS_PRE_config >>>>>
701 23:49:39.997247 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
702 23:49:40.000042 Exit from DVFS_PRE_config <<<<<
703 23:49:40.003719 Enter into PICG configuration >>>>
704 23:49:40.007306 Exit from PICG configuration <<<<
705 23:49:40.010283 [RX_INPUT] configuration >>>>>
706 23:49:40.013194 [RX_INPUT] configuration <<<<<
707 23:49:40.016623 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
708 23:49:40.023490 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
709 23:49:40.029832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
710 23:49:40.036640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
711 23:49:40.043510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
712 23:49:40.046648 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
713 23:49:40.053098 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
714 23:49:40.056437 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
715 23:49:40.059973 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
716 23:49:40.063450 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
717 23:49:40.067016 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
718 23:49:40.073140 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
719 23:49:40.076880 ===================================
720 23:49:40.079819 LPDDR4 DRAM CONFIGURATION
721 23:49:40.083153 ===================================
722 23:49:40.083603 EX_ROW_EN[0] = 0x0
723 23:49:40.087821 EX_ROW_EN[1] = 0x0
724 23:49:40.088347 LP4Y_EN = 0x0
725 23:49:40.091407 WORK_FSP = 0x0
726 23:49:40.091932 WL = 0x2
727 23:49:40.095291 RL = 0x2
728 23:49:40.095835 BL = 0x2
729 23:49:40.096184 RPST = 0x0
730 23:49:40.098517 RD_PRE = 0x0
731 23:49:40.098949 WR_PRE = 0x1
732 23:49:40.101864 WR_PST = 0x0
733 23:49:40.102311 DBI_WR = 0x0
734 23:49:40.106009 DBI_RD = 0x0
735 23:49:40.106451 OTF = 0x1
736 23:49:40.108881 ===================================
737 23:49:40.113062 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
738 23:49:40.116510 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
739 23:49:40.123872 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
740 23:49:40.127365 ===================================
741 23:49:40.127797 LPDDR4 DRAM CONFIGURATION
742 23:49:40.131486 ===================================
743 23:49:40.134683 EX_ROW_EN[0] = 0x10
744 23:49:40.135186 EX_ROW_EN[1] = 0x0
745 23:49:40.138362 LP4Y_EN = 0x0
746 23:49:40.138803 WORK_FSP = 0x0
747 23:49:40.142817 WL = 0x2
748 23:49:40.143262 RL = 0x2
749 23:49:40.143608 BL = 0x2
750 23:49:40.146058 RPST = 0x0
751 23:49:40.146489 RD_PRE = 0x0
752 23:49:40.149221 WR_PRE = 0x1
753 23:49:40.149674 WR_PST = 0x0
754 23:49:40.153555 DBI_WR = 0x0
755 23:49:40.153986 DBI_RD = 0x0
756 23:49:40.156746 OTF = 0x1
757 23:49:40.160552 ===================================
758 23:49:40.163953 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
759 23:49:40.169692 nWR fixed to 40
760 23:49:40.173112 [ModeRegInit_LP4] CH0 RK0
761 23:49:40.173555 [ModeRegInit_LP4] CH0 RK1
762 23:49:40.176375 [ModeRegInit_LP4] CH1 RK0
763 23:49:40.179865 [ModeRegInit_LP4] CH1 RK1
764 23:49:40.180293 match AC timing 13
765 23:49:40.183761 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
766 23:49:40.187380 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
767 23:49:40.194750 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
768 23:49:40.198337 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
769 23:49:40.201971 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
770 23:49:40.205752 [EMI DOE] emi_dcm 0
771 23:49:40.208999 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
772 23:49:40.209434 ==
773 23:49:40.212915 Dram Type= 6, Freq= 0, CH_0, rank 0
774 23:49:40.216157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 23:49:40.216820 ==
776 23:49:40.220266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
777 23:49:40.227211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
778 23:49:40.237102 [CA 0] Center 38 (7~69) winsize 63
779 23:49:40.240953 [CA 1] Center 38 (7~69) winsize 63
780 23:49:40.244841 [CA 2] Center 35 (5~66) winsize 62
781 23:49:40.248327 [CA 3] Center 35 (5~66) winsize 62
782 23:49:40.252275 [CA 4] Center 34 (4~65) winsize 62
783 23:49:40.252748 [CA 5] Center 34 (4~64) winsize 61
784 23:49:40.256164
785 23:49:40.256693 [CmdBusTrainingLP45] Vref(ca) range 1: 34
786 23:49:40.259964
787 23:49:40.260410 [CATrainingPosCal] consider 1 rank data
788 23:49:40.263402 u2DelayCellTimex100 = 270/100 ps
789 23:49:40.267142 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
790 23:49:40.271015 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
791 23:49:40.274895 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
792 23:49:40.278368 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
793 23:49:40.282316 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
794 23:49:40.285748 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
795 23:49:40.286280
796 23:49:40.289537 CA PerBit enable=1, Macro0, CA PI delay=34
797 23:49:40.290043
798 23:49:40.292882 [CBTSetCACLKResult] CA Dly = 34
799 23:49:40.293346 CS Dly: 6 (0~37)
800 23:49:40.296949 ==
801 23:49:40.297458 Dram Type= 6, Freq= 0, CH_0, rank 1
802 23:49:40.304436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 23:49:40.304936 ==
804 23:49:40.308494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
805 23:49:40.315067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
806 23:49:40.323597 [CA 0] Center 38 (7~69) winsize 63
807 23:49:40.327593 [CA 1] Center 38 (7~69) winsize 63
808 23:49:40.331008 [CA 2] Center 35 (5~66) winsize 62
809 23:49:40.334554 [CA 3] Center 35 (5~66) winsize 62
810 23:49:40.338489 [CA 4] Center 34 (4~65) winsize 62
811 23:49:40.338919 [CA 5] Center 34 (4~65) winsize 62
812 23:49:40.339277
813 23:49:40.342501 [CmdBusTrainingLP45] Vref(ca) range 1: 32
814 23:49:40.343109
815 23:49:40.346404 [CATrainingPosCal] consider 2 rank data
816 23:49:40.350048 u2DelayCellTimex100 = 270/100 ps
817 23:49:40.353322 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
818 23:49:40.356835 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
819 23:49:40.360680 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
820 23:49:40.364472 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
821 23:49:40.368406 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
822 23:49:40.372231 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
823 23:49:40.372729
824 23:49:40.376259 CA PerBit enable=1, Macro0, CA PI delay=34
825 23:49:40.376727
826 23:49:40.379903 [CBTSetCACLKResult] CA Dly = 34
827 23:49:40.380216 CS Dly: 6 (0~37)
828 23:49:40.380458
829 23:49:40.383335 ----->DramcWriteLeveling(PI) begin...
830 23:49:40.383666 ==
831 23:49:40.387180 Dram Type= 6, Freq= 0, CH_0, rank 0
832 23:49:40.390635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
833 23:49:40.393900 ==
834 23:49:40.394057 Write leveling (Byte 0): 31 => 31
835 23:49:40.397043 Write leveling (Byte 1): 29 => 29
836 23:49:40.400070 DramcWriteLeveling(PI) end<-----
837 23:49:40.400204
838 23:49:40.400309 ==
839 23:49:40.403506 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:49:40.410593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:49:40.410702 ==
842 23:49:40.410787 [Gating] SW mode calibration
843 23:49:40.420295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
844 23:49:40.423700 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
845 23:49:40.427215 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
846 23:49:40.433897 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 23:49:40.436771 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
848 23:49:40.440196 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
849 23:49:40.447147 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 23:49:40.450591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 23:49:40.454348 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 23:49:40.457795 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 23:49:40.465450 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 23:49:40.468899 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:49:40.472233 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:49:40.475391 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:49:40.482327 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:49:40.486442 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:49:40.489498 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:49:40.492999 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:49:40.499287 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:49:40.502829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:49:40.506186 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
864 23:49:40.512714 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:49:40.516167 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:49:40.519616 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:49:40.526118 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:49:40.529552 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:49:40.533031 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:49:40.539719 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:49:40.543124 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:49:40.546516 0 9 12 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
873 23:49:40.553039 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
874 23:49:40.556533 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 23:49:40.559786 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 23:49:40.566221 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 23:49:40.569689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 23:49:40.572984 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 23:49:40.579502 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (1 0)
880 23:49:40.583047 0 10 12 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
881 23:49:40.586501 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
882 23:49:40.593082 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 23:49:40.596739 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 23:49:40.599245 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 23:49:40.606060 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 23:49:40.609561 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 23:49:40.612892 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
888 23:49:40.616169 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
889 23:49:40.622948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 23:49:40.625881 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 23:49:40.629107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 23:49:40.636023 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 23:49:40.639203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 23:49:40.642937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 23:49:40.649022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
896 23:49:40.652226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
897 23:49:40.655727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 23:49:40.662238 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 23:49:40.666236 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 23:49:40.669345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 23:49:40.675757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 23:49:40.679138 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 23:49:40.682545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:49:40.689638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:49:40.692749 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:49:40.696054 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:49:40.699739 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:49:40.705946 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:49:40.709637 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:49:40.715964 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:49:40.719545 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:49:40.722264 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
913 23:49:40.725881 Total UI for P1: 0, mck2ui 16
914 23:49:40.729399 best dqsien dly found for B0: ( 0, 14, 10)
915 23:49:40.732686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 23:49:40.735953 Total UI for P1: 0, mck2ui 16
917 23:49:40.739313 best dqsien dly found for B1: ( 0, 14, 12)
918 23:49:40.742435 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
919 23:49:40.749211 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
920 23:49:40.749639
921 23:49:40.752608 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
922 23:49:40.756078 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
923 23:49:40.759746 [Gating] SW calibration Done
924 23:49:40.760605 ==
925 23:49:40.763090 Dram Type= 6, Freq= 0, CH_0, rank 0
926 23:49:40.766065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 23:49:40.766543 ==
928 23:49:40.766877 RX Vref Scan: 0
929 23:49:40.769148
930 23:49:40.769566 RX Vref 0 -> 0, step: 1
931 23:49:40.769894
932 23:49:40.772692 RX Delay -130 -> 252, step: 16
933 23:49:40.775739 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
934 23:49:40.782400 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 23:49:40.785997 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
936 23:49:40.788961 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
937 23:49:40.792435 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 23:49:40.795785 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
939 23:49:40.799158 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 23:49:40.805717 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 23:49:40.809178 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 23:49:40.812609 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
943 23:49:40.815986 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 23:49:40.819200 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 23:49:40.825845 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 23:49:40.829465 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 23:49:40.832513 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 23:49:40.835676 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 23:49:40.836099 ==
950 23:49:40.838926 Dram Type= 6, Freq= 0, CH_0, rank 0
951 23:49:40.846118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 23:49:40.846542 ==
953 23:49:40.846873 DQS Delay:
954 23:49:40.849426 DQS0 = 0, DQS1 = 0
955 23:49:40.849846 DQM Delay:
956 23:49:40.850292 DQM0 = 82, DQM1 = 69
957 23:49:40.852430 DQ Delay:
958 23:49:40.855882 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =85
959 23:49:40.858784 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
960 23:49:40.862923 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
961 23:49:40.866288 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 23:49:40.866712
963 23:49:40.867045
964 23:49:40.867661 ==
965 23:49:40.869188 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:49:40.872639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:49:40.873347 ==
968 23:49:40.873909
969 23:49:40.874389
970 23:49:40.875969 TX Vref Scan disable
971 23:49:40.876455 == TX Byte 0 ==
972 23:49:40.882638 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
973 23:49:40.886013 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
974 23:49:40.886432 == TX Byte 1 ==
975 23:49:40.892467 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 23:49:40.895742 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 23:49:40.896161 ==
978 23:49:40.899344 Dram Type= 6, Freq= 0, CH_0, rank 0
979 23:49:40.902650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 23:49:40.903075 ==
981 23:49:40.916500 TX Vref=22, minBit 11, minWin=26, winSum=439
982 23:49:40.919994 TX Vref=24, minBit 11, minWin=26, winSum=438
983 23:49:40.923288 TX Vref=26, minBit 7, minWin=27, winSum=447
984 23:49:40.926662 TX Vref=28, minBit 0, minWin=27, winSum=445
985 23:49:40.929747 TX Vref=30, minBit 10, minWin=27, winSum=444
986 23:49:40.936513 TX Vref=32, minBit 2, minWin=27, winSum=441
987 23:49:40.940048 [TxChooseVref] Worse bit 7, Min win 27, Win sum 447, Final Vref 26
988 23:49:40.940538
989 23:49:40.943407 Final TX Range 1 Vref 26
990 23:49:40.943869
991 23:49:40.944228 ==
992 23:49:40.946540 Dram Type= 6, Freq= 0, CH_0, rank 0
993 23:49:40.949852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 23:49:40.953282 ==
995 23:49:40.953748
996 23:49:40.954114
997 23:49:40.954454 TX Vref Scan disable
998 23:49:40.956911 == TX Byte 0 ==
999 23:49:40.960234 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1000 23:49:40.967029 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1001 23:49:40.967502 == TX Byte 1 ==
1002 23:49:40.970160 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1003 23:49:40.973838 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1004 23:49:40.976668
1005 23:49:40.977130 [DATLAT]
1006 23:49:40.977498 Freq=800, CH0 RK0
1007 23:49:40.977841
1008 23:49:40.980313 DATLAT Default: 0xa
1009 23:49:40.980922 0, 0xFFFF, sum = 0
1010 23:49:40.983953 1, 0xFFFF, sum = 0
1011 23:49:40.984542 2, 0xFFFF, sum = 0
1012 23:49:40.987132 3, 0xFFFF, sum = 0
1013 23:49:40.987605 4, 0xFFFF, sum = 0
1014 23:49:40.990678 5, 0xFFFF, sum = 0
1015 23:49:40.991257 6, 0xFFFF, sum = 0
1016 23:49:40.993844 7, 0xFFFF, sum = 0
1017 23:49:40.994428 8, 0xFFFF, sum = 0
1018 23:49:40.997093 9, 0x0, sum = 1
1019 23:49:40.997566 10, 0x0, sum = 2
1020 23:49:41.000027 11, 0x0, sum = 3
1021 23:49:41.000511 12, 0x0, sum = 4
1022 23:49:41.003850 best_step = 10
1023 23:49:41.004314
1024 23:49:41.004746 ==
1025 23:49:41.007206 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 23:49:41.010291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 23:49:41.010755 ==
1028 23:49:41.013708 RX Vref Scan: 1
1029 23:49:41.014196
1030 23:49:41.014567 Set Vref Range= 32 -> 127
1031 23:49:41.014909
1032 23:49:41.017223 RX Vref 32 -> 127, step: 1
1033 23:49:41.017684
1034 23:49:41.021187 RX Delay -111 -> 252, step: 8
1035 23:49:41.021650
1036 23:49:41.023723 Set Vref, RX VrefLevel [Byte0]: 32
1037 23:49:41.027076 [Byte1]: 32
1038 23:49:41.027534
1039 23:49:41.030297 Set Vref, RX VrefLevel [Byte0]: 33
1040 23:49:41.033344 [Byte1]: 33
1041 23:49:41.037374
1042 23:49:41.037829 Set Vref, RX VrefLevel [Byte0]: 34
1043 23:49:41.040411 [Byte1]: 34
1044 23:49:41.045016
1045 23:49:41.045488 Set Vref, RX VrefLevel [Byte0]: 35
1046 23:49:41.048048 [Byte1]: 35
1047 23:49:41.052363
1048 23:49:41.052817 Set Vref, RX VrefLevel [Byte0]: 36
1049 23:49:41.055813 [Byte1]: 36
1050 23:49:41.060259
1051 23:49:41.060765 Set Vref, RX VrefLevel [Byte0]: 37
1052 23:49:41.063555 [Byte1]: 37
1053 23:49:41.067873
1054 23:49:41.068298 Set Vref, RX VrefLevel [Byte0]: 38
1055 23:49:41.071291 [Byte1]: 38
1056 23:49:41.075477
1057 23:49:41.076064 Set Vref, RX VrefLevel [Byte0]: 39
1058 23:49:41.079110 [Byte1]: 39
1059 23:49:41.082871
1060 23:49:41.083304 Set Vref, RX VrefLevel [Byte0]: 40
1061 23:49:41.086487 [Byte1]: 40
1062 23:49:41.090939
1063 23:49:41.091404 Set Vref, RX VrefLevel [Byte0]: 41
1064 23:49:41.094920 [Byte1]: 41
1065 23:49:41.098197
1066 23:49:41.098666 Set Vref, RX VrefLevel [Byte0]: 42
1067 23:49:41.102506 [Byte1]: 42
1068 23:49:41.106088
1069 23:49:41.106555 Set Vref, RX VrefLevel [Byte0]: 43
1070 23:49:41.109379 [Byte1]: 43
1071 23:49:41.113519
1072 23:49:41.113983 Set Vref, RX VrefLevel [Byte0]: 44
1073 23:49:41.116965 [Byte1]: 44
1074 23:49:41.121434
1075 23:49:41.121998 Set Vref, RX VrefLevel [Byte0]: 45
1076 23:49:41.125061 [Byte1]: 45
1077 23:49:41.129675
1078 23:49:41.130136 Set Vref, RX VrefLevel [Byte0]: 46
1079 23:49:41.133010 [Byte1]: 46
1080 23:49:41.137321
1081 23:49:41.137814 Set Vref, RX VrefLevel [Byte0]: 47
1082 23:49:41.140265 [Byte1]: 47
1083 23:49:41.144635
1084 23:49:41.145150 Set Vref, RX VrefLevel [Byte0]: 48
1085 23:49:41.147698 [Byte1]: 48
1086 23:49:41.152699
1087 23:49:41.153325 Set Vref, RX VrefLevel [Byte0]: 49
1088 23:49:41.155485 [Byte1]: 49
1089 23:49:41.159603
1090 23:49:41.160061 Set Vref, RX VrefLevel [Byte0]: 50
1091 23:49:41.162812 [Byte1]: 50
1092 23:49:41.167117
1093 23:49:41.167609 Set Vref, RX VrefLevel [Byte0]: 51
1094 23:49:41.170478 [Byte1]: 51
1095 23:49:41.174660
1096 23:49:41.175084 Set Vref, RX VrefLevel [Byte0]: 52
1097 23:49:41.178404 [Byte1]: 52
1098 23:49:41.182770
1099 23:49:41.183217 Set Vref, RX VrefLevel [Byte0]: 53
1100 23:49:41.186227 [Byte1]: 53
1101 23:49:41.189967
1102 23:49:41.190409 Set Vref, RX VrefLevel [Byte0]: 54
1103 23:49:41.193907 [Byte1]: 54
1104 23:49:41.197586
1105 23:49:41.198020 Set Vref, RX VrefLevel [Byte0]: 55
1106 23:49:41.200933 [Byte1]: 55
1107 23:49:41.205851
1108 23:49:41.206378 Set Vref, RX VrefLevel [Byte0]: 56
1109 23:49:41.208656 [Byte1]: 56
1110 23:49:41.213342
1111 23:49:41.213781 Set Vref, RX VrefLevel [Byte0]: 57
1112 23:49:41.216540 [Byte1]: 57
1113 23:49:41.220695
1114 23:49:41.221132 Set Vref, RX VrefLevel [Byte0]: 58
1115 23:49:41.224196 [Byte1]: 58
1116 23:49:41.228417
1117 23:49:41.229012 Set Vref, RX VrefLevel [Byte0]: 59
1118 23:49:41.231376 [Byte1]: 59
1119 23:49:41.236221
1120 23:49:41.236763 Set Vref, RX VrefLevel [Byte0]: 60
1121 23:49:41.239056 [Byte1]: 60
1122 23:49:41.243782
1123 23:49:41.244206 Set Vref, RX VrefLevel [Byte0]: 61
1124 23:49:41.246744 [Byte1]: 61
1125 23:49:41.251109
1126 23:49:41.251544 Set Vref, RX VrefLevel [Byte0]: 62
1127 23:49:41.254635 [Byte1]: 62
1128 23:49:41.259340
1129 23:49:41.259892 Set Vref, RX VrefLevel [Byte0]: 63
1130 23:49:41.262076 [Byte1]: 63
1131 23:49:41.266584
1132 23:49:41.267010 Set Vref, RX VrefLevel [Byte0]: 64
1133 23:49:41.269978 [Byte1]: 64
1134 23:49:41.273996
1135 23:49:41.274430 Set Vref, RX VrefLevel [Byte0]: 65
1136 23:49:41.277745 [Byte1]: 65
1137 23:49:41.282287
1138 23:49:41.282744 Set Vref, RX VrefLevel [Byte0]: 66
1139 23:49:41.285743 [Byte1]: 66
1140 23:49:41.290038
1141 23:49:41.290605 Set Vref, RX VrefLevel [Byte0]: 67
1142 23:49:41.292671 [Byte1]: 67
1143 23:49:41.297350
1144 23:49:41.297931 Set Vref, RX VrefLevel [Byte0]: 68
1145 23:49:41.300686 [Byte1]: 68
1146 23:49:41.305102
1147 23:49:41.305648 Set Vref, RX VrefLevel [Byte0]: 69
1148 23:49:41.307970 [Byte1]: 69
1149 23:49:41.312765
1150 23:49:41.313233 Set Vref, RX VrefLevel [Byte0]: 70
1151 23:49:41.316080 [Byte1]: 70
1152 23:49:41.320066
1153 23:49:41.320536 Set Vref, RX VrefLevel [Byte0]: 71
1154 23:49:41.324016 [Byte1]: 71
1155 23:49:41.327879
1156 23:49:41.328453 Set Vref, RX VrefLevel [Byte0]: 72
1157 23:49:41.331454 [Byte1]: 72
1158 23:49:41.335516
1159 23:49:41.335980 Set Vref, RX VrefLevel [Byte0]: 73
1160 23:49:41.339018 [Byte1]: 73
1161 23:49:41.343395
1162 23:49:41.343855 Set Vref, RX VrefLevel [Byte0]: 74
1163 23:49:41.347792 [Byte1]: 74
1164 23:49:41.350897
1165 23:49:41.351354 Set Vref, RX VrefLevel [Byte0]: 75
1166 23:49:41.354121 [Byte1]: 75
1167 23:49:41.358212
1168 23:49:41.358722 Set Vref, RX VrefLevel [Byte0]: 76
1169 23:49:41.361826 [Byte1]: 76
1170 23:49:41.365988
1171 23:49:41.366449 Set Vref, RX VrefLevel [Byte0]: 77
1172 23:49:41.369129 [Byte1]: 77
1173 23:49:41.373664
1174 23:49:41.374157 Set Vref, RX VrefLevel [Byte0]: 78
1175 23:49:41.377077 [Byte1]: 78
1176 23:49:41.381711
1177 23:49:41.382281 Set Vref, RX VrefLevel [Byte0]: 79
1178 23:49:41.384892 [Byte1]: 79
1179 23:49:41.389514
1180 23:49:41.389987 Set Vref, RX VrefLevel [Byte0]: 80
1181 23:49:41.392049 [Byte1]: 80
1182 23:49:41.396962
1183 23:49:41.397552 Final RX Vref Byte 0 = 62 to rank0
1184 23:49:41.399965 Final RX Vref Byte 1 = 55 to rank0
1185 23:49:41.403342 Final RX Vref Byte 0 = 62 to rank1
1186 23:49:41.406635 Final RX Vref Byte 1 = 55 to rank1==
1187 23:49:41.410122 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 23:49:41.416630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 23:49:41.417291 ==
1190 23:49:41.417674 DQS Delay:
1191 23:49:41.418175 DQS0 = 0, DQS1 = 0
1192 23:49:41.419987 DQM Delay:
1193 23:49:41.420458 DQM0 = 82, DQM1 = 68
1194 23:49:41.423248 DQ Delay:
1195 23:49:41.426459 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1196 23:49:41.426930 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1197 23:49:41.429740 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1198 23:49:41.433165 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1199 23:49:41.436641
1200 23:49:41.437109
1201 23:49:41.443560 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1202 23:49:41.446615 CH0 RK0: MR19=606, MR18=2C2B
1203 23:49:41.453269 CH0_RK0: MR19=0x606, MR18=0x2C2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1204 23:49:41.453819
1205 23:49:41.456584 ----->DramcWriteLeveling(PI) begin...
1206 23:49:41.457053 ==
1207 23:49:41.459854 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:49:41.463459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 23:49:41.464001 ==
1210 23:49:41.466631 Write leveling (Byte 0): 34 => 34
1211 23:49:41.469815 Write leveling (Byte 1): 29 => 29
1212 23:49:41.473065 DramcWriteLeveling(PI) end<-----
1213 23:49:41.473523
1214 23:49:41.473919 ==
1215 23:49:41.476692 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 23:49:41.479699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 23:49:41.480244 ==
1218 23:49:41.483192 [Gating] SW mode calibration
1219 23:49:41.489561 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 23:49:41.496892 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 23:49:41.499895 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 23:49:41.503175 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 23:49:41.509966 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1224 23:49:41.513355 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 23:49:41.516685 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:49:41.523133 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:49:41.526610 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:49:41.529479 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:49:41.537005 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:49:41.580725 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:49:41.581755 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:49:41.582240 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:49:41.582600 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:49:41.582935 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:49:41.583258 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:49:41.583568 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:49:41.583878 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:49:41.584188 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1239 23:49:41.584602 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1240 23:49:41.621751 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 23:49:41.622351 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:49:41.622802 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:49:41.623610 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:49:41.623981 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:49:41.624324 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:49:41.624693 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:49:41.625028 0 9 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
1248 23:49:41.625348 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:49:41.626150 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:49:41.629707 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:49:41.632896 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:49:41.636679 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:49:41.639768 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:49:41.646964 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1255 23:49:41.649724 0 10 8 | B1->B0 | 3232 2424 | 1 0 | (1 0) (1 0)
1256 23:49:41.653300 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:49:41.656434 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:49:41.662989 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:49:41.666463 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:49:41.669896 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:49:41.676165 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:49:41.679648 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1263 23:49:41.683194 0 11 8 | B1->B0 | 2e2e 3a3a | 0 1 | (0 0) (0 0)
1264 23:49:41.690078 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1265 23:49:41.693140 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:49:41.697230 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:49:41.700870 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:49:41.708001 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:49:41.711830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:49:41.715044 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1271 23:49:41.718150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1272 23:49:41.725712 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:49:41.728877 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:49:41.732195 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:49:41.735646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:49:41.742182 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:49:41.745750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:49:41.748958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:49:41.755557 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:49:41.759183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:49:41.762486 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:49:41.769203 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:49:41.772040 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:49:41.775456 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:49:41.782174 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:49:41.785692 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:49:41.789225 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1288 23:49:41.795593 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 23:49:41.796010 Total UI for P1: 0, mck2ui 16
1290 23:49:41.802241 best dqsien dly found for B0: ( 0, 14, 8)
1291 23:49:41.802776 Total UI for P1: 0, mck2ui 16
1292 23:49:41.805604 best dqsien dly found for B1: ( 0, 14, 10)
1293 23:49:41.812249 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1294 23:49:41.815614 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1295 23:49:41.816104
1296 23:49:41.818769 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 23:49:41.822311 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1298 23:49:41.825410 [Gating] SW calibration Done
1299 23:49:41.825985 ==
1300 23:49:41.828679 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 23:49:41.832183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 23:49:41.832699 ==
1303 23:49:41.835488 RX Vref Scan: 0
1304 23:49:41.835957
1305 23:49:41.836320 RX Vref 0 -> 0, step: 1
1306 23:49:41.836708
1307 23:49:41.838840 RX Delay -130 -> 252, step: 16
1308 23:49:41.841731 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1309 23:49:41.848600 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1310 23:49:41.852231 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1311 23:49:41.855127 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1312 23:49:41.858330 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1313 23:49:41.861816 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1314 23:49:41.868621 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1315 23:49:41.872194 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1316 23:49:41.875877 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1317 23:49:41.878270 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1318 23:49:41.881812 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1319 23:49:41.888374 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1320 23:49:41.892245 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1321 23:49:41.895211 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1322 23:49:41.898587 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1323 23:49:41.901681 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1324 23:49:41.905059 ==
1325 23:49:41.908682 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 23:49:41.911668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 23:49:41.912090 ==
1328 23:49:41.912423 DQS Delay:
1329 23:49:41.914814 DQS0 = 0, DQS1 = 0
1330 23:49:41.915377 DQM Delay:
1331 23:49:41.918347 DQM0 = 81, DQM1 = 70
1332 23:49:41.918890 DQ Delay:
1333 23:49:41.922032 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1334 23:49:41.925361 DQ4 =85, DQ5 =61, DQ6 =93, DQ7 =93
1335 23:49:41.928911 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1336 23:49:41.931731 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =85
1337 23:49:41.932282
1338 23:49:41.932787
1339 23:49:41.933111 ==
1340 23:49:41.935169 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 23:49:41.938410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 23:49:41.938836 ==
1343 23:49:41.939195
1344 23:49:41.939507
1345 23:49:41.941581 TX Vref Scan disable
1346 23:49:41.945187 == TX Byte 0 ==
1347 23:49:41.948411 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1348 23:49:41.951594 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1349 23:49:41.955004 == TX Byte 1 ==
1350 23:49:41.958368 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1351 23:49:41.961805 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1352 23:49:41.962517 ==
1353 23:49:41.964758 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 23:49:41.968545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 23:49:41.971262 ==
1356 23:49:41.983541 TX Vref=22, minBit 1, minWin=27, winSum=436
1357 23:49:41.987179 TX Vref=24, minBit 1, minWin=27, winSum=437
1358 23:49:41.990075 TX Vref=26, minBit 1, minWin=27, winSum=440
1359 23:49:41.993311 TX Vref=28, minBit 1, minWin=27, winSum=443
1360 23:49:41.996487 TX Vref=30, minBit 1, minWin=27, winSum=443
1361 23:49:42.000081 TX Vref=32, minBit 1, minWin=27, winSum=444
1362 23:49:42.006616 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 32
1363 23:49:42.007193
1364 23:49:42.010148 Final TX Range 1 Vref 32
1365 23:49:42.010727
1366 23:49:42.011214 ==
1367 23:49:42.013732 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 23:49:42.016804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 23:49:42.017197 ==
1370 23:49:42.017541
1371 23:49:42.020122
1372 23:49:42.020543 TX Vref Scan disable
1373 23:49:42.023305 == TX Byte 0 ==
1374 23:49:42.026689 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1375 23:49:42.030051 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1376 23:49:42.033200 == TX Byte 1 ==
1377 23:49:42.036986 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1378 23:49:42.039808 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1379 23:49:42.043175
1380 23:49:42.043284 [DATLAT]
1381 23:49:42.043377 Freq=800, CH0 RK1
1382 23:49:42.043466
1383 23:49:42.046387 DATLAT Default: 0xa
1384 23:49:42.046495 0, 0xFFFF, sum = 0
1385 23:49:42.050064 1, 0xFFFF, sum = 0
1386 23:49:42.050147 2, 0xFFFF, sum = 0
1387 23:49:42.053012 3, 0xFFFF, sum = 0
1388 23:49:42.053095 4, 0xFFFF, sum = 0
1389 23:49:42.056719 5, 0xFFFF, sum = 0
1390 23:49:42.060092 6, 0xFFFF, sum = 0
1391 23:49:42.060188 7, 0xFFFF, sum = 0
1392 23:49:42.062966 8, 0xFFFF, sum = 0
1393 23:49:42.063061 9, 0x0, sum = 1
1394 23:49:42.063137 10, 0x0, sum = 2
1395 23:49:42.066357 11, 0x0, sum = 3
1396 23:49:42.066470 12, 0x0, sum = 4
1397 23:49:42.069942 best_step = 10
1398 23:49:42.070357
1399 23:49:42.070684 ==
1400 23:49:42.073099 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 23:49:42.076913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 23:49:42.077334 ==
1403 23:49:42.079843 RX Vref Scan: 0
1404 23:49:42.080205
1405 23:49:42.080516 RX Vref 0 -> 0, step: 1
1406 23:49:42.080847
1407 23:49:42.083183 RX Delay -111 -> 252, step: 8
1408 23:49:42.089995 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1409 23:49:42.093435 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1410 23:49:42.096691 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1411 23:49:42.100125 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1412 23:49:42.103898 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1413 23:49:42.110037 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1414 23:49:42.113188 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1415 23:49:42.116886 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1416 23:49:42.119995 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1417 23:49:42.123563 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1418 23:49:42.130133 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1419 23:49:42.133567 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1420 23:49:42.136681 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1421 23:49:42.139783 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1422 23:49:42.143207 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1423 23:49:42.150191 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1424 23:49:42.150625 ==
1425 23:49:42.153261 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 23:49:42.156714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 23:49:42.157251 ==
1428 23:49:42.157731 DQS Delay:
1429 23:49:42.160063 DQS0 = 0, DQS1 = 0
1430 23:49:42.160651 DQM Delay:
1431 23:49:42.163557 DQM0 = 78, DQM1 = 69
1432 23:49:42.163973 DQ Delay:
1433 23:49:42.166475 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1434 23:49:42.170229 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1435 23:49:42.173330 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1436 23:49:42.176803 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1437 23:49:42.177222
1438 23:49:42.177569
1439 23:49:42.186460 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1440 23:49:42.187060 CH0 RK1: MR19=606, MR18=4C27
1441 23:49:42.193214 CH0_RK1: MR19=0x606, MR18=0x4C27, DQSOSC=390, MR23=63, INC=97, DEC=64
1442 23:49:42.196267 [RxdqsGatingPostProcess] freq 800
1443 23:49:42.203179 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 23:49:42.206390 Pre-setting of DQS Precalculation
1445 23:49:42.209831 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 23:49:42.210272 ==
1447 23:49:42.213585 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 23:49:42.216689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 23:49:42.220061 ==
1450 23:49:42.223199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 23:49:42.229813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 23:49:42.238545 [CA 0] Center 36 (6~66) winsize 61
1453 23:49:42.241890 [CA 1] Center 36 (6~67) winsize 62
1454 23:49:42.244904 [CA 2] Center 34 (4~64) winsize 61
1455 23:49:42.248296 [CA 3] Center 34 (4~64) winsize 61
1456 23:49:42.252105 [CA 4] Center 34 (4~64) winsize 61
1457 23:49:42.255416 [CA 5] Center 33 (3~64) winsize 62
1458 23:49:42.255860
1459 23:49:42.258490 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1460 23:49:42.258913
1461 23:49:42.262008 [CATrainingPosCal] consider 1 rank data
1462 23:49:42.265062 u2DelayCellTimex100 = 270/100 ps
1463 23:49:42.268598 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1464 23:49:42.271862 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1465 23:49:42.278236 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1466 23:49:42.281642 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1467 23:49:42.285008 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1468 23:49:42.288277 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1469 23:49:42.288744
1470 23:49:42.291890 CA PerBit enable=1, Macro0, CA PI delay=33
1471 23:49:42.292326
1472 23:49:42.294951 [CBTSetCACLKResult] CA Dly = 33
1473 23:49:42.295384 CS Dly: 5 (0~36)
1474 23:49:42.295820 ==
1475 23:49:42.298325 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 23:49:42.305201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 23:49:42.305635 ==
1478 23:49:42.308242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 23:49:42.315000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 23:49:42.324607 [CA 0] Center 36 (6~66) winsize 61
1481 23:49:42.328005 [CA 1] Center 36 (6~67) winsize 62
1482 23:49:42.331315 [CA 2] Center 34 (4~65) winsize 62
1483 23:49:42.334522 [CA 3] Center 33 (3~64) winsize 62
1484 23:49:42.338139 [CA 4] Center 34 (4~65) winsize 62
1485 23:49:42.341267 [CA 5] Center 33 (3~64) winsize 62
1486 23:49:42.341748
1487 23:49:42.344887 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1488 23:49:42.345415
1489 23:49:42.348322 [CATrainingPosCal] consider 2 rank data
1490 23:49:42.351328 u2DelayCellTimex100 = 270/100 ps
1491 23:49:42.354733 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1492 23:49:42.358561 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1493 23:49:42.362489 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1494 23:49:42.366159 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1495 23:49:42.369883 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1496 23:49:42.373677 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1497 23:49:42.374228
1498 23:49:42.377352 CA PerBit enable=1, Macro0, CA PI delay=33
1499 23:49:42.377876
1500 23:49:42.381521 [CBTSetCACLKResult] CA Dly = 33
1501 23:49:42.382047 CS Dly: 6 (0~38)
1502 23:49:42.382484
1503 23:49:42.384713 ----->DramcWriteLeveling(PI) begin...
1504 23:49:42.385279 ==
1505 23:49:42.388424 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 23:49:42.392405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 23:49:42.395353 ==
1508 23:49:42.395930 Write leveling (Byte 0): 30 => 30
1509 23:49:42.398854 Write leveling (Byte 1): 30 => 30
1510 23:49:42.402356 DramcWriteLeveling(PI) end<-----
1511 23:49:42.402944
1512 23:49:42.403433 ==
1513 23:49:42.405436 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 23:49:42.412322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 23:49:42.412953 ==
1516 23:49:42.415801 [Gating] SW mode calibration
1517 23:49:42.422246 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 23:49:42.425429 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 23:49:42.431854 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 23:49:42.435312 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1521 23:49:42.438441 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1522 23:49:42.442261 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:49:42.448758 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:49:42.452321 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:49:42.455578 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:49:42.461859 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:49:42.465651 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:49:42.468632 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:49:42.475187 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:49:42.478736 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:49:42.481839 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:49:42.488831 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:49:42.492056 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:49:42.495429 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:49:42.501871 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:49:42.505272 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 23:49:42.508464 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:49:42.515287 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:49:42.518981 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:49:42.521940 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:49:42.528749 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:49:42.531936 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:49:42.535314 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:49:42.538859 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:49:42.544960 0 9 8 | B1->B0 | 2e2e 2929 | 0 1 | (0 0) (1 1)
1546 23:49:42.549053 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:49:42.552069 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:49:42.558902 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:49:42.561726 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:49:42.565326 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 23:49:42.572326 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 23:49:42.575153 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1553 23:49:42.578525 0 10 8 | B1->B0 | 2c2c 2929 | 0 1 | (1 1) (1 0)
1554 23:49:42.585281 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:49:42.588727 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:49:42.591949 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:49:42.598737 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:49:42.602424 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 23:49:42.605389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 23:49:42.612022 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
1561 23:49:42.615366 0 11 8 | B1->B0 | 3a3a 3c3c | 0 1 | (1 1) (0 0)
1562 23:49:42.618778 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:49:42.625489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:49:42.628417 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:49:42.632239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:49:42.635529 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 23:49:42.642055 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:49:42.645315 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 23:49:42.649193 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:49:42.655655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:49:42.658824 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:49:42.662071 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:49:42.668926 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:49:42.671850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:49:42.675368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:49:42.682383 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:49:42.685378 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:49:42.688773 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:49:42.695712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:49:42.698680 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:49:42.702209 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:49:42.709137 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:49:42.711627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:49:42.715469 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:49:42.718883 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 23:49:42.725287 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 23:49:42.728335 Total UI for P1: 0, mck2ui 16
1588 23:49:42.732086 best dqsien dly found for B0: ( 0, 14, 8)
1589 23:49:42.735247 Total UI for P1: 0, mck2ui 16
1590 23:49:42.738629 best dqsien dly found for B1: ( 0, 14, 8)
1591 23:49:42.741885 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1592 23:49:42.744881 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1593 23:49:42.744962
1594 23:49:42.748672 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1595 23:49:42.751829 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1596 23:49:42.755298 [Gating] SW calibration Done
1597 23:49:42.755379 ==
1598 23:49:42.758593 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 23:49:42.761954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 23:49:42.762037 ==
1601 23:49:42.765350 RX Vref Scan: 0
1602 23:49:42.765431
1603 23:49:42.765495 RX Vref 0 -> 0, step: 1
1604 23:49:42.765555
1605 23:49:42.768509 RX Delay -130 -> 252, step: 16
1606 23:49:42.772137 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1607 23:49:42.778195 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1608 23:49:42.781619 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1609 23:49:42.785363 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1610 23:49:42.788689 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1611 23:49:42.791736 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1612 23:49:42.798643 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1613 23:49:42.801698 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1614 23:49:42.804853 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1615 23:49:42.808533 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1616 23:49:42.811687 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1617 23:49:42.818454 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1618 23:49:42.822002 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1619 23:49:42.825254 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1620 23:49:42.828263 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1621 23:49:42.831619 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1622 23:49:42.835243 ==
1623 23:49:42.838527 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 23:49:42.841938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 23:49:42.842020 ==
1626 23:49:42.842084 DQS Delay:
1627 23:49:42.844905 DQS0 = 0, DQS1 = 0
1628 23:49:42.844986 DQM Delay:
1629 23:49:42.848175 DQM0 = 81, DQM1 = 72
1630 23:49:42.848256 DQ Delay:
1631 23:49:42.851459 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1632 23:49:42.855302 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1633 23:49:42.858371 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1634 23:49:42.861869 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1635 23:49:42.861951
1636 23:49:42.862014
1637 23:49:42.862073 ==
1638 23:49:42.864979 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 23:49:42.868226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 23:49:42.868307 ==
1641 23:49:42.868371
1642 23:49:42.868430
1643 23:49:42.871704 TX Vref Scan disable
1644 23:49:42.874680 == TX Byte 0 ==
1645 23:49:42.878368 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1646 23:49:42.881550 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1647 23:49:42.885031 == TX Byte 1 ==
1648 23:49:42.888305 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1649 23:49:42.891892 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1650 23:49:42.891973 ==
1651 23:49:42.895357 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 23:49:42.898052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 23:49:42.901788 ==
1654 23:49:42.912863 TX Vref=22, minBit 8, minWin=27, winSum=444
1655 23:49:42.916111 TX Vref=24, minBit 1, minWin=27, winSum=444
1656 23:49:42.919534 TX Vref=26, minBit 1, minWin=27, winSum=446
1657 23:49:42.922587 TX Vref=28, minBit 11, minWin=27, winSum=452
1658 23:49:42.926043 TX Vref=30, minBit 1, minWin=28, winSum=453
1659 23:49:42.929572 TX Vref=32, minBit 9, minWin=27, winSum=452
1660 23:49:42.936815 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 30
1661 23:49:42.936897
1662 23:49:42.939998 Final TX Range 1 Vref 30
1663 23:49:42.940079
1664 23:49:42.940143 ==
1665 23:49:42.943525 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 23:49:42.946954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 23:49:42.947036 ==
1668 23:49:42.947100
1669 23:49:42.947159
1670 23:49:42.950293 TX Vref Scan disable
1671 23:49:42.953281 == TX Byte 0 ==
1672 23:49:42.956690 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1673 23:49:42.960067 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1674 23:49:42.963959 == TX Byte 1 ==
1675 23:49:42.967372 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1676 23:49:42.970024 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1677 23:49:42.970107
1678 23:49:42.973113 [DATLAT]
1679 23:49:42.973194 Freq=800, CH1 RK0
1680 23:49:42.973258
1681 23:49:42.976614 DATLAT Default: 0xa
1682 23:49:42.976720 0, 0xFFFF, sum = 0
1683 23:49:42.980281 1, 0xFFFF, sum = 0
1684 23:49:42.980364 2, 0xFFFF, sum = 0
1685 23:49:42.983135 3, 0xFFFF, sum = 0
1686 23:49:42.983218 4, 0xFFFF, sum = 0
1687 23:49:42.986921 5, 0xFFFF, sum = 0
1688 23:49:42.987003 6, 0xFFFF, sum = 0
1689 23:49:42.990159 7, 0xFFFF, sum = 0
1690 23:49:42.990241 8, 0xFFFF, sum = 0
1691 23:49:42.993496 9, 0x0, sum = 1
1692 23:49:42.993579 10, 0x0, sum = 2
1693 23:49:42.996635 11, 0x0, sum = 3
1694 23:49:42.996718 12, 0x0, sum = 4
1695 23:49:42.999726 best_step = 10
1696 23:49:42.999807
1697 23:49:42.999871 ==
1698 23:49:43.003431 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 23:49:43.006387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 23:49:43.006469 ==
1701 23:49:43.006534 RX Vref Scan: 1
1702 23:49:43.010140
1703 23:49:43.010220 Set Vref Range= 32 -> 127
1704 23:49:43.010285
1705 23:49:43.013313 RX Vref 32 -> 127, step: 1
1706 23:49:43.013395
1707 23:49:43.017011 RX Delay -111 -> 252, step: 8
1708 23:49:43.017092
1709 23:49:43.020160 Set Vref, RX VrefLevel [Byte0]: 32
1710 23:49:43.023415 [Byte1]: 32
1711 23:49:43.023496
1712 23:49:43.026839 Set Vref, RX VrefLevel [Byte0]: 33
1713 23:49:43.030180 [Byte1]: 33
1714 23:49:43.032978
1715 23:49:43.033059 Set Vref, RX VrefLevel [Byte0]: 34
1716 23:49:43.036695 [Byte1]: 34
1717 23:49:43.040509
1718 23:49:43.044053 Set Vref, RX VrefLevel [Byte0]: 35
1719 23:49:43.044135 [Byte1]: 35
1720 23:49:43.048235
1721 23:49:43.048316 Set Vref, RX VrefLevel [Byte0]: 36
1722 23:49:43.051501 [Byte1]: 36
1723 23:49:43.056423
1724 23:49:43.056530 Set Vref, RX VrefLevel [Byte0]: 37
1725 23:49:43.059208 [Byte1]: 37
1726 23:49:43.063919
1727 23:49:43.064001 Set Vref, RX VrefLevel [Byte0]: 38
1728 23:49:43.067272 [Byte1]: 38
1729 23:49:43.071338
1730 23:49:43.071419 Set Vref, RX VrefLevel [Byte0]: 39
1731 23:49:43.074622 [Byte1]: 39
1732 23:49:43.078659
1733 23:49:43.078743 Set Vref, RX VrefLevel [Byte0]: 40
1734 23:49:43.082436 [Byte1]: 40
1735 23:49:43.086578
1736 23:49:43.086658 Set Vref, RX VrefLevel [Byte0]: 41
1737 23:49:43.090072 [Byte1]: 41
1738 23:49:43.094143
1739 23:49:43.094223 Set Vref, RX VrefLevel [Byte0]: 42
1740 23:49:43.097469 [Byte1]: 42
1741 23:49:43.102050
1742 23:49:43.102131 Set Vref, RX VrefLevel [Byte0]: 43
1743 23:49:43.105096 [Byte1]: 43
1744 23:49:43.109740
1745 23:49:43.109821 Set Vref, RX VrefLevel [Byte0]: 44
1746 23:49:43.112619 [Byte1]: 44
1747 23:49:43.117223
1748 23:49:43.117304 Set Vref, RX VrefLevel [Byte0]: 45
1749 23:49:43.120517 [Byte1]: 45
1750 23:49:43.124604
1751 23:49:43.124685 Set Vref, RX VrefLevel [Byte0]: 46
1752 23:49:43.128357 [Byte1]: 46
1753 23:49:43.132464
1754 23:49:43.132579 Set Vref, RX VrefLevel [Byte0]: 47
1755 23:49:43.135973 [Byte1]: 47
1756 23:49:43.140132
1757 23:49:43.140242 Set Vref, RX VrefLevel [Byte0]: 48
1758 23:49:43.143339 [Byte1]: 48
1759 23:49:43.148107
1760 23:49:43.148188 Set Vref, RX VrefLevel [Byte0]: 49
1761 23:49:43.151505 [Byte1]: 49
1762 23:49:43.155771
1763 23:49:43.155852 Set Vref, RX VrefLevel [Byte0]: 50
1764 23:49:43.158856 [Byte1]: 50
1765 23:49:43.162984
1766 23:49:43.163064 Set Vref, RX VrefLevel [Byte0]: 51
1767 23:49:43.166513 [Byte1]: 51
1768 23:49:43.171110
1769 23:49:43.171191 Set Vref, RX VrefLevel [Byte0]: 52
1770 23:49:43.174246 [Byte1]: 52
1771 23:49:43.178281
1772 23:49:43.178362 Set Vref, RX VrefLevel [Byte0]: 53
1773 23:49:43.181844 [Byte1]: 53
1774 23:49:43.186401
1775 23:49:43.186482 Set Vref, RX VrefLevel [Byte0]: 54
1776 23:49:43.189724 [Byte1]: 54
1777 23:49:43.194106
1778 23:49:43.194186 Set Vref, RX VrefLevel [Byte0]: 55
1779 23:49:43.197186 [Byte1]: 55
1780 23:49:43.201352
1781 23:49:43.201432 Set Vref, RX VrefLevel [Byte0]: 56
1782 23:49:43.204996 [Byte1]: 56
1783 23:49:43.209460
1784 23:49:43.209541 Set Vref, RX VrefLevel [Byte0]: 57
1785 23:49:43.212416 [Byte1]: 57
1786 23:49:43.216889
1787 23:49:43.216970 Set Vref, RX VrefLevel [Byte0]: 58
1788 23:49:43.220171 [Byte1]: 58
1789 23:49:43.224287
1790 23:49:43.224394 Set Vref, RX VrefLevel [Byte0]: 59
1791 23:49:43.227627 [Byte1]: 59
1792 23:49:43.232156
1793 23:49:43.232237 Set Vref, RX VrefLevel [Byte0]: 60
1794 23:49:43.235700 [Byte1]: 60
1795 23:49:43.239635
1796 23:49:43.239719 Set Vref, RX VrefLevel [Byte0]: 61
1797 23:49:43.243163 [Byte1]: 61
1798 23:49:43.247273
1799 23:49:43.247354 Set Vref, RX VrefLevel [Byte0]: 62
1800 23:49:43.250384 [Byte1]: 62
1801 23:49:43.254887
1802 23:49:43.254968 Set Vref, RX VrefLevel [Byte0]: 63
1803 23:49:43.258288 [Byte1]: 63
1804 23:49:43.262799
1805 23:49:43.262880 Set Vref, RX VrefLevel [Byte0]: 64
1806 23:49:43.265876 [Byte1]: 64
1807 23:49:43.270164
1808 23:49:43.270285 Set Vref, RX VrefLevel [Byte0]: 65
1809 23:49:43.273543 [Byte1]: 65
1810 23:49:43.278022
1811 23:49:43.278103 Set Vref, RX VrefLevel [Byte0]: 66
1812 23:49:43.281092 [Byte1]: 66
1813 23:49:43.285489
1814 23:49:43.285612 Set Vref, RX VrefLevel [Byte0]: 67
1815 23:49:43.289019 [Byte1]: 67
1816 23:49:43.293377
1817 23:49:43.293458 Set Vref, RX VrefLevel [Byte0]: 68
1818 23:49:43.296613 [Byte1]: 68
1819 23:49:43.300840
1820 23:49:43.300921 Set Vref, RX VrefLevel [Byte0]: 69
1821 23:49:43.304304 [Byte1]: 69
1822 23:49:43.308822
1823 23:49:43.308902 Set Vref, RX VrefLevel [Byte0]: 70
1824 23:49:43.311880 [Byte1]: 70
1825 23:49:43.316175
1826 23:49:43.316256 Set Vref, RX VrefLevel [Byte0]: 71
1827 23:49:43.319581 [Byte1]: 71
1828 23:49:43.323856
1829 23:49:43.323943 Set Vref, RX VrefLevel [Byte0]: 72
1830 23:49:43.327245 [Byte1]: 72
1831 23:49:43.331201
1832 23:49:43.331309 Set Vref, RX VrefLevel [Byte0]: 73
1833 23:49:43.334537 [Byte1]: 73
1834 23:49:43.339120
1835 23:49:43.339201 Set Vref, RX VrefLevel [Byte0]: 74
1836 23:49:43.342032 [Byte1]: 74
1837 23:49:43.346578
1838 23:49:43.346661 Set Vref, RX VrefLevel [Byte0]: 75
1839 23:49:43.349713 [Byte1]: 75
1840 23:49:43.354299
1841 23:49:43.354380 Final RX Vref Byte 0 = 54 to rank0
1842 23:49:43.357601 Final RX Vref Byte 1 = 53 to rank0
1843 23:49:43.361265 Final RX Vref Byte 0 = 54 to rank1
1844 23:49:43.364116 Final RX Vref Byte 1 = 53 to rank1==
1845 23:49:43.367631 Dram Type= 6, Freq= 0, CH_1, rank 0
1846 23:49:43.374707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 23:49:43.374790 ==
1848 23:49:43.374855 DQS Delay:
1849 23:49:43.374914 DQS0 = 0, DQS1 = 0
1850 23:49:43.377710 DQM Delay:
1851 23:49:43.377791 DQM0 = 80, DQM1 = 72
1852 23:49:43.380663 DQ Delay:
1853 23:49:43.384340 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1854 23:49:43.384447 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1855 23:49:43.387834 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1856 23:49:43.391022 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =80
1857 23:49:43.394443
1858 23:49:43.394522
1859 23:49:43.400844 [DQSOSCAuto] RK0, (LSB)MR18= 0x1621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1860 23:49:43.404438 CH1 RK0: MR19=606, MR18=1621
1861 23:49:43.410855 CH1_RK0: MR19=0x606, MR18=0x1621, DQSOSC=401, MR23=63, INC=91, DEC=61
1862 23:49:43.410937
1863 23:49:43.414209 ----->DramcWriteLeveling(PI) begin...
1864 23:49:43.414292 ==
1865 23:49:43.417449 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 23:49:43.421003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 23:49:43.421110 ==
1868 23:49:43.424405 Write leveling (Byte 0): 26 => 26
1869 23:49:43.427537 Write leveling (Byte 1): 32 => 32
1870 23:49:43.430925 DramcWriteLeveling(PI) end<-----
1871 23:49:43.431006
1872 23:49:43.431070 ==
1873 23:49:43.434396 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 23:49:43.437718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 23:49:43.437800 ==
1876 23:49:43.441224 [Gating] SW mode calibration
1877 23:49:43.447669 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1878 23:49:43.454792 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1879 23:49:43.457332 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1880 23:49:43.461057 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1881 23:49:43.467578 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1882 23:49:43.471524 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:49:43.474280 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:49:43.481401 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:49:43.484309 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:49:43.487967 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:49:43.494197 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:49:43.497675 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:49:43.501314 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:49:43.504721 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:49:43.511301 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:49:43.514226 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:49:43.517597 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:49:43.524496 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:49:43.527851 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:49:43.531117 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1897 23:49:43.537986 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1898 23:49:43.541470 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:49:43.544398 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:49:43.551436 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:49:43.554505 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:49:43.558074 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:49:43.564324 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:49:43.568342 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1905 23:49:43.571170 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1906 23:49:43.578013 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 23:49:43.581627 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 23:49:43.584480 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 23:49:43.591474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 23:49:43.594477 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 23:49:43.597806 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 23:49:43.601433 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
1913 23:49:43.607742 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1914 23:49:43.611273 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 23:49:43.614963 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 23:49:43.621391 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 23:49:43.624615 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 23:49:43.628275 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 23:49:43.634665 0 11 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1920 23:49:43.638392 0 11 4 | B1->B0 | 3030 3a3a | 0 0 | (1 1) (1 1)
1921 23:49:43.641519 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1922 23:49:43.648293 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 23:49:43.651345 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 23:49:43.654647 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 23:49:43.661527 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 23:49:43.664717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 23:49:43.668029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 23:49:43.674759 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1929 23:49:43.678120 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:49:43.681088 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:49:43.688163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:49:43.691280 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:49:43.694793 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:49:43.701418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 23:49:43.705168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 23:49:43.707772 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 23:49:43.711169 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 23:49:43.718067 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 23:49:43.721212 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 23:49:43.724476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 23:49:43.731517 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 23:49:43.734390 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 23:49:43.737976 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 23:49:43.744752 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1945 23:49:43.748207 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 23:49:43.751771 Total UI for P1: 0, mck2ui 16
1947 23:49:43.754955 best dqsien dly found for B0: ( 0, 14, 4)
1948 23:49:43.757864 Total UI for P1: 0, mck2ui 16
1949 23:49:43.761523 best dqsien dly found for B1: ( 0, 14, 4)
1950 23:49:43.764757 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1951 23:49:43.767983 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1952 23:49:43.768373
1953 23:49:43.771757 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1954 23:49:43.774835 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1955 23:49:43.778514 [Gating] SW calibration Done
1956 23:49:43.778931 ==
1957 23:49:43.781525 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 23:49:43.784959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 23:49:43.785382 ==
1960 23:49:43.787953 RX Vref Scan: 0
1961 23:49:43.788370
1962 23:49:43.791369 RX Vref 0 -> 0, step: 1
1963 23:49:43.791790
1964 23:49:43.792118 RX Delay -130 -> 252, step: 16
1965 23:49:43.798252 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1966 23:49:43.801612 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1967 23:49:43.805027 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1968 23:49:43.808548 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1969 23:49:43.811715 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1970 23:49:43.818039 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1971 23:49:43.821933 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1972 23:49:43.824903 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1973 23:49:43.828217 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1974 23:49:43.831619 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1975 23:49:43.838507 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1976 23:49:43.841668 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1977 23:49:43.844650 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1978 23:49:43.848162 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1979 23:49:43.851883 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1980 23:49:43.858043 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1981 23:49:43.858504 ==
1982 23:49:43.861637 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 23:49:43.864856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 23:49:43.865358 ==
1985 23:49:43.865744 DQS Delay:
1986 23:49:43.868028 DQS0 = 0, DQS1 = 0
1987 23:49:43.868677 DQM Delay:
1988 23:49:43.871397 DQM0 = 79, DQM1 = 73
1989 23:49:43.871888 DQ Delay:
1990 23:49:43.874726 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1991 23:49:43.878129 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1992 23:49:43.881094 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1993 23:49:43.884882 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1994 23:49:43.885340
1995 23:49:43.885703
1996 23:49:43.886037 ==
1997 23:49:43.888222 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 23:49:43.891180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 23:49:43.891643 ==
2000 23:49:43.894534
2001 23:49:43.894985
2002 23:49:43.895348 TX Vref Scan disable
2003 23:49:43.897931 == TX Byte 0 ==
2004 23:49:43.901481 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2005 23:49:43.904744 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2006 23:49:43.907866 == TX Byte 1 ==
2007 23:49:43.911035 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2008 23:49:43.914811 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2009 23:49:43.915235 ==
2010 23:49:43.918316 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 23:49:43.924502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 23:49:43.924993 ==
2013 23:49:43.937064 TX Vref=22, minBit 0, minWin=28, winSum=451
2014 23:49:43.940715 TX Vref=24, minBit 3, minWin=28, winSum=453
2015 23:49:43.944082 TX Vref=26, minBit 4, minWin=28, winSum=458
2016 23:49:43.947305 TX Vref=28, minBit 11, minWin=28, winSum=462
2017 23:49:43.950661 TX Vref=30, minBit 3, minWin=28, winSum=457
2018 23:49:43.957121 TX Vref=32, minBit 3, minWin=28, winSum=456
2019 23:49:43.960329 [TxChooseVref] Worse bit 11, Min win 28, Win sum 462, Final Vref 28
2020 23:49:43.960847
2021 23:49:43.964109 Final TX Range 1 Vref 28
2022 23:49:43.964594
2023 23:49:43.965018 ==
2024 23:49:43.967027 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 23:49:43.970299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 23:49:43.970887 ==
2027 23:49:43.973622
2028 23:49:43.974046
2029 23:49:43.974383 TX Vref Scan disable
2030 23:49:43.977266 == TX Byte 0 ==
2031 23:49:43.980972 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2032 23:49:43.987154 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2033 23:49:43.987581 == TX Byte 1 ==
2034 23:49:43.990453 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2035 23:49:43.993897 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2036 23:49:43.997125
2037 23:49:43.997545 [DATLAT]
2038 23:49:43.997873 Freq=800, CH1 RK1
2039 23:49:43.998189
2040 23:49:44.000668 DATLAT Default: 0xa
2041 23:49:44.001129 0, 0xFFFF, sum = 0
2042 23:49:44.003574 1, 0xFFFF, sum = 0
2043 23:49:44.004002 2, 0xFFFF, sum = 0
2044 23:49:44.007215 3, 0xFFFF, sum = 0
2045 23:49:44.007701 4, 0xFFFF, sum = 0
2046 23:49:44.010525 5, 0xFFFF, sum = 0
2047 23:49:44.014081 6, 0xFFFF, sum = 0
2048 23:49:44.014632 7, 0xFFFF, sum = 0
2049 23:49:44.017129 8, 0xFFFF, sum = 0
2050 23:49:44.017558 9, 0x0, sum = 1
2051 23:49:44.017897 10, 0x0, sum = 2
2052 23:49:44.020305 11, 0x0, sum = 3
2053 23:49:44.020757 12, 0x0, sum = 4
2054 23:49:44.023738 best_step = 10
2055 23:49:44.024169
2056 23:49:44.024502 ==
2057 23:49:44.027340 Dram Type= 6, Freq= 0, CH_1, rank 1
2058 23:49:44.030801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2059 23:49:44.031329 ==
2060 23:49:44.033947 RX Vref Scan: 0
2061 23:49:44.034375
2062 23:49:44.034707 RX Vref 0 -> 0, step: 1
2063 23:49:44.035019
2064 23:49:44.036867 RX Delay -111 -> 252, step: 8
2065 23:49:44.043787 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2066 23:49:44.047510 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2067 23:49:44.050842 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2068 23:49:44.053632 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2069 23:49:44.057213 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2070 23:49:44.064178 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2071 23:49:44.067108 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2072 23:49:44.070740 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2073 23:49:44.073986 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2074 23:49:44.077233 iDelay=209, Bit 9, Center 60 (-63 ~ 184) 248
2075 23:49:44.083947 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2076 23:49:44.087332 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2077 23:49:44.090380 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2078 23:49:44.094065 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2079 23:49:44.100278 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2080 23:49:44.103566 iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248
2081 23:49:44.104030 ==
2082 23:49:44.107241 Dram Type= 6, Freq= 0, CH_1, rank 1
2083 23:49:44.110307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2084 23:49:44.110787 ==
2085 23:49:44.111128 DQS Delay:
2086 23:49:44.113491 DQS0 = 0, DQS1 = 0
2087 23:49:44.113917 DQM Delay:
2088 23:49:44.117114 DQM0 = 77, DQM1 = 72
2089 23:49:44.117536 DQ Delay:
2090 23:49:44.120511 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2091 23:49:44.124064 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2092 23:49:44.127029 DQ8 =60, DQ9 =60, DQ10 =80, DQ11 =64
2093 23:49:44.129975 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
2094 23:49:44.130398
2095 23:49:44.130732
2096 23:49:44.139965 [DQSOSCAuto] RK1, (LSB)MR18= 0x2239, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2097 23:49:44.140400 CH1 RK1: MR19=606, MR18=2239
2098 23:49:44.147068 CH1_RK1: MR19=0x606, MR18=0x2239, DQSOSC=395, MR23=63, INC=94, DEC=63
2099 23:49:44.150190 [RxdqsGatingPostProcess] freq 800
2100 23:49:44.157165 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2101 23:49:44.160379 Pre-setting of DQS Precalculation
2102 23:49:44.163364 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2103 23:49:44.170151 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2104 23:49:44.179669 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2105 23:49:44.180092
2106 23:49:44.180420
2107 23:49:44.183300 [Calibration Summary] 1600 Mbps
2108 23:49:44.183722 CH 0, Rank 0
2109 23:49:44.186515 SW Impedance : PASS
2110 23:49:44.186934 DUTY Scan : NO K
2111 23:49:44.190036 ZQ Calibration : PASS
2112 23:49:44.192692 Jitter Meter : NO K
2113 23:49:44.193115 CBT Training : PASS
2114 23:49:44.196720 Write leveling : PASS
2115 23:49:44.199560 RX DQS gating : PASS
2116 23:49:44.200114 RX DQ/DQS(RDDQC) : PASS
2117 23:49:44.203058 TX DQ/DQS : PASS
2118 23:49:44.203745 RX DATLAT : PASS
2119 23:49:44.206010 RX DQ/DQS(Engine): PASS
2120 23:49:44.209592 TX OE : NO K
2121 23:49:44.210191 All Pass.
2122 23:49:44.210687
2123 23:49:44.211145 CH 0, Rank 1
2124 23:49:44.212684 SW Impedance : PASS
2125 23:49:44.216064 DUTY Scan : NO K
2126 23:49:44.216533 ZQ Calibration : PASS
2127 23:49:44.219397 Jitter Meter : NO K
2128 23:49:44.222766 CBT Training : PASS
2129 23:49:44.223278 Write leveling : PASS
2130 23:49:44.226600 RX DQS gating : PASS
2131 23:49:44.229494 RX DQ/DQS(RDDQC) : PASS
2132 23:49:44.229976 TX DQ/DQS : PASS
2133 23:49:44.232938 RX DATLAT : PASS
2134 23:49:44.236399 RX DQ/DQS(Engine): PASS
2135 23:49:44.236909 TX OE : NO K
2136 23:49:44.239841 All Pass.
2137 23:49:44.240435
2138 23:49:44.240990 CH 1, Rank 0
2139 23:49:44.242731 SW Impedance : PASS
2140 23:49:44.243192 DUTY Scan : NO K
2141 23:49:44.245900 ZQ Calibration : PASS
2142 23:49:44.249820 Jitter Meter : NO K
2143 23:49:44.250289 CBT Training : PASS
2144 23:49:44.252800 Write leveling : PASS
2145 23:49:44.253282 RX DQS gating : PASS
2146 23:49:44.256152 RX DQ/DQS(RDDQC) : PASS
2147 23:49:44.259673 TX DQ/DQS : PASS
2148 23:49:44.260159 RX DATLAT : PASS
2149 23:49:44.262504 RX DQ/DQS(Engine): PASS
2150 23:49:44.265843 TX OE : NO K
2151 23:49:44.266323 All Pass.
2152 23:49:44.266804
2153 23:49:44.267255 CH 1, Rank 1
2154 23:49:44.269340 SW Impedance : PASS
2155 23:49:44.272913 DUTY Scan : NO K
2156 23:49:44.273394 ZQ Calibration : PASS
2157 23:49:44.276282 Jitter Meter : NO K
2158 23:49:44.279004 CBT Training : PASS
2159 23:49:44.279421 Write leveling : PASS
2160 23:49:44.282848 RX DQS gating : PASS
2161 23:49:44.285879 RX DQ/DQS(RDDQC) : PASS
2162 23:49:44.286298 TX DQ/DQS : PASS
2163 23:49:44.289261 RX DATLAT : PASS
2164 23:49:44.292525 RX DQ/DQS(Engine): PASS
2165 23:49:44.292977 TX OE : NO K
2166 23:49:44.295885 All Pass.
2167 23:49:44.296299
2168 23:49:44.296655 DramC Write-DBI off
2169 23:49:44.299279 PER_BANK_REFRESH: Hybrid Mode
2170 23:49:44.299696 TX_TRACKING: ON
2171 23:49:44.302656 [GetDramInforAfterCalByMRR] Vendor 6.
2172 23:49:44.309408 [GetDramInforAfterCalByMRR] Revision 606.
2173 23:49:44.312710 [GetDramInforAfterCalByMRR] Revision 2 0.
2174 23:49:44.313357 MR0 0x3b3b
2175 23:49:44.313922 MR8 0x5151
2176 23:49:44.316141 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 23:49:44.316646
2178 23:49:44.319104 MR0 0x3b3b
2179 23:49:44.319566 MR8 0x5151
2180 23:49:44.322781 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2181 23:49:44.323304
2182 23:49:44.332707 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2183 23:49:44.335661 [FAST_K] Save calibration result to emmc
2184 23:49:44.339249 [FAST_K] Save calibration result to emmc
2185 23:49:44.342250 dram_init: config_dvfs: 1
2186 23:49:44.345672 dramc_set_vcore_voltage set vcore to 662500
2187 23:49:44.349038 Read voltage for 1200, 2
2188 23:49:44.349519 Vio18 = 0
2189 23:49:44.350006 Vcore = 662500
2190 23:49:44.352827 Vdram = 0
2191 23:49:44.353308 Vddq = 0
2192 23:49:44.353787 Vmddr = 0
2193 23:49:44.359108 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2194 23:49:44.362587 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2195 23:49:44.366190 MEM_TYPE=3, freq_sel=15
2196 23:49:44.369126 sv_algorithm_assistance_LP4_1600
2197 23:49:44.372627 ============ PULL DRAM RESETB DOWN ============
2198 23:49:44.376097 ========== PULL DRAM RESETB DOWN end =========
2199 23:49:44.382374 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2200 23:49:44.385620 ===================================
2201 23:49:44.386085 LPDDR4 DRAM CONFIGURATION
2202 23:49:44.388889 ===================================
2203 23:49:44.392476 EX_ROW_EN[0] = 0x0
2204 23:49:44.396060 EX_ROW_EN[1] = 0x0
2205 23:49:44.396521 LP4Y_EN = 0x0
2206 23:49:44.399374 WORK_FSP = 0x0
2207 23:49:44.399788 WL = 0x4
2208 23:49:44.402190 RL = 0x4
2209 23:49:44.402608 BL = 0x2
2210 23:49:44.405860 RPST = 0x0
2211 23:49:44.406279 RD_PRE = 0x0
2212 23:49:44.409181 WR_PRE = 0x1
2213 23:49:44.409597 WR_PST = 0x0
2214 23:49:44.412479 DBI_WR = 0x0
2215 23:49:44.412927 DBI_RD = 0x0
2216 23:49:44.416159 OTF = 0x1
2217 23:49:44.418904 ===================================
2218 23:49:44.422642 ===================================
2219 23:49:44.423065 ANA top config
2220 23:49:44.426007 ===================================
2221 23:49:44.429199 DLL_ASYNC_EN = 0
2222 23:49:44.432628 ALL_SLAVE_EN = 0
2223 23:49:44.433048 NEW_RANK_MODE = 1
2224 23:49:44.435977 DLL_IDLE_MODE = 1
2225 23:49:44.439229 LP45_APHY_COMB_EN = 1
2226 23:49:44.442723 TX_ODT_DIS = 1
2227 23:49:44.443190 NEW_8X_MODE = 1
2228 23:49:44.446160 ===================================
2229 23:49:44.449192 ===================================
2230 23:49:44.452752 data_rate = 2400
2231 23:49:44.455795 CKR = 1
2232 23:49:44.458963 DQ_P2S_RATIO = 8
2233 23:49:44.462292 ===================================
2234 23:49:44.465755 CA_P2S_RATIO = 8
2235 23:49:44.469148 DQ_CA_OPEN = 0
2236 23:49:44.469565 DQ_SEMI_OPEN = 0
2237 23:49:44.472462 CA_SEMI_OPEN = 0
2238 23:49:44.476009 CA_FULL_RATE = 0
2239 23:49:44.478927 DQ_CKDIV4_EN = 0
2240 23:49:44.482401 CA_CKDIV4_EN = 0
2241 23:49:44.485707 CA_PREDIV_EN = 0
2242 23:49:44.486148 PH8_DLY = 17
2243 23:49:44.489241 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2244 23:49:44.492514 DQ_AAMCK_DIV = 4
2245 23:49:44.495890 CA_AAMCK_DIV = 4
2246 23:49:44.499058 CA_ADMCK_DIV = 4
2247 23:49:44.502664 DQ_TRACK_CA_EN = 0
2248 23:49:44.503120 CA_PICK = 1200
2249 23:49:44.505702 CA_MCKIO = 1200
2250 23:49:44.508951 MCKIO_SEMI = 0
2251 23:49:44.512499 PLL_FREQ = 2366
2252 23:49:44.515876 DQ_UI_PI_RATIO = 32
2253 23:49:44.519310 CA_UI_PI_RATIO = 0
2254 23:49:44.522462 ===================================
2255 23:49:44.526257 ===================================
2256 23:49:44.529198 memory_type:LPDDR4
2257 23:49:44.529879 GP_NUM : 10
2258 23:49:44.532366 SRAM_EN : 1
2259 23:49:44.532864 MD32_EN : 0
2260 23:49:44.535750 ===================================
2261 23:49:44.539256 [ANA_INIT] >>>>>>>>>>>>>>
2262 23:49:44.542843 <<<<<< [CONFIGURE PHASE]: ANA_TX
2263 23:49:44.546213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2264 23:49:44.549008 ===================================
2265 23:49:44.552524 data_rate = 2400,PCW = 0X5b00
2266 23:49:44.555970 ===================================
2267 23:49:44.559208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2268 23:49:44.562693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 23:49:44.569254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 23:49:44.572766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2271 23:49:44.576247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2272 23:49:44.579108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2273 23:49:44.582762 [ANA_INIT] flow start
2274 23:49:44.586087 [ANA_INIT] PLL >>>>>>>>
2275 23:49:44.586526 [ANA_INIT] PLL <<<<<<<<
2276 23:49:44.589394 [ANA_INIT] MIDPI >>>>>>>>
2277 23:49:44.592402 [ANA_INIT] MIDPI <<<<<<<<
2278 23:49:44.595814 [ANA_INIT] DLL >>>>>>>>
2279 23:49:44.596262 [ANA_INIT] DLL <<<<<<<<
2280 23:49:44.598977 [ANA_INIT] flow end
2281 23:49:44.602288 ============ LP4 DIFF to SE enter ============
2282 23:49:44.606008 ============ LP4 DIFF to SE exit ============
2283 23:49:44.609033 [ANA_INIT] <<<<<<<<<<<<<
2284 23:49:44.612235 [Flow] Enable top DCM control >>>>>
2285 23:49:44.615814 [Flow] Enable top DCM control <<<<<
2286 23:49:44.619329 Enable DLL master slave shuffle
2287 23:49:44.625569 ==============================================================
2288 23:49:44.626013 Gating Mode config
2289 23:49:44.632313 ==============================================================
2290 23:49:44.632941 Config description:
2291 23:49:44.642211 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2292 23:49:44.648711 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2293 23:49:44.655528 SELPH_MODE 0: By rank 1: By Phase
2294 23:49:44.658804 ==============================================================
2295 23:49:44.662136 GAT_TRACK_EN = 1
2296 23:49:44.665756 RX_GATING_MODE = 2
2297 23:49:44.668634 RX_GATING_TRACK_MODE = 2
2298 23:49:44.672130 SELPH_MODE = 1
2299 23:49:44.675960 PICG_EARLY_EN = 1
2300 23:49:44.678758 VALID_LAT_VALUE = 1
2301 23:49:44.682249 ==============================================================
2302 23:49:44.688552 Enter into Gating configuration >>>>
2303 23:49:44.689128 Exit from Gating configuration <<<<
2304 23:49:44.692145 Enter into DVFS_PRE_config >>>>>
2305 23:49:44.705435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2306 23:49:44.708993 Exit from DVFS_PRE_config <<<<<
2307 23:49:44.712034 Enter into PICG configuration >>>>
2308 23:49:44.712668 Exit from PICG configuration <<<<
2309 23:49:44.715479 [RX_INPUT] configuration >>>>>
2310 23:49:44.718616 [RX_INPUT] configuration <<<<<
2311 23:49:44.725681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2312 23:49:44.729121 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2313 23:49:44.735371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 23:49:44.742009 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 23:49:44.748711 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 23:49:44.755177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 23:49:44.758697 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2318 23:49:44.762419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2319 23:49:44.765062 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2320 23:49:44.772197 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2321 23:49:44.775541 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2322 23:49:44.778888 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 23:49:44.782176 ===================================
2324 23:49:44.785478 LPDDR4 DRAM CONFIGURATION
2325 23:49:44.789040 ===================================
2326 23:49:44.791756 EX_ROW_EN[0] = 0x0
2327 23:49:44.792179 EX_ROW_EN[1] = 0x0
2328 23:49:44.795321 LP4Y_EN = 0x0
2329 23:49:44.795896 WORK_FSP = 0x0
2330 23:49:44.798869 WL = 0x4
2331 23:49:44.799449 RL = 0x4
2332 23:49:44.802059 BL = 0x2
2333 23:49:44.802569 RPST = 0x0
2334 23:49:44.805680 RD_PRE = 0x0
2335 23:49:44.806147 WR_PRE = 0x1
2336 23:49:44.808293 WR_PST = 0x0
2337 23:49:44.808808 DBI_WR = 0x0
2338 23:49:44.811809 DBI_RD = 0x0
2339 23:49:44.812275 OTF = 0x1
2340 23:49:44.815011 ===================================
2341 23:49:44.821653 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2342 23:49:44.824909 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2343 23:49:44.828598 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2344 23:49:44.832332 ===================================
2345 23:49:44.835011 LPDDR4 DRAM CONFIGURATION
2346 23:49:44.838397 ===================================
2347 23:49:44.838865 EX_ROW_EN[0] = 0x10
2348 23:49:44.841816 EX_ROW_EN[1] = 0x0
2349 23:49:44.845193 LP4Y_EN = 0x0
2350 23:49:44.845657 WORK_FSP = 0x0
2351 23:49:44.848324 WL = 0x4
2352 23:49:44.848928 RL = 0x4
2353 23:49:44.851653 BL = 0x2
2354 23:49:44.852135 RPST = 0x0
2355 23:49:44.855135 RD_PRE = 0x0
2356 23:49:44.855728 WR_PRE = 0x1
2357 23:49:44.858459 WR_PST = 0x0
2358 23:49:44.858939 DBI_WR = 0x0
2359 23:49:44.861618 DBI_RD = 0x0
2360 23:49:44.862222 OTF = 0x1
2361 23:49:44.865005 ===================================
2362 23:49:44.871769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2363 23:49:44.872307 ==
2364 23:49:44.875083 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 23:49:44.878170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 23:49:44.881623 ==
2367 23:49:44.881867 [Duty_Offset_Calibration]
2368 23:49:44.884920 B0:2 B1:0 CA:3
2369 23:49:44.885112
2370 23:49:44.887960 [DutyScan_Calibration_Flow] k_type=0
2371 23:49:44.896353
2372 23:49:44.896551 ==CLK 0==
2373 23:49:44.899832 Final CLK duty delay cell = 0
2374 23:49:44.903424 [0] MAX Duty = 5062%(X100), DQS PI = 20
2375 23:49:44.906842 [0] MIN Duty = 4906%(X100), DQS PI = 54
2376 23:49:44.907114 [0] AVG Duty = 4984%(X100)
2377 23:49:44.909546
2378 23:49:44.913016 CH0 CLK Duty spec in!! Max-Min= 156%
2379 23:49:44.916322 [DutyScan_Calibration_Flow] ====Done====
2380 23:49:44.916629
2381 23:49:44.919988 [DutyScan_Calibration_Flow] k_type=1
2382 23:49:44.934942
2383 23:49:44.935423 ==DQS 0 ==
2384 23:49:44.938788 Final DQS duty delay cell = 0
2385 23:49:44.942014 [0] MAX Duty = 5062%(X100), DQS PI = 12
2386 23:49:44.945293 [0] MIN Duty = 4907%(X100), DQS PI = 44
2387 23:49:44.948350 [0] AVG Duty = 4984%(X100)
2388 23:49:44.948918
2389 23:49:44.949313 ==DQS 1 ==
2390 23:49:44.951845 Final DQS duty delay cell = -4
2391 23:49:44.955646 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2392 23:49:44.958974 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2393 23:49:44.962094 [-4] AVG Duty = 4937%(X100)
2394 23:49:44.962565
2395 23:49:44.965382 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2396 23:49:44.965845
2397 23:49:44.968408 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2398 23:49:44.971812 [DutyScan_Calibration_Flow] ====Done====
2399 23:49:44.972277
2400 23:49:44.975551 [DutyScan_Calibration_Flow] k_type=3
2401 23:49:44.992748
2402 23:49:44.993219 ==DQM 0 ==
2403 23:49:44.996067 Final DQM duty delay cell = 0
2404 23:49:44.999370 [0] MAX Duty = 5124%(X100), DQS PI = 28
2405 23:49:45.003048 [0] MIN Duty = 4876%(X100), DQS PI = 48
2406 23:49:45.003622 [0] AVG Duty = 5000%(X100)
2407 23:49:45.006235
2408 23:49:45.006654 ==DQM 1 ==
2409 23:49:45.009534 Final DQM duty delay cell = 4
2410 23:49:45.013145 [4] MAX Duty = 5124%(X100), DQS PI = 50
2411 23:49:45.016152 [4] MIN Duty = 5000%(X100), DQS PI = 14
2412 23:49:45.019261 [4] AVG Duty = 5062%(X100)
2413 23:49:45.019665
2414 23:49:45.022673 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2415 23:49:45.023052
2416 23:49:45.025932 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2417 23:49:45.029400 [DutyScan_Calibration_Flow] ====Done====
2418 23:49:45.029834
2419 23:49:45.033258 [DutyScan_Calibration_Flow] k_type=2
2420 23:49:45.048138
2421 23:49:45.048760 ==DQ 0 ==
2422 23:49:45.051263 Final DQ duty delay cell = -4
2423 23:49:45.054180 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2424 23:49:45.057628 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2425 23:49:45.061124 [-4] AVG Duty = 4969%(X100)
2426 23:49:45.061591
2427 23:49:45.061995 ==DQ 1 ==
2428 23:49:45.064255 Final DQ duty delay cell = -4
2429 23:49:45.067408 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2430 23:49:45.070983 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2431 23:49:45.074194 [-4] AVG Duty = 4922%(X100)
2432 23:49:45.074619
2433 23:49:45.077397 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2434 23:49:45.078049
2435 23:49:45.081079 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2436 23:49:45.084507 [DutyScan_Calibration_Flow] ====Done====
2437 23:49:45.084978 ==
2438 23:49:45.088025 Dram Type= 6, Freq= 0, CH_1, rank 0
2439 23:49:45.090748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 23:49:45.091184 ==
2441 23:49:45.094197 [Duty_Offset_Calibration]
2442 23:49:45.094628 B0:1 B1:-2 CA:1
2443 23:49:45.094974
2444 23:49:45.097415 [DutyScan_Calibration_Flow] k_type=0
2445 23:49:45.108123
2446 23:49:45.108597 ==CLK 0==
2447 23:49:45.111454 Final CLK duty delay cell = 0
2448 23:49:45.114859 [0] MAX Duty = 5062%(X100), DQS PI = 30
2449 23:49:45.118342 [0] MIN Duty = 4875%(X100), DQS PI = 0
2450 23:49:45.118767 [0] AVG Duty = 4968%(X100)
2451 23:49:45.121323
2452 23:49:45.121845 CH1 CLK Duty spec in!! Max-Min= 187%
2453 23:49:45.128420 [DutyScan_Calibration_Flow] ====Done====
2454 23:49:45.128948
2455 23:49:45.131751 [DutyScan_Calibration_Flow] k_type=1
2456 23:49:45.146798
2457 23:49:45.147242 ==DQS 0 ==
2458 23:49:45.150003 Final DQS duty delay cell = -4
2459 23:49:45.153748 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2460 23:49:45.156532 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2461 23:49:45.160050 [-4] AVG Duty = 4953%(X100)
2462 23:49:45.160474
2463 23:49:45.160875 ==DQS 1 ==
2464 23:49:45.163563 Final DQS duty delay cell = 0
2465 23:49:45.166488 [0] MAX Duty = 5062%(X100), DQS PI = 0
2466 23:49:45.169922 [0] MIN Duty = 4875%(X100), DQS PI = 26
2467 23:49:45.173105 [0] AVG Duty = 4968%(X100)
2468 23:49:45.173550
2469 23:49:45.176738 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2470 23:49:45.177176
2471 23:49:45.180200 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2472 23:49:45.183316 [DutyScan_Calibration_Flow] ====Done====
2473 23:49:45.183745
2474 23:49:45.186844 [DutyScan_Calibration_Flow] k_type=3
2475 23:49:45.203098
2476 23:49:45.203523 ==DQM 0 ==
2477 23:49:45.206719 Final DQM duty delay cell = 0
2478 23:49:45.209801 [0] MAX Duty = 5000%(X100), DQS PI = 22
2479 23:49:45.213092 [0] MIN Duty = 4876%(X100), DQS PI = 2
2480 23:49:45.213521 [0] AVG Duty = 4938%(X100)
2481 23:49:45.216640
2482 23:49:45.217064 ==DQM 1 ==
2483 23:49:45.219930 Final DQM duty delay cell = 0
2484 23:49:45.223478 [0] MAX Duty = 5031%(X100), DQS PI = 36
2485 23:49:45.226613 [0] MIN Duty = 4907%(X100), DQS PI = 2
2486 23:49:45.227058 [0] AVG Duty = 4969%(X100)
2487 23:49:45.229933
2488 23:49:45.233257 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2489 23:49:45.233758
2490 23:49:45.236839 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2491 23:49:45.239992 [DutyScan_Calibration_Flow] ====Done====
2492 23:49:45.240417
2493 23:49:45.243118 [DutyScan_Calibration_Flow] k_type=2
2494 23:49:45.259580
2495 23:49:45.260127 ==DQ 0 ==
2496 23:49:45.262835 Final DQ duty delay cell = 0
2497 23:49:45.266156 [0] MAX Duty = 5062%(X100), DQS PI = 18
2498 23:49:45.269903 [0] MIN Duty = 4938%(X100), DQS PI = 54
2499 23:49:45.270507 [0] AVG Duty = 5000%(X100)
2500 23:49:45.273290
2501 23:49:45.273764 ==DQ 1 ==
2502 23:49:45.276315 Final DQ duty delay cell = 0
2503 23:49:45.279480 [0] MAX Duty = 5125%(X100), DQS PI = 36
2504 23:49:45.283134 [0] MIN Duty = 4969%(X100), DQS PI = 26
2505 23:49:45.283610 [0] AVG Duty = 5047%(X100)
2506 23:49:45.283988
2507 23:49:45.286199 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2508 23:49:45.289326
2509 23:49:45.293133 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2510 23:49:45.296146 [DutyScan_Calibration_Flow] ====Done====
2511 23:49:45.299708 nWR fixed to 30
2512 23:49:45.300177 [ModeRegInit_LP4] CH0 RK0
2513 23:49:45.303028 [ModeRegInit_LP4] CH0 RK1
2514 23:49:45.306543 [ModeRegInit_LP4] CH1 RK0
2515 23:49:45.307010 [ModeRegInit_LP4] CH1 RK1
2516 23:49:45.309868 match AC timing 7
2517 23:49:45.313164 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2518 23:49:45.316792 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2519 23:49:45.323002 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2520 23:49:45.326573 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2521 23:49:45.333638 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2522 23:49:45.334193 ==
2523 23:49:45.336250 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 23:49:45.339903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 23:49:45.340373 ==
2526 23:49:45.346331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 23:49:45.349699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2528 23:49:45.359648 [CA 0] Center 40 (10~71) winsize 62
2529 23:49:45.363010 [CA 1] Center 39 (9~70) winsize 62
2530 23:49:45.366414 [CA 2] Center 36 (6~66) winsize 61
2531 23:49:45.369903 [CA 3] Center 35 (5~66) winsize 62
2532 23:49:45.373225 [CA 4] Center 34 (4~65) winsize 62
2533 23:49:45.376255 [CA 5] Center 33 (3~63) winsize 61
2534 23:49:45.376821
2535 23:49:45.379649 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2536 23:49:45.380375
2537 23:49:45.383092 [CATrainingPosCal] consider 1 rank data
2538 23:49:45.386343 u2DelayCellTimex100 = 270/100 ps
2539 23:49:45.389592 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2540 23:49:45.396510 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2541 23:49:45.399591 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2542 23:49:45.403462 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2543 23:49:45.406069 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2544 23:49:45.410227 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2545 23:49:45.410730
2546 23:49:45.413280 CA PerBit enable=1, Macro0, CA PI delay=33
2547 23:49:45.413759
2548 23:49:45.416131 [CBTSetCACLKResult] CA Dly = 33
2549 23:49:45.416664 CS Dly: 7 (0~38)
2550 23:49:45.419978 ==
2551 23:49:45.423185 Dram Type= 6, Freq= 0, CH_0, rank 1
2552 23:49:45.425970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 23:49:45.426470 ==
2554 23:49:45.429343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2555 23:49:45.436425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2556 23:49:45.446031 [CA 0] Center 40 (10~71) winsize 62
2557 23:49:45.449373 [CA 1] Center 40 (10~70) winsize 61
2558 23:49:45.452723 [CA 2] Center 35 (5~66) winsize 62
2559 23:49:45.455556 [CA 3] Center 35 (5~66) winsize 62
2560 23:49:45.459155 [CA 4] Center 34 (4~65) winsize 62
2561 23:49:45.462646 [CA 5] Center 33 (3~63) winsize 61
2562 23:49:45.463228
2563 23:49:45.465663 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2564 23:49:45.466199
2565 23:49:45.469186 [CATrainingPosCal] consider 2 rank data
2566 23:49:45.472602 u2DelayCellTimex100 = 270/100 ps
2567 23:49:45.475474 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2568 23:49:45.482314 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2569 23:49:45.486039 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2570 23:49:45.489310 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2571 23:49:45.492504 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2572 23:49:45.495956 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2573 23:49:45.496587
2574 23:49:45.499272 CA PerBit enable=1, Macro0, CA PI delay=33
2575 23:49:45.499756
2576 23:49:45.502516 [CBTSetCACLKResult] CA Dly = 33
2577 23:49:45.502987 CS Dly: 7 (0~39)
2578 23:49:45.506056
2579 23:49:45.509241 ----->DramcWriteLeveling(PI) begin...
2580 23:49:45.509729 ==
2581 23:49:45.512532 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 23:49:45.516029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 23:49:45.516720 ==
2584 23:49:45.519534 Write leveling (Byte 0): 31 => 31
2585 23:49:45.522308 Write leveling (Byte 1): 31 => 31
2586 23:49:45.526140 DramcWriteLeveling(PI) end<-----
2587 23:49:45.526612
2588 23:49:45.527021 ==
2589 23:49:45.529080 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 23:49:45.532504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 23:49:45.533032 ==
2592 23:49:45.536035 [Gating] SW mode calibration
2593 23:49:45.542255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2594 23:49:45.549209 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2595 23:49:45.552767 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2596 23:49:45.556011 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2597 23:49:45.562159 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 23:49:45.565643 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 23:49:45.569015 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 23:49:45.572605 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 23:49:45.578966 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 23:49:45.582286 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2603 23:49:45.585786 1 0 0 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
2604 23:49:45.592013 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2605 23:49:45.595244 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 23:49:45.598733 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 23:49:45.605379 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 23:49:45.608875 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 23:49:45.611950 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 23:49:45.618922 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2611 23:49:45.622312 1 1 0 | B1->B0 | 2b2b 3535 | 0 1 | (0 0) (1 1)
2612 23:49:45.625606 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2613 23:49:45.631913 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 23:49:45.635179 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 23:49:45.638766 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 23:49:45.645012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 23:49:45.648674 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 23:49:45.652096 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2619 23:49:45.659039 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2620 23:49:45.661644 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2621 23:49:45.665425 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:49:45.671829 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:49:45.675142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:49:45.678730 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:49:45.685083 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:49:45.688664 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 23:49:45.691990 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 23:49:45.698688 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 23:49:45.702201 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 23:49:45.705739 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 23:49:45.708642 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 23:49:45.715482 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 23:49:45.718691 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 23:49:45.722151 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2635 23:49:45.728996 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2636 23:49:45.731959 Total UI for P1: 0, mck2ui 16
2637 23:49:45.735289 best dqsien dly found for B0: ( 1, 3, 28)
2638 23:49:45.738665 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2639 23:49:45.741734 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 23:49:45.745047 Total UI for P1: 0, mck2ui 16
2641 23:49:45.748337 best dqsien dly found for B1: ( 1, 4, 2)
2642 23:49:45.751996 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2643 23:49:45.755562 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2644 23:49:45.756278
2645 23:49:45.761923 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2646 23:49:45.765224 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2647 23:49:45.765668 [Gating] SW calibration Done
2648 23:49:45.769080 ==
2649 23:49:45.769507 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 23:49:45.775849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 23:49:45.776408 ==
2652 23:49:45.776815 RX Vref Scan: 0
2653 23:49:45.777143
2654 23:49:45.778616 RX Vref 0 -> 0, step: 1
2655 23:49:45.779068
2656 23:49:45.782039 RX Delay -40 -> 252, step: 8
2657 23:49:45.785281 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2658 23:49:45.788762 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2659 23:49:45.792325 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2660 23:49:45.799129 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2661 23:49:45.801850 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2662 23:49:45.805142 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2663 23:49:45.808758 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2664 23:49:45.812155 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2665 23:49:45.818650 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2666 23:49:45.821993 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2667 23:49:45.825542 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2668 23:49:45.828519 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2669 23:49:45.831862 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2670 23:49:45.835203 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2671 23:49:45.842292 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2672 23:49:45.845434 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2673 23:49:45.845901 ==
2674 23:49:45.848887 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 23:49:45.851807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 23:49:45.852274 ==
2677 23:49:45.854989 DQS Delay:
2678 23:49:45.855407 DQS0 = 0, DQS1 = 0
2679 23:49:45.855739 DQM Delay:
2680 23:49:45.858522 DQM0 = 112, DQM1 = 102
2681 23:49:45.858943 DQ Delay:
2682 23:49:45.861934 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2683 23:49:45.865228 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2684 23:49:45.868629 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2685 23:49:45.875252 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2686 23:49:45.875782
2687 23:49:45.876153
2688 23:49:45.876463 ==
2689 23:49:45.878638 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 23:49:45.881747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 23:49:45.882172 ==
2692 23:49:45.882668
2693 23:49:45.883110
2694 23:49:45.885129 TX Vref Scan disable
2695 23:49:45.885632 == TX Byte 0 ==
2696 23:49:45.891765 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2697 23:49:45.895234 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2698 23:49:45.895656 == TX Byte 1 ==
2699 23:49:45.902194 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2700 23:49:45.905365 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2701 23:49:45.905789 ==
2702 23:49:45.908737 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 23:49:45.911693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 23:49:45.912293 ==
2705 23:49:45.924244 TX Vref=22, minBit 4, minWin=25, winSum=415
2706 23:49:45.927892 TX Vref=24, minBit 0, minWin=26, winSum=423
2707 23:49:45.931409 TX Vref=26, minBit 4, minWin=26, winSum=429
2708 23:49:45.934404 TX Vref=28, minBit 12, minWin=26, winSum=434
2709 23:49:45.937668 TX Vref=30, minBit 1, minWin=27, winSum=436
2710 23:49:45.944284 TX Vref=32, minBit 2, minWin=26, winSum=427
2711 23:49:45.947637 [TxChooseVref] Worse bit 1, Min win 27, Win sum 436, Final Vref 30
2712 23:49:45.948070
2713 23:49:45.950979 Final TX Range 1 Vref 30
2714 23:49:45.951438
2715 23:49:45.951863 ==
2716 23:49:45.954419 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 23:49:45.958217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 23:49:45.958753 ==
2719 23:49:45.960930
2720 23:49:45.961361
2721 23:49:45.961799 TX Vref Scan disable
2722 23:49:45.964311 == TX Byte 0 ==
2723 23:49:45.967883 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2724 23:49:45.971272 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2725 23:49:45.974256 == TX Byte 1 ==
2726 23:49:45.977878 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2727 23:49:45.981298 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2728 23:49:45.981957
2729 23:49:45.984777 [DATLAT]
2730 23:49:45.985349 Freq=1200, CH0 RK0
2731 23:49:45.985788
2732 23:49:45.987705 DATLAT Default: 0xd
2733 23:49:45.988218 0, 0xFFFF, sum = 0
2734 23:49:45.991337 1, 0xFFFF, sum = 0
2735 23:49:45.992004 2, 0xFFFF, sum = 0
2736 23:49:45.994528 3, 0xFFFF, sum = 0
2737 23:49:45.995159 4, 0xFFFF, sum = 0
2738 23:49:45.997558 5, 0xFFFF, sum = 0
2739 23:49:45.998148 6, 0xFFFF, sum = 0
2740 23:49:46.001275 7, 0xFFFF, sum = 0
2741 23:49:46.001750 8, 0xFFFF, sum = 0
2742 23:49:46.004481 9, 0xFFFF, sum = 0
2743 23:49:46.007994 10, 0xFFFF, sum = 0
2744 23:49:46.008601 11, 0xFFFF, sum = 0
2745 23:49:46.011567 12, 0x0, sum = 1
2746 23:49:46.012114 13, 0x0, sum = 2
2747 23:49:46.012655 14, 0x0, sum = 3
2748 23:49:46.014803 15, 0x0, sum = 4
2749 23:49:46.015296 best_step = 13
2750 23:49:46.015645
2751 23:49:46.016053 ==
2752 23:49:46.018299 Dram Type= 6, Freq= 0, CH_0, rank 0
2753 23:49:46.024524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2754 23:49:46.025142 ==
2755 23:49:46.025493 RX Vref Scan: 1
2756 23:49:46.025995
2757 23:49:46.028048 Set Vref Range= 32 -> 127
2758 23:49:46.028539
2759 23:49:46.030739 RX Vref 32 -> 127, step: 1
2760 23:49:46.031170
2761 23:49:46.034656 RX Delay -37 -> 252, step: 4
2762 23:49:46.035091
2763 23:49:46.037802 Set Vref, RX VrefLevel [Byte0]: 32
2764 23:49:46.041137 [Byte1]: 32
2765 23:49:46.041692
2766 23:49:46.044575 Set Vref, RX VrefLevel [Byte0]: 33
2767 23:49:46.048257 [Byte1]: 33
2768 23:49:46.048868
2769 23:49:46.051593 Set Vref, RX VrefLevel [Byte0]: 34
2770 23:49:46.054237 [Byte1]: 34
2771 23:49:46.058952
2772 23:49:46.059385 Set Vref, RX VrefLevel [Byte0]: 35
2773 23:49:46.062401 [Byte1]: 35
2774 23:49:46.066731
2775 23:49:46.067166 Set Vref, RX VrefLevel [Byte0]: 36
2776 23:49:46.070426 [Byte1]: 36
2777 23:49:46.075257
2778 23:49:46.075795 Set Vref, RX VrefLevel [Byte0]: 37
2779 23:49:46.078505 [Byte1]: 37
2780 23:49:46.083232
2781 23:49:46.083816 Set Vref, RX VrefLevel [Byte0]: 38
2782 23:49:46.086102 [Byte1]: 38
2783 23:49:46.090489
2784 23:49:46.090906 Set Vref, RX VrefLevel [Byte0]: 39
2785 23:49:46.094244 [Byte1]: 39
2786 23:49:46.098823
2787 23:49:46.099262 Set Vref, RX VrefLevel [Byte0]: 40
2788 23:49:46.102162 [Byte1]: 40
2789 23:49:46.106824
2790 23:49:46.107307 Set Vref, RX VrefLevel [Byte0]: 41
2791 23:49:46.113434 [Byte1]: 41
2792 23:49:46.114149
2793 23:49:46.116442 Set Vref, RX VrefLevel [Byte0]: 42
2794 23:49:46.119886 [Byte1]: 42
2795 23:49:46.120417
2796 23:49:46.123222 Set Vref, RX VrefLevel [Byte0]: 43
2797 23:49:46.126630 [Byte1]: 43
2798 23:49:46.131009
2799 23:49:46.131496 Set Vref, RX VrefLevel [Byte0]: 44
2800 23:49:46.133979 [Byte1]: 44
2801 23:49:46.138580
2802 23:49:46.139045 Set Vref, RX VrefLevel [Byte0]: 45
2803 23:49:46.142070 [Byte1]: 45
2804 23:49:46.146629
2805 23:49:46.147108 Set Vref, RX VrefLevel [Byte0]: 46
2806 23:49:46.150118 [Byte1]: 46
2807 23:49:46.155002
2808 23:49:46.155423 Set Vref, RX VrefLevel [Byte0]: 47
2809 23:49:46.157944 [Byte1]: 47
2810 23:49:46.162887
2811 23:49:46.163351 Set Vref, RX VrefLevel [Byte0]: 48
2812 23:49:46.166158 [Byte1]: 48
2813 23:49:46.170631
2814 23:49:46.171054 Set Vref, RX VrefLevel [Byte0]: 49
2815 23:49:46.173971 [Byte1]: 49
2816 23:49:46.178725
2817 23:49:46.179168 Set Vref, RX VrefLevel [Byte0]: 50
2818 23:49:46.182136 [Byte1]: 50
2819 23:49:46.186799
2820 23:49:46.187231 Set Vref, RX VrefLevel [Byte0]: 51
2821 23:49:46.190295 [Byte1]: 51
2822 23:49:46.194637
2823 23:49:46.195059 Set Vref, RX VrefLevel [Byte0]: 52
2824 23:49:46.197832 [Byte1]: 52
2825 23:49:46.202761
2826 23:49:46.203193 Set Vref, RX VrefLevel [Byte0]: 53
2827 23:49:46.206193 [Byte1]: 53
2828 23:49:46.210945
2829 23:49:46.211491 Set Vref, RX VrefLevel [Byte0]: 54
2830 23:49:46.214242 [Byte1]: 54
2831 23:49:46.218826
2832 23:49:46.219391 Set Vref, RX VrefLevel [Byte0]: 55
2833 23:49:46.222098 [Byte1]: 55
2834 23:49:46.226780
2835 23:49:46.227248 Set Vref, RX VrefLevel [Byte0]: 56
2836 23:49:46.230241 [Byte1]: 56
2837 23:49:46.234511
2838 23:49:46.234977 Set Vref, RX VrefLevel [Byte0]: 57
2839 23:49:46.238009 [Byte1]: 57
2840 23:49:46.242634
2841 23:49:46.243049 Set Vref, RX VrefLevel [Byte0]: 58
2842 23:49:46.246271 [Byte1]: 58
2843 23:49:46.250836
2844 23:49:46.251299 Set Vref, RX VrefLevel [Byte0]: 59
2845 23:49:46.254586 [Byte1]: 59
2846 23:49:46.258696
2847 23:49:46.259235 Set Vref, RX VrefLevel [Byte0]: 60
2848 23:49:46.262256 [Byte1]: 60
2849 23:49:46.266473
2850 23:49:46.266925 Set Vref, RX VrefLevel [Byte0]: 61
2851 23:49:46.269941 [Byte1]: 61
2852 23:49:46.275216
2853 23:49:46.275632 Set Vref, RX VrefLevel [Byte0]: 62
2854 23:49:46.278049 [Byte1]: 62
2855 23:49:46.282778
2856 23:49:46.283206 Set Vref, RX VrefLevel [Byte0]: 63
2857 23:49:46.286270 [Byte1]: 63
2858 23:49:46.290676
2859 23:49:46.291123 Set Vref, RX VrefLevel [Byte0]: 64
2860 23:49:46.293908 [Byte1]: 64
2861 23:49:46.298691
2862 23:49:46.299143 Set Vref, RX VrefLevel [Byte0]: 65
2863 23:49:46.302188 [Byte1]: 65
2864 23:49:46.306598
2865 23:49:46.307022 Set Vref, RX VrefLevel [Byte0]: 66
2866 23:49:46.310082 [Byte1]: 66
2867 23:49:46.314589
2868 23:49:46.315039 Set Vref, RX VrefLevel [Byte0]: 67
2869 23:49:46.318115 [Byte1]: 67
2870 23:49:46.322840
2871 23:49:46.323356 Set Vref, RX VrefLevel [Byte0]: 68
2872 23:49:46.326012 [Byte1]: 68
2873 23:49:46.330761
2874 23:49:46.331279 Set Vref, RX VrefLevel [Byte0]: 69
2875 23:49:46.334097 [Byte1]: 69
2876 23:49:46.338859
2877 23:49:46.339295 Set Vref, RX VrefLevel [Byte0]: 70
2878 23:49:46.341926 [Byte1]: 70
2879 23:49:46.347061
2880 23:49:46.347510 Set Vref, RX VrefLevel [Byte0]: 71
2881 23:49:46.350069 [Byte1]: 71
2882 23:49:46.355030
2883 23:49:46.355579 Set Vref, RX VrefLevel [Byte0]: 72
2884 23:49:46.358265 [Byte1]: 72
2885 23:49:46.363119
2886 23:49:46.363641 Set Vref, RX VrefLevel [Byte0]: 73
2887 23:49:46.366241 [Byte1]: 73
2888 23:49:46.370682
2889 23:49:46.371160 Set Vref, RX VrefLevel [Byte0]: 74
2890 23:49:46.377569 [Byte1]: 74
2891 23:49:46.378085
2892 23:49:46.380921 Final RX Vref Byte 0 = 60 to rank0
2893 23:49:46.384226 Final RX Vref Byte 1 = 47 to rank0
2894 23:49:46.387389 Final RX Vref Byte 0 = 60 to rank1
2895 23:49:46.390640 Final RX Vref Byte 1 = 47 to rank1==
2896 23:49:46.393997 Dram Type= 6, Freq= 0, CH_0, rank 0
2897 23:49:46.397094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 23:49:46.397552 ==
2899 23:49:46.397908 DQS Delay:
2900 23:49:46.400766 DQS0 = 0, DQS1 = 0
2901 23:49:46.401181 DQM Delay:
2902 23:49:46.403898 DQM0 = 112, DQM1 = 98
2903 23:49:46.404347 DQ Delay:
2904 23:49:46.406978 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2905 23:49:46.410415 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2906 23:49:46.413810 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =90
2907 23:49:46.417033 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2908 23:49:46.417499
2909 23:49:46.417828
2910 23:49:46.427037 [DQSOSCAuto] RK0, (LSB)MR18= 0x0, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2911 23:49:46.427741 CH0 RK0: MR19=404, MR18=0
2912 23:49:46.433630 CH0_RK0: MR19=0x404, MR18=0x0, DQSOSC=410, MR23=63, INC=39, DEC=26
2913 23:49:46.434064
2914 23:49:46.437219 ----->DramcWriteLeveling(PI) begin...
2915 23:49:46.437664 ==
2916 23:49:46.440658 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 23:49:46.447106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 23:49:46.447534 ==
2919 23:49:46.450533 Write leveling (Byte 0): 31 => 31
2920 23:49:46.450983 Write leveling (Byte 1): 31 => 31
2921 23:49:46.453997 DramcWriteLeveling(PI) end<-----
2922 23:49:46.454434
2923 23:49:46.454774 ==
2924 23:49:46.457515 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 23:49:46.463936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 23:49:46.464380 ==
2927 23:49:46.467774 [Gating] SW mode calibration
2928 23:49:46.473786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2929 23:49:46.477165 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2930 23:49:46.483936 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2931 23:49:46.487152 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 23:49:46.490668 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 23:49:46.497539 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 23:49:46.500961 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 23:49:46.504039 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 23:49:46.507103 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2937 23:49:46.514250 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
2938 23:49:46.517322 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2939 23:49:46.520670 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 23:49:46.527245 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 23:49:46.530762 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 23:49:46.533905 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 23:49:46.540655 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 23:49:46.544246 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2945 23:49:46.547553 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2946 23:49:46.554105 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2947 23:49:46.557461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 23:49:46.560984 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 23:49:46.567256 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 23:49:46.570652 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 23:49:46.574193 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 23:49:46.580939 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2953 23:49:46.584386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2954 23:49:46.587720 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2955 23:49:46.590657 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 23:49:46.597482 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 23:49:46.601005 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 23:49:46.604323 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 23:49:46.610845 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 23:49:46.614412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 23:49:46.617903 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 23:49:46.624387 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 23:49:46.627614 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 23:49:46.631061 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 23:49:46.637465 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 23:49:46.640553 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 23:49:46.644228 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 23:49:46.651030 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 23:49:46.654515 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2970 23:49:46.657651 Total UI for P1: 0, mck2ui 16
2971 23:49:46.660928 best dqsien dly found for B0: ( 1, 3, 26)
2972 23:49:46.664409 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 23:49:46.667157 Total UI for P1: 0, mck2ui 16
2974 23:49:46.670913 best dqsien dly found for B1: ( 1, 3, 28)
2975 23:49:46.674229 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2976 23:49:46.677497 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2977 23:49:46.677942
2978 23:49:46.680817 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2979 23:49:46.687298 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2980 23:49:46.687969 [Gating] SW calibration Done
2981 23:49:46.688366 ==
2982 23:49:46.691050 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 23:49:46.697406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 23:49:46.697875 ==
2985 23:49:46.698287 RX Vref Scan: 0
2986 23:49:46.698634
2987 23:49:46.701016 RX Vref 0 -> 0, step: 1
2988 23:49:46.701516
2989 23:49:46.704076 RX Delay -40 -> 252, step: 8
2990 23:49:46.707713 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2991 23:49:46.710702 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2992 23:49:46.713983 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2993 23:49:46.720688 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2994 23:49:46.724208 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2995 23:49:46.727365 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2996 23:49:46.730997 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2997 23:49:46.733907 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2998 23:49:46.737658 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2999 23:49:46.743897 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3000 23:49:46.747283 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3001 23:49:46.750820 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
3002 23:49:46.754173 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3003 23:49:46.757383 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
3004 23:49:46.763919 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3005 23:49:46.767452 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3006 23:49:46.767878 ==
3007 23:49:46.770589 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 23:49:46.774088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 23:49:46.774538 ==
3010 23:49:46.777328 DQS Delay:
3011 23:49:46.777842 DQS0 = 0, DQS1 = 0
3012 23:49:46.778275 DQM Delay:
3013 23:49:46.780759 DQM0 = 113, DQM1 = 100
3014 23:49:46.781237 DQ Delay:
3015 23:49:46.784198 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3016 23:49:46.787697 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
3017 23:49:46.790534 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
3018 23:49:46.797293 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
3019 23:49:46.797858
3020 23:49:46.798401
3021 23:49:46.798872 ==
3022 23:49:46.800767 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 23:49:46.804596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 23:49:46.805063 ==
3025 23:49:46.805454
3026 23:49:46.805920
3027 23:49:46.807422 TX Vref Scan disable
3028 23:49:46.807800 == TX Byte 0 ==
3029 23:49:46.814233 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3030 23:49:46.817125 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3031 23:49:46.817573 == TX Byte 1 ==
3032 23:49:46.824275 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3033 23:49:46.827411 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3034 23:49:46.827871 ==
3035 23:49:46.830841 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 23:49:46.833733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 23:49:46.834215 ==
3038 23:49:46.846235 TX Vref=22, minBit 0, minWin=26, winSum=422
3039 23:49:46.849909 TX Vref=24, minBit 1, minWin=26, winSum=424
3040 23:49:46.853331 TX Vref=26, minBit 5, minWin=26, winSum=432
3041 23:49:46.856408 TX Vref=28, minBit 0, minWin=27, winSum=443
3042 23:49:46.859830 TX Vref=30, minBit 2, minWin=27, winSum=440
3043 23:49:46.862907 TX Vref=32, minBit 13, minWin=26, winSum=439
3044 23:49:46.869777 [TxChooseVref] Worse bit 0, Min win 27, Win sum 443, Final Vref 28
3045 23:49:46.870231
3046 23:49:46.873346 Final TX Range 1 Vref 28
3047 23:49:46.873804
3048 23:49:46.874131 ==
3049 23:49:46.876507 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 23:49:46.880127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 23:49:46.880552 ==
3052 23:49:46.881013
3053 23:49:46.883201
3054 23:49:46.883649 TX Vref Scan disable
3055 23:49:46.886318 == TX Byte 0 ==
3056 23:49:46.889877 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3057 23:49:46.893217 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3058 23:49:46.896670 == TX Byte 1 ==
3059 23:49:46.899728 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3060 23:49:46.903155 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3061 23:49:46.903608
3062 23:49:46.906424 [DATLAT]
3063 23:49:46.906902 Freq=1200, CH0 RK1
3064 23:49:46.907269
3065 23:49:46.909899 DATLAT Default: 0xd
3066 23:49:46.910507 0, 0xFFFF, sum = 0
3067 23:49:46.913171 1, 0xFFFF, sum = 0
3068 23:49:46.913589 2, 0xFFFF, sum = 0
3069 23:49:46.917063 3, 0xFFFF, sum = 0
3070 23:49:46.917517 4, 0xFFFF, sum = 0
3071 23:49:46.919970 5, 0xFFFF, sum = 0
3072 23:49:46.920428 6, 0xFFFF, sum = 0
3073 23:49:46.922909 7, 0xFFFF, sum = 0
3074 23:49:46.923365 8, 0xFFFF, sum = 0
3075 23:49:46.926432 9, 0xFFFF, sum = 0
3076 23:49:46.929996 10, 0xFFFF, sum = 0
3077 23:49:46.930576 11, 0xFFFF, sum = 0
3078 23:49:46.932997 12, 0x0, sum = 1
3079 23:49:46.933422 13, 0x0, sum = 2
3080 23:49:46.933794 14, 0x0, sum = 3
3081 23:49:46.936625 15, 0x0, sum = 4
3082 23:49:46.937189 best_step = 13
3083 23:49:46.937527
3084 23:49:46.939884 ==
3085 23:49:46.940335 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 23:49:46.946717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 23:49:46.947172 ==
3088 23:49:46.947504 RX Vref Scan: 0
3089 23:49:46.947843
3090 23:49:46.949756 RX Vref 0 -> 0, step: 1
3091 23:49:46.950172
3092 23:49:46.952962 RX Delay -37 -> 252, step: 4
3093 23:49:46.956538 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3094 23:49:46.963180 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3095 23:49:46.966504 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3096 23:49:46.969920 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3097 23:49:46.973101 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3098 23:49:46.976181 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3099 23:49:46.979730 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3100 23:49:46.986630 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3101 23:49:46.989648 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3102 23:49:46.993157 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3103 23:49:46.996408 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3104 23:49:46.999612 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3105 23:49:47.006397 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3106 23:49:47.009490 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3107 23:49:47.013056 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3108 23:49:47.016253 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3109 23:49:47.016884 ==
3110 23:49:47.019449 Dram Type= 6, Freq= 0, CH_0, rank 1
3111 23:49:47.026574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 23:49:47.027042 ==
3113 23:49:47.027404 DQS Delay:
3114 23:49:47.029570 DQS0 = 0, DQS1 = 0
3115 23:49:47.029986 DQM Delay:
3116 23:49:47.030358 DQM0 = 110, DQM1 = 99
3117 23:49:47.033207 DQ Delay:
3118 23:49:47.036356 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3119 23:49:47.039623 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3120 23:49:47.043177 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3121 23:49:47.046586 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3122 23:49:47.047151
3123 23:49:47.047488
3124 23:49:47.052846 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3125 23:49:47.056329 CH0 RK1: MR19=403, MR18=10F7
3126 23:49:47.063017 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3127 23:49:47.066150 [RxdqsGatingPostProcess] freq 1200
3128 23:49:47.072670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3129 23:49:47.076146 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 23:49:47.079522 best DQS1 dly(2T, 0.5T) = (0, 12)
3131 23:49:47.082632 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 23:49:47.083048 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3133 23:49:47.086303 best DQS0 dly(2T, 0.5T) = (0, 11)
3134 23:49:47.089423 best DQS1 dly(2T, 0.5T) = (0, 11)
3135 23:49:47.092631 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3136 23:49:47.095993 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3137 23:49:47.099398 Pre-setting of DQS Precalculation
3138 23:49:47.106256 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3139 23:49:47.106700 ==
3140 23:49:47.109532 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 23:49:47.112555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 23:49:47.112997 ==
3143 23:49:47.119395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 23:49:47.122709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3145 23:49:47.132274 [CA 0] Center 37 (7~67) winsize 61
3146 23:49:47.135926 [CA 1] Center 37 (7~68) winsize 62
3147 23:49:47.139168 [CA 2] Center 34 (5~64) winsize 60
3148 23:49:47.142376 [CA 3] Center 33 (3~64) winsize 62
3149 23:49:47.145783 [CA 4] Center 34 (4~64) winsize 61
3150 23:49:47.148767 [CA 5] Center 33 (3~63) winsize 61
3151 23:49:47.149180
3152 23:49:47.152218 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3153 23:49:47.152671
3154 23:49:47.155753 [CATrainingPosCal] consider 1 rank data
3155 23:49:47.158741 u2DelayCellTimex100 = 270/100 ps
3156 23:49:47.162243 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3157 23:49:47.168772 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3158 23:49:47.172149 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3159 23:49:47.175518 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3160 23:49:47.179049 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 23:49:47.182240 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3162 23:49:47.182654
3163 23:49:47.185316 CA PerBit enable=1, Macro0, CA PI delay=33
3164 23:49:47.185736
3165 23:49:47.188920 [CBTSetCACLKResult] CA Dly = 33
3166 23:49:47.189351 CS Dly: 6 (0~37)
3167 23:49:47.192156 ==
3168 23:49:47.192603 Dram Type= 6, Freq= 0, CH_1, rank 1
3169 23:49:47.198846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 23:49:47.199262 ==
3171 23:49:47.202369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3172 23:49:47.209172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3173 23:49:47.218400 [CA 0] Center 37 (8~67) winsize 60
3174 23:49:47.221645 [CA 1] Center 37 (7~68) winsize 62
3175 23:49:47.224871 [CA 2] Center 34 (4~65) winsize 62
3176 23:49:47.228208 [CA 3] Center 33 (3~64) winsize 62
3177 23:49:47.231335 [CA 4] Center 34 (4~65) winsize 62
3178 23:49:47.234785 [CA 5] Center 33 (3~63) winsize 61
3179 23:49:47.235203
3180 23:49:47.238282 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3181 23:49:47.238721
3182 23:49:47.241090 [CATrainingPosCal] consider 2 rank data
3183 23:49:47.244646 u2DelayCellTimex100 = 270/100 ps
3184 23:49:47.248190 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3185 23:49:47.251151 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3186 23:49:47.258103 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3187 23:49:47.261100 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3188 23:49:47.264437 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3189 23:49:47.268117 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3190 23:49:47.268658
3191 23:49:47.271534 CA PerBit enable=1, Macro0, CA PI delay=33
3192 23:49:47.271906
3193 23:49:47.274393 [CBTSetCACLKResult] CA Dly = 33
3194 23:49:47.274922 CS Dly: 7 (0~40)
3195 23:49:47.275425
3196 23:49:47.278211 ----->DramcWriteLeveling(PI) begin...
3197 23:49:47.281166 ==
3198 23:49:47.284893 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 23:49:47.287627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 23:49:47.288177 ==
3201 23:49:47.291098 Write leveling (Byte 0): 27 => 27
3202 23:49:47.294583 Write leveling (Byte 1): 28 => 28
3203 23:49:47.298263 DramcWriteLeveling(PI) end<-----
3204 23:49:47.298697
3205 23:49:47.299034 ==
3206 23:49:47.301136 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 23:49:47.304656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 23:49:47.305093 ==
3209 23:49:47.308204 [Gating] SW mode calibration
3210 23:49:47.314959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3211 23:49:47.317880 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3212 23:49:47.324749 0 15 0 | B1->B0 | 3232 302f | 0 1 | (0 0) (0 0)
3213 23:49:47.328138 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 23:49:47.331098 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 23:49:47.337558 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 23:49:47.340856 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 23:49:47.344544 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 23:49:47.351005 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 23:49:47.354440 0 15 28 | B1->B0 | 2d2d 3131 | 1 1 | (1 0) (1 0)
3220 23:49:47.357805 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
3221 23:49:47.364241 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 23:49:47.367893 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 23:49:47.370752 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 23:49:47.377474 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 23:49:47.381082 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 23:49:47.384353 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3227 23:49:47.390737 1 0 28 | B1->B0 | 3e3e 3f3f | 0 0 | (0 0) (0 0)
3228 23:49:47.394365 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 23:49:47.397680 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 23:49:47.404384 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 23:49:47.407799 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 23:49:47.410943 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 23:49:47.417638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 23:49:47.421164 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 23:49:47.423932 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3236 23:49:47.431042 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3237 23:49:47.433906 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 23:49:47.437978 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 23:49:47.440961 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 23:49:47.447380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 23:49:47.450602 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 23:49:47.454161 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 23:49:47.460660 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 23:49:47.464189 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 23:49:47.467488 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 23:49:47.473929 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 23:49:47.477493 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 23:49:47.480645 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 23:49:47.487348 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 23:49:47.490665 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 23:49:47.494205 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3252 23:49:47.500881 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 23:49:47.501299 Total UI for P1: 0, mck2ui 16
3254 23:49:47.507269 best dqsien dly found for B0: ( 1, 3, 28)
3255 23:49:47.507689 Total UI for P1: 0, mck2ui 16
3256 23:49:47.514230 best dqsien dly found for B1: ( 1, 3, 28)
3257 23:49:47.517161 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3258 23:49:47.520745 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3259 23:49:47.521163
3260 23:49:47.524252 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3261 23:49:47.527623 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3262 23:49:47.530927 [Gating] SW calibration Done
3263 23:49:47.531342 ==
3264 23:49:47.533652 Dram Type= 6, Freq= 0, CH_1, rank 0
3265 23:49:47.537163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3266 23:49:47.537581 ==
3267 23:49:47.540506 RX Vref Scan: 0
3268 23:49:47.540966
3269 23:49:47.541295 RX Vref 0 -> 0, step: 1
3270 23:49:47.541605
3271 23:49:47.544094 RX Delay -40 -> 252, step: 8
3272 23:49:47.547330 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3273 23:49:47.554266 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3274 23:49:47.557108 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3275 23:49:47.560781 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3276 23:49:47.564319 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3277 23:49:47.567083 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3278 23:49:47.573839 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3279 23:49:47.576950 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3280 23:49:47.580536 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3281 23:49:47.583960 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3282 23:49:47.587366 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3283 23:49:47.593903 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3284 23:49:47.597366 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3285 23:49:47.600857 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3286 23:49:47.603984 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3287 23:49:47.607212 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3288 23:49:47.607626 ==
3289 23:49:47.610776 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 23:49:47.617746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 23:49:47.618276 ==
3292 23:49:47.618612 DQS Delay:
3293 23:49:47.620378 DQS0 = 0, DQS1 = 0
3294 23:49:47.620824 DQM Delay:
3295 23:49:47.623705 DQM0 = 115, DQM1 = 106
3296 23:49:47.624116 DQ Delay:
3297 23:49:47.627373 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3298 23:49:47.630728 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3299 23:49:47.634053 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3300 23:49:47.637290 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3301 23:49:47.637705
3302 23:49:47.638031
3303 23:49:47.638335 ==
3304 23:49:47.640672 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 23:49:47.644031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 23:49:47.647517 ==
3307 23:49:47.647931
3308 23:49:47.648269
3309 23:49:47.648744 TX Vref Scan disable
3310 23:49:47.650878 == TX Byte 0 ==
3311 23:49:47.653775 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3312 23:49:47.657593 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3313 23:49:47.660885 == TX Byte 1 ==
3314 23:49:47.664430 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3315 23:49:47.667315 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3316 23:49:47.667739 ==
3317 23:49:47.670694 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 23:49:47.677766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 23:49:47.678336 ==
3320 23:49:47.688410 TX Vref=22, minBit 11, minWin=24, winSum=410
3321 23:49:47.691277 TX Vref=24, minBit 11, minWin=24, winSum=412
3322 23:49:47.694836 TX Vref=26, minBit 10, minWin=25, winSum=421
3323 23:49:47.698363 TX Vref=28, minBit 9, minWin=25, winSum=425
3324 23:49:47.701424 TX Vref=30, minBit 11, minWin=25, winSum=424
3325 23:49:47.707935 TX Vref=32, minBit 9, minWin=25, winSum=420
3326 23:49:47.711405 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
3327 23:49:47.711881
3328 23:49:47.714473 Final TX Range 1 Vref 28
3329 23:49:47.714936
3330 23:49:47.715301 ==
3331 23:49:47.718013 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 23:49:47.721249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 23:49:47.724791 ==
3334 23:49:47.725211
3335 23:49:47.725755
3336 23:49:47.726132 TX Vref Scan disable
3337 23:49:47.728751 == TX Byte 0 ==
3338 23:49:47.731165 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3339 23:49:47.734728 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3340 23:49:47.738284 == TX Byte 1 ==
3341 23:49:47.741452 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3342 23:49:47.744658 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3343 23:49:47.748111
3344 23:49:47.748538 [DATLAT]
3345 23:49:47.748915 Freq=1200, CH1 RK0
3346 23:49:47.749232
3347 23:49:47.751337 DATLAT Default: 0xd
3348 23:49:47.751756 0, 0xFFFF, sum = 0
3349 23:49:47.754727 1, 0xFFFF, sum = 0
3350 23:49:47.755151 2, 0xFFFF, sum = 0
3351 23:49:47.758526 3, 0xFFFF, sum = 0
3352 23:49:47.761172 4, 0xFFFF, sum = 0
3353 23:49:47.761603 5, 0xFFFF, sum = 0
3354 23:49:47.764655 6, 0xFFFF, sum = 0
3355 23:49:47.765082 7, 0xFFFF, sum = 0
3356 23:49:47.768257 8, 0xFFFF, sum = 0
3357 23:49:47.768712 9, 0xFFFF, sum = 0
3358 23:49:47.771492 10, 0xFFFF, sum = 0
3359 23:49:47.771918 11, 0xFFFF, sum = 0
3360 23:49:47.774491 12, 0x0, sum = 1
3361 23:49:47.774911 13, 0x0, sum = 2
3362 23:49:47.777911 14, 0x0, sum = 3
3363 23:49:47.778334 15, 0x0, sum = 4
3364 23:49:47.778667 best_step = 13
3365 23:49:47.781443
3366 23:49:47.781852 ==
3367 23:49:47.784678 Dram Type= 6, Freq= 0, CH_1, rank 0
3368 23:49:47.788275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3369 23:49:47.788723 ==
3370 23:49:47.789050 RX Vref Scan: 1
3371 23:49:47.789354
3372 23:49:47.791608 Set Vref Range= 32 -> 127
3373 23:49:47.792053
3374 23:49:47.794588 RX Vref 32 -> 127, step: 1
3375 23:49:47.795028
3376 23:49:47.798089 RX Delay -21 -> 252, step: 4
3377 23:49:47.798503
3378 23:49:47.801444 Set Vref, RX VrefLevel [Byte0]: 32
3379 23:49:47.804608 [Byte1]: 32
3380 23:49:47.805046
3381 23:49:47.808272 Set Vref, RX VrefLevel [Byte0]: 33
3382 23:49:47.811612 [Byte1]: 33
3383 23:49:47.812052
3384 23:49:47.814878 Set Vref, RX VrefLevel [Byte0]: 34
3385 23:49:47.817846 [Byte1]: 34
3386 23:49:47.822597
3387 23:49:47.823033 Set Vref, RX VrefLevel [Byte0]: 35
3388 23:49:47.825588 [Byte1]: 35
3389 23:49:47.830242
3390 23:49:47.830653 Set Vref, RX VrefLevel [Byte0]: 36
3391 23:49:47.833308 [Byte1]: 36
3392 23:49:47.838330
3393 23:49:47.838741 Set Vref, RX VrefLevel [Byte0]: 37
3394 23:49:47.841371 [Byte1]: 37
3395 23:49:47.846407
3396 23:49:47.846930 Set Vref, RX VrefLevel [Byte0]: 38
3397 23:49:47.849742 [Byte1]: 38
3398 23:49:47.853989
3399 23:49:47.854424 Set Vref, RX VrefLevel [Byte0]: 39
3400 23:49:47.857641 [Byte1]: 39
3401 23:49:47.862283
3402 23:49:47.862947 Set Vref, RX VrefLevel [Byte0]: 40
3403 23:49:47.865506 [Byte1]: 40
3404 23:49:47.870093
3405 23:49:47.870547 Set Vref, RX VrefLevel [Byte0]: 41
3406 23:49:47.873586 [Byte1]: 41
3407 23:49:47.878441
3408 23:49:47.878984 Set Vref, RX VrefLevel [Byte0]: 42
3409 23:49:47.881161 [Byte1]: 42
3410 23:49:47.886128
3411 23:49:47.886592 Set Vref, RX VrefLevel [Byte0]: 43
3412 23:49:47.888890 [Byte1]: 43
3413 23:49:47.893554
3414 23:49:47.893963 Set Vref, RX VrefLevel [Byte0]: 44
3415 23:49:47.896970 [Byte1]: 44
3416 23:49:47.901676
3417 23:49:47.902087 Set Vref, RX VrefLevel [Byte0]: 45
3418 23:49:47.904997 [Byte1]: 45
3419 23:49:47.909453
3420 23:49:47.909862 Set Vref, RX VrefLevel [Byte0]: 46
3421 23:49:47.912994 [Byte1]: 46
3422 23:49:47.917539
3423 23:49:47.917949 Set Vref, RX VrefLevel [Byte0]: 47
3424 23:49:47.920895 [Byte1]: 47
3425 23:49:47.925473
3426 23:49:47.925883 Set Vref, RX VrefLevel [Byte0]: 48
3427 23:49:47.929117 [Byte1]: 48
3428 23:49:47.933636
3429 23:49:47.934045 Set Vref, RX VrefLevel [Byte0]: 49
3430 23:49:47.936472 [Byte1]: 49
3431 23:49:47.941061
3432 23:49:47.941473 Set Vref, RX VrefLevel [Byte0]: 50
3433 23:49:47.944670 [Byte1]: 50
3434 23:49:47.949256
3435 23:49:47.949959 Set Vref, RX VrefLevel [Byte0]: 51
3436 23:49:47.952510 [Byte1]: 51
3437 23:49:47.957138
3438 23:49:47.957555 Set Vref, RX VrefLevel [Byte0]: 52
3439 23:49:47.960317 [Byte1]: 52
3440 23:49:47.964948
3441 23:49:47.965364 Set Vref, RX VrefLevel [Byte0]: 53
3442 23:49:47.968168 [Byte1]: 53
3443 23:49:47.972979
3444 23:49:47.973397 Set Vref, RX VrefLevel [Byte0]: 54
3445 23:49:47.976331 [Byte1]: 54
3446 23:49:47.981021
3447 23:49:47.981590 Set Vref, RX VrefLevel [Byte0]: 55
3448 23:49:47.984355 [Byte1]: 55
3449 23:49:47.988807
3450 23:49:47.989225 Set Vref, RX VrefLevel [Byte0]: 56
3451 23:49:47.992129 [Byte1]: 56
3452 23:49:47.996641
3453 23:49:47.997068 Set Vref, RX VrefLevel [Byte0]: 57
3454 23:49:47.999677 [Byte1]: 57
3455 23:49:48.004696
3456 23:49:48.005119 Set Vref, RX VrefLevel [Byte0]: 58
3457 23:49:48.007776 [Byte1]: 58
3458 23:49:48.012862
3459 23:49:48.013294 Set Vref, RX VrefLevel [Byte0]: 59
3460 23:49:48.015750 [Byte1]: 59
3461 23:49:48.020717
3462 23:49:48.021145 Set Vref, RX VrefLevel [Byte0]: 60
3463 23:49:48.023544 [Byte1]: 60
3464 23:49:48.028162
3465 23:49:48.028623 Set Vref, RX VrefLevel [Byte0]: 61
3466 23:49:48.031647 [Byte1]: 61
3467 23:49:48.036300
3468 23:49:48.036849 Set Vref, RX VrefLevel [Byte0]: 62
3469 23:49:48.039817 [Byte1]: 62
3470 23:49:48.044001
3471 23:49:48.044422 Set Vref, RX VrefLevel [Byte0]: 63
3472 23:49:48.047723 [Byte1]: 63
3473 23:49:48.051955
3474 23:49:48.052423 Set Vref, RX VrefLevel [Byte0]: 64
3475 23:49:48.055350 [Byte1]: 64
3476 23:49:48.060370
3477 23:49:48.061027 Set Vref, RX VrefLevel [Byte0]: 65
3478 23:49:48.063305 [Byte1]: 65
3479 23:49:48.067823
3480 23:49:48.068245 Set Vref, RX VrefLevel [Byte0]: 66
3481 23:49:48.071237 [Byte1]: 66
3482 23:49:48.075794
3483 23:49:48.076242 Set Vref, RX VrefLevel [Byte0]: 67
3484 23:49:48.079493 [Byte1]: 67
3485 23:49:48.083488
3486 23:49:48.083908 Set Vref, RX VrefLevel [Byte0]: 68
3487 23:49:48.087183 [Byte1]: 68
3488 23:49:48.092022
3489 23:49:48.092658 Set Vref, RX VrefLevel [Byte0]: 69
3490 23:49:48.095297 [Byte1]: 69
3491 23:49:48.099581
3492 23:49:48.100123 Set Vref, RX VrefLevel [Byte0]: 70
3493 23:49:48.103102 [Byte1]: 70
3494 23:49:48.107462
3495 23:49:48.107976 Set Vref, RX VrefLevel [Byte0]: 71
3496 23:49:48.110812 [Byte1]: 71
3497 23:49:48.115346
3498 23:49:48.115902 Set Vref, RX VrefLevel [Byte0]: 72
3499 23:49:48.119059 [Byte1]: 72
3500 23:49:48.123387
3501 23:49:48.123821 Final RX Vref Byte 0 = 55 to rank0
3502 23:49:48.126915 Final RX Vref Byte 1 = 50 to rank0
3503 23:49:48.130195 Final RX Vref Byte 0 = 55 to rank1
3504 23:49:48.133114 Final RX Vref Byte 1 = 50 to rank1==
3505 23:49:48.136719 Dram Type= 6, Freq= 0, CH_1, rank 0
3506 23:49:48.143150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 23:49:48.143590 ==
3508 23:49:48.143931 DQS Delay:
3509 23:49:48.144261 DQS0 = 0, DQS1 = 0
3510 23:49:48.146783 DQM Delay:
3511 23:49:48.147233 DQM0 = 114, DQM1 = 105
3512 23:49:48.150221 DQ Delay:
3513 23:49:48.153731 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =112
3514 23:49:48.157243 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3515 23:49:48.159975 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3516 23:49:48.163869 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3517 23:49:48.164315
3518 23:49:48.164734
3519 23:49:48.169875 [DQSOSCAuto] RK0, (LSB)MR18= 0xeef5, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3520 23:49:48.173297 CH1 RK0: MR19=303, MR18=EEF5
3521 23:49:48.179764 CH1_RK0: MR19=0x303, MR18=0xEEF5, DQSOSC=414, MR23=63, INC=38, DEC=25
3522 23:49:48.180188
3523 23:49:48.183403 ----->DramcWriteLeveling(PI) begin...
3524 23:49:48.183967 ==
3525 23:49:48.186711 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 23:49:48.190078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 23:49:48.193739 ==
3528 23:49:48.194237 Write leveling (Byte 0): 22 => 22
3529 23:49:48.196510 Write leveling (Byte 1): 27 => 27
3530 23:49:48.200057 DramcWriteLeveling(PI) end<-----
3531 23:49:48.200506
3532 23:49:48.200908 ==
3533 23:49:48.203303 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 23:49:48.209857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 23:49:48.210308 ==
3536 23:49:48.210651 [Gating] SW mode calibration
3537 23:49:48.220212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3538 23:49:48.223684 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3539 23:49:48.229913 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 23:49:48.233503 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 23:49:48.236717 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 23:49:48.239798 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 23:49:48.246807 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 23:49:48.249869 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3545 23:49:48.253101 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
3546 23:49:48.260253 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 23:49:48.263490 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 23:49:48.266568 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 23:49:48.273394 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 23:49:48.276771 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 23:49:48.279684 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 23:49:48.286610 1 0 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3553 23:49:48.289807 1 0 24 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
3554 23:49:48.293066 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3555 23:49:48.299811 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 23:49:48.303234 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 23:49:48.306434 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 23:49:48.312809 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 23:49:48.316482 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 23:49:48.319711 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 23:49:48.326253 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3562 23:49:48.329925 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3563 23:49:48.333237 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 23:49:48.339795 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 23:49:48.342846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 23:49:48.346160 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 23:49:48.352525 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 23:49:48.355769 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 23:49:48.359452 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 23:49:48.366071 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 23:49:48.369606 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 23:49:48.373025 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 23:49:48.379563 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 23:49:48.382647 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 23:49:48.385980 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 23:49:48.392532 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3577 23:49:48.395667 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3578 23:49:48.399391 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3579 23:49:48.402269 Total UI for P1: 0, mck2ui 16
3580 23:49:48.405698 best dqsien dly found for B0: ( 1, 3, 22)
3581 23:49:48.409107 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3582 23:49:48.412597 Total UI for P1: 0, mck2ui 16
3583 23:49:48.415988 best dqsien dly found for B1: ( 1, 3, 26)
3584 23:49:48.419123 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3585 23:49:48.425830 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3586 23:49:48.426335
3587 23:49:48.429064 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3588 23:49:48.431972 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3589 23:49:48.435448 [Gating] SW calibration Done
3590 23:49:48.435886 ==
3591 23:49:48.439201 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 23:49:48.442397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 23:49:48.442831 ==
3594 23:49:48.445480 RX Vref Scan: 0
3595 23:49:48.445929
3596 23:49:48.446267 RX Vref 0 -> 0, step: 1
3597 23:49:48.446617
3598 23:49:48.448775 RX Delay -40 -> 252, step: 8
3599 23:49:48.452467 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3600 23:49:48.458645 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3601 23:49:48.462115 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3602 23:49:48.465081 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3603 23:49:48.468471 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3604 23:49:48.472080 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3605 23:49:48.475626 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3606 23:49:48.481865 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3607 23:49:48.485189 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3608 23:49:48.488230 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3609 23:49:48.491639 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3610 23:49:48.494759 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3611 23:49:48.501679 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3612 23:49:48.505010 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3613 23:49:48.508331 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3614 23:49:48.511661 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3615 23:49:48.512119 ==
3616 23:49:48.515115 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 23:49:48.521431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 23:49:48.521875 ==
3619 23:49:48.522214 DQS Delay:
3620 23:49:48.524892 DQS0 = 0, DQS1 = 0
3621 23:49:48.525324 DQM Delay:
3622 23:49:48.528487 DQM0 = 110, DQM1 = 107
3623 23:49:48.529055 DQ Delay:
3624 23:49:48.531375 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3625 23:49:48.534515 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3626 23:49:48.538023 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3627 23:49:48.541330 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3628 23:49:48.541769
3629 23:49:48.542107
3630 23:49:48.542449 ==
3631 23:49:48.545034 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 23:49:48.547874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 23:49:48.551300 ==
3634 23:49:48.551735
3635 23:49:48.552080
3636 23:49:48.552400 TX Vref Scan disable
3637 23:49:48.554744 == TX Byte 0 ==
3638 23:49:48.557990 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3639 23:49:48.561135 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3640 23:49:48.564527 == TX Byte 1 ==
3641 23:49:48.567532 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3642 23:49:48.571532 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3643 23:49:48.574617 ==
3644 23:49:48.577563 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 23:49:48.581202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 23:49:48.581748 ==
3647 23:49:48.592315 TX Vref=22, minBit 0, minWin=25, winSum=422
3648 23:49:48.595730 TX Vref=24, minBit 9, minWin=25, winSum=423
3649 23:49:48.599147 TX Vref=26, minBit 8, minWin=26, winSum=431
3650 23:49:48.602169 TX Vref=28, minBit 1, minWin=26, winSum=431
3651 23:49:48.605985 TX Vref=30, minBit 4, minWin=26, winSum=432
3652 23:49:48.612662 TX Vref=32, minBit 0, minWin=26, winSum=428
3653 23:49:48.615684 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 30
3654 23:49:48.616103
3655 23:49:48.619247 Final TX Range 1 Vref 30
3656 23:49:48.619664
3657 23:49:48.619990 ==
3658 23:49:48.622467 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 23:49:48.625797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 23:49:48.626220 ==
3661 23:49:48.629028
3662 23:49:48.629441
3663 23:49:48.629769 TX Vref Scan disable
3664 23:49:48.632287 == TX Byte 0 ==
3665 23:49:48.635518 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3666 23:49:48.642117 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3667 23:49:48.642718 == TX Byte 1 ==
3668 23:49:48.645233 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3669 23:49:48.652106 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3670 23:49:48.652527
3671 23:49:48.652896 [DATLAT]
3672 23:49:48.653206 Freq=1200, CH1 RK1
3673 23:49:48.653536
3674 23:49:48.656123 DATLAT Default: 0xd
3675 23:49:48.656539 0, 0xFFFF, sum = 0
3676 23:49:48.658572 1, 0xFFFF, sum = 0
3677 23:49:48.662193 2, 0xFFFF, sum = 0
3678 23:49:48.662722 3, 0xFFFF, sum = 0
3679 23:49:48.665498 4, 0xFFFF, sum = 0
3680 23:49:48.665922 5, 0xFFFF, sum = 0
3681 23:49:48.668456 6, 0xFFFF, sum = 0
3682 23:49:48.668954 7, 0xFFFF, sum = 0
3683 23:49:48.671953 8, 0xFFFF, sum = 0
3684 23:49:48.672379 9, 0xFFFF, sum = 0
3685 23:49:48.675573 10, 0xFFFF, sum = 0
3686 23:49:48.676024 11, 0xFFFF, sum = 0
3687 23:49:48.678374 12, 0x0, sum = 1
3688 23:49:48.678799 13, 0x0, sum = 2
3689 23:49:48.682473 14, 0x0, sum = 3
3690 23:49:48.683026 15, 0x0, sum = 4
3691 23:49:48.685229 best_step = 13
3692 23:49:48.685647
3693 23:49:48.685976 ==
3694 23:49:48.688488 Dram Type= 6, Freq= 0, CH_1, rank 1
3695 23:49:48.691918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3696 23:49:48.692342 ==
3697 23:49:48.692717 RX Vref Scan: 0
3698 23:49:48.694802
3699 23:49:48.695219 RX Vref 0 -> 0, step: 1
3700 23:49:48.695553
3701 23:49:48.698401 RX Delay -21 -> 252, step: 4
3702 23:49:48.705041 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3703 23:49:48.708223 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3704 23:49:48.711577 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3705 23:49:48.715162 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3706 23:49:48.718185 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3707 23:49:48.724698 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3708 23:49:48.728325 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3709 23:49:48.731494 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3710 23:49:48.734631 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3711 23:49:48.738534 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3712 23:49:48.744677 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3713 23:49:48.748376 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3714 23:49:48.751358 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3715 23:49:48.754661 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3716 23:49:48.758124 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3717 23:49:48.764172 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3718 23:49:48.764661 ==
3719 23:49:48.767540 Dram Type= 6, Freq= 0, CH_1, rank 1
3720 23:49:48.771168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3721 23:49:48.771635 ==
3722 23:49:48.772012 DQS Delay:
3723 23:49:48.774817 DQS0 = 0, DQS1 = 0
3724 23:49:48.775294 DQM Delay:
3725 23:49:48.777538 DQM0 = 111, DQM1 = 110
3726 23:49:48.777999 DQ Delay:
3727 23:49:48.781117 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3728 23:49:48.784265 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3729 23:49:48.787649 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3730 23:49:48.790883 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3731 23:49:48.794019
3732 23:49:48.794434
3733 23:49:48.801140 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3734 23:49:48.804316 CH1 RK1: MR19=304, MR18=FC0B
3735 23:49:48.810566 CH1_RK1: MR19=0x304, MR18=0xFC0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3736 23:49:48.814017 [RxdqsGatingPostProcess] freq 1200
3737 23:49:48.817241 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3738 23:49:48.820795 best DQS0 dly(2T, 0.5T) = (0, 11)
3739 23:49:48.824170 best DQS1 dly(2T, 0.5T) = (0, 11)
3740 23:49:48.827298 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3741 23:49:48.830476 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3742 23:49:48.833795 best DQS0 dly(2T, 0.5T) = (0, 11)
3743 23:49:48.837071 best DQS1 dly(2T, 0.5T) = (0, 11)
3744 23:49:48.840470 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3745 23:49:48.843897 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3746 23:49:48.847076 Pre-setting of DQS Precalculation
3747 23:49:48.850675 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3748 23:49:48.860803 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3749 23:49:48.867056 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3750 23:49:48.867481
3751 23:49:48.867808
3752 23:49:48.870364 [Calibration Summary] 2400 Mbps
3753 23:49:48.870896 CH 0, Rank 0
3754 23:49:48.874043 SW Impedance : PASS
3755 23:49:48.874599 DUTY Scan : NO K
3756 23:49:48.876989 ZQ Calibration : PASS
3757 23:49:48.880437 Jitter Meter : NO K
3758 23:49:48.881073 CBT Training : PASS
3759 23:49:48.883810 Write leveling : PASS
3760 23:49:48.887196 RX DQS gating : PASS
3761 23:49:48.887669 RX DQ/DQS(RDDQC) : PASS
3762 23:49:48.890046 TX DQ/DQS : PASS
3763 23:49:48.893567 RX DATLAT : PASS
3764 23:49:48.894040 RX DQ/DQS(Engine): PASS
3765 23:49:48.896890 TX OE : NO K
3766 23:49:48.897390 All Pass.
3767 23:49:48.897767
3768 23:49:48.900354 CH 0, Rank 1
3769 23:49:48.900851 SW Impedance : PASS
3770 23:49:48.903317 DUTY Scan : NO K
3771 23:49:48.903779 ZQ Calibration : PASS
3772 23:49:48.906909 Jitter Meter : NO K
3773 23:49:48.910120 CBT Training : PASS
3774 23:49:48.910587 Write leveling : PASS
3775 23:49:48.913403 RX DQS gating : PASS
3776 23:49:48.917121 RX DQ/DQS(RDDQC) : PASS
3777 23:49:48.917586 TX DQ/DQS : PASS
3778 23:49:48.919778 RX DATLAT : PASS
3779 23:49:48.923711 RX DQ/DQS(Engine): PASS
3780 23:49:48.924132 TX OE : NO K
3781 23:49:48.926702 All Pass.
3782 23:49:48.927119
3783 23:49:48.927449 CH 1, Rank 0
3784 23:49:48.929935 SW Impedance : PASS
3785 23:49:48.930353 DUTY Scan : NO K
3786 23:49:48.933254 ZQ Calibration : PASS
3787 23:49:48.936381 Jitter Meter : NO K
3788 23:49:48.936834 CBT Training : PASS
3789 23:49:48.940472 Write leveling : PASS
3790 23:49:48.943361 RX DQS gating : PASS
3791 23:49:48.943784 RX DQ/DQS(RDDQC) : PASS
3792 23:49:48.946585 TX DQ/DQS : PASS
3793 23:49:48.950041 RX DATLAT : PASS
3794 23:49:48.950589 RX DQ/DQS(Engine): PASS
3795 23:49:48.953281 TX OE : NO K
3796 23:49:48.953829 All Pass.
3797 23:49:48.954250
3798 23:49:48.956363 CH 1, Rank 1
3799 23:49:48.956827 SW Impedance : PASS
3800 23:49:48.960419 DUTY Scan : NO K
3801 23:49:48.960994 ZQ Calibration : PASS
3802 23:49:48.963280 Jitter Meter : NO K
3803 23:49:48.966242 CBT Training : PASS
3804 23:49:48.966665 Write leveling : PASS
3805 23:49:48.969839 RX DQS gating : PASS
3806 23:49:48.973106 RX DQ/DQS(RDDQC) : PASS
3807 23:49:48.973526 TX DQ/DQS : PASS
3808 23:49:48.976690 RX DATLAT : PASS
3809 23:49:48.980016 RX DQ/DQS(Engine): PASS
3810 23:49:48.980640 TX OE : NO K
3811 23:49:48.982948 All Pass.
3812 23:49:48.983362
3813 23:49:48.983689 DramC Write-DBI off
3814 23:49:48.986378 PER_BANK_REFRESH: Hybrid Mode
3815 23:49:48.986954 TX_TRACKING: ON
3816 23:49:48.996371 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3817 23:49:48.999181 [FAST_K] Save calibration result to emmc
3818 23:49:49.002502 dramc_set_vcore_voltage set vcore to 650000
3819 23:49:49.006225 Read voltage for 600, 5
3820 23:49:49.006650 Vio18 = 0
3821 23:49:49.009295 Vcore = 650000
3822 23:49:49.009721 Vdram = 0
3823 23:49:49.010084 Vddq = 0
3824 23:49:49.012702 Vmddr = 0
3825 23:49:49.016061 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3826 23:49:49.022904 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3827 23:49:49.023375 MEM_TYPE=3, freq_sel=19
3828 23:49:49.026155 sv_algorithm_assistance_LP4_1600
3829 23:49:49.032600 ============ PULL DRAM RESETB DOWN ============
3830 23:49:49.036083 ========== PULL DRAM RESETB DOWN end =========
3831 23:49:49.039471 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3832 23:49:49.042905 ===================================
3833 23:49:49.045773 LPDDR4 DRAM CONFIGURATION
3834 23:49:49.049245 ===================================
3835 23:49:49.052691 EX_ROW_EN[0] = 0x0
3836 23:49:49.053161 EX_ROW_EN[1] = 0x0
3837 23:49:49.055946 LP4Y_EN = 0x0
3838 23:49:49.056410 WORK_FSP = 0x0
3839 23:49:49.059283 WL = 0x2
3840 23:49:49.059746 RL = 0x2
3841 23:49:49.062208 BL = 0x2
3842 23:49:49.062671 RPST = 0x0
3843 23:49:49.065568 RD_PRE = 0x0
3844 23:49:49.066034 WR_PRE = 0x1
3845 23:49:49.069050 WR_PST = 0x0
3846 23:49:49.069514 DBI_WR = 0x0
3847 23:49:49.072696 DBI_RD = 0x0
3848 23:49:49.073186 OTF = 0x1
3849 23:49:49.075810 ===================================
3850 23:49:49.078812 ===================================
3851 23:49:49.082486 ANA top config
3852 23:49:49.086042 ===================================
3853 23:49:49.089307 DLL_ASYNC_EN = 0
3854 23:49:49.089872 ALL_SLAVE_EN = 1
3855 23:49:49.092499 NEW_RANK_MODE = 1
3856 23:49:49.095555 DLL_IDLE_MODE = 1
3857 23:49:49.099166 LP45_APHY_COMB_EN = 1
3858 23:49:49.099656 TX_ODT_DIS = 1
3859 23:49:49.102078 NEW_8X_MODE = 1
3860 23:49:49.105510 ===================================
3861 23:49:49.108975 ===================================
3862 23:49:49.112606 data_rate = 1200
3863 23:49:49.115537 CKR = 1
3864 23:49:49.119000 DQ_P2S_RATIO = 8
3865 23:49:49.122379 ===================================
3866 23:49:49.125165 CA_P2S_RATIO = 8
3867 23:49:49.125660 DQ_CA_OPEN = 0
3868 23:49:49.128678 DQ_SEMI_OPEN = 0
3869 23:49:49.132006 CA_SEMI_OPEN = 0
3870 23:49:49.135415 CA_FULL_RATE = 0
3871 23:49:49.138347 DQ_CKDIV4_EN = 1
3872 23:49:49.141807 CA_CKDIV4_EN = 1
3873 23:49:49.142274 CA_PREDIV_EN = 0
3874 23:49:49.145809 PH8_DLY = 0
3875 23:49:49.148664 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3876 23:49:49.152007 DQ_AAMCK_DIV = 4
3877 23:49:49.155432 CA_AAMCK_DIV = 4
3878 23:49:49.155885 CA_ADMCK_DIV = 4
3879 23:49:49.158511 DQ_TRACK_CA_EN = 0
3880 23:49:49.161862 CA_PICK = 600
3881 23:49:49.165608 CA_MCKIO = 600
3882 23:49:49.168677 MCKIO_SEMI = 0
3883 23:49:49.172004 PLL_FREQ = 2288
3884 23:49:49.175320 DQ_UI_PI_RATIO = 32
3885 23:49:49.178759 CA_UI_PI_RATIO = 0
3886 23:49:49.179442 ===================================
3887 23:49:49.182381 ===================================
3888 23:49:49.185107 memory_type:LPDDR4
3889 23:49:49.188636 GP_NUM : 10
3890 23:49:49.189103 SRAM_EN : 1
3891 23:49:49.192008 MD32_EN : 0
3892 23:49:49.195470 ===================================
3893 23:49:49.198126 [ANA_INIT] >>>>>>>>>>>>>>
3894 23:49:49.201690 <<<<<< [CONFIGURE PHASE]: ANA_TX
3895 23:49:49.205080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3896 23:49:49.208198 ===================================
3897 23:49:49.209033 data_rate = 1200,PCW = 0X5800
3898 23:49:49.211353 ===================================
3899 23:49:49.218206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3900 23:49:49.221539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 23:49:49.228509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3902 23:49:49.231414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3903 23:49:49.234891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3904 23:49:49.238106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3905 23:49:49.241708 [ANA_INIT] flow start
3906 23:49:49.244486 [ANA_INIT] PLL >>>>>>>>
3907 23:49:49.244955 [ANA_INIT] PLL <<<<<<<<
3908 23:49:49.247928 [ANA_INIT] MIDPI >>>>>>>>
3909 23:49:49.251588 [ANA_INIT] MIDPI <<<<<<<<
3910 23:49:49.252011 [ANA_INIT] DLL >>>>>>>>
3911 23:49:49.254858 [ANA_INIT] flow end
3912 23:49:49.258103 ============ LP4 DIFF to SE enter ============
3913 23:49:49.264767 ============ LP4 DIFF to SE exit ============
3914 23:49:49.265196 [ANA_INIT] <<<<<<<<<<<<<
3915 23:49:49.267667 [Flow] Enable top DCM control >>>>>
3916 23:49:49.270850 [Flow] Enable top DCM control <<<<<
3917 23:49:49.274274 Enable DLL master slave shuffle
3918 23:49:49.280913 ==============================================================
3919 23:49:49.281343 Gating Mode config
3920 23:49:49.287703 ==============================================================
3921 23:49:49.290872 Config description:
3922 23:49:49.297750 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3923 23:49:49.304033 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3924 23:49:49.310773 SELPH_MODE 0: By rank 1: By Phase
3925 23:49:49.317316 ==============================================================
3926 23:49:49.320883 GAT_TRACK_EN = 1
3927 23:49:49.321311 RX_GATING_MODE = 2
3928 23:49:49.323752 RX_GATING_TRACK_MODE = 2
3929 23:49:49.327182 SELPH_MODE = 1
3930 23:49:49.330684 PICG_EARLY_EN = 1
3931 23:49:49.333669 VALID_LAT_VALUE = 1
3932 23:49:49.340660 ==============================================================
3933 23:49:49.343887 Enter into Gating configuration >>>>
3934 23:49:49.346982 Exit from Gating configuration <<<<
3935 23:49:49.350851 Enter into DVFS_PRE_config >>>>>
3936 23:49:49.360107 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3937 23:49:49.363609 Exit from DVFS_PRE_config <<<<<
3938 23:49:49.366979 Enter into PICG configuration >>>>
3939 23:49:49.370524 Exit from PICG configuration <<<<
3940 23:49:49.373822 [RX_INPUT] configuration >>>>>
3941 23:49:49.377227 [RX_INPUT] configuration <<<<<
3942 23:49:49.380719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3943 23:49:49.387013 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3944 23:49:49.394056 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3945 23:49:49.396936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3946 23:49:49.403819 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3947 23:49:49.410551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3948 23:49:49.413521 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3949 23:49:49.420239 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3950 23:49:49.423402 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3951 23:49:49.427255 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3952 23:49:49.430077 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3953 23:49:49.436680 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 23:49:49.440050 ===================================
3955 23:49:49.440706 LPDDR4 DRAM CONFIGURATION
3956 23:49:49.443408 ===================================
3957 23:49:49.446789 EX_ROW_EN[0] = 0x0
3958 23:49:49.450312 EX_ROW_EN[1] = 0x0
3959 23:49:49.450737 LP4Y_EN = 0x0
3960 23:49:49.453697 WORK_FSP = 0x0
3961 23:49:49.454139 WL = 0x2
3962 23:49:49.456875 RL = 0x2
3963 23:49:49.457368 BL = 0x2
3964 23:49:49.460172 RPST = 0x0
3965 23:49:49.460639 RD_PRE = 0x0
3966 23:49:49.463423 WR_PRE = 0x1
3967 23:49:49.463858 WR_PST = 0x0
3968 23:49:49.466891 DBI_WR = 0x0
3969 23:49:49.467438 DBI_RD = 0x0
3970 23:49:49.470449 OTF = 0x1
3971 23:49:49.473040 ===================================
3972 23:49:49.476532 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3973 23:49:49.479949 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3974 23:49:49.486926 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3975 23:49:49.489708 ===================================
3976 23:49:49.490131 LPDDR4 DRAM CONFIGURATION
3977 23:49:49.493142 ===================================
3978 23:49:49.496733 EX_ROW_EN[0] = 0x10
3979 23:49:49.499616 EX_ROW_EN[1] = 0x0
3980 23:49:49.500155 LP4Y_EN = 0x0
3981 23:49:49.502824 WORK_FSP = 0x0
3982 23:49:49.503268 WL = 0x2
3983 23:49:49.506500 RL = 0x2
3984 23:49:49.507058 BL = 0x2
3985 23:49:49.509394 RPST = 0x0
3986 23:49:49.509818 RD_PRE = 0x0
3987 23:49:49.513092 WR_PRE = 0x1
3988 23:49:49.513526 WR_PST = 0x0
3989 23:49:49.516229 DBI_WR = 0x0
3990 23:49:49.516700 DBI_RD = 0x0
3991 23:49:49.519602 OTF = 0x1
3992 23:49:49.523082 ===================================
3993 23:49:49.529348 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3994 23:49:49.533006 nWR fixed to 30
3995 23:49:49.533446 [ModeRegInit_LP4] CH0 RK0
3996 23:49:49.536156 [ModeRegInit_LP4] CH0 RK1
3997 23:49:49.539214 [ModeRegInit_LP4] CH1 RK0
3998 23:49:49.542403 [ModeRegInit_LP4] CH1 RK1
3999 23:49:49.542843 match AC timing 17
4000 23:49:49.549261 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4001 23:49:49.552689 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4002 23:49:49.555553 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4003 23:49:49.562256 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4004 23:49:49.565768 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4005 23:49:49.566205 ==
4006 23:49:49.569138 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 23:49:49.572690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 23:49:49.573119 ==
4009 23:49:49.578690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4010 23:49:49.585827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4011 23:49:49.588817 [CA 0] Center 37 (7~67) winsize 61
4012 23:49:49.592306 [CA 1] Center 36 (6~67) winsize 62
4013 23:49:49.595590 [CA 2] Center 35 (5~65) winsize 61
4014 23:49:49.599019 [CA 3] Center 35 (5~65) winsize 61
4015 23:49:49.602072 [CA 4] Center 34 (4~65) winsize 62
4016 23:49:49.605497 [CA 5] Center 34 (4~65) winsize 62
4017 23:49:49.605923
4018 23:49:49.608666 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4019 23:49:49.609156
4020 23:49:49.611876 [CATrainingPosCal] consider 1 rank data
4021 23:49:49.615758 u2DelayCellTimex100 = 270/100 ps
4022 23:49:49.618592 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4023 23:49:49.622670 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4024 23:49:49.625388 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4025 23:49:49.628836 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4026 23:49:49.631684 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4027 23:49:49.635292 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4028 23:49:49.638802
4029 23:49:49.641879 CA PerBit enable=1, Macro0, CA PI delay=34
4030 23:49:49.642303
4031 23:49:49.645143 [CBTSetCACLKResult] CA Dly = 34
4032 23:49:49.645567 CS Dly: 5 (0~36)
4033 23:49:49.645904 ==
4034 23:49:49.648972 Dram Type= 6, Freq= 0, CH_0, rank 1
4035 23:49:49.651536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 23:49:49.652019 ==
4037 23:49:49.658442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4038 23:49:49.665380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4039 23:49:49.668651 [CA 0] Center 37 (7~67) winsize 61
4040 23:49:49.671763 [CA 1] Center 37 (7~67) winsize 61
4041 23:49:49.675066 [CA 2] Center 35 (5~65) winsize 61
4042 23:49:49.678707 [CA 3] Center 35 (5~65) winsize 61
4043 23:49:49.681970 [CA 4] Center 34 (4~65) winsize 62
4044 23:49:49.685077 [CA 5] Center 33 (3~64) winsize 62
4045 23:49:49.685514
4046 23:49:49.688633 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4047 23:49:49.689072
4048 23:49:49.691586 [CATrainingPosCal] consider 2 rank data
4049 23:49:49.695319 u2DelayCellTimex100 = 270/100 ps
4050 23:49:49.698560 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4051 23:49:49.701734 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4052 23:49:49.705185 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4053 23:49:49.708746 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4054 23:49:49.711660 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4055 23:49:49.718085 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4056 23:49:49.718545
4057 23:49:49.721791 CA PerBit enable=1, Macro0, CA PI delay=34
4058 23:49:49.722219
4059 23:49:49.724649 [CBTSetCACLKResult] CA Dly = 34
4060 23:49:49.725073 CS Dly: 5 (0~37)
4061 23:49:49.725409
4062 23:49:49.728109 ----->DramcWriteLeveling(PI) begin...
4063 23:49:49.728539 ==
4064 23:49:49.731629 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 23:49:49.738204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 23:49:49.738709 ==
4067 23:49:49.741801 Write leveling (Byte 0): 35 => 35
4068 23:49:49.742377 Write leveling (Byte 1): 31 => 31
4069 23:49:49.745050 DramcWriteLeveling(PI) end<-----
4070 23:49:49.745519
4071 23:49:49.745902 ==
4072 23:49:49.748307 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 23:49:49.754902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 23:49:49.755461 ==
4075 23:49:49.758362 [Gating] SW mode calibration
4076 23:49:49.764986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4077 23:49:49.768098 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4078 23:49:49.774849 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 23:49:49.778251 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 23:49:49.780998 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4081 23:49:49.788217 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4082 23:49:49.791440 0 9 16 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
4083 23:49:49.794515 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 23:49:49.801270 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 23:49:49.804640 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 23:49:49.807897 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 23:49:49.814781 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 23:49:49.817799 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 23:49:49.821352 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4090 23:49:49.827506 0 10 16 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
4091 23:49:49.830917 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 23:49:49.834489 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 23:49:49.837503 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 23:49:49.844473 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 23:49:49.847807 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 23:49:49.851126 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 23:49:49.857821 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4098 23:49:49.860980 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4099 23:49:49.863985 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 23:49:49.870921 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 23:49:49.874459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 23:49:49.877989 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 23:49:49.884276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 23:49:49.887171 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 23:49:49.890717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 23:49:49.897462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 23:49:49.900783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 23:49:49.903904 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 23:49:49.910566 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 23:49:49.913925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 23:49:49.917074 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 23:49:49.924152 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 23:49:49.927374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4114 23:49:49.930430 Total UI for P1: 0, mck2ui 16
4115 23:49:49.933477 best dqsien dly found for B0: ( 0, 13, 10)
4116 23:49:49.936970 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4117 23:49:49.943826 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4118 23:49:49.944295 Total UI for P1: 0, mck2ui 16
4119 23:49:49.950311 best dqsien dly found for B1: ( 0, 13, 18)
4120 23:49:49.953674 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4121 23:49:49.957273 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4122 23:49:49.957807
4123 23:49:49.960219 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4124 23:49:49.963699 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4125 23:49:49.966698 [Gating] SW calibration Done
4126 23:49:49.967259 ==
4127 23:49:49.970382 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 23:49:49.973186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 23:49:49.973671 ==
4130 23:49:49.976740 RX Vref Scan: 0
4131 23:49:49.977217
4132 23:49:49.977603 RX Vref 0 -> 0, step: 1
4133 23:49:49.977955
4134 23:49:49.980019 RX Delay -230 -> 252, step: 16
4135 23:49:49.986707 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4136 23:49:49.990421 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4137 23:49:49.993662 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4138 23:49:49.996409 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4139 23:49:50.002971 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4140 23:49:50.006254 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4141 23:49:50.009648 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4142 23:49:50.013322 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4143 23:49:50.016241 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4144 23:49:50.023350 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4145 23:49:50.026764 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4146 23:49:50.029502 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4147 23:49:50.032924 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4148 23:49:50.039216 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4149 23:49:50.042960 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4150 23:49:50.045873 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4151 23:49:50.046356 ==
4152 23:49:50.049567 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 23:49:50.056160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 23:49:50.056690 ==
4155 23:49:50.057096 DQS Delay:
4156 23:49:50.057443 DQS0 = 0, DQS1 = 0
4157 23:49:50.059071 DQM Delay:
4158 23:49:50.059535 DQM0 = 36, DQM1 = 27
4159 23:49:50.062343 DQ Delay:
4160 23:49:50.066046 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4161 23:49:50.066631 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4162 23:49:50.069550 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =25
4163 23:49:50.072400 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4164 23:49:50.076168
4165 23:49:50.076676
4166 23:49:50.077069 ==
4167 23:49:50.079367 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 23:49:50.082609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 23:49:50.083186 ==
4170 23:49:50.083578
4171 23:49:50.083919
4172 23:49:50.085886 TX Vref Scan disable
4173 23:49:50.086374 == TX Byte 0 ==
4174 23:49:50.092371 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4175 23:49:50.095802 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4176 23:49:50.096372 == TX Byte 1 ==
4177 23:49:50.102217 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4178 23:49:50.105869 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4179 23:49:50.106339 ==
4180 23:49:50.109012 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 23:49:50.112475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 23:49:50.112998 ==
4183 23:49:50.113372
4184 23:49:50.113746
4185 23:49:50.116090 TX Vref Scan disable
4186 23:49:50.119153 == TX Byte 0 ==
4187 23:49:50.122164 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4188 23:49:50.128703 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4189 23:49:50.129178 == TX Byte 1 ==
4190 23:49:50.132197 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4191 23:49:50.139182 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4192 23:49:50.139663
4193 23:49:50.140033 [DATLAT]
4194 23:49:50.140404 Freq=600, CH0 RK0
4195 23:49:50.140780
4196 23:49:50.142029 DATLAT Default: 0x9
4197 23:49:50.142510 0, 0xFFFF, sum = 0
4198 23:49:50.145396 1, 0xFFFF, sum = 0
4199 23:49:50.145871 2, 0xFFFF, sum = 0
4200 23:49:50.149098 3, 0xFFFF, sum = 0
4201 23:49:50.152288 4, 0xFFFF, sum = 0
4202 23:49:50.152816 5, 0xFFFF, sum = 0
4203 23:49:50.155761 6, 0xFFFF, sum = 0
4204 23:49:50.156262 7, 0xFFFF, sum = 0
4205 23:49:50.158613 8, 0x0, sum = 1
4206 23:49:50.159105 9, 0x0, sum = 2
4207 23:49:50.159481 10, 0x0, sum = 3
4208 23:49:50.162053 11, 0x0, sum = 4
4209 23:49:50.162543 best_step = 9
4210 23:49:50.162916
4211 23:49:50.163272 ==
4212 23:49:50.165363 Dram Type= 6, Freq= 0, CH_0, rank 0
4213 23:49:50.171884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 23:49:50.172449 ==
4215 23:49:50.172848 RX Vref Scan: 1
4216 23:49:50.173169
4217 23:49:50.175333 RX Vref 0 -> 0, step: 1
4218 23:49:50.175791
4219 23:49:50.178418 RX Delay -195 -> 252, step: 8
4220 23:49:50.178843
4221 23:49:50.181971 Set Vref, RX VrefLevel [Byte0]: 60
4222 23:49:50.185306 [Byte1]: 47
4223 23:49:50.185835
4224 23:49:50.188730 Final RX Vref Byte 0 = 60 to rank0
4225 23:49:50.191924 Final RX Vref Byte 1 = 47 to rank0
4226 23:49:50.194947 Final RX Vref Byte 0 = 60 to rank1
4227 23:49:50.198517 Final RX Vref Byte 1 = 47 to rank1==
4228 23:49:50.201900 Dram Type= 6, Freq= 0, CH_0, rank 0
4229 23:49:50.204958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 23:49:50.205537 ==
4231 23:49:50.208259 DQS Delay:
4232 23:49:50.208845 DQS0 = 0, DQS1 = 0
4233 23:49:50.211967 DQM Delay:
4234 23:49:50.212451 DQM0 = 33, DQM1 = 28
4235 23:49:50.212893 DQ Delay:
4236 23:49:50.215318 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4237 23:49:50.218165 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4238 23:49:50.221438 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4239 23:49:50.224705 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4240 23:49:50.225210
4241 23:49:50.225623
4242 23:49:50.234944 [DQSOSCAuto] RK0, (LSB)MR18= 0x4544, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4243 23:49:50.237917 CH0 RK0: MR19=808, MR18=4544
4244 23:49:50.244737 CH0_RK0: MR19=0x808, MR18=0x4544, DQSOSC=396, MR23=63, INC=167, DEC=111
4245 23:49:50.245205
4246 23:49:50.247906 ----->DramcWriteLeveling(PI) begin...
4247 23:49:50.248381 ==
4248 23:49:50.251417 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 23:49:50.254779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 23:49:50.255250 ==
4251 23:49:50.257717 Write leveling (Byte 0): 35 => 35
4252 23:49:50.261203 Write leveling (Byte 1): 30 => 30
4253 23:49:50.264917 DramcWriteLeveling(PI) end<-----
4254 23:49:50.265488
4255 23:49:50.265855 ==
4256 23:49:50.267802 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 23:49:50.271211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 23:49:50.271818 ==
4259 23:49:50.274637 [Gating] SW mode calibration
4260 23:49:50.281225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4261 23:49:50.288066 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4262 23:49:50.291040 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 23:49:50.294026 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 23:49:50.300884 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4265 23:49:50.304133 0 9 12 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
4266 23:49:50.307096 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
4267 23:49:50.314328 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 23:49:50.317406 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 23:49:50.320411 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 23:49:50.327141 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 23:49:50.330502 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 23:49:50.333856 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 23:49:50.340325 0 10 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
4274 23:49:50.343779 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4275 23:49:50.347046 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 23:49:50.353990 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 23:49:50.356948 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 23:49:50.360196 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 23:49:50.366480 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 23:49:50.369790 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 23:49:50.373332 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 23:49:50.380329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4283 23:49:50.383170 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 23:49:50.386672 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 23:49:50.393070 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 23:49:50.396487 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 23:49:50.399631 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 23:49:50.406593 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 23:49:50.409965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 23:49:50.413134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 23:49:50.420208 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 23:49:50.423500 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 23:49:50.426740 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 23:49:50.432813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 23:49:50.436745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 23:49:50.439476 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 23:49:50.446180 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4298 23:49:50.446658 Total UI for P1: 0, mck2ui 16
4299 23:49:50.453384 best dqsien dly found for B0: ( 0, 13, 10)
4300 23:49:50.456349 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4301 23:49:50.459640 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 23:49:50.463213 Total UI for P1: 0, mck2ui 16
4303 23:49:50.465744 best dqsien dly found for B1: ( 0, 13, 18)
4304 23:49:50.469152 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4305 23:49:50.472861 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4306 23:49:50.473352
4307 23:49:50.479625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4308 23:49:50.482771 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4309 23:49:50.486166 [Gating] SW calibration Done
4310 23:49:50.486591 ==
4311 23:49:50.489069 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 23:49:50.492525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 23:49:50.492999 ==
4314 23:49:50.493336 RX Vref Scan: 0
4315 23:49:50.493649
4316 23:49:50.496102 RX Vref 0 -> 0, step: 1
4317 23:49:50.496525
4318 23:49:50.498876 RX Delay -230 -> 252, step: 16
4319 23:49:50.502293 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4320 23:49:50.508660 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4321 23:49:50.512389 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4322 23:49:50.515753 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4323 23:49:50.518720 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4324 23:49:50.522124 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4325 23:49:50.528829 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4326 23:49:50.532412 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4327 23:49:50.535697 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4328 23:49:50.538739 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4329 23:49:50.545378 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4330 23:49:50.548608 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4331 23:49:50.552317 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4332 23:49:50.555299 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4333 23:49:50.562131 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4334 23:49:50.565034 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4335 23:49:50.565625 ==
4336 23:49:50.568428 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 23:49:50.572654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 23:49:50.573198 ==
4339 23:49:50.575153 DQS Delay:
4340 23:49:50.575577 DQS0 = 0, DQS1 = 0
4341 23:49:50.575927 DQM Delay:
4342 23:49:50.578952 DQM0 = 35, DQM1 = 27
4343 23:49:50.579498 DQ Delay:
4344 23:49:50.581644 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4345 23:49:50.585373 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4346 23:49:50.588377 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4347 23:49:50.591762 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4348 23:49:50.592199
4349 23:49:50.592538
4350 23:49:50.592926 ==
4351 23:49:50.595201 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 23:49:50.601647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 23:49:50.602077 ==
4354 23:49:50.602445
4355 23:49:50.602758
4356 23:49:50.603085 TX Vref Scan disable
4357 23:49:50.605081 == TX Byte 0 ==
4358 23:49:50.608555 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4359 23:49:50.615114 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4360 23:49:50.615559 == TX Byte 1 ==
4361 23:49:50.618100 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4362 23:49:50.625132 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4363 23:49:50.625564 ==
4364 23:49:50.628345 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 23:49:50.631916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 23:49:50.632337 ==
4367 23:49:50.632730
4368 23:49:50.633051
4369 23:49:50.634911 TX Vref Scan disable
4370 23:49:50.638112 == TX Byte 0 ==
4371 23:49:50.641755 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4372 23:49:50.644835 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4373 23:49:50.647980 == TX Byte 1 ==
4374 23:49:50.651541 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4375 23:49:50.654940 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4376 23:49:50.655250
4377 23:49:50.655489 [DATLAT]
4378 23:49:50.658129 Freq=600, CH0 RK1
4379 23:49:50.658431
4380 23:49:50.658685 DATLAT Default: 0x9
4381 23:49:50.661223 0, 0xFFFF, sum = 0
4382 23:49:50.664639 1, 0xFFFF, sum = 0
4383 23:49:50.664946 2, 0xFFFF, sum = 0
4384 23:49:50.668288 3, 0xFFFF, sum = 0
4385 23:49:50.668615 4, 0xFFFF, sum = 0
4386 23:49:50.671705 5, 0xFFFF, sum = 0
4387 23:49:50.672008 6, 0xFFFF, sum = 0
4388 23:49:50.674755 7, 0xFFFF, sum = 0
4389 23:49:50.675062 8, 0x0, sum = 1
4390 23:49:50.678180 9, 0x0, sum = 2
4391 23:49:50.678489 10, 0x0, sum = 3
4392 23:49:50.678730 11, 0x0, sum = 4
4393 23:49:50.681406 best_step = 9
4394 23:49:50.681833
4395 23:49:50.682090 ==
4396 23:49:50.684522 Dram Type= 6, Freq= 0, CH_0, rank 1
4397 23:49:50.688094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 23:49:50.688492 ==
4399 23:49:50.691144 RX Vref Scan: 0
4400 23:49:50.691459
4401 23:49:50.691695 RX Vref 0 -> 0, step: 1
4402 23:49:50.694764
4403 23:49:50.695160 RX Delay -195 -> 252, step: 8
4404 23:49:50.701900 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4405 23:49:50.705364 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4406 23:49:50.708939 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4407 23:49:50.712419 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4408 23:49:50.718659 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4409 23:49:50.722078 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4410 23:49:50.725425 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4411 23:49:50.728500 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4412 23:49:50.732273 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4413 23:49:50.739194 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4414 23:49:50.742013 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4415 23:49:50.745345 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4416 23:49:50.748680 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4417 23:49:50.755410 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4418 23:49:50.758944 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4419 23:49:50.762022 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4420 23:49:50.762509 ==
4421 23:49:50.765252 Dram Type= 6, Freq= 0, CH_0, rank 1
4422 23:49:50.772239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 23:49:50.772860 ==
4424 23:49:50.773236 DQS Delay:
4425 23:49:50.773591 DQS0 = 0, DQS1 = 0
4426 23:49:50.775246 DQM Delay:
4427 23:49:50.775710 DQM0 = 33, DQM1 = 28
4428 23:49:50.778673 DQ Delay:
4429 23:49:50.781910 DQ0 =28, DQ1 =36, DQ2 =28, DQ3 =28
4430 23:49:50.782389 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4431 23:49:50.785412 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4432 23:49:50.791601 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4433 23:49:50.792132
4434 23:49:50.792689
4435 23:49:50.798991 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4436 23:49:50.802201 CH0 RK1: MR19=808, MR18=6E3E
4437 23:49:50.808343 CH0_RK1: MR19=0x808, MR18=0x6E3E, DQSOSC=389, MR23=63, INC=173, DEC=115
4438 23:49:50.811774 [RxdqsGatingPostProcess] freq 600
4439 23:49:50.815040 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4440 23:49:50.818592 Pre-setting of DQS Precalculation
4441 23:49:50.825023 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4442 23:49:50.825509 ==
4443 23:49:50.828219 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 23:49:50.831831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 23:49:50.832429 ==
4446 23:49:50.838430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4447 23:49:50.841634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4448 23:49:50.846149 [CA 0] Center 36 (6~66) winsize 61
4449 23:49:50.849225 [CA 1] Center 36 (6~66) winsize 61
4450 23:49:50.852354 [CA 2] Center 34 (4~65) winsize 62
4451 23:49:50.855594 [CA 3] Center 34 (4~65) winsize 62
4452 23:49:50.858989 [CA 4] Center 34 (4~65) winsize 62
4453 23:49:50.862354 [CA 5] Center 33 (3~64) winsize 62
4454 23:49:50.862823
4455 23:49:50.866209 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4456 23:49:50.866766
4457 23:49:50.869166 [CATrainingPosCal] consider 1 rank data
4458 23:49:50.872277 u2DelayCellTimex100 = 270/100 ps
4459 23:49:50.876104 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4460 23:49:50.882948 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4461 23:49:50.885570 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 23:49:50.889358 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 23:49:50.891970 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 23:49:50.895330 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4465 23:49:50.895799
4466 23:49:50.899289 CA PerBit enable=1, Macro0, CA PI delay=33
4467 23:49:50.899874
4468 23:49:50.902597 [CBTSetCACLKResult] CA Dly = 33
4469 23:49:50.905368 CS Dly: 4 (0~35)
4470 23:49:50.905852 ==
4471 23:49:50.908651 Dram Type= 6, Freq= 0, CH_1, rank 1
4472 23:49:50.911872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 23:49:50.912393 ==
4474 23:49:50.915528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4475 23:49:50.922276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4476 23:49:50.926000 [CA 0] Center 35 (5~66) winsize 62
4477 23:49:50.929178 [CA 1] Center 35 (5~66) winsize 62
4478 23:49:50.932701 [CA 2] Center 34 (4~65) winsize 62
4479 23:49:50.936139 [CA 3] Center 34 (3~65) winsize 63
4480 23:49:50.938892 [CA 4] Center 34 (4~65) winsize 62
4481 23:49:50.942607 [CA 5] Center 33 (3~64) winsize 62
4482 23:49:50.943088
4483 23:49:50.945746 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4484 23:49:50.946227
4485 23:49:50.949478 [CATrainingPosCal] consider 2 rank data
4486 23:49:50.952445 u2DelayCellTimex100 = 270/100 ps
4487 23:49:50.955850 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4488 23:49:50.962571 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4489 23:49:50.966456 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4490 23:49:50.968835 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4491 23:49:50.972685 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4492 23:49:50.975911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4493 23:49:50.976399
4494 23:49:50.979237 CA PerBit enable=1, Macro0, CA PI delay=33
4495 23:49:50.979765
4496 23:49:50.982445 [CBTSetCACLKResult] CA Dly = 33
4497 23:49:50.986170 CS Dly: 4 (0~36)
4498 23:49:50.986666
4499 23:49:50.988979 ----->DramcWriteLeveling(PI) begin...
4500 23:49:50.989553 ==
4501 23:49:50.992256 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 23:49:50.995998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 23:49:50.996750 ==
4504 23:49:50.998666 Write leveling (Byte 0): 29 => 29
4505 23:49:51.002032 Write leveling (Byte 1): 31 => 31
4506 23:49:51.005903 DramcWriteLeveling(PI) end<-----
4507 23:49:51.006517
4508 23:49:51.006893 ==
4509 23:49:51.008489 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 23:49:51.012045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 23:49:51.012528 ==
4512 23:49:51.015620 [Gating] SW mode calibration
4513 23:49:51.022475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4514 23:49:51.028828 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4515 23:49:51.032245 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 23:49:51.035389 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4517 23:49:51.041882 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4518 23:49:51.045524 0 9 12 | B1->B0 | 3131 3030 | 0 1 | (0 0) (1 1)
4519 23:49:51.048456 0 9 16 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
4520 23:49:51.055241 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 23:49:51.058607 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 23:49:51.061941 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 23:49:51.068541 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 23:49:51.071711 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4525 23:49:51.075150 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4526 23:49:51.081602 0 10 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4527 23:49:51.085440 0 10 16 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
4528 23:49:51.088642 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 23:49:51.095153 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 23:49:51.098067 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 23:49:51.101458 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 23:49:51.104741 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 23:49:51.111412 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 23:49:51.114922 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4535 23:49:51.118190 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 23:49:51.124787 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 23:49:51.128360 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 23:49:51.131163 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 23:49:51.138025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 23:49:51.141358 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 23:49:51.144718 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 23:49:51.151149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 23:49:51.154360 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 23:49:51.157672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 23:49:51.164179 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 23:49:51.167691 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 23:49:51.171308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 23:49:51.177816 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 23:49:51.181028 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 23:49:51.184667 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 23:49:51.191401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4552 23:49:51.191956 Total UI for P1: 0, mck2ui 16
4553 23:49:51.197924 best dqsien dly found for B0: ( 0, 13, 14)
4554 23:49:51.201236 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4555 23:49:51.204333 Total UI for P1: 0, mck2ui 16
4556 23:49:51.207573 best dqsien dly found for B1: ( 0, 13, 16)
4557 23:49:51.210855 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4558 23:49:51.214209 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4559 23:49:51.214679
4560 23:49:51.217810 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4561 23:49:51.220742 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4562 23:49:51.224110 [Gating] SW calibration Done
4563 23:49:51.224644 ==
4564 23:49:51.227637 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 23:49:51.234263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 23:49:51.234811 ==
4567 23:49:51.235264 RX Vref Scan: 0
4568 23:49:51.235618
4569 23:49:51.237491 RX Vref 0 -> 0, step: 1
4570 23:49:51.237971
4571 23:49:51.240831 RX Delay -230 -> 252, step: 16
4572 23:49:51.244113 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4573 23:49:51.247231 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4574 23:49:51.250555 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4575 23:49:51.257258 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4576 23:49:51.260883 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4577 23:49:51.264207 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4578 23:49:51.267119 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4579 23:49:51.270369 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4580 23:49:51.277185 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4581 23:49:51.280693 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4582 23:49:51.284001 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4583 23:49:51.287104 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4584 23:49:51.293538 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4585 23:49:51.296885 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4586 23:49:51.300600 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4587 23:49:51.303518 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4588 23:49:51.306993 ==
4589 23:49:51.309953 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 23:49:51.313756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 23:49:51.314280 ==
4592 23:49:51.314652 DQS Delay:
4593 23:49:51.316705 DQS0 = 0, DQS1 = 0
4594 23:49:51.317168 DQM Delay:
4595 23:49:51.319952 DQM0 = 38, DQM1 = 28
4596 23:49:51.320415 DQ Delay:
4597 23:49:51.323469 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4598 23:49:51.327142 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4599 23:49:51.330386 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4600 23:49:51.333284 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4601 23:49:51.333750
4602 23:49:51.334113
4603 23:49:51.334453 ==
4604 23:49:51.336706 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 23:49:51.340258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 23:49:51.340764 ==
4607 23:49:51.341135
4608 23:49:51.341478
4609 23:49:51.343627 TX Vref Scan disable
4610 23:49:51.346819 == TX Byte 0 ==
4611 23:49:51.355861 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4612 23:49:51.356336 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4613 23:49:51.357128 == TX Byte 1 ==
4614 23:49:51.360003 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4615 23:49:51.363263 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4616 23:49:51.363774 ==
4617 23:49:51.366418 Dram Type= 6, Freq= 0, CH_1, rank 0
4618 23:49:51.372912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 23:49:51.373383 ==
4620 23:49:51.373753
4621 23:49:51.374271
4622 23:49:51.374651 TX Vref Scan disable
4623 23:49:51.377036 == TX Byte 0 ==
4624 23:49:51.380509 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4625 23:49:51.387258 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4626 23:49:51.387817 == TX Byte 1 ==
4627 23:49:51.390781 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4628 23:49:51.397078 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4629 23:49:51.397544
4630 23:49:51.397908 [DATLAT]
4631 23:49:51.398246 Freq=600, CH1 RK0
4632 23:49:51.398574
4633 23:49:51.401167 DATLAT Default: 0x9
4634 23:49:51.401753 0, 0xFFFF, sum = 0
4635 23:49:51.404073 1, 0xFFFF, sum = 0
4636 23:49:51.406981 2, 0xFFFF, sum = 0
4637 23:49:51.407455 3, 0xFFFF, sum = 0
4638 23:49:51.410027 4, 0xFFFF, sum = 0
4639 23:49:51.410713 5, 0xFFFF, sum = 0
4640 23:49:51.413592 6, 0xFFFF, sum = 0
4641 23:49:51.414061 7, 0xFFFF, sum = 0
4642 23:49:51.417132 8, 0x0, sum = 1
4643 23:49:51.417600 9, 0x0, sum = 2
4644 23:49:51.420316 10, 0x0, sum = 3
4645 23:49:51.420822 11, 0x0, sum = 4
4646 23:49:51.421201 best_step = 9
4647 23:49:51.421541
4648 23:49:51.423967 ==
4649 23:49:51.424429 Dram Type= 6, Freq= 0, CH_1, rank 0
4650 23:49:51.430041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 23:49:51.430633 ==
4652 23:49:51.431017 RX Vref Scan: 1
4653 23:49:51.431360
4654 23:49:51.433371 RX Vref 0 -> 0, step: 1
4655 23:49:51.433835
4656 23:49:51.436877 RX Delay -195 -> 252, step: 8
4657 23:49:51.437375
4658 23:49:51.440221 Set Vref, RX VrefLevel [Byte0]: 55
4659 23:49:51.443904 [Byte1]: 50
4660 23:49:51.444366
4661 23:49:51.447018 Final RX Vref Byte 0 = 55 to rank0
4662 23:49:51.450187 Final RX Vref Byte 1 = 50 to rank0
4663 23:49:51.453572 Final RX Vref Byte 0 = 55 to rank1
4664 23:49:51.456608 Final RX Vref Byte 1 = 50 to rank1==
4665 23:49:51.459821 Dram Type= 6, Freq= 0, CH_1, rank 0
4666 23:49:51.463478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 23:49:51.464115 ==
4668 23:49:51.466680 DQS Delay:
4669 23:49:51.467239 DQS0 = 0, DQS1 = 0
4670 23:49:51.470213 DQM Delay:
4671 23:49:51.470777 DQM0 = 38, DQM1 = 30
4672 23:49:51.471147 DQ Delay:
4673 23:49:51.473374 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4674 23:49:51.476682 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4675 23:49:51.480377 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4676 23:49:51.483363 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4677 23:49:51.483920
4678 23:49:51.484280
4679 23:49:51.493419 [DQSOSCAuto] RK0, (LSB)MR18= 0x222f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4680 23:49:51.496356 CH1 RK0: MR19=808, MR18=222F
4681 23:49:51.502841 CH1_RK0: MR19=0x808, MR18=0x222F, DQSOSC=400, MR23=63, INC=163, DEC=109
4682 23:49:51.503392
4683 23:49:51.506208 ----->DramcWriteLeveling(PI) begin...
4684 23:49:51.506729 ==
4685 23:49:51.509550 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 23:49:51.512751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 23:49:51.513222 ==
4688 23:49:51.515916 Write leveling (Byte 0): 30 => 30
4689 23:49:51.519959 Write leveling (Byte 1): 30 => 30
4690 23:49:51.523294 DramcWriteLeveling(PI) end<-----
4691 23:49:51.523851
4692 23:49:51.524218 ==
4693 23:49:51.526227 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 23:49:51.529900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 23:49:51.530473 ==
4696 23:49:51.533286 [Gating] SW mode calibration
4697 23:49:51.539246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4698 23:49:51.546450 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4699 23:49:51.549370 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4700 23:49:51.553053 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4701 23:49:51.559498 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4702 23:49:51.562881 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 0)
4703 23:49:51.565761 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 23:49:51.572625 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 23:49:51.575968 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 23:49:51.579297 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 23:49:51.585737 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 23:49:51.588990 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4709 23:49:51.591939 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4710 23:49:51.598613 0 10 12 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
4711 23:49:51.601692 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4712 23:49:51.605460 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 23:49:51.611920 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 23:49:51.615040 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 23:49:51.618460 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 23:49:51.624925 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 23:49:51.628324 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 23:49:51.631421 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 23:49:51.638336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4720 23:49:51.642026 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 23:49:51.644784 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 23:49:51.651895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 23:49:51.655260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 23:49:51.658145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 23:49:51.664832 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 23:49:51.667744 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 23:49:51.671381 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 23:49:51.678115 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 23:49:51.681453 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 23:49:51.684881 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 23:49:51.691411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 23:49:51.694737 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 23:49:51.697981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 23:49:51.704576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 23:49:51.705042 Total UI for P1: 0, mck2ui 16
4736 23:49:51.711027 best dqsien dly found for B0: ( 0, 13, 10)
4737 23:49:51.711456 Total UI for P1: 0, mck2ui 16
4738 23:49:51.718033 best dqsien dly found for B1: ( 0, 13, 10)
4739 23:49:51.721026 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4740 23:49:51.724425 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4741 23:49:51.724893
4742 23:49:51.727369 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4743 23:49:51.730811 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4744 23:49:51.734449 [Gating] SW calibration Done
4745 23:49:51.734899 ==
4746 23:49:51.737640 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 23:49:51.741183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 23:49:51.741623 ==
4749 23:49:51.744514 RX Vref Scan: 0
4750 23:49:51.744987
4751 23:49:51.745428 RX Vref 0 -> 0, step: 1
4752 23:49:51.745844
4753 23:49:51.747936 RX Delay -230 -> 252, step: 16
4754 23:49:51.754140 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4755 23:49:51.757523 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4756 23:49:51.760860 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4757 23:49:51.764663 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4758 23:49:51.768003 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4759 23:49:51.774293 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4760 23:49:51.777803 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4761 23:49:51.781261 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4762 23:49:51.784343 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4763 23:49:51.790988 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4764 23:49:51.794311 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4765 23:49:51.797542 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4766 23:49:51.801271 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4767 23:49:51.807274 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4768 23:49:51.810401 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4769 23:49:51.814001 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4770 23:49:51.814593 ==
4771 23:49:51.817843 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 23:49:51.820440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 23:49:51.820950 ==
4774 23:49:51.823940 DQS Delay:
4775 23:49:51.824397 DQS0 = 0, DQS1 = 0
4776 23:49:51.827425 DQM Delay:
4777 23:49:51.827880 DQM0 = 40, DQM1 = 34
4778 23:49:51.830530 DQ Delay:
4779 23:49:51.830989 DQ0 =41, DQ1 =41, DQ2 =17, DQ3 =41
4780 23:49:51.833768 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4781 23:49:51.837186 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4782 23:49:51.840658 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4783 23:49:51.841108
4784 23:49:51.843577
4785 23:49:51.844088 ==
4786 23:49:51.847033 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 23:49:51.850519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 23:49:51.851045 ==
4789 23:49:51.851468
4790 23:49:51.851787
4791 23:49:51.853870 TX Vref Scan disable
4792 23:49:51.854384 == TX Byte 0 ==
4793 23:49:51.860096 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4794 23:49:51.863691 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4795 23:49:51.864224 == TX Byte 1 ==
4796 23:49:51.870755 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4797 23:49:51.873430 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4798 23:49:51.874043 ==
4799 23:49:51.876993 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 23:49:51.880178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 23:49:51.880800 ==
4802 23:49:51.881256
4803 23:49:51.881639
4804 23:49:51.883443 TX Vref Scan disable
4805 23:49:51.886729 == TX Byte 0 ==
4806 23:49:51.889911 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4807 23:49:51.893593 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4808 23:49:51.896802 == TX Byte 1 ==
4809 23:49:51.899835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4810 23:49:51.903500 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4811 23:49:51.903917
4812 23:49:51.906388 [DATLAT]
4813 23:49:51.907001 Freq=600, CH1 RK1
4814 23:49:51.907358
4815 23:49:51.909667 DATLAT Default: 0x9
4816 23:49:51.910083 0, 0xFFFF, sum = 0
4817 23:49:51.913116 1, 0xFFFF, sum = 0
4818 23:49:51.913561 2, 0xFFFF, sum = 0
4819 23:49:51.916755 3, 0xFFFF, sum = 0
4820 23:49:51.917180 4, 0xFFFF, sum = 0
4821 23:49:51.919855 5, 0xFFFF, sum = 0
4822 23:49:51.920280 6, 0xFFFF, sum = 0
4823 23:49:51.922968 7, 0xFFFF, sum = 0
4824 23:49:51.923390 8, 0x0, sum = 1
4825 23:49:51.926347 9, 0x0, sum = 2
4826 23:49:51.926772 10, 0x0, sum = 3
4827 23:49:51.929559 11, 0x0, sum = 4
4828 23:49:51.929984 best_step = 9
4829 23:49:51.930314
4830 23:49:51.930619 ==
4831 23:49:51.932926 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 23:49:51.939677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 23:49:51.940098 ==
4834 23:49:51.940427 RX Vref Scan: 0
4835 23:49:51.940781
4836 23:49:51.942991 RX Vref 0 -> 0, step: 1
4837 23:49:51.943410
4838 23:49:51.946164 RX Delay -195 -> 252, step: 8
4839 23:49:51.949679 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4840 23:49:51.956528 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4841 23:49:51.959360 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4842 23:49:51.963173 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4843 23:49:51.966213 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4844 23:49:51.969690 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4845 23:49:51.976585 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4846 23:49:51.979332 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4847 23:49:51.982812 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4848 23:49:51.986307 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4849 23:49:51.993035 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4850 23:49:51.995984 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4851 23:49:51.999913 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4852 23:49:52.003147 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4853 23:49:52.009333 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4854 23:49:52.012641 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4855 23:49:52.013096 ==
4856 23:49:52.015694 Dram Type= 6, Freq= 0, CH_1, rank 1
4857 23:49:52.019445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4858 23:49:52.019863 ==
4859 23:49:52.022967 DQS Delay:
4860 23:49:52.023416 DQS0 = 0, DQS1 = 0
4861 23:49:52.023783 DQM Delay:
4862 23:49:52.025814 DQM0 = 36, DQM1 = 30
4863 23:49:52.026229 DQ Delay:
4864 23:49:52.029125 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4865 23:49:52.032692 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4866 23:49:52.036116 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4867 23:49:52.039454 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4868 23:49:52.039908
4869 23:49:52.040256
4870 23:49:52.049089 [DQSOSCAuto] RK1, (LSB)MR18= 0x3556, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4871 23:49:52.049576 CH1 RK1: MR19=808, MR18=3556
4872 23:49:52.056040 CH1_RK1: MR19=0x808, MR18=0x3556, DQSOSC=393, MR23=63, INC=169, DEC=113
4873 23:49:52.059250 [RxdqsGatingPostProcess] freq 600
4874 23:49:52.066051 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4875 23:49:52.069197 Pre-setting of DQS Precalculation
4876 23:49:52.072868 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4877 23:49:52.079007 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4878 23:49:52.089166 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4879 23:49:52.089800
4880 23:49:52.090146
4881 23:49:52.092198 [Calibration Summary] 1200 Mbps
4882 23:49:52.092802 CH 0, Rank 0
4883 23:49:52.095717 SW Impedance : PASS
4884 23:49:52.096137 DUTY Scan : NO K
4885 23:49:52.099137 ZQ Calibration : PASS
4886 23:49:52.102093 Jitter Meter : NO K
4887 23:49:52.102619 CBT Training : PASS
4888 23:49:52.105443 Write leveling : PASS
4889 23:49:52.106000 RX DQS gating : PASS
4890 23:49:52.108788 RX DQ/DQS(RDDQC) : PASS
4891 23:49:52.112484 TX DQ/DQS : PASS
4892 23:49:52.113128 RX DATLAT : PASS
4893 23:49:52.115690 RX DQ/DQS(Engine): PASS
4894 23:49:52.118634 TX OE : NO K
4895 23:49:52.119054 All Pass.
4896 23:49:52.119382
4897 23:49:52.119690 CH 0, Rank 1
4898 23:49:52.122146 SW Impedance : PASS
4899 23:49:52.125296 DUTY Scan : NO K
4900 23:49:52.125716 ZQ Calibration : PASS
4901 23:49:52.129027 Jitter Meter : NO K
4902 23:49:52.131957 CBT Training : PASS
4903 23:49:52.132441 Write leveling : PASS
4904 23:49:52.135354 RX DQS gating : PASS
4905 23:49:52.138588 RX DQ/DQS(RDDQC) : PASS
4906 23:49:52.139007 TX DQ/DQS : PASS
4907 23:49:52.142061 RX DATLAT : PASS
4908 23:49:52.145102 RX DQ/DQS(Engine): PASS
4909 23:49:52.145521 TX OE : NO K
4910 23:49:52.149003 All Pass.
4911 23:49:52.149538
4912 23:49:52.149877 CH 1, Rank 0
4913 23:49:52.152308 SW Impedance : PASS
4914 23:49:52.152770 DUTY Scan : NO K
4915 23:49:52.155342 ZQ Calibration : PASS
4916 23:49:52.155761 Jitter Meter : NO K
4917 23:49:52.158679 CBT Training : PASS
4918 23:49:52.161997 Write leveling : PASS
4919 23:49:52.162419 RX DQS gating : PASS
4920 23:49:52.165437 RX DQ/DQS(RDDQC) : PASS
4921 23:49:52.168668 TX DQ/DQS : PASS
4922 23:49:52.169087 RX DATLAT : PASS
4923 23:49:52.171848 RX DQ/DQS(Engine): PASS
4924 23:49:52.175035 TX OE : NO K
4925 23:49:52.175624 All Pass.
4926 23:49:52.175971
4927 23:49:52.176543 CH 1, Rank 1
4928 23:49:52.178752 SW Impedance : PASS
4929 23:49:52.181639 DUTY Scan : NO K
4930 23:49:52.182093 ZQ Calibration : PASS
4931 23:49:52.185096 Jitter Meter : NO K
4932 23:49:52.188957 CBT Training : PASS
4933 23:49:52.189374 Write leveling : PASS
4934 23:49:52.191846 RX DQS gating : PASS
4935 23:49:52.195161 RX DQ/DQS(RDDQC) : PASS
4936 23:49:52.195614 TX DQ/DQS : PASS
4937 23:49:52.198865 RX DATLAT : PASS
4938 23:49:52.201824 RX DQ/DQS(Engine): PASS
4939 23:49:52.202347 TX OE : NO K
4940 23:49:52.205066 All Pass.
4941 23:49:52.205519
4942 23:49:52.205869 DramC Write-DBI off
4943 23:49:52.208387 PER_BANK_REFRESH: Hybrid Mode
4944 23:49:52.208865 TX_TRACKING: ON
4945 23:49:52.218630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4946 23:49:52.221907 [FAST_K] Save calibration result to emmc
4947 23:49:52.224641 dramc_set_vcore_voltage set vcore to 662500
4948 23:49:52.227989 Read voltage for 933, 3
4949 23:49:52.228402 Vio18 = 0
4950 23:49:52.231339 Vcore = 662500
4951 23:49:52.231750 Vdram = 0
4952 23:49:52.232105 Vddq = 0
4953 23:49:52.232683 Vmddr = 0
4954 23:49:52.238263 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4955 23:49:52.244600 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4956 23:49:52.245058 MEM_TYPE=3, freq_sel=17
4957 23:49:52.248363 sv_algorithm_assistance_LP4_1600
4958 23:49:52.251177 ============ PULL DRAM RESETB DOWN ============
4959 23:49:52.257953 ========== PULL DRAM RESETB DOWN end =========
4960 23:49:52.261634 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4961 23:49:52.264850 ===================================
4962 23:49:52.268314 LPDDR4 DRAM CONFIGURATION
4963 23:49:52.271348 ===================================
4964 23:49:52.271800 EX_ROW_EN[0] = 0x0
4965 23:49:52.275029 EX_ROW_EN[1] = 0x0
4966 23:49:52.275588 LP4Y_EN = 0x0
4967 23:49:52.277640 WORK_FSP = 0x0
4968 23:49:52.278091 WL = 0x3
4969 23:49:52.281140 RL = 0x3
4970 23:49:52.284621 BL = 0x2
4971 23:49:52.285242 RPST = 0x0
4972 23:49:52.288088 RD_PRE = 0x0
4973 23:49:52.288541 WR_PRE = 0x1
4974 23:49:52.290884 WR_PST = 0x0
4975 23:49:52.291335 DBI_WR = 0x0
4976 23:49:52.294293 DBI_RD = 0x0
4977 23:49:52.294750 OTF = 0x1
4978 23:49:52.297862 ===================================
4979 23:49:52.300782 ===================================
4980 23:49:52.304217 ANA top config
4981 23:49:52.307921 ===================================
4982 23:49:52.308449 DLL_ASYNC_EN = 0
4983 23:49:52.310782 ALL_SLAVE_EN = 1
4984 23:49:52.314202 NEW_RANK_MODE = 1
4985 23:49:52.317673 DLL_IDLE_MODE = 1
4986 23:49:52.320521 LP45_APHY_COMB_EN = 1
4987 23:49:52.321016 TX_ODT_DIS = 1
4988 23:49:52.324038 NEW_8X_MODE = 1
4989 23:49:52.327336 ===================================
4990 23:49:52.331012 ===================================
4991 23:49:52.334278 data_rate = 1866
4992 23:49:52.337123 CKR = 1
4993 23:49:52.340836 DQ_P2S_RATIO = 8
4994 23:49:52.344420 ===================================
4995 23:49:52.344933 CA_P2S_RATIO = 8
4996 23:49:52.347583 DQ_CA_OPEN = 0
4997 23:49:52.351011 DQ_SEMI_OPEN = 0
4998 23:49:52.354114 CA_SEMI_OPEN = 0
4999 23:49:52.357105 CA_FULL_RATE = 0
5000 23:49:52.360653 DQ_CKDIV4_EN = 1
5001 23:49:52.361125 CA_CKDIV4_EN = 1
5002 23:49:52.363803 CA_PREDIV_EN = 0
5003 23:49:52.367353 PH8_DLY = 0
5004 23:49:52.370285 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5005 23:49:52.373565 DQ_AAMCK_DIV = 4
5006 23:49:52.377209 CA_AAMCK_DIV = 4
5007 23:49:52.377763 CA_ADMCK_DIV = 4
5008 23:49:52.380190 DQ_TRACK_CA_EN = 0
5009 23:49:52.383939 CA_PICK = 933
5010 23:49:52.386929 CA_MCKIO = 933
5011 23:49:52.390262 MCKIO_SEMI = 0
5012 23:49:52.393817 PLL_FREQ = 3732
5013 23:49:52.397066 DQ_UI_PI_RATIO = 32
5014 23:49:52.397519 CA_UI_PI_RATIO = 0
5015 23:49:52.400437 ===================================
5016 23:49:52.403897 ===================================
5017 23:49:52.407427 memory_type:LPDDR4
5018 23:49:52.410208 GP_NUM : 10
5019 23:49:52.410763 SRAM_EN : 1
5020 23:49:52.413391 MD32_EN : 0
5021 23:49:52.417075 ===================================
5022 23:49:52.420351 [ANA_INIT] >>>>>>>>>>>>>>
5023 23:49:52.423717 <<<<<< [CONFIGURE PHASE]: ANA_TX
5024 23:49:52.427371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5025 23:49:52.429955 ===================================
5026 23:49:52.430407 data_rate = 1866,PCW = 0X8f00
5027 23:49:52.433323 ===================================
5028 23:49:52.436765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5029 23:49:52.443270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5030 23:49:52.450313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5031 23:49:52.453221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5032 23:49:52.456798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5033 23:49:52.460333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5034 23:49:52.463697 [ANA_INIT] flow start
5035 23:49:52.466725 [ANA_INIT] PLL >>>>>>>>
5036 23:49:52.467176 [ANA_INIT] PLL <<<<<<<<
5037 23:49:52.469822 [ANA_INIT] MIDPI >>>>>>>>
5038 23:49:52.473181 [ANA_INIT] MIDPI <<<<<<<<
5039 23:49:52.473623 [ANA_INIT] DLL >>>>>>>>
5040 23:49:52.476375 [ANA_INIT] flow end
5041 23:49:52.480160 ============ LP4 DIFF to SE enter ============
5042 23:49:52.483192 ============ LP4 DIFF to SE exit ============
5043 23:49:52.486520 [ANA_INIT] <<<<<<<<<<<<<
5044 23:49:52.489845 [Flow] Enable top DCM control >>>>>
5045 23:49:52.493276 [Flow] Enable top DCM control <<<<<
5046 23:49:52.496346 Enable DLL master slave shuffle
5047 23:49:52.502894 ==============================================================
5048 23:49:52.503329 Gating Mode config
5049 23:49:52.509432 ==============================================================
5050 23:49:52.509848 Config description:
5051 23:49:52.519323 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5052 23:49:52.526354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5053 23:49:52.532618 SELPH_MODE 0: By rank 1: By Phase
5054 23:49:52.539488 ==============================================================
5055 23:49:52.539948 GAT_TRACK_EN = 1
5056 23:49:52.542493 RX_GATING_MODE = 2
5057 23:49:52.546281 RX_GATING_TRACK_MODE = 2
5058 23:49:52.549521 SELPH_MODE = 1
5059 23:49:52.552989 PICG_EARLY_EN = 1
5060 23:49:52.555780 VALID_LAT_VALUE = 1
5061 23:49:52.562466 ==============================================================
5062 23:49:52.566027 Enter into Gating configuration >>>>
5063 23:49:52.569086 Exit from Gating configuration <<<<
5064 23:49:52.572433 Enter into DVFS_PRE_config >>>>>
5065 23:49:52.582741 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5066 23:49:52.585904 Exit from DVFS_PRE_config <<<<<
5067 23:49:52.588806 Enter into PICG configuration >>>>
5068 23:49:52.592205 Exit from PICG configuration <<<<
5069 23:49:52.595867 [RX_INPUT] configuration >>>>>
5070 23:49:52.596427 [RX_INPUT] configuration <<<<<
5071 23:49:52.602500 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5072 23:49:52.608854 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5073 23:49:52.615701 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 23:49:52.619027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 23:49:52.625297 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5076 23:49:52.632433 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5077 23:49:52.635712 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5078 23:49:52.638820 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5079 23:49:52.645902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5080 23:49:52.648776 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5081 23:49:52.652236 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5082 23:49:52.658350 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5083 23:49:52.661881 ===================================
5084 23:49:52.662344 LPDDR4 DRAM CONFIGURATION
5085 23:49:52.665610 ===================================
5086 23:49:52.668921 EX_ROW_EN[0] = 0x0
5087 23:49:52.672093 EX_ROW_EN[1] = 0x0
5088 23:49:52.672708 LP4Y_EN = 0x0
5089 23:49:52.675233 WORK_FSP = 0x0
5090 23:49:52.675695 WL = 0x3
5091 23:49:52.678252 RL = 0x3
5092 23:49:52.678666 BL = 0x2
5093 23:49:52.681945 RPST = 0x0
5094 23:49:52.682394 RD_PRE = 0x0
5095 23:49:52.685331 WR_PRE = 0x1
5096 23:49:52.685742 WR_PST = 0x0
5097 23:49:52.688427 DBI_WR = 0x0
5098 23:49:52.688933 DBI_RD = 0x0
5099 23:49:52.691629 OTF = 0x1
5100 23:49:52.694916 ===================================
5101 23:49:52.698184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5102 23:49:52.701386 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5103 23:49:52.708303 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5104 23:49:52.711452 ===================================
5105 23:49:52.711992 LPDDR4 DRAM CONFIGURATION
5106 23:49:52.715448 ===================================
5107 23:49:52.718379 EX_ROW_EN[0] = 0x10
5108 23:49:52.721364 EX_ROW_EN[1] = 0x0
5109 23:49:52.721784 LP4Y_EN = 0x0
5110 23:49:52.724675 WORK_FSP = 0x0
5111 23:49:52.725093 WL = 0x3
5112 23:49:52.727766 RL = 0x3
5113 23:49:52.728185 BL = 0x2
5114 23:49:52.731373 RPST = 0x0
5115 23:49:52.731789 RD_PRE = 0x0
5116 23:49:52.734647 WR_PRE = 0x1
5117 23:49:52.735065 WR_PST = 0x0
5118 23:49:52.737900 DBI_WR = 0x0
5119 23:49:52.738521 DBI_RD = 0x0
5120 23:49:52.741282 OTF = 0x1
5121 23:49:52.745030 ===================================
5122 23:49:52.750973 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5123 23:49:52.754752 nWR fixed to 30
5124 23:49:52.755174 [ModeRegInit_LP4] CH0 RK0
5125 23:49:52.757664 [ModeRegInit_LP4] CH0 RK1
5126 23:49:52.760972 [ModeRegInit_LP4] CH1 RK0
5127 23:49:52.764544 [ModeRegInit_LP4] CH1 RK1
5128 23:49:52.764991 match AC timing 9
5129 23:49:52.767963 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5130 23:49:52.774477 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5131 23:49:52.777635 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5132 23:49:52.784578 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5133 23:49:52.787271 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5134 23:49:52.787689 ==
5135 23:49:52.790818 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 23:49:52.794274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 23:49:52.794695 ==
5138 23:49:52.800883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 23:49:52.807357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5140 23:49:52.810585 [CA 0] Center 38 (8~69) winsize 62
5141 23:49:52.814117 [CA 1] Center 38 (8~69) winsize 62
5142 23:49:52.817335 [CA 2] Center 35 (5~66) winsize 62
5143 23:49:52.820885 [CA 3] Center 35 (5~66) winsize 62
5144 23:49:52.824058 [CA 4] Center 34 (4~65) winsize 62
5145 23:49:52.826908 [CA 5] Center 34 (4~64) winsize 61
5146 23:49:52.827332
5147 23:49:52.830380 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5148 23:49:52.830805
5149 23:49:52.834234 [CATrainingPosCal] consider 1 rank data
5150 23:49:52.837257 u2DelayCellTimex100 = 270/100 ps
5151 23:49:52.840525 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5152 23:49:52.844011 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5153 23:49:52.847202 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5154 23:49:52.850819 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5155 23:49:52.853594 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5156 23:49:52.857164 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5157 23:49:52.857588
5158 23:49:52.863912 CA PerBit enable=1, Macro0, CA PI delay=34
5159 23:49:52.864337
5160 23:49:52.864727 [CBTSetCACLKResult] CA Dly = 34
5161 23:49:52.866719 CS Dly: 6 (0~37)
5162 23:49:52.867139 ==
5163 23:49:52.870628 Dram Type= 6, Freq= 0, CH_0, rank 1
5164 23:49:52.873854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 23:49:52.874280 ==
5166 23:49:52.880264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5167 23:49:52.887336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5168 23:49:52.890767 [CA 0] Center 38 (8~69) winsize 62
5169 23:49:52.893680 [CA 1] Center 38 (7~69) winsize 63
5170 23:49:52.897004 [CA 2] Center 35 (5~66) winsize 62
5171 23:49:52.900362 [CA 3] Center 35 (5~66) winsize 62
5172 23:49:52.903773 [CA 4] Center 34 (4~65) winsize 62
5173 23:49:52.907239 [CA 5] Center 33 (3~64) winsize 62
5174 23:49:52.907662
5175 23:49:52.910402 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5176 23:49:52.910969
5177 23:49:52.913881 [CATrainingPosCal] consider 2 rank data
5178 23:49:52.916996 u2DelayCellTimex100 = 270/100 ps
5179 23:49:52.920333 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5180 23:49:52.923701 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5181 23:49:52.926801 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5182 23:49:52.930019 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5183 23:49:52.933621 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5184 23:49:52.936686 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5185 23:49:52.937108
5186 23:49:52.943298 CA PerBit enable=1, Macro0, CA PI delay=34
5187 23:49:52.943738
5188 23:49:52.944068 [CBTSetCACLKResult] CA Dly = 34
5189 23:49:52.946780 CS Dly: 7 (0~39)
5190 23:49:52.947200
5191 23:49:52.949998 ----->DramcWriteLeveling(PI) begin...
5192 23:49:52.950425 ==
5193 23:49:52.953434 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 23:49:52.956826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 23:49:52.957251 ==
5196 23:49:52.960549 Write leveling (Byte 0): 33 => 33
5197 23:49:52.963078 Write leveling (Byte 1): 29 => 29
5198 23:49:52.966610 DramcWriteLeveling(PI) end<-----
5199 23:49:52.967039
5200 23:49:52.967370 ==
5201 23:49:52.970390 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 23:49:52.976756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 23:49:52.977283 ==
5204 23:49:52.977621 [Gating] SW mode calibration
5205 23:49:52.986718 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5206 23:49:52.990255 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5207 23:49:52.992996 0 14 0 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
5208 23:49:52.999791 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5209 23:49:53.003287 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 23:49:53.009810 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 23:49:53.012949 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 23:49:53.016221 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5213 23:49:53.019389 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5214 23:49:53.026115 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5215 23:49:53.029330 0 15 0 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (1 0)
5216 23:49:53.032677 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5217 23:49:53.039348 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 23:49:53.042778 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 23:49:53.046136 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 23:49:53.052833 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5221 23:49:53.055486 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5222 23:49:53.059352 0 15 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5223 23:49:53.066173 1 0 0 | B1->B0 | 2626 3f3f | 0 0 | (0 0) (0 0)
5224 23:49:53.069276 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5225 23:49:53.072815 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 23:49:53.079269 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 23:49:53.082575 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 23:49:53.085522 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 23:49:53.092279 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 23:49:53.095798 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5231 23:49:53.099294 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5232 23:49:53.105790 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5233 23:49:53.109098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 23:49:53.112353 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 23:49:53.119250 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 23:49:53.122115 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 23:49:53.125955 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 23:49:53.131710 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 23:49:53.135249 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 23:49:53.138827 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 23:49:53.145092 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 23:49:53.148670 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 23:49:53.152048 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 23:49:53.158663 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 23:49:53.161743 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 23:49:53.165131 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 23:49:53.171507 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5248 23:49:53.175056 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 23:49:53.178630 Total UI for P1: 0, mck2ui 16
5250 23:49:53.181837 best dqsien dly found for B0: ( 1, 3, 0)
5251 23:49:53.185023 Total UI for P1: 0, mck2ui 16
5252 23:49:53.188554 best dqsien dly found for B1: ( 1, 3, 2)
5253 23:49:53.191452 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5254 23:49:53.195191 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5255 23:49:53.195742
5256 23:49:53.198098 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5257 23:49:53.201566 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5258 23:49:53.205124 [Gating] SW calibration Done
5259 23:49:53.205592 ==
5260 23:49:53.208618 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 23:49:53.211595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 23:49:53.212182 ==
5263 23:49:53.214689 RX Vref Scan: 0
5264 23:49:53.215157
5265 23:49:53.218087 RX Vref 0 -> 0, step: 1
5266 23:49:53.218552
5267 23:49:53.218920 RX Delay -80 -> 252, step: 8
5268 23:49:53.225016 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5269 23:49:53.228006 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5270 23:49:53.231106 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5271 23:49:53.234953 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5272 23:49:53.237805 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5273 23:49:53.241181 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5274 23:49:53.248154 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5275 23:49:53.251157 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5276 23:49:53.254610 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5277 23:49:53.257767 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5278 23:49:53.261610 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5279 23:49:53.267755 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5280 23:49:53.271257 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5281 23:49:53.274433 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5282 23:49:53.277572 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5283 23:49:53.281256 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5284 23:49:53.281752 ==
5285 23:49:53.284272 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 23:49:53.291470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 23:49:53.292063 ==
5288 23:49:53.292434 DQS Delay:
5289 23:49:53.294419 DQS0 = 0, DQS1 = 0
5290 23:49:53.294907 DQM Delay:
5291 23:49:53.297397 DQM0 = 94, DQM1 = 82
5292 23:49:53.298062 DQ Delay:
5293 23:49:53.300956 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5294 23:49:53.304199 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5295 23:49:53.307781 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5296 23:49:53.311002 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5297 23:49:53.311474
5298 23:49:53.311807
5299 23:49:53.312130 ==
5300 23:49:53.314601 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 23:49:53.317429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 23:49:53.317879 ==
5303 23:49:53.318217
5304 23:49:53.318529
5305 23:49:53.320715 TX Vref Scan disable
5306 23:49:53.324406 == TX Byte 0 ==
5307 23:49:53.327553 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5308 23:49:53.330759 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5309 23:49:53.334252 == TX Byte 1 ==
5310 23:49:53.337566 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5311 23:49:53.340708 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5312 23:49:53.341132 ==
5313 23:49:53.344143 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 23:49:53.347806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 23:49:53.350678 ==
5316 23:49:53.351097
5317 23:49:53.351428
5318 23:49:53.351737 TX Vref Scan disable
5319 23:49:53.354563 == TX Byte 0 ==
5320 23:49:53.357513 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5321 23:49:53.364185 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5322 23:49:53.364737 == TX Byte 1 ==
5323 23:49:53.367582 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5324 23:49:53.374535 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5325 23:49:53.375115
5326 23:49:53.375484 [DATLAT]
5327 23:49:53.375827 Freq=933, CH0 RK0
5328 23:49:53.376158
5329 23:49:53.377422 DATLAT Default: 0xd
5330 23:49:53.377886 0, 0xFFFF, sum = 0
5331 23:49:53.380808 1, 0xFFFF, sum = 0
5332 23:49:53.381371 2, 0xFFFF, sum = 0
5333 23:49:53.384112 3, 0xFFFF, sum = 0
5334 23:49:53.387475 4, 0xFFFF, sum = 0
5335 23:49:53.387949 5, 0xFFFF, sum = 0
5336 23:49:53.390702 6, 0xFFFF, sum = 0
5337 23:49:53.391176 7, 0xFFFF, sum = 0
5338 23:49:53.394597 8, 0xFFFF, sum = 0
5339 23:49:53.395187 9, 0xFFFF, sum = 0
5340 23:49:53.397759 10, 0x0, sum = 1
5341 23:49:53.398236 11, 0x0, sum = 2
5342 23:49:53.401038 12, 0x0, sum = 3
5343 23:49:53.401513 13, 0x0, sum = 4
5344 23:49:53.401891 best_step = 11
5345 23:49:53.402234
5346 23:49:53.404347 ==
5347 23:49:53.407411 Dram Type= 6, Freq= 0, CH_0, rank 0
5348 23:49:53.410652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 23:49:53.411122 ==
5350 23:49:53.411484 RX Vref Scan: 1
5351 23:49:53.411824
5352 23:49:53.413971 RX Vref 0 -> 0, step: 1
5353 23:49:53.414436
5354 23:49:53.417138 RX Delay -69 -> 252, step: 4
5355 23:49:53.417558
5356 23:49:53.420391 Set Vref, RX VrefLevel [Byte0]: 60
5357 23:49:53.424083 [Byte1]: 47
5358 23:49:53.424507
5359 23:49:53.427231 Final RX Vref Byte 0 = 60 to rank0
5360 23:49:53.431063 Final RX Vref Byte 1 = 47 to rank0
5361 23:49:53.433694 Final RX Vref Byte 0 = 60 to rank1
5362 23:49:53.437063 Final RX Vref Byte 1 = 47 to rank1==
5363 23:49:53.440623 Dram Type= 6, Freq= 0, CH_0, rank 0
5364 23:49:53.443609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 23:49:53.447006 ==
5366 23:49:53.447426 DQS Delay:
5367 23:49:53.447759 DQS0 = 0, DQS1 = 0
5368 23:49:53.450577 DQM Delay:
5369 23:49:53.450873 DQM0 = 95, DQM1 = 83
5370 23:49:53.453878 DQ Delay:
5371 23:49:53.456914 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5372 23:49:53.457218 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5373 23:49:53.460346 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =76
5374 23:49:53.467260 DQ12 =86, DQ13 =88, DQ14 =92, DQ15 =92
5375 23:49:53.467708
5376 23:49:53.467963
5377 23:49:53.473503 [DQSOSCAuto] RK0, (LSB)MR18= 0x1817, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5378 23:49:53.476792 CH0 RK0: MR19=505, MR18=1817
5379 23:49:53.483274 CH0_RK0: MR19=0x505, MR18=0x1817, DQSOSC=414, MR23=63, INC=63, DEC=42
5380 23:49:53.483673
5381 23:49:53.486718 ----->DramcWriteLeveling(PI) begin...
5382 23:49:53.487145 ==
5383 23:49:53.490331 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 23:49:53.493701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 23:49:53.494123 ==
5386 23:49:53.496750 Write leveling (Byte 0): 31 => 31
5387 23:49:53.500252 Write leveling (Byte 1): 30 => 30
5388 23:49:53.503493 DramcWriteLeveling(PI) end<-----
5389 23:49:53.503914
5390 23:49:53.504242 ==
5391 23:49:53.506809 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 23:49:53.510043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 23:49:53.510510 ==
5394 23:49:53.513642 [Gating] SW mode calibration
5395 23:49:53.520842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5396 23:49:53.526558 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5397 23:49:53.530074 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
5398 23:49:53.533898 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 23:49:53.540410 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 23:49:53.543215 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 23:49:53.547224 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 23:49:53.553482 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5403 23:49:53.556376 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5404 23:49:53.559915 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5405 23:49:53.566988 0 15 0 | B1->B0 | 2a2a 2323 | 1 0 | (0 1) (0 0)
5406 23:49:53.569700 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 23:49:53.572909 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 23:49:53.579837 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 23:49:53.582889 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 23:49:53.586293 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5411 23:49:53.592744 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5412 23:49:53.596785 0 15 28 | B1->B0 | 2828 3535 | 0 1 | (0 0) (0 0)
5413 23:49:53.599250 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5414 23:49:53.606223 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 23:49:53.609453 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 23:49:53.612944 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 23:49:53.619253 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 23:49:53.622545 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 23:49:53.626106 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 23:49:53.632422 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5421 23:49:53.636070 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5422 23:49:53.639229 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 23:49:53.645944 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 23:49:53.649319 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 23:49:53.652638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 23:49:53.658947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 23:49:53.662343 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 23:49:53.665719 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 23:49:53.672103 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 23:49:53.675414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 23:49:53.678534 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 23:49:53.685537 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 23:49:53.688636 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 23:49:53.692010 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 23:49:53.698832 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 23:49:53.701820 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5437 23:49:53.705474 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 23:49:53.708515 Total UI for P1: 0, mck2ui 16
5439 23:49:53.711983 best dqsien dly found for B0: ( 1, 2, 28)
5440 23:49:53.715297 Total UI for P1: 0, mck2ui 16
5441 23:49:53.718326 best dqsien dly found for B1: ( 1, 2, 30)
5442 23:49:53.721758 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5443 23:49:53.725068 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5444 23:49:53.725494
5445 23:49:53.732035 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5446 23:49:53.734902 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5447 23:49:53.735331 [Gating] SW calibration Done
5448 23:49:53.738540 ==
5449 23:49:53.741630 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 23:49:53.744752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 23:49:53.745179 ==
5452 23:49:53.745514 RX Vref Scan: 0
5453 23:49:53.745829
5454 23:49:53.748183 RX Vref 0 -> 0, step: 1
5455 23:49:53.748634
5456 23:49:53.751576 RX Delay -80 -> 252, step: 8
5457 23:49:53.754979 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5458 23:49:53.758507 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5459 23:49:53.761643 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5460 23:49:53.768275 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5461 23:49:53.771787 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5462 23:49:53.775109 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5463 23:49:53.778700 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5464 23:49:53.781306 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5465 23:49:53.788185 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5466 23:49:53.791533 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5467 23:49:53.794774 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5468 23:49:53.797530 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5469 23:49:53.800917 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5470 23:49:53.807807 iDelay=208, Bit 13, Center 87 (-8 ~ 183) 192
5471 23:49:53.811513 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5472 23:49:53.814624 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5473 23:49:53.815095 ==
5474 23:49:53.818121 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 23:49:53.820859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 23:49:53.821328 ==
5477 23:49:53.824299 DQS Delay:
5478 23:49:53.824823 DQS0 = 0, DQS1 = 0
5479 23:49:53.827596 DQM Delay:
5480 23:49:53.828056 DQM0 = 91, DQM1 = 81
5481 23:49:53.828426 DQ Delay:
5482 23:49:53.830579 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5483 23:49:53.834118 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =107
5484 23:49:53.837501 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5485 23:49:53.840702 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5486 23:49:53.841170
5487 23:49:53.843760
5488 23:49:53.844179 ==
5489 23:49:53.846879 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 23:49:53.850505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 23:49:53.850933 ==
5492 23:49:53.851270
5493 23:49:53.851576
5494 23:49:53.853840 TX Vref Scan disable
5495 23:49:53.854263 == TX Byte 0 ==
5496 23:49:53.860312 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5497 23:49:53.863865 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5498 23:49:53.864287 == TX Byte 1 ==
5499 23:49:53.870500 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5500 23:49:53.873568 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5501 23:49:53.874100 ==
5502 23:49:53.876739 Dram Type= 6, Freq= 0, CH_0, rank 1
5503 23:49:53.880455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 23:49:53.881041 ==
5505 23:49:53.881382
5506 23:49:53.881693
5507 23:49:53.883248 TX Vref Scan disable
5508 23:49:53.886965 == TX Byte 0 ==
5509 23:49:53.890500 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5510 23:49:53.893324 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5511 23:49:53.896647 == TX Byte 1 ==
5512 23:49:53.900006 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5513 23:49:53.903720 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5514 23:49:53.904141
5515 23:49:53.906737 [DATLAT]
5516 23:49:53.907279 Freq=933, CH0 RK1
5517 23:49:53.907721
5518 23:49:53.909492 DATLAT Default: 0xb
5519 23:49:53.909916 0, 0xFFFF, sum = 0
5520 23:49:53.913081 1, 0xFFFF, sum = 0
5521 23:49:53.913511 2, 0xFFFF, sum = 0
5522 23:49:53.916512 3, 0xFFFF, sum = 0
5523 23:49:53.916961 4, 0xFFFF, sum = 0
5524 23:49:53.919567 5, 0xFFFF, sum = 0
5525 23:49:53.919994 6, 0xFFFF, sum = 0
5526 23:49:53.922994 7, 0xFFFF, sum = 0
5527 23:49:53.926735 8, 0xFFFF, sum = 0
5528 23:49:53.927165 9, 0xFFFF, sum = 0
5529 23:49:53.929481 10, 0x0, sum = 1
5530 23:49:53.929911 11, 0x0, sum = 2
5531 23:49:53.930248 12, 0x0, sum = 3
5532 23:49:53.932888 13, 0x0, sum = 4
5533 23:49:53.933317 best_step = 11
5534 23:49:53.933654
5535 23:49:53.933963 ==
5536 23:49:53.936270 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 23:49:53.943149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 23:49:53.943575 ==
5539 23:49:53.943912 RX Vref Scan: 0
5540 23:49:53.944227
5541 23:49:53.946298 RX Vref 0 -> 0, step: 1
5542 23:49:53.946721
5543 23:49:53.949449 RX Delay -77 -> 252, step: 4
5544 23:49:53.952709 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5545 23:49:53.959903 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5546 23:49:53.962498 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5547 23:49:53.965893 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5548 23:49:53.969739 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5549 23:49:53.972879 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5550 23:49:53.975722 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5551 23:49:53.982681 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5552 23:49:53.985605 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5553 23:49:53.989186 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5554 23:49:53.992376 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5555 23:49:53.999089 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5556 23:49:54.002377 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5557 23:49:54.005702 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5558 23:49:54.008968 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5559 23:49:54.012428 iDelay=199, Bit 15, Center 90 (3 ~ 178) 176
5560 23:49:54.012886 ==
5561 23:49:54.015622 Dram Type= 6, Freq= 0, CH_0, rank 1
5562 23:49:54.022242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 23:49:54.022670 ==
5564 23:49:54.023002 DQS Delay:
5565 23:49:54.025451 DQS0 = 0, DQS1 = 0
5566 23:49:54.025965 DQM Delay:
5567 23:49:54.026445 DQM0 = 92, DQM1 = 84
5568 23:49:54.028708 DQ Delay:
5569 23:49:54.032160 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5570 23:49:54.035575 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =102
5571 23:49:54.038931 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5572 23:49:54.042220 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5573 23:49:54.042642
5574 23:49:54.042973
5575 23:49:54.048720 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5576 23:49:54.052101 CH0 RK1: MR19=505, MR18=2F0F
5577 23:49:54.058619 CH0_RK1: MR19=0x505, MR18=0x2F0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5578 23:49:54.061633 [RxdqsGatingPostProcess] freq 933
5579 23:49:54.065344 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5580 23:49:54.068295 best DQS0 dly(2T, 0.5T) = (0, 11)
5581 23:49:54.071632 best DQS1 dly(2T, 0.5T) = (0, 11)
5582 23:49:54.074972 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5583 23:49:54.078760 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5584 23:49:54.082028 best DQS0 dly(2T, 0.5T) = (0, 10)
5585 23:49:54.084967 best DQS1 dly(2T, 0.5T) = (0, 10)
5586 23:49:54.088663 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5587 23:49:54.091310 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5588 23:49:54.094757 Pre-setting of DQS Precalculation
5589 23:49:54.098276 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5590 23:49:54.101334 ==
5591 23:49:54.105119 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 23:49:54.108054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 23:49:54.108484 ==
5594 23:49:54.111357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 23:49:54.117872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5596 23:49:54.121553 [CA 0] Center 37 (7~67) winsize 61
5597 23:49:54.124643 [CA 1] Center 37 (7~67) winsize 61
5598 23:49:54.128068 [CA 2] Center 34 (5~64) winsize 60
5599 23:49:54.131564 [CA 3] Center 34 (5~64) winsize 60
5600 23:49:54.135140 [CA 4] Center 34 (5~64) winsize 60
5601 23:49:54.138208 [CA 5] Center 34 (4~64) winsize 61
5602 23:49:54.138647
5603 23:49:54.141751 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5604 23:49:54.142176
5605 23:49:54.144620 [CATrainingPosCal] consider 1 rank data
5606 23:49:54.148377 u2DelayCellTimex100 = 270/100 ps
5607 23:49:54.151933 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5608 23:49:54.155229 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5609 23:49:54.161827 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5610 23:49:54.165138 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5611 23:49:54.168173 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5612 23:49:54.171917 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5613 23:49:54.172457
5614 23:49:54.175144 CA PerBit enable=1, Macro0, CA PI delay=34
5615 23:49:54.175563
5616 23:49:54.178017 [CBTSetCACLKResult] CA Dly = 34
5617 23:49:54.178438 CS Dly: 5 (0~36)
5618 23:49:54.181564 ==
5619 23:49:54.181984 Dram Type= 6, Freq= 0, CH_1, rank 1
5620 23:49:54.187939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 23:49:54.188365 ==
5622 23:49:54.191483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5623 23:49:54.197860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5624 23:49:54.201706 [CA 0] Center 38 (8~68) winsize 61
5625 23:49:54.205222 [CA 1] Center 37 (7~68) winsize 62
5626 23:49:54.208044 [CA 2] Center 35 (5~65) winsize 61
5627 23:49:54.211324 [CA 3] Center 34 (4~65) winsize 62
5628 23:49:54.214655 [CA 4] Center 35 (5~65) winsize 61
5629 23:49:54.217924 [CA 5] Center 34 (4~65) winsize 62
5630 23:49:54.218343
5631 23:49:54.221662 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5632 23:49:54.222085
5633 23:49:54.224919 [CATrainingPosCal] consider 2 rank data
5634 23:49:54.227888 u2DelayCellTimex100 = 270/100 ps
5635 23:49:54.231566 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5636 23:49:54.235007 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5637 23:49:54.241384 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5638 23:49:54.244930 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5639 23:49:54.248246 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5640 23:49:54.251490 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5641 23:49:54.251910
5642 23:49:54.254743 CA PerBit enable=1, Macro0, CA PI delay=34
5643 23:49:54.255165
5644 23:49:54.258363 [CBTSetCACLKResult] CA Dly = 34
5645 23:49:54.258789 CS Dly: 6 (0~39)
5646 23:49:54.259122
5647 23:49:54.261805 ----->DramcWriteLeveling(PI) begin...
5648 23:49:54.264686 ==
5649 23:49:54.268338 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 23:49:54.271717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 23:49:54.272169 ==
5652 23:49:54.274937 Write leveling (Byte 0): 25 => 25
5653 23:49:54.278028 Write leveling (Byte 1): 29 => 29
5654 23:49:54.281262 DramcWriteLeveling(PI) end<-----
5655 23:49:54.281695
5656 23:49:54.282024 ==
5657 23:49:54.284751 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 23:49:54.288205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 23:49:54.288665 ==
5660 23:49:54.290984 [Gating] SW mode calibration
5661 23:49:54.298217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5662 23:49:54.304480 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5663 23:49:54.307892 0 14 0 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)
5664 23:49:54.311430 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 23:49:54.317880 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 23:49:54.321090 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 23:49:54.324399 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 23:49:54.330992 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5669 23:49:54.334481 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5670 23:49:54.337607 0 14 28 | B1->B0 | 3030 3030 | 1 0 | (1 0) (1 0)
5671 23:49:54.344071 0 15 0 | B1->B0 | 2d2d 2c2c | 1 1 | (1 0) (1 0)
5672 23:49:54.347448 0 15 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5673 23:49:54.350961 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 23:49:54.357438 0 15 12 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
5675 23:49:54.360805 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 23:49:54.364334 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 23:49:54.367165 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 23:49:54.374088 0 15 28 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5679 23:49:54.377514 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 23:49:54.380630 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 23:49:54.387452 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 23:49:54.390867 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 23:49:54.393895 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 23:49:54.400938 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 23:49:54.404000 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 23:49:54.407277 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 23:49:54.413670 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 23:49:54.416960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 23:49:54.420619 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 23:49:54.427553 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 23:49:54.430536 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 23:49:54.433919 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 23:49:54.440243 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 23:49:54.443723 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 23:49:54.447158 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 23:49:54.453745 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 23:49:54.457098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 23:49:54.460198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 23:49:54.466737 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 23:49:54.470416 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 23:49:54.474112 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5702 23:49:54.480603 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5703 23:49:54.481186 Total UI for P1: 0, mck2ui 16
5704 23:49:54.486720 best dqsien dly found for B1: ( 1, 2, 24)
5705 23:49:54.490358 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 23:49:54.493824 Total UI for P1: 0, mck2ui 16
5707 23:49:54.496448 best dqsien dly found for B0: ( 1, 2, 26)
5708 23:49:54.499909 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5709 23:49:54.503688 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5710 23:49:54.504266
5711 23:49:54.506602 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5712 23:49:54.510272 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5713 23:49:54.513143 [Gating] SW calibration Done
5714 23:49:54.513610 ==
5715 23:49:54.516198 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 23:49:54.520244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 23:49:54.523060 ==
5718 23:49:54.523542 RX Vref Scan: 0
5719 23:49:54.523940
5720 23:49:54.526263 RX Vref 0 -> 0, step: 1
5721 23:49:54.526870
5722 23:49:54.530152 RX Delay -80 -> 252, step: 8
5723 23:49:54.532952 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5724 23:49:54.536379 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5725 23:49:54.539852 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5726 23:49:54.543110 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5727 23:49:54.549538 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5728 23:49:54.553030 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5729 23:49:54.556465 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5730 23:49:54.559416 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5731 23:49:54.562813 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5732 23:49:54.566299 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5733 23:49:54.572967 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5734 23:49:54.576262 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5735 23:49:54.579275 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5736 23:49:54.582553 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5737 23:49:54.586009 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5738 23:49:54.592746 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5739 23:49:54.593388 ==
5740 23:49:54.595846 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 23:49:54.599080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 23:49:54.599619 ==
5743 23:49:54.599964 DQS Delay:
5744 23:49:54.602155 DQS0 = 0, DQS1 = 0
5745 23:49:54.602608 DQM Delay:
5746 23:49:54.605775 DQM0 = 94, DQM1 = 86
5747 23:49:54.606317 DQ Delay:
5748 23:49:54.609034 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =87
5749 23:49:54.612763 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5750 23:49:54.615685 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5751 23:49:54.619434 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5752 23:49:54.619976
5753 23:49:54.620316
5754 23:49:54.620778 ==
5755 23:49:54.622363 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 23:49:54.628734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 23:49:54.629173 ==
5758 23:49:54.629510
5759 23:49:54.629839
5760 23:49:54.630138 TX Vref Scan disable
5761 23:49:54.631752 == TX Byte 0 ==
5762 23:49:54.635454 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5763 23:49:54.641933 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5764 23:49:54.642369 == TX Byte 1 ==
5765 23:49:54.645031 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5766 23:49:54.651912 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5767 23:49:54.652348 ==
5768 23:49:54.655021 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 23:49:54.658154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 23:49:54.658600 ==
5771 23:49:54.658932
5772 23:49:54.659262
5773 23:49:54.661718 TX Vref Scan disable
5774 23:49:54.662158 == TX Byte 0 ==
5775 23:49:54.668037 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5776 23:49:54.671452 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5777 23:49:54.674992 == TX Byte 1 ==
5778 23:49:54.678482 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5779 23:49:54.681526 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5780 23:49:54.682023
5781 23:49:54.682360 [DATLAT]
5782 23:49:54.684626 Freq=933, CH1 RK0
5783 23:49:54.685075
5784 23:49:54.685426 DATLAT Default: 0xd
5785 23:49:54.687879 0, 0xFFFF, sum = 0
5786 23:49:54.691299 1, 0xFFFF, sum = 0
5787 23:49:54.691835 2, 0xFFFF, sum = 0
5788 23:49:54.694698 3, 0xFFFF, sum = 0
5789 23:49:54.695145 4, 0xFFFF, sum = 0
5790 23:49:54.698400 5, 0xFFFF, sum = 0
5791 23:49:54.698946 6, 0xFFFF, sum = 0
5792 23:49:54.701435 7, 0xFFFF, sum = 0
5793 23:49:54.701975 8, 0xFFFF, sum = 0
5794 23:49:54.704369 9, 0xFFFF, sum = 0
5795 23:49:54.704901 10, 0x0, sum = 1
5796 23:49:54.708017 11, 0x0, sum = 2
5797 23:49:54.708536 12, 0x0, sum = 3
5798 23:49:54.711050 13, 0x0, sum = 4
5799 23:49:54.711482 best_step = 11
5800 23:49:54.711839
5801 23:49:54.712152 ==
5802 23:49:54.714540 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 23:49:54.718053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 23:49:54.721311 ==
5805 23:49:54.721746 RX Vref Scan: 1
5806 23:49:54.722085
5807 23:49:54.724503 RX Vref 0 -> 0, step: 1
5808 23:49:54.725072
5809 23:49:54.725429 RX Delay -61 -> 252, step: 4
5810 23:49:54.727690
5811 23:49:54.728341 Set Vref, RX VrefLevel [Byte0]: 55
5812 23:49:54.731071 [Byte1]: 50
5813 23:49:54.735722
5814 23:49:54.736251 Final RX Vref Byte 0 = 55 to rank0
5815 23:49:54.739126 Final RX Vref Byte 1 = 50 to rank0
5816 23:49:54.742633 Final RX Vref Byte 0 = 55 to rank1
5817 23:49:54.745975 Final RX Vref Byte 1 = 50 to rank1==
5818 23:49:54.749388 Dram Type= 6, Freq= 0, CH_1, rank 0
5819 23:49:54.755825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 23:49:54.756252 ==
5821 23:49:54.756684 DQS Delay:
5822 23:49:54.757017 DQS0 = 0, DQS1 = 0
5823 23:49:54.759106 DQM Delay:
5824 23:49:54.759549 DQM0 = 96, DQM1 = 88
5825 23:49:54.762573 DQ Delay:
5826 23:49:54.765611 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =94
5827 23:49:54.769059 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5828 23:49:54.772440 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5829 23:49:54.776053 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =94
5830 23:49:54.776496
5831 23:49:54.776967
5832 23:49:54.782378 [DQSOSCAuto] RK0, (LSB)MR18= 0x20a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5833 23:49:54.785513 CH1 RK0: MR19=505, MR18=20A
5834 23:49:54.792341 CH1_RK0: MR19=0x505, MR18=0x20A, DQSOSC=418, MR23=63, INC=62, DEC=41
5835 23:49:54.792987
5836 23:49:54.795536 ----->DramcWriteLeveling(PI) begin...
5837 23:49:54.795987 ==
5838 23:49:54.799020 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 23:49:54.802025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 23:49:54.802473 ==
5841 23:49:54.805698 Write leveling (Byte 0): 29 => 29
5842 23:49:54.808599 Write leveling (Byte 1): 29 => 29
5843 23:49:54.812118 DramcWriteLeveling(PI) end<-----
5844 23:49:54.812553
5845 23:49:54.813034 ==
5846 23:49:54.815412 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 23:49:54.818723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 23:49:54.819246 ==
5849 23:49:54.822030 [Gating] SW mode calibration
5850 23:49:54.828986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5851 23:49:54.835261 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5852 23:49:54.838506 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5853 23:49:54.845228 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 23:49:54.848745 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 23:49:54.852039 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 23:49:54.858884 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 23:49:54.861627 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5858 23:49:54.865005 0 14 24 | B1->B0 | 3434 2c2c | 0 1 | (0 1) (1 0)
5859 23:49:54.871566 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5860 23:49:54.874964 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5861 23:49:54.878471 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 23:49:54.884738 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 23:49:54.888239 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 23:49:54.891923 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 23:49:54.895167 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5866 23:49:54.901591 0 15 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (1 1)
5867 23:49:54.904549 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5868 23:49:54.908735 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 23:49:54.915074 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 23:49:54.917827 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 23:49:54.921130 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 23:49:54.927771 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 23:49:54.931077 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 23:49:54.934831 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5875 23:49:54.941291 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5876 23:49:54.944499 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 23:49:54.948001 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 23:49:54.954671 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 23:49:54.957921 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 23:49:54.960958 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 23:49:54.968026 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 23:49:54.970808 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 23:49:54.974460 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 23:49:54.981268 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 23:49:54.984116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 23:49:54.987392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 23:49:54.994144 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 23:49:54.997769 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 23:49:55.000992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 23:49:55.007745 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5891 23:49:55.010455 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5892 23:49:55.013822 Total UI for P1: 0, mck2ui 16
5893 23:49:55.017287 best dqsien dly found for B0: ( 1, 2, 24)
5894 23:49:55.020634 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5895 23:49:55.023752 Total UI for P1: 0, mck2ui 16
5896 23:49:55.027154 best dqsien dly found for B1: ( 1, 2, 28)
5897 23:49:55.030379 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5898 23:49:55.033934 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5899 23:49:55.034505
5900 23:49:55.040701 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5901 23:49:55.044165 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5902 23:49:55.044671 [Gating] SW calibration Done
5903 23:49:55.047297 ==
5904 23:49:55.050692 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 23:49:55.053819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 23:49:55.054289 ==
5907 23:49:55.054652 RX Vref Scan: 0
5908 23:49:55.055008
5909 23:49:55.057157 RX Vref 0 -> 0, step: 1
5910 23:49:55.057625
5911 23:49:55.060448 RX Delay -80 -> 252, step: 8
5912 23:49:55.063712 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5913 23:49:55.067071 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5914 23:49:55.070590 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5915 23:49:55.077133 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5916 23:49:55.080630 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5917 23:49:55.083718 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5918 23:49:55.087653 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5919 23:49:55.090096 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5920 23:49:55.096711 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5921 23:49:55.100048 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5922 23:49:55.103595 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5923 23:49:55.106774 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5924 23:49:55.110324 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5925 23:49:55.116962 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5926 23:49:55.119777 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5927 23:49:55.123453 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5928 23:49:55.123922 ==
5929 23:49:55.126939 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 23:49:55.130037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 23:49:55.130778 ==
5932 23:49:55.133183 DQS Delay:
5933 23:49:55.133796 DQS0 = 0, DQS1 = 0
5934 23:49:55.136226 DQM Delay:
5935 23:49:55.136722 DQM0 = 93, DQM1 = 86
5936 23:49:55.137092 DQ Delay:
5937 23:49:55.139967 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5938 23:49:55.142978 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5939 23:49:55.146575 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5940 23:49:55.149815 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5941 23:49:55.150280
5942 23:49:55.150645
5943 23:49:55.153372 ==
5944 23:49:55.153840 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 23:49:55.159985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 23:49:55.160454 ==
5947 23:49:55.160882
5948 23:49:55.161226
5949 23:49:55.163328 TX Vref Scan disable
5950 23:49:55.163791 == TX Byte 0 ==
5951 23:49:55.166490 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5952 23:49:55.173210 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5953 23:49:55.173681 == TX Byte 1 ==
5954 23:49:55.176338 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5955 23:49:55.183229 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5956 23:49:55.183760 ==
5957 23:49:55.186552 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 23:49:55.189650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 23:49:55.190082 ==
5960 23:49:55.190413
5961 23:49:55.190719
5962 23:49:55.193121 TX Vref Scan disable
5963 23:49:55.196290 == TX Byte 0 ==
5964 23:49:55.199508 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5965 23:49:55.203344 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5966 23:49:55.206267 == TX Byte 1 ==
5967 23:49:55.209677 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5968 23:49:55.212939 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5969 23:49:55.213364
5970 23:49:55.213698 [DATLAT]
5971 23:49:55.216406 Freq=933, CH1 RK1
5972 23:49:55.216864
5973 23:49:55.219382 DATLAT Default: 0xb
5974 23:49:55.219923 0, 0xFFFF, sum = 0
5975 23:49:55.223163 1, 0xFFFF, sum = 0
5976 23:49:55.223592 2, 0xFFFF, sum = 0
5977 23:49:55.226241 3, 0xFFFF, sum = 0
5978 23:49:55.226785 4, 0xFFFF, sum = 0
5979 23:49:55.229722 5, 0xFFFF, sum = 0
5980 23:49:55.230150 6, 0xFFFF, sum = 0
5981 23:49:55.232816 7, 0xFFFF, sum = 0
5982 23:49:55.233276 8, 0xFFFF, sum = 0
5983 23:49:55.236213 9, 0xFFFF, sum = 0
5984 23:49:55.236670 10, 0x0, sum = 1
5985 23:49:55.239724 11, 0x0, sum = 2
5986 23:49:55.240156 12, 0x0, sum = 3
5987 23:49:55.242529 13, 0x0, sum = 4
5988 23:49:55.243016 best_step = 11
5989 23:49:55.243354
5990 23:49:55.243665 ==
5991 23:49:55.246456 Dram Type= 6, Freq= 0, CH_1, rank 1
5992 23:49:55.249565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5993 23:49:55.249992 ==
5994 23:49:55.252928 RX Vref Scan: 0
5995 23:49:55.253351
5996 23:49:55.256466 RX Vref 0 -> 0, step: 1
5997 23:49:55.256931
5998 23:49:55.257266 RX Delay -69 -> 252, step: 4
5999 23:49:55.264324 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
6000 23:49:55.267779 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
6001 23:49:55.270937 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
6002 23:49:55.274419 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
6003 23:49:55.277377 iDelay=203, Bit 4, Center 92 (-5 ~ 190) 196
6004 23:49:55.284134 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
6005 23:49:55.287237 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
6006 23:49:55.290891 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
6007 23:49:55.293981 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
6008 23:49:55.297281 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
6009 23:49:55.300935 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
6010 23:49:55.307417 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6011 23:49:55.310571 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
6012 23:49:55.313735 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
6013 23:49:55.317132 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
6014 23:49:55.320497 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
6015 23:49:55.321019 ==
6016 23:49:55.323904 Dram Type= 6, Freq= 0, CH_1, rank 1
6017 23:49:55.330410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6018 23:49:55.330920 ==
6019 23:49:55.331305 DQS Delay:
6020 23:49:55.333530 DQS0 = 0, DQS1 = 0
6021 23:49:55.333988 DQM Delay:
6022 23:49:55.334427 DQM0 = 91, DQM1 = 90
6023 23:49:55.337416 DQ Delay:
6024 23:49:55.340702 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6025 23:49:55.343912 DQ4 =92, DQ5 =100, DQ6 =102, DQ7 =88
6026 23:49:55.347203 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
6027 23:49:55.350783 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
6028 23:49:55.351238
6029 23:49:55.351675
6030 23:49:55.357099 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
6031 23:49:55.360703 CH1 RK1: MR19=505, MR18=C1F
6032 23:49:55.367552 CH1_RK1: MR19=0x505, MR18=0xC1F, DQSOSC=412, MR23=63, INC=63, DEC=42
6033 23:49:55.370884 [RxdqsGatingPostProcess] freq 933
6034 23:49:55.373858 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6035 23:49:55.377252 best DQS0 dly(2T, 0.5T) = (0, 10)
6036 23:49:55.380289 best DQS1 dly(2T, 0.5T) = (0, 10)
6037 23:49:55.383623 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6038 23:49:55.387021 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6039 23:49:55.390344 best DQS0 dly(2T, 0.5T) = (0, 10)
6040 23:49:55.393537 best DQS1 dly(2T, 0.5T) = (0, 10)
6041 23:49:55.396902 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6042 23:49:55.400402 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6043 23:49:55.403777 Pre-setting of DQS Precalculation
6044 23:49:55.406700 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6045 23:49:55.416916 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6046 23:49:55.423537 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6047 23:49:55.423981
6048 23:49:55.424439
6049 23:49:55.426402 [Calibration Summary] 1866 Mbps
6050 23:49:55.426857 CH 0, Rank 0
6051 23:49:55.430133 SW Impedance : PASS
6052 23:49:55.430612 DUTY Scan : NO K
6053 23:49:55.433400 ZQ Calibration : PASS
6054 23:49:55.436307 Jitter Meter : NO K
6055 23:49:55.436788 CBT Training : PASS
6056 23:49:55.439951 Write leveling : PASS
6057 23:49:55.443141 RX DQS gating : PASS
6058 23:49:55.443568 RX DQ/DQS(RDDQC) : PASS
6059 23:49:55.446496 TX DQ/DQS : PASS
6060 23:49:55.449738 RX DATLAT : PASS
6061 23:49:55.450165 RX DQ/DQS(Engine): PASS
6062 23:49:55.452965 TX OE : NO K
6063 23:49:55.453389 All Pass.
6064 23:49:55.453719
6065 23:49:55.456514 CH 0, Rank 1
6066 23:49:55.456978 SW Impedance : PASS
6067 23:49:55.459699 DUTY Scan : NO K
6068 23:49:55.460120 ZQ Calibration : PASS
6069 23:49:55.463001 Jitter Meter : NO K
6070 23:49:55.466390 CBT Training : PASS
6071 23:49:55.466812 Write leveling : PASS
6072 23:49:55.469768 RX DQS gating : PASS
6073 23:49:55.473115 RX DQ/DQS(RDDQC) : PASS
6074 23:49:55.473537 TX DQ/DQS : PASS
6075 23:49:55.476637 RX DATLAT : PASS
6076 23:49:55.479877 RX DQ/DQS(Engine): PASS
6077 23:49:55.480315 TX OE : NO K
6078 23:49:55.483220 All Pass.
6079 23:49:55.483751
6080 23:49:55.484089 CH 1, Rank 0
6081 23:49:55.486478 SW Impedance : PASS
6082 23:49:55.486905 DUTY Scan : NO K
6083 23:49:55.489438 ZQ Calibration : PASS
6084 23:49:55.493128 Jitter Meter : NO K
6085 23:49:55.493552 CBT Training : PASS
6086 23:49:55.496490 Write leveling : PASS
6087 23:49:55.499463 RX DQS gating : PASS
6088 23:49:55.499885 RX DQ/DQS(RDDQC) : PASS
6089 23:49:55.502761 TX DQ/DQS : PASS
6090 23:49:55.506242 RX DATLAT : PASS
6091 23:49:55.506667 RX DQ/DQS(Engine): PASS
6092 23:49:55.509638 TX OE : NO K
6093 23:49:55.510063 All Pass.
6094 23:49:55.510393
6095 23:49:55.512931 CH 1, Rank 1
6096 23:49:55.513354 SW Impedance : PASS
6097 23:49:55.516105 DUTY Scan : NO K
6098 23:49:55.519590 ZQ Calibration : PASS
6099 23:49:55.520020 Jitter Meter : NO K
6100 23:49:55.522776 CBT Training : PASS
6101 23:49:55.526638 Write leveling : PASS
6102 23:49:55.527174 RX DQS gating : PASS
6103 23:49:55.529081 RX DQ/DQS(RDDQC) : PASS
6104 23:49:55.529504 TX DQ/DQS : PASS
6105 23:49:55.532554 RX DATLAT : PASS
6106 23:49:55.536082 RX DQ/DQS(Engine): PASS
6107 23:49:55.536527 TX OE : NO K
6108 23:49:55.539181 All Pass.
6109 23:49:55.539622
6110 23:49:55.539956 DramC Write-DBI off
6111 23:49:55.542666 PER_BANK_REFRESH: Hybrid Mode
6112 23:49:55.545784 TX_TRACKING: ON
6113 23:49:55.552709 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6114 23:49:55.556037 [FAST_K] Save calibration result to emmc
6115 23:49:55.558951 dramc_set_vcore_voltage set vcore to 650000
6116 23:49:55.562394 Read voltage for 400, 6
6117 23:49:55.562898 Vio18 = 0
6118 23:49:55.565847 Vcore = 650000
6119 23:49:55.566383 Vdram = 0
6120 23:49:55.566720 Vddq = 0
6121 23:49:55.569229 Vmddr = 0
6122 23:49:55.572115 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6123 23:49:55.578777 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6124 23:49:55.579220 MEM_TYPE=3, freq_sel=20
6125 23:49:55.582591 sv_algorithm_assistance_LP4_800
6126 23:49:55.589275 ============ PULL DRAM RESETB DOWN ============
6127 23:49:55.592138 ========== PULL DRAM RESETB DOWN end =========
6128 23:49:55.595605 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6129 23:49:55.598938 ===================================
6130 23:49:55.602393 LPDDR4 DRAM CONFIGURATION
6131 23:49:55.605412 ===================================
6132 23:49:55.608702 EX_ROW_EN[0] = 0x0
6133 23:49:55.609311 EX_ROW_EN[1] = 0x0
6134 23:49:55.612180 LP4Y_EN = 0x0
6135 23:49:55.612679 WORK_FSP = 0x0
6136 23:49:55.615305 WL = 0x2
6137 23:49:55.615877 RL = 0x2
6138 23:49:55.618614 BL = 0x2
6139 23:49:55.619077 RPST = 0x0
6140 23:49:55.621902 RD_PRE = 0x0
6141 23:49:55.622365 WR_PRE = 0x1
6142 23:49:55.625577 WR_PST = 0x0
6143 23:49:55.626153 DBI_WR = 0x0
6144 23:49:55.628704 DBI_RD = 0x0
6145 23:49:55.629168 OTF = 0x1
6146 23:49:55.631789 ===================================
6147 23:49:55.635230 ===================================
6148 23:49:55.638819 ANA top config
6149 23:49:55.641663 ===================================
6150 23:49:55.645355 DLL_ASYNC_EN = 0
6151 23:49:55.645819 ALL_SLAVE_EN = 1
6152 23:49:55.648400 NEW_RANK_MODE = 1
6153 23:49:55.651687 DLL_IDLE_MODE = 1
6154 23:49:55.655219 LP45_APHY_COMB_EN = 1
6155 23:49:55.655689 TX_ODT_DIS = 1
6156 23:49:55.658385 NEW_8X_MODE = 1
6157 23:49:55.661621 ===================================
6158 23:49:55.665039 ===================================
6159 23:49:55.668145 data_rate = 800
6160 23:49:55.671619 CKR = 1
6161 23:49:55.675586 DQ_P2S_RATIO = 4
6162 23:49:55.678014 ===================================
6163 23:49:55.681588 CA_P2S_RATIO = 4
6164 23:49:55.682125 DQ_CA_OPEN = 0
6165 23:49:55.685053 DQ_SEMI_OPEN = 1
6166 23:49:55.688109 CA_SEMI_OPEN = 1
6167 23:49:55.691521 CA_FULL_RATE = 0
6168 23:49:55.695189 DQ_CKDIV4_EN = 0
6169 23:49:55.698687 CA_CKDIV4_EN = 1
6170 23:49:55.699236 CA_PREDIV_EN = 0
6171 23:49:55.701733 PH8_DLY = 0
6172 23:49:55.704976 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6173 23:49:55.708046 DQ_AAMCK_DIV = 0
6174 23:49:55.712115 CA_AAMCK_DIV = 0
6175 23:49:55.715013 CA_ADMCK_DIV = 4
6176 23:49:55.715599 DQ_TRACK_CA_EN = 0
6177 23:49:55.718325 CA_PICK = 800
6178 23:49:55.721791 CA_MCKIO = 400
6179 23:49:55.724856 MCKIO_SEMI = 400
6180 23:49:55.728131 PLL_FREQ = 3016
6181 23:49:55.731518 DQ_UI_PI_RATIO = 32
6182 23:49:55.734817 CA_UI_PI_RATIO = 32
6183 23:49:55.737872 ===================================
6184 23:49:55.741369 ===================================
6185 23:49:55.741853 memory_type:LPDDR4
6186 23:49:55.744906 GP_NUM : 10
6187 23:49:55.748089 SRAM_EN : 1
6188 23:49:55.748521 MD32_EN : 0
6189 23:49:55.751022 ===================================
6190 23:49:55.754455 [ANA_INIT] >>>>>>>>>>>>>>
6191 23:49:55.758166 <<<<<< [CONFIGURE PHASE]: ANA_TX
6192 23:49:55.760902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6193 23:49:55.764192 ===================================
6194 23:49:55.767947 data_rate = 800,PCW = 0X7400
6195 23:49:55.770966 ===================================
6196 23:49:55.774450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6197 23:49:55.777555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6198 23:49:55.791137 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6199 23:49:55.793965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6200 23:49:55.797094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6201 23:49:55.800678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6202 23:49:55.804074 [ANA_INIT] flow start
6203 23:49:55.807162 [ANA_INIT] PLL >>>>>>>>
6204 23:49:55.807643 [ANA_INIT] PLL <<<<<<<<
6205 23:49:55.810567 [ANA_INIT] MIDPI >>>>>>>>
6206 23:49:55.814067 [ANA_INIT] MIDPI <<<<<<<<
6207 23:49:55.814643 [ANA_INIT] DLL >>>>>>>>
6208 23:49:55.817306 [ANA_INIT] flow end
6209 23:49:55.820954 ============ LP4 DIFF to SE enter ============
6210 23:49:55.824052 ============ LP4 DIFF to SE exit ============
6211 23:49:55.827606 [ANA_INIT] <<<<<<<<<<<<<
6212 23:49:55.830918 [Flow] Enable top DCM control >>>>>
6213 23:49:55.833751 [Flow] Enable top DCM control <<<<<
6214 23:49:55.837344 Enable DLL master slave shuffle
6215 23:49:55.844059 ==============================================================
6216 23:49:55.844707 Gating Mode config
6217 23:49:55.850196 ==============================================================
6218 23:49:55.853621 Config description:
6219 23:49:55.860177 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6220 23:49:55.866690 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6221 23:49:55.873642 SELPH_MODE 0: By rank 1: By Phase
6222 23:49:55.880540 ==============================================================
6223 23:49:55.881142 GAT_TRACK_EN = 0
6224 23:49:55.883490 RX_GATING_MODE = 2
6225 23:49:55.887022 RX_GATING_TRACK_MODE = 2
6226 23:49:55.890340 SELPH_MODE = 1
6227 23:49:55.893810 PICG_EARLY_EN = 1
6228 23:49:55.896538 VALID_LAT_VALUE = 1
6229 23:49:55.903123 ==============================================================
6230 23:49:55.906438 Enter into Gating configuration >>>>
6231 23:49:55.910162 Exit from Gating configuration <<<<
6232 23:49:55.913819 Enter into DVFS_PRE_config >>>>>
6233 23:49:55.923360 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6234 23:49:55.926842 Exit from DVFS_PRE_config <<<<<
6235 23:49:55.930009 Enter into PICG configuration >>>>
6236 23:49:55.932868 Exit from PICG configuration <<<<
6237 23:49:55.936426 [RX_INPUT] configuration >>>>>
6238 23:49:55.940016 [RX_INPUT] configuration <<<<<
6239 23:49:55.942717 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6240 23:49:55.949542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6241 23:49:55.957024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6242 23:49:55.959699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6243 23:49:55.966255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6244 23:49:55.972857 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6245 23:49:55.976008 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6246 23:49:55.982876 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6247 23:49:55.986162 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6248 23:49:55.989177 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6249 23:49:55.992471 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6250 23:49:55.999368 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 23:49:56.003011 ===================================
6252 23:49:56.003596 LPDDR4 DRAM CONFIGURATION
6253 23:49:56.006091 ===================================
6254 23:49:56.009105 EX_ROW_EN[0] = 0x0
6255 23:49:56.012622 EX_ROW_EN[1] = 0x0
6256 23:49:56.013342 LP4Y_EN = 0x0
6257 23:49:56.015900 WORK_FSP = 0x0
6258 23:49:56.016366 WL = 0x2
6259 23:49:56.019531 RL = 0x2
6260 23:49:56.019994 BL = 0x2
6261 23:49:56.022715 RPST = 0x0
6262 23:49:56.023177 RD_PRE = 0x0
6263 23:49:56.025892 WR_PRE = 0x1
6264 23:49:56.026454 WR_PST = 0x0
6265 23:49:56.029347 DBI_WR = 0x0
6266 23:49:56.029936 DBI_RD = 0x0
6267 23:49:56.032238 OTF = 0x1
6268 23:49:56.035448 ===================================
6269 23:49:56.038846 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6270 23:49:56.042269 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6271 23:49:56.049202 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6272 23:49:56.052078 ===================================
6273 23:49:56.052543 LPDDR4 DRAM CONFIGURATION
6274 23:49:56.055645 ===================================
6275 23:49:56.058679 EX_ROW_EN[0] = 0x10
6276 23:49:56.062154 EX_ROW_EN[1] = 0x0
6277 23:49:56.062576 LP4Y_EN = 0x0
6278 23:49:56.065547 WORK_FSP = 0x0
6279 23:49:56.065968 WL = 0x2
6280 23:49:56.068647 RL = 0x2
6281 23:49:56.069106 BL = 0x2
6282 23:49:56.071998 RPST = 0x0
6283 23:49:56.072420 RD_PRE = 0x0
6284 23:49:56.075677 WR_PRE = 0x1
6285 23:49:56.076201 WR_PST = 0x0
6286 23:49:56.078675 DBI_WR = 0x0
6287 23:49:56.079203 DBI_RD = 0x0
6288 23:49:56.083233 OTF = 0x1
6289 23:49:56.085583 ===================================
6290 23:49:56.091771 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6291 23:49:56.095114 nWR fixed to 30
6292 23:49:56.095535 [ModeRegInit_LP4] CH0 RK0
6293 23:49:56.098339 [ModeRegInit_LP4] CH0 RK1
6294 23:49:56.101555 [ModeRegInit_LP4] CH1 RK0
6295 23:49:56.104949 [ModeRegInit_LP4] CH1 RK1
6296 23:49:56.105368 match AC timing 19
6297 23:49:56.112181 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6298 23:49:56.115217 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6299 23:49:56.119102 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6300 23:49:56.125063 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6301 23:49:56.128664 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6302 23:49:56.129083 ==
6303 23:49:56.131530 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 23:49:56.135394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 23:49:56.135861 ==
6306 23:49:56.141594 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 23:49:56.148522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6308 23:49:56.151512 [CA 0] Center 36 (8~64) winsize 57
6309 23:49:56.151977 [CA 1] Center 36 (8~64) winsize 57
6310 23:49:56.155031 [CA 2] Center 36 (8~64) winsize 57
6311 23:49:56.158442 [CA 3] Center 36 (8~64) winsize 57
6312 23:49:56.162045 [CA 4] Center 36 (8~64) winsize 57
6313 23:49:56.165010 [CA 5] Center 36 (8~64) winsize 57
6314 23:49:56.165475
6315 23:49:56.168502 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6316 23:49:56.169127
6317 23:49:56.171835 [CATrainingPosCal] consider 1 rank data
6318 23:49:56.175452 u2DelayCellTimex100 = 270/100 ps
6319 23:49:56.178180 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 23:49:56.185035 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 23:49:56.188211 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 23:49:56.192136 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 23:49:56.194870 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 23:49:56.198226 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 23:49:56.198647
6326 23:49:56.201525 CA PerBit enable=1, Macro0, CA PI delay=36
6327 23:49:56.201945
6328 23:49:56.205229 [CBTSetCACLKResult] CA Dly = 36
6329 23:49:56.205653 CS Dly: 1 (0~32)
6330 23:49:56.208124 ==
6331 23:49:56.211608 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 23:49:56.214435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 23:49:56.214971 ==
6334 23:49:56.221534 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6335 23:49:56.224554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6336 23:49:56.227790 [CA 0] Center 36 (8~64) winsize 57
6337 23:49:56.231288 [CA 1] Center 36 (8~64) winsize 57
6338 23:49:56.234336 [CA 2] Center 36 (8~64) winsize 57
6339 23:49:56.237877 [CA 3] Center 36 (8~64) winsize 57
6340 23:49:56.240988 [CA 4] Center 36 (8~64) winsize 57
6341 23:49:56.244282 [CA 5] Center 36 (8~64) winsize 57
6342 23:49:56.244876
6343 23:49:56.247928 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6344 23:49:56.248530
6345 23:49:56.250847 [CATrainingPosCal] consider 2 rank data
6346 23:49:56.254321 u2DelayCellTimex100 = 270/100 ps
6347 23:49:56.257856 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 23:49:56.261408 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 23:49:56.264248 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 23:49:56.271002 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 23:49:56.274562 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 23:49:56.277597 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6353 23:49:56.278171
6354 23:49:56.280829 CA PerBit enable=1, Macro0, CA PI delay=36
6355 23:49:56.281292
6356 23:49:56.284294 [CBTSetCACLKResult] CA Dly = 36
6357 23:49:56.284803 CS Dly: 1 (0~32)
6358 23:49:56.285236
6359 23:49:56.287972 ----->DramcWriteLeveling(PI) begin...
6360 23:49:56.288596 ==
6361 23:49:56.290743 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 23:49:56.297397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 23:49:56.297962 ==
6364 23:49:56.300941 Write leveling (Byte 0): 40 => 8
6365 23:49:56.303727 Write leveling (Byte 1): 40 => 8
6366 23:49:56.304116 DramcWriteLeveling(PI) end<-----
6367 23:49:56.304443
6368 23:49:56.307057 ==
6369 23:49:56.310664 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 23:49:56.313442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 23:49:56.313648 ==
6372 23:49:56.317041 [Gating] SW mode calibration
6373 23:49:56.323649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6374 23:49:56.326860 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6375 23:49:56.333210 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6376 23:49:56.336494 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6377 23:49:56.340000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 23:49:56.346719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6379 23:49:56.349987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 23:49:56.353207 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 23:49:56.359896 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 23:49:56.363098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6383 23:49:56.366736 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 23:49:56.370152 Total UI for P1: 0, mck2ui 16
6385 23:49:56.373170 best dqsien dly found for B0: ( 0, 14, 24)
6386 23:49:56.377047 Total UI for P1: 0, mck2ui 16
6387 23:49:56.380211 best dqsien dly found for B1: ( 0, 14, 24)
6388 23:49:56.383601 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6389 23:49:56.387069 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6390 23:49:56.390290
6391 23:49:56.393157 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6392 23:49:56.396808 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6393 23:49:56.400325 [Gating] SW calibration Done
6394 23:49:56.400829 ==
6395 23:49:56.403294 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 23:49:56.406328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 23:49:56.406806 ==
6398 23:49:56.409553 RX Vref Scan: 0
6399 23:49:56.410018
6400 23:49:56.410379 RX Vref 0 -> 0, step: 1
6401 23:49:56.410722
6402 23:49:56.413157 RX Delay -410 -> 252, step: 16
6403 23:49:56.416975 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6404 23:49:56.423107 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6405 23:49:56.426754 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6406 23:49:56.429755 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6407 23:49:56.433410 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6408 23:49:56.439458 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6409 23:49:56.442674 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6410 23:49:56.445679 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6411 23:49:56.449062 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6412 23:49:56.455939 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6413 23:49:56.459182 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6414 23:49:56.462700 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6415 23:49:56.469392 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6416 23:49:56.472077 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6417 23:49:56.475631 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6418 23:49:56.479162 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6419 23:49:56.479754 ==
6420 23:49:56.482655 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 23:49:56.489044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 23:49:56.489642 ==
6423 23:49:56.490132 DQS Delay:
6424 23:49:56.492323 DQS0 = 59, DQS1 = 59
6425 23:49:56.492837 DQM Delay:
6426 23:49:56.496058 DQM0 = 18, DQM1 = 10
6427 23:49:56.496663 DQ Delay:
6428 23:49:56.499170 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6429 23:49:56.502047 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6430 23:49:56.505453 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6431 23:49:56.508706 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6432 23:49:56.509126
6433 23:49:56.509453
6434 23:49:56.509756 ==
6435 23:49:56.512106 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 23:49:56.515435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 23:49:56.515849 ==
6438 23:49:56.516173
6439 23:49:56.516475
6440 23:49:56.518599 TX Vref Scan disable
6441 23:49:56.519010 == TX Byte 0 ==
6442 23:49:56.525150 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6443 23:49:56.528517 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6444 23:49:56.528962 == TX Byte 1 ==
6445 23:49:56.535660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6446 23:49:56.538468 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6447 23:49:56.539060 ==
6448 23:49:56.542017 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 23:49:56.545395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 23:49:56.545868 ==
6451 23:49:56.546327
6452 23:49:56.546719
6453 23:49:56.548369 TX Vref Scan disable
6454 23:49:56.548852 == TX Byte 0 ==
6455 23:49:56.554948 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6456 23:49:56.558399 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6457 23:49:56.558892 == TX Byte 1 ==
6458 23:49:56.565078 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6459 23:49:56.568501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6460 23:49:56.569089
6461 23:49:56.569637 [DATLAT]
6462 23:49:56.571881 Freq=400, CH0 RK0
6463 23:49:56.572310
6464 23:49:56.572852 DATLAT Default: 0xf
6465 23:49:56.575300 0, 0xFFFF, sum = 0
6466 23:49:56.575806 1, 0xFFFF, sum = 0
6467 23:49:56.578115 2, 0xFFFF, sum = 0
6468 23:49:56.578590 3, 0xFFFF, sum = 0
6469 23:49:56.581655 4, 0xFFFF, sum = 0
6470 23:49:56.582129 5, 0xFFFF, sum = 0
6471 23:49:56.584860 6, 0xFFFF, sum = 0
6472 23:49:56.587808 7, 0xFFFF, sum = 0
6473 23:49:56.588282 8, 0xFFFF, sum = 0
6474 23:49:56.591515 9, 0xFFFF, sum = 0
6475 23:49:56.591951 10, 0xFFFF, sum = 0
6476 23:49:56.594712 11, 0xFFFF, sum = 0
6477 23:49:56.595190 12, 0xFFFF, sum = 0
6478 23:49:56.598005 13, 0x0, sum = 1
6479 23:49:56.598479 14, 0x0, sum = 2
6480 23:49:56.601015 15, 0x0, sum = 3
6481 23:49:56.601545 16, 0x0, sum = 4
6482 23:49:56.604236 best_step = 14
6483 23:49:56.604824
6484 23:49:56.605284 ==
6485 23:49:56.608068 Dram Type= 6, Freq= 0, CH_0, rank 0
6486 23:49:56.610912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 23:49:56.611301 ==
6488 23:49:56.611617 RX Vref Scan: 1
6489 23:49:56.614319
6490 23:49:56.614729 RX Vref 0 -> 0, step: 1
6491 23:49:56.615084
6492 23:49:56.617751 RX Delay -359 -> 252, step: 8
6493 23:49:56.618165
6494 23:49:56.621070 Set Vref, RX VrefLevel [Byte0]: 60
6495 23:49:56.624251 [Byte1]: 47
6496 23:49:56.628769
6497 23:49:56.629288 Final RX Vref Byte 0 = 60 to rank0
6498 23:49:56.632192 Final RX Vref Byte 1 = 47 to rank0
6499 23:49:56.635351 Final RX Vref Byte 0 = 60 to rank1
6500 23:49:56.638451 Final RX Vref Byte 1 = 47 to rank1==
6501 23:49:56.641751 Dram Type= 6, Freq= 0, CH_0, rank 0
6502 23:49:56.648525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 23:49:56.648987 ==
6504 23:49:56.649439 DQS Delay:
6505 23:49:56.651915 DQS0 = 60, DQS1 = 68
6506 23:49:56.652349 DQM Delay:
6507 23:49:56.652884 DQM0 = 14, DQM1 = 13
6508 23:49:56.655109 DQ Delay:
6509 23:49:56.658356 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6510 23:49:56.661385 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6511 23:49:56.661924 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6512 23:49:56.665044 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6513 23:49:56.668608
6514 23:49:56.669072
6515 23:49:56.674922 [DQSOSCAuto] RK0, (LSB)MR18= 0x8482, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6516 23:49:56.678603 CH0 RK0: MR19=C0C, MR18=8482
6517 23:49:56.684473 CH0_RK0: MR19=0xC0C, MR18=0x8482, DQSOSC=393, MR23=63, INC=382, DEC=254
6518 23:49:56.684987 ==
6519 23:49:56.688256 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 23:49:56.691607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 23:49:56.692076 ==
6522 23:49:56.694993 [Gating] SW mode calibration
6523 23:49:56.701247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6524 23:49:56.708222 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6525 23:49:56.711996 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6526 23:49:56.714344 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6527 23:49:56.721257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 23:49:56.724377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6529 23:49:56.728224 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 23:49:56.734755 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 23:49:56.737992 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 23:49:56.741033 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6533 23:49:56.747533 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 23:49:56.748007 Total UI for P1: 0, mck2ui 16
6535 23:49:56.754385 best dqsien dly found for B0: ( 0, 14, 24)
6536 23:49:56.754849 Total UI for P1: 0, mck2ui 16
6537 23:49:56.757661 best dqsien dly found for B1: ( 0, 14, 24)
6538 23:49:56.764455 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6539 23:49:56.767703 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6540 23:49:56.768176
6541 23:49:56.770872 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6542 23:49:56.774121 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6543 23:49:56.777836 [Gating] SW calibration Done
6544 23:49:56.778376 ==
6545 23:49:56.781154 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 23:49:56.784728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 23:49:56.785302 ==
6548 23:49:56.787760 RX Vref Scan: 0
6549 23:49:56.788278
6550 23:49:56.788800 RX Vref 0 -> 0, step: 1
6551 23:49:56.789240
6552 23:49:56.790488 RX Delay -410 -> 252, step: 16
6553 23:49:56.797443 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6554 23:49:56.800638 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6555 23:49:56.803929 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6556 23:49:56.807261 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6557 23:49:56.813711 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6558 23:49:56.817216 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6559 23:49:56.820933 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6560 23:49:56.823715 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6561 23:49:56.830709 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6562 23:49:56.834352 iDelay=230, Bit 9, Center -67 (-314 ~ 181) 496
6563 23:49:56.836984 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6564 23:49:56.840471 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6565 23:49:56.846902 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6566 23:49:56.850480 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6567 23:49:56.854226 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6568 23:49:56.857125 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6569 23:49:56.860285 ==
6570 23:49:56.860797 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 23:49:56.867002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 23:49:56.867475 ==
6573 23:49:56.867826 DQS Delay:
6574 23:49:56.870675 DQS0 = 59, DQS1 = 67
6575 23:49:56.871163 DQM Delay:
6576 23:49:56.873764 DQM0 = 16, DQM1 = 17
6577 23:49:56.874224 DQ Delay:
6578 23:49:56.877049 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6579 23:49:56.880950 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6580 23:49:56.884024 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6581 23:49:56.886998 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6582 23:49:56.887458
6583 23:49:56.887813
6584 23:49:56.888149 ==
6585 23:49:56.890154 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 23:49:56.893388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 23:49:56.893849 ==
6588 23:49:56.894190
6589 23:49:56.894495
6590 23:49:56.897316 TX Vref Scan disable
6591 23:49:56.897844 == TX Byte 0 ==
6592 23:49:56.903412 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6593 23:49:56.907009 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6594 23:49:56.907492 == TX Byte 1 ==
6595 23:49:56.913616 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6596 23:49:56.916957 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6597 23:49:56.917502 ==
6598 23:49:56.920228 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 23:49:56.924128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 23:49:56.924740 ==
6601 23:49:56.925110
6602 23:49:56.925445
6603 23:49:56.926484 TX Vref Scan disable
6604 23:49:56.926941 == TX Byte 0 ==
6605 23:49:56.933867 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6606 23:49:56.937278 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6607 23:49:56.937739 == TX Byte 1 ==
6608 23:49:56.943208 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6609 23:49:56.946785 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6610 23:49:56.947249
6611 23:49:56.947624 [DATLAT]
6612 23:49:56.950034 Freq=400, CH0 RK1
6613 23:49:56.950496
6614 23:49:56.950853 DATLAT Default: 0xe
6615 23:49:56.953541 0, 0xFFFF, sum = 0
6616 23:49:56.954005 1, 0xFFFF, sum = 0
6617 23:49:56.956739 2, 0xFFFF, sum = 0
6618 23:49:56.957205 3, 0xFFFF, sum = 0
6619 23:49:56.959628 4, 0xFFFF, sum = 0
6620 23:49:56.960094 5, 0xFFFF, sum = 0
6621 23:49:56.962877 6, 0xFFFF, sum = 0
6622 23:49:56.963340 7, 0xFFFF, sum = 0
6623 23:49:56.966701 8, 0xFFFF, sum = 0
6624 23:49:56.967249 9, 0xFFFF, sum = 0
6625 23:49:56.969971 10, 0xFFFF, sum = 0
6626 23:49:56.973113 11, 0xFFFF, sum = 0
6627 23:49:56.973538 12, 0xFFFF, sum = 0
6628 23:49:56.976873 13, 0x0, sum = 1
6629 23:49:56.977295 14, 0x0, sum = 2
6630 23:49:56.979795 15, 0x0, sum = 3
6631 23:49:56.980321 16, 0x0, sum = 4
6632 23:49:56.980708 best_step = 14
6633 23:49:56.981018
6634 23:49:56.983125 ==
6635 23:49:56.986133 Dram Type= 6, Freq= 0, CH_0, rank 1
6636 23:49:56.989434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 23:49:56.989853 ==
6638 23:49:56.990179 RX Vref Scan: 0
6639 23:49:56.990487
6640 23:49:56.992898 RX Vref 0 -> 0, step: 1
6641 23:49:56.993354
6642 23:49:56.996001 RX Delay -359 -> 252, step: 8
6643 23:49:57.003360 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6644 23:49:57.006449 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6645 23:49:57.009704 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6646 23:49:57.013503 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6647 23:49:57.019756 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6648 23:49:57.023318 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6649 23:49:57.026580 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6650 23:49:57.030203 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6651 23:49:57.036270 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6652 23:49:57.039477 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6653 23:49:57.042638 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6654 23:49:57.049502 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6655 23:49:57.052733 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6656 23:49:57.056159 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6657 23:49:57.059444 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6658 23:49:57.066244 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6659 23:49:57.066706 ==
6660 23:49:57.069594 Dram Type= 6, Freq= 0, CH_0, rank 1
6661 23:49:57.072658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 23:49:57.073078 ==
6663 23:49:57.073401 DQS Delay:
6664 23:49:57.076221 DQS0 = 60, DQS1 = 72
6665 23:49:57.076710 DQM Delay:
6666 23:49:57.079377 DQM0 = 11, DQM1 = 16
6667 23:49:57.079955 DQ Delay:
6668 23:49:57.082505 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6669 23:49:57.085813 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6670 23:49:57.089084 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6671 23:49:57.092320 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6672 23:49:57.092830
6673 23:49:57.093193
6674 23:49:57.099283 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6675 23:49:57.102270 CH0 RK1: MR19=C0C, MR18=C77D
6676 23:49:57.108969 CH0_RK1: MR19=0xC0C, MR18=0xC77D, DQSOSC=385, MR23=63, INC=398, DEC=265
6677 23:49:57.112465 [RxdqsGatingPostProcess] freq 400
6678 23:49:57.119102 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6679 23:49:57.122430 best DQS0 dly(2T, 0.5T) = (0, 10)
6680 23:49:57.122933 best DQS1 dly(2T, 0.5T) = (0, 10)
6681 23:49:57.125728 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6682 23:49:57.132050 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6683 23:49:57.132693 best DQS0 dly(2T, 0.5T) = (0, 10)
6684 23:49:57.135622 best DQS1 dly(2T, 0.5T) = (0, 10)
6685 23:49:57.138497 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6686 23:49:57.141945 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6687 23:49:57.145365 Pre-setting of DQS Precalculation
6688 23:49:57.151862 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6689 23:49:57.152339 ==
6690 23:49:57.155369 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 23:49:57.158434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 23:49:57.158911 ==
6693 23:49:57.164843 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 23:49:57.171748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6695 23:49:57.175183 [CA 0] Center 36 (8~64) winsize 57
6696 23:49:57.175730 [CA 1] Center 36 (8~64) winsize 57
6697 23:49:57.178553 [CA 2] Center 36 (8~64) winsize 57
6698 23:49:57.182002 [CA 3] Center 36 (8~64) winsize 57
6699 23:49:57.185059 [CA 4] Center 36 (8~64) winsize 57
6700 23:49:57.188227 [CA 5] Center 36 (8~64) winsize 57
6701 23:49:57.188694
6702 23:49:57.191656 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6703 23:49:57.192149
6704 23:49:57.198228 [CATrainingPosCal] consider 1 rank data
6705 23:49:57.198757 u2DelayCellTimex100 = 270/100 ps
6706 23:49:57.205013 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 23:49:57.208580 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 23:49:57.211384 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 23:49:57.214890 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 23:49:57.218176 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 23:49:57.221310 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 23:49:57.221845
6713 23:49:57.224829 CA PerBit enable=1, Macro0, CA PI delay=36
6714 23:49:57.225305
6715 23:49:57.227700 [CBTSetCACLKResult] CA Dly = 36
6716 23:49:57.230947 CS Dly: 1 (0~32)
6717 23:49:57.231420 ==
6718 23:49:57.234680 Dram Type= 6, Freq= 0, CH_1, rank 1
6719 23:49:57.238017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 23:49:57.238597 ==
6721 23:49:57.244415 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6722 23:49:57.247571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6723 23:49:57.250915 [CA 0] Center 36 (8~64) winsize 57
6724 23:49:57.254507 [CA 1] Center 36 (8~64) winsize 57
6725 23:49:57.257581 [CA 2] Center 36 (8~64) winsize 57
6726 23:49:57.261011 [CA 3] Center 36 (8~64) winsize 57
6727 23:49:57.264425 [CA 4] Center 36 (8~64) winsize 57
6728 23:49:57.267839 [CA 5] Center 36 (8~64) winsize 57
6729 23:49:57.268314
6730 23:49:57.270589 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6731 23:49:57.271131
6732 23:49:57.274439 [CATrainingPosCal] consider 2 rank data
6733 23:49:57.277516 u2DelayCellTimex100 = 270/100 ps
6734 23:49:57.281129 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 23:49:57.283867 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 23:49:57.290729 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 23:49:57.293854 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 23:49:57.296979 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 23:49:57.300502 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6740 23:49:57.300959
6741 23:49:57.303931 CA PerBit enable=1, Macro0, CA PI delay=36
6742 23:49:57.304360
6743 23:49:57.307373 [CBTSetCACLKResult] CA Dly = 36
6744 23:49:57.307802 CS Dly: 1 (0~32)
6745 23:49:57.308341
6746 23:49:57.310346 ----->DramcWriteLeveling(PI) begin...
6747 23:49:57.314123 ==
6748 23:49:57.316985 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 23:49:57.320076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 23:49:57.320511 ==
6751 23:49:57.323786 Write leveling (Byte 0): 40 => 8
6752 23:49:57.327360 Write leveling (Byte 1): 40 => 8
6753 23:49:57.330661 DramcWriteLeveling(PI) end<-----
6754 23:49:57.331095
6755 23:49:57.331526 ==
6756 23:49:57.333266 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 23:49:57.336940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 23:49:57.337506 ==
6759 23:49:57.340217 [Gating] SW mode calibration
6760 23:49:57.346684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6761 23:49:57.353416 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6762 23:49:57.356738 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6763 23:49:57.359963 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6764 23:49:57.366469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 23:49:57.369761 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6766 23:49:57.372896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 23:49:57.380166 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 23:49:57.383236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 23:49:57.386508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6770 23:49:57.393106 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 23:49:57.393584 Total UI for P1: 0, mck2ui 16
6772 23:49:57.399259 best dqsien dly found for B0: ( 0, 14, 24)
6773 23:49:57.399736 Total UI for P1: 0, mck2ui 16
6774 23:49:57.402996 best dqsien dly found for B1: ( 0, 14, 24)
6775 23:49:57.409630 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6776 23:49:57.413002 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6777 23:49:57.413477
6778 23:49:57.416286 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6779 23:49:57.419318 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6780 23:49:57.422781 [Gating] SW calibration Done
6781 23:49:57.423254 ==
6782 23:49:57.426175 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 23:49:57.429048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 23:49:57.429526 ==
6785 23:49:57.432459 RX Vref Scan: 0
6786 23:49:57.432996
6787 23:49:57.433468 RX Vref 0 -> 0, step: 1
6788 23:49:57.433902
6789 23:49:57.435927 RX Delay -410 -> 252, step: 16
6790 23:49:57.442235 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6791 23:49:57.445322 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6792 23:49:57.448779 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6793 23:49:57.452262 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6794 23:49:57.458653 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6795 23:49:57.462302 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6796 23:49:57.465227 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6797 23:49:57.468710 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6798 23:49:57.475560 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6799 23:49:57.478975 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6800 23:49:57.481944 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6801 23:49:57.485145 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6802 23:49:57.491638 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6803 23:49:57.495494 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6804 23:49:57.498633 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6805 23:49:57.504923 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6806 23:49:57.505386 ==
6807 23:49:57.508265 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 23:49:57.511651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 23:49:57.512141 ==
6810 23:49:57.512504 DQS Delay:
6811 23:49:57.515134 DQS0 = 51, DQS1 = 67
6812 23:49:57.515703 DQM Delay:
6813 23:49:57.518274 DQM0 = 12, DQM1 = 17
6814 23:49:57.518734 DQ Delay:
6815 23:49:57.521730 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6816 23:49:57.525088 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6817 23:49:57.528553 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6818 23:49:57.531658 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6819 23:49:57.532228
6820 23:49:57.532647
6821 23:49:57.532999 ==
6822 23:49:57.534879 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 23:49:57.538042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 23:49:57.538508 ==
6825 23:49:57.538869
6826 23:49:57.539203
6827 23:49:57.541101 TX Vref Scan disable
6828 23:49:57.544600 == TX Byte 0 ==
6829 23:49:57.548142 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 23:49:57.551631 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 23:49:57.552090 == TX Byte 1 ==
6832 23:49:57.558211 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6833 23:49:57.561325 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6834 23:49:57.561787 ==
6835 23:49:57.564625 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 23:49:57.568031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 23:49:57.568493 ==
6838 23:49:57.568901
6839 23:49:57.569209
6840 23:49:57.570945 TX Vref Scan disable
6841 23:49:57.574353 == TX Byte 0 ==
6842 23:49:57.578079 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6843 23:49:57.581290 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6844 23:49:57.584818 == TX Byte 1 ==
6845 23:49:57.587552 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6846 23:49:57.591001 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6847 23:49:57.591417
6848 23:49:57.591742 [DATLAT]
6849 23:49:57.594708 Freq=400, CH1 RK0
6850 23:49:57.595223
6851 23:49:57.595573 DATLAT Default: 0xf
6852 23:49:57.598048 0, 0xFFFF, sum = 0
6853 23:49:57.601124 1, 0xFFFF, sum = 0
6854 23:49:57.601564 2, 0xFFFF, sum = 0
6855 23:49:57.604035 3, 0xFFFF, sum = 0
6856 23:49:57.604468 4, 0xFFFF, sum = 0
6857 23:49:57.607391 5, 0xFFFF, sum = 0
6858 23:49:57.607825 6, 0xFFFF, sum = 0
6859 23:49:57.610765 7, 0xFFFF, sum = 0
6860 23:49:57.611197 8, 0xFFFF, sum = 0
6861 23:49:57.614335 9, 0xFFFF, sum = 0
6862 23:49:57.614885 10, 0xFFFF, sum = 0
6863 23:49:57.617184 11, 0xFFFF, sum = 0
6864 23:49:57.617610 12, 0xFFFF, sum = 0
6865 23:49:57.620735 13, 0x0, sum = 1
6866 23:49:57.621158 14, 0x0, sum = 2
6867 23:49:57.624111 15, 0x0, sum = 3
6868 23:49:57.624865 16, 0x0, sum = 4
6869 23:49:57.627342 best_step = 14
6870 23:49:57.627758
6871 23:49:57.628084 ==
6872 23:49:57.630555 Dram Type= 6, Freq= 0, CH_1, rank 0
6873 23:49:57.634139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 23:49:57.634696 ==
6875 23:49:57.637298 RX Vref Scan: 1
6876 23:49:57.637718
6877 23:49:57.638047 RX Vref 0 -> 0, step: 1
6878 23:49:57.638354
6879 23:49:57.640493 RX Delay -375 -> 252, step: 8
6880 23:49:57.641144
6881 23:49:57.643727 Set Vref, RX VrefLevel [Byte0]: 55
6882 23:49:57.647454 [Byte1]: 50
6883 23:49:57.651829
6884 23:49:57.652457 Final RX Vref Byte 0 = 55 to rank0
6885 23:49:57.654873 Final RX Vref Byte 1 = 50 to rank0
6886 23:49:57.658287 Final RX Vref Byte 0 = 55 to rank1
6887 23:49:57.661636 Final RX Vref Byte 1 = 50 to rank1==
6888 23:49:57.665109 Dram Type= 6, Freq= 0, CH_1, rank 0
6889 23:49:57.671526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 23:49:57.672040 ==
6891 23:49:57.672628 DQS Delay:
6892 23:49:57.675110 DQS0 = 52, DQS1 = 64
6893 23:49:57.675586 DQM Delay:
6894 23:49:57.675933 DQM0 = 9, DQM1 = 11
6895 23:49:57.678346 DQ Delay:
6896 23:49:57.681346 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6897 23:49:57.681772 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6898 23:49:57.684660 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6899 23:49:57.688196 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6900 23:49:57.688665
6901 23:49:57.689009
6902 23:49:57.697869 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c70, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6903 23:49:57.701310 CH1 RK0: MR19=C0C, MR18=5C70
6904 23:49:57.707849 CH1_RK0: MR19=0xC0C, MR18=0x5C70, DQSOSC=395, MR23=63, INC=378, DEC=252
6905 23:49:57.708277 ==
6906 23:49:57.711265 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 23:49:57.714840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 23:49:57.715342 ==
6909 23:49:57.718474 [Gating] SW mode calibration
6910 23:49:57.724676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6911 23:49:57.731035 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6912 23:49:57.734822 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6913 23:49:57.737863 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6914 23:49:57.744244 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 23:49:57.747628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6916 23:49:57.750994 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 23:49:57.754352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 23:49:57.760995 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 23:49:57.764098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6920 23:49:57.767912 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 23:49:57.770933 Total UI for P1: 0, mck2ui 16
6922 23:49:57.774149 best dqsien dly found for B0: ( 0, 14, 24)
6923 23:49:57.777649 Total UI for P1: 0, mck2ui 16
6924 23:49:57.781046 best dqsien dly found for B1: ( 0, 14, 24)
6925 23:49:57.783952 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6926 23:49:57.791124 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6927 23:49:57.791550
6928 23:49:57.794270 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6929 23:49:57.797097 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6930 23:49:57.800461 [Gating] SW calibration Done
6931 23:49:57.800905 ==
6932 23:49:57.803983 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 23:49:57.807344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 23:49:57.807769 ==
6935 23:49:57.810661 RX Vref Scan: 0
6936 23:49:57.811082
6937 23:49:57.811416 RX Vref 0 -> 0, step: 1
6938 23:49:57.811726
6939 23:49:57.814080 RX Delay -410 -> 252, step: 16
6940 23:49:57.820489 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6941 23:49:57.823905 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6942 23:49:57.827487 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6943 23:49:57.830780 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6944 23:49:57.834099 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6945 23:49:57.840291 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6946 23:49:57.843668 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6947 23:49:57.847020 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6948 23:49:57.853680 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6949 23:49:57.856675 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6950 23:49:57.860019 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6951 23:49:57.863799 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6952 23:49:57.870448 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6953 23:49:57.873648 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6954 23:49:57.876514 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6955 23:49:57.879974 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6956 23:49:57.883308 ==
6957 23:49:57.883837 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 23:49:57.890297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 23:49:57.890780 ==
6960 23:49:57.891146 DQS Delay:
6961 23:49:57.893411 DQS0 = 59, DQS1 = 59
6962 23:49:57.893878 DQM Delay:
6963 23:49:57.896860 DQM0 = 19, DQM1 = 11
6964 23:49:57.897330 DQ Delay:
6965 23:49:57.899829 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6966 23:49:57.903079 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6967 23:49:57.906775 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6968 23:49:57.909715 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6969 23:49:57.910162
6970 23:49:57.910597
6971 23:49:57.910917 ==
6972 23:49:57.913338 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 23:49:57.916698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 23:49:57.917163 ==
6975 23:49:57.917563
6976 23:49:57.917885
6977 23:49:57.920034 TX Vref Scan disable
6978 23:49:57.920528 == TX Byte 0 ==
6979 23:49:57.926397 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6980 23:49:57.929808 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6981 23:49:57.930239 == TX Byte 1 ==
6982 23:49:57.936718 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6983 23:49:57.939758 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6984 23:49:57.940260 ==
6985 23:49:57.943242 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 23:49:57.946558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 23:49:57.947144 ==
6988 23:49:57.947492
6989 23:49:57.947858
6990 23:49:57.949849 TX Vref Scan disable
6991 23:49:57.950269 == TX Byte 0 ==
6992 23:49:57.956413 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6993 23:49:57.959834 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6994 23:49:57.960271 == TX Byte 1 ==
6995 23:49:57.966066 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6996 23:49:57.969493 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6997 23:49:57.969920
6998 23:49:57.970253 [DATLAT]
6999 23:49:57.973059 Freq=400, CH1 RK1
7000 23:49:57.973481
7001 23:49:57.973812 DATLAT Default: 0xe
7002 23:49:57.975930 0, 0xFFFF, sum = 0
7003 23:49:57.976454 1, 0xFFFF, sum = 0
7004 23:49:57.979668 2, 0xFFFF, sum = 0
7005 23:49:57.980227 3, 0xFFFF, sum = 0
7006 23:49:57.983060 4, 0xFFFF, sum = 0
7007 23:49:57.983490 5, 0xFFFF, sum = 0
7008 23:49:57.986327 6, 0xFFFF, sum = 0
7009 23:49:57.986874 7, 0xFFFF, sum = 0
7010 23:49:57.989398 8, 0xFFFF, sum = 0
7011 23:49:57.989828 9, 0xFFFF, sum = 0
7012 23:49:57.992705 10, 0xFFFF, sum = 0
7013 23:49:57.996241 11, 0xFFFF, sum = 0
7014 23:49:57.996710 12, 0xFFFF, sum = 0
7015 23:49:57.999619 13, 0x0, sum = 1
7016 23:49:58.000170 14, 0x0, sum = 2
7017 23:49:58.002404 15, 0x0, sum = 3
7018 23:49:58.002846 16, 0x0, sum = 4
7019 23:49:58.003294 best_step = 14
7020 23:49:58.003766
7021 23:49:58.006031 ==
7022 23:49:58.009309 Dram Type= 6, Freq= 0, CH_1, rank 1
7023 23:49:58.012694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7024 23:49:58.013133 ==
7025 23:49:58.013571 RX Vref Scan: 0
7026 23:49:58.013987
7027 23:49:58.016026 RX Vref 0 -> 0, step: 1
7028 23:49:58.016457
7029 23:49:58.019312 RX Delay -359 -> 252, step: 8
7030 23:49:58.026108 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7031 23:49:58.029978 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7032 23:49:58.032869 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7033 23:49:58.039195 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7034 23:49:58.043033 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7035 23:49:58.045692 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7036 23:49:58.049151 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7037 23:49:58.056084 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7038 23:49:58.059227 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7039 23:49:58.062340 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7040 23:49:58.065472 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7041 23:49:58.072456 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7042 23:49:58.075598 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7043 23:49:58.079177 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7044 23:49:58.082475 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7045 23:49:58.088955 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7046 23:49:58.089510 ==
7047 23:49:58.092504 Dram Type= 6, Freq= 0, CH_1, rank 1
7048 23:49:58.095425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7049 23:49:58.096001 ==
7050 23:49:58.096407 DQS Delay:
7051 23:49:58.098581 DQS0 = 60, DQS1 = 64
7052 23:49:58.099137 DQM Delay:
7053 23:49:58.102184 DQM0 = 12, DQM1 = 10
7054 23:49:58.102613 DQ Delay:
7055 23:49:58.105119 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7056 23:49:58.108608 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7057 23:49:58.112245 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7058 23:49:58.115074 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7059 23:49:58.115502
7060 23:49:58.115926
7061 23:49:58.121864 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7062 23:49:58.125297 CH1 RK1: MR19=C0C, MR18=76A6
7063 23:49:58.132054 CH1_RK1: MR19=0xC0C, MR18=0x76A6, DQSOSC=389, MR23=63, INC=390, DEC=260
7064 23:49:58.135203 [RxdqsGatingPostProcess] freq 400
7065 23:49:58.142081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7066 23:49:58.145149 best DQS0 dly(2T, 0.5T) = (0, 10)
7067 23:49:58.148091 best DQS1 dly(2T, 0.5T) = (0, 10)
7068 23:49:58.151745 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7069 23:49:58.152191 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7070 23:49:58.155114 best DQS0 dly(2T, 0.5T) = (0, 10)
7071 23:49:58.158607 best DQS1 dly(2T, 0.5T) = (0, 10)
7072 23:49:58.161793 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7073 23:49:58.165040 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7074 23:49:58.168419 Pre-setting of DQS Precalculation
7075 23:49:58.175033 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7076 23:49:58.181390 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7077 23:49:58.188516 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7078 23:49:58.189171
7079 23:49:58.189526
7080 23:49:58.191755 [Calibration Summary] 800 Mbps
7081 23:49:58.192229 CH 0, Rank 0
7082 23:49:58.195134 SW Impedance : PASS
7083 23:49:58.198032 DUTY Scan : NO K
7084 23:49:58.198527 ZQ Calibration : PASS
7085 23:49:58.201398 Jitter Meter : NO K
7086 23:49:58.204855 CBT Training : PASS
7087 23:49:58.205333 Write leveling : PASS
7088 23:49:58.208251 RX DQS gating : PASS
7089 23:49:58.211839 RX DQ/DQS(RDDQC) : PASS
7090 23:49:58.212314 TX DQ/DQS : PASS
7091 23:49:58.214651 RX DATLAT : PASS
7092 23:49:58.217937 RX DQ/DQS(Engine): PASS
7093 23:49:58.218481 TX OE : NO K
7094 23:49:58.220939 All Pass.
7095 23:49:58.221360
7096 23:49:58.221689 CH 0, Rank 1
7097 23:49:58.224590 SW Impedance : PASS
7098 23:49:58.225099 DUTY Scan : NO K
7099 23:49:58.227756 ZQ Calibration : PASS
7100 23:49:58.231312 Jitter Meter : NO K
7101 23:49:58.231913 CBT Training : PASS
7102 23:49:58.234234 Write leveling : NO K
7103 23:49:58.234846 RX DQS gating : PASS
7104 23:49:58.237861 RX DQ/DQS(RDDQC) : PASS
7105 23:49:58.241108 TX DQ/DQS : PASS
7106 23:49:58.241588 RX DATLAT : PASS
7107 23:49:58.244172 RX DQ/DQS(Engine): PASS
7108 23:49:58.248334 TX OE : NO K
7109 23:49:58.248861 All Pass.
7110 23:49:58.249207
7111 23:49:58.249517 CH 1, Rank 0
7112 23:49:58.250787 SW Impedance : PASS
7113 23:49:58.254035 DUTY Scan : NO K
7114 23:49:58.254460 ZQ Calibration : PASS
7115 23:49:58.257263 Jitter Meter : NO K
7116 23:49:58.260641 CBT Training : PASS
7117 23:49:58.261068 Write leveling : PASS
7118 23:49:58.264337 RX DQS gating : PASS
7119 23:49:58.267888 RX DQ/DQS(RDDQC) : PASS
7120 23:49:58.268310 TX DQ/DQS : PASS
7121 23:49:58.270656 RX DATLAT : PASS
7122 23:49:58.274004 RX DQ/DQS(Engine): PASS
7123 23:49:58.274430 TX OE : NO K
7124 23:49:58.277069 All Pass.
7125 23:49:58.277563
7126 23:49:58.277901 CH 1, Rank 1
7127 23:49:58.280529 SW Impedance : PASS
7128 23:49:58.280972 DUTY Scan : NO K
7129 23:49:58.283631 ZQ Calibration : PASS
7130 23:49:58.287070 Jitter Meter : NO K
7131 23:49:58.287496 CBT Training : PASS
7132 23:49:58.290216 Write leveling : NO K
7133 23:49:58.293802 RX DQS gating : PASS
7134 23:49:58.294420 RX DQ/DQS(RDDQC) : PASS
7135 23:49:58.297083 TX DQ/DQS : PASS
7136 23:49:58.300180 RX DATLAT : PASS
7137 23:49:58.300676 RX DQ/DQS(Engine): PASS
7138 23:49:58.303652 TX OE : NO K
7139 23:49:58.304132 All Pass.
7140 23:49:58.304534
7141 23:49:58.307088 DramC Write-DBI off
7142 23:49:58.310114 PER_BANK_REFRESH: Hybrid Mode
7143 23:49:58.310587 TX_TRACKING: ON
7144 23:49:58.319802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7145 23:49:58.323520 [FAST_K] Save calibration result to emmc
7146 23:49:58.326640 dramc_set_vcore_voltage set vcore to 725000
7147 23:49:58.329961 Read voltage for 1600, 0
7148 23:49:58.330424 Vio18 = 0
7149 23:49:58.330819 Vcore = 725000
7150 23:49:58.333573 Vdram = 0
7151 23:49:58.333999 Vddq = 0
7152 23:49:58.334419 Vmddr = 0
7153 23:49:58.340053 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7154 23:49:58.342986 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7155 23:49:58.346545 MEM_TYPE=3, freq_sel=13
7156 23:49:58.350013 sv_algorithm_assistance_LP4_3733
7157 23:49:58.353481 ============ PULL DRAM RESETB DOWN ============
7158 23:49:58.356381 ========== PULL DRAM RESETB DOWN end =========
7159 23:49:58.362853 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7160 23:49:58.366187 ===================================
7161 23:49:58.369894 LPDDR4 DRAM CONFIGURATION
7162 23:49:58.370385 ===================================
7163 23:49:58.373234 EX_ROW_EN[0] = 0x0
7164 23:49:58.376099 EX_ROW_EN[1] = 0x0
7165 23:49:58.376486 LP4Y_EN = 0x0
7166 23:49:58.379618 WORK_FSP = 0x1
7167 23:49:58.380079 WL = 0x5
7168 23:49:58.382627 RL = 0x5
7169 23:49:58.383096 BL = 0x2
7170 23:49:58.386154 RPST = 0x0
7171 23:49:58.386612 RD_PRE = 0x0
7172 23:49:58.389508 WR_PRE = 0x1
7173 23:49:58.389945 WR_PST = 0x1
7174 23:49:58.392697 DBI_WR = 0x0
7175 23:49:58.393163 DBI_RD = 0x0
7176 23:49:58.396205 OTF = 0x1
7177 23:49:58.399437 ===================================
7178 23:49:58.402581 ===================================
7179 23:49:58.403048 ANA top config
7180 23:49:58.405989 ===================================
7181 23:49:58.409546 DLL_ASYNC_EN = 0
7182 23:49:58.412667 ALL_SLAVE_EN = 0
7183 23:49:58.416060 NEW_RANK_MODE = 1
7184 23:49:58.416649 DLL_IDLE_MODE = 1
7185 23:49:58.419690 LP45_APHY_COMB_EN = 1
7186 23:49:58.422623 TX_ODT_DIS = 0
7187 23:49:58.426027 NEW_8X_MODE = 1
7188 23:49:58.429584 ===================================
7189 23:49:58.432927 ===================================
7190 23:49:58.436227 data_rate = 3200
7191 23:49:58.439313 CKR = 1
7192 23:49:58.439752 DQ_P2S_RATIO = 8
7193 23:49:58.442583 ===================================
7194 23:49:58.445901 CA_P2S_RATIO = 8
7195 23:49:58.449506 DQ_CA_OPEN = 0
7196 23:49:58.452180 DQ_SEMI_OPEN = 0
7197 23:49:58.455771 CA_SEMI_OPEN = 0
7198 23:49:58.458675 CA_FULL_RATE = 0
7199 23:49:58.459138 DQ_CKDIV4_EN = 0
7200 23:49:58.462372 CA_CKDIV4_EN = 0
7201 23:49:58.465553 CA_PREDIV_EN = 0
7202 23:49:58.468985 PH8_DLY = 12
7203 23:49:58.472065 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7204 23:49:58.475360 DQ_AAMCK_DIV = 4
7205 23:49:58.475822 CA_AAMCK_DIV = 4
7206 23:49:58.478552 CA_ADMCK_DIV = 4
7207 23:49:58.481698 DQ_TRACK_CA_EN = 0
7208 23:49:58.485214 CA_PICK = 1600
7209 23:49:58.488658 CA_MCKIO = 1600
7210 23:49:58.492083 MCKIO_SEMI = 0
7211 23:49:58.495268 PLL_FREQ = 3068
7212 23:49:58.498704 DQ_UI_PI_RATIO = 32
7213 23:49:58.499187 CA_UI_PI_RATIO = 0
7214 23:49:58.501802 ===================================
7215 23:49:58.505038 ===================================
7216 23:49:58.508552 memory_type:LPDDR4
7217 23:49:58.511918 GP_NUM : 10
7218 23:49:58.512363 SRAM_EN : 1
7219 23:49:58.514972 MD32_EN : 0
7220 23:49:58.518251 ===================================
7221 23:49:58.521207 [ANA_INIT] >>>>>>>>>>>>>>
7222 23:49:58.524732 <<<<<< [CONFIGURE PHASE]: ANA_TX
7223 23:49:58.528121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7224 23:49:58.531658 ===================================
7225 23:49:58.532119 data_rate = 3200,PCW = 0X7600
7226 23:49:58.534646 ===================================
7227 23:49:58.537999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7228 23:49:58.544438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7229 23:49:58.551037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7230 23:49:58.554578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7231 23:49:58.557420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7232 23:49:58.561151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7233 23:49:58.564599 [ANA_INIT] flow start
7234 23:49:58.567668 [ANA_INIT] PLL >>>>>>>>
7235 23:49:58.568128 [ANA_INIT] PLL <<<<<<<<
7236 23:49:58.570963 [ANA_INIT] MIDPI >>>>>>>>
7237 23:49:58.574080 [ANA_INIT] MIDPI <<<<<<<<
7238 23:49:58.574539 [ANA_INIT] DLL >>>>>>>>
7239 23:49:58.577522 [ANA_INIT] DLL <<<<<<<<
7240 23:49:58.580461 [ANA_INIT] flow end
7241 23:49:58.584138 ============ LP4 DIFF to SE enter ============
7242 23:49:58.587256 ============ LP4 DIFF to SE exit ============
7243 23:49:58.590910 [ANA_INIT] <<<<<<<<<<<<<
7244 23:49:58.593941 [Flow] Enable top DCM control >>>>>
7245 23:49:58.597262 [Flow] Enable top DCM control <<<<<
7246 23:49:58.600360 Enable DLL master slave shuffle
7247 23:49:58.604067 ==============================================================
7248 23:49:58.607415 Gating Mode config
7249 23:49:58.614067 ==============================================================
7250 23:49:58.614601 Config description:
7251 23:49:58.623356 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7252 23:49:58.630720 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7253 23:49:58.637125 SELPH_MODE 0: By rank 1: By Phase
7254 23:49:58.640667 ==============================================================
7255 23:49:58.643305 GAT_TRACK_EN = 1
7256 23:49:58.646908 RX_GATING_MODE = 2
7257 23:49:58.649905 RX_GATING_TRACK_MODE = 2
7258 23:49:58.653246 SELPH_MODE = 1
7259 23:49:58.656738 PICG_EARLY_EN = 1
7260 23:49:58.660336 VALID_LAT_VALUE = 1
7261 23:49:58.663621 ==============================================================
7262 23:49:58.666542 Enter into Gating configuration >>>>
7263 23:49:58.669867 Exit from Gating configuration <<<<
7264 23:49:58.673010 Enter into DVFS_PRE_config >>>>>
7265 23:49:58.687072 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7266 23:49:58.689761 Exit from DVFS_PRE_config <<<<<
7267 23:49:58.693271 Enter into PICG configuration >>>>
7268 23:49:58.696539 Exit from PICG configuration <<<<
7269 23:49:58.696988 [RX_INPUT] configuration >>>>>
7270 23:49:58.699811 [RX_INPUT] configuration <<<<<
7271 23:49:58.706444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7272 23:49:58.709972 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7273 23:49:58.716339 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7274 23:49:58.722616 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7275 23:49:58.729919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7276 23:49:58.736083 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7277 23:49:58.739202 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7278 23:49:58.742847 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7279 23:49:58.749046 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7280 23:49:58.752462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7281 23:49:58.755848 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7282 23:49:58.762265 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 23:49:58.765663 ===================================
7284 23:49:58.766135 LPDDR4 DRAM CONFIGURATION
7285 23:49:58.768881 ===================================
7286 23:49:58.772509 EX_ROW_EN[0] = 0x0
7287 23:49:58.773050 EX_ROW_EN[1] = 0x0
7288 23:49:58.775702 LP4Y_EN = 0x0
7289 23:49:58.776215 WORK_FSP = 0x1
7290 23:49:58.779214 WL = 0x5
7291 23:49:58.779718 RL = 0x5
7292 23:49:58.782463 BL = 0x2
7293 23:49:58.785952 RPST = 0x0
7294 23:49:58.786572 RD_PRE = 0x0
7295 23:49:58.789127 WR_PRE = 0x1
7296 23:49:58.789637 WR_PST = 0x1
7297 23:49:58.791853 DBI_WR = 0x0
7298 23:49:58.792307 DBI_RD = 0x0
7299 23:49:58.795407 OTF = 0x1
7300 23:49:58.798936 ===================================
7301 23:49:58.802592 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7302 23:49:58.805399 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7303 23:49:58.809231 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7304 23:49:58.811950 ===================================
7305 23:49:58.815507 LPDDR4 DRAM CONFIGURATION
7306 23:49:58.818605 ===================================
7307 23:49:58.822221 EX_ROW_EN[0] = 0x10
7308 23:49:58.822820 EX_ROW_EN[1] = 0x0
7309 23:49:58.825346 LP4Y_EN = 0x0
7310 23:49:58.825801 WORK_FSP = 0x1
7311 23:49:58.828743 WL = 0x5
7312 23:49:58.829283 RL = 0x5
7313 23:49:58.831874 BL = 0x2
7314 23:49:58.835230 RPST = 0x0
7315 23:49:58.835649 RD_PRE = 0x0
7316 23:49:58.838477 WR_PRE = 0x1
7317 23:49:58.839008 WR_PST = 0x1
7318 23:49:58.841704 DBI_WR = 0x0
7319 23:49:58.842122 DBI_RD = 0x0
7320 23:49:58.845147 OTF = 0x1
7321 23:49:58.848658 ===================================
7322 23:49:58.851722 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7323 23:49:58.854869 ==
7324 23:49:58.858114 Dram Type= 6, Freq= 0, CH_0, rank 0
7325 23:49:58.861628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 23:49:58.862052 ==
7327 23:49:58.864849 [Duty_Offset_Calibration]
7328 23:49:58.865374 B0:2 B1:0 CA:3
7329 23:49:58.865792
7330 23:49:58.868082 [DutyScan_Calibration_Flow] k_type=0
7331 23:49:58.877973
7332 23:49:58.878393 ==CLK 0==
7333 23:49:58.881384 Final CLK duty delay cell = 0
7334 23:49:58.884666 [0] MAX Duty = 5031%(X100), DQS PI = 12
7335 23:49:58.888034 [0] MIN Duty = 4907%(X100), DQS PI = 6
7336 23:49:58.891480 [0] AVG Duty = 4969%(X100)
7337 23:49:58.891899
7338 23:49:58.894836 CH0 CLK Duty spec in!! Max-Min= 124%
7339 23:49:58.897999 [DutyScan_Calibration_Flow] ====Done====
7340 23:49:58.898542
7341 23:49:58.901044 [DutyScan_Calibration_Flow] k_type=1
7342 23:49:58.917785
7343 23:49:58.918253 ==DQS 0 ==
7344 23:49:58.921513 Final DQS duty delay cell = 0
7345 23:49:58.924300 [0] MAX Duty = 5094%(X100), DQS PI = 14
7346 23:49:58.927777 [0] MIN Duty = 4875%(X100), DQS PI = 48
7347 23:49:58.931095 [0] AVG Duty = 4984%(X100)
7348 23:49:58.931520
7349 23:49:58.932087 ==DQS 1 ==
7350 23:49:58.934567 Final DQS duty delay cell = 0
7351 23:49:58.937507 [0] MAX Duty = 5156%(X100), DQS PI = 30
7352 23:49:58.940909 [0] MIN Duty = 5031%(X100), DQS PI = 14
7353 23:49:58.944584 [0] AVG Duty = 5093%(X100)
7354 23:49:58.945081
7355 23:49:58.947557 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7356 23:49:58.948030
7357 23:49:58.950826 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7358 23:49:58.954489 [DutyScan_Calibration_Flow] ====Done====
7359 23:49:58.955007
7360 23:49:58.957267 [DutyScan_Calibration_Flow] k_type=3
7361 23:49:58.975778
7362 23:49:58.976106 ==DQM 0 ==
7363 23:49:58.978757 Final DQM duty delay cell = 0
7364 23:49:58.981916 [0] MAX Duty = 5156%(X100), DQS PI = 28
7365 23:49:58.985732 [0] MIN Duty = 4875%(X100), DQS PI = 0
7366 23:49:58.985925 [0] AVG Duty = 5015%(X100)
7367 23:49:58.989046
7368 23:49:58.989238 ==DQM 1 ==
7369 23:49:58.992248 Final DQM duty delay cell = 4
7370 23:49:58.995182 [4] MAX Duty = 5187%(X100), DQS PI = 62
7371 23:49:58.998964 [4] MIN Duty = 5031%(X100), DQS PI = 12
7372 23:49:59.002244 [4] AVG Duty = 5109%(X100)
7373 23:49:59.002500
7374 23:49:59.005662 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7375 23:49:59.005853
7376 23:49:59.008764 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7377 23:49:59.012200 [DutyScan_Calibration_Flow] ====Done====
7378 23:49:59.012691
7379 23:49:59.015718 [DutyScan_Calibration_Flow] k_type=2
7380 23:49:59.032015
7381 23:49:59.032534 ==DQ 0 ==
7382 23:49:59.035124 Final DQ duty delay cell = -4
7383 23:49:59.038647 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7384 23:49:59.042087 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7385 23:49:59.045506 [-4] AVG Duty = 4938%(X100)
7386 23:49:59.045949
7387 23:49:59.046444 ==DQ 1 ==
7388 23:49:59.048632 Final DQ duty delay cell = 0
7389 23:49:59.051837 [0] MAX Duty = 5156%(X100), DQS PI = 58
7390 23:49:59.055786 [0] MIN Duty = 5000%(X100), DQS PI = 16
7391 23:49:59.058322 [0] AVG Duty = 5078%(X100)
7392 23:49:59.058743
7393 23:49:59.061804 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7394 23:49:59.062227
7395 23:49:59.065025 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7396 23:49:59.068187 [DutyScan_Calibration_Flow] ====Done====
7397 23:49:59.068655 ==
7398 23:49:59.072097 Dram Type= 6, Freq= 0, CH_1, rank 0
7399 23:49:59.075161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7400 23:49:59.075594 ==
7401 23:49:59.078635 [Duty_Offset_Calibration]
7402 23:49:59.079052 B0:1 B1:-2 CA:1
7403 23:49:59.079475
7404 23:49:59.081968 [DutyScan_Calibration_Flow] k_type=0
7405 23:49:59.092273
7406 23:49:59.092796 ==CLK 0==
7407 23:49:59.095897 Final CLK duty delay cell = 0
7408 23:49:59.099338 [0] MAX Duty = 5062%(X100), DQS PI = 20
7409 23:49:59.102476 [0] MIN Duty = 4844%(X100), DQS PI = 58
7410 23:49:59.102894 [0] AVG Duty = 4953%(X100)
7411 23:49:59.105987
7412 23:49:59.109472 CH1 CLK Duty spec in!! Max-Min= 218%
7413 23:49:59.112472 [DutyScan_Calibration_Flow] ====Done====
7414 23:49:59.112918
7415 23:49:59.115656 [DutyScan_Calibration_Flow] k_type=1
7416 23:49:59.132108
7417 23:49:59.132525 ==DQS 0 ==
7418 23:49:59.135125 Final DQS duty delay cell = 0
7419 23:49:59.138822 [0] MAX Duty = 5187%(X100), DQS PI = 24
7420 23:49:59.142043 [0] MIN Duty = 5062%(X100), DQS PI = 0
7421 23:49:59.145041 [0] AVG Duty = 5124%(X100)
7422 23:49:59.145460
7423 23:49:59.145791 ==DQS 1 ==
7424 23:49:59.148382 Final DQS duty delay cell = 0
7425 23:49:59.151875 [0] MAX Duty = 5093%(X100), DQS PI = 62
7426 23:49:59.155243 [0] MIN Duty = 4844%(X100), DQS PI = 24
7427 23:49:59.158730 [0] AVG Duty = 4968%(X100)
7428 23:49:59.159151
7429 23:49:59.162026 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7430 23:49:59.162476
7431 23:49:59.164871 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7432 23:49:59.168243 [DutyScan_Calibration_Flow] ====Done====
7433 23:49:59.168704
7434 23:49:59.171645 [DutyScan_Calibration_Flow] k_type=3
7435 23:49:59.188727
7436 23:49:59.189124 ==DQM 0 ==
7437 23:49:59.192327 Final DQM duty delay cell = 0
7438 23:49:59.195176 [0] MAX Duty = 5031%(X100), DQS PI = 24
7439 23:49:59.198737 [0] MIN Duty = 4813%(X100), DQS PI = 54
7440 23:49:59.201885 [0] AVG Duty = 4922%(X100)
7441 23:49:59.202332
7442 23:49:59.202699 ==DQM 1 ==
7443 23:49:59.204987 Final DQM duty delay cell = 0
7444 23:49:59.208682 [0] MAX Duty = 5062%(X100), DQS PI = 34
7445 23:49:59.211770 [0] MIN Duty = 4875%(X100), DQS PI = 24
7446 23:49:59.215354 [0] AVG Duty = 4968%(X100)
7447 23:49:59.215773
7448 23:49:59.218736 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7449 23:49:59.219214
7450 23:49:59.221849 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7451 23:49:59.225344 [DutyScan_Calibration_Flow] ====Done====
7452 23:49:59.225765
7453 23:49:59.228527 [DutyScan_Calibration_Flow] k_type=2
7454 23:49:59.245551
7455 23:49:59.245967 ==DQ 0 ==
7456 23:49:59.248660 Final DQ duty delay cell = 0
7457 23:49:59.251977 [0] MAX Duty = 5093%(X100), DQS PI = 20
7458 23:49:59.255625 [0] MIN Duty = 4938%(X100), DQS PI = 0
7459 23:49:59.256043 [0] AVG Duty = 5015%(X100)
7460 23:49:59.258705
7461 23:49:59.259118 ==DQ 1 ==
7462 23:49:59.261943 Final DQ duty delay cell = 0
7463 23:49:59.265552 [0] MAX Duty = 5156%(X100), DQS PI = 36
7464 23:49:59.268926 [0] MIN Duty = 4969%(X100), DQS PI = 24
7465 23:49:59.269342 [0] AVG Duty = 5062%(X100)
7466 23:49:59.269667
7467 23:49:59.272307 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7468 23:49:59.275537
7469 23:49:59.278603 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7470 23:49:59.282485 [DutyScan_Calibration_Flow] ====Done====
7471 23:49:59.285110 nWR fixed to 30
7472 23:49:59.285532 [ModeRegInit_LP4] CH0 RK0
7473 23:49:59.288839 [ModeRegInit_LP4] CH0 RK1
7474 23:49:59.292290 [ModeRegInit_LP4] CH1 RK0
7475 23:49:59.295634 [ModeRegInit_LP4] CH1 RK1
7476 23:49:59.296048 match AC timing 5
7477 23:49:59.298458 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7478 23:49:59.305464 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7479 23:49:59.309013 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7480 23:49:59.315075 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7481 23:49:59.318471 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7482 23:49:59.318924 [MiockJmeterHQA]
7483 23:49:59.319267
7484 23:49:59.321575 [DramcMiockJmeter] u1RxGatingPI = 0
7485 23:49:59.325614 0 : 4263, 4032
7486 23:49:59.326107 4 : 4257, 4031
7487 23:49:59.328537 8 : 4257, 4029
7488 23:49:59.329004 12 : 4255, 4029
7489 23:49:59.329341 16 : 4255, 4030
7490 23:49:59.331727 20 : 4365, 4140
7491 23:49:59.332151 24 : 4257, 4029
7492 23:49:59.334819 28 : 4252, 4029
7493 23:49:59.335275 32 : 4366, 4140
7494 23:49:59.338404 36 : 4258, 4032
7495 23:49:59.338829 40 : 4250, 4026
7496 23:49:59.339163 44 : 4255, 4029
7497 23:49:59.341734 48 : 4252, 4030
7498 23:49:59.342160 52 : 4253, 4029
7499 23:49:59.345299 56 : 4258, 4032
7500 23:49:59.345730 60 : 4255, 4030
7501 23:49:59.348456 64 : 4253, 4030
7502 23:49:59.348920 68 : 4368, 4142
7503 23:49:59.351980 72 : 4253, 4029
7504 23:49:59.352406 76 : 4252, 4030
7505 23:49:59.352995 80 : 4252, 4029
7506 23:49:59.354983 84 : 4253, 4029
7507 23:49:59.355414 88 : 4368, 4142
7508 23:49:59.358674 92 : 4252, 4029
7509 23:49:59.359112 96 : 4253, 4029
7510 23:49:59.361679 100 : 4363, 4140
7511 23:49:59.362105 104 : 4365, 3747
7512 23:49:59.362527 108 : 4253, 7
7513 23:49:59.364939 112 : 4363, 0
7514 23:49:59.365368 116 : 4255, 0
7515 23:49:59.368587 120 : 4254, 0
7516 23:49:59.369053 124 : 4366, 0
7517 23:49:59.369390 128 : 4366, 0
7518 23:49:59.371600 132 : 4252, 0
7519 23:49:59.372027 136 : 4361, 0
7520 23:49:59.375243 140 : 4252, 0
7521 23:49:59.375671 144 : 4252, 0
7522 23:49:59.376005 148 : 4250, 0
7523 23:49:59.378398 152 : 4252, 0
7524 23:49:59.378822 156 : 4252, 0
7525 23:49:59.381736 160 : 4363, 0
7526 23:49:59.382159 164 : 4252, 0
7527 23:49:59.382492 168 : 4252, 0
7528 23:49:59.385081 172 : 4255, 0
7529 23:49:59.385508 176 : 4253, 0
7530 23:49:59.388667 180 : 4252, 0
7531 23:49:59.389127 184 : 4258, 0
7532 23:49:59.389464 188 : 4252, 0
7533 23:49:59.391418 192 : 4252, 0
7534 23:49:59.391842 196 : 4252, 0
7535 23:49:59.392178 200 : 4253, 0
7536 23:49:59.394673 204 : 4253, 0
7537 23:49:59.395098 208 : 4257, 0
7538 23:49:59.397932 212 : 4253, 0
7539 23:49:59.398358 216 : 4250, 0
7540 23:49:59.398694 220 : 4255, 0
7541 23:49:59.401483 224 : 4252, 0
7542 23:49:59.401943 228 : 4253, 0
7543 23:49:59.404968 232 : 4365, 0
7544 23:49:59.405395 236 : 4252, 1263
7545 23:49:59.408026 240 : 4257, 4032
7546 23:49:59.408447 244 : 4255, 4029
7547 23:49:59.411164 248 : 4363, 4140
7548 23:49:59.411592 252 : 4363, 4140
7549 23:49:59.411934 256 : 4250, 4027
7550 23:49:59.414667 260 : 4368, 4143
7551 23:49:59.415092 264 : 4366, 4140
7552 23:49:59.418057 268 : 4253, 4029
7553 23:49:59.418482 272 : 4255, 4029
7554 23:49:59.421413 276 : 4252, 4029
7555 23:49:59.421838 280 : 4255, 4029
7556 23:49:59.424739 284 : 4253, 4029
7557 23:49:59.425167 288 : 4258, 4031
7558 23:49:59.427986 292 : 4255, 4029
7559 23:49:59.428410 296 : 4363, 4140
7560 23:49:59.431152 300 : 4363, 4140
7561 23:49:59.431578 304 : 4253, 4029
7562 23:49:59.434487 308 : 4253, 4029
7563 23:49:59.434911 312 : 4363, 4139
7564 23:49:59.435246 316 : 4366, 4140
7565 23:49:59.437910 320 : 4253, 4029
7566 23:49:59.438333 324 : 4253, 4029
7567 23:49:59.441222 328 : 4253, 4029
7568 23:49:59.441645 332 : 4252, 4029
7569 23:49:59.443977 336 : 4253, 4029
7570 23:49:59.444399 340 : 4363, 4140
7571 23:49:59.447329 344 : 4252, 4027
7572 23:49:59.447752 348 : 4255, 4030
7573 23:49:59.450863 352 : 4363, 4138
7574 23:49:59.451289 356 : 4253, 2992
7575 23:49:59.453796 360 : 4255, 3
7576 23:49:59.454354
7577 23:49:59.454691 MIOCK jitter meter ch=0
7578 23:49:59.455004
7579 23:49:59.457014 1T = (360-108) = 252 dly cells
7580 23:49:59.463881 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7581 23:49:59.464409 ==
7582 23:49:59.467457 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 23:49:59.470544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 23:49:59.470980 ==
7585 23:49:59.476896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7586 23:49:59.480438 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7587 23:49:59.487324 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7588 23:49:59.490331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7589 23:49:59.500769 [CA 0] Center 44 (14~75) winsize 62
7590 23:49:59.503674 [CA 1] Center 43 (13~74) winsize 62
7591 23:49:59.507146 [CA 2] Center 40 (11~69) winsize 59
7592 23:49:59.510262 [CA 3] Center 39 (10~68) winsize 59
7593 23:49:59.513606 [CA 4] Center 37 (8~67) winsize 60
7594 23:49:59.517104 [CA 5] Center 37 (7~67) winsize 61
7595 23:49:59.517641
7596 23:49:59.520074 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7597 23:49:59.520493
7598 23:49:59.527193 [CATrainingPosCal] consider 1 rank data
7599 23:49:59.527609 u2DelayCellTimex100 = 258/100 ps
7600 23:49:59.533532 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7601 23:49:59.536935 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7602 23:49:59.540596 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7603 23:49:59.543547 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7604 23:49:59.546989 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7605 23:49:59.550293 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7606 23:49:59.550789
7607 23:49:59.553611 CA PerBit enable=1, Macro0, CA PI delay=37
7608 23:49:59.554287
7609 23:49:59.556967 [CBTSetCACLKResult] CA Dly = 37
7610 23:49:59.560150 CS Dly: 11 (0~42)
7611 23:49:59.563257 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7612 23:49:59.566928 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7613 23:49:59.567348 ==
7614 23:49:59.569857 Dram Type= 6, Freq= 0, CH_0, rank 1
7615 23:49:59.576681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 23:49:59.577235 ==
7617 23:49:59.580072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7618 23:49:59.586676 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7619 23:49:59.590135 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7620 23:49:59.596607 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7621 23:49:59.604850 [CA 0] Center 44 (14~75) winsize 62
7622 23:49:59.607602 [CA 1] Center 43 (13~74) winsize 62
7623 23:49:59.611093 [CA 2] Center 39 (10~69) winsize 60
7624 23:49:59.614232 [CA 3] Center 39 (10~68) winsize 59
7625 23:49:59.617623 [CA 4] Center 37 (8~67) winsize 60
7626 23:49:59.621025 [CA 5] Center 36 (7~66) winsize 60
7627 23:49:59.621489
7628 23:49:59.624509 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7629 23:49:59.625000
7630 23:49:59.627430 [CATrainingPosCal] consider 2 rank data
7631 23:49:59.631091 u2DelayCellTimex100 = 258/100 ps
7632 23:49:59.637584 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7633 23:49:59.640860 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7634 23:49:59.644467 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7635 23:49:59.647567 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7636 23:49:59.650951 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7637 23:49:59.653930 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7638 23:49:59.654539
7639 23:49:59.657624 CA PerBit enable=1, Macro0, CA PI delay=36
7640 23:49:59.658094
7641 23:49:59.661064 [CBTSetCACLKResult] CA Dly = 36
7642 23:49:59.664295 CS Dly: 11 (0~42)
7643 23:49:59.667278 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7644 23:49:59.670632 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7645 23:49:59.671134
7646 23:49:59.674045 ----->DramcWriteLeveling(PI) begin...
7647 23:49:59.674525 ==
7648 23:49:59.677713 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 23:49:59.684078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 23:49:59.684647 ==
7651 23:49:59.687506 Write leveling (Byte 0): 37 => 37
7652 23:49:59.690594 Write leveling (Byte 1): 27 => 27
7653 23:49:59.691081 DramcWriteLeveling(PI) end<-----
7654 23:49:59.691469
7655 23:49:59.693665 ==
7656 23:49:59.697406 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 23:49:59.700700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 23:49:59.701123 ==
7659 23:49:59.704187 [Gating] SW mode calibration
7660 23:49:59.710399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7661 23:49:59.713945 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7662 23:49:59.720347 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 23:49:59.723883 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 23:49:59.727525 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 23:49:59.733896 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 23:49:59.737380 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7667 23:49:59.740909 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (1 1) (1 1)
7668 23:49:59.747502 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7669 23:49:59.750422 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7670 23:49:59.753636 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 23:49:59.760391 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 23:49:59.763486 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 23:49:59.767328 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7674 23:49:59.773633 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7675 23:49:59.776791 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7676 23:49:59.780236 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7677 23:49:59.786864 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7678 23:49:59.790183 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 23:49:59.793559 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 23:49:59.799969 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 23:49:59.803515 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7682 23:49:59.807228 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7683 23:49:59.813284 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7684 23:49:59.816887 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7685 23:49:59.820037 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7686 23:49:59.826583 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 23:49:59.830026 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 23:49:59.833296 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 23:49:59.839844 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 23:49:59.843523 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7691 23:49:59.846343 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7692 23:49:59.853067 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 23:49:59.856601 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 23:49:59.860133 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 23:49:59.862871 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 23:49:59.869594 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 23:49:59.873245 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 23:49:59.876265 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 23:49:59.882870 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 23:49:59.886618 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 23:49:59.889783 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 23:49:59.896482 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 23:49:59.899721 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 23:49:59.902597 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 23:49:59.909006 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7706 23:49:59.912930 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7707 23:49:59.915745 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7708 23:49:59.919179 Total UI for P1: 0, mck2ui 16
7709 23:49:59.922658 best dqsien dly found for B0: ( 1, 9, 14)
7710 23:49:59.929263 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7711 23:49:59.932299 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7712 23:49:59.935813 Total UI for P1: 0, mck2ui 16
7713 23:49:59.939227 best dqsien dly found for B1: ( 1, 9, 24)
7714 23:49:59.942296 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7715 23:49:59.945577 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7716 23:49:59.946128
7717 23:49:59.949105 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7718 23:49:59.955463 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7719 23:49:59.956101 [Gating] SW calibration Done
7720 23:49:59.956703 ==
7721 23:49:59.959107 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 23:49:59.965459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 23:49:59.966011 ==
7724 23:49:59.966441 RX Vref Scan: 0
7725 23:49:59.966800
7726 23:49:59.968832 RX Vref 0 -> 0, step: 1
7727 23:49:59.969353
7728 23:49:59.972211 RX Delay 0 -> 252, step: 8
7729 23:49:59.975443 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7730 23:49:59.978934 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7731 23:49:59.982016 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7732 23:49:59.988732 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7733 23:49:59.991797 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7734 23:49:59.995339 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7735 23:49:59.998554 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7736 23:50:00.001820 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7737 23:50:00.008299 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7738 23:50:00.011930 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7739 23:50:00.015293 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7740 23:50:00.018382 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7741 23:50:00.021838 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7742 23:50:00.028398 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7743 23:50:00.031265 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7744 23:50:00.034853 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7745 23:50:00.035280 ==
7746 23:50:00.038078 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 23:50:00.041329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 23:50:00.044468 ==
7749 23:50:00.044970 DQS Delay:
7750 23:50:00.045311 DQS0 = 0, DQS1 = 0
7751 23:50:00.047895 DQM Delay:
7752 23:50:00.048316 DQM0 = 128, DQM1 = 124
7753 23:50:00.051395 DQ Delay:
7754 23:50:00.055010 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7755 23:50:00.057893 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =143
7756 23:50:00.061260 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7757 23:50:00.064980 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7758 23:50:00.065409
7759 23:50:00.065787
7760 23:50:00.066252 ==
7761 23:50:00.068034 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 23:50:00.070963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 23:50:00.071390 ==
7764 23:50:00.071725
7765 23:50:00.074761
7766 23:50:00.075224 TX Vref Scan disable
7767 23:50:00.077961 == TX Byte 0 ==
7768 23:50:00.081294 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7769 23:50:00.084201 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7770 23:50:00.087588 == TX Byte 1 ==
7771 23:50:00.091078 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7772 23:50:00.094319 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7773 23:50:00.094746 ==
7774 23:50:00.097542 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 23:50:00.104269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 23:50:00.104745 ==
7777 23:50:00.116963
7778 23:50:00.120315 TX Vref early break, caculate TX vref
7779 23:50:00.123615 TX Vref=16, minBit 8, minWin=20, winSum=363
7780 23:50:00.127332 TX Vref=18, minBit 8, minWin=22, winSum=379
7781 23:50:00.130356 TX Vref=20, minBit 11, minWin=21, winSum=381
7782 23:50:00.133763 TX Vref=22, minBit 8, minWin=23, winSum=393
7783 23:50:00.137424 TX Vref=24, minBit 8, minWin=23, winSum=398
7784 23:50:00.143661 TX Vref=26, minBit 9, minWin=24, winSum=409
7785 23:50:00.147079 TX Vref=28, minBit 8, minWin=24, winSum=409
7786 23:50:00.150185 TX Vref=30, minBit 8, minWin=24, winSum=404
7787 23:50:00.153370 TX Vref=32, minBit 8, minWin=23, winSum=394
7788 23:50:00.156723 TX Vref=34, minBit 9, minWin=21, winSum=385
7789 23:50:00.163441 [TxChooseVref] Worse bit 9, Min win 24, Win sum 409, Final Vref 26
7790 23:50:00.163870
7791 23:50:00.166741 Final TX Range 0 Vref 26
7792 23:50:00.167162
7793 23:50:00.167492 ==
7794 23:50:00.170335 Dram Type= 6, Freq= 0, CH_0, rank 0
7795 23:50:00.173742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7796 23:50:00.174165 ==
7797 23:50:00.174496
7798 23:50:00.174804
7799 23:50:00.176396 TX Vref Scan disable
7800 23:50:00.183345 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7801 23:50:00.183772 == TX Byte 0 ==
7802 23:50:00.186914 u2DelayCellOfst[0]=15 cells (4 PI)
7803 23:50:00.190337 u2DelayCellOfst[1]=18 cells (5 PI)
7804 23:50:00.193077 u2DelayCellOfst[2]=11 cells (3 PI)
7805 23:50:00.196613 u2DelayCellOfst[3]=15 cells (4 PI)
7806 23:50:00.199884 u2DelayCellOfst[4]=7 cells (2 PI)
7807 23:50:00.203204 u2DelayCellOfst[5]=0 cells (0 PI)
7808 23:50:00.206639 u2DelayCellOfst[6]=18 cells (5 PI)
7809 23:50:00.209770 u2DelayCellOfst[7]=18 cells (5 PI)
7810 23:50:00.213070 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7811 23:50:00.216381 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7812 23:50:00.219954 == TX Byte 1 ==
7813 23:50:00.223033 u2DelayCellOfst[8]=0 cells (0 PI)
7814 23:50:00.223450 u2DelayCellOfst[9]=3 cells (1 PI)
7815 23:50:00.226544 u2DelayCellOfst[10]=11 cells (3 PI)
7816 23:50:00.229515 u2DelayCellOfst[11]=7 cells (2 PI)
7817 23:50:00.233036 u2DelayCellOfst[12]=15 cells (4 PI)
7818 23:50:00.236342 u2DelayCellOfst[13]=15 cells (4 PI)
7819 23:50:00.239846 u2DelayCellOfst[14]=18 cells (5 PI)
7820 23:50:00.242850 u2DelayCellOfst[15]=15 cells (4 PI)
7821 23:50:00.249740 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7822 23:50:00.252719 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7823 23:50:00.253139 DramC Write-DBI on
7824 23:50:00.253562 ==
7825 23:50:00.255841 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 23:50:00.262661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 23:50:00.263086 ==
7828 23:50:00.263461
7829 23:50:00.263944
7830 23:50:00.264261 TX Vref Scan disable
7831 23:50:00.267022 == TX Byte 0 ==
7832 23:50:00.269920 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7833 23:50:00.273640 == TX Byte 1 ==
7834 23:50:00.277192 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7835 23:50:00.279988 DramC Write-DBI off
7836 23:50:00.280638
7837 23:50:00.280998 [DATLAT]
7838 23:50:00.281313 Freq=1600, CH0 RK0
7839 23:50:00.281795
7840 23:50:00.283489 DATLAT Default: 0xf
7841 23:50:00.284054 0, 0xFFFF, sum = 0
7842 23:50:00.286926 1, 0xFFFF, sum = 0
7843 23:50:00.287389 2, 0xFFFF, sum = 0
7844 23:50:00.290080 3, 0xFFFF, sum = 0
7845 23:50:00.293605 4, 0xFFFF, sum = 0
7846 23:50:00.294029 5, 0xFFFF, sum = 0
7847 23:50:00.297108 6, 0xFFFF, sum = 0
7848 23:50:00.297531 7, 0xFFFF, sum = 0
7849 23:50:00.300378 8, 0xFFFF, sum = 0
7850 23:50:00.300833 9, 0xFFFF, sum = 0
7851 23:50:00.303299 10, 0xFFFF, sum = 0
7852 23:50:00.303727 11, 0xFFFF, sum = 0
7853 23:50:00.306555 12, 0xFFFF, sum = 0
7854 23:50:00.306981 13, 0xFFFF, sum = 0
7855 23:50:00.309875 14, 0x0, sum = 1
7856 23:50:00.310301 15, 0x0, sum = 2
7857 23:50:00.313297 16, 0x0, sum = 3
7858 23:50:00.313723 17, 0x0, sum = 4
7859 23:50:00.316626 best_step = 15
7860 23:50:00.317046
7861 23:50:00.317373 ==
7862 23:50:00.319845 Dram Type= 6, Freq= 0, CH_0, rank 0
7863 23:50:00.323331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7864 23:50:00.323753 ==
7865 23:50:00.326780 RX Vref Scan: 1
7866 23:50:00.327198
7867 23:50:00.327528 Set Vref Range= 24 -> 127
7868 23:50:00.327835
7869 23:50:00.330134 RX Vref 24 -> 127, step: 1
7870 23:50:00.330554
7871 23:50:00.333527 RX Delay 11 -> 252, step: 4
7872 23:50:00.333947
7873 23:50:00.336534 Set Vref, RX VrefLevel [Byte0]: 24
7874 23:50:00.339898 [Byte1]: 24
7875 23:50:00.340315
7876 23:50:00.343237 Set Vref, RX VrefLevel [Byte0]: 25
7877 23:50:00.346575 [Byte1]: 25
7878 23:50:00.346992
7879 23:50:00.350106 Set Vref, RX VrefLevel [Byte0]: 26
7880 23:50:00.353054 [Byte1]: 26
7881 23:50:00.357109
7882 23:50:00.357529 Set Vref, RX VrefLevel [Byte0]: 27
7883 23:50:00.360499 [Byte1]: 27
7884 23:50:00.365104
7885 23:50:00.365524 Set Vref, RX VrefLevel [Byte0]: 28
7886 23:50:00.368358 [Byte1]: 28
7887 23:50:00.372402
7888 23:50:00.372857 Set Vref, RX VrefLevel [Byte0]: 29
7889 23:50:00.375492 [Byte1]: 29
7890 23:50:00.380388
7891 23:50:00.380919 Set Vref, RX VrefLevel [Byte0]: 30
7892 23:50:00.383610 [Byte1]: 30
7893 23:50:00.387825
7894 23:50:00.388244 Set Vref, RX VrefLevel [Byte0]: 31
7895 23:50:00.390968 [Byte1]: 31
7896 23:50:00.395835
7897 23:50:00.396252 Set Vref, RX VrefLevel [Byte0]: 32
7898 23:50:00.398688 [Byte1]: 32
7899 23:50:00.403337
7900 23:50:00.403894 Set Vref, RX VrefLevel [Byte0]: 33
7901 23:50:00.406548 [Byte1]: 33
7902 23:50:00.410550
7903 23:50:00.411159 Set Vref, RX VrefLevel [Byte0]: 34
7904 23:50:00.413724 [Byte1]: 34
7905 23:50:00.418220
7906 23:50:00.418681 Set Vref, RX VrefLevel [Byte0]: 35
7907 23:50:00.421642 [Byte1]: 35
7908 23:50:00.425929
7909 23:50:00.426397 Set Vref, RX VrefLevel [Byte0]: 36
7910 23:50:00.429097 [Byte1]: 36
7911 23:50:00.433012
7912 23:50:00.433495 Set Vref, RX VrefLevel [Byte0]: 37
7913 23:50:00.437127 [Byte1]: 37
7914 23:50:00.441229
7915 23:50:00.441818 Set Vref, RX VrefLevel [Byte0]: 38
7916 23:50:00.444518 [Byte1]: 38
7917 23:50:00.448378
7918 23:50:00.448921 Set Vref, RX VrefLevel [Byte0]: 39
7919 23:50:00.451694 [Byte1]: 39
7920 23:50:00.456543
7921 23:50:00.457069 Set Vref, RX VrefLevel [Byte0]: 40
7922 23:50:00.459400 [Byte1]: 40
7923 23:50:00.464205
7924 23:50:00.464729 Set Vref, RX VrefLevel [Byte0]: 41
7925 23:50:00.467474 [Byte1]: 41
7926 23:50:00.471494
7927 23:50:00.471976 Set Vref, RX VrefLevel [Byte0]: 42
7928 23:50:00.474864 [Byte1]: 42
7929 23:50:00.479160
7930 23:50:00.479636 Set Vref, RX VrefLevel [Byte0]: 43
7931 23:50:00.482199 [Byte1]: 43
7932 23:50:00.487003
7933 23:50:00.487545 Set Vref, RX VrefLevel [Byte0]: 44
7934 23:50:00.489992 [Byte1]: 44
7935 23:50:00.494571
7936 23:50:00.495052 Set Vref, RX VrefLevel [Byte0]: 45
7937 23:50:00.497853 [Byte1]: 45
7938 23:50:00.501954
7939 23:50:00.502434 Set Vref, RX VrefLevel [Byte0]: 46
7940 23:50:00.505304 [Byte1]: 46
7941 23:50:00.509696
7942 23:50:00.510173 Set Vref, RX VrefLevel [Byte0]: 47
7943 23:50:00.513010 [Byte1]: 47
7944 23:50:00.517215
7945 23:50:00.517694 Set Vref, RX VrefLevel [Byte0]: 48
7946 23:50:00.520249 [Byte1]: 48
7947 23:50:00.524792
7948 23:50:00.525227 Set Vref, RX VrefLevel [Byte0]: 49
7949 23:50:00.528735 [Byte1]: 49
7950 23:50:00.532320
7951 23:50:00.532817 Set Vref, RX VrefLevel [Byte0]: 50
7952 23:50:00.535593 [Byte1]: 50
7953 23:50:00.540272
7954 23:50:00.540889 Set Vref, RX VrefLevel [Byte0]: 51
7955 23:50:00.543324 [Byte1]: 51
7956 23:50:00.547779
7957 23:50:00.548217 Set Vref, RX VrefLevel [Byte0]: 52
7958 23:50:00.550903 [Byte1]: 52
7959 23:50:00.555069
7960 23:50:00.555504 Set Vref, RX VrefLevel [Byte0]: 53
7961 23:50:00.558327 [Byte1]: 53
7962 23:50:00.562745
7963 23:50:00.563254 Set Vref, RX VrefLevel [Byte0]: 54
7964 23:50:00.566134 [Byte1]: 54
7965 23:50:00.570270
7966 23:50:00.570758 Set Vref, RX VrefLevel [Byte0]: 55
7967 23:50:00.573734 [Byte1]: 55
7968 23:50:00.578101
7969 23:50:00.578540 Set Vref, RX VrefLevel [Byte0]: 56
7970 23:50:00.581263 [Byte1]: 56
7971 23:50:00.585845
7972 23:50:00.586381 Set Vref, RX VrefLevel [Byte0]: 57
7973 23:50:00.589198 [Byte1]: 57
7974 23:50:00.593019
7975 23:50:00.593455 Set Vref, RX VrefLevel [Byte0]: 58
7976 23:50:00.596678 [Byte1]: 58
7977 23:50:00.600679
7978 23:50:00.601113 Set Vref, RX VrefLevel [Byte0]: 59
7979 23:50:00.604376 [Byte1]: 59
7980 23:50:00.608330
7981 23:50:00.608797 Set Vref, RX VrefLevel [Byte0]: 60
7982 23:50:00.611927 [Byte1]: 60
7983 23:50:00.615925
7984 23:50:00.616369 Set Vref, RX VrefLevel [Byte0]: 61
7985 23:50:00.619638 [Byte1]: 61
7986 23:50:00.623934
7987 23:50:00.624494 Set Vref, RX VrefLevel [Byte0]: 62
7988 23:50:00.627131 [Byte1]: 62
7989 23:50:00.631491
7990 23:50:00.631929 Set Vref, RX VrefLevel [Byte0]: 63
7991 23:50:00.634977 [Byte1]: 63
7992 23:50:00.639070
7993 23:50:00.639690 Set Vref, RX VrefLevel [Byte0]: 64
7994 23:50:00.642008 [Byte1]: 64
7995 23:50:00.646678
7996 23:50:00.647216 Set Vref, RX VrefLevel [Byte0]: 65
7997 23:50:00.649931 [Byte1]: 65
7998 23:50:00.654030
7999 23:50:00.654497 Set Vref, RX VrefLevel [Byte0]: 66
8000 23:50:00.657483 [Byte1]: 66
8001 23:50:00.661974
8002 23:50:00.662409 Set Vref, RX VrefLevel [Byte0]: 67
8003 23:50:00.664815 [Byte1]: 67
8004 23:50:00.669310
8005 23:50:00.669785 Set Vref, RX VrefLevel [Byte0]: 68
8006 23:50:00.672725 [Byte1]: 68
8007 23:50:00.677459
8008 23:50:00.677880 Set Vref, RX VrefLevel [Byte0]: 69
8009 23:50:00.680487 [Byte1]: 69
8010 23:50:00.684662
8011 23:50:00.685082 Set Vref, RX VrefLevel [Byte0]: 70
8012 23:50:00.688233 [Byte1]: 70
8013 23:50:00.692476
8014 23:50:00.693062 Set Vref, RX VrefLevel [Byte0]: 71
8015 23:50:00.695509 [Byte1]: 71
8016 23:50:00.699608
8017 23:50:00.700191 Set Vref, RX VrefLevel [Byte0]: 72
8018 23:50:00.703553 [Byte1]: 72
8019 23:50:00.707342
8020 23:50:00.707764 Set Vref, RX VrefLevel [Byte0]: 73
8021 23:50:00.711031 [Byte1]: 73
8022 23:50:00.714912
8023 23:50:00.715379 Set Vref, RX VrefLevel [Byte0]: 74
8024 23:50:00.718400 [Byte1]: 74
8025 23:50:00.722483
8026 23:50:00.723039 Set Vref, RX VrefLevel [Byte0]: 75
8027 23:50:00.725911 [Byte1]: 75
8028 23:50:00.730415
8029 23:50:00.730882 Set Vref, RX VrefLevel [Byte0]: 76
8030 23:50:00.733402 [Byte1]: 76
8031 23:50:00.738113
8032 23:50:00.738694 Set Vref, RX VrefLevel [Byte0]: 77
8033 23:50:00.741583 [Byte1]: 77
8034 23:50:00.745425
8035 23:50:00.745890 Final RX Vref Byte 0 = 63 to rank0
8036 23:50:00.748628 Final RX Vref Byte 1 = 59 to rank0
8037 23:50:00.752083 Final RX Vref Byte 0 = 63 to rank1
8038 23:50:00.755455 Final RX Vref Byte 1 = 59 to rank1==
8039 23:50:00.758515 Dram Type= 6, Freq= 0, CH_0, rank 0
8040 23:50:00.765662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 23:50:00.766240 ==
8042 23:50:00.766841 DQS Delay:
8043 23:50:00.768848 DQS0 = 0, DQS1 = 0
8044 23:50:00.769334 DQM Delay:
8045 23:50:00.769818 DQM0 = 126, DQM1 = 119
8046 23:50:00.771885 DQ Delay:
8047 23:50:00.775327 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8048 23:50:00.778809 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
8049 23:50:00.781902 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8050 23:50:00.785204 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8051 23:50:00.785689
8052 23:50:00.786177
8053 23:50:00.786632
8054 23:50:00.788507 [DramC_TX_OE_Calibration] TA2
8055 23:50:00.791864 Original DQ_B0 (3 6) =30, OEN = 27
8056 23:50:00.795206 Original DQ_B1 (3 6) =30, OEN = 27
8057 23:50:00.798452 24, 0x0, End_B0=24 End_B1=24
8058 23:50:00.799048 25, 0x0, End_B0=25 End_B1=25
8059 23:50:00.801584 26, 0x0, End_B0=26 End_B1=26
8060 23:50:00.805112 27, 0x0, End_B0=27 End_B1=27
8061 23:50:00.808781 28, 0x0, End_B0=28 End_B1=28
8062 23:50:00.811657 29, 0x0, End_B0=29 End_B1=29
8063 23:50:00.812192 30, 0x0, End_B0=30 End_B1=30
8064 23:50:00.814890 31, 0x4141, End_B0=30 End_B1=30
8065 23:50:00.818239 Byte0 end_step=30 best_step=27
8066 23:50:00.821698 Byte1 end_step=30 best_step=27
8067 23:50:00.824852 Byte0 TX OE(2T, 0.5T) = (3, 3)
8068 23:50:00.828168 Byte1 TX OE(2T, 0.5T) = (3, 3)
8069 23:50:00.828865
8070 23:50:00.829310
8071 23:50:00.834789 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8072 23:50:00.838152 CH0 RK0: MR19=303, MR18=1111
8073 23:50:00.844817 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8074 23:50:00.845414
8075 23:50:00.847549 ----->DramcWriteLeveling(PI) begin...
8076 23:50:00.848031 ==
8077 23:50:00.850909 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 23:50:00.854708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 23:50:00.855244 ==
8080 23:50:00.857678 Write leveling (Byte 0): 32 => 32
8081 23:50:00.861034 Write leveling (Byte 1): 27 => 27
8082 23:50:00.864462 DramcWriteLeveling(PI) end<-----
8083 23:50:00.864996
8084 23:50:00.865409 ==
8085 23:50:00.867792 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 23:50:00.870945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 23:50:00.871496 ==
8088 23:50:00.874738 [Gating] SW mode calibration
8089 23:50:00.881269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8090 23:50:00.887912 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8091 23:50:00.891406 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 23:50:00.897798 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 23:50:00.901134 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 23:50:00.904133 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8095 23:50:00.910821 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8096 23:50:00.914026 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8097 23:50:00.917470 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 23:50:00.923760 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 23:50:00.927253 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 23:50:00.931227 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 23:50:00.937833 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8102 23:50:00.941332 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
8103 23:50:00.944081 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8104 23:50:00.950542 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8105 23:50:00.953938 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 23:50:00.957358 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 23:50:00.963774 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 23:50:00.966890 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 23:50:00.970180 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8110 23:50:00.976730 1 6 12 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
8111 23:50:00.980360 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8112 23:50:00.983552 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 23:50:00.990107 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 23:50:00.993513 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 23:50:00.997008 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 23:50:01.003310 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 23:50:01.006915 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 23:50:01.010260 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8119 23:50:01.013198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8120 23:50:01.020132 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8121 23:50:01.023808 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 23:50:01.027028 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 23:50:01.033164 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 23:50:01.036371 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 23:50:01.039967 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 23:50:01.046529 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 23:50:01.050080 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 23:50:01.053106 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 23:50:01.059990 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 23:50:01.063148 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 23:50:01.066384 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 23:50:01.073155 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 23:50:01.076041 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8134 23:50:01.079544 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8135 23:50:01.082823 Total UI for P1: 0, mck2ui 16
8136 23:50:01.086278 best dqsien dly found for B0: ( 1, 9, 8)
8137 23:50:01.093259 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8138 23:50:01.096643 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8139 23:50:01.099704 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 23:50:01.102819 Total UI for P1: 0, mck2ui 16
8141 23:50:01.106070 best dqsien dly found for B1: ( 1, 9, 18)
8142 23:50:01.110009 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8143 23:50:01.112789 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8144 23:50:01.113260
8145 23:50:01.119874 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8146 23:50:01.122650 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8147 23:50:01.126250 [Gating] SW calibration Done
8148 23:50:01.126842 ==
8149 23:50:01.129417 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 23:50:01.132760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 23:50:01.133263 ==
8152 23:50:01.133633 RX Vref Scan: 0
8153 23:50:01.133995
8154 23:50:01.136233 RX Vref 0 -> 0, step: 1
8155 23:50:01.136783
8156 23:50:01.139535 RX Delay 0 -> 252, step: 8
8157 23:50:01.143108 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8158 23:50:01.146052 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8159 23:50:01.149303 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8160 23:50:01.156033 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8161 23:50:01.159248 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8162 23:50:01.162243 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8163 23:50:01.166063 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8164 23:50:01.169000 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8165 23:50:01.175650 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8166 23:50:01.179101 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8167 23:50:01.182289 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8168 23:50:01.185926 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8169 23:50:01.192371 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8170 23:50:01.195897 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8171 23:50:01.198995 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8172 23:50:01.202324 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8173 23:50:01.202795 ==
8174 23:50:01.205601 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 23:50:01.212380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 23:50:01.212925 ==
8177 23:50:01.213325 DQS Delay:
8178 23:50:01.213674 DQS0 = 0, DQS1 = 0
8179 23:50:01.215479 DQM Delay:
8180 23:50:01.215942 DQM0 = 128, DQM1 = 121
8181 23:50:01.219412 DQ Delay:
8182 23:50:01.222212 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8183 23:50:01.225235 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8184 23:50:01.229108 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8185 23:50:01.231967 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8186 23:50:01.232434
8187 23:50:01.232823
8188 23:50:01.233161 ==
8189 23:50:01.235322 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 23:50:01.238791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 23:50:01.241836 ==
8192 23:50:01.242415
8193 23:50:01.242781
8194 23:50:01.243124 TX Vref Scan disable
8195 23:50:01.245108 == TX Byte 0 ==
8196 23:50:01.248476 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8197 23:50:01.251524 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8198 23:50:01.255344 == TX Byte 1 ==
8199 23:50:01.258744 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8200 23:50:01.261636 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8201 23:50:01.264897 ==
8202 23:50:01.265365 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 23:50:01.271644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 23:50:01.272140 ==
8205 23:50:01.285009
8206 23:50:01.288525 TX Vref early break, caculate TX vref
8207 23:50:01.292277 TX Vref=16, minBit 0, minWin=22, winSum=367
8208 23:50:01.295149 TX Vref=18, minBit 8, minWin=22, winSum=371
8209 23:50:01.298581 TX Vref=20, minBit 8, minWin=22, winSum=382
8210 23:50:01.301529 TX Vref=22, minBit 8, minWin=23, winSum=390
8211 23:50:01.305095 TX Vref=24, minBit 7, minWin=23, winSum=396
8212 23:50:01.311774 TX Vref=26, minBit 8, minWin=24, winSum=408
8213 23:50:01.315245 TX Vref=28, minBit 8, minWin=24, winSum=405
8214 23:50:01.318139 TX Vref=30, minBit 8, minWin=23, winSum=401
8215 23:50:01.321397 TX Vref=32, minBit 8, minWin=23, winSum=397
8216 23:50:01.324973 TX Vref=34, minBit 8, minWin=22, winSum=389
8217 23:50:01.331395 TX Vref=36, minBit 8, minWin=22, winSum=375
8218 23:50:01.334750 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 26
8219 23:50:01.335236
8220 23:50:01.338507 Final TX Range 0 Vref 26
8221 23:50:01.339112
8222 23:50:01.339610 ==
8223 23:50:01.341473 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 23:50:01.344923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 23:50:01.345505 ==
8226 23:50:01.347725
8227 23:50:01.348205
8228 23:50:01.348791 TX Vref Scan disable
8229 23:50:01.354441 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8230 23:50:01.354910 == TX Byte 0 ==
8231 23:50:01.358123 u2DelayCellOfst[0]=18 cells (5 PI)
8232 23:50:01.361415 u2DelayCellOfst[1]=22 cells (6 PI)
8233 23:50:01.364298 u2DelayCellOfst[2]=15 cells (4 PI)
8234 23:50:01.367636 u2DelayCellOfst[3]=15 cells (4 PI)
8235 23:50:01.371161 u2DelayCellOfst[4]=11 cells (3 PI)
8236 23:50:01.374520 u2DelayCellOfst[5]=0 cells (0 PI)
8237 23:50:01.377477 u2DelayCellOfst[6]=22 cells (6 PI)
8238 23:50:01.380763 u2DelayCellOfst[7]=22 cells (6 PI)
8239 23:50:01.384297 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8240 23:50:01.387783 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8241 23:50:01.391606 == TX Byte 1 ==
8242 23:50:01.394507 u2DelayCellOfst[8]=0 cells (0 PI)
8243 23:50:01.397441 u2DelayCellOfst[9]=3 cells (1 PI)
8244 23:50:01.400499 u2DelayCellOfst[10]=7 cells (2 PI)
8245 23:50:01.403990 u2DelayCellOfst[11]=7 cells (2 PI)
8246 23:50:01.407430 u2DelayCellOfst[12]=15 cells (4 PI)
8247 23:50:01.410579 u2DelayCellOfst[13]=15 cells (4 PI)
8248 23:50:01.414167 u2DelayCellOfst[14]=15 cells (4 PI)
8249 23:50:01.414606 u2DelayCellOfst[15]=11 cells (3 PI)
8250 23:50:01.420651 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8251 23:50:01.423828 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8252 23:50:01.427481 DramC Write-DBI on
8253 23:50:01.427915 ==
8254 23:50:01.430270 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 23:50:01.433797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 23:50:01.434240 ==
8257 23:50:01.434613
8258 23:50:01.434962
8259 23:50:01.437230 TX Vref Scan disable
8260 23:50:01.437725 == TX Byte 0 ==
8261 23:50:01.443901 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8262 23:50:01.444351 == TX Byte 1 ==
8263 23:50:01.447006 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8264 23:50:01.450415 DramC Write-DBI off
8265 23:50:01.450839
8266 23:50:01.451164 [DATLAT]
8267 23:50:01.453720 Freq=1600, CH0 RK1
8268 23:50:01.454141
8269 23:50:01.454473 DATLAT Default: 0xf
8270 23:50:01.457085 0, 0xFFFF, sum = 0
8271 23:50:01.457513 1, 0xFFFF, sum = 0
8272 23:50:01.460702 2, 0xFFFF, sum = 0
8273 23:50:01.461125 3, 0xFFFF, sum = 0
8274 23:50:01.463625 4, 0xFFFF, sum = 0
8275 23:50:01.466844 5, 0xFFFF, sum = 0
8276 23:50:01.467304 6, 0xFFFF, sum = 0
8277 23:50:01.470257 7, 0xFFFF, sum = 0
8278 23:50:01.470682 8, 0xFFFF, sum = 0
8279 23:50:01.473852 9, 0xFFFF, sum = 0
8280 23:50:01.474275 10, 0xFFFF, sum = 0
8281 23:50:01.477225 11, 0xFFFF, sum = 0
8282 23:50:01.477649 12, 0xFFFF, sum = 0
8283 23:50:01.480730 13, 0xCFFF, sum = 0
8284 23:50:01.481181 14, 0x0, sum = 1
8285 23:50:01.483552 15, 0x0, sum = 2
8286 23:50:01.483973 16, 0x0, sum = 3
8287 23:50:01.487106 17, 0x0, sum = 4
8288 23:50:01.487526 best_step = 15
8289 23:50:01.487855
8290 23:50:01.488160 ==
8291 23:50:01.490534 Dram Type= 6, Freq= 0, CH_0, rank 1
8292 23:50:01.493396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 23:50:01.493817 ==
8294 23:50:01.497044 RX Vref Scan: 0
8295 23:50:01.497455
8296 23:50:01.500402 RX Vref 0 -> 0, step: 1
8297 23:50:01.500862
8298 23:50:01.501191 RX Delay 3 -> 252, step: 4
8299 23:50:01.507343 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8300 23:50:01.510928 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8301 23:50:01.514235 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8302 23:50:01.517407 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8303 23:50:01.520632 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8304 23:50:01.527614 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8305 23:50:01.530710 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8306 23:50:01.533961 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8307 23:50:01.537587 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8308 23:50:01.540216 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8309 23:50:01.547552 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8310 23:50:01.550536 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8311 23:50:01.553479 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8312 23:50:01.557192 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8313 23:50:01.563410 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8314 23:50:01.566667 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8315 23:50:01.566750 ==
8316 23:50:01.570371 Dram Type= 6, Freq= 0, CH_0, rank 1
8317 23:50:01.573915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 23:50:01.573996 ==
8319 23:50:01.576574 DQS Delay:
8320 23:50:01.576661 DQS0 = 0, DQS1 = 0
8321 23:50:01.576730 DQM Delay:
8322 23:50:01.580295 DQM0 = 124, DQM1 = 117
8323 23:50:01.580389 DQ Delay:
8324 23:50:01.583833 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =120
8325 23:50:01.586522 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8326 23:50:01.589996 DQ8 =108, DQ9 =104, DQ10 =118, DQ11 =112
8327 23:50:01.596561 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8328 23:50:01.596675
8329 23:50:01.596739
8330 23:50:01.596798
8331 23:50:01.600268 [DramC_TX_OE_Calibration] TA2
8332 23:50:01.600348 Original DQ_B0 (3 6) =30, OEN = 27
8333 23:50:01.603002 Original DQ_B1 (3 6) =30, OEN = 27
8334 23:50:01.606603 24, 0x0, End_B0=24 End_B1=24
8335 23:50:01.609987 25, 0x0, End_B0=25 End_B1=25
8336 23:50:01.612921 26, 0x0, End_B0=26 End_B1=26
8337 23:50:01.616430 27, 0x0, End_B0=27 End_B1=27
8338 23:50:01.616512 28, 0x0, End_B0=28 End_B1=28
8339 23:50:01.619797 29, 0x0, End_B0=29 End_B1=29
8340 23:50:01.622665 30, 0x0, End_B0=30 End_B1=30
8341 23:50:01.626769 31, 0x4141, End_B0=30 End_B1=30
8342 23:50:01.629971 Byte0 end_step=30 best_step=27
8343 23:50:01.630052 Byte1 end_step=30 best_step=27
8344 23:50:01.632871 Byte0 TX OE(2T, 0.5T) = (3, 3)
8345 23:50:01.636353 Byte1 TX OE(2T, 0.5T) = (3, 3)
8346 23:50:01.636433
8347 23:50:01.636497
8348 23:50:01.646397 [DQSOSCAuto] RK1, (LSB)MR18= 0x2513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8349 23:50:01.646481 CH0 RK1: MR19=303, MR18=2513
8350 23:50:01.652862 CH0_RK1: MR19=0x303, MR18=0x2513, DQSOSC=391, MR23=63, INC=24, DEC=16
8351 23:50:01.656610 [RxdqsGatingPostProcess] freq 1600
8352 23:50:01.663140 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8353 23:50:01.666357 best DQS0 dly(2T, 0.5T) = (1, 1)
8354 23:50:01.669449 best DQS1 dly(2T, 0.5T) = (1, 1)
8355 23:50:01.672673 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8356 23:50:01.675962 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8357 23:50:01.676043 best DQS0 dly(2T, 0.5T) = (1, 1)
8358 23:50:01.679372 best DQS1 dly(2T, 0.5T) = (1, 1)
8359 23:50:01.682586 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8360 23:50:01.685998 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8361 23:50:01.689539 Pre-setting of DQS Precalculation
8362 23:50:01.696143 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8363 23:50:01.696224 ==
8364 23:50:01.699313 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 23:50:01.702513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 23:50:01.702594 ==
8367 23:50:01.709485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8368 23:50:01.712817 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8369 23:50:01.715782 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8370 23:50:01.722542 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8371 23:50:01.731646 [CA 0] Center 42 (13~71) winsize 59
8372 23:50:01.734638 [CA 1] Center 42 (12~72) winsize 61
8373 23:50:01.737884 [CA 2] Center 37 (9~66) winsize 58
8374 23:50:01.741769 [CA 3] Center 36 (7~66) winsize 60
8375 23:50:01.744917 [CA 4] Center 37 (8~67) winsize 60
8376 23:50:01.747830 [CA 5] Center 36 (7~66) winsize 60
8377 23:50:01.747910
8378 23:50:01.751430 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8379 23:50:01.751510
8380 23:50:01.754797 [CATrainingPosCal] consider 1 rank data
8381 23:50:01.757965 u2DelayCellTimex100 = 258/100 ps
8382 23:50:01.764448 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8383 23:50:01.767684 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8384 23:50:01.770786 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8385 23:50:01.774352 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8386 23:50:01.777684 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8387 23:50:01.781140 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8388 23:50:01.781219
8389 23:50:01.784085 CA PerBit enable=1, Macro0, CA PI delay=36
8390 23:50:01.784165
8391 23:50:01.787310 [CBTSetCACLKResult] CA Dly = 36
8392 23:50:01.790587 CS Dly: 9 (0~40)
8393 23:50:01.793911 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8394 23:50:01.797554 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8395 23:50:01.797634 ==
8396 23:50:01.800935 Dram Type= 6, Freq= 0, CH_1, rank 1
8397 23:50:01.807587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 23:50:01.807669 ==
8399 23:50:01.810632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8400 23:50:01.813926 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8401 23:50:01.820757 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8402 23:50:01.827111 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8403 23:50:01.834494 [CA 0] Center 42 (13~72) winsize 60
8404 23:50:01.837799 [CA 1] Center 42 (12~72) winsize 61
8405 23:50:01.841351 [CA 2] Center 38 (9~67) winsize 59
8406 23:50:01.844925 [CA 3] Center 36 (7~66) winsize 60
8407 23:50:01.847602 [CA 4] Center 38 (8~68) winsize 61
8408 23:50:01.851311 [CA 5] Center 36 (7~66) winsize 60
8409 23:50:01.851391
8410 23:50:01.854499 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8411 23:50:01.854579
8412 23:50:01.858103 [CATrainingPosCal] consider 2 rank data
8413 23:50:01.860828 u2DelayCellTimex100 = 258/100 ps
8414 23:50:01.864218 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8415 23:50:01.871037 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8416 23:50:01.874551 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8417 23:50:01.877957 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8418 23:50:01.881424 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8419 23:50:01.884942 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8420 23:50:01.885022
8421 23:50:01.887706 CA PerBit enable=1, Macro0, CA PI delay=36
8422 23:50:01.887787
8423 23:50:01.891001 [CBTSetCACLKResult] CA Dly = 36
8424 23:50:01.894317 CS Dly: 10 (0~43)
8425 23:50:01.897946 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8426 23:50:01.901131 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8427 23:50:01.901211
8428 23:50:01.904342 ----->DramcWriteLeveling(PI) begin...
8429 23:50:01.904424 ==
8430 23:50:01.907964 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 23:50:01.913847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 23:50:01.913928 ==
8433 23:50:01.917340 Write leveling (Byte 0): 25 => 25
8434 23:50:01.917421 Write leveling (Byte 1): 29 => 29
8435 23:50:01.920669 DramcWriteLeveling(PI) end<-----
8436 23:50:01.920772
8437 23:50:01.920837 ==
8438 23:50:01.924249 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 23:50:01.930453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 23:50:01.930533 ==
8441 23:50:01.934413 [Gating] SW mode calibration
8442 23:50:01.940389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8443 23:50:01.943993 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8444 23:50:01.950911 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 23:50:01.954023 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 23:50:01.957405 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 23:50:01.964226 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8448 23:50:01.967037 1 4 16 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
8449 23:50:01.970555 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 23:50:01.976868 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 23:50:01.980487 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 23:50:01.983767 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 23:50:01.990323 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 23:50:01.993838 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 23:50:01.996920 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8456 23:50:02.003678 1 5 16 | B1->B0 | 2929 2c2c | 0 1 | (0 0) (0 1)
8457 23:50:02.006961 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8458 23:50:02.010029 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 23:50:02.016913 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 23:50:02.020364 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 23:50:02.023355 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 23:50:02.030088 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 23:50:02.033124 1 6 12 | B1->B0 | 3535 3030 | 0 0 | (0 0) (0 0)
8464 23:50:02.036851 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 23:50:02.039720 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 23:50:02.046355 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 23:50:02.049831 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 23:50:02.053474 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 23:50:02.059742 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 23:50:02.062933 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 23:50:02.066521 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 23:50:02.072828 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8473 23:50:02.076452 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 23:50:02.079805 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 23:50:02.086185 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 23:50:02.089713 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 23:50:02.093057 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 23:50:02.099505 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 23:50:02.102960 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 23:50:02.106148 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 23:50:02.112758 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 23:50:02.116161 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 23:50:02.119898 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 23:50:02.126152 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 23:50:02.129418 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 23:50:02.132995 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 23:50:02.139347 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8488 23:50:02.142847 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8489 23:50:02.145838 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 23:50:02.149155 Total UI for P1: 0, mck2ui 16
8491 23:50:02.152779 best dqsien dly found for B0: ( 1, 9, 16)
8492 23:50:02.155967 Total UI for P1: 0, mck2ui 16
8493 23:50:02.159527 best dqsien dly found for B1: ( 1, 9, 14)
8494 23:50:02.162672 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8495 23:50:02.166007 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8496 23:50:02.166471
8497 23:50:02.172628 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8498 23:50:02.175843 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8499 23:50:02.179310 [Gating] SW calibration Done
8500 23:50:02.179863 ==
8501 23:50:02.182748 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 23:50:02.185927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 23:50:02.186396 ==
8504 23:50:02.186762 RX Vref Scan: 0
8505 23:50:02.189403
8506 23:50:02.189864 RX Vref 0 -> 0, step: 1
8507 23:50:02.190229
8508 23:50:02.192724 RX Delay 0 -> 252, step: 8
8509 23:50:02.195655 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8510 23:50:02.199302 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8511 23:50:02.205692 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8512 23:50:02.209565 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8513 23:50:02.212176 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8514 23:50:02.215716 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8515 23:50:02.219180 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8516 23:50:02.225799 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8517 23:50:02.228774 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8518 23:50:02.232480 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8519 23:50:02.236109 iDelay=208, Bit 10, Center 127 (80 ~ 175) 96
8520 23:50:02.239270 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8521 23:50:02.245423 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8522 23:50:02.248590 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8523 23:50:02.252271 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8524 23:50:02.255215 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8525 23:50:02.255666 ==
8526 23:50:02.258371 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 23:50:02.265124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 23:50:02.265571 ==
8529 23:50:02.265932 DQS Delay:
8530 23:50:02.268905 DQS0 = 0, DQS1 = 0
8531 23:50:02.269363 DQM Delay:
8532 23:50:02.269726 DQM0 = 133, DQM1 = 126
8533 23:50:02.272180 DQ Delay:
8534 23:50:02.275372 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8535 23:50:02.278542 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8536 23:50:02.281987 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8537 23:50:02.285166 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8538 23:50:02.285629
8539 23:50:02.285959
8540 23:50:02.286266 ==
8541 23:50:02.288438 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 23:50:02.295168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 23:50:02.295763 ==
8544 23:50:02.296111
8545 23:50:02.296419
8546 23:50:02.296737 TX Vref Scan disable
8547 23:50:02.297949 == TX Byte 0 ==
8548 23:50:02.301371 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8549 23:50:02.308411 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8550 23:50:02.308856 == TX Byte 1 ==
8551 23:50:02.311593 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8552 23:50:02.318206 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8553 23:50:02.318644 ==
8554 23:50:02.321254 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 23:50:02.324779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 23:50:02.325197 ==
8557 23:50:02.336814
8558 23:50:02.340325 TX Vref early break, caculate TX vref
8559 23:50:02.343766 TX Vref=16, minBit 8, minWin=21, winSum=360
8560 23:50:02.346968 TX Vref=18, minBit 8, minWin=21, winSum=367
8561 23:50:02.350345 TX Vref=20, minBit 8, minWin=22, winSum=376
8562 23:50:02.353302 TX Vref=22, minBit 8, minWin=23, winSum=389
8563 23:50:02.356844 TX Vref=24, minBit 11, minWin=23, winSum=398
8564 23:50:02.363792 TX Vref=26, minBit 15, minWin=24, winSum=408
8565 23:50:02.367079 TX Vref=28, minBit 1, minWin=25, winSum=418
8566 23:50:02.370078 TX Vref=30, minBit 1, minWin=25, winSum=417
8567 23:50:02.373671 TX Vref=32, minBit 8, minWin=23, winSum=404
8568 23:50:02.376965 TX Vref=34, minBit 1, minWin=23, winSum=393
8569 23:50:02.383144 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8570 23:50:02.383575
8571 23:50:02.386839 Final TX Range 0 Vref 28
8572 23:50:02.387260
8573 23:50:02.387585 ==
8574 23:50:02.389877 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 23:50:02.393086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 23:50:02.393505 ==
8577 23:50:02.393851
8578 23:50:02.394156
8579 23:50:02.396650 TX Vref Scan disable
8580 23:50:02.402887 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8581 23:50:02.403304 == TX Byte 0 ==
8582 23:50:02.406187 u2DelayCellOfst[0]=18 cells (5 PI)
8583 23:50:02.409611 u2DelayCellOfst[1]=15 cells (4 PI)
8584 23:50:02.412741 u2DelayCellOfst[2]=0 cells (0 PI)
8585 23:50:02.416017 u2DelayCellOfst[3]=7 cells (2 PI)
8586 23:50:02.419176 u2DelayCellOfst[4]=7 cells (2 PI)
8587 23:50:02.422847 u2DelayCellOfst[5]=22 cells (6 PI)
8588 23:50:02.426380 u2DelayCellOfst[6]=18 cells (5 PI)
8589 23:50:02.429398 u2DelayCellOfst[7]=7 cells (2 PI)
8590 23:50:02.432781 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8591 23:50:02.436035 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8592 23:50:02.439622 == TX Byte 1 ==
8593 23:50:02.442458 u2DelayCellOfst[8]=0 cells (0 PI)
8594 23:50:02.446111 u2DelayCellOfst[9]=11 cells (3 PI)
8595 23:50:02.449592 u2DelayCellOfst[10]=15 cells (4 PI)
8596 23:50:02.450009 u2DelayCellOfst[11]=11 cells (3 PI)
8597 23:50:02.452830 u2DelayCellOfst[12]=18 cells (5 PI)
8598 23:50:02.456013 u2DelayCellOfst[13]=22 cells (6 PI)
8599 23:50:02.459061 u2DelayCellOfst[14]=22 cells (6 PI)
8600 23:50:02.462256 u2DelayCellOfst[15]=22 cells (6 PI)
8601 23:50:02.469347 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8602 23:50:02.472078 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8603 23:50:02.472533 DramC Write-DBI on
8604 23:50:02.475877 ==
8605 23:50:02.478958 Dram Type= 6, Freq= 0, CH_1, rank 0
8606 23:50:02.482212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8607 23:50:02.482630 ==
8608 23:50:02.482958
8609 23:50:02.483261
8610 23:50:02.485726 TX Vref Scan disable
8611 23:50:02.486141 == TX Byte 0 ==
8612 23:50:02.492026 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8613 23:50:02.492444 == TX Byte 1 ==
8614 23:50:02.495961 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8615 23:50:02.498574 DramC Write-DBI off
8616 23:50:02.498991
8617 23:50:02.499323 [DATLAT]
8618 23:50:02.502086 Freq=1600, CH1 RK0
8619 23:50:02.502504
8620 23:50:02.502830 DATLAT Default: 0xf
8621 23:50:02.505551 0, 0xFFFF, sum = 0
8622 23:50:02.505973 1, 0xFFFF, sum = 0
8623 23:50:02.508660 2, 0xFFFF, sum = 0
8624 23:50:02.509081 3, 0xFFFF, sum = 0
8625 23:50:02.511908 4, 0xFFFF, sum = 0
8626 23:50:02.512474 5, 0xFFFF, sum = 0
8627 23:50:02.515355 6, 0xFFFF, sum = 0
8628 23:50:02.518494 7, 0xFFFF, sum = 0
8629 23:50:02.518919 8, 0xFFFF, sum = 0
8630 23:50:02.521907 9, 0xFFFF, sum = 0
8631 23:50:02.522547 10, 0xFFFF, sum = 0
8632 23:50:02.524965 11, 0xFFFF, sum = 0
8633 23:50:02.525493 12, 0xFFFF, sum = 0
8634 23:50:02.528535 13, 0x8FFF, sum = 0
8635 23:50:02.528957 14, 0x0, sum = 1
8636 23:50:02.531645 15, 0x0, sum = 2
8637 23:50:02.532067 16, 0x0, sum = 3
8638 23:50:02.534875 17, 0x0, sum = 4
8639 23:50:02.535398 best_step = 15
8640 23:50:02.535761
8641 23:50:02.536093 ==
8642 23:50:02.538686 Dram Type= 6, Freq= 0, CH_1, rank 0
8643 23:50:02.541572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8644 23:50:02.545151 ==
8645 23:50:02.545702 RX Vref Scan: 1
8646 23:50:02.546121
8647 23:50:02.548396 Set Vref Range= 24 -> 127
8648 23:50:02.548855
8649 23:50:02.551156 RX Vref 24 -> 127, step: 1
8650 23:50:02.551573
8651 23:50:02.551898 RX Delay 11 -> 252, step: 4
8652 23:50:02.552205
8653 23:50:02.555000 Set Vref, RX VrefLevel [Byte0]: 24
8654 23:50:02.558122 [Byte1]: 24
8655 23:50:02.561719
8656 23:50:02.562176 Set Vref, RX VrefLevel [Byte0]: 25
8657 23:50:02.565197 [Byte1]: 25
8658 23:50:02.569418
8659 23:50:02.569833 Set Vref, RX VrefLevel [Byte0]: 26
8660 23:50:02.572678 [Byte1]: 26
8661 23:50:02.577202
8662 23:50:02.577615 Set Vref, RX VrefLevel [Byte0]: 27
8663 23:50:02.580195 [Byte1]: 27
8664 23:50:02.585066
8665 23:50:02.585480 Set Vref, RX VrefLevel [Byte0]: 28
8666 23:50:02.587715 [Byte1]: 28
8667 23:50:02.592063
8668 23:50:02.592474 Set Vref, RX VrefLevel [Byte0]: 29
8669 23:50:02.595521 [Byte1]: 29
8670 23:50:02.599924
8671 23:50:02.600338 Set Vref, RX VrefLevel [Byte0]: 30
8672 23:50:02.603358 [Byte1]: 30
8673 23:50:02.607393
8674 23:50:02.607814 Set Vref, RX VrefLevel [Byte0]: 31
8675 23:50:02.610854 [Byte1]: 31
8676 23:50:02.615099
8677 23:50:02.615515 Set Vref, RX VrefLevel [Byte0]: 32
8678 23:50:02.618335 [Byte1]: 32
8679 23:50:02.622934
8680 23:50:02.623346 Set Vref, RX VrefLevel [Byte0]: 33
8681 23:50:02.626335 [Byte1]: 33
8682 23:50:02.630251
8683 23:50:02.630676 Set Vref, RX VrefLevel [Byte0]: 34
8684 23:50:02.633611 [Byte1]: 34
8685 23:50:02.638301
8686 23:50:02.638715 Set Vref, RX VrefLevel [Byte0]: 35
8687 23:50:02.641087 [Byte1]: 35
8688 23:50:02.645681
8689 23:50:02.646271 Set Vref, RX VrefLevel [Byte0]: 36
8690 23:50:02.648782 [Byte1]: 36
8691 23:50:02.653398
8692 23:50:02.653814 Set Vref, RX VrefLevel [Byte0]: 37
8693 23:50:02.656697 [Byte1]: 37
8694 23:50:02.660728
8695 23:50:02.661160 Set Vref, RX VrefLevel [Byte0]: 38
8696 23:50:02.663856 [Byte1]: 38
8697 23:50:02.668589
8698 23:50:02.669059 Set Vref, RX VrefLevel [Byte0]: 39
8699 23:50:02.671622 [Byte1]: 39
8700 23:50:02.675838
8701 23:50:02.676249 Set Vref, RX VrefLevel [Byte0]: 40
8702 23:50:02.679145 [Byte1]: 40
8703 23:50:02.683978
8704 23:50:02.684395 Set Vref, RX VrefLevel [Byte0]: 41
8705 23:50:02.686682 [Byte1]: 41
8706 23:50:02.691274
8707 23:50:02.691945 Set Vref, RX VrefLevel [Byte0]: 42
8708 23:50:02.694535 [Byte1]: 42
8709 23:50:02.699067
8710 23:50:02.699483 Set Vref, RX VrefLevel [Byte0]: 43
8711 23:50:02.702264 [Byte1]: 43
8712 23:50:02.706225
8713 23:50:02.706638 Set Vref, RX VrefLevel [Byte0]: 44
8714 23:50:02.709989 [Byte1]: 44
8715 23:50:02.713951
8716 23:50:02.714362 Set Vref, RX VrefLevel [Byte0]: 45
8717 23:50:02.717330 [Byte1]: 45
8718 23:50:02.722309
8719 23:50:02.722724 Set Vref, RX VrefLevel [Byte0]: 46
8720 23:50:02.725309 [Byte1]: 46
8721 23:50:02.729192
8722 23:50:02.729606 Set Vref, RX VrefLevel [Byte0]: 47
8723 23:50:02.732699 [Byte1]: 47
8724 23:50:02.736753
8725 23:50:02.737167 Set Vref, RX VrefLevel [Byte0]: 48
8726 23:50:02.740508 [Byte1]: 48
8727 23:50:02.744723
8728 23:50:02.745314 Set Vref, RX VrefLevel [Byte0]: 49
8729 23:50:02.748099 [Byte1]: 49
8730 23:50:02.752486
8731 23:50:02.753009 Set Vref, RX VrefLevel [Byte0]: 50
8732 23:50:02.755696 [Byte1]: 50
8733 23:50:02.760033
8734 23:50:02.760493 Set Vref, RX VrefLevel [Byte0]: 51
8735 23:50:02.763034 [Byte1]: 51
8736 23:50:02.767560
8737 23:50:02.768241 Set Vref, RX VrefLevel [Byte0]: 52
8738 23:50:02.771171 [Byte1]: 52
8739 23:50:02.774917
8740 23:50:02.775373 Set Vref, RX VrefLevel [Byte0]: 53
8741 23:50:02.778280 [Byte1]: 53
8742 23:50:02.782583
8743 23:50:02.783039 Set Vref, RX VrefLevel [Byte0]: 54
8744 23:50:02.786075 [Byte1]: 54
8745 23:50:02.790019
8746 23:50:02.790488 Set Vref, RX VrefLevel [Byte0]: 55
8747 23:50:02.793541 [Byte1]: 55
8748 23:50:02.798127
8749 23:50:02.798585 Set Vref, RX VrefLevel [Byte0]: 56
8750 23:50:02.801042 [Byte1]: 56
8751 23:50:02.805500
8752 23:50:02.805974 Set Vref, RX VrefLevel [Byte0]: 57
8753 23:50:02.809113 [Byte1]: 57
8754 23:50:02.813321
8755 23:50:02.813776 Set Vref, RX VrefLevel [Byte0]: 58
8756 23:50:02.816332 [Byte1]: 58
8757 23:50:02.820517
8758 23:50:02.820975 Set Vref, RX VrefLevel [Byte0]: 59
8759 23:50:02.823823 [Byte1]: 59
8760 23:50:02.828232
8761 23:50:02.828704 Set Vref, RX VrefLevel [Byte0]: 60
8762 23:50:02.831560 [Byte1]: 60
8763 23:50:02.835804
8764 23:50:02.836220 Set Vref, RX VrefLevel [Byte0]: 61
8765 23:50:02.839316 [Byte1]: 61
8766 23:50:02.843608
8767 23:50:02.844067 Set Vref, RX VrefLevel [Byte0]: 62
8768 23:50:02.846801 [Byte1]: 62
8769 23:50:02.851179
8770 23:50:02.851635 Set Vref, RX VrefLevel [Byte0]: 63
8771 23:50:02.854888 [Byte1]: 63
8772 23:50:02.858592
8773 23:50:02.859053 Set Vref, RX VrefLevel [Byte0]: 64
8774 23:50:02.861901 [Byte1]: 64
8775 23:50:02.866304
8776 23:50:02.866760 Set Vref, RX VrefLevel [Byte0]: 65
8777 23:50:02.869916 [Byte1]: 65
8778 23:50:02.873731
8779 23:50:02.874205 Set Vref, RX VrefLevel [Byte0]: 66
8780 23:50:02.877119 [Byte1]: 66
8781 23:50:02.881924
8782 23:50:02.882426 Set Vref, RX VrefLevel [Byte0]: 67
8783 23:50:02.885063 [Byte1]: 67
8784 23:50:02.889471
8785 23:50:02.889928 Set Vref, RX VrefLevel [Byte0]: 68
8786 23:50:02.892498 [Byte1]: 68
8787 23:50:02.897231
8788 23:50:02.897686 Set Vref, RX VrefLevel [Byte0]: 69
8789 23:50:02.899956 [Byte1]: 69
8790 23:50:02.904555
8791 23:50:02.905042 Set Vref, RX VrefLevel [Byte0]: 70
8792 23:50:02.907510 [Byte1]: 70
8793 23:50:02.912140
8794 23:50:02.912633 Final RX Vref Byte 0 = 55 to rank0
8795 23:50:02.915552 Final RX Vref Byte 1 = 57 to rank0
8796 23:50:02.918476 Final RX Vref Byte 0 = 55 to rank1
8797 23:50:02.922041 Final RX Vref Byte 1 = 57 to rank1==
8798 23:50:02.925117 Dram Type= 6, Freq= 0, CH_1, rank 0
8799 23:50:02.931813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 23:50:02.932273 ==
8801 23:50:02.932682 DQS Delay:
8802 23:50:02.933031 DQS0 = 0, DQS1 = 0
8803 23:50:02.935168 DQM Delay:
8804 23:50:02.935623 DQM0 = 131, DQM1 = 123
8805 23:50:02.938475 DQ Delay:
8806 23:50:02.941891 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8807 23:50:02.945022 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8808 23:50:02.948671 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8809 23:50:02.951862 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8810 23:50:02.952275
8811 23:50:02.952645
8812 23:50:02.953014
8813 23:50:02.955157 [DramC_TX_OE_Calibration] TA2
8814 23:50:02.958460 Original DQ_B0 (3 6) =30, OEN = 27
8815 23:50:02.961881 Original DQ_B1 (3 6) =30, OEN = 27
8816 23:50:02.965086 24, 0x0, End_B0=24 End_B1=24
8817 23:50:02.965509 25, 0x0, End_B0=25 End_B1=25
8818 23:50:02.968460 26, 0x0, End_B0=26 End_B1=26
8819 23:50:02.971535 27, 0x0, End_B0=27 End_B1=27
8820 23:50:02.974978 28, 0x0, End_B0=28 End_B1=28
8821 23:50:02.978809 29, 0x0, End_B0=29 End_B1=29
8822 23:50:02.979234 30, 0x0, End_B0=30 End_B1=30
8823 23:50:02.981928 31, 0x4141, End_B0=30 End_B1=30
8824 23:50:02.985079 Byte0 end_step=30 best_step=27
8825 23:50:02.988317 Byte1 end_step=30 best_step=27
8826 23:50:02.991508 Byte0 TX OE(2T, 0.5T) = (3, 3)
8827 23:50:02.994926 Byte1 TX OE(2T, 0.5T) = (3, 3)
8828 23:50:02.995345
8829 23:50:02.995673
8830 23:50:03.001569 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8831 23:50:03.004525 CH1 RK0: MR19=303, MR18=B0F
8832 23:50:03.011693 CH1_RK0: MR19=0x303, MR18=0xB0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8833 23:50:03.012195
8834 23:50:03.014546 ----->DramcWriteLeveling(PI) begin...
8835 23:50:03.015010 ==
8836 23:50:03.018077 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 23:50:03.021608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 23:50:03.022028 ==
8839 23:50:03.024405 Write leveling (Byte 0): 23 => 23
8840 23:50:03.027887 Write leveling (Byte 1): 28 => 28
8841 23:50:03.031653 DramcWriteLeveling(PI) end<-----
8842 23:50:03.032185
8843 23:50:03.032519 ==
8844 23:50:03.034777 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 23:50:03.037957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 23:50:03.038493 ==
8847 23:50:03.041298 [Gating] SW mode calibration
8848 23:50:03.048246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8849 23:50:03.054355 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8850 23:50:03.058167 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 23:50:03.061341 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 23:50:03.067929 1 4 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8853 23:50:03.070773 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8854 23:50:03.074735 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 23:50:03.081100 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 23:50:03.084535 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 23:50:03.088000 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 23:50:03.094306 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 23:50:03.097781 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 23:50:03.101213 1 5 8 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
8861 23:50:03.107797 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8862 23:50:03.111251 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 23:50:03.113940 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 23:50:03.120532 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 23:50:03.124422 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 23:50:03.128128 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 23:50:03.134217 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8868 23:50:03.137427 1 6 8 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
8869 23:50:03.140736 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8870 23:50:03.147347 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 23:50:03.150880 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 23:50:03.154176 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 23:50:03.160700 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 23:50:03.164472 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 23:50:03.167459 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 23:50:03.174176 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8877 23:50:03.177133 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8878 23:50:03.180626 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8879 23:50:03.187561 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 23:50:03.190615 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 23:50:03.193846 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 23:50:03.200419 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 23:50:03.203594 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 23:50:03.207042 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 23:50:03.213560 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 23:50:03.216901 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 23:50:03.220592 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 23:50:03.223605 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 23:50:03.230680 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 23:50:03.233286 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 23:50:03.236698 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 23:50:03.243437 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8893 23:50:03.247017 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8894 23:50:03.250278 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 23:50:03.253495 Total UI for P1: 0, mck2ui 16
8896 23:50:03.256716 best dqsien dly found for B0: ( 1, 9, 10)
8897 23:50:03.260246 Total UI for P1: 0, mck2ui 16
8898 23:50:03.263825 best dqsien dly found for B1: ( 1, 9, 12)
8899 23:50:03.267015 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8900 23:50:03.269889 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8901 23:50:03.273144
8902 23:50:03.276861 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8903 23:50:03.279818 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8904 23:50:03.283332 [Gating] SW calibration Done
8905 23:50:03.283793 ==
8906 23:50:03.286468 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 23:50:03.290264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 23:50:03.290752 ==
8909 23:50:03.293408 RX Vref Scan: 0
8910 23:50:03.293866
8911 23:50:03.294226 RX Vref 0 -> 0, step: 1
8912 23:50:03.294568
8913 23:50:03.296671 RX Delay 0 -> 252, step: 8
8914 23:50:03.299961 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8915 23:50:03.303737 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8916 23:50:03.309979 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8917 23:50:03.313430 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8918 23:50:03.316398 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8919 23:50:03.319969 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8920 23:50:03.323232 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8921 23:50:03.330048 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8922 23:50:03.333173 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8923 23:50:03.336410 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8924 23:50:03.339753 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8925 23:50:03.343126 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8926 23:50:03.350045 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8927 23:50:03.352843 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8928 23:50:03.356305 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8929 23:50:03.359502 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8930 23:50:03.360022 ==
8931 23:50:03.363019 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 23:50:03.369822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 23:50:03.370361 ==
8934 23:50:03.370952 DQS Delay:
8935 23:50:03.373090 DQS0 = 0, DQS1 = 0
8936 23:50:03.373547 DQM Delay:
8937 23:50:03.375982 DQM0 = 129, DQM1 = 128
8938 23:50:03.376555 DQ Delay:
8939 23:50:03.379388 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8940 23:50:03.382872 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8941 23:50:03.386491 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8942 23:50:03.389264 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8943 23:50:03.389733
8944 23:50:03.390106
8945 23:50:03.390457 ==
8946 23:50:03.393042 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 23:50:03.399040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 23:50:03.399523 ==
8949 23:50:03.399904
8950 23:50:03.400239
8951 23:50:03.400623 TX Vref Scan disable
8952 23:50:03.402874 == TX Byte 0 ==
8953 23:50:03.406140 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8954 23:50:03.409343 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8955 23:50:03.412877 == TX Byte 1 ==
8956 23:50:03.416245 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8957 23:50:03.419377 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8958 23:50:03.422341 ==
8959 23:50:03.426112 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 23:50:03.428973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 23:50:03.429546 ==
8962 23:50:03.443247
8963 23:50:03.446892 TX Vref early break, caculate TX vref
8964 23:50:03.449484 TX Vref=16, minBit 0, minWin=22, winSum=380
8965 23:50:03.452862 TX Vref=18, minBit 0, minWin=23, winSum=387
8966 23:50:03.456275 TX Vref=20, minBit 0, minWin=23, winSum=395
8967 23:50:03.459634 TX Vref=22, minBit 0, minWin=24, winSum=403
8968 23:50:03.462674 TX Vref=24, minBit 0, minWin=24, winSum=413
8969 23:50:03.469331 TX Vref=26, minBit 0, minWin=25, winSum=420
8970 23:50:03.472660 TX Vref=28, minBit 0, minWin=25, winSum=419
8971 23:50:03.475782 TX Vref=30, minBit 0, minWin=25, winSum=415
8972 23:50:03.479157 TX Vref=32, minBit 0, minWin=24, winSum=410
8973 23:50:03.482621 TX Vref=34, minBit 5, minWin=22, winSum=399
8974 23:50:03.486183 TX Vref=36, minBit 0, minWin=23, winSum=391
8975 23:50:03.492528 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8976 23:50:03.493032
8977 23:50:03.496177 Final TX Range 0 Vref 26
8978 23:50:03.496775
8979 23:50:03.497148 ==
8980 23:50:03.499881 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 23:50:03.502572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 23:50:03.503144 ==
8983 23:50:03.503530
8984 23:50:03.506066
8985 23:50:03.506540 TX Vref Scan disable
8986 23:50:03.512715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8987 23:50:03.513278 == TX Byte 0 ==
8988 23:50:03.515654 u2DelayCellOfst[0]=18 cells (5 PI)
8989 23:50:03.519328 u2DelayCellOfst[1]=11 cells (3 PI)
8990 23:50:03.522455 u2DelayCellOfst[2]=0 cells (0 PI)
8991 23:50:03.525891 u2DelayCellOfst[3]=3 cells (1 PI)
8992 23:50:03.528970 u2DelayCellOfst[4]=7 cells (2 PI)
8993 23:50:07.033885 u2DelayCellOfst[5]=18 cells (5 PI)
8994 23:50:07.034363 u2DelayCellOfst[6]=15 cells (4 PI)
8995 23:50:07.034693 u2DelayCellOfst[7]=3 cells (1 PI)
8996 23:50:07.034996 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8997 23:50:07.035294 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8998 23:50:07.035583 == TX Byte 1 ==
8999 23:50:07.035868 u2DelayCellOfst[8]=0 cells (0 PI)
9000 23:50:07.036146 u2DelayCellOfst[9]=7 cells (2 PI)
9001 23:50:07.036422 u2DelayCellOfst[10]=15 cells (4 PI)
9002 23:50:07.036730 u2DelayCellOfst[11]=7 cells (2 PI)
9003 23:50:07.037007 u2DelayCellOfst[12]=18 cells (5 PI)
9004 23:50:07.037280 u2DelayCellOfst[13]=18 cells (5 PI)
9005 23:50:07.037553 u2DelayCellOfst[14]=22 cells (6 PI)
9006 23:50:07.037822 u2DelayCellOfst[15]=18 cells (5 PI)
9007 23:50:07.038091 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9008 23:50:07.038361 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9009 23:50:07.038629 DramC Write-DBI on
9010 23:50:07.038901 ==
9011 23:50:07.039171 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 23:50:07.039445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 23:50:07.039673 ==
9014 23:50:07.039726
9015 23:50:07.039777
9016 23:50:07.039829 TX Vref Scan disable
9017 23:50:07.039881 == TX Byte 0 ==
9018 23:50:07.039933 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9019 23:50:07.039985 == TX Byte 1 ==
9020 23:50:07.040037 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9021 23:50:07.040089 DramC Write-DBI off
9022 23:50:07.040142
9023 23:50:07.040193 [DATLAT]
9024 23:50:07.040245 Freq=1600, CH1 RK1
9025 23:50:07.040297
9026 23:50:07.040348 DATLAT Default: 0xf
9027 23:50:07.040400 0, 0xFFFF, sum = 0
9028 23:50:07.040454 1, 0xFFFF, sum = 0
9029 23:50:07.040508 2, 0xFFFF, sum = 0
9030 23:50:07.040563 3, 0xFFFF, sum = 0
9031 23:50:07.040649 4, 0xFFFF, sum = 0
9032 23:50:07.040702 5, 0xFFFF, sum = 0
9033 23:50:07.040755 6, 0xFFFF, sum = 0
9034 23:50:07.040807 7, 0xFFFF, sum = 0
9035 23:50:07.040860 8, 0xFFFF, sum = 0
9036 23:50:07.040913 9, 0xFFFF, sum = 0
9037 23:50:07.040966 10, 0xFFFF, sum = 0
9038 23:50:07.041018 11, 0xFFFF, sum = 0
9039 23:50:07.041071 12, 0xFFFF, sum = 0
9040 23:50:07.041124 13, 0x8FFF, sum = 0
9041 23:50:07.041176 14, 0x0, sum = 1
9042 23:50:07.041229 15, 0x0, sum = 2
9043 23:50:07.041282 16, 0x0, sum = 3
9044 23:50:07.041334 17, 0x0, sum = 4
9045 23:50:07.041386 best_step = 15
9046 23:50:07.041438
9047 23:50:07.041489 ==
9048 23:50:07.041540 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 23:50:07.041592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 23:50:07.041645 ==
9051 23:50:07.041697 RX Vref Scan: 0
9052 23:50:07.041749
9053 23:50:07.041800 RX Vref 0 -> 0, step: 1
9054 23:50:07.041852
9055 23:50:07.041903 RX Delay 3 -> 252, step: 4
9056 23:50:07.041955 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9057 23:50:07.042006 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9058 23:50:07.042058 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9059 23:50:07.042110 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9060 23:50:07.042161 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9061 23:50:07.042212 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9062 23:50:07.042263 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9063 23:50:07.042315 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
9064 23:50:07.042367 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9065 23:50:07.042418 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9066 23:50:07.042469 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9067 23:50:07.042521 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9068 23:50:07.042572 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
9069 23:50:07.042624 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9070 23:50:07.042675 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9071 23:50:07.042727 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9072 23:50:07.042778 ==
9073 23:50:07.042830 Dram Type= 6, Freq= 0, CH_1, rank 1
9074 23:50:07.042882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9075 23:50:07.042934 ==
9076 23:50:07.042985 DQS Delay:
9077 23:50:07.043036 DQS0 = 0, DQS1 = 0
9078 23:50:07.043088 DQM Delay:
9079 23:50:07.043140 DQM0 = 127, DQM1 = 125
9080 23:50:07.043191 DQ Delay:
9081 23:50:07.043243 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =124
9082 23:50:07.043295 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9083 23:50:07.043346 DQ8 =108, DQ9 =112, DQ10 =130, DQ11 =118
9084 23:50:07.043398 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =134
9085 23:50:07.043449
9086 23:50:07.043500
9087 23:50:07.043551
9088 23:50:07.043602 [DramC_TX_OE_Calibration] TA2
9089 23:50:07.043654 Original DQ_B0 (3 6) =30, OEN = 27
9090 23:50:07.043706 Original DQ_B1 (3 6) =30, OEN = 27
9091 23:50:07.043757 24, 0x0, End_B0=24 End_B1=24
9092 23:50:07.043810 25, 0x0, End_B0=25 End_B1=25
9093 23:50:07.043863 26, 0x0, End_B0=26 End_B1=26
9094 23:50:07.043915 27, 0x0, End_B0=27 End_B1=27
9095 23:50:07.043968 28, 0x0, End_B0=28 End_B1=28
9096 23:50:07.044020 29, 0x0, End_B0=29 End_B1=29
9097 23:50:07.044072 30, 0x0, End_B0=30 End_B1=30
9098 23:50:07.044125 31, 0x4141, End_B0=30 End_B1=30
9099 23:50:07.044178 Byte0 end_step=30 best_step=27
9100 23:50:07.044229 Byte1 end_step=30 best_step=27
9101 23:50:07.044281 Byte0 TX OE(2T, 0.5T) = (3, 3)
9102 23:50:07.044333 Byte1 TX OE(2T, 0.5T) = (3, 3)
9103 23:50:07.044385
9104 23:50:07.044436
9105 23:50:07.044487 [DQSOSCAuto] RK1, (LSB)MR18= 0xe19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
9106 23:50:07.044541 CH1 RK1: MR19=303, MR18=E19
9107 23:50:07.044599 CH1_RK1: MR19=0x303, MR18=0xE19, DQSOSC=397, MR23=63, INC=23, DEC=15
9108 23:50:07.044653 [RxdqsGatingPostProcess] freq 1600
9109 23:50:07.044705 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9110 23:50:07.044757 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 23:50:07.044810 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 23:50:07.044862 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 23:50:07.044914 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 23:50:07.044966 best DQS0 dly(2T, 0.5T) = (1, 1)
9115 23:50:07.045018 best DQS1 dly(2T, 0.5T) = (1, 1)
9116 23:50:07.045070 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9117 23:50:07.045122 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9118 23:50:07.045174 Pre-setting of DQS Precalculation
9119 23:50:07.045226 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9120 23:50:07.045279 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9121 23:50:07.045332 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 23:50:07.045385
9123 23:50:07.045437
9124 23:50:07.045488 [Calibration Summary] 3200 Mbps
9125 23:50:07.045541 CH 0, Rank 0
9126 23:50:07.045592 SW Impedance : PASS
9127 23:50:07.045645 DUTY Scan : NO K
9128 23:50:07.045698 ZQ Calibration : PASS
9129 23:50:07.045750 Jitter Meter : NO K
9130 23:50:07.045802 CBT Training : PASS
9131 23:50:07.045854 Write leveling : PASS
9132 23:50:07.046106 RX DQS gating : PASS
9133 23:50:07.046165 RX DQ/DQS(RDDQC) : PASS
9134 23:50:07.046219 TX DQ/DQS : PASS
9135 23:50:07.046273 RX DATLAT : PASS
9136 23:50:07.046325 RX DQ/DQS(Engine): PASS
9137 23:50:07.046377 TX OE : PASS
9138 23:50:07.046430 All Pass.
9139 23:50:07.046482
9140 23:50:07.046558 CH 0, Rank 1
9141 23:50:07.046612 SW Impedance : PASS
9142 23:50:07.046665 DUTY Scan : NO K
9143 23:50:07.046719 ZQ Calibration : PASS
9144 23:50:07.046772 Jitter Meter : NO K
9145 23:50:07.046826 CBT Training : PASS
9146 23:50:07.046879 Write leveling : PASS
9147 23:50:07.046932 RX DQS gating : PASS
9148 23:50:07.046986 RX DQ/DQS(RDDQC) : PASS
9149 23:50:07.047039 TX DQ/DQS : PASS
9150 23:50:07.047093 RX DATLAT : PASS
9151 23:50:07.047146 RX DQ/DQS(Engine): PASS
9152 23:50:07.047199 TX OE : PASS
9153 23:50:07.047252 All Pass.
9154 23:50:07.047306
9155 23:50:07.047359 CH 1, Rank 0
9156 23:50:07.047412 SW Impedance : PASS
9157 23:50:07.047465 DUTY Scan : NO K
9158 23:50:07.047519 ZQ Calibration : PASS
9159 23:50:07.047572 Jitter Meter : NO K
9160 23:50:07.047625 CBT Training : PASS
9161 23:50:07.047678 Write leveling : PASS
9162 23:50:07.047731 RX DQS gating : PASS
9163 23:50:07.047785 RX DQ/DQS(RDDQC) : PASS
9164 23:50:07.047838 TX DQ/DQS : PASS
9165 23:50:07.047891 RX DATLAT : PASS
9166 23:50:07.047944 RX DQ/DQS(Engine): PASS
9167 23:50:07.047997 TX OE : PASS
9168 23:50:07.048050 All Pass.
9169 23:50:07.048104
9170 23:50:07.048157 CH 1, Rank 1
9171 23:50:07.048210 SW Impedance : PASS
9172 23:50:07.048263 DUTY Scan : NO K
9173 23:50:07.048316 ZQ Calibration : PASS
9174 23:50:07.048369 Jitter Meter : NO K
9175 23:50:07.048422 CBT Training : PASS
9176 23:50:07.048475 Write leveling : PASS
9177 23:50:07.048528 RX DQS gating : PASS
9178 23:50:07.048587 RX DQ/DQS(RDDQC) : PASS
9179 23:50:07.048642 TX DQ/DQS : PASS
9180 23:50:07.048695 RX DATLAT : PASS
9181 23:50:07.048749 RX DQ/DQS(Engine): PASS
9182 23:50:07.048802 TX OE : PASS
9183 23:50:07.048856 All Pass.
9184 23:50:07.048909
9185 23:50:07.048962 DramC Write-DBI on
9186 23:50:07.049015 PER_BANK_REFRESH: Hybrid Mode
9187 23:50:07.049068 TX_TRACKING: ON
9188 23:50:07.049122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9189 23:50:07.049178 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9190 23:50:07.049232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9191 23:50:07.049286 [FAST_K] Save calibration result to emmc
9192 23:50:07.049340 sync common calibartion params.
9193 23:50:07.049394 sync cbt_mode0:1, 1:1
9194 23:50:07.049447 dram_init: ddr_geometry: 2
9195 23:50:07.049501 dram_init: ddr_geometry: 2
9196 23:50:07.049554 dram_init: ddr_geometry: 2
9197 23:50:07.049608 0:dram_rank_size:100000000
9198 23:50:07.049663 1:dram_rank_size:100000000
9199 23:50:07.049718 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9200 23:50:07.049773 DFS_SHUFFLE_HW_MODE: ON
9201 23:50:07.049826 dramc_set_vcore_voltage set vcore to 725000
9202 23:50:07.049879 Read voltage for 1600, 0
9203 23:50:07.049932 Vio18 = 0
9204 23:50:07.049986 Vcore = 725000
9205 23:50:07.050039 Vdram = 0
9206 23:50:07.050092 Vddq = 0
9207 23:50:07.050145 Vmddr = 0
9208 23:50:07.050198 switch to 3200 Mbps bootup
9209 23:50:07.050251 [DramcRunTimeConfig]
9210 23:50:07.050304 PHYPLL
9211 23:50:07.050358 DPM_CONTROL_AFTERK: ON
9212 23:50:07.050411 PER_BANK_REFRESH: ON
9213 23:50:07.050464 REFRESH_OVERHEAD_REDUCTION: ON
9214 23:50:07.050517 CMD_PICG_NEW_MODE: OFF
9215 23:50:07.050570 XRTWTW_NEW_MODE: ON
9216 23:50:07.050623 XRTRTR_NEW_MODE: ON
9217 23:50:07.050676 TX_TRACKING: ON
9218 23:50:07.050729 RDSEL_TRACKING: OFF
9219 23:50:07.050783 DQS Precalculation for DVFS: ON
9220 23:50:07.050836 RX_TRACKING: OFF
9221 23:50:07.050889 HW_GATING DBG: ON
9222 23:50:07.050942 ZQCS_ENABLE_LP4: ON
9223 23:50:07.050996 RX_PICG_NEW_MODE: ON
9224 23:50:07.051049 TX_PICG_NEW_MODE: ON
9225 23:50:07.051102 ENABLE_RX_DCM_DPHY: ON
9226 23:50:07.051155 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9227 23:50:07.051209 DUMMY_READ_FOR_TRACKING: OFF
9228 23:50:07.051262 !!! SPM_CONTROL_AFTERK: OFF
9229 23:50:07.051322 !!! SPM could not control APHY
9230 23:50:07.051376 IMPEDANCE_TRACKING: ON
9231 23:50:07.051430 TEMP_SENSOR: ON
9232 23:50:07.051483 HW_SAVE_FOR_SR: OFF
9233 23:50:07.051536 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9234 23:50:07.051589 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9235 23:50:07.051642 Read ODT Tracking: ON
9236 23:50:07.051695 Refresh Rate DeBounce: ON
9237 23:50:07.051748 DFS_NO_QUEUE_FLUSH: ON
9238 23:50:07.051801 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9239 23:50:07.051855 ENABLE_DFS_RUNTIME_MRW: OFF
9240 23:50:07.051908 DDR_RESERVE_NEW_MODE: ON
9241 23:50:07.051961 MR_CBT_SWITCH_FREQ: ON
9242 23:50:07.052013 =========================
9243 23:50:07.052066 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9244 23:50:07.052120 dram_init: ddr_geometry: 2
9245 23:50:07.052173 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9246 23:50:07.052227 dram_init: dram init end (result: 0)
9247 23:50:07.052281 DRAM-K: Full calibration passed in 24616 msecs
9248 23:50:07.052335 MRC: failed to locate region type 0.
9249 23:50:07.052388 DRAM rank0 size:0x100000000,
9250 23:50:07.052441 DRAM rank1 size=0x100000000
9251 23:50:07.052494 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9252 23:50:07.052548 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9253 23:50:07.052607 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9254 23:50:07.052661 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9255 23:50:07.052715 DRAM rank0 size:0x100000000,
9256 23:50:07.052768 DRAM rank1 size=0x100000000
9257 23:50:07.052822 CBMEM:
9258 23:50:07.052875 IMD: root @ 0xfffff000 254 entries.
9259 23:50:07.052929 IMD: root @ 0xffffec00 62 entries.
9260 23:50:07.052982 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9261 23:50:07.053036 WARNING: RO_VPD is uninitialized or empty.
9262 23:50:07.053090 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9263 23:50:07.053143 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9264 23:50:07.053197 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9265 23:50:07.053251 BS: romstage times (exec / console): total (unknown) / 24069 ms
9266 23:50:07.053305
9267 23:50:07.053357
9268 23:50:07.053604 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9269 23:50:07.053666 ARM64: Exception handlers installed.
9270 23:50:07.053721 ARM64: Testing exception
9271 23:50:07.053776 ARM64: Done test exception
9272 23:50:07.053830 Enumerating buses...
9273 23:50:07.053884 Show all devs... Before device enumeration.
9274 23:50:07.053938 Root Device: enabled 1
9275 23:50:07.053992 CPU_CLUSTER: 0: enabled 1
9276 23:50:07.054045 CPU: 00: enabled 1
9277 23:50:07.054099 Compare with tree...
9278 23:50:07.054152 Root Device: enabled 1
9279 23:50:07.054204 CPU_CLUSTER: 0: enabled 1
9280 23:50:07.054258 CPU: 00: enabled 1
9281 23:50:07.054311 Root Device scanning...
9282 23:50:07.054364 scan_static_bus for Root Device
9283 23:50:07.054418 CPU_CLUSTER: 0 enabled
9284 23:50:07.054472 scan_static_bus for Root Device done
9285 23:50:07.054526 scan_bus: bus Root Device finished in 8 msecs
9286 23:50:07.054579 done
9287 23:50:07.054633 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9288 23:50:07.054688 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9289 23:50:07.054742 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9290 23:50:07.054796 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9291 23:50:07.054850 Allocating resources...
9292 23:50:07.054903 Reading resources...
9293 23:50:07.054956 Root Device read_resources bus 0 link: 0
9294 23:50:07.055010 DRAM rank0 size:0x100000000,
9295 23:50:07.055064 DRAM rank1 size=0x100000000
9296 23:50:07.055117 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9297 23:50:07.055174 CPU: 00 missing read_resources
9298 23:50:07.055227 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9299 23:50:07.055281 Root Device read_resources bus 0 link: 0 done
9300 23:50:07.055334 Done reading resources.
9301 23:50:07.055388 Show resources in subtree (Root Device)...After reading.
9302 23:50:07.055441 Root Device child on link 0 CPU_CLUSTER: 0
9303 23:50:07.055495 CPU_CLUSTER: 0 child on link 0 CPU: 00
9304 23:50:07.055549 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9305 23:50:07.055602 CPU: 00
9306 23:50:07.055656 Root Device assign_resources, bus 0 link: 0
9307 23:50:07.055709 CPU_CLUSTER: 0 missing set_resources
9308 23:50:07.055763 Root Device assign_resources, bus 0 link: 0 done
9309 23:50:07.055816 Done setting resources.
9310 23:50:07.055869 Show resources in subtree (Root Device)...After assigning values.
9311 23:50:07.055923 Root Device child on link 0 CPU_CLUSTER: 0
9312 23:50:07.055977 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 23:50:07.056030 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 23:50:07.056084 CPU: 00
9315 23:50:07.056138 Done allocating resources.
9316 23:50:07.056192 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9317 23:50:07.056245 Enabling resources...
9318 23:50:07.056299 done.
9319 23:50:07.056352 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9320 23:50:07.056406 Initializing devices...
9321 23:50:07.056459 Root Device init
9322 23:50:07.056512 init hardware done!
9323 23:50:07.056571 0x00000018: ctrlr->caps
9324 23:50:07.056627 52.000 MHz: ctrlr->f_max
9325 23:50:07.056682 0.400 MHz: ctrlr->f_min
9326 23:50:07.056738 0x40ff8080: ctrlr->voltages
9327 23:50:07.056794 sclk: 390625
9328 23:50:07.056848 Bus Width = 1
9329 23:50:07.056901 sclk: 390625
9330 23:50:07.056954 Bus Width = 1
9331 23:50:07.057007 Early init status = 3
9332 23:50:07.057061 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9333 23:50:07.057115 in-header: 03 fc 00 00 01 00 00 00
9334 23:50:07.057169 in-data: 00
9335 23:50:07.057222 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9336 23:50:07.057276 in-header: 03 fd 00 00 00 00 00 00
9337 23:50:07.057330 in-data:
9338 23:50:07.057383 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9339 23:50:07.057437 in-header: 03 fc 00 00 01 00 00 00
9340 23:50:07.057490 in-data: 00
9341 23:50:07.057543 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9342 23:50:07.057596 in-header: 03 fd 00 00 00 00 00 00
9343 23:50:07.057650 in-data:
9344 23:50:07.057703 [SSUSB] Setting up USB HOST controller...
9345 23:50:07.057756 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9346 23:50:07.057810 [SSUSB] phy power-on done.
9347 23:50:07.057863 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9348 23:50:07.057918 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9349 23:50:07.057972 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9350 23:50:07.058026 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9351 23:50:07.058079 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9352 23:50:07.058133 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9353 23:50:07.058187 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9354 23:50:07.058241 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9355 23:50:07.058295 SPM: binary array size = 0x9dc
9356 23:50:07.058349 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9357 23:50:07.058403 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9358 23:50:07.058456 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9359 23:50:07.058511 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9360 23:50:07.058565 configure_display: Starting display init
9361 23:50:07.058617 anx7625_power_on_init: Init interface.
9362 23:50:07.058670 anx7625_disable_pd_protocol: Disabled PD feature.
9363 23:50:07.058722 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9364 23:50:07.058776 anx7625_start_dp_work: Secure OCM version=00
9365 23:50:07.058828 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9366 23:50:07.058881 sp_tx_get_edid_block: EDID Block = 1
9367 23:50:07.058934 Extracted contents:
9368 23:50:07.058987 header: 00 ff ff ff ff ff ff 00
9369 23:50:07.059041 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9370 23:50:07.059094 version: 01 04
9371 23:50:07.059149 basic params: 95 1f 11 78 0a
9372 23:50:07.059202 chroma info: 76 90 94 55 54 90 27 21 50 54
9373 23:50:07.059451 established: 00 00 00
9374 23:50:07.059515 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9375 23:50:07.059571 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9376 23:50:07.059625 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 23:50:07.059679 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9378 23:50:07.059733 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9379 23:50:07.059787 extensions: 00
9380 23:50:07.059841 checksum: fb
9381 23:50:07.059894
9382 23:50:07.059948 Manufacturer: IVO Model 57d Serial Number 0
9383 23:50:07.060001 Made week 0 of 2020
9384 23:50:07.060054 EDID version: 1.4
9385 23:50:07.060108 Digital display
9386 23:50:07.060161 6 bits per primary color channel
9387 23:50:07.060216 DisplayPort interface
9388 23:50:07.060269 Maximum image size: 31 cm x 17 cm
9389 23:50:07.060323 Gamma: 220%
9390 23:50:07.060376 Check DPMS levels
9391 23:50:07.060429 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9392 23:50:07.060482 First detailed timing is preferred timing
9393 23:50:07.060536 Established timings supported:
9394 23:50:07.060606 Standard timings supported:
9395 23:50:07.060660 Detailed timings
9396 23:50:07.060716 Hex of detail: 383680a07038204018303c0035ae10000019
9397 23:50:07.060771 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9398 23:50:07.060825 0780 0798 07c8 0820 hborder 0
9399 23:50:07.060879 0438 043b 0447 0458 vborder 0
9400 23:50:07.060932 -hsync -vsync
9401 23:50:07.060985 Did detailed timing
9402 23:50:07.061039 Hex of detail: 000000000000000000000000000000000000
9403 23:50:07.061093 Manufacturer-specified data, tag 0
9404 23:50:07.061145 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9405 23:50:07.061198 ASCII string: InfoVision
9406 23:50:07.061252 Hex of detail: 000000fe00523134304e574635205248200a
9407 23:50:07.061305 ASCII string: R140NWF5 RH
9408 23:50:07.061359 Checksum
9409 23:50:07.061412 Checksum: 0xfb (valid)
9410 23:50:07.061465 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9411 23:50:07.061518 DSI data_rate: 832800000 bps
9412 23:50:07.061572 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9413 23:50:07.061625 anx7625_parse_edid: pixelclock(138800).
9414 23:50:07.061679 hactive(1920), hsync(48), hfp(24), hbp(88)
9415 23:50:07.061732 vactive(1080), vsync(12), vfp(3), vbp(17)
9416 23:50:07.061785 anx7625_dsi_config: config dsi.
9417 23:50:07.061837 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9418 23:50:07.061891 anx7625_dsi_config: success to config DSI
9419 23:50:07.061944 anx7625_dp_start: MIPI phy setup OK.
9420 23:50:07.061997 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9421 23:50:07.062050 mtk_ddp_mode_set invalid vrefresh 60
9422 23:50:07.062103 main_disp_path_setup
9423 23:50:07.062156 ovl_layer_smi_id_en
9424 23:50:07.062210 ovl_layer_smi_id_en
9425 23:50:07.062263 ccorr_config
9426 23:50:07.062316 aal_config
9427 23:50:07.062369 gamma_config
9428 23:50:07.062422 postmask_config
9429 23:50:07.062474 dither_config
9430 23:50:07.062527 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9431 23:50:07.062580 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9432 23:50:07.062634 Root Device init finished in 554 msecs
9433 23:50:07.062687 CPU_CLUSTER: 0 init
9434 23:50:07.062740 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9435 23:50:07.062795 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9436 23:50:07.062849 APU_MBOX 0x190000b0 = 0x10001
9437 23:50:07.062903 APU_MBOX 0x190001b0 = 0x10001
9438 23:50:07.062956 APU_MBOX 0x190005b0 = 0x10001
9439 23:50:07.063010 APU_MBOX 0x190006b0 = 0x10001
9440 23:50:07.063062 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9441 23:50:07.063116 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9442 23:50:07.063170 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9443 23:50:07.063224 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9444 23:50:07.063278 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9445 23:50:07.063331 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9446 23:50:07.063385 CPU_CLUSTER: 0 init finished in 81 msecs
9447 23:50:07.063438 Devices initialized
9448 23:50:07.063491 Show all devs... After init.
9449 23:50:07.063544 Root Device: enabled 1
9450 23:50:07.063597 CPU_CLUSTER: 0: enabled 1
9451 23:50:07.063652 CPU: 00: enabled 1
9452 23:50:07.063706 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9453 23:50:07.063760 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9454 23:50:07.063814 ELOG: NV offset 0x57f000 size 0x1000
9455 23:50:07.063867 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9456 23:50:07.063920 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9457 23:50:07.063973 ELOG: Event(17) added with size 13 at 2024-05-29 23:50:05 UTC
9458 23:50:07.064027 out: cmd=0x121: 03 db 21 01 00 00 00 00
9459 23:50:07.064081 in-header: 03 2a 00 00 2c 00 00 00
9460 23:50:07.064134 in-data: 34 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9461 23:50:07.064199 ELOG: Event(A1) added with size 10 at 2024-05-29 23:50:05 UTC
9462 23:50:07.064257 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9463 23:50:07.064311 ELOG: Event(A0) added with size 9 at 2024-05-29 23:50:05 UTC
9464 23:50:07.064365 elog_add_boot_reason: Logged dev mode boot
9465 23:50:07.064418 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9466 23:50:07.064472 Finalize devices...
9467 23:50:07.064525 Devices finalized
9468 23:50:07.064590 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9469 23:50:07.064645 Writing coreboot table at 0xffe64000
9470 23:50:07.064893 0. 000000000010a000-0000000000113fff: RAMSTAGE
9471 23:50:07.064953 1. 0000000040000000-00000000400fffff: RAM
9472 23:50:07.065008 2. 0000000040100000-000000004032afff: RAMSTAGE
9473 23:50:07.065062 3. 000000004032b000-00000000545fffff: RAM
9474 23:50:07.065116 4. 0000000054600000-000000005465ffff: BL31
9475 23:50:07.065169 5. 0000000054660000-00000000ffe63fff: RAM
9476 23:50:07.065223 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9477 23:50:07.065276 7. 0000000100000000-000000023fffffff: RAM
9478 23:50:07.065330 Passing 5 GPIOs to payload:
9479 23:50:07.065384 NAME | PORT | POLARITY | VALUE
9480 23:50:07.065437 EC in RW | 0x000000aa | low | undefined
9481 23:50:07.065491 EC interrupt | 0x00000005 | low | undefined
9482 23:50:07.065544 TPM interrupt | 0x000000ab | high | undefined
9483 23:50:07.065597 SD card detect | 0x00000011 | high | undefined
9484 23:50:07.065651 speaker enable | 0x00000093 | high | undefined
9485 23:50:07.065704 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9486 23:50:07.065758 in-header: 03 f9 00 00 02 00 00 00
9487 23:50:07.065810 in-data: 02 00
9488 23:50:07.065863 ADC[4]: Raw value=892601 ID=7
9489 23:50:07.065917 ADC[3]: Raw value=212700 ID=1
9490 23:50:07.065970 RAM Code: 0x71
9491 23:50:07.066023 ADC[6]: Raw value=74722 ID=0
9492 23:50:07.066076 ADC[5]: Raw value=211960 ID=1
9493 23:50:07.066128 SKU Code: 0x1
9494 23:50:07.066182 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f5e
9495 23:50:07.066235 coreboot table: 964 bytes.
9496 23:50:07.066288 IMD ROOT 0. 0xfffff000 0x00001000
9497 23:50:07.066342 IMD SMALL 1. 0xffffe000 0x00001000
9498 23:50:07.066395 RO MCACHE 2. 0xffffc000 0x00001104
9499 23:50:07.066449 CONSOLE 3. 0xfff7c000 0x00080000
9500 23:50:07.066502 FMAP 4. 0xfff7b000 0x00000452
9501 23:50:07.066556 TIME STAMP 5. 0xfff7a000 0x00000910
9502 23:50:07.066625 VBOOT WORK 6. 0xfff66000 0x00014000
9503 23:50:07.066677 RAMOOPS 7. 0xffe66000 0x00100000
9504 23:50:07.066729 COREBOOT 8. 0xffe64000 0x00002000
9505 23:50:07.066782 IMD small region:
9506 23:50:07.066834 IMD ROOT 0. 0xffffec00 0x00000400
9507 23:50:07.066886 VPD 1. 0xffffeb80 0x0000006c
9508 23:50:07.066938 MMC STATUS 2. 0xffffeb60 0x00000004
9509 23:50:07.066990 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9510 23:50:07.067042 Probing TPM: done!
9511 23:50:07.067094 Connected to device vid:did:rid of 1ae0:0028:00
9512 23:50:07.067147 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9513 23:50:07.067200 Initialized TPM device CR50 revision 0
9514 23:50:07.067252 Checking cr50 for pending updates
9515 23:50:07.067304 Reading cr50 TPM mode
9516 23:50:07.067356 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9517 23:50:07.067408 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9518 23:50:07.067461 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9519 23:50:07.067513 Checking segment from ROM address 0x40100000
9520 23:50:07.067565 Checking segment from ROM address 0x4010001c
9521 23:50:07.067617 Loading segment from ROM address 0x40100000
9522 23:50:07.067668 code (compression=0)
9523 23:50:07.067721 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9524 23:50:07.067773 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9525 23:50:07.067826 it's not compressed!
9526 23:50:07.067879 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9527 23:50:07.067932 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9528 23:50:07.067984 Loading segment from ROM address 0x4010001c
9529 23:50:07.068036 Entry Point 0x80000000
9530 23:50:07.068088 Loaded segments
9531 23:50:07.068140 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9532 23:50:07.068192 Jumping to boot code at 0x80000000(0xffe64000)
9533 23:50:07.068244 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9534 23:50:07.068297 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9535 23:50:07.068349 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9536 23:50:07.068401 Checking segment from ROM address 0x40100000
9537 23:50:07.068453 Checking segment from ROM address 0x4010001c
9538 23:50:07.068505 Loading segment from ROM address 0x40100000
9539 23:50:07.068564 code (compression=1)
9540 23:50:07.068648 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9541 23:50:07.068701 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9542 23:50:07.068753 using LZMA
9543 23:50:07.068805 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9544 23:50:07.068857 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9545 23:50:07.068909 Loading segment from ROM address 0x4010001c
9546 23:50:07.068961 Entry Point 0x54601000
9547 23:50:07.069013 Loaded segments
9548 23:50:07.069065 NOTICE: MT8192 bl31_setup
9549 23:50:07.069118 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9550 23:50:07.069171 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9551 23:50:07.069223 WARNING: region 0:
9552 23:50:07.069275 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 23:50:07.069327 WARNING: region 1:
9554 23:50:07.069379 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9555 23:50:07.069431 WARNING: region 2:
9556 23:50:07.069483 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9557 23:50:07.069536 WARNING: region 3:
9558 23:50:07.069588 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9559 23:50:07.069639 WARNING: region 4:
9560 23:50:07.069691 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9561 23:50:07.069744 WARNING: region 5:
9562 23:50:07.069796 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 23:50:07.070036 WARNING: region 6:
9564 23:50:07.070094 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9565 23:50:07.070148 WARNING: region 7:
9566 23:50:07.070200 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 23:50:07.070252 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9568 23:50:07.070305 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9569 23:50:07.070357 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9570 23:50:07.070408 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9571 23:50:07.070460 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9572 23:50:07.070513 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9573 23:50:07.070565 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9574 23:50:07.070618 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9575 23:50:07.070726 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9576 23:50:07.070781 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9577 23:50:07.070833 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9578 23:50:07.070886 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9579 23:50:07.070938 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9580 23:50:07.070990 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9581 23:50:07.071041 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9582 23:50:07.071093 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9583 23:50:07.071145 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9584 23:50:07.071198 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9585 23:50:07.071250 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9586 23:50:07.071301 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9587 23:50:07.071353 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9588 23:50:07.071405 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9589 23:50:07.071457 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9590 23:50:07.071509 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9591 23:50:07.071561 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9592 23:50:07.071612 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9593 23:50:07.071664 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9594 23:50:07.071716 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9595 23:50:07.071768 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9596 23:50:07.071820 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9597 23:50:07.071871 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9598 23:50:07.071923 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9599 23:50:07.071975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9600 23:50:07.072026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9601 23:50:07.072078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9602 23:50:07.072129 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9603 23:50:07.072181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9604 23:50:07.072233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9605 23:50:07.072285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9606 23:50:07.072337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9607 23:50:07.072389 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9608 23:50:07.072441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9609 23:50:07.072493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9610 23:50:07.072545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9611 23:50:07.072640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9612 23:50:07.072692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9613 23:50:07.072744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9614 23:50:07.072796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9615 23:50:07.072848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9616 23:50:07.072900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9617 23:50:07.072952 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9618 23:50:07.073004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9619 23:50:07.073056 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9620 23:50:07.073107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9621 23:50:07.073159 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9622 23:50:07.073211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9623 23:50:07.073263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9624 23:50:07.073315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9625 23:50:07.073367 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9626 23:50:07.073418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9627 23:50:07.073470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9628 23:50:07.073522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9629 23:50:07.073573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9630 23:50:07.073625 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9631 23:50:07.073676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9632 23:50:07.073728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9633 23:50:07.073779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9634 23:50:07.073831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9635 23:50:07.073882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9636 23:50:07.073934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9637 23:50:07.073985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9638 23:50:07.074038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9639 23:50:07.074090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9640 23:50:07.074141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9641 23:50:07.074383 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9642 23:50:07.074441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9643 23:50:07.074494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9644 23:50:07.074546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9645 23:50:07.074599 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9646 23:50:07.074651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9647 23:50:07.074703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9648 23:50:07.074755 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9649 23:50:07.074807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9650 23:50:07.074859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9651 23:50:07.074911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9652 23:50:07.074962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9653 23:50:07.075014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9654 23:50:07.075066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9655 23:50:07.075118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9656 23:50:07.075170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9657 23:50:07.075222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9658 23:50:07.075274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9659 23:50:07.075326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9660 23:50:07.075378 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9661 23:50:07.075429 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9662 23:50:07.075481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9663 23:50:07.075533 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9664 23:50:07.075585 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9665 23:50:07.075637 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9666 23:50:07.075707 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9667 23:50:07.075762 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9668 23:50:07.075815 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9669 23:50:07.075867 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9670 23:50:07.075919 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9671 23:50:07.075971 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9672 23:50:07.076023 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9673 23:50:07.076075 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9674 23:50:07.076127 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9675 23:50:07.076179 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9676 23:50:07.076231 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9677 23:50:07.076282 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9678 23:50:07.076334 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9679 23:50:07.076387 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9680 23:50:07.076438 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9681 23:50:07.076490 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9682 23:50:07.076542 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9683 23:50:07.076645 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9684 23:50:07.076698 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9685 23:50:07.076751 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9686 23:50:07.076803 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9687 23:50:07.076856 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9688 23:50:07.076908 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9689 23:50:07.076960 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9690 23:50:07.077011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9691 23:50:07.077064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9692 23:50:07.077116 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9693 23:50:07.077168 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9694 23:50:07.077219 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9695 23:50:07.077271 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9696 23:50:07.077323 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9697 23:50:07.077376 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9698 23:50:07.077427 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9699 23:50:07.077479 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9700 23:50:07.077531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9701 23:50:07.077583 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9702 23:50:07.077634 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9703 23:50:07.077686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9704 23:50:07.077737 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9705 23:50:07.077789 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9706 23:50:07.077841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9707 23:50:07.077893 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9708 23:50:07.077945 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9709 23:50:07.077997 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9710 23:50:07.078049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9711 23:50:07.078101 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9712 23:50:07.078153 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9713 23:50:07.078205 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9714 23:50:07.078257 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9715 23:50:07.078308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9716 23:50:07.078378 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9717 23:50:07.078431 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9718 23:50:07.078676 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9719 23:50:07.078737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9720 23:50:07.078790 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9721 23:50:07.078843 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9722 23:50:07.078895 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9723 23:50:07.078947 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9724 23:50:07.078999 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9725 23:50:07.079051 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9726 23:50:07.079103 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9727 23:50:07.079155 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9728 23:50:07.079207 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9729 23:50:07.079259 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9730 23:50:07.079311 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9731 23:50:07.079362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9732 23:50:07.079414 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9733 23:50:07.079466 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9734 23:50:07.079518 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9735 23:50:07.079569 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9736 23:50:07.079622 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9737 23:50:07.079673 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9738 23:50:07.079725 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9739 23:50:07.079778 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9740 23:50:07.079830 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9741 23:50:07.079881 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9742 23:50:07.079933 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9743 23:50:07.079985 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9744 23:50:07.080037 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9745 23:50:07.080088 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9746 23:50:07.080140 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9747 23:50:07.080192 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9748 23:50:07.080243 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9749 23:50:07.080295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9750 23:50:07.080347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9751 23:50:07.080398 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9752 23:50:07.080450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9753 23:50:07.080502 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9754 23:50:07.080554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9755 23:50:07.080658 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9756 23:50:07.080710 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9757 23:50:07.080762 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9758 23:50:07.080814 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9759 23:50:07.080866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9760 23:50:07.080917 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9761 23:50:07.080969 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9762 23:50:07.081021 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9763 23:50:07.081073 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9764 23:50:07.081125 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9765 23:50:07.081176 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9766 23:50:07.081228 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9767 23:50:07.081280 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9768 23:50:07.081332 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9769 23:50:07.081384 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9770 23:50:07.081435 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9771 23:50:07.081487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9772 23:50:07.081539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9773 23:50:07.081591 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9774 23:50:07.081643 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9775 23:50:07.081694 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9776 23:50:07.081745 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9777 23:50:07.081797 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9778 23:50:07.081849 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9779 23:50:07.081901 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9780 23:50:07.081952 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9781 23:50:07.082004 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9782 23:50:07.082056 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9783 23:50:07.082108 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9784 23:50:07.082159 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9785 23:50:07.082211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9786 23:50:07.082264 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9787 23:50:07.082316 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9788 23:50:07.082368 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9789 23:50:07.082419 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9790 23:50:07.082471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9791 23:50:07.082523 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9792 23:50:07.082574 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9793 23:50:07.082626 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9794 23:50:07.082869 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9795 23:50:07.082927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9796 23:50:07.082980 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9797 23:50:07.083032 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9798 23:50:07.083085 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9799 23:50:07.083137 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9800 23:50:07.083189 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9801 23:50:07.083240 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9802 23:50:07.083292 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9803 23:50:07.083345 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9804 23:50:07.083396 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9805 23:50:07.083448 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9806 23:50:07.083501 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9807 23:50:07.083553 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9808 23:50:07.083605 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9809 23:50:07.083656 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9810 23:50:07.083708 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9811 23:50:07.083760 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9812 23:50:07.083812 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9813 23:50:07.083863 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9814 23:50:07.083915 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9815 23:50:07.083967 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9816 23:50:07.084019 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9817 23:50:07.084070 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9818 23:50:07.084122 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9819 23:50:07.084173 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9820 23:50:07.084225 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9821 23:50:07.084277 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9822 23:50:07.084329 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9823 23:50:07.084381 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9824 23:50:07.084433 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9825 23:50:07.084484 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9826 23:50:07.084539 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9827 23:50:07.084628 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9828 23:50:07.084693 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9829 23:50:07.084835 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9830 23:50:07.084968 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9831 23:50:07.085064 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9832 23:50:07.085118 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9833 23:50:07.085170 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9834 23:50:07.085222 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9835 23:50:07.085275 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9836 23:50:07.085327 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9837 23:50:07.085379 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9838 23:50:07.085433 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9839 23:50:07.085485 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9840 23:50:07.085537 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9841 23:50:07.085588 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9842 23:50:07.085640 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9843 23:50:07.085692 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9844 23:50:07.085744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9845 23:50:07.085797 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9846 23:50:07.085848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9847 23:50:07.085900 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9848 23:50:07.085952 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9849 23:50:07.086003 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9850 23:50:07.086055 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9851 23:50:07.086107 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9852 23:50:07.086159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9853 23:50:07.086210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9854 23:50:07.086262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9855 23:50:07.086314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9856 23:50:07.086366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9857 23:50:07.086418 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9858 23:50:07.086469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9859 23:50:07.086521 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9860 23:50:07.086573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9861 23:50:07.086625 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9862 23:50:07.086676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9863 23:50:07.086728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9864 23:50:07.086780 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9865 23:50:07.086832 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9866 23:50:07.086883 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9867 23:50:07.086935 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9868 23:50:07.086987 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9869 23:50:07.087038 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9870 23:50:07.087090 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9871 23:50:07.087142 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9872 23:50:07.087383 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9873 23:50:07.087441 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9874 23:50:07.087495 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9875 23:50:07.087547 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9876 23:50:07.087599 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9877 23:50:07.087650 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9878 23:50:07.087702 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9879 23:50:07.087754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9880 23:50:07.087806 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9881 23:50:07.087858 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9882 23:50:07.087909 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9883 23:50:07.087961 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9884 23:50:07.089565 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9885 23:50:07.096453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9886 23:50:07.099615 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9887 23:50:07.106461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9888 23:50:07.109937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9889 23:50:07.113544 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9890 23:50:07.119672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9891 23:50:07.123120 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9892 23:50:07.126417 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9893 23:50:07.132817 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9894 23:50:07.136751 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9895 23:50:07.143200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9896 23:50:07.146782 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9897 23:50:07.149785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9898 23:50:07.156785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9899 23:50:07.159731 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9900 23:50:07.166298 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9901 23:50:07.169706 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9902 23:50:07.176348 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9903 23:50:07.278908 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9904 23:50:07.279384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9905 23:50:07.279719 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9906 23:50:07.280028 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9907 23:50:07.280327 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9908 23:50:07.280662 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9909 23:50:07.280959 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9910 23:50:07.281242 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9911 23:50:07.281518 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9912 23:50:07.281793 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9913 23:50:07.282114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9914 23:50:07.282433 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9915 23:50:07.282708 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9916 23:50:07.282978 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9917 23:50:07.283247 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9918 23:50:07.283516 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9919 23:50:07.283785 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9920 23:50:07.284056 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9921 23:50:07.284324 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9922 23:50:07.284614 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9923 23:50:07.284887 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9924 23:50:07.285159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9925 23:50:07.285564 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9926 23:50:07.289029 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9927 23:50:07.292480 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9928 23:50:07.295374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9929 23:50:07.302194 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9930 23:50:07.305102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9931 23:50:07.311936 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9932 23:50:07.315690 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9933 23:50:07.321876 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9934 23:50:07.325153 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9935 23:50:07.331895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9936 23:50:07.335255 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9937 23:50:07.338529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9938 23:50:07.345226 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9939 23:50:07.348666 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9940 23:50:07.354901 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9941 23:50:07.358294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9942 23:50:07.365213 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9943 23:50:07.368599 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9944 23:50:07.371832 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9945 23:50:07.378372 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9946 23:50:07.382052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9947 23:50:07.388197 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9948 23:50:07.391440 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9949 23:50:07.397992 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9950 23:50:07.401645 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9951 23:50:07.407825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9952 23:50:07.411260 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9953 23:50:07.414974 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9954 23:50:07.421137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9955 23:50:07.424066 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9956 23:50:07.431013 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9957 23:50:07.434826 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9958 23:50:07.440644 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9959 23:50:07.444388 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9960 23:50:07.451221 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9961 23:50:07.454231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9962 23:50:07.457535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9963 23:50:07.463866 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9964 23:50:07.467444 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9965 23:50:07.474198 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9966 23:50:07.477392 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9967 23:50:07.483903 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9968 23:50:07.487508 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9969 23:50:07.490818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9970 23:50:07.497574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9971 23:50:07.500909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9972 23:50:07.507172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9973 23:50:07.510533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9974 23:50:07.516923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9975 23:50:07.520493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9976 23:50:07.526845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9977 23:50:07.530426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9978 23:50:07.536980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9979 23:50:07.540258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9980 23:50:07.547139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9981 23:50:07.550351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9982 23:50:07.556664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9983 23:50:07.560339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9984 23:50:07.566564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9985 23:50:07.570098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9986 23:50:07.576522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9987 23:50:07.579906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9988 23:50:07.586871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9989 23:50:07.590015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9990 23:50:07.596241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9991 23:50:07.599825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9992 23:50:07.606267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9993 23:50:07.609445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9994 23:50:07.616463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9995 23:50:07.620102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9996 23:50:07.626110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9997 23:50:07.629721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9998 23:50:07.636106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9999 23:50:07.639497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10000 23:50:07.646104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10001 23:50:07.649606 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10002 23:50:07.652587 INFO: [APUAPC] vio 0
10003 23:50:07.655763 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10004 23:50:07.659576 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10005 23:50:07.662696 INFO: [APUAPC] D0_APC_0: 0x400510
10006 23:50:07.666152 INFO: [APUAPC] D0_APC_1: 0x0
10007 23:50:07.669424 INFO: [APUAPC] D0_APC_2: 0x1540
10008 23:50:07.672656 INFO: [APUAPC] D0_APC_3: 0x0
10009 23:50:07.675699 INFO: [APUAPC] D1_APC_0: 0xffffffff
10010 23:50:07.679047 INFO: [APUAPC] D1_APC_1: 0xffffffff
10011 23:50:07.682713 INFO: [APUAPC] D1_APC_2: 0x3fffff
10012 23:50:07.685950 INFO: [APUAPC] D1_APC_3: 0x0
10013 23:50:07.688906 INFO: [APUAPC] D2_APC_0: 0xffffffff
10014 23:50:07.692621 INFO: [APUAPC] D2_APC_1: 0xffffffff
10015 23:50:07.695644 INFO: [APUAPC] D2_APC_2: 0x3fffff
10016 23:50:07.698932 INFO: [APUAPC] D2_APC_3: 0x0
10017 23:50:07.702518 INFO: [APUAPC] D3_APC_0: 0xffffffff
10018 23:50:07.705881 INFO: [APUAPC] D3_APC_1: 0xffffffff
10019 23:50:07.709162 INFO: [APUAPC] D3_APC_2: 0x3fffff
10020 23:50:07.712530 INFO: [APUAPC] D3_APC_3: 0x0
10021 23:50:07.715523 INFO: [APUAPC] D4_APC_0: 0xffffffff
10022 23:50:07.719241 INFO: [APUAPC] D4_APC_1: 0xffffffff
10023 23:50:07.722478 INFO: [APUAPC] D4_APC_2: 0x3fffff
10024 23:50:07.725519 INFO: [APUAPC] D4_APC_3: 0x0
10025 23:50:07.729111 INFO: [APUAPC] D5_APC_0: 0xffffffff
10026 23:50:07.732062 INFO: [APUAPC] D5_APC_1: 0xffffffff
10027 23:50:07.735680 INFO: [APUAPC] D5_APC_2: 0x3fffff
10028 23:50:07.739492 INFO: [APUAPC] D5_APC_3: 0x0
10029 23:50:07.742338 INFO: [APUAPC] D6_APC_0: 0xffffffff
10030 23:50:07.745735 INFO: [APUAPC] D6_APC_1: 0xffffffff
10031 23:50:07.748464 INFO: [APUAPC] D6_APC_2: 0x3fffff
10032 23:50:07.752057 INFO: [APUAPC] D6_APC_3: 0x0
10033 23:50:07.755668 INFO: [APUAPC] D7_APC_0: 0xffffffff
10034 23:50:07.758813 INFO: [APUAPC] D7_APC_1: 0xffffffff
10035 23:50:07.762011 INFO: [APUAPC] D7_APC_2: 0x3fffff
10036 23:50:07.765729 INFO: [APUAPC] D7_APC_3: 0x0
10037 23:50:07.768743 INFO: [APUAPC] D8_APC_0: 0xffffffff
10038 23:50:07.771998 INFO: [APUAPC] D8_APC_1: 0xffffffff
10039 23:50:07.775365 INFO: [APUAPC] D8_APC_2: 0x3fffff
10040 23:50:07.778872 INFO: [APUAPC] D8_APC_3: 0x0
10041 23:50:07.781902 INFO: [APUAPC] D9_APC_0: 0xffffffff
10042 23:50:07.785011 INFO: [APUAPC] D9_APC_1: 0xffffffff
10043 23:50:07.788223 INFO: [APUAPC] D9_APC_2: 0x3fffff
10044 23:50:07.788668 INFO: [APUAPC] D9_APC_3: 0x0
10045 23:50:07.795123 INFO: [APUAPC] D10_APC_0: 0xffffffff
10046 23:50:07.798156 INFO: [APUAPC] D10_APC_1: 0xffffffff
10047 23:50:07.801564 INFO: [APUAPC] D10_APC_2: 0x3fffff
10048 23:50:07.804885 INFO: [APUAPC] D10_APC_3: 0x0
10049 23:50:07.807778 INFO: [APUAPC] D11_APC_0: 0xffffffff
10050 23:50:07.811577 INFO: [APUAPC] D11_APC_1: 0xffffffff
10051 23:50:07.814766 INFO: [APUAPC] D11_APC_2: 0x3fffff
10052 23:50:07.818288 INFO: [APUAPC] D11_APC_3: 0x0
10053 23:50:07.821676 INFO: [APUAPC] D12_APC_0: 0xffffffff
10054 23:50:07.824660 INFO: [APUAPC] D12_APC_1: 0xffffffff
10055 23:50:07.828173 INFO: [APUAPC] D12_APC_2: 0x3fffff
10056 23:50:07.831434 INFO: [APUAPC] D12_APC_3: 0x0
10057 23:50:07.834866 INFO: [APUAPC] D13_APC_0: 0xffffffff
10058 23:50:07.838200 INFO: [APUAPC] D13_APC_1: 0xffffffff
10059 23:50:07.841448 INFO: [APUAPC] D13_APC_2: 0x3fffff
10060 23:50:07.844908 INFO: [APUAPC] D13_APC_3: 0x0
10061 23:50:07.848391 INFO: [APUAPC] D14_APC_0: 0xffffffff
10062 23:50:07.851491 INFO: [APUAPC] D14_APC_1: 0xffffffff
10063 23:50:07.854954 INFO: [APUAPC] D14_APC_2: 0x3fffff
10064 23:50:07.857786 INFO: [APUAPC] D14_APC_3: 0x0
10065 23:50:07.861194 INFO: [APUAPC] D15_APC_0: 0xffffffff
10066 23:50:07.864615 INFO: [APUAPC] D15_APC_1: 0xffffffff
10067 23:50:07.867853 INFO: [APUAPC] D15_APC_2: 0x3fffff
10068 23:50:07.871264 INFO: [APUAPC] D15_APC_3: 0x0
10069 23:50:07.874354 INFO: [APUAPC] APC_CON: 0x4
10070 23:50:07.874778 INFO: [NOCDAPC] D0_APC_0: 0x0
10071 23:50:07.878261 INFO: [NOCDAPC] D0_APC_1: 0x0
10072 23:50:07.881205 INFO: [NOCDAPC] D1_APC_0: 0x0
10073 23:50:07.884424 INFO: [NOCDAPC] D1_APC_1: 0xfff
10074 23:50:07.887969 INFO: [NOCDAPC] D2_APC_0: 0x0
10075 23:50:07.890865 INFO: [NOCDAPC] D2_APC_1: 0xfff
10076 23:50:07.894124 INFO: [NOCDAPC] D3_APC_0: 0x0
10077 23:50:07.898313 INFO: [NOCDAPC] D3_APC_1: 0xfff
10078 23:50:07.901095 INFO: [NOCDAPC] D4_APC_0: 0x0
10079 23:50:07.904527 INFO: [NOCDAPC] D4_APC_1: 0xfff
10080 23:50:07.904981 INFO: [NOCDAPC] D5_APC_0: 0x0
10081 23:50:07.907431 INFO: [NOCDAPC] D5_APC_1: 0xfff
10082 23:50:07.911029 INFO: [NOCDAPC] D6_APC_0: 0x0
10083 23:50:07.914164 INFO: [NOCDAPC] D6_APC_1: 0xfff
10084 23:50:07.917943 INFO: [NOCDAPC] D7_APC_0: 0x0
10085 23:50:07.920715 INFO: [NOCDAPC] D7_APC_1: 0xfff
10086 23:50:07.923972 INFO: [NOCDAPC] D8_APC_0: 0x0
10087 23:50:07.927607 INFO: [NOCDAPC] D8_APC_1: 0xfff
10088 23:50:07.930874 INFO: [NOCDAPC] D9_APC_0: 0x0
10089 23:50:07.934057 INFO: [NOCDAPC] D9_APC_1: 0xfff
10090 23:50:07.937348 INFO: [NOCDAPC] D10_APC_0: 0x0
10091 23:50:07.940633 INFO: [NOCDAPC] D10_APC_1: 0xfff
10092 23:50:07.941054 INFO: [NOCDAPC] D11_APC_0: 0x0
10093 23:50:07.944026 INFO: [NOCDAPC] D11_APC_1: 0xfff
10094 23:50:07.947210 INFO: [NOCDAPC] D12_APC_0: 0x0
10095 23:50:07.950927 INFO: [NOCDAPC] D12_APC_1: 0xfff
10096 23:50:07.954172 INFO: [NOCDAPC] D13_APC_0: 0x0
10097 23:50:07.957117 INFO: [NOCDAPC] D13_APC_1: 0xfff
10098 23:50:07.960661 INFO: [NOCDAPC] D14_APC_0: 0x0
10099 23:50:07.964217 INFO: [NOCDAPC] D14_APC_1: 0xfff
10100 23:50:07.967015 INFO: [NOCDAPC] D15_APC_0: 0x0
10101 23:50:07.970760 INFO: [NOCDAPC] D15_APC_1: 0xfff
10102 23:50:07.973769 INFO: [NOCDAPC] APC_CON: 0x4
10103 23:50:07.977276 INFO: [APUAPC] set_apusys_apc done
10104 23:50:07.980472 INFO: [DEVAPC] devapc_init done
10105 23:50:07.983769 INFO: GICv3 without legacy support detected.
10106 23:50:07.987293 INFO: ARM GICv3 driver initialized in EL3
10107 23:50:07.990220 INFO: Maximum SPI INTID supported: 639
10108 23:50:07.997175 INFO: BL31: Initializing runtime services
10109 23:50:08.000721 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10110 23:50:08.003524 INFO: SPM: enable CPC mode
10111 23:50:08.010221 INFO: mcdi ready for mcusys-off-idle and system suspend
10112 23:50:08.014043 INFO: BL31: Preparing for EL3 exit to normal world
10113 23:50:08.016828 INFO: Entry point address = 0x80000000
10114 23:50:08.020205 INFO: SPSR = 0x8
10115 23:50:08.025359
10116 23:50:08.025774
10117 23:50:08.026101
10118 23:50:08.028314 Starting depthcharge on Spherion...
10119 23:50:08.028800
10120 23:50:08.029137 Wipe memory regions:
10121 23:50:08.029448
10122 23:50:08.031749 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10123 23:50:08.032249 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10124 23:50:08.032681 Setting prompt string to ['asurada:']
10125 23:50:08.033089 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10126 23:50:08.033758 [0x00000040000000, 0x00000054600000)
10127 23:50:08.154218
10128 23:50:08.154701 [0x00000054660000, 0x00000080000000)
10129 23:50:08.414694
10130 23:50:08.415261 [0x000000821a7280, 0x000000ffe64000)
10131 23:50:09.159979
10132 23:50:09.160548 [0x00000100000000, 0x00000240000000)
10133 23:50:11.050484
10134 23:50:11.053391 Initializing XHCI USB controller at 0x11200000.
10135 23:50:12.091995
10136 23:50:12.095425 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10137 23:50:12.095838
10138 23:50:12.096163
10139 23:50:12.096990 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10141 23:50:12.198030 asurada: tftpboot 192.168.201.1 14084321/tftp-deploy-8g3zsbyk/kernel/image.itb 14084321/tftp-deploy-8g3zsbyk/kernel/cmdline
10142 23:50:12.198561 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10143 23:50:12.198953 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10144 23:50:12.203582 tftpboot 192.168.201.1 14084321/tftp-deploy-8g3zsbyk/kernel/image.itp-deploy-8g3zsbyk/kernel/cmdline
10145 23:50:12.204002
10146 23:50:12.204328 Waiting for link
10147 23:50:12.364197
10148 23:50:12.364752 R8152: Initializing
10149 23:50:12.365097
10150 23:50:12.367507 Version 6 (ocp_data = 5c30)
10151 23:50:12.367926
10152 23:50:12.370674 R8152: Done initializing
10153 23:50:12.371090
10154 23:50:12.371418 Adding net device
10155 23:50:14.271659
10156 23:50:14.272215 done.
10157 23:50:14.272659
10158 23:50:14.273111 MAC: 00:24:32:30:78:ff
10159 23:50:14.273626
10160 23:50:14.274762 Sending DHCP discover... done.
10161 23:50:14.275220
10162 23:50:14.278004 Waiting for reply... done.
10163 23:50:14.278547
10164 23:50:14.281450 Sending DHCP request... done.
10165 23:50:14.281915
10166 23:50:14.284814 Waiting for reply... done.
10167 23:50:14.285278
10168 23:50:14.285651 My ip is 192.168.201.21
10169 23:50:14.285962
10170 23:50:14.288026 The DHCP server ip is 192.168.201.1
10171 23:50:14.288448
10172 23:50:14.294432 TFTP server IP predefined by user: 192.168.201.1
10173 23:50:14.294859
10174 23:50:14.301324 Bootfile predefined by user: 14084321/tftp-deploy-8g3zsbyk/kernel/image.itb
10175 23:50:14.301749
10176 23:50:14.302083 Sending tftp read request... done.
10177 23:50:14.304514
10178 23:50:14.311245 Waiting for the transfer...
10179 23:50:14.311686
10180 23:50:14.908364 00000000 ################################################################
10181 23:50:14.908506
10182 23:50:15.464395 00080000 ################################################################
10183 23:50:15.464595
10184 23:50:16.016816 00100000 ################################################################
10185 23:50:16.016976
10186 23:50:16.552747 00180000 ################################################################
10187 23:50:16.552956
10188 23:50:17.114499 00200000 ################################################################
10189 23:50:17.114693
10190 23:50:17.669146 00280000 ################################################################
10191 23:50:17.669338
10192 23:50:18.236361 00300000 ################################################################
10193 23:50:18.236551
10194 23:50:18.794560 00380000 ################################################################
10195 23:50:18.794743
10196 23:50:19.362776 00400000 ################################################################
10197 23:50:19.362929
10198 23:50:19.911661 00480000 ################################################################
10199 23:50:19.911855
10200 23:50:20.445640 00500000 ################################################################
10201 23:50:20.445809
10202 23:50:21.002353 00580000 ################################################################
10203 23:50:21.002536
10204 23:50:21.575029 00600000 ################################################################
10205 23:50:21.575165
10206 23:50:22.140750 00680000 ################################################################
10207 23:50:22.140908
10208 23:50:22.695177 00700000 ################################################################
10209 23:50:22.695323
10210 23:50:23.257785 00780000 ################################################################
10211 23:50:23.257943
10212 23:50:23.822130 00800000 ################################################################
10213 23:50:23.822315
10214 23:50:24.394340 00880000 ################################################################
10215 23:50:24.394491
10216 23:50:25.028972 00900000 ################################################################
10217 23:50:25.029481
10218 23:50:25.603299 00980000 ################################################################
10219 23:50:25.603450
10220 23:50:26.187738 00a00000 ################################################################
10221 23:50:26.187918
10222 23:50:26.744596 00a80000 ################################################################
10223 23:50:26.744806
10224 23:50:27.310601 00b00000 ################################################################
10225 23:50:27.310753
10226 23:50:27.884331 00b80000 ################################################################
10227 23:50:27.884484
10228 23:50:28.472461 00c00000 ################################################################
10229 23:50:28.472647
10230 23:50:29.070518 00c80000 ################################################################
10231 23:50:29.070663
10232 23:50:29.664470 00d00000 ################################################################
10233 23:50:29.664684
10234 23:50:30.248807 00d80000 ################################################################
10235 23:50:30.248978
10236 23:50:30.836391 00e00000 ################################################################
10237 23:50:30.836537
10238 23:50:31.406325 00e80000 ################################################################
10239 23:50:31.406469
10240 23:50:31.977439 00f00000 ################################################################
10241 23:50:31.977575
10242 23:50:32.546206 00f80000 ################################################################
10243 23:50:32.546339
10244 23:50:33.128444 01000000 ################################################################
10245 23:50:33.128613
10246 23:50:33.715831 01080000 ################################################################
10247 23:50:33.715978
10248 23:50:34.309070 01100000 ################################################################
10249 23:50:34.309221
10250 23:50:34.897192 01180000 ################################################################
10251 23:50:34.897337
10252 23:50:35.485338 01200000 ################################################################
10253 23:50:35.485494
10254 23:50:36.065535 01280000 ################################################################
10255 23:50:36.065686
10256 23:50:36.664837 01300000 ################################################################
10257 23:50:36.665031
10258 23:50:37.227821 01380000 ################################################################
10259 23:50:37.228009
10260 23:50:37.801424 01400000 ################################################################
10261 23:50:37.801567
10262 23:50:38.368248 01480000 ################################################################
10263 23:50:38.368399
10264 23:50:38.937275 01500000 ################################################################
10265 23:50:38.937428
10266 23:50:39.520400 01580000 ################################################################
10267 23:50:39.520592
10268 23:50:40.109693 01600000 ################################################################
10269 23:50:40.109907
10270 23:50:40.683478 01680000 ################################################################
10271 23:50:40.683636
10272 23:50:41.267508 01700000 ################################################################
10273 23:50:41.267665
10274 23:50:41.852029 01780000 ################################################################
10275 23:50:41.852173
10276 23:50:42.435458 01800000 ################################################################
10277 23:50:42.435625
10278 23:50:42.997594 01880000 ################################################################
10279 23:50:42.997775
10280 23:50:43.536257 01900000 ################################################################
10281 23:50:43.536426
10282 23:50:44.094310 01980000 ################################################################
10283 23:50:44.094449
10284 23:50:44.661964 01a00000 ################################################################
10285 23:50:44.662113
10286 23:50:45.219104 01a80000 ################################################################
10287 23:50:45.219249
10288 23:50:45.759089 01b00000 ################################################################
10289 23:50:45.759230
10290 23:50:46.317304 01b80000 ################################################################
10291 23:50:46.317467
10292 23:50:46.864277 01c00000 ################################################################
10293 23:50:46.864414
10294 23:50:47.424415 01c80000 ################################################################
10295 23:50:47.424554
10296 23:50:47.979753 01d00000 ################################################################
10297 23:50:47.979898
10298 23:50:48.501712 01d80000 ################################################################
10299 23:50:48.501874
10300 23:50:48.882374 01e00000 ############################################### done.
10301 23:50:48.882546
10302 23:50:48.885720 The bootfile was 31841054 bytes long.
10303 23:50:48.885852
10304 23:50:48.888479 Sending tftp read request... done.
10305 23:50:48.888608
10306 23:50:48.888711 Waiting for the transfer...
10307 23:50:48.888818
10308 23:50:48.892517 00000000 # done.
10309 23:50:48.892660
10310 23:50:48.898368 Command line loaded dynamically from TFTP file: 14084321/tftp-deploy-8g3zsbyk/kernel/cmdline
10311 23:50:48.898492
10312 23:50:48.922040 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10313 23:50:48.922256
10314 23:50:48.922398 Loading FIT.
10315 23:50:48.922526
10316 23:50:48.924996 Image ramdisk-1 has 18728275 bytes.
10317 23:50:48.925158
10318 23:50:48.928679 Image fdt-1 has 47258 bytes.
10319 23:50:48.928859
10320 23:50:48.931849 Image kernel-1 has 13063488 bytes.
10321 23:50:48.932008
10322 23:50:48.941834 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10323 23:50:48.941992
10324 23:50:48.958284 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10325 23:50:48.958428
10326 23:50:48.964700 Choosing best match conf-1 for compat google,spherion-rev2.
10327 23:50:48.964816
10328 23:50:48.972581 Connected to device vid:did:rid of 1ae0:0028:00
10329 23:50:48.981152
10330 23:50:48.983868 tpm_get_response: command 0x17b, return code 0x0
10331 23:50:48.983993
10332 23:50:48.990933 ec_init: CrosEC protocol v3 supported (256, 248)
10333 23:50:48.991071
10334 23:50:48.993903 tpm_cleanup: add release locality here.
10335 23:50:48.994014
10336 23:50:48.997311 Shutting down all USB controllers.
10337 23:50:48.997419
10338 23:50:49.000464 Removing current net device
10339 23:50:49.000614
10340 23:50:49.007779 Exiting depthcharge with code 4 at timestamp: 70342683
10341 23:50:49.007902
10342 23:50:49.010515 LZMA decompressing kernel-1 to 0x821a6718
10343 23:50:49.010624
10344 23:50:49.014384 LZMA decompressing kernel-1 to 0x40000000
10345 23:50:50.624995
10346 23:50:50.625155 jumping to kernel
10347 23:50:50.625609 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10348 23:50:50.625725 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10349 23:50:50.625816 Setting prompt string to ['Linux version [0-9]']
10350 23:50:50.625882 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10351 23:50:50.625981 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10352 23:50:50.706944
10353 23:50:50.710234 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10354 23:50:50.713882 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10355 23:50:50.713980 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10356 23:50:50.714051 Setting prompt string to []
10357 23:50:50.714126 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10358 23:50:50.714197 Using line separator: #'\n'#
10359 23:50:50.714255 No login prompt set.
10360 23:50:50.714314 Parsing kernel messages
10361 23:50:50.714368 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10362 23:50:50.714468 [login-action] Waiting for messages, (timeout 00:03:42)
10363 23:50:50.714532 Waiting using forced prompt support (timeout 00:01:51)
10364 23:50:50.733383 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10365 23:50:50.736456 [ 0.000000] random: crng init done
10366 23:50:50.743026 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10367 23:50:50.746650 [ 0.000000] efi: UEFI not found.
10368 23:50:50.753464 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10369 23:50:50.759509 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10370 23:50:50.769558 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10371 23:50:50.779351 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10372 23:50:50.786262 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10373 23:50:50.792945 [ 0.000000] printk: bootconsole [mtk8250] enabled
10374 23:50:50.799627 [ 0.000000] NUMA: No NUMA configuration found
10375 23:50:50.806083 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10376 23:50:50.809319 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10377 23:50:50.812455 [ 0.000000] Zone ranges:
10378 23:50:50.819434 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10379 23:50:50.822942 [ 0.000000] DMA32 empty
10380 23:50:50.829850 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10381 23:50:50.832673 [ 0.000000] Movable zone start for each node
10382 23:50:50.835657 [ 0.000000] Early memory node ranges
10383 23:50:50.842588 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10384 23:50:50.849007 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10385 23:50:50.856217 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10386 23:50:50.862153 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10387 23:50:50.868809 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10388 23:50:50.875515 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10389 23:50:50.931910 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10390 23:50:50.938671 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10391 23:50:50.945111 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10392 23:50:50.948107 [ 0.000000] psci: probing for conduit method from DT.
10393 23:50:50.954665 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10394 23:50:50.958064 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10395 23:50:50.964762 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10396 23:50:50.968004 [ 0.000000] psci: SMC Calling Convention v1.2
10397 23:50:50.974466 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10398 23:50:50.977763 [ 0.000000] Detected VIPT I-cache on CPU0
10399 23:50:50.984435 [ 0.000000] CPU features: detected: GIC system register CPU interface
10400 23:50:50.990995 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10401 23:50:50.997503 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10402 23:50:51.004352 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10403 23:50:51.010963 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10404 23:50:51.017610 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10405 23:50:51.023961 [ 0.000000] alternatives: applying boot alternatives
10406 23:50:51.031031 [ 0.000000] Fallback order for Node 0: 0
10407 23:50:51.037147 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10408 23:50:51.040551 [ 0.000000] Policy zone: Normal
10409 23:50:51.063730 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10410 23:50:51.073487 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10411 23:50:51.084178 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10412 23:50:51.094296 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10413 23:50:51.101496 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10414 23:50:51.104046 <6>[ 0.000000] software IO TLB: area num 8.
10415 23:50:51.160470 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10416 23:50:51.309975 <6>[ 0.000000] Memory: 7945900K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406868K reserved, 32768K cma-reserved)
10417 23:50:51.316508 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10418 23:50:51.323366 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10419 23:50:51.326710 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10420 23:50:51.332823 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10421 23:50:51.339758 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10422 23:50:51.342872 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10423 23:50:51.352826 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10424 23:50:51.359248 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10425 23:50:51.365752 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10426 23:50:51.372963 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10427 23:50:51.375635 <6>[ 0.000000] GICv3: 608 SPIs implemented
10428 23:50:51.379375 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10429 23:50:51.385519 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10430 23:50:51.389053 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10431 23:50:51.395386 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10432 23:50:51.408788 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10433 23:50:51.418939 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10434 23:50:51.428794 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10435 23:50:51.436522 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10436 23:50:51.449715 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10437 23:50:51.455856 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10438 23:50:51.462579 <6>[ 0.009183] Console: colour dummy device 80x25
10439 23:50:51.472487 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10440 23:50:51.479382 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10441 23:50:51.483410 <6>[ 0.029227] LSM: Security Framework initializing
10442 23:50:51.489412 <6>[ 0.034193] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 23:50:51.499129 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 23:50:51.505995 <6>[ 0.051471] cblist_init_generic: Setting adjustable number of callback queues.
10445 23:50:51.512394 <6>[ 0.058915] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 23:50:51.522497 <6>[ 0.065293] cblist_init_generic: Setting adjustable number of callback queues.
10447 23:50:51.528769 <6>[ 0.072719] cblist_init_generic: Setting shift to 3 and lim to 1.
10448 23:50:51.532490 <6>[ 0.079120] rcu: Hierarchical SRCU implementation.
10449 23:50:51.538917 <6>[ 0.084136] rcu: Max phase no-delay instances is 1000.
10450 23:50:51.545432 <6>[ 0.091171] EFI services will not be available.
10451 23:50:51.549315 <6>[ 0.096128] smp: Bringing up secondary CPUs ...
10452 23:50:51.557125 <6>[ 0.101206] Detected VIPT I-cache on CPU1
10453 23:50:51.563585 <6>[ 0.101278] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10454 23:50:51.570401 <6>[ 0.101310] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10455 23:50:51.573695 <6>[ 0.101645] Detected VIPT I-cache on CPU2
10456 23:50:51.580440 <6>[ 0.101695] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10457 23:50:51.590577 <6>[ 0.101713] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10458 23:50:51.593887 <6>[ 0.101975] Detected VIPT I-cache on CPU3
10459 23:50:51.600196 <6>[ 0.102023] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10460 23:50:51.606756 <6>[ 0.102038] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10461 23:50:51.610110 <6>[ 0.102342] CPU features: detected: Spectre-v4
10462 23:50:51.617090 <6>[ 0.102349] CPU features: detected: Spectre-BHB
10463 23:50:51.620508 <6>[ 0.102354] Detected PIPT I-cache on CPU4
10464 23:50:51.626900 <6>[ 0.102412] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10465 23:50:51.633487 <6>[ 0.102428] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10466 23:50:51.640403 <6>[ 0.102716] Detected PIPT I-cache on CPU5
10467 23:50:51.647191 <6>[ 0.102779] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10468 23:50:51.653674 <6>[ 0.102795] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10469 23:50:51.657110 <6>[ 0.103075] Detected PIPT I-cache on CPU6
10470 23:50:51.663451 <6>[ 0.103141] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10471 23:50:51.670488 <6>[ 0.103157] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10472 23:50:51.673317 <6>[ 0.103452] Detected PIPT I-cache on CPU7
10473 23:50:51.683339 <6>[ 0.103516] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10474 23:50:51.690061 <6>[ 0.103532] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10475 23:50:51.693153 <6>[ 0.103578] smp: Brought up 1 node, 8 CPUs
10476 23:50:51.700087 <6>[ 0.244861] SMP: Total of 8 processors activated.
10477 23:50:51.703398 <6>[ 0.249782] CPU features: detected: 32-bit EL0 Support
10478 23:50:51.713202 <6>[ 0.255145] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10479 23:50:51.719794 <6>[ 0.264000] CPU features: detected: Common not Private translations
10480 23:50:51.722844 <6>[ 0.270516] CPU features: detected: CRC32 instructions
10481 23:50:51.729691 <6>[ 0.275868] CPU features: detected: RCpc load-acquire (LDAPR)
10482 23:50:51.736384 <6>[ 0.281865] CPU features: detected: LSE atomic instructions
10483 23:50:51.743078 <6>[ 0.287647] CPU features: detected: Privileged Access Never
10484 23:50:51.746382 <6>[ 0.293462] CPU features: detected: RAS Extension Support
10485 23:50:51.755936 <6>[ 0.299071] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10486 23:50:51.759110 <6>[ 0.306292] CPU: All CPU(s) started at EL2
10487 23:50:51.765846 <6>[ 0.310626] alternatives: applying system-wide alternatives
10488 23:50:51.774947 <6>[ 0.321484] devtmpfs: initialized
10489 23:50:51.790384 <6>[ 0.330374] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10490 23:50:51.797459 <6>[ 0.340335] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10491 23:50:51.803814 <6>[ 0.348361] pinctrl core: initialized pinctrl subsystem
10492 23:50:51.807204 <6>[ 0.355014] DMI not present or invalid.
10493 23:50:51.813979 <6>[ 0.359422] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10494 23:50:51.823655 <6>[ 0.366295] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10495 23:50:51.830199 <6>[ 0.373870] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10496 23:50:51.840222 <6>[ 0.382088] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10497 23:50:51.843393 <6>[ 0.390330] audit: initializing netlink subsys (disabled)
10498 23:50:51.853665 <5>[ 0.396023] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10499 23:50:51.860046 <6>[ 0.396723] thermal_sys: Registered thermal governor 'step_wise'
10500 23:50:51.866816 <6>[ 0.403990] thermal_sys: Registered thermal governor 'power_allocator'
10501 23:50:51.870146 <6>[ 0.410243] cpuidle: using governor menu
10502 23:50:51.876727 <6>[ 0.421202] NET: Registered PF_QIPCRTR protocol family
10503 23:50:51.883160 <6>[ 0.426698] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10504 23:50:51.886405 <6>[ 0.433800] ASID allocator initialised with 32768 entries
10505 23:50:51.893762 <6>[ 0.440370] Serial: AMBA PL011 UART driver
10506 23:50:51.902460 <4>[ 0.449096] Trying to register duplicate clock ID: 134
10507 23:50:51.960924 <6>[ 0.510546] KASLR enabled
10508 23:50:51.975326 <6>[ 0.518282] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10509 23:50:51.981896 <6>[ 0.525294] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10510 23:50:51.988712 <6>[ 0.531783] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10511 23:50:51.995415 <6>[ 0.538787] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10512 23:50:52.001373 <6>[ 0.545276] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10513 23:50:52.008051 <6>[ 0.552279] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10514 23:50:52.015286 <6>[ 0.558764] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10515 23:50:52.022104 <6>[ 0.565771] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10516 23:50:52.024849 <6>[ 0.573291] ACPI: Interpreter disabled.
10517 23:50:52.033429 <6>[ 0.579713] iommu: Default domain type: Translated
10518 23:50:52.039940 <6>[ 0.584826] iommu: DMA domain TLB invalidation policy: strict mode
10519 23:50:52.043104 <5>[ 0.591482] SCSI subsystem initialized
10520 23:50:52.049952 <6>[ 0.595650] usbcore: registered new interface driver usbfs
10521 23:50:52.056584 <6>[ 0.601381] usbcore: registered new interface driver hub
10522 23:50:52.059940 <6>[ 0.606932] usbcore: registered new device driver usb
10523 23:50:52.066574 <6>[ 0.613020] pps_core: LinuxPPS API ver. 1 registered
10524 23:50:52.076432 <6>[ 0.618212] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10525 23:50:52.080280 <6>[ 0.627558] PTP clock support registered
10526 23:50:52.083892 <6>[ 0.631799] EDAC MC: Ver: 3.0.0
10527 23:50:52.091022 <6>[ 0.636949] FPGA manager framework
10528 23:50:52.097287 <6>[ 0.640633] Advanced Linux Sound Architecture Driver Initialized.
10529 23:50:52.100649 <6>[ 0.647397] vgaarb: loaded
10530 23:50:52.106824 <6>[ 0.650560] clocksource: Switched to clocksource arch_sys_counter
10531 23:50:52.110369 <5>[ 0.657005] VFS: Disk quotas dquot_6.6.0
10532 23:50:52.116885 <6>[ 0.661190] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10533 23:50:52.120096 <6>[ 0.668377] pnp: PnP ACPI: disabled
10534 23:50:52.128408 <6>[ 0.675054] NET: Registered PF_INET protocol family
10535 23:50:52.138433 <6>[ 0.680641] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10536 23:50:52.149913 <6>[ 0.692951] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10537 23:50:52.160040 <6>[ 0.701760] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10538 23:50:52.166376 <6>[ 0.709731] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10539 23:50:52.172998 <6>[ 0.718428] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10540 23:50:52.184822 <6>[ 0.728165] TCP: Hash tables configured (established 65536 bind 65536)
10541 23:50:52.191622 <6>[ 0.735031] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 23:50:52.197953 <6>[ 0.742226] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10543 23:50:52.204700 <6>[ 0.749923] NET: Registered PF_UNIX/PF_LOCAL protocol family
10544 23:50:52.211670 <6>[ 0.756071] RPC: Registered named UNIX socket transport module.
10545 23:50:52.214663 <6>[ 0.762225] RPC: Registered udp transport module.
10546 23:50:52.221366 <6>[ 0.767158] RPC: Registered tcp transport module.
10547 23:50:52.228090 <6>[ 0.772088] RPC: Registered tcp NFSv4.1 backchannel transport module.
10548 23:50:52.231313 <6>[ 0.778754] PCI: CLS 0 bytes, default 64
10549 23:50:52.234616 <6>[ 0.783057] Unpacking initramfs...
10550 23:50:52.251876 <6>[ 0.795161] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10551 23:50:52.261834 <6>[ 0.803793] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10552 23:50:52.265475 <6>[ 0.812620] kvm [1]: IPA Size Limit: 40 bits
10553 23:50:52.272005 <6>[ 0.817145] kvm [1]: GICv3: no GICV resource entry
10554 23:50:52.275125 <6>[ 0.822162] kvm [1]: disabling GICv2 emulation
10555 23:50:52.281458 <6>[ 0.826848] kvm [1]: GIC system register CPU interface enabled
10556 23:50:52.291997 <6>[ 0.838577] kvm [1]: vgic interrupt IRQ18
10557 23:50:52.295082 <6>[ 0.842967] kvm [1]: VHE mode initialized successfully
10558 23:50:52.302864 <5>[ 0.849386] Initialise system trusted keyrings
10559 23:50:52.309326 <6>[ 0.854249] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10560 23:50:52.317832 <6>[ 0.864257] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10561 23:50:52.324481 <5>[ 0.870718] NFS: Registering the id_resolver key type
10562 23:50:52.327892 <5>[ 0.876020] Key type id_resolver registered
10563 23:50:52.334312 <5>[ 0.880432] Key type id_legacy registered
10564 23:50:52.341022 <6>[ 0.884706] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10565 23:50:52.347731 <6>[ 0.891627] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10566 23:50:52.354303 <6>[ 0.899385] 9p: Installing v9fs 9p2000 file system support
10567 23:50:52.391852 <5>[ 0.938344] Key type asymmetric registered
10568 23:50:52.395314 <5>[ 0.942675] Asymmetric key parser 'x509' registered
10569 23:50:52.405084 <6>[ 0.947834] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10570 23:50:52.408458 <6>[ 0.955449] io scheduler mq-deadline registered
10571 23:50:52.411774 <6>[ 0.960210] io scheduler kyber registered
10572 23:50:52.430658 <6>[ 0.977188] EINJ: ACPI disabled.
10573 23:50:52.463019 <4>[ 1.003057] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 23:50:52.473372 <4>[ 1.013669] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 23:50:52.488065 <6>[ 1.034382] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10576 23:50:52.496017 <6>[ 1.042357] printk: console [ttyS0] disabled
10577 23:50:52.524422 <6>[ 1.066989] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10578 23:50:52.530928 <6>[ 1.076457] printk: console [ttyS0] enabled
10579 23:50:52.534065 <6>[ 1.076457] printk: console [ttyS0] enabled
10580 23:50:52.540508 <6>[ 1.085352] printk: bootconsole [mtk8250] disabled
10581 23:50:52.544394 <6>[ 1.085352] printk: bootconsole [mtk8250] disabled
10582 23:50:52.550474 <6>[ 1.096354] SuperH (H)SCI(F) driver initialized
10583 23:50:52.553948 <6>[ 1.101628] msm_serial: driver initialized
10584 23:50:52.567962 <6>[ 1.110484] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10585 23:50:52.577470 <6>[ 1.119030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10586 23:50:52.584186 <6>[ 1.127572] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10587 23:50:52.593976 <6>[ 1.136203] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10588 23:50:52.604268 <6>[ 1.144909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10589 23:50:52.610736 <6>[ 1.153628] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10590 23:50:52.620389 <6>[ 1.162168] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10591 23:50:52.627577 <6>[ 1.170965] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10592 23:50:52.637231 <6>[ 1.179506] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10593 23:50:52.649029 <6>[ 1.195159] loop: module loaded
10594 23:50:52.655827 <6>[ 1.201061] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10595 23:50:52.678307 <4>[ 1.224441] mtk-pmic-keys: Failed to locate of_node [id: -1]
10596 23:50:52.684900 <6>[ 1.231357] megasas: 07.719.03.00-rc1
10597 23:50:52.694687 <6>[ 1.241112] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10598 23:50:52.703639 <6>[ 1.249941] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10599 23:50:52.720587 <6>[ 1.266565] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10600 23:50:52.776841 <6>[ 1.316381] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10601 23:50:53.025178 <6>[ 1.571538] Freeing initrd memory: 18284K
10602 23:50:53.036394 <6>[ 1.582930] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10603 23:50:53.047657 <6>[ 1.593983] tun: Universal TUN/TAP device driver, 1.6
10604 23:50:53.051248 <6>[ 1.600070] thunder_xcv, ver 1.0
10605 23:50:53.054790 <6>[ 1.603573] thunder_bgx, ver 1.0
10606 23:50:53.057628 <6>[ 1.607066] nicpf, ver 1.0
10607 23:50:53.068143 <6>[ 1.611087] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10608 23:50:53.071852 <6>[ 1.618563] hns3: Copyright (c) 2017 Huawei Corporation.
10609 23:50:53.074694 <6>[ 1.624149] hclge is initializing
10610 23:50:53.081810 <6>[ 1.627730] e1000: Intel(R) PRO/1000 Network Driver
10611 23:50:53.088087 <6>[ 1.632859] e1000: Copyright (c) 1999-2006 Intel Corporation.
10612 23:50:53.091698 <6>[ 1.638873] e1000e: Intel(R) PRO/1000 Network Driver
10613 23:50:53.098646 <6>[ 1.644089] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10614 23:50:53.104761 <6>[ 1.650275] igb: Intel(R) Gigabit Ethernet Network Driver
10615 23:50:53.111591 <6>[ 1.655924] igb: Copyright (c) 2007-2014 Intel Corporation.
10616 23:50:53.118456 <6>[ 1.661760] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10617 23:50:53.124656 <6>[ 1.668278] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10618 23:50:53.128350 <6>[ 1.674747] sky2: driver version 1.30
10619 23:50:53.134853 <6>[ 1.679676] usbcore: registered new device driver r8152-cfgselector
10620 23:50:53.141525 <6>[ 1.686211] usbcore: registered new interface driver r8152
10621 23:50:53.144495 <6>[ 1.692036] VFIO - User Level meta-driver version: 0.3
10622 23:50:53.153907 <6>[ 1.700300] usbcore: registered new interface driver usb-storage
10623 23:50:53.160652 <6>[ 1.706747] usbcore: registered new device driver onboard-usb-hub
10624 23:50:53.170010 <6>[ 1.715930] mt6397-rtc mt6359-rtc: registered as rtc0
10625 23:50:53.179929 <6>[ 1.721406] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:50:53 UTC (1717026653)
10626 23:50:53.183087 <6>[ 1.731009] i2c_dev: i2c /dev entries driver
10627 23:50:53.199769 <6>[ 1.742706] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10628 23:50:53.206608 <4>[ 1.751425] cpu cpu0: supply cpu not found, using dummy regulator
10629 23:50:53.213061 <4>[ 1.757850] cpu cpu1: supply cpu not found, using dummy regulator
10630 23:50:53.219813 <4>[ 1.764255] cpu cpu2: supply cpu not found, using dummy regulator
10631 23:50:53.226369 <4>[ 1.770672] cpu cpu3: supply cpu not found, using dummy regulator
10632 23:50:53.232885 <4>[ 1.777068] cpu cpu4: supply cpu not found, using dummy regulator
10633 23:50:53.239919 <4>[ 1.783463] cpu cpu5: supply cpu not found, using dummy regulator
10634 23:50:53.246513 <4>[ 1.789872] cpu cpu6: supply cpu not found, using dummy regulator
10635 23:50:53.252831 <4>[ 1.796271] cpu cpu7: supply cpu not found, using dummy regulator
10636 23:50:53.270632 <6>[ 1.816921] cpu cpu0: EM: created perf domain
10637 23:50:53.274117 <6>[ 1.821851] cpu cpu4: EM: created perf domain
10638 23:50:53.281798 <6>[ 1.827468] sdhci: Secure Digital Host Controller Interface driver
10639 23:50:53.287986 <6>[ 1.833900] sdhci: Copyright(c) Pierre Ossman
10640 23:50:53.294490 <6>[ 1.838865] Synopsys Designware Multimedia Card Interface Driver
10641 23:50:53.301514 <6>[ 1.845493] sdhci-pltfm: SDHCI platform and OF driver helper
10642 23:50:53.304435 <6>[ 1.845633] mmc0: CQHCI version 5.10
10643 23:50:53.311587 <6>[ 1.855514] ledtrig-cpu: registered to indicate activity on CPUs
10644 23:50:53.317676 <6>[ 1.862569] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10645 23:50:53.324420 <6>[ 1.869629] usbcore: registered new interface driver usbhid
10646 23:50:53.327731 <6>[ 1.875460] usbhid: USB HID core driver
10647 23:50:53.334627 <6>[ 1.879652] spi_master spi0: will run message pump with realtime priority
10648 23:50:53.379612 <6>[ 1.918932] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10649 23:50:53.397714 <6>[ 1.933983] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10650 23:50:53.404873 <6>[ 1.948852] cros-ec-spi spi0.0: Chrome EC device registered
10651 23:50:53.408468 <6>[ 1.954900] mmc0: Command Queue Engine enabled
10652 23:50:53.414918 <6>[ 1.959701] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10653 23:50:53.421922 <6>[ 1.967523] mmcblk0: mmc0:0001 DA4128 116 GiB
10654 23:50:53.431914 <6>[ 1.967598] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10655 23:50:53.435057 <6>[ 1.976077] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10656 23:50:53.441511 <6>[ 1.982652] NET: Registered PF_PACKET protocol family
10657 23:50:53.448515 <6>[ 1.988920] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10658 23:50:53.451400 <6>[ 1.992857] 9pnet: Installing 9P2000 support
10659 23:50:53.455634 <6>[ 1.998617] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10660 23:50:53.462253 <5>[ 2.002546] Key type dns_resolver registered
10661 23:50:53.468093 <6>[ 2.008323] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10662 23:50:53.472869 <6>[ 2.012800] registered taskstats version 1
10663 23:50:53.478225 <5>[ 2.023176] Loading compiled-in X.509 certificates
10664 23:50:53.504868 <4>[ 2.044565] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 23:50:53.515157 <4>[ 2.055246] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 23:50:53.528836 <6>[ 2.074940] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10667 23:50:53.536242 <6>[ 2.081912] xhci-mtk 11200000.usb: xHCI Host Controller
10668 23:50:53.542325 <6>[ 2.087419] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10669 23:50:53.552379 <6>[ 2.095255] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10670 23:50:53.559204 <6>[ 2.104673] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10671 23:50:53.566143 <6>[ 2.110759] xhci-mtk 11200000.usb: xHCI Host Controller
10672 23:50:53.572380 <6>[ 2.116239] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10673 23:50:53.579202 <6>[ 2.123884] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10674 23:50:53.585651 <6>[ 2.131499] hub 1-0:1.0: USB hub found
10675 23:50:53.589101 <6>[ 2.135514] hub 1-0:1.0: 1 port detected
10676 23:50:53.595528 <6>[ 2.139781] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10677 23:50:53.601993 <6>[ 2.148301] hub 2-0:1.0: USB hub found
10678 23:50:53.605424 <6>[ 2.152306] hub 2-0:1.0: 1 port detected
10679 23:50:53.612903 <6>[ 2.159370] mtk-msdc 11f70000.mmc: Got CD GPIO
10680 23:50:53.625058 <6>[ 2.167796] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10681 23:50:53.631374 <6>[ 2.175834] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10682 23:50:53.641463 <4>[ 2.183735] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10683 23:50:53.651455 <6>[ 2.193260] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10684 23:50:53.658218 <6>[ 2.201340] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10685 23:50:53.665224 <6>[ 2.209434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10686 23:50:53.674851 <6>[ 2.217362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10687 23:50:53.681124 <6>[ 2.225179] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10688 23:50:53.691685 <6>[ 2.232996] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10689 23:50:53.701422 <6>[ 2.243624] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10690 23:50:53.708401 <6>[ 2.252006] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10691 23:50:53.718278 <6>[ 2.260344] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10692 23:50:53.724854 <6>[ 2.268682] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10693 23:50:53.735154 <6>[ 2.277020] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10694 23:50:53.741534 <6>[ 2.285360] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10695 23:50:53.750930 <6>[ 2.293697] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10696 23:50:53.757942 <6>[ 2.302036] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10697 23:50:53.767493 <6>[ 2.310374] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10698 23:50:53.774372 <6>[ 2.318716] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10699 23:50:53.784522 <6>[ 2.327056] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10700 23:50:53.790882 <6>[ 2.335394] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10701 23:50:53.800725 <6>[ 2.343732] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10702 23:50:53.811001 <6>[ 2.352070] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10703 23:50:53.817511 <6>[ 2.360409] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10704 23:50:53.824242 <6>[ 2.369145] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10705 23:50:53.830745 <6>[ 2.376334] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10706 23:50:53.837079 <6>[ 2.383115] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10707 23:50:53.843850 <6>[ 2.389885] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10708 23:50:53.850572 <6>[ 2.396815] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10709 23:50:53.860486 <6>[ 2.403662] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10710 23:50:53.870793 <6>[ 2.412791] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10711 23:50:53.880628 <6>[ 2.421912] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10712 23:50:53.890835 <6>[ 2.431212] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10713 23:50:53.900425 <6>[ 2.440680] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10714 23:50:53.906832 <6>[ 2.450149] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10715 23:50:53.917067 <6>[ 2.459270] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10716 23:50:53.927171 <6>[ 2.468742] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10717 23:50:53.936988 <6>[ 2.477860] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10718 23:50:53.947220 <6>[ 2.487155] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10719 23:50:53.956783 <6>[ 2.497315] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10720 23:50:53.966635 <6>[ 2.508988] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10721 23:50:53.973013 <6>[ 2.518763] Trying to probe devices needed for running init ...
10722 23:50:53.996202 <6>[ 2.539133] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10723 23:50:54.024429 <6>[ 2.570327] hub 2-1:1.0: USB hub found
10724 23:50:54.027237 <6>[ 2.574809] hub 2-1:1.0: 3 ports detected
10725 23:50:54.035800 <6>[ 2.582020] hub 2-1:1.0: USB hub found
10726 23:50:54.038992 <6>[ 2.586353] hub 2-1:1.0: 3 ports detected
10727 23:50:54.147704 <6>[ 2.690856] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10728 23:50:54.302529 <6>[ 2.848940] hub 1-1:1.0: USB hub found
10729 23:50:54.305702 <6>[ 2.853436] hub 1-1:1.0: 4 ports detected
10730 23:50:54.316135 <6>[ 2.862359] hub 1-1:1.0: USB hub found
10731 23:50:54.319453 <6>[ 2.866895] hub 1-1:1.0: 4 ports detected
10732 23:50:54.387787 <6>[ 2.931085] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10733 23:50:54.496420 <6>[ 3.039477] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10734 23:50:54.532748 <4>[ 3.076104] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10735 23:50:54.542551 <4>[ 3.085205] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10736 23:50:54.581889 <6>[ 3.128426] r8152 2-1.3:1.0 eth0: v1.12.13
10737 23:50:54.639264 <6>[ 3.182868] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10738 23:50:54.772236 <6>[ 3.318713] hub 1-1.4:1.0: USB hub found
10739 23:50:54.775694 <6>[ 3.323379] hub 1-1.4:1.0: 2 ports detected
10740 23:50:54.784715 <6>[ 3.331659] hub 1-1.4:1.0: USB hub found
10741 23:50:54.788391 <6>[ 3.336245] hub 1-1.4:1.0: 2 ports detected
10742 23:50:55.083452 <6>[ 3.626894] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10743 23:50:55.275224 <6>[ 3.818893] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10744 23:50:56.147123 <6>[ 4.693890] r8152 2-1.3:1.0 eth0: carrier on
10745 23:50:58.768068 <5>[ 4.714629] Sending DHCP requests .., OK
10746 23:50:58.774506 <6>[ 7.318949] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10747 23:50:58.777740 <6>[ 7.327244] IP-Config: Complete:
10748 23:50:58.790938 <6>[ 7.330737] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10749 23:50:58.797755 <6>[ 7.341445] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10750 23:50:58.803991 <6>[ 7.350060] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10751 23:50:58.810587 <6>[ 7.350069] nameserver0=192.168.201.1
10752 23:50:58.814056 <6>[ 7.362209] clk: Disabling unused clocks
10753 23:50:58.817604 <6>[ 7.367886] ALSA device list:
10754 23:50:58.824289 <6>[ 7.371124] No soundcards found.
10755 23:50:58.831725 <6>[ 7.378496] Freeing unused kernel memory: 8512K
10756 23:50:58.835029 <6>[ 7.383474] Run /init as init process
10757 23:50:58.844170 Loading, please wait...
10758 23:50:58.873539 Starting systemd-udevd version 252.22-1~deb12u1
10759 23:50:59.129218 <6>[ 7.672700] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10760 23:50:59.139136 <6>[ 7.681944] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10761 23:50:59.148857 <6>[ 7.690758] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10762 23:50:59.162467 <3>[ 7.705745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 23:50:59.168700 <6>[ 7.707196] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10764 23:50:59.178831 <3>[ 7.713940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 23:50:59.185241 <3>[ 7.713947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 23:50:59.195545 <3>[ 7.714697] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 23:50:59.198854 <6>[ 7.722525] mc: Linux media interface: v0.10
10768 23:50:59.204947 <4>[ 7.722969] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10769 23:50:59.212486 <4>[ 7.723690] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10770 23:50:59.219498 <6>[ 7.724405] remoteproc remoteproc0: scp is available
10771 23:50:59.222834 <6>[ 7.724460] remoteproc remoteproc0: powering up scp
10772 23:50:59.232284 <6>[ 7.724465] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10773 23:50:59.238850 <6>[ 7.724476] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10774 23:50:59.246337 <6>[ 7.726232] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10775 23:50:59.252828 <3>[ 7.745938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 23:50:59.262668 <4>[ 7.748928] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10777 23:50:59.266057 <4>[ 7.748928] Fallback method does not support PEC.
10778 23:50:59.276034 <3>[ 7.764231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10779 23:50:59.282519 <3>[ 7.765411] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 23:50:59.289116 <6>[ 7.776740] videodev: Linux video capture interface: v2.00
10781 23:50:59.296142 <3>[ 7.783773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 23:50:59.306167 <3>[ 7.800423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 23:50:59.315584 <3>[ 7.805239] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 23:50:59.322675 <6>[ 7.824186] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10785 23:50:59.329082 <3>[ 7.827616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 23:50:59.338846 <6>[ 7.830902] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10787 23:50:59.345595 <6>[ 7.835659] pci_bus 0000:00: root bus resource [bus 00-ff]
10788 23:50:59.355595 <6>[ 7.839622] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10789 23:50:59.362154 <6>[ 7.839881] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10790 23:50:59.372029 <3>[ 7.841479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 23:50:59.378805 <6>[ 7.849476] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10792 23:50:59.388753 <6>[ 7.849480] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10793 23:50:59.395079 <6>[ 7.849524] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10794 23:50:59.405391 <6>[ 7.850292] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10795 23:50:59.408814 <6>[ 7.850300] remoteproc remoteproc0: remote processor scp is now up
10796 23:50:59.418597 <6>[ 7.850300] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10797 23:50:59.424667 <3>[ 7.858263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 23:50:59.431246 <3>[ 7.858271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 23:50:59.441487 <3>[ 7.858428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 23:50:59.447940 <6>[ 7.860915] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10801 23:50:59.457864 <6>[ 7.863412] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10802 23:50:59.464451 <6>[ 7.866559] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10803 23:50:59.474666 <3>[ 7.873371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 23:50:59.477481 <6>[ 7.874010] Bluetooth: Core ver 2.22
10805 23:50:59.480503 <6>[ 7.874065] NET: Registered PF_BLUETOOTH protocol family
10806 23:50:59.487600 <6>[ 7.874068] Bluetooth: HCI device and connection manager initialized
10807 23:50:59.493974 <6>[ 7.874083] Bluetooth: HCI socket layer initialized
10808 23:50:59.500333 <6>[ 7.874089] Bluetooth: L2CAP socket layer initialized
10809 23:50:59.504392 <6>[ 7.874098] Bluetooth: SCO socket layer initialized
10810 23:50:59.510162 <6>[ 7.881539] pci 0000:00:00.0: supports D1 D2
10811 23:50:59.517187 <3>[ 7.890745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 23:50:59.523375 <6>[ 7.896478] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10813 23:50:59.530137 <6>[ 7.897561] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10814 23:50:59.543460 <6>[ 7.898575] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10815 23:50:59.549963 <6>[ 7.898673] usbcore: registered new interface driver uvcvideo
10816 23:50:59.556222 <3>[ 7.906559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 23:50:59.566135 <6>[ 7.917112] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10818 23:50:59.573409 <3>[ 7.923663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 23:50:59.582707 <3>[ 7.923688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 23:50:59.589552 <6>[ 7.930902] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10821 23:50:59.592744 <6>[ 7.941570] usbcore: registered new interface driver btusb
10822 23:50:59.599545 <6>[ 7.941787] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10823 23:50:59.609706 <4>[ 7.942284] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 23:50:59.616109 <3>[ 7.942295] Bluetooth: hci0: Failed to load firmware file (-2)
10825 23:50:59.622927 <3>[ 7.942298] Bluetooth: hci0: Failed to set up firmware (-2)
10826 23:50:59.632504 <4>[ 7.942302] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10827 23:50:59.639462 <6>[ 7.946983] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10828 23:50:59.649291 <6>[ 8.192898] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10829 23:50:59.655595 <6>[ 8.200385] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10830 23:50:59.659027 <6>[ 8.207963] pci 0000:01:00.0: supports D1 D2
10831 23:50:59.665530 <6>[ 8.212482] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10832 23:50:59.690403 <6>[ 8.234806] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10833 23:50:59.697161 <6>[ 8.241735] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10834 23:50:59.703766 <6>[ 8.249814] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10835 23:50:59.714100 <6>[ 8.257810] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10836 23:50:59.720462 <6>[ 8.265811] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10837 23:50:59.730483 <6>[ 8.273812] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10838 23:50:59.733896 <6>[ 8.281811] pci 0000:00:00.0: PCI bridge to [bus 01]
10839 23:50:59.743852 <6>[ 8.287027] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10840 23:50:59.750601 <6>[ 8.295145] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10841 23:50:59.756825 <6>[ 8.301987] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10842 23:50:59.763147 <6>[ 8.308845] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10843 23:50:59.787304 <5>[ 8.331322] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10844 23:50:59.809730 <5>[ 8.353489] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10845 23:50:59.816366 <5>[ 8.361096] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10846 23:50:59.825868 <4>[ 8.369602] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10847 23:50:59.832685 <6>[ 8.378537] cfg80211: failed to load regulatory.db
10848 23:50:59.890622 <6>[ 8.434587] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10849 23:50:59.897332 <6>[ 8.442193] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10850 23:50:59.921570 <6>[ 8.469174] mt7921e 0000:01:00.0: ASIC revision: 79610010
10851 23:51:00.027815 <6>[ 8.571013] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10852 23:51:00.030515 <6>[ 8.571013]
10853 23:51:00.034036 Begin: Loading essential drivers ... done.
10854 23:51:00.037399 Begin: Running /scripts/init-premount ... done.
10855 23:51:00.043751 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10856 23:51:00.054171 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10857 23:51:00.056825 Device /sys/class/net/eth0 found
10858 23:51:00.057270 done.
10859 23:51:00.063429 Begin: Waiting up to 180 secs for any network device to become available ... done.
10860 23:51:00.124088 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10861 23:51:00.130685 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10862 23:51:00.137152 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10863 23:51:00.143749 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10864 23:51:00.150789 host : mt8192-asurada-spherion-r0-cbg-8
10865 23:51:00.156788 domain : lava-rack
10866 23:51:00.160751 rootserver: 192.168.201.1 rootpath:
10867 23:51:00.161254 filename :
10868 23:51:00.294938 <6>[ 8.839085] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10869 23:51:00.362780 done.
10870 23:51:00.371628 Begin: Running /scripts/nfs-bottom ... done.
10871 23:51:00.387420 Begin: Running /scripts/init-bottom ... done.
10872 23:51:01.768549 <6>[ 10.316419] NET: Registered PF_INET6 protocol family
10873 23:51:01.776276 <6>[ 10.323815] Segment Routing with IPv6
10874 23:51:01.779646 <6>[ 10.327830] In-situ OAM (IOAM) with IPv6
10875 23:51:01.957615 <30>[ 10.478776] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10876 23:51:01.964131 <30>[ 10.511933] systemd[1]: Detected architecture arm64.
10877 23:51:01.972992
10878 23:51:01.976381 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10879 23:51:01.976460
10880 23:51:02.000337 <30>[ 10.548175] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10881 23:51:03.067131 <30>[ 11.611762] systemd[1]: Queued start job for default target graphical.target.
10882 23:51:03.116042 <30>[ 11.660195] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10883 23:51:03.122454 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10884 23:51:03.144404 <30>[ 11.688721] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10885 23:51:03.154152 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10886 23:51:03.172487 <30>[ 11.716657] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10887 23:51:03.182164 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10888 23:51:03.200234 <30>[ 11.744349] systemd[1]: Created slice user.slice - User and Session Slice.
10889 23:51:03.206194 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10890 23:51:03.230537 <30>[ 11.771716] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10891 23:51:03.240257 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10892 23:51:03.258135 <30>[ 11.799271] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10893 23:51:03.264645 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10894 23:51:03.293365 <30>[ 11.827505] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10895 23:51:03.303046 <30>[ 11.847445] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10896 23:51:03.309330 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10897 23:51:03.327097 <30>[ 11.871241] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10898 23:51:03.336457 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10899 23:51:03.355082 <30>[ 11.899357] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10900 23:51:03.364820 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10901 23:51:03.379413 <30>[ 11.927291] systemd[1]: Reached target paths.target - Path Units.
10902 23:51:03.389826 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10903 23:51:03.406673 <30>[ 11.951317] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10904 23:51:03.413526 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10905 23:51:03.426801 <30>[ 11.974830] systemd[1]: Reached target slices.target - Slice Units.
10906 23:51:03.436961 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10907 23:51:03.451647 <30>[ 11.999351] systemd[1]: Reached target swap.target - Swaps.
10908 23:51:03.458022 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10909 23:51:03.479018 <30>[ 12.023262] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10910 23:51:03.488722 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10911 23:51:03.507137 <30>[ 12.051332] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10912 23:51:03.516523 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10913 23:51:03.538202 <30>[ 12.082656] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10914 23:51:03.548223 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10915 23:51:03.563830 <30>[ 12.108331] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10916 23:51:03.573686 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10917 23:51:03.590879 <30>[ 12.135375] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10918 23:51:03.597584 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10919 23:51:03.615787 <30>[ 12.160263] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10920 23:51:03.625425 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10921 23:51:03.644813 <30>[ 12.189489] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10922 23:51:03.654733 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10923 23:51:03.670543 <30>[ 12.215222] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10924 23:51:03.680659 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10925 23:51:03.722748 <30>[ 12.266885] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10926 23:51:03.729194 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10927 23:51:03.750544 <30>[ 12.295159] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10928 23:51:03.757121 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10929 23:51:03.783732 <30>[ 12.327980] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10930 23:51:03.790091 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10931 23:51:03.817335 <30>[ 12.355092] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10932 23:51:03.859350 <30>[ 12.403629] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10933 23:51:03.869145 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10934 23:51:03.891818 <30>[ 12.436552] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10935 23:51:03.898371 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10936 23:51:03.924243 <30>[ 12.468313] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10937 23:51:03.930701 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10938 23:51:03.954547 <30>[ 12.499232] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10939 23:51:03.961579 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10940 23:51:03.971494 <6>[ 12.516060] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10941 23:51:03.985769 <30>[ 12.530395] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10942 23:51:03.995796 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10943 23:51:04.019872 <30>[ 12.564612] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10944 23:51:04.026769 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10945 23:51:04.050559 <30>[ 12.595197] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10946 23:51:04.060459 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 12.610273] fuse: init (API version 7.37)
10947 23:51:04.063765 .
10948 23:51:04.118843 <30>[ 12.663345] systemd[1]: Starting systemd-journald.service - Journal Service...
10949 23:51:04.125072 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10950 23:51:04.150892 <30>[ 12.695210] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10951 23:51:04.157179 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10952 23:51:04.214821 <30>[ 12.755930] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10953 23:51:04.221106 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10954 23:51:04.243937 <30>[ 12.788527] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10955 23:51:04.253741 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10956 23:51:04.275655 <30>[ 12.820011] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10957 23:51:04.282238 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10958 23:51:04.311505 <30>[ 12.856149] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10959 23:51:04.318290 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10960 23:51:04.331617 <3>[ 12.876242] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 23:51:04.341376 <30>[ 12.885611] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10962 23:51:04.348052 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10963 23:51:04.363268 <3>[ 12.907870] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 23:51:04.373139 <30>[ 12.917301] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10965 23:51:04.379706 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10966 23:51:04.399378 <30>[ 12.943711] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10967 23:51:04.409646 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10968 23:51:04.416668 <3>[ 12.960922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 23:51:04.427557 <30>[ 12.972262] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10970 23:51:04.434261 <30>[ 12.980280] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10971 23:51:04.448059 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 12.992776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 23:51:04.454453 onfigfs…[0m - Load Kernel Module configfs.
10973 23:51:04.468523 <30>[ 13.015804] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10974 23:51:04.479024 <30>[ 13.023749] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10975 23:51:04.489184 <3>[ 13.024641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 23:51:04.495992 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10977 23:51:04.516793 <30>[ 13.060958] systemd[1]: modprobe@drm.service: Deactivated successfully.
10978 23:51:04.523057 <3>[ 13.063949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 23:51:04.533103 <30>[ 13.068846] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10980 23:51:04.539528 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10981 23:51:04.555143 <3>[ 13.099919] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 23:51:04.566631 <30>[ 13.110976] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10983 23:51:04.576731 <30>[ 13.120136] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10984 23:51:04.590131 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Lo<3>[ 13.133859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 23:51:04.593568 ad Kernel Module efi_pstore.
10986 23:51:04.612421 <30>[ 13.156533] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10987 23:51:04.619089 <30>[ 13.164466] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10988 23:51:04.629426 <3>[ 13.166389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 23:51:04.635916 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10990 23:51:04.657306 <30>[ 13.201694] systemd[1]: modprobe@loop.service: Deactivated successfully.
10991 23:51:04.663801 <3>[ 13.207787] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 23:51:04.673955 <30>[ 13.210090] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10993 23:51:04.680373 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10994 23:51:04.700248 <30>[ 13.244822] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10995 23:51:04.709983 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10996 23:51:04.731688 <30>[ 13.272180] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10997 23:51:04.751966 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel c<4>[ 13.289506] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10998 23:51:04.761633 <3>[ 13.305935] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10999 23:51:04.761717 ommand line.
11000 23:51:04.779796 <30>[ 13.324493] systemd[1]: Started systemd-journald.service - Journal Service.
11001 23:51:04.787291 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11002 23:51:04.811630 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11003 23:51:04.832045 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11004 23:51:04.853478 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11005 23:51:04.894486 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11006 23:51:04.915071 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11007 23:51:04.939461 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11008 23:51:04.963625 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11009 23:51:04.987157 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11010 23:51:05.020981 <46>[ 13.565674] systemd-journald[308]: Received client request to flush runtime journal.
11011 23:51:05.035142 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11012 23:51:05.072377 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11013 23:51:05.091582 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11014 23:51:05.112013 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11015 23:51:05.810821 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11016 23:51:06.142666 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11017 23:51:06.199030 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11018 23:51:06.447508 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11019 23:51:06.546627 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11020 23:51:06.562708 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11021 23:51:06.586017 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11022 23:51:06.638745 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11023 23:51:06.664754 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11024 23:51:06.940973 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11025 23:51:07.004979 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11026 23:51:07.058887 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11027 23:51:07.323124 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11028 23:51:07.364490 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11029 23:51:07.390891 <6>[ 15.939256] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11030 23:51:07.411709 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11031 23:51:07.452305 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11032 23:51:07.487533 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11033 23:51:07.560627 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11034 23:51:07.579607 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11035 23:51:07.598800 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11036 23:51:07.642749 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11037 23:51:07.664086 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11038 23:51:07.682790 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11039 23:51:07.708988 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11040 23:51:07.758679 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11041 23:51:07.776681 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11042 23:51:07.798975 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11043 23:51:07.821992 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11044 23:51:07.841910 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11045 23:51:07.866495 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11046 23:51:07.884962 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11047 23:51:07.902487 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11048 23:51:07.921530 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11049 23:51:07.972237 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11050 23:51:07.994021 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11051 23:51:08.016243 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11052 23:51:08.033827 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11053 23:51:08.050510 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11054 23:51:08.099487 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11055 23:51:08.135046 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11056 23:51:08.219575 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11057 23:51:08.246482 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11058 23:51:08.318818 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11059 23:51:08.375186 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11060 23:51:08.408396 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11061 23:51:08.427571 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11062 23:51:08.449869 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11063 23:51:08.480737 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11064 23:51:08.644336 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11065 23:51:08.667826 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11066 23:51:08.688947 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11067 23:51:08.757494 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11068 23:51:08.801087 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11069 23:51:08.861046
11070 23:51:08.864341 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11071 23:51:08.864425
11072 23:51:08.867353 debian-bookworm-arm64 login: root (automatic login)
11073 23:51:08.867434
11074 23:51:09.186530 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11075 23:51:09.186680
11076 23:51:09.193578 The programs included with the Debian GNU/Linux system are free software;
11077 23:51:09.199773 the exact distribution terms for each program are described in the
11078 23:51:09.203614 individual files in /usr/share/doc/*/copyright.
11079 23:51:09.203690
11080 23:51:09.209781 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11081 23:51:09.213364 permitted by applicable law.
11082 23:51:10.319305 Matched prompt #10: / #
11084 23:51:10.319599 Setting prompt string to ['/ #']
11085 23:51:10.319693 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11087 23:51:10.319899 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11088 23:51:10.319986 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11089 23:51:10.320058 Setting prompt string to ['/ #']
11090 23:51:10.320123 Forcing a shell prompt, looking for ['/ #']
11092 23:51:10.370311 / #
11093 23:51:10.370421 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11094 23:51:10.370499 Waiting using forced prompt support (timeout 00:02:30)
11095 23:51:10.375518
11096 23:51:10.375785 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11097 23:51:10.375882 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11099 23:51:10.476227 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte'
11100 23:51:10.481478 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084321/extract-nfsrootfs-oelg8jte'
11102 23:51:10.581962 / # export NFS_SERVER_IP='192.168.201.1'
11103 23:51:10.587601 export NFS_SERVER_IP='192.168.201.1'
11104 23:51:10.587899 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11105 23:51:10.588004 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11106 23:51:10.588092 end: 2 depthcharge-action (duration 00:01:37) [common]
11107 23:51:10.588190 start: 3 lava-test-retry (timeout 00:07:44) [common]
11108 23:51:10.588283 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
11109 23:51:10.588362 Using namespace: common
11111 23:51:10.688663 / # #
11112 23:51:10.688820 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11113 23:51:10.693634 #
11114 23:51:10.693899 Using /lava-14084321
11116 23:51:10.794181 / # export SHELL=/bin/bash
11117 23:51:10.799879 export SHELL=/bin/bash
11119 23:51:10.900440 / # . /lava-14084321/environment
11120 23:51:10.905960 . /lava-14084321/environment
11122 23:51:11.012520 / # /lava-14084321/bin/lava-test-runner /lava-14084321/0
11123 23:51:11.012647 Test shell timeout: 10s (minimum of the action and connection timeout)
11124 23:51:11.017707 /lava-14084321/bin/lava-test-runner /lava-14084321/0
11125 23:51:11.307856 + export TESTRUN_ID=0_timesync-off
11126 23:51:11.310882 + TESTRUN_ID=0_timesync-off
11127 23:51:11.313929 + cd /lava-14084321/0/tests/0_timesync-off
11128 23:51:11.317163 ++ cat uuid
11129 23:51:11.325018 + UUID=14084321_1.6.2.3.1
11130 23:51:11.325101 + set +x
11131 23:51:11.331649 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14084321_1.6.2.3.1>
11132 23:51:11.331909 Received signal: <STARTRUN> 0_timesync-off 14084321_1.6.2.3.1
11133 23:51:11.331993 Starting test lava.0_timesync-off (14084321_1.6.2.3.1)
11134 23:51:11.332123 Skipping test definition patterns.
11135 23:51:11.334603 + systemctl stop systemd-timesyncd
11136 23:51:11.417612 + set +x
11137 23:51:11.421140 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14084321_1.6.2.3.1>
11138 23:51:11.421401 Received signal: <ENDRUN> 0_timesync-off 14084321_1.6.2.3.1
11139 23:51:11.421489 Ending use of test pattern.
11140 23:51:11.421551 Ending test lava.0_timesync-off (14084321_1.6.2.3.1), duration 0.09
11142 23:51:11.507629 + export TESTRUN_ID=1_kselftest-dt
11143 23:51:11.510537 + TESTRUN_ID=1_kselftest-dt
11144 23:51:11.513868 + cd /lava-14084321/0/tests/1_kselftest-dt
11145 23:51:11.517245 ++ cat uuid
11146 23:51:11.523650 + UUID=14084321_1.6.2.3.5
11147 23:51:11.523733 + set +x
11148 23:51:11.530217 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14084321_1.6.2.3.5>
11149 23:51:11.530472 Received signal: <STARTRUN> 1_kselftest-dt 14084321_1.6.2.3.5
11150 23:51:11.530544 Starting test lava.1_kselftest-dt (14084321_1.6.2.3.5)
11151 23:51:11.530624 Skipping test definition patterns.
11152 23:51:11.533780 + cd ./automated/linux/kselftest/
11153 23:51:11.559511 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11154 23:51:11.601462 INFO: install_deps skipped
11155 23:51:12.109892 --2024-05-29 23:51:12-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11156 23:51:12.116138 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11157 23:51:12.243727 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11158 23:51:12.376778 HTTP request sent, awaiting response... 200 OK
11159 23:51:12.380047 Length: 1642292 (1.6M) [application/octet-stream]
11160 23:51:12.383184 Saving to: 'kselftest_armhf.tar.gz'
11161 23:51:12.383260
11162 23:51:12.383330
11163 23:51:12.642649 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11164 23:51:12.909272 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11165 23:51:13.174195 kselftest_armhf.tar 13%[=> ] 219.84K 425KB/s
11166 23:51:13.402533 kselftest_armhf.tar 56%[==========> ] 898.59K 1.13MB/s
11167 23:51:13.668687 kselftest_armhf.tar 85%[================> ] 1.34M 1.34MB/s
11168 23:51:13.935879 kselftest_armhf.tar 86%[================> ] 1.36M 1.08MB/s
11169 23:51:14.119738 kselftest_armhf.tar 90%[=================> ] 1.41M 951KB/s
11170 23:51:14.126652 kselftest_armhf.tar 100%[===================>] 1.57M 944KB/s in 1.7s
11171 23:51:14.126810
11172 23:51:14.271474 2024-05-29 23:51:14 (944 KB/s) - 'kselftest_armhf.tar.gz' saved [1642292/1642292]
11173 23:51:14.271627
11174 23:51:18.722133 skiplist:
11175 23:51:18.725696 ========================================
11176 23:51:18.728551 ========================================
11177 23:51:18.801327 ============== Tests to run ===============
11178 23:51:18.804765 ===========End Tests to run ===============
11179 23:51:18.810925 shardfile-dt fail
11180 23:51:18.834650 ./kselftest.sh: 131: cannot open /lava-14084321/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11181 23:51:18.837795 + ../../utils/send-to-lava.sh ./output/result.txt
11182 23:51:18.917186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11183 23:51:18.917334 + set +x
11184 23:51:18.917623 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11186 23:51:18.923753 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14084321_1.6.2.3.5>
11187 23:51:18.924007 Received signal: <ENDRUN> 1_kselftest-dt 14084321_1.6.2.3.5
11188 23:51:18.924081 Ending use of test pattern.
11189 23:51:18.924143 Ending test lava.1_kselftest-dt (14084321_1.6.2.3.5), duration 7.39
11191 23:51:18.924359 ok: lava_test_shell seems to have completed
11192 23:51:18.924449 shardfile-dt: fail
11193 23:51:18.924537 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11194 23:51:18.924652 end: 3 lava-test-retry (duration 00:00:08) [common]
11195 23:51:18.924739 start: 4 finalize (timeout 00:07:36) [common]
11196 23:51:18.924837 start: 4.1 power-off (timeout 00:00:30) [common]
11197 23:51:18.924985 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11198 23:51:19.001033 >> Command sent successfully.
11199 23:51:19.003844 Returned 0 in 0 seconds
11200 23:51:19.104206 end: 4.1 power-off (duration 00:00:00) [common]
11202 23:51:19.104548 start: 4.2 read-feedback (timeout 00:07:36) [common]
11204 23:51:19.105122 Listened to connection for namespace 'common' for up to 1s
11205 23:51:20.105779 Finalising connection for namespace 'common'
11206 23:51:20.105953 Disconnecting from shell: Finalise
11207 23:51:20.106030 / #
11208 23:51:20.206350 end: 4.2 read-feedback (duration 00:00:01) [common]
11209 23:51:20.206530 end: 4 finalize (duration 00:00:01) [common]
11210 23:51:20.206642 Cleaning after the job
11211 23:51:20.206741 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/ramdisk
11212 23:51:20.209044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/kernel
11213 23:51:20.220934 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/dtb
11214 23:51:20.221128 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/nfsrootfs
11215 23:51:20.286114 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084321/tftp-deploy-8g3zsbyk/modules
11216 23:51:20.292435 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084321
11217 23:51:20.851747 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084321
11218 23:51:20.851931 Job finished correctly