Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 23:58:16.049755 lava-dispatcher, installed at version: 2024.03
2 23:58:16.049971 start: 0 validate
3 23:58:16.050113 Start time: 2024-05-29 23:58:16.050105+00:00 (UTC)
4 23:58:16.050241 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:58:16.050379 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:58:16.312403 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:58:16.312587 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:58:16.578202 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:58:16.578368 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:58:16.835728 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:58:16.835963 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:58:17.093154 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:58:17.093349 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:58:17.361114 validate duration: 1.31
16 23:58:17.361566 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:58:17.361738 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:58:17.361884 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:58:17.362081 Not decompressing ramdisk as can be used compressed.
20 23:58:17.362233 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:58:17.362355 saving as /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/ramdisk/initrd.cpio.gz
22 23:58:17.362481 total size: 5628169 (5 MB)
23 23:58:17.364209 progress 0 % (0 MB)
24 23:58:17.366883 progress 5 % (0 MB)
25 23:58:17.369422 progress 10 % (0 MB)
26 23:58:17.371567 progress 15 % (0 MB)
27 23:58:17.374019 progress 20 % (1 MB)
28 23:58:17.376169 progress 25 % (1 MB)
29 23:58:17.378547 progress 30 % (1 MB)
30 23:58:17.380920 progress 35 % (1 MB)
31 23:58:17.383009 progress 40 % (2 MB)
32 23:58:17.385463 progress 45 % (2 MB)
33 23:58:17.387557 progress 50 % (2 MB)
34 23:58:17.389984 progress 55 % (2 MB)
35 23:58:17.392343 progress 60 % (3 MB)
36 23:58:17.394476 progress 65 % (3 MB)
37 23:58:17.396790 progress 70 % (3 MB)
38 23:58:17.398261 progress 75 % (4 MB)
39 23:58:17.399885 progress 80 % (4 MB)
40 23:58:17.401408 progress 85 % (4 MB)
41 23:58:17.402981 progress 90 % (4 MB)
42 23:58:17.404732 progress 95 % (5 MB)
43 23:58:17.406130 progress 100 % (5 MB)
44 23:58:17.406341 5 MB downloaded in 0.04 s (122.37 MB/s)
45 23:58:17.406525 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:58:17.406791 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:58:17.407019 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:58:17.407130 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:58:17.407285 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:58:17.407372 saving as /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/kernel/Image
52 23:58:17.407436 total size: 54682112 (52 MB)
53 23:58:17.407499 No compression specified
54 23:58:17.408733 progress 0 % (0 MB)
55 23:58:17.423432 progress 5 % (2 MB)
56 23:58:17.437704 progress 10 % (5 MB)
57 23:58:17.452142 progress 15 % (7 MB)
58 23:58:17.466565 progress 20 % (10 MB)
59 23:58:17.480957 progress 25 % (13 MB)
60 23:58:17.495100 progress 30 % (15 MB)
61 23:58:17.509401 progress 35 % (18 MB)
62 23:58:17.523980 progress 40 % (20 MB)
63 23:58:17.538131 progress 45 % (23 MB)
64 23:58:17.552706 progress 50 % (26 MB)
65 23:58:17.567033 progress 55 % (28 MB)
66 23:58:17.582165 progress 60 % (31 MB)
67 23:58:17.596668 progress 65 % (33 MB)
68 23:58:17.611217 progress 70 % (36 MB)
69 23:58:17.625901 progress 75 % (39 MB)
70 23:58:17.640502 progress 80 % (41 MB)
71 23:58:17.655249 progress 85 % (44 MB)
72 23:58:17.669665 progress 90 % (46 MB)
73 23:58:17.684656 progress 95 % (49 MB)
74 23:58:17.699632 progress 100 % (52 MB)
75 23:58:17.700003 52 MB downloaded in 0.29 s (178.25 MB/s)
76 23:58:17.700194 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:58:17.700530 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:58:17.700654 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:58:17.700776 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:58:17.700942 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:58:17.701068 saving as /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/dtb/mt8192-asurada-spherion-r0.dtb
83 23:58:17.701278 total size: 47258 (0 MB)
84 23:58:17.701375 No compression specified
85 23:58:17.702660 progress 69 % (0 MB)
86 23:58:17.702964 progress 100 % (0 MB)
87 23:58:17.703158 0 MB downloaded in 0.00 s (24.00 MB/s)
88 23:58:17.703320 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:58:17.703567 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:58:17.703672 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:58:17.703774 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:58:17.703890 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:58:17.704012 saving as /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/nfsrootfs/full.rootfs.tar
95 23:58:17.704078 total size: 120894716 (115 MB)
96 23:58:17.704180 Using unxz to decompress xz
97 23:58:17.709927 progress 0 % (0 MB)
98 23:58:18.075853 progress 5 % (5 MB)
99 23:58:18.452628 progress 10 % (11 MB)
100 23:58:18.860688 progress 15 % (17 MB)
101 23:58:19.231800 progress 20 % (23 MB)
102 23:58:19.580506 progress 25 % (28 MB)
103 23:58:19.944587 progress 30 % (34 MB)
104 23:58:20.312694 progress 35 % (40 MB)
105 23:58:20.483602 progress 40 % (46 MB)
106 23:58:20.679252 progress 45 % (51 MB)
107 23:58:21.045200 progress 50 % (57 MB)
108 23:58:21.437665 progress 55 % (63 MB)
109 23:58:21.786827 progress 60 % (69 MB)
110 23:58:22.204874 progress 65 % (74 MB)
111 23:58:22.635552 progress 70 % (80 MB)
112 23:58:23.041623 progress 75 % (86 MB)
113 23:58:23.403412 progress 80 % (92 MB)
114 23:58:23.777398 progress 85 % (98 MB)
115 23:58:24.185311 progress 90 % (103 MB)
116 23:58:24.574071 progress 95 % (109 MB)
117 23:58:25.003524 progress 100 % (115 MB)
118 23:58:25.011215 115 MB downloaded in 7.31 s (15.78 MB/s)
119 23:58:25.011573 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:58:25.011920 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:58:25.012038 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:58:25.012162 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:58:25.012400 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:58:25.012486 saving as /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/modules/modules.tar
126 23:58:25.012553 total size: 8601444 (8 MB)
127 23:58:25.012623 Using unxz to decompress xz
128 23:58:25.017256 progress 0 % (0 MB)
129 23:58:25.042032 progress 5 % (0 MB)
130 23:58:25.076432 progress 10 % (0 MB)
131 23:58:25.107358 progress 15 % (1 MB)
132 23:58:25.135719 progress 20 % (1 MB)
133 23:58:25.165221 progress 25 % (2 MB)
134 23:58:25.193316 progress 30 % (2 MB)
135 23:58:25.219959 progress 35 % (2 MB)
136 23:58:25.247016 progress 40 % (3 MB)
137 23:58:25.276590 progress 45 % (3 MB)
138 23:58:25.304029 progress 50 % (4 MB)
139 23:58:25.332844 progress 55 % (4 MB)
140 23:58:25.360857 progress 60 % (4 MB)
141 23:58:25.386160 progress 65 % (5 MB)
142 23:58:25.413668 progress 70 % (5 MB)
143 23:58:25.441203 progress 75 % (6 MB)
144 23:58:25.466308 progress 80 % (6 MB)
145 23:58:25.494013 progress 85 % (7 MB)
146 23:58:25.519693 progress 90 % (7 MB)
147 23:58:25.551184 progress 95 % (7 MB)
148 23:58:25.580488 progress 100 % (8 MB)
149 23:58:25.586105 8 MB downloaded in 0.57 s (14.30 MB/s)
150 23:58:25.586384 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:58:25.586678 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:58:25.586797 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:58:25.586897 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:58:30.059273 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj
156 23:58:30.059518 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:58:30.059668 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 23:58:30.059906 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4
159 23:58:30.060100 makedir: /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin
160 23:58:30.060248 makedir: /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/tests
161 23:58:30.060474 makedir: /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/results
162 23:58:30.060633 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-add-keys
163 23:58:30.060843 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-add-sources
164 23:58:30.061048 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-background-process-start
165 23:58:30.061229 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-background-process-stop
166 23:58:30.061364 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-common-functions
167 23:58:30.061502 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-echo-ipv4
168 23:58:30.061641 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-install-packages
169 23:58:30.061784 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-installed-packages
170 23:58:30.061956 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-os-build
171 23:58:30.062125 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-probe-channel
172 23:58:30.062288 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-probe-ip
173 23:58:30.062465 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-target-ip
174 23:58:30.062625 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-target-mac
175 23:58:30.062789 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-target-storage
176 23:58:30.062966 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-case
177 23:58:30.063129 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-event
178 23:58:30.063288 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-feedback
179 23:58:30.063455 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-raise
180 23:58:30.063614 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-reference
181 23:58:30.063781 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-runner
182 23:58:30.063948 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-set
183 23:58:30.064110 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-test-shell
184 23:58:30.064275 Updating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-add-keys (debian)
185 23:58:30.064513 Updating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-add-sources (debian)
186 23:58:30.064747 Updating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-install-packages (debian)
187 23:58:30.064985 Updating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-installed-packages (debian)
188 23:58:30.065213 Updating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/bin/lava-os-build (debian)
189 23:58:30.065425 Creating /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/environment
190 23:58:30.065590 LAVA metadata
191 23:58:30.065704 - LAVA_JOB_ID=14084370
192 23:58:30.065829 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:58:30.066007 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 23:58:30.066126 skipped lava-vland-overlay
195 23:58:30.066262 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:58:30.066414 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 23:58:30.066529 skipped lava-multinode-overlay
198 23:58:30.066665 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:58:30.066821 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 23:58:30.066954 Loading test definitions
201 23:58:30.067111 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 23:58:30.067247 Using /lava-14084370 at stage 0
203 23:58:30.067728 uuid=14084370_1.6.2.3.1 testdef=None
204 23:58:30.067876 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:58:30.068025 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 23:58:30.068805 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:58:30.069227 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 23:58:30.070165 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:58:30.070593 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 23:58:30.071510 runner path: /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/0/tests/0_timesync-off test_uuid 14084370_1.6.2.3.1
213 23:58:30.071759 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:58:30.072192 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 23:58:30.072324 Using /lava-14084370 at stage 0
217 23:58:30.072500 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:58:30.072650 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/0/tests/1_kselftest-rtc'
219 23:58:32.170192 Running '/usr/bin/git checkout kernelci.org
220 23:58:32.285538 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 23:58:32.286696 uuid=14084370_1.6.2.3.5 testdef=None
222 23:58:32.286947 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 23:58:32.287394 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 23:58:32.288833 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:58:32.289270 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 23:58:32.291150 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:58:32.291596 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 23:58:32.293406 runner path: /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/0/tests/1_kselftest-rtc test_uuid 14084370_1.6.2.3.5
232 23:58:32.293555 BOARD='mt8192-asurada-spherion-r0'
233 23:58:32.293670 BRANCH='cip-gitlab'
234 23:58:32.293785 SKIPFILE='/dev/null'
235 23:58:32.293900 SKIP_INSTALL='True'
236 23:58:32.294008 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:58:32.294122 TST_CASENAME=''
238 23:58:32.294234 TST_CMDFILES='rtc'
239 23:58:32.294471 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:58:32.294873 Creating lava-test-runner.conf files
242 23:58:32.294993 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084370/lava-overlay-11jt1ck4/lava-14084370/0 for stage 0
243 23:58:32.295155 - 0_timesync-off
244 23:58:32.295272 - 1_kselftest-rtc
245 23:58:32.295439 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 23:58:32.295593 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 23:58:40.348469 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:58:40.348678 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 23:58:40.348817 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:58:40.348951 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:58:40.349072 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 23:58:40.516915 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:58:40.517300 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:58:40.517421 extracting modules file /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj
255 23:58:40.782373 extracting modules file /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084370/extract-overlay-ramdisk-eswuhtxu/ramdisk
256 23:58:41.038594 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 23:58:41.038785 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:58:41.038915 [common] Applying overlay to NFS
259 23:58:41.039018 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084370/compress-overlay-u5waamj0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj
260 23:58:42.104792 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:58:42.104956 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:58:42.105057 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:58:42.105198 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:58:42.105323 Building ramdisk /var/lib/lava/dispatcher/tmp/14084370/extract-overlay-ramdisk-eswuhtxu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084370/extract-overlay-ramdisk-eswuhtxu/ramdisk
265 23:58:42.428007 >> 130335 blocks
266 23:58:44.650601 rename /var/lib/lava/dispatcher/tmp/14084370/extract-overlay-ramdisk-eswuhtxu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/ramdisk/ramdisk.cpio.gz
267 23:58:44.651048 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 23:58:44.651203 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 23:58:44.651311 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 23:58:44.651428 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/kernel/Image']
271 23:58:59.222756 Returned 0 in 14 seconds
272 23:58:59.323506 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/kernel/image.itb
273 23:58:59.711210 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:58:59.711587 output: Created: Thu May 30 00:58:59 2024
275 23:58:59.711667 output: Image 0 (kernel-1)
276 23:58:59.711737 output: Description:
277 23:58:59.711804 output: Created: Thu May 30 00:58:59 2024
278 23:58:59.711871 output: Type: Kernel Image
279 23:58:59.711933 output: Compression: lzma compressed
280 23:58:59.711996 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
281 23:58:59.712058 output: Architecture: AArch64
282 23:58:59.712119 output: OS: Linux
283 23:58:59.712180 output: Load Address: 0x00000000
284 23:58:59.712239 output: Entry Point: 0x00000000
285 23:58:59.712303 output: Hash algo: crc32
286 23:58:59.712372 output: Hash value: 907bf91d
287 23:58:59.712451 output: Image 1 (fdt-1)
288 23:58:59.712533 output: Description: mt8192-asurada-spherion-r0
289 23:58:59.712592 output: Created: Thu May 30 00:58:59 2024
290 23:58:59.712658 output: Type: Flat Device Tree
291 23:58:59.712740 output: Compression: uncompressed
292 23:58:59.712804 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:58:59.712869 output: Architecture: AArch64
294 23:58:59.712941 output: Hash algo: crc32
295 23:58:59.713035 output: Hash value: 0f8e4d2e
296 23:58:59.713124 output: Image 2 (ramdisk-1)
297 23:58:59.713221 output: Description: unavailable
298 23:58:59.713319 output: Created: Thu May 30 00:58:59 2024
299 23:58:59.713413 output: Type: RAMDisk Image
300 23:58:59.713502 output: Compression: Unknown Compression
301 23:58:59.713562 output: Data Size: 18729957 Bytes = 18290.97 KiB = 17.86 MiB
302 23:58:59.713636 output: Architecture: AArch64
303 23:58:59.713705 output: OS: Linux
304 23:58:59.713772 output: Load Address: unavailable
305 23:58:59.713845 output: Entry Point: unavailable
306 23:58:59.713902 output: Hash algo: crc32
307 23:58:59.713958 output: Hash value: 92b3e9b8
308 23:58:59.714014 output: Default Configuration: 'conf-1'
309 23:58:59.714070 output: Configuration 0 (conf-1)
310 23:58:59.714126 output: Description: mt8192-asurada-spherion-r0
311 23:58:59.714182 output: Kernel: kernel-1
312 23:58:59.714237 output: Init Ramdisk: ramdisk-1
313 23:58:59.714293 output: FDT: fdt-1
314 23:58:59.714348 output: Loadables: kernel-1
315 23:58:59.714407 output:
316 23:58:59.714643 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 23:58:59.714774 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 23:58:59.714913 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 23:58:59.715061 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 23:58:59.715175 No LXC device requested
321 23:58:59.715293 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:58:59.715417 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 23:58:59.715535 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:58:59.715638 Checking files for TFTP limit of 4294967296 bytes.
325 23:58:59.716353 end: 1 tftp-deploy (duration 00:00:42) [common]
326 23:58:59.716486 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:58:59.716604 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:58:59.716783 substitutions:
329 23:58:59.716888 - {DTB}: 14084370/tftp-deploy-psre5b8m/dtb/mt8192-asurada-spherion-r0.dtb
330 23:58:59.716991 - {INITRD}: 14084370/tftp-deploy-psre5b8m/ramdisk/ramdisk.cpio.gz
331 23:58:59.717086 - {KERNEL}: 14084370/tftp-deploy-psre5b8m/kernel/Image
332 23:58:59.717178 - {LAVA_MAC}: None
333 23:58:59.717269 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj
334 23:58:59.717360 - {NFS_SERVER_IP}: 192.168.201.1
335 23:58:59.717450 - {PRESEED_CONFIG}: None
336 23:58:59.717520 - {PRESEED_LOCAL}: None
337 23:58:59.717580 - {RAMDISK}: 14084370/tftp-deploy-psre5b8m/ramdisk/ramdisk.cpio.gz
338 23:58:59.717638 - {ROOT_PART}: None
339 23:58:59.717696 - {ROOT}: None
340 23:58:59.717753 - {SERVER_IP}: 192.168.201.1
341 23:58:59.717810 - {TEE}: None
342 23:58:59.717866 Parsed boot commands:
343 23:58:59.717922 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:58:59.718127 Parsed boot commands: tftpboot 192.168.201.1 14084370/tftp-deploy-psre5b8m/kernel/image.itb 14084370/tftp-deploy-psre5b8m/kernel/cmdline
345 23:58:59.718232 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:58:59.718326 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:58:59.718443 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:58:59.718569 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:58:59.718679 Not connected, no need to disconnect.
350 23:58:59.718790 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:58:59.718897 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:58:59.718970 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:58:59.722656 Setting prompt string to ['lava-test: # ']
354 23:58:59.723120 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:58:59.723283 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:58:59.723436 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:58:59.723538 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:58:59.723893 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 23:59:04.853789 >> Command sent successfully.
360 23:59:04.857179 Returned 0 in 5 seconds
361 23:59:04.957576 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:59:04.957933 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:59:04.958057 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:59:04.958200 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:59:04.958327 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:59:04.958452 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:59:04.959140 [Enter `^Ec?' for help]
369 23:59:05.130315
370 23:59:05.130530
371 23:59:05.130638 F0: 102B 0000
372 23:59:05.130729
373 23:59:05.130815 F3: 1001 0000 [0200]
374 23:59:05.130920
375 23:59:05.133652 F3: 1001 0000
376 23:59:05.133744
377 23:59:05.133879 F7: 102D 0000
378 23:59:05.133963
379 23:59:05.134045 F1: 0000 0000
380 23:59:05.136928
381 23:59:05.137048 V0: 0000 0000 [0001]
382 23:59:05.137167
383 23:59:05.137290 00: 0007 8000
384 23:59:05.140362
385 23:59:05.140477 01: 0000 0000
386 23:59:05.140548
387 23:59:05.140613 BP: 0C00 0209 [0000]
388 23:59:05.140675
389 23:59:05.143632 G0: 1182 0000
390 23:59:05.143765
391 23:59:05.143833 EC: 0000 0021 [4000]
392 23:59:05.143897
393 23:59:05.146986 S7: 0000 0000 [0000]
394 23:59:05.147072
395 23:59:05.147139 CC: 0000 0000 [0001]
396 23:59:05.150459
397 23:59:05.150571 T0: 0000 0040 [010F]
398 23:59:05.150668
399 23:59:05.150760 Jump to BL
400 23:59:05.150850
401 23:59:05.177063
402 23:59:05.177235
403 23:59:05.184003 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 23:59:05.187914 ARM64: Exception handlers installed.
405 23:59:05.191096 ARM64: Testing exception
406 23:59:05.194366 ARM64: Done test exception
407 23:59:05.201237 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 23:59:05.211187 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 23:59:05.218294 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 23:59:05.228438 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 23:59:05.235150 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 23:59:05.242017 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 23:59:05.254232 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 23:59:05.260754 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 23:59:05.279565 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 23:59:05.282811 WDT: Last reset was cold boot
417 23:59:05.285953 SPI1(PAD0) initialized at 2873684 Hz
418 23:59:05.289723 SPI5(PAD0) initialized at 992727 Hz
419 23:59:05.292787 VBOOT: Loading verstage.
420 23:59:05.299737 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 23:59:05.303051 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 23:59:05.306505 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 23:59:05.309884 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 23:59:05.317298 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 23:59:05.323985 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 23:59:05.334584 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 23:59:05.334712
428 23:59:05.334827
429 23:59:05.344972 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 23:59:05.348560 ARM64: Exception handlers installed.
431 23:59:05.348701 ARM64: Testing exception
432 23:59:05.352005 ARM64: Done test exception
433 23:59:05.355354 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 23:59:05.362130 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 23:59:05.375494 Probing TPM: . done!
436 23:59:05.375634 TPM ready after 0 ms
437 23:59:05.382844 Connected to device vid:did:rid of 1ae0:0028:00
438 23:59:05.389450 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 23:59:05.449216 Initialized TPM device CR50 revision 0
440 23:59:05.459587 tlcl_send_startup: Startup return code is 0
441 23:59:05.459712 TPM: setup succeeded
442 23:59:05.470946 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 23:59:05.479954 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 23:59:05.492450 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 23:59:05.502165 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 23:59:05.505951 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 23:59:05.509267 in-header: 03 07 00 00 08 00 00 00
448 23:59:05.513461 in-data: aa e4 47 04 13 02 00 00
449 23:59:05.513560 Chrome EC: UHEPI supported
450 23:59:05.519905 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 23:59:05.525331 in-header: 03 95 00 00 08 00 00 00
452 23:59:05.528693 in-data: 18 20 20 08 00 00 00 00
453 23:59:05.528789 Phase 1
454 23:59:05.532030 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 23:59:05.539856 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 23:59:05.547417 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 23:59:05.547525 Recovery requested (1009000e)
458 23:59:05.557619 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:59:05.563005 tlcl_extend: response is 0
460 23:59:05.572791 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:59:05.577990 tlcl_extend: response is 0
462 23:59:05.585013 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:59:05.604786 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 23:59:05.611565 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:59:05.611662
466 23:59:05.611734
467 23:59:05.621632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:59:05.625054 ARM64: Exception handlers installed.
469 23:59:05.628171 ARM64: Testing exception
470 23:59:05.628270 ARM64: Done test exception
471 23:59:05.650692 pmic_efuse_setting: Set efuses in 11 msecs
472 23:59:05.653433 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:59:05.660405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:59:05.664432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:59:05.667759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:59:05.674542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:59:05.678672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:59:05.681973 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:59:05.689678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:59:05.693372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:59:05.697159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:59:05.704253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:59:05.707577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:59:05.711313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:59:05.714697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:59:05.723087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:59:05.726700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:59:05.734196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:59:05.741404 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:59:05.745419 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:59:05.752602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:59:05.756439 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:59:05.764041 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:59:05.767385 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:59:05.774934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:59:05.778960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:59:05.782449 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:59:05.789804 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:59:05.793536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:59:05.801159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:59:05.804219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:59:05.808286 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:59:05.815674 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:59:05.818838 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:59:05.822565 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:59:05.830026 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:59:05.833669 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:59:05.841409 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:59:05.845189 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:59:05.848671 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:59:05.852880 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:59:05.859326 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:59:05.863306 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:59:05.866668 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:59:05.870585 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:59:05.873964 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:59:05.881589 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:59:05.885450 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:59:05.888902 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:59:05.893067 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:59:05.896883 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:59:05.899944 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:59:05.904174 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:59:05.914931 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 23:59:05.922673 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:59:05.925749 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:59:05.933167 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:59:05.944424 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:59:05.947914 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:59:05.951674 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:59:05.954940 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:59:05.963750 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
533 23:59:05.967081 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:59:05.976036 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 23:59:05.979424 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:59:05.988466 [RTC]rtc_get_frequency_meter,154: input=15, output=760
537 23:59:05.997858 [RTC]rtc_get_frequency_meter,154: input=23, output=942
538 23:59:06.007014 [RTC]rtc_get_frequency_meter,154: input=19, output=848
539 23:59:06.016551 [RTC]rtc_get_frequency_meter,154: input=17, output=804
540 23:59:06.026016 [RTC]rtc_get_frequency_meter,154: input=16, output=783
541 23:59:06.035306 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 23:59:06.045401 [RTC]rtc_get_frequency_meter,154: input=17, output=804
543 23:59:06.048933 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 23:59:06.055978 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 23:59:06.059593 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:59:06.063161 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 23:59:06.066806 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:59:06.070809 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 23:59:06.074331 ADC[4]: Raw value=906573 ID=7
550 23:59:06.078133 ADC[3]: Raw value=213441 ID=1
551 23:59:06.078230 RAM Code: 0x71
552 23:59:06.081297 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:59:06.089246 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:59:06.096722 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 23:59:06.104323 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 23:59:06.104433 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:59:06.108066 in-header: 03 07 00 00 08 00 00 00
558 23:59:06.111326 in-data: aa e4 47 04 13 02 00 00
559 23:59:06.115337 Chrome EC: UHEPI supported
560 23:59:06.122213 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:59:06.125557 in-header: 03 95 00 00 08 00 00 00
562 23:59:06.129157 in-data: 18 20 20 08 00 00 00 00
563 23:59:06.132976 MRC: failed to locate region type 0.
564 23:59:06.140475 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:59:06.143851 DRAM-K: Running full calibration
566 23:59:06.148034 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 23:59:06.151427 header.status = 0x0
568 23:59:06.155235 header.version = 0x6 (expected: 0x6)
569 23:59:06.159311 header.size = 0xd00 (expected: 0xd00)
570 23:59:06.159403 header.flags = 0x0
571 23:59:06.165842 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:59:06.183161 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 23:59:06.190588 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:59:06.194691 dram_init: ddr_geometry: 2
575 23:59:06.194803 [EMI] MDL number = 2
576 23:59:06.198167 [EMI] Get MDL freq = 0
577 23:59:06.198260 dram_init: ddr_type: 0
578 23:59:06.201940 is_discrete_lpddr4: 1
579 23:59:06.205367 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:59:06.205457
581 23:59:06.205526
582 23:59:06.205591 [Bian_co] ETT version 0.0.0.1
583 23:59:06.213587 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 23:59:06.213679
585 23:59:06.217467 dramc_set_vcore_voltage set vcore to 650000
586 23:59:06.217558 Read voltage for 800, 4
587 23:59:06.217640 Vio18 = 0
588 23:59:06.220791 Vcore = 650000
589 23:59:06.220888 Vdram = 0
590 23:59:06.220961 Vddq = 0
591 23:59:06.224853 Vmddr = 0
592 23:59:06.224959 dram_init: config_dvfs: 1
593 23:59:06.228753 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:59:06.236032 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:59:06.239995 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
596 23:59:06.243412 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
597 23:59:06.246802 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 23:59:06.250857 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 23:59:06.254146 MEM_TYPE=3, freq_sel=18
600 23:59:06.254240 sv_algorithm_assistance_LP4_1600
601 23:59:06.261511 ============ PULL DRAM RESETB DOWN ============
602 23:59:06.264841 ========== PULL DRAM RESETB DOWN end =========
603 23:59:06.268971 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:59:06.272214 ===================================
605 23:59:06.276143 LPDDR4 DRAM CONFIGURATION
606 23:59:06.276260 ===================================
607 23:59:06.279892 EX_ROW_EN[0] = 0x0
608 23:59:06.283734 EX_ROW_EN[1] = 0x0
609 23:59:06.283833 LP4Y_EN = 0x0
610 23:59:06.283905 WORK_FSP = 0x0
611 23:59:06.287647 WL = 0x2
612 23:59:06.287740 RL = 0x2
613 23:59:06.290720 BL = 0x2
614 23:59:06.290837 RPST = 0x0
615 23:59:06.293955 RD_PRE = 0x0
616 23:59:06.294044 WR_PRE = 0x1
617 23:59:06.297559 WR_PST = 0x0
618 23:59:06.297651 DBI_WR = 0x0
619 23:59:06.300712 DBI_RD = 0x0
620 23:59:06.303839 OTF = 0x1
621 23:59:06.307122 ===================================
622 23:59:06.307213 ===================================
623 23:59:06.310773 ANA top config
624 23:59:06.313940 ===================================
625 23:59:06.317382 DLL_ASYNC_EN = 0
626 23:59:06.317474 ALL_SLAVE_EN = 1
627 23:59:06.320681 NEW_RANK_MODE = 1
628 23:59:06.323817 DLL_IDLE_MODE = 1
629 23:59:06.327142 LP45_APHY_COMB_EN = 1
630 23:59:06.331680 TX_ODT_DIS = 1
631 23:59:06.331782 NEW_8X_MODE = 1
632 23:59:06.334446 ===================================
633 23:59:06.338432 ===================================
634 23:59:06.341624 data_rate = 1600
635 23:59:06.344942 CKR = 1
636 23:59:06.348368 DQ_P2S_RATIO = 8
637 23:59:06.351649 ===================================
638 23:59:06.351739 CA_P2S_RATIO = 8
639 23:59:06.355031 DQ_CA_OPEN = 0
640 23:59:06.358285 DQ_SEMI_OPEN = 0
641 23:59:06.361433 CA_SEMI_OPEN = 0
642 23:59:06.364678 CA_FULL_RATE = 0
643 23:59:06.368115 DQ_CKDIV4_EN = 1
644 23:59:06.368253 CA_CKDIV4_EN = 1
645 23:59:06.371504 CA_PREDIV_EN = 0
646 23:59:06.374922 PH8_DLY = 0
647 23:59:06.378324 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:59:06.381447 DQ_AAMCK_DIV = 4
649 23:59:06.384579 CA_AAMCK_DIV = 4
650 23:59:06.384703 CA_ADMCK_DIV = 4
651 23:59:06.388544 DQ_TRACK_CA_EN = 0
652 23:59:06.391589 CA_PICK = 800
653 23:59:06.394831 CA_MCKIO = 800
654 23:59:06.398522 MCKIO_SEMI = 0
655 23:59:06.402352 PLL_FREQ = 3068
656 23:59:06.402442 DQ_UI_PI_RATIO = 32
657 23:59:06.405448 CA_UI_PI_RATIO = 0
658 23:59:06.409282 ===================================
659 23:59:06.413417 ===================================
660 23:59:06.416697 memory_type:LPDDR4
661 23:59:06.416813 GP_NUM : 10
662 23:59:06.420533 SRAM_EN : 1
663 23:59:06.420619 MD32_EN : 0
664 23:59:06.423730 ===================================
665 23:59:06.427486 [ANA_INIT] >>>>>>>>>>>>>>
666 23:59:06.431491 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:59:06.435016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:59:06.435150 ===================================
669 23:59:06.438384 data_rate = 1600,PCW = 0X7600
670 23:59:06.441813 ===================================
671 23:59:06.445030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:59:06.451611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:59:06.458416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:59:06.461874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:59:06.464506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:59:06.468272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:59:06.471711 [ANA_INIT] flow start
678 23:59:06.471847 [ANA_INIT] PLL >>>>>>>>
679 23:59:06.475121 [ANA_INIT] PLL <<<<<<<<
680 23:59:06.477964 [ANA_INIT] MIDPI >>>>>>>>
681 23:59:06.478080 [ANA_INIT] MIDPI <<<<<<<<
682 23:59:06.481381 [ANA_INIT] DLL >>>>>>>>
683 23:59:06.484766 [ANA_INIT] flow end
684 23:59:06.488076 ============ LP4 DIFF to SE enter ============
685 23:59:06.491308 ============ LP4 DIFF to SE exit ============
686 23:59:06.495250 [ANA_INIT] <<<<<<<<<<<<<
687 23:59:06.498481 [Flow] Enable top DCM control >>>>>
688 23:59:06.501453 [Flow] Enable top DCM control <<<<<
689 23:59:06.504933 Enable DLL master slave shuffle
690 23:59:06.508251 ==============================================================
691 23:59:06.511447 Gating Mode config
692 23:59:06.518424 ==============================================================
693 23:59:06.518547 Config description:
694 23:59:06.528433 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:59:06.534914 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:59:06.538223 SELPH_MODE 0: By rank 1: By Phase
697 23:59:06.545148 ==============================================================
698 23:59:06.548125 GAT_TRACK_EN = 1
699 23:59:06.551836 RX_GATING_MODE = 2
700 23:59:06.555082 RX_GATING_TRACK_MODE = 2
701 23:59:06.558731 SELPH_MODE = 1
702 23:59:06.561347 PICG_EARLY_EN = 1
703 23:59:06.561438 VALID_LAT_VALUE = 1
704 23:59:06.568094 ==============================================================
705 23:59:06.571457 Enter into Gating configuration >>>>
706 23:59:06.575025 Exit from Gating configuration <<<<
707 23:59:06.578393 Enter into DVFS_PRE_config >>>>>
708 23:59:06.588113 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:59:06.591593 Exit from DVFS_PRE_config <<<<<
710 23:59:06.595133 Enter into PICG configuration >>>>
711 23:59:06.598359 Exit from PICG configuration <<<<
712 23:59:06.601710 [RX_INPUT] configuration >>>>>
713 23:59:06.604863 [RX_INPUT] configuration <<<<<
714 23:59:06.608481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:59:06.615101 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:59:06.621795 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:59:06.628382 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:59:06.635127 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:59:06.638660 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:59:06.645535 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:59:06.648799 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:59:06.651958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:59:06.655176 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:59:06.658339 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:59:06.664976 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:59:06.668418 ===================================
727 23:59:06.671879 LPDDR4 DRAM CONFIGURATION
728 23:59:06.675162 ===================================
729 23:59:06.675274 EX_ROW_EN[0] = 0x0
730 23:59:06.678533 EX_ROW_EN[1] = 0x0
731 23:59:06.678646 LP4Y_EN = 0x0
732 23:59:06.681958 WORK_FSP = 0x0
733 23:59:06.682046 WL = 0x2
734 23:59:06.685544 RL = 0x2
735 23:59:06.685631 BL = 0x2
736 23:59:06.688731 RPST = 0x0
737 23:59:06.688818 RD_PRE = 0x0
738 23:59:06.692177 WR_PRE = 0x1
739 23:59:06.692265 WR_PST = 0x0
740 23:59:06.695615 DBI_WR = 0x0
741 23:59:06.695703 DBI_RD = 0x0
742 23:59:06.698392 OTF = 0x1
743 23:59:06.701748 ===================================
744 23:59:06.705137 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:59:06.708545 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:59:06.715052 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:59:06.718892 ===================================
748 23:59:06.719008 LPDDR4 DRAM CONFIGURATION
749 23:59:06.722150 ===================================
750 23:59:06.725671 EX_ROW_EN[0] = 0x10
751 23:59:06.728697 EX_ROW_EN[1] = 0x0
752 23:59:06.728787 LP4Y_EN = 0x0
753 23:59:06.731890 WORK_FSP = 0x0
754 23:59:06.731979 WL = 0x2
755 23:59:06.735664 RL = 0x2
756 23:59:06.735752 BL = 0x2
757 23:59:06.738499 RPST = 0x0
758 23:59:06.738588 RD_PRE = 0x0
759 23:59:06.741724 WR_PRE = 0x1
760 23:59:06.741812 WR_PST = 0x0
761 23:59:06.745450 DBI_WR = 0x0
762 23:59:06.745539 DBI_RD = 0x0
763 23:59:06.748441 OTF = 0x1
764 23:59:06.751845 ===================================
765 23:59:06.758480 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:59:06.761899 nWR fixed to 40
767 23:59:06.762011 [ModeRegInit_LP4] CH0 RK0
768 23:59:06.765398 [ModeRegInit_LP4] CH0 RK1
769 23:59:06.768573 [ModeRegInit_LP4] CH1 RK0
770 23:59:06.768660 [ModeRegInit_LP4] CH1 RK1
771 23:59:06.771564 match AC timing 13
772 23:59:06.775058 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 23:59:06.778608 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:59:06.785472 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:59:06.788714 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:59:06.795442 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:59:06.795552 [EMI DOE] emi_dcm 0
778 23:59:06.801697 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:59:06.801839 ==
780 23:59:06.805111 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:59:06.808537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:59:06.808628 ==
783 23:59:06.811771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:59:06.818490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:59:06.828596 [CA 0] Center 36 (6~67) winsize 62
786 23:59:06.832078 [CA 1] Center 36 (6~67) winsize 62
787 23:59:06.835076 [CA 2] Center 34 (4~65) winsize 62
788 23:59:06.838757 [CA 3] Center 34 (4~64) winsize 61
789 23:59:06.842120 [CA 4] Center 33 (3~63) winsize 61
790 23:59:06.844872 [CA 5] Center 32 (2~63) winsize 62
791 23:59:06.844959
792 23:59:06.848184 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:59:06.848272
794 23:59:06.851925 [CATrainingPosCal] consider 1 rank data
795 23:59:06.855113 u2DelayCellTimex100 = 270/100 ps
796 23:59:06.858429 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
797 23:59:06.862039 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:59:06.868485 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
799 23:59:06.871894 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
800 23:59:06.875285 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
801 23:59:06.878662 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
802 23:59:06.878822
803 23:59:06.881860 CA PerBit enable=1, Macro0, CA PI delay=32
804 23:59:06.881947
805 23:59:06.884876 [CBTSetCACLKResult] CA Dly = 32
806 23:59:06.884963 CS Dly: 4 (0~35)
807 23:59:06.888280 ==
808 23:59:06.888431 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:59:06.895219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:59:06.895369 ==
811 23:59:06.898428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:59:06.905135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:59:06.914628 [CA 0] Center 36 (6~67) winsize 62
814 23:59:06.918041 [CA 1] Center 36 (6~67) winsize 62
815 23:59:06.921430 [CA 2] Center 34 (4~65) winsize 62
816 23:59:06.924773 [CA 3] Center 33 (3~64) winsize 62
817 23:59:06.927980 [CA 4] Center 32 (2~63) winsize 62
818 23:59:06.931446 [CA 5] Center 32 (2~63) winsize 62
819 23:59:06.931535
820 23:59:06.934836 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 23:59:06.934923
822 23:59:06.938396 [CATrainingPosCal] consider 2 rank data
823 23:59:06.941493 u2DelayCellTimex100 = 270/100 ps
824 23:59:06.944623 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
825 23:59:06.948436 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:59:06.954573 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
827 23:59:06.958142 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
828 23:59:06.961550 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
829 23:59:06.964832 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
830 23:59:06.964957
831 23:59:06.968151 CA PerBit enable=1, Macro0, CA PI delay=32
832 23:59:06.968309
833 23:59:06.971935 [CBTSetCACLKResult] CA Dly = 32
834 23:59:06.972077 CS Dly: 4 (0~36)
835 23:59:06.972191
836 23:59:06.974571 ----->DramcWriteLeveling(PI) begin...
837 23:59:06.978415 ==
838 23:59:06.978533 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:59:06.986135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 23:59:06.986234 ==
841 23:59:06.986304 Write leveling (Byte 0): 32 => 32
842 23:59:06.989440 Write leveling (Byte 1): 30 => 30
843 23:59:06.993492 DramcWriteLeveling(PI) end<-----
844 23:59:06.993582
845 23:59:06.993651 ==
846 23:59:06.996827 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:59:06.999838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 23:59:06.999928 ==
849 23:59:07.003382 [Gating] SW mode calibration
850 23:59:07.010895 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:59:07.017487 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:59:07.020945 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 23:59:07.024472 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 23:59:07.030574 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 23:59:07.033865 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:59:07.037827 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:59:07.043881 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:59:07.047200 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:59:07.051149 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:59:07.057641 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:59:07.061075 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:59:07.064469 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:59:07.067901 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:59:07.074291 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:59:07.077473 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:59:07.081044 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:59:07.087737 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:59:07.091330 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 23:59:07.094638 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 23:59:07.101237 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
871 23:59:07.104452 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:59:07.107663 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:59:07.114674 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:59:07.118024 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:59:07.120974 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:59:07.124854 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:59:07.131100 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:59:07.134844 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
879 23:59:07.137773 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
880 23:59:07.144471 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:59:07.147679 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:59:07.151018 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:59:07.158018 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:59:07.161144 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:59:07.164327 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
886 23:59:07.171575 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 1)
887 23:59:07.174909 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 23:59:07.178017 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:59:07.184319 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:59:07.187591 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:59:07.191421 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:59:07.197948 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:59:07.201197 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
894 23:59:07.204526 0 11 8 | B1->B0 | 2d2d 3b3b | 0 1 | (0 0) (0 0)
895 23:59:07.211382 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
896 23:59:07.214551 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:59:07.217804 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:59:07.221165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:59:07.228146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:59:07.231468 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:59:07.234557 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 23:59:07.241005 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
903 23:59:07.244745 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:59:07.247917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:59:07.254789 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:59:07.257838 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:59:07.260930 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:59:07.268081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:59:07.271180 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:59:07.274309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:59:07.280942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:59:07.284716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:59:07.287937 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:59:07.294429 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:59:07.297663 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:59:07.301556 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:59:07.307955 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 23:59:07.311214 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
919 23:59:07.314361 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 23:59:07.318266 Total UI for P1: 0, mck2ui 16
921 23:59:07.321434 best dqsien dly found for B0: ( 0, 14, 6)
922 23:59:07.324999 Total UI for P1: 0, mck2ui 16
923 23:59:07.328673 best dqsien dly found for B1: ( 0, 14, 8)
924 23:59:07.332004 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 23:59:07.335450 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 23:59:07.335553
927 23:59:07.339142 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 23:59:07.342371 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:59:07.345561 [Gating] SW calibration Done
930 23:59:07.345676 ==
931 23:59:07.348838 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:59:07.352004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:59:07.352120 ==
934 23:59:07.355378 RX Vref Scan: 0
935 23:59:07.355466
936 23:59:07.355535 RX Vref 0 -> 0, step: 1
937 23:59:07.355600
938 23:59:07.359280 RX Delay -130 -> 252, step: 16
939 23:59:07.365833 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 23:59:07.369072 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 23:59:07.372331 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 23:59:07.375743 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 23:59:07.379097 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 23:59:07.382231 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 23:59:07.389300 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 23:59:07.392290 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
947 23:59:07.395892 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 23:59:07.398830 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
949 23:59:07.402441 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
950 23:59:07.409272 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 23:59:07.412726 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
952 23:59:07.415777 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
953 23:59:07.418928 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
954 23:59:07.422746 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 23:59:07.425850 ==
956 23:59:07.429172 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:59:07.432306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:59:07.432425 ==
959 23:59:07.432546 DQS Delay:
960 23:59:07.435525 DQS0 = 0, DQS1 = 0
961 23:59:07.435651 DQM Delay:
962 23:59:07.439440 DQM0 = 90, DQM1 = 81
963 23:59:07.439570 DQ Delay:
964 23:59:07.442635 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
965 23:59:07.445942 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
966 23:59:07.449279 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
967 23:59:07.452557 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
968 23:59:07.452705
969 23:59:07.452823
970 23:59:07.452939 ==
971 23:59:07.455712 Dram Type= 6, Freq= 0, CH_0, rank 0
972 23:59:07.459057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 23:59:07.459195 ==
974 23:59:07.459312
975 23:59:07.459427
976 23:59:07.462312 TX Vref Scan disable
977 23:59:07.465633 == TX Byte 0 ==
978 23:59:07.468911 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
979 23:59:07.472734 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
980 23:59:07.476028 == TX Byte 1 ==
981 23:59:07.479385 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
982 23:59:07.482476 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
983 23:59:07.482567 ==
984 23:59:07.485747 Dram Type= 6, Freq= 0, CH_0, rank 0
985 23:59:07.489556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 23:59:07.492275 ==
987 23:59:07.503954 TX Vref=22, minBit 3, minWin=27, winSum=448
988 23:59:07.507182 TX Vref=24, minBit 10, minWin=27, winSum=454
989 23:59:07.510404 TX Vref=26, minBit 0, minWin=28, winSum=455
990 23:59:07.513707 TX Vref=28, minBit 8, minWin=28, winSum=457
991 23:59:07.517387 TX Vref=30, minBit 2, minWin=28, winSum=457
992 23:59:07.523929 TX Vref=32, minBit 8, minWin=28, winSum=457
993 23:59:07.527215 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 28
994 23:59:07.527308
995 23:59:07.530484 Final TX Range 1 Vref 28
996 23:59:07.530574
997 23:59:07.530645 ==
998 23:59:07.534039 Dram Type= 6, Freq= 0, CH_0, rank 0
999 23:59:07.537025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 23:59:07.537114 ==
1001 23:59:07.537183
1002 23:59:07.540272
1003 23:59:07.540367 TX Vref Scan disable
1004 23:59:07.543672 == TX Byte 0 ==
1005 23:59:07.547119 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1006 23:59:07.550582 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1007 23:59:07.553872 == TX Byte 1 ==
1008 23:59:07.557007 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1009 23:59:07.560534 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1010 23:59:07.563981
1011 23:59:07.564105 [DATLAT]
1012 23:59:07.564215 Freq=800, CH0 RK0
1013 23:59:07.564322
1014 23:59:07.567064 DATLAT Default: 0xa
1015 23:59:07.567180 0, 0xFFFF, sum = 0
1016 23:59:07.570836 1, 0xFFFF, sum = 0
1017 23:59:07.570974 2, 0xFFFF, sum = 0
1018 23:59:07.573967 3, 0xFFFF, sum = 0
1019 23:59:07.577170 4, 0xFFFF, sum = 0
1020 23:59:07.577306 5, 0xFFFF, sum = 0
1021 23:59:07.580449 6, 0xFFFF, sum = 0
1022 23:59:07.580583 7, 0xFFFF, sum = 0
1023 23:59:07.583587 8, 0xFFFF, sum = 0
1024 23:59:07.583720 9, 0x0, sum = 1
1025 23:59:07.583855 10, 0x0, sum = 2
1026 23:59:07.586814 11, 0x0, sum = 3
1027 23:59:07.586946 12, 0x0, sum = 4
1028 23:59:07.590193 best_step = 10
1029 23:59:07.590323
1030 23:59:07.590440 ==
1031 23:59:07.593416 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 23:59:07.596796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 23:59:07.596889 ==
1034 23:59:07.600706 RX Vref Scan: 1
1035 23:59:07.600841
1036 23:59:07.600961 Set Vref Range= 32 -> 127
1037 23:59:07.604026
1038 23:59:07.604161 RX Vref 32 -> 127, step: 1
1039 23:59:07.604281
1040 23:59:07.607160 RX Delay -95 -> 252, step: 8
1041 23:59:07.607288
1042 23:59:07.610478 Set Vref, RX VrefLevel [Byte0]: 32
1043 23:59:07.613754 [Byte1]: 32
1044 23:59:07.613881
1045 23:59:07.617130 Set Vref, RX VrefLevel [Byte0]: 33
1046 23:59:07.620249 [Byte1]: 33
1047 23:59:07.624230
1048 23:59:07.624367 Set Vref, RX VrefLevel [Byte0]: 34
1049 23:59:07.627555 [Byte1]: 34
1050 23:59:07.631488
1051 23:59:07.631620 Set Vref, RX VrefLevel [Byte0]: 35
1052 23:59:07.634731 [Byte1]: 35
1053 23:59:07.639366
1054 23:59:07.639495 Set Vref, RX VrefLevel [Byte0]: 36
1055 23:59:07.642676 [Byte1]: 36
1056 23:59:07.647750
1057 23:59:07.647865 Set Vref, RX VrefLevel [Byte0]: 37
1058 23:59:07.651125 [Byte1]: 37
1059 23:59:07.654924
1060 23:59:07.655016 Set Vref, RX VrefLevel [Byte0]: 38
1061 23:59:07.658654 [Byte1]: 38
1062 23:59:07.662714
1063 23:59:07.662805 Set Vref, RX VrefLevel [Byte0]: 39
1064 23:59:07.666416 [Byte1]: 39
1065 23:59:07.670790
1066 23:59:07.670881 Set Vref, RX VrefLevel [Byte0]: 40
1067 23:59:07.673655 [Byte1]: 40
1068 23:59:07.677410
1069 23:59:07.677498 Set Vref, RX VrefLevel [Byte0]: 41
1070 23:59:07.681008 [Byte1]: 41
1071 23:59:07.684967
1072 23:59:07.685055 Set Vref, RX VrefLevel [Byte0]: 42
1073 23:59:07.688357 [Byte1]: 42
1074 23:59:07.692995
1075 23:59:07.693096 Set Vref, RX VrefLevel [Byte0]: 43
1076 23:59:07.695671 [Byte1]: 43
1077 23:59:07.699993
1078 23:59:07.700091 Set Vref, RX VrefLevel [Byte0]: 44
1079 23:59:07.703652 [Byte1]: 44
1080 23:59:07.707840
1081 23:59:07.707938 Set Vref, RX VrefLevel [Byte0]: 45
1082 23:59:07.711036 [Byte1]: 45
1083 23:59:07.715579
1084 23:59:07.715699 Set Vref, RX VrefLevel [Byte0]: 46
1085 23:59:07.718783 [Byte1]: 46
1086 23:59:07.722643
1087 23:59:07.722736 Set Vref, RX VrefLevel [Byte0]: 47
1088 23:59:07.725963 [Byte1]: 47
1089 23:59:07.730601
1090 23:59:07.730697 Set Vref, RX VrefLevel [Byte0]: 48
1091 23:59:07.733758 [Byte1]: 48
1092 23:59:07.738474
1093 23:59:07.738569 Set Vref, RX VrefLevel [Byte0]: 49
1094 23:59:07.741646 [Byte1]: 49
1095 23:59:07.745860
1096 23:59:07.745996 Set Vref, RX VrefLevel [Byte0]: 50
1097 23:59:07.748834 [Byte1]: 50
1098 23:59:07.753438
1099 23:59:07.753577 Set Vref, RX VrefLevel [Byte0]: 51
1100 23:59:07.756806 [Byte1]: 51
1101 23:59:07.760704
1102 23:59:07.760841 Set Vref, RX VrefLevel [Byte0]: 52
1103 23:59:07.764376 [Byte1]: 52
1104 23:59:07.768630
1105 23:59:07.768745 Set Vref, RX VrefLevel [Byte0]: 53
1106 23:59:07.771900 [Byte1]: 53
1107 23:59:07.776355
1108 23:59:07.776493 Set Vref, RX VrefLevel [Byte0]: 54
1109 23:59:07.779536 [Byte1]: 54
1110 23:59:07.784050
1111 23:59:07.784186 Set Vref, RX VrefLevel [Byte0]: 55
1112 23:59:07.787169 [Byte1]: 55
1113 23:59:07.791083
1114 23:59:07.791217 Set Vref, RX VrefLevel [Byte0]: 56
1115 23:59:07.794485 [Byte1]: 56
1116 23:59:07.798994
1117 23:59:07.799132 Set Vref, RX VrefLevel [Byte0]: 57
1118 23:59:07.802443 [Byte1]: 57
1119 23:59:07.806907
1120 23:59:07.807052 Set Vref, RX VrefLevel [Byte0]: 58
1121 23:59:07.810094 [Byte1]: 58
1122 23:59:07.814024
1123 23:59:07.814160 Set Vref, RX VrefLevel [Byte0]: 59
1124 23:59:07.817527 [Byte1]: 59
1125 23:59:07.821978
1126 23:59:07.822070 Set Vref, RX VrefLevel [Byte0]: 60
1127 23:59:07.824974 [Byte1]: 60
1128 23:59:07.829180
1129 23:59:07.829271 Set Vref, RX VrefLevel [Byte0]: 61
1130 23:59:07.832392 [Byte1]: 61
1131 23:59:07.836793
1132 23:59:07.836882 Set Vref, RX VrefLevel [Byte0]: 62
1133 23:59:07.840232 [Byte1]: 62
1134 23:59:07.844608
1135 23:59:07.844702 Set Vref, RX VrefLevel [Byte0]: 63
1136 23:59:07.847905 [Byte1]: 63
1137 23:59:07.851836
1138 23:59:07.851922 Set Vref, RX VrefLevel [Byte0]: 64
1139 23:59:07.855216 [Byte1]: 64
1140 23:59:07.859678
1141 23:59:07.859765 Set Vref, RX VrefLevel [Byte0]: 65
1142 23:59:07.863006 [Byte1]: 65
1143 23:59:07.867594
1144 23:59:07.867729 Set Vref, RX VrefLevel [Byte0]: 66
1145 23:59:07.870816 [Byte1]: 66
1146 23:59:07.875143
1147 23:59:07.875273 Set Vref, RX VrefLevel [Byte0]: 67
1148 23:59:07.878192 [Byte1]: 67
1149 23:59:07.882337
1150 23:59:07.882467 Set Vref, RX VrefLevel [Byte0]: 68
1151 23:59:07.886058 [Byte1]: 68
1152 23:59:07.890012
1153 23:59:07.890142 Set Vref, RX VrefLevel [Byte0]: 69
1154 23:59:07.893462 [Byte1]: 69
1155 23:59:07.898033
1156 23:59:07.898134 Set Vref, RX VrefLevel [Byte0]: 70
1157 23:59:07.901280 [Byte1]: 70
1158 23:59:07.905933
1159 23:59:07.906141 Set Vref, RX VrefLevel [Byte0]: 71
1160 23:59:07.908905 [Byte1]: 71
1161 23:59:07.912768
1162 23:59:07.912975 Set Vref, RX VrefLevel [Byte0]: 72
1163 23:59:07.916459 [Byte1]: 72
1164 23:59:07.920383
1165 23:59:07.920560 Set Vref, RX VrefLevel [Byte0]: 73
1166 23:59:07.924237 [Byte1]: 73
1167 23:59:07.928099
1168 23:59:07.928255 Set Vref, RX VrefLevel [Byte0]: 74
1169 23:59:07.931779 [Byte1]: 74
1170 23:59:07.936111
1171 23:59:07.936236 Set Vref, RX VrefLevel [Byte0]: 75
1172 23:59:07.939318 [Byte1]: 75
1173 23:59:07.943152
1174 23:59:07.943289 Set Vref, RX VrefLevel [Byte0]: 76
1175 23:59:07.946320 [Byte1]: 76
1176 23:59:07.951134
1177 23:59:07.951268 Set Vref, RX VrefLevel [Byte0]: 77
1178 23:59:07.954355 [Byte1]: 77
1179 23:59:07.958464
1180 23:59:07.958569 Final RX Vref Byte 0 = 48 to rank0
1181 23:59:07.961815 Final RX Vref Byte 1 = 60 to rank0
1182 23:59:07.964949 Final RX Vref Byte 0 = 48 to rank1
1183 23:59:07.968634 Final RX Vref Byte 1 = 60 to rank1==
1184 23:59:07.971726 Dram Type= 6, Freq= 0, CH_0, rank 0
1185 23:59:07.978235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 23:59:07.978324 ==
1187 23:59:07.978393 DQS Delay:
1188 23:59:07.978456 DQS0 = 0, DQS1 = 0
1189 23:59:07.982197 DQM Delay:
1190 23:59:07.982295 DQM0 = 91, DQM1 = 86
1191 23:59:07.985061 DQ Delay:
1192 23:59:07.988736 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1193 23:59:07.991712 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1194 23:59:07.994897 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1195 23:59:07.998163 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1196 23:59:07.998248
1197 23:59:07.998316
1198 23:59:08.005449 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1199 23:59:08.008890 CH0 RK0: MR19=606, MR18=4D43
1200 23:59:08.015733 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1201 23:59:08.015831
1202 23:59:08.018470 ----->DramcWriteLeveling(PI) begin...
1203 23:59:08.018578 ==
1204 23:59:08.021686 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 23:59:08.024947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 23:59:08.025033 ==
1207 23:59:08.028880 Write leveling (Byte 0): 32 => 32
1208 23:59:08.032088 Write leveling (Byte 1): 32 => 32
1209 23:59:08.035380 DramcWriteLeveling(PI) end<-----
1210 23:59:08.035519
1211 23:59:08.035614 ==
1212 23:59:08.038587 Dram Type= 6, Freq= 0, CH_0, rank 1
1213 23:59:08.041685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1214 23:59:08.041770 ==
1215 23:59:08.045555 [Gating] SW mode calibration
1216 23:59:08.092706 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1217 23:59:08.093170 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1218 23:59:08.093342 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1219 23:59:08.093441 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 23:59:08.093697 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1221 23:59:08.093770 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:59:08.094023 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:59:08.094140 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:59:08.094239 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:59:08.094333 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:59:08.112719 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:59:08.113121 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:59:08.113280 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:59:08.113411 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:59:08.116526 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:59:08.119804 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:59:08.122612 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:59:08.129718 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:59:08.132950 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:59:08.136033 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1236 23:59:08.139635 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1237 23:59:08.146236 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:59:08.149362 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:59:08.153182 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:59:08.159691 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:59:08.162776 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:59:08.166057 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:59:08.173232 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:59:08.176473 0 9 8 | B1->B0 | 2b2b 2b2b | 1 1 | (1 1) (1 1)
1245 23:59:08.179699 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 23:59:08.186277 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 23:59:08.189477 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 23:59:08.193113 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:59:08.199416 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:59:08.203106 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:59:08.206085 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:59:08.212666 0 10 8 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (1 0)
1253 23:59:08.216103 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:59:08.220127 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:59:08.223416 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:59:08.231604 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:59:08.235343 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:59:08.238696 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:59:08.242007 0 11 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1260 23:59:08.245350 0 11 8 | B1->B0 | 3c3c 3b3b | 0 0 | (0 0) (0 0)
1261 23:59:08.252441 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 23:59:08.256263 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 23:59:08.259466 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 23:59:08.263368 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 23:59:08.269757 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:59:08.273080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:59:08.276298 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1268 23:59:08.283514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1269 23:59:08.286711 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1270 23:59:08.289992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:59:08.296236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:59:08.300049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:59:08.303232 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:59:08.309780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:59:08.313023 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:59:08.316775 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:59:08.320002 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:59:08.326487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:59:08.330004 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:59:08.333556 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:59:08.340009 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:59:08.343468 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:59:08.346633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:59:08.353152 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1285 23:59:08.356265 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 23:59:08.359854 Total UI for P1: 0, mck2ui 16
1287 23:59:08.363692 best dqsien dly found for B0: ( 0, 14, 8)
1288 23:59:08.366926 Total UI for P1: 0, mck2ui 16
1289 23:59:08.369707 best dqsien dly found for B1: ( 0, 14, 8)
1290 23:59:08.373611 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1291 23:59:08.376759 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1292 23:59:08.376885
1293 23:59:08.379976 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1294 23:59:08.383196 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1295 23:59:08.386476 [Gating] SW calibration Done
1296 23:59:08.386571 ==
1297 23:59:08.389722 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 23:59:08.392981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 23:59:08.393066 ==
1300 23:59:08.396264 RX Vref Scan: 0
1301 23:59:08.396401
1302 23:59:08.400130 RX Vref 0 -> 0, step: 1
1303 23:59:08.400271
1304 23:59:08.400427 RX Delay -130 -> 252, step: 16
1305 23:59:08.406563 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1306 23:59:08.409853 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1307 23:59:08.413050 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1308 23:59:08.416414 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1309 23:59:08.419682 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1310 23:59:08.426606 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1311 23:59:08.429867 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1312 23:59:08.433161 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1313 23:59:08.436329 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1314 23:59:08.440206 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1315 23:59:08.446498 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1316 23:59:08.450031 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1317 23:59:08.453383 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1318 23:59:08.456415 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1319 23:59:08.460181 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1320 23:59:08.466584 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1321 23:59:08.466714 ==
1322 23:59:08.470021 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 23:59:08.473176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 23:59:08.473339 ==
1325 23:59:08.473482 DQS Delay:
1326 23:59:08.476723 DQS0 = 0, DQS1 = 0
1327 23:59:08.476849 DQM Delay:
1328 23:59:08.479867 DQM0 = 92, DQM1 = 83
1329 23:59:08.479991 DQ Delay:
1330 23:59:08.482982 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1331 23:59:08.486866 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1332 23:59:08.490118 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1333 23:59:08.493336 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1334 23:59:08.493463
1335 23:59:08.493578
1336 23:59:08.493692 ==
1337 23:59:08.496614 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 23:59:08.499993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 23:59:08.500117 ==
1340 23:59:08.503416
1341 23:59:08.503540
1342 23:59:08.503655 TX Vref Scan disable
1343 23:59:08.506529 == TX Byte 0 ==
1344 23:59:08.510273 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1345 23:59:08.513299 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1346 23:59:08.516411 == TX Byte 1 ==
1347 23:59:08.519676 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1348 23:59:08.523544 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1349 23:59:08.523674 ==
1350 23:59:08.526751 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 23:59:08.533433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 23:59:08.533559 ==
1353 23:59:08.545319 TX Vref=22, minBit 8, minWin=27, winSum=448
1354 23:59:08.548109 TX Vref=24, minBit 1, minWin=28, winSum=454
1355 23:59:08.551881 TX Vref=26, minBit 10, minWin=27, winSum=455
1356 23:59:08.555023 TX Vref=28, minBit 7, minWin=28, winSum=458
1357 23:59:08.558301 TX Vref=30, minBit 10, minWin=27, winSum=453
1358 23:59:08.565399 TX Vref=32, minBit 10, minWin=27, winSum=452
1359 23:59:08.568156 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 28
1360 23:59:08.568295
1361 23:59:08.571836 Final TX Range 1 Vref 28
1362 23:59:08.571970
1363 23:59:08.572091 ==
1364 23:59:08.575055 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 23:59:08.578148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 23:59:08.578279 ==
1367 23:59:08.582036
1368 23:59:08.582160
1369 23:59:08.582277 TX Vref Scan disable
1370 23:59:08.585231 == TX Byte 0 ==
1371 23:59:08.588241 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1372 23:59:08.591961 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1373 23:59:08.595210 == TX Byte 1 ==
1374 23:59:08.598852 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1375 23:59:08.602193 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1376 23:59:08.602322
1377 23:59:08.605536 [DATLAT]
1378 23:59:08.605664 Freq=800, CH0 RK1
1379 23:59:08.605780
1380 23:59:08.608736 DATLAT Default: 0xa
1381 23:59:08.608859 0, 0xFFFF, sum = 0
1382 23:59:08.612053 1, 0xFFFF, sum = 0
1383 23:59:08.612178 2, 0xFFFF, sum = 0
1384 23:59:08.615154 3, 0xFFFF, sum = 0
1385 23:59:08.615282 4, 0xFFFF, sum = 0
1386 23:59:08.618529 5, 0xFFFF, sum = 0
1387 23:59:08.618693 6, 0xFFFF, sum = 0
1388 23:59:08.622192 7, 0xFFFF, sum = 0
1389 23:59:08.625391 8, 0xFFFF, sum = 0
1390 23:59:08.625519 9, 0x0, sum = 1
1391 23:59:08.625640 10, 0x0, sum = 2
1392 23:59:08.628695 11, 0x0, sum = 3
1393 23:59:08.628820 12, 0x0, sum = 4
1394 23:59:08.632205 best_step = 10
1395 23:59:08.632330
1396 23:59:08.632483 ==
1397 23:59:08.635248 Dram Type= 6, Freq= 0, CH_0, rank 1
1398 23:59:08.638422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 23:59:08.638550 ==
1400 23:59:08.642149 RX Vref Scan: 0
1401 23:59:08.642277
1402 23:59:08.642393 RX Vref 0 -> 0, step: 1
1403 23:59:08.642507
1404 23:59:08.645323 RX Delay -79 -> 252, step: 8
1405 23:59:08.651815 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1406 23:59:08.655402 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1407 23:59:08.658656 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1408 23:59:08.661884 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1409 23:59:08.665584 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1410 23:59:08.671827 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1411 23:59:08.675403 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1412 23:59:08.679034 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1413 23:59:08.682264 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1414 23:59:08.685332 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1415 23:59:08.688710 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1416 23:59:08.695356 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1417 23:59:08.698461 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1418 23:59:08.702149 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1419 23:59:08.706060 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1420 23:59:08.709004 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1421 23:59:08.712390 ==
1422 23:59:08.715435 Dram Type= 6, Freq= 0, CH_0, rank 1
1423 23:59:08.718717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 23:59:08.718801 ==
1425 23:59:08.718869 DQS Delay:
1426 23:59:08.722154 DQS0 = 0, DQS1 = 0
1427 23:59:08.722239 DQM Delay:
1428 23:59:08.725203 DQM0 = 92, DQM1 = 82
1429 23:59:08.725287 DQ Delay:
1430 23:59:08.728841 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1431 23:59:08.732128 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1432 23:59:08.735388 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1433 23:59:08.738652 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1434 23:59:08.738737
1435 23:59:08.738804
1436 23:59:08.745454 [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1437 23:59:08.748765 CH0 RK1: MR19=606, MR18=4111
1438 23:59:08.755368 CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63
1439 23:59:08.758411 [RxdqsGatingPostProcess] freq 800
1440 23:59:08.765317 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1441 23:59:08.765405 Pre-setting of DQS Precalculation
1442 23:59:08.771594 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1443 23:59:08.771682 ==
1444 23:59:08.775060 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 23:59:08.778234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:59:08.778319 ==
1447 23:59:08.785401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 23:59:08.791807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 23:59:08.800184 [CA 0] Center 36 (6~67) winsize 62
1450 23:59:08.803212 [CA 1] Center 36 (6~67) winsize 62
1451 23:59:08.806457 [CA 2] Center 35 (5~66) winsize 62
1452 23:59:08.809671 [CA 3] Center 35 (5~65) winsize 61
1453 23:59:08.813476 [CA 4] Center 34 (4~65) winsize 62
1454 23:59:08.816477 [CA 5] Center 34 (4~65) winsize 62
1455 23:59:08.816562
1456 23:59:08.820281 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 23:59:08.820391
1458 23:59:08.823494 [CATrainingPosCal] consider 1 rank data
1459 23:59:08.826801 u2DelayCellTimex100 = 270/100 ps
1460 23:59:08.830059 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 23:59:08.833212 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 23:59:08.840136 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1463 23:59:08.843400 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 23:59:08.846638 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 23:59:08.849846 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 23:59:08.849931
1467 23:59:08.853576 CA PerBit enable=1, Macro0, CA PI delay=34
1468 23:59:08.853687
1469 23:59:08.857052 [CBTSetCACLKResult] CA Dly = 34
1470 23:59:08.857135 CS Dly: 6 (0~37)
1471 23:59:08.857202 ==
1472 23:59:08.860068 Dram Type= 6, Freq= 0, CH_1, rank 1
1473 23:59:08.866735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 23:59:08.866821 ==
1475 23:59:08.870644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1476 23:59:08.877058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1477 23:59:08.886895 [CA 0] Center 36 (6~67) winsize 62
1478 23:59:08.890089 [CA 1] Center 37 (6~68) winsize 63
1479 23:59:08.894131 [CA 2] Center 35 (5~66) winsize 62
1480 23:59:08.897280 [CA 3] Center 34 (4~65) winsize 62
1481 23:59:08.900594 [CA 4] Center 35 (5~66) winsize 62
1482 23:59:08.904092 [CA 5] Center 34 (4~65) winsize 62
1483 23:59:08.904223
1484 23:59:08.907836 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1485 23:59:08.907966
1486 23:59:08.911571 [CATrainingPosCal] consider 2 rank data
1487 23:59:08.915487 u2DelayCellTimex100 = 270/100 ps
1488 23:59:08.918873 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1489 23:59:08.922852 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 23:59:08.926352 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1491 23:59:08.929412 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1492 23:59:08.933044 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1493 23:59:08.936355 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 23:59:08.936495
1495 23:59:08.939345 CA PerBit enable=1, Macro0, CA PI delay=34
1496 23:59:08.939470
1497 23:59:08.943116 [CBTSetCACLKResult] CA Dly = 34
1498 23:59:08.943242 CS Dly: 6 (0~38)
1499 23:59:08.943360
1500 23:59:08.946345 ----->DramcWriteLeveling(PI) begin...
1501 23:59:08.949657 ==
1502 23:59:08.949783 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 23:59:08.955931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 23:59:08.956064 ==
1505 23:59:08.959510 Write leveling (Byte 0): 28 => 28
1506 23:59:08.962786 Write leveling (Byte 1): 28 => 28
1507 23:59:08.965963 DramcWriteLeveling(PI) end<-----
1508 23:59:08.966091
1509 23:59:08.966211 ==
1510 23:59:08.969188 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 23:59:08.972928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 23:59:08.973059 ==
1513 23:59:08.976129 [Gating] SW mode calibration
1514 23:59:08.982454 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1515 23:59:08.985996 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1516 23:59:08.992632 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1517 23:59:08.995907 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1518 23:59:08.999156 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:59:09.006493 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:59:09.009683 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:59:09.012679 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:59:09.019419 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:59:09.022585 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:59:09.025850 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:59:09.032961 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:59:09.036138 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:59:09.039454 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:59:09.046414 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:59:09.049615 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:59:09.052718 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:59:09.059685 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:59:09.063000 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:59:09.066086 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1534 23:59:09.069618 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:59:09.076119 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:59:09.079688 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:59:09.082950 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:59:09.089413 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:59:09.093083 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:59:09.096169 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:59:09.102980 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1542 23:59:09.106328 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1543 23:59:09.109614 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 23:59:09.116235 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 23:59:09.119774 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 23:59:09.123349 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:59:09.129986 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:59:09.133091 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1549 23:59:09.136394 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
1550 23:59:09.139604 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1551 23:59:09.146244 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:59:09.149678 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:59:09.153280 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:59:09.160113 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:59:09.163283 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:59:09.166499 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:59:09.173266 0 11 4 | B1->B0 | 2727 3838 | 0 1 | (0 0) (0 0)
1558 23:59:09.176322 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1559 23:59:09.179920 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:59:09.186517 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 23:59:09.190157 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 23:59:09.193372 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:59:09.199801 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:59:09.203539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:59:09.206866 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:59:09.209874 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:59:09.216329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:59:09.220090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:59:09.223209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:59:09.230127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:59:09.233851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:59:09.236839 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:59:09.243378 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:59:09.246663 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:59:09.249913 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:59:09.256579 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:59:09.260319 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:59:09.263470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:59:09.269945 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:59:09.273183 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:59:09.277137 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1582 23:59:09.280258 Total UI for P1: 0, mck2ui 16
1583 23:59:09.283464 best dqsien dly found for B1: ( 0, 14, 2)
1584 23:59:09.286761 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 23:59:09.289962 Total UI for P1: 0, mck2ui 16
1586 23:59:09.293635 best dqsien dly found for B0: ( 0, 14, 4)
1587 23:59:09.300210 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1588 23:59:09.303338 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1589 23:59:09.303423
1590 23:59:09.306817 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1591 23:59:09.310057 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1592 23:59:09.313405 [Gating] SW calibration Done
1593 23:59:09.313489 ==
1594 23:59:09.316630 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 23:59:09.320061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 23:59:09.320145 ==
1597 23:59:09.320213 RX Vref Scan: 0
1598 23:59:09.323319
1599 23:59:09.323402 RX Vref 0 -> 0, step: 1
1600 23:59:09.323469
1601 23:59:09.326553 RX Delay -130 -> 252, step: 16
1602 23:59:09.330326 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1603 23:59:09.333576 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1604 23:59:09.340055 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1605 23:59:09.343760 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1606 23:59:09.347110 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1607 23:59:09.350359 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1608 23:59:09.353633 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1609 23:59:09.360117 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1610 23:59:09.363371 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1611 23:59:09.367092 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1612 23:59:09.370173 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1613 23:59:09.373314 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1614 23:59:09.380260 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1615 23:59:09.383405 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1616 23:59:09.387035 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1617 23:59:09.390255 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1618 23:59:09.390375 ==
1619 23:59:09.393681 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 23:59:09.400086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 23:59:09.400170 ==
1622 23:59:09.400237 DQS Delay:
1623 23:59:09.400314 DQS0 = 0, DQS1 = 0
1624 23:59:09.403779 DQM Delay:
1625 23:59:09.403862 DQM0 = 92, DQM1 = 87
1626 23:59:09.407122 DQ Delay:
1627 23:59:09.410103 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1628 23:59:09.410189 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1629 23:59:09.413618 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1630 23:59:09.417029 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1631 23:59:09.420348
1632 23:59:09.420454
1633 23:59:09.420522 ==
1634 23:59:09.423771 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 23:59:09.426922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 23:59:09.427006 ==
1637 23:59:09.427073
1638 23:59:09.427135
1639 23:59:09.430638 TX Vref Scan disable
1640 23:59:09.430722 == TX Byte 0 ==
1641 23:59:09.437153 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1642 23:59:09.440587 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1643 23:59:09.440685 == TX Byte 1 ==
1644 23:59:09.447131 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1645 23:59:09.450251 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1646 23:59:09.450336 ==
1647 23:59:09.453442 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 23:59:09.456633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 23:59:09.456719 ==
1650 23:59:09.471390 TX Vref=22, minBit 1, minWin=27, winSum=439
1651 23:59:09.474730 TX Vref=24, minBit 1, minWin=26, winSum=440
1652 23:59:09.478183 TX Vref=26, minBit 1, minWin=27, winSum=445
1653 23:59:09.481229 TX Vref=28, minBit 2, minWin=27, winSum=449
1654 23:59:09.484439 TX Vref=30, minBit 0, minWin=27, winSum=451
1655 23:59:09.488214 TX Vref=32, minBit 2, minWin=26, winSum=446
1656 23:59:09.495028 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 30
1657 23:59:09.495160
1658 23:59:09.498304 Final TX Range 1 Vref 30
1659 23:59:09.498431
1660 23:59:09.498549 ==
1661 23:59:09.501562 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 23:59:09.504907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 23:59:09.505016 ==
1664 23:59:09.505120
1665 23:59:09.505228
1666 23:59:09.508188 TX Vref Scan disable
1667 23:59:09.511302 == TX Byte 0 ==
1668 23:59:09.514822 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1669 23:59:09.518083 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1670 23:59:09.521845 == TX Byte 1 ==
1671 23:59:09.524896 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1672 23:59:09.528436 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1673 23:59:09.528548
1674 23:59:09.528645 [DATLAT]
1675 23:59:09.531930 Freq=800, CH1 RK0
1676 23:59:09.532016
1677 23:59:09.535221 DATLAT Default: 0xa
1678 23:59:09.535307 0, 0xFFFF, sum = 0
1679 23:59:09.538496 1, 0xFFFF, sum = 0
1680 23:59:09.538582 2, 0xFFFF, sum = 0
1681 23:59:09.541758 3, 0xFFFF, sum = 0
1682 23:59:09.541844 4, 0xFFFF, sum = 0
1683 23:59:09.545010 5, 0xFFFF, sum = 0
1684 23:59:09.545096 6, 0xFFFF, sum = 0
1685 23:59:09.548271 7, 0xFFFF, sum = 0
1686 23:59:09.548366 8, 0xFFFF, sum = 0
1687 23:59:09.551413 9, 0x0, sum = 1
1688 23:59:09.551499 10, 0x0, sum = 2
1689 23:59:09.555338 11, 0x0, sum = 3
1690 23:59:09.555439 12, 0x0, sum = 4
1691 23:59:09.555537 best_step = 10
1692 23:59:09.555612
1693 23:59:09.558466 ==
1694 23:59:09.558549 Dram Type= 6, Freq= 0, CH_1, rank 0
1695 23:59:09.564841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1696 23:59:09.564926 ==
1697 23:59:09.564993 RX Vref Scan: 1
1698 23:59:09.565055
1699 23:59:09.568007 Set Vref Range= 32 -> 127
1700 23:59:09.568136
1701 23:59:09.571913 RX Vref 32 -> 127, step: 1
1702 23:59:09.572035
1703 23:59:09.574990 RX Delay -79 -> 252, step: 8
1704 23:59:09.575089
1705 23:59:09.578121 Set Vref, RX VrefLevel [Byte0]: 32
1706 23:59:09.581307 [Byte1]: 32
1707 23:59:09.581392
1708 23:59:09.585179 Set Vref, RX VrefLevel [Byte0]: 33
1709 23:59:09.588522 [Byte1]: 33
1710 23:59:09.588622
1711 23:59:09.591607 Set Vref, RX VrefLevel [Byte0]: 34
1712 23:59:09.594898 [Byte1]: 34
1713 23:59:09.595056
1714 23:59:09.598650 Set Vref, RX VrefLevel [Byte0]: 35
1715 23:59:09.601764 [Byte1]: 35
1716 23:59:09.605700
1717 23:59:09.605830 Set Vref, RX VrefLevel [Byte0]: 36
1718 23:59:09.609120 [Byte1]: 36
1719 23:59:09.613477
1720 23:59:09.613604 Set Vref, RX VrefLevel [Byte0]: 37
1721 23:59:09.616678 [Byte1]: 37
1722 23:59:09.620901
1723 23:59:09.621035 Set Vref, RX VrefLevel [Byte0]: 38
1724 23:59:09.624165 [Byte1]: 38
1725 23:59:09.628140
1726 23:59:09.628270 Set Vref, RX VrefLevel [Byte0]: 39
1727 23:59:09.631344 [Byte1]: 39
1728 23:59:09.636037
1729 23:59:09.636121 Set Vref, RX VrefLevel [Byte0]: 40
1730 23:59:09.639075 [Byte1]: 40
1731 23:59:09.643233
1732 23:59:09.643319 Set Vref, RX VrefLevel [Byte0]: 41
1733 23:59:09.646580 [Byte1]: 41
1734 23:59:09.650978
1735 23:59:09.651063 Set Vref, RX VrefLevel [Byte0]: 42
1736 23:59:09.654252 [Byte1]: 42
1737 23:59:09.658677
1738 23:59:09.658760 Set Vref, RX VrefLevel [Byte0]: 43
1739 23:59:09.661886 [Byte1]: 43
1740 23:59:09.666467
1741 23:59:09.666551 Set Vref, RX VrefLevel [Byte0]: 44
1742 23:59:09.669633 [Byte1]: 44
1743 23:59:09.673445
1744 23:59:09.673529 Set Vref, RX VrefLevel [Byte0]: 45
1745 23:59:09.676719 [Byte1]: 45
1746 23:59:09.681247
1747 23:59:09.681331 Set Vref, RX VrefLevel [Byte0]: 46
1748 23:59:09.684507 [Byte1]: 46
1749 23:59:09.689030
1750 23:59:09.689113 Set Vref, RX VrefLevel [Byte0]: 47
1751 23:59:09.691934 [Byte1]: 47
1752 23:59:09.696111
1753 23:59:09.696199 Set Vref, RX VrefLevel [Byte0]: 48
1754 23:59:09.700044 [Byte1]: 48
1755 23:59:09.703780
1756 23:59:09.703862 Set Vref, RX VrefLevel [Byte0]: 49
1757 23:59:09.706972 [Byte1]: 49
1758 23:59:09.711521
1759 23:59:09.711605 Set Vref, RX VrefLevel [Byte0]: 50
1760 23:59:09.714682 [Byte1]: 50
1761 23:59:09.718642
1762 23:59:09.718725 Set Vref, RX VrefLevel [Byte0]: 51
1763 23:59:09.721849 [Byte1]: 51
1764 23:59:09.726217
1765 23:59:09.726293 Set Vref, RX VrefLevel [Byte0]: 52
1766 23:59:09.729968 [Byte1]: 52
1767 23:59:09.733656
1768 23:59:09.733732 Set Vref, RX VrefLevel [Byte0]: 53
1769 23:59:09.737558 [Byte1]: 53
1770 23:59:09.741423
1771 23:59:09.741499 Set Vref, RX VrefLevel [Byte0]: 54
1772 23:59:09.744746 [Byte1]: 54
1773 23:59:09.749054
1774 23:59:09.749133 Set Vref, RX VrefLevel [Byte0]: 55
1775 23:59:09.752142 [Byte1]: 55
1776 23:59:09.756544
1777 23:59:09.756625 Set Vref, RX VrefLevel [Byte0]: 56
1778 23:59:09.759747 [Byte1]: 56
1779 23:59:09.763916
1780 23:59:09.763998 Set Vref, RX VrefLevel [Byte0]: 57
1781 23:59:09.767502 [Byte1]: 57
1782 23:59:09.771547
1783 23:59:09.771632 Set Vref, RX VrefLevel [Byte0]: 58
1784 23:59:09.774899 [Byte1]: 58
1785 23:59:09.779409
1786 23:59:09.779520 Set Vref, RX VrefLevel [Byte0]: 59
1787 23:59:09.782310 [Byte1]: 59
1788 23:59:09.786707
1789 23:59:09.786832 Set Vref, RX VrefLevel [Byte0]: 60
1790 23:59:09.789973 [Byte1]: 60
1791 23:59:09.794516
1792 23:59:09.794641 Set Vref, RX VrefLevel [Byte0]: 61
1793 23:59:09.797677 [Byte1]: 61
1794 23:59:09.802558
1795 23:59:09.802690 Set Vref, RX VrefLevel [Byte0]: 62
1796 23:59:09.805476 [Byte1]: 62
1797 23:59:09.809347
1798 23:59:09.809479 Set Vref, RX VrefLevel [Byte0]: 63
1799 23:59:09.813014 [Byte1]: 63
1800 23:59:09.817072
1801 23:59:09.817198 Set Vref, RX VrefLevel [Byte0]: 64
1802 23:59:09.819980 [Byte1]: 64
1803 23:59:09.824572
1804 23:59:09.824697 Set Vref, RX VrefLevel [Byte0]: 65
1805 23:59:09.827716 [Byte1]: 65
1806 23:59:09.832203
1807 23:59:09.832347 Set Vref, RX VrefLevel [Byte0]: 66
1808 23:59:09.835305 [Byte1]: 66
1809 23:59:09.839689
1810 23:59:09.839811 Set Vref, RX VrefLevel [Byte0]: 67
1811 23:59:09.842871 [Byte1]: 67
1812 23:59:09.846928
1813 23:59:09.847052 Set Vref, RX VrefLevel [Byte0]: 68
1814 23:59:09.850792 [Byte1]: 68
1815 23:59:09.854632
1816 23:59:09.854765 Set Vref, RX VrefLevel [Byte0]: 69
1817 23:59:09.858332 [Byte1]: 69
1818 23:59:09.862330
1819 23:59:09.862456 Set Vref, RX VrefLevel [Byte0]: 70
1820 23:59:09.865861 [Byte1]: 70
1821 23:59:09.869771
1822 23:59:09.869896 Final RX Vref Byte 0 = 55 to rank0
1823 23:59:09.872858 Final RX Vref Byte 1 = 55 to rank0
1824 23:59:09.876778 Final RX Vref Byte 0 = 55 to rank1
1825 23:59:09.879819 Final RX Vref Byte 1 = 55 to rank1==
1826 23:59:09.883035 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 23:59:09.886601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 23:59:09.890121 ==
1829 23:59:09.890205 DQS Delay:
1830 23:59:09.890271 DQS0 = 0, DQS1 = 0
1831 23:59:09.893515 DQM Delay:
1832 23:59:09.893599 DQM0 = 95, DQM1 = 89
1833 23:59:09.896578 DQ Delay:
1834 23:59:09.896661 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1835 23:59:09.900003 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1836 23:59:09.903512 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1837 23:59:09.906544 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1838 23:59:09.910296
1839 23:59:09.910380
1840 23:59:09.916712 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1841 23:59:09.919946 CH1 RK0: MR19=606, MR18=2E4A
1842 23:59:09.926956 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1843 23:59:09.927045
1844 23:59:09.930113 ----->DramcWriteLeveling(PI) begin...
1845 23:59:09.930199 ==
1846 23:59:09.933509 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 23:59:09.936554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 23:59:09.936629 ==
1849 23:59:09.940313 Write leveling (Byte 0): 27 => 27
1850 23:59:09.943339 Write leveling (Byte 1): 27 => 27
1851 23:59:09.946553 DramcWriteLeveling(PI) end<-----
1852 23:59:09.946632
1853 23:59:09.946696 ==
1854 23:59:09.950490 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 23:59:09.953755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 23:59:09.953839 ==
1857 23:59:09.956996 [Gating] SW mode calibration
1858 23:59:09.963178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 23:59:09.970206 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 23:59:09.973432 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 23:59:09.976995 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1862 23:59:09.983506 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:59:09.986811 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:59:09.990140 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:59:09.993983 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:59:09.999982 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:59:10.003362 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:59:10.007196 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:59:10.013855 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:59:10.017101 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:59:10.020013 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:59:10.027166 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:59:10.030445 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:59:10.033587 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:59:10.040636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1876 23:59:10.043845 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1877 23:59:10.047016 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1878 23:59:10.053829 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:59:10.057015 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:59:10.060216 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:59:10.067331 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:59:10.070283 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:59:10.074026 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:59:10.080249 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:59:10.083407 0 9 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 1)
1886 23:59:10.087275 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1887 23:59:10.090541 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:59:10.097137 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:59:10.100428 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:59:10.103603 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:59:10.110540 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 23:59:10.114084 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1893 23:59:10.117227 0 10 4 | B1->B0 | 2929 2f2f | 0 0 | (1 1) (0 0)
1894 23:59:10.124009 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:59:10.127314 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:59:10.130338 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:59:10.137263 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:59:10.140669 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:59:10.143492 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:59:10.150483 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1901 23:59:10.153671 0 11 4 | B1->B0 | 3b3b 3030 | 1 0 | (0 0) (0 0)
1902 23:59:10.157183 0 11 8 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
1903 23:59:10.163683 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:59:10.167005 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:59:10.170935 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:59:10.173981 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:59:10.180431 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 23:59:10.184018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1909 23:59:10.186928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1910 23:59:10.193933 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:59:10.197040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:59:10.201012 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:59:10.207485 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:59:10.210510 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:59:10.213727 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:59:10.221026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:59:10.224152 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:59:10.227445 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:59:10.233761 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:59:10.237327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:59:10.240501 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:59:10.247028 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:59:10.250691 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:59:10.253903 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1925 23:59:10.260613 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1926 23:59:10.264084 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1927 23:59:10.267538 Total UI for P1: 0, mck2ui 16
1928 23:59:10.270442 best dqsien dly found for B1: ( 0, 14, 2)
1929 23:59:10.273528 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 23:59:10.277434 Total UI for P1: 0, mck2ui 16
1931 23:59:10.280547 best dqsien dly found for B0: ( 0, 14, 6)
1932 23:59:10.283790 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1933 23:59:10.287101 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1934 23:59:10.287185
1935 23:59:10.290187 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1936 23:59:10.293906 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1937 23:59:10.297079 [Gating] SW calibration Done
1938 23:59:10.297164 ==
1939 23:59:10.300652 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 23:59:10.303821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 23:59:10.307050 ==
1942 23:59:10.307134 RX Vref Scan: 0
1943 23:59:10.307202
1944 23:59:10.310343 RX Vref 0 -> 0, step: 1
1945 23:59:10.310427
1946 23:59:10.314123 RX Delay -130 -> 252, step: 16
1947 23:59:10.317212 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1948 23:59:10.320455 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1949 23:59:10.323705 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1950 23:59:10.327480 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1951 23:59:10.333978 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1952 23:59:10.337191 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1953 23:59:10.340440 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1954 23:59:10.344149 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1955 23:59:10.347140 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1956 23:59:10.354143 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1957 23:59:10.357368 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1958 23:59:10.360643 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1959 23:59:10.363846 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1960 23:59:10.367124 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1961 23:59:10.373768 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1962 23:59:10.377205 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1963 23:59:10.377291 ==
1964 23:59:10.380777 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 23:59:10.384124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 23:59:10.384208 ==
1967 23:59:10.387538 DQS Delay:
1968 23:59:10.387622 DQS0 = 0, DQS1 = 0
1969 23:59:10.387689 DQM Delay:
1970 23:59:10.390714 DQM0 = 92, DQM1 = 88
1971 23:59:10.390798 DQ Delay:
1972 23:59:10.394063 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1973 23:59:10.397370 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1974 23:59:10.400550 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1975 23:59:10.404144 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1976 23:59:10.404228
1977 23:59:10.404295
1978 23:59:10.404384 ==
1979 23:59:10.407316 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 23:59:10.414398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 23:59:10.414484 ==
1982 23:59:10.414552
1983 23:59:10.414614
1984 23:59:10.414673 TX Vref Scan disable
1985 23:59:10.417628 == TX Byte 0 ==
1986 23:59:10.420825 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1987 23:59:10.424452 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1988 23:59:10.427477 == TX Byte 1 ==
1989 23:59:10.430644 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1990 23:59:10.434448 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1991 23:59:10.437668 ==
1992 23:59:10.440777 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:59:10.444100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:59:10.444215 ==
1995 23:59:10.456319 TX Vref=22, minBit 1, minWin=26, winSum=437
1996 23:59:10.460021 TX Vref=24, minBit 2, minWin=26, winSum=444
1997 23:59:10.463049 TX Vref=26, minBit 0, minWin=27, winSum=448
1998 23:59:10.466375 TX Vref=28, minBit 2, minWin=27, winSum=449
1999 23:59:10.469575 TX Vref=30, minBit 2, minWin=27, winSum=448
2000 23:59:10.473405 TX Vref=32, minBit 2, minWin=27, winSum=449
2001 23:59:10.480055 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
2002 23:59:10.480144
2003 23:59:10.483260 Final TX Range 1 Vref 28
2004 23:59:10.483346
2005 23:59:10.483413 ==
2006 23:59:10.486532 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 23:59:10.489549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 23:59:10.489680 ==
2009 23:59:10.492808
2010 23:59:10.492934
2011 23:59:10.493050 TX Vref Scan disable
2012 23:59:10.496533 == TX Byte 0 ==
2013 23:59:10.499927 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2014 23:59:10.503353 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2015 23:59:10.506419 == TX Byte 1 ==
2016 23:59:10.509834 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2017 23:59:10.513014 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2018 23:59:10.516655
2019 23:59:10.516740 [DATLAT]
2020 23:59:10.516808 Freq=800, CH1 RK1
2021 23:59:10.516873
2022 23:59:10.520332 DATLAT Default: 0xa
2023 23:59:10.520454 0, 0xFFFF, sum = 0
2024 23:59:10.523503 1, 0xFFFF, sum = 0
2025 23:59:10.523588 2, 0xFFFF, sum = 0
2026 23:59:10.526753 3, 0xFFFF, sum = 0
2027 23:59:10.526839 4, 0xFFFF, sum = 0
2028 23:59:10.530137 5, 0xFFFF, sum = 0
2029 23:59:10.530223 6, 0xFFFF, sum = 0
2030 23:59:10.533555 7, 0xFFFF, sum = 0
2031 23:59:10.533641 8, 0xFFFF, sum = 0
2032 23:59:10.536551 9, 0x0, sum = 1
2033 23:59:10.536637 10, 0x0, sum = 2
2034 23:59:10.539760 11, 0x0, sum = 3
2035 23:59:10.539845 12, 0x0, sum = 4
2036 23:59:10.542947 best_step = 10
2037 23:59:10.543031
2038 23:59:10.543099 ==
2039 23:59:10.546770 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 23:59:10.550080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 23:59:10.550166 ==
2042 23:59:10.553230 RX Vref Scan: 0
2043 23:59:10.553314
2044 23:59:10.553381 RX Vref 0 -> 0, step: 1
2045 23:59:10.553444
2046 23:59:10.556459 RX Delay -79 -> 252, step: 8
2047 23:59:10.563400 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2048 23:59:10.566520 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2049 23:59:10.569679 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2050 23:59:10.573342 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2051 23:59:10.576492 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2052 23:59:10.579626 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2053 23:59:10.586611 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2054 23:59:10.590229 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2055 23:59:10.593224 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2056 23:59:10.596411 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2057 23:59:10.599709 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2058 23:59:10.606801 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2059 23:59:10.609863 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2060 23:59:10.612876 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2061 23:59:10.616266 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2062 23:59:10.619985 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2063 23:59:10.620092 ==
2064 23:59:10.623078 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 23:59:10.629592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 23:59:10.629678 ==
2067 23:59:10.629747 DQS Delay:
2068 23:59:10.633127 DQS0 = 0, DQS1 = 0
2069 23:59:10.633211 DQM Delay:
2070 23:59:10.633278 DQM0 = 97, DQM1 = 91
2071 23:59:10.636566 DQ Delay:
2072 23:59:10.639991 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2073 23:59:10.643078 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2074 23:59:10.646361 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2075 23:59:10.649610 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2076 23:59:10.649694
2077 23:59:10.649760
2078 23:59:10.656713 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2079 23:59:10.659998 CH1 RK1: MR19=606, MR18=450F
2080 23:59:10.666796 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2081 23:59:10.669945 [RxdqsGatingPostProcess] freq 800
2082 23:59:10.673178 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2083 23:59:10.676410 Pre-setting of DQS Precalculation
2084 23:59:10.683126 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2085 23:59:10.690427 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2086 23:59:10.696307 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2087 23:59:10.696431
2088 23:59:10.696500
2089 23:59:10.700279 [Calibration Summary] 1600 Mbps
2090 23:59:10.700403 CH 0, Rank 0
2091 23:59:10.703180 SW Impedance : PASS
2092 23:59:10.706454 DUTY Scan : NO K
2093 23:59:10.706565 ZQ Calibration : PASS
2094 23:59:10.709718 Jitter Meter : NO K
2095 23:59:10.713000 CBT Training : PASS
2096 23:59:10.713085 Write leveling : PASS
2097 23:59:10.716720 RX DQS gating : PASS
2098 23:59:10.719707 RX DQ/DQS(RDDQC) : PASS
2099 23:59:10.719807 TX DQ/DQS : PASS
2100 23:59:10.723355 RX DATLAT : PASS
2101 23:59:10.726988 RX DQ/DQS(Engine): PASS
2102 23:59:10.727073 TX OE : NO K
2103 23:59:10.730203 All Pass.
2104 23:59:10.730287
2105 23:59:10.730354 CH 0, Rank 1
2106 23:59:10.733518 SW Impedance : PASS
2107 23:59:10.733602 DUTY Scan : NO K
2108 23:59:10.736660 ZQ Calibration : PASS
2109 23:59:10.739786 Jitter Meter : NO K
2110 23:59:10.739900 CBT Training : PASS
2111 23:59:10.743427 Write leveling : PASS
2112 23:59:10.743511 RX DQS gating : PASS
2113 23:59:10.746780 RX DQ/DQS(RDDQC) : PASS
2114 23:59:10.750133 TX DQ/DQS : PASS
2115 23:59:10.750219 RX DATLAT : PASS
2116 23:59:10.753542 RX DQ/DQS(Engine): PASS
2117 23:59:10.756957 TX OE : NO K
2118 23:59:10.757042 All Pass.
2119 23:59:10.757109
2120 23:59:10.757172 CH 1, Rank 0
2121 23:59:10.760012 SW Impedance : PASS
2122 23:59:10.763300 DUTY Scan : NO K
2123 23:59:10.763385 ZQ Calibration : PASS
2124 23:59:10.766944 Jitter Meter : NO K
2125 23:59:10.770171 CBT Training : PASS
2126 23:59:10.770255 Write leveling : PASS
2127 23:59:10.773361 RX DQS gating : PASS
2128 23:59:10.776553 RX DQ/DQS(RDDQC) : PASS
2129 23:59:10.776637 TX DQ/DQS : PASS
2130 23:59:10.779703 RX DATLAT : PASS
2131 23:59:10.779788 RX DQ/DQS(Engine): PASS
2132 23:59:10.783587 TX OE : NO K
2133 23:59:10.783672 All Pass.
2134 23:59:10.783738
2135 23:59:10.786663 CH 1, Rank 1
2136 23:59:10.786747 SW Impedance : PASS
2137 23:59:10.789729 DUTY Scan : NO K
2138 23:59:10.793424 ZQ Calibration : PASS
2139 23:59:10.793508 Jitter Meter : NO K
2140 23:59:10.796699 CBT Training : PASS
2141 23:59:10.799890 Write leveling : PASS
2142 23:59:10.799974 RX DQS gating : PASS
2143 23:59:10.803082 RX DQ/DQS(RDDQC) : PASS
2144 23:59:10.806903 TX DQ/DQS : PASS
2145 23:59:10.806989 RX DATLAT : PASS
2146 23:59:10.810083 RX DQ/DQS(Engine): PASS
2147 23:59:10.813220 TX OE : NO K
2148 23:59:10.813304 All Pass.
2149 23:59:10.813371
2150 23:59:10.813434 DramC Write-DBI off
2151 23:59:10.816588 PER_BANK_REFRESH: Hybrid Mode
2152 23:59:10.819876 TX_TRACKING: ON
2153 23:59:10.823104 [GetDramInforAfterCalByMRR] Vendor 6.
2154 23:59:10.827046 [GetDramInforAfterCalByMRR] Revision 606.
2155 23:59:10.829901 [GetDramInforAfterCalByMRR] Revision 2 0.
2156 23:59:10.829989 MR0 0x3b3b
2157 23:59:10.833414 MR8 0x5151
2158 23:59:10.836479 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 23:59:10.836563
2160 23:59:10.836630 MR0 0x3b3b
2161 23:59:10.836697 MR8 0x5151
2162 23:59:10.840391 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 23:59:10.840476
2164 23:59:10.850135 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2165 23:59:10.853390 [FAST_K] Save calibration result to emmc
2166 23:59:10.857404 [FAST_K] Save calibration result to emmc
2167 23:59:10.860584 dram_init: config_dvfs: 1
2168 23:59:10.863320 dramc_set_vcore_voltage set vcore to 662500
2169 23:59:10.866930 Read voltage for 1200, 2
2170 23:59:10.867015 Vio18 = 0
2171 23:59:10.867082 Vcore = 662500
2172 23:59:10.870496 Vdram = 0
2173 23:59:10.870580 Vddq = 0
2174 23:59:10.870648 Vmddr = 0
2175 23:59:10.876720 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2176 23:59:10.880326 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2177 23:59:10.883654 MEM_TYPE=3, freq_sel=15
2178 23:59:10.886938 sv_algorithm_assistance_LP4_1600
2179 23:59:10.890256 ============ PULL DRAM RESETB DOWN ============
2180 23:59:10.893475 ========== PULL DRAM RESETB DOWN end =========
2181 23:59:10.900205 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2182 23:59:10.903454 ===================================
2183 23:59:10.907549 LPDDR4 DRAM CONFIGURATION
2184 23:59:10.910607 ===================================
2185 23:59:10.910695 EX_ROW_EN[0] = 0x0
2186 23:59:10.913601 EX_ROW_EN[1] = 0x0
2187 23:59:10.913686 LP4Y_EN = 0x0
2188 23:59:10.916851 WORK_FSP = 0x0
2189 23:59:10.916935 WL = 0x4
2190 23:59:10.920089 RL = 0x4
2191 23:59:10.920200 BL = 0x2
2192 23:59:10.924098 RPST = 0x0
2193 23:59:10.924183 RD_PRE = 0x0
2194 23:59:10.927267 WR_PRE = 0x1
2195 23:59:10.927350 WR_PST = 0x0
2196 23:59:10.930424 DBI_WR = 0x0
2197 23:59:10.930508 DBI_RD = 0x0
2198 23:59:10.933723 OTF = 0x1
2199 23:59:10.936947 ===================================
2200 23:59:10.940568 ===================================
2201 23:59:10.940653 ANA top config
2202 23:59:10.943589 ===================================
2203 23:59:10.947362 DLL_ASYNC_EN = 0
2204 23:59:10.950410 ALL_SLAVE_EN = 0
2205 23:59:10.953933 NEW_RANK_MODE = 1
2206 23:59:10.954018 DLL_IDLE_MODE = 1
2207 23:59:10.956994 LP45_APHY_COMB_EN = 1
2208 23:59:10.960274 TX_ODT_DIS = 1
2209 23:59:10.963942 NEW_8X_MODE = 1
2210 23:59:10.966951 ===================================
2211 23:59:10.970437 ===================================
2212 23:59:10.973580 data_rate = 2400
2213 23:59:10.973680 CKR = 1
2214 23:59:10.976881 DQ_P2S_RATIO = 8
2215 23:59:10.980859 ===================================
2216 23:59:10.983866 CA_P2S_RATIO = 8
2217 23:59:10.987163 DQ_CA_OPEN = 0
2218 23:59:10.990546 DQ_SEMI_OPEN = 0
2219 23:59:10.990633 CA_SEMI_OPEN = 0
2220 23:59:10.993804 CA_FULL_RATE = 0
2221 23:59:10.997166 DQ_CKDIV4_EN = 0
2222 23:59:11.000531 CA_CKDIV4_EN = 0
2223 23:59:11.003735 CA_PREDIV_EN = 0
2224 23:59:11.007693 PH8_DLY = 17
2225 23:59:11.007891 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2226 23:59:11.010717 DQ_AAMCK_DIV = 4
2227 23:59:11.013954 CA_AAMCK_DIV = 4
2228 23:59:11.017122 CA_ADMCK_DIV = 4
2229 23:59:11.020904 DQ_TRACK_CA_EN = 0
2230 23:59:11.024106 CA_PICK = 1200
2231 23:59:11.024191 CA_MCKIO = 1200
2232 23:59:11.027392 MCKIO_SEMI = 0
2233 23:59:11.030687 PLL_FREQ = 2366
2234 23:59:11.033921 DQ_UI_PI_RATIO = 32
2235 23:59:11.037334 CA_UI_PI_RATIO = 0
2236 23:59:11.040559 ===================================
2237 23:59:11.044485 ===================================
2238 23:59:11.047579 memory_type:LPDDR4
2239 23:59:11.047683 GP_NUM : 10
2240 23:59:11.050727 SRAM_EN : 1
2241 23:59:11.050812 MD32_EN : 0
2242 23:59:11.054560 ===================================
2243 23:59:11.058124 [ANA_INIT] >>>>>>>>>>>>>>
2244 23:59:11.061178 <<<<<< [CONFIGURE PHASE]: ANA_TX
2245 23:59:11.064560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2246 23:59:11.067915 ===================================
2247 23:59:11.071072 data_rate = 2400,PCW = 0X5b00
2248 23:59:11.074337 ===================================
2249 23:59:11.077408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2250 23:59:11.080967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 23:59:11.088213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 23:59:11.091234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2253 23:59:11.094364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2254 23:59:11.100795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2255 23:59:11.100883 [ANA_INIT] flow start
2256 23:59:11.104359 [ANA_INIT] PLL >>>>>>>>
2257 23:59:11.104519 [ANA_INIT] PLL <<<<<<<<
2258 23:59:11.107581 [ANA_INIT] MIDPI >>>>>>>>
2259 23:59:11.110717 [ANA_INIT] MIDPI <<<<<<<<
2260 23:59:11.114613 [ANA_INIT] DLL >>>>>>>>
2261 23:59:11.114737 [ANA_INIT] DLL <<<<<<<<
2262 23:59:11.117579 [ANA_INIT] flow end
2263 23:59:11.120672 ============ LP4 DIFF to SE enter ============
2264 23:59:11.124445 ============ LP4 DIFF to SE exit ============
2265 23:59:11.127512 [ANA_INIT] <<<<<<<<<<<<<
2266 23:59:11.131051 [Flow] Enable top DCM control >>>>>
2267 23:59:11.134192 [Flow] Enable top DCM control <<<<<
2268 23:59:11.137412 Enable DLL master slave shuffle
2269 23:59:11.144495 ==============================================================
2270 23:59:11.144627 Gating Mode config
2271 23:59:11.150843 ==============================================================
2272 23:59:11.150973 Config description:
2273 23:59:11.160744 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2274 23:59:11.167707 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2275 23:59:11.174110 SELPH_MODE 0: By rank 1: By Phase
2276 23:59:11.177379 ==============================================================
2277 23:59:11.181372 GAT_TRACK_EN = 1
2278 23:59:11.184359 RX_GATING_MODE = 2
2279 23:59:11.187548 RX_GATING_TRACK_MODE = 2
2280 23:59:11.191345 SELPH_MODE = 1
2281 23:59:11.194418 PICG_EARLY_EN = 1
2282 23:59:11.197537 VALID_LAT_VALUE = 1
2283 23:59:11.200881 ==============================================================
2284 23:59:11.204175 Enter into Gating configuration >>>>
2285 23:59:11.207890 Exit from Gating configuration <<<<
2286 23:59:11.210967 Enter into DVFS_PRE_config >>>>>
2287 23:59:11.224766 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2288 23:59:11.224933 Exit from DVFS_PRE_config <<<<<
2289 23:59:11.227813 Enter into PICG configuration >>>>
2290 23:59:11.230928 Exit from PICG configuration <<<<
2291 23:59:11.234478 [RX_INPUT] configuration >>>>>
2292 23:59:11.237691 [RX_INPUT] configuration <<<<<
2293 23:59:11.244550 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2294 23:59:11.247803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2295 23:59:11.254935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 23:59:11.261494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 23:59:11.267889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 23:59:11.274377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 23:59:11.278542 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2300 23:59:11.281529 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2301 23:59:11.284657 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2302 23:59:11.291128 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2303 23:59:11.294977 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2304 23:59:11.297948 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 23:59:11.301152 ===================================
2306 23:59:11.304593 LPDDR4 DRAM CONFIGURATION
2307 23:59:11.308201 ===================================
2308 23:59:11.308331 EX_ROW_EN[0] = 0x0
2309 23:59:11.311607 EX_ROW_EN[1] = 0x0
2310 23:59:11.311735 LP4Y_EN = 0x0
2311 23:59:11.314854 WORK_FSP = 0x0
2312 23:59:11.314981 WL = 0x4
2313 23:59:11.318046 RL = 0x4
2314 23:59:11.318168 BL = 0x2
2315 23:59:11.321287 RPST = 0x0
2316 23:59:11.321412 RD_PRE = 0x0
2317 23:59:11.324520 WR_PRE = 0x1
2318 23:59:11.328142 WR_PST = 0x0
2319 23:59:11.328263 DBI_WR = 0x0
2320 23:59:11.331744 DBI_RD = 0x0
2321 23:59:11.331829 OTF = 0x1
2322 23:59:11.334603 ===================================
2323 23:59:11.337935 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2324 23:59:11.341240 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2325 23:59:11.348580 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 23:59:11.351319 ===================================
2327 23:59:11.354739 LPDDR4 DRAM CONFIGURATION
2328 23:59:11.354846 ===================================
2329 23:59:11.358384 EX_ROW_EN[0] = 0x10
2330 23:59:11.361929 EX_ROW_EN[1] = 0x0
2331 23:59:11.362062 LP4Y_EN = 0x0
2332 23:59:11.365180 WORK_FSP = 0x0
2333 23:59:11.365291 WL = 0x4
2334 23:59:11.368476 RL = 0x4
2335 23:59:11.368591 BL = 0x2
2336 23:59:11.371728 RPST = 0x0
2337 23:59:11.371814 RD_PRE = 0x0
2338 23:59:11.374846 WR_PRE = 0x1
2339 23:59:11.374931 WR_PST = 0x0
2340 23:59:11.378585 DBI_WR = 0x0
2341 23:59:11.378674 DBI_RD = 0x0
2342 23:59:11.381738 OTF = 0x1
2343 23:59:11.384996 ===================================
2344 23:59:11.391563 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2345 23:59:11.391654 ==
2346 23:59:11.394673 Dram Type= 6, Freq= 0, CH_0, rank 0
2347 23:59:11.398502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2348 23:59:11.398589 ==
2349 23:59:11.401521 [Duty_Offset_Calibration]
2350 23:59:11.401605 B0:2 B1:1 CA:1
2351 23:59:11.401673
2352 23:59:11.404908 [DutyScan_Calibration_Flow] k_type=0
2353 23:59:11.415325
2354 23:59:11.415467 ==CLK 0==
2355 23:59:11.418495 Final CLK duty delay cell = 0
2356 23:59:11.421772 [0] MAX Duty = 5187%(X100), DQS PI = 24
2357 23:59:11.424999 [0] MIN Duty = 4844%(X100), DQS PI = 48
2358 23:59:11.425130 [0] AVG Duty = 5015%(X100)
2359 23:59:11.428421
2360 23:59:11.432285 CH0 CLK Duty spec in!! Max-Min= 343%
2361 23:59:11.435490 [DutyScan_Calibration_Flow] ====Done====
2362 23:59:11.435625
2363 23:59:11.438628 [DutyScan_Calibration_Flow] k_type=1
2364 23:59:11.453871
2365 23:59:11.454011 ==DQS 0 ==
2366 23:59:11.457335 Final DQS duty delay cell = -4
2367 23:59:11.460264 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2368 23:59:11.463628 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2369 23:59:11.467048 [-4] AVG Duty = 4937%(X100)
2370 23:59:11.467138
2371 23:59:11.467207 ==DQS 1 ==
2372 23:59:11.470567 Final DQS duty delay cell = 0
2373 23:59:11.474085 [0] MAX Duty = 5156%(X100), DQS PI = 0
2374 23:59:11.477507 [0] MIN Duty = 5000%(X100), DQS PI = 34
2375 23:59:11.480433 [0] AVG Duty = 5078%(X100)
2376 23:59:11.480521
2377 23:59:11.484042 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2378 23:59:11.484148
2379 23:59:11.487515 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2380 23:59:11.490506 [DutyScan_Calibration_Flow] ====Done====
2381 23:59:11.490592
2382 23:59:11.493613 [DutyScan_Calibration_Flow] k_type=3
2383 23:59:11.510538
2384 23:59:11.510650 ==DQM 0 ==
2385 23:59:11.513849 Final DQM duty delay cell = 0
2386 23:59:11.517050 [0] MAX Duty = 5156%(X100), DQS PI = 30
2387 23:59:11.520393 [0] MIN Duty = 4875%(X100), DQS PI = 58
2388 23:59:11.523658 [0] AVG Duty = 5015%(X100)
2389 23:59:11.523743
2390 23:59:11.523810 ==DQM 1 ==
2391 23:59:11.527402 Final DQM duty delay cell = 0
2392 23:59:11.530696 [0] MAX Duty = 5093%(X100), DQS PI = 0
2393 23:59:11.533961 [0] MIN Duty = 5031%(X100), DQS PI = 16
2394 23:59:11.534046 [0] AVG Duty = 5062%(X100)
2395 23:59:11.537247
2396 23:59:11.540279 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2397 23:59:11.540389
2398 23:59:11.544029 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2399 23:59:11.547528 [DutyScan_Calibration_Flow] ====Done====
2400 23:59:11.547614
2401 23:59:11.550774 [DutyScan_Calibration_Flow] k_type=2
2402 23:59:11.567153
2403 23:59:11.567350 ==DQ 0 ==
2404 23:59:11.570334 Final DQ duty delay cell = 0
2405 23:59:11.573445 [0] MAX Duty = 5031%(X100), DQS PI = 24
2406 23:59:11.577399 [0] MIN Duty = 4844%(X100), DQS PI = 62
2407 23:59:11.577485 [0] AVG Duty = 4937%(X100)
2408 23:59:11.577552
2409 23:59:11.580650 ==DQ 1 ==
2410 23:59:11.583602 Final DQ duty delay cell = 0
2411 23:59:11.587395 [0] MAX Duty = 5062%(X100), DQS PI = 8
2412 23:59:11.590911 [0] MIN Duty = 4969%(X100), DQS PI = 2
2413 23:59:11.591039 [0] AVG Duty = 5015%(X100)
2414 23:59:11.591136
2415 23:59:11.593531 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2416 23:59:11.593614
2417 23:59:11.597004 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2418 23:59:11.603801 [DutyScan_Calibration_Flow] ====Done====
2419 23:59:11.603887 ==
2420 23:59:11.607002 Dram Type= 6, Freq= 0, CH_1, rank 0
2421 23:59:11.610468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2422 23:59:11.610553 ==
2423 23:59:11.613572 [Duty_Offset_Calibration]
2424 23:59:11.613660 B0:1 B1:0 CA:0
2425 23:59:11.613749
2426 23:59:11.616778 [DutyScan_Calibration_Flow] k_type=0
2427 23:59:11.625838
2428 23:59:11.625934 ==CLK 0==
2429 23:59:11.629153 Final CLK duty delay cell = -4
2430 23:59:11.632524 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2431 23:59:11.635669 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2432 23:59:11.639578 [-4] AVG Duty = 4953%(X100)
2433 23:59:11.639667
2434 23:59:11.642805 CH1 CLK Duty spec in!! Max-Min= 156%
2435 23:59:11.646062 [DutyScan_Calibration_Flow] ====Done====
2436 23:59:11.646150
2437 23:59:11.649093 [DutyScan_Calibration_Flow] k_type=1
2438 23:59:11.665986
2439 23:59:11.666088 ==DQS 0 ==
2440 23:59:11.669036 Final DQS duty delay cell = 0
2441 23:59:11.672718 [0] MAX Duty = 5062%(X100), DQS PI = 12
2442 23:59:11.675765 [0] MIN Duty = 4844%(X100), DQS PI = 0
2443 23:59:11.675866 [0] AVG Duty = 4953%(X100)
2444 23:59:11.679414
2445 23:59:11.679497 ==DQS 1 ==
2446 23:59:11.682714 Final DQS duty delay cell = 0
2447 23:59:11.686015 [0] MAX Duty = 5187%(X100), DQS PI = 18
2448 23:59:11.689145 [0] MIN Duty = 4938%(X100), DQS PI = 12
2449 23:59:11.692356 [0] AVG Duty = 5062%(X100)
2450 23:59:11.692480
2451 23:59:11.695601 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2452 23:59:11.695714
2453 23:59:11.699281 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2454 23:59:11.702634 [DutyScan_Calibration_Flow] ====Done====
2455 23:59:11.702747
2456 23:59:11.705757 [DutyScan_Calibration_Flow] k_type=3
2457 23:59:11.722616
2458 23:59:11.722737 ==DQM 0 ==
2459 23:59:11.726051 Final DQM duty delay cell = 0
2460 23:59:11.728873 [0] MAX Duty = 5156%(X100), DQS PI = 6
2461 23:59:11.732650 [0] MIN Duty = 5031%(X100), DQS PI = 0
2462 23:59:11.732750 [0] AVG Duty = 5093%(X100)
2463 23:59:11.735904
2464 23:59:11.736030 ==DQM 1 ==
2465 23:59:11.739248 Final DQM duty delay cell = 0
2466 23:59:11.742526 [0] MAX Duty = 5031%(X100), DQS PI = 26
2467 23:59:11.745771 [0] MIN Duty = 4875%(X100), DQS PI = 36
2468 23:59:11.745855 [0] AVG Duty = 4953%(X100)
2469 23:59:11.745921
2470 23:59:11.752692 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2471 23:59:11.752776
2472 23:59:11.755817 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2473 23:59:11.759070 [DutyScan_Calibration_Flow] ====Done====
2474 23:59:11.759155
2475 23:59:11.762420 [DutyScan_Calibration_Flow] k_type=2
2476 23:59:11.777940
2477 23:59:11.778046 ==DQ 0 ==
2478 23:59:11.781554 Final DQ duty delay cell = -4
2479 23:59:11.784539 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2480 23:59:11.788310 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2481 23:59:11.791553 [-4] AVG Duty = 4984%(X100)
2482 23:59:11.791667
2483 23:59:11.791776 ==DQ 1 ==
2484 23:59:11.794757 Final DQ duty delay cell = 0
2485 23:59:11.798025 [0] MAX Duty = 5125%(X100), DQS PI = 20
2486 23:59:11.801383 [0] MIN Duty = 4969%(X100), DQS PI = 12
2487 23:59:11.801473 [0] AVG Duty = 5047%(X100)
2488 23:59:11.804982
2489 23:59:11.808502 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2490 23:59:11.808589
2491 23:59:11.811594 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2492 23:59:11.814797 [DutyScan_Calibration_Flow] ====Done====
2493 23:59:11.817960 nWR fixed to 30
2494 23:59:11.818048 [ModeRegInit_LP4] CH0 RK0
2495 23:59:11.821650 [ModeRegInit_LP4] CH0 RK1
2496 23:59:11.824909 [ModeRegInit_LP4] CH1 RK0
2497 23:59:11.828163 [ModeRegInit_LP4] CH1 RK1
2498 23:59:11.828251 match AC timing 7
2499 23:59:11.831260 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2500 23:59:11.838332 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2501 23:59:11.841476 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2502 23:59:11.844962 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2503 23:59:11.851406 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2504 23:59:11.851501 ==
2505 23:59:11.854930 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:59:11.858309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 23:59:11.858398 ==
2508 23:59:11.865188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2509 23:59:11.868630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2510 23:59:11.878133 [CA 0] Center 39 (8~70) winsize 63
2511 23:59:11.881971 [CA 1] Center 39 (8~70) winsize 63
2512 23:59:11.885146 [CA 2] Center 35 (5~66) winsize 62
2513 23:59:11.888269 [CA 3] Center 34 (4~65) winsize 62
2514 23:59:11.891963 [CA 4] Center 33 (3~64) winsize 62
2515 23:59:11.894962 [CA 5] Center 32 (3~62) winsize 60
2516 23:59:11.895050
2517 23:59:11.898674 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2518 23:59:11.898761
2519 23:59:11.901875 [CATrainingPosCal] consider 1 rank data
2520 23:59:11.905042 u2DelayCellTimex100 = 270/100 ps
2521 23:59:11.908225 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2522 23:59:11.911527 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2523 23:59:11.918705 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2524 23:59:11.921876 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2525 23:59:11.925213 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2526 23:59:11.928525 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2527 23:59:11.928614
2528 23:59:11.931804 CA PerBit enable=1, Macro0, CA PI delay=32
2529 23:59:11.931895
2530 23:59:11.935052 [CBTSetCACLKResult] CA Dly = 32
2531 23:59:11.935139 CS Dly: 6 (0~37)
2532 23:59:11.935225 ==
2533 23:59:11.938438 Dram Type= 6, Freq= 0, CH_0, rank 1
2534 23:59:11.945124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 23:59:11.945234 ==
2536 23:59:11.948953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 23:59:11.954978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2538 23:59:11.964114 [CA 0] Center 38 (8~69) winsize 62
2539 23:59:11.967597 [CA 1] Center 38 (8~69) winsize 62
2540 23:59:11.970935 [CA 2] Center 35 (4~66) winsize 63
2541 23:59:11.974079 [CA 3] Center 34 (4~65) winsize 62
2542 23:59:11.977652 [CA 4] Center 33 (3~64) winsize 62
2543 23:59:11.980851 [CA 5] Center 32 (3~62) winsize 60
2544 23:59:11.980975
2545 23:59:11.983996 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2546 23:59:11.984140
2547 23:59:11.987547 [CATrainingPosCal] consider 2 rank data
2548 23:59:11.990776 u2DelayCellTimex100 = 270/100 ps
2549 23:59:11.994798 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2550 23:59:11.997965 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2551 23:59:12.003987 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2552 23:59:12.007777 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2553 23:59:12.011061 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2554 23:59:12.014354 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2555 23:59:12.014544
2556 23:59:12.017627 CA PerBit enable=1, Macro0, CA PI delay=32
2557 23:59:12.017760
2558 23:59:12.020809 [CBTSetCACLKResult] CA Dly = 32
2559 23:59:12.020926 CS Dly: 6 (0~38)
2560 23:59:12.021018
2561 23:59:12.024103 ----->DramcWriteLeveling(PI) begin...
2562 23:59:12.027351 ==
2563 23:59:12.027469 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 23:59:12.034142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 23:59:12.034307 ==
2566 23:59:12.037379 Write leveling (Byte 0): 32 => 32
2567 23:59:12.040704 Write leveling (Byte 1): 30 => 30
2568 23:59:12.040864 DramcWriteLeveling(PI) end<-----
2569 23:59:12.044005
2570 23:59:12.044142 ==
2571 23:59:12.047344 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 23:59:12.050902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 23:59:12.051038 ==
2574 23:59:12.054097 [Gating] SW mode calibration
2575 23:59:12.061036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2576 23:59:12.064378 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2577 23:59:12.070955 0 15 0 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2578 23:59:12.074247 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2579 23:59:12.077434 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 23:59:12.084677 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 23:59:12.087771 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 23:59:12.090762 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 23:59:12.097393 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2584 23:59:12.101526 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2585 23:59:12.104135 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2586 23:59:12.111266 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 23:59:12.114612 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:59:12.117776 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 23:59:12.124524 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 23:59:12.127691 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 23:59:12.131073 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
2592 23:59:12.134356 1 0 28 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
2593 23:59:12.141094 1 1 0 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2594 23:59:12.144567 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 23:59:12.147530 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:59:12.154451 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:59:12.157575 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 23:59:12.160774 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 23:59:12.168146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 23:59:12.171345 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 23:59:12.174634 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2602 23:59:12.181244 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:59:12.184205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:59:12.188134 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:59:12.194418 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:59:12.197626 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:59:12.201558 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:59:12.204789 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:59:12.211038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:59:12.214926 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:59:12.217929 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:59:12.224563 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:59:12.227768 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:59:12.231459 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:59:12.238073 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2616 23:59:12.241656 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 23:59:12.244912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2618 23:59:12.248057 Total UI for P1: 0, mck2ui 16
2619 23:59:12.251606 best dqsien dly found for B0: ( 1, 3, 26)
2620 23:59:12.257798 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 23:59:12.257889 Total UI for P1: 0, mck2ui 16
2622 23:59:12.264496 best dqsien dly found for B1: ( 1, 4, 0)
2623 23:59:12.267796 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2624 23:59:12.271064 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2625 23:59:12.271180
2626 23:59:12.274940 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2627 23:59:12.278364 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2628 23:59:12.281703 [Gating] SW calibration Done
2629 23:59:12.281908 ==
2630 23:59:12.284943 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 23:59:12.288175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 23:59:12.288267 ==
2633 23:59:12.291250 RX Vref Scan: 0
2634 23:59:12.291367
2635 23:59:12.291467 RX Vref 0 -> 0, step: 1
2636 23:59:12.291566
2637 23:59:12.294992 RX Delay -40 -> 252, step: 8
2638 23:59:12.297863 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2639 23:59:12.301807 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2640 23:59:12.308310 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2641 23:59:12.311548 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2642 23:59:12.314768 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2643 23:59:12.318025 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2644 23:59:12.321922 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2645 23:59:12.328415 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2646 23:59:12.331782 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2647 23:59:12.334889 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2648 23:59:12.338522 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2649 23:59:12.341518 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2650 23:59:12.348335 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2651 23:59:12.351816 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2652 23:59:12.355008 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2653 23:59:12.358390 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2654 23:59:12.358477 ==
2655 23:59:12.361915 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 23:59:12.364960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 23:59:12.368479 ==
2658 23:59:12.368610 DQS Delay:
2659 23:59:12.368728 DQS0 = 0, DQS1 = 0
2660 23:59:12.372104 DQM Delay:
2661 23:59:12.372192 DQM0 = 121, DQM1 = 113
2662 23:59:12.375303 DQ Delay:
2663 23:59:12.378540 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2664 23:59:12.381764 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2665 23:59:12.385016 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2666 23:59:12.388466 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2667 23:59:12.388595
2668 23:59:12.388712
2669 23:59:12.388830 ==
2670 23:59:12.391935 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 23:59:12.395070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 23:59:12.395198 ==
2673 23:59:12.395316
2674 23:59:12.395434
2675 23:59:12.398552 TX Vref Scan disable
2676 23:59:12.401479 == TX Byte 0 ==
2677 23:59:12.405236 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2678 23:59:12.408405 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2679 23:59:12.411655 == TX Byte 1 ==
2680 23:59:12.415077 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2681 23:59:12.418715 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2682 23:59:12.418849 ==
2683 23:59:12.422001 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 23:59:12.425258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 23:59:12.428541 ==
2686 23:59:12.438786 TX Vref=22, minBit 0, minWin=25, winSum=410
2687 23:59:12.442011 TX Vref=24, minBit 0, minWin=25, winSum=415
2688 23:59:12.445165 TX Vref=26, minBit 13, minWin=25, winSum=419
2689 23:59:12.448477 TX Vref=28, minBit 10, minWin=25, winSum=422
2690 23:59:12.451638 TX Vref=30, minBit 0, minWin=26, winSum=426
2691 23:59:12.458953 TX Vref=32, minBit 0, minWin=26, winSum=423
2692 23:59:12.462502 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2693 23:59:12.462637
2694 23:59:12.465383 Final TX Range 1 Vref 30
2695 23:59:12.465517
2696 23:59:12.465635 ==
2697 23:59:12.468424 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 23:59:12.472107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 23:59:12.472240 ==
2700 23:59:12.475362
2701 23:59:12.475494
2702 23:59:12.475614 TX Vref Scan disable
2703 23:59:12.478731 == TX Byte 0 ==
2704 23:59:12.482406 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2705 23:59:12.485295 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2706 23:59:12.488671 == TX Byte 1 ==
2707 23:59:12.492313 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 23:59:12.495738 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 23:59:12.495876
2710 23:59:12.499077 [DATLAT]
2711 23:59:12.499212 Freq=1200, CH0 RK0
2712 23:59:12.499334
2713 23:59:12.502122 DATLAT Default: 0xd
2714 23:59:12.502254 0, 0xFFFF, sum = 0
2715 23:59:12.505671 1, 0xFFFF, sum = 0
2716 23:59:12.505811 2, 0xFFFF, sum = 0
2717 23:59:12.508564 3, 0xFFFF, sum = 0
2718 23:59:12.508697 4, 0xFFFF, sum = 0
2719 23:59:12.512382 5, 0xFFFF, sum = 0
2720 23:59:12.512533 6, 0xFFFF, sum = 0
2721 23:59:12.515265 7, 0xFFFF, sum = 0
2722 23:59:12.515393 8, 0xFFFF, sum = 0
2723 23:59:12.518793 9, 0xFFFF, sum = 0
2724 23:59:12.522271 10, 0xFFFF, sum = 0
2725 23:59:12.522391 11, 0xFFFF, sum = 0
2726 23:59:12.525464 12, 0x0, sum = 1
2727 23:59:12.525581 13, 0x0, sum = 2
2728 23:59:12.525681 14, 0x0, sum = 3
2729 23:59:12.528673 15, 0x0, sum = 4
2730 23:59:12.528762 best_step = 13
2731 23:59:12.528832
2732 23:59:12.528896 ==
2733 23:59:12.532273 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 23:59:12.538754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 23:59:12.538919 ==
2736 23:59:12.539040 RX Vref Scan: 1
2737 23:59:12.539164
2738 23:59:12.541909 Set Vref Range= 32 -> 127
2739 23:59:12.542043
2740 23:59:12.545229 RX Vref 32 -> 127, step: 1
2741 23:59:12.545353
2742 23:59:12.548582 RX Delay -13 -> 252, step: 4
2743 23:59:12.548722
2744 23:59:12.551847 Set Vref, RX VrefLevel [Byte0]: 32
2745 23:59:12.555022 [Byte1]: 32
2746 23:59:12.555151
2747 23:59:12.558330 Set Vref, RX VrefLevel [Byte0]: 33
2748 23:59:12.562194 [Byte1]: 33
2749 23:59:12.562337
2750 23:59:12.565161 Set Vref, RX VrefLevel [Byte0]: 34
2751 23:59:12.568316 [Byte1]: 34
2752 23:59:12.572988
2753 23:59:12.573135 Set Vref, RX VrefLevel [Byte0]: 35
2754 23:59:12.576520 [Byte1]: 35
2755 23:59:12.580681
2756 23:59:12.580818 Set Vref, RX VrefLevel [Byte0]: 36
2757 23:59:12.583922 [Byte1]: 36
2758 23:59:12.588837
2759 23:59:12.588971 Set Vref, RX VrefLevel [Byte0]: 37
2760 23:59:12.591549 [Byte1]: 37
2761 23:59:12.596508
2762 23:59:12.596649 Set Vref, RX VrefLevel [Byte0]: 38
2763 23:59:12.599971 [Byte1]: 38
2764 23:59:12.604235
2765 23:59:12.604370 Set Vref, RX VrefLevel [Byte0]: 39
2766 23:59:12.607623 [Byte1]: 39
2767 23:59:12.611947
2768 23:59:12.612076 Set Vref, RX VrefLevel [Byte0]: 40
2769 23:59:12.615518 [Byte1]: 40
2770 23:59:12.620164
2771 23:59:12.620301 Set Vref, RX VrefLevel [Byte0]: 41
2772 23:59:12.623170 [Byte1]: 41
2773 23:59:12.628121
2774 23:59:12.628255 Set Vref, RX VrefLevel [Byte0]: 42
2775 23:59:12.631412 [Byte1]: 42
2776 23:59:12.636172
2777 23:59:12.636299 Set Vref, RX VrefLevel [Byte0]: 43
2778 23:59:12.639313 [Byte1]: 43
2779 23:59:12.643737
2780 23:59:12.643866 Set Vref, RX VrefLevel [Byte0]: 44
2781 23:59:12.646935 [Byte1]: 44
2782 23:59:12.651394
2783 23:59:12.651527 Set Vref, RX VrefLevel [Byte0]: 45
2784 23:59:12.655242 [Byte1]: 45
2785 23:59:12.659624
2786 23:59:12.659759 Set Vref, RX VrefLevel [Byte0]: 46
2787 23:59:12.662906 [Byte1]: 46
2788 23:59:12.667354
2789 23:59:12.667486 Set Vref, RX VrefLevel [Byte0]: 47
2790 23:59:12.670631 [Byte1]: 47
2791 23:59:12.675111
2792 23:59:12.675240 Set Vref, RX VrefLevel [Byte0]: 48
2793 23:59:12.678407 [Byte1]: 48
2794 23:59:12.683465
2795 23:59:12.683553 Set Vref, RX VrefLevel [Byte0]: 49
2796 23:59:12.686746 [Byte1]: 49
2797 23:59:12.691349
2798 23:59:12.691438 Set Vref, RX VrefLevel [Byte0]: 50
2799 23:59:12.694590 [Byte1]: 50
2800 23:59:12.699098
2801 23:59:12.699190 Set Vref, RX VrefLevel [Byte0]: 51
2802 23:59:12.702259 [Byte1]: 51
2803 23:59:12.706936
2804 23:59:12.707024 Set Vref, RX VrefLevel [Byte0]: 52
2805 23:59:12.710367 [Byte1]: 52
2806 23:59:12.714652
2807 23:59:12.714746 Set Vref, RX VrefLevel [Byte0]: 53
2808 23:59:12.717885 [Byte1]: 53
2809 23:59:12.722600
2810 23:59:12.722688 Set Vref, RX VrefLevel [Byte0]: 54
2811 23:59:12.726080 [Byte1]: 54
2812 23:59:12.730785
2813 23:59:12.730875 Set Vref, RX VrefLevel [Byte0]: 55
2814 23:59:12.734096 [Byte1]: 55
2815 23:59:12.738476
2816 23:59:12.738595 Set Vref, RX VrefLevel [Byte0]: 56
2817 23:59:12.741573 [Byte1]: 56
2818 23:59:12.746200
2819 23:59:12.746289 Set Vref, RX VrefLevel [Byte0]: 57
2820 23:59:12.749507 [Byte1]: 57
2821 23:59:12.754027
2822 23:59:12.754116 Set Vref, RX VrefLevel [Byte0]: 58
2823 23:59:12.757222 [Byte1]: 58
2824 23:59:12.762392
2825 23:59:12.762532 Set Vref, RX VrefLevel [Byte0]: 59
2826 23:59:12.765659 [Byte1]: 59
2827 23:59:12.770182
2828 23:59:12.770296 Set Vref, RX VrefLevel [Byte0]: 60
2829 23:59:12.773443 [Byte1]: 60
2830 23:59:12.778090
2831 23:59:12.778174 Set Vref, RX VrefLevel [Byte0]: 61
2832 23:59:12.781362 [Byte1]: 61
2833 23:59:12.785918
2834 23:59:12.786010 Set Vref, RX VrefLevel [Byte0]: 62
2835 23:59:12.789163 [Byte1]: 62
2836 23:59:12.793687
2837 23:59:12.793772 Set Vref, RX VrefLevel [Byte0]: 63
2838 23:59:12.796932 [Byte1]: 63
2839 23:59:12.801644
2840 23:59:12.801729 Set Vref, RX VrefLevel [Byte0]: 64
2841 23:59:12.804661 [Byte1]: 64
2842 23:59:12.809795
2843 23:59:12.809883 Set Vref, RX VrefLevel [Byte0]: 65
2844 23:59:12.812942 [Byte1]: 65
2845 23:59:12.817318
2846 23:59:12.817420 Set Vref, RX VrefLevel [Byte0]: 66
2847 23:59:12.820371 [Byte1]: 66
2848 23:59:12.825167
2849 23:59:12.825258 Set Vref, RX VrefLevel [Byte0]: 67
2850 23:59:12.828929 [Byte1]: 67
2851 23:59:12.833028
2852 23:59:12.833117 Set Vref, RX VrefLevel [Byte0]: 68
2853 23:59:12.836110 [Byte1]: 68
2854 23:59:12.840743
2855 23:59:12.840834 Set Vref, RX VrefLevel [Byte0]: 69
2856 23:59:12.844543 [Byte1]: 69
2857 23:59:12.848990
2858 23:59:12.849081 Final RX Vref Byte 0 = 57 to rank0
2859 23:59:12.852195 Final RX Vref Byte 1 = 48 to rank0
2860 23:59:12.855638 Final RX Vref Byte 0 = 57 to rank1
2861 23:59:12.858890 Final RX Vref Byte 1 = 48 to rank1==
2862 23:59:12.861848 Dram Type= 6, Freq= 0, CH_0, rank 0
2863 23:59:12.868841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 23:59:12.868954 ==
2865 23:59:12.869027 DQS Delay:
2866 23:59:12.869097 DQS0 = 0, DQS1 = 0
2867 23:59:12.872349 DQM Delay:
2868 23:59:12.872457 DQM0 = 120, DQM1 = 112
2869 23:59:12.875408 DQ Delay:
2870 23:59:12.878928 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2871 23:59:12.882237 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2872 23:59:12.885420 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2873 23:59:12.888643 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2874 23:59:12.888736
2875 23:59:12.888802
2876 23:59:12.899004 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2877 23:59:12.899128 CH0 RK0: MR19=404, MR18=150E
2878 23:59:12.905549 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2879 23:59:12.905668
2880 23:59:12.908832 ----->DramcWriteLeveling(PI) begin...
2881 23:59:12.908922 ==
2882 23:59:12.912138 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 23:59:12.915333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 23:59:12.918530 ==
2885 23:59:12.922003 Write leveling (Byte 0): 34 => 34
2886 23:59:12.922116 Write leveling (Byte 1): 27 => 27
2887 23:59:12.925643 DramcWriteLeveling(PI) end<-----
2888 23:59:12.925749
2889 23:59:12.925853 ==
2890 23:59:12.928897 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 23:59:12.935615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 23:59:12.935719 ==
2893 23:59:12.938547 [Gating] SW mode calibration
2894 23:59:12.945240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2895 23:59:12.948832 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2896 23:59:12.955444 0 15 0 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (0 0)
2897 23:59:12.958692 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 23:59:12.962231 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:59:12.968757 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 23:59:12.972364 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 23:59:12.975110 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 23:59:12.978580 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 23:59:12.985149 0 15 28 | B1->B0 | 3333 3131 | 0 0 | (1 0) (0 1)
2904 23:59:12.988665 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2905 23:59:12.992058 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 23:59:12.998456 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:59:13.002181 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 23:59:13.005499 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 23:59:13.012027 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 23:59:13.015296 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 23:59:13.018632 1 0 28 | B1->B0 | 3737 3939 | 0 0 | (0 0) (0 0)
2912 23:59:13.025882 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2913 23:59:13.028962 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:59:13.032064 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:59:13.039014 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 23:59:13.042339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 23:59:13.045598 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 23:59:13.052005 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 23:59:13.055674 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2920 23:59:13.058668 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2921 23:59:13.061861 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:59:13.069182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:59:13.072199 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:59:13.075450 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:59:13.082447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:59:13.085675 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:59:13.089272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:59:13.095736 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:59:13.099334 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:59:13.102635 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:59:13.109091 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:59:13.112597 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:59:13.115921 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:59:13.122278 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:59:13.125594 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2936 23:59:13.128863 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2937 23:59:13.132717 Total UI for P1: 0, mck2ui 16
2938 23:59:13.135848 best dqsien dly found for B0: ( 1, 3, 30)
2939 23:59:13.139117 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 23:59:13.142364 Total UI for P1: 0, mck2ui 16
2941 23:59:13.146034 best dqsien dly found for B1: ( 1, 3, 30)
2942 23:59:13.149409 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2943 23:59:13.152584 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2944 23:59:13.155842
2945 23:59:13.158994 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2946 23:59:13.162579 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2947 23:59:13.165586 [Gating] SW calibration Done
2948 23:59:13.165673 ==
2949 23:59:13.169382 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 23:59:13.172367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 23:59:13.172471 ==
2952 23:59:13.172558 RX Vref Scan: 0
2953 23:59:13.172641
2954 23:59:13.175935 RX Vref 0 -> 0, step: 1
2955 23:59:13.176022
2956 23:59:13.179158 RX Delay -40 -> 252, step: 8
2957 23:59:13.182406 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2958 23:59:13.185619 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2959 23:59:13.192816 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2960 23:59:13.195656 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2961 23:59:13.198749 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2962 23:59:13.202640 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2963 23:59:13.205741 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2964 23:59:13.212451 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2965 23:59:13.215527 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2966 23:59:13.219075 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2967 23:59:13.222563 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2968 23:59:13.225701 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2969 23:59:13.232617 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2970 23:59:13.235883 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2971 23:59:13.239089 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2972 23:59:13.242131 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2973 23:59:13.242228 ==
2974 23:59:13.245478 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 23:59:13.249318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 23:59:13.252519 ==
2977 23:59:13.252603 DQS Delay:
2978 23:59:13.252671 DQS0 = 0, DQS1 = 0
2979 23:59:13.255756 DQM Delay:
2980 23:59:13.255852 DQM0 = 122, DQM1 = 112
2981 23:59:13.258933 DQ Delay:
2982 23:59:13.262289 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2983 23:59:13.266061 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2984 23:59:13.269364 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2985 23:59:13.272396 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2986 23:59:13.272479
2987 23:59:13.272582
2988 23:59:13.272642 ==
2989 23:59:13.276039 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:59:13.279359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:59:13.279444 ==
2992 23:59:13.279510
2993 23:59:13.279596
2994 23:59:13.282574 TX Vref Scan disable
2995 23:59:13.285824 == TX Byte 0 ==
2996 23:59:13.289166 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2997 23:59:13.292315 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2998 23:59:13.295582 == TX Byte 1 ==
2999 23:59:13.299591 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3000 23:59:13.302734 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3001 23:59:13.302819 ==
3002 23:59:13.305924 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 23:59:13.309195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 23:59:13.312231 ==
3005 23:59:13.323370 TX Vref=22, minBit 3, minWin=25, winSum=414
3006 23:59:13.326659 TX Vref=24, minBit 3, minWin=25, winSum=418
3007 23:59:13.329746 TX Vref=26, minBit 3, minWin=25, winSum=418
3008 23:59:13.333681 TX Vref=28, minBit 1, minWin=26, winSum=424
3009 23:59:13.336422 TX Vref=30, minBit 1, minWin=26, winSum=423
3010 23:59:13.343438 TX Vref=32, minBit 12, minWin=25, winSum=424
3011 23:59:13.346458 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 28
3012 23:59:13.346546
3013 23:59:13.350280 Final TX Range 1 Vref 28
3014 23:59:13.350383
3015 23:59:13.350472 ==
3016 23:59:13.353317 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 23:59:13.356578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 23:59:13.356690 ==
3019 23:59:13.356787
3020 23:59:13.360412
3021 23:59:13.360562 TX Vref Scan disable
3022 23:59:13.363601 == TX Byte 0 ==
3023 23:59:13.366934 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3024 23:59:13.370048 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3025 23:59:13.373330 == TX Byte 1 ==
3026 23:59:13.376570 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3027 23:59:13.379926 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3028 23:59:13.383575
3029 23:59:13.383702 [DATLAT]
3030 23:59:13.383822 Freq=1200, CH0 RK1
3031 23:59:13.383936
3032 23:59:13.387130 DATLAT Default: 0xd
3033 23:59:13.387256 0, 0xFFFF, sum = 0
3034 23:59:13.390323 1, 0xFFFF, sum = 0
3035 23:59:13.390453 2, 0xFFFF, sum = 0
3036 23:59:13.393593 3, 0xFFFF, sum = 0
3037 23:59:13.393727 4, 0xFFFF, sum = 0
3038 23:59:13.396728 5, 0xFFFF, sum = 0
3039 23:59:13.396855 6, 0xFFFF, sum = 0
3040 23:59:13.400147 7, 0xFFFF, sum = 0
3041 23:59:13.403332 8, 0xFFFF, sum = 0
3042 23:59:13.403448 9, 0xFFFF, sum = 0
3043 23:59:13.406519 10, 0xFFFF, sum = 0
3044 23:59:13.406605 11, 0xFFFF, sum = 0
3045 23:59:13.410288 12, 0x0, sum = 1
3046 23:59:13.410373 13, 0x0, sum = 2
3047 23:59:13.413399 14, 0x0, sum = 3
3048 23:59:13.413485 15, 0x0, sum = 4
3049 23:59:13.413554 best_step = 13
3050 23:59:13.413616
3051 23:59:13.416687 ==
3052 23:59:13.416771 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 23:59:13.423797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 23:59:13.423883 ==
3055 23:59:13.423951 RX Vref Scan: 0
3056 23:59:13.424013
3057 23:59:13.426766 RX Vref 0 -> 0, step: 1
3058 23:59:13.426850
3059 23:59:13.430276 RX Delay -13 -> 252, step: 4
3060 23:59:13.433399 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3061 23:59:13.436548 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3062 23:59:13.443685 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3063 23:59:13.446724 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3064 23:59:13.450191 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3065 23:59:13.453527 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3066 23:59:13.457085 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3067 23:59:13.463577 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3068 23:59:13.466768 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3069 23:59:13.469991 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3070 23:59:13.473298 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3071 23:59:13.477058 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3072 23:59:13.483425 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3073 23:59:13.486796 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3074 23:59:13.489834 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3075 23:59:13.493622 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3076 23:59:13.493706 ==
3077 23:59:13.496770 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 23:59:13.503365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 23:59:13.503480 ==
3080 23:59:13.503578 DQS Delay:
3081 23:59:13.506618 DQS0 = 0, DQS1 = 0
3082 23:59:13.506715 DQM Delay:
3083 23:59:13.506809 DQM0 = 120, DQM1 = 110
3084 23:59:13.509957 DQ Delay:
3085 23:59:13.513235 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3086 23:59:13.516466 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3087 23:59:13.519874 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3088 23:59:13.523052 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3089 23:59:13.523162
3090 23:59:13.523289
3091 23:59:13.533266 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3092 23:59:13.533371 CH0 RK1: MR19=403, MR18=11F2
3093 23:59:13.539753 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3094 23:59:13.543502 [RxdqsGatingPostProcess] freq 1200
3095 23:59:13.550556 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3096 23:59:13.553253 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 23:59:13.557110 best DQS1 dly(2T, 0.5T) = (0, 12)
3098 23:59:13.557188 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 23:59:13.560246 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3100 23:59:13.563349 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 23:59:13.566733 best DQS1 dly(2T, 0.5T) = (0, 11)
3102 23:59:13.570188 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 23:59:13.573606 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3104 23:59:13.576689 Pre-setting of DQS Precalculation
3105 23:59:13.583362 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3106 23:59:13.583474 ==
3107 23:59:13.586858 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 23:59:13.590097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 23:59:13.590217 ==
3110 23:59:13.597164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 23:59:13.600324 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3112 23:59:13.609986 [CA 0] Center 37 (7~68) winsize 62
3113 23:59:13.613164 [CA 1] Center 37 (7~68) winsize 62
3114 23:59:13.616432 [CA 2] Center 34 (4~65) winsize 62
3115 23:59:13.619730 [CA 3] Center 34 (4~64) winsize 61
3116 23:59:13.622995 [CA 4] Center 34 (4~64) winsize 61
3117 23:59:13.626707 [CA 5] Center 33 (3~63) winsize 61
3118 23:59:13.626816
3119 23:59:13.629661 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3120 23:59:13.629745
3121 23:59:13.633430 [CATrainingPosCal] consider 1 rank data
3122 23:59:13.636747 u2DelayCellTimex100 = 270/100 ps
3123 23:59:13.639923 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 23:59:13.643148 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 23:59:13.649774 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3126 23:59:13.653652 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 23:59:13.656846 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 23:59:13.659963 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3129 23:59:13.660089
3130 23:59:13.663229 CA PerBit enable=1, Macro0, CA PI delay=33
3131 23:59:13.663354
3132 23:59:13.666533 [CBTSetCACLKResult] CA Dly = 33
3133 23:59:13.666665 CS Dly: 8 (0~39)
3134 23:59:13.666780 ==
3135 23:59:13.669774 Dram Type= 6, Freq= 0, CH_1, rank 1
3136 23:59:13.676322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 23:59:13.676419 ==
3138 23:59:13.680169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 23:59:13.686442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 23:59:13.695725 [CA 0] Center 37 (7~68) winsize 62
3141 23:59:13.698471 [CA 1] Center 37 (7~68) winsize 62
3142 23:59:13.702006 [CA 2] Center 35 (5~65) winsize 61
3143 23:59:13.705359 [CA 3] Center 34 (4~65) winsize 62
3144 23:59:13.709140 [CA 4] Center 34 (4~65) winsize 62
3145 23:59:13.712053 [CA 5] Center 34 (4~64) winsize 61
3146 23:59:13.712135
3147 23:59:13.715260 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3148 23:59:13.715347
3149 23:59:13.719083 [CATrainingPosCal] consider 2 rank data
3150 23:59:13.722245 u2DelayCellTimex100 = 270/100 ps
3151 23:59:13.725587 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 23:59:13.728755 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 23:59:13.735259 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 23:59:13.738988 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 23:59:13.742563 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 23:59:13.745777 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3157 23:59:13.745864
3158 23:59:13.749011 CA PerBit enable=1, Macro0, CA PI delay=33
3159 23:59:13.749098
3160 23:59:13.752151 [CBTSetCACLKResult] CA Dly = 33
3161 23:59:13.752263 CS Dly: 9 (0~41)
3162 23:59:13.752373
3163 23:59:13.755839 ----->DramcWriteLeveling(PI) begin...
3164 23:59:13.755926 ==
3165 23:59:13.759392 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 23:59:13.766063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 23:59:13.766160 ==
3168 23:59:13.769291 Write leveling (Byte 0): 28 => 28
3169 23:59:13.772566 Write leveling (Byte 1): 28 => 28
3170 23:59:13.772656 DramcWriteLeveling(PI) end<-----
3171 23:59:13.772762
3172 23:59:13.775778 ==
3173 23:59:13.779058 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 23:59:13.782295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 23:59:13.782385 ==
3176 23:59:13.786040 [Gating] SW mode calibration
3177 23:59:13.792464 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3178 23:59:13.795666 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3179 23:59:13.802367 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:59:13.805914 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:59:13.809260 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:59:13.816085 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 23:59:13.819573 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 23:59:13.822333 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 23:59:13.829154 0 15 24 | B1->B0 | 3131 2a2a | 1 1 | (1 0) (1 0)
3186 23:59:13.832685 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3187 23:59:13.835818 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:59:13.839516 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:59:13.845859 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:59:13.848972 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 23:59:13.852623 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 23:59:13.859570 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 23:59:13.862814 1 0 24 | B1->B0 | 2e2e 3a3a | 0 1 | (0 0) (1 1)
3194 23:59:13.865800 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:59:13.872917 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:59:13.876143 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:59:13.879332 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:59:13.885974 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:59:13.889308 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 23:59:13.892479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 23:59:13.899471 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3202 23:59:13.902576 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3203 23:59:13.906317 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:59:13.912748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:59:13.916022 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:59:13.919464 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:59:13.923081 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:59:13.929548 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:59:13.932561 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:59:13.936589 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:59:13.942956 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:59:13.945791 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:59:13.949389 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:59:13.956032 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:59:13.959327 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:59:13.962816 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:59:13.969112 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3218 23:59:13.972584 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 23:59:13.975860 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 23:59:13.979382 Total UI for P1: 0, mck2ui 16
3221 23:59:13.982374 best dqsien dly found for B0: ( 1, 3, 26)
3222 23:59:13.986107 Total UI for P1: 0, mck2ui 16
3223 23:59:13.989448 best dqsien dly found for B1: ( 1, 3, 26)
3224 23:59:13.992657 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3225 23:59:13.995915 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3226 23:59:13.995991
3227 23:59:14.002345 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3228 23:59:14.006180 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3229 23:59:14.006320 [Gating] SW calibration Done
3230 23:59:14.009504 ==
3231 23:59:14.009579 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 23:59:14.015890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 23:59:14.015996 ==
3234 23:59:14.016090 RX Vref Scan: 0
3235 23:59:14.016182
3236 23:59:14.019392 RX Vref 0 -> 0, step: 1
3237 23:59:14.019479
3238 23:59:14.022628 RX Delay -40 -> 252, step: 8
3239 23:59:14.025898 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3240 23:59:14.029224 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3241 23:59:14.032443 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3242 23:59:14.039474 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3243 23:59:14.042535 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3244 23:59:14.045880 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3245 23:59:14.049156 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3246 23:59:14.052404 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3247 23:59:14.059513 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3248 23:59:14.062459 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3249 23:59:14.065728 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3250 23:59:14.069545 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3251 23:59:14.072534 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3252 23:59:14.078939 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3253 23:59:14.082670 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3254 23:59:14.085932 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3255 23:59:14.086050 ==
3256 23:59:14.089203 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 23:59:14.092362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 23:59:14.092448 ==
3259 23:59:14.095759 DQS Delay:
3260 23:59:14.095844 DQS0 = 0, DQS1 = 0
3261 23:59:14.099588 DQM Delay:
3262 23:59:14.099682 DQM0 = 119, DQM1 = 116
3263 23:59:14.099750 DQ Delay:
3264 23:59:14.102809 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3265 23:59:14.109258 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3266 23:59:14.112539 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3267 23:59:14.116081 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3268 23:59:14.116298
3269 23:59:14.116441
3270 23:59:14.116568 ==
3271 23:59:14.119072 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 23:59:14.122617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 23:59:14.122782 ==
3274 23:59:14.122907
3275 23:59:14.123024
3276 23:59:14.125703 TX Vref Scan disable
3277 23:59:14.129491 == TX Byte 0 ==
3278 23:59:14.132703 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 23:59:14.135986 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 23:59:14.139268 == TX Byte 1 ==
3281 23:59:14.142926 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3282 23:59:14.146140 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3283 23:59:14.146254 ==
3284 23:59:14.149500 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 23:59:14.152763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 23:59:14.152848 ==
3287 23:59:14.165800 TX Vref=22, minBit 9, minWin=24, winSum=412
3288 23:59:14.168789 TX Vref=24, minBit 9, minWin=25, winSum=414
3289 23:59:14.172019 TX Vref=26, minBit 1, minWin=25, winSum=421
3290 23:59:14.175828 TX Vref=28, minBit 1, minWin=26, winSum=427
3291 23:59:14.179037 TX Vref=30, minBit 1, minWin=26, winSum=429
3292 23:59:14.182309 TX Vref=32, minBit 2, minWin=26, winSum=428
3293 23:59:14.189134 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3294 23:59:14.189251
3295 23:59:14.192193 Final TX Range 1 Vref 30
3296 23:59:14.192296
3297 23:59:14.192388 ==
3298 23:59:14.195372 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 23:59:14.199116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 23:59:14.199208 ==
3301 23:59:14.199276
3302 23:59:14.202178
3303 23:59:14.202253 TX Vref Scan disable
3304 23:59:14.205552 == TX Byte 0 ==
3305 23:59:14.208857 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 23:59:14.212315 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 23:59:14.215635 == TX Byte 1 ==
3308 23:59:14.218898 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 23:59:14.222165 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 23:59:14.222289
3311 23:59:14.225927 [DATLAT]
3312 23:59:14.226050 Freq=1200, CH1 RK0
3313 23:59:14.226169
3314 23:59:14.229074 DATLAT Default: 0xd
3315 23:59:14.229199 0, 0xFFFF, sum = 0
3316 23:59:14.232148 1, 0xFFFF, sum = 0
3317 23:59:14.232275 2, 0xFFFF, sum = 0
3318 23:59:14.235389 3, 0xFFFF, sum = 0
3319 23:59:14.235516 4, 0xFFFF, sum = 0
3320 23:59:14.239535 5, 0xFFFF, sum = 0
3321 23:59:14.239668 6, 0xFFFF, sum = 0
3322 23:59:14.242544 7, 0xFFFF, sum = 0
3323 23:59:14.242680 8, 0xFFFF, sum = 0
3324 23:59:14.245779 9, 0xFFFF, sum = 0
3325 23:59:14.248811 10, 0xFFFF, sum = 0
3326 23:59:14.248939 11, 0xFFFF, sum = 0
3327 23:59:14.252129 12, 0x0, sum = 1
3328 23:59:14.252270 13, 0x0, sum = 2
3329 23:59:14.252406 14, 0x0, sum = 3
3330 23:59:14.255356 15, 0x0, sum = 4
3331 23:59:14.255498 best_step = 13
3332 23:59:14.255614
3333 23:59:14.255735 ==
3334 23:59:14.259119 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 23:59:14.265701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 23:59:14.265827 ==
3337 23:59:14.265951 RX Vref Scan: 1
3338 23:59:14.266060
3339 23:59:14.268912 Set Vref Range= 32 -> 127
3340 23:59:14.269031
3341 23:59:14.272233 RX Vref 32 -> 127, step: 1
3342 23:59:14.272389
3343 23:59:14.275253 RX Delay -5 -> 252, step: 4
3344 23:59:14.275382
3345 23:59:14.279196 Set Vref, RX VrefLevel [Byte0]: 32
3346 23:59:14.281907 [Byte1]: 32
3347 23:59:14.282039
3348 23:59:14.285654 Set Vref, RX VrefLevel [Byte0]: 33
3349 23:59:14.288880 [Byte1]: 33
3350 23:59:14.288985
3351 23:59:14.291813 Set Vref, RX VrefLevel [Byte0]: 34
3352 23:59:14.295768 [Byte1]: 34
3353 23:59:14.299684
3354 23:59:14.299764 Set Vref, RX VrefLevel [Byte0]: 35
3355 23:59:14.302813 [Byte1]: 35
3356 23:59:14.307190
3357 23:59:14.307354 Set Vref, RX VrefLevel [Byte0]: 36
3358 23:59:14.310397 [Byte1]: 36
3359 23:59:14.314818
3360 23:59:14.314935 Set Vref, RX VrefLevel [Byte0]: 37
3361 23:59:14.318398 [Byte1]: 37
3362 23:59:14.323090
3363 23:59:14.323220 Set Vref, RX VrefLevel [Byte0]: 38
3364 23:59:14.325982 [Byte1]: 38
3365 23:59:14.331015
3366 23:59:14.331126 Set Vref, RX VrefLevel [Byte0]: 39
3367 23:59:14.334059 [Byte1]: 39
3368 23:59:14.338601
3369 23:59:14.338741 Set Vref, RX VrefLevel [Byte0]: 40
3370 23:59:14.341665 [Byte1]: 40
3371 23:59:14.346765
3372 23:59:14.346847 Set Vref, RX VrefLevel [Byte0]: 41
3373 23:59:14.349932 [Byte1]: 41
3374 23:59:14.354296
3375 23:59:14.354374 Set Vref, RX VrefLevel [Byte0]: 42
3376 23:59:14.357633 [Byte1]: 42
3377 23:59:14.362164
3378 23:59:14.362238 Set Vref, RX VrefLevel [Byte0]: 43
3379 23:59:14.365365 [Byte1]: 43
3380 23:59:14.369770
3381 23:59:14.369858 Set Vref, RX VrefLevel [Byte0]: 44
3382 23:59:14.373102 [Byte1]: 44
3383 23:59:14.377660
3384 23:59:14.377738 Set Vref, RX VrefLevel [Byte0]: 45
3385 23:59:14.380992 [Byte1]: 45
3386 23:59:14.385427
3387 23:59:14.385511 Set Vref, RX VrefLevel [Byte0]: 46
3388 23:59:14.389047 [Byte1]: 46
3389 23:59:14.393216
3390 23:59:14.393347 Set Vref, RX VrefLevel [Byte0]: 47
3391 23:59:14.396643 [Byte1]: 47
3392 23:59:14.401698
3393 23:59:14.401827 Set Vref, RX VrefLevel [Byte0]: 48
3394 23:59:14.405045 [Byte1]: 48
3395 23:59:14.409360
3396 23:59:14.409485 Set Vref, RX VrefLevel [Byte0]: 49
3397 23:59:14.412491 [Byte1]: 49
3398 23:59:14.417123
3399 23:59:14.417247 Set Vref, RX VrefLevel [Byte0]: 50
3400 23:59:14.420314 [Byte1]: 50
3401 23:59:14.424733
3402 23:59:14.424855 Set Vref, RX VrefLevel [Byte0]: 51
3403 23:59:14.428721 [Byte1]: 51
3404 23:59:14.432815
3405 23:59:14.432937 Set Vref, RX VrefLevel [Byte0]: 52
3406 23:59:14.436240 [Byte1]: 52
3407 23:59:14.440587
3408 23:59:14.440710 Set Vref, RX VrefLevel [Byte0]: 53
3409 23:59:14.443622 [Byte1]: 53
3410 23:59:14.448802
3411 23:59:14.448927 Set Vref, RX VrefLevel [Byte0]: 54
3412 23:59:14.451801 [Byte1]: 54
3413 23:59:14.456292
3414 23:59:14.456418 Set Vref, RX VrefLevel [Byte0]: 55
3415 23:59:14.459937 [Byte1]: 55
3416 23:59:14.464063
3417 23:59:14.464188 Set Vref, RX VrefLevel [Byte0]: 56
3418 23:59:14.467338 [Byte1]: 56
3419 23:59:14.471795
3420 23:59:14.471917 Set Vref, RX VrefLevel [Byte0]: 57
3421 23:59:14.475103 [Byte1]: 57
3422 23:59:14.479630
3423 23:59:14.479750 Set Vref, RX VrefLevel [Byte0]: 58
3424 23:59:14.483456 [Byte1]: 58
3425 23:59:14.488117
3426 23:59:14.488239 Set Vref, RX VrefLevel [Byte0]: 59
3427 23:59:14.490698 [Byte1]: 59
3428 23:59:14.495327
3429 23:59:14.495447 Set Vref, RX VrefLevel [Byte0]: 60
3430 23:59:14.498981 [Byte1]: 60
3431 23:59:14.503176
3432 23:59:14.503300 Set Vref, RX VrefLevel [Byte0]: 61
3433 23:59:14.506607 [Byte1]: 61
3434 23:59:14.511297
3435 23:59:14.511420 Set Vref, RX VrefLevel [Byte0]: 62
3436 23:59:14.514271 [Byte1]: 62
3437 23:59:14.518874
3438 23:59:14.518962 Set Vref, RX VrefLevel [Byte0]: 63
3439 23:59:14.522698 [Byte1]: 63
3440 23:59:14.527032
3441 23:59:14.527108 Set Vref, RX VrefLevel [Byte0]: 64
3442 23:59:14.530269 [Byte1]: 64
3443 23:59:14.535343
3444 23:59:14.535419 Set Vref, RX VrefLevel [Byte0]: 65
3445 23:59:14.537851 [Byte1]: 65
3446 23:59:14.542384
3447 23:59:14.542466 Set Vref, RX VrefLevel [Byte0]: 66
3448 23:59:14.545625 [Byte1]: 66
3449 23:59:14.550573
3450 23:59:14.550654 Set Vref, RX VrefLevel [Byte0]: 67
3451 23:59:14.553414 [Byte1]: 67
3452 23:59:14.558430
3453 23:59:14.558520 Set Vref, RX VrefLevel [Byte0]: 68
3454 23:59:14.561666 [Byte1]: 68
3455 23:59:14.565976
3456 23:59:14.566057 Set Vref, RX VrefLevel [Byte0]: 69
3457 23:59:14.569730 [Byte1]: 69
3458 23:59:14.573997
3459 23:59:14.574077 Final RX Vref Byte 0 = 55 to rank0
3460 23:59:14.577349 Final RX Vref Byte 1 = 48 to rank0
3461 23:59:14.580417 Final RX Vref Byte 0 = 55 to rank1
3462 23:59:14.583772 Final RX Vref Byte 1 = 48 to rank1==
3463 23:59:14.587618 Dram Type= 6, Freq= 0, CH_1, rank 0
3464 23:59:14.594250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 23:59:14.594337 ==
3466 23:59:14.594404 DQS Delay:
3467 23:59:14.594466 DQS0 = 0, DQS1 = 0
3468 23:59:14.597543 DQM Delay:
3469 23:59:14.597617 DQM0 = 120, DQM1 = 116
3470 23:59:14.600871 DQ Delay:
3471 23:59:14.604164 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3472 23:59:14.607455 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =122
3473 23:59:14.610534 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3474 23:59:14.613658 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3475 23:59:14.613750
3476 23:59:14.613817
3477 23:59:14.621079 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3478 23:59:14.623961 CH1 RK0: MR19=404, MR18=215
3479 23:59:14.630658 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3480 23:59:14.630748
3481 23:59:14.634485 ----->DramcWriteLeveling(PI) begin...
3482 23:59:14.634567 ==
3483 23:59:14.637231 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 23:59:14.640491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 23:59:14.640570 ==
3486 23:59:14.644316 Write leveling (Byte 0): 26 => 26
3487 23:59:14.647617 Write leveling (Byte 1): 30 => 30
3488 23:59:14.650957 DramcWriteLeveling(PI) end<-----
3489 23:59:14.651050
3490 23:59:14.651118 ==
3491 23:59:14.654172 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 23:59:14.657429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 23:59:14.660821 ==
3494 23:59:14.660905 [Gating] SW mode calibration
3495 23:59:14.671177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3496 23:59:14.674080 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3497 23:59:14.677821 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 23:59:14.684068 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 23:59:14.687582 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 23:59:14.690997 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 23:59:14.697731 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 23:59:14.701056 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3503 23:59:14.704274 0 15 24 | B1->B0 | 2c2c 3333 | 1 1 | (1 0) (1 0)
3504 23:59:14.710912 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3505 23:59:14.714471 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 23:59:14.717859 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 23:59:14.720826 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 23:59:14.728075 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 23:59:14.731243 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 23:59:14.734273 1 0 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3511 23:59:14.741531 1 0 24 | B1->B0 | 4545 2727 | 0 0 | (0 0) (1 1)
3512 23:59:14.744241 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3513 23:59:14.748156 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:59:14.754570 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 23:59:14.757840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 23:59:14.761134 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 23:59:14.767616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 23:59:14.771301 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3519 23:59:14.774458 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3520 23:59:14.781633 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3521 23:59:14.785014 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:59:14.788276 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:59:14.794622 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:59:14.798201 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:59:14.801141 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:59:14.804868 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:59:14.811172 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:59:14.815013 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:59:14.818289 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:59:14.824760 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:59:14.828016 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:59:14.831250 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:59:14.837800 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:59:14.841125 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3535 23:59:14.844458 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3536 23:59:14.847666 Total UI for P1: 0, mck2ui 16
3537 23:59:14.851514 best dqsien dly found for B1: ( 1, 3, 20)
3538 23:59:14.857945 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3539 23:59:14.861558 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 23:59:14.864464 Total UI for P1: 0, mck2ui 16
3541 23:59:14.867994 best dqsien dly found for B0: ( 1, 3, 26)
3542 23:59:14.871078 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3543 23:59:14.874847 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3544 23:59:14.874954
3545 23:59:14.877978 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3546 23:59:14.881536 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3547 23:59:14.884717 [Gating] SW calibration Done
3548 23:59:14.884814 ==
3549 23:59:14.887904 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 23:59:14.891173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 23:59:14.891261 ==
3552 23:59:14.894423 RX Vref Scan: 0
3553 23:59:14.894504
3554 23:59:14.897520 RX Vref 0 -> 0, step: 1
3555 23:59:14.897610
3556 23:59:14.897676 RX Delay -40 -> 252, step: 8
3557 23:59:14.904366 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3558 23:59:14.907626 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3559 23:59:14.910841 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3560 23:59:14.914180 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3561 23:59:14.918054 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3562 23:59:14.924812 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3563 23:59:14.927517 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3564 23:59:14.930949 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3565 23:59:14.934347 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3566 23:59:14.940842 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3567 23:59:14.944026 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3568 23:59:14.947396 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3569 23:59:14.950627 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3570 23:59:14.953767 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3571 23:59:14.961066 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3572 23:59:14.964300 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3573 23:59:14.964406 ==
3574 23:59:14.967362 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 23:59:14.971061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 23:59:14.971139 ==
3577 23:59:14.974035 DQS Delay:
3578 23:59:14.974117 DQS0 = 0, DQS1 = 0
3579 23:59:14.974183 DQM Delay:
3580 23:59:14.977457 DQM0 = 120, DQM1 = 118
3581 23:59:14.977608 DQ Delay:
3582 23:59:14.980899 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3583 23:59:14.983779 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3584 23:59:14.987700 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3585 23:59:14.994196 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3586 23:59:14.994344
3587 23:59:14.994472
3588 23:59:14.994596 ==
3589 23:59:14.997468 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 23:59:15.000671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 23:59:15.000809 ==
3592 23:59:15.000932
3593 23:59:15.001057
3594 23:59:15.003721 TX Vref Scan disable
3595 23:59:15.003858 == TX Byte 0 ==
3596 23:59:15.010300 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3597 23:59:15.013514 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3598 23:59:15.013660 == TX Byte 1 ==
3599 23:59:15.020231 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3600 23:59:15.023582 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3601 23:59:15.023671 ==
3602 23:59:15.026872 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 23:59:15.030358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 23:59:15.030438 ==
3605 23:59:15.043681 TX Vref=22, minBit 9, minWin=25, winSum=420
3606 23:59:15.046977 TX Vref=24, minBit 10, minWin=25, winSum=427
3607 23:59:15.050039 TX Vref=26, minBit 9, minWin=25, winSum=426
3608 23:59:15.053136 TX Vref=28, minBit 2, minWin=26, winSum=432
3609 23:59:15.056458 TX Vref=30, minBit 9, minWin=26, winSum=435
3610 23:59:15.063634 TX Vref=32, minBit 6, minWin=26, winSum=435
3611 23:59:15.066959 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3612 23:59:15.067073
3613 23:59:15.070375 Final TX Range 1 Vref 30
3614 23:59:15.070472
3615 23:59:15.070542 ==
3616 23:59:15.073363 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 23:59:15.076521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 23:59:15.076610 ==
3619 23:59:15.079708
3620 23:59:15.079793
3621 23:59:15.079860 TX Vref Scan disable
3622 23:59:15.083435 == TX Byte 0 ==
3623 23:59:15.086819 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3624 23:59:15.093146 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3625 23:59:15.093241 == TX Byte 1 ==
3626 23:59:15.096319 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3627 23:59:15.102837 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3628 23:59:15.102931
3629 23:59:15.103000 [DATLAT]
3630 23:59:15.103063 Freq=1200, CH1 RK1
3631 23:59:15.103124
3632 23:59:15.106468 DATLAT Default: 0xd
3633 23:59:15.106555 0, 0xFFFF, sum = 0
3634 23:59:15.109817 1, 0xFFFF, sum = 0
3635 23:59:15.112864 2, 0xFFFF, sum = 0
3636 23:59:15.112951 3, 0xFFFF, sum = 0
3637 23:59:15.116486 4, 0xFFFF, sum = 0
3638 23:59:15.116575 5, 0xFFFF, sum = 0
3639 23:59:15.119462 6, 0xFFFF, sum = 0
3640 23:59:15.119569 7, 0xFFFF, sum = 0
3641 23:59:15.123148 8, 0xFFFF, sum = 0
3642 23:59:15.123266 9, 0xFFFF, sum = 0
3643 23:59:15.126547 10, 0xFFFF, sum = 0
3644 23:59:15.126662 11, 0xFFFF, sum = 0
3645 23:59:15.129786 12, 0x0, sum = 1
3646 23:59:15.129902 13, 0x0, sum = 2
3647 23:59:15.133177 14, 0x0, sum = 3
3648 23:59:15.133263 15, 0x0, sum = 4
3649 23:59:15.136331 best_step = 13
3650 23:59:15.136416
3651 23:59:15.136481 ==
3652 23:59:15.139630 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 23:59:15.142886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 23:59:15.142972 ==
3655 23:59:15.143039 RX Vref Scan: 0
3656 23:59:15.146096
3657 23:59:15.146181 RX Vref 0 -> 0, step: 1
3658 23:59:15.146247
3659 23:59:15.149402 RX Delay -5 -> 252, step: 4
3660 23:59:15.152638 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3661 23:59:15.159569 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3662 23:59:15.162435 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3663 23:59:15.165824 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3664 23:59:15.169415 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3665 23:59:15.172581 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3666 23:59:15.179597 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3667 23:59:15.182966 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3668 23:59:15.186180 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3669 23:59:15.189316 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3670 23:59:15.192570 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3671 23:59:15.199646 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3672 23:59:15.202584 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3673 23:59:15.205793 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3674 23:59:15.209475 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3675 23:59:15.212470 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3676 23:59:15.216074 ==
3677 23:59:15.218939 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 23:59:15.222421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 23:59:15.222535 ==
3680 23:59:15.222633 DQS Delay:
3681 23:59:15.225891 DQS0 = 0, DQS1 = 0
3682 23:59:15.225965 DQM Delay:
3683 23:59:15.229314 DQM0 = 120, DQM1 = 116
3684 23:59:15.229399 DQ Delay:
3685 23:59:15.232763 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3686 23:59:15.236170 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3687 23:59:15.239268 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3688 23:59:15.242268 DQ12 =126, DQ13 =122, DQ14 =122, DQ15 =124
3689 23:59:15.242395
3690 23:59:15.242493
3691 23:59:15.252718 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3692 23:59:15.255975 CH1 RK1: MR19=403, MR18=14F0
3693 23:59:15.259180 CH1_RK1: MR19=0x403, MR18=0x14F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3694 23:59:15.262452 [RxdqsGatingPostProcess] freq 1200
3695 23:59:15.269370 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3696 23:59:15.272502 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 23:59:15.275430 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 23:59:15.279154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 23:59:15.282329 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 23:59:15.285688 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 23:59:15.288898 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 23:59:15.292578 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 23:59:15.295813 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 23:59:15.295929 Pre-setting of DQS Precalculation
3705 23:59:15.302240 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3706 23:59:15.308677 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3707 23:59:15.316249 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3708 23:59:15.316426
3709 23:59:15.316501
3710 23:59:15.318856 [Calibration Summary] 2400 Mbps
3711 23:59:15.322096 CH 0, Rank 0
3712 23:59:15.322206 SW Impedance : PASS
3713 23:59:15.325675 DUTY Scan : NO K
3714 23:59:15.328745 ZQ Calibration : PASS
3715 23:59:15.328844 Jitter Meter : NO K
3716 23:59:15.331862 CBT Training : PASS
3717 23:59:15.335616 Write leveling : PASS
3718 23:59:15.335713 RX DQS gating : PASS
3719 23:59:15.339066 RX DQ/DQS(RDDQC) : PASS
3720 23:59:15.342683 TX DQ/DQS : PASS
3721 23:59:15.342796 RX DATLAT : PASS
3722 23:59:15.345585 RX DQ/DQS(Engine): PASS
3723 23:59:15.345691 TX OE : NO K
3724 23:59:15.349058 All Pass.
3725 23:59:15.349144
3726 23:59:15.349212 CH 0, Rank 1
3727 23:59:15.351912 SW Impedance : PASS
3728 23:59:15.352005 DUTY Scan : NO K
3729 23:59:15.355165 ZQ Calibration : PASS
3730 23:59:15.358522 Jitter Meter : NO K
3731 23:59:15.358621 CBT Training : PASS
3732 23:59:15.362566 Write leveling : PASS
3733 23:59:15.365680 RX DQS gating : PASS
3734 23:59:15.365781 RX DQ/DQS(RDDQC) : PASS
3735 23:59:15.368978 TX DQ/DQS : PASS
3736 23:59:15.372349 RX DATLAT : PASS
3737 23:59:15.372501 RX DQ/DQS(Engine): PASS
3738 23:59:15.375523 TX OE : NO K
3739 23:59:15.375639 All Pass.
3740 23:59:15.375737
3741 23:59:15.378874 CH 1, Rank 0
3742 23:59:15.378986 SW Impedance : PASS
3743 23:59:15.382176 DUTY Scan : NO K
3744 23:59:15.385621 ZQ Calibration : PASS
3745 23:59:15.385707 Jitter Meter : NO K
3746 23:59:15.388535 CBT Training : PASS
3747 23:59:15.392124 Write leveling : PASS
3748 23:59:15.392212 RX DQS gating : PASS
3749 23:59:15.394994 RX DQ/DQS(RDDQC) : PASS
3750 23:59:15.395083 TX DQ/DQS : PASS
3751 23:59:15.398777 RX DATLAT : PASS
3752 23:59:15.401817 RX DQ/DQS(Engine): PASS
3753 23:59:15.401899 TX OE : NO K
3754 23:59:15.405116 All Pass.
3755 23:59:15.405194
3756 23:59:15.405264 CH 1, Rank 1
3757 23:59:15.408377 SW Impedance : PASS
3758 23:59:15.408494 DUTY Scan : NO K
3759 23:59:15.412308 ZQ Calibration : PASS
3760 23:59:15.415589 Jitter Meter : NO K
3761 23:59:15.415714 CBT Training : PASS
3762 23:59:15.418232 Write leveling : PASS
3763 23:59:15.422118 RX DQS gating : PASS
3764 23:59:15.422211 RX DQ/DQS(RDDQC) : PASS
3765 23:59:15.425328 TX DQ/DQS : PASS
3766 23:59:15.428471 RX DATLAT : PASS
3767 23:59:15.428563 RX DQ/DQS(Engine): PASS
3768 23:59:15.431637 TX OE : NO K
3769 23:59:15.431809 All Pass.
3770 23:59:15.431921
3771 23:59:15.435425 DramC Write-DBI off
3772 23:59:15.438670 PER_BANK_REFRESH: Hybrid Mode
3773 23:59:15.438812 TX_TRACKING: ON
3774 23:59:15.448459 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 23:59:15.452126 [FAST_K] Save calibration result to emmc
3776 23:59:15.455436 dramc_set_vcore_voltage set vcore to 650000
3777 23:59:15.458747 Read voltage for 600, 5
3778 23:59:15.458835 Vio18 = 0
3779 23:59:15.458904 Vcore = 650000
3780 23:59:15.461519 Vdram = 0
3781 23:59:15.461606 Vddq = 0
3782 23:59:15.461674 Vmddr = 0
3783 23:59:15.468655 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 23:59:15.471686 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 23:59:15.474954 MEM_TYPE=3, freq_sel=19
3786 23:59:15.478329 sv_algorithm_assistance_LP4_1600
3787 23:59:15.481460 ============ PULL DRAM RESETB DOWN ============
3788 23:59:15.484742 ========== PULL DRAM RESETB DOWN end =========
3789 23:59:15.491301 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 23:59:15.495111 ===================================
3791 23:59:15.495230 LPDDR4 DRAM CONFIGURATION
3792 23:59:15.498297 ===================================
3793 23:59:15.501846 EX_ROW_EN[0] = 0x0
3794 23:59:15.504789 EX_ROW_EN[1] = 0x0
3795 23:59:15.504872 LP4Y_EN = 0x0
3796 23:59:15.508361 WORK_FSP = 0x0
3797 23:59:15.508479 WL = 0x2
3798 23:59:15.511684 RL = 0x2
3799 23:59:15.511811 BL = 0x2
3800 23:59:15.514693 RPST = 0x0
3801 23:59:15.514800 RD_PRE = 0x0
3802 23:59:15.518013 WR_PRE = 0x1
3803 23:59:15.518122 WR_PST = 0x0
3804 23:59:15.521530 DBI_WR = 0x0
3805 23:59:15.521639 DBI_RD = 0x0
3806 23:59:15.524651 OTF = 0x1
3807 23:59:15.528414 ===================================
3808 23:59:15.531602 ===================================
3809 23:59:15.531717 ANA top config
3810 23:59:15.534558 ===================================
3811 23:59:15.538406 DLL_ASYNC_EN = 0
3812 23:59:15.541569 ALL_SLAVE_EN = 1
3813 23:59:15.545001 NEW_RANK_MODE = 1
3814 23:59:15.545090 DLL_IDLE_MODE = 1
3815 23:59:15.548288 LP45_APHY_COMB_EN = 1
3816 23:59:15.551491 TX_ODT_DIS = 1
3817 23:59:15.554574 NEW_8X_MODE = 1
3818 23:59:15.557890 ===================================
3819 23:59:15.561312 ===================================
3820 23:59:15.565041 data_rate = 1200
3821 23:59:15.565128 CKR = 1
3822 23:59:15.568229 DQ_P2S_RATIO = 8
3823 23:59:15.571635 ===================================
3824 23:59:15.574601 CA_P2S_RATIO = 8
3825 23:59:15.577689 DQ_CA_OPEN = 0
3826 23:59:15.581279 DQ_SEMI_OPEN = 0
3827 23:59:15.584785 CA_SEMI_OPEN = 0
3828 23:59:15.584879 CA_FULL_RATE = 0
3829 23:59:15.588016 DQ_CKDIV4_EN = 1
3830 23:59:15.591400 CA_CKDIV4_EN = 1
3831 23:59:15.594378 CA_PREDIV_EN = 0
3832 23:59:15.598133 PH8_DLY = 0
3833 23:59:15.601356 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3834 23:59:15.601442 DQ_AAMCK_DIV = 4
3835 23:59:15.604610 CA_AAMCK_DIV = 4
3836 23:59:15.607831 CA_ADMCK_DIV = 4
3837 23:59:15.611099 DQ_TRACK_CA_EN = 0
3838 23:59:15.614523 CA_PICK = 600
3839 23:59:15.617325 CA_MCKIO = 600
3840 23:59:15.617415 MCKIO_SEMI = 0
3841 23:59:15.621195 PLL_FREQ = 2288
3842 23:59:15.624313 DQ_UI_PI_RATIO = 32
3843 23:59:15.627445 CA_UI_PI_RATIO = 0
3844 23:59:15.631369 ===================================
3845 23:59:15.634347 ===================================
3846 23:59:15.637334 memory_type:LPDDR4
3847 23:59:15.637421 GP_NUM : 10
3848 23:59:15.640648 SRAM_EN : 1
3849 23:59:15.643871 MD32_EN : 0
3850 23:59:15.647378 ===================================
3851 23:59:15.647478 [ANA_INIT] >>>>>>>>>>>>>>
3852 23:59:15.651002 <<<<<< [CONFIGURE PHASE]: ANA_TX
3853 23:59:15.654326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3854 23:59:15.657489 ===================================
3855 23:59:15.660767 data_rate = 1200,PCW = 0X5800
3856 23:59:15.664049 ===================================
3857 23:59:15.667439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3858 23:59:15.673889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 23:59:15.677031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 23:59:15.684187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3861 23:59:15.687514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3862 23:59:15.690732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3863 23:59:15.694039 [ANA_INIT] flow start
3864 23:59:15.694152 [ANA_INIT] PLL >>>>>>>>
3865 23:59:15.697246 [ANA_INIT] PLL <<<<<<<<
3866 23:59:15.700917 [ANA_INIT] MIDPI >>>>>>>>
3867 23:59:15.701036 [ANA_INIT] MIDPI <<<<<<<<
3868 23:59:15.703866 [ANA_INIT] DLL >>>>>>>>
3869 23:59:15.707346 [ANA_INIT] flow end
3870 23:59:15.710706 ============ LP4 DIFF to SE enter ============
3871 23:59:15.713566 ============ LP4 DIFF to SE exit ============
3872 23:59:15.717375 [ANA_INIT] <<<<<<<<<<<<<
3873 23:59:15.720634 [Flow] Enable top DCM control >>>>>
3874 23:59:15.723847 [Flow] Enable top DCM control <<<<<
3875 23:59:15.727156 Enable DLL master slave shuffle
3876 23:59:15.730287 ==============================================================
3877 23:59:15.733956 Gating Mode config
3878 23:59:15.737098 ==============================================================
3879 23:59:15.740292 Config description:
3880 23:59:15.750916 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3881 23:59:15.756911 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3882 23:59:15.760247 SELPH_MODE 0: By rank 1: By Phase
3883 23:59:15.766764 ==============================================================
3884 23:59:15.770485 GAT_TRACK_EN = 1
3885 23:59:15.773861 RX_GATING_MODE = 2
3886 23:59:15.777258 RX_GATING_TRACK_MODE = 2
3887 23:59:15.780508 SELPH_MODE = 1
3888 23:59:15.783837 PICG_EARLY_EN = 1
3889 23:59:15.783980 VALID_LAT_VALUE = 1
3890 23:59:15.790465 ==============================================================
3891 23:59:15.793603 Enter into Gating configuration >>>>
3892 23:59:15.796868 Exit from Gating configuration <<<<
3893 23:59:15.800725 Enter into DVFS_PRE_config >>>>>
3894 23:59:15.810478 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3895 23:59:15.813676 Exit from DVFS_PRE_config <<<<<
3896 23:59:15.817693 Enter into PICG configuration >>>>
3897 23:59:15.820322 Exit from PICG configuration <<<<
3898 23:59:15.823258 [RX_INPUT] configuration >>>>>
3899 23:59:15.826751 [RX_INPUT] configuration <<<<<
3900 23:59:15.829942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3901 23:59:15.836541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3902 23:59:15.843816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 23:59:15.850037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 23:59:15.856540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 23:59:15.863189 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 23:59:15.866426 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3907 23:59:15.870100 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3908 23:59:15.873105 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3909 23:59:15.876665 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3910 23:59:15.883526 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3911 23:59:15.886477 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 23:59:15.889622 ===================================
3913 23:59:15.893071 LPDDR4 DRAM CONFIGURATION
3914 23:59:15.896622 ===================================
3915 23:59:15.896763 EX_ROW_EN[0] = 0x0
3916 23:59:15.899858 EX_ROW_EN[1] = 0x0
3917 23:59:15.899965 LP4Y_EN = 0x0
3918 23:59:15.903177 WORK_FSP = 0x0
3919 23:59:15.903284 WL = 0x2
3920 23:59:15.906487 RL = 0x2
3921 23:59:15.909643 BL = 0x2
3922 23:59:15.909753 RPST = 0x0
3923 23:59:15.912942 RD_PRE = 0x0
3924 23:59:15.913024 WR_PRE = 0x1
3925 23:59:15.916186 WR_PST = 0x0
3926 23:59:15.916300 DBI_WR = 0x0
3927 23:59:15.919428 DBI_RD = 0x0
3928 23:59:15.919555 OTF = 0x1
3929 23:59:15.923184 ===================================
3930 23:59:15.926610 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3931 23:59:15.932936 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3932 23:59:15.936053 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 23:59:15.939748 ===================================
3934 23:59:15.942749 LPDDR4 DRAM CONFIGURATION
3935 23:59:15.946214 ===================================
3936 23:59:15.946351 EX_ROW_EN[0] = 0x10
3937 23:59:15.949466 EX_ROW_EN[1] = 0x0
3938 23:59:15.949585 LP4Y_EN = 0x0
3939 23:59:15.952716 WORK_FSP = 0x0
3940 23:59:15.952826 WL = 0x2
3941 23:59:15.955916 RL = 0x2
3942 23:59:15.956007 BL = 0x2
3943 23:59:15.959295 RPST = 0x0
3944 23:59:15.962590 RD_PRE = 0x0
3945 23:59:15.962731 WR_PRE = 0x1
3946 23:59:15.965899 WR_PST = 0x0
3947 23:59:15.966015 DBI_WR = 0x0
3948 23:59:15.969193 DBI_RD = 0x0
3949 23:59:15.969293 OTF = 0x1
3950 23:59:15.972855 ===================================
3951 23:59:15.979383 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3952 23:59:15.983163 nWR fixed to 30
3953 23:59:15.986327 [ModeRegInit_LP4] CH0 RK0
3954 23:59:15.986435 [ModeRegInit_LP4] CH0 RK1
3955 23:59:15.989537 [ModeRegInit_LP4] CH1 RK0
3956 23:59:15.993317 [ModeRegInit_LP4] CH1 RK1
3957 23:59:15.993426 match AC timing 17
3958 23:59:15.999812 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3959 23:59:16.002982 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3960 23:59:16.006167 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3961 23:59:16.012619 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3962 23:59:16.016531 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3963 23:59:16.016675 ==
3964 23:59:16.019687 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 23:59:16.023004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 23:59:16.023092 ==
3967 23:59:16.029439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 23:59:16.036597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3969 23:59:16.039256 [CA 0] Center 35 (5~66) winsize 62
3970 23:59:16.043154 [CA 1] Center 35 (5~66) winsize 62
3971 23:59:16.046452 [CA 2] Center 33 (3~64) winsize 62
3972 23:59:16.049653 [CA 3] Center 33 (2~64) winsize 63
3973 23:59:16.052876 [CA 4] Center 33 (2~64) winsize 63
3974 23:59:16.056009 [CA 5] Center 32 (2~63) winsize 62
3975 23:59:16.056131
3976 23:59:16.059581 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3977 23:59:16.059704
3978 23:59:16.062865 [CATrainingPosCal] consider 1 rank data
3979 23:59:16.065936 u2DelayCellTimex100 = 270/100 ps
3980 23:59:16.069486 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3981 23:59:16.072981 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3982 23:59:16.076260 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3983 23:59:16.079092 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3984 23:59:16.082463 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3985 23:59:16.086418 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3986 23:59:16.089553
3987 23:59:16.092562 CA PerBit enable=1, Macro0, CA PI delay=32
3988 23:59:16.092645
3989 23:59:16.096034 [CBTSetCACLKResult] CA Dly = 32
3990 23:59:16.096151 CS Dly: 4 (0~35)
3991 23:59:16.096253 ==
3992 23:59:16.099319 Dram Type= 6, Freq= 0, CH_0, rank 1
3993 23:59:16.102548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 23:59:16.102666 ==
3995 23:59:16.109664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 23:59:16.116041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3997 23:59:16.119449 [CA 0] Center 35 (5~66) winsize 62
3998 23:59:16.122392 [CA 1] Center 35 (5~66) winsize 62
3999 23:59:16.125735 [CA 2] Center 33 (3~64) winsize 62
4000 23:59:16.129577 [CA 3] Center 33 (3~64) winsize 62
4001 23:59:16.132816 [CA 4] Center 32 (2~63) winsize 62
4002 23:59:16.135968 [CA 5] Center 32 (2~63) winsize 62
4003 23:59:16.136080
4004 23:59:16.139330 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4005 23:59:16.139434
4006 23:59:16.142509 [CATrainingPosCal] consider 2 rank data
4007 23:59:16.145780 u2DelayCellTimex100 = 270/100 ps
4008 23:59:16.149063 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4009 23:59:16.152968 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4010 23:59:16.156299 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4011 23:59:16.159582 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4012 23:59:16.163051 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4013 23:59:16.169259 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4014 23:59:16.169419
4015 23:59:16.172637 CA PerBit enable=1, Macro0, CA PI delay=32
4016 23:59:16.172726
4017 23:59:16.175818 [CBTSetCACLKResult] CA Dly = 32
4018 23:59:16.175917 CS Dly: 4 (0~36)
4019 23:59:16.176019
4020 23:59:16.179537 ----->DramcWriteLeveling(PI) begin...
4021 23:59:16.179639 ==
4022 23:59:16.182703 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 23:59:16.186315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 23:59:16.189221 ==
4025 23:59:16.189322 Write leveling (Byte 0): 34 => 34
4026 23:59:16.192780 Write leveling (Byte 1): 33 => 33
4027 23:59:16.196029 DramcWriteLeveling(PI) end<-----
4028 23:59:16.196129
4029 23:59:16.196197 ==
4030 23:59:16.199109 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 23:59:16.205861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 23:59:16.205990 ==
4033 23:59:16.209256 [Gating] SW mode calibration
4034 23:59:16.216048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 23:59:16.219363 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4036 23:59:16.225758 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 23:59:16.229713 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 23:59:16.232516 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 23:59:16.236107 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4040 23:59:16.242862 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4041 23:59:16.246014 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 23:59:16.249160 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 23:59:16.255644 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 23:59:16.259356 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 23:59:16.262573 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 23:59:16.268942 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 23:59:16.272617 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
4048 23:59:16.275299 0 10 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
4049 23:59:16.282480 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:59:16.285704 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:59:16.289021 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:59:16.295442 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 23:59:16.299051 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 23:59:16.302036 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 23:59:16.308907 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4056 23:59:16.312034 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4057 23:59:16.315649 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:59:16.322312 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:59:16.325588 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:59:16.328700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:59:16.335173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:59:16.338464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:59:16.341652 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:59:16.348596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:59:16.352071 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:59:16.355482 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:59:16.361821 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:59:16.365143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:59:16.368489 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:59:16.374851 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:59:16.378412 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4072 23:59:16.381721 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 23:59:16.384818 Total UI for P1: 0, mck2ui 16
4074 23:59:16.388192 best dqsien dly found for B0: ( 0, 13, 12)
4075 23:59:16.391459 Total UI for P1: 0, mck2ui 16
4076 23:59:16.395346 best dqsien dly found for B1: ( 0, 13, 14)
4077 23:59:16.398513 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4078 23:59:16.401868 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4079 23:59:16.401969
4080 23:59:16.405131 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4081 23:59:16.411468 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4082 23:59:16.411709 [Gating] SW calibration Done
4083 23:59:16.411814 ==
4084 23:59:16.415029 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 23:59:16.421343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 23:59:16.421461 ==
4087 23:59:16.421565 RX Vref Scan: 0
4088 23:59:16.421668
4089 23:59:16.424792 RX Vref 0 -> 0, step: 1
4090 23:59:16.424878
4091 23:59:16.428326 RX Delay -230 -> 252, step: 16
4092 23:59:16.431711 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4093 23:59:16.435458 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4094 23:59:16.441200 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4095 23:59:16.444382 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4096 23:59:16.448315 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4097 23:59:16.451588 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4098 23:59:16.454739 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4099 23:59:16.461033 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4100 23:59:16.464537 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4101 23:59:16.467642 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4102 23:59:16.471317 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4103 23:59:16.477711 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4104 23:59:16.481379 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4105 23:59:16.484650 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4106 23:59:16.487472 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4107 23:59:16.494109 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4108 23:59:16.494396 ==
4109 23:59:16.497410 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 23:59:16.501341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 23:59:16.501485 ==
4112 23:59:16.501605 DQS Delay:
4113 23:59:16.504551 DQS0 = 0, DQS1 = 0
4114 23:59:16.504678 DQM Delay:
4115 23:59:16.507891 DQM0 = 53, DQM1 = 46
4116 23:59:16.508016 DQ Delay:
4117 23:59:16.511298 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4118 23:59:16.514179 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4119 23:59:16.517453 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4120 23:59:16.520795 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4121 23:59:16.520880
4122 23:59:16.520947
4123 23:59:16.521008 ==
4124 23:59:16.524500 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 23:59:16.527581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 23:59:16.527698 ==
4127 23:59:16.527797
4128 23:59:16.527910
4129 23:59:16.530688 TX Vref Scan disable
4130 23:59:16.534373 == TX Byte 0 ==
4131 23:59:16.537701 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4132 23:59:16.540639 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4133 23:59:16.544139 == TX Byte 1 ==
4134 23:59:16.547631 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4135 23:59:16.550788 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4136 23:59:16.550875 ==
4137 23:59:16.554511 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 23:59:16.560713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 23:59:16.560802 ==
4140 23:59:16.560891
4141 23:59:16.560975
4142 23:59:16.561056 TX Vref Scan disable
4143 23:59:16.565087 == TX Byte 0 ==
4144 23:59:16.568422 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4145 23:59:16.575068 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4146 23:59:16.575164 == TX Byte 1 ==
4147 23:59:16.578191 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4148 23:59:16.584882 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4149 23:59:16.585013
4150 23:59:16.585119 [DATLAT]
4151 23:59:16.585224 Freq=600, CH0 RK0
4152 23:59:16.585320
4153 23:59:16.588537 DATLAT Default: 0x9
4154 23:59:16.588627 0, 0xFFFF, sum = 0
4155 23:59:16.591543 1, 0xFFFF, sum = 0
4156 23:59:16.594984 2, 0xFFFF, sum = 0
4157 23:59:16.595087 3, 0xFFFF, sum = 0
4158 23:59:16.597973 4, 0xFFFF, sum = 0
4159 23:59:16.598095 5, 0xFFFF, sum = 0
4160 23:59:16.601341 6, 0xFFFF, sum = 0
4161 23:59:16.601439 7, 0xFFFF, sum = 0
4162 23:59:16.604654 8, 0x0, sum = 1
4163 23:59:16.604750 9, 0x0, sum = 2
4164 23:59:16.604840 10, 0x0, sum = 3
4165 23:59:16.608516 11, 0x0, sum = 4
4166 23:59:16.608611 best_step = 9
4167 23:59:16.608700
4168 23:59:16.608784 ==
4169 23:59:16.611690 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 23:59:16.618381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 23:59:16.618506 ==
4172 23:59:16.618601 RX Vref Scan: 1
4173 23:59:16.618685
4174 23:59:16.621667 RX Vref 0 -> 0, step: 1
4175 23:59:16.621762
4176 23:59:16.624963 RX Delay -163 -> 252, step: 8
4177 23:59:16.625059
4178 23:59:16.628355 Set Vref, RX VrefLevel [Byte0]: 57
4179 23:59:16.631601 [Byte1]: 48
4180 23:59:16.631699
4181 23:59:16.634839 Final RX Vref Byte 0 = 57 to rank0
4182 23:59:16.637872 Final RX Vref Byte 1 = 48 to rank0
4183 23:59:16.641172 Final RX Vref Byte 0 = 57 to rank1
4184 23:59:16.644484 Final RX Vref Byte 1 = 48 to rank1==
4185 23:59:16.647703 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 23:59:16.651217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 23:59:16.651306 ==
4188 23:59:16.654443 DQS Delay:
4189 23:59:16.654529 DQS0 = 0, DQS1 = 0
4190 23:59:16.658536 DQM Delay:
4191 23:59:16.658622 DQM0 = 52, DQM1 = 46
4192 23:59:16.658709 DQ Delay:
4193 23:59:16.661365 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4194 23:59:16.664279 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4195 23:59:16.667910 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4196 23:59:16.671083 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4197 23:59:16.671169
4198 23:59:16.671273
4199 23:59:16.680995 [DQSOSCAuto] RK0, (LSB)MR18= 0x7367, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4200 23:59:16.684439 CH0 RK0: MR19=808, MR18=7367
4201 23:59:16.687677 CH0_RK0: MR19=0x808, MR18=0x7367, DQSOSC=388, MR23=63, INC=174, DEC=116
4202 23:59:16.691256
4203 23:59:16.694417 ----->DramcWriteLeveling(PI) begin...
4204 23:59:16.694506 ==
4205 23:59:16.697613 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 23:59:16.701245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 23:59:16.701337 ==
4208 23:59:16.704792 Write leveling (Byte 0): 34 => 34
4209 23:59:16.708217 Write leveling (Byte 1): 33 => 33
4210 23:59:16.711536 DramcWriteLeveling(PI) end<-----
4211 23:59:16.711623
4212 23:59:16.711709 ==
4213 23:59:16.714754 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 23:59:16.718071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 23:59:16.718188 ==
4216 23:59:16.721400 [Gating] SW mode calibration
4217 23:59:16.727856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 23:59:16.731748 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 23:59:16.738113 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 23:59:16.741362 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 23:59:16.744456 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 23:59:16.751586 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
4223 23:59:16.754753 0 9 16 | B1->B0 | 2c2c 2828 | 0 0 | (1 1) (0 0)
4224 23:59:16.757810 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:59:16.764253 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 23:59:16.768161 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 23:59:16.771383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 23:59:16.777818 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 23:59:16.781404 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 23:59:16.784390 0 10 12 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4231 23:59:16.791325 0 10 16 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
4232 23:59:16.794658 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:59:16.797916 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:59:16.804125 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:59:16.807929 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:59:16.810952 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:59:16.817471 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 23:59:16.820794 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4239 23:59:16.823986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:59:16.830666 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:59:16.833997 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:59:16.837344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:59:16.844691 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:59:16.847598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:59:16.850796 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:59:16.857729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:59:16.860996 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:59:16.864176 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:59:16.867361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:59:16.874165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:59:16.877360 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:59:16.880643 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:59:16.887229 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:59:16.890746 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4255 23:59:16.893830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 23:59:16.897425 Total UI for P1: 0, mck2ui 16
4257 23:59:16.900889 best dqsien dly found for B0: ( 0, 13, 12)
4258 23:59:16.903867 Total UI for P1: 0, mck2ui 16
4259 23:59:16.907167 best dqsien dly found for B1: ( 0, 13, 12)
4260 23:59:16.910776 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4261 23:59:16.917133 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4262 23:59:16.917227
4263 23:59:16.920129 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4264 23:59:16.923874 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 23:59:16.926914 [Gating] SW calibration Done
4266 23:59:16.926997 ==
4267 23:59:16.930625 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 23:59:16.934083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 23:59:16.934166 ==
4270 23:59:16.937271 RX Vref Scan: 0
4271 23:59:16.937349
4272 23:59:16.937441 RX Vref 0 -> 0, step: 1
4273 23:59:16.937522
4274 23:59:16.940482 RX Delay -230 -> 252, step: 16
4275 23:59:16.943725 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4276 23:59:16.950338 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4277 23:59:16.953713 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4278 23:59:16.956864 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4279 23:59:16.959942 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4280 23:59:16.966364 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4281 23:59:16.970226 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4282 23:59:16.973602 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4283 23:59:16.976568 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4284 23:59:16.979611 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4285 23:59:16.986522 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4286 23:59:16.989742 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4287 23:59:16.993688 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4288 23:59:16.996661 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4289 23:59:17.002952 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4290 23:59:17.006690 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4291 23:59:17.006780 ==
4292 23:59:17.009850 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 23:59:17.013370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 23:59:17.013456 ==
4295 23:59:17.016736 DQS Delay:
4296 23:59:17.016853 DQS0 = 0, DQS1 = 0
4297 23:59:17.016938 DQM Delay:
4298 23:59:17.019851 DQM0 = 51, DQM1 = 43
4299 23:59:17.019930 DQ Delay:
4300 23:59:17.023402 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4301 23:59:17.027040 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4302 23:59:17.029959 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4303 23:59:17.033196 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4304 23:59:17.033293
4305 23:59:17.033377
4306 23:59:17.033456 ==
4307 23:59:17.036813 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 23:59:17.043081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 23:59:17.043190 ==
4310 23:59:17.043278
4311 23:59:17.043364
4312 23:59:17.043442 TX Vref Scan disable
4313 23:59:17.046995 == TX Byte 0 ==
4314 23:59:17.050206 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4315 23:59:17.053817 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4316 23:59:17.056911 == TX Byte 1 ==
4317 23:59:17.060273 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4318 23:59:17.066578 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4319 23:59:17.066698 ==
4320 23:59:17.070150 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 23:59:17.073482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 23:59:17.073584 ==
4323 23:59:17.073701
4324 23:59:17.073804
4325 23:59:17.076623 TX Vref Scan disable
4326 23:59:17.076746 == TX Byte 0 ==
4327 23:59:17.083606 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4328 23:59:17.086807 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4329 23:59:17.089937 == TX Byte 1 ==
4330 23:59:17.092978 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4331 23:59:17.096317 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4332 23:59:17.096454
4333 23:59:17.096554 [DATLAT]
4334 23:59:17.099635 Freq=600, CH0 RK1
4335 23:59:17.099722
4336 23:59:17.099789 DATLAT Default: 0x9
4337 23:59:17.103340 0, 0xFFFF, sum = 0
4338 23:59:17.103454 1, 0xFFFF, sum = 0
4339 23:59:17.106970 2, 0xFFFF, sum = 0
4340 23:59:17.109692 3, 0xFFFF, sum = 0
4341 23:59:17.109815 4, 0xFFFF, sum = 0
4342 23:59:17.112834 5, 0xFFFF, sum = 0
4343 23:59:17.112969 6, 0xFFFF, sum = 0
4344 23:59:17.116477 7, 0xFFFF, sum = 0
4345 23:59:17.116594 8, 0x0, sum = 1
4346 23:59:17.116701 9, 0x0, sum = 2
4347 23:59:17.119600 10, 0x0, sum = 3
4348 23:59:17.119719 11, 0x0, sum = 4
4349 23:59:17.122822 best_step = 9
4350 23:59:17.122938
4351 23:59:17.123036 ==
4352 23:59:17.126726 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 23:59:17.129806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 23:59:17.129927 ==
4355 23:59:17.132868 RX Vref Scan: 0
4356 23:59:17.132955
4357 23:59:17.133022 RX Vref 0 -> 0, step: 1
4358 23:59:17.133090
4359 23:59:17.136056 RX Delay -163 -> 252, step: 8
4360 23:59:17.143899 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4361 23:59:17.146849 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4362 23:59:17.150103 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4363 23:59:17.153392 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4364 23:59:17.157340 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4365 23:59:17.163910 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4366 23:59:17.167197 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4367 23:59:17.170420 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4368 23:59:17.173581 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4369 23:59:17.176704 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4370 23:59:17.183782 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4371 23:59:17.186909 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4372 23:59:17.190206 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4373 23:59:17.193836 iDelay=205, Bit 13, Center 56 (-83 ~ 196) 280
4374 23:59:17.200126 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4375 23:59:17.203181 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4376 23:59:17.203323 ==
4377 23:59:17.207047 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 23:59:17.210478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 23:59:17.210594 ==
4380 23:59:17.213519 DQS Delay:
4381 23:59:17.213626 DQS0 = 0, DQS1 = 0
4382 23:59:17.213720 DQM Delay:
4383 23:59:17.216629 DQM0 = 53, DQM1 = 46
4384 23:59:17.216712 DQ Delay:
4385 23:59:17.219940 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4386 23:59:17.223092 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4387 23:59:17.226868 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4388 23:59:17.230139 DQ12 =48, DQ13 =56, DQ14 =56, DQ15 =52
4389 23:59:17.230220
4390 23:59:17.230284
4391 23:59:17.239870 [DQSOSCAuto] RK1, (LSB)MR18= 0x6022, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4392 23:59:17.243010 CH0 RK1: MR19=808, MR18=6022
4393 23:59:17.246151 CH0_RK1: MR19=0x808, MR18=0x6022, DQSOSC=391, MR23=63, INC=171, DEC=114
4394 23:59:17.249952 [RxdqsGatingPostProcess] freq 600
4395 23:59:17.256539 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4396 23:59:17.259732 Pre-setting of DQS Precalculation
4397 23:59:17.263117 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4398 23:59:17.263206 ==
4399 23:59:17.266348 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 23:59:17.272805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 23:59:17.272895 ==
4402 23:59:17.276642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 23:59:17.282980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4404 23:59:17.286433 [CA 0] Center 35 (5~66) winsize 62
4405 23:59:17.289457 [CA 1] Center 35 (5~66) winsize 62
4406 23:59:17.293163 [CA 2] Center 34 (4~65) winsize 62
4407 23:59:17.296521 [CA 3] Center 34 (4~65) winsize 62
4408 23:59:17.299707 [CA 4] Center 34 (4~65) winsize 62
4409 23:59:17.302695 [CA 5] Center 33 (3~64) winsize 62
4410 23:59:17.302776
4411 23:59:17.305946 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4412 23:59:17.306032
4413 23:59:17.309663 [CATrainingPosCal] consider 1 rank data
4414 23:59:17.312704 u2DelayCellTimex100 = 270/100 ps
4415 23:59:17.316190 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 23:59:17.319785 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 23:59:17.326288 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 23:59:17.329373 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 23:59:17.332314 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 23:59:17.335840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 23:59:17.335938
4422 23:59:17.339001 CA PerBit enable=1, Macro0, CA PI delay=33
4423 23:59:17.339131
4424 23:59:17.342454 [CBTSetCACLKResult] CA Dly = 33
4425 23:59:17.342541 CS Dly: 6 (0~37)
4426 23:59:17.345916 ==
4427 23:59:17.346003 Dram Type= 6, Freq= 0, CH_1, rank 1
4428 23:59:17.352681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 23:59:17.352782 ==
4430 23:59:17.355788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4431 23:59:17.362469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4432 23:59:17.366243 [CA 0] Center 36 (5~67) winsize 63
4433 23:59:17.369612 [CA 1] Center 36 (5~67) winsize 63
4434 23:59:17.372755 [CA 2] Center 35 (5~65) winsize 61
4435 23:59:17.376089 [CA 3] Center 34 (4~65) winsize 62
4436 23:59:17.379461 [CA 4] Center 34 (4~65) winsize 62
4437 23:59:17.382653 [CA 5] Center 34 (4~65) winsize 62
4438 23:59:17.382753
4439 23:59:17.385893 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4440 23:59:17.385985
4441 23:59:17.389651 [CATrainingPosCal] consider 2 rank data
4442 23:59:17.392905 u2DelayCellTimex100 = 270/100 ps
4443 23:59:17.396004 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4444 23:59:17.399118 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4445 23:59:17.406332 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4446 23:59:17.409489 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4447 23:59:17.412778 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4448 23:59:17.416262 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4449 23:59:17.416410
4450 23:59:17.419167 CA PerBit enable=1, Macro0, CA PI delay=34
4451 23:59:17.419272
4452 23:59:17.422464 [CBTSetCACLKResult] CA Dly = 34
4453 23:59:17.422549 CS Dly: 6 (0~38)
4454 23:59:17.422615
4455 23:59:17.425595 ----->DramcWriteLeveling(PI) begin...
4456 23:59:17.429383 ==
4457 23:59:17.432606 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 23:59:17.435822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 23:59:17.435914 ==
4460 23:59:17.438932 Write leveling (Byte 0): 29 => 29
4461 23:59:17.442680 Write leveling (Byte 1): 29 => 29
4462 23:59:17.445621 DramcWriteLeveling(PI) end<-----
4463 23:59:17.445706
4464 23:59:17.445772 ==
4465 23:59:17.448950 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 23:59:17.452733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 23:59:17.452835 ==
4468 23:59:17.456140 [Gating] SW mode calibration
4469 23:59:17.462518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4470 23:59:17.469387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4471 23:59:17.472228 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 23:59:17.475524 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 23:59:17.478903 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 23:59:17.485548 0 9 12 | B1->B0 | 3131 2b2b | 1 0 | (1 1) (1 0)
4475 23:59:17.488638 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 23:59:17.492402 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 23:59:17.498722 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 23:59:17.502598 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 23:59:17.505917 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 23:59:17.512256 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 23:59:17.515927 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4482 23:59:17.518805 0 10 12 | B1->B0 | 3232 3737 | 0 0 | (0 0) (0 0)
4483 23:59:17.525286 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:59:17.529323 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:59:17.532422 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:59:17.538752 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:59:17.542031 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 23:59:17.545208 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 23:59:17.551899 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 23:59:17.555784 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4491 23:59:17.558489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:59:17.565441 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:59:17.568495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:59:17.572138 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:59:17.578884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:59:17.581878 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:59:17.585386 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:59:17.591971 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:59:17.595316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:59:17.598722 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:59:17.605820 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:59:17.608432 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:59:17.611584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:59:17.615636 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:59:17.621883 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4506 23:59:17.625462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4507 23:59:17.628553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 23:59:17.632225 Total UI for P1: 0, mck2ui 16
4509 23:59:17.635158 best dqsien dly found for B0: ( 0, 13, 10)
4510 23:59:17.638351 Total UI for P1: 0, mck2ui 16
4511 23:59:17.641644 best dqsien dly found for B1: ( 0, 13, 12)
4512 23:59:17.645632 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4513 23:59:17.648306 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4514 23:59:17.652114
4515 23:59:17.655537 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4516 23:59:17.658665 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4517 23:59:17.661785 [Gating] SW calibration Done
4518 23:59:17.661869 ==
4519 23:59:17.665035 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 23:59:17.668297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 23:59:17.668426 ==
4522 23:59:17.668525 RX Vref Scan: 0
4523 23:59:17.671442
4524 23:59:17.671529 RX Vref 0 -> 0, step: 1
4525 23:59:17.671597
4526 23:59:17.674931 RX Delay -230 -> 252, step: 16
4527 23:59:17.678435 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4528 23:59:17.685014 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4529 23:59:17.688486 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4530 23:59:17.691558 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4531 23:59:17.695124 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4532 23:59:17.698365 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4533 23:59:17.704721 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4534 23:59:17.707855 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4535 23:59:17.711487 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4536 23:59:17.714264 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4537 23:59:17.721386 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4538 23:59:17.724610 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4539 23:59:17.727893 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4540 23:59:17.731234 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4541 23:59:17.737883 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4542 23:59:17.741653 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4543 23:59:17.741763 ==
4544 23:59:17.744743 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 23:59:17.747778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 23:59:17.747892 ==
4547 23:59:17.750932 DQS Delay:
4548 23:59:17.751014 DQS0 = 0, DQS1 = 0
4549 23:59:17.751099 DQM Delay:
4550 23:59:17.754194 DQM0 = 46, DQM1 = 46
4551 23:59:17.754272 DQ Delay:
4552 23:59:17.757492 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4553 23:59:17.760808 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4554 23:59:17.764734 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4555 23:59:17.767921 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4556 23:59:17.768016
4557 23:59:17.768107
4558 23:59:17.768193 ==
4559 23:59:17.771370 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 23:59:17.777785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 23:59:17.777887 ==
4562 23:59:17.777981
4563 23:59:17.778067
4564 23:59:17.778151 TX Vref Scan disable
4565 23:59:17.781722 == TX Byte 0 ==
4566 23:59:17.784679 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 23:59:17.791296 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 23:59:17.791416 == TX Byte 1 ==
4569 23:59:17.794351 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4570 23:59:17.801337 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4571 23:59:17.801465 ==
4572 23:59:17.804422 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 23:59:17.807891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 23:59:17.808008 ==
4575 23:59:17.808108
4576 23:59:17.808210
4577 23:59:17.811221 TX Vref Scan disable
4578 23:59:17.814838 == TX Byte 0 ==
4579 23:59:17.817676 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4580 23:59:17.821322 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4581 23:59:17.824600 == TX Byte 1 ==
4582 23:59:17.827549 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 23:59:17.831352 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 23:59:17.831446
4585 23:59:17.831536 [DATLAT]
4586 23:59:17.834701 Freq=600, CH1 RK0
4587 23:59:17.834818
4588 23:59:17.834926 DATLAT Default: 0x9
4589 23:59:17.837881 0, 0xFFFF, sum = 0
4590 23:59:17.837991 1, 0xFFFF, sum = 0
4591 23:59:17.841071 2, 0xFFFF, sum = 0
4592 23:59:17.844257 3, 0xFFFF, sum = 0
4593 23:59:17.844388 4, 0xFFFF, sum = 0
4594 23:59:17.847735 5, 0xFFFF, sum = 0
4595 23:59:17.847856 6, 0xFFFF, sum = 0
4596 23:59:17.851240 7, 0xFFFF, sum = 0
4597 23:59:17.851362 8, 0x0, sum = 1
4598 23:59:17.851456 9, 0x0, sum = 2
4599 23:59:17.854266 10, 0x0, sum = 3
4600 23:59:17.854351 11, 0x0, sum = 4
4601 23:59:17.857374 best_step = 9
4602 23:59:17.857466
4603 23:59:17.857557 ==
4604 23:59:17.860971 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 23:59:17.864010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 23:59:17.864110 ==
4607 23:59:17.867351 RX Vref Scan: 1
4608 23:59:17.867452
4609 23:59:17.867544 RX Vref 0 -> 0, step: 1
4610 23:59:17.867629
4611 23:59:17.871204 RX Delay -163 -> 252, step: 8
4612 23:59:17.871313
4613 23:59:17.874499 Set Vref, RX VrefLevel [Byte0]: 55
4614 23:59:17.877663 [Byte1]: 48
4615 23:59:17.881608
4616 23:59:17.881711 Final RX Vref Byte 0 = 55 to rank0
4617 23:59:17.884803 Final RX Vref Byte 1 = 48 to rank0
4618 23:59:17.888603 Final RX Vref Byte 0 = 55 to rank1
4619 23:59:17.891747 Final RX Vref Byte 1 = 48 to rank1==
4620 23:59:17.895000 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 23:59:17.901920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 23:59:17.902044 ==
4623 23:59:17.902146 DQS Delay:
4624 23:59:17.902244 DQS0 = 0, DQS1 = 0
4625 23:59:17.905054 DQM Delay:
4626 23:59:17.905169 DQM0 = 48, DQM1 = 44
4627 23:59:17.908324 DQ Delay:
4628 23:59:17.911581 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4629 23:59:17.911714 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4630 23:59:17.914749 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4631 23:59:17.921635 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4632 23:59:17.921737
4633 23:59:17.921828
4634 23:59:17.928354 [DQSOSCAuto] RK0, (LSB)MR18= 0x456b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4635 23:59:17.931516 CH1 RK0: MR19=808, MR18=456B
4636 23:59:17.938408 CH1_RK0: MR19=0x808, MR18=0x456B, DQSOSC=389, MR23=63, INC=173, DEC=115
4637 23:59:17.938511
4638 23:59:17.941636 ----->DramcWriteLeveling(PI) begin...
4639 23:59:17.941780 ==
4640 23:59:17.944962 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 23:59:17.947986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 23:59:17.948104 ==
4643 23:59:17.951271 Write leveling (Byte 0): 30 => 30
4644 23:59:17.955062 Write leveling (Byte 1): 28 => 28
4645 23:59:17.957977 DramcWriteLeveling(PI) end<-----
4646 23:59:17.958073
4647 23:59:17.958145 ==
4648 23:59:17.961516 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 23:59:17.964994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 23:59:17.965091 ==
4651 23:59:17.968397 [Gating] SW mode calibration
4652 23:59:17.974635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4653 23:59:17.981661 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4654 23:59:17.985004 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 23:59:17.988235 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 23:59:17.994791 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 23:59:17.997858 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 1) (0 0)
4658 23:59:18.001109 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 23:59:18.007964 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 23:59:18.011209 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 23:59:18.014578 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 23:59:18.021099 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 23:59:18.024263 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 23:59:18.027880 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 23:59:18.034428 0 10 12 | B1->B0 | 4343 3636 | 0 0 | (0 0) (0 0)
4666 23:59:18.037557 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4667 23:59:18.041258 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 23:59:18.047783 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:59:18.051059 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:59:18.054514 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 23:59:18.061272 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 23:59:18.064374 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 23:59:18.067551 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:59:18.074017 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:59:18.077138 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:59:18.080944 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:59:18.087124 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:59:18.090367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:59:18.093664 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:59:18.100152 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:59:18.103920 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:59:18.107071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:59:18.113661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:59:18.117296 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:59:18.120546 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:59:18.127038 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:59:18.130375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:59:18.134160 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4689 23:59:18.140596 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 23:59:18.140715 Total UI for P1: 0, mck2ui 16
4691 23:59:18.143510 best dqsien dly found for B0: ( 0, 13, 10)
4692 23:59:18.147336 Total UI for P1: 0, mck2ui 16
4693 23:59:18.150661 best dqsien dly found for B1: ( 0, 13, 8)
4694 23:59:18.157162 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4695 23:59:18.160486 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4696 23:59:18.160572
4697 23:59:18.163918 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4698 23:59:18.166944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4699 23:59:18.171018 [Gating] SW calibration Done
4700 23:59:18.171140 ==
4701 23:59:18.173907 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 23:59:18.177276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 23:59:18.177369 ==
4704 23:59:18.177459 RX Vref Scan: 0
4705 23:59:18.180547
4706 23:59:18.180636 RX Vref 0 -> 0, step: 1
4707 23:59:18.180726
4708 23:59:18.183853 RX Delay -230 -> 252, step: 16
4709 23:59:18.187099 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4710 23:59:18.193810 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4711 23:59:18.197017 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4712 23:59:18.200306 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4713 23:59:18.203525 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4714 23:59:18.207349 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4715 23:59:18.213689 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4716 23:59:18.216930 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4717 23:59:18.220651 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4718 23:59:18.223815 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4719 23:59:18.227090 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4720 23:59:18.233559 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4721 23:59:18.236903 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4722 23:59:18.240108 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4723 23:59:18.243249 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4724 23:59:18.250228 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4725 23:59:18.250344 ==
4726 23:59:18.253728 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 23:59:18.257003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 23:59:18.257091 ==
4729 23:59:18.257164 DQS Delay:
4730 23:59:18.260279 DQS0 = 0, DQS1 = 0
4731 23:59:18.260384 DQM Delay:
4732 23:59:18.263490 DQM0 = 53, DQM1 = 52
4733 23:59:18.263604 DQ Delay:
4734 23:59:18.266692 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4735 23:59:18.270026 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4736 23:59:18.273727 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4737 23:59:18.276716 DQ12 =57, DQ13 =65, DQ14 =57, DQ15 =65
4738 23:59:18.276801
4739 23:59:18.276866
4740 23:59:18.276934 ==
4741 23:59:18.280289 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 23:59:18.283546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 23:59:18.283623 ==
4744 23:59:18.283694
4745 23:59:18.287023
4746 23:59:18.287156 TX Vref Scan disable
4747 23:59:18.290440 == TX Byte 0 ==
4748 23:59:18.293485 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4749 23:59:18.296681 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4750 23:59:18.300298 == TX Byte 1 ==
4751 23:59:18.303384 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4752 23:59:18.306569 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4753 23:59:18.306703 ==
4754 23:59:18.309834 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 23:59:18.316322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 23:59:18.316464 ==
4757 23:59:18.316585
4758 23:59:18.316700
4759 23:59:18.316816 TX Vref Scan disable
4760 23:59:18.321458 == TX Byte 0 ==
4761 23:59:18.324734 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4762 23:59:18.331028 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4763 23:59:18.331116 == TX Byte 1 ==
4764 23:59:18.334353 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4765 23:59:18.340828 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4766 23:59:18.340914
4767 23:59:18.340987 [DATLAT]
4768 23:59:18.341050 Freq=600, CH1 RK1
4769 23:59:18.341111
4770 23:59:18.344050 DATLAT Default: 0x9
4771 23:59:18.344123 0, 0xFFFF, sum = 0
4772 23:59:18.347399 1, 0xFFFF, sum = 0
4773 23:59:18.351157 2, 0xFFFF, sum = 0
4774 23:59:18.351238 3, 0xFFFF, sum = 0
4775 23:59:18.354335 4, 0xFFFF, sum = 0
4776 23:59:18.354427 5, 0xFFFF, sum = 0
4777 23:59:18.357519 6, 0xFFFF, sum = 0
4778 23:59:18.357605 7, 0xFFFF, sum = 0
4779 23:59:18.361354 8, 0x0, sum = 1
4780 23:59:18.361433 9, 0x0, sum = 2
4781 23:59:18.361499 10, 0x0, sum = 3
4782 23:59:18.364233 11, 0x0, sum = 4
4783 23:59:18.364348 best_step = 9
4784 23:59:18.364427
4785 23:59:18.364491 ==
4786 23:59:18.367331 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 23:59:18.374538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 23:59:18.374623 ==
4789 23:59:18.374689 RX Vref Scan: 0
4790 23:59:18.374756
4791 23:59:18.377807 RX Vref 0 -> 0, step: 1
4792 23:59:18.377887
4793 23:59:18.381118 RX Delay -163 -> 252, step: 8
4794 23:59:18.384279 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4795 23:59:18.391157 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4796 23:59:18.394420 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4797 23:59:18.397854 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4798 23:59:18.401215 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4799 23:59:18.404464 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4800 23:59:18.411276 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4801 23:59:18.414190 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4802 23:59:18.417634 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4803 23:59:18.420612 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4804 23:59:18.424275 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4805 23:59:18.430805 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4806 23:59:18.433962 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4807 23:59:18.437904 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4808 23:59:18.440925 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4809 23:59:18.447440 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4810 23:59:18.447528 ==
4811 23:59:18.450663 Dram Type= 6, Freq= 0, CH_1, rank 1
4812 23:59:18.453967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4813 23:59:18.454082 ==
4814 23:59:18.454149 DQS Delay:
4815 23:59:18.457244 DQS0 = 0, DQS1 = 0
4816 23:59:18.457326 DQM Delay:
4817 23:59:18.461139 DQM0 = 48, DQM1 = 44
4818 23:59:18.461217 DQ Delay:
4819 23:59:18.464295 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4820 23:59:18.467362 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4821 23:59:18.470933 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4822 23:59:18.474178 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4823 23:59:18.474265
4824 23:59:18.474328
4825 23:59:18.480650 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4826 23:59:18.484116 CH1 RK1: MR19=808, MR18=6921
4827 23:59:18.490783 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4828 23:59:18.494033 [RxdqsGatingPostProcess] freq 600
4829 23:59:18.500818 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4830 23:59:18.504007 Pre-setting of DQS Precalculation
4831 23:59:18.507084 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4832 23:59:18.514035 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4833 23:59:18.520685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4834 23:59:18.520807
4835 23:59:18.520916
4836 23:59:18.524124 [Calibration Summary] 1200 Mbps
4837 23:59:18.526945 CH 0, Rank 0
4838 23:59:18.527025 SW Impedance : PASS
4839 23:59:18.530453 DUTY Scan : NO K
4840 23:59:18.533940 ZQ Calibration : PASS
4841 23:59:18.534025 Jitter Meter : NO K
4842 23:59:18.537423 CBT Training : PASS
4843 23:59:18.537508 Write leveling : PASS
4844 23:59:18.540776 RX DQS gating : PASS
4845 23:59:18.543486 RX DQ/DQS(RDDQC) : PASS
4846 23:59:18.543582 TX DQ/DQS : PASS
4847 23:59:18.546808 RX DATLAT : PASS
4848 23:59:18.550590 RX DQ/DQS(Engine): PASS
4849 23:59:18.550682 TX OE : NO K
4850 23:59:18.553748 All Pass.
4851 23:59:18.553842
4852 23:59:18.553931 CH 0, Rank 1
4853 23:59:18.556903 SW Impedance : PASS
4854 23:59:18.557001 DUTY Scan : NO K
4855 23:59:18.560211 ZQ Calibration : PASS
4856 23:59:18.563746 Jitter Meter : NO K
4857 23:59:18.563887 CBT Training : PASS
4858 23:59:18.567065 Write leveling : PASS
4859 23:59:18.570411 RX DQS gating : PASS
4860 23:59:18.570539 RX DQ/DQS(RDDQC) : PASS
4861 23:59:18.573545 TX DQ/DQS : PASS
4862 23:59:18.577502 RX DATLAT : PASS
4863 23:59:18.577639 RX DQ/DQS(Engine): PASS
4864 23:59:18.580217 TX OE : NO K
4865 23:59:18.580376 All Pass.
4866 23:59:18.580493
4867 23:59:18.583648 CH 1, Rank 0
4868 23:59:18.583765 SW Impedance : PASS
4869 23:59:18.586821 DUTY Scan : NO K
4870 23:59:18.586956 ZQ Calibration : PASS
4871 23:59:18.590102 Jitter Meter : NO K
4872 23:59:18.593509 CBT Training : PASS
4873 23:59:18.593649 Write leveling : PASS
4874 23:59:18.596786 RX DQS gating : PASS
4875 23:59:18.600099 RX DQ/DQS(RDDQC) : PASS
4876 23:59:18.600230 TX DQ/DQS : PASS
4877 23:59:18.603388 RX DATLAT : PASS
4878 23:59:18.606729 RX DQ/DQS(Engine): PASS
4879 23:59:18.606839 TX OE : NO K
4880 23:59:18.609965 All Pass.
4881 23:59:18.610051
4882 23:59:18.610125 CH 1, Rank 1
4883 23:59:18.613748 SW Impedance : PASS
4884 23:59:18.613859 DUTY Scan : NO K
4885 23:59:18.617134 ZQ Calibration : PASS
4886 23:59:18.620260 Jitter Meter : NO K
4887 23:59:18.620353 CBT Training : PASS
4888 23:59:18.623493 Write leveling : PASS
4889 23:59:18.626682 RX DQS gating : PASS
4890 23:59:18.626776 RX DQ/DQS(RDDQC) : PASS
4891 23:59:18.630284 TX DQ/DQS : PASS
4892 23:59:18.633418 RX DATLAT : PASS
4893 23:59:18.633504 RX DQ/DQS(Engine): PASS
4894 23:59:18.636745 TX OE : NO K
4895 23:59:18.636869 All Pass.
4896 23:59:18.636968
4897 23:59:18.639992 DramC Write-DBI off
4898 23:59:18.643524 PER_BANK_REFRESH: Hybrid Mode
4899 23:59:18.643644 TX_TRACKING: ON
4900 23:59:18.653563 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4901 23:59:18.657072 [FAST_K] Save calibration result to emmc
4902 23:59:18.660097 dramc_set_vcore_voltage set vcore to 662500
4903 23:59:18.660206 Read voltage for 933, 3
4904 23:59:18.663501 Vio18 = 0
4905 23:59:18.663578 Vcore = 662500
4906 23:59:18.663643 Vdram = 0
4907 23:59:18.666922 Vddq = 0
4908 23:59:18.667047 Vmddr = 0
4909 23:59:18.670113 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4910 23:59:18.676803 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4911 23:59:18.680109 MEM_TYPE=3, freq_sel=17
4912 23:59:18.683548 sv_algorithm_assistance_LP4_1600
4913 23:59:18.687102 ============ PULL DRAM RESETB DOWN ============
4914 23:59:18.690128 ========== PULL DRAM RESETB DOWN end =========
4915 23:59:18.697011 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4916 23:59:18.700100 ===================================
4917 23:59:18.700240 LPDDR4 DRAM CONFIGURATION
4918 23:59:18.703481 ===================================
4919 23:59:18.706694 EX_ROW_EN[0] = 0x0
4920 23:59:18.706824 EX_ROW_EN[1] = 0x0
4921 23:59:18.709904 LP4Y_EN = 0x0
4922 23:59:18.710031 WORK_FSP = 0x0
4923 23:59:18.713796 WL = 0x3
4924 23:59:18.713926 RL = 0x3
4925 23:59:18.716849 BL = 0x2
4926 23:59:18.716977 RPST = 0x0
4927 23:59:18.720075 RD_PRE = 0x0
4928 23:59:18.723659 WR_PRE = 0x1
4929 23:59:18.723789 WR_PST = 0x0
4930 23:59:18.726935 DBI_WR = 0x0
4931 23:59:18.727058 DBI_RD = 0x0
4932 23:59:18.729888 OTF = 0x1
4933 23:59:18.733279 ===================================
4934 23:59:18.736759 ===================================
4935 23:59:18.736885 ANA top config
4936 23:59:18.739912 ===================================
4937 23:59:18.743761 DLL_ASYNC_EN = 0
4938 23:59:18.746678 ALL_SLAVE_EN = 1
4939 23:59:18.746791 NEW_RANK_MODE = 1
4940 23:59:18.749663 DLL_IDLE_MODE = 1
4941 23:59:18.753499 LP45_APHY_COMB_EN = 1
4942 23:59:18.756769 TX_ODT_DIS = 1
4943 23:59:18.756891 NEW_8X_MODE = 1
4944 23:59:18.760050 ===================================
4945 23:59:18.763257 ===================================
4946 23:59:18.766482 data_rate = 1866
4947 23:59:18.769641 CKR = 1
4948 23:59:18.773106 DQ_P2S_RATIO = 8
4949 23:59:18.776378 ===================================
4950 23:59:18.780141 CA_P2S_RATIO = 8
4951 23:59:18.783595 DQ_CA_OPEN = 0
4952 23:59:18.783706 DQ_SEMI_OPEN = 0
4953 23:59:18.786453 CA_SEMI_OPEN = 0
4954 23:59:18.790146 CA_FULL_RATE = 0
4955 23:59:18.792876 DQ_CKDIV4_EN = 1
4956 23:59:18.796306 CA_CKDIV4_EN = 1
4957 23:59:18.799874 CA_PREDIV_EN = 0
4958 23:59:18.799960 PH8_DLY = 0
4959 23:59:18.802943 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4960 23:59:18.806052 DQ_AAMCK_DIV = 4
4961 23:59:18.809826 CA_AAMCK_DIV = 4
4962 23:59:18.812878 CA_ADMCK_DIV = 4
4963 23:59:18.816336 DQ_TRACK_CA_EN = 0
4964 23:59:18.819416 CA_PICK = 933
4965 23:59:18.819548 CA_MCKIO = 933
4966 23:59:18.822676 MCKIO_SEMI = 0
4967 23:59:18.826263 PLL_FREQ = 3732
4968 23:59:18.829253 DQ_UI_PI_RATIO = 32
4969 23:59:18.833137 CA_UI_PI_RATIO = 0
4970 23:59:18.836484 ===================================
4971 23:59:18.839684 ===================================
4972 23:59:18.842933 memory_type:LPDDR4
4973 23:59:18.843020 GP_NUM : 10
4974 23:59:18.846263 SRAM_EN : 1
4975 23:59:18.846355 MD32_EN : 0
4976 23:59:18.849140 ===================================
4977 23:59:18.853010 [ANA_INIT] >>>>>>>>>>>>>>
4978 23:59:18.855767 <<<<<< [CONFIGURE PHASE]: ANA_TX
4979 23:59:18.858986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4980 23:59:18.862748 ===================================
4981 23:59:18.866249 data_rate = 1866,PCW = 0X8f00
4982 23:59:18.869333 ===================================
4983 23:59:18.872608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4984 23:59:18.879038 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 23:59:18.882292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4986 23:59:18.888895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4987 23:59:18.892626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4988 23:59:18.895841 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4989 23:59:18.895935 [ANA_INIT] flow start
4990 23:59:18.899080 [ANA_INIT] PLL >>>>>>>>
4991 23:59:18.902379 [ANA_INIT] PLL <<<<<<<<
4992 23:59:18.902505 [ANA_INIT] MIDPI >>>>>>>>
4993 23:59:18.905635 [ANA_INIT] MIDPI <<<<<<<<
4994 23:59:18.909260 [ANA_INIT] DLL >>>>>>>>
4995 23:59:18.909360 [ANA_INIT] flow end
4996 23:59:18.915846 ============ LP4 DIFF to SE enter ============
4997 23:59:18.919480 ============ LP4 DIFF to SE exit ============
4998 23:59:18.919570 [ANA_INIT] <<<<<<<<<<<<<
4999 23:59:18.922380 [Flow] Enable top DCM control >>>>>
5000 23:59:18.925712 [Flow] Enable top DCM control <<<<<
5001 23:59:18.928998 Enable DLL master slave shuffle
5002 23:59:18.935626 ==============================================================
5003 23:59:18.938884 Gating Mode config
5004 23:59:18.942635 ==============================================================
5005 23:59:18.945701 Config description:
5006 23:59:18.955644 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5007 23:59:18.962030 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5008 23:59:18.965844 SELPH_MODE 0: By rank 1: By Phase
5009 23:59:18.972113 ==============================================================
5010 23:59:18.975471 GAT_TRACK_EN = 1
5011 23:59:18.978694 RX_GATING_MODE = 2
5012 23:59:18.981962 RX_GATING_TRACK_MODE = 2
5013 23:59:18.982090 SELPH_MODE = 1
5014 23:59:18.985311 PICG_EARLY_EN = 1
5015 23:59:18.988640 VALID_LAT_VALUE = 1
5016 23:59:18.995762 ==============================================================
5017 23:59:18.998883 Enter into Gating configuration >>>>
5018 23:59:19.001972 Exit from Gating configuration <<<<
5019 23:59:19.005365 Enter into DVFS_PRE_config >>>>>
5020 23:59:19.015820 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5021 23:59:19.018653 Exit from DVFS_PRE_config <<<<<
5022 23:59:19.021735 Enter into PICG configuration >>>>
5023 23:59:19.025495 Exit from PICG configuration <<<<
5024 23:59:19.028858 [RX_INPUT] configuration >>>>>
5025 23:59:19.032033 [RX_INPUT] configuration <<<<<
5026 23:59:19.035038 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5027 23:59:19.041851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5028 23:59:19.048390 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 23:59:19.055294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 23:59:19.058706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 23:59:19.065213 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 23:59:19.071962 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5033 23:59:19.075107 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5034 23:59:19.078156 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5035 23:59:19.081359 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5036 23:59:19.085325 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5037 23:59:19.091693 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5038 23:59:19.094966 ===================================
5039 23:59:19.098366 LPDDR4 DRAM CONFIGURATION
5040 23:59:19.101684 ===================================
5041 23:59:19.101772 EX_ROW_EN[0] = 0x0
5042 23:59:19.104776 EX_ROW_EN[1] = 0x0
5043 23:59:19.104870 LP4Y_EN = 0x0
5044 23:59:19.107833 WORK_FSP = 0x0
5045 23:59:19.107916 WL = 0x3
5046 23:59:19.111524 RL = 0x3
5047 23:59:19.111608 BL = 0x2
5048 23:59:19.114798 RPST = 0x0
5049 23:59:19.114920 RD_PRE = 0x0
5050 23:59:19.117936 WR_PRE = 0x1
5051 23:59:19.118016 WR_PST = 0x0
5052 23:59:19.121739 DBI_WR = 0x0
5053 23:59:19.121866 DBI_RD = 0x0
5054 23:59:19.124887 OTF = 0x1
5055 23:59:19.127961 ===================================
5056 23:59:19.131248 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5057 23:59:19.134953 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5058 23:59:19.141286 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 23:59:19.144490 ===================================
5060 23:59:19.144575 LPDDR4 DRAM CONFIGURATION
5061 23:59:19.148282 ===================================
5062 23:59:19.151457 EX_ROW_EN[0] = 0x10
5063 23:59:19.154747 EX_ROW_EN[1] = 0x0
5064 23:59:19.154899 LP4Y_EN = 0x0
5065 23:59:19.157939 WORK_FSP = 0x0
5066 23:59:19.158069 WL = 0x3
5067 23:59:19.161047 RL = 0x3
5068 23:59:19.161196 BL = 0x2
5069 23:59:19.164483 RPST = 0x0
5070 23:59:19.164612 RD_PRE = 0x0
5071 23:59:19.167817 WR_PRE = 0x1
5072 23:59:19.167947 WR_PST = 0x0
5073 23:59:19.170979 DBI_WR = 0x0
5074 23:59:19.171109 DBI_RD = 0x0
5075 23:59:19.174108 OTF = 0x1
5076 23:59:19.177452 ===================================
5077 23:59:19.184072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5078 23:59:19.187433 nWR fixed to 30
5079 23:59:19.191004 [ModeRegInit_LP4] CH0 RK0
5080 23:59:19.191095 [ModeRegInit_LP4] CH0 RK1
5081 23:59:19.194204 [ModeRegInit_LP4] CH1 RK0
5082 23:59:19.197554 [ModeRegInit_LP4] CH1 RK1
5083 23:59:19.197641 match AC timing 9
5084 23:59:19.204023 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5085 23:59:19.207350 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5086 23:59:19.210519 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5087 23:59:19.217430 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5088 23:59:19.220646 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5089 23:59:19.220777 ==
5090 23:59:19.223918 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 23:59:19.227588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 23:59:19.227735 ==
5093 23:59:19.233917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 23:59:19.240343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5095 23:59:19.243558 [CA 0] Center 37 (6~68) winsize 63
5096 23:59:19.247317 [CA 1] Center 37 (6~68) winsize 63
5097 23:59:19.250355 [CA 2] Center 34 (4~65) winsize 62
5098 23:59:19.253959 [CA 3] Center 34 (3~65) winsize 63
5099 23:59:19.257126 [CA 4] Center 33 (3~64) winsize 62
5100 23:59:19.260323 [CA 5] Center 32 (2~62) winsize 61
5101 23:59:19.260428
5102 23:59:19.263528 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5103 23:59:19.263610
5104 23:59:19.267347 [CATrainingPosCal] consider 1 rank data
5105 23:59:19.270790 u2DelayCellTimex100 = 270/100 ps
5106 23:59:19.274005 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5107 23:59:19.277266 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5108 23:59:19.280399 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5109 23:59:19.283987 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5110 23:59:19.287103 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5111 23:59:19.290430 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5112 23:59:19.293687
5113 23:59:19.297286 CA PerBit enable=1, Macro0, CA PI delay=32
5114 23:59:19.297410
5115 23:59:19.300114 [CBTSetCACLKResult] CA Dly = 32
5116 23:59:19.300236 CS Dly: 5 (0~36)
5117 23:59:19.300333 ==
5118 23:59:19.303636 Dram Type= 6, Freq= 0, CH_0, rank 1
5119 23:59:19.307382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 23:59:19.307467 ==
5121 23:59:19.313932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5122 23:59:19.320305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5123 23:59:19.323599 [CA 0] Center 37 (6~68) winsize 63
5124 23:59:19.327255 [CA 1] Center 37 (6~68) winsize 63
5125 23:59:19.330317 [CA 2] Center 34 (4~65) winsize 62
5126 23:59:19.334119 [CA 3] Center 34 (3~65) winsize 63
5127 23:59:19.337424 [CA 4] Center 33 (3~63) winsize 61
5128 23:59:19.340486 [CA 5] Center 32 (2~62) winsize 61
5129 23:59:19.340598
5130 23:59:19.343669 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5131 23:59:19.343788
5132 23:59:19.346856 [CATrainingPosCal] consider 2 rank data
5133 23:59:19.350617 u2DelayCellTimex100 = 270/100 ps
5134 23:59:19.353770 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5135 23:59:19.357369 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5136 23:59:19.360447 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5137 23:59:19.363612 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5138 23:59:19.367014 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5139 23:59:19.373730 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5140 23:59:19.373819
5141 23:59:19.376959 CA PerBit enable=1, Macro0, CA PI delay=32
5142 23:59:19.377044
5143 23:59:19.380196 [CBTSetCACLKResult] CA Dly = 32
5144 23:59:19.380305 CS Dly: 5 (0~37)
5145 23:59:19.380394
5146 23:59:19.383372 ----->DramcWriteLeveling(PI) begin...
5147 23:59:19.383449 ==
5148 23:59:19.386569 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 23:59:19.393197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 23:59:19.393290 ==
5151 23:59:19.397082 Write leveling (Byte 0): 32 => 32
5152 23:59:19.397161 Write leveling (Byte 1): 28 => 28
5153 23:59:19.400331 DramcWriteLeveling(PI) end<-----
5154 23:59:19.400444
5155 23:59:19.400551 ==
5156 23:59:19.403526 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 23:59:19.410331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 23:59:19.410416 ==
5159 23:59:19.413243 [Gating] SW mode calibration
5160 23:59:19.420098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5161 23:59:19.423585 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5162 23:59:19.430106 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5163 23:59:19.433700 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 23:59:19.436808 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 23:59:19.443325 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 23:59:19.446492 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 23:59:19.450202 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 23:59:19.456635 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5169 23:59:19.459841 0 14 28 | B1->B0 | 3232 2a2a | 1 0 | (1 1) (0 0)
5170 23:59:19.463597 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5171 23:59:19.466626 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 23:59:19.473574 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 23:59:19.476898 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 23:59:19.480206 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 23:59:19.486784 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 23:59:19.490077 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 23:59:19.493471 0 15 28 | B1->B0 | 2727 3d3d | 0 1 | (0 0) (0 0)
5178 23:59:19.500064 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5179 23:59:19.503236 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:59:19.506468 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 23:59:19.513172 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 23:59:19.516723 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 23:59:19.519915 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 23:59:19.526641 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5185 23:59:19.529608 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5186 23:59:19.533250 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5187 23:59:19.539543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:59:19.543022 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:59:19.546206 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:59:19.553433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:59:19.556631 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:59:19.559797 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:59:19.566510 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:59:19.569649 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:59:19.572752 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:59:19.579797 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:59:19.582997 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:59:19.586252 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:59:19.592735 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:59:19.595895 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:59:19.599135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5202 23:59:19.605668 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5203 23:59:19.609695 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 23:59:19.612477 Total UI for P1: 0, mck2ui 16
5205 23:59:19.615672 best dqsien dly found for B0: ( 1, 2, 30)
5206 23:59:19.619498 Total UI for P1: 0, mck2ui 16
5207 23:59:19.622209 best dqsien dly found for B1: ( 1, 3, 0)
5208 23:59:19.625507 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5209 23:59:19.629357 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5210 23:59:19.629490
5211 23:59:19.632613 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5212 23:59:19.635667 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5213 23:59:19.638971 [Gating] SW calibration Done
5214 23:59:19.639103 ==
5215 23:59:19.642146 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 23:59:19.645308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 23:59:19.645420 ==
5218 23:59:19.648925 RX Vref Scan: 0
5219 23:59:19.649038
5220 23:59:19.651805 RX Vref 0 -> 0, step: 1
5221 23:59:19.651929
5222 23:59:19.652035 RX Delay -80 -> 252, step: 8
5223 23:59:19.659224 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5224 23:59:19.662204 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5225 23:59:19.665192 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5226 23:59:19.668616 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5227 23:59:19.672259 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5228 23:59:19.675607 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5229 23:59:19.682003 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5230 23:59:19.685372 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5231 23:59:19.688531 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5232 23:59:19.692133 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5233 23:59:19.695387 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5234 23:59:19.702067 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5235 23:59:19.705270 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5236 23:59:19.708571 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5237 23:59:19.712000 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5238 23:59:19.715286 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5239 23:59:19.715430 ==
5240 23:59:19.718600 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 23:59:19.725068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 23:59:19.725238 ==
5243 23:59:19.725344 DQS Delay:
5244 23:59:19.728351 DQS0 = 0, DQS1 = 0
5245 23:59:19.728502 DQM Delay:
5246 23:59:19.731613 DQM0 = 104, DQM1 = 94
5247 23:59:19.731734 DQ Delay:
5248 23:59:19.734891 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5249 23:59:19.738172 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5250 23:59:19.741356 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5251 23:59:19.744633 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5252 23:59:19.744763
5253 23:59:19.744867
5254 23:59:19.744971 ==
5255 23:59:19.747896 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 23:59:19.751146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 23:59:19.751264 ==
5258 23:59:19.754992
5259 23:59:19.755126
5260 23:59:19.755238 TX Vref Scan disable
5261 23:59:19.758086 == TX Byte 0 ==
5262 23:59:19.761733 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5263 23:59:19.764641 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5264 23:59:19.768854 == TX Byte 1 ==
5265 23:59:19.771683 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5266 23:59:19.774754 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5267 23:59:19.774876 ==
5268 23:59:19.778533 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 23:59:19.784558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 23:59:19.784738 ==
5271 23:59:19.784865
5272 23:59:19.785015
5273 23:59:19.785119 TX Vref Scan disable
5274 23:59:19.788708 == TX Byte 0 ==
5275 23:59:19.792314 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5276 23:59:19.799040 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5277 23:59:19.799161 == TX Byte 1 ==
5278 23:59:19.802281 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5279 23:59:19.805684 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5280 23:59:19.809347
5281 23:59:19.809446 [DATLAT]
5282 23:59:19.809514 Freq=933, CH0 RK0
5283 23:59:19.809578
5284 23:59:19.812365 DATLAT Default: 0xd
5285 23:59:19.812465 0, 0xFFFF, sum = 0
5286 23:59:19.815704 1, 0xFFFF, sum = 0
5287 23:59:19.815793 2, 0xFFFF, sum = 0
5288 23:59:19.819007 3, 0xFFFF, sum = 0
5289 23:59:19.822201 4, 0xFFFF, sum = 0
5290 23:59:19.822290 5, 0xFFFF, sum = 0
5291 23:59:19.825683 6, 0xFFFF, sum = 0
5292 23:59:19.825802 7, 0xFFFF, sum = 0
5293 23:59:19.828611 8, 0xFFFF, sum = 0
5294 23:59:19.828688 9, 0xFFFF, sum = 0
5295 23:59:19.831955 10, 0x0, sum = 1
5296 23:59:19.832075 11, 0x0, sum = 2
5297 23:59:19.835362 12, 0x0, sum = 3
5298 23:59:19.835470 13, 0x0, sum = 4
5299 23:59:19.835555 best_step = 11
5300 23:59:19.835617
5301 23:59:19.838373 ==
5302 23:59:19.842185 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 23:59:19.845513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 23:59:19.845715 ==
5305 23:59:19.845856 RX Vref Scan: 1
5306 23:59:19.845995
5307 23:59:19.848520 RX Vref 0 -> 0, step: 1
5308 23:59:19.848610
5309 23:59:19.852143 RX Delay -53 -> 252, step: 4
5310 23:59:19.852255
5311 23:59:19.855477 Set Vref, RX VrefLevel [Byte0]: 57
5312 23:59:19.858552 [Byte1]: 48
5313 23:59:19.858647
5314 23:59:19.861802 Final RX Vref Byte 0 = 57 to rank0
5315 23:59:19.864982 Final RX Vref Byte 1 = 48 to rank0
5316 23:59:19.868227 Final RX Vref Byte 0 = 57 to rank1
5317 23:59:19.871454 Final RX Vref Byte 1 = 48 to rank1==
5318 23:59:19.875079 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 23:59:19.878106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 23:59:19.881713 ==
5321 23:59:19.881815 DQS Delay:
5322 23:59:19.881887 DQS0 = 0, DQS1 = 0
5323 23:59:19.885018 DQM Delay:
5324 23:59:19.885107 DQM0 = 105, DQM1 = 95
5325 23:59:19.888164 DQ Delay:
5326 23:59:19.891890 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5327 23:59:19.895043 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5328 23:59:19.898398 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =88
5329 23:59:19.901523 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5330 23:59:19.901617
5331 23:59:19.901687
5332 23:59:19.908227 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5333 23:59:19.911366 CH0 RK0: MR19=505, MR18=3129
5334 23:59:19.918343 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5335 23:59:19.918452
5336 23:59:19.921487 ----->DramcWriteLeveling(PI) begin...
5337 23:59:19.921595 ==
5338 23:59:19.924617 Dram Type= 6, Freq= 0, CH_0, rank 1
5339 23:59:19.928234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 23:59:19.928350 ==
5341 23:59:19.931261 Write leveling (Byte 0): 31 => 31
5342 23:59:19.934579 Write leveling (Byte 1): 29 => 29
5343 23:59:19.937757 DramcWriteLeveling(PI) end<-----
5344 23:59:19.937877
5345 23:59:19.937973 ==
5346 23:59:19.941633 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 23:59:19.944958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 23:59:19.948286 ==
5349 23:59:19.948417 [Gating] SW mode calibration
5350 23:59:19.958174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5351 23:59:19.961449 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5352 23:59:19.964633 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5353 23:59:19.971048 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:59:19.974934 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:59:19.978163 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 23:59:19.984519 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 23:59:19.988198 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 23:59:19.991101 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5359 23:59:19.997760 0 14 28 | B1->B0 | 2f2f 2d2d | 0 1 | (0 1) (1 0)
5360 23:59:20.001290 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5361 23:59:20.004393 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:59:20.010866 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 23:59:20.014527 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 23:59:20.017773 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 23:59:20.024037 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 23:59:20.027637 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5367 23:59:20.031052 0 15 28 | B1->B0 | 3939 3a3a | 0 0 | (0 0) (0 0)
5368 23:59:20.037544 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:59:20.040529 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:59:20.044270 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:59:20.050903 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:59:20.054097 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:59:20.057340 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 23:59:20.060744 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 23:59:20.067326 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5376 23:59:20.070584 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:59:20.073986 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:59:20.081172 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:59:20.083869 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:59:20.087783 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:59:20.094229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:59:20.096950 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:59:20.100548 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:59:20.107482 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:59:20.110536 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:59:20.113904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:59:20.120436 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:59:20.123921 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:59:20.126853 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:59:20.134008 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:59:20.137008 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5392 23:59:20.140664 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5393 23:59:20.144099 Total UI for P1: 0, mck2ui 16
5394 23:59:20.147086 best dqsien dly found for B1: ( 1, 2, 28)
5395 23:59:20.153939 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 23:59:20.154087 Total UI for P1: 0, mck2ui 16
5397 23:59:20.160572 best dqsien dly found for B0: ( 1, 2, 30)
5398 23:59:20.163815 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5399 23:59:20.166994 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5400 23:59:20.167131
5401 23:59:20.170246 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5402 23:59:20.173461 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5403 23:59:20.177086 [Gating] SW calibration Done
5404 23:59:20.177167 ==
5405 23:59:20.180246 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 23:59:20.183997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 23:59:20.184104 ==
5408 23:59:20.187091 RX Vref Scan: 0
5409 23:59:20.187184
5410 23:59:20.187290 RX Vref 0 -> 0, step: 1
5411 23:59:20.187387
5412 23:59:20.190369 RX Delay -80 -> 252, step: 8
5413 23:59:20.193617 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5414 23:59:20.200092 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5415 23:59:20.203290 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5416 23:59:20.206964 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5417 23:59:20.209910 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5418 23:59:20.213593 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5419 23:59:20.216829 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5420 23:59:20.223331 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5421 23:59:20.227060 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5422 23:59:20.229998 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5423 23:59:20.233537 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5424 23:59:20.236412 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5425 23:59:20.239800 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5426 23:59:20.246446 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5427 23:59:20.250325 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5428 23:59:20.253430 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5429 23:59:20.253526 ==
5430 23:59:20.256757 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 23:59:20.259946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 23:59:20.260037 ==
5433 23:59:20.262976 DQS Delay:
5434 23:59:20.263057 DQS0 = 0, DQS1 = 0
5435 23:59:20.266688 DQM Delay:
5436 23:59:20.266779 DQM0 = 104, DQM1 = 93
5437 23:59:20.266865 DQ Delay:
5438 23:59:20.273118 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5439 23:59:20.276378 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5440 23:59:20.280128 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5441 23:59:20.283238 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5442 23:59:20.283322
5443 23:59:20.283408
5444 23:59:20.283494 ==
5445 23:59:20.286417 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 23:59:20.289524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 23:59:20.289643 ==
5448 23:59:20.289740
5449 23:59:20.289840
5450 23:59:20.293434 TX Vref Scan disable
5451 23:59:20.293517 == TX Byte 0 ==
5452 23:59:20.299473 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5453 23:59:20.302734 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5454 23:59:20.302822 == TX Byte 1 ==
5455 23:59:20.309895 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5456 23:59:20.313049 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5457 23:59:20.313131 ==
5458 23:59:20.316261 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 23:59:20.319640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 23:59:20.319731 ==
5461 23:59:20.319835
5462 23:59:20.319944
5463 23:59:20.322825 TX Vref Scan disable
5464 23:59:20.326351 == TX Byte 0 ==
5465 23:59:20.329509 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5466 23:59:20.332928 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5467 23:59:20.336079 == TX Byte 1 ==
5468 23:59:20.339378 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5469 23:59:20.342986 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5470 23:59:20.345994
5471 23:59:20.346108 [DATLAT]
5472 23:59:20.346206 Freq=933, CH0 RK1
5473 23:59:20.346302
5474 23:59:20.349581 DATLAT Default: 0xb
5475 23:59:20.349694 0, 0xFFFF, sum = 0
5476 23:59:20.352971 1, 0xFFFF, sum = 0
5477 23:59:20.353060 2, 0xFFFF, sum = 0
5478 23:59:20.356508 3, 0xFFFF, sum = 0
5479 23:59:20.356596 4, 0xFFFF, sum = 0
5480 23:59:20.359646 5, 0xFFFF, sum = 0
5481 23:59:20.359734 6, 0xFFFF, sum = 0
5482 23:59:20.362588 7, 0xFFFF, sum = 0
5483 23:59:20.366025 8, 0xFFFF, sum = 0
5484 23:59:20.366116 9, 0xFFFF, sum = 0
5485 23:59:20.366186 10, 0x0, sum = 1
5486 23:59:20.369992 11, 0x0, sum = 2
5487 23:59:20.370116 12, 0x0, sum = 3
5488 23:59:20.372750 13, 0x0, sum = 4
5489 23:59:20.372868 best_step = 11
5490 23:59:20.372971
5491 23:59:20.373065 ==
5492 23:59:20.376414 Dram Type= 6, Freq= 0, CH_0, rank 1
5493 23:59:20.382844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 23:59:20.382968 ==
5495 23:59:20.383070 RX Vref Scan: 0
5496 23:59:20.383164
5497 23:59:20.386024 RX Vref 0 -> 0, step: 1
5498 23:59:20.386139
5499 23:59:20.389222 RX Delay -53 -> 252, step: 4
5500 23:59:20.393054 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5501 23:59:20.399316 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5502 23:59:20.402623 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5503 23:59:20.406537 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5504 23:59:20.409762 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5505 23:59:20.413002 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5506 23:59:20.416396 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5507 23:59:20.422814 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5508 23:59:20.425936 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5509 23:59:20.429536 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5510 23:59:20.432961 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5511 23:59:20.436125 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5512 23:59:20.442692 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5513 23:59:20.445950 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5514 23:59:20.449117 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5515 23:59:20.452327 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5516 23:59:20.452421 ==
5517 23:59:20.456285 Dram Type= 6, Freq= 0, CH_0, rank 1
5518 23:59:20.459744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 23:59:20.462554 ==
5520 23:59:20.462674 DQS Delay:
5521 23:59:20.462779 DQS0 = 0, DQS1 = 0
5522 23:59:20.466015 DQM Delay:
5523 23:59:20.466132 DQM0 = 104, DQM1 = 94
5524 23:59:20.469603 DQ Delay:
5525 23:59:20.472813 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5526 23:59:20.476074 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5527 23:59:20.479655 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =86
5528 23:59:20.482735 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5529 23:59:20.482848
5530 23:59:20.482954
5531 23:59:20.489224 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5532 23:59:20.492353 CH0 RK1: MR19=505, MR18=2902
5533 23:59:20.498878 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5534 23:59:20.502511 [RxdqsGatingPostProcess] freq 933
5535 23:59:20.508877 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5536 23:59:20.509026 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 23:59:20.512106 best DQS1 dly(2T, 0.5T) = (0, 11)
5538 23:59:20.515976 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 23:59:20.519335 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5540 23:59:20.522704 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 23:59:20.525833 best DQS1 dly(2T, 0.5T) = (0, 10)
5542 23:59:20.529187 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 23:59:20.532519 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5544 23:59:20.535379 Pre-setting of DQS Precalculation
5545 23:59:20.542067 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5546 23:59:20.542196 ==
5547 23:59:20.545594 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 23:59:20.548749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 23:59:20.548847 ==
5550 23:59:20.555633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5551 23:59:20.558967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5552 23:59:20.562350 [CA 0] Center 36 (6~67) winsize 62
5553 23:59:20.565634 [CA 1] Center 36 (6~67) winsize 62
5554 23:59:20.569467 [CA 2] Center 34 (4~65) winsize 62
5555 23:59:20.572517 [CA 3] Center 34 (4~64) winsize 61
5556 23:59:20.575760 [CA 4] Center 34 (4~64) winsize 61
5557 23:59:20.578936 [CA 5] Center 33 (3~64) winsize 62
5558 23:59:20.579061
5559 23:59:20.582510 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5560 23:59:20.582658
5561 23:59:20.585535 [CATrainingPosCal] consider 1 rank data
5562 23:59:20.589425 u2DelayCellTimex100 = 270/100 ps
5563 23:59:20.592161 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 23:59:20.598999 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 23:59:20.602515 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5566 23:59:20.605996 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 23:59:20.608865 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 23:59:20.612315 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 23:59:20.612469
5570 23:59:20.615612 CA PerBit enable=1, Macro0, CA PI delay=33
5571 23:59:20.615704
5572 23:59:20.619016 [CBTSetCACLKResult] CA Dly = 33
5573 23:59:20.619113 CS Dly: 6 (0~37)
5574 23:59:20.622097 ==
5575 23:59:20.625406 Dram Type= 6, Freq= 0, CH_1, rank 1
5576 23:59:20.628703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 23:59:20.628807 ==
5578 23:59:20.631951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5579 23:59:20.639098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5580 23:59:20.642362 [CA 0] Center 36 (6~67) winsize 62
5581 23:59:20.645555 [CA 1] Center 37 (7~68) winsize 62
5582 23:59:20.649021 [CA 2] Center 35 (5~65) winsize 61
5583 23:59:20.652636 [CA 3] Center 34 (4~65) winsize 62
5584 23:59:20.655622 [CA 4] Center 34 (4~65) winsize 62
5585 23:59:20.659150 [CA 5] Center 33 (3~64) winsize 62
5586 23:59:20.659295
5587 23:59:20.662467 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5588 23:59:20.662609
5589 23:59:20.665677 [CATrainingPosCal] consider 2 rank data
5590 23:59:20.669602 u2DelayCellTimex100 = 270/100 ps
5591 23:59:20.672783 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5592 23:59:20.675995 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5593 23:59:20.682475 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5594 23:59:20.686151 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5595 23:59:20.689439 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5596 23:59:20.692518 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5597 23:59:20.692681
5598 23:59:20.695889 CA PerBit enable=1, Macro0, CA PI delay=33
5599 23:59:20.696052
5600 23:59:20.699021 [CBTSetCACLKResult] CA Dly = 33
5601 23:59:20.699159 CS Dly: 7 (0~40)
5602 23:59:20.699282
5603 23:59:20.702848 ----->DramcWriteLeveling(PI) begin...
5604 23:59:20.702978 ==
5605 23:59:20.706022 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 23:59:20.712690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 23:59:20.712855 ==
5608 23:59:20.716354 Write leveling (Byte 0): 26 => 26
5609 23:59:20.719258 Write leveling (Byte 1): 26 => 26
5610 23:59:20.719388 DramcWriteLeveling(PI) end<-----
5611 23:59:20.722461
5612 23:59:20.722605 ==
5613 23:59:20.726242 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 23:59:20.729273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 23:59:20.729395 ==
5616 23:59:20.732765 [Gating] SW mode calibration
5617 23:59:20.739326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5618 23:59:20.742460 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5619 23:59:20.749316 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 23:59:20.752576 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 23:59:20.756152 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 23:59:20.762461 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 23:59:20.766083 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 23:59:20.769498 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 23:59:20.776079 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 0)
5626 23:59:20.779105 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5627 23:59:20.782439 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 23:59:20.789608 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 23:59:20.792731 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 23:59:20.795934 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 23:59:20.802594 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 23:59:20.806197 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5633 23:59:20.809586 0 15 24 | B1->B0 | 2727 3030 | 0 1 | (0 0) (0 0)
5634 23:59:20.816074 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5635 23:59:20.819135 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:59:20.822515 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 23:59:20.828820 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 23:59:20.832207 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 23:59:20.836012 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 23:59:20.839245 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 23:59:20.845767 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5642 23:59:20.849206 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5643 23:59:20.852155 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:59:20.858960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:59:20.862017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:59:20.865486 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:59:20.872351 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:59:20.875472 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:59:20.879126 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:59:20.885583 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:59:20.888953 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:59:20.892213 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:59:20.899321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:59:20.901984 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:59:20.905832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:59:20.912265 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:59:20.915455 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5658 23:59:20.918672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5659 23:59:20.922481 Total UI for P1: 0, mck2ui 16
5660 23:59:20.925634 best dqsien dly found for B1: ( 1, 2, 24)
5661 23:59:20.932183 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 23:59:20.932346 Total UI for P1: 0, mck2ui 16
5663 23:59:20.938773 best dqsien dly found for B0: ( 1, 2, 26)
5664 23:59:20.941802 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5665 23:59:20.945646 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5666 23:59:20.945795
5667 23:59:20.948862 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5668 23:59:20.952022 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5669 23:59:20.955164 [Gating] SW calibration Done
5670 23:59:20.955315 ==
5671 23:59:20.958648 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 23:59:20.962332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 23:59:20.962486 ==
5674 23:59:20.965380 RX Vref Scan: 0
5675 23:59:20.965531
5676 23:59:20.965654 RX Vref 0 -> 0, step: 1
5677 23:59:20.965764
5678 23:59:20.968246 RX Delay -80 -> 252, step: 8
5679 23:59:20.971934 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5680 23:59:20.978282 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5681 23:59:20.981817 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5682 23:59:20.984953 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5683 23:59:20.988730 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5684 23:59:20.991963 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5685 23:59:20.995041 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5686 23:59:21.001594 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5687 23:59:21.004961 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5688 23:59:21.008248 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5689 23:59:21.011684 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5690 23:59:21.014761 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5691 23:59:21.018113 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5692 23:59:21.025430 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5693 23:59:21.028646 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5694 23:59:21.031907 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5695 23:59:21.032038 ==
5696 23:59:21.035102 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 23:59:21.038278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 23:59:21.038410 ==
5699 23:59:21.041763 DQS Delay:
5700 23:59:21.041889 DQS0 = 0, DQS1 = 0
5701 23:59:21.045350 DQM Delay:
5702 23:59:21.045476 DQM0 = 103, DQM1 = 99
5703 23:59:21.045580 DQ Delay:
5704 23:59:21.048141 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5705 23:59:21.051788 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5706 23:59:21.054986 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5707 23:59:21.061400 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5708 23:59:21.061587
5709 23:59:21.061715
5710 23:59:21.061831 ==
5711 23:59:21.065150 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 23:59:21.068255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 23:59:21.068400 ==
5714 23:59:21.068523
5715 23:59:21.068639
5716 23:59:21.071294 TX Vref Scan disable
5717 23:59:21.071424 == TX Byte 0 ==
5718 23:59:21.078081 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 23:59:21.081667 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 23:59:21.081807 == TX Byte 1 ==
5721 23:59:21.088367 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5722 23:59:21.091365 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5723 23:59:21.091519 ==
5724 23:59:21.094504 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 23:59:21.098361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 23:59:21.098507 ==
5727 23:59:21.098615
5728 23:59:21.098712
5729 23:59:21.101672 TX Vref Scan disable
5730 23:59:21.104855 == TX Byte 0 ==
5731 23:59:21.107935 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 23:59:21.111599 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 23:59:21.114567 == TX Byte 1 ==
5734 23:59:21.118088 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5735 23:59:21.121372 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5736 23:59:21.121512
5737 23:59:21.124614 [DATLAT]
5738 23:59:21.124745 Freq=933, CH1 RK0
5739 23:59:21.124847
5740 23:59:21.128117 DATLAT Default: 0xd
5741 23:59:21.128242 0, 0xFFFF, sum = 0
5742 23:59:21.131837 1, 0xFFFF, sum = 0
5743 23:59:21.131967 2, 0xFFFF, sum = 0
5744 23:59:21.135033 3, 0xFFFF, sum = 0
5745 23:59:21.135159 4, 0xFFFF, sum = 0
5746 23:59:21.138308 5, 0xFFFF, sum = 0
5747 23:59:21.138432 6, 0xFFFF, sum = 0
5748 23:59:21.141660 7, 0xFFFF, sum = 0
5749 23:59:21.141786 8, 0xFFFF, sum = 0
5750 23:59:21.144914 9, 0xFFFF, sum = 0
5751 23:59:21.145038 10, 0x0, sum = 1
5752 23:59:21.148280 11, 0x0, sum = 2
5753 23:59:21.148414 12, 0x0, sum = 3
5754 23:59:21.151631 13, 0x0, sum = 4
5755 23:59:21.151753 best_step = 11
5756 23:59:21.151856
5757 23:59:21.151953 ==
5758 23:59:21.155230 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 23:59:21.161299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 23:59:21.161450 ==
5761 23:59:21.161557 RX Vref Scan: 1
5762 23:59:21.161654
5763 23:59:21.164315 RX Vref 0 -> 0, step: 1
5764 23:59:21.164445
5765 23:59:21.168244 RX Delay -45 -> 252, step: 4
5766 23:59:21.168391
5767 23:59:21.171504 Set Vref, RX VrefLevel [Byte0]: 55
5768 23:59:21.174700 [Byte1]: 48
5769 23:59:21.174826
5770 23:59:21.177864 Final RX Vref Byte 0 = 55 to rank0
5771 23:59:21.180989 Final RX Vref Byte 1 = 48 to rank0
5772 23:59:21.184857 Final RX Vref Byte 0 = 55 to rank1
5773 23:59:21.188013 Final RX Vref Byte 1 = 48 to rank1==
5774 23:59:21.191092 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 23:59:21.194294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 23:59:21.194433 ==
5777 23:59:21.197901 DQS Delay:
5778 23:59:21.197992 DQS0 = 0, DQS1 = 0
5779 23:59:21.198079 DQM Delay:
5780 23:59:21.201062 DQM0 = 104, DQM1 = 100
5781 23:59:21.201149 DQ Delay:
5782 23:59:21.204679 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5783 23:59:21.207487 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =104
5784 23:59:21.211216 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =94
5785 23:59:21.217486 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5786 23:59:21.217609
5787 23:59:21.217685
5788 23:59:21.224272 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5789 23:59:21.227201 CH1 RK0: MR19=505, MR18=1B32
5790 23:59:21.233831 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5791 23:59:21.233993
5792 23:59:21.237136 ----->DramcWriteLeveling(PI) begin...
5793 23:59:21.237231 ==
5794 23:59:21.241019 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 23:59:21.244241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 23:59:21.244332 ==
5797 23:59:21.247557 Write leveling (Byte 0): 27 => 27
5798 23:59:21.250776 Write leveling (Byte 1): 29 => 29
5799 23:59:21.254015 DramcWriteLeveling(PI) end<-----
5800 23:59:21.254118
5801 23:59:21.254184 ==
5802 23:59:21.257231 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 23:59:21.260361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 23:59:21.260450 ==
5805 23:59:21.264056 [Gating] SW mode calibration
5806 23:59:21.270784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5807 23:59:21.277034 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5808 23:59:21.280251 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 23:59:21.287211 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 23:59:21.290110 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 23:59:21.293351 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 23:59:21.299832 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 23:59:21.303150 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 23:59:21.306850 0 14 24 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
5815 23:59:21.313425 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5816 23:59:21.316796 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 23:59:21.320288 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 23:59:21.326490 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 23:59:21.329631 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 23:59:21.332868 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 23:59:21.339521 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5822 23:59:21.343111 0 15 24 | B1->B0 | 3737 2a2a | 0 0 | (0 0) (0 0)
5823 23:59:21.346357 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5824 23:59:21.352846 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 23:59:21.357025 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 23:59:21.359425 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 23:59:21.363290 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 23:59:21.370013 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 23:59:21.372858 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 23:59:21.376680 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5831 23:59:21.383285 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:59:21.386373 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:59:21.389717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:59:21.396544 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:59:21.399603 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:59:21.402805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:59:21.409513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:59:21.412779 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:59:21.416078 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:59:21.422596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:59:21.425840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:59:21.429469 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:59:21.435876 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 23:59:21.439095 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:59:21.442566 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5846 23:59:21.449301 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5847 23:59:21.452967 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5848 23:59:21.456359 Total UI for P1: 0, mck2ui 16
5849 23:59:21.459535 best dqsien dly found for B0: ( 1, 2, 24)
5850 23:59:21.462942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 23:59:21.465988 Total UI for P1: 0, mck2ui 16
5852 23:59:21.469252 best dqsien dly found for B1: ( 1, 2, 28)
5853 23:59:21.472555 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5854 23:59:21.476447 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5855 23:59:21.476589
5856 23:59:21.479672 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5857 23:59:21.486192 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5858 23:59:21.486328 [Gating] SW calibration Done
5859 23:59:21.486428 ==
5860 23:59:21.489265 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 23:59:21.496558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 23:59:21.496725 ==
5863 23:59:21.496839 RX Vref Scan: 0
5864 23:59:21.496951
5865 23:59:21.499867 RX Vref 0 -> 0, step: 1
5866 23:59:21.499959
5867 23:59:21.502923 RX Delay -80 -> 252, step: 8
5868 23:59:21.505985 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5869 23:59:21.509775 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5870 23:59:21.512986 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5871 23:59:21.516091 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5872 23:59:21.522714 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5873 23:59:21.525965 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5874 23:59:21.529235 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5875 23:59:21.532433 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5876 23:59:21.535618 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5877 23:59:21.538927 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5878 23:59:21.545882 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5879 23:59:21.549299 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5880 23:59:21.552616 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5881 23:59:21.556488 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5882 23:59:21.559472 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5883 23:59:21.565879 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5884 23:59:21.566003 ==
5885 23:59:21.569187 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 23:59:21.572565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 23:59:21.572663 ==
5888 23:59:21.572732 DQS Delay:
5889 23:59:21.575836 DQS0 = 0, DQS1 = 0
5890 23:59:21.575942 DQM Delay:
5891 23:59:21.579082 DQM0 = 102, DQM1 = 97
5892 23:59:21.579194 DQ Delay:
5893 23:59:21.582709 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5894 23:59:21.585889 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5895 23:59:21.589108 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5896 23:59:21.592930 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5897 23:59:21.593037
5898 23:59:21.593104
5899 23:59:21.593172 ==
5900 23:59:21.596506 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 23:59:21.599268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 23:59:21.602849 ==
5903 23:59:21.602953
5904 23:59:21.603044
5905 23:59:21.603127 TX Vref Scan disable
5906 23:59:21.605796 == TX Byte 0 ==
5907 23:59:21.609568 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5908 23:59:21.612634 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5909 23:59:21.615744 == TX Byte 1 ==
5910 23:59:21.619068 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5911 23:59:21.622247 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5912 23:59:21.626043 ==
5913 23:59:21.626192 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 23:59:21.632498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 23:59:21.632605 ==
5916 23:59:21.632674
5917 23:59:21.632736
5918 23:59:21.635783 TX Vref Scan disable
5919 23:59:21.635862 == TX Byte 0 ==
5920 23:59:21.642260 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5921 23:59:21.646082 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5922 23:59:21.646260 == TX Byte 1 ==
5923 23:59:21.652550 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5924 23:59:21.655810 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5925 23:59:21.655953
5926 23:59:21.656080 [DATLAT]
5927 23:59:21.658948 Freq=933, CH1 RK1
5928 23:59:21.659070
5929 23:59:21.659167 DATLAT Default: 0xb
5930 23:59:21.662086 0, 0xFFFF, sum = 0
5931 23:59:21.662235 1, 0xFFFF, sum = 0
5932 23:59:21.665381 2, 0xFFFF, sum = 0
5933 23:59:21.665528 3, 0xFFFF, sum = 0
5934 23:59:21.669273 4, 0xFFFF, sum = 0
5935 23:59:21.669381 5, 0xFFFF, sum = 0
5936 23:59:21.672276 6, 0xFFFF, sum = 0
5937 23:59:21.672373 7, 0xFFFF, sum = 0
5938 23:59:21.675454 8, 0xFFFF, sum = 0
5939 23:59:21.678687 9, 0xFFFF, sum = 0
5940 23:59:21.678815 10, 0x0, sum = 1
5941 23:59:21.678916 11, 0x0, sum = 2
5942 23:59:21.681956 12, 0x0, sum = 3
5943 23:59:21.682039 13, 0x0, sum = 4
5944 23:59:21.685613 best_step = 11
5945 23:59:21.685728
5946 23:59:21.685800 ==
5947 23:59:21.688651 Dram Type= 6, Freq= 0, CH_1, rank 1
5948 23:59:21.692048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5949 23:59:21.692143 ==
5950 23:59:21.695435 RX Vref Scan: 0
5951 23:59:21.695531
5952 23:59:21.695607 RX Vref 0 -> 0, step: 1
5953 23:59:21.695672
5954 23:59:21.698870 RX Delay -53 -> 252, step: 4
5955 23:59:21.705933 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5956 23:59:21.709329 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5957 23:59:21.712755 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5958 23:59:21.716290 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5959 23:59:21.719486 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5960 23:59:21.726091 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5961 23:59:21.729158 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5962 23:59:21.732524 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5963 23:59:21.735717 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5964 23:59:21.739566 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5965 23:59:21.742793 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5966 23:59:21.749052 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5967 23:59:21.752803 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5968 23:59:21.755954 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5969 23:59:21.759133 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5970 23:59:21.766171 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5971 23:59:21.766358 ==
5972 23:59:21.769364 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 23:59:21.772586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 23:59:21.772732 ==
5975 23:59:21.772855 DQS Delay:
5976 23:59:21.775747 DQS0 = 0, DQS1 = 0
5977 23:59:21.775897 DQM Delay:
5978 23:59:21.779148 DQM0 = 105, DQM1 = 99
5979 23:59:21.779284 DQ Delay:
5980 23:59:21.782991 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5981 23:59:21.786060 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5982 23:59:21.789257 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =92
5983 23:59:21.792509 DQ12 =110, DQ13 =104, DQ14 =104, DQ15 =108
5984 23:59:21.792646
5985 23:59:21.792768
5986 23:59:21.802405 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5987 23:59:21.802595 CH1 RK1: MR19=505, MR18=2F01
5988 23:59:21.808910 CH1_RK1: MR19=0x505, MR18=0x2F01, DQSOSC=407, MR23=63, INC=65, DEC=43
5989 23:59:21.812571 [RxdqsGatingPostProcess] freq 933
5990 23:59:21.819033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5991 23:59:21.822293 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 23:59:21.825843 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 23:59:21.829238 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 23:59:21.832533 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 23:59:21.832644 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 23:59:21.835729 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 23:59:21.839468 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 23:59:21.842579 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 23:59:21.845753 Pre-setting of DQS Precalculation
6000 23:59:21.852284 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6001 23:59:21.859367 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6002 23:59:21.865620 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6003 23:59:21.865762
6004 23:59:21.865840
6005 23:59:21.869235 [Calibration Summary] 1866 Mbps
6006 23:59:21.869341 CH 0, Rank 0
6007 23:59:21.872527 SW Impedance : PASS
6008 23:59:21.875655 DUTY Scan : NO K
6009 23:59:21.875782 ZQ Calibration : PASS
6010 23:59:21.878876 Jitter Meter : NO K
6011 23:59:21.882512 CBT Training : PASS
6012 23:59:21.882617 Write leveling : PASS
6013 23:59:21.885666 RX DQS gating : PASS
6014 23:59:21.888856 RX DQ/DQS(RDDQC) : PASS
6015 23:59:21.888954 TX DQ/DQS : PASS
6016 23:59:21.892218 RX DATLAT : PASS
6017 23:59:21.895672 RX DQ/DQS(Engine): PASS
6018 23:59:21.895762 TX OE : NO K
6019 23:59:21.898811 All Pass.
6020 23:59:21.898904
6021 23:59:21.898972 CH 0, Rank 1
6022 23:59:21.902075 SW Impedance : PASS
6023 23:59:21.902164 DUTY Scan : NO K
6024 23:59:21.905339 ZQ Calibration : PASS
6025 23:59:21.908511 Jitter Meter : NO K
6026 23:59:21.908602 CBT Training : PASS
6027 23:59:21.912426 Write leveling : PASS
6028 23:59:21.915429 RX DQS gating : PASS
6029 23:59:21.915521 RX DQ/DQS(RDDQC) : PASS
6030 23:59:21.918938 TX DQ/DQS : PASS
6031 23:59:21.919072 RX DATLAT : PASS
6032 23:59:21.922274 RX DQ/DQS(Engine): PASS
6033 23:59:21.925281 TX OE : NO K
6034 23:59:21.925408 All Pass.
6035 23:59:21.925505
6036 23:59:21.925603 CH 1, Rank 0
6037 23:59:21.928553 SW Impedance : PASS
6038 23:59:21.932283 DUTY Scan : NO K
6039 23:59:21.932414 ZQ Calibration : PASS
6040 23:59:21.935500 Jitter Meter : NO K
6041 23:59:21.938853 CBT Training : PASS
6042 23:59:21.938949 Write leveling : PASS
6043 23:59:21.942012 RX DQS gating : PASS
6044 23:59:21.945477 RX DQ/DQS(RDDQC) : PASS
6045 23:59:21.945570 TX DQ/DQS : PASS
6046 23:59:21.948753 RX DATLAT : PASS
6047 23:59:21.952525 RX DQ/DQS(Engine): PASS
6048 23:59:21.952627 TX OE : NO K
6049 23:59:21.952707 All Pass.
6050 23:59:21.955742
6051 23:59:21.955830 CH 1, Rank 1
6052 23:59:21.958551 SW Impedance : PASS
6053 23:59:21.958648 DUTY Scan : NO K
6054 23:59:21.962039 ZQ Calibration : PASS
6055 23:59:21.962150 Jitter Meter : NO K
6056 23:59:21.965752 CBT Training : PASS
6057 23:59:21.969183 Write leveling : PASS
6058 23:59:21.969281 RX DQS gating : PASS
6059 23:59:21.972249 RX DQ/DQS(RDDQC) : PASS
6060 23:59:21.975280 TX DQ/DQS : PASS
6061 23:59:21.975384 RX DATLAT : PASS
6062 23:59:21.979121 RX DQ/DQS(Engine): PASS
6063 23:59:21.982051 TX OE : NO K
6064 23:59:21.982157 All Pass.
6065 23:59:21.982230
6066 23:59:21.985089 DramC Write-DBI off
6067 23:59:21.985188 PER_BANK_REFRESH: Hybrid Mode
6068 23:59:21.988771 TX_TRACKING: ON
6069 23:59:21.998494 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6070 23:59:22.001760 [FAST_K] Save calibration result to emmc
6071 23:59:22.005468 dramc_set_vcore_voltage set vcore to 650000
6072 23:59:22.005625 Read voltage for 400, 6
6073 23:59:22.008633 Vio18 = 0
6074 23:59:22.008769 Vcore = 650000
6075 23:59:22.008887 Vdram = 0
6076 23:59:22.011992 Vddq = 0
6077 23:59:22.012120 Vmddr = 0
6078 23:59:22.015417 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6079 23:59:22.021894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6080 23:59:22.024893 MEM_TYPE=3, freq_sel=20
6081 23:59:22.028528 sv_algorithm_assistance_LP4_800
6082 23:59:22.031649 ============ PULL DRAM RESETB DOWN ============
6083 23:59:22.035395 ========== PULL DRAM RESETB DOWN end =========
6084 23:59:22.041850 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6085 23:59:22.044897 ===================================
6086 23:59:22.045013 LPDDR4 DRAM CONFIGURATION
6087 23:59:22.048099 ===================================
6088 23:59:22.051477 EX_ROW_EN[0] = 0x0
6089 23:59:22.051576 EX_ROW_EN[1] = 0x0
6090 23:59:22.055284 LP4Y_EN = 0x0
6091 23:59:22.055381 WORK_FSP = 0x0
6092 23:59:22.058699 WL = 0x2
6093 23:59:22.058800 RL = 0x2
6094 23:59:22.061888 BL = 0x2
6095 23:59:22.064829 RPST = 0x0
6096 23:59:22.064934 RD_PRE = 0x0
6097 23:59:22.067910 WR_PRE = 0x1
6098 23:59:22.068028 WR_PST = 0x0
6099 23:59:22.071545 DBI_WR = 0x0
6100 23:59:22.071639 DBI_RD = 0x0
6101 23:59:22.074933 OTF = 0x1
6102 23:59:22.078001 ===================================
6103 23:59:22.081496 ===================================
6104 23:59:22.081603 ANA top config
6105 23:59:22.085015 ===================================
6106 23:59:22.087998 DLL_ASYNC_EN = 0
6107 23:59:22.091581 ALL_SLAVE_EN = 1
6108 23:59:22.091689 NEW_RANK_MODE = 1
6109 23:59:22.095025 DLL_IDLE_MODE = 1
6110 23:59:22.097866 LP45_APHY_COMB_EN = 1
6111 23:59:22.101701 TX_ODT_DIS = 1
6112 23:59:22.101804 NEW_8X_MODE = 1
6113 23:59:22.104973 ===================================
6114 23:59:22.108291 ===================================
6115 23:59:22.111805 data_rate = 800
6116 23:59:22.114840 CKR = 1
6117 23:59:22.118038 DQ_P2S_RATIO = 4
6118 23:59:22.121362 ===================================
6119 23:59:22.124631 CA_P2S_RATIO = 4
6120 23:59:22.127949 DQ_CA_OPEN = 0
6121 23:59:22.128087 DQ_SEMI_OPEN = 1
6122 23:59:22.131897 CA_SEMI_OPEN = 1
6123 23:59:22.134519 CA_FULL_RATE = 0
6124 23:59:22.138271 DQ_CKDIV4_EN = 0
6125 23:59:22.141235 CA_CKDIV4_EN = 1
6126 23:59:22.144639 CA_PREDIV_EN = 0
6127 23:59:22.144781 PH8_DLY = 0
6128 23:59:22.147801 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6129 23:59:22.151050 DQ_AAMCK_DIV = 0
6130 23:59:22.154338 CA_AAMCK_DIV = 0
6131 23:59:22.158116 CA_ADMCK_DIV = 4
6132 23:59:22.161411 DQ_TRACK_CA_EN = 0
6133 23:59:22.161511 CA_PICK = 800
6134 23:59:22.164725 CA_MCKIO = 400
6135 23:59:22.167800 MCKIO_SEMI = 400
6136 23:59:22.170991 PLL_FREQ = 3016
6137 23:59:22.174238 DQ_UI_PI_RATIO = 32
6138 23:59:22.178207 CA_UI_PI_RATIO = 32
6139 23:59:22.181250 ===================================
6140 23:59:22.184473 ===================================
6141 23:59:22.187942 memory_type:LPDDR4
6142 23:59:22.188052 GP_NUM : 10
6143 23:59:22.190913 SRAM_EN : 1
6144 23:59:22.191009 MD32_EN : 0
6145 23:59:22.194560 ===================================
6146 23:59:22.197812 [ANA_INIT] >>>>>>>>>>>>>>
6147 23:59:22.200995 <<<<<< [CONFIGURE PHASE]: ANA_TX
6148 23:59:22.204741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6149 23:59:22.207785 ===================================
6150 23:59:22.211154 data_rate = 800,PCW = 0X7400
6151 23:59:22.214786 ===================================
6152 23:59:22.218293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6153 23:59:22.221334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 23:59:22.234350 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6155 23:59:22.237544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6156 23:59:22.241115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6157 23:59:22.244830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6158 23:59:22.247883 [ANA_INIT] flow start
6159 23:59:22.251043 [ANA_INIT] PLL >>>>>>>>
6160 23:59:22.251146 [ANA_INIT] PLL <<<<<<<<
6161 23:59:22.254539 [ANA_INIT] MIDPI >>>>>>>>
6162 23:59:22.257647 [ANA_INIT] MIDPI <<<<<<<<
6163 23:59:22.257772 [ANA_INIT] DLL >>>>>>>>
6164 23:59:22.260835 [ANA_INIT] flow end
6165 23:59:22.264065 ============ LP4 DIFF to SE enter ============
6166 23:59:22.271291 ============ LP4 DIFF to SE exit ============
6167 23:59:22.271426 [ANA_INIT] <<<<<<<<<<<<<
6168 23:59:22.274480 [Flow] Enable top DCM control >>>>>
6169 23:59:22.277488 [Flow] Enable top DCM control <<<<<
6170 23:59:22.280949 Enable DLL master slave shuffle
6171 23:59:22.287688 ==============================================================
6172 23:59:22.287854 Gating Mode config
6173 23:59:22.294002 ==============================================================
6174 23:59:22.297651 Config description:
6175 23:59:22.303959 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6176 23:59:22.310876 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6177 23:59:22.317149 SELPH_MODE 0: By rank 1: By Phase
6178 23:59:22.324162 ==============================================================
6179 23:59:22.324307 GAT_TRACK_EN = 0
6180 23:59:22.327061 RX_GATING_MODE = 2
6181 23:59:22.330385 RX_GATING_TRACK_MODE = 2
6182 23:59:22.334147 SELPH_MODE = 1
6183 23:59:22.337442 PICG_EARLY_EN = 1
6184 23:59:22.340720 VALID_LAT_VALUE = 1
6185 23:59:22.347353 ==============================================================
6186 23:59:22.350848 Enter into Gating configuration >>>>
6187 23:59:22.353757 Exit from Gating configuration <<<<
6188 23:59:22.357570 Enter into DVFS_PRE_config >>>>>
6189 23:59:22.367444 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6190 23:59:22.370661 Exit from DVFS_PRE_config <<<<<
6191 23:59:22.373805 Enter into PICG configuration >>>>
6192 23:59:22.377895 Exit from PICG configuration <<<<
6193 23:59:22.378051 [RX_INPUT] configuration >>>>>
6194 23:59:22.380998 [RX_INPUT] configuration <<<<<
6195 23:59:22.387621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6196 23:59:22.393803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6197 23:59:22.397575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6198 23:59:22.403921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6199 23:59:22.410793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 23:59:22.417219 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 23:59:22.420378 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6202 23:59:22.424397 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6203 23:59:22.430749 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6204 23:59:22.433891 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6205 23:59:22.437125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6206 23:59:22.440280 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6207 23:59:22.444130 ===================================
6208 23:59:22.447351 LPDDR4 DRAM CONFIGURATION
6209 23:59:22.450509 ===================================
6210 23:59:22.453965 EX_ROW_EN[0] = 0x0
6211 23:59:22.454133 EX_ROW_EN[1] = 0x0
6212 23:59:22.457190 LP4Y_EN = 0x0
6213 23:59:22.457336 WORK_FSP = 0x0
6214 23:59:22.460350 WL = 0x2
6215 23:59:22.460500 RL = 0x2
6216 23:59:22.464122 BL = 0x2
6217 23:59:22.464263 RPST = 0x0
6218 23:59:22.467361 RD_PRE = 0x0
6219 23:59:22.467489 WR_PRE = 0x1
6220 23:59:22.470563 WR_PST = 0x0
6221 23:59:22.470685 DBI_WR = 0x0
6222 23:59:22.473692 DBI_RD = 0x0
6223 23:59:22.477075 OTF = 0x1
6224 23:59:22.477231 ===================================
6225 23:59:22.484346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6226 23:59:22.487378 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6227 23:59:22.490608 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6228 23:59:22.493807 ===================================
6229 23:59:22.497143 LPDDR4 DRAM CONFIGURATION
6230 23:59:22.500471 ===================================
6231 23:59:22.503742 EX_ROW_EN[0] = 0x10
6232 23:59:22.503877 EX_ROW_EN[1] = 0x0
6233 23:59:22.506834 LP4Y_EN = 0x0
6234 23:59:22.506958 WORK_FSP = 0x0
6235 23:59:22.510224 WL = 0x2
6236 23:59:22.510344 RL = 0x2
6237 23:59:22.513472 BL = 0x2
6238 23:59:22.513589 RPST = 0x0
6239 23:59:22.517092 RD_PRE = 0x0
6240 23:59:22.517212 WR_PRE = 0x1
6241 23:59:22.520243 WR_PST = 0x0
6242 23:59:22.520368 DBI_WR = 0x0
6243 23:59:22.523464 DBI_RD = 0x0
6244 23:59:22.523585 OTF = 0x1
6245 23:59:22.526802 ===================================
6246 23:59:22.533367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6247 23:59:22.538566 nWR fixed to 30
6248 23:59:22.541693 [ModeRegInit_LP4] CH0 RK0
6249 23:59:22.541831 [ModeRegInit_LP4] CH0 RK1
6250 23:59:22.545260 [ModeRegInit_LP4] CH1 RK0
6251 23:59:22.548298 [ModeRegInit_LP4] CH1 RK1
6252 23:59:22.548442 match AC timing 19
6253 23:59:22.555017 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6254 23:59:22.558688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6255 23:59:22.561685 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6256 23:59:22.568120 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6257 23:59:22.571992 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6258 23:59:22.572106 ==
6259 23:59:22.575404 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 23:59:22.578641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 23:59:22.578743 ==
6262 23:59:22.584812 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 23:59:22.591576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6264 23:59:22.594827 [CA 0] Center 36 (8~64) winsize 57
6265 23:59:22.598480 [CA 1] Center 36 (8~64) winsize 57
6266 23:59:22.601437 [CA 2] Center 36 (8~64) winsize 57
6267 23:59:22.601535 [CA 3] Center 36 (8~64) winsize 57
6268 23:59:22.604725 [CA 4] Center 36 (8~64) winsize 57
6269 23:59:22.607885 [CA 5] Center 36 (8~64) winsize 57
6270 23:59:22.607980
6271 23:59:22.614543 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6272 23:59:22.614652
6273 23:59:22.618570 [CATrainingPosCal] consider 1 rank data
6274 23:59:22.621390 u2DelayCellTimex100 = 270/100 ps
6275 23:59:22.624579 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:59:22.627874 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:59:22.631032 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 23:59:22.634385 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 23:59:22.637663 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 23:59:22.641486 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 23:59:22.641635
6282 23:59:22.644993 CA PerBit enable=1, Macro0, CA PI delay=36
6283 23:59:22.645139
6284 23:59:22.647905 [CBTSetCACLKResult] CA Dly = 36
6285 23:59:22.651050 CS Dly: 1 (0~32)
6286 23:59:22.651193 ==
6287 23:59:22.654760 Dram Type= 6, Freq= 0, CH_0, rank 1
6288 23:59:22.657664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 23:59:22.657816 ==
6290 23:59:22.664321 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6291 23:59:22.670991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6292 23:59:22.671192 [CA 0] Center 36 (8~64) winsize 57
6293 23:59:22.674709 [CA 1] Center 36 (8~64) winsize 57
6294 23:59:22.677911 [CA 2] Center 36 (8~64) winsize 57
6295 23:59:22.681157 [CA 3] Center 36 (8~64) winsize 57
6296 23:59:22.684438 [CA 4] Center 36 (8~64) winsize 57
6297 23:59:22.687715 [CA 5] Center 36 (8~64) winsize 57
6298 23:59:22.687856
6299 23:59:22.690796 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6300 23:59:22.690911
6301 23:59:22.693987 [CATrainingPosCal] consider 2 rank data
6302 23:59:22.697562 u2DelayCellTimex100 = 270/100 ps
6303 23:59:22.700791 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 23:59:22.707844 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 23:59:22.710654 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 23:59:22.713719 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 23:59:22.717076 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 23:59:22.720757 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 23:59:22.720852
6310 23:59:22.723783 CA PerBit enable=1, Macro0, CA PI delay=36
6311 23:59:22.723877
6312 23:59:22.727408 [CBTSetCACLKResult] CA Dly = 36
6313 23:59:22.727508 CS Dly: 1 (0~32)
6314 23:59:22.730581
6315 23:59:22.734349 ----->DramcWriteLeveling(PI) begin...
6316 23:59:22.734459 ==
6317 23:59:22.737626 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 23:59:22.740927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 23:59:22.741028 ==
6320 23:59:22.744052 Write leveling (Byte 0): 40 => 8
6321 23:59:22.747348 Write leveling (Byte 1): 40 => 8
6322 23:59:22.750683 DramcWriteLeveling(PI) end<-----
6323 23:59:22.750832
6324 23:59:22.750933 ==
6325 23:59:22.754062 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 23:59:22.757534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 23:59:22.757677 ==
6328 23:59:22.760335 [Gating] SW mode calibration
6329 23:59:22.766934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6330 23:59:22.773616 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6331 23:59:22.776963 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 23:59:22.780308 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6333 23:59:22.787112 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 23:59:22.790448 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 23:59:22.793538 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 23:59:22.800718 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 23:59:22.803661 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 23:59:22.806999 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 23:59:22.810344 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 23:59:22.813504 Total UI for P1: 0, mck2ui 16
6341 23:59:22.817562 best dqsien dly found for B0: ( 0, 14, 24)
6342 23:59:22.820358 Total UI for P1: 0, mck2ui 16
6343 23:59:22.823444 best dqsien dly found for B1: ( 0, 14, 24)
6344 23:59:22.826902 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6345 23:59:22.833925 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6346 23:59:22.834107
6347 23:59:22.836894 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 23:59:22.840448 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6349 23:59:22.843474 [Gating] SW calibration Done
6350 23:59:22.843613 ==
6351 23:59:22.847138 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 23:59:22.850590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 23:59:22.850736 ==
6354 23:59:22.850855 RX Vref Scan: 0
6355 23:59:22.853964
6356 23:59:22.854096 RX Vref 0 -> 0, step: 1
6357 23:59:22.854218
6358 23:59:22.856973 RX Delay -410 -> 252, step: 16
6359 23:59:22.860113 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6360 23:59:22.866656 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6361 23:59:22.869839 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6362 23:59:22.873587 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6363 23:59:22.876501 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6364 23:59:22.883570 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6365 23:59:22.886637 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6366 23:59:22.890189 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6367 23:59:22.893536 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6368 23:59:22.900103 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6369 23:59:22.903433 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6370 23:59:22.906640 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6371 23:59:22.909798 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6372 23:59:22.916926 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6373 23:59:22.920018 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6374 23:59:22.923279 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6375 23:59:22.923386 ==
6376 23:59:22.926538 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 23:59:22.932943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 23:59:22.933068 ==
6379 23:59:22.933139 DQS Delay:
6380 23:59:22.936667 DQS0 = 27, DQS1 = 35
6381 23:59:22.936760 DQM Delay:
6382 23:59:22.936829 DQM0 = 10, DQM1 = 11
6383 23:59:22.939682 DQ Delay:
6384 23:59:22.943464 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6385 23:59:22.943564 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6386 23:59:22.946496 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6387 23:59:22.949413 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6388 23:59:22.949536
6389 23:59:22.953003
6390 23:59:22.953099 ==
6391 23:59:22.956471 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 23:59:22.959426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 23:59:22.959532 ==
6394 23:59:22.959601
6395 23:59:22.959664
6396 23:59:22.962732 TX Vref Scan disable
6397 23:59:22.962826 == TX Byte 0 ==
6398 23:59:22.965971 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 23:59:22.973058 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 23:59:22.973186 == TX Byte 1 ==
6401 23:59:22.976400 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 23:59:22.982717 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 23:59:22.982845 ==
6404 23:59:22.986366 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 23:59:22.989638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 23:59:22.989797 ==
6407 23:59:22.989920
6408 23:59:22.990035
6409 23:59:22.992849 TX Vref Scan disable
6410 23:59:22.992985 == TX Byte 0 ==
6411 23:59:22.996023 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 23:59:23.003005 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 23:59:23.003188 == TX Byte 1 ==
6414 23:59:23.006078 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 23:59:23.012426 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 23:59:23.012559
6417 23:59:23.012631 [DATLAT]
6418 23:59:23.012697 Freq=400, CH0 RK0
6419 23:59:23.016422
6420 23:59:23.016518 DATLAT Default: 0xf
6421 23:59:23.019439 0, 0xFFFF, sum = 0
6422 23:59:23.019553 1, 0xFFFF, sum = 0
6423 23:59:23.022918 2, 0xFFFF, sum = 0
6424 23:59:23.023015 3, 0xFFFF, sum = 0
6425 23:59:23.025991 4, 0xFFFF, sum = 0
6426 23:59:23.026083 5, 0xFFFF, sum = 0
6427 23:59:23.029196 6, 0xFFFF, sum = 0
6428 23:59:23.029291 7, 0xFFFF, sum = 0
6429 23:59:23.032604 8, 0xFFFF, sum = 0
6430 23:59:23.032700 9, 0xFFFF, sum = 0
6431 23:59:23.036235 10, 0xFFFF, sum = 0
6432 23:59:23.036372 11, 0xFFFF, sum = 0
6433 23:59:23.039603 12, 0xFFFF, sum = 0
6434 23:59:23.039696 13, 0x0, sum = 1
6435 23:59:23.042820 14, 0x0, sum = 2
6436 23:59:23.042911 15, 0x0, sum = 3
6437 23:59:23.045873 16, 0x0, sum = 4
6438 23:59:23.045967 best_step = 14
6439 23:59:23.046036
6440 23:59:23.046100 ==
6441 23:59:23.049484 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 23:59:23.052521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 23:59:23.056519 ==
6444 23:59:23.056629 RX Vref Scan: 1
6445 23:59:23.056699
6446 23:59:23.059538 RX Vref 0 -> 0, step: 1
6447 23:59:23.059628
6448 23:59:23.062545 RX Delay -311 -> 252, step: 8
6449 23:59:23.062640
6450 23:59:23.066130 Set Vref, RX VrefLevel [Byte0]: 57
6451 23:59:23.068989 [Byte1]: 48
6452 23:59:23.069087
6453 23:59:23.072295 Final RX Vref Byte 0 = 57 to rank0
6454 23:59:23.076172 Final RX Vref Byte 1 = 48 to rank0
6455 23:59:23.079424 Final RX Vref Byte 0 = 57 to rank1
6456 23:59:23.082643 Final RX Vref Byte 1 = 48 to rank1==
6457 23:59:23.085918 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 23:59:23.089008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 23:59:23.089170 ==
6460 23:59:23.092610 DQS Delay:
6461 23:59:23.092747 DQS0 = 28, DQS1 = 36
6462 23:59:23.095747 DQM Delay:
6463 23:59:23.095897 DQM0 = 11, DQM1 = 13
6464 23:59:23.096015 DQ Delay:
6465 23:59:23.099092 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6466 23:59:23.102282 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6467 23:59:23.105585 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6468 23:59:23.108753 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6469 23:59:23.108896
6470 23:59:23.109017
6471 23:59:23.118745 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6472 23:59:23.122313 CH0 RK0: MR19=C0C, MR18=C9B7
6473 23:59:23.125895 CH0_RK0: MR19=0xC0C, MR18=0xC9B7, DQSOSC=384, MR23=63, INC=400, DEC=267
6474 23:59:23.128862 ==
6475 23:59:23.128983 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 23:59:23.135907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 23:59:23.136062 ==
6478 23:59:23.138888 [Gating] SW mode calibration
6479 23:59:23.145428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6480 23:59:23.148775 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6481 23:59:23.155229 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 23:59:23.158877 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 23:59:23.162408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 23:59:23.168514 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 23:59:23.172222 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 23:59:23.175129 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 23:59:23.181885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 23:59:23.185235 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 23:59:23.189115 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 23:59:23.192247 Total UI for P1: 0, mck2ui 16
6491 23:59:23.195767 best dqsien dly found for B0: ( 0, 14, 24)
6492 23:59:23.198670 Total UI for P1: 0, mck2ui 16
6493 23:59:23.202091 best dqsien dly found for B1: ( 0, 14, 24)
6494 23:59:23.205309 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6495 23:59:23.208612 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6496 23:59:23.208760
6497 23:59:23.212166 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 23:59:23.218395 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6499 23:59:23.218540 [Gating] SW calibration Done
6500 23:59:23.222112 ==
6501 23:59:23.222233 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 23:59:23.228742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 23:59:23.228853 ==
6504 23:59:23.228955 RX Vref Scan: 0
6505 23:59:23.229025
6506 23:59:23.231678 RX Vref 0 -> 0, step: 1
6507 23:59:23.231802
6508 23:59:23.234961 RX Delay -410 -> 252, step: 16
6509 23:59:23.238736 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6510 23:59:23.241739 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6511 23:59:23.248651 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6512 23:59:23.251889 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6513 23:59:23.255128 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6514 23:59:23.258524 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6515 23:59:23.265053 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6516 23:59:23.268030 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6517 23:59:23.271699 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6518 23:59:23.274809 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6519 23:59:23.281316 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6520 23:59:23.284930 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6521 23:59:23.287848 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6522 23:59:23.291291 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6523 23:59:23.297861 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6524 23:59:23.301082 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6525 23:59:23.301209 ==
6526 23:59:23.304549 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 23:59:23.308026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 23:59:23.308127 ==
6529 23:59:23.311499 DQS Delay:
6530 23:59:23.311595 DQS0 = 19, DQS1 = 35
6531 23:59:23.314517 DQM Delay:
6532 23:59:23.314613 DQM0 = 5, DQM1 = 12
6533 23:59:23.314704 DQ Delay:
6534 23:59:23.317820 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6535 23:59:23.321725 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6536 23:59:23.324899 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6537 23:59:23.327934 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6538 23:59:23.328031
6539 23:59:23.328123
6540 23:59:23.328209 ==
6541 23:59:23.331078 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 23:59:23.338147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 23:59:23.338268 ==
6544 23:59:23.338367
6545 23:59:23.338453
6546 23:59:23.338536 TX Vref Scan disable
6547 23:59:23.341597 == TX Byte 0 ==
6548 23:59:23.344919 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6549 23:59:23.348204 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6550 23:59:23.351136 == TX Byte 1 ==
6551 23:59:23.354435 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 23:59:23.357745 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 23:59:23.357845 ==
6554 23:59:23.361017 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 23:59:23.368177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 23:59:23.368304 ==
6557 23:59:23.368409
6558 23:59:23.368494
6559 23:59:23.368577 TX Vref Scan disable
6560 23:59:23.371521 == TX Byte 0 ==
6561 23:59:23.374777 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6562 23:59:23.378014 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6563 23:59:23.381251 == TX Byte 1 ==
6564 23:59:23.384362 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6565 23:59:23.388072 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6566 23:59:23.388179
6567 23:59:23.391009 [DATLAT]
6568 23:59:23.391105 Freq=400, CH0 RK1
6569 23:59:23.391197
6570 23:59:23.394300 DATLAT Default: 0xe
6571 23:59:23.394399 0, 0xFFFF, sum = 0
6572 23:59:23.398273 1, 0xFFFF, sum = 0
6573 23:59:23.398376 2, 0xFFFF, sum = 0
6574 23:59:23.401103 3, 0xFFFF, sum = 0
6575 23:59:23.401250 4, 0xFFFF, sum = 0
6576 23:59:23.404573 5, 0xFFFF, sum = 0
6577 23:59:23.404716 6, 0xFFFF, sum = 0
6578 23:59:23.408031 7, 0xFFFF, sum = 0
6579 23:59:23.408170 8, 0xFFFF, sum = 0
6580 23:59:23.411355 9, 0xFFFF, sum = 0
6581 23:59:23.411473 10, 0xFFFF, sum = 0
6582 23:59:23.414648 11, 0xFFFF, sum = 0
6583 23:59:23.414741 12, 0xFFFF, sum = 0
6584 23:59:23.417688 13, 0x0, sum = 1
6585 23:59:23.417778 14, 0x0, sum = 2
6586 23:59:23.421200 15, 0x0, sum = 3
6587 23:59:23.421291 16, 0x0, sum = 4
6588 23:59:23.424737 best_step = 14
6589 23:59:23.424832
6590 23:59:23.424901 ==
6591 23:59:23.428047 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 23:59:23.431185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 23:59:23.431285 ==
6594 23:59:23.434488 RX Vref Scan: 0
6595 23:59:23.434583
6596 23:59:23.434674 RX Vref 0 -> 0, step: 1
6597 23:59:23.434760
6598 23:59:23.437376 RX Delay -311 -> 252, step: 8
6599 23:59:23.445528 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6600 23:59:23.448801 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6601 23:59:23.452595 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6602 23:59:23.455715 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6603 23:59:23.462260 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6604 23:59:23.465753 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6605 23:59:23.468743 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6606 23:59:23.472037 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6607 23:59:23.478653 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6608 23:59:23.482017 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6609 23:59:23.485940 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6610 23:59:23.489191 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6611 23:59:23.495750 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6612 23:59:23.498812 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6613 23:59:23.501941 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6614 23:59:23.508830 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6615 23:59:23.508964 ==
6616 23:59:23.512272 Dram Type= 6, Freq= 0, CH_0, rank 1
6617 23:59:23.515258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 23:59:23.515355 ==
6619 23:59:23.515448 DQS Delay:
6620 23:59:23.518708 DQS0 = 24, DQS1 = 36
6621 23:59:23.518801 DQM Delay:
6622 23:59:23.522347 DQM0 = 8, DQM1 = 13
6623 23:59:23.522443 DQ Delay:
6624 23:59:23.525544 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6625 23:59:23.529067 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6626 23:59:23.532199 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6627 23:59:23.535115 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6628 23:59:23.535217
6629 23:59:23.535308
6630 23:59:23.542029 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6631 23:59:23.545719 CH0 RK1: MR19=C0C, MR18=BC5C
6632 23:59:23.551747 CH0_RK1: MR19=0xC0C, MR18=0xBC5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6633 23:59:23.555656 [RxdqsGatingPostProcess] freq 400
6634 23:59:23.558858 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6635 23:59:23.562141 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 23:59:23.565268 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 23:59:23.568522 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 23:59:23.571900 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 23:59:23.575475 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 23:59:23.578604 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 23:59:23.581769 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 23:59:23.584984 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 23:59:23.588914 Pre-setting of DQS Precalculation
6644 23:59:23.592221 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6645 23:59:23.592320 ==
6646 23:59:23.595400 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 23:59:23.601834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 23:59:23.602046 ==
6649 23:59:23.605159 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 23:59:23.612134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6651 23:59:23.615258 [CA 0] Center 36 (8~64) winsize 57
6652 23:59:23.618959 [CA 1] Center 36 (8~64) winsize 57
6653 23:59:23.621991 [CA 2] Center 36 (8~64) winsize 57
6654 23:59:23.625045 [CA 3] Center 36 (8~64) winsize 57
6655 23:59:23.628653 [CA 4] Center 36 (8~64) winsize 57
6656 23:59:23.632124 [CA 5] Center 36 (8~64) winsize 57
6657 23:59:23.632266
6658 23:59:23.635545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6659 23:59:23.635636
6660 23:59:23.638462 [CATrainingPosCal] consider 1 rank data
6661 23:59:23.642055 u2DelayCellTimex100 = 270/100 ps
6662 23:59:23.645152 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:59:23.648604 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:59:23.652132 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 23:59:23.655123 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 23:59:23.658414 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 23:59:23.661743 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 23:59:23.665572
6669 23:59:23.668834 CA PerBit enable=1, Macro0, CA PI delay=36
6670 23:59:23.668923
6671 23:59:23.672104 [CBTSetCACLKResult] CA Dly = 36
6672 23:59:23.672190 CS Dly: 1 (0~32)
6673 23:59:23.672257 ==
6674 23:59:23.675528 Dram Type= 6, Freq= 0, CH_1, rank 1
6675 23:59:23.678603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 23:59:23.678692 ==
6677 23:59:23.684743 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6678 23:59:23.691822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6679 23:59:23.695017 [CA 0] Center 36 (8~64) winsize 57
6680 23:59:23.698203 [CA 1] Center 36 (8~64) winsize 57
6681 23:59:23.701655 [CA 2] Center 36 (8~64) winsize 57
6682 23:59:23.704880 [CA 3] Center 36 (8~64) winsize 57
6683 23:59:23.708205 [CA 4] Center 36 (8~64) winsize 57
6684 23:59:23.708321 [CA 5] Center 36 (8~64) winsize 57
6685 23:59:23.711468
6686 23:59:23.714661 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6687 23:59:23.714783
6688 23:59:23.718216 [CATrainingPosCal] consider 2 rank data
6689 23:59:23.721487 u2DelayCellTimex100 = 270/100 ps
6690 23:59:23.725516 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 23:59:23.728288 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 23:59:23.731419 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 23:59:23.734727 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 23:59:23.737854 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 23:59:23.741448 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 23:59:23.741541
6697 23:59:23.744713 CA PerBit enable=1, Macro0, CA PI delay=36
6698 23:59:23.744817
6699 23:59:23.747692 [CBTSetCACLKResult] CA Dly = 36
6700 23:59:23.751405 CS Dly: 1 (0~32)
6701 23:59:23.751552
6702 23:59:23.754609 ----->DramcWriteLeveling(PI) begin...
6703 23:59:23.754719 ==
6704 23:59:23.758230 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 23:59:23.761461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 23:59:23.761599 ==
6707 23:59:23.764661 Write leveling (Byte 0): 40 => 8
6708 23:59:23.768013 Write leveling (Byte 1): 40 => 8
6709 23:59:23.771143 DramcWriteLeveling(PI) end<-----
6710 23:59:23.771303
6711 23:59:23.771452 ==
6712 23:59:23.774929 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 23:59:23.778242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 23:59:23.778377 ==
6715 23:59:23.781678 [Gating] SW mode calibration
6716 23:59:23.787880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6717 23:59:23.794763 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6718 23:59:23.797857 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 23:59:23.801156 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6720 23:59:23.807550 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 23:59:23.810879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 23:59:23.814279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 23:59:23.821144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 23:59:23.824513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 23:59:23.827762 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 23:59:23.834442 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 23:59:23.837469 Total UI for P1: 0, mck2ui 16
6728 23:59:23.841372 best dqsien dly found for B0: ( 0, 14, 24)
6729 23:59:23.844533 Total UI for P1: 0, mck2ui 16
6730 23:59:23.847548 best dqsien dly found for B1: ( 0, 14, 24)
6731 23:59:23.850752 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6732 23:59:23.854081 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6733 23:59:23.854194
6734 23:59:23.857446 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 23:59:23.860712 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6736 23:59:23.864159 [Gating] SW calibration Done
6737 23:59:23.864291 ==
6738 23:59:23.867297 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 23:59:23.870974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 23:59:23.871076 ==
6741 23:59:23.873930 RX Vref Scan: 0
6742 23:59:23.874024
6743 23:59:23.877314 RX Vref 0 -> 0, step: 1
6744 23:59:23.877408
6745 23:59:23.877499 RX Delay -410 -> 252, step: 16
6746 23:59:23.884073 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6747 23:59:23.887482 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6748 23:59:23.890552 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6749 23:59:23.897615 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6750 23:59:23.900852 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6751 23:59:23.903857 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6752 23:59:23.907511 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6753 23:59:23.910813 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6754 23:59:23.917174 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6755 23:59:23.920285 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6756 23:59:23.923554 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6757 23:59:23.930672 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6758 23:59:23.933831 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6759 23:59:23.937049 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6760 23:59:23.940242 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6761 23:59:23.947010 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6762 23:59:23.947161 ==
6763 23:59:23.950364 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 23:59:23.953694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 23:59:23.953850 ==
6766 23:59:23.953966 DQS Delay:
6767 23:59:23.956939 DQS0 = 35, DQS1 = 35
6768 23:59:23.957062 DQM Delay:
6769 23:59:23.960301 DQM0 = 18, DQM1 = 14
6770 23:59:23.960414 DQ Delay:
6771 23:59:23.963495 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6772 23:59:23.967081 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6773 23:59:23.970054 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6774 23:59:23.973621 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6775 23:59:23.973756
6776 23:59:23.973875
6777 23:59:23.973988 ==
6778 23:59:23.977238 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 23:59:23.980288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 23:59:23.980465 ==
6781 23:59:23.980613
6782 23:59:23.980738
6783 23:59:23.983424 TX Vref Scan disable
6784 23:59:23.987048 == TX Byte 0 ==
6785 23:59:23.989833 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 23:59:23.993931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 23:59:23.996644 == TX Byte 1 ==
6788 23:59:24.000187 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 23:59:24.003635 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 23:59:24.003749 ==
6791 23:59:24.006866 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 23:59:24.010021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 23:59:24.010115 ==
6794 23:59:24.010213
6795 23:59:24.010306
6796 23:59:24.013128 TX Vref Scan disable
6797 23:59:24.016915 == TX Byte 0 ==
6798 23:59:24.020349 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 23:59:24.023329 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 23:59:24.026660 == TX Byte 1 ==
6801 23:59:24.029896 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 23:59:24.033266 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 23:59:24.033393
6804 23:59:24.033475 [DATLAT]
6805 23:59:24.037117 Freq=400, CH1 RK0
6806 23:59:24.037220
6807 23:59:24.037316 DATLAT Default: 0xf
6808 23:59:24.040385 0, 0xFFFF, sum = 0
6809 23:59:24.040475 1, 0xFFFF, sum = 0
6810 23:59:24.043629 2, 0xFFFF, sum = 0
6811 23:59:24.043730 3, 0xFFFF, sum = 0
6812 23:59:24.046730 4, 0xFFFF, sum = 0
6813 23:59:24.049954 5, 0xFFFF, sum = 0
6814 23:59:24.050060 6, 0xFFFF, sum = 0
6815 23:59:24.053695 7, 0xFFFF, sum = 0
6816 23:59:24.053835 8, 0xFFFF, sum = 0
6817 23:59:24.056895 9, 0xFFFF, sum = 0
6818 23:59:24.057031 10, 0xFFFF, sum = 0
6819 23:59:24.060166 11, 0xFFFF, sum = 0
6820 23:59:24.060303 12, 0xFFFF, sum = 0
6821 23:59:24.063530 13, 0x0, sum = 1
6822 23:59:24.063664 14, 0x0, sum = 2
6823 23:59:24.066825 15, 0x0, sum = 3
6824 23:59:24.066958 16, 0x0, sum = 4
6825 23:59:24.070070 best_step = 14
6826 23:59:24.070197
6827 23:59:24.070313 ==
6828 23:59:24.073303 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 23:59:24.076434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 23:59:24.076566 ==
6831 23:59:24.076688 RX Vref Scan: 1
6832 23:59:24.076801
6833 23:59:24.079963 RX Vref 0 -> 0, step: 1
6834 23:59:24.080093
6835 23:59:24.083390 RX Delay -311 -> 252, step: 8
6836 23:59:24.083515
6837 23:59:24.086430 Set Vref, RX VrefLevel [Byte0]: 55
6838 23:59:24.089807 [Byte1]: 48
6839 23:59:24.093663
6840 23:59:24.096738 Final RX Vref Byte 0 = 55 to rank0
6841 23:59:24.096865 Final RX Vref Byte 1 = 48 to rank0
6842 23:59:24.100401 Final RX Vref Byte 0 = 55 to rank1
6843 23:59:24.103497 Final RX Vref Byte 1 = 48 to rank1==
6844 23:59:24.106944 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 23:59:24.113492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 23:59:24.113633 ==
6847 23:59:24.113733 DQS Delay:
6848 23:59:24.116896 DQS0 = 28, DQS1 = 32
6849 23:59:24.116985 DQM Delay:
6850 23:59:24.117052 DQM0 = 9, DQM1 = 11
6851 23:59:24.120165 DQ Delay:
6852 23:59:24.123224 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6853 23:59:24.123368 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6854 23:59:24.126899 DQ8 =0, DQ9 =4, DQ10 =8, DQ11 =4
6855 23:59:24.129912 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6856 23:59:24.130027
6857 23:59:24.133239
6858 23:59:24.139727 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6859 23:59:24.143008 CH1 RK0: MR19=C0C, MR18=92CC
6860 23:59:24.150103 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6861 23:59:24.150226 ==
6862 23:59:24.153395 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 23:59:24.156319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 23:59:24.156427 ==
6865 23:59:24.159720 [Gating] SW mode calibration
6866 23:59:24.166819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6867 23:59:24.173514 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6868 23:59:24.176500 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 23:59:24.179691 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6870 23:59:24.186177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 23:59:24.189872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 23:59:24.192861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 23:59:24.199713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 23:59:24.203188 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 23:59:24.206420 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 23:59:24.209556 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 23:59:24.212742 Total UI for P1: 0, mck2ui 16
6878 23:59:24.216651 best dqsien dly found for B0: ( 0, 14, 24)
6879 23:59:24.220149 Total UI for P1: 0, mck2ui 16
6880 23:59:24.223528 best dqsien dly found for B1: ( 0, 14, 24)
6881 23:59:24.226342 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6882 23:59:24.229781 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6883 23:59:24.233241
6884 23:59:24.236485 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 23:59:24.239727 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6886 23:59:24.242673 [Gating] SW calibration Done
6887 23:59:24.242809 ==
6888 23:59:24.245965 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 23:59:24.249796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 23:59:24.249888 ==
6891 23:59:24.249958 RX Vref Scan: 0
6892 23:59:24.252982
6893 23:59:24.253087 RX Vref 0 -> 0, step: 1
6894 23:59:24.253157
6895 23:59:24.256186 RX Delay -410 -> 252, step: 16
6896 23:59:24.259443 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6897 23:59:24.266610 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6898 23:59:24.269490 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6899 23:59:24.272665 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6900 23:59:24.276040 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6901 23:59:24.282527 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6902 23:59:24.285696 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6903 23:59:24.289831 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6904 23:59:24.292861 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6905 23:59:24.299332 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6906 23:59:24.302848 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6907 23:59:24.306409 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6908 23:59:24.309234 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6909 23:59:24.315742 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6910 23:59:24.319069 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6911 23:59:24.322797 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6912 23:59:24.322959 ==
6913 23:59:24.325847 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 23:59:24.329405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 23:59:24.332605 ==
6916 23:59:24.332745 DQS Delay:
6917 23:59:24.332866 DQS0 = 35, DQS1 = 35
6918 23:59:24.336218 DQM Delay:
6919 23:59:24.336373 DQM0 = 18, DQM1 = 13
6920 23:59:24.339235 DQ Delay:
6921 23:59:24.342227 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6922 23:59:24.342363 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6923 23:59:24.345844 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6924 23:59:24.349340 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6925 23:59:24.349473
6926 23:59:24.352480
6927 23:59:24.352683 ==
6928 23:59:24.355466 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 23:59:24.359146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 23:59:24.359268 ==
6931 23:59:24.359366
6932 23:59:24.359457
6933 23:59:24.362407 TX Vref Scan disable
6934 23:59:24.362512 == TX Byte 0 ==
6935 23:59:24.365694 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6936 23:59:24.372492 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6937 23:59:24.372656 == TX Byte 1 ==
6938 23:59:24.375974 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 23:59:24.382570 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 23:59:24.382709 ==
6941 23:59:24.385780 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 23:59:24.389149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 23:59:24.389242 ==
6944 23:59:24.389309
6945 23:59:24.389371
6946 23:59:24.392332 TX Vref Scan disable
6947 23:59:24.392436 == TX Byte 0 ==
6948 23:59:24.395611 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6949 23:59:24.402250 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6950 23:59:24.402362 == TX Byte 1 ==
6951 23:59:24.405474 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6952 23:59:24.412509 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6953 23:59:24.412699
6954 23:59:24.412820 [DATLAT]
6955 23:59:24.412968 Freq=400, CH1 RK1
6956 23:59:24.413083
6957 23:59:24.415689 DATLAT Default: 0xe
6958 23:59:24.415817 0, 0xFFFF, sum = 0
6959 23:59:24.418722 1, 0xFFFF, sum = 0
6960 23:59:24.422595 2, 0xFFFF, sum = 0
6961 23:59:24.422730 3, 0xFFFF, sum = 0
6962 23:59:24.425757 4, 0xFFFF, sum = 0
6963 23:59:24.425873 5, 0xFFFF, sum = 0
6964 23:59:24.428894 6, 0xFFFF, sum = 0
6965 23:59:24.429011 7, 0xFFFF, sum = 0
6966 23:59:24.432268 8, 0xFFFF, sum = 0
6967 23:59:24.432422 9, 0xFFFF, sum = 0
6968 23:59:24.435496 10, 0xFFFF, sum = 0
6969 23:59:24.435612 11, 0xFFFF, sum = 0
6970 23:59:24.438787 12, 0xFFFF, sum = 0
6971 23:59:24.438906 13, 0x0, sum = 1
6972 23:59:24.442417 14, 0x0, sum = 2
6973 23:59:24.442548 15, 0x0, sum = 3
6974 23:59:24.445438 16, 0x0, sum = 4
6975 23:59:24.445557 best_step = 14
6976 23:59:24.445656
6977 23:59:24.445752 ==
6978 23:59:24.449122 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 23:59:24.452148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 23:59:24.455273 ==
6981 23:59:24.455400 RX Vref Scan: 0
6982 23:59:24.455501
6983 23:59:24.459061 RX Vref 0 -> 0, step: 1
6984 23:59:24.459176
6985 23:59:24.462196 RX Delay -311 -> 252, step: 8
6986 23:59:24.465092 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6987 23:59:24.472019 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6988 23:59:24.475324 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6989 23:59:24.478452 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6990 23:59:24.482093 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6991 23:59:24.488801 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6992 23:59:24.492157 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6993 23:59:24.495539 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6994 23:59:24.498802 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6995 23:59:24.505577 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6996 23:59:24.508772 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6997 23:59:24.512039 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6998 23:59:24.515326 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6999 23:59:24.522021 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7000 23:59:24.524878 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7001 23:59:24.528141 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7002 23:59:24.528273 ==
7003 23:59:24.531455 Dram Type= 6, Freq= 0, CH_1, rank 1
7004 23:59:24.538101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7005 23:59:24.538278 ==
7006 23:59:24.538385 DQS Delay:
7007 23:59:24.541912 DQS0 = 28, DQS1 = 32
7008 23:59:24.542048 DQM Delay:
7009 23:59:24.542147 DQM0 = 11, DQM1 = 11
7010 23:59:24.545142 DQ Delay:
7011 23:59:24.548080 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7012 23:59:24.551361 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7013 23:59:24.551505 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7014 23:59:24.558059 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7015 23:59:24.558271
7016 23:59:24.558398
7017 23:59:24.564468 [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7018 23:59:24.568298 CH1 RK1: MR19=C0C, MR18=C758
7019 23:59:24.574753 CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265
7020 23:59:24.577782 [RxdqsGatingPostProcess] freq 400
7021 23:59:24.581384 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7022 23:59:24.584975 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 23:59:24.588085 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 23:59:24.591297 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 23:59:24.594572 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 23:59:24.597768 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 23:59:24.601715 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 23:59:24.604941 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 23:59:24.608444 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 23:59:24.611407 Pre-setting of DQS Precalculation
7031 23:59:24.614587 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7032 23:59:24.621077 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7033 23:59:24.631267 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7034 23:59:24.631472
7035 23:59:24.631598
7036 23:59:24.634411 [Calibration Summary] 800 Mbps
7037 23:59:24.634543 CH 0, Rank 0
7038 23:59:24.637623 SW Impedance : PASS
7039 23:59:24.637752 DUTY Scan : NO K
7040 23:59:24.641154 ZQ Calibration : PASS
7041 23:59:24.644804 Jitter Meter : NO K
7042 23:59:24.644940 CBT Training : PASS
7043 23:59:24.647996 Write leveling : PASS
7044 23:59:24.648105 RX DQS gating : PASS
7045 23:59:24.651401 RX DQ/DQS(RDDQC) : PASS
7046 23:59:24.654565 TX DQ/DQS : PASS
7047 23:59:24.654706 RX DATLAT : PASS
7048 23:59:24.657735 RX DQ/DQS(Engine): PASS
7049 23:59:24.660933 TX OE : NO K
7050 23:59:24.661068 All Pass.
7051 23:59:24.661185
7052 23:59:24.661300 CH 0, Rank 1
7053 23:59:24.664418 SW Impedance : PASS
7054 23:59:24.667501 DUTY Scan : NO K
7055 23:59:24.667598 ZQ Calibration : PASS
7056 23:59:24.671274 Jitter Meter : NO K
7057 23:59:24.674346 CBT Training : PASS
7058 23:59:24.674437 Write leveling : NO K
7059 23:59:24.677377 RX DQS gating : PASS
7060 23:59:24.680790 RX DQ/DQS(RDDQC) : PASS
7061 23:59:24.680930 TX DQ/DQS : PASS
7062 23:59:24.684323 RX DATLAT : PASS
7063 23:59:24.687445 RX DQ/DQS(Engine): PASS
7064 23:59:24.687584 TX OE : NO K
7065 23:59:24.687705 All Pass.
7066 23:59:24.691328
7067 23:59:24.691461 CH 1, Rank 0
7068 23:59:24.694239 SW Impedance : PASS
7069 23:59:24.694370 DUTY Scan : NO K
7070 23:59:24.697707 ZQ Calibration : PASS
7071 23:59:24.697841 Jitter Meter : NO K
7072 23:59:24.701008 CBT Training : PASS
7073 23:59:24.704520 Write leveling : PASS
7074 23:59:24.704655 RX DQS gating : PASS
7075 23:59:24.707783 RX DQ/DQS(RDDQC) : PASS
7076 23:59:24.710988 TX DQ/DQS : PASS
7077 23:59:24.711125 RX DATLAT : PASS
7078 23:59:24.714170 RX DQ/DQS(Engine): PASS
7079 23:59:24.717468 TX OE : NO K
7080 23:59:24.717566 All Pass.
7081 23:59:24.717634
7082 23:59:24.717698 CH 1, Rank 1
7083 23:59:24.720674 SW Impedance : PASS
7084 23:59:24.724397 DUTY Scan : NO K
7085 23:59:24.724493 ZQ Calibration : PASS
7086 23:59:24.727678 Jitter Meter : NO K
7087 23:59:24.730965 CBT Training : PASS
7088 23:59:24.731058 Write leveling : NO K
7089 23:59:24.734068 RX DQS gating : PASS
7090 23:59:24.737862 RX DQ/DQS(RDDQC) : PASS
7091 23:59:24.737989 TX DQ/DQS : PASS
7092 23:59:24.740890 RX DATLAT : PASS
7093 23:59:24.744114 RX DQ/DQS(Engine): PASS
7094 23:59:24.744206 TX OE : NO K
7095 23:59:24.744277 All Pass.
7096 23:59:24.744349
7097 23:59:24.747450 DramC Write-DBI off
7098 23:59:24.751158 PER_BANK_REFRESH: Hybrid Mode
7099 23:59:24.751302 TX_TRACKING: ON
7100 23:59:24.760810 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7101 23:59:24.764155 [FAST_K] Save calibration result to emmc
7102 23:59:24.767432 dramc_set_vcore_voltage set vcore to 725000
7103 23:59:24.770671 Read voltage for 1600, 0
7104 23:59:24.770812 Vio18 = 0
7105 23:59:24.774808 Vcore = 725000
7106 23:59:24.774948 Vdram = 0
7107 23:59:24.775069 Vddq = 0
7108 23:59:24.775186 Vmddr = 0
7109 23:59:24.780832 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7110 23:59:24.787164 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7111 23:59:24.787349 MEM_TYPE=3, freq_sel=13
7112 23:59:24.790653 sv_algorithm_assistance_LP4_3733
7113 23:59:24.795340 ============ PULL DRAM RESETB DOWN ============
7114 23:59:24.800506 ========== PULL DRAM RESETB DOWN end =========
7115 23:59:24.804258 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7116 23:59:24.806891 ===================================
7117 23:59:24.810699 LPDDR4 DRAM CONFIGURATION
7118 23:59:24.813695 ===================================
7119 23:59:24.813793 EX_ROW_EN[0] = 0x0
7120 23:59:24.817102 EX_ROW_EN[1] = 0x0
7121 23:59:24.817196 LP4Y_EN = 0x0
7122 23:59:24.820240 WORK_FSP = 0x1
7123 23:59:24.820392 WL = 0x5
7124 23:59:24.824149 RL = 0x5
7125 23:59:24.824283 BL = 0x2
7126 23:59:24.827355 RPST = 0x0
7127 23:59:24.830559 RD_PRE = 0x0
7128 23:59:24.830669 WR_PRE = 0x1
7129 23:59:24.833840 WR_PST = 0x1
7130 23:59:24.833950 DBI_WR = 0x0
7131 23:59:24.837036 DBI_RD = 0x0
7132 23:59:24.837142 OTF = 0x1
7133 23:59:24.840307 ===================================
7134 23:59:24.843463 ===================================
7135 23:59:24.847296 ANA top config
7136 23:59:24.850576 ===================================
7137 23:59:24.850668 DLL_ASYNC_EN = 0
7138 23:59:24.853756 ALL_SLAVE_EN = 0
7139 23:59:24.857060 NEW_RANK_MODE = 1
7140 23:59:24.860228 DLL_IDLE_MODE = 1
7141 23:59:24.860357 LP45_APHY_COMB_EN = 1
7142 23:59:24.863394 TX_ODT_DIS = 0
7143 23:59:24.866725 NEW_8X_MODE = 1
7144 23:59:24.869889 ===================================
7145 23:59:24.873224 ===================================
7146 23:59:24.877042 data_rate = 3200
7147 23:59:24.880289 CKR = 1
7148 23:59:24.883566 DQ_P2S_RATIO = 8
7149 23:59:24.886444 ===================================
7150 23:59:24.886585 CA_P2S_RATIO = 8
7151 23:59:24.889934 DQ_CA_OPEN = 0
7152 23:59:24.893284 DQ_SEMI_OPEN = 0
7153 23:59:24.896485 CA_SEMI_OPEN = 0
7154 23:59:24.899683 CA_FULL_RATE = 0
7155 23:59:24.903395 DQ_CKDIV4_EN = 0
7156 23:59:24.903484 CA_CKDIV4_EN = 0
7157 23:59:24.906884 CA_PREDIV_EN = 0
7158 23:59:24.909803 PH8_DLY = 12
7159 23:59:24.913100 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7160 23:59:24.916291 DQ_AAMCK_DIV = 4
7161 23:59:24.919928 CA_AAMCK_DIV = 4
7162 23:59:24.920021 CA_ADMCK_DIV = 4
7163 23:59:24.922923 DQ_TRACK_CA_EN = 0
7164 23:59:24.926601 CA_PICK = 1600
7165 23:59:24.930096 CA_MCKIO = 1600
7166 23:59:24.932996 MCKIO_SEMI = 0
7167 23:59:24.936297 PLL_FREQ = 3068
7168 23:59:24.939933 DQ_UI_PI_RATIO = 32
7169 23:59:24.940023 CA_UI_PI_RATIO = 0
7170 23:59:24.943086 ===================================
7171 23:59:24.946508 ===================================
7172 23:59:24.949347 memory_type:LPDDR4
7173 23:59:24.952915 GP_NUM : 10
7174 23:59:24.953004 SRAM_EN : 1
7175 23:59:24.956100 MD32_EN : 0
7176 23:59:24.959348 ===================================
7177 23:59:24.962655 [ANA_INIT] >>>>>>>>>>>>>>
7178 23:59:24.965870 <<<<<< [CONFIGURE PHASE]: ANA_TX
7179 23:59:24.969231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7180 23:59:24.972499 ===================================
7181 23:59:24.972596 data_rate = 3200,PCW = 0X7600
7182 23:59:24.976283 ===================================
7183 23:59:24.982962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7184 23:59:24.986178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 23:59:24.992512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7186 23:59:24.996094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7187 23:59:24.999215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7188 23:59:25.002934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7189 23:59:25.006113 [ANA_INIT] flow start
7190 23:59:25.009445 [ANA_INIT] PLL >>>>>>>>
7191 23:59:25.009605 [ANA_INIT] PLL <<<<<<<<
7192 23:59:25.012762 [ANA_INIT] MIDPI >>>>>>>>
7193 23:59:25.016006 [ANA_INIT] MIDPI <<<<<<<<
7194 23:59:25.016143 [ANA_INIT] DLL >>>>>>>>
7195 23:59:25.019825 [ANA_INIT] DLL <<<<<<<<
7196 23:59:25.022633 [ANA_INIT] flow end
7197 23:59:25.026147 ============ LP4 DIFF to SE enter ============
7198 23:59:25.029644 ============ LP4 DIFF to SE exit ============
7199 23:59:25.032572 [ANA_INIT] <<<<<<<<<<<<<
7200 23:59:25.035948 [Flow] Enable top DCM control >>>>>
7201 23:59:25.039508 [Flow] Enable top DCM control <<<<<
7202 23:59:25.042860 Enable DLL master slave shuffle
7203 23:59:25.045886 ==============================================================
7204 23:59:25.049352 Gating Mode config
7205 23:59:25.055976 ==============================================================
7206 23:59:25.056115 Config description:
7207 23:59:25.065695 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7208 23:59:25.072485 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7209 23:59:25.075709 SELPH_MODE 0: By rank 1: By Phase
7210 23:59:25.082165 ==============================================================
7211 23:59:25.085430 GAT_TRACK_EN = 1
7212 23:59:25.089300 RX_GATING_MODE = 2
7213 23:59:25.092525 RX_GATING_TRACK_MODE = 2
7214 23:59:25.095732 SELPH_MODE = 1
7215 23:59:25.098939 PICG_EARLY_EN = 1
7216 23:59:25.102118 VALID_LAT_VALUE = 1
7217 23:59:25.105290 ==============================================================
7218 23:59:25.108921 Enter into Gating configuration >>>>
7219 23:59:25.112114 Exit from Gating configuration <<<<
7220 23:59:25.115380 Enter into DVFS_PRE_config >>>>>
7221 23:59:25.128945 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7222 23:59:25.129156 Exit from DVFS_PRE_config <<<<<
7223 23:59:25.131991 Enter into PICG configuration >>>>
7224 23:59:25.135183 Exit from PICG configuration <<<<
7225 23:59:25.138443 [RX_INPUT] configuration >>>>>
7226 23:59:25.141789 [RX_INPUT] configuration <<<<<
7227 23:59:25.148615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7228 23:59:25.151726 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7229 23:59:25.158413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7230 23:59:25.165451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7231 23:59:25.171803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 23:59:25.178248 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 23:59:25.181805 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7234 23:59:25.185378 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7235 23:59:25.188486 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7236 23:59:25.195171 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7237 23:59:25.198375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7238 23:59:25.201688 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7239 23:59:25.204948 ===================================
7240 23:59:25.208070 LPDDR4 DRAM CONFIGURATION
7241 23:59:25.211201 ===================================
7242 23:59:25.214635 EX_ROW_EN[0] = 0x0
7243 23:59:25.214730 EX_ROW_EN[1] = 0x0
7244 23:59:25.218034 LP4Y_EN = 0x0
7245 23:59:25.218121 WORK_FSP = 0x1
7246 23:59:25.221563 WL = 0x5
7247 23:59:25.221652 RL = 0x5
7248 23:59:25.224950 BL = 0x2
7249 23:59:25.225039 RPST = 0x0
7250 23:59:25.228109 RD_PRE = 0x0
7251 23:59:25.228196 WR_PRE = 0x1
7252 23:59:25.231375 WR_PST = 0x1
7253 23:59:25.231466 DBI_WR = 0x0
7254 23:59:25.234636 DBI_RD = 0x0
7255 23:59:25.234727 OTF = 0x1
7256 23:59:25.237767 ===================================
7257 23:59:25.244847 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7258 23:59:25.248112 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7259 23:59:25.251387 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7260 23:59:25.254464 ===================================
7261 23:59:25.257883 LPDDR4 DRAM CONFIGURATION
7262 23:59:25.261478 ===================================
7263 23:59:25.261574 EX_ROW_EN[0] = 0x10
7264 23:59:25.264670 EX_ROW_EN[1] = 0x0
7265 23:59:25.267908 LP4Y_EN = 0x0
7266 23:59:25.268030 WORK_FSP = 0x1
7267 23:59:25.271171 WL = 0x5
7268 23:59:25.271260 RL = 0x5
7269 23:59:25.274430 BL = 0x2
7270 23:59:25.274517 RPST = 0x0
7271 23:59:25.277718 RD_PRE = 0x0
7272 23:59:25.277835 WR_PRE = 0x1
7273 23:59:25.280969 WR_PST = 0x1
7274 23:59:25.281058 DBI_WR = 0x0
7275 23:59:25.284114 DBI_RD = 0x0
7276 23:59:25.284202 OTF = 0x1
7277 23:59:25.287674 ===================================
7278 23:59:25.294031 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7279 23:59:25.294202 ==
7280 23:59:25.297446 Dram Type= 6, Freq= 0, CH_0, rank 0
7281 23:59:25.301100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7282 23:59:25.303931 ==
7283 23:59:25.304051 [Duty_Offset_Calibration]
7284 23:59:25.307482 B0:2 B1:1 CA:1
7285 23:59:25.307600
7286 23:59:25.310691 [DutyScan_Calibration_Flow] k_type=0
7287 23:59:25.319647
7288 23:59:25.319781 ==CLK 0==
7289 23:59:25.323044 Final CLK duty delay cell = 0
7290 23:59:25.326743 [0] MAX Duty = 5187%(X100), DQS PI = 22
7291 23:59:25.330008 [0] MIN Duty = 4907%(X100), DQS PI = 0
7292 23:59:25.330109 [0] AVG Duty = 5047%(X100)
7293 23:59:25.330197
7294 23:59:25.333267 CH0 CLK Duty spec in!! Max-Min= 280%
7295 23:59:25.340081 [DutyScan_Calibration_Flow] ====Done====
7296 23:59:25.340223
7297 23:59:25.343380 [DutyScan_Calibration_Flow] k_type=1
7298 23:59:25.358856
7299 23:59:25.359038 ==DQS 0 ==
7300 23:59:25.362538 Final DQS duty delay cell = -4
7301 23:59:25.365649 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7302 23:59:25.369042 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7303 23:59:25.372123 [-4] AVG Duty = 4891%(X100)
7304 23:59:25.372217
7305 23:59:25.372286 ==DQS 1 ==
7306 23:59:25.375316 Final DQS duty delay cell = 0
7307 23:59:25.378619 [0] MAX Duty = 5187%(X100), DQS PI = 4
7308 23:59:25.381919 [0] MIN Duty = 5031%(X100), DQS PI = 52
7309 23:59:25.385175 [0] AVG Duty = 5109%(X100)
7310 23:59:25.385273
7311 23:59:25.388452 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7312 23:59:25.388543
7313 23:59:25.391828 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7314 23:59:25.395112 [DutyScan_Calibration_Flow] ====Done====
7315 23:59:25.395251
7316 23:59:25.398410 [DutyScan_Calibration_Flow] k_type=3
7317 23:59:25.415820
7318 23:59:25.415979 ==DQM 0 ==
7319 23:59:25.418883 Final DQM duty delay cell = 0
7320 23:59:25.422084 [0] MAX Duty = 5187%(X100), DQS PI = 26
7321 23:59:25.425169 [0] MIN Duty = 4875%(X100), DQS PI = 60
7322 23:59:25.428841 [0] AVG Duty = 5031%(X100)
7323 23:59:25.428989
7324 23:59:25.429114 ==DQM 1 ==
7325 23:59:25.432041 Final DQM duty delay cell = -4
7326 23:59:25.435634 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7327 23:59:25.438553 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7328 23:59:25.442237 [-4] AVG Duty = 4875%(X100)
7329 23:59:25.442386
7330 23:59:25.445541 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7331 23:59:25.445675
7332 23:59:25.448480 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7333 23:59:25.452056 [DutyScan_Calibration_Flow] ====Done====
7334 23:59:25.452183
7335 23:59:25.455260 [DutyScan_Calibration_Flow] k_type=2
7336 23:59:25.473095
7337 23:59:25.473304 ==DQ 0 ==
7338 23:59:25.476141 Final DQ duty delay cell = 0
7339 23:59:25.479556 [0] MAX Duty = 5062%(X100), DQS PI = 26
7340 23:59:25.482591 [0] MIN Duty = 4907%(X100), DQS PI = 0
7341 23:59:25.482751 [0] AVG Duty = 4984%(X100)
7342 23:59:25.485846
7343 23:59:25.485978 ==DQ 1 ==
7344 23:59:25.489755 Final DQ duty delay cell = 0
7345 23:59:25.493020 [0] MAX Duty = 5125%(X100), DQS PI = 6
7346 23:59:25.496270 [0] MIN Duty = 4907%(X100), DQS PI = 34
7347 23:59:25.496434 [0] AVG Duty = 5016%(X100)
7348 23:59:25.496556
7349 23:59:25.499572 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7350 23:59:25.502844
7351 23:59:25.506134 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7352 23:59:25.509424 [DutyScan_Calibration_Flow] ====Done====
7353 23:59:25.509562 ==
7354 23:59:25.512714 Dram Type= 6, Freq= 0, CH_1, rank 0
7355 23:59:25.515941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7356 23:59:25.516090 ==
7357 23:59:25.519150 [Duty_Offset_Calibration]
7358 23:59:25.519285 B0:1 B1:0 CA:0
7359 23:59:25.519417
7360 23:59:25.522471 [DutyScan_Calibration_Flow] k_type=0
7361 23:59:25.532184
7362 23:59:25.532396 ==CLK 0==
7363 23:59:25.535359 Final CLK duty delay cell = -4
7364 23:59:25.538843 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7365 23:59:25.542402 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7366 23:59:25.545270 [-4] AVG Duty = 4922%(X100)
7367 23:59:25.545406
7368 23:59:25.548961 CH1 CLK Duty spec in!! Max-Min= 156%
7369 23:59:25.552043 [DutyScan_Calibration_Flow] ====Done====
7370 23:59:25.552173
7371 23:59:25.555685 [DutyScan_Calibration_Flow] k_type=1
7372 23:59:25.572362
7373 23:59:25.572595 ==DQS 0 ==
7374 23:59:25.575886 Final DQS duty delay cell = 0
7375 23:59:25.578924 [0] MAX Duty = 5094%(X100), DQS PI = 32
7376 23:59:25.582548 [0] MIN Duty = 4844%(X100), DQS PI = 44
7377 23:59:25.582651 [0] AVG Duty = 4969%(X100)
7378 23:59:25.585610
7379 23:59:25.585697 ==DQS 1 ==
7380 23:59:25.589340 Final DQS duty delay cell = 0
7381 23:59:25.592591 [0] MAX Duty = 5249%(X100), DQS PI = 16
7382 23:59:25.595802 [0] MIN Duty = 4938%(X100), DQS PI = 8
7383 23:59:25.595894 [0] AVG Duty = 5093%(X100)
7384 23:59:25.599053
7385 23:59:25.602383 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7386 23:59:25.602473
7387 23:59:25.605631 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7388 23:59:25.609161 [DutyScan_Calibration_Flow] ====Done====
7389 23:59:25.609252
7390 23:59:25.612124 [DutyScan_Calibration_Flow] k_type=3
7391 23:59:25.629041
7392 23:59:25.629221 ==DQM 0 ==
7393 23:59:25.632924 Final DQM duty delay cell = 0
7394 23:59:25.636260 [0] MAX Duty = 5218%(X100), DQS PI = 16
7395 23:59:25.639110 [0] MIN Duty = 4969%(X100), DQS PI = 48
7396 23:59:25.642396 [0] AVG Duty = 5093%(X100)
7397 23:59:25.642491
7398 23:59:25.642557 ==DQM 1 ==
7399 23:59:25.645587 Final DQM duty delay cell = 0
7400 23:59:25.649369 [0] MAX Duty = 5093%(X100), DQS PI = 16
7401 23:59:25.652565 [0] MIN Duty = 4907%(X100), DQS PI = 34
7402 23:59:25.655985 [0] AVG Duty = 5000%(X100)
7403 23:59:25.656123
7404 23:59:25.659303 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7405 23:59:25.659433
7406 23:59:25.662531 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7407 23:59:25.665823 [DutyScan_Calibration_Flow] ====Done====
7408 23:59:25.665931
7409 23:59:25.676290 [DutyScan_Calibration_Flow] k_type=2
7410 23:59:25.685470
7411 23:59:25.685639 ==DQ 0 ==
7412 23:59:25.688885 Final DQ duty delay cell = -4
7413 23:59:25.691968 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7414 23:59:25.695386 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7415 23:59:25.698398 [-4] AVG Duty = 4968%(X100)
7416 23:59:25.698507
7417 23:59:25.698601 ==DQ 1 ==
7418 23:59:25.701816 Final DQ duty delay cell = 0
7419 23:59:25.705250 [0] MAX Duty = 5124%(X100), DQS PI = 16
7420 23:59:25.708770 [0] MIN Duty = 4938%(X100), DQS PI = 8
7421 23:59:25.711837 [0] AVG Duty = 5031%(X100)
7422 23:59:25.711927
7423 23:59:25.715486 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7424 23:59:25.715573
7425 23:59:25.718691 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7426 23:59:25.721857 [DutyScan_Calibration_Flow] ====Done====
7427 23:59:25.724947 nWR fixed to 30
7428 23:59:25.728858 [ModeRegInit_LP4] CH0 RK0
7429 23:59:25.728952 [ModeRegInit_LP4] CH0 RK1
7430 23:59:25.732119 [ModeRegInit_LP4] CH1 RK0
7431 23:59:25.735413 [ModeRegInit_LP4] CH1 RK1
7432 23:59:25.735500 match AC timing 5
7433 23:59:25.742023 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7434 23:59:25.745030 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7435 23:59:25.748210 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7436 23:59:25.755368 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7437 23:59:25.758528 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7438 23:59:25.758619 [MiockJmeterHQA]
7439 23:59:25.758685
7440 23:59:25.761648 [DramcMiockJmeter] u1RxGatingPI = 0
7441 23:59:25.765341 0 : 4363, 4138
7442 23:59:25.765427 4 : 4253, 4026
7443 23:59:25.768486 8 : 4364, 4137
7444 23:59:25.768576 12 : 4252, 4027
7445 23:59:25.768646 16 : 4253, 4026
7446 23:59:25.771757 20 : 4366, 4140
7447 23:59:25.771844 24 : 4363, 4137
7448 23:59:25.775046 28 : 4252, 4027
7449 23:59:25.775132 32 : 4252, 4027
7450 23:59:25.778331 36 : 4253, 4027
7451 23:59:25.778419 40 : 4363, 4138
7452 23:59:25.781507 44 : 4252, 4027
7453 23:59:25.781612 48 : 4363, 4138
7454 23:59:25.781682 52 : 4252, 4027
7455 23:59:25.784732 56 : 4250, 4027
7456 23:59:25.784820 60 : 4253, 4029
7457 23:59:25.788583 64 : 4252, 4029
7458 23:59:25.788672 68 : 4360, 4138
7459 23:59:25.791829 72 : 4249, 4027
7460 23:59:25.791935 76 : 4361, 4137
7461 23:59:25.792005 80 : 4250, 4027
7462 23:59:25.795302 84 : 4250, 4027
7463 23:59:25.795410 88 : 4250, 47
7464 23:59:25.798349 92 : 4253, 0
7465 23:59:25.798454 96 : 4252, 0
7466 23:59:25.798522 100 : 4252, 0
7467 23:59:25.801547 104 : 4250, 0
7468 23:59:25.801638 108 : 4249, 0
7469 23:59:25.805176 112 : 4249, 0
7470 23:59:25.805272 116 : 4361, 0
7471 23:59:25.805340 120 : 4360, 0
7472 23:59:25.808237 124 : 4249, 0
7473 23:59:25.808376 128 : 4250, 0
7474 23:59:25.811661 132 : 4250, 0
7475 23:59:25.811777 136 : 4363, 0
7476 23:59:25.811875 140 : 4250, 0
7477 23:59:25.814725 144 : 4250, 0
7478 23:59:25.814813 148 : 4252, 0
7479 23:59:25.818441 152 : 4250, 0
7480 23:59:25.818530 156 : 4250, 0
7481 23:59:25.818598 160 : 4252, 0
7482 23:59:25.821428 164 : 4250, 0
7483 23:59:25.821516 168 : 4361, 0
7484 23:59:25.821582 172 : 4360, 0
7485 23:59:25.824858 176 : 4249, 0
7486 23:59:25.824946 180 : 4250, 0
7487 23:59:25.828276 184 : 4250, 0
7488 23:59:25.828419 188 : 4252, 0
7489 23:59:25.828510 192 : 4250, 0
7490 23:59:25.831357 196 : 4250, 0
7491 23:59:25.831445 200 : 4250, 0
7492 23:59:25.834800 204 : 4360, 1344
7493 23:59:25.834894 208 : 4250, 3947
7494 23:59:25.838037 212 : 4361, 4137
7495 23:59:25.838148 216 : 4250, 4026
7496 23:59:25.838218 220 : 4250, 4027
7497 23:59:25.841471 224 : 4249, 4027
7498 23:59:25.841560 228 : 4252, 4029
7499 23:59:25.845130 232 : 4250, 4026
7500 23:59:25.845224 236 : 4250, 4027
7501 23:59:25.847747 240 : 4250, 4027
7502 23:59:25.847839 244 : 4252, 4029
7503 23:59:25.851619 248 : 4250, 4026
7504 23:59:25.851712 252 : 4361, 4137
7505 23:59:25.854675 256 : 4360, 4138
7506 23:59:25.854795 260 : 4250, 4027
7507 23:59:25.858058 264 : 4363, 4140
7508 23:59:25.858151 268 : 4360, 4138
7509 23:59:25.861311 272 : 4250, 4027
7510 23:59:25.861400 276 : 4250, 4027
7511 23:59:25.865107 280 : 4252, 4029
7512 23:59:25.865198 284 : 4250, 4026
7513 23:59:25.865268 288 : 4250, 4027
7514 23:59:25.868593 292 : 4250, 4027
7515 23:59:25.868688 296 : 4249, 4027
7516 23:59:25.871432 300 : 4250, 4026
7517 23:59:25.871525 304 : 4361, 4137
7518 23:59:25.874372 308 : 4360, 4070
7519 23:59:25.874487 312 : 4250, 2135
7520 23:59:25.878240 316 : 4363, 6
7521 23:59:25.878354
7522 23:59:25.878451 MIOCK jitter meter ch=0
7523 23:59:25.878543
7524 23:59:25.881512 1T = (316-88) = 228 dly cells
7525 23:59:25.887807 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7526 23:59:25.887925 ==
7527 23:59:25.890935 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 23:59:25.894334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 23:59:25.894434 ==
7530 23:59:25.901420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7531 23:59:25.904819 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7532 23:59:25.907664 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7533 23:59:25.914011 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7534 23:59:25.924402 [CA 0] Center 42 (12~73) winsize 62
7535 23:59:25.927629 [CA 1] Center 42 (12~73) winsize 62
7536 23:59:25.930748 [CA 2] Center 37 (8~67) winsize 60
7537 23:59:25.933866 [CA 3] Center 37 (7~67) winsize 61
7538 23:59:25.937785 [CA 4] Center 36 (6~66) winsize 61
7539 23:59:25.940832 [CA 5] Center 35 (6~64) winsize 59
7540 23:59:25.940954
7541 23:59:25.944032 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7542 23:59:25.944126
7543 23:59:25.947150 [CATrainingPosCal] consider 1 rank data
7544 23:59:25.950745 u2DelayCellTimex100 = 285/100 ps
7545 23:59:25.953711 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7546 23:59:25.960521 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7547 23:59:25.964182 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7548 23:59:25.967151 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7549 23:59:25.970639 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7550 23:59:25.974031 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7551 23:59:25.974143
7552 23:59:25.977130 CA PerBit enable=1, Macro0, CA PI delay=35
7553 23:59:25.977229
7554 23:59:25.980935 [CBTSetCACLKResult] CA Dly = 35
7555 23:59:25.983900 CS Dly: 9 (0~40)
7556 23:59:25.987046 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7557 23:59:25.990938 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7558 23:59:25.991047 ==
7559 23:59:25.994129 Dram Type= 6, Freq= 0, CH_0, rank 1
7560 23:59:25.997409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 23:59:25.997512 ==
7562 23:59:26.003628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7563 23:59:26.007049 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7564 23:59:26.013997 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7565 23:59:26.017358 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7566 23:59:26.027631 [CA 0] Center 42 (12~73) winsize 62
7567 23:59:26.030870 [CA 1] Center 42 (12~73) winsize 62
7568 23:59:26.033941 [CA 2] Center 38 (8~68) winsize 61
7569 23:59:26.037654 [CA 3] Center 37 (8~67) winsize 60
7570 23:59:26.040811 [CA 4] Center 36 (6~66) winsize 61
7571 23:59:26.044106 [CA 5] Center 34 (5~64) winsize 60
7572 23:59:26.044233
7573 23:59:26.047294 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7574 23:59:26.047383
7575 23:59:26.050613 [CATrainingPosCal] consider 2 rank data
7576 23:59:26.053882 u2DelayCellTimex100 = 285/100 ps
7577 23:59:26.057143 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7578 23:59:26.064143 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7579 23:59:26.067350 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7580 23:59:26.070564 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7581 23:59:26.073755 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7582 23:59:26.077384 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7583 23:59:26.077601
7584 23:59:26.080782 CA PerBit enable=1, Macro0, CA PI delay=35
7585 23:59:26.080961
7586 23:59:26.083622 [CBTSetCACLKResult] CA Dly = 35
7587 23:59:26.087561 CS Dly: 10 (0~42)
7588 23:59:26.090482 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7589 23:59:26.093853 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7590 23:59:26.094052
7591 23:59:26.097000 ----->DramcWriteLeveling(PI) begin...
7592 23:59:26.097171 ==
7593 23:59:26.100741 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 23:59:26.106899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 23:59:26.107047 ==
7596 23:59:26.110434 Write leveling (Byte 0): 35 => 35
7597 23:59:26.110575 Write leveling (Byte 1): 28 => 28
7598 23:59:26.113777 DramcWriteLeveling(PI) end<-----
7599 23:59:26.113887
7600 23:59:26.113981 ==
7601 23:59:26.117277 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 23:59:26.123635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 23:59:26.123753 ==
7604 23:59:26.126966 [Gating] SW mode calibration
7605 23:59:26.133931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7606 23:59:26.137068 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7607 23:59:26.143517 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7608 23:59:26.146682 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7609 23:59:26.149892 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7610 23:59:26.156909 1 4 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (1 1)
7611 23:59:26.159840 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7612 23:59:26.163712 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7613 23:59:26.170313 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7614 23:59:26.173463 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7615 23:59:26.176712 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 23:59:26.180031 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7617 23:59:26.186441 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7618 23:59:26.190341 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7619 23:59:26.193802 1 5 16 | B1->B0 | 3434 2726 | 1 1 | (1 0) (0 0)
7620 23:59:26.199684 1 5 20 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
7621 23:59:26.203609 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7622 23:59:26.206822 1 5 28 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7623 23:59:26.213583 1 6 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7624 23:59:26.216278 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7625 23:59:26.219610 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7626 23:59:26.226575 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7627 23:59:26.229782 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7628 23:59:26.232833 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7629 23:59:26.240083 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 23:59:26.242976 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 23:59:26.246410 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 23:59:26.252821 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 23:59:26.256010 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 23:59:26.259822 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 23:59:26.266107 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 23:59:26.269434 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 23:59:26.273283 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:59:26.279673 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:59:26.282877 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:59:26.286931 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:59:26.293279 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:59:26.296365 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:59:26.299837 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:59:26.306366 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:59:26.309269 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:59:26.313197 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:59:26.316331 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:59:26.323072 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:59:26.326226 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:59:26.329338 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 23:59:26.335996 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7652 23:59:26.339879 Total UI for P1: 0, mck2ui 16
7653 23:59:26.342978 best dqsien dly found for B0: ( 1, 9, 12)
7654 23:59:26.346096 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 23:59:26.349683 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 23:59:26.352875 Total UI for P1: 0, mck2ui 16
7657 23:59:26.356452 best dqsien dly found for B1: ( 1, 9, 20)
7658 23:59:26.359464 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7659 23:59:26.362802 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7660 23:59:26.362928
7661 23:59:26.370119 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7662 23:59:26.372925 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7663 23:59:26.376034 [Gating] SW calibration Done
7664 23:59:26.376160 ==
7665 23:59:26.380019 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 23:59:26.383137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 23:59:26.383245 ==
7668 23:59:26.383317 RX Vref Scan: 0
7669 23:59:26.383381
7670 23:59:26.386147 RX Vref 0 -> 0, step: 1
7671 23:59:26.386221
7672 23:59:26.389498 RX Delay 0 -> 252, step: 8
7673 23:59:26.392688 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7674 23:59:26.395941 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7675 23:59:26.402373 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7676 23:59:26.405619 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7677 23:59:26.409488 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7678 23:59:26.412504 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7679 23:59:26.415481 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7680 23:59:26.422611 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7681 23:59:26.425742 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7682 23:59:26.429242 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7683 23:59:26.432198 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7684 23:59:26.435336 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7685 23:59:26.442082 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7686 23:59:26.445405 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7687 23:59:26.448649 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7688 23:59:26.452570 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7689 23:59:26.452697 ==
7690 23:59:26.455728 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 23:59:26.462006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 23:59:26.462165 ==
7693 23:59:26.462279 DQS Delay:
7694 23:59:26.462373 DQS0 = 0, DQS1 = 0
7695 23:59:26.465767 DQM Delay:
7696 23:59:26.465882 DQM0 = 136, DQM1 = 129
7697 23:59:26.468987 DQ Delay:
7698 23:59:26.472209 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7699 23:59:26.475507 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7700 23:59:26.478872 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
7701 23:59:26.481877 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7702 23:59:26.482013
7703 23:59:26.482141
7704 23:59:26.482263 ==
7705 23:59:26.485587 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 23:59:26.489127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 23:59:26.489263 ==
7708 23:59:26.492091
7709 23:59:26.492223
7710 23:59:26.492316 TX Vref Scan disable
7711 23:59:26.495870 == TX Byte 0 ==
7712 23:59:26.498618 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7713 23:59:26.502464 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7714 23:59:26.505844 == TX Byte 1 ==
7715 23:59:26.509159 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7716 23:59:26.512315 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7717 23:59:26.512456 ==
7718 23:59:26.515638 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 23:59:26.522023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 23:59:26.522133 ==
7721 23:59:26.534422
7722 23:59:26.537752 TX Vref early break, caculate TX vref
7723 23:59:26.540984 TX Vref=16, minBit 0, minWin=23, winSum=382
7724 23:59:26.544714 TX Vref=18, minBit 0, minWin=22, winSum=385
7725 23:59:26.547864 TX Vref=20, minBit 0, minWin=23, winSum=400
7726 23:59:26.551088 TX Vref=22, minBit 0, minWin=25, winSum=411
7727 23:59:26.554304 TX Vref=24, minBit 0, minWin=24, winSum=413
7728 23:59:26.561463 TX Vref=26, minBit 6, minWin=25, winSum=428
7729 23:59:26.564158 TX Vref=28, minBit 6, minWin=25, winSum=428
7730 23:59:26.567859 TX Vref=30, minBit 1, minWin=24, winSum=413
7731 23:59:26.570913 TX Vref=32, minBit 1, minWin=24, winSum=408
7732 23:59:26.574224 TX Vref=34, minBit 2, minWin=23, winSum=395
7733 23:59:26.581119 [TxChooseVref] Worse bit 6, Min win 25, Win sum 428, Final Vref 26
7734 23:59:26.581235
7735 23:59:26.584174 Final TX Range 0 Vref 26
7736 23:59:26.584291
7737 23:59:26.584382 ==
7738 23:59:26.587826 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 23:59:26.591091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 23:59:26.591186 ==
7741 23:59:26.591256
7742 23:59:26.591320
7743 23:59:26.594303 TX Vref Scan disable
7744 23:59:26.600924 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7745 23:59:26.601046 == TX Byte 0 ==
7746 23:59:26.604090 u2DelayCellOfst[0]=10 cells (3 PI)
7747 23:59:26.607551 u2DelayCellOfst[1]=13 cells (4 PI)
7748 23:59:26.610487 u2DelayCellOfst[2]=10 cells (3 PI)
7749 23:59:26.613986 u2DelayCellOfst[3]=10 cells (3 PI)
7750 23:59:26.617381 u2DelayCellOfst[4]=6 cells (2 PI)
7751 23:59:26.620261 u2DelayCellOfst[5]=0 cells (0 PI)
7752 23:59:26.624166 u2DelayCellOfst[6]=17 cells (5 PI)
7753 23:59:26.627663 u2DelayCellOfst[7]=17 cells (5 PI)
7754 23:59:26.630552 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7755 23:59:26.634146 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7756 23:59:26.637320 == TX Byte 1 ==
7757 23:59:26.637421 u2DelayCellOfst[8]=0 cells (0 PI)
7758 23:59:26.640447 u2DelayCellOfst[9]=0 cells (0 PI)
7759 23:59:26.643687 u2DelayCellOfst[10]=10 cells (3 PI)
7760 23:59:26.647507 u2DelayCellOfst[11]=6 cells (2 PI)
7761 23:59:26.650619 u2DelayCellOfst[12]=10 cells (3 PI)
7762 23:59:26.653830 u2DelayCellOfst[13]=13 cells (4 PI)
7763 23:59:26.657045 u2DelayCellOfst[14]=13 cells (4 PI)
7764 23:59:26.660848 u2DelayCellOfst[15]=10 cells (3 PI)
7765 23:59:26.664162 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7766 23:59:26.670581 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7767 23:59:26.670707 DramC Write-DBI on
7768 23:59:26.670778 ==
7769 23:59:26.673798 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 23:59:26.677474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 23:59:26.680482 ==
7772 23:59:26.680592
7773 23:59:26.680662
7774 23:59:26.680726 TX Vref Scan disable
7775 23:59:26.683783 == TX Byte 0 ==
7776 23:59:26.687687 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7777 23:59:26.690736 == TX Byte 1 ==
7778 23:59:26.693644 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7779 23:59:26.697512 DramC Write-DBI off
7780 23:59:26.697617
7781 23:59:26.697689 [DATLAT]
7782 23:59:26.697753 Freq=1600, CH0 RK0
7783 23:59:26.697815
7784 23:59:26.700534 DATLAT Default: 0xf
7785 23:59:26.700651 0, 0xFFFF, sum = 0
7786 23:59:26.703491 1, 0xFFFF, sum = 0
7787 23:59:26.707440 2, 0xFFFF, sum = 0
7788 23:59:26.707540 3, 0xFFFF, sum = 0
7789 23:59:26.710621 4, 0xFFFF, sum = 0
7790 23:59:26.710715 5, 0xFFFF, sum = 0
7791 23:59:26.714004 6, 0xFFFF, sum = 0
7792 23:59:26.714096 7, 0xFFFF, sum = 0
7793 23:59:26.716811 8, 0xFFFF, sum = 0
7794 23:59:26.716902 9, 0xFFFF, sum = 0
7795 23:59:26.720478 10, 0xFFFF, sum = 0
7796 23:59:26.720572 11, 0xFFFF, sum = 0
7797 23:59:26.723556 12, 0xFFFF, sum = 0
7798 23:59:26.723648 13, 0xFFFF, sum = 0
7799 23:59:26.727163 14, 0x0, sum = 1
7800 23:59:26.727254 15, 0x0, sum = 2
7801 23:59:26.730628 16, 0x0, sum = 3
7802 23:59:26.730720 17, 0x0, sum = 4
7803 23:59:26.733675 best_step = 15
7804 23:59:26.733768
7805 23:59:26.733836 ==
7806 23:59:26.736841 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 23:59:26.740851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 23:59:26.740946 ==
7809 23:59:26.743753 RX Vref Scan: 1
7810 23:59:26.743841
7811 23:59:26.743932 Set Vref Range= 24 -> 127
7812 23:59:26.743998
7813 23:59:26.746684 RX Vref 24 -> 127, step: 1
7814 23:59:26.746771
7815 23:59:26.750426 RX Delay 19 -> 252, step: 4
7816 23:59:26.750516
7817 23:59:26.753851 Set Vref, RX VrefLevel [Byte0]: 24
7818 23:59:26.756677 [Byte1]: 24
7819 23:59:26.756768
7820 23:59:26.760260 Set Vref, RX VrefLevel [Byte0]: 25
7821 23:59:26.763515 [Byte1]: 25
7822 23:59:26.763606
7823 23:59:26.766752 Set Vref, RX VrefLevel [Byte0]: 26
7824 23:59:26.770018 [Byte1]: 26
7825 23:59:26.774419
7826 23:59:26.774519 Set Vref, RX VrefLevel [Byte0]: 27
7827 23:59:26.777830 [Byte1]: 27
7828 23:59:26.781490
7829 23:59:26.781583 Set Vref, RX VrefLevel [Byte0]: 28
7830 23:59:26.785163 [Byte1]: 28
7831 23:59:26.789668
7832 23:59:26.789767 Set Vref, RX VrefLevel [Byte0]: 29
7833 23:59:26.792982 [Byte1]: 29
7834 23:59:26.796852
7835 23:59:26.796957 Set Vref, RX VrefLevel [Byte0]: 30
7836 23:59:26.800045 [Byte1]: 30
7837 23:59:26.804804
7838 23:59:26.804914 Set Vref, RX VrefLevel [Byte0]: 31
7839 23:59:26.807653 [Byte1]: 31
7840 23:59:26.812014
7841 23:59:26.812114 Set Vref, RX VrefLevel [Byte0]: 32
7842 23:59:26.815270 [Byte1]: 32
7843 23:59:26.819710
7844 23:59:26.819827 Set Vref, RX VrefLevel [Byte0]: 33
7845 23:59:26.822929 [Byte1]: 33
7846 23:59:26.827385
7847 23:59:26.827487 Set Vref, RX VrefLevel [Byte0]: 34
7848 23:59:26.830540 [Byte1]: 34
7849 23:59:26.834940
7850 23:59:26.835041 Set Vref, RX VrefLevel [Byte0]: 35
7851 23:59:26.837966 [Byte1]: 35
7852 23:59:26.842157
7853 23:59:26.842259 Set Vref, RX VrefLevel [Byte0]: 36
7854 23:59:26.845461 [Byte1]: 36
7855 23:59:26.849842
7856 23:59:26.849943 Set Vref, RX VrefLevel [Byte0]: 37
7857 23:59:26.853486 [Byte1]: 37
7858 23:59:26.857531
7859 23:59:26.857630 Set Vref, RX VrefLevel [Byte0]: 38
7860 23:59:26.863789 [Byte1]: 38
7861 23:59:26.863908
7862 23:59:26.867564 Set Vref, RX VrefLevel [Byte0]: 39
7863 23:59:26.870624 [Byte1]: 39
7864 23:59:26.870728
7865 23:59:26.873887 Set Vref, RX VrefLevel [Byte0]: 40
7866 23:59:26.877268 [Byte1]: 40
7867 23:59:26.877369
7868 23:59:26.880603 Set Vref, RX VrefLevel [Byte0]: 41
7869 23:59:26.883824 [Byte1]: 41
7870 23:59:26.887710
7871 23:59:26.887811 Set Vref, RX VrefLevel [Byte0]: 42
7872 23:59:26.891414 [Byte1]: 42
7873 23:59:26.895386
7874 23:59:26.895487 Set Vref, RX VrefLevel [Byte0]: 43
7875 23:59:26.898430 [Byte1]: 43
7876 23:59:26.903045
7877 23:59:26.903147 Set Vref, RX VrefLevel [Byte0]: 44
7878 23:59:26.906346 [Byte1]: 44
7879 23:59:26.910698
7880 23:59:26.910800 Set Vref, RX VrefLevel [Byte0]: 45
7881 23:59:26.913607 [Byte1]: 45
7882 23:59:26.918011
7883 23:59:26.918119 Set Vref, RX VrefLevel [Byte0]: 46
7884 23:59:26.921227 [Byte1]: 46
7885 23:59:26.925668
7886 23:59:26.925811 Set Vref, RX VrefLevel [Byte0]: 47
7887 23:59:26.928928 [Byte1]: 47
7888 23:59:26.933324
7889 23:59:26.933423 Set Vref, RX VrefLevel [Byte0]: 48
7890 23:59:26.936510 [Byte1]: 48
7891 23:59:26.941082
7892 23:59:26.941192 Set Vref, RX VrefLevel [Byte0]: 49
7893 23:59:26.944284 [Byte1]: 49
7894 23:59:26.948746
7895 23:59:26.948860 Set Vref, RX VrefLevel [Byte0]: 50
7896 23:59:26.951683 [Byte1]: 50
7897 23:59:26.955795
7898 23:59:26.955931 Set Vref, RX VrefLevel [Byte0]: 51
7899 23:59:26.962313 [Byte1]: 51
7900 23:59:26.962491
7901 23:59:26.965582 Set Vref, RX VrefLevel [Byte0]: 52
7902 23:59:26.969273 [Byte1]: 52
7903 23:59:26.969389
7904 23:59:26.972501 Set Vref, RX VrefLevel [Byte0]: 53
7905 23:59:26.975491 [Byte1]: 53
7906 23:59:26.975612
7907 23:59:26.978955 Set Vref, RX VrefLevel [Byte0]: 54
7908 23:59:26.982291 [Byte1]: 54
7909 23:59:26.986184
7910 23:59:26.986281 Set Vref, RX VrefLevel [Byte0]: 55
7911 23:59:26.989653 [Byte1]: 55
7912 23:59:26.993797
7913 23:59:26.993893 Set Vref, RX VrefLevel [Byte0]: 56
7914 23:59:26.997338 [Byte1]: 56
7915 23:59:27.001350
7916 23:59:27.001442 Set Vref, RX VrefLevel [Byte0]: 57
7917 23:59:27.004648 [Byte1]: 57
7918 23:59:27.009134
7919 23:59:27.009226 Set Vref, RX VrefLevel [Byte0]: 58
7920 23:59:27.012246 [Byte1]: 58
7921 23:59:27.016294
7922 23:59:27.016396 Set Vref, RX VrefLevel [Byte0]: 59
7923 23:59:27.020179 [Byte1]: 59
7924 23:59:27.024185
7925 23:59:27.024269 Set Vref, RX VrefLevel [Byte0]: 60
7926 23:59:27.027668 [Byte1]: 60
7927 23:59:27.032009
7928 23:59:27.032102 Set Vref, RX VrefLevel [Byte0]: 61
7929 23:59:27.035340 [Byte1]: 61
7930 23:59:27.039724
7931 23:59:27.039823 Set Vref, RX VrefLevel [Byte0]: 62
7932 23:59:27.043019 [Byte1]: 62
7933 23:59:27.046974
7934 23:59:27.047065 Set Vref, RX VrefLevel [Byte0]: 63
7935 23:59:27.050215 [Byte1]: 63
7936 23:59:27.054607
7937 23:59:27.054699 Set Vref, RX VrefLevel [Byte0]: 64
7938 23:59:27.057755 [Byte1]: 64
7939 23:59:27.062103
7940 23:59:27.062214 Set Vref, RX VrefLevel [Byte0]: 65
7941 23:59:27.065089 [Byte1]: 65
7942 23:59:27.069422
7943 23:59:27.069525 Set Vref, RX VrefLevel [Byte0]: 66
7944 23:59:27.072764 [Byte1]: 66
7945 23:59:27.077309
7946 23:59:27.077408 Set Vref, RX VrefLevel [Byte0]: 67
7947 23:59:27.080255 [Byte1]: 67
7948 23:59:27.084932
7949 23:59:27.085089 Set Vref, RX VrefLevel [Byte0]: 68
7950 23:59:27.088175 [Byte1]: 68
7951 23:59:27.092291
7952 23:59:27.092440 Set Vref, RX VrefLevel [Byte0]: 69
7953 23:59:27.095506 [Byte1]: 69
7954 23:59:27.099916
7955 23:59:27.100069 Set Vref, RX VrefLevel [Byte0]: 70
7956 23:59:27.103223 [Byte1]: 70
7957 23:59:27.107529
7958 23:59:27.107683 Set Vref, RX VrefLevel [Byte0]: 71
7959 23:59:27.110855 [Byte1]: 71
7960 23:59:27.115171
7961 23:59:27.115326 Set Vref, RX VrefLevel [Byte0]: 72
7962 23:59:27.118328 [Byte1]: 72
7963 23:59:27.122665
7964 23:59:27.122816 Set Vref, RX VrefLevel [Byte0]: 73
7965 23:59:27.125980 [Byte1]: 73
7966 23:59:27.130437
7967 23:59:27.130586 Set Vref, RX VrefLevel [Byte0]: 74
7968 23:59:27.133607 [Byte1]: 74
7969 23:59:27.137902
7970 23:59:27.138051 Set Vref, RX VrefLevel [Byte0]: 75
7971 23:59:27.140936 [Byte1]: 75
7972 23:59:27.145061
7973 23:59:27.145204 Final RX Vref Byte 0 = 60 to rank0
7974 23:59:27.148477 Final RX Vref Byte 1 = 58 to rank0
7975 23:59:27.152193 Final RX Vref Byte 0 = 60 to rank1
7976 23:59:27.155600 Final RX Vref Byte 1 = 58 to rank1==
7977 23:59:27.158996 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 23:59:27.165142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 23:59:27.165281 ==
7980 23:59:27.165381 DQS Delay:
7981 23:59:27.165475 DQS0 = 0, DQS1 = 0
7982 23:59:27.168292 DQM Delay:
7983 23:59:27.168405 DQM0 = 134, DQM1 = 127
7984 23:59:27.171977 DQ Delay:
7985 23:59:27.175009 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7986 23:59:27.178878 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7987 23:59:27.182115 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7988 23:59:27.185299 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7989 23:59:27.185401
7990 23:59:27.185470
7991 23:59:27.185534
7992 23:59:27.188454 [DramC_TX_OE_Calibration] TA2
7993 23:59:27.191928 Original DQ_B0 (3 6) =30, OEN = 27
7994 23:59:27.195000 Original DQ_B1 (3 6) =30, OEN = 27
7995 23:59:27.198977 24, 0x0, End_B0=24 End_B1=24
7996 23:59:27.199075 25, 0x0, End_B0=25 End_B1=25
7997 23:59:27.202170 26, 0x0, End_B0=26 End_B1=26
7998 23:59:27.205012 27, 0x0, End_B0=27 End_B1=27
7999 23:59:27.208440 28, 0x0, End_B0=28 End_B1=28
8000 23:59:27.208531 29, 0x0, End_B0=29 End_B1=29
8001 23:59:27.211685 30, 0x0, End_B0=30 End_B1=30
8002 23:59:27.215013 31, 0x4141, End_B0=30 End_B1=30
8003 23:59:27.218399 Byte0 end_step=30 best_step=27
8004 23:59:27.221769 Byte1 end_step=30 best_step=27
8005 23:59:27.224721 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 23:59:27.228709 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 23:59:27.228807
8008 23:59:27.228878
8009 23:59:27.234979 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8010 23:59:27.238184 CH0 RK0: MR19=303, MR18=2622
8011 23:59:27.245146 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
8012 23:59:27.245266
8013 23:59:27.248275 ----->DramcWriteLeveling(PI) begin...
8014 23:59:27.248407 ==
8015 23:59:27.251297 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 23:59:27.254794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 23:59:27.254889 ==
8018 23:59:27.258457 Write leveling (Byte 0): 34 => 34
8019 23:59:27.261639 Write leveling (Byte 1): 27 => 27
8020 23:59:27.264887 DramcWriteLeveling(PI) end<-----
8021 23:59:27.264983
8022 23:59:27.265054 ==
8023 23:59:27.268151 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:59:27.271466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 23:59:27.271586 ==
8026 23:59:27.274785 [Gating] SW mode calibration
8027 23:59:27.281330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 23:59:27.288216 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 23:59:27.291504 1 4 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8030 23:59:27.294882 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8031 23:59:27.301198 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8032 23:59:27.304422 1 4 12 | B1->B0 | 2323 909 | 0 1 | (0 0) (0 0)
8033 23:59:27.308308 1 4 16 | B1->B0 | 3030 3737 | 0 0 | (0 0) (1 1)
8034 23:59:27.314856 1 4 20 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
8035 23:59:27.318012 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8036 23:59:27.321630 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8037 23:59:27.327813 1 5 0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8038 23:59:27.331224 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8039 23:59:27.334565 1 5 8 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
8040 23:59:27.341211 1 5 12 | B1->B0 | 3434 3736 | 1 1 | (1 0) (0 1)
8041 23:59:27.344754 1 5 16 | B1->B0 | 2e2e 2d2d | 0 1 | (0 0) (0 0)
8042 23:59:27.348028 1 5 20 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
8043 23:59:27.354305 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8044 23:59:27.357944 1 5 28 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8045 23:59:27.360858 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8046 23:59:27.367514 1 6 4 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
8047 23:59:27.371430 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8048 23:59:27.374635 1 6 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
8049 23:59:27.381156 1 6 16 | B1->B0 | 3d3d 4545 | 0 1 | (0 0) (1 1)
8050 23:59:27.384363 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8051 23:59:27.387939 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8052 23:59:27.394182 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8053 23:59:27.398112 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8054 23:59:27.401199 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 23:59:27.404420 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 23:59:27.411001 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8057 23:59:27.414136 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8058 23:59:27.417380 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:59:27.424663 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:59:27.427709 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:59:27.430836 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:59:27.437405 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:59:27.440974 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:59:27.444168 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 23:59:27.451206 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:59:27.453936 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 23:59:27.457631 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:59:27.464028 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:59:27.467179 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:59:27.470690 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:59:27.477109 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:59:27.480832 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8073 23:59:27.484121 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8074 23:59:27.490303 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 23:59:27.490481 Total UI for P1: 0, mck2ui 16
8076 23:59:27.496955 best dqsien dly found for B0: ( 1, 9, 14)
8077 23:59:27.497111 Total UI for P1: 0, mck2ui 16
8078 23:59:27.503649 best dqsien dly found for B1: ( 1, 9, 14)
8079 23:59:27.506929 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8080 23:59:27.510226 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8081 23:59:27.510355
8082 23:59:27.513528 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8083 23:59:27.516822 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8084 23:59:27.520639 [Gating] SW calibration Done
8085 23:59:27.520766 ==
8086 23:59:27.523994 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 23:59:27.527209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 23:59:27.527332 ==
8089 23:59:27.530479 RX Vref Scan: 0
8090 23:59:27.530600
8091 23:59:27.530703 RX Vref 0 -> 0, step: 1
8092 23:59:27.530796
8093 23:59:27.533723 RX Delay 0 -> 252, step: 8
8094 23:59:27.536881 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8095 23:59:27.543803 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8096 23:59:27.546874 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8097 23:59:27.550372 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8098 23:59:27.553538 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8099 23:59:27.556652 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8100 23:59:27.563495 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8101 23:59:27.566679 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8102 23:59:27.570446 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8103 23:59:27.573315 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8104 23:59:27.576849 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8105 23:59:27.583270 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8106 23:59:27.586702 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8107 23:59:27.590007 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8108 23:59:27.593104 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8109 23:59:27.600133 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8110 23:59:27.600295 ==
8111 23:59:27.603166 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 23:59:27.606680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 23:59:27.606805 ==
8114 23:59:27.606907 DQS Delay:
8115 23:59:27.609762 DQS0 = 0, DQS1 = 0
8116 23:59:27.609878 DQM Delay:
8117 23:59:27.613369 DQM0 = 136, DQM1 = 128
8118 23:59:27.613489 DQ Delay:
8119 23:59:27.616507 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8120 23:59:27.619759 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8121 23:59:27.623071 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8122 23:59:27.626381 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8123 23:59:27.626511
8124 23:59:27.626610
8125 23:59:27.629605 ==
8126 23:59:27.629725 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 23:59:27.636174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 23:59:27.636317 ==
8129 23:59:27.636430
8130 23:59:27.636537
8131 23:59:27.639340 TX Vref Scan disable
8132 23:59:27.639460 == TX Byte 0 ==
8133 23:59:27.643131 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8134 23:59:27.649509 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8135 23:59:27.649652 == TX Byte 1 ==
8136 23:59:27.652688 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8137 23:59:27.659352 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8138 23:59:27.659496 ==
8139 23:59:27.663028 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 23:59:27.666150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 23:59:27.666293 ==
8142 23:59:27.680431
8143 23:59:27.683296 TX Vref early break, caculate TX vref
8144 23:59:27.686534 TX Vref=16, minBit 1, minWin=22, winSum=389
8145 23:59:27.690283 TX Vref=18, minBit 3, minWin=23, winSum=395
8146 23:59:27.693400 TX Vref=20, minBit 1, minWin=23, winSum=406
8147 23:59:27.696963 TX Vref=22, minBit 1, minWin=24, winSum=412
8148 23:59:27.700324 TX Vref=24, minBit 1, minWin=25, winSum=423
8149 23:59:27.703429 TX Vref=26, minBit 1, minWin=25, winSum=429
8150 23:59:27.710451 TX Vref=28, minBit 6, minWin=25, winSum=426
8151 23:59:27.713427 TX Vref=30, minBit 1, minWin=25, winSum=417
8152 23:59:27.716962 TX Vref=32, minBit 1, minWin=24, winSum=407
8153 23:59:27.720983 TX Vref=34, minBit 2, minWin=24, winSum=403
8154 23:59:27.726972 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26
8155 23:59:27.727129
8156 23:59:27.730592 Final TX Range 0 Vref 26
8157 23:59:27.730774
8158 23:59:27.730875 ==
8159 23:59:27.733485 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 23:59:27.736628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 23:59:27.736759 ==
8162 23:59:27.736854
8163 23:59:27.736947
8164 23:59:27.740631 TX Vref Scan disable
8165 23:59:27.743894 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8166 23:59:27.747146 == TX Byte 0 ==
8167 23:59:27.750488 u2DelayCellOfst[0]=13 cells (4 PI)
8168 23:59:27.753645 u2DelayCellOfst[1]=17 cells (5 PI)
8169 23:59:27.756973 u2DelayCellOfst[2]=10 cells (3 PI)
8170 23:59:27.760112 u2DelayCellOfst[3]=10 cells (3 PI)
8171 23:59:27.763770 u2DelayCellOfst[4]=6 cells (2 PI)
8172 23:59:27.766942 u2DelayCellOfst[5]=0 cells (0 PI)
8173 23:59:27.767087 u2DelayCellOfst[6]=13 cells (4 PI)
8174 23:59:27.770079 u2DelayCellOfst[7]=17 cells (5 PI)
8175 23:59:27.776764 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8176 23:59:27.780038 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8177 23:59:27.780168 == TX Byte 1 ==
8178 23:59:27.783252 u2DelayCellOfst[8]=0 cells (0 PI)
8179 23:59:27.786532 u2DelayCellOfst[9]=0 cells (0 PI)
8180 23:59:27.790231 u2DelayCellOfst[10]=6 cells (2 PI)
8181 23:59:27.793400 u2DelayCellOfst[11]=3 cells (1 PI)
8182 23:59:27.796674 u2DelayCellOfst[12]=13 cells (4 PI)
8183 23:59:27.799756 u2DelayCellOfst[13]=13 cells (4 PI)
8184 23:59:27.803212 u2DelayCellOfst[14]=13 cells (4 PI)
8185 23:59:27.807065 u2DelayCellOfst[15]=10 cells (3 PI)
8186 23:59:27.810164 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8187 23:59:27.813300 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8188 23:59:27.816429 DramC Write-DBI on
8189 23:59:27.816557 ==
8190 23:59:27.820023 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 23:59:27.823642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 23:59:27.823764 ==
8193 23:59:27.823866
8194 23:59:27.823961
8195 23:59:27.826560 TX Vref Scan disable
8196 23:59:27.829865 == TX Byte 0 ==
8197 23:59:27.833564 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8198 23:59:27.836749 == TX Byte 1 ==
8199 23:59:27.840392 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8200 23:59:27.840513 DramC Write-DBI off
8201 23:59:27.840611
8202 23:59:27.843474 [DATLAT]
8203 23:59:27.843588 Freq=1600, CH0 RK1
8204 23:59:27.843686
8205 23:59:27.846677 DATLAT Default: 0xf
8206 23:59:27.846794 0, 0xFFFF, sum = 0
8207 23:59:27.849859 1, 0xFFFF, sum = 0
8208 23:59:27.849951 2, 0xFFFF, sum = 0
8209 23:59:27.853488 3, 0xFFFF, sum = 0
8210 23:59:27.853579 4, 0xFFFF, sum = 0
8211 23:59:27.856673 5, 0xFFFF, sum = 0
8212 23:59:27.856762 6, 0xFFFF, sum = 0
8213 23:59:27.859842 7, 0xFFFF, sum = 0
8214 23:59:27.859928 8, 0xFFFF, sum = 0
8215 23:59:27.863696 9, 0xFFFF, sum = 0
8216 23:59:27.866654 10, 0xFFFF, sum = 0
8217 23:59:27.866745 11, 0xFFFF, sum = 0
8218 23:59:27.869713 12, 0xFFFF, sum = 0
8219 23:59:27.869801 13, 0xFFFF, sum = 0
8220 23:59:27.873493 14, 0x0, sum = 1
8221 23:59:27.873590 15, 0x0, sum = 2
8222 23:59:27.876850 16, 0x0, sum = 3
8223 23:59:27.876941 17, 0x0, sum = 4
8224 23:59:27.877009 best_step = 15
8225 23:59:27.877071
8226 23:59:27.880223 ==
8227 23:59:27.883414 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 23:59:27.886850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 23:59:27.886947 ==
8230 23:59:27.887015 RX Vref Scan: 0
8231 23:59:27.887077
8232 23:59:27.889986 RX Vref 0 -> 0, step: 1
8233 23:59:27.890073
8234 23:59:27.893124 RX Delay 19 -> 252, step: 4
8235 23:59:27.896307 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8236 23:59:27.900182 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8237 23:59:27.906769 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8238 23:59:27.910137 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8239 23:59:27.913181 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8240 23:59:27.916268 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8241 23:59:27.920125 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8242 23:59:27.926413 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8243 23:59:27.929612 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8244 23:59:27.932975 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8245 23:59:27.936649 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8246 23:59:27.939764 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8247 23:59:27.946197 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8248 23:59:27.949928 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8249 23:59:27.952871 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8250 23:59:27.956448 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8251 23:59:27.956544 ==
8252 23:59:27.959713 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 23:59:27.966095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 23:59:27.966209 ==
8255 23:59:27.966277 DQS Delay:
8256 23:59:27.969367 DQS0 = 0, DQS1 = 0
8257 23:59:27.969453 DQM Delay:
8258 23:59:27.969519 DQM0 = 134, DQM1 = 127
8259 23:59:27.972616 DQ Delay:
8260 23:59:27.975812 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8261 23:59:27.979372 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8262 23:59:27.982600 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8263 23:59:27.986283 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8264 23:59:27.986386
8265 23:59:27.986455
8266 23:59:27.986517
8267 23:59:27.989226 [DramC_TX_OE_Calibration] TA2
8268 23:59:27.992930 Original DQ_B0 (3 6) =30, OEN = 27
8269 23:59:27.995950 Original DQ_B1 (3 6) =30, OEN = 27
8270 23:59:27.999580 24, 0x0, End_B0=24 End_B1=24
8271 23:59:27.999740 25, 0x0, End_B0=25 End_B1=25
8272 23:59:28.002402 26, 0x0, End_B0=26 End_B1=26
8273 23:59:28.006307 27, 0x0, End_B0=27 End_B1=27
8274 23:59:28.009486 28, 0x0, End_B0=28 End_B1=28
8275 23:59:28.012669 29, 0x0, End_B0=29 End_B1=29
8276 23:59:28.012870 30, 0x0, End_B0=30 End_B1=30
8277 23:59:28.015836 31, 0x4141, End_B0=30 End_B1=30
8278 23:59:28.019672 Byte0 end_step=30 best_step=27
8279 23:59:28.022846 Byte1 end_step=30 best_step=27
8280 23:59:28.025982 Byte0 TX OE(2T, 0.5T) = (3, 3)
8281 23:59:28.029256 Byte1 TX OE(2T, 0.5T) = (3, 3)
8282 23:59:28.029349
8283 23:59:28.029415
8284 23:59:28.036253 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8285 23:59:28.039535 CH0 RK1: MR19=303, MR18=2008
8286 23:59:28.046047 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8287 23:59:28.049009 [RxdqsGatingPostProcess] freq 1600
8288 23:59:28.052821 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8289 23:59:28.056142 best DQS0 dly(2T, 0.5T) = (1, 1)
8290 23:59:28.059215 best DQS1 dly(2T, 0.5T) = (1, 1)
8291 23:59:28.062473 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8292 23:59:28.065772 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8293 23:59:28.068861 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 23:59:28.072450 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 23:59:28.075623 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 23:59:28.079235 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 23:59:28.082242 Pre-setting of DQS Precalculation
8298 23:59:28.085317 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8299 23:59:28.085412 ==
8300 23:59:28.088951 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 23:59:28.095489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 23:59:28.095654 ==
8303 23:59:28.098785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8304 23:59:28.102263 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8305 23:59:28.108701 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8306 23:59:28.115106 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8307 23:59:28.122625 [CA 0] Center 42 (12~72) winsize 61
8308 23:59:28.125665 [CA 1] Center 42 (13~72) winsize 60
8309 23:59:28.129440 [CA 2] Center 39 (10~68) winsize 59
8310 23:59:28.132664 [CA 3] Center 38 (9~67) winsize 59
8311 23:59:28.135881 [CA 4] Center 38 (9~68) winsize 60
8312 23:59:28.139085 [CA 5] Center 37 (8~67) winsize 60
8313 23:59:28.139190
8314 23:59:28.142370 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8315 23:59:28.142462
8316 23:59:28.145590 [CATrainingPosCal] consider 1 rank data
8317 23:59:28.149552 u2DelayCellTimex100 = 285/100 ps
8318 23:59:28.155832 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8319 23:59:28.159025 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8320 23:59:28.162200 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8321 23:59:28.165467 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8322 23:59:28.168724 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8323 23:59:28.172040 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8324 23:59:28.172135
8325 23:59:28.175338 CA PerBit enable=1, Macro0, CA PI delay=37
8326 23:59:28.175428
8327 23:59:28.178965 [CBTSetCACLKResult] CA Dly = 37
8328 23:59:28.181935 CS Dly: 10 (0~41)
8329 23:59:28.185659 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8330 23:59:28.188564 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8331 23:59:28.188654 ==
8332 23:59:28.192221 Dram Type= 6, Freq= 0, CH_1, rank 1
8333 23:59:28.195301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 23:59:28.198558 ==
8335 23:59:28.201901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 23:59:28.205149 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 23:59:28.212154 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 23:59:28.218209 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 23:59:28.225835 [CA 0] Center 42 (13~72) winsize 60
8340 23:59:28.229095 [CA 1] Center 42 (13~72) winsize 60
8341 23:59:28.232465 [CA 2] Center 39 (10~69) winsize 60
8342 23:59:28.235921 [CA 3] Center 38 (9~68) winsize 60
8343 23:59:28.238907 [CA 4] Center 39 (9~69) winsize 61
8344 23:59:28.242186 [CA 5] Center 38 (9~68) winsize 60
8345 23:59:28.242298
8346 23:59:28.245954 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8347 23:59:28.246092
8348 23:59:28.249264 [CATrainingPosCal] consider 2 rank data
8349 23:59:28.252191 u2DelayCellTimex100 = 285/100 ps
8350 23:59:28.259141 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8351 23:59:28.262391 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8352 23:59:28.265575 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8353 23:59:28.268848 CA3 delay=38 (9~67),Diff = 0 PI (0 cell)
8354 23:59:28.272107 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8355 23:59:28.275510 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8356 23:59:28.275620
8357 23:59:28.279091 CA PerBit enable=1, Macro0, CA PI delay=38
8358 23:59:28.279211
8359 23:59:28.282405 [CBTSetCACLKResult] CA Dly = 38
8360 23:59:28.285362 CS Dly: 11 (0~44)
8361 23:59:28.288930 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 23:59:28.292083 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 23:59:28.292173
8364 23:59:28.295200 ----->DramcWriteLeveling(PI) begin...
8365 23:59:28.295306 ==
8366 23:59:28.298980 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 23:59:28.305529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 23:59:28.305619 ==
8369 23:59:28.309537 Write leveling (Byte 0): 25 => 25
8370 23:59:28.309625 Write leveling (Byte 1): 27 => 27
8371 23:59:28.312525 DramcWriteLeveling(PI) end<-----
8372 23:59:28.312611
8373 23:59:28.312678 ==
8374 23:59:28.315845 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 23:59:28.322276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 23:59:28.322429 ==
8377 23:59:28.326287 [Gating] SW mode calibration
8378 23:59:28.332160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8379 23:59:28.335786 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8380 23:59:28.342542 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 23:59:28.345306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 23:59:28.349424 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8383 23:59:28.355513 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 23:59:28.358669 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 23:59:28.361896 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 23:59:28.368540 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 23:59:28.372001 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 23:59:28.374949 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 23:59:28.382195 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 23:59:28.385474 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8391 23:59:28.388549 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
8392 23:59:28.395154 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 23:59:28.398174 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 23:59:28.401651 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 23:59:28.405064 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 23:59:28.411802 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:59:28.415234 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 23:59:28.418417 1 6 8 | B1->B0 | 2828 3636 | 0 1 | (1 1) (0 0)
8399 23:59:28.424992 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8400 23:59:28.428212 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 23:59:28.431435 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 23:59:28.438779 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 23:59:28.441874 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 23:59:28.444836 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 23:59:28.451471 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:59:28.455385 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8407 23:59:28.458210 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8408 23:59:28.464802 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8409 23:59:28.468067 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:59:28.471668 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:59:28.478339 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:59:28.481352 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:59:28.484797 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:59:28.491581 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:59:28.494856 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:59:28.498132 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:59:28.504552 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:59:28.508327 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:59:28.511488 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:59:28.517911 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:59:28.521502 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:59:28.524815 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8423 23:59:28.531236 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8424 23:59:28.534482 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8425 23:59:28.538321 Total UI for P1: 0, mck2ui 16
8426 23:59:28.541558 best dqsien dly found for B0: ( 1, 9, 10)
8427 23:59:28.544674 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 23:59:28.547919 Total UI for P1: 0, mck2ui 16
8429 23:59:28.551483 best dqsien dly found for B1: ( 1, 9, 12)
8430 23:59:28.554512 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8431 23:59:28.558211 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8432 23:59:28.558341
8433 23:59:28.561326 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8434 23:59:28.567827 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8435 23:59:28.567999 [Gating] SW calibration Done
8436 23:59:28.568125 ==
8437 23:59:28.570935 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 23:59:28.578082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 23:59:28.578258 ==
8440 23:59:28.578384 RX Vref Scan: 0
8441 23:59:28.578502
8442 23:59:28.581058 RX Vref 0 -> 0, step: 1
8443 23:59:28.581192
8444 23:59:28.584777 RX Delay 0 -> 252, step: 8
8445 23:59:28.587899 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8446 23:59:28.591052 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8447 23:59:28.594263 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8448 23:59:28.597695 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8449 23:59:28.604481 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8450 23:59:28.607702 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8451 23:59:28.610950 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8452 23:59:28.614858 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8453 23:59:28.617946 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8454 23:59:28.624672 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8455 23:59:28.627838 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8456 23:59:28.630952 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8457 23:59:28.634218 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8458 23:59:28.637447 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8459 23:59:28.644509 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8460 23:59:28.647682 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8461 23:59:28.647825 ==
8462 23:59:28.651000 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 23:59:28.654250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 23:59:28.654389 ==
8465 23:59:28.657443 DQS Delay:
8466 23:59:28.657585 DQS0 = 0, DQS1 = 0
8467 23:59:28.657705 DQM Delay:
8468 23:59:28.661003 DQM0 = 136, DQM1 = 132
8469 23:59:28.661138 DQ Delay:
8470 23:59:28.663960 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8471 23:59:28.667464 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8472 23:59:28.674161 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8473 23:59:28.677769 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8474 23:59:28.677910
8475 23:59:28.678031
8476 23:59:28.678150 ==
8477 23:59:28.680688 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 23:59:28.683944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 23:59:28.684083 ==
8480 23:59:28.684203
8481 23:59:28.684321
8482 23:59:28.687420 TX Vref Scan disable
8483 23:59:28.690567 == TX Byte 0 ==
8484 23:59:28.693712 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8485 23:59:28.697492 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8486 23:59:28.700675 == TX Byte 1 ==
8487 23:59:28.703969 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8488 23:59:28.706945 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8489 23:59:28.707075 ==
8490 23:59:28.710523 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 23:59:28.714086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 23:59:28.717310 ==
8493 23:59:28.728041
8494 23:59:28.731078 TX Vref early break, caculate TX vref
8495 23:59:28.734609 TX Vref=16, minBit 1, minWin=22, winSum=377
8496 23:59:28.737820 TX Vref=18, minBit 0, minWin=23, winSum=385
8497 23:59:28.740913 TX Vref=20, minBit 0, minWin=23, winSum=394
8498 23:59:28.744724 TX Vref=22, minBit 0, minWin=25, winSum=410
8499 23:59:28.748055 TX Vref=24, minBit 1, minWin=25, winSum=419
8500 23:59:28.754407 TX Vref=26, minBit 6, minWin=25, winSum=429
8501 23:59:28.757639 TX Vref=28, minBit 0, minWin=24, winSum=427
8502 23:59:28.761017 TX Vref=30, minBit 2, minWin=25, winSum=423
8503 23:59:28.764088 TX Vref=32, minBit 0, minWin=25, winSum=415
8504 23:59:28.767647 TX Vref=34, minBit 0, minWin=24, winSum=404
8505 23:59:28.774287 [TxChooseVref] Worse bit 6, Min win 25, Win sum 429, Final Vref 26
8506 23:59:28.774429
8507 23:59:28.777497 Final TX Range 0 Vref 26
8508 23:59:28.777628
8509 23:59:28.777745 ==
8510 23:59:28.781478 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 23:59:28.784526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 23:59:28.784659 ==
8513 23:59:28.784779
8514 23:59:28.784895
8515 23:59:28.787559 TX Vref Scan disable
8516 23:59:28.794389 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8517 23:59:28.794535 == TX Byte 0 ==
8518 23:59:28.797721 u2DelayCellOfst[0]=13 cells (4 PI)
8519 23:59:28.801298 u2DelayCellOfst[1]=10 cells (3 PI)
8520 23:59:28.804680 u2DelayCellOfst[2]=0 cells (0 PI)
8521 23:59:28.807263 u2DelayCellOfst[3]=6 cells (2 PI)
8522 23:59:28.810675 u2DelayCellOfst[4]=6 cells (2 PI)
8523 23:59:28.814484 u2DelayCellOfst[5]=17 cells (5 PI)
8524 23:59:28.817943 u2DelayCellOfst[6]=17 cells (5 PI)
8525 23:59:28.818076 u2DelayCellOfst[7]=3 cells (1 PI)
8526 23:59:28.824257 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8527 23:59:28.827420 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8528 23:59:28.827550 == TX Byte 1 ==
8529 23:59:28.830650 u2DelayCellOfst[8]=0 cells (0 PI)
8530 23:59:28.833882 u2DelayCellOfst[9]=3 cells (1 PI)
8531 23:59:28.837430 u2DelayCellOfst[10]=13 cells (4 PI)
8532 23:59:28.841251 u2DelayCellOfst[11]=3 cells (1 PI)
8533 23:59:28.844056 u2DelayCellOfst[12]=13 cells (4 PI)
8534 23:59:28.847081 u2DelayCellOfst[13]=13 cells (4 PI)
8535 23:59:28.850785 u2DelayCellOfst[14]=17 cells (5 PI)
8536 23:59:28.854008 u2DelayCellOfst[15]=17 cells (5 PI)
8537 23:59:28.857309 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8538 23:59:28.863775 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8539 23:59:28.863913 DramC Write-DBI on
8540 23:59:28.864033 ==
8541 23:59:28.867005 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 23:59:28.870819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 23:59:28.870908 ==
8544 23:59:28.873958
8545 23:59:28.874104
8546 23:59:28.874221 TX Vref Scan disable
8547 23:59:28.876994 == TX Byte 0 ==
8548 23:59:28.880547 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8549 23:59:28.883918 == TX Byte 1 ==
8550 23:59:28.887454 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8551 23:59:28.887587 DramC Write-DBI off
8552 23:59:28.890498
8553 23:59:28.890624 [DATLAT]
8554 23:59:28.890742 Freq=1600, CH1 RK0
8555 23:59:28.890861
8556 23:59:28.893624 DATLAT Default: 0xf
8557 23:59:28.893751 0, 0xFFFF, sum = 0
8558 23:59:28.897030 1, 0xFFFF, sum = 0
8559 23:59:28.897159 2, 0xFFFF, sum = 0
8560 23:59:28.900693 3, 0xFFFF, sum = 0
8561 23:59:28.900832 4, 0xFFFF, sum = 0
8562 23:59:28.903660 5, 0xFFFF, sum = 0
8563 23:59:28.906945 6, 0xFFFF, sum = 0
8564 23:59:28.907078 7, 0xFFFF, sum = 0
8565 23:59:28.910355 8, 0xFFFF, sum = 0
8566 23:59:28.910496 9, 0xFFFF, sum = 0
8567 23:59:28.913872 10, 0xFFFF, sum = 0
8568 23:59:28.914000 11, 0xFFFF, sum = 0
8569 23:59:28.917110 12, 0xFFFF, sum = 0
8570 23:59:28.917236 13, 0xFFFF, sum = 0
8571 23:59:28.920359 14, 0x0, sum = 1
8572 23:59:28.920491 15, 0x0, sum = 2
8573 23:59:28.923587 16, 0x0, sum = 3
8574 23:59:28.923718 17, 0x0, sum = 4
8575 23:59:28.926780 best_step = 15
8576 23:59:28.926910
8577 23:59:28.927028 ==
8578 23:59:28.930644 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 23:59:28.933653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 23:59:28.933779 ==
8581 23:59:28.933896 RX Vref Scan: 1
8582 23:59:28.936957
8583 23:59:28.937085 Set Vref Range= 24 -> 127
8584 23:59:28.937203
8585 23:59:28.940095 RX Vref 24 -> 127, step: 1
8586 23:59:28.940231
8587 23:59:28.943826 RX Delay 27 -> 252, step: 4
8588 23:59:28.943951
8589 23:59:28.946912 Set Vref, RX VrefLevel [Byte0]: 24
8590 23:59:28.950010 [Byte1]: 24
8591 23:59:28.950124
8592 23:59:28.953547 Set Vref, RX VrefLevel [Byte0]: 25
8593 23:59:28.956485 [Byte1]: 25
8594 23:59:28.956574
8595 23:59:28.959999 Set Vref, RX VrefLevel [Byte0]: 26
8596 23:59:28.963218 [Byte1]: 26
8597 23:59:28.967177
8598 23:59:28.967313 Set Vref, RX VrefLevel [Byte0]: 27
8599 23:59:28.970344 [Byte1]: 27
8600 23:59:28.974875
8601 23:59:28.975010 Set Vref, RX VrefLevel [Byte0]: 28
8602 23:59:28.978052 [Byte1]: 28
8603 23:59:28.982576
8604 23:59:28.982705 Set Vref, RX VrefLevel [Byte0]: 29
8605 23:59:28.985797 [Byte1]: 29
8606 23:59:28.989553
8607 23:59:28.989683 Set Vref, RX VrefLevel [Byte0]: 30
8608 23:59:28.993144 [Byte1]: 30
8609 23:59:28.997418
8610 23:59:28.997542 Set Vref, RX VrefLevel [Byte0]: 31
8611 23:59:29.000773 [Byte1]: 31
8612 23:59:29.004638
8613 23:59:29.004784 Set Vref, RX VrefLevel [Byte0]: 32
8614 23:59:29.008081 [Byte1]: 32
8615 23:59:29.012527
8616 23:59:29.012668 Set Vref, RX VrefLevel [Byte0]: 33
8617 23:59:29.015603 [Byte1]: 33
8618 23:59:29.019967
8619 23:59:29.020100 Set Vref, RX VrefLevel [Byte0]: 34
8620 23:59:29.023295 [Byte1]: 34
8621 23:59:29.027704
8622 23:59:29.027835 Set Vref, RX VrefLevel [Byte0]: 35
8623 23:59:29.030926 [Byte1]: 35
8624 23:59:29.034764
8625 23:59:29.034886 Set Vref, RX VrefLevel [Byte0]: 36
8626 23:59:29.038005 [Byte1]: 36
8627 23:59:29.042393
8628 23:59:29.042537 Set Vref, RX VrefLevel [Byte0]: 37
8629 23:59:29.045908 [Byte1]: 37
8630 23:59:29.049905
8631 23:59:29.050103 Set Vref, RX VrefLevel [Byte0]: 38
8632 23:59:29.053672 [Byte1]: 38
8633 23:59:29.057780
8634 23:59:29.057946 Set Vref, RX VrefLevel [Byte0]: 39
8635 23:59:29.060781 [Byte1]: 39
8636 23:59:29.065029
8637 23:59:29.065155 Set Vref, RX VrefLevel [Byte0]: 40
8638 23:59:29.068433 [Byte1]: 40
8639 23:59:29.072780
8640 23:59:29.072871 Set Vref, RX VrefLevel [Byte0]: 41
8641 23:59:29.076052 [Byte1]: 41
8642 23:59:29.080498
8643 23:59:29.080632 Set Vref, RX VrefLevel [Byte0]: 42
8644 23:59:29.083713 [Byte1]: 42
8645 23:59:29.087587
8646 23:59:29.087720 Set Vref, RX VrefLevel [Byte0]: 43
8647 23:59:29.091040 [Byte1]: 43
8648 23:59:29.095488
8649 23:59:29.095623 Set Vref, RX VrefLevel [Byte0]: 44
8650 23:59:29.098828 [Byte1]: 44
8651 23:59:29.102946
8652 23:59:29.103065 Set Vref, RX VrefLevel [Byte0]: 45
8653 23:59:29.105938 [Byte1]: 45
8654 23:59:29.110546
8655 23:59:29.110646 Set Vref, RX VrefLevel [Byte0]: 46
8656 23:59:29.113752 [Byte1]: 46
8657 23:59:29.117611
8658 23:59:29.117695 Set Vref, RX VrefLevel [Byte0]: 47
8659 23:59:29.121011 [Byte1]: 47
8660 23:59:29.125407
8661 23:59:29.125549 Set Vref, RX VrefLevel [Byte0]: 48
8662 23:59:29.129119 [Byte1]: 48
8663 23:59:29.132798
8664 23:59:29.132943 Set Vref, RX VrefLevel [Byte0]: 49
8665 23:59:29.136093 [Byte1]: 49
8666 23:59:29.140448
8667 23:59:29.140599 Set Vref, RX VrefLevel [Byte0]: 50
8668 23:59:29.143677 [Byte1]: 50
8669 23:59:29.147742
8670 23:59:29.147941 Set Vref, RX VrefLevel [Byte0]: 51
8671 23:59:29.151682 [Byte1]: 51
8672 23:59:29.156100
8673 23:59:29.156288 Set Vref, RX VrefLevel [Byte0]: 52
8674 23:59:29.159128 [Byte1]: 52
8675 23:59:29.162990
8676 23:59:29.163127 Set Vref, RX VrefLevel [Byte0]: 53
8677 23:59:29.166554 [Byte1]: 53
8678 23:59:29.170870
8679 23:59:29.170991 Set Vref, RX VrefLevel [Byte0]: 54
8680 23:59:29.173897 [Byte1]: 54
8681 23:59:29.177903
8682 23:59:29.177987 Set Vref, RX VrefLevel [Byte0]: 55
8683 23:59:29.181146 [Byte1]: 55
8684 23:59:29.185856
8685 23:59:29.185969 Set Vref, RX VrefLevel [Byte0]: 56
8686 23:59:29.188947 [Byte1]: 56
8687 23:59:29.193517
8688 23:59:29.193607 Set Vref, RX VrefLevel [Byte0]: 57
8689 23:59:29.196757 [Byte1]: 57
8690 23:59:29.200610
8691 23:59:29.200735 Set Vref, RX VrefLevel [Byte0]: 58
8692 23:59:29.203875 [Byte1]: 58
8693 23:59:29.208298
8694 23:59:29.208391 Set Vref, RX VrefLevel [Byte0]: 59
8695 23:59:29.211621 [Byte1]: 59
8696 23:59:29.215987
8697 23:59:29.216141 Set Vref, RX VrefLevel [Byte0]: 60
8698 23:59:29.219349 [Byte1]: 60
8699 23:59:29.223169
8700 23:59:29.223311 Set Vref, RX VrefLevel [Byte0]: 61
8701 23:59:29.226353 [Byte1]: 61
8702 23:59:29.230804
8703 23:59:29.230910 Set Vref, RX VrefLevel [Byte0]: 62
8704 23:59:29.233977 [Byte1]: 62
8705 23:59:29.238312
8706 23:59:29.238481 Set Vref, RX VrefLevel [Byte0]: 63
8707 23:59:29.241466 [Byte1]: 63
8708 23:59:29.246151
8709 23:59:29.246303 Set Vref, RX VrefLevel [Byte0]: 64
8710 23:59:29.248923 [Byte1]: 64
8711 23:59:29.253216
8712 23:59:29.253330 Set Vref, RX VrefLevel [Byte0]: 65
8713 23:59:29.257108 [Byte1]: 65
8714 23:59:29.261104
8715 23:59:29.261227 Set Vref, RX VrefLevel [Byte0]: 66
8716 23:59:29.264030 [Byte1]: 66
8717 23:59:29.268372
8718 23:59:29.268564 Set Vref, RX VrefLevel [Byte0]: 67
8719 23:59:29.272109 [Byte1]: 67
8720 23:59:29.276031
8721 23:59:29.276204 Set Vref, RX VrefLevel [Byte0]: 68
8722 23:59:29.279346 [Byte1]: 68
8723 23:59:29.283776
8724 23:59:29.283905 Set Vref, RX VrefLevel [Byte0]: 69
8725 23:59:29.286655 [Byte1]: 69
8726 23:59:29.290877
8727 23:59:29.291010 Set Vref, RX VrefLevel [Byte0]: 70
8728 23:59:29.294386 [Byte1]: 70
8729 23:59:29.298847
8730 23:59:29.299040 Set Vref, RX VrefLevel [Byte0]: 71
8731 23:59:29.302076 [Byte1]: 71
8732 23:59:29.306043
8733 23:59:29.306229 Set Vref, RX VrefLevel [Byte0]: 72
8734 23:59:29.309308 [Byte1]: 72
8735 23:59:29.314104
8736 23:59:29.314291 Set Vref, RX VrefLevel [Byte0]: 73
8737 23:59:29.317097 [Byte1]: 73
8738 23:59:29.321606
8739 23:59:29.321791 Set Vref, RX VrefLevel [Byte0]: 74
8740 23:59:29.324894 [Byte1]: 74
8741 23:59:29.329163
8742 23:59:29.329310 Set Vref, RX VrefLevel [Byte0]: 75
8743 23:59:29.331856 [Byte1]: 75
8744 23:59:29.336437
8745 23:59:29.336563 Set Vref, RX VrefLevel [Byte0]: 76
8746 23:59:29.339772 [Byte1]: 76
8747 23:59:29.343835
8748 23:59:29.343986 Set Vref, RX VrefLevel [Byte0]: 77
8749 23:59:29.347270 [Byte1]: 77
8750 23:59:29.351348
8751 23:59:29.351528 Final RX Vref Byte 0 = 56 to rank0
8752 23:59:29.354924 Final RX Vref Byte 1 = 55 to rank0
8753 23:59:29.357768 Final RX Vref Byte 0 = 56 to rank1
8754 23:59:29.361599 Final RX Vref Byte 1 = 55 to rank1==
8755 23:59:29.365028 Dram Type= 6, Freq= 0, CH_1, rank 0
8756 23:59:29.371004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 23:59:29.371103 ==
8758 23:59:29.371172 DQS Delay:
8759 23:59:29.374227 DQS0 = 0, DQS1 = 0
8760 23:59:29.374362 DQM Delay:
8761 23:59:29.374480 DQM0 = 134, DQM1 = 131
8762 23:59:29.378460 DQ Delay:
8763 23:59:29.381279 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8764 23:59:29.384227 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =132
8765 23:59:29.387845 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8766 23:59:29.391395 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8767 23:59:29.391535
8768 23:59:29.391659
8769 23:59:29.391771
8770 23:59:29.394542 [DramC_TX_OE_Calibration] TA2
8771 23:59:29.397606 Original DQ_B0 (3 6) =30, OEN = 27
8772 23:59:29.401112 Original DQ_B1 (3 6) =30, OEN = 27
8773 23:59:29.404528 24, 0x0, End_B0=24 End_B1=24
8774 23:59:29.404675 25, 0x0, End_B0=25 End_B1=25
8775 23:59:29.407536 26, 0x0, End_B0=26 End_B1=26
8776 23:59:29.410812 27, 0x0, End_B0=27 End_B1=27
8777 23:59:29.414707 28, 0x0, End_B0=28 End_B1=28
8778 23:59:29.418032 29, 0x0, End_B0=29 End_B1=29
8779 23:59:29.418174 30, 0x0, End_B0=30 End_B1=30
8780 23:59:29.421332 31, 0x4141, End_B0=30 End_B1=30
8781 23:59:29.424700 Byte0 end_step=30 best_step=27
8782 23:59:29.427875 Byte1 end_step=30 best_step=27
8783 23:59:29.431099 Byte0 TX OE(2T, 0.5T) = (3, 3)
8784 23:59:29.434368 Byte1 TX OE(2T, 0.5T) = (3, 3)
8785 23:59:29.434501
8786 23:59:29.434628
8787 23:59:29.440660 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8788 23:59:29.444093 CH1 RK0: MR19=303, MR18=1724
8789 23:59:29.451019 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8790 23:59:29.451197
8791 23:59:29.453996 ----->DramcWriteLeveling(PI) begin...
8792 23:59:29.454110 ==
8793 23:59:29.457190 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 23:59:29.460521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 23:59:29.460629 ==
8796 23:59:29.464373 Write leveling (Byte 0): 26 => 26
8797 23:59:29.467523 Write leveling (Byte 1): 29 => 29
8798 23:59:29.470995 DramcWriteLeveling(PI) end<-----
8799 23:59:29.471076
8800 23:59:29.471140 ==
8801 23:59:29.474201 Dram Type= 6, Freq= 0, CH_1, rank 1
8802 23:59:29.477707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8803 23:59:29.477858 ==
8804 23:59:29.480852 [Gating] SW mode calibration
8805 23:59:29.487345 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8806 23:59:29.494278 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8807 23:59:29.497100 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 23:59:29.500794 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 23:59:29.507608 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8810 23:59:29.510620 1 4 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (0 0)
8811 23:59:29.514134 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 23:59:29.520661 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 23:59:29.523796 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 23:59:29.527136 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 23:59:29.533620 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 23:59:29.536959 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8817 23:59:29.540246 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8818 23:59:29.547273 1 5 12 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 1)
8819 23:59:29.550339 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 23:59:29.553455 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 23:59:29.560378 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 23:59:29.563506 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 23:59:29.566491 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 23:59:29.573631 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8825 23:59:29.576695 1 6 8 | B1->B0 | 3131 2626 | 0 0 | (0 0) (0 0)
8826 23:59:29.579735 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8827 23:59:29.586495 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 23:59:29.589952 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 23:59:29.593075 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 23:59:29.599628 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 23:59:29.603528 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 23:59:29.606451 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8833 23:59:29.613433 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8834 23:59:29.616738 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8835 23:59:29.620001 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8836 23:59:29.626560 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:59:29.629650 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 23:59:29.633049 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 23:59:29.639931 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 23:59:29.643051 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 23:59:29.646488 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 23:59:29.652933 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 23:59:29.656712 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 23:59:29.659340 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 23:59:29.666340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 23:59:29.669428 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 23:59:29.673181 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 23:59:29.679686 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8849 23:59:29.682934 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8850 23:59:29.686352 Total UI for P1: 0, mck2ui 16
8851 23:59:29.689468 best dqsien dly found for B1: ( 1, 9, 4)
8852 23:59:29.693128 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8853 23:59:29.695998 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 23:59:29.699572 Total UI for P1: 0, mck2ui 16
8855 23:59:29.703001 best dqsien dly found for B0: ( 1, 9, 10)
8856 23:59:29.706134 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8857 23:59:29.709358 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8858 23:59:29.712657
8859 23:59:29.715967 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8860 23:59:29.719286 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8861 23:59:29.722527 [Gating] SW calibration Done
8862 23:59:29.722641 ==
8863 23:59:29.725785 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 23:59:29.729498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 23:59:29.729588 ==
8866 23:59:29.732663 RX Vref Scan: 0
8867 23:59:29.732744
8868 23:59:29.732812 RX Vref 0 -> 0, step: 1
8869 23:59:29.732877
8870 23:59:29.735999 RX Delay 0 -> 252, step: 8
8871 23:59:29.739604 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8872 23:59:29.742733 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8873 23:59:29.749243 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8874 23:59:29.752797 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8875 23:59:29.756069 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8876 23:59:29.759299 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8877 23:59:29.762529 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8878 23:59:29.768911 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8879 23:59:29.772793 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8880 23:59:29.775811 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8881 23:59:29.778837 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8882 23:59:29.782109 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8883 23:59:29.789294 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8884 23:59:29.793007 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8885 23:59:29.795720 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8886 23:59:29.798687 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8887 23:59:29.798804 ==
8888 23:59:29.802080 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 23:59:29.808779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 23:59:29.808915 ==
8891 23:59:29.809013 DQS Delay:
8892 23:59:29.812497 DQS0 = 0, DQS1 = 0
8893 23:59:29.812628 DQM Delay:
8894 23:59:29.815517 DQM0 = 136, DQM1 = 134
8895 23:59:29.815610 DQ Delay:
8896 23:59:29.818708 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8897 23:59:29.821989 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8898 23:59:29.825893 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8899 23:59:29.829093 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8900 23:59:29.829185
8901 23:59:29.829252
8902 23:59:29.829315 ==
8903 23:59:29.832068 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 23:59:29.838459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 23:59:29.838567 ==
8906 23:59:29.838637
8907 23:59:29.838700
8908 23:59:29.838759 TX Vref Scan disable
8909 23:59:29.841668 == TX Byte 0 ==
8910 23:59:29.845528 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8911 23:59:29.849035 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8912 23:59:29.852057 == TX Byte 1 ==
8913 23:59:29.855030 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8914 23:59:29.861527 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8915 23:59:29.861649 ==
8916 23:59:29.864874 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 23:59:29.868321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 23:59:29.868421 ==
8919 23:59:29.880839
8920 23:59:29.883977 TX Vref early break, caculate TX vref
8921 23:59:29.887534 TX Vref=16, minBit 0, minWin=23, winSum=383
8922 23:59:29.890764 TX Vref=18, minBit 0, minWin=23, winSum=392
8923 23:59:29.894087 TX Vref=20, minBit 0, minWin=24, winSum=400
8924 23:59:29.897209 TX Vref=22, minBit 0, minWin=24, winSum=410
8925 23:59:29.900659 TX Vref=24, minBit 0, minWin=25, winSum=419
8926 23:59:29.907410 TX Vref=26, minBit 0, minWin=26, winSum=426
8927 23:59:29.910659 TX Vref=28, minBit 0, minWin=26, winSum=425
8928 23:59:29.913941 TX Vref=30, minBit 6, minWin=25, winSum=421
8929 23:59:29.917286 TX Vref=32, minBit 0, minWin=25, winSum=416
8930 23:59:29.920308 TX Vref=34, minBit 0, minWin=24, winSum=403
8931 23:59:29.927281 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8932 23:59:29.927397
8933 23:59:29.930419 Final TX Range 0 Vref 26
8934 23:59:29.930513
8935 23:59:29.930582 ==
8936 23:59:29.934234 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 23:59:29.937392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 23:59:29.937489 ==
8939 23:59:29.937558
8940 23:59:29.937622
8941 23:59:29.940636 TX Vref Scan disable
8942 23:59:29.947182 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8943 23:59:29.947333 == TX Byte 0 ==
8944 23:59:29.950948 u2DelayCellOfst[0]=20 cells (6 PI)
8945 23:59:29.954155 u2DelayCellOfst[1]=13 cells (4 PI)
8946 23:59:29.957440 u2DelayCellOfst[2]=0 cells (0 PI)
8947 23:59:29.960498 u2DelayCellOfst[3]=10 cells (3 PI)
8948 23:59:29.964115 u2DelayCellOfst[4]=13 cells (4 PI)
8949 23:59:29.967437 u2DelayCellOfst[5]=20 cells (6 PI)
8950 23:59:29.970676 u2DelayCellOfst[6]=20 cells (6 PI)
8951 23:59:29.970769 u2DelayCellOfst[7]=10 cells (3 PI)
8952 23:59:29.977391 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8953 23:59:29.980989 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8954 23:59:29.981084 == TX Byte 1 ==
8955 23:59:29.984224 u2DelayCellOfst[8]=0 cells (0 PI)
8956 23:59:29.987686 u2DelayCellOfst[9]=3 cells (1 PI)
8957 23:59:29.990951 u2DelayCellOfst[10]=10 cells (3 PI)
8958 23:59:29.993964 u2DelayCellOfst[11]=3 cells (1 PI)
8959 23:59:29.996979 u2DelayCellOfst[12]=13 cells (4 PI)
8960 23:59:30.000317 u2DelayCellOfst[13]=13 cells (4 PI)
8961 23:59:30.004246 u2DelayCellOfst[14]=17 cells (5 PI)
8962 23:59:30.007537 u2DelayCellOfst[15]=17 cells (5 PI)
8963 23:59:30.010442 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8964 23:59:30.016971 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8965 23:59:30.017110 DramC Write-DBI on
8966 23:59:30.017212 ==
8967 23:59:30.020707 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 23:59:30.024275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 23:59:30.024426 ==
8970 23:59:30.024524
8971 23:59:30.027388
8972 23:59:30.027499 TX Vref Scan disable
8973 23:59:30.030452 == TX Byte 0 ==
8974 23:59:30.033644 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8975 23:59:30.037561 == TX Byte 1 ==
8976 23:59:30.040706 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8977 23:59:30.040842 DramC Write-DBI off
8978 23:59:30.040957
8979 23:59:30.043633 [DATLAT]
8980 23:59:30.043749 Freq=1600, CH1 RK1
8981 23:59:30.043848
8982 23:59:30.047488 DATLAT Default: 0xf
8983 23:59:30.047601 0, 0xFFFF, sum = 0
8984 23:59:30.050842 1, 0xFFFF, sum = 0
8985 23:59:30.050969 2, 0xFFFF, sum = 0
8986 23:59:30.053946 3, 0xFFFF, sum = 0
8987 23:59:30.054061 4, 0xFFFF, sum = 0
8988 23:59:30.057134 5, 0xFFFF, sum = 0
8989 23:59:30.057260 6, 0xFFFF, sum = 0
8990 23:59:30.060329 7, 0xFFFF, sum = 0
8991 23:59:30.063517 8, 0xFFFF, sum = 0
8992 23:59:30.063631 9, 0xFFFF, sum = 0
8993 23:59:30.067310 10, 0xFFFF, sum = 0
8994 23:59:30.067426 11, 0xFFFF, sum = 0
8995 23:59:30.070346 12, 0xFFFF, sum = 0
8996 23:59:30.070491 13, 0xFFFF, sum = 0
8997 23:59:30.073633 14, 0x0, sum = 1
8998 23:59:30.073755 15, 0x0, sum = 2
8999 23:59:30.076886 16, 0x0, sum = 3
9000 23:59:30.076986 17, 0x0, sum = 4
9001 23:59:30.077057 best_step = 15
9002 23:59:30.080651
9003 23:59:30.080743 ==
9004 23:59:30.083848 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 23:59:30.086822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 23:59:30.086949 ==
9007 23:59:30.087050 RX Vref Scan: 0
9008 23:59:30.087146
9009 23:59:30.090482 RX Vref 0 -> 0, step: 1
9010 23:59:30.090605
9011 23:59:30.093907 RX Delay 19 -> 252, step: 4
9012 23:59:30.096981 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9013 23:59:30.099993 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9014 23:59:30.107071 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9015 23:59:30.110282 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9016 23:59:30.113501 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9017 23:59:30.116548 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9018 23:59:30.120545 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9019 23:59:30.126552 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9020 23:59:30.130078 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9021 23:59:30.133717 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9022 23:59:30.136837 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9023 23:59:30.139815 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9024 23:59:30.146804 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9025 23:59:30.149870 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9026 23:59:30.153093 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9027 23:59:30.157119 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9028 23:59:30.157241 ==
9029 23:59:30.160185 Dram Type= 6, Freq= 0, CH_1, rank 1
9030 23:59:30.166534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9031 23:59:30.166668 ==
9032 23:59:30.166769 DQS Delay:
9033 23:59:30.166863 DQS0 = 0, DQS1 = 0
9034 23:59:30.169906 DQM Delay:
9035 23:59:30.170017 DQM0 = 134, DQM1 = 130
9036 23:59:30.173636 DQ Delay:
9037 23:59:30.176697 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =130
9038 23:59:30.179946 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9039 23:59:30.183220 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9040 23:59:30.186567 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9041 23:59:30.186686
9042 23:59:30.186783
9043 23:59:30.186878
9044 23:59:30.189777 [DramC_TX_OE_Calibration] TA2
9045 23:59:30.193785 Original DQ_B0 (3 6) =30, OEN = 27
9046 23:59:30.196755 Original DQ_B1 (3 6) =30, OEN = 27
9047 23:59:30.200031 24, 0x0, End_B0=24 End_B1=24
9048 23:59:30.200164 25, 0x0, End_B0=25 End_B1=25
9049 23:59:30.203346 26, 0x0, End_B0=26 End_B1=26
9050 23:59:30.206674 27, 0x0, End_B0=27 End_B1=27
9051 23:59:30.210001 28, 0x0, End_B0=28 End_B1=28
9052 23:59:30.210102 29, 0x0, End_B0=29 End_B1=29
9053 23:59:30.213256 30, 0x0, End_B0=30 End_B1=30
9054 23:59:30.216556 31, 0x4141, End_B0=30 End_B1=30
9055 23:59:30.220017 Byte0 end_step=30 best_step=27
9056 23:59:30.223173 Byte1 end_step=30 best_step=27
9057 23:59:30.226677 Byte0 TX OE(2T, 0.5T) = (3, 3)
9058 23:59:30.229433 Byte1 TX OE(2T, 0.5T) = (3, 3)
9059 23:59:30.229527
9060 23:59:30.229595
9061 23:59:30.236354 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9062 23:59:30.239397 CH1 RK1: MR19=303, MR18=2207
9063 23:59:30.246063 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9064 23:59:30.249676 [RxdqsGatingPostProcess] freq 1600
9065 23:59:30.252979 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9066 23:59:30.255867 best DQS0 dly(2T, 0.5T) = (1, 1)
9067 23:59:30.259379 best DQS1 dly(2T, 0.5T) = (1, 1)
9068 23:59:30.263062 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9069 23:59:30.266271 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9070 23:59:30.269495 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 23:59:30.272674 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 23:59:30.275887 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 23:59:30.279675 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 23:59:30.282726 Pre-setting of DQS Precalculation
9075 23:59:30.286038 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9076 23:59:30.292451 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9077 23:59:30.299497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9078 23:59:30.302635
9079 23:59:30.302752
9080 23:59:30.302847 [Calibration Summary] 3200 Mbps
9081 23:59:30.306344 CH 0, Rank 0
9082 23:59:30.306457 SW Impedance : PASS
9083 23:59:30.309345 DUTY Scan : NO K
9084 23:59:30.312615 ZQ Calibration : PASS
9085 23:59:30.312710 Jitter Meter : NO K
9086 23:59:30.315834 CBT Training : PASS
9087 23:59:30.319726 Write leveling : PASS
9088 23:59:30.319842 RX DQS gating : PASS
9089 23:59:30.322893 RX DQ/DQS(RDDQC) : PASS
9090 23:59:30.326103 TX DQ/DQS : PASS
9091 23:59:30.326193 RX DATLAT : PASS
9092 23:59:30.329454 RX DQ/DQS(Engine): PASS
9093 23:59:30.332682 TX OE : PASS
9094 23:59:30.332770 All Pass.
9095 23:59:30.332838
9096 23:59:30.332902 CH 0, Rank 1
9097 23:59:30.336363 SW Impedance : PASS
9098 23:59:30.339748 DUTY Scan : NO K
9099 23:59:30.339835 ZQ Calibration : PASS
9100 23:59:30.342923 Jitter Meter : NO K
9101 23:59:30.343011 CBT Training : PASS
9102 23:59:30.345931 Write leveling : PASS
9103 23:59:30.349678 RX DQS gating : PASS
9104 23:59:30.349766 RX DQ/DQS(RDDQC) : PASS
9105 23:59:30.352754 TX DQ/DQS : PASS
9106 23:59:30.355726 RX DATLAT : PASS
9107 23:59:30.355814 RX DQ/DQS(Engine): PASS
9108 23:59:30.359204 TX OE : PASS
9109 23:59:30.359292 All Pass.
9110 23:59:30.359360
9111 23:59:30.362495 CH 1, Rank 0
9112 23:59:30.362584 SW Impedance : PASS
9113 23:59:30.366384 DUTY Scan : NO K
9114 23:59:30.369162 ZQ Calibration : PASS
9115 23:59:30.369250 Jitter Meter : NO K
9116 23:59:30.372738 CBT Training : PASS
9117 23:59:30.376184 Write leveling : PASS
9118 23:59:30.376300 RX DQS gating : PASS
9119 23:59:30.379433 RX DQ/DQS(RDDQC) : PASS
9120 23:59:30.382721 TX DQ/DQS : PASS
9121 23:59:30.382813 RX DATLAT : PASS
9122 23:59:30.385548 RX DQ/DQS(Engine): PASS
9123 23:59:30.389016 TX OE : PASS
9124 23:59:30.389110 All Pass.
9125 23:59:30.389178
9126 23:59:30.389242 CH 1, Rank 1
9127 23:59:30.392771 SW Impedance : PASS
9128 23:59:30.395961 DUTY Scan : NO K
9129 23:59:30.396052 ZQ Calibration : PASS
9130 23:59:30.399198 Jitter Meter : NO K
9131 23:59:30.399285 CBT Training : PASS
9132 23:59:30.402539 Write leveling : PASS
9133 23:59:30.405843 RX DQS gating : PASS
9134 23:59:30.405930 RX DQ/DQS(RDDQC) : PASS
9135 23:59:30.408935 TX DQ/DQS : PASS
9136 23:59:30.412046 RX DATLAT : PASS
9137 23:59:30.412134 RX DQ/DQS(Engine): PASS
9138 23:59:30.415638 TX OE : PASS
9139 23:59:30.415742 All Pass.
9140 23:59:30.415849
9141 23:59:30.418639 DramC Write-DBI on
9142 23:59:30.422371 PER_BANK_REFRESH: Hybrid Mode
9143 23:59:30.422490 TX_TRACKING: ON
9144 23:59:30.432456 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9145 23:59:30.438820 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9146 23:59:30.445327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9147 23:59:30.452167 [FAST_K] Save calibration result to emmc
9148 23:59:30.452314 sync common calibartion params.
9149 23:59:30.455403 sync cbt_mode0:1, 1:1
9150 23:59:30.458740 dram_init: ddr_geometry: 2
9151 23:59:30.458837 dram_init: ddr_geometry: 2
9152 23:59:30.461895 dram_init: ddr_geometry: 2
9153 23:59:30.465095 0:dram_rank_size:100000000
9154 23:59:30.468896 1:dram_rank_size:100000000
9155 23:59:30.471966 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9156 23:59:30.475179 DFS_SHUFFLE_HW_MODE: ON
9157 23:59:30.478656 dramc_set_vcore_voltage set vcore to 725000
9158 23:59:30.481739 Read voltage for 1600, 0
9159 23:59:30.481866 Vio18 = 0
9160 23:59:30.485364 Vcore = 725000
9161 23:59:30.485488 Vdram = 0
9162 23:59:30.485588 Vddq = 0
9163 23:59:30.485720 Vmddr = 0
9164 23:59:30.488615 switch to 3200 Mbps bootup
9165 23:59:30.491551 [DramcRunTimeConfig]
9166 23:59:30.491660 PHYPLL
9167 23:59:30.491758 DPM_CONTROL_AFTERK: ON
9168 23:59:30.494934 PER_BANK_REFRESH: ON
9169 23:59:30.498784 REFRESH_OVERHEAD_REDUCTION: ON
9170 23:59:30.501814 CMD_PICG_NEW_MODE: OFF
9171 23:59:30.501937 XRTWTW_NEW_MODE: ON
9172 23:59:30.505396 XRTRTR_NEW_MODE: ON
9173 23:59:30.505510 TX_TRACKING: ON
9174 23:59:30.508797 RDSEL_TRACKING: OFF
9175 23:59:30.508894 DQS Precalculation for DVFS: ON
9176 23:59:30.512013 RX_TRACKING: OFF
9177 23:59:30.512133 HW_GATING DBG: ON
9178 23:59:30.514974 ZQCS_ENABLE_LP4: ON
9179 23:59:30.518366 RX_PICG_NEW_MODE: ON
9180 23:59:30.518481 TX_PICG_NEW_MODE: ON
9181 23:59:30.521919 ENABLE_RX_DCM_DPHY: ON
9182 23:59:30.524923 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9183 23:59:30.525039 DUMMY_READ_FOR_TRACKING: OFF
9184 23:59:30.528055 !!! SPM_CONTROL_AFTERK: OFF
9185 23:59:30.532071 !!! SPM could not control APHY
9186 23:59:30.535094 IMPEDANCE_TRACKING: ON
9187 23:59:30.535188 TEMP_SENSOR: ON
9188 23:59:30.538396 HW_SAVE_FOR_SR: OFF
9189 23:59:30.538488 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9190 23:59:30.545370 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9191 23:59:30.545485 Read ODT Tracking: ON
9192 23:59:30.548530 Refresh Rate DeBounce: ON
9193 23:59:30.551992 DFS_NO_QUEUE_FLUSH: ON
9194 23:59:30.554977 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9195 23:59:30.555092 ENABLE_DFS_RUNTIME_MRW: OFF
9196 23:59:30.558180 DDR_RESERVE_NEW_MODE: ON
9197 23:59:30.561386 MR_CBT_SWITCH_FREQ: ON
9198 23:59:30.561516 =========================
9199 23:59:30.581350 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9200 23:59:30.584291 dram_init: ddr_geometry: 2
9201 23:59:30.603207 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9202 23:59:30.606458 dram_init: dram init end (result: 0)
9203 23:59:30.612724 DRAM-K: Full calibration passed in 24458 msecs
9204 23:59:30.616416 MRC: failed to locate region type 0.
9205 23:59:30.616537 DRAM rank0 size:0x100000000,
9206 23:59:30.619302 DRAM rank1 size=0x100000000
9207 23:59:30.629274 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9208 23:59:30.636211 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9209 23:59:30.642967 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9210 23:59:30.649802 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9211 23:59:30.653213 DRAM rank0 size:0x100000000,
9212 23:59:30.656492 DRAM rank1 size=0x100000000
9213 23:59:30.656625 CBMEM:
9214 23:59:30.659549 IMD: root @ 0xfffff000 254 entries.
9215 23:59:30.662800 IMD: root @ 0xffffec00 62 entries.
9216 23:59:30.666077 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9217 23:59:30.669400 WARNING: RO_VPD is uninitialized or empty.
9218 23:59:30.675936 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9219 23:59:30.682976 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9220 23:59:30.695670 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9221 23:59:30.707060 BS: romstage times (exec / console): total (unknown) / 23990 ms
9222 23:59:30.707188
9223 23:59:30.707262
9224 23:59:30.716792 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9225 23:59:30.720031 ARM64: Exception handlers installed.
9226 23:59:30.723903 ARM64: Testing exception
9227 23:59:30.727003 ARM64: Done test exception
9228 23:59:30.727095 Enumerating buses...
9229 23:59:30.730152 Show all devs... Before device enumeration.
9230 23:59:30.733298 Root Device: enabled 1
9231 23:59:30.737091 CPU_CLUSTER: 0: enabled 1
9232 23:59:30.737185 CPU: 00: enabled 1
9233 23:59:30.740322 Compare with tree...
9234 23:59:30.740424 Root Device: enabled 1
9235 23:59:30.743272 CPU_CLUSTER: 0: enabled 1
9236 23:59:30.747119 CPU: 00: enabled 1
9237 23:59:30.747212 Root Device scanning...
9238 23:59:30.749864 scan_static_bus for Root Device
9239 23:59:30.753443 CPU_CLUSTER: 0 enabled
9240 23:59:30.756838 scan_static_bus for Root Device done
9241 23:59:30.760219 scan_bus: bus Root Device finished in 8 msecs
9242 23:59:30.760318 done
9243 23:59:30.766723 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9244 23:59:30.770388 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9245 23:59:30.776690 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9246 23:59:30.780031 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9247 23:59:30.783325 Allocating resources...
9248 23:59:30.786658 Reading resources...
9249 23:59:30.789831 Root Device read_resources bus 0 link: 0
9250 23:59:30.789918 DRAM rank0 size:0x100000000,
9251 23:59:30.792941 DRAM rank1 size=0x100000000
9252 23:59:30.796621 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9253 23:59:30.799557 CPU: 00 missing read_resources
9254 23:59:30.806314 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9255 23:59:30.810163 Root Device read_resources bus 0 link: 0 done
9256 23:59:30.810294 Done reading resources.
9257 23:59:30.816432 Show resources in subtree (Root Device)...After reading.
9258 23:59:30.819706 Root Device child on link 0 CPU_CLUSTER: 0
9259 23:59:30.823010 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 23:59:30.833142 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 23:59:30.833271 CPU: 00
9262 23:59:30.836108 Root Device assign_resources, bus 0 link: 0
9263 23:59:30.839922 CPU_CLUSTER: 0 missing set_resources
9264 23:59:30.846201 Root Device assign_resources, bus 0 link: 0 done
9265 23:59:30.846312 Done setting resources.
9266 23:59:30.852836 Show resources in subtree (Root Device)...After assigning values.
9267 23:59:30.856032 Root Device child on link 0 CPU_CLUSTER: 0
9268 23:59:30.859403 CPU_CLUSTER: 0 child on link 0 CPU: 00
9269 23:59:30.869809 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9270 23:59:30.869913 CPU: 00
9271 23:59:30.872947 Done allocating resources.
9272 23:59:30.876118 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9273 23:59:30.879365 Enabling resources...
9274 23:59:30.879454 done.
9275 23:59:30.886270 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9276 23:59:30.886365 Initializing devices...
9277 23:59:30.889639 Root Device init
9278 23:59:30.889725 init hardware done!
9279 23:59:30.892631 0x00000018: ctrlr->caps
9280 23:59:30.895829 52.000 MHz: ctrlr->f_max
9281 23:59:30.895921 0.400 MHz: ctrlr->f_min
9282 23:59:30.899669 0x40ff8080: ctrlr->voltages
9283 23:59:30.899794 sclk: 390625
9284 23:59:30.902760 Bus Width = 1
9285 23:59:30.902856 sclk: 390625
9286 23:59:30.905792 Bus Width = 1
9287 23:59:30.905911 Early init status = 3
9288 23:59:30.912454 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9289 23:59:30.915636 in-header: 03 fc 00 00 01 00 00 00
9290 23:59:30.918792 in-data: 00
9291 23:59:30.922663 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9292 23:59:30.927929 in-header: 03 fd 00 00 00 00 00 00
9293 23:59:30.931171 in-data:
9294 23:59:30.934367 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9295 23:59:30.938806 in-header: 03 fc 00 00 01 00 00 00
9296 23:59:30.942081 in-data: 00
9297 23:59:30.945463 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9298 23:59:30.950843 in-header: 03 fd 00 00 00 00 00 00
9299 23:59:30.954131 in-data:
9300 23:59:30.957527 [SSUSB] Setting up USB HOST controller...
9301 23:59:30.960810 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9302 23:59:30.963989 [SSUSB] phy power-on done.
9303 23:59:30.967261 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9304 23:59:30.974210 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9305 23:59:30.977351 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9306 23:59:30.984323 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9307 23:59:30.990859 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9308 23:59:30.997634 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9309 23:59:31.003994 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9310 23:59:31.010703 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9311 23:59:31.013753 SPM: binary array size = 0x9dc
9312 23:59:31.017180 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9313 23:59:31.024074 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9314 23:59:31.030352 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9315 23:59:31.033603 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9316 23:59:31.040626 configure_display: Starting display init
9317 23:59:31.074314 anx7625_power_on_init: Init interface.
9318 23:59:31.077651 anx7625_disable_pd_protocol: Disabled PD feature.
9319 23:59:31.080814 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9320 23:59:31.108683 anx7625_start_dp_work: Secure OCM version=00
9321 23:59:31.111785 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9322 23:59:31.126657 sp_tx_get_edid_block: EDID Block = 1
9323 23:59:31.229141 Extracted contents:
9324 23:59:31.232273 header: 00 ff ff ff ff ff ff 00
9325 23:59:31.236175 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9326 23:59:31.239030 version: 01 04
9327 23:59:31.242518 basic params: 95 1f 11 78 0a
9328 23:59:31.245954 chroma info: 76 90 94 55 54 90 27 21 50 54
9329 23:59:31.249214 established: 00 00 00
9330 23:59:31.255878 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9331 23:59:31.258830 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9332 23:59:31.265469 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9333 23:59:31.272499 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9334 23:59:31.278901 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9335 23:59:31.282499 extensions: 00
9336 23:59:31.282626 checksum: fb
9337 23:59:31.282721
9338 23:59:31.285726 Manufacturer: IVO Model 57d Serial Number 0
9339 23:59:31.288978 Made week 0 of 2020
9340 23:59:31.289097 EDID version: 1.4
9341 23:59:31.292184 Digital display
9342 23:59:31.295369 6 bits per primary color channel
9343 23:59:31.295488 DisplayPort interface
9344 23:59:31.298858 Maximum image size: 31 cm x 17 cm
9345 23:59:31.302637 Gamma: 220%
9346 23:59:31.302757 Check DPMS levels
9347 23:59:31.305832 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9348 23:59:31.308995 First detailed timing is preferred timing
9349 23:59:31.312116 Established timings supported:
9350 23:59:31.315864 Standard timings supported:
9351 23:59:31.315974 Detailed timings
9352 23:59:31.322389 Hex of detail: 383680a07038204018303c0035ae10000019
9353 23:59:31.325686 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9354 23:59:31.332517 0780 0798 07c8 0820 hborder 0
9355 23:59:31.335728 0438 043b 0447 0458 vborder 0
9356 23:59:31.339325 -hsync -vsync
9357 23:59:31.339442 Did detailed timing
9358 23:59:31.341915 Hex of detail: 000000000000000000000000000000000000
9359 23:59:31.345768 Manufacturer-specified data, tag 0
9360 23:59:31.351929 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9361 23:59:31.352069 ASCII string: InfoVision
9362 23:59:31.358929 Hex of detail: 000000fe00523134304e574635205248200a
9363 23:59:31.362116 ASCII string: R140NWF5 RH
9364 23:59:31.362236 Checksum
9365 23:59:31.362333 Checksum: 0xfb (valid)
9366 23:59:31.369051 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9367 23:59:31.371956 DSI data_rate: 832800000 bps
9368 23:59:31.375426 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9369 23:59:31.381965 anx7625_parse_edid: pixelclock(138800).
9370 23:59:31.385160 hactive(1920), hsync(48), hfp(24), hbp(88)
9371 23:59:31.388188 vactive(1080), vsync(12), vfp(3), vbp(17)
9372 23:59:31.391915 anx7625_dsi_config: config dsi.
9373 23:59:31.398737 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9374 23:59:31.411430 anx7625_dsi_config: success to config DSI
9375 23:59:31.414563 anx7625_dp_start: MIPI phy setup OK.
9376 23:59:31.417626 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9377 23:59:31.421609 mtk_ddp_mode_set invalid vrefresh 60
9378 23:59:31.424625 main_disp_path_setup
9379 23:59:31.424738 ovl_layer_smi_id_en
9380 23:59:31.427735 ovl_layer_smi_id_en
9381 23:59:31.427846 ccorr_config
9382 23:59:31.427942 aal_config
9383 23:59:31.430996 gamma_config
9384 23:59:31.431105 postmask_config
9385 23:59:31.434315 dither_config
9386 23:59:31.438347 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9387 23:59:31.444771 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9388 23:59:31.448073 Root Device init finished in 555 msecs
9389 23:59:31.448191 CPU_CLUSTER: 0 init
9390 23:59:31.457954 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9391 23:59:31.461091 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9392 23:59:31.465059 APU_MBOX 0x190000b0 = 0x10001
9393 23:59:31.467892 APU_MBOX 0x190001b0 = 0x10001
9394 23:59:31.471063 APU_MBOX 0x190005b0 = 0x10001
9395 23:59:31.474526 APU_MBOX 0x190006b0 = 0x10001
9396 23:59:31.477495 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9397 23:59:31.490321 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9398 23:59:31.502411 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9399 23:59:31.509306 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9400 23:59:31.521138 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9401 23:59:31.530155 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9402 23:59:31.533564 CPU_CLUSTER: 0 init finished in 81 msecs
9403 23:59:31.536745 Devices initialized
9404 23:59:31.540013 Show all devs... After init.
9405 23:59:31.540128 Root Device: enabled 1
9406 23:59:31.543253 CPU_CLUSTER: 0: enabled 1
9407 23:59:31.546472 CPU: 00: enabled 1
9408 23:59:31.550083 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9409 23:59:31.553035 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9410 23:59:31.556278 ELOG: NV offset 0x57f000 size 0x1000
9411 23:59:31.563593 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9412 23:59:31.570140 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9413 23:59:31.572939 ELOG: Event(17) added with size 13 at 2024-05-29 23:54:50 UTC
9414 23:59:31.579669 out: cmd=0x121: 03 db 21 01 00 00 00 00
9415 23:59:31.583173 in-header: 03 dd 00 00 2c 00 00 00
9416 23:59:31.592749 in-data: 82 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9417 23:59:31.599701 ELOG: Event(A1) added with size 10 at 2024-05-29 23:54:50 UTC
9418 23:59:31.606292 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9419 23:59:31.612637 ELOG: Event(A0) added with size 9 at 2024-05-29 23:54:50 UTC
9420 23:59:31.616215 elog_add_boot_reason: Logged dev mode boot
9421 23:59:31.622830 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9422 23:59:31.622982 Finalize devices...
9423 23:59:31.626011 Devices finalized
9424 23:59:31.629424 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9425 23:59:31.632363 Writing coreboot table at 0xffe64000
9426 23:59:31.635478 0. 000000000010a000-0000000000113fff: RAMSTAGE
9427 23:59:31.639343 1. 0000000040000000-00000000400fffff: RAM
9428 23:59:31.645969 2. 0000000040100000-000000004032afff: RAMSTAGE
9429 23:59:31.649219 3. 000000004032b000-00000000545fffff: RAM
9430 23:59:31.652692 4. 0000000054600000-000000005465ffff: BL31
9431 23:59:31.655812 5. 0000000054660000-00000000ffe63fff: RAM
9432 23:59:31.662519 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9433 23:59:31.665785 7. 0000000100000000-000000023fffffff: RAM
9434 23:59:31.668943 Passing 5 GPIOs to payload:
9435 23:59:31.672215 NAME | PORT | POLARITY | VALUE
9436 23:59:31.675555 EC in RW | 0x000000aa | low | undefined
9437 23:59:31.682609 EC interrupt | 0x00000005 | low | undefined
9438 23:59:31.685959 TPM interrupt | 0x000000ab | high | undefined
9439 23:59:31.692432 SD card detect | 0x00000011 | high | undefined
9440 23:59:31.695639 speaker enable | 0x00000093 | high | undefined
9441 23:59:31.699258 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9442 23:59:31.702479 in-header: 03 f9 00 00 02 00 00 00
9443 23:59:31.705791 in-data: 02 00
9444 23:59:31.709149 ADC[4]: Raw value=904357 ID=7
9445 23:59:31.712460 ADC[3]: Raw value=213441 ID=1
9446 23:59:31.712596 RAM Code: 0x71
9447 23:59:31.715702 ADC[6]: Raw value=75701 ID=0
9448 23:59:31.718809 ADC[5]: Raw value=213072 ID=1
9449 23:59:31.718943 SKU Code: 0x1
9450 23:59:31.725769 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7651
9451 23:59:31.725930 coreboot table: 964 bytes.
9452 23:59:31.729021 IMD ROOT 0. 0xfffff000 0x00001000
9453 23:59:31.732011 IMD SMALL 1. 0xffffe000 0x00001000
9454 23:59:31.735647 RO MCACHE 2. 0xffffc000 0x00001104
9455 23:59:31.738706 CONSOLE 3. 0xfff7c000 0x00080000
9456 23:59:31.741914 FMAP 4. 0xfff7b000 0x00000452
9457 23:59:31.745289 TIME STAMP 5. 0xfff7a000 0x00000910
9458 23:59:31.748849 VBOOT WORK 6. 0xfff66000 0x00014000
9459 23:59:31.752040 RAMOOPS 7. 0xffe66000 0x00100000
9460 23:59:31.755250 COREBOOT 8. 0xffe64000 0x00002000
9461 23:59:31.758493 IMD small region:
9462 23:59:31.762408 IMD ROOT 0. 0xffffec00 0x00000400
9463 23:59:31.765373 VPD 1. 0xffffeb80 0x0000006c
9464 23:59:31.768901 MMC STATUS 2. 0xffffeb60 0x00000004
9465 23:59:31.772206 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9466 23:59:31.775416 Probing TPM: done!
9467 23:59:31.779337 Connected to device vid:did:rid of 1ae0:0028:00
9468 23:59:31.789923 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9469 23:59:31.793628 Initialized TPM device CR50 revision 0
9470 23:59:31.796844 Checking cr50 for pending updates
9471 23:59:31.800825 Reading cr50 TPM mode
9472 23:59:31.809530 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9473 23:59:31.816484 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9474 23:59:31.856558 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9475 23:59:31.859738 Checking segment from ROM address 0x40100000
9476 23:59:31.863360 Checking segment from ROM address 0x4010001c
9477 23:59:31.869813 Loading segment from ROM address 0x40100000
9478 23:59:31.869968 code (compression=0)
9479 23:59:31.876782 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9480 23:59:31.886896 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9481 23:59:31.887035 it's not compressed!
9482 23:59:31.893223 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9483 23:59:31.896510 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9484 23:59:31.916818 Loading segment from ROM address 0x4010001c
9485 23:59:31.917015 Entry Point 0x80000000
9486 23:59:31.919702 Loaded segments
9487 23:59:31.923575 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9488 23:59:31.930096 Jumping to boot code at 0x80000000(0xffe64000)
9489 23:59:31.936450 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9490 23:59:31.943472 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9491 23:59:31.951348 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9492 23:59:31.954387 Checking segment from ROM address 0x40100000
9493 23:59:31.957705 Checking segment from ROM address 0x4010001c
9494 23:59:31.964600 Loading segment from ROM address 0x40100000
9495 23:59:31.964698 code (compression=1)
9496 23:59:31.971549 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9497 23:59:31.980970 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9498 23:59:31.981098 using LZMA
9499 23:59:31.989393 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9500 23:59:31.996274 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9501 23:59:31.999549 Loading segment from ROM address 0x4010001c
9502 23:59:31.999672 Entry Point 0x54601000
9503 23:59:32.002792 Loaded segments
9504 23:59:32.005974 NOTICE: MT8192 bl31_setup
9505 23:59:32.013161 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9506 23:59:32.016335 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9507 23:59:32.019553 WARNING: region 0:
9508 23:59:32.023425 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 23:59:32.023555 WARNING: region 1:
9510 23:59:32.029958 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9511 23:59:32.033231 WARNING: region 2:
9512 23:59:32.036387 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9513 23:59:32.039501 WARNING: region 3:
9514 23:59:32.043253 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 23:59:32.046590 WARNING: region 4:
9516 23:59:32.049714 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9517 23:59:32.053425 WARNING: region 5:
9518 23:59:32.056216 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 23:59:32.059925 WARNING: region 6:
9520 23:59:32.063071 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 23:59:32.063160 WARNING: region 7:
9522 23:59:32.070271 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 23:59:32.076473 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9524 23:59:32.080035 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9525 23:59:32.083647 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9526 23:59:32.090160 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9527 23:59:32.093335 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9528 23:59:32.097077 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9529 23:59:32.103091 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9530 23:59:32.106444 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9531 23:59:32.109726 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9532 23:59:32.116850 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9533 23:59:32.120263 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9534 23:59:32.123407 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9535 23:59:32.130000 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9536 23:59:32.133636 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9537 23:59:32.140682 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9538 23:59:32.143678 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9539 23:59:32.146824 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9540 23:59:32.153691 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9541 23:59:32.156818 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9542 23:59:32.160583 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9543 23:59:32.167219 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9544 23:59:32.170595 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9545 23:59:32.177040 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9546 23:59:32.180243 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9547 23:59:32.183888 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9548 23:59:32.190306 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9549 23:59:32.193766 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9550 23:59:32.200207 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9551 23:59:32.203401 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9552 23:59:32.207200 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9553 23:59:32.213613 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9554 23:59:32.216866 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9555 23:59:32.220288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9556 23:59:32.227048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9557 23:59:32.230713 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9558 23:59:32.234058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9559 23:59:32.237257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9560 23:59:32.244079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9561 23:59:32.247149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9562 23:59:32.250435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9563 23:59:32.254089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9564 23:59:32.257249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9565 23:59:32.263672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9566 23:59:32.267295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9567 23:59:32.270279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9568 23:59:32.277376 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9569 23:59:32.280632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9570 23:59:32.283891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9571 23:59:32.287124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9572 23:59:32.294191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9573 23:59:32.297237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9574 23:59:32.303902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9575 23:59:32.307240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9576 23:59:32.313713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9577 23:59:32.317542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9578 23:59:32.320212 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9579 23:59:32.327208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9580 23:59:32.330334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9581 23:59:32.337544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9582 23:59:32.340777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9583 23:59:32.347341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9584 23:59:32.350896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9585 23:59:32.354094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9586 23:59:32.360671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9587 23:59:32.364258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9588 23:59:32.370571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9589 23:59:32.373785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9590 23:59:32.380517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9591 23:59:32.383699 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9592 23:59:32.387027 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9593 23:59:32.393982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9594 23:59:32.397179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9595 23:59:32.404125 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9596 23:59:32.407136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9597 23:59:32.413847 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9598 23:59:32.417145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9599 23:59:32.423595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9600 23:59:32.426804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9601 23:59:32.430691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9602 23:59:32.437128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9603 23:59:32.440305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9604 23:59:32.447466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9605 23:59:32.450693 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9606 23:59:32.457325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9607 23:59:32.460230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9608 23:59:32.463587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9609 23:59:32.470372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9610 23:59:32.473898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9611 23:59:32.480223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9612 23:59:32.483670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9613 23:59:32.490571 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9614 23:59:32.494047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9615 23:59:32.497221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9616 23:59:32.503612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9617 23:59:32.507460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9618 23:59:32.513753 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9619 23:59:32.517418 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9620 23:59:32.520544 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9621 23:59:32.523798 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9622 23:59:32.530431 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9623 23:59:32.533674 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9624 23:59:32.536962 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9625 23:59:32.543975 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9626 23:59:32.547184 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9627 23:59:32.553597 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9628 23:59:32.557241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9629 23:59:32.560734 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9630 23:59:32.567367 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9631 23:59:32.570246 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9632 23:59:32.576960 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9633 23:59:32.581015 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9634 23:59:32.584012 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9635 23:59:32.590462 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9636 23:59:32.593571 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9637 23:59:32.600924 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9638 23:59:32.604177 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9639 23:59:32.607137 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9640 23:59:32.610441 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9641 23:59:32.617255 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9642 23:59:32.620421 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9643 23:59:32.624129 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9644 23:59:32.627475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9645 23:59:32.633897 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9646 23:59:32.637180 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9647 23:59:32.640359 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9648 23:59:32.647496 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9649 23:59:32.650715 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9650 23:59:32.657192 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9651 23:59:32.660444 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9652 23:59:32.664135 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9653 23:59:32.670548 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9654 23:59:32.673719 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9655 23:59:32.677582 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9656 23:59:32.683785 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9657 23:59:32.687623 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9658 23:59:32.693896 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9659 23:59:32.697536 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9660 23:59:32.700710 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9661 23:59:32.707291 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9662 23:59:32.710986 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9663 23:59:32.717660 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9664 23:59:32.720530 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9665 23:59:32.723873 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9666 23:59:32.730662 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9667 23:59:32.733793 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9668 23:59:32.737151 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9669 23:59:32.744231 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9670 23:59:32.747393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9671 23:59:32.753928 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9672 23:59:32.757130 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9673 23:59:32.760961 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9674 23:59:32.767350 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9675 23:59:32.770567 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9676 23:59:32.777663 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9677 23:59:32.780916 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9678 23:59:32.784053 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9679 23:59:32.790543 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9680 23:59:32.794119 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9681 23:59:32.797369 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9682 23:59:32.803951 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9683 23:59:32.807193 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9684 23:59:32.814250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9685 23:59:32.817380 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9686 23:59:32.820474 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9687 23:59:32.827169 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9688 23:59:32.830255 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9689 23:59:32.837190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9690 23:59:32.840106 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9691 23:59:32.843605 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9692 23:59:32.850246 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9693 23:59:32.853491 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9694 23:59:32.860545 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9695 23:59:32.863903 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9696 23:59:32.867042 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9697 23:59:32.873992 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9698 23:59:32.877396 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9699 23:59:32.883702 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9700 23:59:32.886974 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9701 23:59:32.890314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9702 23:59:32.896734 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9703 23:59:32.899842 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9704 23:59:32.903537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9705 23:59:32.910338 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9706 23:59:32.913463 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9707 23:59:32.920485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9708 23:59:32.923721 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9709 23:59:32.926831 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9710 23:59:32.933527 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9711 23:59:32.936660 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9712 23:59:32.943118 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9713 23:59:32.946329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9714 23:59:32.953309 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9715 23:59:32.956395 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9716 23:59:32.959704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9717 23:59:32.966470 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9718 23:59:32.969867 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9719 23:59:32.976371 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9720 23:59:32.980133 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9721 23:59:32.983392 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9722 23:59:32.989789 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9723 23:59:32.993015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9724 23:59:32.999690 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9725 23:59:33.002678 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9726 23:59:33.010045 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9727 23:59:33.012950 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9728 23:59:33.016694 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9729 23:59:33.022754 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9730 23:59:33.026139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9731 23:59:33.033196 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9732 23:59:33.036352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9733 23:59:33.039672 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9734 23:59:33.046049 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9735 23:59:33.049921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9736 23:59:33.056379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9737 23:59:33.059605 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9738 23:59:33.063442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9739 23:59:33.069780 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9740 23:59:33.073044 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9741 23:59:33.079468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9742 23:59:33.083132 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9743 23:59:33.089456 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9744 23:59:33.092999 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9745 23:59:33.096122 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9746 23:59:33.102898 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9747 23:59:33.105868 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9748 23:59:33.112894 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9749 23:59:33.116157 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9750 23:59:33.119198 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9751 23:59:33.126060 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9752 23:59:33.129105 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9753 23:59:33.132996 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9754 23:59:33.136114 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9755 23:59:33.142493 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9756 23:59:33.146300 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9757 23:59:33.149266 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9758 23:59:33.156121 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9759 23:59:33.159356 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9760 23:59:33.166107 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9761 23:59:33.169320 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9762 23:59:33.172572 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9763 23:59:33.179032 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9764 23:59:33.182176 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9765 23:59:33.185848 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9766 23:59:33.192402 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9767 23:59:33.195676 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9768 23:59:33.198787 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9769 23:59:33.205812 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9770 23:59:33.208917 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9771 23:59:33.212387 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9772 23:59:33.219570 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9773 23:59:33.222582 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9774 23:59:33.228796 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9775 23:59:33.232426 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9776 23:59:33.235603 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9777 23:59:33.242046 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9778 23:59:33.245878 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9779 23:59:33.249141 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9780 23:59:33.255447 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9781 23:59:33.259107 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9782 23:59:33.262148 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9783 23:59:33.269100 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9784 23:59:33.272297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9785 23:59:33.279262 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9786 23:59:33.282539 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9787 23:59:33.285720 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9788 23:59:33.292181 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9789 23:59:33.296081 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9790 23:59:33.299151 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9791 23:59:33.305860 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9792 23:59:33.309284 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9793 23:59:33.312309 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9794 23:59:33.315625 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9795 23:59:33.318789 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9796 23:59:33.325581 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9797 23:59:33.328964 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9798 23:59:33.332065 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9799 23:59:33.335813 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9800 23:59:33.342570 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9801 23:59:33.345473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9802 23:59:33.349250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9803 23:59:33.355643 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9804 23:59:33.359183 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9805 23:59:33.362175 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9806 23:59:33.368975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9807 23:59:33.372646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9808 23:59:33.375613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9809 23:59:33.382763 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9810 23:59:33.386054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9811 23:59:33.392308 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9812 23:59:33.395556 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9813 23:59:33.398783 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9814 23:59:33.405407 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9815 23:59:33.409140 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9816 23:59:33.415671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9817 23:59:33.418720 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9818 23:59:33.425523 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9819 23:59:33.428690 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9820 23:59:33.432425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9821 23:59:33.439074 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9822 23:59:33.442330 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9823 23:59:33.448842 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9824 23:59:33.451857 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9825 23:59:33.455296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9826 23:59:33.461949 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9827 23:59:33.465171 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9828 23:59:33.472041 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9829 23:59:33.475309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9830 23:59:33.478363 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9831 23:59:33.484891 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9832 23:59:33.488693 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9833 23:59:33.495158 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9834 23:59:33.498353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9835 23:59:33.505045 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9836 23:59:33.508464 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9837 23:59:33.511643 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9838 23:59:33.518280 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9839 23:59:33.521306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9840 23:59:33.528154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9841 23:59:33.531280 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9842 23:59:33.534589 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9843 23:59:33.541437 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9844 23:59:33.544594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9845 23:59:33.551515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9846 23:59:33.554467 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9847 23:59:33.557783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9848 23:59:33.564549 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9849 23:59:33.567617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9850 23:59:33.574437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9851 23:59:33.577774 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9852 23:59:33.581288 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9853 23:59:33.587801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9854 23:59:33.591402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9855 23:59:33.597997 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9856 23:59:33.601279 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9857 23:59:33.607816 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9858 23:59:33.611003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9859 23:59:33.614211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9860 23:59:33.620791 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9861 23:59:33.624021 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9862 23:59:33.631340 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9863 23:59:33.634196 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9864 23:59:33.637670 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9865 23:59:33.644487 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9866 23:59:33.647460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9867 23:59:33.654056 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9868 23:59:33.657321 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9869 23:59:33.660555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9870 23:59:33.667845 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9871 23:59:33.670604 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9872 23:59:33.677252 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9873 23:59:33.680591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9874 23:59:33.683924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9875 23:59:33.690701 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9876 23:59:33.694000 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9877 23:59:33.700502 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9878 23:59:33.704042 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9879 23:59:33.710969 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9880 23:59:33.713744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9881 23:59:33.717236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9882 23:59:33.723898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9883 23:59:33.727097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9884 23:59:33.734298 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9885 23:59:33.736924 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9886 23:59:33.743781 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9887 23:59:33.747236 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9888 23:59:33.753766 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9889 23:59:33.756959 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9890 23:59:33.760197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9891 23:59:33.766712 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9892 23:59:33.770554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9893 23:59:33.777003 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9894 23:59:33.780311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9895 23:59:33.786672 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9896 23:59:33.790451 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9897 23:59:33.793632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9898 23:59:33.800039 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9899 23:59:33.803702 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9900 23:59:33.810688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9901 23:59:33.813555 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9902 23:59:33.820484 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9903 23:59:33.823677 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9904 23:59:33.826898 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9905 23:59:33.833836 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9906 23:59:33.837127 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9907 23:59:33.843829 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9908 23:59:33.846556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9909 23:59:33.853754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9910 23:59:33.856843 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9911 23:59:33.859903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9912 23:59:33.867047 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9913 23:59:33.870240 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9914 23:59:33.877041 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9915 23:59:33.880396 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9916 23:59:33.886547 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9917 23:59:33.889724 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9918 23:59:33.893441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9919 23:59:33.899668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9920 23:59:33.903512 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9921 23:59:33.909713 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9922 23:59:33.913251 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9923 23:59:33.920407 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9924 23:59:33.923275 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9925 23:59:33.926456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9926 23:59:33.933377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9927 23:59:33.936775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9928 23:59:33.943454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9929 23:59:33.946452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9930 23:59:33.952870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9931 23:59:33.956548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9932 23:59:33.962979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9933 23:59:33.966355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9934 23:59:33.973220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9935 23:59:33.976476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9936 23:59:33.982711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9937 23:59:33.985965 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9938 23:59:33.992476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9939 23:59:33.996186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9940 23:59:34.002845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9941 23:59:34.006077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9942 23:59:34.009268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9943 23:59:34.016142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9944 23:59:34.019193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9945 23:59:34.025992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9946 23:59:34.029652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9947 23:59:34.036018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9948 23:59:34.039113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9949 23:59:34.045847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9950 23:59:34.048989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9951 23:59:34.056108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9952 23:59:34.059347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9953 23:59:34.066256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9954 23:59:34.068917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9955 23:59:34.076051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9956 23:59:34.082368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9957 23:59:34.085303 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9958 23:59:34.085449 INFO: [APUAPC] vio 0
9959 23:59:34.092736 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9960 23:59:34.095922 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9961 23:59:34.099892 INFO: [APUAPC] D0_APC_0: 0x400510
9962 23:59:34.103022 INFO: [APUAPC] D0_APC_1: 0x0
9963 23:59:34.105958 INFO: [APUAPC] D0_APC_2: 0x1540
9964 23:59:34.109616 INFO: [APUAPC] D0_APC_3: 0x0
9965 23:59:34.112828 INFO: [APUAPC] D1_APC_0: 0xffffffff
9966 23:59:34.115967 INFO: [APUAPC] D1_APC_1: 0xffffffff
9967 23:59:34.119172 INFO: [APUAPC] D1_APC_2: 0x3fffff
9968 23:59:34.122291 INFO: [APUAPC] D1_APC_3: 0x0
9969 23:59:34.126094 INFO: [APUAPC] D2_APC_0: 0xffffffff
9970 23:59:34.129230 INFO: [APUAPC] D2_APC_1: 0xffffffff
9971 23:59:34.132529 INFO: [APUAPC] D2_APC_2: 0x3fffff
9972 23:59:34.135778 INFO: [APUAPC] D2_APC_3: 0x0
9973 23:59:34.138971 INFO: [APUAPC] D3_APC_0: 0xffffffff
9974 23:59:34.142749 INFO: [APUAPC] D3_APC_1: 0xffffffff
9975 23:59:34.145917 INFO: [APUAPC] D3_APC_2: 0x3fffff
9976 23:59:34.148972 INFO: [APUAPC] D3_APC_3: 0x0
9977 23:59:34.152504 INFO: [APUAPC] D4_APC_0: 0xffffffff
9978 23:59:34.155694 INFO: [APUAPC] D4_APC_1: 0xffffffff
9979 23:59:34.159141 INFO: [APUAPC] D4_APC_2: 0x3fffff
9980 23:59:34.159254 INFO: [APUAPC] D4_APC_3: 0x0
9981 23:59:34.165864 INFO: [APUAPC] D5_APC_0: 0xffffffff
9982 23:59:34.169083 INFO: [APUAPC] D5_APC_1: 0xffffffff
9983 23:59:34.172231 INFO: [APUAPC] D5_APC_2: 0x3fffff
9984 23:59:34.172350 INFO: [APUAPC] D5_APC_3: 0x0
9985 23:59:34.175481 INFO: [APUAPC] D6_APC_0: 0xffffffff
9986 23:59:34.182009 INFO: [APUAPC] D6_APC_1: 0xffffffff
9987 23:59:34.185227 INFO: [APUAPC] D6_APC_2: 0x3fffff
9988 23:59:34.185347 INFO: [APUAPC] D6_APC_3: 0x0
9989 23:59:34.189213 INFO: [APUAPC] D7_APC_0: 0xffffffff
9990 23:59:34.191782 INFO: [APUAPC] D7_APC_1: 0xffffffff
9991 23:59:34.195134 INFO: [APUAPC] D7_APC_2: 0x3fffff
9992 23:59:34.198991 INFO: [APUAPC] D7_APC_3: 0x0
9993 23:59:34.202239 INFO: [APUAPC] D8_APC_0: 0xffffffff
9994 23:59:34.205639 INFO: [APUAPC] D8_APC_1: 0xffffffff
9995 23:59:34.208732 INFO: [APUAPC] D8_APC_2: 0x3fffff
9996 23:59:34.211802 INFO: [APUAPC] D8_APC_3: 0x0
9997 23:59:34.215464 INFO: [APUAPC] D9_APC_0: 0xffffffff
9998 23:59:34.218419 INFO: [APUAPC] D9_APC_1: 0xffffffff
9999 23:59:34.222271 INFO: [APUAPC] D9_APC_2: 0x3fffff
10000 23:59:34.225489 INFO: [APUAPC] D9_APC_3: 0x0
10001 23:59:34.228672 INFO: [APUAPC] D10_APC_0: 0xffffffff
10002 23:59:34.231888 INFO: [APUAPC] D10_APC_1: 0xffffffff
10003 23:59:34.235093 INFO: [APUAPC] D10_APC_2: 0x3fffff
10004 23:59:34.238801 INFO: [APUAPC] D10_APC_3: 0x0
10005 23:59:34.242246 INFO: [APUAPC] D11_APC_0: 0xffffffff
10006 23:59:34.245657 INFO: [APUAPC] D11_APC_1: 0xffffffff
10007 23:59:34.248886 INFO: [APUAPC] D11_APC_2: 0x3fffff
10008 23:59:34.252000 INFO: [APUAPC] D11_APC_3: 0x0
10009 23:59:34.255600 INFO: [APUAPC] D12_APC_0: 0xffffffff
10010 23:59:34.258546 INFO: [APUAPC] D12_APC_1: 0xffffffff
10011 23:59:34.262394 INFO: [APUAPC] D12_APC_2: 0x3fffff
10012 23:59:34.265438 INFO: [APUAPC] D12_APC_3: 0x0
10013 23:59:34.268526 INFO: [APUAPC] D13_APC_0: 0xffffffff
10014 23:59:34.271907 INFO: [APUAPC] D13_APC_1: 0xffffffff
10015 23:59:34.275618 INFO: [APUAPC] D13_APC_2: 0x3fffff
10016 23:59:34.278842 INFO: [APUAPC] D13_APC_3: 0x0
10017 23:59:34.281964 INFO: [APUAPC] D14_APC_0: 0xffffffff
10018 23:59:34.285151 INFO: [APUAPC] D14_APC_1: 0xffffffff
10019 23:59:34.288485 INFO: [APUAPC] D14_APC_2: 0x3fffff
10020 23:59:34.292402 INFO: [APUAPC] D14_APC_3: 0x0
10021 23:59:34.295327 INFO: [APUAPC] D15_APC_0: 0xffffffff
10022 23:59:34.298858 INFO: [APUAPC] D15_APC_1: 0xffffffff
10023 23:59:34.301800 INFO: [APUAPC] D15_APC_2: 0x3fffff
10024 23:59:34.305680 INFO: [APUAPC] D15_APC_3: 0x0
10025 23:59:34.308856 INFO: [APUAPC] APC_CON: 0x4
10026 23:59:34.312300 INFO: [NOCDAPC] D0_APC_0: 0x0
10027 23:59:34.315485 INFO: [NOCDAPC] D0_APC_1: 0x0
10028 23:59:34.318759 INFO: [NOCDAPC] D1_APC_0: 0x0
10029 23:59:34.321997 INFO: [NOCDAPC] D1_APC_1: 0xfff
10030 23:59:34.322114 INFO: [NOCDAPC] D2_APC_0: 0x0
10031 23:59:34.325013 INFO: [NOCDAPC] D2_APC_1: 0xfff
10032 23:59:34.328463 INFO: [NOCDAPC] D3_APC_0: 0x0
10033 23:59:34.331592 INFO: [NOCDAPC] D3_APC_1: 0xfff
10034 23:59:34.335402 INFO: [NOCDAPC] D4_APC_0: 0x0
10035 23:59:34.338724 INFO: [NOCDAPC] D4_APC_1: 0xfff
10036 23:59:34.341826 INFO: [NOCDAPC] D5_APC_0: 0x0
10037 23:59:34.344995 INFO: [NOCDAPC] D5_APC_1: 0xfff
10038 23:59:34.348249 INFO: [NOCDAPC] D6_APC_0: 0x0
10039 23:59:34.352007 INFO: [NOCDAPC] D6_APC_1: 0xfff
10040 23:59:34.355010 INFO: [NOCDAPC] D7_APC_0: 0x0
10041 23:59:34.355122 INFO: [NOCDAPC] D7_APC_1: 0xfff
10042 23:59:34.358531 INFO: [NOCDAPC] D8_APC_0: 0x0
10043 23:59:34.361846 INFO: [NOCDAPC] D8_APC_1: 0xfff
10044 23:59:34.364952 INFO: [NOCDAPC] D9_APC_0: 0x0
10045 23:59:34.368213 INFO: [NOCDAPC] D9_APC_1: 0xfff
10046 23:59:34.371349 INFO: [NOCDAPC] D10_APC_0: 0x0
10047 23:59:34.374862 INFO: [NOCDAPC] D10_APC_1: 0xfff
10048 23:59:34.378132 INFO: [NOCDAPC] D11_APC_0: 0x0
10049 23:59:34.381335 INFO: [NOCDAPC] D11_APC_1: 0xfff
10050 23:59:34.384504 INFO: [NOCDAPC] D12_APC_0: 0x0
10051 23:59:34.388290 INFO: [NOCDAPC] D12_APC_1: 0xfff
10052 23:59:34.391480 INFO: [NOCDAPC] D13_APC_0: 0x0
10053 23:59:34.394635 INFO: [NOCDAPC] D13_APC_1: 0xfff
10054 23:59:34.398470 INFO: [NOCDAPC] D14_APC_0: 0x0
10055 23:59:34.401636 INFO: [NOCDAPC] D14_APC_1: 0xfff
10056 23:59:34.401734 INFO: [NOCDAPC] D15_APC_0: 0x0
10057 23:59:34.404832 INFO: [NOCDAPC] D15_APC_1: 0xfff
10058 23:59:34.407876 INFO: [NOCDAPC] APC_CON: 0x4
10059 23:59:34.411456 INFO: [APUAPC] set_apusys_apc done
10060 23:59:34.414760 INFO: [DEVAPC] devapc_init done
10061 23:59:34.417877 INFO: GICv3 without legacy support detected.
10062 23:59:34.424834 INFO: ARM GICv3 driver initialized in EL3
10063 23:59:34.427917 INFO: Maximum SPI INTID supported: 639
10064 23:59:34.431488 INFO: BL31: Initializing runtime services
10065 23:59:34.437620 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10066 23:59:34.441059 INFO: SPM: enable CPC mode
10067 23:59:34.444109 INFO: mcdi ready for mcusys-off-idle and system suspend
10068 23:59:34.451100 INFO: BL31: Preparing for EL3 exit to normal world
10069 23:59:34.454401 INFO: Entry point address = 0x80000000
10070 23:59:34.454495 INFO: SPSR = 0x8
10071 23:59:34.460642
10072 23:59:34.460730
10073 23:59:34.460800
10074 23:59:34.464344 Starting depthcharge on Spherion...
10075 23:59:34.464436
10076 23:59:34.464506 Wipe memory regions:
10077 23:59:34.464571
10078 23:59:34.465239 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10079 23:59:34.465349 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10080 23:59:34.465449 Setting prompt string to ['asurada:']
10081 23:59:34.465535 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10082 23:59:34.467410 [0x00000040000000, 0x00000054600000)
10083 23:59:34.589860
10084 23:59:34.590084 [0x00000054660000, 0x00000080000000)
10085 23:59:34.850121
10086 23:59:34.850341 [0x000000821a7280, 0x000000ffe64000)
10087 23:59:35.595189
10088 23:59:35.595406 [0x00000100000000, 0x00000240000000)
10089 23:59:37.485135
10090 23:59:37.488144 Initializing XHCI USB controller at 0x11200000.
10091 23:59:38.525768
10092 23:59:38.528720 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10093 23:59:38.528861
10094 23:59:38.528975
10095 23:59:38.529334 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 23:59:38.629807 asurada: tftpboot 192.168.201.1 14084370/tftp-deploy-psre5b8m/kernel/image.itb 14084370/tftp-deploy-psre5b8m/kernel/cmdline
10098 23:59:38.630047 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 23:59:38.630178 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10100 23:59:38.634487 tftpboot 192.168.201.1 14084370/tftp-deploy-psre5b8m/kernel/image.itp-deploy-psre5b8m/kernel/cmdline
10101 23:59:38.634590
10102 23:59:38.634662 Waiting for link
10103 23:59:38.795580
10104 23:59:38.795744 R8152: Initializing
10105 23:59:38.795816
10106 23:59:38.798607 Version 9 (ocp_data = 6010)
10107 23:59:38.798710
10108 23:59:38.801777 R8152: Done initializing
10109 23:59:38.801869
10110 23:59:38.801938 Adding net device
10111 23:59:40.746894
10112 23:59:40.747061 done.
10113 23:59:40.747135
10114 23:59:40.747200 MAC: 00:e0:4c:78:7a:aa
10115 23:59:40.747262
10116 23:59:40.750507 Sending DHCP discover... done.
10117 23:59:40.750608
10118 23:59:40.753583 Waiting for reply... done.
10119 23:59:40.753681
10120 23:59:40.757032 Sending DHCP request... done.
10121 23:59:40.757129
10122 23:59:40.762456 Waiting for reply... done.
10123 23:59:40.762575
10124 23:59:40.762649 My ip is 192.168.201.12
10125 23:59:40.762713
10126 23:59:40.765393 The DHCP server ip is 192.168.201.1
10127 23:59:40.765483
10128 23:59:40.771989 TFTP server IP predefined by user: 192.168.201.1
10129 23:59:40.772155
10130 23:59:40.778688 Bootfile predefined by user: 14084370/tftp-deploy-psre5b8m/kernel/image.itb
10131 23:59:40.778856
10132 23:59:40.782084 Sending tftp read request... done.
10133 23:59:40.782223
10134 23:59:40.785540 Waiting for the transfer...
10135 23:59:40.785646
10136 23:59:41.041403 00000000 ################################################################
10137 23:59:41.041578
10138 23:59:41.302317 00080000 ################################################################
10139 23:59:41.302503
10140 23:59:41.555738 00100000 ################################################################
10141 23:59:41.555899
10142 23:59:41.817377 00180000 ################################################################
10143 23:59:41.817531
10144 23:59:42.076316 00200000 ################################################################
10145 23:59:42.076484
10146 23:59:42.334671 00280000 ################################################################
10147 23:59:42.334831
10148 23:59:42.587290 00300000 ################################################################
10149 23:59:42.587459
10150 23:59:42.844053 00380000 ################################################################
10151 23:59:42.844244
10152 23:59:43.101445 00400000 ################################################################
10153 23:59:43.101605
10154 23:59:43.361472 00480000 ################################################################
10155 23:59:43.361661
10156 23:59:43.617418 00500000 ################################################################
10157 23:59:43.617645
10158 23:59:43.877259 00580000 ################################################################
10159 23:59:43.877478
10160 23:59:44.147114 00600000 ################################################################
10161 23:59:44.147257
10162 23:59:44.409496 00680000 ################################################################
10163 23:59:44.409677
10164 23:59:44.669557 00700000 ################################################################
10165 23:59:44.669709
10166 23:59:44.929101 00780000 ################################################################
10167 23:59:44.929236
10168 23:59:45.188359 00800000 ################################################################
10169 23:59:45.188498
10170 23:59:45.440712 00880000 ################################################################
10171 23:59:45.440917
10172 23:59:45.692855 00900000 ################################################################
10173 23:59:45.693025
10174 23:59:45.945605 00980000 ################################################################
10175 23:59:45.945748
10176 23:59:46.200696 00a00000 ################################################################
10177 23:59:46.200835
10178 23:59:46.459369 00a80000 ################################################################
10179 23:59:46.459510
10180 23:59:46.717054 00b00000 ################################################################
10181 23:59:46.717251
10182 23:59:46.971488 00b80000 ################################################################
10183 23:59:46.971660
10184 23:59:47.230454 00c00000 ################################################################
10185 23:59:47.230659
10186 23:59:47.487306 00c80000 ################################################################
10187 23:59:47.487450
10188 23:59:47.742830 00d00000 ################################################################
10189 23:59:47.743029
10190 23:59:47.994761 00d80000 ################################################################
10191 23:59:47.994977
10192 23:59:48.248948 00e00000 ################################################################
10193 23:59:48.249112
10194 23:59:48.503865 00e80000 ################################################################
10195 23:59:48.504036
10196 23:59:48.762950 00f00000 ################################################################
10197 23:59:48.763127
10198 23:59:49.009300 00f80000 ################################################################
10199 23:59:49.009488
10200 23:59:49.253986 01000000 ################################################################
10201 23:59:49.254163
10202 23:59:49.501297 01080000 ################################################################
10203 23:59:49.501475
10204 23:59:49.749938 01100000 ################################################################
10205 23:59:49.750116
10206 23:59:50.015350 01180000 ################################################################
10207 23:59:50.015526
10208 23:59:50.268736 01200000 ################################################################
10209 23:59:50.268936
10210 23:59:50.532413 01280000 ################################################################
10211 23:59:50.532559
10212 23:59:50.790719 01300000 ################################################################
10213 23:59:50.790906
10214 23:59:51.038900 01380000 ################################################################
10215 23:59:51.039114
10216 23:59:51.291745 01400000 ################################################################
10217 23:59:51.291901
10218 23:59:51.544131 01480000 ################################################################
10219 23:59:51.544332
10220 23:59:51.812293 01500000 ################################################################
10221 23:59:51.812503
10222 23:59:52.068500 01580000 ################################################################
10223 23:59:52.068724
10224 23:59:52.319833 01600000 ################################################################
10225 23:59:52.319986
10226 23:59:52.579253 01680000 ################################################################
10227 23:59:52.579432
10228 23:59:52.833291 01700000 ################################################################
10229 23:59:52.833472
10230 23:59:53.083456 01780000 ################################################################
10231 23:59:53.083644
10232 23:59:53.334991 01800000 ################################################################
10233 23:59:53.335145
10234 23:59:53.586680 01880000 ################################################################
10235 23:59:53.586864
10236 23:59:53.838228 01900000 ################################################################
10237 23:59:53.838403
10238 23:59:54.091621 01980000 ################################################################
10239 23:59:54.091779
10240 23:59:54.346260 01a00000 ################################################################
10241 23:59:54.346457
10242 23:59:54.599080 01a80000 ################################################################
10243 23:59:54.599319
10244 23:59:54.848159 01b00000 ################################################################
10245 23:59:54.848387
10246 23:59:55.110349 01b80000 ################################################################
10247 23:59:55.110494
10248 23:59:55.360283 01c00000 ################################################################
10249 23:59:55.360450
10250 23:59:55.608714 01c80000 ################################################################
10251 23:59:55.608857
10252 23:59:55.862770 01d00000 ################################################################
10253 23:59:55.862946
10254 23:59:56.115704 01d80000 ################################################################
10255 23:59:56.115843
10256 23:59:56.302831 01e00000 ################################################ done.
10257 23:59:56.303002
10258 23:59:56.306068 The bootfile was 31842738 bytes long.
10259 23:59:56.306190
10260 23:59:56.308949 Sending tftp read request... done.
10261 23:59:56.309063
10262 23:59:56.309179 Waiting for the transfer...
10263 23:59:56.309306
10264 23:59:56.312163 00000000 # done.
10265 23:59:56.312283
10266 23:59:56.318890 Command line loaded dynamically from TFTP file: 14084370/tftp-deploy-psre5b8m/kernel/cmdline
10267 23:59:56.319016
10268 23:59:56.341779 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10269 23:59:56.341899
10270 23:59:56.341971 Loading FIT.
10271 23:59:56.342034
10272 23:59:56.345239 Image ramdisk-1 has 18729957 bytes.
10273 23:59:56.345327
10274 23:59:56.348972 Image fdt-1 has 47258 bytes.
10275 23:59:56.349085
10276 23:59:56.352031 Image kernel-1 has 13063488 bytes.
10277 23:59:56.352140
10278 23:59:56.361729 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10279 23:59:56.361850
10280 23:59:56.378667 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10281 23:59:56.378776
10282 23:59:56.385148 Choosing best match conf-1 for compat google,spherion-rev2.
10283 23:59:56.388228
10284 23:59:56.393063 Connected to device vid:did:rid of 1ae0:0028:00
10285 23:59:56.401363
10286 23:59:56.404069 tpm_get_response: command 0x17b, return code 0x0
10287 23:59:56.404178
10288 23:59:56.407557 ec_init: CrosEC protocol v3 supported (256, 248)
10289 23:59:56.411380
10290 23:59:56.414730 tpm_cleanup: add release locality here.
10291 23:59:56.414829
10292 23:59:56.414904 Shutting down all USB controllers.
10293 23:59:56.418169
10294 23:59:56.418289 Removing current net device
10295 23:59:56.418387
10296 23:59:56.424758 Exiting depthcharge with code 4 at timestamp: 51244622
10297 23:59:56.424853
10298 23:59:56.428192 LZMA decompressing kernel-1 to 0x821a6718
10299 23:59:56.428280
10300 23:59:56.431383 LZMA decompressing kernel-1 to 0x40000000
10301 23:59:58.042085
10302 23:59:58.042255 jumping to kernel
10303 23:59:58.043148 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10304 23:59:58.043281 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10305 23:59:58.043393 Setting prompt string to ['Linux version [0-9]']
10306 23:59:58.043501 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10307 23:59:58.043608 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10308 23:59:58.124280
10309 23:59:58.127768 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10310 23:59:58.131291 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10311 23:59:58.131463 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10312 23:59:58.131596 Setting prompt string to []
10313 23:59:58.131735 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10314 23:59:58.131868 Using line separator: #'\n'#
10315 23:59:58.131983 No login prompt set.
10316 23:59:58.132102 Parsing kernel messages
10317 23:59:58.132197 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10318 23:59:58.132403 [login-action] Waiting for messages, (timeout 00:04:02)
10319 23:59:58.132509 Waiting using forced prompt support (timeout 00:02:01)
10320 23:59:58.150218 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10321 23:59:58.153811 [ 0.000000] random: crng init done
10322 23:59:58.160370 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10323 23:59:58.163464 [ 0.000000] efi: UEFI not found.
10324 23:59:58.170568 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10325 23:59:58.180273 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10326 23:59:58.186974 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10327 23:59:58.196322 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10328 23:59:58.203186 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10329 23:59:58.209380 [ 0.000000] printk: bootconsole [mtk8250] enabled
10330 23:59:58.216410 [ 0.000000] NUMA: No NUMA configuration found
10331 23:59:58.223085 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10332 23:59:58.226284 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10333 23:59:58.229749 [ 0.000000] Zone ranges:
10334 23:59:58.236400 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10335 23:59:58.239817 [ 0.000000] DMA32 empty
10336 23:59:58.245953 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10337 23:59:58.249244 [ 0.000000] Movable zone start for each node
10338 23:59:58.252653 [ 0.000000] Early memory node ranges
10339 23:59:58.259375 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10340 23:59:58.266096 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10341 23:59:58.272915 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10342 23:59:58.279617 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10343 23:59:58.285729 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10344 23:59:58.292616 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10345 23:59:58.348869 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10346 23:59:58.355632 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10347 23:59:58.361912 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10348 23:59:58.365030 [ 0.000000] psci: probing for conduit method from DT.
10349 23:59:58.371659 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10350 23:59:58.375233 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10351 23:59:58.381658 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10352 23:59:58.385021 [ 0.000000] psci: SMC Calling Convention v1.2
10353 23:59:58.391844 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10354 23:59:58.395351 [ 0.000000] Detected VIPT I-cache on CPU0
10355 23:59:58.401499 [ 0.000000] CPU features: detected: GIC system register CPU interface
10356 23:59:58.408631 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10357 23:59:58.414991 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10358 23:59:58.421600 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10359 23:59:58.428575 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10360 23:59:58.437733 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10361 23:59:58.441017 [ 0.000000] alternatives: applying boot alternatives
10362 23:59:58.447734 [ 0.000000] Fallback order for Node 0: 0
10363 23:59:58.454266 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10364 23:59:58.457698 [ 0.000000] Policy zone: Normal
10365 23:59:58.480828 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10366 23:59:58.490709 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10367 23:59:58.501607 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10368 23:59:58.512041 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10369 23:59:58.518179 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10370 23:59:58.521500 <6>[ 0.000000] software IO TLB: area num 8.
10371 23:59:58.578403 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10372 23:59:58.727417 <6>[ 0.000000] Memory: 7945900K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406868K reserved, 32768K cma-reserved)
10373 23:59:58.734411 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10374 23:59:58.740555 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10375 23:59:58.744053 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10376 23:59:58.750616 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10377 23:59:58.757146 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10378 23:59:58.760317 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10379 23:59:58.770085 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10380 23:59:58.777043 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10381 23:59:58.783655 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10382 23:59:58.790042 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10383 23:59:58.793842 <6>[ 0.000000] GICv3: 608 SPIs implemented
10384 23:59:58.796915 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10385 23:59:58.803143 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10386 23:59:58.806532 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10387 23:59:58.813170 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10388 23:59:58.826343 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10389 23:59:58.839769 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10390 23:59:58.846524 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10391 23:59:58.853955 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10392 23:59:58.867489 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10393 23:59:58.873873 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10394 23:59:58.880392 <6>[ 0.009183] Console: colour dummy device 80x25
10395 23:59:58.890205 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10396 23:59:58.897018 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10397 23:59:58.900248 <6>[ 0.029256] LSM: Security Framework initializing
10398 23:59:58.907223 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10399 23:59:58.916646 <6>[ 0.042037] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10400 23:59:58.926381 <6>[ 0.051505] cblist_init_generic: Setting adjustable number of callback queues.
10401 23:59:58.929736 <6>[ 0.058951] cblist_init_generic: Setting shift to 3 and lim to 1.
10402 23:59:58.939899 <6>[ 0.065289] cblist_init_generic: Setting adjustable number of callback queues.
10403 23:59:58.946788 <6>[ 0.072716] cblist_init_generic: Setting shift to 3 and lim to 1.
10404 23:59:58.949549 <6>[ 0.079153] rcu: Hierarchical SRCU implementation.
10405 23:59:58.956055 <6>[ 0.084169] rcu: Max phase no-delay instances is 1000.
10406 23:59:58.962862 <6>[ 0.091240] EFI services will not be available.
10407 23:59:58.966211 <6>[ 0.096195] smp: Bringing up secondary CPUs ...
10408 23:59:58.974642 <6>[ 0.101273] Detected VIPT I-cache on CPU1
10409 23:59:58.981225 <6>[ 0.101345] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10410 23:59:58.987923 <6>[ 0.101375] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10411 23:59:58.991399 <6>[ 0.101712] Detected VIPT I-cache on CPU2
10412 23:59:59.001471 <6>[ 0.101762] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10413 23:59:59.007824 <6>[ 0.101779] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10414 23:59:59.011172 <6>[ 0.102039] Detected VIPT I-cache on CPU3
10415 23:59:59.017826 <6>[ 0.102087] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10416 23:59:59.024156 <6>[ 0.102100] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10417 23:59:59.027526 <6>[ 0.102403] CPU features: detected: Spectre-v4
10418 23:59:59.034631 <6>[ 0.102410] CPU features: detected: Spectre-BHB
10419 23:59:59.037589 <6>[ 0.102414] Detected PIPT I-cache on CPU4
10420 23:59:59.044704 <6>[ 0.102471] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10421 23:59:59.051032 <6>[ 0.102487] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10422 23:59:59.057765 <6>[ 0.102785] Detected PIPT I-cache on CPU5
10423 23:59:59.064613 <6>[ 0.102848] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10424 23:59:59.071388 <6>[ 0.102864] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10425 23:59:59.074552 <6>[ 0.103144] Detected PIPT I-cache on CPU6
10426 23:59:59.081656 <6>[ 0.103209] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10427 23:59:59.087262 <6>[ 0.103225] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10428 23:59:59.093777 <6>[ 0.103521] Detected PIPT I-cache on CPU7
10429 23:59:59.100648 <6>[ 0.103585] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10430 23:59:59.107241 <6>[ 0.103601] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10431 23:59:59.110520 <6>[ 0.103648] smp: Brought up 1 node, 8 CPUs
10432 23:59:59.117027 <6>[ 0.244847] SMP: Total of 8 processors activated.
10433 23:59:59.120298 <6>[ 0.249767] CPU features: detected: 32-bit EL0 Support
10434 23:59:59.130577 <6>[ 0.255129] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10435 23:59:59.137024 <6>[ 0.263930] CPU features: detected: Common not Private translations
10436 23:59:59.143476 <6>[ 0.270446] CPU features: detected: CRC32 instructions
10437 23:59:59.146698 <6>[ 0.275797] CPU features: detected: RCpc load-acquire (LDAPR)
10438 23:59:59.153533 <6>[ 0.281757] CPU features: detected: LSE atomic instructions
10439 23:59:59.159865 <6>[ 0.287538] CPU features: detected: Privileged Access Never
10440 23:59:59.166418 <6>[ 0.293318] CPU features: detected: RAS Extension Support
10441 23:59:59.173070 <6>[ 0.298927] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10442 23:59:59.176545 <6>[ 0.306191] CPU: All CPU(s) started at EL2
10443 23:59:59.183157 <6>[ 0.310508] alternatives: applying system-wide alternatives
10444 23:59:59.192227 <6>[ 0.321355] devtmpfs: initialized
10445 23:59:59.205135 <6>[ 0.330254] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10446 23:59:59.215053 <6>[ 0.340215] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10447 23:59:59.221468 <6>[ 0.348243] pinctrl core: initialized pinctrl subsystem
10448 23:59:59.224796 <6>[ 0.354891] DMI not present or invalid.
10449 23:59:59.231581 <6>[ 0.359306] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10450 23:59:59.241152 <6>[ 0.366196] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10451 23:59:59.247564 <6>[ 0.373782] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10452 23:59:59.257551 <6>[ 0.382004] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10453 23:59:59.261511 <6>[ 0.390245] audit: initializing netlink subsys (disabled)
10454 23:59:59.271156 <5>[ 0.395937] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10455 23:59:59.277578 <6>[ 0.396641] thermal_sys: Registered thermal governor 'step_wise'
10456 23:59:59.284312 <6>[ 0.403901] thermal_sys: Registered thermal governor 'power_allocator'
10457 23:59:59.287572 <6>[ 0.410157] cpuidle: using governor menu
10458 23:59:59.294229 <6>[ 0.421114] NET: Registered PF_QIPCRTR protocol family
10459 23:59:59.300752 <6>[ 0.426604] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10460 23:59:59.304314 <6>[ 0.433707] ASID allocator initialised with 32768 entries
10461 23:59:59.311735 <6>[ 0.440260] Serial: AMBA PL011 UART driver
10462 23:59:59.320362 <4>[ 0.448997] Trying to register duplicate clock ID: 134
10463 23:59:59.378186 <6>[ 0.510327] KASLR enabled
10464 23:59:59.392810 <6>[ 0.518137] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10465 23:59:59.399240 <6>[ 0.525151] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10466 23:59:59.405804 <6>[ 0.531640] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10467 23:59:59.412947 <6>[ 0.538647] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10468 23:59:59.419174 <6>[ 0.545131] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10469 23:59:59.425678 <6>[ 0.552136] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10470 23:59:59.432300 <6>[ 0.558620] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10471 23:59:59.438755 <6>[ 0.565621] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10472 23:59:59.442225 <6>[ 0.573084] ACPI: Interpreter disabled.
10473 23:59:59.450820 <6>[ 0.579536] iommu: Default domain type: Translated
10474 23:59:59.457685 <6>[ 0.584651] iommu: DMA domain TLB invalidation policy: strict mode
10475 23:59:59.460850 <5>[ 0.591317] SCSI subsystem initialized
10476 23:59:59.467168 <6>[ 0.595561] usbcore: registered new interface driver usbfs
10477 23:59:59.473727 <6>[ 0.601289] usbcore: registered new interface driver hub
10478 23:59:59.477280 <6>[ 0.606839] usbcore: registered new device driver usb
10479 23:59:59.484685 <6>[ 0.612952] pps_core: LinuxPPS API ver. 1 registered
10480 23:59:59.494211 <6>[ 0.618144] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10481 23:59:59.497375 <6>[ 0.627482] PTP clock support registered
10482 23:59:59.500882 <6>[ 0.631725] EDAC MC: Ver: 3.0.0
10483 23:59:59.508127 <6>[ 0.636902] FPGA manager framework
10484 23:59:59.511634 <6>[ 0.640579] Advanced Linux Sound Architecture Driver Initialized.
10485 23:59:59.515083 <6>[ 0.647348] vgaarb: loaded
10486 23:59:59.521786 <6>[ 0.650509] clocksource: Switched to clocksource arch_sys_counter
10487 23:59:59.528351 <5>[ 0.656950] VFS: Disk quotas dquot_6.6.0
10488 23:59:59.534998 <6>[ 0.661137] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10489 23:59:59.538538 <6>[ 0.668327] pnp: PnP ACPI: disabled
10490 23:59:59.546154 <6>[ 0.674947] NET: Registered PF_INET protocol family
10491 23:59:59.556248 <6>[ 0.680546] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10492 23:59:59.567601 <6>[ 0.692862] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10493 23:59:59.577789 <6>[ 0.701676] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10494 23:59:59.584125 <6>[ 0.709643] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10495 23:59:59.590913 <6>[ 0.718339] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10496 23:59:59.602880 <6>[ 0.728091] TCP: Hash tables configured (established 65536 bind 65536)
10497 23:59:59.609409 <6>[ 0.734957] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10498 23:59:59.615645 <6>[ 0.742158] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10499 23:59:59.622716 <6>[ 0.749861] NET: Registered PF_UNIX/PF_LOCAL protocol family
10500 23:59:59.629216 <6>[ 0.756007] RPC: Registered named UNIX socket transport module.
10501 23:59:59.632777 <6>[ 0.762159] RPC: Registered udp transport module.
10502 23:59:59.638939 <6>[ 0.767091] RPC: Registered tcp transport module.
10503 23:59:59.645996 <6>[ 0.772021] RPC: Registered tcp NFSv4.1 backchannel transport module.
10504 23:59:59.649077 <6>[ 0.778689] PCI: CLS 0 bytes, default 64
10505 23:59:59.652521 <6>[ 0.783021] Unpacking initramfs...
10506 23:59:59.669503 <6>[ 0.795032] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10507 23:59:59.679641 <6>[ 0.803676] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10508 23:59:59.683033 <6>[ 0.812499] kvm [1]: IPA Size Limit: 40 bits
10509 23:59:59.689972 <6>[ 0.817026] kvm [1]: GICv3: no GICV resource entry
10510 23:59:59.693038 <6>[ 0.822047] kvm [1]: disabling GICv2 emulation
10511 23:59:59.699445 <6>[ 0.826730] kvm [1]: GIC system register CPU interface enabled
10512 23:59:59.702640 <6>[ 0.832887] kvm [1]: vgic interrupt IRQ18
10513 23:59:59.709280 <6>[ 0.837242] kvm [1]: VHE mode initialized successfully
10514 23:59:59.715883 <5>[ 0.843764] Initialise system trusted keyrings
10515 23:59:59.722507 <6>[ 0.848571] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10516 23:59:59.730006 <6>[ 0.858521] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10517 23:59:59.736764 <5>[ 0.864902] NFS: Registering the id_resolver key type
10518 23:59:59.739986 <5>[ 0.870206] Key type id_resolver registered
10519 23:59:59.746711 <5>[ 0.874619] Key type id_legacy registered
10520 23:59:59.753319 <6>[ 0.878903] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10521 23:59:59.759610 <6>[ 0.885827] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10522 23:59:59.766176 <6>[ 0.893547] 9p: Installing v9fs 9p2000 file system support
10523 23:59:59.802957 <5>[ 0.931440] Key type asymmetric registered
10524 23:59:59.805957 <5>[ 0.935773] Asymmetric key parser 'x509' registered
10525 23:59:59.815879 <6>[ 0.940917] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10526 23:59:59.819093 <6>[ 0.948533] io scheduler mq-deadline registered
10527 23:59:59.822530 <6>[ 0.953311] io scheduler kyber registered
10528 23:59:59.841567 <6>[ 0.970299] EINJ: ACPI disabled.
10529 23:59:59.874258 <4>[ 0.996266] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 23:59:59.884218 <4>[ 1.006922] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 23:59:59.898895 <6>[ 1.027798] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10532 23:59:59.906997 <6>[ 1.035806] printk: console [ttyS0] disabled
10533 23:59:59.935427 <6>[ 1.060440] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10534 23:59:59.941557 <6>[ 1.069911] printk: console [ttyS0] enabled
10535 23:59:59.945235 <6>[ 1.069911] printk: console [ttyS0] enabled
10536 23:59:59.951409 <6>[ 1.078806] printk: bootconsole [mtk8250] disabled
10537 23:59:59.955386 <6>[ 1.078806] printk: bootconsole [mtk8250] disabled
10538 23:59:59.961399 <6>[ 1.089835] SuperH (H)SCI(F) driver initialized
10539 23:59:59.964601 <6>[ 1.095112] msm_serial: driver initialized
10540 23:59:59.978851 <6>[ 1.104028] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10541 23:59:59.988298 <6>[ 1.112576] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10542 23:59:59.995310 <6>[ 1.121118] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10543 00:00:00.005543 <6>[ 1.129745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10544 00:00:00.012095 <6>[ 1.138451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10545 00:00:00.022043 <6>[ 1.147163] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10546 00:00:00.032024 <6>[ 1.155702] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10547 00:00:00.038387 <6>[ 1.164497] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10548 00:00:00.047997 <6>[ 1.173038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10549 00:00:00.059867 <6>[ 1.188681] loop: module loaded
10550 00:00:00.066371 <6>[ 1.194588] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10551 00:00:00.089399 <4>[ 1.217816] mtk-pmic-keys: Failed to locate of_node [id: -1]
10552 00:00:00.095995 <6>[ 1.224608] megasas: 07.719.03.00-rc1
10553 00:00:00.105256 <6>[ 1.234157] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10554 00:00:00.113441 <6>[ 1.241902] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10555 00:00:00.129724 <6>[ 1.258689] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10556 00:00:00.187394 <6>[ 1.309063] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10557 00:00:00.443018 <6>[ 1.571877] Freeing initrd memory: 18284K
10558 00:00:00.454564 <6>[ 1.583559] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10559 00:00:00.465859 <6>[ 1.594427] tun: Universal TUN/TAP device driver, 1.6
10560 00:00:00.469259 <6>[ 1.600485] thunder_xcv, ver 1.0
10561 00:00:00.472582 <6>[ 1.603991] thunder_bgx, ver 1.0
10562 00:00:00.475938 <6>[ 1.607484] nicpf, ver 1.0
10563 00:00:00.485875 <6>[ 1.611491] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10564 00:00:00.489454 <6>[ 1.618967] hns3: Copyright (c) 2017 Huawei Corporation.
10565 00:00:00.495974 <6>[ 1.624553] hclge is initializing
10566 00:00:00.499036 <6>[ 1.628132] e1000: Intel(R) PRO/1000 Network Driver
10567 00:00:00.505670 <6>[ 1.633261] e1000: Copyright (c) 1999-2006 Intel Corporation.
10568 00:00:00.509148 <6>[ 1.639272] e1000e: Intel(R) PRO/1000 Network Driver
10569 00:00:00.515642 <6>[ 1.644488] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10570 00:00:00.522619 <6>[ 1.650675] igb: Intel(R) Gigabit Ethernet Network Driver
10571 00:00:00.529060 <6>[ 1.656325] igb: Copyright (c) 2007-2014 Intel Corporation.
10572 00:00:00.535810 <6>[ 1.662161] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10573 00:00:00.542347 <6>[ 1.668679] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10574 00:00:00.545993 <6>[ 1.675140] sky2: driver version 1.30
10575 00:00:00.552226 <6>[ 1.680058] usbcore: registered new device driver r8152-cfgselector
10576 00:00:00.559161 <6>[ 1.686593] usbcore: registered new interface driver r8152
10577 00:00:00.562264 <6>[ 1.692414] VFIO - User Level meta-driver version: 0.3
10578 00:00:00.571717 <6>[ 1.700668] usbcore: registered new interface driver usb-storage
10579 00:00:00.578412 <6>[ 1.707110] usbcore: registered new device driver onboard-usb-hub
10580 00:00:00.587861 <6>[ 1.716209] mt6397-rtc mt6359-rtc: registered as rtc0
10581 00:00:00.597625 <6>[ 1.721667] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:55:19 UTC (1717026919)
10582 00:00:00.600893 <6>[ 1.731227] i2c_dev: i2c /dev entries driver
10583 00:00:00.617443 <6>[ 1.742989] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10584 00:00:00.624160 <4>[ 1.751711] cpu cpu0: supply cpu not found, using dummy regulator
10585 00:00:00.630638 <4>[ 1.758139] cpu cpu1: supply cpu not found, using dummy regulator
10586 00:00:00.637359 <4>[ 1.764546] cpu cpu2: supply cpu not found, using dummy regulator
10587 00:00:00.644275 <4>[ 1.770960] cpu cpu3: supply cpu not found, using dummy regulator
10588 00:00:00.650393 <4>[ 1.777354] cpu cpu4: supply cpu not found, using dummy regulator
10589 00:00:00.657647 <4>[ 1.783750] cpu cpu5: supply cpu not found, using dummy regulator
10590 00:00:00.663775 <4>[ 1.790150] cpu cpu6: supply cpu not found, using dummy regulator
10591 00:00:00.670387 <4>[ 1.796561] cpu cpu7: supply cpu not found, using dummy regulator
10592 00:00:00.688479 <6>[ 1.817207] cpu cpu0: EM: created perf domain
10593 00:00:00.691691 <6>[ 1.822146] cpu cpu4: EM: created perf domain
10594 00:00:00.698874 <6>[ 1.827698] sdhci: Secure Digital Host Controller Interface driver
10595 00:00:00.705407 <6>[ 1.834131] sdhci: Copyright(c) Pierre Ossman
10596 00:00:00.712500 <6>[ 1.839080] Synopsys Designware Multimedia Card Interface Driver
10597 00:00:00.718677 <6>[ 1.845711] sdhci-pltfm: SDHCI platform and OF driver helper
10598 00:00:00.721985 <6>[ 1.845755] mmc0: CQHCI version 5.10
10599 00:00:00.728616 <6>[ 1.856071] ledtrig-cpu: registered to indicate activity on CPUs
10600 00:00:00.735699 <6>[ 1.863154] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10601 00:00:00.742438 <6>[ 1.870205] usbcore: registered new interface driver usbhid
10602 00:00:00.745921 <6>[ 1.876037] usbhid: USB HID core driver
10603 00:00:00.752403 <6>[ 1.880225] spi_master spi0: will run message pump with realtime priority
10604 00:00:00.797780 <6>[ 1.919830] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10605 00:00:00.817098 <6>[ 1.935751] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10606 00:00:00.820701 <6>[ 1.950087] mmc0: Command Queue Engine enabled
10607 00:00:00.827673 <6>[ 1.950591] cros-ec-spi spi0.0: Chrome EC device registered
10608 00:00:00.834682 <6>[ 1.954822] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10609 00:00:00.837499 <6>[ 1.968004] mmcblk0: mmc0:0001 DA4128 116 GiB
10610 00:00:00.849476 <6>[ 1.974886] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10611 00:00:00.856273 <6>[ 1.977614] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10612 00:00:00.862896 <6>[ 1.985226] NET: Registered PF_PACKET protocol family
10613 00:00:00.866390 <6>[ 1.991185] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10614 00:00:00.872803 <6>[ 1.995507] 9pnet: Installing 9P2000 support
10615 00:00:00.875990 <6>[ 2.001338] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10616 00:00:00.879243 <5>[ 2.005203] Key type dns_resolver registered
10617 00:00:00.885952 <6>[ 2.011117] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 00:00:00.892735 <6>[ 2.015483] registered taskstats version 1
10619 00:00:00.896393 <5>[ 2.025845] Loading compiled-in X.509 certificates
10620 00:00:00.925161 <4>[ 2.047601] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 00:00:00.935346 <4>[ 2.058297] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 00:00:00.948812 <6>[ 2.077973] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10623 00:00:00.956242 <6>[ 2.084785] xhci-mtk 11200000.usb: xHCI Host Controller
10624 00:00:00.962887 <6>[ 2.090292] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10625 00:00:00.972980 <6>[ 2.098154] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10626 00:00:00.979154 <6>[ 2.107592] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10627 00:00:00.986349 <6>[ 2.113802] xhci-mtk 11200000.usb: xHCI Host Controller
10628 00:00:00.992685 <6>[ 2.119314] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10629 00:00:00.999260 <6>[ 2.126971] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10630 00:00:01.005957 <6>[ 2.134906] hub 1-0:1.0: USB hub found
10631 00:00:01.009217 <6>[ 2.138938] hub 1-0:1.0: 1 port detected
10632 00:00:01.016411 <6>[ 2.143233] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10633 00:00:01.022972 <6>[ 2.152042] hub 2-0:1.0: USB hub found
10634 00:00:01.026159 <6>[ 2.156067] hub 2-0:1.0: 1 port detected
10635 00:00:01.035348 <6>[ 2.164017] mtk-msdc 11f70000.mmc: Got CD GPIO
10636 00:00:01.049797 <6>[ 2.175209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10637 00:00:01.056658 <6>[ 2.183236] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10638 00:00:01.066292 <4>[ 2.191162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10639 00:00:01.076568 <6>[ 2.200695] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10640 00:00:01.083009 <6>[ 2.208773] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10641 00:00:01.089420 <6>[ 2.216780] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10642 00:00:01.099682 <6>[ 2.224700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10643 00:00:01.106332 <6>[ 2.232517] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10644 00:00:01.116148 <6>[ 2.240334] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10645 00:00:01.126238 <6>[ 2.250781] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10646 00:00:01.133004 <6>[ 2.259143] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10647 00:00:01.143183 <6>[ 2.267490] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10648 00:00:01.149859 <6>[ 2.275828] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10649 00:00:01.159395 <6>[ 2.284166] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10650 00:00:01.166598 <6>[ 2.292504] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10651 00:00:01.176691 <6>[ 2.300842] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10652 00:00:01.182989 <6>[ 2.309180] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10653 00:00:01.192715 <6>[ 2.317518] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10654 00:00:01.199519 <6>[ 2.325856] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10655 00:00:01.209319 <6>[ 2.334194] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10656 00:00:01.216015 <6>[ 2.342533] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10657 00:00:01.225954 <6>[ 2.350871] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10658 00:00:01.232646 <6>[ 2.359209] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10659 00:00:01.242826 <6>[ 2.367548] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10660 00:00:01.249385 <6>[ 2.376277] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10661 00:00:01.255934 <6>[ 2.383344] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10662 00:00:01.262445 <6>[ 2.390111] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10663 00:00:01.269323 <6>[ 2.396882] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10664 00:00:01.275891 <6>[ 2.403804] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10665 00:00:01.285792 <6>[ 2.410685] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10666 00:00:01.295910 <6>[ 2.419817] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10667 00:00:01.305420 <6>[ 2.428936] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10668 00:00:01.315219 <6>[ 2.438231] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10669 00:00:01.322270 <6>[ 2.447700] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10670 00:00:01.331887 <6>[ 2.457167] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10671 00:00:01.342143 <6>[ 2.466286] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10672 00:00:01.352140 <6>[ 2.475752] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10673 00:00:01.361886 <6>[ 2.484871] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10674 00:00:01.371631 <6>[ 2.494166] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10675 00:00:01.381856 <6>[ 2.504327] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10676 00:00:01.391280 <6>[ 2.515901] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10677 00:00:01.398149 <6>[ 2.525581] Trying to probe devices needed for running init ...
10678 00:00:01.441135 <6>[ 2.566780] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10679 00:00:01.596045 <6>[ 2.724603] hub 1-1:1.0: USB hub found
10680 00:00:01.599222 <6>[ 2.729100] hub 1-1:1.0: 4 ports detected
10681 00:00:01.608760 <6>[ 2.737647] hub 1-1:1.0: USB hub found
10682 00:00:01.611767 <6>[ 2.742025] hub 1-1:1.0: 4 ports detected
10683 00:00:01.721412 <6>[ 2.847132] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10684 00:00:01.748221 <6>[ 2.877007] hub 2-1:1.0: USB hub found
10685 00:00:01.751443 <6>[ 2.881538] hub 2-1:1.0: 3 ports detected
10686 00:00:01.760462 <6>[ 2.889723] hub 2-1:1.0: USB hub found
10687 00:00:01.764513 <6>[ 2.894106] hub 2-1:1.0: 3 ports detected
10688 00:00:01.937185 <6>[ 3.062828] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10689 00:00:02.069639 <6>[ 3.198693] hub 1-1.4:1.0: USB hub found
10690 00:00:02.072983 <6>[ 3.203361] hub 1-1.4:1.0: 2 ports detected
10691 00:00:02.082372 <6>[ 3.211121] hub 1-1.4:1.0: USB hub found
10692 00:00:02.085651 <6>[ 3.215730] hub 1-1.4:1.0: 2 ports detected
10693 00:00:02.149179 <6>[ 3.274955] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10694 00:00:02.257306 <6>[ 3.383321] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10695 00:00:02.294080 <4>[ 3.419801] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10696 00:00:02.304202 <4>[ 3.428940] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10697 00:00:02.342980 <6>[ 3.472315] r8152 2-1.3:1.0 eth0: v1.12.13
10698 00:00:02.381276 <6>[ 3.506832] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10699 00:00:02.573013 <6>[ 3.698612] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10700 00:00:04.033353 <6>[ 5.162880] r8152 2-1.3:1.0 eth0: carrier on
10701 00:00:06.757040 <5>[ 5.190583] Sending DHCP requests .., OK
10702 00:00:06.763400 <6>[ 7.890965] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10703 00:00:06.766751 <6>[ 7.899263] IP-Config: Complete:
10704 00:00:06.780145 <6>[ 7.902755] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10705 00:00:06.787000 <6>[ 7.913460] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10706 00:00:06.793685 <6>[ 7.922076] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10707 00:00:06.800634 <6>[ 7.922086] nameserver0=192.168.201.1
10708 00:00:06.803337 <6>[ 7.934241] clk: Disabling unused clocks
10709 00:00:06.806911 <6>[ 7.939750] ALSA device list:
10710 00:00:06.813257 <6>[ 7.943030] No soundcards found.
10711 00:00:06.820778 <6>[ 7.950609] Freeing unused kernel memory: 8512K
10712 00:00:06.824494 <6>[ 7.955561] Run /init as init process
10713 00:00:06.834392 Loading, please wait...
10714 00:00:06.860192 Starting systemd-udevd version 252.22-1~deb12u1
10715 00:00:07.099306 <6>[ 8.225466] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10716 00:00:07.118470 <6>[ 8.244853] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10717 00:00:07.122383 <6>[ 8.245549] remoteproc remoteproc0: scp is available
10718 00:00:07.131864 <6>[ 8.252781] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10719 00:00:07.138291 <6>[ 8.258341] remoteproc remoteproc0: powering up scp
10720 00:00:07.144910 <6>[ 8.266495] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10721 00:00:07.155182 <6>[ 8.271595] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10722 00:00:07.158507 <6>[ 8.288776] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10723 00:00:07.169165 <3>[ 8.295572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 00:00:07.175800 <4>[ 8.298940] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10725 00:00:07.186121 <3>[ 8.303704] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 00:00:07.192837 <3>[ 8.303718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 00:00:07.202140 <3>[ 8.304695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 00:00:07.208969 <4>[ 8.328507] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10729 00:00:07.215605 <3>[ 8.335513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 00:00:07.225556 <3>[ 8.350907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 00:00:07.232302 <3>[ 8.359004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 00:00:07.235277 <6>[ 8.365846] mc: Linux media interface: v0.10
10733 00:00:07.245418 <3>[ 8.367134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 00:00:07.259756 <3>[ 8.385303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 00:00:07.266507 <6>[ 8.388641] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10736 00:00:07.276425 <3>[ 8.394282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 00:00:07.282505 <6>[ 8.407970] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10738 00:00:07.289461 <3>[ 8.409886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 00:00:07.296278 <6>[ 8.410459] videodev: Linux video capture interface: v2.00
10740 00:00:07.302825 <6>[ 8.416885] pci_bus 0000:00: root bus resource [bus 00-ff]
10741 00:00:07.312745 <6>[ 8.418990] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10742 00:00:07.322787 <6>[ 8.419319] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10743 00:00:07.328820 <6>[ 8.420364] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10744 00:00:07.336414 <3>[ 8.425057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 00:00:07.345810 <6>[ 8.430806] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10746 00:00:07.352299 <6>[ 8.432258] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10747 00:00:07.358901 <6>[ 8.434676] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10748 00:00:07.368807 <6>[ 8.434683] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10749 00:00:07.378735 <6>[ 8.434684] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10750 00:00:07.385812 <6>[ 8.434735] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10751 00:00:07.391907 <6>[ 8.434751] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10752 00:00:07.395273 <6>[ 8.434829] pci 0000:00:00.0: supports D1 D2
10753 00:00:07.402650 <6>[ 8.434831] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10754 00:00:07.412534 <6>[ 8.435914] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10755 00:00:07.419273 <6>[ 8.435999] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10756 00:00:07.426255 <6>[ 8.436024] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10757 00:00:07.432760 <6>[ 8.436039] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10758 00:00:07.439383 <6>[ 8.436054] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10759 00:00:07.446001 <6>[ 8.436159] pci 0000:01:00.0: supports D1 D2
10760 00:00:07.452810 <6>[ 8.436161] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10761 00:00:07.459207 <3>[ 8.436442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 00:00:07.465950 <6>[ 8.446514] remoteproc remoteproc0: remote processor scp is now up
10763 00:00:07.473638 <6>[ 8.446943] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10764 00:00:07.479904 <6>[ 8.446986] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10765 00:00:07.489910 <6>[ 8.446990] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10766 00:00:07.496413 <6>[ 8.446999] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10767 00:00:07.506527 <6>[ 8.447012] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10768 00:00:07.513302 <6>[ 8.447025] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10769 00:00:07.519667 <6>[ 8.447038] pci 0000:00:00.0: PCI bridge to [bus 01]
10770 00:00:07.526832 <6>[ 8.447044] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10771 00:00:07.532804 <6>[ 8.447181] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10772 00:00:07.539760 <6>[ 8.447659] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10773 00:00:07.546605 <6>[ 8.448128] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10774 00:00:07.552612 <6>[ 8.451159] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10775 00:00:07.563358 <3>[ 8.455508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 00:00:07.569369 <4>[ 8.471385] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10777 00:00:07.576058 <4>[ 8.471385] Fallback method does not support PEC.
10778 00:00:07.583084 <3>[ 8.479184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 00:00:07.592800 <3>[ 8.479218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 00:00:07.599570 <3>[ 8.479226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 00:00:07.609746 <3>[ 8.479385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 00:00:07.615682 <5>[ 8.481723] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10783 00:00:07.622438 <5>[ 8.494237] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10784 00:00:07.625657 <6>[ 8.495273] Bluetooth: Core ver 2.22
10785 00:00:07.635839 <5>[ 8.505161] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10786 00:00:07.639248 <6>[ 8.512958] NET: Registered PF_BLUETOOTH protocol family
10787 00:00:07.649059 <4>[ 8.519245] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10788 00:00:07.655880 <6>[ 8.519793] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10789 00:00:07.669226 <6>[ 8.520857] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10790 00:00:07.675570 <6>[ 8.520948] usbcore: registered new interface driver uvcvideo
10791 00:00:07.682332 <6>[ 8.527879] Bluetooth: HCI device and connection manager initialized
10792 00:00:07.685656 <6>[ 8.531150] cfg80211: failed to load regulatory.db
10793 00:00:07.692328 <6>[ 8.532345] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10794 00:00:07.699142 <6>[ 8.538022] Bluetooth: HCI socket layer initialized
10795 00:00:07.705557 <3>[ 8.575021] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10796 00:00:07.711993 <6>[ 8.579448] Bluetooth: L2CAP socket layer initialized
10797 00:00:07.718852 <6>[ 8.579512] Bluetooth: SCO socket layer initialized
10798 00:00:07.725819 <3>[ 8.607884] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10799 00:00:07.732266 <6>[ 8.616426] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10800 00:00:07.738704 <6>[ 8.667926] usbcore: registered new interface driver btusb
10801 00:00:07.748526 <4>[ 8.668987] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10802 00:00:07.755412 <3>[ 8.669002] Bluetooth: hci0: Failed to load firmware file (-2)
10803 00:00:07.761907 <3>[ 8.669009] Bluetooth: hci0: Failed to set up firmware (-2)
10804 00:00:07.771771 <4>[ 8.669016] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10805 00:00:07.778280 <6>[ 8.673560] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10806 00:00:07.800852 <6>[ 8.930815] mt7921e 0000:01:00.0: ASIC revision: 79610010
10807 00:00:07.904536 <6>[ 9.030895] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10808 00:00:07.907932 <6>[ 9.030895]
10809 00:00:07.911393 Begin: Loading essential drivers ... done.
10810 00:00:07.917566 Begin: Running /scripts/init-premount ... done.
10811 00:00:07.924391 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10812 00:00:07.931084 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10813 00:00:07.934232 Device /sys/class/net/eth0 found
10814 00:00:07.934368 done.
10815 00:00:07.944301 Begin: Waiting up to 180 secs for any network device to become available ... done.
10816 00:00:07.976907 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10817 00:00:07.983595 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10818 00:00:07.990585 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10819 00:00:07.997263 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10820 00:00:08.003970 host : mt8192-asurada-spherion-r0-cbg-0
10821 00:00:08.010524 domain : lava-rack
10822 00:00:08.014000 rootserver: 192.168.201.1 rootpath:
10823 00:00:08.014137 filename :
10824 00:00:08.174767 <6>[ 9.300926] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10825 00:00:08.185318 done.
10826 00:00:08.192137 Begin: Running /scripts/nfs-bottom ... done.
10827 00:00:08.209428 Begin: Running /scripts/init-bottom ... done.
10828 00:00:09.490869 <6>[ 10.620887] NET: Registered PF_INET6 protocol family
10829 00:00:09.498501 <6>[ 10.628418] Segment Routing with IPv6
10830 00:00:09.501768 <6>[ 10.632407] In-situ OAM (IOAM) with IPv6
10831 00:00:09.660827 <30>[ 10.763973] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10832 00:00:09.667579 <30>[ 10.797184] systemd[1]: Detected architecture arm64.
10833 00:00:09.675025
10834 00:00:09.678544 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10835 00:00:09.678661
10836 00:00:09.701983 <30>[ 10.831751] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10837 00:00:10.735289 <30>[ 11.861715] systemd[1]: Queued start job for default target graphical.target.
10838 00:00:10.777695 <30>[ 11.904024] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10839 00:00:10.784139 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10840 00:00:10.806070 <30>[ 11.932548] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10841 00:00:10.815448 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10842 00:00:10.834074 <30>[ 11.960510] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10843 00:00:10.844015 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10844 00:00:10.862239 <30>[ 11.989008] systemd[1]: Created slice user.slice - User and Session Slice.
10845 00:00:10.868923 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10846 00:00:10.892724 <30>[ 12.015663] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10847 00:00:10.902348 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10848 00:00:10.919818 <30>[ 12.043040] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10849 00:00:10.926429 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10850 00:00:10.954529 <30>[ 12.071438] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10851 00:00:10.964976 <30>[ 12.091365] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10852 00:00:10.971321 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10853 00:00:10.988284 <30>[ 12.114896] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10854 00:00:10.994765 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10855 00:00:11.012013 <30>[ 12.138832] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10856 00:00:11.021751 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10857 00:00:11.036702 <30>[ 12.166837] systemd[1]: Reached target paths.target - Path Units.
10858 00:00:11.046831 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10859 00:00:11.064252 <30>[ 12.190762] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10860 00:00:11.070951 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10861 00:00:11.088213 <30>[ 12.214742] systemd[1]: Reached target slices.target - Slice Units.
10862 00:00:11.094475 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10863 00:00:11.109658 <30>[ 12.239282] systemd[1]: Reached target swap.target - Swaps.
10864 00:00:11.115783 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10865 00:00:11.139893 <30>[ 12.266849] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10866 00:00:11.150311 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10867 00:00:11.168765 <30>[ 12.295712] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10868 00:00:11.178768 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10869 00:00:11.199051 <30>[ 12.325614] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10870 00:00:11.208935 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10871 00:00:11.226326 <30>[ 12.352797] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10872 00:00:11.235884 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10873 00:00:11.252640 <30>[ 12.379619] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10874 00:00:11.259815 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10875 00:00:11.281749 <30>[ 12.408312] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10876 00:00:11.291889 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10877 00:00:11.311353 <30>[ 12.438325] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10878 00:00:11.321462 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10879 00:00:11.336875 <30>[ 12.463304] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10880 00:00:11.346312 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10881 00:00:11.396412 <30>[ 12.522989] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10882 00:00:11.402617 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10883 00:00:11.425026 <30>[ 12.551465] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10884 00:00:11.431119 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10885 00:00:11.457581 <30>[ 12.584078] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10886 00:00:11.464368 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10887 00:00:11.490991 <30>[ 12.611341] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10888 00:00:11.506264 <30>[ 12.632818] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10889 00:00:11.515967 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10890 00:00:11.536086 <30>[ 12.662935] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10891 00:00:11.545872 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10892 00:00:11.569680 <30>[ 12.696478] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10893 00:00:11.576367 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10894 00:00:11.610967 <6>[ 12.737725] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10895 00:00:11.617493 <30>[ 12.739403] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10896 00:00:11.627734 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10897 00:00:11.650045 <30>[ 12.776546] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10898 00:00:11.659528 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10899 00:00:11.680520 <30>[ 12.806922] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10900 00:00:11.686545 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10901 00:00:11.712458 <30>[ 12.839095] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10902 00:00:11.722262 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.852119] fuse: init (API version 7.37)
10903 00:00:11.725534 el Module loop...
10904 00:00:11.750989 <30>[ 12.877889] systemd[1]: Starting systemd-journald.service - Journal Service...
10905 00:00:11.757545 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10906 00:00:11.796996 <30>[ 12.923787] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10907 00:00:11.803971 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10908 00:00:11.832514 <30>[ 12.955836] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10909 00:00:11.839206 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10910 00:00:11.865704 <30>[ 12.992510] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10911 00:00:11.876125 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10912 00:00:11.924524 <30>[ 13.051521] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10913 00:00:11.931225 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10914 00:00:11.957581 <30>[ 13.083623] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10915 00:00:11.967608 [[0;32m OK [0m] Mounted [0;<3>[ 13.093857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 00:00:11.974212 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10917 00:00:11.992925 <30>[ 13.119236] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10918 00:00:11.999312 <3>[ 13.123887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 00:00:12.009355 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10920 00:00:12.029592 <30>[ 13.155118] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10921 00:00:12.039019 [[0;32m OK [0m] Mounted [0;<3>[ 13.165264] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 00:00:12.045553 1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10923 00:00:12.065705 <30>[ 13.191970] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10924 00:00:12.075935 <3>[ 13.199500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 00:00:12.082285 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10926 00:00:12.099096 <30>[ 13.228188] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10927 00:00:12.108777 <3>[ 13.233018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 00:00:12.118987 <30>[ 13.236230] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10929 00:00:12.125602 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10930 00:00:12.142153 <3>[ 13.269126] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 00:00:12.154036 <30>[ 13.280988] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10932 00:00:12.161154 <30>[ 13.289383] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10933 00:00:12.174831 [[0;32m OK [0m] Finished [0<3>[ 13.299243] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 00:00:12.178244 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10935 00:00:12.194666 <30>[ 13.324461] systemd[1]: modprobe@drm.service: Deactivated successfully.
10936 00:00:12.206085 <30>[ 13.332588] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10937 00:00:12.212118 <3>[ 13.332737] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 00:00:12.222556 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10939 00:00:12.241975 <30>[ 13.368441] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10940 00:00:12.252065 <30>[ 13.376927] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10941 00:00:12.259071 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10942 00:00:12.277087 <30>[ 13.403638] systemd[1]: Started systemd-journald.service - Journal Service.
10943 00:00:12.283187 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10944 00:00:12.305864 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10945 00:00:12.327104 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10946 00:00:12.346380 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10947 00:00:12.374544 <4>[ 13.494803] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10948 00:00:12.384813 <3>[ 13.510477] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10949 00:00:12.390930 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10950 00:00:12.415514 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10951 00:00:12.433565 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10952 00:00:12.458903 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10953 00:00:12.496293 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10954 00:00:12.520710 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10955 00:00:12.545462 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10956 00:00:12.573442 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10957 00:00:12.608868 <46>[ 13.735733] systemd-journald[302]: Received client request to flush runtime journal.
10958 00:00:12.633247 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10959 00:00:12.667334 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10960 00:00:12.933265 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10961 00:00:12.952631 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10962 00:00:12.974356 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10963 00:00:13.396049 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10964 00:00:14.026993 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10965 00:00:14.049172 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10966 00:00:14.109336 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10967 00:00:14.193877 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10968 00:00:14.212374 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10969 00:00:14.232096 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10970 00:00:14.289024 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10971 00:00:14.319264 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10972 00:00:14.540302 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10973 00:00:14.605525 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10974 00:00:14.643249 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10975 00:00:14.672450 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10976 00:00:14.849868 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10977 00:00:14.878696 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10978 00:00:14.992697 <6>[ 16.122867] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10979 00:00:15.003323 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10980 00:00:15.049890 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10981 00:00:15.088467 <4>[ 16.218691] power_supply_show_property: 4 callbacks suppressed
10982 00:00:15.098475 <3>[ 16.218719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 00:00:15.105274 <3>[ 16.219573] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10984 00:00:15.118393 <3>[ 16.245138] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 00:00:15.146384 <3>[ 16.273797] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 00:00:15.176715 <3>[ 16.303680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 00:00:15.186779 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10988 00:00:15.211698 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Swit<3>[ 16.336564] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 00:00:15.211869 ch Status /dev/rfkill Watch.
10990 00:00:15.240297 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Sync<3>[ 16.366439] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 00:00:15.240506 hronization.
10992 00:00:15.260168 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10993 00:00:15.274147 [[0;32m OK [<3>[ 16.398222] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 00:00:15.280827 0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10995 00:00:15.307147 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kb<3>[ 16.432647] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 00:00:15.310230 d_backlight.
10997 00:00:15.345606 <3>[ 16.472882] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 00:00:15.352639 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10999 00:00:15.372226 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11000 00:00:15.387768 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11001 00:00:15.404170 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11002 00:00:15.440021 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11003 00:00:15.462040 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11004 00:00:15.480336 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11005 00:00:15.498320 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11006 00:00:15.519105 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11007 00:00:15.535641 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11008 00:00:15.553638 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11009 00:00:15.571694 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11010 00:00:15.588280 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11011 00:00:15.629867 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11012 00:00:15.663292 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11013 00:00:15.752695 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11014 00:00:15.777475 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11015 00:00:15.799645 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11016 00:00:15.867029 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11017 00:00:15.912532 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11018 00:00:15.939824 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11019 00:00:15.957604 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11020 00:00:15.976645 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11021 00:00:16.006097 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11022 00:00:16.044739 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11023 00:00:16.195680 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11024 00:00:16.221270 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11025 00:00:16.238637 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11026 00:00:16.281594 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11027 00:00:16.330572 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11028 00:00:16.413319
11029 00:00:16.416799 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11030 00:00:16.416886
11031 00:00:16.420047 debian-bookworm-arm64 login: root (automatic login)
11032 00:00:16.420192
11033 00:00:16.721810 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11034 00:00:16.722027
11035 00:00:16.728572 The programs included with the Debian GNU/Linux system are free software;
11036 00:00:16.735049 the exact distribution terms for each program are described in the
11037 00:00:16.738603 individual files in /usr/share/doc/*/copyright.
11038 00:00:16.738735
11039 00:00:16.745305 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11040 00:00:16.748582 permitted by applicable law.
11041 00:00:17.702261 Matched prompt #10: / #
11043 00:00:17.702538 Setting prompt string to ['/ #']
11044 00:00:17.702637 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11046 00:00:17.702838 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11047 00:00:17.702926 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
11048 00:00:17.703000 Setting prompt string to ['/ #']
11049 00:00:17.703063 Forcing a shell prompt, looking for ['/ #']
11051 00:00:17.753262 / #
11052 00:00:17.753413 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11053 00:00:17.753501 Waiting using forced prompt support (timeout 00:02:30)
11054 00:00:17.758403
11055 00:00:17.758682 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11056 00:00:17.758782 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
11058 00:00:17.859133 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj'
11059 00:00:17.864067 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084370/extract-nfsrootfs-pwy1i0lj'
11061 00:00:17.964675 / # export NFS_SERVER_IP='192.168.201.1'
11062 00:00:17.970603 export NFS_SERVER_IP='192.168.201.1'
11063 00:00:17.970909 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11064 00:00:17.971013 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
11065 00:00:17.971112 end: 2 depthcharge-action (duration 00:01:18) [common]
11066 00:00:17.971208 start: 3 lava-test-retry (timeout 00:07:59) [common]
11067 00:00:17.971295 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
11068 00:00:17.971376 Using namespace: common
11070 00:00:18.071692 / # #
11071 00:00:18.071855 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11072 00:00:18.076924 #
11073 00:00:18.077264 Using /lava-14084370
11075 00:00:18.177670 / # export SHELL=/bin/bash
11076 00:00:18.182760 export SHELL=/bin/bash
11078 00:00:18.283369 / # . /lava-14084370/environment
11079 00:00:18.288920 . /lava-14084370/environment
11081 00:00:18.395093 / # /lava-14084370/bin/lava-test-runner /lava-14084370/0
11082 00:00:18.395297 Test shell timeout: 10s (minimum of the action and connection timeout)
11083 00:00:18.399916 /lava-14084370/bin/lava-test-runner /lava-14084370/0
11084 00:00:18.638029 + export TESTRUN_ID=0_timesync-off
11085 00:00:18.641329 + TESTRUN_ID=0_timesync-off
11086 00:00:18.644642 + cd /lava-14084370/0/tests/0_timesync-off
11087 00:00:18.647979 ++ cat uuid
11088 00:00:18.652798 + UUID=14084370_1.6.2.3.1
11089 00:00:18.652897 + set +x
11090 00:00:18.658850 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14084370_1.6.2.3.1>
11091 00:00:18.659148 Received signal: <STARTRUN> 0_timesync-off 14084370_1.6.2.3.1
11092 00:00:18.659256 Starting test lava.0_timesync-off (14084370_1.6.2.3.1)
11093 00:00:18.659400 Skipping test definition patterns.
11094 00:00:18.662099 + systemctl stop systemd-timesyncd
11095 00:00:18.740148 + set +x
11096 00:00:18.743373 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14084370_1.6.2.3.1>
11097 00:00:18.743678 Received signal: <ENDRUN> 0_timesync-off 14084370_1.6.2.3.1
11098 00:00:18.743780 Ending use of test pattern.
11099 00:00:18.743860 Ending test lava.0_timesync-off (14084370_1.6.2.3.1), duration 0.08
11101 00:00:18.801483 + export TESTRUN_ID=1_kselftest-rtc
11102 00:00:18.805188 + TESTRUN_ID=1_kselftest-rtc
11103 00:00:18.808370 + cd /lava-14084370/0/tests/1_kselftest-rtc
11104 00:00:18.811759 ++ cat uuid
11105 00:00:18.814749 + UUID=14084370_1.6.2.3.5
11106 00:00:18.814840 + set +x
11107 00:00:18.817894 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14084370_1.6.2.3.5>
11108 00:00:18.818157 Received signal: <STARTRUN> 1_kselftest-rtc 14084370_1.6.2.3.5
11109 00:00:18.818231 Starting test lava.1_kselftest-rtc (14084370_1.6.2.3.5)
11110 00:00:18.818317 Skipping test definition patterns.
11111 00:00:18.821347 + cd ./automated/linux/kselftest/
11112 00:00:18.851617 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11113 00:00:18.883482 INFO: install_deps skipped
11114 00:00:19.382602 --2024-05-29 23:55:38-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11115 00:00:19.389815 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11116 00:00:19.522422 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11117 00:00:19.655840 HTTP request sent, awaiting response... 200 OK
11118 00:00:19.659190 Length: 1642292 (1.6M) [application/octet-stream]
11119 00:00:19.662492 Saving to: 'kselftest_armhf.tar.gz'
11120 00:00:19.662577
11121 00:00:19.662644
11122 00:00:19.921668 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11123 00:00:20.187420 kselftest_armhf.tar 2%[ ] 47.81K 175KB/s
11124 00:00:20.635167 kselftest_armhf.tar 13%[=> ] 216.08K 395KB/s
11125 00:00:20.641026 kselftest_armhf.tar 48%[========> ] 781.71K 777KB/s
11126 00:00:20.647671 kselftest_armhf.tar 100%[===================>] 1.57M 1.54MB/s in 1.0s
11127 00:00:20.647807
11128 00:00:20.793401 2024-05-29 23:55:39 (1.54 MB/s) - 'kselftest_armhf.tar.gz' saved [1642292/1642292]
11129 00:00:20.793576
11130 00:00:24.590555 skiplist:
11131 00:00:24.593645 ========================================
11132 00:00:24.596936 ========================================
11133 00:00:24.634837 rtc:rtctest
11134 00:00:24.653846 ============== Tests to run ===============
11135 00:00:24.654031 rtc:rtctest
11136 00:00:24.656987 ===========End Tests to run ===============
11137 00:00:24.660204 shardfile-rtc pass
11138 00:00:24.750713 <12>[ 25.882143] kselftest: Running tests in rtc
11139 00:00:24.759272 TAP version 13
11140 00:00:24.772401 1..1
11141 00:00:24.801812 # selftests: rtc: rtctest
11142 00:00:25.260181 # TAP version 13
11143 00:00:25.260337 # 1..8
11144 00:00:25.263442 # # Starting 8 tests from 2 test cases.
11145 00:00:25.267283 # # RUN rtc.date_read ...
11146 00:00:25.273841 # # rtctest.c:49:date_read:Current RTC date/time is 29/05/2024 23:55:43.
11147 00:00:25.276940 # # OK rtc.date_read
11148 00:00:25.280597 # ok 1 rtc.date_read
11149 00:00:25.283389 # # RUN rtc.date_read_loop ...
11150 00:00:25.293409 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11151 00:00:36.490975 <6>[ 37.627024] vpu: disabling
11152 00:00:36.494322 <6>[ 37.630130] vproc2: disabling
11153 00:00:36.497683 <6>[ 37.633468] vproc1: disabling
11154 00:00:36.501169 <6>[ 37.636841] vaud18: disabling
11155 00:00:36.507977 <6>[ 37.640707] vsram_others: disabling
11156 00:00:36.511720 <6>[ 37.644711] va09: disabling
11157 00:00:36.514968 <6>[ 37.647878] vsram_md: disabling
11158 00:00:36.518061 <6>[ 37.651552] Vgpu: disabling
11159 00:00:55.050988 # # rtctest.c:115:date_read_loop:Performed 2615 RTC time reads.
11160 00:00:55.054004 # # OK rtc.date_read_loop
11161 00:00:55.057853 # ok 2 rtc.date_read_loop
11162 00:00:55.060574 # # RUN rtc.uie_read ...
11163 00:00:58.036543 # # OK rtc.uie_read
11164 00:00:58.039924 # ok 3 rtc.uie_read
11165 00:00:58.043212 # # RUN rtc.uie_select ...
11166 00:01:01.036256 # # OK rtc.uie_select
11167 00:01:01.039676 # ok 4 rtc.uie_select
11168 00:01:01.042695 # # RUN rtc.alarm_alm_set ...
11169 00:01:01.049263 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 23:56:23.
11170 00:01:01.052553 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11171 00:01:01.059439 # # alarm_alm_set: Test terminated by assertion
11172 00:01:01.062774 # # FAIL rtc.alarm_alm_set
11173 00:01:01.062909 # not ok 5 rtc.alarm_alm_set
11174 00:01:01.069261 # # RUN rtc.alarm_wkalm_set ...
11175 00:01:01.075403 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 29/05/2024 23:56:23.
11176 00:01:04.038673 # # OK rtc.alarm_wkalm_set
11177 00:01:04.038806 # ok 6 rtc.alarm_wkalm_set
11178 00:01:04.045298 # # RUN rtc.alarm_alm_set_minute ...
11179 00:01:04.048620 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 23:57:00.
11180 00:01:04.055284 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11181 00:01:04.062170 # # alarm_alm_set_minute: Test terminated by assertion
11182 00:01:04.065338 # # FAIL rtc.alarm_alm_set_minute
11183 00:01:04.068729 # not ok 7 rtc.alarm_alm_set_minute
11184 00:01:04.072047 # # RUN rtc.alarm_wkalm_set_minute ...
11185 00:01:04.078611 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 29/05/2024 23:57:00.
11186 00:01:41.034848 # # OK rtc.alarm_wkalm_set_minute
11187 00:01:41.038122 # ok 8 rtc.alarm_wkalm_set_minute
11188 00:01:41.038220 # # FAILED: 6 / 8 tests passed.
11189 00:01:41.044838 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11190 00:01:41.048124 not ok 1 selftests: rtc: rtctest # exit=1
11191 00:01:42.416219 rtc_rtctest_rtc_date_read pass
11192 00:01:42.419508 rtc_rtctest_rtc_date_read_loop pass
11193 00:01:42.422863 rtc_rtctest_rtc_uie_read pass
11194 00:01:42.426223 rtc_rtctest_rtc_uie_select pass
11195 00:01:42.429582 rtc_rtctest_rtc_alarm_alm_set fail
11196 00:01:42.432838 rtc_rtctest_rtc_alarm_wkalm_set pass
11197 00:01:42.436181 rtc_rtctest_rtc_alarm_alm_set_minute fail
11198 00:01:42.439637 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11199 00:01:42.442262 rtc_rtctest fail
11200 00:01:42.490853 + ../../utils/send-to-lava.sh ./output/result.txt
11201 00:01:42.538938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11202 00:01:42.539253 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11204 00:01:42.573477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11205 00:01:42.573782 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11207 00:01:42.609609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11208 00:01:42.609924 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11210 00:01:42.638962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11211 00:01:42.639237 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11213 00:01:42.667498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11214 00:01:42.667799 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11216 00:01:42.700517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11217 00:01:42.700852 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11219 00:01:42.736872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11220 00:01:42.737162 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11222 00:01:42.772781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11223 00:01:42.773090 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11225 00:01:42.804062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11226 00:01:42.804370 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11228 00:01:42.833036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11229 00:01:42.833146 + set +x
11230 00:01:42.833390 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11232 00:01:42.839251 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14084370_1.6.2.3.5>
11233 00:01:42.839367 <LAVA_TEST_RUNNER EXIT>
11234 00:01:42.839656 Received signal: <ENDRUN> 1_kselftest-rtc 14084370_1.6.2.3.5
11235 00:01:42.839733 Ending use of test pattern.
11236 00:01:42.839798 Ending test lava.1_kselftest-rtc (14084370_1.6.2.3.5), duration 84.02
11238 00:01:42.840025 ok: lava_test_shell seems to have completed
11239 00:01:42.840163 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11240 00:01:42.840258 end: 3.1 lava-test-shell (duration 00:01:25) [common]
11241 00:01:42.840355 end: 3 lava-test-retry (duration 00:01:25) [common]
11242 00:01:42.840447 start: 4 finalize (timeout 00:06:35) [common]
11243 00:01:42.840539 start: 4.1 power-off (timeout 00:00:30) [common]
11244 00:01:42.840701 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11245 00:01:42.919180 >> Command sent successfully.
11246 00:01:42.921825 Returned 0 in 0 seconds
11247 00:01:43.022220 end: 4.1 power-off (duration 00:00:00) [common]
11249 00:01:43.022553 start: 4.2 read-feedback (timeout 00:06:34) [common]
11250 00:01:43.022819 Listened to connection for namespace 'common' for up to 1s
11251 00:01:43.023116 Listened to connection for namespace 'common' for up to 1s
11252 00:01:44.023763 Finalising connection for namespace 'common'
11253 00:01:44.023926 Disconnecting from shell: Finalise
11254 00:01:44.024005 / #
11255 00:01:44.124366 end: 4.2 read-feedback (duration 00:00:01) [common]
11256 00:01:44.124604 end: 4 finalize (duration 00:00:01) [common]
11257 00:01:44.124788 Cleaning after the job
11258 00:01:44.124955 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/ramdisk
11259 00:01:44.128044 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/kernel
11260 00:01:44.142348 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/dtb
11261 00:01:44.142656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/nfsrootfs
11262 00:01:44.210728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084370/tftp-deploy-psre5b8m/modules
11263 00:01:44.216542 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084370
11264 00:01:44.779842 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084370
11265 00:01:44.780027 Job finished correctly