Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 23:55:35.943587 lava-dispatcher, installed at version: 2024.03
2 23:55:35.943915 start: 0 validate
3 23:55:35.944154 Start time: 2024-05-29 23:55:35.944129+00:00 (UTC)
4 23:55:35.944399 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:55:35.944649 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:55:36.204863 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:55:36.205072 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:55:36.470070 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:55:36.470289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:55:36.727915 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:55:36.728094 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:55:36.993919 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:55:36.994115 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:55:37.261175 validate duration: 1.32
16 23:55:37.261648 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:55:37.261851 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:55:37.262071 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:55:37.262282 Not decompressing ramdisk as can be used compressed.
20 23:55:37.262442 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:55:37.262594 saving as /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/ramdisk/initrd.cpio.gz
22 23:55:37.262714 total size: 5628169 (5 MB)
23 23:55:37.264776 progress 0 % (0 MB)
24 23:55:37.266907 progress 5 % (0 MB)
25 23:55:37.268737 progress 10 % (0 MB)
26 23:55:37.270277 progress 15 % (0 MB)
27 23:55:37.271987 progress 20 % (1 MB)
28 23:55:37.273531 progress 25 % (1 MB)
29 23:55:37.275126 progress 30 % (1 MB)
30 23:55:37.276825 progress 35 % (1 MB)
31 23:55:37.278254 progress 40 % (2 MB)
32 23:55:37.279839 progress 45 % (2 MB)
33 23:55:37.281406 progress 50 % (2 MB)
34 23:55:37.283001 progress 55 % (2 MB)
35 23:55:37.284734 progress 60 % (3 MB)
36 23:55:37.286232 progress 65 % (3 MB)
37 23:55:37.288039 progress 70 % (3 MB)
38 23:55:37.289520 progress 75 % (4 MB)
39 23:55:37.291124 progress 80 % (4 MB)
40 23:55:37.292584 progress 85 % (4 MB)
41 23:55:37.294231 progress 90 % (4 MB)
42 23:55:37.296218 progress 95 % (5 MB)
43 23:55:37.298133 progress 100 % (5 MB)
44 23:55:37.298387 5 MB downloaded in 0.04 s (150.46 MB/s)
45 23:55:37.298596 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:55:37.298979 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:55:37.299129 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:55:37.299244 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:55:37.299414 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:55:37.299512 saving as /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/kernel/Image
52 23:55:37.299601 total size: 54682112 (52 MB)
53 23:55:37.299691 No compression specified
54 23:55:37.301525 progress 0 % (0 MB)
55 23:55:37.315904 progress 5 % (2 MB)
56 23:55:37.332805 progress 10 % (5 MB)
57 23:55:37.350211 progress 15 % (7 MB)
58 23:55:37.364481 progress 20 % (10 MB)
59 23:55:37.378868 progress 25 % (13 MB)
60 23:55:37.393049 progress 30 % (15 MB)
61 23:55:37.407921 progress 35 % (18 MB)
62 23:55:37.422229 progress 40 % (20 MB)
63 23:55:37.436544 progress 45 % (23 MB)
64 23:55:37.451217 progress 50 % (26 MB)
65 23:55:37.467711 progress 55 % (28 MB)
66 23:55:37.488870 progress 60 % (31 MB)
67 23:55:37.505307 progress 65 % (33 MB)
68 23:55:37.519736 progress 70 % (36 MB)
69 23:55:37.533818 progress 75 % (39 MB)
70 23:55:37.547944 progress 80 % (41 MB)
71 23:55:37.561871 progress 85 % (44 MB)
72 23:55:37.579042 progress 90 % (46 MB)
73 23:55:37.593297 progress 95 % (49 MB)
74 23:55:37.607282 progress 100 % (52 MB)
75 23:55:37.607589 52 MB downloaded in 0.31 s (169.32 MB/s)
76 23:55:37.607755 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:55:37.608030 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:55:37.608165 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:55:37.608254 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:55:37.608405 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:55:37.608483 saving as /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/dtb/mt8192-asurada-spherion-r0.dtb
83 23:55:37.608546 total size: 47258 (0 MB)
84 23:55:37.608610 No compression specified
85 23:55:37.609741 progress 69 % (0 MB)
86 23:55:37.610052 progress 100 % (0 MB)
87 23:55:37.610221 0 MB downloaded in 0.00 s (26.96 MB/s)
88 23:55:37.610354 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:55:37.610611 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:55:37.610725 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:55:37.610837 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:55:37.611003 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:55:37.611084 saving as /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/nfsrootfs/full.rootfs.tar
95 23:55:37.611174 total size: 120894716 (115 MB)
96 23:55:37.611237 Using unxz to decompress xz
97 23:55:37.615682 progress 0 % (0 MB)
98 23:55:37.983052 progress 5 % (5 MB)
99 23:55:38.375047 progress 10 % (11 MB)
100 23:55:38.770474 progress 15 % (17 MB)
101 23:55:39.109896 progress 20 % (23 MB)
102 23:55:39.429051 progress 25 % (28 MB)
103 23:55:39.839567 progress 30 % (34 MB)
104 23:55:40.241840 progress 35 % (40 MB)
105 23:55:40.431994 progress 40 % (46 MB)
106 23:55:40.632881 progress 45 % (51 MB)
107 23:55:40.972562 progress 50 % (57 MB)
108 23:55:41.398731 progress 55 % (63 MB)
109 23:55:41.774368 progress 60 % (69 MB)
110 23:55:42.152946 progress 65 % (74 MB)
111 23:55:42.531245 progress 70 % (80 MB)
112 23:55:42.914844 progress 75 % (86 MB)
113 23:55:43.306600 progress 80 % (92 MB)
114 23:55:43.732235 progress 85 % (98 MB)
115 23:55:44.126694 progress 90 % (103 MB)
116 23:55:44.487215 progress 95 % (109 MB)
117 23:55:44.860903 progress 100 % (115 MB)
118 23:55:44.866363 115 MB downloaded in 7.26 s (15.89 MB/s)
119 23:55:44.866721 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:55:44.867127 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:55:44.867264 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:55:44.867391 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:55:44.867606 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:55:44.867713 saving as /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/modules/modules.tar
126 23:55:44.867808 total size: 8601444 (8 MB)
127 23:55:44.867907 Using unxz to decompress xz
128 23:55:44.873135 progress 0 % (0 MB)
129 23:55:44.893822 progress 5 % (0 MB)
130 23:55:44.919717 progress 10 % (0 MB)
131 23:55:44.946540 progress 15 % (1 MB)
132 23:55:44.972028 progress 20 % (1 MB)
133 23:55:44.998057 progress 25 % (2 MB)
134 23:55:45.023758 progress 30 % (2 MB)
135 23:55:45.048150 progress 35 % (2 MB)
136 23:55:45.076047 progress 40 % (3 MB)
137 23:55:45.104004 progress 45 % (3 MB)
138 23:55:45.135996 progress 50 % (4 MB)
139 23:55:45.162003 progress 55 % (4 MB)
140 23:55:45.187105 progress 60 % (4 MB)
141 23:55:45.215172 progress 65 % (5 MB)
142 23:55:45.248915 progress 70 % (5 MB)
143 23:55:45.280652 progress 75 % (6 MB)
144 23:55:45.305855 progress 80 % (6 MB)
145 23:55:45.334638 progress 85 % (7 MB)
146 23:55:45.360072 progress 90 % (7 MB)
147 23:55:45.389893 progress 95 % (7 MB)
148 23:55:45.419110 progress 100 % (8 MB)
149 23:55:45.424897 8 MB downloaded in 0.56 s (14.72 MB/s)
150 23:55:45.425212 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:55:45.425489 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:55:45.425587 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:55:45.425682 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:55:49.218455 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo
156 23:55:49.218673 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:55:49.218781 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:55:49.218948 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9
159 23:55:49.219079 makedir: /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin
160 23:55:49.219182 makedir: /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/tests
161 23:55:49.219283 makedir: /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/results
162 23:55:49.219386 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-add-keys
163 23:55:49.219534 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-add-sources
164 23:55:49.219667 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-background-process-start
165 23:55:49.219799 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-background-process-stop
166 23:55:49.219928 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-common-functions
167 23:55:49.220061 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-echo-ipv4
168 23:55:49.220189 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-install-packages
169 23:55:49.220318 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-installed-packages
170 23:55:49.220611 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-os-build
171 23:55:49.220743 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-probe-channel
172 23:55:49.220893 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-probe-ip
173 23:55:49.221022 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-target-ip
174 23:55:49.221148 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-target-mac
175 23:55:49.221273 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-target-storage
176 23:55:49.221401 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-case
177 23:55:49.221528 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-event
178 23:55:49.221652 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-feedback
179 23:55:49.221778 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-raise
180 23:55:49.221902 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-reference
181 23:55:49.222029 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-runner
182 23:55:49.222154 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-set
183 23:55:49.222283 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-test-shell
184 23:55:49.222411 Updating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-add-keys (debian)
185 23:55:49.222564 Updating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-add-sources (debian)
186 23:55:49.222705 Updating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-install-packages (debian)
187 23:55:49.222890 Updating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-installed-packages (debian)
188 23:55:49.223068 Updating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/bin/lava-os-build (debian)
189 23:55:49.223194 Creating /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/environment
190 23:55:49.223296 LAVA metadata
191 23:55:49.223364 - LAVA_JOB_ID=14084344
192 23:55:49.223427 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:55:49.223535 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:55:49.223602 skipped lava-vland-overlay
195 23:55:49.223694 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:55:49.223790 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:55:49.223866 skipped lava-multinode-overlay
198 23:55:49.223947 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:55:49.224026 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:55:49.224101 Loading test definitions
201 23:55:49.224189 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:55:49.224259 Using /lava-14084344 at stage 0
203 23:55:49.224580 uuid=14084344_1.6.2.3.1 testdef=None
204 23:55:49.224668 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:55:49.224752 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:55:49.225269 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:55:49.225488 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:55:49.226123 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:55:49.226352 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:55:49.226900 runner path: /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/0/tests/0_timesync-off test_uuid 14084344_1.6.2.3.1
213 23:55:49.227065 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:55:49.227292 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:55:49.227365 Using /lava-14084344 at stage 0
217 23:55:49.227462 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:55:49.227549 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/0/tests/1_kselftest-tpm2'
219 23:55:51.559887 Running '/usr/bin/git checkout kernelci.org
220 23:55:51.731469 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 23:55:51.732635 uuid=14084344_1.6.2.3.5 testdef=None
222 23:55:51.732889 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:55:51.733335 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 23:55:51.734714 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:55:51.735140 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 23:55:51.736978 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:55:51.737418 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 23:55:51.739185 runner path: /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/0/tests/1_kselftest-tpm2 test_uuid 14084344_1.6.2.3.5
232 23:55:51.739327 BOARD='mt8192-asurada-spherion-r0'
233 23:55:51.739444 BRANCH='cip-gitlab'
234 23:55:51.739550 SKIPFILE='/dev/null'
235 23:55:51.739660 SKIP_INSTALL='True'
236 23:55:51.739769 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:55:51.739882 TST_CASENAME=''
238 23:55:51.739989 TST_CMDFILES='tpm2'
239 23:55:51.740226 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:55:51.740648 Creating lava-test-runner.conf files
242 23:55:51.740763 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084344/lava-overlay-crxlemy9/lava-14084344/0 for stage 0
243 23:55:51.740920 - 0_timesync-off
244 23:55:51.741034 - 1_kselftest-tpm2
245 23:55:51.741192 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:55:51.741347 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 23:55:59.573645 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:55:59.573798 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 23:55:59.573893 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:55:59.573994 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:55:59.574086 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 23:55:59.760546 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:55:59.760943 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 23:55:59.761061 extracting modules file /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo
255 23:56:00.026371 extracting modules file /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084344/extract-overlay-ramdisk-xno1yjzw/ramdisk
256 23:56:00.259253 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:56:00.259414 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 23:56:00.259511 [common] Applying overlay to NFS
259 23:56:00.259583 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084344/compress-overlay-axn3tmm7/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo
260 23:56:01.278174 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:56:01.278347 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 23:56:01.278445 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:56:01.278534 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 23:56:01.278619 Building ramdisk /var/lib/lava/dispatcher/tmp/14084344/extract-overlay-ramdisk-xno1yjzw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084344/extract-overlay-ramdisk-xno1yjzw/ramdisk
265 23:56:01.632173 >> 130335 blocks
266 23:56:03.781382 rename /var/lib/lava/dispatcher/tmp/14084344/extract-overlay-ramdisk-xno1yjzw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/ramdisk/ramdisk.cpio.gz
267 23:56:03.781847 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 23:56:03.781964 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 23:56:03.782070 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 23:56:03.782181 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/kernel/Image']
271 23:56:18.528441 Returned 0 in 14 seconds
272 23:56:18.629204 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/kernel/image.itb
273 23:56:19.009034 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:56:19.009496 output: Created: Thu May 30 00:56:18 2024
275 23:56:19.009599 output: Image 0 (kernel-1)
276 23:56:19.009694 output: Description:
277 23:56:19.009786 output: Created: Thu May 30 00:56:18 2024
278 23:56:19.009877 output: Type: Kernel Image
279 23:56:19.009963 output: Compression: lzma compressed
280 23:56:19.010048 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
281 23:56:19.010133 output: Architecture: AArch64
282 23:56:19.010218 output: OS: Linux
283 23:56:19.010303 output: Load Address: 0x00000000
284 23:56:19.010387 output: Entry Point: 0x00000000
285 23:56:19.010473 output: Hash algo: crc32
286 23:56:19.010552 output: Hash value: 907bf91d
287 23:56:19.010633 output: Image 1 (fdt-1)
288 23:56:19.010716 output: Description: mt8192-asurada-spherion-r0
289 23:56:19.010798 output: Created: Thu May 30 00:56:18 2024
290 23:56:19.010880 output: Type: Flat Device Tree
291 23:56:19.010959 output: Compression: uncompressed
292 23:56:19.011038 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:56:19.011117 output: Architecture: AArch64
294 23:56:19.011195 output: Hash algo: crc32
295 23:56:19.011276 output: Hash value: 0f8e4d2e
296 23:56:19.011354 output: Image 2 (ramdisk-1)
297 23:56:19.011431 output: Description: unavailable
298 23:56:19.011510 output: Created: Thu May 30 00:56:18 2024
299 23:56:19.011588 output: Type: RAMDisk Image
300 23:56:19.011666 output: Compression: Unknown Compression
301 23:56:19.011745 output: Data Size: 18729213 Bytes = 18290.25 KiB = 17.86 MiB
302 23:56:19.011825 output: Architecture: AArch64
303 23:56:19.011915 output: OS: Linux
304 23:56:19.011995 output: Load Address: unavailable
305 23:56:19.012074 output: Entry Point: unavailable
306 23:56:19.012163 output: Hash algo: crc32
307 23:56:19.012241 output: Hash value: 30193d5c
308 23:56:19.012318 output: Default Configuration: 'conf-1'
309 23:56:19.012407 output: Configuration 0 (conf-1)
310 23:56:19.012485 output: Description: mt8192-asurada-spherion-r0
311 23:56:19.012563 output: Kernel: kernel-1
312 23:56:19.012641 output: Init Ramdisk: ramdisk-1
313 23:56:19.012719 output: FDT: fdt-1
314 23:56:19.012799 output: Loadables: kernel-1
315 23:56:19.012878 output:
316 23:56:19.013142 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 23:56:19.013280 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 23:56:19.013434 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 23:56:19.013583 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 23:56:19.013699 No LXC device requested
321 23:56:19.013811 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:56:19.013933 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 23:56:19.014044 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:56:19.014140 Checking files for TFTP limit of 4294967296 bytes.
325 23:56:19.014805 end: 1 tftp-deploy (duration 00:00:42) [common]
326 23:56:19.014950 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:56:19.015073 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:56:19.015241 substitutions:
329 23:56:19.015335 - {DTB}: 14084344/tftp-deploy-o2txuo6c/dtb/mt8192-asurada-spherion-r0.dtb
330 23:56:19.015425 - {INITRD}: 14084344/tftp-deploy-o2txuo6c/ramdisk/ramdisk.cpio.gz
331 23:56:19.015511 - {KERNEL}: 14084344/tftp-deploy-o2txuo6c/kernel/Image
332 23:56:19.015594 - {LAVA_MAC}: None
333 23:56:19.015689 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo
334 23:56:19.015775 - {NFS_SERVER_IP}: 192.168.201.1
335 23:56:19.015856 - {PRESEED_CONFIG}: None
336 23:56:19.015935 - {PRESEED_LOCAL}: None
337 23:56:19.016014 - {RAMDISK}: 14084344/tftp-deploy-o2txuo6c/ramdisk/ramdisk.cpio.gz
338 23:56:19.016094 - {ROOT_PART}: None
339 23:56:19.016175 - {ROOT}: None
340 23:56:19.016254 - {SERVER_IP}: 192.168.201.1
341 23:56:19.016351 - {TEE}: None
342 23:56:19.016438 Parsed boot commands:
343 23:56:19.016517 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:56:19.016761 Parsed boot commands: tftpboot 192.168.201.1 14084344/tftp-deploy-o2txuo6c/kernel/image.itb 14084344/tftp-deploy-o2txuo6c/kernel/cmdline
345 23:56:19.016886 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:56:19.017004 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:56:19.017133 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:56:19.017256 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:56:19.017360 Not connected, no need to disconnect.
350 23:56:19.017464 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:56:19.017585 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:56:19.017682 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:56:19.022053 Setting prompt string to ['lava-test: # ']
354 23:56:19.022535 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:56:19.022688 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:56:19.022827 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:56:19.022956 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:56:19.023248 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 23:56:24.158756 >> Command sent successfully.
360 23:56:24.161287 Returned 0 in 5 seconds
361 23:56:24.261741 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:56:24.262220 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:56:24.262361 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:56:24.262455 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:56:24.262522 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:56:24.262591 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:56:24.262972 [Enter `^Ec?' for help]
369 23:56:24.435060
370 23:56:24.435215
371 23:56:24.435292 F0: 102B 0000
372 23:56:24.435360
373 23:56:24.435428 F3: 1001 0000 [0200]
374 23:56:24.438808
375 23:56:24.438897 F3: 1001 0000
376 23:56:24.438968
377 23:56:24.439032 F7: 102D 0000
378 23:56:24.439093
379 23:56:24.441870 F1: 0000 0000
380 23:56:24.441956
381 23:56:24.442024 V0: 0000 0000 [0001]
382 23:56:24.442088
383 23:56:24.445508 00: 0007 8000
384 23:56:24.445627
385 23:56:24.445727 01: 0000 0000
386 23:56:24.445823
387 23:56:24.448313 BP: 0C00 0209 [0000]
388 23:56:24.448424
389 23:56:24.448518 G0: 1182 0000
390 23:56:24.448607
391 23:56:24.452105 EC: 0000 0021 [4000]
392 23:56:24.452189
393 23:56:24.452257 S7: 0000 0000 [0000]
394 23:56:24.452320
395 23:56:24.455870 CC: 0000 0000 [0001]
396 23:56:24.455954
397 23:56:24.456020 T0: 0000 0040 [010F]
398 23:56:24.456083
399 23:56:24.456142 Jump to BL
400 23:56:24.456200
401 23:56:24.482179
402 23:56:24.482279
403 23:56:24.489612 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 23:56:24.493350 ARM64: Exception handlers installed.
405 23:56:24.497039 ARM64: Testing exception
406 23:56:24.500534 ARM64: Done test exception
407 23:56:24.506893 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 23:56:24.517282 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 23:56:24.524179 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 23:56:24.533905 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 23:56:24.540666 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 23:56:24.547657 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 23:56:24.559098 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 23:56:24.565886 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 23:56:24.584965 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 23:56:24.588190 WDT: Last reset was cold boot
417 23:56:24.592037 SPI1(PAD0) initialized at 2873684 Hz
418 23:56:24.595128 SPI5(PAD0) initialized at 992727 Hz
419 23:56:24.598556 VBOOT: Loading verstage.
420 23:56:24.605301 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 23:56:24.609089 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 23:56:24.612536 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 23:56:24.615591 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 23:56:24.622515 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 23:56:24.629330 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 23:56:24.640098 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 23:56:24.640188
428 23:56:24.640292
429 23:56:24.650588 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 23:56:24.654300 ARM64: Exception handlers installed.
431 23:56:24.658015 ARM64: Testing exception
432 23:56:24.658131 ARM64: Done test exception
433 23:56:24.664205 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 23:56:24.667312 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 23:56:24.681277 Probing TPM: . done!
436 23:56:24.681372 TPM ready after 0 ms
437 23:56:24.687733 Connected to device vid:did:rid of 1ae0:0028:00
438 23:56:24.695170 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 23:56:24.754814 Initialized TPM device CR50 revision 0
440 23:56:24.766593 tlcl_send_startup: Startup return code is 0
441 23:56:24.766720 TPM: setup succeeded
442 23:56:24.778156 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 23:56:24.786791 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 23:56:24.799056 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 23:56:24.808971 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 23:56:24.812748 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 23:56:24.816759 in-header: 03 07 00 00 08 00 00 00
448 23:56:24.819870 in-data: aa e4 47 04 13 02 00 00
449 23:56:24.823675 Chrome EC: UHEPI supported
450 23:56:24.826967 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 23:56:24.830753 in-header: 03 95 00 00 08 00 00 00
452 23:56:24.834702 in-data: 18 20 20 08 00 00 00 00
453 23:56:24.834818 Phase 1
454 23:56:24.838328 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 23:56:24.846077 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 23:56:24.853143 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 23:56:24.853260 Recovery requested (1009000e)
458 23:56:24.865363 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:56:24.869099 tlcl_extend: response is 0
460 23:56:24.880277 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:56:24.884610 tlcl_extend: response is 0
462 23:56:24.891508 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:56:24.910956 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 23:56:24.917353 BS: bootblock times (exec / console): total (unknown) / 149 ms
465 23:56:24.917490
466 23:56:24.917611
467 23:56:24.927674 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:56:24.930500 ARM64: Exception handlers installed.
469 23:56:24.934071 ARM64: Testing exception
470 23:56:24.934202 ARM64: Done test exception
471 23:56:24.956354 pmic_efuse_setting: Set efuses in 11 msecs
472 23:56:24.960156 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:56:24.966290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:56:24.969689 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:56:24.977190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:56:24.980848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:56:24.984591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:56:24.988236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:56:24.995867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:56:24.999723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:56:25.003187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:56:25.006908 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:56:25.014575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:56:25.018491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:56:25.022710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:56:25.029669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:56:25.033297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:56:25.040540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:56:25.044196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:56:25.051825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:56:25.059503 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:56:25.063432 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:56:25.066839 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:56:25.073650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:56:25.081569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:56:25.085350 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:56:25.088264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:56:25.095870 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:56:25.099671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:56:25.107594 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:56:25.110582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:56:25.114711 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:56:25.121295 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:56:25.125353 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:56:25.129290 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:56:25.136591 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:56:25.140728 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:56:25.144402 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:56:25.151409 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:56:25.154998 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:56:25.158562 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:56:25.166088 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:56:25.169755 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:56:25.173280 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:56:25.177653 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:56:25.180495 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:56:25.188257 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:56:25.192059 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:56:25.196058 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:56:25.199709 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:56:25.203249 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:56:25.206522 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:56:25.210419 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:56:25.217817 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 23:56:25.229456 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:56:25.232970 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:56:25.240649 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:56:25.247588 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:56:25.254831 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:56:25.258711 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:56:25.261750 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:56:25.269865 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
533 23:56:25.273780 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:56:25.281894 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 23:56:25.285380 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:56:25.294963 [RTC]rtc_get_frequency_meter,154: input=15, output=759
537 23:56:25.303956 [RTC]rtc_get_frequency_meter,154: input=23, output=942
538 23:56:25.313232 [RTC]rtc_get_frequency_meter,154: input=19, output=851
539 23:56:25.322750 [RTC]rtc_get_frequency_meter,154: input=17, output=805
540 23:56:25.332273 [RTC]rtc_get_frequency_meter,154: input=16, output=782
541 23:56:25.341724 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 23:56:25.351785 [RTC]rtc_get_frequency_meter,154: input=17, output=805
543 23:56:25.355547 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 23:56:25.359322 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 23:56:25.363140 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:56:25.369913 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 23:56:25.373523 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:56:25.377068 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 23:56:25.380974 ADC[4]: Raw value=905465 ID=7
550 23:56:25.385067 ADC[3]: Raw value=213441 ID=1
551 23:56:25.385165 RAM Code: 0x71
552 23:56:25.388047 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:56:25.391978 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:56:25.403408 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 23:56:25.407152 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 23:56:25.410498 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:56:25.415872 in-header: 03 07 00 00 08 00 00 00
558 23:56:25.418935 in-data: aa e4 47 04 13 02 00 00
559 23:56:25.422718 Chrome EC: UHEPI supported
560 23:56:25.430023 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:56:25.434190 in-header: 03 95 00 00 08 00 00 00
562 23:56:25.434272 in-data: 18 20 20 08 00 00 00 00
563 23:56:25.438168 MRC: failed to locate region type 0.
564 23:56:25.445511 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:56:25.449595 DRAM-K: Running full calibration
566 23:56:25.453029 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 23:56:25.457579 header.status = 0x0
568 23:56:25.460651 header.version = 0x6 (expected: 0x6)
569 23:56:25.464425 header.size = 0xd00 (expected: 0xd00)
570 23:56:25.464516 header.flags = 0x0
571 23:56:25.471637 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:56:25.489186 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
573 23:56:25.496664 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:56:25.496758 dram_init: ddr_geometry: 2
575 23:56:25.500489 [EMI] MDL number = 2
576 23:56:25.503766 [EMI] Get MDL freq = 0
577 23:56:25.503879 dram_init: ddr_type: 0
578 23:56:25.507052 is_discrete_lpddr4: 1
579 23:56:25.511480 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:56:25.511575
581 23:56:25.511672
582 23:56:25.511764 [Bian_co] ETT version 0.0.0.1
583 23:56:25.518363 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 23:56:25.518444
585 23:56:25.522259 dramc_set_vcore_voltage set vcore to 650000
586 23:56:25.522350 Read voltage for 800, 4
587 23:56:25.526197 Vio18 = 0
588 23:56:25.526275 Vcore = 650000
589 23:56:25.526341 Vdram = 0
590 23:56:25.526403 Vddq = 0
591 23:56:25.529910 Vmddr = 0
592 23:56:25.529997 dram_init: config_dvfs: 1
593 23:56:25.537015 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:56:25.540900 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:56:25.544693 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
596 23:56:25.548650 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
597 23:56:25.552405 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 23:56:25.555554 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 23:56:25.559160 MEM_TYPE=3, freq_sel=18
600 23:56:25.562695 sv_algorithm_assistance_LP4_1600
601 23:56:25.566202 ============ PULL DRAM RESETB DOWN ============
602 23:56:25.569726 ========== PULL DRAM RESETB DOWN end =========
603 23:56:25.576279 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:56:25.579148 ===================================
605 23:56:25.579260 LPDDR4 DRAM CONFIGURATION
606 23:56:25.583780 ===================================
607 23:56:25.587037 EX_ROW_EN[0] = 0x0
608 23:56:25.587156 EX_ROW_EN[1] = 0x0
609 23:56:25.590896 LP4Y_EN = 0x0
610 23:56:25.591009 WORK_FSP = 0x0
611 23:56:25.594432 WL = 0x2
612 23:56:25.594544 RL = 0x2
613 23:56:25.594644 BL = 0x2
614 23:56:25.598377 RPST = 0x0
615 23:56:25.598489 RD_PRE = 0x0
616 23:56:25.601751 WR_PRE = 0x1
617 23:56:25.601831 WR_PST = 0x0
618 23:56:25.605175 DBI_WR = 0x0
619 23:56:25.605262 DBI_RD = 0x0
620 23:56:25.608662 OTF = 0x1
621 23:56:25.611678 ===================================
622 23:56:25.614936 ===================================
623 23:56:25.615022 ANA top config
624 23:56:25.618736 ===================================
625 23:56:25.621944 DLL_ASYNC_EN = 0
626 23:56:25.625284 ALL_SLAVE_EN = 1
627 23:56:25.628556 NEW_RANK_MODE = 1
628 23:56:25.628674 DLL_IDLE_MODE = 1
629 23:56:25.631598 LP45_APHY_COMB_EN = 1
630 23:56:25.635527 TX_ODT_DIS = 1
631 23:56:25.639285 NEW_8X_MODE = 1
632 23:56:25.642690 ===================================
633 23:56:25.642824 ===================================
634 23:56:25.645825 data_rate = 1600
635 23:56:25.649047 CKR = 1
636 23:56:25.652556 DQ_P2S_RATIO = 8
637 23:56:25.656152 ===================================
638 23:56:25.659924 CA_P2S_RATIO = 8
639 23:56:25.663172 DQ_CA_OPEN = 0
640 23:56:25.663256 DQ_SEMI_OPEN = 0
641 23:56:25.665986 CA_SEMI_OPEN = 0
642 23:56:25.669597 CA_FULL_RATE = 0
643 23:56:25.672933 DQ_CKDIV4_EN = 1
644 23:56:25.676092 CA_CKDIV4_EN = 1
645 23:56:25.679376 CA_PREDIV_EN = 0
646 23:56:25.679464 PH8_DLY = 0
647 23:56:25.682828 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:56:25.686109 DQ_AAMCK_DIV = 4
649 23:56:25.689284 CA_AAMCK_DIV = 4
650 23:56:25.692761 CA_ADMCK_DIV = 4
651 23:56:25.695889 DQ_TRACK_CA_EN = 0
652 23:56:25.695971 CA_PICK = 800
653 23:56:25.699682 CA_MCKIO = 800
654 23:56:25.703267 MCKIO_SEMI = 0
655 23:56:25.706559 PLL_FREQ = 3068
656 23:56:25.710383 DQ_UI_PI_RATIO = 32
657 23:56:25.710491 CA_UI_PI_RATIO = 0
658 23:56:25.714453 ===================================
659 23:56:25.717434 ===================================
660 23:56:25.721387 memory_type:LPDDR4
661 23:56:25.721473 GP_NUM : 10
662 23:56:25.725119 SRAM_EN : 1
663 23:56:25.725205 MD32_EN : 0
664 23:56:25.728963 ===================================
665 23:56:25.733103 [ANA_INIT] >>>>>>>>>>>>>>
666 23:56:25.736516 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:56:25.740140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:56:25.743270 ===================================
669 23:56:25.743383 data_rate = 1600,PCW = 0X7600
670 23:56:25.746678 ===================================
671 23:56:25.750659 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:56:25.756768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:56:25.763749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:56:25.766990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:56:25.770262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:56:25.773638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:56:25.776787 [ANA_INIT] flow start
678 23:56:25.776899 [ANA_INIT] PLL >>>>>>>>
679 23:56:25.780096 [ANA_INIT] PLL <<<<<<<<
680 23:56:25.783221 [ANA_INIT] MIDPI >>>>>>>>
681 23:56:25.787045 [ANA_INIT] MIDPI <<<<<<<<
682 23:56:25.787157 [ANA_INIT] DLL >>>>>>>>
683 23:56:25.790420 [ANA_INIT] flow end
684 23:56:25.793868 ============ LP4 DIFF to SE enter ============
685 23:56:25.796568 ============ LP4 DIFF to SE exit ============
686 23:56:25.800187 [ANA_INIT] <<<<<<<<<<<<<
687 23:56:25.803477 [Flow] Enable top DCM control >>>>>
688 23:56:25.806907 [Flow] Enable top DCM control <<<<<
689 23:56:25.810570 Enable DLL master slave shuffle
690 23:56:25.816940 ==============================================================
691 23:56:25.817066 Gating Mode config
692 23:56:25.823743 ==============================================================
693 23:56:25.823856 Config description:
694 23:56:25.833565 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:56:25.840635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:56:25.846888 SELPH_MODE 0: By rank 1: By Phase
697 23:56:25.850435 ==============================================================
698 23:56:25.853550 GAT_TRACK_EN = 1
699 23:56:25.856892 RX_GATING_MODE = 2
700 23:56:25.860414 RX_GATING_TRACK_MODE = 2
701 23:56:25.863204 SELPH_MODE = 1
702 23:56:25.867098 PICG_EARLY_EN = 1
703 23:56:25.869946 VALID_LAT_VALUE = 1
704 23:56:25.873731 ==============================================================
705 23:56:25.876979 Enter into Gating configuration >>>>
706 23:56:25.880156 Exit from Gating configuration <<<<
707 23:56:25.884012 Enter into DVFS_PRE_config >>>>>
708 23:56:25.896722 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:56:25.900285 Exit from DVFS_PRE_config <<<<<
710 23:56:25.900395 Enter into PICG configuration >>>>
711 23:56:25.903705 Exit from PICG configuration <<<<
712 23:56:25.906685 [RX_INPUT] configuration >>>>>
713 23:56:25.909945 [RX_INPUT] configuration <<<<<
714 23:56:25.917027 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:56:25.920474 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:56:25.926556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:56:25.933375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:56:25.940667 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:56:25.946941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:56:25.950231 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:56:25.953601 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:56:25.957066 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:56:25.963651 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:56:25.966578 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:56:25.970298 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:56:25.973716 ===================================
727 23:56:25.977255 LPDDR4 DRAM CONFIGURATION
728 23:56:25.980115 ===================================
729 23:56:25.980227 EX_ROW_EN[0] = 0x0
730 23:56:25.983276 EX_ROW_EN[1] = 0x0
731 23:56:25.986914 LP4Y_EN = 0x0
732 23:56:25.987027 WORK_FSP = 0x0
733 23:56:25.990235 WL = 0x2
734 23:56:25.990344 RL = 0x2
735 23:56:25.993500 BL = 0x2
736 23:56:25.993620 RPST = 0x0
737 23:56:25.997236 RD_PRE = 0x0
738 23:56:25.997317 WR_PRE = 0x1
739 23:56:26.000257 WR_PST = 0x0
740 23:56:26.000371 DBI_WR = 0x0
741 23:56:26.003623 DBI_RD = 0x0
742 23:56:26.003699 OTF = 0x1
743 23:56:26.007175 ===================================
744 23:56:26.010060 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:56:26.017250 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:56:26.020666 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:56:26.024152 ===================================
748 23:56:26.027262 LPDDR4 DRAM CONFIGURATION
749 23:56:26.030143 ===================================
750 23:56:26.030217 EX_ROW_EN[0] = 0x10
751 23:56:26.033990 EX_ROW_EN[1] = 0x0
752 23:56:26.034102 LP4Y_EN = 0x0
753 23:56:26.037229 WORK_FSP = 0x0
754 23:56:26.037314 WL = 0x2
755 23:56:26.040503 RL = 0x2
756 23:56:26.040589 BL = 0x2
757 23:56:26.043664 RPST = 0x0
758 23:56:26.043748 RD_PRE = 0x0
759 23:56:26.046873 WR_PRE = 0x1
760 23:56:26.046957 WR_PST = 0x0
761 23:56:26.050778 DBI_WR = 0x0
762 23:56:26.050863 DBI_RD = 0x0
763 23:56:26.054170 OTF = 0x1
764 23:56:26.057468 ===================================
765 23:56:26.063642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:56:26.067490 nWR fixed to 40
767 23:56:26.070588 [ModeRegInit_LP4] CH0 RK0
768 23:56:26.070672 [ModeRegInit_LP4] CH0 RK1
769 23:56:26.073676 [ModeRegInit_LP4] CH1 RK0
770 23:56:26.076992 [ModeRegInit_LP4] CH1 RK1
771 23:56:26.077104 match AC timing 13
772 23:56:26.083791 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 23:56:26.087196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:56:26.090453 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:56:26.097400 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:56:26.100899 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:56:26.101010 [EMI DOE] emi_dcm 0
778 23:56:26.107099 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:56:26.107211 ==
780 23:56:26.110577 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:56:26.114178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:56:26.114298 ==
783 23:56:26.120606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:56:26.123870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:56:26.134432 [CA 0] Center 36 (6~67) winsize 62
786 23:56:26.138084 [CA 1] Center 36 (6~67) winsize 62
787 23:56:26.141473 [CA 2] Center 34 (4~65) winsize 62
788 23:56:26.144484 [CA 3] Center 33 (3~64) winsize 62
789 23:56:26.148219 [CA 4] Center 33 (2~64) winsize 63
790 23:56:26.151437 [CA 5] Center 32 (2~62) winsize 61
791 23:56:26.151540
792 23:56:26.154689 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:56:26.154768
794 23:56:26.157903 [CATrainingPosCal] consider 1 rank data
795 23:56:26.161218 u2DelayCellTimex100 = 270/100 ps
796 23:56:26.164460 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
797 23:56:26.167635 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:56:26.174800 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
799 23:56:26.177813 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
800 23:56:26.181139 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
801 23:56:26.184457 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
802 23:56:26.184537
803 23:56:26.187842 CA PerBit enable=1, Macro0, CA PI delay=32
804 23:56:26.187951
805 23:56:26.191127 [CBTSetCACLKResult] CA Dly = 32
806 23:56:26.191251 CS Dly: 5 (0~36)
807 23:56:26.191350 ==
808 23:56:26.194475 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:56:26.201386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:56:26.201501 ==
811 23:56:26.204808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:56:26.211241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:56:26.220845 [CA 0] Center 36 (6~67) winsize 62
814 23:56:26.223987 [CA 1] Center 36 (6~67) winsize 62
815 23:56:26.227613 [CA 2] Center 34 (3~65) winsize 63
816 23:56:26.230910 [CA 3] Center 33 (3~64) winsize 62
817 23:56:26.233886 [CA 4] Center 32 (2~63) winsize 62
818 23:56:26.237075 [CA 5] Center 32 (2~63) winsize 62
819 23:56:26.237192
820 23:56:26.240815 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 23:56:26.240922
822 23:56:26.243925 [CATrainingPosCal] consider 2 rank data
823 23:56:26.247100 u2DelayCellTimex100 = 270/100 ps
824 23:56:26.251083 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
825 23:56:26.254370 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:56:26.260474 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
827 23:56:26.263782 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
828 23:56:26.267725 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
829 23:56:26.270773 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
830 23:56:26.270889
831 23:56:26.273842 CA PerBit enable=1, Macro0, CA PI delay=32
832 23:56:26.273974
833 23:56:26.277627 [CBTSetCACLKResult] CA Dly = 32
834 23:56:26.277756 CS Dly: 5 (0~37)
835 23:56:26.277875
836 23:56:26.281714 ----->DramcWriteLeveling(PI) begin...
837 23:56:26.281839 ==
838 23:56:26.284861 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:56:26.288314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 23:56:26.291714 ==
841 23:56:26.291832 Write leveling (Byte 0): 33 => 33
842 23:56:26.295941 Write leveling (Byte 1): 31 => 31
843 23:56:26.299674 DramcWriteLeveling(PI) end<-----
844 23:56:26.299785
845 23:56:26.299882 ==
846 23:56:26.302899 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:56:26.306090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 23:56:26.306178 ==
849 23:56:26.310159 [Gating] SW mode calibration
850 23:56:26.316848 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:56:26.323509 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:56:26.326696 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 23:56:26.329926 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 23:56:26.336760 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 23:56:26.340513 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:56:26.343233 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:56:26.350376 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:56:26.353240 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:56:26.356779 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:56:26.359993 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:56:26.366785 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:56:26.370133 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:56:26.373658 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:56:26.380025 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:56:26.383699 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:56:26.386960 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:56:26.393651 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:56:26.396709 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:56:26.399903 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 23:56:26.406859 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 23:56:26.409953 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 23:56:26.413750 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:56:26.420283 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:56:26.423528 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:56:26.426686 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:56:26.433700 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:56:26.437141 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:56:26.440255 0 9 8 | B1->B0 | 2323 2e2e | 1 0 | (1 1) (0 0)
879 23:56:26.443702 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
880 23:56:26.450182 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:56:26.453682 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:56:26.456837 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:56:26.463860 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:56:26.467179 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:56:26.470555 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
886 23:56:26.476778 0 10 8 | B1->B0 | 3030 2525 | 0 1 | (0 0) (0 0)
887 23:56:26.480379 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
888 23:56:26.483465 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:56:26.490253 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:56:26.493855 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:56:26.497040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:56:26.503537 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:56:26.506739 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
894 23:56:26.509974 0 11 8 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
895 23:56:26.516767 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
896 23:56:26.520280 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:56:26.523996 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:56:26.527076 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:56:26.533596 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:56:26.537249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:56:26.540550 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:56:26.546738 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
903 23:56:26.550494 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:56:26.554037 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:56:26.560316 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:56:26.563853 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:56:26.566975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:56:26.573932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:56:26.577095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:56:26.580291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:56:26.586933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:56:26.590419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:56:26.593377 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:56:26.600553 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:56:26.603815 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:56:26.606980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:56:26.613658 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 23:56:26.616700 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:56:26.620538 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 23:56:26.623722 Total UI for P1: 0, mck2ui 16
921 23:56:26.627056 best dqsien dly found for B0: ( 0, 14, 6)
922 23:56:26.630202 Total UI for P1: 0, mck2ui 16
923 23:56:26.633591 best dqsien dly found for B1: ( 0, 14, 10)
924 23:56:26.638094 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 23:56:26.640685 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
926 23:56:26.640802
927 23:56:26.643966 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 23:56:26.647370 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
929 23:56:26.650705 [Gating] SW calibration Done
930 23:56:26.650816 ==
931 23:56:26.655128 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:56:26.657685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:56:26.657790 ==
934 23:56:26.661156 RX Vref Scan: 0
935 23:56:26.661267
936 23:56:26.664576 RX Vref 0 -> 0, step: 1
937 23:56:26.664662
938 23:56:26.664732 RX Delay -130 -> 252, step: 16
939 23:56:26.670872 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 23:56:26.674440 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 23:56:26.677599 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
942 23:56:26.680801 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
943 23:56:26.684236 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 23:56:26.691004 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 23:56:26.694546 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 23:56:26.697334 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
947 23:56:26.701384 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
948 23:56:26.704246 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
949 23:56:26.711352 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
950 23:56:26.714516 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
951 23:56:26.717455 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
952 23:56:26.721009 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
953 23:56:26.724176 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
954 23:56:26.731222 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
955 23:56:26.731336 ==
956 23:56:26.734382 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:56:26.737790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:56:26.737902 ==
959 23:56:26.737999 DQS Delay:
960 23:56:26.741223 DQS0 = 0, DQS1 = 0
961 23:56:26.741334 DQM Delay:
962 23:56:26.744062 DQM0 = 92, DQM1 = 85
963 23:56:26.744163 DQ Delay:
964 23:56:26.747901 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
965 23:56:26.751256 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
966 23:56:26.754733 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
967 23:56:26.757867 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
968 23:56:26.757979
969 23:56:26.758075
970 23:56:26.758175 ==
971 23:56:26.761017 Dram Type= 6, Freq= 0, CH_0, rank 0
972 23:56:26.764359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 23:56:26.764447 ==
974 23:56:26.767931
975 23:56:26.768038
976 23:56:26.768133 TX Vref Scan disable
977 23:56:26.771224 == TX Byte 0 ==
978 23:56:26.774651 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
979 23:56:26.778197 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
980 23:56:26.781507 == TX Byte 1 ==
981 23:56:26.784494 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
982 23:56:26.787943 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
983 23:56:26.788052 ==
984 23:56:26.791354 Dram Type= 6, Freq= 0, CH_0, rank 0
985 23:56:26.797738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 23:56:26.797848 ==
987 23:56:26.810119 TX Vref=22, minBit 8, minWin=27, winSum=448
988 23:56:26.813120 TX Vref=24, minBit 8, minWin=27, winSum=452
989 23:56:26.816717 TX Vref=26, minBit 8, minWin=27, winSum=452
990 23:56:26.819932 TX Vref=28, minBit 4, minWin=28, winSum=457
991 23:56:26.823088 TX Vref=30, minBit 5, minWin=28, winSum=457
992 23:56:26.826204 TX Vref=32, minBit 2, minWin=28, winSum=453
993 23:56:26.833005 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 28
994 23:56:26.833096
995 23:56:26.836864 Final TX Range 1 Vref 28
996 23:56:26.836975
997 23:56:26.837073 ==
998 23:56:26.839623 Dram Type= 6, Freq= 0, CH_0, rank 0
999 23:56:26.843406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 23:56:26.843512 ==
1001 23:56:26.843606
1002 23:56:26.846632
1003 23:56:26.846715 TX Vref Scan disable
1004 23:56:26.849916 == TX Byte 0 ==
1005 23:56:26.853003 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1006 23:56:26.856516 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1007 23:56:26.859573 == TX Byte 1 ==
1008 23:56:26.863716 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1009 23:56:26.866733 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1010 23:56:26.869561
1011 23:56:26.869664 [DATLAT]
1012 23:56:26.869761 Freq=800, CH0 RK0
1013 23:56:26.869852
1014 23:56:26.873405 DATLAT Default: 0xa
1015 23:56:26.873481 0, 0xFFFF, sum = 0
1016 23:56:26.876852 1, 0xFFFF, sum = 0
1017 23:56:26.876930 2, 0xFFFF, sum = 0
1018 23:56:26.880481 3, 0xFFFF, sum = 0
1019 23:56:26.880589 4, 0xFFFF, sum = 0
1020 23:56:26.883296 5, 0xFFFF, sum = 0
1021 23:56:26.883373 6, 0xFFFF, sum = 0
1022 23:56:26.886463 7, 0xFFFF, sum = 0
1023 23:56:26.886567 8, 0xFFFF, sum = 0
1024 23:56:26.890208 9, 0x0, sum = 1
1025 23:56:26.890325 10, 0x0, sum = 2
1026 23:56:26.893138 11, 0x0, sum = 3
1027 23:56:26.893244 12, 0x0, sum = 4
1028 23:56:26.896731 best_step = 10
1029 23:56:26.896807
1030 23:56:26.896871 ==
1031 23:56:26.900011 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 23:56:26.902973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 23:56:26.903077 ==
1034 23:56:26.906712 RX Vref Scan: 1
1035 23:56:26.906815
1036 23:56:26.906912 Set Vref Range= 32 -> 127
1037 23:56:26.907002
1038 23:56:26.909954 RX Vref 32 -> 127, step: 1
1039 23:56:26.910055
1040 23:56:26.913123 RX Delay -95 -> 252, step: 8
1041 23:56:26.913203
1042 23:56:26.916491 Set Vref, RX VrefLevel [Byte0]: 32
1043 23:56:26.920196 [Byte1]: 32
1044 23:56:26.920300
1045 23:56:26.923090 Set Vref, RX VrefLevel [Byte0]: 33
1046 23:56:26.926975 [Byte1]: 33
1047 23:56:26.930296
1048 23:56:26.930373 Set Vref, RX VrefLevel [Byte0]: 34
1049 23:56:26.933124 [Byte1]: 34
1050 23:56:26.937716
1051 23:56:26.937819 Set Vref, RX VrefLevel [Byte0]: 35
1052 23:56:26.940825 [Byte1]: 35
1053 23:56:26.945472
1054 23:56:26.945574 Set Vref, RX VrefLevel [Byte0]: 36
1055 23:56:26.948530 [Byte1]: 36
1056 23:56:26.953111
1057 23:56:26.953190 Set Vref, RX VrefLevel [Byte0]: 37
1058 23:56:26.956745 [Byte1]: 37
1059 23:56:26.960681
1060 23:56:26.960789 Set Vref, RX VrefLevel [Byte0]: 38
1061 23:56:26.963798 [Byte1]: 38
1062 23:56:26.968186
1063 23:56:26.968293 Set Vref, RX VrefLevel [Byte0]: 39
1064 23:56:26.971607 [Byte1]: 39
1065 23:56:26.975924
1066 23:56:26.976007 Set Vref, RX VrefLevel [Byte0]: 40
1067 23:56:26.979236 [Byte1]: 40
1068 23:56:26.983315
1069 23:56:26.983427 Set Vref, RX VrefLevel [Byte0]: 41
1070 23:56:26.986548 [Byte1]: 41
1071 23:56:26.991035
1072 23:56:26.991124 Set Vref, RX VrefLevel [Byte0]: 42
1073 23:56:26.993890 [Byte1]: 42
1074 23:56:26.998318
1075 23:56:26.998424 Set Vref, RX VrefLevel [Byte0]: 43
1076 23:56:27.001523 [Byte1]: 43
1077 23:56:27.005910
1078 23:56:27.006012 Set Vref, RX VrefLevel [Byte0]: 44
1079 23:56:27.009492 [Byte1]: 44
1080 23:56:27.013600
1081 23:56:27.013704 Set Vref, RX VrefLevel [Byte0]: 45
1082 23:56:27.016613 [Byte1]: 45
1083 23:56:27.021164
1084 23:56:27.021241 Set Vref, RX VrefLevel [Byte0]: 46
1085 23:56:27.024321 [Byte1]: 46
1086 23:56:27.028697
1087 23:56:27.028806 Set Vref, RX VrefLevel [Byte0]: 47
1088 23:56:27.032088 [Byte1]: 47
1089 23:56:27.036598
1090 23:56:27.036678 Set Vref, RX VrefLevel [Byte0]: 48
1091 23:56:27.039318 [Byte1]: 48
1092 23:56:27.043714
1093 23:56:27.043818 Set Vref, RX VrefLevel [Byte0]: 49
1094 23:56:27.047183 [Byte1]: 49
1095 23:56:27.051314
1096 23:56:27.051418 Set Vref, RX VrefLevel [Byte0]: 50
1097 23:56:27.054560 [Byte1]: 50
1098 23:56:27.059604
1099 23:56:27.059680 Set Vref, RX VrefLevel [Byte0]: 51
1100 23:56:27.062566 [Byte1]: 51
1101 23:56:27.066762
1102 23:56:27.066837 Set Vref, RX VrefLevel [Byte0]: 52
1103 23:56:27.069800 [Byte1]: 52
1104 23:56:27.074584
1105 23:56:27.074690 Set Vref, RX VrefLevel [Byte0]: 53
1106 23:56:27.077523 [Byte1]: 53
1107 23:56:27.081895
1108 23:56:27.081995 Set Vref, RX VrefLevel [Byte0]: 54
1109 23:56:27.085083 [Byte1]: 54
1110 23:56:27.089572
1111 23:56:27.089676 Set Vref, RX VrefLevel [Byte0]: 55
1112 23:56:27.092935 [Byte1]: 55
1113 23:56:27.097192
1114 23:56:27.097267 Set Vref, RX VrefLevel [Byte0]: 56
1115 23:56:27.100774 [Byte1]: 56
1116 23:56:27.104740
1117 23:56:27.104845 Set Vref, RX VrefLevel [Byte0]: 57
1118 23:56:27.108326 [Byte1]: 57
1119 23:56:27.112226
1120 23:56:27.112335 Set Vref, RX VrefLevel [Byte0]: 58
1121 23:56:27.115887 [Byte1]: 58
1122 23:56:27.120273
1123 23:56:27.120383 Set Vref, RX VrefLevel [Byte0]: 59
1124 23:56:27.123703 [Byte1]: 59
1125 23:56:27.127860
1126 23:56:27.127965 Set Vref, RX VrefLevel [Byte0]: 60
1127 23:56:27.130949 [Byte1]: 60
1128 23:56:27.135388
1129 23:56:27.135511 Set Vref, RX VrefLevel [Byte0]: 61
1130 23:56:27.138573 [Byte1]: 61
1131 23:56:27.143179
1132 23:56:27.143300 Set Vref, RX VrefLevel [Byte0]: 62
1133 23:56:27.146103 [Byte1]: 62
1134 23:56:27.150205
1135 23:56:27.150326 Set Vref, RX VrefLevel [Byte0]: 63
1136 23:56:27.153341 [Byte1]: 63
1137 23:56:27.158201
1138 23:56:27.158306 Set Vref, RX VrefLevel [Byte0]: 64
1139 23:56:27.161474 [Byte1]: 64
1140 23:56:27.165711
1141 23:56:27.165836 Set Vref, RX VrefLevel [Byte0]: 65
1142 23:56:27.168782 [Byte1]: 65
1143 23:56:27.173079
1144 23:56:27.173198 Set Vref, RX VrefLevel [Byte0]: 66
1145 23:56:27.176438 [Byte1]: 66
1146 23:56:27.180895
1147 23:56:27.181015 Set Vref, RX VrefLevel [Byte0]: 67
1148 23:56:27.183910 [Byte1]: 67
1149 23:56:27.188280
1150 23:56:27.188395 Set Vref, RX VrefLevel [Byte0]: 68
1151 23:56:27.192145 [Byte1]: 68
1152 23:56:27.196264
1153 23:56:27.196375 Set Vref, RX VrefLevel [Byte0]: 69
1154 23:56:27.199422 [Byte1]: 69
1155 23:56:27.203635
1156 23:56:27.203719 Set Vref, RX VrefLevel [Byte0]: 70
1157 23:56:27.207147 [Byte1]: 70
1158 23:56:27.210931
1159 23:56:27.211016 Set Vref, RX VrefLevel [Byte0]: 71
1160 23:56:27.214878 [Byte1]: 71
1161 23:56:27.218589
1162 23:56:27.218667 Set Vref, RX VrefLevel [Byte0]: 72
1163 23:56:27.222325 [Byte1]: 72
1164 23:56:27.226774
1165 23:56:27.226878 Set Vref, RX VrefLevel [Byte0]: 73
1166 23:56:27.229775 [Byte1]: 73
1167 23:56:27.234331
1168 23:56:27.234437 Set Vref, RX VrefLevel [Byte0]: 74
1169 23:56:27.237337 [Byte1]: 74
1170 23:56:27.241871
1171 23:56:27.241976 Set Vref, RX VrefLevel [Byte0]: 75
1172 23:56:27.245005 [Byte1]: 75
1173 23:56:27.249509
1174 23:56:27.249617 Set Vref, RX VrefLevel [Byte0]: 76
1175 23:56:27.252674 [Byte1]: 76
1176 23:56:27.256719
1177 23:56:27.256821 Set Vref, RX VrefLevel [Byte0]: 77
1178 23:56:27.260157 [Byte1]: 77
1179 23:56:27.264323
1180 23:56:27.264428 Set Vref, RX VrefLevel [Byte0]: 78
1181 23:56:27.268267 [Byte1]: 78
1182 23:56:27.272218
1183 23:56:27.272325 Final RX Vref Byte 0 = 53 to rank0
1184 23:56:27.275457 Final RX Vref Byte 1 = 60 to rank0
1185 23:56:27.278696 Final RX Vref Byte 0 = 53 to rank1
1186 23:56:27.282321 Final RX Vref Byte 1 = 60 to rank1==
1187 23:56:27.285237 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 23:56:27.292042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 23:56:27.292141 ==
1190 23:56:27.292206 DQS Delay:
1191 23:56:27.292267 DQS0 = 0, DQS1 = 0
1192 23:56:27.295119 DQM Delay:
1193 23:56:27.295223 DQM0 = 91, DQM1 = 85
1194 23:56:27.298888 DQ Delay:
1195 23:56:27.298991 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1196 23:56:27.302456 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1197 23:56:27.305592 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1198 23:56:27.308931 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1199 23:56:27.309012
1200 23:56:27.312366
1201 23:56:27.318714 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1202 23:56:27.322466 CH0 RK0: MR19=606, MR18=4A41
1203 23:56:27.328990 CH0_RK0: MR19=0x606, MR18=0x4A41, DQSOSC=391, MR23=63, INC=96, DEC=64
1204 23:56:27.329102
1205 23:56:27.332314 ----->DramcWriteLeveling(PI) begin...
1206 23:56:27.332434 ==
1207 23:56:27.336002 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:56:27.339027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 23:56:27.339108 ==
1210 23:56:27.342699 Write leveling (Byte 0): 35 => 35
1211 23:56:27.346051 Write leveling (Byte 1): 30 => 30
1212 23:56:27.349151 DramcWriteLeveling(PI) end<-----
1213 23:56:27.349278
1214 23:56:27.349389 ==
1215 23:56:27.352569 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 23:56:27.396526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 23:56:27.396675 ==
1218 23:56:27.396743 [Gating] SW mode calibration
1219 23:56:27.397022 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 23:56:27.397297 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 23:56:27.397386 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 23:56:27.397513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 23:56:27.397628 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1224 23:56:27.397697 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:56:27.397943 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:56:27.398008 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:56:27.418375 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:56:27.418679 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:56:27.418748 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:56:27.421748 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:56:27.421829 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:56:27.425389 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:56:27.428629 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:56:27.432203 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:56:27.438259 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:56:27.442026 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:56:27.444956 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:56:27.451982 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1239 23:56:27.455243 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1240 23:56:27.458432 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:56:27.464808 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:56:27.468774 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:56:27.471755 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:56:27.474785 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:56:27.481969 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:56:27.485028 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:56:27.488533 0 9 8 | B1->B0 | 2e2e 2b2b | 1 1 | (1 1) (1 1)
1248 23:56:27.494742 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:56:27.498602 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:56:27.501576 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:56:27.508382 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:56:27.511535 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:56:27.514660 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:56:27.521592 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1255 23:56:27.524949 0 10 8 | B1->B0 | 2525 2c2c | 1 1 | (1 1) (1 0)
1256 23:56:27.528701 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1257 23:56:27.532230 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:56:27.539934 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:56:27.543724 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:56:27.546851 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:56:27.550087 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:56:27.557243 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1263 23:56:27.560265 0 11 8 | B1->B0 | 3b3b 3737 | 0 0 | (0 0) (1 1)
1264 23:56:27.563797 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 23:56:27.567389 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:56:27.573722 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:56:27.577179 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:56:27.580585 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:56:27.587707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:56:27.590725 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 23:56:27.593803 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:56:27.600326 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1273 23:56:27.604131 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:56:27.607748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:56:27.614132 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:56:27.617297 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:56:27.620800 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:56:27.627191 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:56:27.630947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:56:27.634036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:56:27.640934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:56:27.644152 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:56:27.647396 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:56:27.650459 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:56:27.657732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:56:27.660754 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:56:27.664465 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1288 23:56:27.671163 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 23:56:27.674213 Total UI for P1: 0, mck2ui 16
1290 23:56:27.677358 best dqsien dly found for B0: ( 0, 14, 8)
1291 23:56:27.677447 Total UI for P1: 0, mck2ui 16
1292 23:56:27.684283 best dqsien dly found for B1: ( 0, 14, 8)
1293 23:56:27.687416 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1294 23:56:27.691585 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1295 23:56:27.691670
1296 23:56:27.694625 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 23:56:27.697832 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 23:56:27.701316 [Gating] SW calibration Done
1299 23:56:27.701399 ==
1300 23:56:27.704477 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 23:56:27.707976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 23:56:27.708086 ==
1303 23:56:27.710959 RX Vref Scan: 0
1304 23:56:27.711042
1305 23:56:27.711120 RX Vref 0 -> 0, step: 1
1306 23:56:27.711182
1307 23:56:27.714444 RX Delay -130 -> 252, step: 16
1308 23:56:27.718017 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1309 23:56:27.721378 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1310 23:56:27.727697 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1311 23:56:27.731442 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1312 23:56:27.734440 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1313 23:56:27.737669 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1314 23:56:27.741340 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1315 23:56:27.748125 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1316 23:56:27.751219 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1317 23:56:27.754373 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1318 23:56:27.757622 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
1319 23:56:27.761517 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1320 23:56:27.767724 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1321 23:56:27.771401 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1322 23:56:27.774533 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1323 23:56:27.777871 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1324 23:56:27.777950 ==
1325 23:56:27.780856 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 23:56:27.787800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 23:56:27.787883 ==
1328 23:56:27.787949 DQS Delay:
1329 23:56:27.791102 DQS0 = 0, DQS1 = 0
1330 23:56:27.791184 DQM Delay:
1331 23:56:27.791248 DQM0 = 93, DQM1 = 86
1332 23:56:27.794885 DQ Delay:
1333 23:56:27.797853 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1334 23:56:27.800888 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =93
1335 23:56:27.804571 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1336 23:56:27.807670 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1337 23:56:27.807752
1338 23:56:27.807817
1339 23:56:27.807880 ==
1340 23:56:27.810856 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 23:56:27.814643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 23:56:27.814747 ==
1343 23:56:27.814846
1344 23:56:27.814939
1345 23:56:27.817888 TX Vref Scan disable
1346 23:56:27.817957 == TX Byte 0 ==
1347 23:56:27.824207 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1348 23:56:27.827630 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1349 23:56:27.827742 == TX Byte 1 ==
1350 23:56:27.834387 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1351 23:56:27.838131 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1352 23:56:27.838240 ==
1353 23:56:27.841159 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 23:56:27.844187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 23:56:27.844291 ==
1356 23:56:27.859135 TX Vref=22, minBit 10, minWin=27, winSum=447
1357 23:56:27.862337 TX Vref=24, minBit 1, minWin=28, winSum=454
1358 23:56:27.865508 TX Vref=26, minBit 10, minWin=27, winSum=454
1359 23:56:27.868977 TX Vref=28, minBit 1, minWin=28, winSum=456
1360 23:56:27.872492 TX Vref=30, minBit 2, minWin=28, winSum=456
1361 23:56:27.879296 TX Vref=32, minBit 2, minWin=28, winSum=455
1362 23:56:27.882525 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 28
1363 23:56:27.882609
1364 23:56:27.885733 Final TX Range 1 Vref 28
1365 23:56:27.885816
1366 23:56:27.885880 ==
1367 23:56:27.889283 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 23:56:27.892737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 23:56:27.892820 ==
1370 23:56:27.892884
1371 23:56:27.895745
1372 23:56:27.895824 TX Vref Scan disable
1373 23:56:27.899360 == TX Byte 0 ==
1374 23:56:27.902455 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1375 23:56:27.905914 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1376 23:56:27.908856 == TX Byte 1 ==
1377 23:56:27.912427 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1378 23:56:27.918768 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1379 23:56:27.918866
1380 23:56:27.918959 [DATLAT]
1381 23:56:27.919046 Freq=800, CH0 RK1
1382 23:56:27.919132
1383 23:56:27.922665 DATLAT Default: 0xa
1384 23:56:27.922758 0, 0xFFFF, sum = 0
1385 23:56:27.925742 1, 0xFFFF, sum = 0
1386 23:56:27.925838 2, 0xFFFF, sum = 0
1387 23:56:27.929000 3, 0xFFFF, sum = 0
1388 23:56:27.929095 4, 0xFFFF, sum = 0
1389 23:56:27.932131 5, 0xFFFF, sum = 0
1390 23:56:27.936140 6, 0xFFFF, sum = 0
1391 23:56:27.936238 7, 0xFFFF, sum = 0
1392 23:56:27.938921 8, 0xFFFF, sum = 0
1393 23:56:27.938990 9, 0x0, sum = 1
1394 23:56:27.939050 10, 0x0, sum = 2
1395 23:56:27.942535 11, 0x0, sum = 3
1396 23:56:27.942604 12, 0x0, sum = 4
1397 23:56:27.945644 best_step = 10
1398 23:56:27.945739
1399 23:56:27.945826 ==
1400 23:56:27.949154 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 23:56:27.952443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 23:56:27.952521 ==
1403 23:56:27.955608 RX Vref Scan: 0
1404 23:56:27.955676
1405 23:56:27.955735 RX Vref 0 -> 0, step: 1
1406 23:56:27.955794
1407 23:56:27.959473 RX Delay -79 -> 252, step: 8
1408 23:56:27.965746 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1409 23:56:27.969003 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1410 23:56:27.972460 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1411 23:56:27.976144 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1412 23:56:27.979047 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1413 23:56:27.985614 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1414 23:56:27.989221 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1415 23:56:27.992192 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1416 23:56:27.995679 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1417 23:56:27.998894 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1418 23:56:28.005424 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1419 23:56:28.009191 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1420 23:56:28.012396 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1421 23:56:28.015368 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1422 23:56:28.018921 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1423 23:56:28.025368 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1424 23:56:28.025450 ==
1425 23:56:28.029371 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 23:56:28.032292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 23:56:28.032385 ==
1428 23:56:28.032451 DQS Delay:
1429 23:56:28.035490 DQS0 = 0, DQS1 = 0
1430 23:56:28.035571 DQM Delay:
1431 23:56:28.038767 DQM0 = 93, DQM1 = 83
1432 23:56:28.038849 DQ Delay:
1433 23:56:28.042532 DQ0 =92, DQ1 =92, DQ2 =92, DQ3 =92
1434 23:56:28.045606 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1435 23:56:28.049516 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1436 23:56:28.052370 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1437 23:56:28.052451
1438 23:56:28.052514
1439 23:56:28.062543 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1440 23:56:28.062624 CH0 RK1: MR19=606, MR18=4415
1441 23:56:28.068803 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1442 23:56:28.072057 [RxdqsGatingPostProcess] freq 800
1443 23:56:28.079272 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 23:56:28.082660 Pre-setting of DQS Precalculation
1445 23:56:28.086268 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 23:56:28.086348 ==
1447 23:56:28.089356 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 23:56:28.092477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 23:56:28.092558 ==
1450 23:56:28.098968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 23:56:28.105778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 23:56:28.113929 [CA 0] Center 36 (6~67) winsize 62
1453 23:56:28.117609 [CA 1] Center 36 (6~67) winsize 62
1454 23:56:28.120884 [CA 2] Center 35 (5~66) winsize 62
1455 23:56:28.124136 [CA 3] Center 34 (4~65) winsize 62
1456 23:56:28.127530 [CA 4] Center 34 (4~65) winsize 62
1457 23:56:28.130775 [CA 5] Center 34 (4~64) winsize 61
1458 23:56:28.130855
1459 23:56:28.134599 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1460 23:56:28.134679
1461 23:56:28.137736 [CATrainingPosCal] consider 1 rank data
1462 23:56:28.140910 u2DelayCellTimex100 = 270/100 ps
1463 23:56:28.144588 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 23:56:28.147750 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 23:56:28.150843 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1466 23:56:28.157728 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 23:56:28.160859 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 23:56:28.164104 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1469 23:56:28.164183
1470 23:56:28.167799 CA PerBit enable=1, Macro0, CA PI delay=34
1471 23:56:28.167937
1472 23:56:28.171327 [CBTSetCACLKResult] CA Dly = 34
1473 23:56:28.171433 CS Dly: 5 (0~36)
1474 23:56:28.171522 ==
1475 23:56:28.174079 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 23:56:28.181153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 23:56:28.181233 ==
1478 23:56:28.184194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 23:56:28.190856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 23:56:28.200609 [CA 0] Center 36 (6~67) winsize 62
1481 23:56:28.204735 [CA 1] Center 37 (6~68) winsize 63
1482 23:56:28.208526 [CA 2] Center 35 (4~66) winsize 63
1483 23:56:28.212019 [CA 3] Center 34 (4~65) winsize 62
1484 23:56:28.215848 [CA 4] Center 34 (4~65) winsize 62
1485 23:56:28.215930 [CA 5] Center 34 (4~65) winsize 62
1486 23:56:28.215995
1487 23:56:28.219674 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1488 23:56:28.223658
1489 23:56:28.223740 [CATrainingPosCal] consider 2 rank data
1490 23:56:28.227823 u2DelayCellTimex100 = 270/100 ps
1491 23:56:28.230833 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 23:56:28.234637 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 23:56:28.237537 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1494 23:56:28.241134 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 23:56:28.247517 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 23:56:28.251025 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1497 23:56:28.251121
1498 23:56:28.254128 CA PerBit enable=1, Macro0, CA PI delay=34
1499 23:56:28.254236
1500 23:56:28.257696 [CBTSetCACLKResult] CA Dly = 34
1501 23:56:28.257778 CS Dly: 6 (0~38)
1502 23:56:28.257842
1503 23:56:28.260760 ----->DramcWriteLeveling(PI) begin...
1504 23:56:28.260844 ==
1505 23:56:28.264238 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 23:56:28.270826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 23:56:28.270910 ==
1508 23:56:28.274533 Write leveling (Byte 0): 29 => 29
1509 23:56:28.274615 Write leveling (Byte 1): 29 => 29
1510 23:56:28.277793 DramcWriteLeveling(PI) end<-----
1511 23:56:28.277906
1512 23:56:28.277997 ==
1513 23:56:28.280941 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 23:56:28.287968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 23:56:28.288051 ==
1516 23:56:28.290999 [Gating] SW mode calibration
1517 23:56:28.297790 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 23:56:28.300917 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 23:56:28.307702 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 23:56:28.310870 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1521 23:56:28.314412 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:56:28.320994 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:56:28.324492 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:56:28.327744 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:56:28.330818 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:56:28.337558 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:56:28.341319 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:56:28.344237 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:56:28.351004 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:56:28.354624 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:56:28.357796 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:56:28.364948 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:56:28.367969 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:56:28.371002 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:56:28.377974 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 23:56:28.381014 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1537 23:56:28.384665 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:56:28.391319 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:56:28.394492 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:56:28.398242 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:56:28.401359 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:56:28.408307 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:56:28.411329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:56:28.414463 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1545 23:56:28.421394 0 9 8 | B1->B0 | 3030 3433 | 0 1 | (0 0) (0 0)
1546 23:56:28.424344 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:56:28.428229 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:56:28.434594 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:56:28.438214 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:56:28.441280 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 23:56:28.447960 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1552 23:56:28.451908 0 10 4 | B1->B0 | 3232 2a2a | 1 1 | (0 0) (0 0)
1553 23:56:28.454616 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1554 23:56:28.461595 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:56:28.464689 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:56:28.468294 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:56:28.471825 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:56:28.477960 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 23:56:28.481611 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 23:56:28.484396 0 11 4 | B1->B0 | 2a2a 3535 | 0 0 | (0 0) (0 0)
1561 23:56:28.491124 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1562 23:56:28.494413 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:56:28.498094 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:56:28.504772 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:56:28.508156 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:56:28.511338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 23:56:28.518082 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:56:28.521281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1569 23:56:28.524592 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:56:28.531165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:56:28.535059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:56:28.538263 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:56:28.544967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:56:28.548183 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:56:28.551598 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:56:28.558049 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:56:28.561540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:56:28.564583 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:56:28.568317 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:56:28.574799 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:56:28.578397 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:56:28.581574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:56:28.588513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:56:28.591181 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 23:56:28.594888 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 23:56:28.598344 Total UI for P1: 0, mck2ui 16
1587 23:56:28.601363 best dqsien dly found for B0: ( 0, 14, 4)
1588 23:56:28.605110 Total UI for P1: 0, mck2ui 16
1589 23:56:28.608177 best dqsien dly found for B1: ( 0, 14, 4)
1590 23:56:28.611824 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1591 23:56:28.615438 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1592 23:56:28.615513
1593 23:56:28.618455 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 23:56:28.625074 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1595 23:56:28.625207 [Gating] SW calibration Done
1596 23:56:28.625302 ==
1597 23:56:28.628538 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 23:56:28.635253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 23:56:28.635366 ==
1600 23:56:28.635460 RX Vref Scan: 0
1601 23:56:28.635548
1602 23:56:28.638325 RX Vref 0 -> 0, step: 1
1603 23:56:28.638399
1604 23:56:28.641422 RX Delay -130 -> 252, step: 16
1605 23:56:28.645238 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1606 23:56:28.648540 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1607 23:56:28.651506 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1608 23:56:28.658308 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1609 23:56:28.661356 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1610 23:56:28.665107 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1611 23:56:28.668165 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1612 23:56:28.671742 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1613 23:56:28.678243 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1614 23:56:28.681864 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1615 23:56:28.685107 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1616 23:56:28.688222 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1617 23:56:28.691397 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1618 23:56:28.698205 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1619 23:56:28.701695 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1620 23:56:28.704965 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1621 23:56:28.705048 ==
1622 23:56:28.708075 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 23:56:28.712008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 23:56:28.712100 ==
1625 23:56:28.715103 DQS Delay:
1626 23:56:28.715194 DQS0 = 0, DQS1 = 0
1627 23:56:28.718253 DQM Delay:
1628 23:56:28.718372 DQM0 = 93, DQM1 = 87
1629 23:56:28.718464 DQ Delay:
1630 23:56:28.721428 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1631 23:56:28.724972 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1632 23:56:28.728040 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1633 23:56:28.731508 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1634 23:56:28.731590
1635 23:56:28.731653
1636 23:56:28.734834 ==
1637 23:56:28.738062 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 23:56:28.741620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 23:56:28.741700 ==
1640 23:56:28.741763
1641 23:56:28.741822
1642 23:56:28.745014 TX Vref Scan disable
1643 23:56:28.745111 == TX Byte 0 ==
1644 23:56:28.748314 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1645 23:56:28.754935 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1646 23:56:28.755092 == TX Byte 1 ==
1647 23:56:28.758004 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1648 23:56:28.765090 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1649 23:56:28.765219 ==
1650 23:56:28.768629 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 23:56:28.771966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 23:56:28.772051 ==
1653 23:56:28.784504 TX Vref=22, minBit 3, minWin=26, winSum=438
1654 23:56:28.787700 TX Vref=24, minBit 7, minWin=26, winSum=444
1655 23:56:28.791544 TX Vref=26, minBit 3, minWin=26, winSum=443
1656 23:56:28.794548 TX Vref=28, minBit 1, minWin=27, winSum=447
1657 23:56:28.797871 TX Vref=30, minBit 1, minWin=27, winSum=450
1658 23:56:28.801675 TX Vref=32, minBit 1, minWin=27, winSum=445
1659 23:56:28.808024 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1660 23:56:28.808114
1661 23:56:28.811256 Final TX Range 1 Vref 30
1662 23:56:28.811338
1663 23:56:28.811402 ==
1664 23:56:28.814353 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 23:56:28.818185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 23:56:28.818258 ==
1667 23:56:28.818326
1668 23:56:28.821482
1669 23:56:28.821564 TX Vref Scan disable
1670 23:56:28.824632 == TX Byte 0 ==
1671 23:56:28.827651 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1672 23:56:28.831299 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1673 23:56:28.834396 == TX Byte 1 ==
1674 23:56:28.837644 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1675 23:56:28.841246 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1676 23:56:28.844886
1677 23:56:28.844958 [DATLAT]
1678 23:56:28.845021 Freq=800, CH1 RK0
1679 23:56:28.845087
1680 23:56:28.847713 DATLAT Default: 0xa
1681 23:56:28.847779 0, 0xFFFF, sum = 0
1682 23:56:28.851137 1, 0xFFFF, sum = 0
1683 23:56:28.851210 2, 0xFFFF, sum = 0
1684 23:56:28.854780 3, 0xFFFF, sum = 0
1685 23:56:28.854860 4, 0xFFFF, sum = 0
1686 23:56:28.857907 5, 0xFFFF, sum = 0
1687 23:56:28.857979 6, 0xFFFF, sum = 0
1688 23:56:28.861378 7, 0xFFFF, sum = 0
1689 23:56:28.861463 8, 0xFFFF, sum = 0
1690 23:56:28.864773 9, 0x0, sum = 1
1691 23:56:28.864848 10, 0x0, sum = 2
1692 23:56:28.867949 11, 0x0, sum = 3
1693 23:56:28.868025 12, 0x0, sum = 4
1694 23:56:28.871214 best_step = 10
1695 23:56:28.871287
1696 23:56:28.871359 ==
1697 23:56:28.874532 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 23:56:28.877988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 23:56:28.878070 ==
1700 23:56:28.881604 RX Vref Scan: 1
1701 23:56:28.881684
1702 23:56:28.881755 Set Vref Range= 32 -> 127
1703 23:56:28.881826
1704 23:56:28.885024 RX Vref 32 -> 127, step: 1
1705 23:56:28.885099
1706 23:56:28.887850 RX Delay -79 -> 252, step: 8
1707 23:56:28.887922
1708 23:56:28.891361 Set Vref, RX VrefLevel [Byte0]: 32
1709 23:56:28.894559 [Byte1]: 32
1710 23:56:28.894641
1711 23:56:28.898438 Set Vref, RX VrefLevel [Byte0]: 33
1712 23:56:28.901530 [Byte1]: 33
1713 23:56:28.904663
1714 23:56:28.904746 Set Vref, RX VrefLevel [Byte0]: 34
1715 23:56:28.908283 [Byte1]: 34
1716 23:56:28.912617
1717 23:56:28.912700 Set Vref, RX VrefLevel [Byte0]: 35
1718 23:56:28.915615 [Byte1]: 35
1719 23:56:28.919961
1720 23:56:28.920037 Set Vref, RX VrefLevel [Byte0]: 36
1721 23:56:28.923061 [Byte1]: 36
1722 23:56:28.927595
1723 23:56:28.927671 Set Vref, RX VrefLevel [Byte0]: 37
1724 23:56:28.930769 [Byte1]: 37
1725 23:56:28.935009
1726 23:56:28.935098 Set Vref, RX VrefLevel [Byte0]: 38
1727 23:56:28.938129 [Byte1]: 38
1728 23:56:28.942607
1729 23:56:28.942680 Set Vref, RX VrefLevel [Byte0]: 39
1730 23:56:28.945698 [Byte1]: 39
1731 23:56:28.950197
1732 23:56:28.950271 Set Vref, RX VrefLevel [Byte0]: 40
1733 23:56:28.953319 [Byte1]: 40
1734 23:56:28.957835
1735 23:56:28.957909 Set Vref, RX VrefLevel [Byte0]: 41
1736 23:56:28.960958 [Byte1]: 41
1737 23:56:28.965537
1738 23:56:28.965658 Set Vref, RX VrefLevel [Byte0]: 42
1739 23:56:28.968443 [Byte1]: 42
1740 23:56:28.972775
1741 23:56:28.972912 Set Vref, RX VrefLevel [Byte0]: 43
1742 23:56:28.975879 [Byte1]: 43
1743 23:56:28.980051
1744 23:56:28.980173 Set Vref, RX VrefLevel [Byte0]: 44
1745 23:56:28.983480 [Byte1]: 44
1746 23:56:28.987507
1747 23:56:28.987635 Set Vref, RX VrefLevel [Byte0]: 45
1748 23:56:28.991332 [Byte1]: 45
1749 23:56:28.995224
1750 23:56:28.995302 Set Vref, RX VrefLevel [Byte0]: 46
1751 23:56:28.998817 [Byte1]: 46
1752 23:56:29.003204
1753 23:56:29.003346 Set Vref, RX VrefLevel [Byte0]: 47
1754 23:56:29.006086 [Byte1]: 47
1755 23:56:29.010582
1756 23:56:29.010685 Set Vref, RX VrefLevel [Byte0]: 48
1757 23:56:29.014147 [Byte1]: 48
1758 23:56:29.017793
1759 23:56:29.017864 Set Vref, RX VrefLevel [Byte0]: 49
1760 23:56:29.021330 [Byte1]: 49
1761 23:56:29.025717
1762 23:56:29.025790 Set Vref, RX VrefLevel [Byte0]: 50
1763 23:56:29.028732 [Byte1]: 50
1764 23:56:29.033325
1765 23:56:29.033400 Set Vref, RX VrefLevel [Byte0]: 51
1766 23:56:29.036376 [Byte1]: 51
1767 23:56:29.040888
1768 23:56:29.040965 Set Vref, RX VrefLevel [Byte0]: 52
1769 23:56:29.043875 [Byte1]: 52
1770 23:56:29.048180
1771 23:56:29.048254 Set Vref, RX VrefLevel [Byte0]: 53
1772 23:56:29.051504 [Byte1]: 53
1773 23:56:29.055723
1774 23:56:29.055799 Set Vref, RX VrefLevel [Byte0]: 54
1775 23:56:29.059346 [Byte1]: 54
1776 23:56:29.063099
1777 23:56:29.063234 Set Vref, RX VrefLevel [Byte0]: 55
1778 23:56:29.066837 [Byte1]: 55
1779 23:56:29.070559
1780 23:56:29.070690 Set Vref, RX VrefLevel [Byte0]: 56
1781 23:56:29.074157 [Byte1]: 56
1782 23:56:29.078531
1783 23:56:29.078671 Set Vref, RX VrefLevel [Byte0]: 57
1784 23:56:29.081670 [Byte1]: 57
1785 23:56:29.085794
1786 23:56:29.085924 Set Vref, RX VrefLevel [Byte0]: 58
1787 23:56:29.089217 [Byte1]: 58
1788 23:56:29.093689
1789 23:56:29.093824 Set Vref, RX VrefLevel [Byte0]: 59
1790 23:56:29.096924 [Byte1]: 59
1791 23:56:29.101161
1792 23:56:29.101295 Set Vref, RX VrefLevel [Byte0]: 60
1793 23:56:29.104193 [Byte1]: 60
1794 23:56:29.108283
1795 23:56:29.108425 Set Vref, RX VrefLevel [Byte0]: 61
1796 23:56:29.112106 [Byte1]: 61
1797 23:56:29.115919
1798 23:56:29.116042 Set Vref, RX VrefLevel [Byte0]: 62
1799 23:56:29.119431 [Byte1]: 62
1800 23:56:29.123630
1801 23:56:29.123753 Set Vref, RX VrefLevel [Byte0]: 63
1802 23:56:29.126995 [Byte1]: 63
1803 23:56:29.130925
1804 23:56:29.131052 Set Vref, RX VrefLevel [Byte0]: 64
1805 23:56:29.134574 [Byte1]: 64
1806 23:56:29.138886
1807 23:56:29.139017 Set Vref, RX VrefLevel [Byte0]: 65
1808 23:56:29.142014 [Byte1]: 65
1809 23:56:29.146304
1810 23:56:29.146444 Set Vref, RX VrefLevel [Byte0]: 66
1811 23:56:29.149542 [Byte1]: 66
1812 23:56:29.153845
1813 23:56:29.153984 Set Vref, RX VrefLevel [Byte0]: 67
1814 23:56:29.157214 [Byte1]: 67
1815 23:56:29.161221
1816 23:56:29.161357 Set Vref, RX VrefLevel [Byte0]: 68
1817 23:56:29.164713 [Byte1]: 68
1818 23:56:29.169132
1819 23:56:29.169266 Set Vref, RX VrefLevel [Byte0]: 69
1820 23:56:29.172347 [Byte1]: 69
1821 23:56:29.176602
1822 23:56:29.176740 Set Vref, RX VrefLevel [Byte0]: 70
1823 23:56:29.179551 [Byte1]: 70
1824 23:56:29.184037
1825 23:56:29.184168 Set Vref, RX VrefLevel [Byte0]: 71
1826 23:56:29.187247 [Byte1]: 71
1827 23:56:29.191385
1828 23:56:29.191526 Set Vref, RX VrefLevel [Byte0]: 72
1829 23:56:29.194826 [Byte1]: 72
1830 23:56:29.198822
1831 23:56:29.198952 Final RX Vref Byte 0 = 56 to rank0
1832 23:56:29.202389 Final RX Vref Byte 1 = 55 to rank0
1833 23:56:29.205757 Final RX Vref Byte 0 = 56 to rank1
1834 23:56:29.209345 Final RX Vref Byte 1 = 55 to rank1==
1835 23:56:29.212567 Dram Type= 6, Freq= 0, CH_1, rank 0
1836 23:56:29.215871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1837 23:56:29.218944 ==
1838 23:56:29.219071 DQS Delay:
1839 23:56:29.219185 DQS0 = 0, DQS1 = 0
1840 23:56:29.222668 DQM Delay:
1841 23:56:29.222801 DQM0 = 95, DQM1 = 90
1842 23:56:29.225714 DQ Delay:
1843 23:56:29.229056 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1844 23:56:29.232954 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1845 23:56:29.233085 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1846 23:56:29.239262 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1847 23:56:29.239390
1848 23:56:29.239516
1849 23:56:29.245818 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1850 23:56:29.249155 CH1 RK0: MR19=606, MR18=2E4B
1851 23:56:29.255823 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1852 23:56:29.255961
1853 23:56:29.259268 ----->DramcWriteLeveling(PI) begin...
1854 23:56:29.259401 ==
1855 23:56:29.262448 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 23:56:29.265622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 23:56:29.265762 ==
1858 23:56:29.269257 Write leveling (Byte 0): 25 => 25
1859 23:56:29.272273 Write leveling (Byte 1): 27 => 27
1860 23:56:29.276219 DramcWriteLeveling(PI) end<-----
1861 23:56:29.276362
1862 23:56:29.276482 ==
1863 23:56:29.279292 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 23:56:29.282320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 23:56:29.282448 ==
1866 23:56:29.285906 [Gating] SW mode calibration
1867 23:56:29.292856 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1868 23:56:29.299313 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1869 23:56:29.302219 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1870 23:56:29.305908 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1871 23:56:29.312431 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:56:29.316198 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:56:29.319347 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:56:29.326289 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:56:29.329755 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:56:29.332762 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:56:29.339654 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:56:29.342802 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:56:29.345911 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:56:29.349826 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:56:29.355968 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:56:29.359258 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:56:29.362797 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:56:29.369503 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1885 23:56:29.372633 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1886 23:56:29.376523 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1887 23:56:29.383026 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:56:29.386101 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:56:29.389981 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:56:29.395952 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:56:29.399090 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:56:29.402995 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:56:29.410020 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:56:29.412822 0 9 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1895 23:56:29.415808 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1896 23:56:29.422788 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 23:56:29.425982 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 23:56:29.429785 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:56:29.433061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 23:56:29.439144 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 23:56:29.442755 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1902 23:56:29.445905 0 10 4 | B1->B0 | 2828 3030 | 1 0 | (1 0) (0 1)
1903 23:56:29.452958 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1904 23:56:29.456118 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:56:29.459328 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:56:29.466098 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:56:29.469758 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:56:29.472817 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:56:29.479856 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:56:29.482782 0 11 4 | B1->B0 | 3737 3030 | 0 1 | (0 0) (0 0)
1911 23:56:29.486353 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 23:56:29.492866 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 23:56:29.496276 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:56:29.499753 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:56:29.505988 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:56:29.509498 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 23:56:29.513076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 23:56:29.516216 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1919 23:56:29.522917 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:56:29.526602 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:56:29.529473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:56:29.536293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:56:29.539502 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:56:29.543301 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:56:29.549881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:56:29.552912 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:56:29.556709 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:56:29.563815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:56:29.566888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:56:29.570146 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:56:29.576474 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:56:29.580025 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:56:29.583034 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:56:29.586777 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1935 23:56:29.593233 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 23:56:29.596784 Total UI for P1: 0, mck2ui 16
1937 23:56:29.599928 best dqsien dly found for B0: ( 0, 14, 4)
1938 23:56:29.600062 Total UI for P1: 0, mck2ui 16
1939 23:56:29.606780 best dqsien dly found for B1: ( 0, 14, 4)
1940 23:56:29.610483 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1941 23:56:29.613553 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1942 23:56:29.613699
1943 23:56:29.616640 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 23:56:29.620251 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1945 23:56:29.623915 [Gating] SW calibration Done
1946 23:56:29.624053 ==
1947 23:56:29.626900 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 23:56:29.630047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 23:56:29.630177 ==
1950 23:56:29.633195 RX Vref Scan: 0
1951 23:56:29.633322
1952 23:56:29.633451 RX Vref 0 -> 0, step: 1
1953 23:56:29.633566
1954 23:56:29.636904 RX Delay -130 -> 252, step: 16
1955 23:56:29.640011 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1956 23:56:29.647083 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1957 23:56:29.650339 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1958 23:56:29.653275 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1959 23:56:29.656741 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1960 23:56:29.660363 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1961 23:56:29.666815 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1962 23:56:29.670554 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1963 23:56:29.673708 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1964 23:56:29.676944 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1965 23:56:29.680155 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1966 23:56:29.687199 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1967 23:56:29.690308 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1968 23:56:29.693704 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1969 23:56:29.696762 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1970 23:56:29.700619 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1971 23:56:29.700749 ==
1972 23:56:29.703895 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 23:56:29.710700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 23:56:29.710839 ==
1975 23:56:29.710966 DQS Delay:
1976 23:56:29.713762 DQS0 = 0, DQS1 = 0
1977 23:56:29.713893 DQM Delay:
1978 23:56:29.714019 DQM0 = 93, DQM1 = 91
1979 23:56:29.716862 DQ Delay:
1980 23:56:29.720612 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1981 23:56:29.723850 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1982 23:56:29.726911 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1983 23:56:29.730221 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1984 23:56:29.730350
1985 23:56:29.730470
1986 23:56:29.730590 ==
1987 23:56:29.733398 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 23:56:29.737063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 23:56:29.737190 ==
1990 23:56:29.737315
1991 23:56:29.737435
1992 23:56:29.740050 TX Vref Scan disable
1993 23:56:29.743664 == TX Byte 0 ==
1994 23:56:29.746736 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1995 23:56:29.750287 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1996 23:56:29.753698 == TX Byte 1 ==
1997 23:56:29.757149 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1998 23:56:29.760411 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1999 23:56:29.760495 ==
2000 23:56:29.763721 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 23:56:29.766923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 23:56:29.767034 ==
2003 23:56:29.781266 TX Vref=22, minBit 2, minWin=26, winSum=440
2004 23:56:29.785042 TX Vref=24, minBit 0, minWin=27, winSum=442
2005 23:56:29.788102 TX Vref=26, minBit 5, minWin=26, winSum=440
2006 23:56:29.791542 TX Vref=28, minBit 0, minWin=27, winSum=449
2007 23:56:29.794450 TX Vref=30, minBit 0, minWin=27, winSum=446
2008 23:56:29.801317 TX Vref=32, minBit 0, minWin=27, winSum=446
2009 23:56:29.804631 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 28
2010 23:56:29.804813
2011 23:56:29.807789 Final TX Range 1 Vref 28
2012 23:56:29.807880
2013 23:56:29.807957 ==
2014 23:56:29.811559 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 23:56:29.814795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 23:56:29.814942 ==
2017 23:56:29.815055
2018 23:56:29.817917
2019 23:56:29.818031 TX Vref Scan disable
2020 23:56:29.821332 == TX Byte 0 ==
2021 23:56:29.824779 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2022 23:56:29.831155 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2023 23:56:29.831252 == TX Byte 1 ==
2024 23:56:29.834724 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2025 23:56:29.841234 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2026 23:56:29.841315
2027 23:56:29.841378 [DATLAT]
2028 23:56:29.841437 Freq=800, CH1 RK1
2029 23:56:29.841494
2030 23:56:29.844363 DATLAT Default: 0xa
2031 23:56:29.844457 0, 0xFFFF, sum = 0
2032 23:56:29.848089 1, 0xFFFF, sum = 0
2033 23:56:29.848200 2, 0xFFFF, sum = 0
2034 23:56:29.851640 3, 0xFFFF, sum = 0
2035 23:56:29.851722 4, 0xFFFF, sum = 0
2036 23:56:29.854753 5, 0xFFFF, sum = 0
2037 23:56:29.857941 6, 0xFFFF, sum = 0
2038 23:56:29.858027 7, 0xFFFF, sum = 0
2039 23:56:29.861267 8, 0xFFFF, sum = 0
2040 23:56:29.861351 9, 0x0, sum = 1
2041 23:56:29.861417 10, 0x0, sum = 2
2042 23:56:29.864875 11, 0x0, sum = 3
2043 23:56:29.864986 12, 0x0, sum = 4
2044 23:56:29.867826 best_step = 10
2045 23:56:29.867926
2046 23:56:29.868034 ==
2047 23:56:29.871440 Dram Type= 6, Freq= 0, CH_1, rank 1
2048 23:56:29.874799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2049 23:56:29.874908 ==
2050 23:56:29.878300 RX Vref Scan: 0
2051 23:56:29.878408
2052 23:56:29.878501 RX Vref 0 -> 0, step: 1
2053 23:56:29.878590
2054 23:56:29.881629 RX Delay -63 -> 252, step: 8
2055 23:56:29.887947 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2056 23:56:29.891264 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2057 23:56:29.895082 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2058 23:56:29.898216 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2059 23:56:29.901289 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2060 23:56:29.905227 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2061 23:56:29.911316 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2062 23:56:29.914770 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2063 23:56:29.917851 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2064 23:56:29.921702 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2065 23:56:29.925083 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2066 23:56:29.931848 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2067 23:56:29.934924 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2068 23:56:29.938215 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2069 23:56:29.941356 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2070 23:56:29.944629 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2071 23:56:29.944711 ==
2072 23:56:29.948278 Dram Type= 6, Freq= 0, CH_1, rank 1
2073 23:56:29.954694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2074 23:56:29.954775 ==
2075 23:56:29.954878 DQS Delay:
2076 23:56:29.958205 DQS0 = 0, DQS1 = 0
2077 23:56:29.958361 DQM Delay:
2078 23:56:29.958483 DQM0 = 97, DQM1 = 91
2079 23:56:29.961332 DQ Delay:
2080 23:56:29.965046 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2081 23:56:29.967964 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2082 23:56:29.972084 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2083 23:56:29.974963 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2084 23:56:29.975080
2085 23:56:29.975180
2086 23:56:29.981272 [DQSOSCAuto] RK1, (LSB)MR18= 0x4912, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2087 23:56:29.985142 CH1 RK1: MR19=606, MR18=4912
2088 23:56:29.991683 CH1_RK1: MR19=0x606, MR18=0x4912, DQSOSC=391, MR23=63, INC=96, DEC=64
2089 23:56:29.995327 [RxdqsGatingPostProcess] freq 800
2090 23:56:29.998405 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2091 23:56:30.001787 Pre-setting of DQS Precalculation
2092 23:56:30.008241 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2093 23:56:30.015205 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2094 23:56:30.021810 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2095 23:56:30.021924
2096 23:56:30.022018
2097 23:56:30.025206 [Calibration Summary] 1600 Mbps
2098 23:56:30.025309 CH 0, Rank 0
2099 23:56:30.028364 SW Impedance : PASS
2100 23:56:30.031898 DUTY Scan : NO K
2101 23:56:30.031981 ZQ Calibration : PASS
2102 23:56:30.034740 Jitter Meter : NO K
2103 23:56:30.038384 CBT Training : PASS
2104 23:56:30.038464 Write leveling : PASS
2105 23:56:30.041760 RX DQS gating : PASS
2106 23:56:30.045462 RX DQ/DQS(RDDQC) : PASS
2107 23:56:30.045614 TX DQ/DQS : PASS
2108 23:56:30.048553 RX DATLAT : PASS
2109 23:56:30.051705 RX DQ/DQS(Engine): PASS
2110 23:56:30.051786 TX OE : NO K
2111 23:56:30.051850 All Pass.
2112 23:56:30.051909
2113 23:56:30.054898 CH 0, Rank 1
2114 23:56:30.058214 SW Impedance : PASS
2115 23:56:30.058297 DUTY Scan : NO K
2116 23:56:30.061781 ZQ Calibration : PASS
2117 23:56:30.061863 Jitter Meter : NO K
2118 23:56:30.064779 CBT Training : PASS
2119 23:56:30.068531 Write leveling : PASS
2120 23:56:30.068609 RX DQS gating : PASS
2121 23:56:30.071444 RX DQ/DQS(RDDQC) : PASS
2122 23:56:30.074549 TX DQ/DQS : PASS
2123 23:56:30.074632 RX DATLAT : PASS
2124 23:56:30.078326 RX DQ/DQS(Engine): PASS
2125 23:56:30.081683 TX OE : NO K
2126 23:56:30.081782 All Pass.
2127 23:56:30.081867
2128 23:56:30.081929 CH 1, Rank 0
2129 23:56:30.084800 SW Impedance : PASS
2130 23:56:30.088498 DUTY Scan : NO K
2131 23:56:30.088586 ZQ Calibration : PASS
2132 23:56:30.091725 Jitter Meter : NO K
2133 23:56:30.094872 CBT Training : PASS
2134 23:56:30.094985 Write leveling : PASS
2135 23:56:30.098125 RX DQS gating : PASS
2136 23:56:30.098236 RX DQ/DQS(RDDQC) : PASS
2137 23:56:30.102200 TX DQ/DQS : PASS
2138 23:56:30.105129 RX DATLAT : PASS
2139 23:56:30.105212 RX DQ/DQS(Engine): PASS
2140 23:56:30.108108 TX OE : NO K
2141 23:56:30.108216 All Pass.
2142 23:56:30.108310
2143 23:56:30.111852 CH 1, Rank 1
2144 23:56:30.111960 SW Impedance : PASS
2145 23:56:30.114769 DUTY Scan : NO K
2146 23:56:30.118135 ZQ Calibration : PASS
2147 23:56:30.118220 Jitter Meter : NO K
2148 23:56:30.121749 CBT Training : PASS
2149 23:56:30.125157 Write leveling : PASS
2150 23:56:30.125239 RX DQS gating : PASS
2151 23:56:30.128101 RX DQ/DQS(RDDQC) : PASS
2152 23:56:30.131516 TX DQ/DQS : PASS
2153 23:56:30.131599 RX DATLAT : PASS
2154 23:56:30.135205 RX DQ/DQS(Engine): PASS
2155 23:56:30.138202 TX OE : NO K
2156 23:56:30.138291 All Pass.
2157 23:56:30.138355
2158 23:56:30.138415 DramC Write-DBI off
2159 23:56:30.141643 PER_BANK_REFRESH: Hybrid Mode
2160 23:56:30.145125 TX_TRACKING: ON
2161 23:56:30.148248 [GetDramInforAfterCalByMRR] Vendor 6.
2162 23:56:30.151709 [GetDramInforAfterCalByMRR] Revision 606.
2163 23:56:30.155339 [GetDramInforAfterCalByMRR] Revision 2 0.
2164 23:56:30.155424 MR0 0x3b3b
2165 23:56:30.158413 MR8 0x5151
2166 23:56:30.161621 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 23:56:30.161703
2168 23:56:30.161767 MR0 0x3b3b
2169 23:56:30.161827 MR8 0x5151
2170 23:56:30.164793 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 23:56:30.164875
2172 23:56:30.175008 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2173 23:56:30.178511 [FAST_K] Save calibration result to emmc
2174 23:56:30.181613 [FAST_K] Save calibration result to emmc
2175 23:56:30.185204 dram_init: config_dvfs: 1
2176 23:56:30.188701 dramc_set_vcore_voltage set vcore to 662500
2177 23:56:30.191709 Read voltage for 1200, 2
2178 23:56:30.191791 Vio18 = 0
2179 23:56:30.191855 Vcore = 662500
2180 23:56:30.194911 Vdram = 0
2181 23:56:30.194993 Vddq = 0
2182 23:56:30.195058 Vmddr = 0
2183 23:56:30.201936 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2184 23:56:30.205054 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2185 23:56:30.208222 MEM_TYPE=3, freq_sel=15
2186 23:56:30.211901 sv_algorithm_assistance_LP4_1600
2187 23:56:30.215073 ============ PULL DRAM RESETB DOWN ============
2188 23:56:30.218240 ========== PULL DRAM RESETB DOWN end =========
2189 23:56:30.225191 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2190 23:56:30.228384 ===================================
2191 23:56:30.231891 LPDDR4 DRAM CONFIGURATION
2192 23:56:30.234957 ===================================
2193 23:56:30.235040 EX_ROW_EN[0] = 0x0
2194 23:56:30.238910 EX_ROW_EN[1] = 0x0
2195 23:56:30.238991 LP4Y_EN = 0x0
2196 23:56:30.241587 WORK_FSP = 0x0
2197 23:56:30.241669 WL = 0x4
2198 23:56:30.244982 RL = 0x4
2199 23:56:30.245087 BL = 0x2
2200 23:56:30.248303 RPST = 0x0
2201 23:56:30.248409 RD_PRE = 0x0
2202 23:56:30.251920 WR_PRE = 0x1
2203 23:56:30.252001 WR_PST = 0x0
2204 23:56:30.255106 DBI_WR = 0x0
2205 23:56:30.255187 DBI_RD = 0x0
2206 23:56:30.258105 OTF = 0x1
2207 23:56:30.262084 ===================================
2208 23:56:30.264839 ===================================
2209 23:56:30.264921 ANA top config
2210 23:56:30.268008 ===================================
2211 23:56:30.271333 DLL_ASYNC_EN = 0
2212 23:56:30.274890 ALL_SLAVE_EN = 0
2213 23:56:30.278612 NEW_RANK_MODE = 1
2214 23:56:30.278695 DLL_IDLE_MODE = 1
2215 23:56:30.281565 LP45_APHY_COMB_EN = 1
2216 23:56:30.285045 TX_ODT_DIS = 1
2217 23:56:30.288576 NEW_8X_MODE = 1
2218 23:56:30.291674 ===================================
2219 23:56:30.294837 ===================================
2220 23:56:30.298767 data_rate = 2400
2221 23:56:30.298902 CKR = 1
2222 23:56:30.301626 DQ_P2S_RATIO = 8
2223 23:56:30.304815 ===================================
2224 23:56:30.308919 CA_P2S_RATIO = 8
2225 23:56:30.311679 DQ_CA_OPEN = 0
2226 23:56:30.314968 DQ_SEMI_OPEN = 0
2227 23:56:30.318798 CA_SEMI_OPEN = 0
2228 23:56:30.318926 CA_FULL_RATE = 0
2229 23:56:30.321909 DQ_CKDIV4_EN = 0
2230 23:56:30.325203 CA_CKDIV4_EN = 0
2231 23:56:30.328402 CA_PREDIV_EN = 0
2232 23:56:30.332215 PH8_DLY = 17
2233 23:56:30.332347 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2234 23:56:30.335480 DQ_AAMCK_DIV = 4
2235 23:56:30.338527 CA_AAMCK_DIV = 4
2236 23:56:30.341809 CA_ADMCK_DIV = 4
2237 23:56:30.345528 DQ_TRACK_CA_EN = 0
2238 23:56:30.348596 CA_PICK = 1200
2239 23:56:30.352245 CA_MCKIO = 1200
2240 23:56:30.352374 MCKIO_SEMI = 0
2241 23:56:30.355342 PLL_FREQ = 2366
2242 23:56:30.358347 DQ_UI_PI_RATIO = 32
2243 23:56:30.361917 CA_UI_PI_RATIO = 0
2244 23:56:30.365343 ===================================
2245 23:56:30.368568 ===================================
2246 23:56:30.371898 memory_type:LPDDR4
2247 23:56:30.372024 GP_NUM : 10
2248 23:56:30.375141 SRAM_EN : 1
2249 23:56:30.375267 MD32_EN : 0
2250 23:56:30.378528 ===================================
2251 23:56:30.382287 [ANA_INIT] >>>>>>>>>>>>>>
2252 23:56:30.385297 <<<<<< [CONFIGURE PHASE]: ANA_TX
2253 23:56:30.388517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2254 23:56:30.391917 ===================================
2255 23:56:30.395462 data_rate = 2400,PCW = 0X5b00
2256 23:56:30.399103 ===================================
2257 23:56:30.402001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2258 23:56:30.408710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 23:56:30.412464 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2260 23:56:30.418747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2261 23:56:30.422377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2262 23:56:30.425633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2263 23:56:30.425743 [ANA_INIT] flow start
2264 23:56:30.428844 [ANA_INIT] PLL >>>>>>>>
2265 23:56:30.432015 [ANA_INIT] PLL <<<<<<<<
2266 23:56:30.432125 [ANA_INIT] MIDPI >>>>>>>>
2267 23:56:30.435738 [ANA_INIT] MIDPI <<<<<<<<
2268 23:56:30.439103 [ANA_INIT] DLL >>>>>>>>
2269 23:56:30.439200 [ANA_INIT] DLL <<<<<<<<
2270 23:56:30.441882 [ANA_INIT] flow end
2271 23:56:30.445690 ============ LP4 DIFF to SE enter ============
2272 23:56:30.448818 ============ LP4 DIFF to SE exit ============
2273 23:56:30.452016 [ANA_INIT] <<<<<<<<<<<<<
2274 23:56:30.455731 [Flow] Enable top DCM control >>>>>
2275 23:56:30.458846 [Flow] Enable top DCM control <<<<<
2276 23:56:30.461978 Enable DLL master slave shuffle
2277 23:56:30.468951 ==============================================================
2278 23:56:30.469061 Gating Mode config
2279 23:56:30.475846 ==============================================================
2280 23:56:30.475926 Config description:
2281 23:56:30.485982 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2282 23:56:30.492254 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2283 23:56:30.498891 SELPH_MODE 0: By rank 1: By Phase
2284 23:56:30.502249 ==============================================================
2285 23:56:30.505225 GAT_TRACK_EN = 1
2286 23:56:30.508744 RX_GATING_MODE = 2
2287 23:56:30.511922 RX_GATING_TRACK_MODE = 2
2288 23:56:30.515311 SELPH_MODE = 1
2289 23:56:30.518944 PICG_EARLY_EN = 1
2290 23:56:30.522325 VALID_LAT_VALUE = 1
2291 23:56:30.525685 ==============================================================
2292 23:56:30.528659 Enter into Gating configuration >>>>
2293 23:56:30.532691 Exit from Gating configuration <<<<
2294 23:56:30.535864 Enter into DVFS_PRE_config >>>>>
2295 23:56:30.548696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2296 23:56:30.552494 Exit from DVFS_PRE_config <<<<<
2297 23:56:30.555562 Enter into PICG configuration >>>>
2298 23:56:30.555670 Exit from PICG configuration <<<<
2299 23:56:30.558828 [RX_INPUT] configuration >>>>>
2300 23:56:30.562565 [RX_INPUT] configuration <<<<<
2301 23:56:30.569411 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2302 23:56:30.572579 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2303 23:56:30.579220 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2304 23:56:30.585690 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2305 23:56:30.592641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 23:56:30.599364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 23:56:30.602237 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2308 23:56:30.605812 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2309 23:56:30.609229 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2310 23:56:30.615545 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2311 23:56:30.618589 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2312 23:56:30.622267 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2313 23:56:30.625269 ===================================
2314 23:56:30.628720 LPDDR4 DRAM CONFIGURATION
2315 23:56:30.632005 ===================================
2316 23:56:30.635819 EX_ROW_EN[0] = 0x0
2317 23:56:30.635952 EX_ROW_EN[1] = 0x0
2318 23:56:30.639049 LP4Y_EN = 0x0
2319 23:56:30.639176 WORK_FSP = 0x0
2320 23:56:30.642485 WL = 0x4
2321 23:56:30.642611 RL = 0x4
2322 23:56:30.645757 BL = 0x2
2323 23:56:30.645881 RPST = 0x0
2324 23:56:30.648610 RD_PRE = 0x0
2325 23:56:30.648727 WR_PRE = 0x1
2326 23:56:30.652468 WR_PST = 0x0
2327 23:56:30.652595 DBI_WR = 0x0
2328 23:56:30.655289 DBI_RD = 0x0
2329 23:56:30.655508 OTF = 0x1
2330 23:56:30.658579 ===================================
2331 23:56:30.662456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2332 23:56:30.669389 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2333 23:56:30.672200 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2334 23:56:30.675381 ===================================
2335 23:56:30.679162 LPDDR4 DRAM CONFIGURATION
2336 23:56:30.682168 ===================================
2337 23:56:30.682293 EX_ROW_EN[0] = 0x10
2338 23:56:30.685950 EX_ROW_EN[1] = 0x0
2339 23:56:30.686066 LP4Y_EN = 0x0
2340 23:56:30.688971 WORK_FSP = 0x0
2341 23:56:30.689141 WL = 0x4
2342 23:56:30.692284 RL = 0x4
2343 23:56:30.695518 BL = 0x2
2344 23:56:30.695644 RPST = 0x0
2345 23:56:30.698702 RD_PRE = 0x0
2346 23:56:30.698824 WR_PRE = 0x1
2347 23:56:30.702721 WR_PST = 0x0
2348 23:56:30.702841 DBI_WR = 0x0
2349 23:56:30.705738 DBI_RD = 0x0
2350 23:56:30.705858 OTF = 0x1
2351 23:56:30.709014 ===================================
2352 23:56:30.715670 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2353 23:56:30.715778 ==
2354 23:56:30.719276 Dram Type= 6, Freq= 0, CH_0, rank 0
2355 23:56:30.722354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 23:56:30.722426 ==
2357 23:56:30.725754 [Duty_Offset_Calibration]
2358 23:56:30.725872 B0:2 B1:1 CA:1
2359 23:56:30.729268
2360 23:56:30.732346 [DutyScan_Calibration_Flow] k_type=0
2361 23:56:30.739994
2362 23:56:30.740114 ==CLK 0==
2363 23:56:30.743499 Final CLK duty delay cell = 0
2364 23:56:30.747049 [0] MAX Duty = 5187%(X100), DQS PI = 24
2365 23:56:30.750527 [0] MIN Duty = 4875%(X100), DQS PI = 0
2366 23:56:30.750602 [0] AVG Duty = 5031%(X100)
2367 23:56:30.750665
2368 23:56:30.753349 CH0 CLK Duty spec in!! Max-Min= 312%
2369 23:56:30.760031 [DutyScan_Calibration_Flow] ====Done====
2370 23:56:30.760137
2371 23:56:30.763720 [DutyScan_Calibration_Flow] k_type=1
2372 23:56:30.778562
2373 23:56:30.778696 ==DQS 0 ==
2374 23:56:30.782126 Final DQS duty delay cell = -4
2375 23:56:30.785412 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2376 23:56:30.788676 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2377 23:56:30.792266 [-4] AVG Duty = 4937%(X100)
2378 23:56:30.792418
2379 23:56:30.792536 ==DQS 1 ==
2380 23:56:30.795364 Final DQS duty delay cell = 0
2381 23:56:30.798784 [0] MAX Duty = 5156%(X100), DQS PI = 14
2382 23:56:30.801906 [0] MIN Duty = 5000%(X100), DQS PI = 34
2383 23:56:30.805661 [0] AVG Duty = 5078%(X100)
2384 23:56:30.805792
2385 23:56:30.808910 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2386 23:56:30.809041
2387 23:56:30.811892 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2388 23:56:30.815645 [DutyScan_Calibration_Flow] ====Done====
2389 23:56:30.815766
2390 23:56:30.818606 [DutyScan_Calibration_Flow] k_type=3
2391 23:56:30.835680
2392 23:56:30.835767 ==DQM 0 ==
2393 23:56:30.838800 Final DQM duty delay cell = 0
2394 23:56:30.842170 [0] MAX Duty = 5156%(X100), DQS PI = 30
2395 23:56:30.845716 [0] MIN Duty = 4875%(X100), DQS PI = 58
2396 23:56:30.845799 [0] AVG Duty = 5015%(X100)
2397 23:56:30.849290
2398 23:56:30.849373 ==DQM 1 ==
2399 23:56:30.852754 Final DQM duty delay cell = 0
2400 23:56:30.855593 [0] MAX Duty = 5093%(X100), DQS PI = 0
2401 23:56:30.859386 [0] MIN Duty = 5031%(X100), DQS PI = 14
2402 23:56:30.859470 [0] AVG Duty = 5062%(X100)
2403 23:56:30.859543
2404 23:56:30.862678 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2405 23:56:30.866470
2406 23:56:30.869263 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2407 23:56:30.872202 [DutyScan_Calibration_Flow] ====Done====
2408 23:56:30.872284
2409 23:56:30.875663 [DutyScan_Calibration_Flow] k_type=2
2410 23:56:30.891976
2411 23:56:30.892070 ==DQ 0 ==
2412 23:56:30.895345 Final DQ duty delay cell = 0
2413 23:56:30.898644 [0] MAX Duty = 5062%(X100), DQS PI = 32
2414 23:56:30.902105 [0] MIN Duty = 4844%(X100), DQS PI = 62
2415 23:56:30.902225 [0] AVG Duty = 4953%(X100)
2416 23:56:30.902325
2417 23:56:30.905051 ==DQ 1 ==
2418 23:56:30.908938 Final DQ duty delay cell = 0
2419 23:56:30.912160 [0] MAX Duty = 5093%(X100), DQS PI = 10
2420 23:56:30.915394 [0] MIN Duty = 4907%(X100), DQS PI = 36
2421 23:56:30.915477 [0] AVG Duty = 5000%(X100)
2422 23:56:30.915542
2423 23:56:30.918448 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2424 23:56:30.922067
2425 23:56:30.925246 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2426 23:56:30.929162 [DutyScan_Calibration_Flow] ====Done====
2427 23:56:30.929246 ==
2428 23:56:30.931979 Dram Type= 6, Freq= 0, CH_1, rank 0
2429 23:56:30.935308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2430 23:56:30.935386 ==
2431 23:56:30.938558 [Duty_Offset_Calibration]
2432 23:56:30.938630 B0:1 B1:0 CA:1
2433 23:56:30.938691
2434 23:56:30.941723 [DutyScan_Calibration_Flow] k_type=0
2435 23:56:30.951102
2436 23:56:30.951186 ==CLK 0==
2437 23:56:30.954322 Final CLK duty delay cell = -4
2438 23:56:30.958123 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2439 23:56:30.961446 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2440 23:56:30.964358 [-4] AVG Duty = 4938%(X100)
2441 23:56:30.964440
2442 23:56:30.968011 CH1 CLK Duty spec in!! Max-Min= 124%
2443 23:56:30.971192 [DutyScan_Calibration_Flow] ====Done====
2444 23:56:30.971274
2445 23:56:30.974438 [DutyScan_Calibration_Flow] k_type=1
2446 23:56:30.991394
2447 23:56:30.991477 ==DQS 0 ==
2448 23:56:30.994178 Final DQS duty delay cell = 0
2449 23:56:30.997394 [0] MAX Duty = 5062%(X100), DQS PI = 14
2450 23:56:31.001006 [0] MIN Duty = 4875%(X100), DQS PI = 0
2451 23:56:31.001080 [0] AVG Duty = 4968%(X100)
2452 23:56:31.001147
2453 23:56:31.004691 ==DQS 1 ==
2454 23:56:31.007791 Final DQS duty delay cell = 0
2455 23:56:31.011263 [0] MAX Duty = 5187%(X100), DQS PI = 18
2456 23:56:31.014159 [0] MIN Duty = 4938%(X100), DQS PI = 58
2457 23:56:31.014268 [0] AVG Duty = 5062%(X100)
2458 23:56:31.017377
2459 23:56:31.020756 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2460 23:56:31.020840
2461 23:56:31.024502 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2462 23:56:31.027884 [DutyScan_Calibration_Flow] ====Done====
2463 23:56:31.027994
2464 23:56:31.030866 [DutyScan_Calibration_Flow] k_type=3
2465 23:56:31.047749
2466 23:56:31.047838 ==DQM 0 ==
2467 23:56:31.050966 Final DQM duty delay cell = 0
2468 23:56:31.053981 [0] MAX Duty = 5187%(X100), DQS PI = 10
2469 23:56:31.057667 [0] MIN Duty = 5031%(X100), DQS PI = 0
2470 23:56:31.057783 [0] AVG Duty = 5109%(X100)
2471 23:56:31.057898
2472 23:56:31.061245 ==DQM 1 ==
2473 23:56:31.064358 Final DQM duty delay cell = 0
2474 23:56:31.067492 [0] MAX Duty = 5031%(X100), DQS PI = 16
2475 23:56:31.071408 [0] MIN Duty = 4875%(X100), DQS PI = 36
2476 23:56:31.071533 [0] AVG Duty = 4953%(X100)
2477 23:56:31.071644
2478 23:56:31.074404 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2479 23:56:31.078156
2480 23:56:31.081226 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2481 23:56:31.084499 [DutyScan_Calibration_Flow] ====Done====
2482 23:56:31.084619
2483 23:56:31.087882 [DutyScan_Calibration_Flow] k_type=2
2484 23:56:31.103218
2485 23:56:31.103324 ==DQ 0 ==
2486 23:56:31.106349 Final DQ duty delay cell = -4
2487 23:56:31.110195 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2488 23:56:31.113161 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2489 23:56:31.116667 [-4] AVG Duty = 4984%(X100)
2490 23:56:31.116746
2491 23:56:31.116810 ==DQ 1 ==
2492 23:56:31.119901 Final DQ duty delay cell = 0
2493 23:56:31.123313 [0] MAX Duty = 5125%(X100), DQS PI = 20
2494 23:56:31.126893 [0] MIN Duty = 4969%(X100), DQS PI = 12
2495 23:56:31.127048 [0] AVG Duty = 5047%(X100)
2496 23:56:31.129782
2497 23:56:31.133372 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2498 23:56:31.133510
2499 23:56:31.136954 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2500 23:56:31.140519 [DutyScan_Calibration_Flow] ====Done====
2501 23:56:31.143318 nWR fixed to 30
2502 23:56:31.143487 [ModeRegInit_LP4] CH0 RK0
2503 23:56:31.146796 [ModeRegInit_LP4] CH0 RK1
2504 23:56:31.149848 [ModeRegInit_LP4] CH1 RK0
2505 23:56:31.153233 [ModeRegInit_LP4] CH1 RK1
2506 23:56:31.153359 match AC timing 7
2507 23:56:31.156465 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2508 23:56:31.163377 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2509 23:56:31.166779 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2510 23:56:31.170159 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2511 23:56:31.176848 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2512 23:56:31.176931 ==
2513 23:56:31.180044 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 23:56:31.183781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 23:56:31.183865 ==
2516 23:56:31.190033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2517 23:56:31.193678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2518 23:56:31.203722 [CA 0] Center 39 (8~70) winsize 63
2519 23:56:31.207158 [CA 1] Center 39 (8~70) winsize 63
2520 23:56:31.210502 [CA 2] Center 35 (5~66) winsize 62
2521 23:56:31.213562 [CA 3] Center 34 (4~65) winsize 62
2522 23:56:31.216759 [CA 4] Center 33 (3~64) winsize 62
2523 23:56:31.220531 [CA 5] Center 32 (3~62) winsize 60
2524 23:56:31.220616
2525 23:56:31.223549 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2526 23:56:31.223621
2527 23:56:31.226591 [CATrainingPosCal] consider 1 rank data
2528 23:56:31.230505 u2DelayCellTimex100 = 270/100 ps
2529 23:56:31.233575 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 23:56:31.236890 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2531 23:56:31.243573 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2532 23:56:31.246689 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2533 23:56:31.250149 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2534 23:56:31.253785 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2535 23:56:31.253927
2536 23:56:31.257046 CA PerBit enable=1, Macro0, CA PI delay=32
2537 23:56:31.257167
2538 23:56:31.260262 [CBTSetCACLKResult] CA Dly = 32
2539 23:56:31.260372 CS Dly: 6 (0~37)
2540 23:56:31.263757 ==
2541 23:56:31.263886 Dram Type= 6, Freq= 0, CH_0, rank 1
2542 23:56:31.269931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 23:56:31.270041 ==
2544 23:56:31.273780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2545 23:56:31.279837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2546 23:56:31.288947 [CA 0] Center 38 (8~69) winsize 62
2547 23:56:31.292690 [CA 1] Center 38 (8~69) winsize 62
2548 23:56:31.296097 [CA 2] Center 35 (4~66) winsize 63
2549 23:56:31.299435 [CA 3] Center 34 (4~65) winsize 62
2550 23:56:31.302998 [CA 4] Center 33 (3~63) winsize 61
2551 23:56:31.306289 [CA 5] Center 32 (3~62) winsize 60
2552 23:56:31.306372
2553 23:56:31.309382 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2554 23:56:31.309465
2555 23:56:31.312500 [CATrainingPosCal] consider 2 rank data
2556 23:56:31.316632 u2DelayCellTimex100 = 270/100 ps
2557 23:56:31.319475 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 23:56:31.322714 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2559 23:56:31.329481 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2560 23:56:31.333306 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2561 23:56:31.336518 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2562 23:56:31.339781 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2563 23:56:31.339864
2564 23:56:31.343116 CA PerBit enable=1, Macro0, CA PI delay=32
2565 23:56:31.343199
2566 23:56:31.346419 [CBTSetCACLKResult] CA Dly = 32
2567 23:56:31.346502 CS Dly: 6 (0~38)
2568 23:56:31.346567
2569 23:56:31.349772 ----->DramcWriteLeveling(PI) begin...
2570 23:56:31.349856 ==
2571 23:56:31.352610 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 23:56:31.359884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 23:56:31.360004 ==
2574 23:56:31.363287 Write leveling (Byte 0): 33 => 33
2575 23:56:31.366785 Write leveling (Byte 1): 27 => 27
2576 23:56:31.366869 DramcWriteLeveling(PI) end<-----
2577 23:56:31.366936
2578 23:56:31.369731 ==
2579 23:56:31.372777 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 23:56:31.375990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 23:56:31.376064 ==
2582 23:56:31.379784 [Gating] SW mode calibration
2583 23:56:31.386590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2584 23:56:31.389801 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2585 23:56:31.396658 0 15 0 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
2586 23:56:31.400012 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2587 23:56:31.402885 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 23:56:31.409605 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 23:56:31.413075 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:56:31.416309 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 23:56:31.422819 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2592 23:56:31.426148 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2593 23:56:31.429957 1 0 0 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
2594 23:56:31.436555 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 23:56:31.439661 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 23:56:31.442834 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:56:31.446046 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:56:31.452956 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 23:56:31.456295 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
2600 23:56:31.459831 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2601 23:56:31.466384 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
2602 23:56:31.469916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 23:56:31.473242 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 23:56:31.479934 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 23:56:31.483194 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:56:31.486273 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:56:31.493075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 23:56:31.496240 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2609 23:56:31.500006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2610 23:56:31.506218 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:56:31.509981 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:56:31.513224 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:56:31.519908 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:56:31.523486 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:56:31.526639 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:56:31.533087 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:56:31.536715 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:56:31.539899 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:56:31.543313 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:56:31.549700 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:56:31.553410 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:56:31.556533 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:56:31.562955 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:56:31.566793 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2625 23:56:31.569929 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 23:56:31.573747 Total UI for P1: 0, mck2ui 16
2627 23:56:31.576896 best dqsien dly found for B0: ( 1, 3, 28)
2628 23:56:31.583558 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 23:56:31.583686 Total UI for P1: 0, mck2ui 16
2630 23:56:31.586704 best dqsien dly found for B1: ( 1, 3, 30)
2631 23:56:31.593191 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2632 23:56:31.596932 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2633 23:56:31.597028
2634 23:56:31.599967 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2635 23:56:31.603132 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2636 23:56:31.606745 [Gating] SW calibration Done
2637 23:56:31.606848 ==
2638 23:56:31.610256 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 23:56:31.613054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 23:56:31.613158 ==
2641 23:56:31.617050 RX Vref Scan: 0
2642 23:56:31.617128
2643 23:56:31.617208 RX Vref 0 -> 0, step: 1
2644 23:56:31.617269
2645 23:56:31.620056 RX Delay -40 -> 252, step: 8
2646 23:56:31.623219 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2647 23:56:31.630423 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2648 23:56:31.633311 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2649 23:56:31.636275 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2650 23:56:31.639988 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2651 23:56:31.643235 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2652 23:56:31.646846 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2653 23:56:31.653432 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2654 23:56:31.656530 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2655 23:56:31.660040 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2656 23:56:31.663571 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2657 23:56:31.666620 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2658 23:56:31.673589 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2659 23:56:31.676641 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2660 23:56:31.679809 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2661 23:56:31.683599 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2662 23:56:31.683687 ==
2663 23:56:31.686959 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 23:56:31.693584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 23:56:31.693716 ==
2666 23:56:31.693835 DQS Delay:
2667 23:56:31.693952 DQS0 = 0, DQS1 = 0
2668 23:56:31.696902 DQM Delay:
2669 23:56:31.697025 DQM0 = 121, DQM1 = 113
2670 23:56:31.700052 DQ Delay:
2671 23:56:31.703187 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2672 23:56:31.707083 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2673 23:56:31.710060 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2674 23:56:31.713792 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2675 23:56:31.713915
2676 23:56:31.714030
2677 23:56:31.714139 ==
2678 23:56:31.717252 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 23:56:31.720198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 23:56:31.720313 ==
2681 23:56:31.720429
2682 23:56:31.723419
2683 23:56:31.723537 TX Vref Scan disable
2684 23:56:31.727328 == TX Byte 0 ==
2685 23:56:31.730462 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2686 23:56:31.733654 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2687 23:56:31.736787 == TX Byte 1 ==
2688 23:56:31.740591 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2689 23:56:31.743351 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2690 23:56:31.743452 ==
2691 23:56:31.747095 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 23:56:31.753426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 23:56:31.753507 ==
2694 23:56:31.764576 TX Vref=22, minBit 0, minWin=25, winSum=410
2695 23:56:31.767765 TX Vref=24, minBit 1, minWin=25, winSum=417
2696 23:56:31.770969 TX Vref=26, minBit 0, minWin=26, winSum=422
2697 23:56:31.774591 TX Vref=28, minBit 0, minWin=26, winSum=422
2698 23:56:31.778329 TX Vref=30, minBit 1, minWin=26, winSum=426
2699 23:56:31.781146 TX Vref=32, minBit 0, minWin=26, winSum=421
2700 23:56:31.787683 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 30
2701 23:56:31.787774
2702 23:56:31.791292 Final TX Range 1 Vref 30
2703 23:56:31.791369
2704 23:56:31.791433 ==
2705 23:56:31.794238 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 23:56:31.798043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 23:56:31.798129 ==
2708 23:56:31.798196
2709 23:56:31.800955
2710 23:56:31.801066 TX Vref Scan disable
2711 23:56:31.804389 == TX Byte 0 ==
2712 23:56:31.807873 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2713 23:56:31.810930 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2714 23:56:31.814333 == TX Byte 1 ==
2715 23:56:31.817715 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2716 23:56:31.821290 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2717 23:56:31.821384
2718 23:56:31.824315 [DATLAT]
2719 23:56:31.824430 Freq=1200, CH0 RK0
2720 23:56:31.824532
2721 23:56:31.828129 DATLAT Default: 0xd
2722 23:56:31.828214 0, 0xFFFF, sum = 0
2723 23:56:31.831243 1, 0xFFFF, sum = 0
2724 23:56:31.831356 2, 0xFFFF, sum = 0
2725 23:56:31.834416 3, 0xFFFF, sum = 0
2726 23:56:31.834532 4, 0xFFFF, sum = 0
2727 23:56:31.837611 5, 0xFFFF, sum = 0
2728 23:56:31.837702 6, 0xFFFF, sum = 0
2729 23:56:31.841566 7, 0xFFFF, sum = 0
2730 23:56:31.841655 8, 0xFFFF, sum = 0
2731 23:56:31.844334 9, 0xFFFF, sum = 0
2732 23:56:31.847790 10, 0xFFFF, sum = 0
2733 23:56:31.847869 11, 0xFFFF, sum = 0
2734 23:56:31.851385 12, 0x0, sum = 1
2735 23:56:31.851464 13, 0x0, sum = 2
2736 23:56:31.851529 14, 0x0, sum = 3
2737 23:56:31.854703 15, 0x0, sum = 4
2738 23:56:31.854778 best_step = 13
2739 23:56:31.854839
2740 23:56:31.857802 ==
2741 23:56:31.857902 Dram Type= 6, Freq= 0, CH_0, rank 0
2742 23:56:31.864753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2743 23:56:31.864844 ==
2744 23:56:31.864927 RX Vref Scan: 1
2745 23:56:31.865029
2746 23:56:31.868217 Set Vref Range= 32 -> 127
2747 23:56:31.868317
2748 23:56:31.871085 RX Vref 32 -> 127, step: 1
2749 23:56:31.871164
2750 23:56:31.874378 RX Delay -13 -> 252, step: 4
2751 23:56:31.874455
2752 23:56:31.878262 Set Vref, RX VrefLevel [Byte0]: 32
2753 23:56:31.881531 [Byte1]: 32
2754 23:56:31.881622
2755 23:56:31.884580 Set Vref, RX VrefLevel [Byte0]: 33
2756 23:56:31.887837 [Byte1]: 33
2757 23:56:31.887939
2758 23:56:31.891079 Set Vref, RX VrefLevel [Byte0]: 34
2759 23:56:31.895050 [Byte1]: 34
2760 23:56:31.898506
2761 23:56:31.898609 Set Vref, RX VrefLevel [Byte0]: 35
2762 23:56:31.901917 [Byte1]: 35
2763 23:56:31.906419
2764 23:56:31.906549 Set Vref, RX VrefLevel [Byte0]: 36
2765 23:56:31.910613 [Byte1]: 36
2766 23:56:31.914233
2767 23:56:31.914389 Set Vref, RX VrefLevel [Byte0]: 37
2768 23:56:31.917353 [Byte1]: 37
2769 23:56:31.922040
2770 23:56:31.922146 Set Vref, RX VrefLevel [Byte0]: 38
2771 23:56:31.925469 [Byte1]: 38
2772 23:56:31.929913
2773 23:56:31.930023 Set Vref, RX VrefLevel [Byte0]: 39
2774 23:56:31.933031 [Byte1]: 39
2775 23:56:31.937703
2776 23:56:31.937800 Set Vref, RX VrefLevel [Byte0]: 40
2777 23:56:31.941276 [Byte1]: 40
2778 23:56:31.945652
2779 23:56:31.945737 Set Vref, RX VrefLevel [Byte0]: 41
2780 23:56:31.949489 [Byte1]: 41
2781 23:56:31.953886
2782 23:56:31.953969 Set Vref, RX VrefLevel [Byte0]: 42
2783 23:56:31.957318 [Byte1]: 42
2784 23:56:31.961565
2785 23:56:31.961679 Set Vref, RX VrefLevel [Byte0]: 43
2786 23:56:31.964655 [Byte1]: 43
2787 23:56:31.969703
2788 23:56:31.969797 Set Vref, RX VrefLevel [Byte0]: 44
2789 23:56:31.972876 [Byte1]: 44
2790 23:56:31.977414
2791 23:56:31.977507 Set Vref, RX VrefLevel [Byte0]: 45
2792 23:56:31.980442 [Byte1]: 45
2793 23:56:31.985480
2794 23:56:31.985649 Set Vref, RX VrefLevel [Byte0]: 46
2795 23:56:31.989022 [Byte1]: 46
2796 23:56:31.993404
2797 23:56:31.993578 Set Vref, RX VrefLevel [Byte0]: 47
2798 23:56:31.996646 [Byte1]: 47
2799 23:56:32.001006
2800 23:56:32.001134 Set Vref, RX VrefLevel [Byte0]: 48
2801 23:56:32.004108 [Byte1]: 48
2802 23:56:32.009256
2803 23:56:32.009364 Set Vref, RX VrefLevel [Byte0]: 49
2804 23:56:32.012514 [Byte1]: 49
2805 23:56:32.016764
2806 23:56:32.016841 Set Vref, RX VrefLevel [Byte0]: 50
2807 23:56:32.020064 [Byte1]: 50
2808 23:56:32.025324
2809 23:56:32.025409 Set Vref, RX VrefLevel [Byte0]: 51
2810 23:56:32.027971 [Byte1]: 51
2811 23:56:32.032666
2812 23:56:32.032739 Set Vref, RX VrefLevel [Byte0]: 52
2813 23:56:32.036076 [Byte1]: 52
2814 23:56:32.040326
2815 23:56:32.040443 Set Vref, RX VrefLevel [Byte0]: 53
2816 23:56:32.044218 [Byte1]: 53
2817 23:56:32.048699
2818 23:56:32.048806 Set Vref, RX VrefLevel [Byte0]: 54
2819 23:56:32.052309 [Byte1]: 54
2820 23:56:32.056215
2821 23:56:32.056307 Set Vref, RX VrefLevel [Byte0]: 55
2822 23:56:32.059626 [Byte1]: 55
2823 23:56:32.064403
2824 23:56:32.064512 Set Vref, RX VrefLevel [Byte0]: 56
2825 23:56:32.067714 [Byte1]: 56
2826 23:56:32.071996
2827 23:56:32.072078 Set Vref, RX VrefLevel [Byte0]: 57
2828 23:56:32.075505 [Byte1]: 57
2829 23:56:32.079963
2830 23:56:32.080044 Set Vref, RX VrefLevel [Byte0]: 58
2831 23:56:32.082995 [Byte1]: 58
2832 23:56:32.087843
2833 23:56:32.087955 Set Vref, RX VrefLevel [Byte0]: 59
2834 23:56:32.091763 [Byte1]: 59
2835 23:56:32.096121
2836 23:56:32.099230 Set Vref, RX VrefLevel [Byte0]: 60
2837 23:56:32.099314 [Byte1]: 60
2838 23:56:32.103663
2839 23:56:32.103745 Set Vref, RX VrefLevel [Byte0]: 61
2840 23:56:32.107298 [Byte1]: 61
2841 23:56:32.111798
2842 23:56:32.111880 Set Vref, RX VrefLevel [Byte0]: 62
2843 23:56:32.115389 [Byte1]: 62
2844 23:56:32.119612
2845 23:56:32.119724 Set Vref, RX VrefLevel [Byte0]: 63
2846 23:56:32.122721 [Byte1]: 63
2847 23:56:32.127151
2848 23:56:32.127235 Set Vref, RX VrefLevel [Byte0]: 64
2849 23:56:32.130411 [Byte1]: 64
2850 23:56:32.135016
2851 23:56:32.135098 Set Vref, RX VrefLevel [Byte0]: 65
2852 23:56:32.138895 [Byte1]: 65
2853 23:56:32.143419
2854 23:56:32.143502 Set Vref, RX VrefLevel [Byte0]: 66
2855 23:56:32.146579 [Byte1]: 66
2856 23:56:32.150985
2857 23:56:32.151100 Set Vref, RX VrefLevel [Byte0]: 67
2858 23:56:32.154173 [Byte1]: 67
2859 23:56:32.159358
2860 23:56:32.159464 Set Vref, RX VrefLevel [Byte0]: 68
2861 23:56:32.162431 [Byte1]: 68
2862 23:56:32.166774
2863 23:56:32.166865 Set Vref, RX VrefLevel [Byte0]: 69
2864 23:56:32.170231 [Byte1]: 69
2865 23:56:32.174857
2866 23:56:32.174940 Final RX Vref Byte 0 = 55 to rank0
2867 23:56:32.178042 Final RX Vref Byte 1 = 49 to rank0
2868 23:56:32.181103 Final RX Vref Byte 0 = 55 to rank1
2869 23:56:32.185054 Final RX Vref Byte 1 = 49 to rank1==
2870 23:56:32.188296 Dram Type= 6, Freq= 0, CH_0, rank 0
2871 23:56:32.194706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 23:56:32.194792 ==
2873 23:56:32.194858 DQS Delay:
2874 23:56:32.194919 DQS0 = 0, DQS1 = 0
2875 23:56:32.198063 DQM Delay:
2876 23:56:32.198146 DQM0 = 120, DQM1 = 112
2877 23:56:32.201255 DQ Delay:
2878 23:56:32.204349 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2879 23:56:32.207912 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2880 23:56:32.211253 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2881 23:56:32.214886 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2882 23:56:32.214984
2883 23:56:32.215072
2884 23:56:32.221390 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2885 23:56:32.224352 CH0 RK0: MR19=404, MR18=150E
2886 23:56:32.231394 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2887 23:56:32.231502
2888 23:56:32.234645 ----->DramcWriteLeveling(PI) begin...
2889 23:56:32.234727 ==
2890 23:56:32.238420 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 23:56:32.241496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 23:56:32.244854 ==
2893 23:56:32.244941 Write leveling (Byte 0): 35 => 35
2894 23:56:32.248139 Write leveling (Byte 1): 28 => 28
2895 23:56:32.251202 DramcWriteLeveling(PI) end<-----
2896 23:56:32.251321
2897 23:56:32.251408 ==
2898 23:56:32.255017 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 23:56:32.261387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 23:56:32.261469 ==
2901 23:56:32.261546 [Gating] SW mode calibration
2902 23:56:32.271437 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2903 23:56:32.275087 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2904 23:56:32.278131 0 15 0 | B1->B0 | 3434 2d2d | 0 1 | (0 0) (0 0)
2905 23:56:32.285028 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 23:56:32.287979 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 23:56:32.291685 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 23:56:32.298364 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 23:56:32.301919 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 23:56:32.305028 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 23:56:32.311478 0 15 28 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
2912 23:56:32.315002 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 23:56:32.318351 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 23:56:32.325218 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 23:56:32.328220 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 23:56:32.331239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 23:56:32.338607 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 23:56:32.341629 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 23:56:34.109754 1 0 28 | B1->B0 | 3737 3737 | 0 0 | (1 1) (0 0)
2920 23:56:34.109982 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2921 23:56:34.110096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 23:56:34.110192 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 23:56:34.110284 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 23:56:34.110384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:56:34.110475 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 23:56:34.110568 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 23:56:34.110659 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2928 23:56:34.110746 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2929 23:56:34.110843 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:56:34.110932 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:56:34.111018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:56:34.111114 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:56:34.111201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:56:34.111286 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:56:34.111384 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:56:34.111472 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:56:34.111563 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:56:34.111652 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:56:34.111737 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:56:34.111829 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:56:34.111920 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:56:34.112005 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2943 23:56:34.112099 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2944 23:56:34.112185 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2945 23:56:34.112271 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 23:56:34.112375 Total UI for P1: 0, mck2ui 16
2947 23:56:34.112465 best dqsien dly found for B0: ( 1, 3, 30)
2948 23:56:34.112557 Total UI for P1: 0, mck2ui 16
2949 23:56:34.112667 best dqsien dly found for B1: ( 1, 3, 28)
2950 23:56:34.112755 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2951 23:56:34.112852 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2952 23:56:34.112939
2953 23:56:34.113024 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2954 23:56:34.113119 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2955 23:56:34.113204 [Gating] SW calibration Done
2956 23:56:34.113288 ==
2957 23:56:34.113382 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 23:56:34.113469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 23:56:34.113560 ==
2960 23:56:34.113648 RX Vref Scan: 0
2961 23:56:34.113732
2962 23:56:34.113822 RX Vref 0 -> 0, step: 1
2963 23:56:34.113910
2964 23:56:34.113995 RX Delay -40 -> 252, step: 8
2965 23:56:34.114086 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2966 23:56:34.114174 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2967 23:56:34.114259 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2968 23:56:34.114354 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2969 23:56:34.114441 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2970 23:56:34.114542 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2971 23:56:34.114640 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2972 23:56:34.114725 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2973 23:56:34.114816 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2974 23:56:34.114907 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2975 23:56:34.114992 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2976 23:56:34.115083 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2977 23:56:34.115172 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2978 23:56:34.115256 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2979 23:56:34.115350 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2980 23:56:34.115437 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2981 23:56:34.115521 ==
2982 23:56:34.115616 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 23:56:34.115701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 23:56:34.115791 ==
2985 23:56:34.115879 DQS Delay:
2986 23:56:34.115964 DQS0 = 0, DQS1 = 0
2987 23:56:34.116054 DQM Delay:
2988 23:56:34.116142 DQM0 = 122, DQM1 = 112
2989 23:56:34.116226 DQ Delay:
2990 23:56:34.116320 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2991 23:56:34.116415 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2992 23:56:34.116515 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2993 23:56:34.116614 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2994 23:56:34.116698
2995 23:56:34.116789
2996 23:56:34.116878 ==
2997 23:56:34.116963 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 23:56:34.117070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 23:56:34.117153 ==
3000 23:56:34.117235
3001 23:56:34.117326
3002 23:56:34.117410 TX Vref Scan disable
3003 23:56:34.117497 == TX Byte 0 ==
3004 23:56:34.117584 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3005 23:56:34.117667 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3006 23:56:34.117816 == TX Byte 1 ==
3007 23:56:34.117921 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3008 23:56:34.118011 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3009 23:56:34.118133 ==
3010 23:56:34.118220 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 23:56:34.118313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 23:56:34.118432 ==
3013 23:56:34.118521 TX Vref=22, minBit 1, minWin=25, winSum=415
3014 23:56:34.118607 TX Vref=24, minBit 0, minWin=26, winSum=421
3015 23:56:34.118713 TX Vref=26, minBit 3, minWin=25, winSum=420
3016 23:56:34.118820 TX Vref=28, minBit 1, minWin=26, winSum=425
3017 23:56:34.118905 TX Vref=30, minBit 2, minWin=26, winSum=427
3018 23:56:34.119029 TX Vref=32, minBit 1, minWin=26, winSum=426
3019 23:56:34.119113 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 30
3020 23:56:34.119214
3021 23:56:34.119317 Final TX Range 1 Vref 30
3022 23:56:34.119402
3023 23:56:34.119520 ==
3024 23:56:34.119607 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 23:56:34.119689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 23:56:34.119853 ==
3027 23:56:34.119951
3028 23:56:34.120074
3029 23:56:34.120156 TX Vref Scan disable
3030 23:56:34.120259 == TX Byte 0 ==
3031 23:56:34.120368 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3032 23:56:34.120431 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3033 23:56:34.120493 == TX Byte 1 ==
3034 23:56:34.120554 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3035 23:56:34.120836 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3036 23:56:34.120901
3037 23:56:34.121021 [DATLAT]
3038 23:56:34.121121 Freq=1200, CH0 RK1
3039 23:56:34.121176
3040 23:56:34.121237 DATLAT Default: 0xd
3041 23:56:34.121291 0, 0xFFFF, sum = 0
3042 23:56:34.121352 1, 0xFFFF, sum = 0
3043 23:56:34.121410 2, 0xFFFF, sum = 0
3044 23:56:34.121471 3, 0xFFFF, sum = 0
3045 23:56:34.121526 4, 0xFFFF, sum = 0
3046 23:56:34.121580 5, 0xFFFF, sum = 0
3047 23:56:34.121640 6, 0xFFFF, sum = 0
3048 23:56:34.121700 7, 0xFFFF, sum = 0
3049 23:56:34.121757 8, 0xFFFF, sum = 0
3050 23:56:34.121811 9, 0xFFFF, sum = 0
3051 23:56:34.121865 10, 0xFFFF, sum = 0
3052 23:56:34.121925 11, 0xFFFF, sum = 0
3053 23:56:34.121988 12, 0x0, sum = 1
3054 23:56:34.122042 13, 0x0, sum = 2
3055 23:56:34.122096 14, 0x0, sum = 3
3056 23:56:34.122156 15, 0x0, sum = 4
3057 23:56:34.122218 best_step = 13
3058 23:56:34.122272
3059 23:56:34.122324 ==
3060 23:56:34.122382 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 23:56:34.122443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 23:56:34.122499 ==
3063 23:56:34.122552 RX Vref Scan: 0
3064 23:56:34.122611
3065 23:56:34.122670 RX Vref 0 -> 0, step: 1
3066 23:56:34.122726
3067 23:56:34.122779 RX Delay -13 -> 252, step: 4
3068 23:56:34.122832 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3069 23:56:34.122908 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3070 23:56:34.122984 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3071 23:56:34.123038 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3072 23:56:34.123091 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3073 23:56:34.123152 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3074 23:56:34.123205 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3075 23:56:34.123264 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3076 23:56:34.123317 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3077 23:56:34.123376 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3078 23:56:34.123435 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3079 23:56:34.123493 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3080 23:56:34.123547 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3081 23:56:34.123604 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3082 23:56:34.123661 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3083 23:56:34.123714 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3084 23:56:34.123772 ==
3085 23:56:34.123825 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 23:56:34.123886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 23:56:34.123956 ==
3088 23:56:34.124016 DQS Delay:
3089 23:56:34.124088 DQS0 = 0, DQS1 = 0
3090 23:56:34.124201 DQM Delay:
3091 23:56:34.124294 DQM0 = 120, DQM1 = 110
3092 23:56:34.124397 DQ Delay:
3093 23:56:34.124457 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3094 23:56:34.124518 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3095 23:56:34.124573 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =100
3096 23:56:34.124631 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3097 23:56:34.124698
3098 23:56:34.124788
3099 23:56:34.124843 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3100 23:56:34.124906 CH0 RK1: MR19=403, MR18=12F3
3101 23:56:34.124970 CH0_RK1: MR19=0x403, MR18=0x12F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3102 23:56:34.125026 [RxdqsGatingPostProcess] freq 1200
3103 23:56:34.125081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3104 23:56:34.125141 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 23:56:34.125200 best DQS1 dly(2T, 0.5T) = (0, 11)
3106 23:56:34.125261 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 23:56:34.125315 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3108 23:56:34.125374 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 23:56:34.125432 best DQS1 dly(2T, 0.5T) = (0, 11)
3110 23:56:34.125492 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 23:56:34.125547 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3112 23:56:34.125606 Pre-setting of DQS Precalculation
3113 23:56:34.125664 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3114 23:56:34.125725 ==
3115 23:56:34.125780 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 23:56:34.125834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 23:56:34.125897 ==
3118 23:56:34.125957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3119 23:56:34.126013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3120 23:56:34.126067 [CA 0] Center 37 (7~68) winsize 62
3121 23:56:34.126127 [CA 1] Center 37 (7~68) winsize 62
3122 23:56:34.126190 [CA 2] Center 35 (5~65) winsize 61
3123 23:56:34.126245 [CA 3] Center 34 (4~64) winsize 61
3124 23:56:34.126299 [CA 4] Center 34 (4~64) winsize 61
3125 23:56:34.126358 [CA 5] Center 33 (3~63) winsize 61
3126 23:56:34.126416
3127 23:56:34.126472 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3128 23:56:34.126532
3129 23:56:34.126592 [CATrainingPosCal] consider 1 rank data
3130 23:56:34.126650 u2DelayCellTimex100 = 270/100 ps
3131 23:56:34.126705 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 23:56:34.126764 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 23:56:34.126824 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3134 23:56:34.126883 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 23:56:34.126939 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 23:56:34.126999 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3137 23:56:34.127054
3138 23:56:34.127116 CA PerBit enable=1, Macro0, CA PI delay=33
3139 23:56:34.127171
3140 23:56:34.127230 [CBTSetCACLKResult] CA Dly = 33
3141 23:56:34.127285 CS Dly: 8 (0~39)
3142 23:56:34.127345 ==
3143 23:56:34.127402 Dram Type= 6, Freq= 0, CH_1, rank 1
3144 23:56:34.127463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 23:56:34.127518 ==
3146 23:56:34.127577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3147 23:56:34.127635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3148 23:56:34.127694 [CA 0] Center 37 (7~68) winsize 62
3149 23:56:34.127749 [CA 1] Center 38 (8~68) winsize 61
3150 23:56:34.127854 [CA 2] Center 35 (5~65) winsize 61
3151 23:56:34.127948 [CA 3] Center 34 (4~65) winsize 62
3152 23:56:34.128038 [CA 4] Center 34 (4~65) winsize 62
3153 23:56:34.128126 [CA 5] Center 34 (4~64) winsize 61
3154 23:56:34.128215
3155 23:56:34.128319 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3156 23:56:34.128408
3157 23:56:34.128468 [CATrainingPosCal] consider 2 rank data
3158 23:56:34.128523 u2DelayCellTimex100 = 270/100 ps
3159 23:56:34.128585 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 23:56:34.128639 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3161 23:56:34.128698 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3162 23:56:34.128752 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 23:56:34.128813 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 23:56:34.128888 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3165 23:56:34.128955
3166 23:56:34.129238 CA PerBit enable=1, Macro0, CA PI delay=33
3167 23:56:34.129321
3168 23:56:34.129377 [CBTSetCACLKResult] CA Dly = 33
3169 23:56:34.129436 CS Dly: 9 (0~41)
3170 23:56:34.129489
3171 23:56:34.129547 ----->DramcWriteLeveling(PI) begin...
3172 23:56:34.129606 ==
3173 23:56:34.129660 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 23:56:34.129719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 23:56:34.129777 ==
3176 23:56:34.129834 Write leveling (Byte 0): 26 => 26
3177 23:56:34.129890 Write leveling (Byte 1): 27 => 27
3178 23:56:34.129948 DramcWriteLeveling(PI) end<-----
3179 23:56:34.130002
3180 23:56:34.130079 ==
3181 23:56:34.130197 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 23:56:34.130288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 23:56:34.130378 ==
3184 23:56:34.130467 [Gating] SW mode calibration
3185 23:56:34.130527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3186 23:56:34.130586 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3187 23:56:34.130640 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 23:56:34.130701 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 23:56:34.130756 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 23:56:34.130819 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 23:56:34.130888 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 23:56:34.130993 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 23:56:34.131083 0 15 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
3194 23:56:34.131168 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3195 23:56:34.131263 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 23:56:34.131352 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 23:56:34.131441 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 23:56:34.131533 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 23:56:34.131618 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 23:56:34.131707 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 23:56:34.131800 1 0 24 | B1->B0 | 3333 3f3f | 0 1 | (0 0) (0 0)
3202 23:56:34.131886 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 23:56:34.131976 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 23:56:34.132061 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 23:56:34.132146 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 23:56:34.132236 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 23:56:34.132320 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 23:56:34.132393 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 23:56:34.132455 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3210 23:56:34.132510 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3211 23:56:34.132596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:56:34.132655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:56:34.132718 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:56:34.132773 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:56:34.132828 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:56:34.132892 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:56:34.132966 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:56:34.133063 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:56:34.133130 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:56:34.133190 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:56:34.133251 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:56:34.133306 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:56:34.133366 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:56:34.133427 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:56:34.133542 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 23:56:34.133641 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 23:56:34.133732 Total UI for P1: 0, mck2ui 16
3228 23:56:34.133818 best dqsien dly found for B0: ( 1, 3, 24)
3229 23:56:34.133911 Total UI for P1: 0, mck2ui 16
3230 23:56:34.134002 best dqsien dly found for B1: ( 1, 3, 24)
3231 23:56:34.134091 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3232 23:56:34.134184 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3233 23:56:34.134271
3234 23:56:34.134360 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3235 23:56:34.134453 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3236 23:56:34.134545 [Gating] SW calibration Done
3237 23:56:34.134646 ==
3238 23:56:34.134738 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:56:34.134828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:56:34.134920 ==
3241 23:56:34.135005 RX Vref Scan: 0
3242 23:56:34.135093
3243 23:56:34.135184 RX Vref 0 -> 0, step: 1
3244 23:56:34.135268
3245 23:56:34.135360 RX Delay -40 -> 252, step: 8
3246 23:56:34.135450 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3247 23:56:34.135535 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3248 23:56:34.135628 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 23:56:34.135720 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3250 23:56:34.135809 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3251 23:56:34.135897 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3252 23:56:34.135988 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3253 23:56:34.136077 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3254 23:56:34.136169 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3255 23:56:34.136256 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3256 23:56:34.136353 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3257 23:56:34.136418 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3258 23:56:34.136474 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 23:56:34.136529 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3260 23:56:34.136593 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3261 23:56:34.136649 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3262 23:56:34.136709 ==
3263 23:56:34.136764 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 23:56:34.136825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 23:56:34.136883 ==
3266 23:56:34.136943 DQS Delay:
3267 23:56:34.137036 DQS0 = 0, DQS1 = 0
3268 23:56:34.137098 DQM Delay:
3269 23:56:34.137155 DQM0 = 120, DQM1 = 116
3270 23:56:34.137215 DQ Delay:
3271 23:56:34.137465 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3272 23:56:34.137533 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3273 23:56:34.137594 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3274 23:56:34.137651 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3275 23:56:34.137743
3276 23:56:34.137810
3277 23:56:34.137865 ==
3278 23:56:34.137925 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 23:56:34.137981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 23:56:34.138042 ==
3281 23:56:34.138100
3282 23:56:34.138161
3283 23:56:34.138216 TX Vref Scan disable
3284 23:56:34.138276 == TX Byte 0 ==
3285 23:56:34.138335 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3286 23:56:34.138390 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3287 23:56:34.138451 == TX Byte 1 ==
3288 23:56:34.138510 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3289 23:56:34.138569 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3290 23:56:34.138625 ==
3291 23:56:34.138686 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 23:56:34.138741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 23:56:34.138803 ==
3294 23:56:34.138858 TX Vref=22, minBit 9, minWin=24, winSum=411
3295 23:56:34.138917 TX Vref=24, minBit 9, minWin=25, winSum=419
3296 23:56:34.138973 TX Vref=26, minBit 1, minWin=26, winSum=427
3297 23:56:34.139036 TX Vref=28, minBit 1, minWin=26, winSum=429
3298 23:56:34.139092 TX Vref=30, minBit 2, minWin=26, winSum=432
3299 23:56:34.139147 TX Vref=32, minBit 2, minWin=26, winSum=431
3300 23:56:34.139207 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
3301 23:56:34.139268
3302 23:56:34.139325 Final TX Range 1 Vref 30
3303 23:56:34.139380
3304 23:56:34.139440 ==
3305 23:56:34.139499 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 23:56:34.139557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 23:56:34.139613 ==
3308 23:56:34.139671
3309 23:56:34.139730
3310 23:56:34.139787 TX Vref Scan disable
3311 23:56:34.139841 == TX Byte 0 ==
3312 23:56:34.139895 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3313 23:56:34.139960 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3314 23:56:34.140018 == TX Byte 1 ==
3315 23:56:34.140074 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3316 23:56:34.140129 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3317 23:56:34.140189
3318 23:56:34.140248 [DATLAT]
3319 23:56:34.140306 Freq=1200, CH1 RK0
3320 23:56:34.140384
3321 23:56:34.140444 DATLAT Default: 0xd
3322 23:56:34.140503 0, 0xFFFF, sum = 0
3323 23:56:34.140563 1, 0xFFFF, sum = 0
3324 23:56:34.140618 2, 0xFFFF, sum = 0
3325 23:56:34.140677 3, 0xFFFF, sum = 0
3326 23:56:34.140737 4, 0xFFFF, sum = 0
3327 23:56:34.140794 5, 0xFFFF, sum = 0
3328 23:56:34.140848 6, 0xFFFF, sum = 0
3329 23:56:34.140950 7, 0xFFFF, sum = 0
3330 23:56:34.141017 8, 0xFFFF, sum = 0
3331 23:56:34.141074 9, 0xFFFF, sum = 0
3332 23:56:34.141129 10, 0xFFFF, sum = 0
3333 23:56:34.141189 11, 0xFFFF, sum = 0
3334 23:56:34.141249 12, 0x0, sum = 1
3335 23:56:34.141307 13, 0x0, sum = 2
3336 23:56:34.141361 14, 0x0, sum = 3
3337 23:56:34.141418 15, 0x0, sum = 4
3338 23:56:34.141477 best_step = 13
3339 23:56:34.141534
3340 23:56:34.141588 ==
3341 23:56:34.141641 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 23:56:34.141701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 23:56:34.141762 ==
3344 23:56:34.141816 RX Vref Scan: 1
3345 23:56:34.141869
3346 23:56:34.141926 Set Vref Range= 32 -> 127
3347 23:56:34.141985
3348 23:56:34.142040 RX Vref 32 -> 127, step: 1
3349 23:56:34.142095
3350 23:56:34.142148 RX Delay -5 -> 252, step: 4
3351 23:56:34.142210
3352 23:56:34.142266 Set Vref, RX VrefLevel [Byte0]: 32
3353 23:56:34.142320 [Byte1]: 32
3354 23:56:34.142373
3355 23:56:34.142430 Set Vref, RX VrefLevel [Byte0]: 33
3356 23:56:34.142489 [Byte1]: 33
3357 23:56:34.142545
3358 23:56:34.142600 Set Vref, RX VrefLevel [Byte0]: 34
3359 23:56:34.142653 [Byte1]: 34
3360 23:56:34.142715
3361 23:56:34.142770 Set Vref, RX VrefLevel [Byte0]: 35
3362 23:56:34.142824 [Byte1]: 35
3363 23:56:34.142876
3364 23:56:34.142934 Set Vref, RX VrefLevel [Byte0]: 36
3365 23:56:34.142991 [Byte1]: 36
3366 23:56:34.143048
3367 23:56:34.143102 Set Vref, RX VrefLevel [Byte0]: 37
3368 23:56:34.143155 [Byte1]: 37
3369 23:56:34.143216
3370 23:56:34.143272 Set Vref, RX VrefLevel [Byte0]: 38
3371 23:56:34.143325 [Byte1]: 38
3372 23:56:34.143378
3373 23:56:34.143435 Set Vref, RX VrefLevel [Byte0]: 39
3374 23:56:34.143494 [Byte1]: 39
3375 23:56:34.143550
3376 23:56:34.143604 Set Vref, RX VrefLevel [Byte0]: 40
3377 23:56:34.143656 [Byte1]: 40
3378 23:56:34.143718
3379 23:56:34.143774 Set Vref, RX VrefLevel [Byte0]: 41
3380 23:56:34.143826 [Byte1]: 41
3381 23:56:34.143879
3382 23:56:34.143936 Set Vref, RX VrefLevel [Byte0]: 42
3383 23:56:34.143995 [Byte1]: 42
3384 23:56:34.144051
3385 23:56:34.144105 Set Vref, RX VrefLevel [Byte0]: 43
3386 23:56:34.144187 [Byte1]: 43
3387 23:56:34.144280
3388 23:56:34.144389 Set Vref, RX VrefLevel [Byte0]: 44
3389 23:56:34.144484 [Byte1]: 44
3390 23:56:34.144573
3391 23:56:34.144675 Set Vref, RX VrefLevel [Byte0]: 45
3392 23:56:34.144747 [Byte1]: 45
3393 23:56:34.144805
3394 23:56:34.144858 Set Vref, RX VrefLevel [Byte0]: 46
3395 23:56:34.144915 [Byte1]: 46
3396 23:56:34.144973
3397 23:56:34.145029 Set Vref, RX VrefLevel [Byte0]: 47
3398 23:56:34.145083 [Byte1]: 47
3399 23:56:34.145135
3400 23:56:34.145193 Set Vref, RX VrefLevel [Byte0]: 48
3401 23:56:34.145251 [Byte1]: 48
3402 23:56:34.145342
3403 23:56:34.145397 Set Vref, RX VrefLevel [Byte0]: 49
3404 23:56:34.145462 [Byte1]: 49
3405 23:56:34.145519
3406 23:56:34.145573 Set Vref, RX VrefLevel [Byte0]: 50
3407 23:56:34.145626 [Byte1]: 50
3408 23:56:34.145684
3409 23:56:34.145742 Set Vref, RX VrefLevel [Byte0]: 51
3410 23:56:34.145799 [Byte1]: 51
3411 23:56:34.145852
3412 23:56:34.145904 Set Vref, RX VrefLevel [Byte0]: 52
3413 23:56:34.145966 [Byte1]: 52
3414 23:56:34.146022
3415 23:56:34.146076 Set Vref, RX VrefLevel [Byte0]: 53
3416 23:56:34.146129 [Byte1]: 53
3417 23:56:34.146186
3418 23:56:34.146244 Set Vref, RX VrefLevel [Byte0]: 54
3419 23:56:34.146300 [Byte1]: 54
3420 23:56:34.146353
3421 23:56:34.146404 Set Vref, RX VrefLevel [Byte0]: 55
3422 23:56:34.146467 [Byte1]: 55
3423 23:56:34.146524
3424 23:56:34.146578 Set Vref, RX VrefLevel [Byte0]: 56
3425 23:56:34.146630 [Byte1]: 56
3426 23:56:34.146687
3427 23:56:34.146745 Set Vref, RX VrefLevel [Byte0]: 57
3428 23:56:34.146802 [Byte1]: 57
3429 23:56:34.146854
3430 23:56:34.146906 Set Vref, RX VrefLevel [Byte0]: 58
3431 23:56:34.146969 [Byte1]: 58
3432 23:56:34.147024
3433 23:56:34.147078 Set Vref, RX VrefLevel [Byte0]: 59
3434 23:56:34.147131 [Byte1]: 59
3435 23:56:34.147188
3436 23:56:34.147246 Set Vref, RX VrefLevel [Byte0]: 60
3437 23:56:34.147494 [Byte1]: 60
3438 23:56:34.147556
3439 23:56:34.147611 Set Vref, RX VrefLevel [Byte0]: 61
3440 23:56:34.147670 [Byte1]: 61
3441 23:56:34.147728
3442 23:56:34.147790 Set Vref, RX VrefLevel [Byte0]: 62
3443 23:56:34.147864 [Byte1]: 62
3444 23:56:34.147943
3445 23:56:34.148003 Set Vref, RX VrefLevel [Byte0]: 63
3446 23:56:34.148061 [Byte1]: 63
3447 23:56:34.148116
3448 23:56:34.148188 Set Vref, RX VrefLevel [Byte0]: 64
3449 23:56:34.148245 [Byte1]: 64
3450 23:56:34.148301
3451 23:56:34.148380 Set Vref, RX VrefLevel [Byte0]: 65
3452 23:56:34.148461 [Byte1]: 65
3453 23:56:34.148517
3454 23:56:34.148572 Set Vref, RX VrefLevel [Byte0]: 66
3455 23:56:34.148652 [Byte1]: 66
3456 23:56:34.148715
3457 23:56:34.148821 Set Vref, RX VrefLevel [Byte0]: 67
3458 23:56:34.148876 [Byte1]: 67
3459 23:56:34.148934
3460 23:56:34.149024 Set Vref, RX VrefLevel [Byte0]: 68
3461 23:56:34.149082 [Byte1]: 68
3462 23:56:34.149136
3463 23:56:34.149194 Final RX Vref Byte 0 = 53 to rank0
3464 23:56:34.149253 Final RX Vref Byte 1 = 48 to rank0
3465 23:56:34.149309 Final RX Vref Byte 0 = 53 to rank1
3466 23:56:34.149362 Final RX Vref Byte 1 = 48 to rank1==
3467 23:56:34.149420 Dram Type= 6, Freq= 0, CH_1, rank 0
3468 23:56:34.149478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 23:56:34.149535 ==
3470 23:56:34.149590 DQS Delay:
3471 23:56:34.149642 DQS0 = 0, DQS1 = 0
3472 23:56:34.149700 DQM Delay:
3473 23:56:34.149758 DQM0 = 120, DQM1 = 116
3474 23:56:34.149813 DQ Delay:
3475 23:56:34.149866 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3476 23:56:34.149923 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3477 23:56:34.149981 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3478 23:56:34.150037 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3479 23:56:34.150092
3480 23:56:34.150144
3481 23:56:34.150202 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3482 23:56:34.150264 CH1 RK0: MR19=304, MR18=FF12
3483 23:56:34.150317 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3484 23:56:34.150370
3485 23:56:34.150428 ----->DramcWriteLeveling(PI) begin...
3486 23:56:34.150489 ==
3487 23:56:34.150545 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 23:56:34.150599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 23:56:34.150651 ==
3490 23:56:34.150713 Write leveling (Byte 0): 27 => 27
3491 23:56:34.150800 Write leveling (Byte 1): 29 => 29
3492 23:56:34.150856 DramcWriteLeveling(PI) end<-----
3493 23:56:34.150909
3494 23:56:34.150973 ==
3495 23:56:34.151029 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 23:56:34.151085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 23:56:34.151138 ==
3498 23:56:34.151196 [Gating] SW mode calibration
3499 23:56:34.151254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3500 23:56:34.151311 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3501 23:56:34.151364 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 23:56:34.151423 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 23:56:34.151482 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 23:56:34.151538 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 23:56:34.151593 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 23:56:34.151646 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3507 23:56:34.151698 0 15 24 | B1->B0 | 2828 3131 | 0 0 | (0 1) (0 0)
3508 23:56:34.151761 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3509 23:56:34.151814 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 23:56:34.151867 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 23:56:34.151936 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 23:56:34.152011 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 23:56:34.152066 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 23:56:34.152121 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
3515 23:56:34.152173 1 0 24 | B1->B0 | 4545 3232 | 0 0 | (0 0) (0 0)
3516 23:56:34.152233 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 23:56:34.152289 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 23:56:34.152364 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 23:56:34.152432 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 23:56:34.152496 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 23:56:34.152551 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 23:56:34.152605 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 23:56:34.152658 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3524 23:56:34.152718 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3525 23:56:34.152806 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:56:34.152919 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:56:34.153012 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:56:34.153083 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:56:34.153136 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:56:34.153189 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:56:34.153251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:56:34.153305 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:56:34.153357 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:56:34.153424 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:56:34.153499 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:56:34.153569 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 23:56:34.153626 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:56:34.154249 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3539 23:56:34.161245 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3540 23:56:34.164129 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3541 23:56:34.167311 Total UI for P1: 0, mck2ui 16
3542 23:56:34.170876 best dqsien dly found for B1: ( 1, 3, 22)
3543 23:56:34.174356 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 23:56:34.177615 Total UI for P1: 0, mck2ui 16
3545 23:56:34.180891 best dqsien dly found for B0: ( 1, 3, 28)
3546 23:56:34.184107 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3547 23:56:34.187018 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3548 23:56:34.187164
3549 23:56:34.194184 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3550 23:56:34.197277 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3551 23:56:34.197360 [Gating] SW calibration Done
3552 23:56:34.200461 ==
3553 23:56:34.200543 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 23:56:34.207310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 23:56:34.207393 ==
3556 23:56:34.207458 RX Vref Scan: 0
3557 23:56:34.207521
3558 23:56:34.210674 RX Vref 0 -> 0, step: 1
3559 23:56:34.210755
3560 23:56:34.213968 RX Delay -40 -> 252, step: 8
3561 23:56:34.217393 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3562 23:56:34.220588 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3563 23:56:34.223579 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3564 23:56:34.230450 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3565 23:56:34.234026 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3566 23:56:34.237146 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3567 23:56:34.240547 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3568 23:56:34.243757 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3569 23:56:34.250758 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3570 23:56:34.253998 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3571 23:56:34.257060 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3572 23:56:34.260577 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3573 23:56:34.264441 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3574 23:56:34.270585 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3575 23:56:34.273514 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3576 23:56:34.277362 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3577 23:56:34.277454 ==
3578 23:56:34.280365 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 23:56:34.283555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 23:56:34.287322 ==
3581 23:56:34.287447 DQS Delay:
3582 23:56:34.287564 DQS0 = 0, DQS1 = 0
3583 23:56:34.290409 DQM Delay:
3584 23:56:34.290531 DQM0 = 119, DQM1 = 117
3585 23:56:34.293743 DQ Delay:
3586 23:56:34.297047 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3587 23:56:34.300953 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3588 23:56:34.303688 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3589 23:56:34.306921 DQ12 =127, DQ13 =123, DQ14 =123, DQ15 =123
3590 23:56:34.307042
3591 23:56:34.307157
3592 23:56:34.307265 ==
3593 23:56:34.310172 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 23:56:34.313236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 23:56:34.313361 ==
3596 23:56:34.313473
3597 23:56:34.317150
3598 23:56:34.317272 TX Vref Scan disable
3599 23:56:34.320007 == TX Byte 0 ==
3600 23:56:34.323444 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3601 23:56:34.326675 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3602 23:56:34.330300 == TX Byte 1 ==
3603 23:56:34.333486 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3604 23:56:34.336722 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3605 23:56:34.336805 ==
3606 23:56:34.340373 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 23:56:34.346475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 23:56:34.346602 ==
3609 23:56:34.357024 TX Vref=22, minBit 7, minWin=25, winSum=418
3610 23:56:34.360054 TX Vref=24, minBit 0, minWin=26, winSum=424
3611 23:56:34.363705 TX Vref=26, minBit 8, minWin=26, winSum=432
3612 23:56:34.366719 TX Vref=28, minBit 2, minWin=26, winSum=431
3613 23:56:34.370134 TX Vref=30, minBit 9, minWin=26, winSum=436
3614 23:56:34.373507 TX Vref=32, minBit 9, minWin=26, winSum=434
3615 23:56:34.380607 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3616 23:56:34.380716
3617 23:56:34.383747 Final TX Range 1 Vref 30
3618 23:56:34.383833
3619 23:56:34.383898 ==
3620 23:56:34.387127 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 23:56:34.390745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 23:56:34.390829 ==
3623 23:56:34.390893
3624 23:56:34.390953
3625 23:56:34.393797 TX Vref Scan disable
3626 23:56:34.397025 == TX Byte 0 ==
3627 23:56:34.400136 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3628 23:56:34.403762 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3629 23:56:34.406834 == TX Byte 1 ==
3630 23:56:34.410422 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3631 23:56:34.414108 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3632 23:56:34.414231
3633 23:56:34.417054 [DATLAT]
3634 23:56:34.417171 Freq=1200, CH1 RK1
3635 23:56:34.417282
3636 23:56:34.420278 DATLAT Default: 0xd
3637 23:56:34.420394 0, 0xFFFF, sum = 0
3638 23:56:34.424036 1, 0xFFFF, sum = 0
3639 23:56:34.424141 2, 0xFFFF, sum = 0
3640 23:56:34.426970 3, 0xFFFF, sum = 0
3641 23:56:34.427054 4, 0xFFFF, sum = 0
3642 23:56:34.430490 5, 0xFFFF, sum = 0
3643 23:56:34.430574 6, 0xFFFF, sum = 0
3644 23:56:34.433649 7, 0xFFFF, sum = 0
3645 23:56:34.433732 8, 0xFFFF, sum = 0
3646 23:56:34.436505 9, 0xFFFF, sum = 0
3647 23:56:34.440528 10, 0xFFFF, sum = 0
3648 23:56:34.440613 11, 0xFFFF, sum = 0
3649 23:56:34.443632 12, 0x0, sum = 1
3650 23:56:34.443715 13, 0x0, sum = 2
3651 23:56:34.446737 14, 0x0, sum = 3
3652 23:56:34.446821 15, 0x0, sum = 4
3653 23:56:34.446887 best_step = 13
3654 23:56:34.446948
3655 23:56:34.449840 ==
3656 23:56:34.453530 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 23:56:34.456530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 23:56:34.456613 ==
3659 23:56:34.456677 RX Vref Scan: 0
3660 23:56:34.456738
3661 23:56:34.460049 RX Vref 0 -> 0, step: 1
3662 23:56:34.460131
3663 23:56:34.463032 RX Delay -5 -> 252, step: 4
3664 23:56:34.466533 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3665 23:56:34.473657 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3666 23:56:34.476658 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3667 23:56:34.479985 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3668 23:56:34.483452 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3669 23:56:34.486581 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3670 23:56:34.493228 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3671 23:56:34.496705 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3672 23:56:34.499818 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3673 23:56:34.502987 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3674 23:56:34.506672 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3675 23:56:34.513032 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3676 23:56:34.516195 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3677 23:56:34.519897 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3678 23:56:34.522996 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3679 23:56:34.526531 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3680 23:56:34.530053 ==
3681 23:56:34.530175 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 23:56:34.536676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 23:56:34.536800 ==
3684 23:56:34.536911 DQS Delay:
3685 23:56:34.539703 DQS0 = 0, DQS1 = 0
3686 23:56:34.539821 DQM Delay:
3687 23:56:34.543472 DQM0 = 120, DQM1 = 116
3688 23:56:34.543592 DQ Delay:
3689 23:56:34.546345 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3690 23:56:34.549682 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3691 23:56:34.552934 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3692 23:56:34.556603 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3693 23:56:34.556725
3694 23:56:34.556835
3695 23:56:34.566452 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3696 23:56:34.566578 CH1 RK1: MR19=403, MR18=10ED
3697 23:56:34.572860 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3698 23:56:34.576105 [RxdqsGatingPostProcess] freq 1200
3699 23:56:34.582627 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3700 23:56:34.586188 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 23:56:34.589365 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 23:56:34.592688 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 23:56:34.596448 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 23:56:34.599689 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 23:56:34.602892 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 23:56:34.605947 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 23:56:34.609959 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 23:56:34.610043 Pre-setting of DQS Precalculation
3709 23:56:34.615913 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3710 23:56:34.622883 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3711 23:56:34.629092 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3712 23:56:34.629176
3713 23:56:34.629241
3714 23:56:34.632903 [Calibration Summary] 2400 Mbps
3715 23:56:34.635878 CH 0, Rank 0
3716 23:56:34.635960 SW Impedance : PASS
3717 23:56:34.639682 DUTY Scan : NO K
3718 23:56:34.642789 ZQ Calibration : PASS
3719 23:56:34.642872 Jitter Meter : NO K
3720 23:56:34.645982 CBT Training : PASS
3721 23:56:34.646065 Write leveling : PASS
3722 23:56:34.649587 RX DQS gating : PASS
3723 23:56:34.652857 RX DQ/DQS(RDDQC) : PASS
3724 23:56:34.652967 TX DQ/DQS : PASS
3725 23:56:34.656194 RX DATLAT : PASS
3726 23:56:34.659534 RX DQ/DQS(Engine): PASS
3727 23:56:34.659618 TX OE : NO K
3728 23:56:34.662759 All Pass.
3729 23:56:34.662842
3730 23:56:34.662908 CH 0, Rank 1
3731 23:56:34.666355 SW Impedance : PASS
3732 23:56:34.666438 DUTY Scan : NO K
3733 23:56:34.669396 ZQ Calibration : PASS
3734 23:56:34.672352 Jitter Meter : NO K
3735 23:56:34.672460 CBT Training : PASS
3736 23:56:34.676101 Write leveling : PASS
3737 23:56:34.679423 RX DQS gating : PASS
3738 23:56:34.679527 RX DQ/DQS(RDDQC) : PASS
3739 23:56:34.682479 TX DQ/DQS : PASS
3740 23:56:34.685968 RX DATLAT : PASS
3741 23:56:34.686054 RX DQ/DQS(Engine): PASS
3742 23:56:34.689375 TX OE : NO K
3743 23:56:34.689459 All Pass.
3744 23:56:34.689525
3745 23:56:34.692542 CH 1, Rank 0
3746 23:56:34.692625 SW Impedance : PASS
3747 23:56:34.695802 DUTY Scan : NO K
3748 23:56:34.698991 ZQ Calibration : PASS
3749 23:56:34.699074 Jitter Meter : NO K
3750 23:56:34.702165 CBT Training : PASS
3751 23:56:34.702279 Write leveling : PASS
3752 23:56:34.705621 RX DQS gating : PASS
3753 23:56:34.708970 RX DQ/DQS(RDDQC) : PASS
3754 23:56:34.709058 TX DQ/DQS : PASS
3755 23:56:34.712228 RX DATLAT : PASS
3756 23:56:34.715932 RX DQ/DQS(Engine): PASS
3757 23:56:34.716040 TX OE : NO K
3758 23:56:34.719310 All Pass.
3759 23:56:34.719388
3760 23:56:34.719457 CH 1, Rank 1
3761 23:56:34.722252 SW Impedance : PASS
3762 23:56:34.722336 DUTY Scan : NO K
3763 23:56:34.725615 ZQ Calibration : PASS
3764 23:56:34.729150 Jitter Meter : NO K
3765 23:56:34.729256 CBT Training : PASS
3766 23:56:34.732321 Write leveling : PASS
3767 23:56:34.735632 RX DQS gating : PASS
3768 23:56:34.735743 RX DQ/DQS(RDDQC) : PASS
3769 23:56:34.738884 TX DQ/DQS : PASS
3770 23:56:34.742354 RX DATLAT : PASS
3771 23:56:34.742461 RX DQ/DQS(Engine): PASS
3772 23:56:34.745564 TX OE : NO K
3773 23:56:34.745658 All Pass.
3774 23:56:34.745752
3775 23:56:34.748609 DramC Write-DBI off
3776 23:56:34.751888 PER_BANK_REFRESH: Hybrid Mode
3777 23:56:34.751974 TX_TRACKING: ON
3778 23:56:34.762155 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3779 23:56:34.765396 [FAST_K] Save calibration result to emmc
3780 23:56:34.768504 dramc_set_vcore_voltage set vcore to 650000
3781 23:56:34.772136 Read voltage for 600, 5
3782 23:56:34.772242 Vio18 = 0
3783 23:56:34.772345 Vcore = 650000
3784 23:56:34.775686 Vdram = 0
3785 23:56:34.775774 Vddq = 0
3786 23:56:34.775858 Vmddr = 0
3787 23:56:34.781907 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3788 23:56:34.785164 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3789 23:56:34.788890 MEM_TYPE=3, freq_sel=19
3790 23:56:34.792124 sv_algorithm_assistance_LP4_1600
3791 23:56:34.795384 ============ PULL DRAM RESETB DOWN ============
3792 23:56:34.798521 ========== PULL DRAM RESETB DOWN end =========
3793 23:56:34.805461 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3794 23:56:34.808357 ===================================
3795 23:56:34.808480 LPDDR4 DRAM CONFIGURATION
3796 23:56:34.811645 ===================================
3797 23:56:34.815449 EX_ROW_EN[0] = 0x0
3798 23:56:34.818681 EX_ROW_EN[1] = 0x0
3799 23:56:34.818807 LP4Y_EN = 0x0
3800 23:56:34.821909 WORK_FSP = 0x0
3801 23:56:34.822037 WL = 0x2
3802 23:56:34.825262 RL = 0x2
3803 23:56:34.825382 BL = 0x2
3804 23:56:34.828432 RPST = 0x0
3805 23:56:34.828553 RD_PRE = 0x0
3806 23:56:34.831781 WR_PRE = 0x1
3807 23:56:34.831903 WR_PST = 0x0
3808 23:56:34.835402 DBI_WR = 0x0
3809 23:56:34.835523 DBI_RD = 0x0
3810 23:56:34.838451 OTF = 0x1
3811 23:56:34.841600 ===================================
3812 23:56:34.845308 ===================================
3813 23:56:34.845430 ANA top config
3814 23:56:34.848239 ===================================
3815 23:56:34.851516 DLL_ASYNC_EN = 0
3816 23:56:34.855362 ALL_SLAVE_EN = 1
3817 23:56:34.858505 NEW_RANK_MODE = 1
3818 23:56:34.858626 DLL_IDLE_MODE = 1
3819 23:56:34.861768 LP45_APHY_COMB_EN = 1
3820 23:56:34.864915 TX_ODT_DIS = 1
3821 23:56:34.868610 NEW_8X_MODE = 1
3822 23:56:34.871826 ===================================
3823 23:56:34.874994 ===================================
3824 23:56:34.878129 data_rate = 1200
3825 23:56:34.878242 CKR = 1
3826 23:56:34.881466 DQ_P2S_RATIO = 8
3827 23:56:34.884637 ===================================
3828 23:56:34.888412 CA_P2S_RATIO = 8
3829 23:56:34.891291 DQ_CA_OPEN = 0
3830 23:56:34.894893 DQ_SEMI_OPEN = 0
3831 23:56:34.898180 CA_SEMI_OPEN = 0
3832 23:56:34.898254 CA_FULL_RATE = 0
3833 23:56:34.901382 DQ_CKDIV4_EN = 1
3834 23:56:34.904723 CA_CKDIV4_EN = 1
3835 23:56:34.908508 CA_PREDIV_EN = 0
3836 23:56:34.911309 PH8_DLY = 0
3837 23:56:34.914667 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3838 23:56:34.914776 DQ_AAMCK_DIV = 4
3839 23:56:34.918205 CA_AAMCK_DIV = 4
3840 23:56:34.921366 CA_ADMCK_DIV = 4
3841 23:56:34.924797 DQ_TRACK_CA_EN = 0
3842 23:56:34.927927 CA_PICK = 600
3843 23:56:34.931417 CA_MCKIO = 600
3844 23:56:34.931528 MCKIO_SEMI = 0
3845 23:56:34.934462 PLL_FREQ = 2288
3846 23:56:34.937948 DQ_UI_PI_RATIO = 32
3847 23:56:34.941424 CA_UI_PI_RATIO = 0
3848 23:56:34.944552 ===================================
3849 23:56:34.947665 ===================================
3850 23:56:34.951084 memory_type:LPDDR4
3851 23:56:34.951193 GP_NUM : 10
3852 23:56:34.954828 SRAM_EN : 1
3853 23:56:34.958029 MD32_EN : 0
3854 23:56:34.961271 ===================================
3855 23:56:34.961383 [ANA_INIT] >>>>>>>>>>>>>>
3856 23:56:34.964323 <<<<<< [CONFIGURE PHASE]: ANA_TX
3857 23:56:34.967584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3858 23:56:34.971317 ===================================
3859 23:56:34.974608 data_rate = 1200,PCW = 0X5800
3860 23:56:34.977735 ===================================
3861 23:56:34.980814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3862 23:56:34.987313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 23:56:34.990913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 23:56:34.997209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3865 23:56:35.001053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3866 23:56:35.004151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3867 23:56:35.004230 [ANA_INIT] flow start
3868 23:56:35.007175 [ANA_INIT] PLL >>>>>>>>
3869 23:56:35.011158 [ANA_INIT] PLL <<<<<<<<
3870 23:56:35.014361 [ANA_INIT] MIDPI >>>>>>>>
3871 23:56:35.014452 [ANA_INIT] MIDPI <<<<<<<<
3872 23:56:35.017384 [ANA_INIT] DLL >>>>>>>>
3873 23:56:35.020784 [ANA_INIT] flow end
3874 23:56:35.024099 ============ LP4 DIFF to SE enter ============
3875 23:56:35.027232 ============ LP4 DIFF to SE exit ============
3876 23:56:35.030932 [ANA_INIT] <<<<<<<<<<<<<
3877 23:56:35.034088 [Flow] Enable top DCM control >>>>>
3878 23:56:35.037812 [Flow] Enable top DCM control <<<<<
3879 23:56:35.040604 Enable DLL master slave shuffle
3880 23:56:35.044037 ==============================================================
3881 23:56:35.047301 Gating Mode config
3882 23:56:35.050865 ==============================================================
3883 23:56:35.053949 Config description:
3884 23:56:35.064092 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3885 23:56:35.070645 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3886 23:56:35.074184 SELPH_MODE 0: By rank 1: By Phase
3887 23:56:35.080353 ==============================================================
3888 23:56:35.084261 GAT_TRACK_EN = 1
3889 23:56:35.087401 RX_GATING_MODE = 2
3890 23:56:35.090673 RX_GATING_TRACK_MODE = 2
3891 23:56:35.093770 SELPH_MODE = 1
3892 23:56:35.097744 PICG_EARLY_EN = 1
3893 23:56:35.097827 VALID_LAT_VALUE = 1
3894 23:56:35.103905 ==============================================================
3895 23:56:35.107026 Enter into Gating configuration >>>>
3896 23:56:35.110836 Exit from Gating configuration <<<<
3897 23:56:35.113810 Enter into DVFS_PRE_config >>>>>
3898 23:56:35.123975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3899 23:56:35.127291 Exit from DVFS_PRE_config <<<<<
3900 23:56:35.130501 Enter into PICG configuration >>>>
3901 23:56:35.134085 Exit from PICG configuration <<<<
3902 23:56:35.137187 [RX_INPUT] configuration >>>>>
3903 23:56:35.140711 [RX_INPUT] configuration <<<<<
3904 23:56:35.143776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3905 23:56:35.150497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3906 23:56:35.157189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3907 23:56:35.163838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3908 23:56:35.170790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 23:56:35.174218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 23:56:35.180654 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3911 23:56:35.183926 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3912 23:56:35.187127 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3913 23:56:35.190577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3914 23:56:35.194426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3915 23:56:35.200500 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 23:56:35.203659 ===================================
3917 23:56:35.207387 LPDDR4 DRAM CONFIGURATION
3918 23:56:35.210580 ===================================
3919 23:56:35.210675 EX_ROW_EN[0] = 0x0
3920 23:56:35.213753 EX_ROW_EN[1] = 0x0
3921 23:56:35.213829 LP4Y_EN = 0x0
3922 23:56:35.217453 WORK_FSP = 0x0
3923 23:56:35.217543 WL = 0x2
3924 23:56:35.220559 RL = 0x2
3925 23:56:35.220635 BL = 0x2
3926 23:56:35.223857 RPST = 0x0
3927 23:56:35.223947 RD_PRE = 0x0
3928 23:56:35.227007 WR_PRE = 0x1
3929 23:56:35.227110 WR_PST = 0x0
3930 23:56:35.230945 DBI_WR = 0x0
3931 23:56:35.231025 DBI_RD = 0x0
3932 23:56:35.233940 OTF = 0x1
3933 23:56:35.237252 ===================================
3934 23:56:35.240579 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3935 23:56:35.244199 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3936 23:56:35.250630 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 23:56:35.254033 ===================================
3938 23:56:35.254110 LPDDR4 DRAM CONFIGURATION
3939 23:56:35.257020 ===================================
3940 23:56:35.260390 EX_ROW_EN[0] = 0x10
3941 23:56:35.263632 EX_ROW_EN[1] = 0x0
3942 23:56:35.263743 LP4Y_EN = 0x0
3943 23:56:35.267208 WORK_FSP = 0x0
3944 23:56:35.267307 WL = 0x2
3945 23:56:35.270669 RL = 0x2
3946 23:56:35.270776 BL = 0x2
3947 23:56:35.273854 RPST = 0x0
3948 23:56:35.273972 RD_PRE = 0x0
3949 23:56:35.276960 WR_PRE = 0x1
3950 23:56:35.277062 WR_PST = 0x0
3951 23:56:35.280212 DBI_WR = 0x0
3952 23:56:35.280337 DBI_RD = 0x0
3953 23:56:35.283776 OTF = 0x1
3954 23:56:35.287007 ===================================
3955 23:56:35.293240 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3956 23:56:35.296878 nWR fixed to 30
3957 23:56:35.300389 [ModeRegInit_LP4] CH0 RK0
3958 23:56:35.300487 [ModeRegInit_LP4] CH0 RK1
3959 23:56:35.303340 [ModeRegInit_LP4] CH1 RK0
3960 23:56:35.306814 [ModeRegInit_LP4] CH1 RK1
3961 23:56:35.306915 match AC timing 17
3962 23:56:35.313713 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3963 23:56:35.316824 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3964 23:56:35.319920 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3965 23:56:35.326691 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3966 23:56:35.329904 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3967 23:56:35.330009 ==
3968 23:56:35.333031 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 23:56:35.336267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 23:56:35.336360 ==
3971 23:56:35.343338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 23:56:35.349887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3973 23:56:35.353490 [CA 0] Center 35 (5~66) winsize 62
3974 23:56:35.356543 [CA 1] Center 36 (5~67) winsize 63
3975 23:56:35.359641 [CA 2] Center 33 (3~64) winsize 62
3976 23:56:35.363442 [CA 3] Center 33 (2~64) winsize 63
3977 23:56:35.366701 [CA 4] Center 33 (2~64) winsize 63
3978 23:56:35.369662 [CA 5] Center 32 (2~63) winsize 62
3979 23:56:35.369757
3980 23:56:35.373354 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3981 23:56:35.373441
3982 23:56:35.376680 [CATrainingPosCal] consider 1 rank data
3983 23:56:35.379663 u2DelayCellTimex100 = 270/100 ps
3984 23:56:35.383163 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3985 23:56:35.386110 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3986 23:56:35.389819 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3987 23:56:35.392910 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 23:56:35.396111 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3989 23:56:35.402761 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3990 23:56:35.402847
3991 23:56:35.406510 CA PerBit enable=1, Macro0, CA PI delay=32
3992 23:56:35.406599
3993 23:56:35.409779 [CBTSetCACLKResult] CA Dly = 32
3994 23:56:35.409879 CS Dly: 3 (0~34)
3995 23:56:35.409969 ==
3996 23:56:35.412686 Dram Type= 6, Freq= 0, CH_0, rank 1
3997 23:56:35.416262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 23:56:35.419278 ==
3999 23:56:35.422865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4000 23:56:35.429367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4001 23:56:35.432716 [CA 0] Center 35 (5~66) winsize 62
4002 23:56:35.436305 [CA 1] Center 35 (5~66) winsize 62
4003 23:56:35.439522 [CA 2] Center 33 (3~64) winsize 62
4004 23:56:35.442671 [CA 3] Center 33 (2~64) winsize 63
4005 23:56:35.446100 [CA 4] Center 33 (2~64) winsize 63
4006 23:56:35.449165 [CA 5] Center 32 (2~63) winsize 62
4007 23:56:35.449240
4008 23:56:35.452381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4009 23:56:35.452460
4010 23:56:35.455912 [CATrainingPosCal] consider 2 rank data
4011 23:56:35.459664 u2DelayCellTimex100 = 270/100 ps
4012 23:56:35.462553 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 23:56:35.465708 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4014 23:56:35.468945 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 23:56:35.472706 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
4016 23:56:35.479177 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4017 23:56:35.482867 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4018 23:56:35.482957
4019 23:56:35.485966 CA PerBit enable=1, Macro0, CA PI delay=32
4020 23:56:35.486042
4021 23:56:35.489420 [CBTSetCACLKResult] CA Dly = 32
4022 23:56:35.489527 CS Dly: 4 (0~36)
4023 23:56:35.489626
4024 23:56:35.492504 ----->DramcWriteLeveling(PI) begin...
4025 23:56:35.492588 ==
4026 23:56:35.495471 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 23:56:35.502229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 23:56:35.502313 ==
4029 23:56:35.505796 Write leveling (Byte 0): 34 => 34
4030 23:56:35.508906 Write leveling (Byte 1): 30 => 30
4031 23:56:35.508997 DramcWriteLeveling(PI) end<-----
4032 23:56:35.509072
4033 23:56:35.512045 ==
4034 23:56:35.515818 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 23:56:35.519222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 23:56:35.519302 ==
4037 23:56:35.522168 [Gating] SW mode calibration
4038 23:56:35.529296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4039 23:56:35.532664 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4040 23:56:35.538906 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 23:56:35.542450 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 23:56:35.545230 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4043 23:56:35.552330 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
4044 23:56:35.555417 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (1 0)
4045 23:56:35.558916 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 23:56:35.565639 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 23:56:35.568647 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 23:56:35.572539 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 23:56:35.579070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 23:56:35.582013 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 23:56:35.585894 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4052 23:56:35.589287 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4053 23:56:35.595275 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 23:56:35.598947 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 23:56:35.602126 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 23:56:35.609168 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 23:56:35.612438 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 23:56:35.615373 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 23:56:35.622252 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4060 23:56:35.625779 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4061 23:56:35.628918 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:56:35.635346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:56:35.639054 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:56:35.642087 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:56:35.648311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:56:35.652121 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:56:35.655201 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:56:35.661657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:56:35.665125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:56:35.668278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:56:35.675504 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:56:35.678454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:56:35.681944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:56:35.688450 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:56:35.691780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4076 23:56:35.695402 Total UI for P1: 0, mck2ui 16
4077 23:56:35.698523 best dqsien dly found for B0: ( 0, 13, 10)
4078 23:56:35.701645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 23:56:35.704900 Total UI for P1: 0, mck2ui 16
4080 23:56:35.708665 best dqsien dly found for B1: ( 0, 13, 14)
4081 23:56:35.711811 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4082 23:56:35.714865 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4083 23:56:35.714964
4084 23:56:35.721962 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4085 23:56:35.725303 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4086 23:56:35.725382 [Gating] SW calibration Done
4087 23:56:35.728218 ==
4088 23:56:35.728319 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 23:56:35.735099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 23:56:35.735173 ==
4091 23:56:35.735239 RX Vref Scan: 0
4092 23:56:35.735298
4093 23:56:35.738904 RX Vref 0 -> 0, step: 1
4094 23:56:35.738988
4095 23:56:35.741828 RX Delay -230 -> 252, step: 16
4096 23:56:35.745046 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4097 23:56:35.748295 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4098 23:56:35.754609 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4099 23:56:35.758415 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4100 23:56:35.761569 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4101 23:56:35.764689 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4102 23:56:35.768510 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4103 23:56:35.775122 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4104 23:56:35.778303 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4105 23:56:35.781688 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4106 23:56:35.785122 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4107 23:56:35.791453 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4108 23:56:35.794643 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4109 23:56:35.798209 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4110 23:56:35.801465 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4111 23:56:35.807947 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4112 23:56:35.808026 ==
4113 23:56:35.811552 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 23:56:35.814556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 23:56:35.814730 ==
4116 23:56:35.814827 DQS Delay:
4117 23:56:35.818208 DQS0 = 0, DQS1 = 0
4118 23:56:35.818314 DQM Delay:
4119 23:56:35.821509 DQM0 = 49, DQM1 = 44
4120 23:56:35.821587 DQ Delay:
4121 23:56:35.824895 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4122 23:56:35.828011 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4123 23:56:35.831198 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4124 23:56:35.834378 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4125 23:56:35.834451
4126 23:56:35.834517
4127 23:56:35.834574 ==
4128 23:56:35.837576 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 23:56:35.841404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 23:56:35.841496 ==
4131 23:56:35.841558
4132 23:56:35.844326
4133 23:56:35.844442 TX Vref Scan disable
4134 23:56:35.847727 == TX Byte 0 ==
4135 23:56:35.851155 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4136 23:56:35.854232 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4137 23:56:35.858016 == TX Byte 1 ==
4138 23:56:35.861276 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4139 23:56:35.865000 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4140 23:56:35.865074 ==
4141 23:56:35.868117 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 23:56:35.874623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 23:56:35.874700 ==
4144 23:56:35.874763
4145 23:56:35.874822
4146 23:56:35.874882 TX Vref Scan disable
4147 23:56:35.878949 == TX Byte 0 ==
4148 23:56:35.882510 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4149 23:56:35.885784 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4150 23:56:35.889238 == TX Byte 1 ==
4151 23:56:35.892509 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4152 23:56:35.895946 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4153 23:56:35.899066
4154 23:56:35.899156 [DATLAT]
4155 23:56:35.899260 Freq=600, CH0 RK0
4156 23:56:35.899337
4157 23:56:35.902560 DATLAT Default: 0x9
4158 23:56:35.902648 0, 0xFFFF, sum = 0
4159 23:56:35.905419 1, 0xFFFF, sum = 0
4160 23:56:35.905495 2, 0xFFFF, sum = 0
4161 23:56:35.909089 3, 0xFFFF, sum = 0
4162 23:56:35.909193 4, 0xFFFF, sum = 0
4163 23:56:35.912320 5, 0xFFFF, sum = 0
4164 23:56:35.915376 6, 0xFFFF, sum = 0
4165 23:56:35.915478 7, 0xFFFF, sum = 0
4166 23:56:35.915575 8, 0x0, sum = 1
4167 23:56:35.918989 9, 0x0, sum = 2
4168 23:56:35.919068 10, 0x0, sum = 3
4169 23:56:35.922603 11, 0x0, sum = 4
4170 23:56:35.922682 best_step = 9
4171 23:56:35.922748
4172 23:56:35.922807 ==
4173 23:56:35.925927 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 23:56:35.932143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 23:56:35.932238 ==
4176 23:56:35.932308 RX Vref Scan: 1
4177 23:56:35.932395
4178 23:56:35.935737 RX Vref 0 -> 0, step: 1
4179 23:56:35.935822
4180 23:56:35.939231 RX Delay -179 -> 252, step: 8
4181 23:56:35.939315
4182 23:56:35.942491 Set Vref, RX VrefLevel [Byte0]: 55
4183 23:56:35.946026 [Byte1]: 49
4184 23:56:35.946109
4185 23:56:35.948826 Final RX Vref Byte 0 = 55 to rank0
4186 23:56:35.952047 Final RX Vref Byte 1 = 49 to rank0
4187 23:56:35.955266 Final RX Vref Byte 0 = 55 to rank1
4188 23:56:35.958501 Final RX Vref Byte 1 = 49 to rank1==
4189 23:56:35.962248 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 23:56:35.965314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 23:56:35.965400 ==
4192 23:56:35.969064 DQS Delay:
4193 23:56:35.969147 DQS0 = 0, DQS1 = 0
4194 23:56:35.969213 DQM Delay:
4195 23:56:35.972330 DQM0 = 53, DQM1 = 46
4196 23:56:35.972423 DQ Delay:
4197 23:56:35.975280 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4198 23:56:35.978970 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =64
4199 23:56:35.982198 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4200 23:56:35.985300 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4201 23:56:35.985380
4202 23:56:35.985445
4203 23:56:35.995558 [DQSOSCAuto] RK0, (LSB)MR18= 0x7569, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4204 23:56:35.998552 CH0 RK0: MR19=808, MR18=7569
4205 23:56:36.001860 CH0_RK0: MR19=0x808, MR18=0x7569, DQSOSC=387, MR23=63, INC=175, DEC=116
4206 23:56:36.005064
4207 23:56:36.008684 ----->DramcWriteLeveling(PI) begin...
4208 23:56:36.008789 ==
4209 23:56:36.011756 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 23:56:36.014929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 23:56:36.015008 ==
4212 23:56:36.018699 Write leveling (Byte 0): 33 => 33
4213 23:56:36.021874 Write leveling (Byte 1): 32 => 32
4214 23:56:36.025091 DramcWriteLeveling(PI) end<-----
4215 23:56:36.025170
4216 23:56:36.025235 ==
4217 23:56:36.028240 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 23:56:36.032135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 23:56:36.032239 ==
4220 23:56:36.035070 [Gating] SW mode calibration
4221 23:56:36.041699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 23:56:36.048506 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 23:56:36.051468 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 23:56:36.054505 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 23:56:36.062052 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 23:56:36.064928 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
4227 23:56:36.068068 0 9 16 | B1->B0 | 2b2b 2424 | 1 0 | (0 0) (1 0)
4228 23:56:36.074370 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 23:56:36.078692 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 23:56:36.081524 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 23:56:36.087898 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 23:56:36.091731 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 23:56:36.094711 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 23:56:36.097919 0 10 12 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
4235 23:56:36.104807 0 10 16 | B1->B0 | 3e3e 4141 | 1 1 | (0 0) (0 0)
4236 23:56:36.108060 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:56:36.111039 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 23:56:36.117628 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 23:56:36.121254 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 23:56:36.124588 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 23:56:36.130833 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 23:56:36.134853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 23:56:36.137602 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:56:36.144708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:56:36.147759 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:56:36.150889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:56:36.157652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:56:36.161512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:56:36.164185 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:56:36.171116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:56:36.174272 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:56:36.177502 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:56:36.184518 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:56:36.187495 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:56:36.190806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:56:36.197906 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:56:36.201069 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:56:36.204125 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4259 23:56:36.211199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4260 23:56:36.211305 Total UI for P1: 0, mck2ui 16
4261 23:56:36.217499 best dqsien dly found for B0: ( 0, 13, 12)
4262 23:56:36.220721 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 23:56:36.224606 Total UI for P1: 0, mck2ui 16
4264 23:56:36.227397 best dqsien dly found for B1: ( 0, 13, 16)
4265 23:56:36.230660 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4266 23:56:36.234072 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4267 23:56:36.234154
4268 23:56:36.237608 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4269 23:56:36.240689 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4270 23:56:36.243958 [Gating] SW calibration Done
4271 23:56:36.244042 ==
4272 23:56:36.247340 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 23:56:36.250742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 23:56:36.253969 ==
4275 23:56:36.254046 RX Vref Scan: 0
4276 23:56:36.254108
4277 23:56:36.257284 RX Vref 0 -> 0, step: 1
4278 23:56:36.257358
4279 23:56:36.260546 RX Delay -230 -> 252, step: 16
4280 23:56:36.263605 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4281 23:56:36.267437 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4282 23:56:36.270537 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4283 23:56:36.273582 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4284 23:56:36.280453 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4285 23:56:36.283963 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4286 23:56:36.287086 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4287 23:56:36.290413 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4288 23:56:36.297274 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4289 23:56:36.300374 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4290 23:56:36.303606 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4291 23:56:36.306967 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4292 23:56:36.310669 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4293 23:56:36.317285 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4294 23:56:36.320529 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4295 23:56:36.323820 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4296 23:56:36.323896 ==
4297 23:56:36.327259 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 23:56:36.334066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 23:56:36.334146 ==
4300 23:56:36.334209 DQS Delay:
4301 23:56:36.334268 DQS0 = 0, DQS1 = 0
4302 23:56:36.337323 DQM Delay:
4303 23:56:36.337398 DQM0 = 53, DQM1 = 41
4304 23:56:36.340249 DQ Delay:
4305 23:56:36.343458 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4306 23:56:36.347326 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4307 23:56:36.347473 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4308 23:56:36.353717 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4309 23:56:36.353799
4310 23:56:36.353863
4311 23:56:36.353941 ==
4312 23:56:36.356984 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 23:56:36.360166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 23:56:36.360250 ==
4315 23:56:36.360317
4316 23:56:36.360389
4317 23:56:36.363268 TX Vref Scan disable
4318 23:56:36.363351 == TX Byte 0 ==
4319 23:56:36.370249 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4320 23:56:36.373481 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4321 23:56:36.373607 == TX Byte 1 ==
4322 23:56:36.380118 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4323 23:56:36.383396 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4324 23:56:36.383521 ==
4325 23:56:36.387006 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 23:56:36.390177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 23:56:36.390305 ==
4328 23:56:36.390421
4329 23:56:36.390532
4330 23:56:36.393291 TX Vref Scan disable
4331 23:56:36.397101 == TX Byte 0 ==
4332 23:56:36.400416 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4333 23:56:36.403488 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4334 23:56:36.406940 == TX Byte 1 ==
4335 23:56:36.410128 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4336 23:56:36.413389 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4337 23:56:36.413472
4338 23:56:36.416994 [DATLAT]
4339 23:56:36.417105 Freq=600, CH0 RK1
4340 23:56:36.417217
4341 23:56:36.420074 DATLAT Default: 0x9
4342 23:56:36.420157 0, 0xFFFF, sum = 0
4343 23:56:36.423090 1, 0xFFFF, sum = 0
4344 23:56:36.423218 2, 0xFFFF, sum = 0
4345 23:56:36.427009 3, 0xFFFF, sum = 0
4346 23:56:36.427094 4, 0xFFFF, sum = 0
4347 23:56:36.429894 5, 0xFFFF, sum = 0
4348 23:56:36.433310 6, 0xFFFF, sum = 0
4349 23:56:36.433425 7, 0xFFFF, sum = 0
4350 23:56:36.433522 8, 0x0, sum = 1
4351 23:56:36.436468 9, 0x0, sum = 2
4352 23:56:36.436586 10, 0x0, sum = 3
4353 23:56:36.440226 11, 0x0, sum = 4
4354 23:56:36.440327 best_step = 9
4355 23:56:36.440427
4356 23:56:36.440515 ==
4357 23:56:36.443460 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 23:56:36.450073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 23:56:36.450184 ==
4360 23:56:36.450278 RX Vref Scan: 0
4361 23:56:36.450367
4362 23:56:36.453558 RX Vref 0 -> 0, step: 1
4363 23:56:36.453686
4364 23:56:36.456336 RX Delay -179 -> 252, step: 8
4365 23:56:36.459802 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4366 23:56:36.463089 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4367 23:56:36.469877 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4368 23:56:36.473522 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4369 23:56:36.476823 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4370 23:56:36.479907 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4371 23:56:36.483421 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4372 23:56:36.489763 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4373 23:56:36.492909 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4374 23:56:36.496740 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4375 23:56:36.500172 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4376 23:56:36.506406 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4377 23:56:36.509608 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4378 23:56:36.513062 iDelay=197, Bit 13, Center 56 (-83 ~ 196) 280
4379 23:56:36.516083 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4380 23:56:36.519567 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4381 23:56:36.522889 ==
4382 23:56:36.522994 Dram Type= 6, Freq= 0, CH_0, rank 1
4383 23:56:36.530083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 23:56:36.530171 ==
4385 23:56:36.530238 DQS Delay:
4386 23:56:36.533287 DQS0 = 0, DQS1 = 0
4387 23:56:36.533370 DQM Delay:
4388 23:56:36.536404 DQM0 = 53, DQM1 = 46
4389 23:56:36.536512 DQ Delay:
4390 23:56:36.540061 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4391 23:56:36.543072 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4392 23:56:36.546338 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4393 23:56:36.549501 DQ12 =48, DQ13 =56, DQ14 =56, DQ15 =52
4394 23:56:36.549584
4395 23:56:36.549650
4396 23:56:36.556545 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4397 23:56:36.559537 CH0 RK1: MR19=808, MR18=6323
4398 23:56:36.566275 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4399 23:56:36.569450 [RxdqsGatingPostProcess] freq 600
4400 23:56:36.572751 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4401 23:56:36.576324 Pre-setting of DQS Precalculation
4402 23:56:36.582713 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4403 23:56:36.582794 ==
4404 23:56:36.586273 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 23:56:36.589650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 23:56:36.589732 ==
4407 23:56:36.596057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 23:56:36.603007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4409 23:56:36.606197 [CA 0] Center 35 (5~66) winsize 62
4410 23:56:36.609664 [CA 1] Center 35 (5~66) winsize 62
4411 23:56:36.613252 [CA 2] Center 34 (4~65) winsize 62
4412 23:56:36.616146 [CA 3] Center 34 (4~65) winsize 62
4413 23:56:36.619314 [CA 4] Center 34 (4~65) winsize 62
4414 23:56:36.623211 [CA 5] Center 33 (3~64) winsize 62
4415 23:56:36.623292
4416 23:56:36.626278 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4417 23:56:36.626359
4418 23:56:36.629341 [CATrainingPosCal] consider 1 rank data
4419 23:56:36.632655 u2DelayCellTimex100 = 270/100 ps
4420 23:56:36.635903 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 23:56:36.639408 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 23:56:36.642915 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 23:56:36.645953 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 23:56:36.649396 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 23:56:36.653048 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 23:56:36.653170
4427 23:56:36.656198 CA PerBit enable=1, Macro0, CA PI delay=33
4428 23:56:36.659394
4429 23:56:36.659476 [CBTSetCACLKResult] CA Dly = 33
4430 23:56:36.662373 CS Dly: 6 (0~37)
4431 23:56:36.662459 ==
4432 23:56:36.665823 Dram Type= 6, Freq= 0, CH_1, rank 1
4433 23:56:36.669309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 23:56:36.669392 ==
4435 23:56:36.676179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 23:56:36.682489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4437 23:56:36.685879 [CA 0] Center 36 (5~67) winsize 63
4438 23:56:36.689589 [CA 1] Center 36 (5~67) winsize 63
4439 23:56:36.692741 [CA 2] Center 34 (4~65) winsize 62
4440 23:56:36.695707 [CA 3] Center 34 (3~65) winsize 63
4441 23:56:36.699024 [CA 4] Center 35 (4~66) winsize 63
4442 23:56:36.702635 [CA 5] Center 34 (3~65) winsize 63
4443 23:56:36.702744
4444 23:56:36.705739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4445 23:56:36.705822
4446 23:56:36.709468 [CATrainingPosCal] consider 2 rank data
4447 23:56:36.712634 u2DelayCellTimex100 = 270/100 ps
4448 23:56:36.716148 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4449 23:56:36.719322 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4450 23:56:36.722788 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 23:56:36.726171 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4452 23:56:36.729126 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 23:56:36.732315 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 23:56:36.732412
4455 23:56:36.739339 CA PerBit enable=1, Macro0, CA PI delay=33
4456 23:56:36.739449
4457 23:56:36.742320 [CBTSetCACLKResult] CA Dly = 33
4458 23:56:36.742420 CS Dly: 7 (0~39)
4459 23:56:36.742511
4460 23:56:36.746011 ----->DramcWriteLeveling(PI) begin...
4461 23:56:36.746097 ==
4462 23:56:36.749690 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 23:56:36.752442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 23:56:36.752522 ==
4465 23:56:36.755738 Write leveling (Byte 0): 26 => 26
4466 23:56:36.759118 Write leveling (Byte 1): 32 => 32
4467 23:56:36.762051 DramcWriteLeveling(PI) end<-----
4468 23:56:36.762130
4469 23:56:36.762226 ==
4470 23:56:36.765891 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 23:56:36.772170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 23:56:36.772275 ==
4473 23:56:36.772371 [Gating] SW mode calibration
4474 23:56:36.782551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4475 23:56:36.785757 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4476 23:56:36.788894 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 23:56:36.795304 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 23:56:36.799137 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4479 23:56:36.802232 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
4480 23:56:36.809033 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4481 23:56:36.812518 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 23:56:36.815807 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 23:56:36.822660 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 23:56:36.825764 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 23:56:36.828997 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 23:56:36.835897 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 23:56:36.839351 0 10 12 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
4488 23:56:36.842607 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 23:56:36.848904 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 23:56:36.852219 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 23:56:36.855387 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 23:56:36.859204 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 23:56:36.865668 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 23:56:36.868964 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 23:56:36.872255 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:56:36.879097 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:56:36.882332 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:56:36.885757 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:56:36.892006 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:56:36.895288 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:56:36.899007 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:56:36.905332 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:56:36.909442 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:56:36.912240 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:56:36.918629 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:56:36.922104 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:56:36.925074 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:56:36.932108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:56:36.935348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:56:36.938604 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4511 23:56:36.945543 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4512 23:56:36.948667 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 23:56:36.951597 Total UI for P1: 0, mck2ui 16
4514 23:56:36.955417 best dqsien dly found for B0: ( 0, 13, 10)
4515 23:56:36.958739 Total UI for P1: 0, mck2ui 16
4516 23:56:36.961892 best dqsien dly found for B1: ( 0, 13, 12)
4517 23:56:36.965139 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4518 23:56:36.968278 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4519 23:56:36.968365
4520 23:56:36.972238 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4521 23:56:36.975231 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4522 23:56:36.978298 [Gating] SW calibration Done
4523 23:56:36.978381 ==
4524 23:56:36.981911 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 23:56:36.984991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 23:56:36.988310 ==
4527 23:56:36.988401 RX Vref Scan: 0
4528 23:56:36.988464
4529 23:56:36.992252 RX Vref 0 -> 0, step: 1
4530 23:56:36.992358
4531 23:56:36.992423 RX Delay -230 -> 252, step: 16
4532 23:56:36.998830 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4533 23:56:37.002351 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4534 23:56:37.005329 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4535 23:56:37.008749 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4536 23:56:37.015175 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4537 23:56:37.018927 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4538 23:56:37.022092 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4539 23:56:37.025202 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4540 23:56:37.028865 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4541 23:56:37.035678 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4542 23:56:37.038800 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4543 23:56:37.041932 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4544 23:56:37.046046 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4545 23:56:37.052376 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4546 23:56:37.055878 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4547 23:56:37.058937 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4548 23:56:37.059046 ==
4549 23:56:37.062045 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 23:56:37.065265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 23:56:37.068714 ==
4552 23:56:37.068818 DQS Delay:
4553 23:56:37.068918 DQS0 = 0, DQS1 = 0
4554 23:56:37.071836 DQM Delay:
4555 23:56:37.071939 DQM0 = 52, DQM1 = 49
4556 23:56:37.075137 DQ Delay:
4557 23:56:37.075217 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4558 23:56:37.078792 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4559 23:56:37.081733 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4560 23:56:37.085492 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4561 23:56:37.085594
4562 23:56:37.088605
4563 23:56:37.088702 ==
4564 23:56:37.091803 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 23:56:37.095250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 23:56:37.095350 ==
4567 23:56:37.095443
4568 23:56:37.095530
4569 23:56:37.098653 TX Vref Scan disable
4570 23:56:37.098725 == TX Byte 0 ==
4571 23:56:37.105601 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4572 23:56:37.108712 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4573 23:56:37.108790 == TX Byte 1 ==
4574 23:56:37.115415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4575 23:56:37.119125 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4576 23:56:37.119228 ==
4577 23:56:37.121597 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 23:56:37.125490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 23:56:37.125596 ==
4580 23:56:37.125691
4581 23:56:37.125780
4582 23:56:37.128754 TX Vref Scan disable
4583 23:56:37.131645 == TX Byte 0 ==
4584 23:56:37.135149 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4585 23:56:37.138254 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4586 23:56:37.141974 == TX Byte 1 ==
4587 23:56:37.145295 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4588 23:56:37.148454 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4589 23:56:37.148532
4590 23:56:37.151498 [DATLAT]
4591 23:56:37.151572 Freq=600, CH1 RK0
4592 23:56:37.151634
4593 23:56:37.155279 DATLAT Default: 0x9
4594 23:56:37.155378 0, 0xFFFF, sum = 0
4595 23:56:37.158320 1, 0xFFFF, sum = 0
4596 23:56:37.158395 2, 0xFFFF, sum = 0
4597 23:56:37.162035 3, 0xFFFF, sum = 0
4598 23:56:37.162135 4, 0xFFFF, sum = 0
4599 23:56:37.165092 5, 0xFFFF, sum = 0
4600 23:56:37.165171 6, 0xFFFF, sum = 0
4601 23:56:37.168111 7, 0xFFFF, sum = 0
4602 23:56:37.168213 8, 0x0, sum = 1
4603 23:56:37.171658 9, 0x0, sum = 2
4604 23:56:37.171744 10, 0x0, sum = 3
4605 23:56:37.174894 11, 0x0, sum = 4
4606 23:56:37.174979 best_step = 9
4607 23:56:37.175052
4608 23:56:37.175120 ==
4609 23:56:37.178357 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 23:56:37.185062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 23:56:37.185149 ==
4612 23:56:37.185215 RX Vref Scan: 1
4613 23:56:37.185277
4614 23:56:37.188279 RX Vref 0 -> 0, step: 1
4615 23:56:37.188391
4616 23:56:37.191651 RX Delay -147 -> 252, step: 8
4617 23:56:37.191735
4618 23:56:37.195310 Set Vref, RX VrefLevel [Byte0]: 53
4619 23:56:37.198591 [Byte1]: 48
4620 23:56:37.198675
4621 23:56:37.201676 Final RX Vref Byte 0 = 53 to rank0
4622 23:56:37.205182 Final RX Vref Byte 1 = 48 to rank0
4623 23:56:37.208015 Final RX Vref Byte 0 = 53 to rank1
4624 23:56:37.211535 Final RX Vref Byte 1 = 48 to rank1==
4625 23:56:37.215501 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 23:56:37.218374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 23:56:37.218485 ==
4628 23:56:37.221849 DQS Delay:
4629 23:56:37.221932 DQS0 = 0, DQS1 = 0
4630 23:56:37.221998 DQM Delay:
4631 23:56:37.225081 DQM0 = 48, DQM1 = 45
4632 23:56:37.225165 DQ Delay:
4633 23:56:37.228138 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4634 23:56:37.231758 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4635 23:56:37.234555 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4636 23:56:37.238040 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4637 23:56:37.238146
4638 23:56:37.238241
4639 23:56:37.248026 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4640 23:56:37.248133 CH1 RK0: MR19=808, MR18=4A70
4641 23:56:37.254957 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4642 23:56:37.255033
4643 23:56:37.258217 ----->DramcWriteLeveling(PI) begin...
4644 23:56:37.258287 ==
4645 23:56:37.261308 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 23:56:37.268244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 23:56:37.268324 ==
4648 23:56:37.271366 Write leveling (Byte 0): 31 => 31
4649 23:56:37.274529 Write leveling (Byte 1): 29 => 29
4650 23:56:37.274630 DramcWriteLeveling(PI) end<-----
4651 23:56:37.277984
4652 23:56:37.278084 ==
4653 23:56:37.281184 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 23:56:37.284769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 23:56:37.284872 ==
4656 23:56:37.287752 [Gating] SW mode calibration
4657 23:56:37.294330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4658 23:56:37.297881 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4659 23:56:37.304726 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 23:56:37.307862 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 23:56:37.311159 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 23:56:37.317665 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
4663 23:56:37.320847 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 23:56:37.324123 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 23:56:37.330852 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 23:56:37.334689 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 23:56:37.337794 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 23:56:37.344720 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 23:56:37.347678 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4670 23:56:37.350845 0 10 12 | B1->B0 | 3434 3737 | 1 0 | (0 0) (0 0)
4671 23:56:37.357998 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4672 23:56:37.361293 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 23:56:37.364274 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 23:56:37.371202 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 23:56:37.374396 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 23:56:37.377656 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 23:56:37.384649 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4678 23:56:37.387768 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4679 23:56:37.390855 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:56:37.394494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:56:37.400914 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:56:37.404337 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:56:37.407925 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:56:37.414558 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:56:37.417837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:56:37.420905 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:56:37.427743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:56:37.430942 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:56:37.434243 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:56:37.441171 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:56:37.444120 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:56:37.447493 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:56:37.453834 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:56:37.457377 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4695 23:56:37.460760 Total UI for P1: 0, mck2ui 16
4696 23:56:37.464037 best dqsien dly found for B1: ( 0, 13, 10)
4697 23:56:37.467368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 23:56:37.470790 Total UI for P1: 0, mck2ui 16
4699 23:56:37.474344 best dqsien dly found for B0: ( 0, 13, 12)
4700 23:56:37.477731 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4701 23:56:37.480841 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4702 23:56:37.483980
4703 23:56:37.487128 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4704 23:56:37.490210 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4705 23:56:37.494023 [Gating] SW calibration Done
4706 23:56:37.494104 ==
4707 23:56:37.496945 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 23:56:37.500933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 23:56:37.501011 ==
4710 23:56:37.501076 RX Vref Scan: 0
4711 23:56:37.501137
4712 23:56:37.503946 RX Vref 0 -> 0, step: 1
4713 23:56:37.504017
4714 23:56:37.507655 RX Delay -230 -> 252, step: 16
4715 23:56:37.510786 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4716 23:56:37.513853 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4717 23:56:37.520768 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4718 23:56:37.524548 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4719 23:56:37.527178 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4720 23:56:37.530394 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4721 23:56:37.534065 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4722 23:56:37.540244 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4723 23:56:37.543445 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4724 23:56:37.547244 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4725 23:56:37.550121 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4726 23:56:37.557138 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4727 23:56:37.560195 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4728 23:56:37.563786 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4729 23:56:37.567074 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4730 23:56:37.573974 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4731 23:56:37.574057 ==
4732 23:56:37.576761 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 23:56:37.580313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 23:56:37.580398 ==
4735 23:56:37.580465 DQS Delay:
4736 23:56:37.583840 DQS0 = 0, DQS1 = 0
4737 23:56:37.583912 DQM Delay:
4738 23:56:37.587027 DQM0 = 50, DQM1 = 47
4739 23:56:37.587100 DQ Delay:
4740 23:56:37.590230 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4741 23:56:37.593306 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4742 23:56:37.596530 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4743 23:56:37.600086 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4744 23:56:37.600172
4745 23:56:37.600239
4746 23:56:37.600300 ==
4747 23:56:37.603636 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 23:56:37.606846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 23:56:37.606929 ==
4750 23:56:37.610090
4751 23:56:37.610176
4752 23:56:37.610243 TX Vref Scan disable
4753 23:56:37.613276 == TX Byte 0 ==
4754 23:56:37.616933 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4755 23:56:37.619882 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4756 23:56:37.624007 == TX Byte 1 ==
4757 23:56:37.626920 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4758 23:56:37.630075 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4759 23:56:37.633501 ==
4760 23:56:37.633584 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 23:56:37.639920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 23:56:37.640009 ==
4763 23:56:37.640111
4764 23:56:37.640202
4765 23:56:37.643570 TX Vref Scan disable
4766 23:56:37.643653 == TX Byte 0 ==
4767 23:56:37.649882 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4768 23:56:37.652993 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4769 23:56:37.653076 == TX Byte 1 ==
4770 23:56:37.659991 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4771 23:56:37.663398 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4772 23:56:37.663482
4773 23:56:37.663547 [DATLAT]
4774 23:56:37.666598 Freq=600, CH1 RK1
4775 23:56:37.666682
4776 23:56:37.666748 DATLAT Default: 0x9
4777 23:56:37.669792 0, 0xFFFF, sum = 0
4778 23:56:37.669876 1, 0xFFFF, sum = 0
4779 23:56:37.672937 2, 0xFFFF, sum = 0
4780 23:56:37.673022 3, 0xFFFF, sum = 0
4781 23:56:37.676548 4, 0xFFFF, sum = 0
4782 23:56:37.676633 5, 0xFFFF, sum = 0
4783 23:56:37.679785 6, 0xFFFF, sum = 0
4784 23:56:37.683535 7, 0xFFFF, sum = 0
4785 23:56:37.683616 8, 0x0, sum = 1
4786 23:56:37.683703 9, 0x0, sum = 2
4787 23:56:37.686309 10, 0x0, sum = 3
4788 23:56:37.686410 11, 0x0, sum = 4
4789 23:56:37.689769 best_step = 9
4790 23:56:37.689881
4791 23:56:37.689973 ==
4792 23:56:37.693171 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 23:56:37.696236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 23:56:37.696353 ==
4795 23:56:37.699667 RX Vref Scan: 0
4796 23:56:37.699741
4797 23:56:37.699802 RX Vref 0 -> 0, step: 1
4798 23:56:37.699860
4799 23:56:37.702880 RX Delay -163 -> 252, step: 8
4800 23:56:37.709878 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4801 23:56:37.713199 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4802 23:56:37.716752 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4803 23:56:37.719785 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4804 23:56:37.723477 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4805 23:56:37.729729 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4806 23:56:37.733051 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4807 23:56:37.736427 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4808 23:56:37.739884 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4809 23:56:37.746429 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4810 23:56:37.749707 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4811 23:56:37.752800 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4812 23:56:37.756699 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4813 23:56:37.759874 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4814 23:56:37.766325 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4815 23:56:37.769596 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4816 23:56:37.769706 ==
4817 23:56:37.773373 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 23:56:37.775980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 23:56:37.776057 ==
4820 23:56:37.779525 DQS Delay:
4821 23:56:37.779602 DQS0 = 0, DQS1 = 0
4822 23:56:37.779665 DQM Delay:
4823 23:56:37.782882 DQM0 = 48, DQM1 = 45
4824 23:56:37.782957 DQ Delay:
4825 23:56:37.786718 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4826 23:56:37.789490 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4827 23:56:37.792697 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4828 23:56:37.795987 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4829 23:56:37.796068
4830 23:56:37.796150
4831 23:56:37.806381 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4832 23:56:37.809668 CH1 RK1: MR19=808, MR18=6C22
4833 23:56:37.812625 CH1_RK1: MR19=0x808, MR18=0x6C22, DQSOSC=389, MR23=63, INC=173, DEC=115
4834 23:56:37.816260 [RxdqsGatingPostProcess] freq 600
4835 23:56:37.822771 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4836 23:56:37.826380 Pre-setting of DQS Precalculation
4837 23:56:37.829523 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4838 23:56:37.839538 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4839 23:56:37.845722 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4840 23:56:37.845810
4841 23:56:37.845880
4842 23:56:37.849553 [Calibration Summary] 1200 Mbps
4843 23:56:37.849646 CH 0, Rank 0
4844 23:56:37.852555 SW Impedance : PASS
4845 23:56:37.852671 DUTY Scan : NO K
4846 23:56:37.855723 ZQ Calibration : PASS
4847 23:56:37.859488 Jitter Meter : NO K
4848 23:56:37.859570 CBT Training : PASS
4849 23:56:37.862727 Write leveling : PASS
4850 23:56:37.862804 RX DQS gating : PASS
4851 23:56:37.865828 RX DQ/DQS(RDDQC) : PASS
4852 23:56:37.869039 TX DQ/DQS : PASS
4853 23:56:37.869148 RX DATLAT : PASS
4854 23:56:37.872957 RX DQ/DQS(Engine): PASS
4855 23:56:37.875955 TX OE : NO K
4856 23:56:37.876033 All Pass.
4857 23:56:37.876101
4858 23:56:37.876161 CH 0, Rank 1
4859 23:56:37.879176 SW Impedance : PASS
4860 23:56:37.883134 DUTY Scan : NO K
4861 23:56:37.883212 ZQ Calibration : PASS
4862 23:56:37.886148 Jitter Meter : NO K
4863 23:56:37.888972 CBT Training : PASS
4864 23:56:37.889058 Write leveling : PASS
4865 23:56:37.892724 RX DQS gating : PASS
4866 23:56:37.896008 RX DQ/DQS(RDDQC) : PASS
4867 23:56:37.896095 TX DQ/DQS : PASS
4868 23:56:37.899048 RX DATLAT : PASS
4869 23:56:37.902096 RX DQ/DQS(Engine): PASS
4870 23:56:37.902208 TX OE : NO K
4871 23:56:37.905624 All Pass.
4872 23:56:37.905709
4873 23:56:37.905774 CH 1, Rank 0
4874 23:56:37.909010 SW Impedance : PASS
4875 23:56:37.909126 DUTY Scan : NO K
4876 23:56:37.912627 ZQ Calibration : PASS
4877 23:56:37.915627 Jitter Meter : NO K
4878 23:56:37.915733 CBT Training : PASS
4879 23:56:37.919205 Write leveling : PASS
4880 23:56:37.919309 RX DQS gating : PASS
4881 23:56:37.922106 RX DQ/DQS(RDDQC) : PASS
4882 23:56:37.925787 TX DQ/DQS : PASS
4883 23:56:37.925901 RX DATLAT : PASS
4884 23:56:37.929073 RX DQ/DQS(Engine): PASS
4885 23:56:37.932088 TX OE : NO K
4886 23:56:37.932190 All Pass.
4887 23:56:37.932284
4888 23:56:37.932394 CH 1, Rank 1
4889 23:56:37.935809 SW Impedance : PASS
4890 23:56:37.939056 DUTY Scan : NO K
4891 23:56:37.939159 ZQ Calibration : PASS
4892 23:56:37.942431 Jitter Meter : NO K
4893 23:56:37.946292 CBT Training : PASS
4894 23:56:37.946401 Write leveling : PASS
4895 23:56:37.949109 RX DQS gating : PASS
4896 23:56:37.952600 RX DQ/DQS(RDDQC) : PASS
4897 23:56:37.952684 TX DQ/DQS : PASS
4898 23:56:37.955695 RX DATLAT : PASS
4899 23:56:37.959203 RX DQ/DQS(Engine): PASS
4900 23:56:37.959287 TX OE : NO K
4901 23:56:37.959354 All Pass.
4902 23:56:37.962596
4903 23:56:37.962708 DramC Write-DBI off
4904 23:56:37.965213 PER_BANK_REFRESH: Hybrid Mode
4905 23:56:37.965323 TX_TRACKING: ON
4906 23:56:37.975502 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4907 23:56:37.978623 [FAST_K] Save calibration result to emmc
4908 23:56:37.982428 dramc_set_vcore_voltage set vcore to 662500
4909 23:56:37.985546 Read voltage for 933, 3
4910 23:56:37.985629 Vio18 = 0
4911 23:56:37.988780 Vcore = 662500
4912 23:56:37.988883 Vdram = 0
4913 23:56:37.988954 Vddq = 0
4914 23:56:37.989016 Vmddr = 0
4915 23:56:37.995604 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4916 23:56:38.001895 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4917 23:56:38.002002 MEM_TYPE=3, freq_sel=17
4918 23:56:38.005650 sv_algorithm_assistance_LP4_1600
4919 23:56:38.008781 ============ PULL DRAM RESETB DOWN ============
4920 23:56:38.015742 ========== PULL DRAM RESETB DOWN end =========
4921 23:56:38.018927 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4922 23:56:38.022106 ===================================
4923 23:56:38.025727 LPDDR4 DRAM CONFIGURATION
4924 23:56:38.028880 ===================================
4925 23:56:38.028967 EX_ROW_EN[0] = 0x0
4926 23:56:38.031977 EX_ROW_EN[1] = 0x0
4927 23:56:38.032062 LP4Y_EN = 0x0
4928 23:56:38.035285 WORK_FSP = 0x0
4929 23:56:38.035363 WL = 0x3
4930 23:56:38.038644 RL = 0x3
4931 23:56:38.038730 BL = 0x2
4932 23:56:38.041879 RPST = 0x0
4933 23:56:38.041988 RD_PRE = 0x0
4934 23:56:38.045680 WR_PRE = 0x1
4935 23:56:38.048992 WR_PST = 0x0
4936 23:56:38.049077 DBI_WR = 0x0
4937 23:56:38.052173 DBI_RD = 0x0
4938 23:56:38.052258 OTF = 0x1
4939 23:56:38.055174 ===================================
4940 23:56:38.058975 ===================================
4941 23:56:38.059062 ANA top config
4942 23:56:38.061997 ===================================
4943 23:56:38.065145 DLL_ASYNC_EN = 0
4944 23:56:38.068842 ALL_SLAVE_EN = 1
4945 23:56:38.072253 NEW_RANK_MODE = 1
4946 23:56:38.075796 DLL_IDLE_MODE = 1
4947 23:56:38.075878 LP45_APHY_COMB_EN = 1
4948 23:56:38.078608 TX_ODT_DIS = 1
4949 23:56:38.082275 NEW_8X_MODE = 1
4950 23:56:38.085533 ===================================
4951 23:56:38.088767 ===================================
4952 23:56:38.091870 data_rate = 1866
4953 23:56:38.095172 CKR = 1
4954 23:56:38.095256 DQ_P2S_RATIO = 8
4955 23:56:38.098798 ===================================
4956 23:56:38.102210 CA_P2S_RATIO = 8
4957 23:56:38.105668 DQ_CA_OPEN = 0
4958 23:56:38.108489 DQ_SEMI_OPEN = 0
4959 23:56:38.111721 CA_SEMI_OPEN = 0
4960 23:56:38.115493 CA_FULL_RATE = 0
4961 23:56:38.115570 DQ_CKDIV4_EN = 1
4962 23:56:38.118640 CA_CKDIV4_EN = 1
4963 23:56:38.121789 CA_PREDIV_EN = 0
4964 23:56:38.125057 PH8_DLY = 0
4965 23:56:38.128336 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4966 23:56:38.131574 DQ_AAMCK_DIV = 4
4967 23:56:38.131658 CA_AAMCK_DIV = 4
4968 23:56:38.135501 CA_ADMCK_DIV = 4
4969 23:56:38.138588 DQ_TRACK_CA_EN = 0
4970 23:56:38.141871 CA_PICK = 933
4971 23:56:38.145035 CA_MCKIO = 933
4972 23:56:38.148289 MCKIO_SEMI = 0
4973 23:56:38.148374 PLL_FREQ = 3732
4974 23:56:38.151896 DQ_UI_PI_RATIO = 32
4975 23:56:38.155063 CA_UI_PI_RATIO = 0
4976 23:56:38.158899 ===================================
4977 23:56:38.161743 ===================================
4978 23:56:38.165540 memory_type:LPDDR4
4979 23:56:38.168621 GP_NUM : 10
4980 23:56:38.168698 SRAM_EN : 1
4981 23:56:38.171656 MD32_EN : 0
4982 23:56:38.174926 ===================================
4983 23:56:38.175008 [ANA_INIT] >>>>>>>>>>>>>>
4984 23:56:38.178682 <<<<<< [CONFIGURE PHASE]: ANA_TX
4985 23:56:38.181734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4986 23:56:38.184804 ===================================
4987 23:56:38.188684 data_rate = 1866,PCW = 0X8f00
4988 23:56:38.192148 ===================================
4989 23:56:38.195026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4990 23:56:38.201690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 23:56:38.205139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 23:56:38.211815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4993 23:56:38.214753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4994 23:56:38.218131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4995 23:56:38.221841 [ANA_INIT] flow start
4996 23:56:38.221951 [ANA_INIT] PLL >>>>>>>>
4997 23:56:38.224940 [ANA_INIT] PLL <<<<<<<<
4998 23:56:38.228385 [ANA_INIT] MIDPI >>>>>>>>
4999 23:56:38.228491 [ANA_INIT] MIDPI <<<<<<<<
5000 23:56:38.231343 [ANA_INIT] DLL >>>>>>>>
5001 23:56:38.235057 [ANA_INIT] flow end
5002 23:56:38.238261 ============ LP4 DIFF to SE enter ============
5003 23:56:38.241684 ============ LP4 DIFF to SE exit ============
5004 23:56:38.244678 [ANA_INIT] <<<<<<<<<<<<<
5005 23:56:38.248543 [Flow] Enable top DCM control >>>>>
5006 23:56:38.251680 [Flow] Enable top DCM control <<<<<
5007 23:56:38.255223 Enable DLL master slave shuffle
5008 23:56:38.258074 ==============================================================
5009 23:56:38.261421 Gating Mode config
5010 23:56:38.265104 ==============================================================
5011 23:56:38.268146 Config description:
5012 23:56:38.278273 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5013 23:56:38.285082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5014 23:56:38.287831 SELPH_MODE 0: By rank 1: By Phase
5015 23:56:38.294677 ==============================================================
5016 23:56:38.298332 GAT_TRACK_EN = 1
5017 23:56:38.301584 RX_GATING_MODE = 2
5018 23:56:38.304767 RX_GATING_TRACK_MODE = 2
5019 23:56:38.308157 SELPH_MODE = 1
5020 23:56:38.311936 PICG_EARLY_EN = 1
5021 23:56:38.314510 VALID_LAT_VALUE = 1
5022 23:56:38.318011 ==============================================================
5023 23:56:38.321515 Enter into Gating configuration >>>>
5024 23:56:38.324906 Exit from Gating configuration <<<<
5025 23:56:38.327854 Enter into DVFS_PRE_config >>>>>
5026 23:56:38.337772 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5027 23:56:38.341033 Exit from DVFS_PRE_config <<<<<
5028 23:56:38.344800 Enter into PICG configuration >>>>
5029 23:56:38.347992 Exit from PICG configuration <<<<
5030 23:56:38.351163 [RX_INPUT] configuration >>>>>
5031 23:56:38.354334 [RX_INPUT] configuration <<<<<
5032 23:56:38.361423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5033 23:56:38.364616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5034 23:56:38.371592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5035 23:56:38.377786 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5036 23:56:38.384577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5037 23:56:38.391174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5038 23:56:38.394237 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5039 23:56:38.397360 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5040 23:56:38.401253 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5041 23:56:38.407770 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5042 23:56:38.410590 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5043 23:56:38.414238 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 23:56:38.417357 ===================================
5045 23:56:38.420538 LPDDR4 DRAM CONFIGURATION
5046 23:56:38.424376 ===================================
5047 23:56:38.424455 EX_ROW_EN[0] = 0x0
5048 23:56:38.427504 EX_ROW_EN[1] = 0x0
5049 23:56:38.430883 LP4Y_EN = 0x0
5050 23:56:38.430985 WORK_FSP = 0x0
5051 23:56:38.434219 WL = 0x3
5052 23:56:38.434325 RL = 0x3
5053 23:56:38.437213 BL = 0x2
5054 23:56:38.437298 RPST = 0x0
5055 23:56:38.440793 RD_PRE = 0x0
5056 23:56:38.440869 WR_PRE = 0x1
5057 23:56:38.443968 WR_PST = 0x0
5058 23:56:38.444073 DBI_WR = 0x0
5059 23:56:38.447127 DBI_RD = 0x0
5060 23:56:38.447200 OTF = 0x1
5061 23:56:38.450749 ===================================
5062 23:56:38.454009 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5063 23:56:38.460452 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5064 23:56:38.464203 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 23:56:38.467309 ===================================
5066 23:56:38.470401 LPDDR4 DRAM CONFIGURATION
5067 23:56:38.473834 ===================================
5068 23:56:38.473917 EX_ROW_EN[0] = 0x10
5069 23:56:38.477082 EX_ROW_EN[1] = 0x0
5070 23:56:38.477162 LP4Y_EN = 0x0
5071 23:56:38.480867 WORK_FSP = 0x0
5072 23:56:38.480994 WL = 0x3
5073 23:56:38.484067 RL = 0x3
5074 23:56:38.487202 BL = 0x2
5075 23:56:38.487276 RPST = 0x0
5076 23:56:38.490330 RD_PRE = 0x0
5077 23:56:38.490401 WR_PRE = 0x1
5078 23:56:38.494089 WR_PST = 0x0
5079 23:56:38.494185 DBI_WR = 0x0
5080 23:56:38.497500 DBI_RD = 0x0
5081 23:56:38.497583 OTF = 0x1
5082 23:56:38.500750 ===================================
5083 23:56:38.507511 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5084 23:56:38.511029 nWR fixed to 30
5085 23:56:38.514495 [ModeRegInit_LP4] CH0 RK0
5086 23:56:38.514576 [ModeRegInit_LP4] CH0 RK1
5087 23:56:38.517642 [ModeRegInit_LP4] CH1 RK0
5088 23:56:38.521062 [ModeRegInit_LP4] CH1 RK1
5089 23:56:38.521138 match AC timing 9
5090 23:56:38.527829 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5091 23:56:38.531210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5092 23:56:38.534482 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5093 23:56:38.541280 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5094 23:56:38.544278 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5095 23:56:38.544369 ==
5096 23:56:38.547722 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 23:56:38.551305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 23:56:38.551389 ==
5099 23:56:38.557546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 23:56:38.564225 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5101 23:56:38.567726 [CA 0] Center 37 (6~68) winsize 63
5102 23:56:38.571027 [CA 1] Center 37 (7~68) winsize 62
5103 23:56:38.573965 [CA 2] Center 34 (4~65) winsize 62
5104 23:56:38.577617 [CA 3] Center 34 (3~65) winsize 63
5105 23:56:38.581016 [CA 4] Center 33 (3~64) winsize 62
5106 23:56:38.584083 [CA 5] Center 32 (2~62) winsize 61
5107 23:56:38.584161
5108 23:56:38.588259 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5109 23:56:38.588330
5110 23:56:38.591019 [CATrainingPosCal] consider 1 rank data
5111 23:56:38.594135 u2DelayCellTimex100 = 270/100 ps
5112 23:56:38.597376 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5113 23:56:38.601154 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5114 23:56:38.604356 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5115 23:56:38.607541 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5116 23:56:38.610701 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5117 23:56:38.614569 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5118 23:56:38.614653
5119 23:56:38.620903 CA PerBit enable=1, Macro0, CA PI delay=32
5120 23:56:38.620986
5121 23:56:38.623797 [CBTSetCACLKResult] CA Dly = 32
5122 23:56:38.623908 CS Dly: 5 (0~36)
5123 23:56:38.624008 ==
5124 23:56:38.627507 Dram Type= 6, Freq= 0, CH_0, rank 1
5125 23:56:38.630583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 23:56:38.630693 ==
5127 23:56:38.637070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5128 23:56:38.643807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5129 23:56:38.647264 [CA 0] Center 37 (6~68) winsize 63
5130 23:56:38.650279 [CA 1] Center 37 (7~68) winsize 62
5131 23:56:38.653686 [CA 2] Center 34 (4~65) winsize 62
5132 23:56:38.657143 [CA 3] Center 34 (4~65) winsize 62
5133 23:56:38.660325 [CA 4] Center 33 (3~64) winsize 62
5134 23:56:38.663488 [CA 5] Center 32 (2~62) winsize 61
5135 23:56:38.663621
5136 23:56:38.667234 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5137 23:56:38.667383
5138 23:56:38.670477 [CATrainingPosCal] consider 2 rank data
5139 23:56:38.673973 u2DelayCellTimex100 = 270/100 ps
5140 23:56:38.677360 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5141 23:56:38.680272 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5142 23:56:38.684132 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5143 23:56:38.687330 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5144 23:56:38.693893 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5145 23:56:38.696852 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5146 23:56:38.696973
5147 23:56:38.700573 CA PerBit enable=1, Macro0, CA PI delay=32
5148 23:56:38.700672
5149 23:56:38.703850 [CBTSetCACLKResult] CA Dly = 32
5150 23:56:38.703953 CS Dly: 6 (0~38)
5151 23:56:38.704046
5152 23:56:38.707053 ----->DramcWriteLeveling(PI) begin...
5153 23:56:38.707171 ==
5154 23:56:38.710239 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 23:56:38.717059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 23:56:38.717186 ==
5157 23:56:38.720447 Write leveling (Byte 0): 32 => 32
5158 23:56:38.720573 Write leveling (Byte 1): 29 => 29
5159 23:56:38.723681 DramcWriteLeveling(PI) end<-----
5160 23:56:38.723800
5161 23:56:38.723938 ==
5162 23:56:38.727192 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 23:56:38.733681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 23:56:38.733807 ==
5165 23:56:38.736691 [Gating] SW mode calibration
5166 23:56:38.743581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5167 23:56:38.747100 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5168 23:56:38.753306 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5169 23:56:38.756792 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 23:56:38.760098 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 23:56:38.766997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 23:56:38.770123 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 23:56:38.773256 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 23:56:38.779851 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5175 23:56:38.783514 0 14 28 | B1->B0 | 3232 2626 | 1 0 | (1 1) (1 0)
5176 23:56:38.786459 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5177 23:56:38.792992 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 23:56:38.796565 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 23:56:38.800007 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 23:56:38.806384 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 23:56:38.809780 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 23:56:38.812996 0 15 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5183 23:56:38.819920 0 15 28 | B1->B0 | 2727 4242 | 0 1 | (0 0) (0 0)
5184 23:56:38.823082 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
5185 23:56:38.826258 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 23:56:38.829503 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 23:56:38.836232 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 23:56:38.839515 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 23:56:38.843324 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 23:56:38.849654 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 23:56:38.852771 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5192 23:56:38.856319 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5193 23:56:38.862598 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:56:38.866236 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:56:38.869177 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:56:38.876292 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:56:38.879646 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:56:38.882765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:56:38.889286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:56:38.892443 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:56:38.895976 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:56:38.902802 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:56:38.905856 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:56:38.909579 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:56:38.916181 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:56:38.918907 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5207 23:56:38.922419 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5208 23:56:38.929283 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5209 23:56:38.929414 Total UI for P1: 0, mck2ui 16
5210 23:56:38.935948 best dqsien dly found for B0: ( 1, 2, 26)
5211 23:56:38.939082 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 23:56:38.942283 Total UI for P1: 0, mck2ui 16
5213 23:56:38.946040 best dqsien dly found for B1: ( 1, 2, 30)
5214 23:56:38.949251 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5215 23:56:38.952347 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5216 23:56:38.952476
5217 23:56:38.955513 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5218 23:56:38.959277 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5219 23:56:38.962442 [Gating] SW calibration Done
5220 23:56:38.962571 ==
5221 23:56:38.965922 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 23:56:38.969122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 23:56:38.972266 ==
5224 23:56:38.972397 RX Vref Scan: 0
5225 23:56:38.972517
5226 23:56:38.975704 RX Vref 0 -> 0, step: 1
5227 23:56:38.975829
5228 23:56:38.975946 RX Delay -80 -> 252, step: 8
5229 23:56:38.982301 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5230 23:56:38.985673 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5231 23:56:38.988916 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5232 23:56:38.992628 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5233 23:56:38.995640 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5234 23:56:39.002611 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5235 23:56:39.005847 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5236 23:56:39.009013 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5237 23:56:39.012530 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5238 23:56:39.015576 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5239 23:56:39.018909 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5240 23:56:39.025654 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5241 23:56:39.029163 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5242 23:56:39.032082 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5243 23:56:39.035422 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5244 23:56:39.038998 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5245 23:56:39.039126 ==
5246 23:56:39.042448 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 23:56:39.049118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 23:56:39.049248 ==
5249 23:56:39.049369 DQS Delay:
5250 23:56:39.052356 DQS0 = 0, DQS1 = 0
5251 23:56:39.052484 DQM Delay:
5252 23:56:39.055513 DQM0 = 105, DQM1 = 96
5253 23:56:39.055637 DQ Delay:
5254 23:56:39.058767 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5255 23:56:39.061971 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5256 23:56:39.065795 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5257 23:56:39.068987 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5258 23:56:39.069071
5259 23:56:39.069137
5260 23:56:39.069210 ==
5261 23:56:39.072421 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 23:56:39.075654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 23:56:39.075738 ==
5264 23:56:39.079177
5265 23:56:39.079259
5266 23:56:39.079323 TX Vref Scan disable
5267 23:56:39.081980 == TX Byte 0 ==
5268 23:56:39.085854 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5269 23:56:39.089002 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5270 23:56:39.092052 == TX Byte 1 ==
5271 23:56:39.095601 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5272 23:56:39.098801 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5273 23:56:39.098902 ==
5274 23:56:39.101778 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 23:56:39.108616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 23:56:39.108696 ==
5277 23:56:39.108763
5278 23:56:39.108833
5279 23:56:39.111715 TX Vref Scan disable
5280 23:56:39.111822 == TX Byte 0 ==
5281 23:56:39.118796 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5282 23:56:39.121819 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5283 23:56:39.121927 == TX Byte 1 ==
5284 23:56:39.128615 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5285 23:56:39.131616 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5286 23:56:39.131730
5287 23:56:39.131833 [DATLAT]
5288 23:56:39.135336 Freq=933, CH0 RK0
5289 23:56:39.135446
5290 23:56:39.135544 DATLAT Default: 0xd
5291 23:56:39.138225 0, 0xFFFF, sum = 0
5292 23:56:39.138337 1, 0xFFFF, sum = 0
5293 23:56:39.142084 2, 0xFFFF, sum = 0
5294 23:56:39.142204 3, 0xFFFF, sum = 0
5295 23:56:39.145212 4, 0xFFFF, sum = 0
5296 23:56:39.145322 5, 0xFFFF, sum = 0
5297 23:56:39.148070 6, 0xFFFF, sum = 0
5298 23:56:39.148179 7, 0xFFFF, sum = 0
5299 23:56:39.151742 8, 0xFFFF, sum = 0
5300 23:56:39.151859 9, 0xFFFF, sum = 0
5301 23:56:39.154653 10, 0x0, sum = 1
5302 23:56:39.154765 11, 0x0, sum = 2
5303 23:56:39.158455 12, 0x0, sum = 3
5304 23:56:39.158571 13, 0x0, sum = 4
5305 23:56:39.161588 best_step = 11
5306 23:56:39.161688
5307 23:56:39.161793 ==
5308 23:56:39.164763 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 23:56:39.168132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 23:56:39.168252 ==
5311 23:56:39.171204 RX Vref Scan: 1
5312 23:56:39.171310
5313 23:56:39.171407 RX Vref 0 -> 0, step: 1
5314 23:56:39.171476
5315 23:56:39.174792 RX Delay -45 -> 252, step: 4
5316 23:56:39.174896
5317 23:56:39.177798 Set Vref, RX VrefLevel [Byte0]: 55
5318 23:56:39.180947 [Byte1]: 49
5319 23:56:39.185491
5320 23:56:39.185602 Final RX Vref Byte 0 = 55 to rank0
5321 23:56:39.188729 Final RX Vref Byte 1 = 49 to rank0
5322 23:56:39.192059 Final RX Vref Byte 0 = 55 to rank1
5323 23:56:39.195628 Final RX Vref Byte 1 = 49 to rank1==
5324 23:56:39.198918 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 23:56:39.205364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 23:56:39.205447 ==
5327 23:56:39.205513 DQS Delay:
5328 23:56:39.205572 DQS0 = 0, DQS1 = 0
5329 23:56:39.208581 DQM Delay:
5330 23:56:39.208687 DQM0 = 104, DQM1 = 95
5331 23:56:39.211956 DQ Delay:
5332 23:56:39.215425 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5333 23:56:39.218352 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5334 23:56:39.222018 DQ8 =86, DQ9 =86, DQ10 =98, DQ11 =90
5335 23:56:39.225329 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5336 23:56:39.225440
5337 23:56:39.225540
5338 23:56:39.231809 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5339 23:56:39.235059 CH0 RK0: MR19=505, MR18=2F26
5340 23:56:39.242366 CH0_RK0: MR19=0x505, MR18=0x2F26, DQSOSC=407, MR23=63, INC=65, DEC=43
5341 23:56:39.242479
5342 23:56:39.245021 ----->DramcWriteLeveling(PI) begin...
5343 23:56:39.245133 ==
5344 23:56:39.248447 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 23:56:39.251625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 23:56:39.251705 ==
5347 23:56:39.255280 Write leveling (Byte 0): 35 => 35
5348 23:56:39.258320 Write leveling (Byte 1): 29 => 29
5349 23:56:39.262177 DramcWriteLeveling(PI) end<-----
5350 23:56:39.262292
5351 23:56:39.262388 ==
5352 23:56:39.265153 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 23:56:39.272245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 23:56:39.272378 ==
5355 23:56:39.272474 [Gating] SW mode calibration
5356 23:56:39.282064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5357 23:56:39.285256 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5358 23:56:39.288520 0 14 0 | B1->B0 | 3434 3333 | 0 1 | (0 0) (0 0)
5359 23:56:39.295046 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 23:56:39.298231 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 23:56:39.301463 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 23:56:39.308440 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 23:56:39.311456 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 23:56:39.315057 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 23:56:39.321992 0 14 28 | B1->B0 | 2b2b 2b2b | 0 0 | (0 1) (0 1)
5366 23:56:39.325247 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (1 0)
5367 23:56:39.328086 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 23:56:39.334886 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 23:56:39.338007 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 23:56:39.341676 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 23:56:39.348453 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 23:56:39.351331 0 15 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5373 23:56:39.354822 0 15 28 | B1->B0 | 3e3e 3737 | 0 0 | (0 0) (0 0)
5374 23:56:39.361429 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5375 23:56:39.364784 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 23:56:39.367992 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 23:56:39.374832 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 23:56:39.378024 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 23:56:39.381334 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 23:56:39.388124 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 23:56:39.391174 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5382 23:56:39.394800 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:56:39.401194 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:56:39.404390 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:56:39.408078 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:56:39.414325 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:56:39.417938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:56:39.421085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:56:39.424820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:56:39.431202 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:56:39.434374 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:56:39.437892 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:56:39.444629 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:56:39.447761 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:56:39.451251 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:56:39.457984 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5397 23:56:39.460948 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5398 23:56:39.464612 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 23:56:39.467662 Total UI for P1: 0, mck2ui 16
5400 23:56:39.471292 best dqsien dly found for B0: ( 1, 2, 26)
5401 23:56:39.474309 Total UI for P1: 0, mck2ui 16
5402 23:56:39.477494 best dqsien dly found for B1: ( 1, 2, 30)
5403 23:56:39.480716 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5404 23:56:39.484344 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5405 23:56:39.484429
5406 23:56:39.490711 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5407 23:56:39.494147 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5408 23:56:39.497881 [Gating] SW calibration Done
5409 23:56:39.497963 ==
5410 23:56:39.500792 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 23:56:39.504631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 23:56:39.504714 ==
5413 23:56:39.504779 RX Vref Scan: 0
5414 23:56:39.504839
5415 23:56:39.507795 RX Vref 0 -> 0, step: 1
5416 23:56:39.507878
5417 23:56:39.510991 RX Delay -80 -> 252, step: 8
5418 23:56:39.514109 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5419 23:56:39.517248 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5420 23:56:39.524073 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5421 23:56:39.527803 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5422 23:56:39.530839 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5423 23:56:39.533954 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5424 23:56:39.537722 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5425 23:56:39.541092 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5426 23:56:39.547458 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5427 23:56:39.551147 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5428 23:56:39.554148 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5429 23:56:39.557539 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5430 23:56:39.560588 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5431 23:56:39.564463 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5432 23:56:39.570627 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5433 23:56:39.574329 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5434 23:56:39.574449 ==
5435 23:56:39.577441 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 23:56:39.580617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 23:56:39.580705 ==
5438 23:56:39.580773 DQS Delay:
5439 23:56:39.584244 DQS0 = 0, DQS1 = 0
5440 23:56:39.584360 DQM Delay:
5441 23:56:39.587281 DQM0 = 105, DQM1 = 93
5442 23:56:39.587367 DQ Delay:
5443 23:56:39.590533 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5444 23:56:39.594301 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5445 23:56:39.597053 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5446 23:56:39.600554 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5447 23:56:39.600644
5448 23:56:39.600711
5449 23:56:39.600774 ==
5450 23:56:39.604065 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 23:56:39.610716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 23:56:39.610831 ==
5453 23:56:39.610956
5454 23:56:39.611053
5455 23:56:39.611159 TX Vref Scan disable
5456 23:56:39.614416 == TX Byte 0 ==
5457 23:56:39.617755 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5458 23:56:39.621317 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5459 23:56:39.624819 == TX Byte 1 ==
5460 23:56:39.627708 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5461 23:56:39.631232 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5462 23:56:39.634283 ==
5463 23:56:39.637566 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 23:56:39.641298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 23:56:39.641387 ==
5466 23:56:39.641460
5467 23:56:39.641521
5468 23:56:39.644298 TX Vref Scan disable
5469 23:56:39.644392 == TX Byte 0 ==
5470 23:56:39.650850 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5471 23:56:39.654671 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5472 23:56:39.654757 == TX Byte 1 ==
5473 23:56:39.660797 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5474 23:56:39.664622 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5475 23:56:39.664708
5476 23:56:39.664776 [DATLAT]
5477 23:56:39.667944 Freq=933, CH0 RK1
5478 23:56:39.668075
5479 23:56:39.668170 DATLAT Default: 0xb
5480 23:56:39.671079 0, 0xFFFF, sum = 0
5481 23:56:39.671192 1, 0xFFFF, sum = 0
5482 23:56:39.674288 2, 0xFFFF, sum = 0
5483 23:56:39.674373 3, 0xFFFF, sum = 0
5484 23:56:39.677495 4, 0xFFFF, sum = 0
5485 23:56:39.677579 5, 0xFFFF, sum = 0
5486 23:56:39.680645 6, 0xFFFF, sum = 0
5487 23:56:39.684469 7, 0xFFFF, sum = 0
5488 23:56:39.684554 8, 0xFFFF, sum = 0
5489 23:56:39.687448 9, 0xFFFF, sum = 0
5490 23:56:39.687532 10, 0x0, sum = 1
5491 23:56:39.687600 11, 0x0, sum = 2
5492 23:56:39.691049 12, 0x0, sum = 3
5493 23:56:39.691134 13, 0x0, sum = 4
5494 23:56:39.694546 best_step = 11
5495 23:56:39.694629
5496 23:56:39.694695 ==
5497 23:56:39.697821 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 23:56:39.700611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 23:56:39.700709 ==
5500 23:56:39.703927 RX Vref Scan: 0
5501 23:56:39.704018
5502 23:56:39.704085 RX Vref 0 -> 0, step: 1
5503 23:56:39.707163
5504 23:56:39.707247 RX Delay -53 -> 252, step: 4
5505 23:56:39.714560 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5506 23:56:39.718327 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5507 23:56:39.721352 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5508 23:56:39.724830 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5509 23:56:39.727936 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5510 23:56:39.734683 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5511 23:56:39.738026 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5512 23:56:39.741133 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5513 23:56:39.744902 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5514 23:56:39.747663 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5515 23:56:39.754756 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5516 23:56:39.757882 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5517 23:56:39.761583 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5518 23:56:39.764599 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5519 23:56:39.767798 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5520 23:56:39.774148 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5521 23:56:39.774264 ==
5522 23:56:39.777501 Dram Type= 6, Freq= 0, CH_0, rank 1
5523 23:56:39.781085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 23:56:39.781164 ==
5525 23:56:39.781228 DQS Delay:
5526 23:56:39.784201 DQS0 = 0, DQS1 = 0
5527 23:56:39.784314 DQM Delay:
5528 23:56:39.787665 DQM0 = 104, DQM1 = 94
5529 23:56:39.787778 DQ Delay:
5530 23:56:39.790532 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5531 23:56:39.794067 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5532 23:56:39.797493 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =90
5533 23:56:39.800581 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5534 23:56:39.800698
5535 23:56:39.800796
5536 23:56:39.811039 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
5537 23:56:39.813698 CH0 RK1: MR19=505, MR18=2D07
5538 23:56:39.820931 CH0_RK1: MR19=0x505, MR18=0x2D07, DQSOSC=407, MR23=63, INC=65, DEC=43
5539 23:56:39.821019 [RxdqsGatingPostProcess] freq 933
5540 23:56:39.827221 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5541 23:56:39.831150 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 23:56:39.834053 best DQS1 dly(2T, 0.5T) = (0, 10)
5543 23:56:39.837120 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 23:56:39.840627 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5545 23:56:39.843736 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 23:56:39.847465 best DQS1 dly(2T, 0.5T) = (0, 10)
5547 23:56:39.850501 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 23:56:39.854038 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5549 23:56:39.857548 Pre-setting of DQS Precalculation
5550 23:56:39.860382 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5551 23:56:39.860489 ==
5552 23:56:39.863626 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 23:56:39.867204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 23:56:39.867310 ==
5555 23:56:39.873981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5556 23:56:39.880456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5557 23:56:39.883590 [CA 0] Center 36 (6~67) winsize 62
5558 23:56:39.887574 [CA 1] Center 36 (6~67) winsize 62
5559 23:56:39.890210 [CA 2] Center 34 (4~65) winsize 62
5560 23:56:39.893928 [CA 3] Center 34 (4~65) winsize 62
5561 23:56:39.897164 [CA 4] Center 34 (4~64) winsize 61
5562 23:56:39.900359 [CA 5] Center 33 (3~64) winsize 62
5563 23:56:39.900474
5564 23:56:39.903548 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5565 23:56:39.903634
5566 23:56:39.907358 [CATrainingPosCal] consider 1 rank data
5567 23:56:39.910219 u2DelayCellTimex100 = 270/100 ps
5568 23:56:39.913480 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 23:56:39.916679 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 23:56:39.920201 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5571 23:56:39.923666 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 23:56:39.927206 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 23:56:39.933182 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5574 23:56:39.933298
5575 23:56:39.936950 CA PerBit enable=1, Macro0, CA PI delay=33
5576 23:56:39.937067
5577 23:56:39.940016 [CBTSetCACLKResult] CA Dly = 33
5578 23:56:39.940130 CS Dly: 7 (0~38)
5579 23:56:39.940210 ==
5580 23:56:39.943607 Dram Type= 6, Freq= 0, CH_1, rank 1
5581 23:56:39.946535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5582 23:56:39.950484 ==
5583 23:56:39.953583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5584 23:56:39.960525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5585 23:56:39.963203 [CA 0] Center 36 (6~67) winsize 62
5586 23:56:39.967252 [CA 1] Center 37 (6~68) winsize 63
5587 23:56:39.970478 [CA 2] Center 35 (5~66) winsize 62
5588 23:56:39.973545 [CA 3] Center 34 (4~65) winsize 62
5589 23:56:39.976636 [CA 4] Center 34 (4~65) winsize 62
5590 23:56:39.980181 [CA 5] Center 33 (3~64) winsize 62
5591 23:56:39.980292
5592 23:56:39.983082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5593 23:56:39.983165
5594 23:56:39.986813 [CATrainingPosCal] consider 2 rank data
5595 23:56:39.989927 u2DelayCellTimex100 = 270/100 ps
5596 23:56:39.992930 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5597 23:56:39.996794 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5598 23:56:39.999962 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5599 23:56:40.003114 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5600 23:56:40.009635 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5601 23:56:40.013775 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5602 23:56:40.013858
5603 23:56:40.016422 CA PerBit enable=1, Macro0, CA PI delay=33
5604 23:56:40.016505
5605 23:56:40.020024 [CBTSetCACLKResult] CA Dly = 33
5606 23:56:40.020107 CS Dly: 8 (0~40)
5607 23:56:40.020173
5608 23:56:40.022817 ----->DramcWriteLeveling(PI) begin...
5609 23:56:40.022901 ==
5610 23:56:40.026567 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 23:56:40.032874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 23:56:40.032964 ==
5613 23:56:40.036450 Write leveling (Byte 0): 25 => 25
5614 23:56:40.039898 Write leveling (Byte 1): 28 => 28
5615 23:56:40.039991 DramcWriteLeveling(PI) end<-----
5616 23:56:40.040070
5617 23:56:40.043352 ==
5618 23:56:40.046247 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 23:56:40.049372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 23:56:40.049489 ==
5621 23:56:40.052961 [Gating] SW mode calibration
5622 23:56:40.059437 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5623 23:56:40.063089 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5624 23:56:40.069683 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 23:56:40.072775 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 23:56:40.076432 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 23:56:40.082726 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 23:56:40.085953 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 23:56:40.089885 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5630 23:56:40.095846 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
5631 23:56:40.099581 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5632 23:56:40.102419 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 23:56:40.109454 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 23:56:40.112710 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 23:56:40.115770 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 23:56:40.122660 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 23:56:40.126110 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 23:56:40.129464 0 15 24 | B1->B0 | 2525 3636 | 0 1 | (0 0) (0 0)
5639 23:56:40.135571 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5640 23:56:40.139361 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 23:56:40.142439 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 23:56:40.149747 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 23:56:40.152514 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 23:56:40.155811 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 23:56:40.162330 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5646 23:56:40.165776 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5647 23:56:40.169122 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:56:40.172475 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:56:40.179087 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:56:40.182553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:56:40.185679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:56:40.192704 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:56:40.196165 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:56:40.199026 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:56:40.206076 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:56:40.209456 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:56:40.212813 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:56:40.219214 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:56:40.222512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:56:40.226370 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:56:40.232461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:56:40.235855 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5663 23:56:40.238938 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5664 23:56:40.245668 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 23:56:40.245749 Total UI for P1: 0, mck2ui 16
5666 23:56:40.252008 best dqsien dly found for B0: ( 1, 2, 26)
5667 23:56:40.252087 Total UI for P1: 0, mck2ui 16
5668 23:56:40.255829 best dqsien dly found for B1: ( 1, 2, 26)
5669 23:56:40.262349 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5670 23:56:40.265541 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5671 23:56:40.265652
5672 23:56:40.268779 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5673 23:56:40.271921 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5674 23:56:40.275288 [Gating] SW calibration Done
5675 23:56:40.275399 ==
5676 23:56:40.279183 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 23:56:40.282001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 23:56:40.282092 ==
5679 23:56:40.285315 RX Vref Scan: 0
5680 23:56:40.285395
5681 23:56:40.285459 RX Vref 0 -> 0, step: 1
5682 23:56:40.285538
5683 23:56:40.289016 RX Delay -80 -> 252, step: 8
5684 23:56:40.291807 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5685 23:56:40.298541 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5686 23:56:40.302141 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5687 23:56:40.305030 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5688 23:56:40.308390 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5689 23:56:40.311984 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5690 23:56:40.315193 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5691 23:56:40.321717 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5692 23:56:40.324931 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5693 23:56:40.328173 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5694 23:56:40.332019 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5695 23:56:40.335201 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5696 23:56:40.338422 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5697 23:56:40.345158 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5698 23:56:40.348823 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5699 23:56:40.351930 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5700 23:56:40.352043 ==
5701 23:56:40.355369 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 23:56:40.358314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 23:56:40.361898 ==
5704 23:56:40.362007 DQS Delay:
5705 23:56:40.362103 DQS0 = 0, DQS1 = 0
5706 23:56:40.364854 DQM Delay:
5707 23:56:40.364982 DQM0 = 103, DQM1 = 98
5708 23:56:40.368037 DQ Delay:
5709 23:56:40.368152 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5710 23:56:40.375247 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5711 23:56:40.375353 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5712 23:56:40.381737 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5713 23:56:40.381850
5714 23:56:40.381942
5715 23:56:40.382029 ==
5716 23:56:40.384841 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 23:56:40.388466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 23:56:40.388572 ==
5719 23:56:40.388668
5720 23:56:40.388757
5721 23:56:40.391635 TX Vref Scan disable
5722 23:56:40.391735 == TX Byte 0 ==
5723 23:56:40.397999 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 23:56:40.401176 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 23:56:40.401252 == TX Byte 1 ==
5726 23:56:40.408196 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5727 23:56:40.411306 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5728 23:56:40.411408 ==
5729 23:56:40.414686 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 23:56:40.418246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 23:56:40.418355 ==
5732 23:56:40.418460
5733 23:56:40.418554
5734 23:56:40.421248 TX Vref Scan disable
5735 23:56:40.424572 == TX Byte 0 ==
5736 23:56:40.428054 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5737 23:56:40.431542 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5738 23:56:40.434917 == TX Byte 1 ==
5739 23:56:40.437970 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5740 23:56:40.441439 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5741 23:56:40.444438
5742 23:56:40.444518 [DATLAT]
5743 23:56:40.444585 Freq=933, CH1 RK0
5744 23:56:40.444646
5745 23:56:40.447724 DATLAT Default: 0xd
5746 23:56:40.447826 0, 0xFFFF, sum = 0
5747 23:56:40.451047 1, 0xFFFF, sum = 0
5748 23:56:40.451157 2, 0xFFFF, sum = 0
5749 23:56:40.455019 3, 0xFFFF, sum = 0
5750 23:56:40.455128 4, 0xFFFF, sum = 0
5751 23:56:40.458118 5, 0xFFFF, sum = 0
5752 23:56:40.458223 6, 0xFFFF, sum = 0
5753 23:56:40.461388 7, 0xFFFF, sum = 0
5754 23:56:40.465024 8, 0xFFFF, sum = 0
5755 23:56:40.465147 9, 0xFFFF, sum = 0
5756 23:56:40.465265 10, 0x0, sum = 1
5757 23:56:40.468086 11, 0x0, sum = 2
5758 23:56:40.468171 12, 0x0, sum = 3
5759 23:56:40.471356 13, 0x0, sum = 4
5760 23:56:40.471439 best_step = 11
5761 23:56:40.471524
5762 23:56:40.471614 ==
5763 23:56:40.474467 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 23:56:40.481428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 23:56:40.481555 ==
5766 23:56:40.481665 RX Vref Scan: 1
5767 23:56:40.481780
5768 23:56:40.484778 RX Vref 0 -> 0, step: 1
5769 23:56:40.484890
5770 23:56:40.487751 RX Delay -45 -> 252, step: 4
5771 23:56:40.487864
5772 23:56:40.491576 Set Vref, RX VrefLevel [Byte0]: 53
5773 23:56:40.494782 [Byte1]: 48
5774 23:56:40.494879
5775 23:56:40.498151 Final RX Vref Byte 0 = 53 to rank0
5776 23:56:40.501243 Final RX Vref Byte 1 = 48 to rank0
5777 23:56:40.504742 Final RX Vref Byte 0 = 53 to rank1
5778 23:56:40.507868 Final RX Vref Byte 1 = 48 to rank1==
5779 23:56:40.511261 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 23:56:40.515084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 23:56:40.515203 ==
5782 23:56:40.518240 DQS Delay:
5783 23:56:40.518343 DQS0 = 0, DQS1 = 0
5784 23:56:40.518445 DQM Delay:
5785 23:56:40.521101 DQM0 = 103, DQM1 = 100
5786 23:56:40.521203 DQ Delay:
5787 23:56:40.524958 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5788 23:56:40.528694 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5789 23:56:40.531731 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5790 23:56:40.534473 DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =110
5791 23:56:40.538442
5792 23:56:40.538552
5793 23:56:40.545000 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5794 23:56:40.548256 CH1 RK0: MR19=505, MR18=172F
5795 23:56:40.554736 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5796 23:56:40.554849
5797 23:56:40.558127 ----->DramcWriteLeveling(PI) begin...
5798 23:56:40.558212 ==
5799 23:56:40.561341 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 23:56:40.564661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 23:56:40.564744 ==
5802 23:56:40.567827 Write leveling (Byte 0): 28 => 28
5803 23:56:40.571145 Write leveling (Byte 1): 28 => 28
5804 23:56:40.574700 DramcWriteLeveling(PI) end<-----
5805 23:56:40.574811
5806 23:56:40.574910 ==
5807 23:56:40.578205 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 23:56:40.581357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 23:56:40.581441 ==
5810 23:56:40.584807 [Gating] SW mode calibration
5811 23:56:40.591404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5812 23:56:40.597565 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5813 23:56:40.601692 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 23:56:40.604927 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 23:56:40.611211 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 23:56:40.614362 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 23:56:40.617742 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 23:56:40.624921 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5819 23:56:40.627657 0 14 24 | B1->B0 | 2828 3333 | 0 1 | (0 1) (1 0)
5820 23:56:40.631346 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
5821 23:56:40.637942 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 23:56:40.640722 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 23:56:40.644224 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 23:56:40.650781 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 23:56:40.654259 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 23:56:40.657690 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5827 23:56:40.664801 0 15 24 | B1->B0 | 3a3a 2a2a | 0 0 | (0 0) (0 0)
5828 23:56:40.667992 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5829 23:56:40.671280 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 23:56:40.678006 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 23:56:40.681023 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 23:56:40.684562 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 23:56:40.690947 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 23:56:40.693951 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 23:56:40.697747 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5836 23:56:40.704269 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5837 23:56:40.707627 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:56:40.710718 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:56:40.714456 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:56:40.721356 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:56:40.724076 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:56:40.727200 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:56:40.734122 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 23:56:40.737816 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:56:40.740905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:56:40.747535 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:56:40.750858 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:56:40.754342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:56:40.760978 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:56:40.763738 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:56:40.767304 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5852 23:56:40.774176 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 23:56:40.774262 Total UI for P1: 0, mck2ui 16
5854 23:56:40.780702 best dqsien dly found for B0: ( 1, 2, 24)
5855 23:56:40.780785 Total UI for P1: 0, mck2ui 16
5856 23:56:40.784159 best dqsien dly found for B1: ( 1, 2, 24)
5857 23:56:40.790519 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5858 23:56:40.794547 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5859 23:56:40.794656
5860 23:56:40.797525 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5861 23:56:40.800847 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5862 23:56:40.804089 [Gating] SW calibration Done
5863 23:56:40.804203 ==
5864 23:56:40.807327 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 23:56:40.811020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 23:56:40.811132 ==
5867 23:56:40.814352 RX Vref Scan: 0
5868 23:56:40.814458
5869 23:56:40.814563 RX Vref 0 -> 0, step: 1
5870 23:56:40.814659
5871 23:56:40.817511 RX Delay -80 -> 252, step: 8
5872 23:56:40.820819 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5873 23:56:40.826973 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5874 23:56:40.830633 iDelay=208, Bit 2, Center 91 (8 ~ 175) 168
5875 23:56:40.833622 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5876 23:56:40.837161 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5877 23:56:40.840872 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5878 23:56:40.843828 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5879 23:56:40.847129 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5880 23:56:40.854004 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5881 23:56:40.857247 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5882 23:56:40.860617 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5883 23:56:40.863782 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5884 23:56:40.867188 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5885 23:56:40.873959 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5886 23:56:40.877740 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5887 23:56:40.881001 iDelay=208, Bit 15, Center 111 (24 ~ 199) 176
5888 23:56:40.881108 ==
5889 23:56:40.883993 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 23:56:40.887298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 23:56:40.887405 ==
5892 23:56:40.890163 DQS Delay:
5893 23:56:40.890269 DQS0 = 0, DQS1 = 0
5894 23:56:40.893781 DQM Delay:
5895 23:56:40.893866 DQM0 = 102, DQM1 = 99
5896 23:56:40.893932 DQ Delay:
5897 23:56:40.897038 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =95
5898 23:56:40.900411 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5899 23:56:40.903440 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5900 23:56:40.910476 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =111
5901 23:56:40.910586
5902 23:56:40.910686
5903 23:56:40.910781 ==
5904 23:56:40.913871 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 23:56:40.916733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 23:56:40.916818 ==
5907 23:56:40.916884
5908 23:56:40.916945
5909 23:56:40.920078 TX Vref Scan disable
5910 23:56:40.920161 == TX Byte 0 ==
5911 23:56:40.927172 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5912 23:56:40.930551 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5913 23:56:40.930655 == TX Byte 1 ==
5914 23:56:40.937353 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5915 23:56:40.940550 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5916 23:56:40.940630 ==
5917 23:56:40.943725 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 23:56:40.947542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 23:56:40.947645 ==
5920 23:56:40.947748
5921 23:56:40.947841
5922 23:56:40.949986 TX Vref Scan disable
5923 23:56:40.953907 == TX Byte 0 ==
5924 23:56:40.957241 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5925 23:56:40.960268 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5926 23:56:40.963779 == TX Byte 1 ==
5927 23:56:40.967097 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5928 23:56:40.970084 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5929 23:56:40.970199
5930 23:56:40.973723 [DATLAT]
5931 23:56:40.973839 Freq=933, CH1 RK1
5932 23:56:40.973934
5933 23:56:40.977021 DATLAT Default: 0xb
5934 23:56:40.977097 0, 0xFFFF, sum = 0
5935 23:56:40.980125 1, 0xFFFF, sum = 0
5936 23:56:40.980240 2, 0xFFFF, sum = 0
5937 23:56:40.983425 3, 0xFFFF, sum = 0
5938 23:56:40.983542 4, 0xFFFF, sum = 0
5939 23:56:40.987063 5, 0xFFFF, sum = 0
5940 23:56:40.987167 6, 0xFFFF, sum = 0
5941 23:56:40.990532 7, 0xFFFF, sum = 0
5942 23:56:40.990635 8, 0xFFFF, sum = 0
5943 23:56:40.993322 9, 0xFFFF, sum = 0
5944 23:56:40.993403 10, 0x0, sum = 1
5945 23:56:40.997306 11, 0x0, sum = 2
5946 23:56:40.997409 12, 0x0, sum = 3
5947 23:56:41.000399 13, 0x0, sum = 4
5948 23:56:41.000503 best_step = 11
5949 23:56:41.000574
5950 23:56:41.000634 ==
5951 23:56:41.003579 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 23:56:41.010268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 23:56:41.010376 ==
5954 23:56:41.010470 RX Vref Scan: 0
5955 23:56:41.010570
5956 23:56:41.013325 RX Vref 0 -> 0, step: 1
5957 23:56:41.013427
5958 23:56:41.016683 RX Delay -45 -> 252, step: 4
5959 23:56:41.020243 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5960 23:56:41.023071 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5961 23:56:41.029735 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5962 23:56:41.033161 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5963 23:56:41.036834 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5964 23:56:41.039883 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5965 23:56:41.043230 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5966 23:56:41.049415 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5967 23:56:41.053003 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5968 23:56:41.056510 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5969 23:56:41.059823 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5970 23:56:41.063324 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5971 23:56:41.069627 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5972 23:56:41.073255 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5973 23:56:41.076277 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5974 23:56:41.079721 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5975 23:56:41.079859 ==
5976 23:56:41.082826 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 23:56:41.089485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 23:56:41.089603 ==
5979 23:56:41.089681 DQS Delay:
5980 23:56:41.089761 DQS0 = 0, DQS1 = 0
5981 23:56:41.093076 DQM Delay:
5982 23:56:41.093169 DQM0 = 104, DQM1 = 99
5983 23:56:41.096414 DQ Delay:
5984 23:56:41.099738 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5985 23:56:41.102879 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5986 23:56:41.106160 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =94
5987 23:56:41.109953 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5988 23:56:41.110090
5989 23:56:41.110217
5990 23:56:41.116183 [DQSOSCAuto] RK1, (LSB)MR18= 0x2dff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5991 23:56:41.119230 CH1 RK1: MR19=504, MR18=2DFF
5992 23:56:41.126484 CH1_RK1: MR19=0x504, MR18=0x2DFF, DQSOSC=407, MR23=63, INC=65, DEC=43
5993 23:56:41.129705 [RxdqsGatingPostProcess] freq 933
5994 23:56:41.136372 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 23:56:41.139438 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 23:56:41.139547 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 23:56:41.142586 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 23:56:41.146018 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 23:56:41.149167 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 23:56:41.152433 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 23:56:41.155875 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 23:56:41.159014 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 23:56:41.162452 Pre-setting of DQS Precalculation
6004 23:56:41.169111 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 23:56:41.175704 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 23:56:41.182260 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 23:56:41.182402
6008 23:56:41.182525
6009 23:56:41.186163 [Calibration Summary] 1866 Mbps
6010 23:56:41.186279 CH 0, Rank 0
6011 23:56:41.189262 SW Impedance : PASS
6012 23:56:41.192459 DUTY Scan : NO K
6013 23:56:41.192560 ZQ Calibration : PASS
6014 23:56:41.196057 Jitter Meter : NO K
6015 23:56:41.199022 CBT Training : PASS
6016 23:56:41.199130 Write leveling : PASS
6017 23:56:41.202488 RX DQS gating : PASS
6018 23:56:41.202591 RX DQ/DQS(RDDQC) : PASS
6019 23:56:41.205609 TX DQ/DQS : PASS
6020 23:56:41.209335 RX DATLAT : PASS
6021 23:56:41.209478 RX DQ/DQS(Engine): PASS
6022 23:56:41.212309 TX OE : NO K
6023 23:56:41.212436 All Pass.
6024 23:56:41.212542
6025 23:56:41.215981 CH 0, Rank 1
6026 23:56:41.216090 SW Impedance : PASS
6027 23:56:41.219094 DUTY Scan : NO K
6028 23:56:41.222515 ZQ Calibration : PASS
6029 23:56:41.222640 Jitter Meter : NO K
6030 23:56:41.226168 CBT Training : PASS
6031 23:56:41.228897 Write leveling : PASS
6032 23:56:41.228985 RX DQS gating : PASS
6033 23:56:41.232625 RX DQ/DQS(RDDQC) : PASS
6034 23:56:41.235859 TX DQ/DQS : PASS
6035 23:56:41.235996 RX DATLAT : PASS
6036 23:56:41.239017 RX DQ/DQS(Engine): PASS
6037 23:56:41.242501 TX OE : NO K
6038 23:56:41.242611 All Pass.
6039 23:56:41.242712
6040 23:56:41.242807 CH 1, Rank 0
6041 23:56:41.245680 SW Impedance : PASS
6042 23:56:41.248905 DUTY Scan : NO K
6043 23:56:41.248990 ZQ Calibration : PASS
6044 23:56:41.252171 Jitter Meter : NO K
6045 23:56:41.252283 CBT Training : PASS
6046 23:56:41.255503 Write leveling : PASS
6047 23:56:41.259071 RX DQS gating : PASS
6048 23:56:41.259159 RX DQ/DQS(RDDQC) : PASS
6049 23:56:41.262161 TX DQ/DQS : PASS
6050 23:56:41.265507 RX DATLAT : PASS
6051 23:56:41.265643 RX DQ/DQS(Engine): PASS
6052 23:56:41.268931 TX OE : NO K
6053 23:56:41.269068 All Pass.
6054 23:56:41.269189
6055 23:56:41.272503 CH 1, Rank 1
6056 23:56:41.272588 SW Impedance : PASS
6057 23:56:41.275868 DUTY Scan : NO K
6058 23:56:41.278984 ZQ Calibration : PASS
6059 23:56:41.279068 Jitter Meter : NO K
6060 23:56:41.282179 CBT Training : PASS
6061 23:56:41.285554 Write leveling : PASS
6062 23:56:41.285639 RX DQS gating : PASS
6063 23:56:41.288784 RX DQ/DQS(RDDQC) : PASS
6064 23:56:41.291891 TX DQ/DQS : PASS
6065 23:56:41.291966 RX DATLAT : PASS
6066 23:56:41.295837 RX DQ/DQS(Engine): PASS
6067 23:56:41.295948 TX OE : NO K
6068 23:56:41.298949 All Pass.
6069 23:56:41.299032
6070 23:56:41.299098 DramC Write-DBI off
6071 23:56:41.302331 PER_BANK_REFRESH: Hybrid Mode
6072 23:56:41.305579 TX_TRACKING: ON
6073 23:56:41.311994 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 23:56:41.315459 [FAST_K] Save calibration result to emmc
6075 23:56:41.321978 dramc_set_vcore_voltage set vcore to 650000
6076 23:56:41.322065 Read voltage for 400, 6
6077 23:56:41.322146 Vio18 = 0
6078 23:56:41.325196 Vcore = 650000
6079 23:56:41.325338 Vdram = 0
6080 23:56:41.325479 Vddq = 0
6081 23:56:41.328863 Vmddr = 0
6082 23:56:41.332238 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 23:56:41.339045 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 23:56:41.341949 MEM_TYPE=3, freq_sel=20
6085 23:56:41.342092 sv_algorithm_assistance_LP4_800
6086 23:56:41.348548 ============ PULL DRAM RESETB DOWN ============
6087 23:56:41.351900 ========== PULL DRAM RESETB DOWN end =========
6088 23:56:41.355624 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 23:56:41.358350 ===================================
6090 23:56:41.361778 LPDDR4 DRAM CONFIGURATION
6091 23:56:41.365043 ===================================
6092 23:56:41.368212 EX_ROW_EN[0] = 0x0
6093 23:56:41.368348 EX_ROW_EN[1] = 0x0
6094 23:56:41.372043 LP4Y_EN = 0x0
6095 23:56:41.372157 WORK_FSP = 0x0
6096 23:56:41.375302 WL = 0x2
6097 23:56:41.375417 RL = 0x2
6098 23:56:41.378695 BL = 0x2
6099 23:56:41.378806 RPST = 0x0
6100 23:56:41.381930 RD_PRE = 0x0
6101 23:56:41.382040 WR_PRE = 0x1
6102 23:56:41.385206 WR_PST = 0x0
6103 23:56:41.385295 DBI_WR = 0x0
6104 23:56:41.388525 DBI_RD = 0x0
6105 23:56:41.388601 OTF = 0x1
6106 23:56:41.391664 ===================================
6107 23:56:41.395530 ===================================
6108 23:56:41.398718 ANA top config
6109 23:56:41.401964 ===================================
6110 23:56:41.405057 DLL_ASYNC_EN = 0
6111 23:56:41.405135 ALL_SLAVE_EN = 1
6112 23:56:41.408747 NEW_RANK_MODE = 1
6113 23:56:41.411820 DLL_IDLE_MODE = 1
6114 23:56:41.415057 LP45_APHY_COMB_EN = 1
6115 23:56:41.415143 TX_ODT_DIS = 1
6116 23:56:41.418172 NEW_8X_MODE = 1
6117 23:56:41.421952 ===================================
6118 23:56:41.424986 ===================================
6119 23:56:41.428621 data_rate = 800
6120 23:56:41.431364 CKR = 1
6121 23:56:41.435019 DQ_P2S_RATIO = 4
6122 23:56:41.438267 ===================================
6123 23:56:41.441601 CA_P2S_RATIO = 4
6124 23:56:41.441681 DQ_CA_OPEN = 0
6125 23:56:41.444871 DQ_SEMI_OPEN = 1
6126 23:56:41.448122 CA_SEMI_OPEN = 1
6127 23:56:41.451522 CA_FULL_RATE = 0
6128 23:56:41.454529 DQ_CKDIV4_EN = 0
6129 23:56:41.458373 CA_CKDIV4_EN = 1
6130 23:56:41.458481 CA_PREDIV_EN = 0
6131 23:56:41.461528 PH8_DLY = 0
6132 23:56:41.464626 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 23:56:41.467825 DQ_AAMCK_DIV = 0
6134 23:56:41.471045 CA_AAMCK_DIV = 0
6135 23:56:41.474639 CA_ADMCK_DIV = 4
6136 23:56:41.474746 DQ_TRACK_CA_EN = 0
6137 23:56:41.477685 CA_PICK = 800
6138 23:56:41.481562 CA_MCKIO = 400
6139 23:56:41.484482 MCKIO_SEMI = 400
6140 23:56:41.487918 PLL_FREQ = 3016
6141 23:56:41.491113 DQ_UI_PI_RATIO = 32
6142 23:56:41.494466 CA_UI_PI_RATIO = 32
6143 23:56:41.497658 ===================================
6144 23:56:41.500939 ===================================
6145 23:56:41.501050 memory_type:LPDDR4
6146 23:56:41.504252 GP_NUM : 10
6147 23:56:41.508090 SRAM_EN : 1
6148 23:56:41.508174 MD32_EN : 0
6149 23:56:41.511268 ===================================
6150 23:56:41.514564 [ANA_INIT] >>>>>>>>>>>>>>
6151 23:56:41.517338 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 23:56:41.521154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 23:56:41.524489 ===================================
6154 23:56:41.527872 data_rate = 800,PCW = 0X7400
6155 23:56:41.530573 ===================================
6156 23:56:41.534305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 23:56:41.537250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 23:56:41.550587 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 23:56:41.553853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 23:56:41.558043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 23:56:41.561076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 23:56:41.563811 [ANA_INIT] flow start
6163 23:56:41.567455 [ANA_INIT] PLL >>>>>>>>
6164 23:56:41.567535 [ANA_INIT] PLL <<<<<<<<
6165 23:56:41.570443 [ANA_INIT] MIDPI >>>>>>>>
6166 23:56:41.573779 [ANA_INIT] MIDPI <<<<<<<<
6167 23:56:41.573890 [ANA_INIT] DLL >>>>>>>>
6168 23:56:41.576987 [ANA_INIT] flow end
6169 23:56:41.580695 ============ LP4 DIFF to SE enter ============
6170 23:56:41.583771 ============ LP4 DIFF to SE exit ============
6171 23:56:41.587152 [ANA_INIT] <<<<<<<<<<<<<
6172 23:56:41.590372 [Flow] Enable top DCM control >>>>>
6173 23:56:41.593553 [Flow] Enable top DCM control <<<<<
6174 23:56:41.597203 Enable DLL master slave shuffle
6175 23:56:41.603621 ==============================================================
6176 23:56:41.603706 Gating Mode config
6177 23:56:41.610635 ==============================================================
6178 23:56:41.613945 Config description:
6179 23:56:41.620141 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 23:56:41.626701 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 23:56:41.634019 SELPH_MODE 0: By rank 1: By Phase
6182 23:56:41.640366 ==============================================================
6183 23:56:41.640470 GAT_TRACK_EN = 0
6184 23:56:41.643383 RX_GATING_MODE = 2
6185 23:56:41.647040 RX_GATING_TRACK_MODE = 2
6186 23:56:41.650075 SELPH_MODE = 1
6187 23:56:41.653812 PICG_EARLY_EN = 1
6188 23:56:41.656958 VALID_LAT_VALUE = 1
6189 23:56:41.663616 ==============================================================
6190 23:56:41.666829 Enter into Gating configuration >>>>
6191 23:56:41.670038 Exit from Gating configuration <<<<
6192 23:56:41.673833 Enter into DVFS_PRE_config >>>>>
6193 23:56:41.683838 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 23:56:41.687108 Exit from DVFS_PRE_config <<<<<
6195 23:56:41.690088 Enter into PICG configuration >>>>
6196 23:56:41.693291 Exit from PICG configuration <<<<
6197 23:56:41.696455 [RX_INPUT] configuration >>>>>
6198 23:56:41.696538 [RX_INPUT] configuration <<<<<
6199 23:56:41.703604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 23:56:41.710012 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 23:56:41.713299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 23:56:41.719802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 23:56:41.726619 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 23:56:41.733395 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 23:56:41.736326 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 23:56:41.739768 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 23:56:41.746910 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 23:56:41.749976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 23:56:41.753156 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 23:56:41.759476 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 23:56:41.762845 ===================================
6212 23:56:41.762960 LPDDR4 DRAM CONFIGURATION
6213 23:56:41.766739 ===================================
6214 23:56:41.769681 EX_ROW_EN[0] = 0x0
6215 23:56:41.769765 EX_ROW_EN[1] = 0x0
6216 23:56:41.773283 LP4Y_EN = 0x0
6217 23:56:41.773364 WORK_FSP = 0x0
6218 23:56:41.776703 WL = 0x2
6219 23:56:41.779573 RL = 0x2
6220 23:56:41.779678 BL = 0x2
6221 23:56:41.782924 RPST = 0x0
6222 23:56:41.783001 RD_PRE = 0x0
6223 23:56:41.786668 WR_PRE = 0x1
6224 23:56:41.786748 WR_PST = 0x0
6225 23:56:41.789904 DBI_WR = 0x0
6226 23:56:41.789980 DBI_RD = 0x0
6227 23:56:41.793086 OTF = 0x1
6228 23:56:41.796473 ===================================
6229 23:56:41.799900 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 23:56:41.802745 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 23:56:41.806561 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 23:56:41.809876 ===================================
6233 23:56:41.813149 LPDDR4 DRAM CONFIGURATION
6234 23:56:41.816502 ===================================
6235 23:56:41.819576 EX_ROW_EN[0] = 0x10
6236 23:56:41.819693 EX_ROW_EN[1] = 0x0
6237 23:56:41.822762 LP4Y_EN = 0x0
6238 23:56:41.822845 WORK_FSP = 0x0
6239 23:56:41.826374 WL = 0x2
6240 23:56:41.826482 RL = 0x2
6241 23:56:41.829158 BL = 0x2
6242 23:56:41.829235 RPST = 0x0
6243 23:56:41.832757 RD_PRE = 0x0
6244 23:56:41.835826 WR_PRE = 0x1
6245 23:56:41.835901 WR_PST = 0x0
6246 23:56:41.839415 DBI_WR = 0x0
6247 23:56:41.839496 DBI_RD = 0x0
6248 23:56:41.842797 OTF = 0x1
6249 23:56:41.845911 ===================================
6250 23:56:41.849153 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 23:56:41.854724 nWR fixed to 30
6252 23:56:41.857793 [ModeRegInit_LP4] CH0 RK0
6253 23:56:41.857894 [ModeRegInit_LP4] CH0 RK1
6254 23:56:41.861487 [ModeRegInit_LP4] CH1 RK0
6255 23:56:41.864540 [ModeRegInit_LP4] CH1 RK1
6256 23:56:41.864614 match AC timing 19
6257 23:56:41.871479 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 23:56:41.874710 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 23:56:41.878013 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 23:56:41.884744 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 23:56:41.887901 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 23:56:41.887986 ==
6263 23:56:41.891107 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 23:56:41.894698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 23:56:41.894780 ==
6266 23:56:41.901233 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 23:56:41.908096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6268 23:56:41.911319 [CA 0] Center 36 (8~64) winsize 57
6269 23:56:41.914746 [CA 1] Center 36 (8~64) winsize 57
6270 23:56:41.918100 [CA 2] Center 36 (8~64) winsize 57
6271 23:56:41.918206 [CA 3] Center 36 (8~64) winsize 57
6272 23:56:41.921180 [CA 4] Center 36 (8~64) winsize 57
6273 23:56:41.924465 [CA 5] Center 36 (8~64) winsize 57
6274 23:56:41.924569
6275 23:56:41.927895 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6276 23:56:41.931041
6277 23:56:41.934480 [CATrainingPosCal] consider 1 rank data
6278 23:56:41.934583 u2DelayCellTimex100 = 270/100 ps
6279 23:56:41.941193 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 23:56:41.944324 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 23:56:41.947870 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 23:56:41.951182 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 23:56:41.954362 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 23:56:41.958027 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 23:56:41.958106
6286 23:56:41.960991 CA PerBit enable=1, Macro0, CA PI delay=36
6287 23:56:41.961094
6288 23:56:41.964413 [CBTSetCACLKResult] CA Dly = 36
6289 23:56:41.967788 CS Dly: 1 (0~32)
6290 23:56:41.967874 ==
6291 23:56:41.971361 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 23:56:41.974412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 23:56:41.974525 ==
6294 23:56:41.981458 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 23:56:41.984658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 23:56:41.987565 [CA 0] Center 36 (8~64) winsize 57
6297 23:56:41.991319 [CA 1] Center 36 (8~64) winsize 57
6298 23:56:41.994564 [CA 2] Center 36 (8~64) winsize 57
6299 23:56:41.997715 [CA 3] Center 36 (8~64) winsize 57
6300 23:56:42.001013 [CA 4] Center 36 (8~64) winsize 57
6301 23:56:42.004660 [CA 5] Center 36 (8~64) winsize 57
6302 23:56:42.004744
6303 23:56:42.007649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 23:56:42.007759
6305 23:56:42.010896 [CATrainingPosCal] consider 2 rank data
6306 23:56:42.014328 u2DelayCellTimex100 = 270/100 ps
6307 23:56:42.017474 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 23:56:42.020712 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 23:56:42.024602 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 23:56:42.031163 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 23:56:42.034352 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 23:56:42.037605 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 23:56:42.037689
6314 23:56:42.041063 CA PerBit enable=1, Macro0, CA PI delay=36
6315 23:56:42.041147
6316 23:56:42.044286 [CBTSetCACLKResult] CA Dly = 36
6317 23:56:42.044392 CS Dly: 1 (0~32)
6318 23:56:42.044459
6319 23:56:42.047452 ----->DramcWriteLeveling(PI) begin...
6320 23:56:42.047562 ==
6321 23:56:42.051214 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 23:56:42.057529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 23:56:42.057614 ==
6324 23:56:42.060928 Write leveling (Byte 0): 40 => 8
6325 23:56:42.064328 Write leveling (Byte 1): 40 => 8
6326 23:56:42.064423 DramcWriteLeveling(PI) end<-----
6327 23:56:42.064491
6328 23:56:42.067677 ==
6329 23:56:42.070920 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 23:56:42.074146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 23:56:42.074226 ==
6332 23:56:42.077103 [Gating] SW mode calibration
6333 23:56:42.084131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 23:56:42.087522 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 23:56:42.094300 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 23:56:42.097448 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 23:56:42.100722 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 23:56:42.107301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 23:56:42.110558 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 23:56:42.114043 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 23:56:42.120637 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 23:56:42.123971 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 23:56:42.127185 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 23:56:42.130833 Total UI for P1: 0, mck2ui 16
6345 23:56:42.133944 best dqsien dly found for B0: ( 0, 14, 24)
6346 23:56:42.137330 Total UI for P1: 0, mck2ui 16
6347 23:56:42.140525 best dqsien dly found for B1: ( 0, 14, 24)
6348 23:56:42.143818 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 23:56:42.147161 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 23:56:42.147244
6351 23:56:42.153992 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 23:56:42.157280 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 23:56:42.157370 [Gating] SW calibration Done
6354 23:56:42.160567 ==
6355 23:56:42.160654 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 23:56:42.167295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 23:56:42.167380 ==
6358 23:56:42.167448 RX Vref Scan: 0
6359 23:56:42.167542
6360 23:56:42.170409 RX Vref 0 -> 0, step: 1
6361 23:56:42.170484
6362 23:56:42.173522 RX Delay -410 -> 252, step: 16
6363 23:56:42.177060 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6364 23:56:42.180905 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6365 23:56:42.186818 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6366 23:56:42.190270 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6367 23:56:42.193448 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6368 23:56:42.197177 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6369 23:56:42.203528 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6370 23:56:42.207071 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6371 23:56:42.210370 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6372 23:56:42.213763 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6373 23:56:42.220365 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6374 23:56:42.223727 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6375 23:56:42.227157 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6376 23:56:42.230601 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6377 23:56:42.236816 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6378 23:56:42.240160 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6379 23:56:42.240267 ==
6380 23:56:42.243555 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 23:56:42.246903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 23:56:42.246987 ==
6383 23:56:42.250247 DQS Delay:
6384 23:56:42.250330 DQS0 = 27, DQS1 = 35
6385 23:56:42.253874 DQM Delay:
6386 23:56:42.253956 DQM0 = 8, DQM1 = 12
6387 23:56:42.254021 DQ Delay:
6388 23:56:42.257022 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6389 23:56:42.260487 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6390 23:56:42.263519 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6391 23:56:42.267087 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6392 23:56:42.267169
6393 23:56:42.267241
6394 23:56:42.267325 ==
6395 23:56:42.270172 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 23:56:42.273563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 23:56:42.276789 ==
6398 23:56:42.276884
6399 23:56:42.276960
6400 23:56:42.277044 TX Vref Scan disable
6401 23:56:42.280298 == TX Byte 0 ==
6402 23:56:42.283791 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 23:56:42.286749 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 23:56:42.289972 == TX Byte 1 ==
6405 23:56:42.294127 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 23:56:42.296552 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 23:56:42.296637 ==
6408 23:56:42.300210 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 23:56:42.306705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 23:56:42.306788 ==
6411 23:56:42.306854
6412 23:56:42.306915
6413 23:56:42.306977 TX Vref Scan disable
6414 23:56:42.309981 == TX Byte 0 ==
6415 23:56:42.313129 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 23:56:42.317013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 23:56:42.320082 == TX Byte 1 ==
6418 23:56:42.323369 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 23:56:42.326974 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 23:56:42.327062
6421 23:56:42.329991 [DATLAT]
6422 23:56:42.330108 Freq=400, CH0 RK0
6423 23:56:42.330211
6424 23:56:42.333342 DATLAT Default: 0xf
6425 23:56:42.333422 0, 0xFFFF, sum = 0
6426 23:56:42.337220 1, 0xFFFF, sum = 0
6427 23:56:42.337314 2, 0xFFFF, sum = 0
6428 23:56:42.340085 3, 0xFFFF, sum = 0
6429 23:56:42.340164 4, 0xFFFF, sum = 0
6430 23:56:42.343212 5, 0xFFFF, sum = 0
6431 23:56:42.343290 6, 0xFFFF, sum = 0
6432 23:56:42.346799 7, 0xFFFF, sum = 0
6433 23:56:42.346875 8, 0xFFFF, sum = 0
6434 23:56:42.350074 9, 0xFFFF, sum = 0
6435 23:56:42.350161 10, 0xFFFF, sum = 0
6436 23:56:42.353425 11, 0xFFFF, sum = 0
6437 23:56:42.353512 12, 0xFFFF, sum = 0
6438 23:56:42.356522 13, 0x0, sum = 1
6439 23:56:42.356607 14, 0x0, sum = 2
6440 23:56:42.359874 15, 0x0, sum = 3
6441 23:56:42.359952 16, 0x0, sum = 4
6442 23:56:42.363521 best_step = 14
6443 23:56:42.363597
6444 23:56:42.363662 ==
6445 23:56:42.366738 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 23:56:42.369850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 23:56:42.369933 ==
6448 23:56:42.373486 RX Vref Scan: 1
6449 23:56:42.373596
6450 23:56:42.373673 RX Vref 0 -> 0, step: 1
6451 23:56:42.373740
6452 23:56:42.376524 RX Delay -311 -> 252, step: 8
6453 23:56:42.376608
6454 23:56:42.379545 Set Vref, RX VrefLevel [Byte0]: 55
6455 23:56:42.383352 [Byte1]: 49
6456 23:56:42.387694
6457 23:56:42.387778 Final RX Vref Byte 0 = 55 to rank0
6458 23:56:42.390996 Final RX Vref Byte 1 = 49 to rank0
6459 23:56:42.394172 Final RX Vref Byte 0 = 55 to rank1
6460 23:56:42.397936 Final RX Vref Byte 1 = 49 to rank1==
6461 23:56:42.401341 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 23:56:42.407538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 23:56:42.407651 ==
6464 23:56:42.407753 DQS Delay:
6465 23:56:42.411310 DQS0 = 28, DQS1 = 36
6466 23:56:42.411421 DQM Delay:
6467 23:56:42.411600 DQM0 = 11, DQM1 = 13
6468 23:56:42.414542 DQ Delay:
6469 23:56:42.417641 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6470 23:56:42.417738 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6471 23:56:42.420869 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6472 23:56:42.424142 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6473 23:56:42.424255
6474 23:56:42.427524
6475 23:56:42.434075 [DQSOSCAuto] RK0, (LSB)MR18= 0xcebc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6476 23:56:42.437458 CH0 RK0: MR19=C0C, MR18=CEBC
6477 23:56:42.444335 CH0_RK0: MR19=0xC0C, MR18=0xCEBC, DQSOSC=384, MR23=63, INC=400, DEC=267
6478 23:56:42.444436 ==
6479 23:56:42.447683 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 23:56:42.450826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 23:56:42.450974 ==
6482 23:56:42.454184 [Gating] SW mode calibration
6483 23:56:42.460904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 23:56:42.467850 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 23:56:42.471392 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 23:56:42.474262 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 23:56:42.477575 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 23:56:42.484182 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 23:56:42.487330 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 23:56:42.490489 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 23:56:42.497579 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 23:56:42.500848 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 23:56:42.504284 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 23:56:42.507171 Total UI for P1: 0, mck2ui 16
6495 23:56:42.510886 best dqsien dly found for B0: ( 0, 14, 24)
6496 23:56:42.514121 Total UI for P1: 0, mck2ui 16
6497 23:56:42.517347 best dqsien dly found for B1: ( 0, 14, 24)
6498 23:56:42.520871 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 23:56:42.523899 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 23:56:42.527260
6501 23:56:42.530613 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 23:56:42.533983 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 23:56:42.537333 [Gating] SW calibration Done
6504 23:56:42.537414 ==
6505 23:56:42.540897 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 23:56:42.544207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 23:56:42.544352 ==
6508 23:56:42.544481 RX Vref Scan: 0
6509 23:56:42.544606
6510 23:56:42.547407 RX Vref 0 -> 0, step: 1
6511 23:56:42.547534
6512 23:56:42.550696 RX Delay -410 -> 252, step: 16
6513 23:56:42.554226 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6514 23:56:42.560868 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6515 23:56:42.563978 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6516 23:56:42.567530 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6517 23:56:42.570326 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6518 23:56:42.577585 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6519 23:56:42.580453 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6520 23:56:42.583806 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6521 23:56:42.587083 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6522 23:56:42.593858 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6523 23:56:42.596950 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6524 23:56:42.600108 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6525 23:56:42.603418 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6526 23:56:42.610193 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6527 23:56:42.613369 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6528 23:56:42.617010 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6529 23:56:42.617142 ==
6530 23:56:42.620312 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 23:56:42.626751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 23:56:42.626838 ==
6533 23:56:42.626905 DQS Delay:
6534 23:56:42.630049 DQS0 = 19, DQS1 = 35
6535 23:56:42.630151 DQM Delay:
6536 23:56:42.630239 DQM0 = 5, DQM1 = 11
6537 23:56:42.633410 DQ Delay:
6538 23:56:42.633510 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6539 23:56:42.636432 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6540 23:56:42.640180 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6541 23:56:42.643163 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6542 23:56:42.643241
6543 23:56:42.643305
6544 23:56:42.643368 ==
6545 23:56:42.647084 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 23:56:42.653693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 23:56:42.653802 ==
6548 23:56:42.653894
6549 23:56:42.653979
6550 23:56:42.654062 TX Vref Scan disable
6551 23:56:42.656974 == TX Byte 0 ==
6552 23:56:42.660082 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6553 23:56:42.663447 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6554 23:56:42.666793 == TX Byte 1 ==
6555 23:56:42.670090 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6556 23:56:42.673262 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6557 23:56:42.676493 ==
6558 23:56:42.676573 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 23:56:42.682984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 23:56:42.683062 ==
6561 23:56:42.683129
6562 23:56:42.683189
6563 23:56:42.686372 TX Vref Scan disable
6564 23:56:42.686440 == TX Byte 0 ==
6565 23:56:42.690310 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6566 23:56:42.696486 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6567 23:56:42.696563 == TX Byte 1 ==
6568 23:56:42.700098 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6569 23:56:42.702840 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6570 23:56:42.706769
6571 23:56:42.706881 [DATLAT]
6572 23:56:42.706978 Freq=400, CH0 RK1
6573 23:56:42.707069
6574 23:56:42.710130 DATLAT Default: 0xe
6575 23:56:42.710222 0, 0xFFFF, sum = 0
6576 23:56:42.713058 1, 0xFFFF, sum = 0
6577 23:56:42.713175 2, 0xFFFF, sum = 0
6578 23:56:42.716262 3, 0xFFFF, sum = 0
6579 23:56:42.716390 4, 0xFFFF, sum = 0
6580 23:56:42.719572 5, 0xFFFF, sum = 0
6581 23:56:42.722988 6, 0xFFFF, sum = 0
6582 23:56:42.723102 7, 0xFFFF, sum = 0
6583 23:56:42.726071 8, 0xFFFF, sum = 0
6584 23:56:42.726190 9, 0xFFFF, sum = 0
6585 23:56:42.729845 10, 0xFFFF, sum = 0
6586 23:56:42.729957 11, 0xFFFF, sum = 0
6587 23:56:42.733049 12, 0xFFFF, sum = 0
6588 23:56:42.733139 13, 0x0, sum = 1
6589 23:56:42.736528 14, 0x0, sum = 2
6590 23:56:42.736613 15, 0x0, sum = 3
6591 23:56:42.739325 16, 0x0, sum = 4
6592 23:56:42.739398 best_step = 14
6593 23:56:42.739459
6594 23:56:42.739521 ==
6595 23:56:42.743203 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 23:56:42.746412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 23:56:42.746520 ==
6598 23:56:42.749350 RX Vref Scan: 0
6599 23:56:42.749423
6600 23:56:42.752658 RX Vref 0 -> 0, step: 1
6601 23:56:42.752759
6602 23:56:42.752857 RX Delay -311 -> 252, step: 8
6603 23:56:42.761694 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6604 23:56:42.764971 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6605 23:56:42.768244 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6606 23:56:42.771401 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6607 23:56:42.778724 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6608 23:56:42.781876 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6609 23:56:42.784908 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6610 23:56:42.788409 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6611 23:56:42.794857 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6612 23:56:42.798396 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6613 23:56:42.801898 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6614 23:56:42.804797 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6615 23:56:42.811872 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6616 23:56:42.814944 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6617 23:56:42.817972 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6618 23:56:42.821511 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6619 23:56:42.825136 ==
6620 23:56:42.828078 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 23:56:42.831907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 23:56:42.832016 ==
6623 23:56:42.832125 DQS Delay:
6624 23:56:42.834710 DQS0 = 24, DQS1 = 32
6625 23:56:42.834822 DQM Delay:
6626 23:56:42.838159 DQM0 = 8, DQM1 = 9
6627 23:56:42.838266 DQ Delay:
6628 23:56:42.841399 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6629 23:56:42.845118 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6630 23:56:42.847843 DQ8 =4, DQ9 =0, DQ10 =8, DQ11 =4
6631 23:56:42.851673 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6632 23:56:42.851752
6633 23:56:42.851817
6634 23:56:42.858279 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6635 23:56:42.861528 CH0 RK1: MR19=C0C, MR18=BC5D
6636 23:56:42.868091 CH0_RK1: MR19=0xC0C, MR18=0xBC5D, DQSOSC=386, MR23=63, INC=396, DEC=264
6637 23:56:42.871245 [RxdqsGatingPostProcess] freq 400
6638 23:56:42.874576 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 23:56:42.877746 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 23:56:42.881498 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 23:56:42.884726 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 23:56:42.888020 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 23:56:42.891629 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 23:56:42.894716 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 23:56:42.897888 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 23:56:42.901166 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 23:56:42.904534 Pre-setting of DQS Precalculation
6648 23:56:42.908059 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 23:56:42.908134 ==
6650 23:56:42.911264 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 23:56:42.917688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 23:56:42.917765 ==
6653 23:56:42.920895 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 23:56:42.927720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6655 23:56:42.931484 [CA 0] Center 36 (8~64) winsize 57
6656 23:56:42.934412 [CA 1] Center 36 (8~64) winsize 57
6657 23:56:42.937604 [CA 2] Center 36 (8~64) winsize 57
6658 23:56:42.940778 [CA 3] Center 36 (8~64) winsize 57
6659 23:56:42.944643 [CA 4] Center 36 (8~64) winsize 57
6660 23:56:42.947503 [CA 5] Center 36 (8~64) winsize 57
6661 23:56:42.947607
6662 23:56:42.951146 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6663 23:56:42.951254
6664 23:56:42.954300 [CATrainingPosCal] consider 1 rank data
6665 23:56:42.957741 u2DelayCellTimex100 = 270/100 ps
6666 23:56:42.960596 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 23:56:42.964278 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 23:56:42.967589 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 23:56:42.970804 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 23:56:42.974069 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 23:56:42.977378 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 23:56:42.981456
6673 23:56:42.983974 CA PerBit enable=1, Macro0, CA PI delay=36
6674 23:56:42.984046
6675 23:56:42.987272 [CBTSetCACLKResult] CA Dly = 36
6676 23:56:42.987352 CS Dly: 1 (0~32)
6677 23:56:42.987416 ==
6678 23:56:42.990537 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 23:56:42.994198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 23:56:42.994280 ==
6681 23:56:43.000631 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 23:56:43.007446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6683 23:56:43.010655 [CA 0] Center 36 (8~64) winsize 57
6684 23:56:43.014333 [CA 1] Center 36 (8~64) winsize 57
6685 23:56:43.017350 [CA 2] Center 36 (8~64) winsize 57
6686 23:56:43.020917 [CA 3] Center 36 (8~64) winsize 57
6687 23:56:43.023995 [CA 4] Center 36 (8~64) winsize 57
6688 23:56:43.024093 [CA 5] Center 36 (8~64) winsize 57
6689 23:56:43.024191
6690 23:56:43.030669 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6691 23:56:43.030778
6692 23:56:43.034025 [CATrainingPosCal] consider 2 rank data
6693 23:56:43.037489 u2DelayCellTimex100 = 270/100 ps
6694 23:56:43.040812 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 23:56:43.044219 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 23:56:43.047250 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 23:56:43.050542 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 23:56:43.053926 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 23:56:43.057150 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 23:56:43.057256
6701 23:56:43.060902 CA PerBit enable=1, Macro0, CA PI delay=36
6702 23:56:43.060981
6703 23:56:43.064030 [CBTSetCACLKResult] CA Dly = 36
6704 23:56:43.067195 CS Dly: 1 (0~32)
6705 23:56:43.067295
6706 23:56:43.071036 ----->DramcWriteLeveling(PI) begin...
6707 23:56:43.071139 ==
6708 23:56:43.073824 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 23:56:43.077062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 23:56:43.077166 ==
6711 23:56:43.080628 Write leveling (Byte 0): 40 => 8
6712 23:56:43.083558 Write leveling (Byte 1): 40 => 8
6713 23:56:43.087157 DramcWriteLeveling(PI) end<-----
6714 23:56:43.087237
6715 23:56:43.087301 ==
6716 23:56:43.090313 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 23:56:43.093496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 23:56:43.093569 ==
6719 23:56:43.097340 [Gating] SW mode calibration
6720 23:56:43.103936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 23:56:43.110283 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 23:56:43.113747 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 23:56:43.117522 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 23:56:43.123947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 23:56:43.127178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 23:56:43.130627 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 23:56:43.136791 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 23:56:43.140869 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 23:56:43.143759 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 23:56:43.150408 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 23:56:43.150495 Total UI for P1: 0, mck2ui 16
6732 23:56:43.156910 best dqsien dly found for B0: ( 0, 14, 24)
6733 23:56:43.156992 Total UI for P1: 0, mck2ui 16
6734 23:56:43.163718 best dqsien dly found for B1: ( 0, 14, 24)
6735 23:56:43.166814 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 23:56:43.170199 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 23:56:43.170276
6738 23:56:43.173498 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 23:56:43.177736 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 23:56:43.180690 [Gating] SW calibration Done
6741 23:56:43.180770 ==
6742 23:56:43.183736 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 23:56:43.187079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 23:56:43.187157 ==
6745 23:56:43.190112 RX Vref Scan: 0
6746 23:56:43.190192
6747 23:56:43.190257 RX Vref 0 -> 0, step: 1
6748 23:56:43.190317
6749 23:56:43.193454 RX Delay -410 -> 252, step: 16
6750 23:56:43.200454 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6751 23:56:43.203968 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6752 23:56:43.207208 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6753 23:56:43.210485 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6754 23:56:43.216718 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6755 23:56:43.220597 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6756 23:56:43.223628 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6757 23:56:43.227043 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6758 23:56:43.233596 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6759 23:56:43.236733 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6760 23:56:43.239959 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6761 23:56:43.243291 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6762 23:56:43.250509 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6763 23:56:43.253542 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6764 23:56:43.256815 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6765 23:56:43.260494 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6766 23:56:43.260613 ==
6767 23:56:43.263408 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 23:56:43.269970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 23:56:43.270076 ==
6770 23:56:43.270171 DQS Delay:
6771 23:56:43.273029 DQS0 = 35, DQS1 = 35
6772 23:56:43.273134 DQM Delay:
6773 23:56:43.276865 DQM0 = 17, DQM1 = 13
6774 23:56:43.276962 DQ Delay:
6775 23:56:43.280046 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6776 23:56:43.283187 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6777 23:56:43.286533 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6778 23:56:43.289566 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6779 23:56:43.289656
6780 23:56:43.289764
6781 23:56:43.289839 ==
6782 23:56:43.292885 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 23:56:43.296706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 23:56:43.296841 ==
6785 23:56:43.296964
6786 23:56:43.297083
6787 23:56:43.299720 TX Vref Scan disable
6788 23:56:43.299835 == TX Byte 0 ==
6789 23:56:43.306202 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 23:56:43.309612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 23:56:43.309698 == TX Byte 1 ==
6792 23:56:43.316565 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 23:56:43.319998 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 23:56:43.320123 ==
6795 23:56:43.323061 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 23:56:43.326034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 23:56:43.326146 ==
6798 23:56:43.326209
6799 23:56:43.326268
6800 23:56:43.329657 TX Vref Scan disable
6801 23:56:43.329763 == TX Byte 0 ==
6802 23:56:43.335972 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 23:56:43.339637 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 23:56:43.339779 == TX Byte 1 ==
6805 23:56:43.346546 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 23:56:43.349688 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 23:56:43.349771
6808 23:56:43.349865 [DATLAT]
6809 23:56:43.353266 Freq=400, CH1 RK0
6810 23:56:43.353382
6811 23:56:43.353477 DATLAT Default: 0xf
6812 23:56:43.356143 0, 0xFFFF, sum = 0
6813 23:56:43.356246 1, 0xFFFF, sum = 0
6814 23:56:43.359599 2, 0xFFFF, sum = 0
6815 23:56:43.359673 3, 0xFFFF, sum = 0
6816 23:56:43.362919 4, 0xFFFF, sum = 0
6817 23:56:43.363003 5, 0xFFFF, sum = 0
6818 23:56:43.366773 6, 0xFFFF, sum = 0
6819 23:56:43.366892 7, 0xFFFF, sum = 0
6820 23:56:43.369680 8, 0xFFFF, sum = 0
6821 23:56:43.369807 9, 0xFFFF, sum = 0
6822 23:56:43.373310 10, 0xFFFF, sum = 0
6823 23:56:43.373392 11, 0xFFFF, sum = 0
6824 23:56:43.376186 12, 0xFFFF, sum = 0
6825 23:56:43.376302 13, 0x0, sum = 1
6826 23:56:43.379539 14, 0x0, sum = 2
6827 23:56:43.379633 15, 0x0, sum = 3
6828 23:56:43.383182 16, 0x0, sum = 4
6829 23:56:43.383294 best_step = 14
6830 23:56:43.383397
6831 23:56:43.383489 ==
6832 23:56:43.386367 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 23:56:43.392748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 23:56:43.392879 ==
6835 23:56:43.392999 RX Vref Scan: 1
6836 23:56:43.393109
6837 23:56:43.396881 RX Vref 0 -> 0, step: 1
6838 23:56:43.396988
6839 23:56:43.399950 RX Delay -311 -> 252, step: 8
6840 23:56:43.400072
6841 23:56:43.402905 Set Vref, RX VrefLevel [Byte0]: 53
6842 23:56:43.406470 [Byte1]: 48
6843 23:56:43.406550
6844 23:56:43.409498 Final RX Vref Byte 0 = 53 to rank0
6845 23:56:43.413240 Final RX Vref Byte 1 = 48 to rank0
6846 23:56:43.416280 Final RX Vref Byte 0 = 53 to rank1
6847 23:56:43.419553 Final RX Vref Byte 1 = 48 to rank1==
6848 23:56:43.423074 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 23:56:43.426310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 23:56:43.429616 ==
6851 23:56:43.429692 DQS Delay:
6852 23:56:43.429755 DQS0 = 32, DQS1 = 32
6853 23:56:43.432913 DQM Delay:
6854 23:56:43.432994 DQM0 = 13, DQM1 = 11
6855 23:56:43.436303 DQ Delay:
6856 23:56:43.439322 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6857 23:56:43.439430 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6858 23:56:43.443142 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6859 23:56:43.446125 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6860 23:56:43.446213
6861 23:56:43.446280
6862 23:56:43.455946 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6863 23:56:43.459912 CH1 RK0: MR19=C0C, MR18=8FC8
6864 23:56:43.465857 CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6865 23:56:43.465946 ==
6866 23:56:43.469535 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 23:56:43.473023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 23:56:43.473108 ==
6869 23:56:43.475847 [Gating] SW mode calibration
6870 23:56:43.482710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 23:56:43.489493 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 23:56:43.492706 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 23:56:43.496021 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 23:56:43.499437 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 23:56:43.505786 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 23:56:43.509703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 23:56:43.512676 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 23:56:43.519529 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 23:56:43.522764 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 23:56:43.526073 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 23:56:43.529154 Total UI for P1: 0, mck2ui 16
6882 23:56:43.532283 best dqsien dly found for B0: ( 0, 14, 24)
6883 23:56:43.535755 Total UI for P1: 0, mck2ui 16
6884 23:56:43.539914 best dqsien dly found for B1: ( 0, 14, 24)
6885 23:56:43.542732 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 23:56:43.546012 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 23:56:43.549692
6888 23:56:43.552479 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 23:56:43.555789 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 23:56:43.559094 [Gating] SW calibration Done
6891 23:56:43.559177 ==
6892 23:56:43.562496 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 23:56:43.565772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 23:56:43.565855 ==
6895 23:56:43.565920 RX Vref Scan: 0
6896 23:56:43.565980
6897 23:56:43.569261 RX Vref 0 -> 0, step: 1
6898 23:56:43.569343
6899 23:56:43.572308 RX Delay -410 -> 252, step: 16
6900 23:56:43.576071 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6901 23:56:43.582363 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6902 23:56:43.585761 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6903 23:56:43.588873 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6904 23:56:43.592470 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6905 23:56:43.598948 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6906 23:56:43.601845 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6907 23:56:43.606063 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6908 23:56:43.609070 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6909 23:56:43.615477 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6910 23:56:43.619031 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6911 23:56:43.622332 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6912 23:56:43.625246 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6913 23:56:43.632159 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6914 23:56:43.635383 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6915 23:56:43.638618 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6916 23:56:43.638701 ==
6917 23:56:43.642435 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 23:56:43.645637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 23:56:43.648704 ==
6920 23:56:43.648787 DQS Delay:
6921 23:56:43.648853 DQS0 = 35, DQS1 = 35
6922 23:56:43.651900 DQM Delay:
6923 23:56:43.651982 DQM0 = 18, DQM1 = 13
6924 23:56:43.655086 DQ Delay:
6925 23:56:43.658636 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6926 23:56:43.658720 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6927 23:56:43.661745 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6928 23:56:43.665290 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6929 23:56:43.665376
6930 23:56:43.668262
6931 23:56:43.668353 ==
6932 23:56:43.671990 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 23:56:43.674829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 23:56:43.674912 ==
6935 23:56:43.674977
6936 23:56:43.675036
6937 23:56:43.678748 TX Vref Scan disable
6938 23:56:43.678831 == TX Byte 0 ==
6939 23:56:43.681905 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6940 23:56:43.688494 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6941 23:56:43.688587 == TX Byte 1 ==
6942 23:56:43.691898 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6943 23:56:43.698434 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6944 23:56:43.698520 ==
6945 23:56:43.701474 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 23:56:43.705119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 23:56:43.705203 ==
6948 23:56:43.705269
6949 23:56:43.705330
6950 23:56:43.707916 TX Vref Scan disable
6951 23:56:43.707998 == TX Byte 0 ==
6952 23:56:43.711298 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6953 23:56:43.717968 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6954 23:56:43.718081 == TX Byte 1 ==
6955 23:56:43.721228 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6956 23:56:43.727984 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6957 23:56:43.728068
6958 23:56:43.728133 [DATLAT]
6959 23:56:43.731415 Freq=400, CH1 RK1
6960 23:56:43.731498
6961 23:56:43.731563 DATLAT Default: 0xe
6962 23:56:43.734263 0, 0xFFFF, sum = 0
6963 23:56:43.734347 1, 0xFFFF, sum = 0
6964 23:56:43.738033 2, 0xFFFF, sum = 0
6965 23:56:43.738117 3, 0xFFFF, sum = 0
6966 23:56:43.741211 4, 0xFFFF, sum = 0
6967 23:56:43.741295 5, 0xFFFF, sum = 0
6968 23:56:43.744355 6, 0xFFFF, sum = 0
6969 23:56:43.744440 7, 0xFFFF, sum = 0
6970 23:56:43.748177 8, 0xFFFF, sum = 0
6971 23:56:43.748261 9, 0xFFFF, sum = 0
6972 23:56:43.751417 10, 0xFFFF, sum = 0
6973 23:56:43.751502 11, 0xFFFF, sum = 0
6974 23:56:43.754328 12, 0xFFFF, sum = 0
6975 23:56:43.754415 13, 0x0, sum = 1
6976 23:56:43.757574 14, 0x0, sum = 2
6977 23:56:43.757653 15, 0x0, sum = 3
6978 23:56:43.761500 16, 0x0, sum = 4
6979 23:56:43.761608 best_step = 14
6980 23:56:43.761699
6981 23:56:43.761786 ==
6982 23:56:43.764713 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 23:56:43.770953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 23:56:43.771059 ==
6985 23:56:43.771156 RX Vref Scan: 0
6986 23:56:43.771243
6987 23:56:43.774797 RX Vref 0 -> 0, step: 1
6988 23:56:43.774898
6989 23:56:43.777976 RX Delay -311 -> 252, step: 8
6990 23:56:43.784784 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6991 23:56:43.787606 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6992 23:56:43.791304 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6993 23:56:43.795198 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6994 23:56:43.801157 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6995 23:56:43.804716 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6996 23:56:43.807954 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6997 23:56:43.811433 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6998 23:56:43.814377 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6999 23:56:43.821096 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7000 23:56:43.824116 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7001 23:56:43.827806 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7002 23:56:43.834510 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7003 23:56:43.837712 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7004 23:56:43.840904 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7005 23:56:43.844204 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7006 23:56:43.844288 ==
7007 23:56:43.847403 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 23:56:43.854500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 23:56:43.854584 ==
7010 23:56:43.854650 DQS Delay:
7011 23:56:43.857656 DQS0 = 28, DQS1 = 36
7012 23:56:43.857739 DQM Delay:
7013 23:56:43.860578 DQM0 = 11, DQM1 = 15
7014 23:56:43.860661 DQ Delay:
7015 23:56:43.864408 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7016 23:56:43.867725 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7017 23:56:43.870880 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7018 23:56:43.873946 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7019 23:56:43.874059
7020 23:56:43.874155
7021 23:56:43.881066 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
7022 23:56:43.884361 CH1 RK1: MR19=C0C, MR18=CB5B
7023 23:56:43.890835 CH1_RK1: MR19=0xC0C, MR18=0xCB5B, DQSOSC=384, MR23=63, INC=400, DEC=267
7024 23:56:43.894348 [RxdqsGatingPostProcess] freq 400
7025 23:56:43.897398 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 23:56:43.900488 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 23:56:43.903714 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 23:56:43.907092 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 23:56:43.910690 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 23:56:43.913777 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 23:56:43.917144 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 23:56:43.920246 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 23:56:43.924021 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 23:56:43.927083 Pre-setting of DQS Precalculation
7035 23:56:43.930176 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 23:56:43.940488 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 23:56:43.947190 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 23:56:43.947275
7039 23:56:43.947341
7040 23:56:43.950239 [Calibration Summary] 800 Mbps
7041 23:56:43.950323 CH 0, Rank 0
7042 23:56:43.953734 SW Impedance : PASS
7043 23:56:43.953821 DUTY Scan : NO K
7044 23:56:43.956909 ZQ Calibration : PASS
7045 23:56:43.960741 Jitter Meter : NO K
7046 23:56:43.960839 CBT Training : PASS
7047 23:56:43.964397 Write leveling : PASS
7048 23:56:43.967475 RX DQS gating : PASS
7049 23:56:43.967579 RX DQ/DQS(RDDQC) : PASS
7050 23:56:43.970329 TX DQ/DQS : PASS
7051 23:56:43.970415 RX DATLAT : PASS
7052 23:56:43.973521 RX DQ/DQS(Engine): PASS
7053 23:56:43.977122 TX OE : NO K
7054 23:56:43.977205 All Pass.
7055 23:56:43.977272
7056 23:56:43.977333 CH 0, Rank 1
7057 23:56:43.980751 SW Impedance : PASS
7058 23:56:43.983729 DUTY Scan : NO K
7059 23:56:43.983819 ZQ Calibration : PASS
7060 23:56:43.986970 Jitter Meter : NO K
7061 23:56:43.990375 CBT Training : PASS
7062 23:56:43.990479 Write leveling : NO K
7063 23:56:43.993518 RX DQS gating : PASS
7064 23:56:43.996865 RX DQ/DQS(RDDQC) : PASS
7065 23:56:43.996947 TX DQ/DQS : PASS
7066 23:56:44.000584 RX DATLAT : PASS
7067 23:56:44.003594 RX DQ/DQS(Engine): PASS
7068 23:56:44.003683 TX OE : NO K
7069 23:56:44.003754 All Pass.
7070 23:56:44.007477
7071 23:56:44.007578 CH 1, Rank 0
7072 23:56:44.010460 SW Impedance : PASS
7073 23:56:44.010559 DUTY Scan : NO K
7074 23:56:44.013539 ZQ Calibration : PASS
7075 23:56:44.016802 Jitter Meter : NO K
7076 23:56:44.016880 CBT Training : PASS
7077 23:56:44.020347 Write leveling : PASS
7078 23:56:44.020424 RX DQS gating : PASS
7079 23:56:44.023319 RX DQ/DQS(RDDQC) : PASS
7080 23:56:44.026996 TX DQ/DQS : PASS
7081 23:56:44.027102 RX DATLAT : PASS
7082 23:56:44.030202 RX DQ/DQS(Engine): PASS
7083 23:56:44.033405 TX OE : NO K
7084 23:56:44.033485 All Pass.
7085 23:56:44.033561
7086 23:56:44.033626 CH 1, Rank 1
7087 23:56:44.036708 SW Impedance : PASS
7088 23:56:44.040298 DUTY Scan : NO K
7089 23:56:44.040397 ZQ Calibration : PASS
7090 23:56:44.043367 Jitter Meter : NO K
7091 23:56:44.046864 CBT Training : PASS
7092 23:56:44.046945 Write leveling : NO K
7093 23:56:44.050210 RX DQS gating : PASS
7094 23:56:44.053306 RX DQ/DQS(RDDQC) : PASS
7095 23:56:44.053390 TX DQ/DQS : PASS
7096 23:56:44.057007 RX DATLAT : PASS
7097 23:56:44.059950 RX DQ/DQS(Engine): PASS
7098 23:56:44.060059 TX OE : NO K
7099 23:56:44.060155 All Pass.
7100 23:56:44.063515
7101 23:56:44.063613 DramC Write-DBI off
7102 23:56:44.067010 PER_BANK_REFRESH: Hybrid Mode
7103 23:56:44.067093 TX_TRACKING: ON
7104 23:56:44.076593 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 23:56:44.080233 [FAST_K] Save calibration result to emmc
7106 23:56:44.083724 dramc_set_vcore_voltage set vcore to 725000
7107 23:56:44.086932 Read voltage for 1600, 0
7108 23:56:44.087017 Vio18 = 0
7109 23:56:44.089990 Vcore = 725000
7110 23:56:44.090094 Vdram = 0
7111 23:56:44.090162 Vddq = 0
7112 23:56:44.090224 Vmddr = 0
7113 23:56:44.097073 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 23:56:44.103473 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 23:56:44.103557 MEM_TYPE=3, freq_sel=13
7116 23:56:44.106460 sv_algorithm_assistance_LP4_3733
7117 23:56:44.110296 ============ PULL DRAM RESETB DOWN ============
7118 23:56:44.116973 ========== PULL DRAM RESETB DOWN end =========
7119 23:56:44.120038 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 23:56:44.123282 ===================================
7121 23:56:44.126471 LPDDR4 DRAM CONFIGURATION
7122 23:56:44.129875 ===================================
7123 23:56:44.129979 EX_ROW_EN[0] = 0x0
7124 23:56:44.133079 EX_ROW_EN[1] = 0x0
7125 23:56:44.133188 LP4Y_EN = 0x0
7126 23:56:44.136464 WORK_FSP = 0x1
7127 23:56:44.136541 WL = 0x5
7128 23:56:44.140067 RL = 0x5
7129 23:56:44.143065 BL = 0x2
7130 23:56:44.143161 RPST = 0x0
7131 23:56:44.146497 RD_PRE = 0x0
7132 23:56:44.146575 WR_PRE = 0x1
7133 23:56:44.150130 WR_PST = 0x1
7134 23:56:44.150226 DBI_WR = 0x0
7135 23:56:44.152844 DBI_RD = 0x0
7136 23:56:44.152932 OTF = 0x1
7137 23:56:44.156296 ===================================
7138 23:56:44.159375 ===================================
7139 23:56:44.162982 ANA top config
7140 23:56:44.166310 ===================================
7141 23:56:44.166391 DLL_ASYNC_EN = 0
7142 23:56:44.169876 ALL_SLAVE_EN = 0
7143 23:56:44.173101 NEW_RANK_MODE = 1
7144 23:56:44.176354 DLL_IDLE_MODE = 1
7145 23:56:44.176438 LP45_APHY_COMB_EN = 1
7146 23:56:44.179655 TX_ODT_DIS = 0
7147 23:56:44.182786 NEW_8X_MODE = 1
7148 23:56:44.186772 ===================================
7149 23:56:44.189303 ===================================
7150 23:56:44.192929 data_rate = 3200
7151 23:56:44.196414 CKR = 1
7152 23:56:44.199724 DQ_P2S_RATIO = 8
7153 23:56:44.202785 ===================================
7154 23:56:44.202884 CA_P2S_RATIO = 8
7155 23:56:44.206059 DQ_CA_OPEN = 0
7156 23:56:44.209277 DQ_SEMI_OPEN = 0
7157 23:56:44.213215 CA_SEMI_OPEN = 0
7158 23:56:44.216234 CA_FULL_RATE = 0
7159 23:56:44.216355 DQ_CKDIV4_EN = 0
7160 23:56:44.219512 CA_CKDIV4_EN = 0
7161 23:56:44.222709 CA_PREDIV_EN = 0
7162 23:56:44.225907 PH8_DLY = 12
7163 23:56:44.229203 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 23:56:44.232444 DQ_AAMCK_DIV = 4
7165 23:56:44.236380 CA_AAMCK_DIV = 4
7166 23:56:44.236511 CA_ADMCK_DIV = 4
7167 23:56:44.239534 DQ_TRACK_CA_EN = 0
7168 23:56:44.242827 CA_PICK = 1600
7169 23:56:44.246126 CA_MCKIO = 1600
7170 23:56:44.249155 MCKIO_SEMI = 0
7171 23:56:44.252972 PLL_FREQ = 3068
7172 23:56:44.255700 DQ_UI_PI_RATIO = 32
7173 23:56:44.255795 CA_UI_PI_RATIO = 0
7174 23:56:44.259332 ===================================
7175 23:56:44.262727 ===================================
7176 23:56:44.265767 memory_type:LPDDR4
7177 23:56:44.269396 GP_NUM : 10
7178 23:56:44.269479 SRAM_EN : 1
7179 23:56:44.272464 MD32_EN : 0
7180 23:56:44.275969 ===================================
7181 23:56:44.279403 [ANA_INIT] >>>>>>>>>>>>>>
7182 23:56:44.282527 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 23:56:44.285894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 23:56:44.289149 ===================================
7185 23:56:44.289233 data_rate = 3200,PCW = 0X7600
7186 23:56:44.292954 ===================================
7187 23:56:44.296088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 23:56:44.302695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 23:56:44.309233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 23:56:44.312882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 23:56:44.316206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 23:56:44.319453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 23:56:44.323034 [ANA_INIT] flow start
7194 23:56:44.323140 [ANA_INIT] PLL >>>>>>>>
7195 23:56:44.326369 [ANA_INIT] PLL <<<<<<<<
7196 23:56:44.329730 [ANA_INIT] MIDPI >>>>>>>>
7197 23:56:44.329806 [ANA_INIT] MIDPI <<<<<<<<
7198 23:56:44.332698 [ANA_INIT] DLL >>>>>>>>
7199 23:56:44.335656 [ANA_INIT] DLL <<<<<<<<
7200 23:56:44.335762 [ANA_INIT] flow end
7201 23:56:44.342949 ============ LP4 DIFF to SE enter ============
7202 23:56:44.346147 ============ LP4 DIFF to SE exit ============
7203 23:56:44.349402 [ANA_INIT] <<<<<<<<<<<<<
7204 23:56:44.352439 [Flow] Enable top DCM control >>>>>
7205 23:56:44.355672 [Flow] Enable top DCM control <<<<<
7206 23:56:44.355771 Enable DLL master slave shuffle
7207 23:56:44.362242 ==============================================================
7208 23:56:44.365943 Gating Mode config
7209 23:56:44.369477 ==============================================================
7210 23:56:44.373119 Config description:
7211 23:56:44.382763 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 23:56:44.389131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 23:56:44.392455 SELPH_MODE 0: By rank 1: By Phase
7214 23:56:44.399053 ==============================================================
7215 23:56:44.402993 GAT_TRACK_EN = 1
7216 23:56:44.405669 RX_GATING_MODE = 2
7217 23:56:44.409044 RX_GATING_TRACK_MODE = 2
7218 23:56:44.412609 SELPH_MODE = 1
7219 23:56:44.412720 PICG_EARLY_EN = 1
7220 23:56:44.415890 VALID_LAT_VALUE = 1
7221 23:56:44.422267 ==============================================================
7222 23:56:44.425744 Enter into Gating configuration >>>>
7223 23:56:44.428928 Exit from Gating configuration <<<<
7224 23:56:44.432476 Enter into DVFS_PRE_config >>>>>
7225 23:56:44.442418 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 23:56:44.445606 Exit from DVFS_PRE_config <<<<<
7227 23:56:44.448967 Enter into PICG configuration >>>>
7228 23:56:44.452160 Exit from PICG configuration <<<<
7229 23:56:44.455404 [RX_INPUT] configuration >>>>>
7230 23:56:44.459206 [RX_INPUT] configuration <<<<<
7231 23:56:44.462805 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 23:56:44.469074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 23:56:44.475949 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 23:56:44.482532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 23:56:44.489005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 23:56:44.492350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 23:56:44.498842 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 23:56:44.502210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 23:56:44.505166 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 23:56:44.508746 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 23:56:44.515688 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 23:56:44.518425 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 23:56:44.521496 ===================================
7244 23:56:44.525031 LPDDR4 DRAM CONFIGURATION
7245 23:56:44.528319 ===================================
7246 23:56:44.528439 EX_ROW_EN[0] = 0x0
7247 23:56:44.531466 EX_ROW_EN[1] = 0x0
7248 23:56:44.531547 LP4Y_EN = 0x0
7249 23:56:44.535076 WORK_FSP = 0x1
7250 23:56:44.535186 WL = 0x5
7251 23:56:44.538501 RL = 0x5
7252 23:56:44.538609 BL = 0x2
7253 23:56:44.541619 RPST = 0x0
7254 23:56:44.541698 RD_PRE = 0x0
7255 23:56:44.545175 WR_PRE = 0x1
7256 23:56:44.548285 WR_PST = 0x1
7257 23:56:44.548402 DBI_WR = 0x0
7258 23:56:44.551613 DBI_RD = 0x0
7259 23:56:44.551688 OTF = 0x1
7260 23:56:44.554777 ===================================
7261 23:56:44.558610 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 23:56:44.562058 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 23:56:44.568770 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 23:56:44.571701 ===================================
7265 23:56:44.574912 LPDDR4 DRAM CONFIGURATION
7266 23:56:44.578624 ===================================
7267 23:56:44.578705 EX_ROW_EN[0] = 0x10
7268 23:56:44.581596 EX_ROW_EN[1] = 0x0
7269 23:56:44.581670 LP4Y_EN = 0x0
7270 23:56:44.584780 WORK_FSP = 0x1
7271 23:56:44.584864 WL = 0x5
7272 23:56:44.588248 RL = 0x5
7273 23:56:44.588381 BL = 0x2
7274 23:56:44.591211 RPST = 0x0
7275 23:56:44.591287 RD_PRE = 0x0
7276 23:56:44.594934 WR_PRE = 0x1
7277 23:56:44.595012 WR_PST = 0x1
7278 23:56:44.598259 DBI_WR = 0x0
7279 23:56:44.598342 DBI_RD = 0x0
7280 23:56:44.601650 OTF = 0x1
7281 23:56:44.604773 ===================================
7282 23:56:44.611191 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 23:56:44.611298 ==
7284 23:56:44.614449 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 23:56:44.618053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 23:56:44.618137 ==
7287 23:56:44.621196 [Duty_Offset_Calibration]
7288 23:56:44.621289 B0:2 B1:1 CA:1
7289 23:56:44.621372
7290 23:56:44.624799 [DutyScan_Calibration_Flow] k_type=0
7291 23:56:44.636001
7292 23:56:44.636086 ==CLK 0==
7293 23:56:44.638987 Final CLK duty delay cell = 0
7294 23:56:44.642310 [0] MAX Duty = 5156%(X100), DQS PI = 22
7295 23:56:44.646160 [0] MIN Duty = 4907%(X100), DQS PI = 0
7296 23:56:44.646276 [0] AVG Duty = 5031%(X100)
7297 23:56:44.649116
7298 23:56:44.652610 CH0 CLK Duty spec in!! Max-Min= 249%
7299 23:56:44.656149 [DutyScan_Calibration_Flow] ====Done====
7300 23:56:44.656252
7301 23:56:44.659453 [DutyScan_Calibration_Flow] k_type=1
7302 23:56:44.675278
7303 23:56:44.675388 ==DQS 0 ==
7304 23:56:44.678469 Final DQS duty delay cell = -4
7305 23:56:44.681786 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7306 23:56:44.684731 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7307 23:56:44.688166 [-4] AVG Duty = 4891%(X100)
7308 23:56:44.688279
7309 23:56:44.688383 ==DQS 1 ==
7310 23:56:44.691740 Final DQS duty delay cell = 0
7311 23:56:44.694615 [0] MAX Duty = 5187%(X100), DQS PI = 10
7312 23:56:44.698267 [0] MIN Duty = 5062%(X100), DQS PI = 30
7313 23:56:44.701507 [0] AVG Duty = 5124%(X100)
7314 23:56:44.701591
7315 23:56:44.704757 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7316 23:56:44.704834
7317 23:56:44.708557 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7318 23:56:44.711715 [DutyScan_Calibration_Flow] ====Done====
7319 23:56:44.711802
7320 23:56:44.714873 [DutyScan_Calibration_Flow] k_type=3
7321 23:56:44.732828
7322 23:56:44.732920 ==DQM 0 ==
7323 23:56:44.736010 Final DQM duty delay cell = 0
7324 23:56:44.739002 [0] MAX Duty = 5187%(X100), DQS PI = 26
7325 23:56:44.742754 [0] MIN Duty = 4875%(X100), DQS PI = 60
7326 23:56:44.742866 [0] AVG Duty = 5031%(X100)
7327 23:56:44.745908
7328 23:56:44.746016 ==DQM 1 ==
7329 23:56:44.748814 Final DQM duty delay cell = 0
7330 23:56:44.752515 [0] MAX Duty = 5187%(X100), DQS PI = 2
7331 23:56:44.755724 [0] MIN Duty = 5031%(X100), DQS PI = 50
7332 23:56:44.759169 [0] AVG Duty = 5109%(X100)
7333 23:56:44.759246
7334 23:56:44.762338 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7335 23:56:44.762449
7336 23:56:44.766130 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7337 23:56:44.768976 [DutyScan_Calibration_Flow] ====Done====
7338 23:56:44.769053
7339 23:56:44.772326 [DutyScan_Calibration_Flow] k_type=2
7340 23:56:44.789455
7341 23:56:44.789569 ==DQ 0 ==
7342 23:56:44.792991 Final DQ duty delay cell = 0
7343 23:56:44.796491 [0] MAX Duty = 5062%(X100), DQS PI = 26
7344 23:56:44.799837 [0] MIN Duty = 4907%(X100), DQS PI = 0
7345 23:56:44.799951 [0] AVG Duty = 4984%(X100)
7346 23:56:44.800046
7347 23:56:44.802742 ==DQ 1 ==
7348 23:56:44.806557 Final DQ duty delay cell = 0
7349 23:56:44.809451 [0] MAX Duty = 5125%(X100), DQS PI = 6
7350 23:56:44.812710 [0] MIN Duty = 4938%(X100), DQS PI = 34
7351 23:56:44.812802 [0] AVG Duty = 5031%(X100)
7352 23:56:44.812874
7353 23:56:44.816564 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7354 23:56:44.816648
7355 23:56:44.819819 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7356 23:56:44.826124 [DutyScan_Calibration_Flow] ====Done====
7357 23:56:44.826208 ==
7358 23:56:44.829744 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 23:56:44.832768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 23:56:44.832852 ==
7361 23:56:44.836523 [Duty_Offset_Calibration]
7362 23:56:44.836609 B0:1 B1:0 CA:0
7363 23:56:44.836676
7364 23:56:44.840068 [DutyScan_Calibration_Flow] k_type=0
7365 23:56:44.848728
7366 23:56:44.848811 ==CLK 0==
7367 23:56:44.852555 Final CLK duty delay cell = -4
7368 23:56:44.855890 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7369 23:56:44.858815 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7370 23:56:44.862215 [-4] AVG Duty = 4906%(X100)
7371 23:56:44.862300
7372 23:56:44.865505 CH1 CLK Duty spec in!! Max-Min= 125%
7373 23:56:44.868626 [DutyScan_Calibration_Flow] ====Done====
7374 23:56:44.868703
7375 23:56:44.871980 [DutyScan_Calibration_Flow] k_type=1
7376 23:56:44.889108
7377 23:56:44.889209 ==DQS 0 ==
7378 23:56:44.892218 Final DQS duty delay cell = 0
7379 23:56:44.896243 [0] MAX Duty = 5094%(X100), DQS PI = 30
7380 23:56:44.899012 [0] MIN Duty = 4844%(X100), DQS PI = 44
7381 23:56:44.899095 [0] AVG Duty = 4969%(X100)
7382 23:56:44.901986
7383 23:56:44.902062 ==DQS 1 ==
7384 23:56:44.905690 Final DQS duty delay cell = 0
7385 23:56:44.909056 [0] MAX Duty = 5249%(X100), DQS PI = 16
7386 23:56:44.912032 [0] MIN Duty = 4938%(X100), DQS PI = 8
7387 23:56:44.915893 [0] AVG Duty = 5093%(X100)
7388 23:56:44.916005
7389 23:56:44.918822 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7390 23:56:44.918934
7391 23:56:44.921938 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7392 23:56:44.925235 [DutyScan_Calibration_Flow] ====Done====
7393 23:56:44.925313
7394 23:56:44.928560 [DutyScan_Calibration_Flow] k_type=3
7395 23:56:44.945867
7396 23:56:44.945960 ==DQM 0 ==
7397 23:56:44.948876 Final DQM duty delay cell = 0
7398 23:56:44.952249 [0] MAX Duty = 5218%(X100), DQS PI = 18
7399 23:56:44.956009 [0] MIN Duty = 4969%(X100), DQS PI = 48
7400 23:56:44.959318 [0] AVG Duty = 5093%(X100)
7401 23:56:44.959420
7402 23:56:44.959514 ==DQM 1 ==
7403 23:56:44.962572 Final DQM duty delay cell = 0
7404 23:56:44.965666 [0] MAX Duty = 5093%(X100), DQS PI = 18
7405 23:56:44.969186 [0] MIN Duty = 4876%(X100), DQS PI = 52
7406 23:56:44.972089 [0] AVG Duty = 4984%(X100)
7407 23:56:44.972193
7408 23:56:44.975763 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7409 23:56:44.975876
7410 23:56:44.979438 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7411 23:56:44.982204 [DutyScan_Calibration_Flow] ====Done====
7412 23:56:44.982285
7413 23:56:44.985456 [DutyScan_Calibration_Flow] k_type=2
7414 23:56:45.002037
7415 23:56:45.002124 ==DQ 0 ==
7416 23:56:45.005140 Final DQ duty delay cell = -4
7417 23:56:45.008294 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7418 23:56:45.011857 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7419 23:56:45.015068 [-4] AVG Duty = 4937%(X100)
7420 23:56:45.015147
7421 23:56:45.015216 ==DQ 1 ==
7422 23:56:45.018638 Final DQ duty delay cell = 0
7423 23:56:45.021557 [0] MAX Duty = 5156%(X100), DQS PI = 18
7424 23:56:45.025465 [0] MIN Duty = 4938%(X100), DQS PI = 8
7425 23:56:45.028189 [0] AVG Duty = 5047%(X100)
7426 23:56:45.028294
7427 23:56:45.031736 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7428 23:56:45.031820
7429 23:56:45.034966 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7430 23:56:45.038130 [DutyScan_Calibration_Flow] ====Done====
7431 23:56:45.041695 nWR fixed to 30
7432 23:56:45.045225 [ModeRegInit_LP4] CH0 RK0
7433 23:56:45.045334 [ModeRegInit_LP4] CH0 RK1
7434 23:56:45.048370 [ModeRegInit_LP4] CH1 RK0
7435 23:56:45.051656 [ModeRegInit_LP4] CH1 RK1
7436 23:56:45.051734 match AC timing 5
7437 23:56:45.058106 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 23:56:45.061907 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 23:56:45.065208 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 23:56:45.071889 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 23:56:45.075136 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 23:56:45.075268 [MiockJmeterHQA]
7443 23:56:45.075385
7444 23:56:45.078553 [DramcMiockJmeter] u1RxGatingPI = 0
7445 23:56:45.081516 0 : 4255, 4027
7446 23:56:45.081642 4 : 4252, 4027
7447 23:56:45.084876 8 : 4368, 4140
7448 23:56:45.085003 12 : 4255, 4026
7449 23:56:45.085118 16 : 4252, 4027
7450 23:56:45.087961 20 : 4363, 4137
7451 23:56:45.088091 24 : 4363, 4138
7452 23:56:45.091805 28 : 4253, 4026
7453 23:56:45.091928 32 : 4363, 4137
7454 23:56:45.094942 36 : 4253, 4027
7455 23:56:45.095065 40 : 4363, 4137
7456 23:56:45.098166 44 : 4252, 4027
7457 23:56:45.098293 48 : 4253, 4027
7458 23:56:45.098410 52 : 4255, 4029
7459 23:56:45.101577 56 : 4253, 4026
7460 23:56:45.101702 60 : 4252, 4027
7461 23:56:45.104629 64 : 4252, 4027
7462 23:56:45.104757 68 : 4252, 4027
7463 23:56:45.108385 72 : 4252, 4027
7464 23:56:45.108505 76 : 4363, 4140
7465 23:56:45.108620 80 : 4252, 4029
7466 23:56:45.111788 84 : 4363, 4140
7467 23:56:45.111914 88 : 4252, 240
7468 23:56:45.114749 92 : 4250, 0
7469 23:56:45.114858 96 : 4255, 0
7470 23:56:45.114953 100 : 4363, 0
7471 23:56:45.118270 104 : 4250, 0
7472 23:56:45.118354 108 : 4250, 0
7473 23:56:45.121143 112 : 4363, 0
7474 23:56:45.121259 116 : 4252, 0
7475 23:56:45.121360 120 : 4250, 0
7476 23:56:45.124942 124 : 4250, 0
7477 23:56:45.125074 128 : 4249, 0
7478 23:56:45.127794 132 : 4250, 0
7479 23:56:45.127907 136 : 4250, 0
7480 23:56:45.128021 140 : 4249, 0
7481 23:56:45.131525 144 : 4250, 0
7482 23:56:45.131647 148 : 4250, 0
7483 23:56:45.134856 152 : 4250, 0
7484 23:56:45.134939 156 : 4250, 0
7485 23:56:45.135005 160 : 4363, 0
7486 23:56:45.138064 164 : 4250, 0
7487 23:56:45.138176 168 : 4361, 0
7488 23:56:45.138272 172 : 4250, 0
7489 23:56:45.141301 176 : 4255, 0
7490 23:56:45.141431 180 : 4250, 0
7491 23:56:45.144312 184 : 4250, 0
7492 23:56:45.144425 188 : 4253, 0
7493 23:56:45.144520 192 : 4249, 0
7494 23:56:45.148064 196 : 4250, 0
7495 23:56:45.148146 200 : 4250, 0
7496 23:56:45.151044 204 : 4250, 1125
7497 23:56:45.151139 208 : 4250, 3972
7498 23:56:45.154572 212 : 4361, 4137
7499 23:56:45.154656 216 : 4250, 4027
7500 23:56:45.157922 220 : 4253, 4027
7501 23:56:45.158053 224 : 4361, 4137
7502 23:56:45.161126 228 : 4250, 4027
7503 23:56:45.161252 232 : 4361, 4138
7504 23:56:45.161372 236 : 4249, 4027
7505 23:56:45.164665 240 : 4250, 4026
7506 23:56:45.164792 244 : 4252, 4027
7507 23:56:45.167735 248 : 4250, 4027
7508 23:56:45.167860 252 : 4254, 4029
7509 23:56:45.171511 256 : 4360, 4137
7510 23:56:45.171635 260 : 4250, 4026
7511 23:56:45.174349 264 : 4250, 4027
7512 23:56:45.174474 268 : 4254, 4029
7513 23:56:45.177889 272 : 4249, 4027
7514 23:56:45.178015 276 : 4363, 4137
7515 23:56:45.181085 280 : 4250, 4027
7516 23:56:45.181211 284 : 4363, 4138
7517 23:56:45.181327 288 : 4250, 4027
7518 23:56:45.184284 292 : 4250, 4026
7519 23:56:45.184419 296 : 4250, 4027
7520 23:56:45.187488 300 : 4250, 4027
7521 23:56:45.187614 304 : 4250, 4027
7522 23:56:45.191389 308 : 4360, 4095
7523 23:56:45.191499 312 : 4250, 2227
7524 23:56:45.194785 316 : 4250, 10
7525 23:56:45.194866
7526 23:56:45.194928 MIOCK jitter meter ch=0
7527 23:56:45.195007
7528 23:56:45.197686 1T = (316-88) = 228 dly cells
7529 23:56:45.204610 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7530 23:56:45.204701 ==
7531 23:56:45.207996 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 23:56:45.211181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 23:56:45.211282 ==
7534 23:56:45.217304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 23:56:45.221222 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 23:56:45.227874 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 23:56:45.230730 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 23:56:45.240677 [CA 0] Center 42 (12~73) winsize 62
7539 23:56:45.244214 [CA 1] Center 42 (12~73) winsize 62
7540 23:56:45.247554 [CA 2] Center 38 (8~68) winsize 61
7541 23:56:45.250693 [CA 3] Center 37 (8~67) winsize 60
7542 23:56:45.254221 [CA 4] Center 36 (6~66) winsize 61
7543 23:56:45.257429 [CA 5] Center 35 (6~64) winsize 59
7544 23:56:45.257506
7545 23:56:45.260839 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7546 23:56:45.260921
7547 23:56:45.264425 [CATrainingPosCal] consider 1 rank data
7548 23:56:45.267566 u2DelayCellTimex100 = 285/100 ps
7549 23:56:45.270691 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7550 23:56:45.277205 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7551 23:56:45.280595 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7552 23:56:45.284525 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7553 23:56:45.287261 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7554 23:56:45.291054 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7555 23:56:45.291139
7556 23:56:45.294020 CA PerBit enable=1, Macro0, CA PI delay=35
7557 23:56:45.294104
7558 23:56:45.297064 [CBTSetCACLKResult] CA Dly = 35
7559 23:56:45.300541 CS Dly: 9 (0~40)
7560 23:56:45.304416 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 23:56:45.307520 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 23:56:45.307605 ==
7563 23:56:45.311135 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 23:56:45.313832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 23:56:45.317175 ==
7566 23:56:45.320571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 23:56:45.324182 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 23:56:45.331145 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 23:56:45.333937 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 23:56:45.344519 [CA 0] Center 42 (12~73) winsize 62
7571 23:56:45.347349 [CA 1] Center 42 (12~73) winsize 62
7572 23:56:45.350944 [CA 2] Center 37 (8~67) winsize 60
7573 23:56:45.354062 [CA 3] Center 37 (7~68) winsize 62
7574 23:56:45.357359 [CA 4] Center 35 (6~65) winsize 60
7575 23:56:45.360757 [CA 5] Center 35 (5~65) winsize 61
7576 23:56:45.360831
7577 23:56:45.364581 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7578 23:56:45.364683
7579 23:56:45.367909 [CATrainingPosCal] consider 2 rank data
7580 23:56:45.370840 u2DelayCellTimex100 = 285/100 ps
7581 23:56:45.374419 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7582 23:56:45.380915 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7583 23:56:45.384053 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7584 23:56:45.387407 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7585 23:56:45.390700 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7586 23:56:45.393957 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7587 23:56:45.394034
7588 23:56:45.397135 CA PerBit enable=1, Macro0, CA PI delay=35
7589 23:56:45.397210
7590 23:56:45.400474 [CBTSetCACLKResult] CA Dly = 35
7591 23:56:45.404526 CS Dly: 10 (0~42)
7592 23:56:45.407478 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 23:56:45.410680 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 23:56:45.410761
7595 23:56:45.413858 ----->DramcWriteLeveling(PI) begin...
7596 23:56:45.413936 ==
7597 23:56:45.417144 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 23:56:45.420635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 23:56:45.424054 ==
7600 23:56:45.424161 Write leveling (Byte 0): 37 => 37
7601 23:56:45.427193 Write leveling (Byte 1): 26 => 26
7602 23:56:45.430407 DramcWriteLeveling(PI) end<-----
7603 23:56:45.430486
7604 23:56:45.430550 ==
7605 23:56:45.434109 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 23:56:45.440741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 23:56:45.440821 ==
7608 23:56:45.440912 [Gating] SW mode calibration
7609 23:56:45.450714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 23:56:45.453776 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 23:56:45.460522 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7612 23:56:45.463659 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 23:56:45.466794 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7614 23:56:45.473604 1 4 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7615 23:56:45.476820 1 4 16 | B1->B0 | 2424 3535 | 0 1 | (0 0) (1 1)
7616 23:56:45.480783 1 4 20 | B1->B0 | 3434 3636 | 0 0 | (0 0) (1 1)
7617 23:56:45.483711 1 4 24 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (1 1)
7618 23:56:45.490226 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7619 23:56:45.493608 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7620 23:56:45.496784 1 5 4 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7621 23:56:45.503896 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 0)
7622 23:56:45.506592 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7623 23:56:45.510295 1 5 16 | B1->B0 | 3434 2f2e | 0 1 | (0 0) (1 0)
7624 23:56:45.516826 1 5 20 | B1->B0 | 2a2a 2b2a | 1 1 | (1 0) (1 1)
7625 23:56:45.520196 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7626 23:56:45.523214 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7627 23:56:45.529477 1 6 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7628 23:56:45.533173 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7629 23:56:45.536237 1 6 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7630 23:56:45.542940 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7631 23:56:45.546100 1 6 16 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7632 23:56:45.549354 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7633 23:56:45.556498 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7634 23:56:45.559554 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 23:56:45.562675 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 23:56:45.569454 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 23:56:45.572536 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 23:56:45.576094 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 23:56:45.582691 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7640 23:56:45.585584 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:56:45.589253 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:56:45.595896 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:56:45.598975 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:56:45.602751 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:56:45.609264 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:56:45.612112 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:56:45.615755 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:56:45.622367 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:56:45.625837 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:56:45.629225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:56:45.635695 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:56:45.639075 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:56:45.642154 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 23:56:45.649260 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 23:56:45.652219 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7656 23:56:45.655480 Total UI for P1: 0, mck2ui 16
7657 23:56:45.658730 best dqsien dly found for B0: ( 1, 9, 10)
7658 23:56:45.662485 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 23:56:45.668774 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 23:56:45.668856 Total UI for P1: 0, mck2ui 16
7661 23:56:45.675340 best dqsien dly found for B1: ( 1, 9, 20)
7662 23:56:45.678659 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7663 23:56:45.682445 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7664 23:56:45.682527
7665 23:56:45.685368 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7666 23:56:45.689018 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7667 23:56:45.692319 [Gating] SW calibration Done
7668 23:56:45.692412 ==
7669 23:56:45.695274 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 23:56:45.698952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 23:56:45.699037 ==
7672 23:56:45.702345 RX Vref Scan: 0
7673 23:56:45.702459
7674 23:56:45.702560 RX Vref 0 -> 0, step: 1
7675 23:56:45.702652
7676 23:56:45.705557 RX Delay 0 -> 252, step: 8
7677 23:56:45.708620 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7678 23:56:45.715740 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7679 23:56:45.718744 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7680 23:56:45.722154 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7681 23:56:45.725683 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7682 23:56:45.729097 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7683 23:56:45.732266 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7684 23:56:45.739174 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7685 23:56:45.742481 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7686 23:56:45.745758 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7687 23:56:45.748915 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7688 23:56:45.752129 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7689 23:56:45.758866 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7690 23:56:45.762321 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7691 23:56:45.765301 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7692 23:56:45.768830 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7693 23:56:45.768970 ==
7694 23:56:45.772003 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 23:56:45.778686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 23:56:45.778824 ==
7697 23:56:45.778958 DQS Delay:
7698 23:56:45.781858 DQS0 = 0, DQS1 = 0
7699 23:56:45.781991 DQM Delay:
7700 23:56:45.782124 DQM0 = 137, DQM1 = 129
7701 23:56:45.785578 DQ Delay:
7702 23:56:45.788778 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7703 23:56:45.792006 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7704 23:56:45.795276 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7705 23:56:45.798682 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7706 23:56:45.798778
7707 23:56:45.798843
7708 23:56:45.798903 ==
7709 23:56:45.801727 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 23:56:45.808236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 23:56:45.808318 ==
7712 23:56:45.808395
7713 23:56:45.808457
7714 23:56:45.808520 TX Vref Scan disable
7715 23:56:45.812131 == TX Byte 0 ==
7716 23:56:45.815626 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7717 23:56:45.818927 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7718 23:56:45.822012 == TX Byte 1 ==
7719 23:56:45.825074 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7720 23:56:45.828228 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7721 23:56:45.831888 ==
7722 23:56:45.835278 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 23:56:45.838226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 23:56:45.838363 ==
7725 23:56:45.851848
7726 23:56:45.855087 TX Vref early break, caculate TX vref
7727 23:56:45.858771 TX Vref=16, minBit 3, minWin=22, winSum=379
7728 23:56:45.861733 TX Vref=18, minBit 0, minWin=23, winSum=385
7729 23:56:45.864967 TX Vref=20, minBit 0, minWin=24, winSum=399
7730 23:56:45.868143 TX Vref=22, minBit 0, minWin=24, winSum=405
7731 23:56:45.871570 TX Vref=24, minBit 7, minWin=24, winSum=412
7732 23:56:45.878122 TX Vref=26, minBit 0, minWin=25, winSum=422
7733 23:56:45.881849 TX Vref=28, minBit 2, minWin=25, winSum=426
7734 23:56:45.884976 TX Vref=30, minBit 0, minWin=25, winSum=414
7735 23:56:45.888366 TX Vref=32, minBit 0, minWin=24, winSum=406
7736 23:56:45.891330 TX Vref=34, minBit 1, minWin=23, winSum=391
7737 23:56:45.898208 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 28
7738 23:56:45.898321
7739 23:56:45.901383 Final TX Range 0 Vref 28
7740 23:56:45.901458
7741 23:56:45.901525 ==
7742 23:56:45.904621 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 23:56:45.908296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 23:56:45.908389 ==
7745 23:56:45.908454
7746 23:56:45.908517
7747 23:56:45.911304 TX Vref Scan disable
7748 23:56:45.918301 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7749 23:56:45.918422 == TX Byte 0 ==
7750 23:56:45.921177 u2DelayCellOfst[0]=13 cells (4 PI)
7751 23:56:45.925015 u2DelayCellOfst[1]=17 cells (5 PI)
7752 23:56:45.928228 u2DelayCellOfst[2]=13 cells (4 PI)
7753 23:56:45.931616 u2DelayCellOfst[3]=10 cells (3 PI)
7754 23:56:45.934696 u2DelayCellOfst[4]=10 cells (3 PI)
7755 23:56:45.937686 u2DelayCellOfst[5]=0 cells (0 PI)
7756 23:56:45.941362 u2DelayCellOfst[6]=20 cells (6 PI)
7757 23:56:45.944570 u2DelayCellOfst[7]=17 cells (5 PI)
7758 23:56:45.947785 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7759 23:56:45.951405 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7760 23:56:45.954311 == TX Byte 1 ==
7761 23:56:45.958420 u2DelayCellOfst[8]=0 cells (0 PI)
7762 23:56:45.958528 u2DelayCellOfst[9]=3 cells (1 PI)
7763 23:56:45.961448 u2DelayCellOfst[10]=10 cells (3 PI)
7764 23:56:45.964852 u2DelayCellOfst[11]=3 cells (1 PI)
7765 23:56:45.967858 u2DelayCellOfst[12]=13 cells (4 PI)
7766 23:56:45.970989 u2DelayCellOfst[13]=10 cells (3 PI)
7767 23:56:45.974772 u2DelayCellOfst[14]=13 cells (4 PI)
7768 23:56:45.977654 u2DelayCellOfst[15]=13 cells (4 PI)
7769 23:56:45.981517 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7770 23:56:45.988221 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7771 23:56:45.988307 DramC Write-DBI on
7772 23:56:45.988396 ==
7773 23:56:45.991173 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 23:56:45.994921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 23:56:45.997707 ==
7776 23:56:45.997782
7777 23:56:45.997845
7778 23:56:45.997903 TX Vref Scan disable
7779 23:56:46.001471 == TX Byte 0 ==
7780 23:56:46.004659 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7781 23:56:46.008282 == TX Byte 1 ==
7782 23:56:46.011515 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7783 23:56:46.014936 DramC Write-DBI off
7784 23:56:46.015040
7785 23:56:46.015141 [DATLAT]
7786 23:56:46.015232 Freq=1600, CH0 RK0
7787 23:56:46.015320
7788 23:56:46.017826 DATLAT Default: 0xf
7789 23:56:46.017940 0, 0xFFFF, sum = 0
7790 23:56:46.021225 1, 0xFFFF, sum = 0
7791 23:56:46.024982 2, 0xFFFF, sum = 0
7792 23:56:46.025088 3, 0xFFFF, sum = 0
7793 23:56:46.028311 4, 0xFFFF, sum = 0
7794 23:56:46.028408 5, 0xFFFF, sum = 0
7795 23:56:46.031595 6, 0xFFFF, sum = 0
7796 23:56:46.031679 7, 0xFFFF, sum = 0
7797 23:56:46.034909 8, 0xFFFF, sum = 0
7798 23:56:46.034993 9, 0xFFFF, sum = 0
7799 23:56:46.038068 10, 0xFFFF, sum = 0
7800 23:56:46.038180 11, 0xFFFF, sum = 0
7801 23:56:46.041336 12, 0xFFFF, sum = 0
7802 23:56:46.041441 13, 0xFFFF, sum = 0
7803 23:56:46.044752 14, 0x0, sum = 1
7804 23:56:46.044838 15, 0x0, sum = 2
7805 23:56:46.047789 16, 0x0, sum = 3
7806 23:56:46.047896 17, 0x0, sum = 4
7807 23:56:46.051182 best_step = 15
7808 23:56:46.051290
7809 23:56:46.051391 ==
7810 23:56:46.054351 Dram Type= 6, Freq= 0, CH_0, rank 0
7811 23:56:46.057678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7812 23:56:46.057783 ==
7813 23:56:46.061484 RX Vref Scan: 1
7814 23:56:46.061576
7815 23:56:46.061664 Set Vref Range= 24 -> 127
7816 23:56:46.061747
7817 23:56:46.064417 RX Vref 24 -> 127, step: 1
7818 23:56:46.064505
7819 23:56:46.068099 RX Delay 19 -> 252, step: 4
7820 23:56:46.068204
7821 23:56:46.071420 Set Vref, RX VrefLevel [Byte0]: 24
7822 23:56:46.074364 [Byte1]: 24
7823 23:56:46.074463
7824 23:56:46.077914 Set Vref, RX VrefLevel [Byte0]: 25
7825 23:56:46.081017 [Byte1]: 25
7826 23:56:46.081122
7827 23:56:46.084382 Set Vref, RX VrefLevel [Byte0]: 26
7828 23:56:46.087569 [Byte1]: 26
7829 23:56:46.091700
7830 23:56:46.091777 Set Vref, RX VrefLevel [Byte0]: 27
7831 23:56:46.095249 [Byte1]: 27
7832 23:56:46.099023
7833 23:56:46.099134 Set Vref, RX VrefLevel [Byte0]: 28
7834 23:56:46.102843 [Byte1]: 28
7835 23:56:46.106721
7836 23:56:46.106845 Set Vref, RX VrefLevel [Byte0]: 29
7837 23:56:46.109959 [Byte1]: 29
7838 23:56:46.114580
7839 23:56:46.114685 Set Vref, RX VrefLevel [Byte0]: 30
7840 23:56:46.117587 [Byte1]: 30
7841 23:56:46.122320
7842 23:56:46.122429 Set Vref, RX VrefLevel [Byte0]: 31
7843 23:56:46.125433 [Byte1]: 31
7844 23:56:46.129316
7845 23:56:46.129402 Set Vref, RX VrefLevel [Byte0]: 32
7846 23:56:46.132738 [Byte1]: 32
7847 23:56:46.137164
7848 23:56:46.137272 Set Vref, RX VrefLevel [Byte0]: 33
7849 23:56:46.140771 [Byte1]: 33
7850 23:56:46.144804
7851 23:56:46.144879 Set Vref, RX VrefLevel [Byte0]: 34
7852 23:56:46.148236 [Byte1]: 34
7853 23:56:46.152503
7854 23:56:46.152591 Set Vref, RX VrefLevel [Byte0]: 35
7855 23:56:46.155483 [Byte1]: 35
7856 23:56:46.160125
7857 23:56:46.160236 Set Vref, RX VrefLevel [Byte0]: 36
7858 23:56:46.163282 [Byte1]: 36
7859 23:56:46.167912
7860 23:56:46.168045 Set Vref, RX VrefLevel [Byte0]: 37
7861 23:56:46.171033 [Byte1]: 37
7862 23:56:46.175127
7863 23:56:46.175253 Set Vref, RX VrefLevel [Byte0]: 38
7864 23:56:46.178283 [Byte1]: 38
7865 23:56:46.182738
7866 23:56:46.182849 Set Vref, RX VrefLevel [Byte0]: 39
7867 23:56:46.185900 [Byte1]: 39
7868 23:56:46.190346
7869 23:56:46.190423 Set Vref, RX VrefLevel [Byte0]: 40
7870 23:56:46.193641 [Byte1]: 40
7871 23:56:46.198160
7872 23:56:46.198240 Set Vref, RX VrefLevel [Byte0]: 41
7873 23:56:46.201356 [Byte1]: 41
7874 23:56:46.205052
7875 23:56:46.205138 Set Vref, RX VrefLevel [Byte0]: 42
7876 23:56:46.208769 [Byte1]: 42
7877 23:56:46.212771
7878 23:56:46.212848 Set Vref, RX VrefLevel [Byte0]: 43
7879 23:56:46.216079 [Byte1]: 43
7880 23:56:46.220628
7881 23:56:46.220710 Set Vref, RX VrefLevel [Byte0]: 44
7882 23:56:46.223953 [Byte1]: 44
7883 23:56:46.228275
7884 23:56:46.228414 Set Vref, RX VrefLevel [Byte0]: 45
7885 23:56:46.231520 [Byte1]: 45
7886 23:56:46.235809
7887 23:56:46.235919 Set Vref, RX VrefLevel [Byte0]: 46
7888 23:56:46.238829 [Byte1]: 46
7889 23:56:46.243092
7890 23:56:46.243175 Set Vref, RX VrefLevel [Byte0]: 47
7891 23:56:46.246264 [Byte1]: 47
7892 23:56:46.250828
7893 23:56:46.250911 Set Vref, RX VrefLevel [Byte0]: 48
7894 23:56:46.254078 [Byte1]: 48
7895 23:56:46.258369
7896 23:56:46.258452 Set Vref, RX VrefLevel [Byte0]: 49
7897 23:56:46.261660 [Byte1]: 49
7898 23:56:46.265774
7899 23:56:46.265901 Set Vref, RX VrefLevel [Byte0]: 50
7900 23:56:46.269080 [Byte1]: 50
7901 23:56:46.273704
7902 23:56:46.273791 Set Vref, RX VrefLevel [Byte0]: 51
7903 23:56:46.276964 [Byte1]: 51
7904 23:56:46.281210
7905 23:56:46.281338 Set Vref, RX VrefLevel [Byte0]: 52
7906 23:56:46.284305 [Byte1]: 52
7907 23:56:46.288489
7908 23:56:46.288599 Set Vref, RX VrefLevel [Byte0]: 53
7909 23:56:46.292581 [Byte1]: 53
7910 23:56:46.296426
7911 23:56:46.296520 Set Vref, RX VrefLevel [Byte0]: 54
7912 23:56:46.299454 [Byte1]: 54
7913 23:56:46.304007
7914 23:56:46.304110 Set Vref, RX VrefLevel [Byte0]: 55
7915 23:56:46.307183 [Byte1]: 55
7916 23:56:46.311471
7917 23:56:46.311589 Set Vref, RX VrefLevel [Byte0]: 56
7918 23:56:46.314712 [Byte1]: 56
7919 23:56:46.319083
7920 23:56:46.319199 Set Vref, RX VrefLevel [Byte0]: 57
7921 23:56:46.322715 [Byte1]: 57
7922 23:56:46.326454
7923 23:56:46.326536 Set Vref, RX VrefLevel [Byte0]: 58
7924 23:56:46.329691 [Byte1]: 58
7925 23:56:46.334216
7926 23:56:46.334345 Set Vref, RX VrefLevel [Byte0]: 59
7927 23:56:46.337769 [Byte1]: 59
7928 23:56:46.341884
7929 23:56:46.341972 Set Vref, RX VrefLevel [Byte0]: 60
7930 23:56:46.345333 [Byte1]: 60
7931 23:56:46.349274
7932 23:56:46.349356 Set Vref, RX VrefLevel [Byte0]: 61
7933 23:56:46.352522 [Byte1]: 61
7934 23:56:46.356489
7935 23:56:46.356573 Set Vref, RX VrefLevel [Byte0]: 62
7936 23:56:46.360213 [Byte1]: 62
7937 23:56:46.364735
7938 23:56:46.364817 Set Vref, RX VrefLevel [Byte0]: 63
7939 23:56:46.367726 [Byte1]: 63
7940 23:56:46.371901
7941 23:56:46.372014 Set Vref, RX VrefLevel [Byte0]: 64
7942 23:56:46.374938 [Byte1]: 64
7943 23:56:46.379944
7944 23:56:46.380051 Set Vref, RX VrefLevel [Byte0]: 65
7945 23:56:46.383021 [Byte1]: 65
7946 23:56:46.387225
7947 23:56:46.387333 Set Vref, RX VrefLevel [Byte0]: 66
7948 23:56:46.390454 [Byte1]: 66
7949 23:56:46.394877
7950 23:56:46.394956 Set Vref, RX VrefLevel [Byte0]: 67
7951 23:56:46.398194 [Byte1]: 67
7952 23:56:46.402138
7953 23:56:46.402244 Set Vref, RX VrefLevel [Byte0]: 68
7954 23:56:46.405218 [Byte1]: 68
7955 23:56:46.409548
7956 23:56:46.409663 Set Vref, RX VrefLevel [Byte0]: 69
7957 23:56:46.413292 [Byte1]: 69
7958 23:56:46.417754
7959 23:56:46.417864 Set Vref, RX VrefLevel [Byte0]: 70
7960 23:56:46.420725 [Byte1]: 70
7961 23:56:46.425299
7962 23:56:46.425402 Set Vref, RX VrefLevel [Byte0]: 71
7963 23:56:46.428450 [Byte1]: 71
7964 23:56:46.432205
7965 23:56:46.432322 Set Vref, RX VrefLevel [Byte0]: 72
7966 23:56:46.435469 [Byte1]: 72
7967 23:56:46.440159
7968 23:56:46.440270 Set Vref, RX VrefLevel [Byte0]: 73
7969 23:56:46.443568 [Byte1]: 73
7970 23:56:46.447598
7971 23:56:46.447702 Set Vref, RX VrefLevel [Byte0]: 74
7972 23:56:46.451031 [Byte1]: 74
7973 23:56:46.455236
7974 23:56:46.455348 Set Vref, RX VrefLevel [Byte0]: 75
7975 23:56:46.458961 [Byte1]: 75
7976 23:56:46.462646
7977 23:56:46.462757 Final RX Vref Byte 0 = 54 to rank0
7978 23:56:46.466374 Final RX Vref Byte 1 = 56 to rank0
7979 23:56:46.469657 Final RX Vref Byte 0 = 54 to rank1
7980 23:56:46.472738 Final RX Vref Byte 1 = 56 to rank1==
7981 23:56:46.476126 Dram Type= 6, Freq= 0, CH_0, rank 0
7982 23:56:46.482798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 23:56:46.482885 ==
7984 23:56:46.482951 DQS Delay:
7985 23:56:46.483013 DQS0 = 0, DQS1 = 0
7986 23:56:46.486466 DQM Delay:
7987 23:56:46.486542 DQM0 = 133, DQM1 = 127
7988 23:56:46.489151 DQ Delay:
7989 23:56:46.493040 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7990 23:56:46.496363 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =138
7991 23:56:46.499574 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7992 23:56:46.502831 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =136
7993 23:56:46.502915
7994 23:56:46.502981
7995 23:56:46.503042
7996 23:56:46.506353 [DramC_TX_OE_Calibration] TA2
7997 23:56:46.509211 Original DQ_B0 (3 6) =30, OEN = 27
7998 23:56:46.512910 Original DQ_B1 (3 6) =30, OEN = 27
7999 23:56:46.516646 24, 0x0, End_B0=24 End_B1=24
8000 23:56:46.516736 25, 0x0, End_B0=25 End_B1=25
8001 23:56:46.519438 26, 0x0, End_B0=26 End_B1=26
8002 23:56:46.522706 27, 0x0, End_B0=27 End_B1=27
8003 23:56:46.526053 28, 0x0, End_B0=28 End_B1=28
8004 23:56:46.526139 29, 0x0, End_B0=29 End_B1=29
8005 23:56:46.529080 30, 0x0, End_B0=30 End_B1=30
8006 23:56:46.532365 31, 0x4141, End_B0=30 End_B1=30
8007 23:56:46.535587 Byte0 end_step=30 best_step=27
8008 23:56:46.538981 Byte1 end_step=30 best_step=27
8009 23:56:46.542218 Byte0 TX OE(2T, 0.5T) = (3, 3)
8010 23:56:46.545443 Byte1 TX OE(2T, 0.5T) = (3, 3)
8011 23:56:46.545522
8012 23:56:46.545591
8013 23:56:46.552564 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8014 23:56:46.555830 CH0 RK0: MR19=303, MR18=2723
8015 23:56:46.562871 CH0_RK0: MR19=0x303, MR18=0x2723, DQSOSC=390, MR23=63, INC=24, DEC=16
8016 23:56:46.562952
8017 23:56:46.565705 ----->DramcWriteLeveling(PI) begin...
8018 23:56:46.565819 ==
8019 23:56:46.569387 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 23:56:46.572354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 23:56:46.572467 ==
8022 23:56:46.575545 Write leveling (Byte 0): 34 => 34
8023 23:56:46.578914 Write leveling (Byte 1): 26 => 26
8024 23:56:46.582293 DramcWriteLeveling(PI) end<-----
8025 23:56:46.582414
8026 23:56:46.582509 ==
8027 23:56:46.585495 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 23:56:46.589366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 23:56:46.589477 ==
8030 23:56:46.592259 [Gating] SW mode calibration
8031 23:56:46.599069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8032 23:56:46.605485 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8033 23:56:46.608783 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 23:56:46.612176 1 4 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8035 23:56:46.618846 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8036 23:56:46.622236 1 4 12 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8037 23:56:46.625477 1 4 16 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)
8038 23:56:46.632254 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8039 23:56:46.635972 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8040 23:56:46.638567 1 4 28 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8041 23:56:46.645625 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8042 23:56:46.648986 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
8043 23:56:46.652158 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8044 23:56:46.658590 1 5 12 | B1->B0 | 3434 3736 | 1 1 | (1 0) (0 1)
8045 23:56:46.662046 1 5 16 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (1 0)
8046 23:56:46.665087 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 23:56:46.671716 1 5 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8048 23:56:46.675313 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8049 23:56:46.678569 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8050 23:56:46.684907 1 6 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8051 23:56:46.688483 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8052 23:56:46.691678 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
8053 23:56:46.698312 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8054 23:56:46.701906 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 23:56:46.705186 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 23:56:46.711882 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 23:56:46.715553 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 23:56:46.718431 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 23:56:46.725193 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 23:56:46.728513 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8061 23:56:46.731802 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8062 23:56:46.735114 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:56:46.741724 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:56:46.744912 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 23:56:46.748984 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:56:46.754974 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 23:56:46.758728 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:56:46.761768 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:56:46.768375 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:56:46.771623 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:56:46.775030 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:56:46.781557 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:56:46.785182 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:56:46.788490 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:56:46.794620 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:56:46.798610 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8077 23:56:46.801708 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8078 23:56:46.808207 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 23:56:46.808291 Total UI for P1: 0, mck2ui 16
8080 23:56:46.814738 best dqsien dly found for B0: ( 1, 9, 14)
8081 23:56:46.814823 Total UI for P1: 0, mck2ui 16
8082 23:56:46.821387 best dqsien dly found for B1: ( 1, 9, 14)
8083 23:56:46.824742 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8084 23:56:46.828319 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8085 23:56:46.828447
8086 23:56:46.831308 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8087 23:56:46.835195 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8088 23:56:46.838036 [Gating] SW calibration Done
8089 23:56:46.838144 ==
8090 23:56:46.841748 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 23:56:46.844816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 23:56:46.844901 ==
8093 23:56:46.848158 RX Vref Scan: 0
8094 23:56:46.848255
8095 23:56:46.848359 RX Vref 0 -> 0, step: 1
8096 23:56:46.848450
8097 23:56:46.851466 RX Delay 0 -> 252, step: 8
8098 23:56:46.854659 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8099 23:56:46.861150 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8100 23:56:46.864685 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8101 23:56:46.868408 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8102 23:56:46.871181 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8103 23:56:46.874839 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8104 23:56:46.881906 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8105 23:56:46.884628 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8106 23:56:46.887814 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8107 23:56:46.891368 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8108 23:56:46.894488 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8109 23:56:46.901370 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8110 23:56:46.904677 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8111 23:56:46.907757 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8112 23:56:46.911152 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8113 23:56:46.914783 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8114 23:56:46.917833 ==
8115 23:56:46.917912 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 23:56:46.924711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 23:56:46.924859 ==
8118 23:56:46.924986 DQS Delay:
8119 23:56:46.927853 DQS0 = 0, DQS1 = 0
8120 23:56:46.927980 DQM Delay:
8121 23:56:46.931086 DQM0 = 136, DQM1 = 128
8122 23:56:46.931223 DQ Delay:
8123 23:56:46.934814 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8124 23:56:46.937796 DQ4 =135, DQ5 =127, DQ6 =139, DQ7 =143
8125 23:56:46.940938 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8126 23:56:46.944495 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8127 23:56:46.944612
8128 23:56:46.944716
8129 23:56:46.944810 ==
8130 23:56:46.947770 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 23:56:46.954143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 23:56:46.954234 ==
8133 23:56:46.954307
8134 23:56:46.954375
8135 23:56:46.954439 TX Vref Scan disable
8136 23:56:46.958229 == TX Byte 0 ==
8137 23:56:46.961310 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8138 23:56:46.967787 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8139 23:56:46.967876 == TX Byte 1 ==
8140 23:56:46.971034 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8141 23:56:46.977433 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8142 23:56:46.977562 ==
8143 23:56:46.981002 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 23:56:46.984539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 23:56:46.984629 ==
8146 23:56:46.997711
8147 23:56:47.001068 TX Vref early break, caculate TX vref
8148 23:56:47.004698 TX Vref=16, minBit 1, minWin=23, winSum=388
8149 23:56:47.007592 TX Vref=18, minBit 1, minWin=23, winSum=393
8150 23:56:47.011255 TX Vref=20, minBit 1, minWin=24, winSum=408
8151 23:56:47.014594 TX Vref=22, minBit 1, minWin=25, winSum=417
8152 23:56:47.017842 TX Vref=24, minBit 1, minWin=25, winSum=421
8153 23:56:47.024077 TX Vref=26, minBit 1, minWin=25, winSum=430
8154 23:56:47.027607 TX Vref=28, minBit 7, minWin=25, winSum=424
8155 23:56:47.030865 TX Vref=30, minBit 1, minWin=25, winSum=417
8156 23:56:47.034157 TX Vref=32, minBit 0, minWin=25, winSum=412
8157 23:56:47.037468 TX Vref=34, minBit 0, minWin=25, winSum=407
8158 23:56:47.044212 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8159 23:56:47.044325
8160 23:56:47.047899 Final TX Range 0 Vref 26
8161 23:56:47.048012
8162 23:56:47.048110 ==
8163 23:56:47.051222 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 23:56:47.054202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 23:56:47.054311 ==
8166 23:56:47.054407
8167 23:56:47.054502
8168 23:56:47.057542 TX Vref Scan disable
8169 23:56:47.064079 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8170 23:56:47.064186 == TX Byte 0 ==
8171 23:56:47.067295 u2DelayCellOfst[0]=13 cells (4 PI)
8172 23:56:47.071083 u2DelayCellOfst[1]=17 cells (5 PI)
8173 23:56:47.074207 u2DelayCellOfst[2]=10 cells (3 PI)
8174 23:56:47.077438 u2DelayCellOfst[3]=10 cells (3 PI)
8175 23:56:47.080860 u2DelayCellOfst[4]=6 cells (2 PI)
8176 23:56:47.084121 u2DelayCellOfst[5]=0 cells (0 PI)
8177 23:56:47.087273 u2DelayCellOfst[6]=13 cells (4 PI)
8178 23:56:47.087357 u2DelayCellOfst[7]=13 cells (4 PI)
8179 23:56:47.094326 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8180 23:56:47.097845 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8181 23:56:47.101074 == TX Byte 1 ==
8182 23:56:47.101175 u2DelayCellOfst[8]=3 cells (1 PI)
8183 23:56:47.104235 u2DelayCellOfst[9]=0 cells (0 PI)
8184 23:56:47.107337 u2DelayCellOfst[10]=6 cells (2 PI)
8185 23:56:47.110950 u2DelayCellOfst[11]=3 cells (1 PI)
8186 23:56:47.114295 u2DelayCellOfst[12]=10 cells (3 PI)
8187 23:56:47.117487 u2DelayCellOfst[13]=10 cells (3 PI)
8188 23:56:47.121039 u2DelayCellOfst[14]=13 cells (4 PI)
8189 23:56:47.124534 u2DelayCellOfst[15]=10 cells (3 PI)
8190 23:56:47.127695 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8191 23:56:47.131160 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8192 23:56:47.134298 DramC Write-DBI on
8193 23:56:47.134379 ==
8194 23:56:47.137397 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 23:56:47.140801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 23:56:47.140887 ==
8197 23:56:47.140956
8198 23:56:47.144185
8199 23:56:47.144300 TX Vref Scan disable
8200 23:56:47.147866 == TX Byte 0 ==
8201 23:56:47.150959 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8202 23:56:47.154064 == TX Byte 1 ==
8203 23:56:47.157180 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8204 23:56:47.157264 DramC Write-DBI off
8205 23:56:47.161055
8206 23:56:47.161138 [DATLAT]
8207 23:56:47.161203 Freq=1600, CH0 RK1
8208 23:56:47.161265
8209 23:56:47.164192 DATLAT Default: 0xf
8210 23:56:47.164276 0, 0xFFFF, sum = 0
8211 23:56:47.167742 1, 0xFFFF, sum = 0
8212 23:56:47.167854 2, 0xFFFF, sum = 0
8213 23:56:47.171073 3, 0xFFFF, sum = 0
8214 23:56:47.174202 4, 0xFFFF, sum = 0
8215 23:56:47.174287 5, 0xFFFF, sum = 0
8216 23:56:47.177733 6, 0xFFFF, sum = 0
8217 23:56:47.177817 7, 0xFFFF, sum = 0
8218 23:56:47.180956 8, 0xFFFF, sum = 0
8219 23:56:47.181069 9, 0xFFFF, sum = 0
8220 23:56:47.183711 10, 0xFFFF, sum = 0
8221 23:56:47.183810 11, 0xFFFF, sum = 0
8222 23:56:47.187138 12, 0xFFFF, sum = 0
8223 23:56:47.187225 13, 0xFFFF, sum = 0
8224 23:56:47.190447 14, 0x0, sum = 1
8225 23:56:47.190566 15, 0x0, sum = 2
8226 23:56:47.193417 16, 0x0, sum = 3
8227 23:56:47.193526 17, 0x0, sum = 4
8228 23:56:47.197202 best_step = 15
8229 23:56:47.197281
8230 23:56:47.197344 ==
8231 23:56:47.200430 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 23:56:47.203727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 23:56:47.203834 ==
8234 23:56:47.207033 RX Vref Scan: 0
8235 23:56:47.207140
8236 23:56:47.207234 RX Vref 0 -> 0, step: 1
8237 23:56:47.207327
8238 23:56:47.210360 RX Delay 19 -> 252, step: 4
8239 23:56:47.213989 iDelay=191, Bit 0, Center 132 (79 ~ 186) 108
8240 23:56:47.220266 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8241 23:56:47.223993 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8242 23:56:47.227222 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8243 23:56:47.230151 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8244 23:56:47.233707 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8245 23:56:47.239918 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8246 23:56:47.243919 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8247 23:56:47.246866 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8248 23:56:47.250188 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8249 23:56:47.253294 iDelay=191, Bit 10, Center 128 (79 ~ 178) 100
8250 23:56:47.260280 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8251 23:56:47.263815 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8252 23:56:47.266690 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8253 23:56:47.270417 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8254 23:56:47.273645 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8255 23:56:47.277353 ==
8256 23:56:47.277438 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 23:56:47.283806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 23:56:47.283890 ==
8259 23:56:47.283955 DQS Delay:
8260 23:56:47.287114 DQS0 = 0, DQS1 = 0
8261 23:56:47.287188 DQM Delay:
8262 23:56:47.290376 DQM0 = 133, DQM1 = 126
8263 23:56:47.290455 DQ Delay:
8264 23:56:47.293623 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =134
8265 23:56:47.297185 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =142
8266 23:56:47.300281 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8267 23:56:47.303184 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =134
8268 23:56:47.303261
8269 23:56:47.303325
8270 23:56:47.303389
8271 23:56:47.306465 [DramC_TX_OE_Calibration] TA2
8272 23:56:47.309812 Original DQ_B0 (3 6) =30, OEN = 27
8273 23:56:47.313208 Original DQ_B1 (3 6) =30, OEN = 27
8274 23:56:47.316282 24, 0x0, End_B0=24 End_B1=24
8275 23:56:47.319838 25, 0x0, End_B0=25 End_B1=25
8276 23:56:47.319921 26, 0x0, End_B0=26 End_B1=26
8277 23:56:47.322912 27, 0x0, End_B0=27 End_B1=27
8278 23:56:47.326667 28, 0x0, End_B0=28 End_B1=28
8279 23:56:47.329924 29, 0x0, End_B0=29 End_B1=29
8280 23:56:47.333134 30, 0x0, End_B0=30 End_B1=30
8281 23:56:47.333246 31, 0x4545, End_B0=30 End_B1=30
8282 23:56:47.336148 Byte0 end_step=30 best_step=27
8283 23:56:47.339829 Byte1 end_step=30 best_step=27
8284 23:56:47.343118 Byte0 TX OE(2T, 0.5T) = (3, 3)
8285 23:56:47.346434 Byte1 TX OE(2T, 0.5T) = (3, 3)
8286 23:56:47.346513
8287 23:56:47.346583
8288 23:56:47.353299 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8289 23:56:47.356664 CH0 RK1: MR19=303, MR18=220B
8290 23:56:47.363034 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8291 23:56:47.366528 [RxdqsGatingPostProcess] freq 1600
8292 23:56:47.372988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8293 23:56:47.373073 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 23:56:47.376255 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 23:56:47.380025 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 23:56:47.383020 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 23:56:47.386466 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 23:56:47.389720 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 23:56:47.393066 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 23:56:47.396447 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 23:56:47.399489 Pre-setting of DQS Precalculation
8302 23:56:47.402752 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8303 23:56:47.402828 ==
8304 23:56:47.406016 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 23:56:47.412972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 23:56:47.413055 ==
8307 23:56:47.416227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 23:56:47.422558 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 23:56:47.426314 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 23:56:47.432974 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 23:56:47.440127 [CA 0] Center 42 (13~72) winsize 60
8312 23:56:47.443894 [CA 1] Center 42 (13~72) winsize 60
8313 23:56:47.446986 [CA 2] Center 39 (10~68) winsize 59
8314 23:56:47.450354 [CA 3] Center 38 (9~68) winsize 60
8315 23:56:47.453316 [CA 4] Center 39 (10~68) winsize 59
8316 23:56:47.457172 [CA 5] Center 37 (8~67) winsize 60
8317 23:56:47.457258
8318 23:56:47.460538 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8319 23:56:47.460625
8320 23:56:47.463933 [CATrainingPosCal] consider 1 rank data
8321 23:56:47.466750 u2DelayCellTimex100 = 285/100 ps
8322 23:56:47.470150 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8323 23:56:47.476773 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8324 23:56:47.480306 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8325 23:56:47.483757 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8326 23:56:47.486974 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8327 23:56:47.490522 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8328 23:56:47.490601
8329 23:56:47.493283 CA PerBit enable=1, Macro0, CA PI delay=37
8330 23:56:47.493360
8331 23:56:47.496942 [CBTSetCACLKResult] CA Dly = 37
8332 23:56:47.500025 CS Dly: 10 (0~41)
8333 23:56:47.503881 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 23:56:47.507176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 23:56:47.507255 ==
8336 23:56:47.510249 Dram Type= 6, Freq= 0, CH_1, rank 1
8337 23:56:47.513398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 23:56:47.516712 ==
8339 23:56:47.519906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 23:56:47.523174 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 23:56:47.530057 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 23:56:47.536724 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 23:56:47.544062 [CA 0] Center 42 (13~72) winsize 60
8344 23:56:47.547128 [CA 1] Center 42 (13~72) winsize 60
8345 23:56:47.550148 [CA 2] Center 39 (10~69) winsize 60
8346 23:56:47.554135 [CA 3] Center 38 (9~68) winsize 60
8347 23:56:47.557094 [CA 4] Center 39 (9~69) winsize 61
8348 23:56:47.560138 [CA 5] Center 38 (9~68) winsize 60
8349 23:56:47.560246
8350 23:56:47.563980 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8351 23:56:47.564086
8352 23:56:47.567403 [CATrainingPosCal] consider 2 rank data
8353 23:56:47.570696 u2DelayCellTimex100 = 285/100 ps
8354 23:56:47.573824 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8355 23:56:47.580646 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8356 23:56:47.584024 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8357 23:56:47.586655 CA3 delay=38 (9~68),Diff = 0 PI (0 cell)
8358 23:56:47.590125 CA4 delay=39 (10~68),Diff = 1 PI (3 cell)
8359 23:56:47.593466 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8360 23:56:47.593585
8361 23:56:47.597134 CA PerBit enable=1, Macro0, CA PI delay=38
8362 23:56:47.597240
8363 23:56:47.600012 [CBTSetCACLKResult] CA Dly = 38
8364 23:56:47.603698 CS Dly: 12 (0~45)
8365 23:56:47.607036 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 23:56:47.610164 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 23:56:47.610269
8368 23:56:47.613662 ----->DramcWriteLeveling(PI) begin...
8369 23:56:47.613740 ==
8370 23:56:47.616878 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 23:56:47.623457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 23:56:47.623542 ==
8373 23:56:47.626699 Write leveling (Byte 0): 24 => 24
8374 23:56:47.630181 Write leveling (Byte 1): 27 => 27
8375 23:56:47.630269 DramcWriteLeveling(PI) end<-----
8376 23:56:47.630335
8377 23:56:47.633139 ==
8378 23:56:47.637151 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 23:56:47.640289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 23:56:47.640403 ==
8381 23:56:47.643237 [Gating] SW mode calibration
8382 23:56:47.649702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8383 23:56:47.653437 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8384 23:56:47.659714 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 23:56:47.663454 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 23:56:47.666436 1 4 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8387 23:56:47.673584 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8388 23:56:47.676723 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 23:56:47.679906 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 23:56:47.686579 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 23:56:47.689787 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 23:56:47.692980 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 23:56:47.699625 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 23:56:47.702780 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8395 23:56:47.706308 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8396 23:56:47.713076 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:56:47.716446 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 23:56:47.719514 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 23:56:47.726286 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 23:56:47.729563 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 23:56:47.733411 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 23:56:47.739811 1 6 8 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
8403 23:56:47.743145 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
8404 23:56:47.746265 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 23:56:47.752527 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:56:47.756345 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 23:56:47.759852 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 23:56:47.762888 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 23:56:47.769142 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 23:56:47.772713 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8411 23:56:47.776103 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8412 23:56:47.783213 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:56:47.786461 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:56:47.789667 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:56:47.796178 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:56:47.799365 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:56:47.802644 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:56:47.809620 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:56:47.812665 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:56:47.815903 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:56:47.823017 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:56:47.826058 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:56:47.829071 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:56:47.835767 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:56:47.839759 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:56:47.842640 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8427 23:56:47.846525 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 23:56:47.853117 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 23:56:47.856298 Total UI for P1: 0, mck2ui 16
8430 23:56:47.859303 best dqsien dly found for B0: ( 1, 9, 12)
8431 23:56:47.862553 Total UI for P1: 0, mck2ui 16
8432 23:56:47.866499 best dqsien dly found for B1: ( 1, 9, 10)
8433 23:56:47.869436 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8434 23:56:47.872564 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8435 23:56:47.872649
8436 23:56:47.876307 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8437 23:56:47.879326 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 23:56:47.882523 [Gating] SW calibration Done
8439 23:56:47.882606 ==
8440 23:56:47.885772 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 23:56:47.889064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 23:56:47.889148 ==
8443 23:56:47.892305 RX Vref Scan: 0
8444 23:56:47.892411
8445 23:56:47.896102 RX Vref 0 -> 0, step: 1
8446 23:56:47.896184
8447 23:56:47.896250 RX Delay 0 -> 252, step: 8
8448 23:56:47.902121 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8449 23:56:47.906101 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8450 23:56:47.909265 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8451 23:56:47.912492 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8452 23:56:47.915791 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96
8453 23:56:47.922587 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8454 23:56:47.925709 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8455 23:56:47.929103 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8456 23:56:47.932574 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8457 23:56:47.935510 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8458 23:56:47.942429 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8459 23:56:47.945607 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8460 23:56:47.948934 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8461 23:56:47.952299 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8462 23:56:47.955620 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8463 23:56:47.962510 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8464 23:56:47.962636 ==
8465 23:56:47.965057 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 23:56:47.968822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 23:56:47.968947 ==
8468 23:56:47.969060 DQS Delay:
8469 23:56:47.971713 DQS0 = 0, DQS1 = 0
8470 23:56:47.971834 DQM Delay:
8471 23:56:47.974851 DQM0 = 136, DQM1 = 132
8472 23:56:47.974956 DQ Delay:
8473 23:56:47.978540 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8474 23:56:47.981761 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8475 23:56:47.984945 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8476 23:56:47.991638 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8477 23:56:47.991749
8478 23:56:47.991845
8479 23:56:47.991937 ==
8480 23:56:47.995001 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 23:56:47.998045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 23:56:47.998142 ==
8483 23:56:47.998233
8484 23:56:47.998322
8485 23:56:48.001286 TX Vref Scan disable
8486 23:56:48.001382 == TX Byte 0 ==
8487 23:56:48.007967 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8488 23:56:48.011788 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8489 23:56:48.011914 == TX Byte 1 ==
8490 23:56:48.018222 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8491 23:56:48.021405 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8492 23:56:48.021526 ==
8493 23:56:48.024704 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 23:56:48.028371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 23:56:48.028496 ==
8496 23:56:48.041528
8497 23:56:48.044764 TX Vref early break, caculate TX vref
8498 23:56:48.048424 TX Vref=16, minBit 9, minWin=22, winSum=380
8499 23:56:48.051265 TX Vref=18, minBit 1, minWin=23, winSum=387
8500 23:56:48.054867 TX Vref=20, minBit 0, minWin=24, winSum=399
8501 23:56:48.058242 TX Vref=22, minBit 1, minWin=24, winSum=408
8502 23:56:48.061839 TX Vref=24, minBit 1, minWin=25, winSum=420
8503 23:56:48.068310 TX Vref=26, minBit 0, minWin=26, winSum=427
8504 23:56:48.071641 TX Vref=28, minBit 2, minWin=25, winSum=425
8505 23:56:48.074735 TX Vref=30, minBit 0, minWin=25, winSum=422
8506 23:56:48.078179 TX Vref=32, minBit 0, minWin=24, winSum=415
8507 23:56:48.081293 TX Vref=34, minBit 0, minWin=24, winSum=402
8508 23:56:48.088157 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8509 23:56:48.088243
8510 23:56:48.091301 Final TX Range 0 Vref 26
8511 23:56:48.091414
8512 23:56:48.091515 ==
8513 23:56:48.094498 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 23:56:48.097944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 23:56:48.098028 ==
8516 23:56:48.098120
8517 23:56:48.098213
8518 23:56:48.101568 TX Vref Scan disable
8519 23:56:48.108078 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8520 23:56:48.108192 == TX Byte 0 ==
8521 23:56:48.111560 u2DelayCellOfst[0]=17 cells (5 PI)
8522 23:56:48.114853 u2DelayCellOfst[1]=10 cells (3 PI)
8523 23:56:48.118185 u2DelayCellOfst[2]=0 cells (0 PI)
8524 23:56:48.121603 u2DelayCellOfst[3]=3 cells (1 PI)
8525 23:56:48.125095 u2DelayCellOfst[4]=10 cells (3 PI)
8526 23:56:48.128058 u2DelayCellOfst[5]=17 cells (5 PI)
8527 23:56:48.131290 u2DelayCellOfst[6]=17 cells (5 PI)
8528 23:56:48.131374 u2DelayCellOfst[7]=3 cells (1 PI)
8529 23:56:48.137947 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8530 23:56:48.141385 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8531 23:56:48.141475 == TX Byte 1 ==
8532 23:56:48.144347 u2DelayCellOfst[8]=0 cells (0 PI)
8533 23:56:48.148096 u2DelayCellOfst[9]=3 cells (1 PI)
8534 23:56:48.151313 u2DelayCellOfst[10]=13 cells (4 PI)
8535 23:56:48.154613 u2DelayCellOfst[11]=3 cells (1 PI)
8536 23:56:48.157783 u2DelayCellOfst[12]=13 cells (4 PI)
8537 23:56:48.161107 u2DelayCellOfst[13]=17 cells (5 PI)
8538 23:56:48.164305 u2DelayCellOfst[14]=17 cells (5 PI)
8539 23:56:48.167878 u2DelayCellOfst[15]=17 cells (5 PI)
8540 23:56:48.171751 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8541 23:56:48.177880 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8542 23:56:48.178003 DramC Write-DBI on
8543 23:56:48.178115 ==
8544 23:56:48.181121 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 23:56:48.184451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 23:56:48.184573 ==
8547 23:56:48.187634
8548 23:56:48.187751
8549 23:56:48.187863 TX Vref Scan disable
8550 23:56:48.191388 == TX Byte 0 ==
8551 23:56:48.194496 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8552 23:56:48.197416 == TX Byte 1 ==
8553 23:56:48.201147 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8554 23:56:48.201252 DramC Write-DBI off
8555 23:56:48.204182
8556 23:56:48.204281 [DATLAT]
8557 23:56:48.204385 Freq=1600, CH1 RK0
8558 23:56:48.204475
8559 23:56:48.207433 DATLAT Default: 0xf
8560 23:56:48.207509 0, 0xFFFF, sum = 0
8561 23:56:48.210656 1, 0xFFFF, sum = 0
8562 23:56:48.210760 2, 0xFFFF, sum = 0
8563 23:56:48.214480 3, 0xFFFF, sum = 0
8564 23:56:48.214580 4, 0xFFFF, sum = 0
8565 23:56:48.217525 5, 0xFFFF, sum = 0
8566 23:56:48.221098 6, 0xFFFF, sum = 0
8567 23:56:48.221178 7, 0xFFFF, sum = 0
8568 23:56:48.224333 8, 0xFFFF, sum = 0
8569 23:56:48.224419 9, 0xFFFF, sum = 0
8570 23:56:48.227581 10, 0xFFFF, sum = 0
8571 23:56:48.227661 11, 0xFFFF, sum = 0
8572 23:56:48.230940 12, 0xFFFF, sum = 0
8573 23:56:48.231042 13, 0xFFFF, sum = 0
8574 23:56:48.234192 14, 0x0, sum = 1
8575 23:56:48.234271 15, 0x0, sum = 2
8576 23:56:48.237347 16, 0x0, sum = 3
8577 23:56:48.237444 17, 0x0, sum = 4
8578 23:56:48.241107 best_step = 15
8579 23:56:48.241215
8580 23:56:48.241317 ==
8581 23:56:48.244311 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 23:56:48.247494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 23:56:48.247599 ==
8584 23:56:48.247701 RX Vref Scan: 1
8585 23:56:48.250758
8586 23:56:48.250843 Set Vref Range= 24 -> 127
8587 23:56:48.250911
8588 23:56:48.254608 RX Vref 24 -> 127, step: 1
8589 23:56:48.254683
8590 23:56:48.257707 RX Delay 27 -> 252, step: 4
8591 23:56:48.257787
8592 23:56:48.260885 Set Vref, RX VrefLevel [Byte0]: 24
8593 23:56:48.264180 [Byte1]: 24
8594 23:56:48.264283
8595 23:56:48.267314 Set Vref, RX VrefLevel [Byte0]: 25
8596 23:56:48.270476 [Byte1]: 25
8597 23:56:48.270583
8598 23:56:48.274376 Set Vref, RX VrefLevel [Byte0]: 26
8599 23:56:48.277376 [Byte1]: 26
8600 23:56:48.281378
8601 23:56:48.281458 Set Vref, RX VrefLevel [Byte0]: 27
8602 23:56:48.284362 [Byte1]: 27
8603 23:56:48.288505
8604 23:56:48.288580 Set Vref, RX VrefLevel [Byte0]: 28
8605 23:56:48.292238 [Byte1]: 28
8606 23:56:48.296087
8607 23:56:48.296186 Set Vref, RX VrefLevel [Byte0]: 29
8608 23:56:48.299252 [Byte1]: 29
8609 23:56:48.303720
8610 23:56:48.303805 Set Vref, RX VrefLevel [Byte0]: 30
8611 23:56:48.307263 [Byte1]: 30
8612 23:56:48.310856
8613 23:56:48.310972 Set Vref, RX VrefLevel [Byte0]: 31
8614 23:56:48.314347 [Byte1]: 31
8615 23:56:48.318850
8616 23:56:48.318959 Set Vref, RX VrefLevel [Byte0]: 32
8617 23:56:48.322482 [Byte1]: 32
8618 23:56:48.326089
8619 23:56:48.326172 Set Vref, RX VrefLevel [Byte0]: 33
8620 23:56:48.329482 [Byte1]: 33
8621 23:56:48.333740
8622 23:56:48.333834 Set Vref, RX VrefLevel [Byte0]: 34
8623 23:56:48.336947 [Byte1]: 34
8624 23:56:48.341593
8625 23:56:48.341676 Set Vref, RX VrefLevel [Byte0]: 35
8626 23:56:48.344571 [Byte1]: 35
8627 23:56:48.348829
8628 23:56:48.348930 Set Vref, RX VrefLevel [Byte0]: 36
8629 23:56:48.352310 [Byte1]: 36
8630 23:56:48.356733
8631 23:56:48.356817 Set Vref, RX VrefLevel [Byte0]: 37
8632 23:56:48.359848 [Byte1]: 37
8633 23:56:48.363675
8634 23:56:48.363758 Set Vref, RX VrefLevel [Byte0]: 38
8635 23:56:48.366967 [Byte1]: 38
8636 23:56:48.371425
8637 23:56:48.371537 Set Vref, RX VrefLevel [Byte0]: 39
8638 23:56:48.374701 [Byte1]: 39
8639 23:56:48.378957
8640 23:56:48.379041 Set Vref, RX VrefLevel [Byte0]: 40
8641 23:56:48.382652 [Byte1]: 40
8642 23:56:48.386215
8643 23:56:48.386300 Set Vref, RX VrefLevel [Byte0]: 41
8644 23:56:48.390034 [Byte1]: 41
8645 23:56:48.394041
8646 23:56:48.394124 Set Vref, RX VrefLevel [Byte0]: 42
8647 23:56:48.397239 [Byte1]: 42
8648 23:56:48.401794
8649 23:56:48.401910 Set Vref, RX VrefLevel [Byte0]: 43
8650 23:56:48.404857 [Byte1]: 43
8651 23:56:48.408772
8652 23:56:48.408848 Set Vref, RX VrefLevel [Byte0]: 44
8653 23:56:48.412539 [Byte1]: 44
8654 23:56:48.417068
8655 23:56:48.417151 Set Vref, RX VrefLevel [Byte0]: 45
8656 23:56:48.419762 [Byte1]: 45
8657 23:56:48.424405
8658 23:56:48.424495 Set Vref, RX VrefLevel [Byte0]: 46
8659 23:56:48.427328 [Byte1]: 46
8660 23:56:48.432078
8661 23:56:48.432186 Set Vref, RX VrefLevel [Byte0]: 47
8662 23:56:48.434718 [Byte1]: 47
8663 23:56:48.439205
8664 23:56:48.439282 Set Vref, RX VrefLevel [Byte0]: 48
8665 23:56:48.442957 [Byte1]: 48
8666 23:56:48.446951
8667 23:56:48.447034 Set Vref, RX VrefLevel [Byte0]: 49
8668 23:56:48.449950 [Byte1]: 49
8669 23:56:48.454375
8670 23:56:48.454460 Set Vref, RX VrefLevel [Byte0]: 50
8671 23:56:48.457935 [Byte1]: 50
8672 23:56:48.461899
8673 23:56:48.461986 Set Vref, RX VrefLevel [Byte0]: 51
8674 23:56:48.465283 [Byte1]: 51
8675 23:56:48.469662
8676 23:56:48.469745 Set Vref, RX VrefLevel [Byte0]: 52
8677 23:56:48.472887 [Byte1]: 52
8678 23:56:48.476660
8679 23:56:48.476742 Set Vref, RX VrefLevel [Byte0]: 53
8680 23:56:48.480499 [Byte1]: 53
8681 23:56:48.484311
8682 23:56:48.484405 Set Vref, RX VrefLevel [Byte0]: 54
8683 23:56:48.487563 [Byte1]: 54
8684 23:56:48.491894
8685 23:56:48.491967 Set Vref, RX VrefLevel [Byte0]: 55
8686 23:56:48.495106 [Byte1]: 55
8687 23:56:48.499974
8688 23:56:48.500046 Set Vref, RX VrefLevel [Byte0]: 56
8689 23:56:48.503009 [Byte1]: 56
8690 23:56:48.507341
8691 23:56:48.507450 Set Vref, RX VrefLevel [Byte0]: 57
8692 23:56:48.509997 [Byte1]: 57
8693 23:56:48.514792
8694 23:56:48.514896 Set Vref, RX VrefLevel [Byte0]: 58
8695 23:56:48.517752 [Byte1]: 58
8696 23:56:48.522143
8697 23:56:48.522245 Set Vref, RX VrefLevel [Byte0]: 59
8698 23:56:48.525295 [Byte1]: 59
8699 23:56:48.529782
8700 23:56:48.529861 Set Vref, RX VrefLevel [Byte0]: 60
8701 23:56:48.533208 [Byte1]: 60
8702 23:56:48.537345
8703 23:56:48.537428 Set Vref, RX VrefLevel [Byte0]: 61
8704 23:56:48.540420 [Byte1]: 61
8705 23:56:48.544867
8706 23:56:48.544950 Set Vref, RX VrefLevel [Byte0]: 62
8707 23:56:48.548161 [Byte1]: 62
8708 23:56:48.552119
8709 23:56:48.552231 Set Vref, RX VrefLevel [Byte0]: 63
8710 23:56:48.555551 [Byte1]: 63
8711 23:56:48.559881
8712 23:56:48.559965 Set Vref, RX VrefLevel [Byte0]: 64
8713 23:56:48.563112 [Byte1]: 64
8714 23:56:48.567318
8715 23:56:48.567431 Set Vref, RX VrefLevel [Byte0]: 65
8716 23:56:48.570415 [Byte1]: 65
8717 23:56:48.574613
8718 23:56:48.574688 Set Vref, RX VrefLevel [Byte0]: 66
8719 23:56:48.578017 [Byte1]: 66
8720 23:56:48.582234
8721 23:56:48.582317 Set Vref, RX VrefLevel [Byte0]: 67
8722 23:56:48.585566 [Byte1]: 67
8723 23:56:48.589851
8724 23:56:48.589935 Set Vref, RX VrefLevel [Byte0]: 68
8725 23:56:48.593043 [Byte1]: 68
8726 23:56:48.597550
8727 23:56:48.597633 Set Vref, RX VrefLevel [Byte0]: 69
8728 23:56:48.600926 [Byte1]: 69
8729 23:56:48.605230
8730 23:56:48.605313 Set Vref, RX VrefLevel [Byte0]: 70
8731 23:56:48.608589 [Byte1]: 70
8732 23:56:48.612443
8733 23:56:48.612527 Set Vref, RX VrefLevel [Byte0]: 71
8734 23:56:48.615937 [Byte1]: 71
8735 23:56:48.619817
8736 23:56:48.619927 Set Vref, RX VrefLevel [Byte0]: 72
8737 23:56:48.623084 [Byte1]: 72
8738 23:56:48.627771
8739 23:56:48.627854 Set Vref, RX VrefLevel [Byte0]: 73
8740 23:56:48.630629 [Byte1]: 73
8741 23:56:48.634892
8742 23:56:48.635002 Set Vref, RX VrefLevel [Byte0]: 74
8743 23:56:48.638062 [Byte1]: 74
8744 23:56:48.642556
8745 23:56:48.642663 Set Vref, RX VrefLevel [Byte0]: 75
8746 23:56:48.645700 [Byte1]: 75
8747 23:56:48.650509
8748 23:56:48.650592 Set Vref, RX VrefLevel [Byte0]: 76
8749 23:56:48.653555 [Byte1]: 76
8750 23:56:48.657757
8751 23:56:48.657866 Set Vref, RX VrefLevel [Byte0]: 77
8752 23:56:48.660786 [Byte1]: 77
8753 23:56:48.664925
8754 23:56:48.665008 Set Vref, RX VrefLevel [Byte0]: 78
8755 23:56:48.668310 [Byte1]: 78
8756 23:56:48.672652
8757 23:56:48.672735 Final RX Vref Byte 0 = 58 to rank0
8758 23:56:48.675734 Final RX Vref Byte 1 = 55 to rank0
8759 23:56:48.679578 Final RX Vref Byte 0 = 58 to rank1
8760 23:56:48.682503 Final RX Vref Byte 1 = 55 to rank1==
8761 23:56:48.686507 Dram Type= 6, Freq= 0, CH_1, rank 0
8762 23:56:48.693021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 23:56:48.693140 ==
8764 23:56:48.693236 DQS Delay:
8765 23:56:48.693327 DQS0 = 0, DQS1 = 0
8766 23:56:48.695969 DQM Delay:
8767 23:56:48.696075 DQM0 = 134, DQM1 = 131
8768 23:56:48.699129 DQ Delay:
8769 23:56:48.702349 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8770 23:56:48.705520 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8771 23:56:48.709378 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8772 23:56:48.712312 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8773 23:56:48.712450
8774 23:56:48.712568
8775 23:56:48.712681
8776 23:56:48.716255 [DramC_TX_OE_Calibration] TA2
8777 23:56:48.719043 Original DQ_B0 (3 6) =30, OEN = 27
8778 23:56:48.722837 Original DQ_B1 (3 6) =30, OEN = 27
8779 23:56:48.725416 24, 0x0, End_B0=24 End_B1=24
8780 23:56:48.725523 25, 0x0, End_B0=25 End_B1=25
8781 23:56:48.729490 26, 0x0, End_B0=26 End_B1=26
8782 23:56:48.732709 27, 0x0, End_B0=27 End_B1=27
8783 23:56:48.735743 28, 0x0, End_B0=28 End_B1=28
8784 23:56:48.735851 29, 0x0, End_B0=29 End_B1=29
8785 23:56:48.739657 30, 0x0, End_B0=30 End_B1=30
8786 23:56:48.742478 31, 0x4545, End_B0=30 End_B1=30
8787 23:56:48.745711 Byte0 end_step=30 best_step=27
8788 23:56:48.749047 Byte1 end_step=30 best_step=27
8789 23:56:48.752551 Byte0 TX OE(2T, 0.5T) = (3, 3)
8790 23:56:48.752670 Byte1 TX OE(2T, 0.5T) = (3, 3)
8791 23:56:48.756041
8792 23:56:48.756160
8793 23:56:48.762477 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8794 23:56:48.765707 CH1 RK0: MR19=303, MR18=1523
8795 23:56:48.772152 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8796 23:56:48.772281
8797 23:56:48.775766 ----->DramcWriteLeveling(PI) begin...
8798 23:56:48.775886 ==
8799 23:56:48.778830 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 23:56:48.782053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 23:56:48.782181 ==
8802 23:56:48.785256 Write leveling (Byte 0): 24 => 24
8803 23:56:48.789142 Write leveling (Byte 1): 29 => 29
8804 23:56:48.792417 DramcWriteLeveling(PI) end<-----
8805 23:56:48.792496
8806 23:56:48.792559 ==
8807 23:56:48.795579 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 23:56:48.798711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 23:56:48.798783 ==
8810 23:56:48.802013 [Gating] SW mode calibration
8811 23:56:48.808903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8812 23:56:48.815525 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8813 23:56:48.818794 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 23:56:48.821972 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 23:56:48.828432 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8816 23:56:48.831889 1 4 12 | B1->B0 | 3434 3130 | 1 1 | (1 1) (1 1)
8817 23:56:48.835164 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 23:56:48.842147 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 23:56:48.845053 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 23:56:48.848326 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 23:56:48.855157 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 23:56:48.858471 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8823 23:56:48.861743 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8824 23:56:48.868832 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8825 23:56:48.872010 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 23:56:48.875295 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 23:56:48.881990 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 23:56:48.885137 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 23:56:48.888291 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 23:56:48.894756 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8831 23:56:48.898128 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8832 23:56:48.901336 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8833 23:56:48.908737 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 23:56:48.911833 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 23:56:48.915105 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 23:56:48.921765 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 23:56:48.925462 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 23:56:48.928274 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8839 23:56:48.935216 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8840 23:56:48.938430 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8841 23:56:48.941428 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8842 23:56:48.948153 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 23:56:48.951415 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 23:56:48.954871 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 23:56:48.961280 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 23:56:48.964669 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 23:56:48.968287 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 23:56:48.971782 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 23:56:48.978093 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 23:56:48.981100 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 23:56:48.984913 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 23:56:48.991551 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 23:56:48.994337 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 23:56:48.998038 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8855 23:56:49.004469 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8856 23:56:49.007734 Total UI for P1: 0, mck2ui 16
8857 23:56:49.010972 best dqsien dly found for B1: ( 1, 9, 4)
8858 23:56:49.014249 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8859 23:56:49.018164 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 23:56:49.021197 Total UI for P1: 0, mck2ui 16
8861 23:56:49.024334 best dqsien dly found for B0: ( 1, 9, 10)
8862 23:56:49.027612 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8863 23:56:49.031418 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8864 23:56:49.031496
8865 23:56:49.037576 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8866 23:56:49.041409 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8867 23:56:49.044458 [Gating] SW calibration Done
8868 23:56:49.044530 ==
8869 23:56:49.047483 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 23:56:49.051519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 23:56:49.051597 ==
8872 23:56:49.051660 RX Vref Scan: 0
8873 23:56:49.051724
8874 23:56:49.054252 RX Vref 0 -> 0, step: 1
8875 23:56:49.054325
8876 23:56:49.057742 RX Delay 0 -> 252, step: 8
8877 23:56:49.060603 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8878 23:56:49.064323 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8879 23:56:49.071060 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8880 23:56:49.074334 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8881 23:56:49.077442 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8882 23:56:49.080611 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8883 23:56:49.084202 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8884 23:56:49.090412 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8885 23:56:49.094209 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8886 23:56:49.097326 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8887 23:56:49.100617 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8888 23:56:49.103808 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8889 23:56:49.110892 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8890 23:56:49.114100 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8891 23:56:49.117386 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8892 23:56:49.120618 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8893 23:56:49.120729 ==
8894 23:56:49.123868 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 23:56:49.130519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 23:56:49.130603 ==
8897 23:56:49.130669 DQS Delay:
8898 23:56:49.133891 DQS0 = 0, DQS1 = 0
8899 23:56:49.133977 DQM Delay:
8900 23:56:49.134043 DQM0 = 136, DQM1 = 133
8901 23:56:49.136928 DQ Delay:
8902 23:56:49.140424 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8903 23:56:49.144000 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8904 23:56:49.146948 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8905 23:56:49.150543 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8906 23:56:49.150627
8907 23:56:49.150693
8908 23:56:49.150753 ==
8909 23:56:49.153735 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 23:56:49.156923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 23:56:49.160127 ==
8912 23:56:49.160210
8913 23:56:49.160276
8914 23:56:49.160344 TX Vref Scan disable
8915 23:56:49.163757 == TX Byte 0 ==
8916 23:56:49.166727 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8917 23:56:49.170600 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8918 23:56:49.173854 == TX Byte 1 ==
8919 23:56:49.177008 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8920 23:56:49.180300 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8921 23:56:49.180414 ==
8922 23:56:49.183809 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 23:56:49.190197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 23:56:49.190302 ==
8925 23:56:49.202123
8926 23:56:49.205603 TX Vref early break, caculate TX vref
8927 23:56:49.209377 TX Vref=16, minBit 0, minWin=23, winSum=386
8928 23:56:49.212170 TX Vref=18, minBit 0, minWin=23, winSum=391
8929 23:56:49.215407 TX Vref=20, minBit 0, minWin=23, winSum=400
8930 23:56:49.219210 TX Vref=22, minBit 0, minWin=25, winSum=412
8931 23:56:49.222274 TX Vref=24, minBit 6, minWin=24, winSum=416
8932 23:56:49.229375 TX Vref=26, minBit 0, minWin=26, winSum=429
8933 23:56:49.232262 TX Vref=28, minBit 6, minWin=25, winSum=428
8934 23:56:49.235436 TX Vref=30, minBit 0, minWin=25, winSum=418
8935 23:56:49.238681 TX Vref=32, minBit 0, minWin=24, winSum=412
8936 23:56:49.242108 TX Vref=34, minBit 0, minWin=24, winSum=406
8937 23:56:49.248848 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8938 23:56:49.248936
8939 23:56:49.252012 Final TX Range 0 Vref 26
8940 23:56:49.252112
8941 23:56:49.252210 ==
8942 23:56:49.255915 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 23:56:49.258736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 23:56:49.258849 ==
8945 23:56:49.258947
8946 23:56:49.259044
8947 23:56:49.261962 TX Vref Scan disable
8948 23:56:49.269164 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8949 23:56:49.269259 == TX Byte 0 ==
8950 23:56:49.272418 u2DelayCellOfst[0]=17 cells (5 PI)
8951 23:56:49.275236 u2DelayCellOfst[1]=10 cells (3 PI)
8952 23:56:49.278555 u2DelayCellOfst[2]=0 cells (0 PI)
8953 23:56:49.282044 u2DelayCellOfst[3]=6 cells (2 PI)
8954 23:56:49.285105 u2DelayCellOfst[4]=10 cells (3 PI)
8955 23:56:49.288914 u2DelayCellOfst[5]=17 cells (5 PI)
8956 23:56:49.292212 u2DelayCellOfst[6]=17 cells (5 PI)
8957 23:56:49.292285 u2DelayCellOfst[7]=6 cells (2 PI)
8958 23:56:49.298740 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8959 23:56:49.301860 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8960 23:56:49.301950 == TX Byte 1 ==
8961 23:56:49.305510 u2DelayCellOfst[8]=0 cells (0 PI)
8962 23:56:49.308657 u2DelayCellOfst[9]=6 cells (2 PI)
8963 23:56:49.312153 u2DelayCellOfst[10]=13 cells (4 PI)
8964 23:56:49.315185 u2DelayCellOfst[11]=10 cells (3 PI)
8965 23:56:49.318541 u2DelayCellOfst[12]=17 cells (5 PI)
8966 23:56:49.321737 u2DelayCellOfst[13]=17 cells (5 PI)
8967 23:56:49.325607 u2DelayCellOfst[14]=20 cells (6 PI)
8968 23:56:49.328904 u2DelayCellOfst[15]=20 cells (6 PI)
8969 23:56:49.332113 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8970 23:56:49.338595 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8971 23:56:49.338699 DramC Write-DBI on
8972 23:56:49.338791 ==
8973 23:56:49.342167 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 23:56:49.345179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 23:56:49.345253 ==
8976 23:56:49.348983
8977 23:56:49.349056
8978 23:56:49.349118 TX Vref Scan disable
8979 23:56:49.352269 == TX Byte 0 ==
8980 23:56:49.355257 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8981 23:56:49.358337 == TX Byte 1 ==
8982 23:56:49.361978 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8983 23:56:49.364902 DramC Write-DBI off
8984 23:56:49.364995
8985 23:56:49.365060 [DATLAT]
8986 23:56:49.365120 Freq=1600, CH1 RK1
8987 23:56:49.365179
8988 23:56:49.368584 DATLAT Default: 0xf
8989 23:56:49.368685 0, 0xFFFF, sum = 0
8990 23:56:49.371823 1, 0xFFFF, sum = 0
8991 23:56:49.371928 2, 0xFFFF, sum = 0
8992 23:56:49.375317 3, 0xFFFF, sum = 0
8993 23:56:49.378983 4, 0xFFFF, sum = 0
8994 23:56:49.379090 5, 0xFFFF, sum = 0
8995 23:56:49.381489 6, 0xFFFF, sum = 0
8996 23:56:49.381603 7, 0xFFFF, sum = 0
8997 23:56:49.384920 8, 0xFFFF, sum = 0
8998 23:56:49.385038 9, 0xFFFF, sum = 0
8999 23:56:49.388105 10, 0xFFFF, sum = 0
9000 23:56:49.388223 11, 0xFFFF, sum = 0
9001 23:56:49.391445 12, 0xFFFF, sum = 0
9002 23:56:49.391568 13, 0xFFFF, sum = 0
9003 23:56:49.395057 14, 0x0, sum = 1
9004 23:56:49.395171 15, 0x0, sum = 2
9005 23:56:49.398090 16, 0x0, sum = 3
9006 23:56:49.398206 17, 0x0, sum = 4
9007 23:56:49.401540 best_step = 15
9008 23:56:49.401649
9009 23:56:49.401746 ==
9010 23:56:49.404530 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 23:56:49.408254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 23:56:49.408370 ==
9013 23:56:49.411703 RX Vref Scan: 0
9014 23:56:49.411816
9015 23:56:49.411923 RX Vref 0 -> 0, step: 1
9016 23:56:49.412018
9017 23:56:49.414800 RX Delay 19 -> 252, step: 4
9018 23:56:49.418060 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9019 23:56:49.425232 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9020 23:56:49.427767 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
9021 23:56:49.431020 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9022 23:56:49.434520 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9023 23:56:49.437653 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9024 23:56:49.444751 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9025 23:56:49.447956 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9026 23:56:49.451158 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9027 23:56:49.454424 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9028 23:56:49.457532 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9029 23:56:49.464140 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9030 23:56:49.467935 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9031 23:56:49.470903 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9032 23:56:49.474314 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9033 23:56:49.477656 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9034 23:56:49.481262 ==
9035 23:56:49.484461 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 23:56:49.487893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 23:56:49.488003 ==
9038 23:56:49.488097 DQS Delay:
9039 23:56:49.490867 DQS0 = 0, DQS1 = 0
9040 23:56:49.490950 DQM Delay:
9041 23:56:49.494535 DQM0 = 134, DQM1 = 130
9042 23:56:49.494618 DQ Delay:
9043 23:56:49.497742 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =130
9044 23:56:49.501432 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9045 23:56:49.504269 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9046 23:56:49.507516 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9047 23:56:49.507624
9048 23:56:49.507739
9049 23:56:49.507850
9050 23:56:49.511046 [DramC_TX_OE_Calibration] TA2
9051 23:56:49.513998 Original DQ_B0 (3 6) =30, OEN = 27
9052 23:56:49.517484 Original DQ_B1 (3 6) =30, OEN = 27
9053 23:56:49.521053 24, 0x0, End_B0=24 End_B1=24
9054 23:56:49.524235 25, 0x0, End_B0=25 End_B1=25
9055 23:56:49.524355 26, 0x0, End_B0=26 End_B1=26
9056 23:56:49.527745 27, 0x0, End_B0=27 End_B1=27
9057 23:56:49.531024 28, 0x0, End_B0=28 End_B1=28
9058 23:56:49.534394 29, 0x0, End_B0=29 End_B1=29
9059 23:56:49.534479 30, 0x0, End_B0=30 End_B1=30
9060 23:56:49.537483 31, 0x4141, End_B0=30 End_B1=30
9061 23:56:49.540725 Byte0 end_step=30 best_step=27
9062 23:56:49.544564 Byte1 end_step=30 best_step=27
9063 23:56:49.547879 Byte0 TX OE(2T, 0.5T) = (3, 3)
9064 23:56:49.551272 Byte1 TX OE(2T, 0.5T) = (3, 3)
9065 23:56:49.551354
9066 23:56:49.551419
9067 23:56:49.557672 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9068 23:56:49.560589 CH1 RK1: MR19=303, MR18=2409
9069 23:56:49.567658 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9070 23:56:49.570769 [RxdqsGatingPostProcess] freq 1600
9071 23:56:49.574177 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9072 23:56:49.577296 best DQS0 dly(2T, 0.5T) = (1, 1)
9073 23:56:49.580552 best DQS1 dly(2T, 0.5T) = (1, 1)
9074 23:56:49.584158 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9075 23:56:49.587411 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9076 23:56:49.590385 best DQS0 dly(2T, 0.5T) = (1, 1)
9077 23:56:49.594196 best DQS1 dly(2T, 0.5T) = (1, 1)
9078 23:56:49.597073 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9079 23:56:49.600924 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9080 23:56:49.604202 Pre-setting of DQS Precalculation
9081 23:56:49.607419 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9082 23:56:49.613950 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9083 23:56:49.623934 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 23:56:49.624067
9085 23:56:49.624191
9086 23:56:49.627425 [Calibration Summary] 3200 Mbps
9087 23:56:49.627546 CH 0, Rank 0
9088 23:56:49.630515 SW Impedance : PASS
9089 23:56:49.630646 DUTY Scan : NO K
9090 23:56:49.634003 ZQ Calibration : PASS
9091 23:56:49.637319 Jitter Meter : NO K
9092 23:56:49.637440 CBT Training : PASS
9093 23:56:49.640294 Write leveling : PASS
9094 23:56:49.640429 RX DQS gating : PASS
9095 23:56:49.643664 RX DQ/DQS(RDDQC) : PASS
9096 23:56:49.646883 TX DQ/DQS : PASS
9097 23:56:49.647008 RX DATLAT : PASS
9098 23:56:49.650443 RX DQ/DQS(Engine): PASS
9099 23:56:49.653518 TX OE : PASS
9100 23:56:49.653646 All Pass.
9101 23:56:49.653764
9102 23:56:49.653875 CH 0, Rank 1
9103 23:56:49.656877 SW Impedance : PASS
9104 23:56:49.660109 DUTY Scan : NO K
9105 23:56:49.660215 ZQ Calibration : PASS
9106 23:56:49.664297 Jitter Meter : NO K
9107 23:56:49.667113 CBT Training : PASS
9108 23:56:49.667257 Write leveling : PASS
9109 23:56:49.670246 RX DQS gating : PASS
9110 23:56:49.673984 RX DQ/DQS(RDDQC) : PASS
9111 23:56:49.674066 TX DQ/DQS : PASS
9112 23:56:49.677146 RX DATLAT : PASS
9113 23:56:49.680495 RX DQ/DQS(Engine): PASS
9114 23:56:49.680581 TX OE : PASS
9115 23:56:49.683763 All Pass.
9116 23:56:49.683868
9117 23:56:49.683971 CH 1, Rank 0
9118 23:56:49.687174 SW Impedance : PASS
9119 23:56:49.687256 DUTY Scan : NO K
9120 23:56:49.690503 ZQ Calibration : PASS
9121 23:56:49.693731 Jitter Meter : NO K
9122 23:56:49.693811 CBT Training : PASS
9123 23:56:49.696638 Write leveling : PASS
9124 23:56:49.700199 RX DQS gating : PASS
9125 23:56:49.700318 RX DQ/DQS(RDDQC) : PASS
9126 23:56:49.703636 TX DQ/DQS : PASS
9127 23:56:49.703746 RX DATLAT : PASS
9128 23:56:49.706554 RX DQ/DQS(Engine): PASS
9129 23:56:49.709820 TX OE : PASS
9130 23:56:49.709899 All Pass.
9131 23:56:49.709981
9132 23:56:49.710060 CH 1, Rank 1
9133 23:56:49.713136 SW Impedance : PASS
9134 23:56:49.716412 DUTY Scan : NO K
9135 23:56:49.716497 ZQ Calibration : PASS
9136 23:56:49.720258 Jitter Meter : NO K
9137 23:56:49.723479 CBT Training : PASS
9138 23:56:49.723595 Write leveling : PASS
9139 23:56:49.726838 RX DQS gating : PASS
9140 23:56:49.730089 RX DQ/DQS(RDDQC) : PASS
9141 23:56:49.730176 TX DQ/DQS : PASS
9142 23:56:49.732946 RX DATLAT : PASS
9143 23:56:49.736309 RX DQ/DQS(Engine): PASS
9144 23:56:49.736410 TX OE : PASS
9145 23:56:49.740321 All Pass.
9146 23:56:49.740440
9147 23:56:49.740544 DramC Write-DBI on
9148 23:56:49.743428 PER_BANK_REFRESH: Hybrid Mode
9149 23:56:49.743526 TX_TRACKING: ON
9150 23:56:49.753212 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9151 23:56:49.759675 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9152 23:56:49.769587 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9153 23:56:49.772999 [FAST_K] Save calibration result to emmc
9154 23:56:49.776496 sync common calibartion params.
9155 23:56:49.776586 sync cbt_mode0:1, 1:1
9156 23:56:49.780295 dram_init: ddr_geometry: 2
9157 23:56:49.783402 dram_init: ddr_geometry: 2
9158 23:56:49.783515 dram_init: ddr_geometry: 2
9159 23:56:49.786413 0:dram_rank_size:100000000
9160 23:56:49.789701 1:dram_rank_size:100000000
9161 23:56:49.792869 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9162 23:56:49.796068 DFS_SHUFFLE_HW_MODE: ON
9163 23:56:49.799989 dramc_set_vcore_voltage set vcore to 725000
9164 23:56:49.802991 Read voltage for 1600, 0
9165 23:56:49.803080 Vio18 = 0
9166 23:56:49.806103 Vcore = 725000
9167 23:56:49.806181 Vdram = 0
9168 23:56:49.806245 Vddq = 0
9169 23:56:49.810033 Vmddr = 0
9170 23:56:49.810118 switch to 3200 Mbps bootup
9171 23:56:49.812937 [DramcRunTimeConfig]
9172 23:56:49.813054 PHYPLL
9173 23:56:49.816085 DPM_CONTROL_AFTERK: ON
9174 23:56:49.816172 PER_BANK_REFRESH: ON
9175 23:56:49.819551 REFRESH_OVERHEAD_REDUCTION: ON
9176 23:56:49.823225 CMD_PICG_NEW_MODE: OFF
9177 23:56:49.823327 XRTWTW_NEW_MODE: ON
9178 23:56:49.826620 XRTRTR_NEW_MODE: ON
9179 23:56:49.826705 TX_TRACKING: ON
9180 23:56:49.829602 RDSEL_TRACKING: OFF
9181 23:56:49.832862 DQS Precalculation for DVFS: ON
9182 23:56:49.832947 RX_TRACKING: OFF
9183 23:56:49.833028 HW_GATING DBG: ON
9184 23:56:49.836539 ZQCS_ENABLE_LP4: ON
9185 23:56:49.839520 RX_PICG_NEW_MODE: ON
9186 23:56:49.839608 TX_PICG_NEW_MODE: ON
9187 23:56:49.842803 ENABLE_RX_DCM_DPHY: ON
9188 23:56:49.846570 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9189 23:56:49.849834 DUMMY_READ_FOR_TRACKING: OFF
9190 23:56:49.849918 !!! SPM_CONTROL_AFTERK: OFF
9191 23:56:49.853019 !!! SPM could not control APHY
9192 23:56:49.856209 IMPEDANCE_TRACKING: ON
9193 23:56:49.856293 TEMP_SENSOR: ON
9194 23:56:49.859555 HW_SAVE_FOR_SR: OFF
9195 23:56:49.862780 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9196 23:56:49.866688 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9197 23:56:49.866771 Read ODT Tracking: ON
9198 23:56:49.869431 Refresh Rate DeBounce: ON
9199 23:56:49.873256 DFS_NO_QUEUE_FLUSH: ON
9200 23:56:49.876079 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9201 23:56:49.876163 ENABLE_DFS_RUNTIME_MRW: OFF
9202 23:56:49.879343 DDR_RESERVE_NEW_MODE: ON
9203 23:56:49.882735 MR_CBT_SWITCH_FREQ: ON
9204 23:56:49.882856 =========================
9205 23:56:49.902694 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9206 23:56:49.905846 dram_init: ddr_geometry: 2
9207 23:56:49.924513 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9208 23:56:49.927784 dram_init: dram init end (result: 0)
9209 23:56:49.934357 DRAM-K: Full calibration passed in 24474 msecs
9210 23:56:49.938051 MRC: failed to locate region type 0.
9211 23:56:49.938128 DRAM rank0 size:0x100000000,
9212 23:56:49.941129 DRAM rank1 size=0x100000000
9213 23:56:49.951299 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9214 23:56:49.957848 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9215 23:56:49.964875 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9216 23:56:49.971171 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9217 23:56:49.974801 DRAM rank0 size:0x100000000,
9218 23:56:49.977986 DRAM rank1 size=0x100000000
9219 23:56:49.978064 CBMEM:
9220 23:56:49.981761 IMD: root @ 0xfffff000 254 entries.
9221 23:56:49.984472 IMD: root @ 0xffffec00 62 entries.
9222 23:56:49.988360 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9223 23:56:49.991879 WARNING: RO_VPD is uninitialized or empty.
9224 23:56:49.997904 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9225 23:56:50.004698 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9226 23:56:50.017174 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9227 23:56:50.028846 BS: romstage times (exec / console): total (unknown) / 23999 ms
9228 23:56:50.028963
9229 23:56:50.029058
9230 23:56:50.038307 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9231 23:56:50.041915 ARM64: Exception handlers installed.
9232 23:56:50.045359 ARM64: Testing exception
9233 23:56:50.048765 ARM64: Done test exception
9234 23:56:50.048851 Enumerating buses...
9235 23:56:50.051694 Show all devs... Before device enumeration.
9236 23:56:50.055136 Root Device: enabled 1
9237 23:56:50.058864 CPU_CLUSTER: 0: enabled 1
9238 23:56:50.058945 CPU: 00: enabled 1
9239 23:56:50.062025 Compare with tree...
9240 23:56:50.062151 Root Device: enabled 1
9241 23:56:50.065088 CPU_CLUSTER: 0: enabled 1
9242 23:56:50.068438 CPU: 00: enabled 1
9243 23:56:50.068564 Root Device scanning...
9244 23:56:50.071754 scan_static_bus for Root Device
9245 23:56:50.074935 CPU_CLUSTER: 0 enabled
9246 23:56:50.078351 scan_static_bus for Root Device done
9247 23:56:50.081401 scan_bus: bus Root Device finished in 8 msecs
9248 23:56:50.081514 done
9249 23:56:50.088622 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9250 23:56:50.091873 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9251 23:56:50.098463 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9252 23:56:50.101685 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9253 23:56:50.104793 Allocating resources...
9254 23:56:50.108124 Reading resources...
9255 23:56:50.111453 Root Device read_resources bus 0 link: 0
9256 23:56:50.111526 DRAM rank0 size:0x100000000,
9257 23:56:50.114664 DRAM rank1 size=0x100000000
9258 23:56:50.117895 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9259 23:56:50.121346 CPU: 00 missing read_resources
9260 23:56:50.124780 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9261 23:56:50.131590 Root Device read_resources bus 0 link: 0 done
9262 23:56:50.131714 Done reading resources.
9263 23:56:50.138426 Show resources in subtree (Root Device)...After reading.
9264 23:56:50.141609 Root Device child on link 0 CPU_CLUSTER: 0
9265 23:56:50.145036 CPU_CLUSTER: 0 child on link 0 CPU: 00
9266 23:56:50.154700 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9267 23:56:50.154789 CPU: 00
9268 23:56:50.157966 Root Device assign_resources, bus 0 link: 0
9269 23:56:50.161035 CPU_CLUSTER: 0 missing set_resources
9270 23:56:50.168052 Root Device assign_resources, bus 0 link: 0 done
9271 23:56:50.168134 Done setting resources.
9272 23:56:50.174718 Show resources in subtree (Root Device)...After assigning values.
9273 23:56:50.178411 Root Device child on link 0 CPU_CLUSTER: 0
9274 23:56:50.181158 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 23:56:50.191449 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 23:56:50.191541 CPU: 00
9277 23:56:50.194453 Done allocating resources.
9278 23:56:50.198290 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9279 23:56:50.201707 Enabling resources...
9280 23:56:50.201790 done.
9281 23:56:50.208147 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9282 23:56:50.208222 Initializing devices...
9283 23:56:50.211488 Root Device init
9284 23:56:50.211571 init hardware done!
9285 23:56:50.214818 0x00000018: ctrlr->caps
9286 23:56:50.218172 52.000 MHz: ctrlr->f_max
9287 23:56:50.218256 0.400 MHz: ctrlr->f_min
9288 23:56:50.221289 0x40ff8080: ctrlr->voltages
9289 23:56:50.221374 sclk: 390625
9290 23:56:50.224499 Bus Width = 1
9291 23:56:50.224584 sclk: 390625
9292 23:56:50.224649 Bus Width = 1
9293 23:56:50.228363 Early init status = 3
9294 23:56:50.234896 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9295 23:56:50.238057 in-header: 03 fc 00 00 01 00 00 00
9296 23:56:50.238142 in-data: 00
9297 23:56:50.244436 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9298 23:56:50.248394 in-header: 03 fd 00 00 00 00 00 00
9299 23:56:50.251637 in-data:
9300 23:56:50.254556 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9301 23:56:50.257789 in-header: 03 fc 00 00 01 00 00 00
9302 23:56:50.261090 in-data: 00
9303 23:56:50.264258 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9304 23:56:50.270127 in-header: 03 fd 00 00 00 00 00 00
9305 23:56:50.274133 in-data:
9306 23:56:50.276819 [SSUSB] Setting up USB HOST controller...
9307 23:56:50.280009 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9308 23:56:50.282985 [SSUSB] phy power-on done.
9309 23:56:50.286663 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9310 23:56:50.293268 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9311 23:56:50.296512 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9312 23:56:50.302930 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9313 23:56:50.309877 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9314 23:56:50.316805 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9315 23:56:50.323251 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9316 23:56:50.329724 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9317 23:56:50.329836 SPM: binary array size = 0x9dc
9318 23:56:50.336881 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9319 23:56:50.343025 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9320 23:56:50.349488 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9321 23:56:50.353518 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9322 23:56:50.359674 configure_display: Starting display init
9323 23:56:50.393102 anx7625_power_on_init: Init interface.
9324 23:56:50.396671 anx7625_disable_pd_protocol: Disabled PD feature.
9325 23:56:50.399848 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9326 23:56:50.428058 anx7625_start_dp_work: Secure OCM version=00
9327 23:56:50.430870 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9328 23:56:50.445718 sp_tx_get_edid_block: EDID Block = 1
9329 23:56:50.548430 Extracted contents:
9330 23:56:50.551738 header: 00 ff ff ff ff ff ff 00
9331 23:56:50.555238 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9332 23:56:50.558326 version: 01 04
9333 23:56:50.561589 basic params: 95 1f 11 78 0a
9334 23:56:50.564628 chroma info: 76 90 94 55 54 90 27 21 50 54
9335 23:56:50.568168 established: 00 00 00
9336 23:56:50.574879 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9337 23:56:50.577969 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9338 23:56:50.584492 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9339 23:56:50.591602 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9340 23:56:50.598039 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9341 23:56:50.601812 extensions: 00
9342 23:56:50.601908 checksum: fb
9343 23:56:50.601975
9344 23:56:50.605096 Manufacturer: IVO Model 57d Serial Number 0
9345 23:56:50.608461 Made week 0 of 2020
9346 23:56:50.608552 EDID version: 1.4
9347 23:56:50.611463 Digital display
9348 23:56:50.614529 6 bits per primary color channel
9349 23:56:50.614642 DisplayPort interface
9350 23:56:50.618070 Maximum image size: 31 cm x 17 cm
9351 23:56:50.621628 Gamma: 220%
9352 23:56:50.621705 Check DPMS levels
9353 23:56:50.624477 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9354 23:56:50.628300 First detailed timing is preferred timing
9355 23:56:50.631241 Established timings supported:
9356 23:56:50.634619 Standard timings supported:
9357 23:56:50.634711 Detailed timings
9358 23:56:50.641063 Hex of detail: 383680a07038204018303c0035ae10000019
9359 23:56:50.645013 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9360 23:56:50.651329 0780 0798 07c8 0820 hborder 0
9361 23:56:50.654349 0438 043b 0447 0458 vborder 0
9362 23:56:50.657697 -hsync -vsync
9363 23:56:50.657807 Did detailed timing
9364 23:56:50.661227 Hex of detail: 000000000000000000000000000000000000
9365 23:56:50.664690 Manufacturer-specified data, tag 0
9366 23:56:50.671102 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9367 23:56:50.671217 ASCII string: InfoVision
9368 23:56:50.677746 Hex of detail: 000000fe00523134304e574635205248200a
9369 23:56:50.681295 ASCII string: R140NWF5 RH
9370 23:56:50.681396 Checksum
9371 23:56:50.681497 Checksum: 0xfb (valid)
9372 23:56:50.687748 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9373 23:56:50.690753 DSI data_rate: 832800000 bps
9374 23:56:50.697356 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9375 23:56:50.701225 anx7625_parse_edid: pixelclock(138800).
9376 23:56:50.704810 hactive(1920), hsync(48), hfp(24), hbp(88)
9377 23:56:50.707829 vactive(1080), vsync(12), vfp(3), vbp(17)
9378 23:56:50.711233 anx7625_dsi_config: config dsi.
9379 23:56:50.717600 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9380 23:56:50.730511 anx7625_dsi_config: success to config DSI
9381 23:56:50.733955 anx7625_dp_start: MIPI phy setup OK.
9382 23:56:50.736738 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9383 23:56:50.740389 mtk_ddp_mode_set invalid vrefresh 60
9384 23:56:50.743390 main_disp_path_setup
9385 23:56:50.743499 ovl_layer_smi_id_en
9386 23:56:50.746521 ovl_layer_smi_id_en
9387 23:56:50.746596 ccorr_config
9388 23:56:50.746671 aal_config
9389 23:56:50.749950 gamma_config
9390 23:56:50.750026 postmask_config
9391 23:56:50.753307 dither_config
9392 23:56:50.756789 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9393 23:56:50.763683 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9394 23:56:50.766537 Root Device init finished in 552 msecs
9395 23:56:50.769889 CPU_CLUSTER: 0 init
9396 23:56:50.776767 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9397 23:56:50.780499 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9398 23:56:50.783422 APU_MBOX 0x190000b0 = 0x10001
9399 23:56:50.786662 APU_MBOX 0x190001b0 = 0x10001
9400 23:56:50.790059 APU_MBOX 0x190005b0 = 0x10001
9401 23:56:50.793518 APU_MBOX 0x190006b0 = 0x10001
9402 23:56:50.796856 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9403 23:56:50.809160 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9404 23:56:50.821838 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9405 23:56:50.828610 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9406 23:56:50.839900 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9407 23:56:50.849168 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9408 23:56:50.852579 CPU_CLUSTER: 0 init finished in 81 msecs
9409 23:56:50.855883 Devices initialized
9410 23:56:50.859195 Show all devs... After init.
9411 23:56:50.859310 Root Device: enabled 1
9412 23:56:50.862583 CPU_CLUSTER: 0: enabled 1
9413 23:56:50.865841 CPU: 00: enabled 1
9414 23:56:50.869150 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9415 23:56:50.872504 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9416 23:56:50.875491 ELOG: NV offset 0x57f000 size 0x1000
9417 23:56:50.882533 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9418 23:56:50.889196 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9419 23:56:50.892497 ELOG: Event(17) added with size 13 at 2024-05-29 23:52:11 UTC
9420 23:56:50.896062 out: cmd=0x121: 03 db 21 01 00 00 00 00
9421 23:56:50.899583 in-header: 03 ce 00 00 2c 00 00 00
9422 23:56:50.912750 in-data: 91 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9423 23:56:50.919262 ELOG: Event(A1) added with size 10 at 2024-05-29 23:52:11 UTC
9424 23:56:50.926253 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9425 23:56:50.932602 ELOG: Event(A0) added with size 9 at 2024-05-29 23:52:11 UTC
9426 23:56:50.935916 elog_add_boot_reason: Logged dev mode boot
9427 23:56:50.939503 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9428 23:56:50.942722 Finalize devices...
9429 23:56:50.942820 Devices finalized
9430 23:56:50.949213 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9431 23:56:50.952415 Writing coreboot table at 0xffe64000
9432 23:56:50.955588 0. 000000000010a000-0000000000113fff: RAMSTAGE
9433 23:56:50.959266 1. 0000000040000000-00000000400fffff: RAM
9434 23:56:50.965509 2. 0000000040100000-000000004032afff: RAMSTAGE
9435 23:56:50.969280 3. 000000004032b000-00000000545fffff: RAM
9436 23:56:50.972651 4. 0000000054600000-000000005465ffff: BL31
9437 23:56:50.975588 5. 0000000054660000-00000000ffe63fff: RAM
9438 23:56:50.982485 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9439 23:56:50.985697 7. 0000000100000000-000000023fffffff: RAM
9440 23:56:50.985812 Passing 5 GPIOs to payload:
9441 23:56:50.992048 NAME | PORT | POLARITY | VALUE
9442 23:56:50.995357 EC in RW | 0x000000aa | low | undefined
9443 23:56:51.002315 EC interrupt | 0x00000005 | low | undefined
9444 23:56:51.005414 TPM interrupt | 0x000000ab | high | undefined
9445 23:56:51.008972 SD card detect | 0x00000011 | high | undefined
9446 23:56:51.015727 speaker enable | 0x00000093 | high | undefined
9447 23:56:51.018883 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9448 23:56:51.022095 in-header: 03 f9 00 00 02 00 00 00
9449 23:56:51.022174 in-data: 02 00
9450 23:56:51.025363 ADC[4]: Raw value=904726 ID=7
9451 23:56:51.029164 ADC[3]: Raw value=213441 ID=1
9452 23:56:51.029244 RAM Code: 0x71
9453 23:56:51.032352 ADC[6]: Raw value=75332 ID=0
9454 23:56:51.035872 ADC[5]: Raw value=213072 ID=1
9455 23:56:51.035980 SKU Code: 0x1
9456 23:56:51.042099 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7651
9457 23:56:51.045882 coreboot table: 964 bytes.
9458 23:56:51.048966 IMD ROOT 0. 0xfffff000 0x00001000
9459 23:56:51.052429 IMD SMALL 1. 0xffffe000 0x00001000
9460 23:56:51.055501 RO MCACHE 2. 0xffffc000 0x00001104
9461 23:56:51.058855 CONSOLE 3. 0xfff7c000 0x00080000
9462 23:56:51.061748 FMAP 4. 0xfff7b000 0x00000452
9463 23:56:51.065823 TIME STAMP 5. 0xfff7a000 0x00000910
9464 23:56:51.068749 VBOOT WORK 6. 0xfff66000 0x00014000
9465 23:56:51.072131 RAMOOPS 7. 0xffe66000 0x00100000
9466 23:56:51.075092 COREBOOT 8. 0xffe64000 0x00002000
9467 23:56:51.075217 IMD small region:
9468 23:56:51.078998 IMD ROOT 0. 0xffffec00 0x00000400
9469 23:56:51.081914 VPD 1. 0xffffeb80 0x0000006c
9470 23:56:51.084890 MMC STATUS 2. 0xffffeb60 0x00000004
9471 23:56:51.091922 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9472 23:56:51.095093 Probing TPM: done!
9473 23:56:51.098250 Connected to device vid:did:rid of 1ae0:0028:00
9474 23:56:51.108786 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9475 23:56:51.112075 Initialized TPM device CR50 revision 0
9476 23:56:51.115798 Checking cr50 for pending updates
9477 23:56:51.118869 Reading cr50 TPM mode
9478 23:56:51.127841 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9479 23:56:51.134272 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9480 23:56:51.174124 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9481 23:56:51.177968 Checking segment from ROM address 0x40100000
9482 23:56:51.181299 Checking segment from ROM address 0x4010001c
9483 23:56:51.187874 Loading segment from ROM address 0x40100000
9484 23:56:51.187958 code (compression=0)
9485 23:56:51.197989 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9486 23:56:51.204175 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9487 23:56:51.204283 it's not compressed!
9488 23:56:51.210997 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9489 23:56:51.214056 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9490 23:56:51.234682 Loading segment from ROM address 0x4010001c
9491 23:56:51.234823 Entry Point 0x80000000
9492 23:56:51.237967 Loaded segments
9493 23:56:51.241414 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9494 23:56:51.248232 Jumping to boot code at 0x80000000(0xffe64000)
9495 23:56:51.254617 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9496 23:56:51.261248 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9497 23:56:51.269397 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9498 23:56:51.272713 Checking segment from ROM address 0x40100000
9499 23:56:51.276275 Checking segment from ROM address 0x4010001c
9500 23:56:51.279262 Loading segment from ROM address 0x40100000
9501 23:56:51.282774 code (compression=1)
9502 23:56:51.289398 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9503 23:56:51.299340 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9504 23:56:51.299426 using LZMA
9505 23:56:51.307656 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9506 23:56:51.313947 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9507 23:56:51.317681 Loading segment from ROM address 0x4010001c
9508 23:56:51.317765 Entry Point 0x54601000
9509 23:56:51.320708 Loaded segments
9510 23:56:51.324372 NOTICE: MT8192 bl31_setup
9511 23:56:51.331086 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9512 23:56:51.334785 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9513 23:56:51.337930 WARNING: region 0:
9514 23:56:51.341186 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 23:56:51.341270 WARNING: region 1:
9516 23:56:51.347715 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9517 23:56:51.351059 WARNING: region 2:
9518 23:56:51.354718 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9519 23:56:51.357904 WARNING: region 3:
9520 23:56:51.361285 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 23:56:51.364452 WARNING: region 4:
9522 23:56:51.371534 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9523 23:56:51.371619 WARNING: region 5:
9524 23:56:51.374687 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 23:56:51.377697 WARNING: region 6:
9526 23:56:51.381309 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 23:56:51.384374 WARNING: region 7:
9528 23:56:51.387550 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 23:56:51.394538 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9530 23:56:51.397699 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9531 23:56:51.401215 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9532 23:56:51.407589 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9533 23:56:51.410801 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9534 23:56:51.414560 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9535 23:56:51.421307 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9536 23:56:51.424532 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9537 23:56:51.430780 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9538 23:56:51.434399 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9539 23:56:51.437749 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9540 23:56:51.444130 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9541 23:56:51.447930 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9542 23:56:51.451024 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9543 23:56:51.457645 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9544 23:56:51.461510 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9545 23:56:51.467435 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9546 23:56:51.471284 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9547 23:56:51.474376 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9548 23:56:51.481234 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9549 23:56:51.484377 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9550 23:56:51.487580 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9551 23:56:51.494632 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9552 23:56:51.497790 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9553 23:56:51.504924 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9554 23:56:51.507521 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9555 23:56:51.511267 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9556 23:56:51.518216 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9557 23:56:51.521188 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9558 23:56:51.528163 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9559 23:56:51.530888 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9560 23:56:51.534953 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9561 23:56:51.541679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9562 23:56:51.544362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9563 23:56:51.547869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9564 23:56:51.551595 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9565 23:56:51.554726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9566 23:56:51.561364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9567 23:56:51.564905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9568 23:56:51.568077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9569 23:56:51.571924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9570 23:56:51.578060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9571 23:56:51.581374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9572 23:56:51.585007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9573 23:56:51.588129 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9574 23:56:51.594887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9575 23:56:51.598058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9576 23:56:51.601802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9577 23:56:51.608320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9578 23:56:51.611711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9579 23:56:51.614689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9580 23:56:51.621683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9581 23:56:51.624719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9582 23:56:51.631575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9583 23:56:51.634863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9584 23:56:51.641913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9585 23:56:51.645405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9586 23:56:51.648279 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9587 23:56:51.655211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9588 23:56:51.658503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9589 23:56:51.665137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9590 23:56:51.669092 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9591 23:56:51.675226 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9592 23:56:51.678500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9593 23:56:51.681995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9594 23:56:51.688842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9595 23:56:51.691782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9596 23:56:51.698879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9597 23:56:51.702120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9598 23:56:51.705182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9599 23:56:51.712310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9600 23:56:51.715279 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9601 23:56:51.722378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9602 23:56:51.725200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9603 23:56:51.732119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9604 23:56:51.735477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9605 23:56:51.742098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9606 23:56:51.745014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9607 23:56:51.748658 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9608 23:56:51.755307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9609 23:56:51.758231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9610 23:56:51.765169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9611 23:56:51.768310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9612 23:56:51.775106 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9613 23:56:51.778279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9614 23:56:51.781882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9615 23:56:51.788576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9616 23:56:51.792075 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9617 23:56:51.798790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9618 23:56:51.801966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9619 23:56:51.808839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9620 23:56:51.811990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9621 23:56:51.815436 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9622 23:56:51.822143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9623 23:56:51.825383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9624 23:56:51.832157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9625 23:56:51.835299 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9626 23:56:51.839147 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9627 23:56:51.842138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9628 23:56:51.849119 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9629 23:56:51.852784 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9630 23:56:51.855722 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9631 23:56:51.862645 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9632 23:56:51.865813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9633 23:56:51.872206 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9634 23:56:51.876086 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9635 23:56:51.879243 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9636 23:56:51.886195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9637 23:56:51.889269 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9638 23:56:51.892678 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9639 23:56:51.899555 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9640 23:56:51.902614 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9641 23:56:51.909530 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9642 23:56:51.912670 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9643 23:56:51.915985 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9644 23:56:51.922476 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9645 23:56:51.926216 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9646 23:56:51.929297 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9647 23:56:51.936163 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9648 23:56:51.939512 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9649 23:56:51.942664 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9650 23:56:51.946175 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9651 23:56:51.949328 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9652 23:56:51.956428 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9653 23:56:51.959389 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9654 23:56:51.966166 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9655 23:56:51.969292 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9656 23:56:51.973044 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9657 23:56:51.979521 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9658 23:56:51.983239 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9659 23:56:51.986448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9660 23:56:51.992606 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9661 23:56:51.996203 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9662 23:56:52.002661 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9663 23:56:52.006419 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9664 23:56:52.009451 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9665 23:56:52.016548 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9666 23:56:52.019283 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9667 23:56:52.026220 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9668 23:56:52.029970 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9669 23:56:52.033424 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9670 23:56:52.039535 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9671 23:56:52.042600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9672 23:56:52.049350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9673 23:56:52.053086 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9674 23:56:52.056547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9675 23:56:52.063231 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9676 23:56:52.066256 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9677 23:56:52.069531 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9678 23:56:52.076559 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9679 23:56:52.079806 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9680 23:56:52.083163 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9681 23:56:52.089649 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9682 23:56:52.093178 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9683 23:56:52.099799 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9684 23:56:52.102809 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9685 23:56:52.106359 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9686 23:56:52.112960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9687 23:56:52.116271 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9688 23:56:52.122905 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9689 23:56:52.126390 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9690 23:56:52.129710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9691 23:56:52.135893 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9692 23:56:52.139734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9693 23:56:52.146242 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9694 23:56:52.149306 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9695 23:56:52.152714 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9696 23:56:52.159265 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9697 23:56:52.162352 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9698 23:56:52.169025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9699 23:56:52.172705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9700 23:56:52.176112 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9701 23:56:52.182848 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9702 23:56:52.186066 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9703 23:56:52.192613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9704 23:56:52.195614 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9705 23:56:52.199386 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9706 23:56:52.205624 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9707 23:56:52.208742 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9708 23:56:52.212651 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9709 23:56:52.219023 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9710 23:56:52.222003 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9711 23:56:52.228940 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9712 23:56:52.232065 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9713 23:56:52.235819 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9714 23:56:52.242448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9715 23:56:52.245855 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9716 23:56:52.252434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9717 23:56:52.255936 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9718 23:56:52.258779 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9719 23:56:52.265728 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9720 23:56:52.268801 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9721 23:56:52.275588 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9722 23:56:52.278762 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9723 23:56:52.282458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9724 23:56:52.288981 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9725 23:56:52.292165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9726 23:56:52.299557 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9727 23:56:52.301842 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9728 23:56:52.308719 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9729 23:56:52.311917 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9730 23:56:52.315088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9731 23:56:52.322053 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9732 23:56:52.325072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9733 23:56:52.331852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9734 23:56:52.335225 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9735 23:56:52.341658 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9736 23:56:52.345421 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9737 23:56:52.348864 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9738 23:56:52.354845 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9739 23:56:52.358260 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9740 23:56:52.365516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9741 23:56:52.368441 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9742 23:56:52.371460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9743 23:56:52.378588 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9744 23:56:52.381807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9745 23:56:52.388106 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9746 23:56:52.391601 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9747 23:56:52.398409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9748 23:56:52.401740 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9749 23:56:52.404922 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9750 23:56:52.411585 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9751 23:56:52.415146 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9752 23:56:52.421352 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9753 23:56:52.424734 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9754 23:56:52.428449 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9755 23:56:52.434903 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9756 23:56:52.438135 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9757 23:56:52.445152 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9758 23:56:52.448487 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9759 23:56:52.451803 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9760 23:56:52.455053 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9761 23:56:52.461579 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9762 23:56:52.464595 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9763 23:56:52.468391 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9764 23:56:52.474944 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9765 23:56:52.477748 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9766 23:56:52.481319 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9767 23:56:52.488252 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9768 23:56:52.491710 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9769 23:56:52.494720 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9770 23:56:52.501254 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9771 23:56:52.504696 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9772 23:56:52.507988 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9773 23:56:52.514894 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9774 23:56:52.517949 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9775 23:56:52.524889 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9776 23:56:52.527828 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9777 23:56:52.530823 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9778 23:56:52.537808 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9779 23:56:52.541014 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9780 23:56:52.544581 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9781 23:56:52.550816 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9782 23:56:52.554640 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9783 23:56:52.561307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9784 23:56:52.564533 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9785 23:56:52.567521 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9786 23:56:52.574181 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9787 23:56:52.577261 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9788 23:56:52.580469 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9789 23:56:52.587061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9790 23:56:52.590297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9791 23:56:52.597472 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9792 23:56:52.600546 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9793 23:56:52.604230 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9794 23:56:52.610470 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9795 23:56:52.613910 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9796 23:56:52.617692 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9797 23:56:52.623782 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9798 23:56:52.627012 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9799 23:56:52.630275 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9800 23:56:52.633909 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9801 23:56:52.637322 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9802 23:56:52.643817 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9803 23:56:52.646916 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9804 23:56:52.650199 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9805 23:56:52.653976 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9806 23:56:52.660329 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9807 23:56:52.663318 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9808 23:56:52.667106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9809 23:56:52.673731 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9810 23:56:52.676769 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9811 23:56:52.679897 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9812 23:56:52.686832 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9813 23:56:52.690152 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9814 23:56:52.697044 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9815 23:56:52.700070 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9816 23:56:52.703160 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9817 23:56:52.710083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9818 23:56:52.713566 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9819 23:56:52.719791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9820 23:56:52.723070 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9821 23:56:52.726758 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9822 23:56:52.733169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9823 23:56:52.736548 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9824 23:56:52.743305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9825 23:56:52.746255 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9826 23:56:52.750016 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9827 23:56:52.756667 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9828 23:56:52.759966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9829 23:56:52.766206 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9830 23:56:52.770046 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9831 23:56:52.776604 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9832 23:56:52.779635 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9833 23:56:52.783341 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9834 23:56:52.789464 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9835 23:56:52.793218 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9836 23:56:52.796360 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9837 23:56:52.803331 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9838 23:56:52.806631 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9839 23:56:52.812745 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9840 23:56:52.816355 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9841 23:56:52.822785 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9842 23:56:52.826570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9843 23:56:52.829737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9844 23:56:52.836032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9845 23:56:52.839959 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9846 23:56:52.846233 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9847 23:56:52.849341 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9848 23:56:52.852877 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9849 23:56:52.859688 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9850 23:56:52.862810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9851 23:56:52.869517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9852 23:56:52.872914 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9853 23:56:52.876071 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9854 23:56:52.882763 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9855 23:56:52.886034 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9856 23:56:52.892796 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9857 23:56:52.896373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9858 23:56:52.899276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9859 23:56:52.906204 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9860 23:56:52.909896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9861 23:56:52.916253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9862 23:56:52.919225 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9863 23:56:52.926168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9864 23:56:52.929496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9865 23:56:52.932967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9866 23:56:52.939499 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9867 23:56:52.942818 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9868 23:56:52.945678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9869 23:56:52.953039 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9870 23:56:52.955678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9871 23:56:52.962566 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9872 23:56:52.965726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9873 23:56:52.972998 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9874 23:56:52.975929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9875 23:56:52.979576 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9876 23:56:52.986038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9877 23:56:52.989731 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9878 23:56:52.995921 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9879 23:56:52.999167 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9880 23:56:53.002939 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9881 23:56:53.009115 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9882 23:56:53.012660 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9883 23:56:53.019381 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9884 23:56:53.022486 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9885 23:56:53.025648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9886 23:56:53.032596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9887 23:56:53.035846 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9888 23:56:53.042131 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9889 23:56:53.045987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9890 23:56:53.052494 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9891 23:56:53.055479 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9892 23:56:53.062170 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9893 23:56:53.065557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9894 23:56:53.069036 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9895 23:56:53.075427 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9896 23:56:53.078676 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9897 23:56:53.085518 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9898 23:56:53.088731 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9899 23:56:53.095462 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9900 23:56:53.098588 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9901 23:56:53.105443 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9902 23:56:53.108469 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9903 23:56:53.111603 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9904 23:56:53.118539 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9905 23:56:53.122108 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9906 23:56:53.128650 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9907 23:56:53.131900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9908 23:56:53.138477 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9909 23:56:53.141713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9910 23:56:53.144961 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9911 23:56:53.151631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9912 23:56:53.154782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9913 23:56:53.161617 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9914 23:56:53.164880 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9915 23:56:53.171902 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9916 23:56:53.174804 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9917 23:56:53.178197 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9918 23:56:53.184845 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9919 23:56:53.187991 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9920 23:56:53.194900 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9921 23:56:53.198473 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9922 23:56:53.204892 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9923 23:56:53.208035 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9924 23:56:53.211734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9925 23:56:53.218477 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9926 23:56:53.221604 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9927 23:56:53.228321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9928 23:56:53.231350 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9929 23:56:53.238295 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9930 23:56:53.241623 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9931 23:56:53.244930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9932 23:56:53.251312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9933 23:56:53.254820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9934 23:56:53.261421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9935 23:56:53.264413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9936 23:56:53.271322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9937 23:56:53.274490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9938 23:56:53.281368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9939 23:56:53.284766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9940 23:56:53.291193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9941 23:56:53.294563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9942 23:56:53.301161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9943 23:56:53.305052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9944 23:56:53.310904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9945 23:56:53.314750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9946 23:56:53.317797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9947 23:56:53.324626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9948 23:56:53.327699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9949 23:56:53.334921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9950 23:56:53.337864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9951 23:56:53.344683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9952 23:56:53.347962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9953 23:56:53.354658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9954 23:56:53.357732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9955 23:56:53.364358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9956 23:56:53.367718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9957 23:56:53.374449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9958 23:56:53.377661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9959 23:56:53.384679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9960 23:56:53.387982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9961 23:56:53.394421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9962 23:56:53.398024 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9963 23:56:53.404550 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9964 23:56:53.404693 INFO: [APUAPC] vio 0
9965 23:56:53.411108 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9966 23:56:53.414691 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9967 23:56:53.417902 INFO: [APUAPC] D0_APC_0: 0x400510
9968 23:56:53.421011 INFO: [APUAPC] D0_APC_1: 0x0
9969 23:56:53.424710 INFO: [APUAPC] D0_APC_2: 0x1540
9970 23:56:53.427662 INFO: [APUAPC] D0_APC_3: 0x0
9971 23:56:53.430884 INFO: [APUAPC] D1_APC_0: 0xffffffff
9972 23:56:53.434812 INFO: [APUAPC] D1_APC_1: 0xffffffff
9973 23:56:53.438134 INFO: [APUAPC] D1_APC_2: 0x3fffff
9974 23:56:53.441329 INFO: [APUAPC] D1_APC_3: 0x0
9975 23:56:53.444524 INFO: [APUAPC] D2_APC_0: 0xffffffff
9976 23:56:53.448148 INFO: [APUAPC] D2_APC_1: 0xffffffff
9977 23:56:53.451046 INFO: [APUAPC] D2_APC_2: 0x3fffff
9978 23:56:53.454281 INFO: [APUAPC] D2_APC_3: 0x0
9979 23:56:53.457932 INFO: [APUAPC] D3_APC_0: 0xffffffff
9980 23:56:53.461610 INFO: [APUAPC] D3_APC_1: 0xffffffff
9981 23:56:53.464515 INFO: [APUAPC] D3_APC_2: 0x3fffff
9982 23:56:53.464640 INFO: [APUAPC] D3_APC_3: 0x0
9983 23:56:53.470811 INFO: [APUAPC] D4_APC_0: 0xffffffff
9984 23:56:53.474150 INFO: [APUAPC] D4_APC_1: 0xffffffff
9985 23:56:53.477597 INFO: [APUAPC] D4_APC_2: 0x3fffff
9986 23:56:53.477723 INFO: [APUAPC] D4_APC_3: 0x0
9987 23:56:53.483895 INFO: [APUAPC] D5_APC_0: 0xffffffff
9988 23:56:53.487166 INFO: [APUAPC] D5_APC_1: 0xffffffff
9989 23:56:53.491186 INFO: [APUAPC] D5_APC_2: 0x3fffff
9990 23:56:53.491319 INFO: [APUAPC] D5_APC_3: 0x0
9991 23:56:53.493972 INFO: [APUAPC] D6_APC_0: 0xffffffff
9992 23:56:53.497658 INFO: [APUAPC] D6_APC_1: 0xffffffff
9993 23:56:53.500934 INFO: [APUAPC] D6_APC_2: 0x3fffff
9994 23:56:53.503985 INFO: [APUAPC] D6_APC_3: 0x0
9995 23:56:53.507184 INFO: [APUAPC] D7_APC_0: 0xffffffff
9996 23:56:53.510830 INFO: [APUAPC] D7_APC_1: 0xffffffff
9997 23:56:53.513995 INFO: [APUAPC] D7_APC_2: 0x3fffff
9998 23:56:53.517325 INFO: [APUAPC] D7_APC_3: 0x0
9999 23:56:53.520922 INFO: [APUAPC] D8_APC_0: 0xffffffff
10000 23:56:53.523952 INFO: [APUAPC] D8_APC_1: 0xffffffff
10001 23:56:53.527312 INFO: [APUAPC] D8_APC_2: 0x3fffff
10002 23:56:53.530899 INFO: [APUAPC] D8_APC_3: 0x0
10003 23:56:53.534067 INFO: [APUAPC] D9_APC_0: 0xffffffff
10004 23:56:53.537251 INFO: [APUAPC] D9_APC_1: 0xffffffff
10005 23:56:53.540891 INFO: [APUAPC] D9_APC_2: 0x3fffff
10006 23:56:53.544089 INFO: [APUAPC] D9_APC_3: 0x0
10007 23:56:53.547258 INFO: [APUAPC] D10_APC_0: 0xffffffff
10008 23:56:53.550527 INFO: [APUAPC] D10_APC_1: 0xffffffff
10009 23:56:53.553672 INFO: [APUAPC] D10_APC_2: 0x3fffff
10010 23:56:53.556813 INFO: [APUAPC] D10_APC_3: 0x0
10011 23:56:53.560516 INFO: [APUAPC] D11_APC_0: 0xffffffff
10012 23:56:53.563503 INFO: [APUAPC] D11_APC_1: 0xffffffff
10013 23:56:53.567162 INFO: [APUAPC] D11_APC_2: 0x3fffff
10014 23:56:53.570466 INFO: [APUAPC] D11_APC_3: 0x0
10015 23:56:53.573509 INFO: [APUAPC] D12_APC_0: 0xffffffff
10016 23:56:53.577194 INFO: [APUAPC] D12_APC_1: 0xffffffff
10017 23:56:53.580567 INFO: [APUAPC] D12_APC_2: 0x3fffff
10018 23:56:53.583497 INFO: [APUAPC] D12_APC_3: 0x0
10019 23:56:53.587254 INFO: [APUAPC] D13_APC_0: 0xffffffff
10020 23:56:53.590333 INFO: [APUAPC] D13_APC_1: 0xffffffff
10021 23:56:53.593468 INFO: [APUAPC] D13_APC_2: 0x3fffff
10022 23:56:53.597146 INFO: [APUAPC] D13_APC_3: 0x0
10023 23:56:53.600358 INFO: [APUAPC] D14_APC_0: 0xffffffff
10024 23:56:53.603444 INFO: [APUAPC] D14_APC_1: 0xffffffff
10025 23:56:53.607186 INFO: [APUAPC] D14_APC_2: 0x3fffff
10026 23:56:53.610176 INFO: [APUAPC] D14_APC_3: 0x0
10027 23:56:53.613753 INFO: [APUAPC] D15_APC_0: 0xffffffff
10028 23:56:53.616959 INFO: [APUAPC] D15_APC_1: 0xffffffff
10029 23:56:53.620183 INFO: [APUAPC] D15_APC_2: 0x3fffff
10030 23:56:53.623897 INFO: [APUAPC] D15_APC_3: 0x0
10031 23:56:53.626802 INFO: [APUAPC] APC_CON: 0x4
10032 23:56:53.630333 INFO: [NOCDAPC] D0_APC_0: 0x0
10033 23:56:53.633383 INFO: [NOCDAPC] D0_APC_1: 0x0
10034 23:56:53.637002 INFO: [NOCDAPC] D1_APC_0: 0x0
10035 23:56:53.639941 INFO: [NOCDAPC] D1_APC_1: 0xfff
10036 23:56:53.643131 INFO: [NOCDAPC] D2_APC_0: 0x0
10037 23:56:53.643240 INFO: [NOCDAPC] D2_APC_1: 0xfff
10038 23:56:53.646267 INFO: [NOCDAPC] D3_APC_0: 0x0
10039 23:56:53.650159 INFO: [NOCDAPC] D3_APC_1: 0xfff
10040 23:56:53.653344 INFO: [NOCDAPC] D4_APC_0: 0x0
10041 23:56:53.656543 INFO: [NOCDAPC] D4_APC_1: 0xfff
10042 23:56:53.659710 INFO: [NOCDAPC] D5_APC_0: 0x0
10043 23:56:53.663683 INFO: [NOCDAPC] D5_APC_1: 0xfff
10044 23:56:53.666651 INFO: [NOCDAPC] D6_APC_0: 0x0
10045 23:56:53.669758 INFO: [NOCDAPC] D6_APC_1: 0xfff
10046 23:56:53.673351 INFO: [NOCDAPC] D7_APC_0: 0x0
10047 23:56:53.676676 INFO: [NOCDAPC] D7_APC_1: 0xfff
10048 23:56:53.676801 INFO: [NOCDAPC] D8_APC_0: 0x0
10049 23:56:53.679700 INFO: [NOCDAPC] D8_APC_1: 0xfff
10050 23:56:53.682905 INFO: [NOCDAPC] D9_APC_0: 0x0
10051 23:56:53.686251 INFO: [NOCDAPC] D9_APC_1: 0xfff
10052 23:56:53.689975 INFO: [NOCDAPC] D10_APC_0: 0x0
10053 23:56:53.692880 INFO: [NOCDAPC] D10_APC_1: 0xfff
10054 23:56:53.696624 INFO: [NOCDAPC] D11_APC_0: 0x0
10055 23:56:53.699705 INFO: [NOCDAPC] D11_APC_1: 0xfff
10056 23:56:53.702770 INFO: [NOCDAPC] D12_APC_0: 0x0
10057 23:56:53.706460 INFO: [NOCDAPC] D12_APC_1: 0xfff
10058 23:56:53.709781 INFO: [NOCDAPC] D13_APC_0: 0x0
10059 23:56:53.713010 INFO: [NOCDAPC] D13_APC_1: 0xfff
10060 23:56:53.716015 INFO: [NOCDAPC] D14_APC_0: 0x0
10061 23:56:53.719756 INFO: [NOCDAPC] D14_APC_1: 0xfff
10062 23:56:53.719885 INFO: [NOCDAPC] D15_APC_0: 0x0
10063 23:56:53.723354 INFO: [NOCDAPC] D15_APC_1: 0xfff
10064 23:56:53.726148 INFO: [NOCDAPC] APC_CON: 0x4
10065 23:56:53.730014 INFO: [APUAPC] set_apusys_apc done
10066 23:56:53.732781 INFO: [DEVAPC] devapc_init done
10067 23:56:53.736291 INFO: GICv3 without legacy support detected.
10068 23:56:53.743121 INFO: ARM GICv3 driver initialized in EL3
10069 23:56:53.746595 INFO: Maximum SPI INTID supported: 639
10070 23:56:53.749736 INFO: BL31: Initializing runtime services
10071 23:56:53.756041 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10072 23:56:53.759950 INFO: SPM: enable CPC mode
10073 23:56:53.763323 INFO: mcdi ready for mcusys-off-idle and system suspend
10074 23:56:53.766484 INFO: BL31: Preparing for EL3 exit to normal world
10075 23:56:53.772678 INFO: Entry point address = 0x80000000
10076 23:56:53.772805 INFO: SPSR = 0x8
10077 23:56:53.779343
10078 23:56:53.779466
10079 23:56:53.779582
10080 23:56:53.782343 Starting depthcharge on Spherion...
10081 23:56:53.782465
10082 23:56:53.782572 Wipe memory regions:
10083 23:56:53.782684
10084 23:56:53.783575 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10085 23:56:53.783741 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10086 23:56:53.783880 Setting prompt string to ['asurada:']
10087 23:56:53.784023 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10088 23:56:53.786165 [0x00000040000000, 0x00000054600000)
10089 23:56:53.908197
10090 23:56:53.908357 [0x00000054660000, 0x00000080000000)
10091 23:56:54.169008
10092 23:56:54.169165 [0x000000821a7280, 0x000000ffe64000)
10093 23:56:54.913774
10094 23:56:54.913906 [0x00000100000000, 0x00000240000000)
10095 23:56:56.803779
10096 23:56:56.807059 Initializing XHCI USB controller at 0x11200000.
10097 23:56:57.844882
10098 23:56:57.847768 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10099 23:56:57.847857
10100 23:56:57.847922
10101 23:56:57.848231 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10103 23:56:57.948656 asurada: tftpboot 192.168.201.1 14084344/tftp-deploy-o2txuo6c/kernel/image.itb 14084344/tftp-deploy-o2txuo6c/kernel/cmdline
10104 23:56:57.948864 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10105 23:56:57.949000 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10106 23:56:57.953174 tftpboot 192.168.201.1 14084344/tftp-deploy-o2txuo6c/kernel/image.ittp-deploy-o2txuo6c/kernel/cmdline
10107 23:56:57.953304
10108 23:56:57.953417 Waiting for link
10109 23:56:58.113627
10110 23:56:58.113764 R8152: Initializing
10111 23:56:58.113834
10112 23:56:58.116680 Version 9 (ocp_data = 6010)
10113 23:56:58.116763
10114 23:56:58.119815 R8152: Done initializing
10115 23:56:58.119898
10116 23:56:58.120001 Adding net device
10117 23:57:00.066671
10118 23:57:00.066850 done.
10119 23:57:00.066951
10120 23:57:00.067062 MAC: 00:e0:4c:78:7a:aa
10121 23:57:00.067162
10122 23:57:00.069626 Sending DHCP discover... done.
10123 23:57:00.069704
10124 23:57:04.592651 Waiting for reply... done.
10125 23:57:04.592823
10126 23:57:04.592928 Sending DHCP request... done.
10127 23:57:04.593031
10128 23:57:04.596391 Waiting for reply... done.
10129 23:57:04.596474
10130 23:57:04.599557 My ip is 192.168.201.12
10131 23:57:04.599639
10132 23:57:04.602720 The DHCP server ip is 192.168.201.1
10133 23:57:04.602803
10134 23:57:04.606215 TFTP server IP predefined by user: 192.168.201.1
10135 23:57:04.606298
10136 23:57:04.612921 Bootfile predefined by user: 14084344/tftp-deploy-o2txuo6c/kernel/image.itb
10137 23:57:04.613003
10138 23:57:04.616110 Sending tftp read request... done.
10139 23:57:04.616193
10140 23:57:04.619165 Waiting for the transfer...
10141 23:57:04.619247
10142 23:57:04.880698 00000000 ################################################################
10143 23:57:04.880861
10144 23:57:05.137606 00080000 ################################################################
10145 23:57:05.137818
10146 23:57:05.402265 00100000 ################################################################
10147 23:57:05.402464
10148 23:57:05.658201 00180000 ################################################################
10149 23:57:05.658377
10150 23:57:05.910735 00200000 ################################################################
10151 23:57:05.910975
10152 23:57:06.166680 00280000 ################################################################
10153 23:57:06.166824
10154 23:57:06.421301 00300000 ################################################################
10155 23:57:06.421463
10156 23:57:06.676058 00380000 ################################################################
10157 23:57:06.676194
10158 23:57:06.929403 00400000 ################################################################
10159 23:57:06.929542
10160 23:57:07.183465 00480000 ################################################################
10161 23:57:07.183626
10162 23:57:07.431967 00500000 ################################################################
10163 23:57:07.432104
10164 23:57:07.686628 00580000 ################################################################
10165 23:57:07.686788
10166 23:57:07.941455 00600000 ################################################################
10167 23:57:07.941603
10168 23:57:08.203035 00680000 ################################################################
10169 23:57:08.203172
10170 23:57:08.472062 00700000 ################################################################
10171 23:57:08.472265
10172 23:57:08.727741 00780000 ################################################################
10173 23:57:08.727945
10174 23:57:09.011734 00800000 ################################################################
10175 23:57:09.011880
10176 23:57:09.273793 00880000 ################################################################
10177 23:57:09.273937
10178 23:57:09.564515 00900000 ################################################################
10179 23:57:09.564664
10180 23:57:09.846831 00980000 ################################################################
10181 23:57:09.847039
10182 23:57:10.128334 00a00000 ################################################################
10183 23:57:10.128496
10184 23:57:10.395742 00a80000 ################################################################
10185 23:57:10.395879
10186 23:57:10.669709 00b00000 ################################################################
10187 23:57:10.669842
10188 23:57:10.921100 00b80000 ################################################################
10189 23:57:10.921259
10190 23:57:11.193917 00c00000 ################################################################
10191 23:57:11.194047
10192 23:57:11.449448 00c80000 ################################################################
10193 23:57:11.449613
10194 23:57:11.701153 00d00000 ################################################################
10195 23:57:11.701294
10196 23:57:11.959824 00d80000 ################################################################
10197 23:57:11.960016
10198 23:57:12.234382 00e00000 ################################################################
10199 23:57:12.234510
10200 23:57:12.497876 00e80000 ################################################################
10201 23:57:12.498014
10202 23:57:12.762386 00f00000 ################################################################
10203 23:57:12.762551
10204 23:57:13.038878 00f80000 ################################################################
10205 23:57:13.039038
10206 23:57:13.300718 01000000 ################################################################
10207 23:57:13.300853
10208 23:57:13.553761 01080000 ################################################################
10209 23:57:13.553950
10210 23:57:13.841969 01100000 ################################################################
10211 23:57:13.842111
10212 23:57:14.101311 01180000 ################################################################
10213 23:57:14.101521
10214 23:57:14.375195 01200000 ################################################################
10215 23:57:14.375367
10216 23:57:14.631952 01280000 ################################################################
10217 23:57:14.632111
10218 23:57:14.888220 01300000 ################################################################
10219 23:57:14.888360
10220 23:57:15.154872 01380000 ################################################################
10221 23:57:15.155008
10222 23:57:15.438532 01400000 ################################################################
10223 23:57:15.438664
10224 23:57:15.714533 01480000 ################################################################
10225 23:57:15.714669
10226 23:57:15.988188 01500000 ################################################################
10227 23:57:15.988359
10228 23:57:16.264469 01580000 ################################################################
10229 23:57:16.264610
10230 23:57:16.517024 01600000 ################################################################
10231 23:57:16.517193
10232 23:57:16.769981 01680000 ################################################################
10233 23:57:16.770135
10234 23:57:17.048870 01700000 ################################################################
10235 23:57:17.049014
10236 23:57:17.340777 01780000 ################################################################
10237 23:57:17.340908
10238 23:57:17.634308 01800000 ################################################################
10239 23:57:17.634501
10240 23:57:17.925405 01880000 ################################################################
10241 23:57:17.925540
10242 23:57:18.194516 01900000 ################################################################
10243 23:57:18.194713
10244 23:57:18.466546 01980000 ################################################################
10245 23:57:18.466741
10246 23:57:18.738846 01a00000 ################################################################
10247 23:57:18.738982
10248 23:57:19.019034 01a80000 ################################################################
10249 23:57:19.019228
10250 23:57:19.269720 01b00000 ################################################################
10251 23:57:19.269880
10252 23:57:19.542616 01b80000 ################################################################
10253 23:57:19.542749
10254 23:57:19.822039 01c00000 ################################################################
10255 23:57:19.822196
10256 23:57:20.095419 01c80000 ################################################################
10257 23:57:20.095554
10258 23:57:20.364056 01d00000 ################################################################
10259 23:57:20.364191
10260 23:57:20.640306 01d80000 ################################################################
10261 23:57:20.640451
10262 23:57:20.830243 01e00000 ############################################### done.
10263 23:57:20.830377
10264 23:57:20.833783 The bootfile was 31841994 bytes long.
10265 23:57:20.833872
10266 23:57:20.837017 Sending tftp read request... done.
10267 23:57:20.837103
10268 23:57:20.837170 Waiting for the transfer...
10269 23:57:20.837232
10270 23:57:20.840589 00000000 # done.
10271 23:57:20.840693
10272 23:57:20.847105 Command line loaded dynamically from TFTP file: 14084344/tftp-deploy-o2txuo6c/kernel/cmdline
10273 23:57:20.847191
10274 23:57:20.870243 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10275 23:57:20.870338
10276 23:57:20.870404 Loading FIT.
10277 23:57:20.870466
10278 23:57:20.873353 Image ramdisk-1 has 18729213 bytes.
10279 23:57:20.873501
10280 23:57:20.876522 Image fdt-1 has 47258 bytes.
10281 23:57:20.876652
10282 23:57:20.880218 Image kernel-1 has 13063488 bytes.
10283 23:57:20.880315
10284 23:57:20.890035 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10285 23:57:20.890119
10286 23:57:20.906975 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10287 23:57:20.907064
10288 23:57:20.913525 Choosing best match conf-1 for compat google,spherion-rev2.
10289 23:57:20.913608
10290 23:57:20.920919 Connected to device vid:did:rid of 1ae0:0028:00
10291 23:57:20.929077
10292 23:57:20.932187 tpm_get_response: command 0x17b, return code 0x0
10293 23:57:20.932293
10294 23:57:20.938955 ec_init: CrosEC protocol v3 supported (256, 248)
10295 23:57:20.939062
10296 23:57:20.942725 tpm_cleanup: add release locality here.
10297 23:57:20.942808
10298 23:57:20.945857 Shutting down all USB controllers.
10299 23:57:20.945939
10300 23:57:20.949589 Removing current net device
10301 23:57:20.949672
10302 23:57:20.952873 Exiting depthcharge with code 4 at timestamp: 56469213
10303 23:57:20.956235
10304 23:57:20.959062 LZMA decompressing kernel-1 to 0x821a6718
10305 23:57:20.959146
10306 23:57:20.962301 LZMA decompressing kernel-1 to 0x40000000
10307 23:57:22.573082
10308 23:57:22.573283 jumping to kernel
10309 23:57:22.574040 end: 2.2.4 bootloader-commands (duration 00:00:29) [common]
10310 23:57:22.574204 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10311 23:57:22.574336 Setting prompt string to ['Linux version [0-9]']
10312 23:57:22.574463 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10313 23:57:22.574591 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10314 23:57:22.654802
10315 23:57:22.658051 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10316 23:57:22.662097 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10317 23:57:22.662247 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10318 23:57:22.662375 Setting prompt string to []
10319 23:57:22.662508 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10320 23:57:22.662637 Using line separator: #'\n'#
10321 23:57:22.662748 No login prompt set.
10322 23:57:22.662868 Parsing kernel messages
10323 23:57:22.662979 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10324 23:57:22.663181 [login-action] Waiting for messages, (timeout 00:03:56)
10325 23:57:22.663304 Waiting using forced prompt support (timeout 00:01:58)
10326 23:57:22.681417 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10327 23:57:22.684724 [ 0.000000] random: crng init done
10328 23:57:22.691280 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10329 23:57:22.694568 [ 0.000000] efi: UEFI not found.
10330 23:57:22.701574 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10331 23:57:22.707830 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10332 23:57:22.717586 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10333 23:57:22.728144 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10334 23:57:22.734443 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10335 23:57:22.740825 [ 0.000000] printk: bootconsole [mtk8250] enabled
10336 23:57:22.747233 [ 0.000000] NUMA: No NUMA configuration found
10337 23:57:22.754255 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10338 23:57:22.757405 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10339 23:57:22.760630 [ 0.000000] Zone ranges:
10340 23:57:22.767886 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10341 23:57:22.770758 [ 0.000000] DMA32 empty
10342 23:57:22.777024 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10343 23:57:22.780202 [ 0.000000] Movable zone start for each node
10344 23:57:22.784441 [ 0.000000] Early memory node ranges
10345 23:57:22.790493 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10346 23:57:22.797103 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10347 23:57:22.803906 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10348 23:57:22.810910 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10349 23:57:22.814009 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10350 23:57:22.823716 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10351 23:57:22.879723 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10352 23:57:22.886083 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10353 23:57:22.893212 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10354 23:57:22.896283 [ 0.000000] psci: probing for conduit method from DT.
10355 23:57:22.902680 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10356 23:57:22.906033 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10357 23:57:22.912718 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10358 23:57:22.915840 [ 0.000000] psci: SMC Calling Convention v1.2
10359 23:57:22.922662 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10360 23:57:22.925740 [ 0.000000] Detected VIPT I-cache on CPU0
10361 23:57:22.932601 [ 0.000000] CPU features: detected: GIC system register CPU interface
10362 23:57:22.939278 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10363 23:57:22.946053 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10364 23:57:22.952678 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10365 23:57:22.959580 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10366 23:57:22.965670 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10367 23:57:22.972813 [ 0.000000] alternatives: applying boot alternatives
10368 23:57:22.975984 [ 0.000000] Fallback order for Node 0: 0
10369 23:57:22.982361 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10370 23:57:22.986194 [ 0.000000] Policy zone: Normal
10371 23:57:23.009071 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10372 23:57:23.022236 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10373 23:57:23.032618 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10374 23:57:23.042693 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10375 23:57:23.049411 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10376 23:57:23.052451 <6>[ 0.000000] software IO TLB: area num 8.
10377 23:57:23.108865 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10378 23:57:23.258194 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10379 23:57:23.264961 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10380 23:57:23.271443 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10381 23:57:23.274992 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10382 23:57:23.281929 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10383 23:57:23.288832 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10384 23:57:23.291770 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10385 23:57:23.301786 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10386 23:57:23.308114 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10387 23:57:23.314528 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10388 23:57:23.321483 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10389 23:57:23.324480 <6>[ 0.000000] GICv3: 608 SPIs implemented
10390 23:57:23.327672 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10391 23:57:23.334728 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10392 23:57:23.337984 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10393 23:57:23.344953 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10394 23:57:23.358158 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10395 23:57:23.367635 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10396 23:57:23.377585 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10397 23:57:23.385336 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10398 23:57:23.397879 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10399 23:57:23.404586 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10400 23:57:23.411459 <6>[ 0.009175] Console: colour dummy device 80x25
10401 23:57:23.421046 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10402 23:57:23.427971 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10403 23:57:23.431384 <6>[ 0.029245] LSM: Security Framework initializing
10404 23:57:23.437701 <6>[ 0.034181] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10405 23:57:23.448184 <6>[ 0.041995] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10406 23:57:23.454529 <6>[ 0.051417] cblist_init_generic: Setting adjustable number of callback queues.
10407 23:57:23.460897 <6>[ 0.058861] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 23:57:23.471102 <6>[ 0.065199] cblist_init_generic: Setting adjustable number of callback queues.
10409 23:57:23.477761 <6>[ 0.072626] cblist_init_generic: Setting shift to 3 and lim to 1.
10410 23:57:23.480872 <6>[ 0.079027] rcu: Hierarchical SRCU implementation.
10411 23:57:23.487653 <6>[ 0.084072] rcu: Max phase no-delay instances is 1000.
10412 23:57:23.494214 <6>[ 0.091141] EFI services will not be available.
10413 23:57:23.497497 <6>[ 0.096101] smp: Bringing up secondary CPUs ...
10414 23:57:23.505676 <6>[ 0.101150] Detected VIPT I-cache on CPU1
10415 23:57:23.512187 <6>[ 0.101222] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10416 23:57:23.519110 <6>[ 0.101252] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10417 23:57:23.522244 <6>[ 0.101589] Detected VIPT I-cache on CPU2
10418 23:57:23.528995 <6>[ 0.101638] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10419 23:57:23.535431 <6>[ 0.101655] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10420 23:57:23.542421 <6>[ 0.101915] Detected VIPT I-cache on CPU3
10421 23:57:23.548796 <6>[ 0.101961] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10422 23:57:23.555756 <6>[ 0.101975] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10423 23:57:23.558864 <6>[ 0.102283] CPU features: detected: Spectre-v4
10424 23:57:23.565805 <6>[ 0.102289] CPU features: detected: Spectre-BHB
10425 23:57:23.569312 <6>[ 0.102294] Detected PIPT I-cache on CPU4
10426 23:57:23.575480 <6>[ 0.102352] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10427 23:57:23.582059 <6>[ 0.102368] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10428 23:57:23.588634 <6>[ 0.102660] Detected PIPT I-cache on CPU5
10429 23:57:23.595683 <6>[ 0.102724] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10430 23:57:23.601821 <6>[ 0.102740] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10431 23:57:23.605281 <6>[ 0.103023] Detected PIPT I-cache on CPU6
10432 23:57:23.612216 <6>[ 0.103089] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10433 23:57:23.618681 <6>[ 0.103104] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10434 23:57:23.625349 <6>[ 0.103398] Detected PIPT I-cache on CPU7
10435 23:57:23.631607 <6>[ 0.103462] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10436 23:57:23.638590 <6>[ 0.103478] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10437 23:57:23.641699 <6>[ 0.103524] smp: Brought up 1 node, 8 CPUs
10438 23:57:23.648100 <6>[ 0.244844] SMP: Total of 8 processors activated.
10439 23:57:23.652012 <6>[ 0.249765] CPU features: detected: 32-bit EL0 Support
10440 23:57:23.661390 <6>[ 0.255128] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10441 23:57:23.668494 <6>[ 0.263929] CPU features: detected: Common not Private translations
10442 23:57:23.671680 <6>[ 0.270445] CPU features: detected: CRC32 instructions
10443 23:57:23.678330 <6>[ 0.275797] CPU features: detected: RCpc load-acquire (LDAPR)
10444 23:57:23.684859 <6>[ 0.281757] CPU features: detected: LSE atomic instructions
10445 23:57:23.691628 <6>[ 0.287574] CPU features: detected: Privileged Access Never
10446 23:57:23.694619 <6>[ 0.293354] CPU features: detected: RAS Extension Support
10447 23:57:23.704389 <6>[ 0.298963] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10448 23:57:23.707972 <6>[ 0.306227] CPU: All CPU(s) started at EL2
10449 23:57:23.714378 <6>[ 0.310544] alternatives: applying system-wide alternatives
10450 23:57:23.723729 <6>[ 0.321393] devtmpfs: initialized
10451 23:57:23.735861 <6>[ 0.330234] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10452 23:57:23.745639 <6>[ 0.340192] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10453 23:57:23.752661 <6>[ 0.348202] pinctrl core: initialized pinctrl subsystem
10454 23:57:23.755579 <6>[ 0.354856] DMI not present or invalid.
10455 23:57:23.762414 <6>[ 0.359266] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10456 23:57:23.771971 <6>[ 0.366122] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10457 23:57:23.778784 <6>[ 0.373705] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10458 23:57:23.788805 <6>[ 0.381926] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10459 23:57:23.791885 <6>[ 0.390169] audit: initializing netlink subsys (disabled)
10460 23:57:23.801712 <5>[ 0.395867] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10461 23:57:23.808536 <6>[ 0.396576] thermal_sys: Registered thermal governor 'step_wise'
10462 23:57:23.815285 <6>[ 0.403833] thermal_sys: Registered thermal governor 'power_allocator'
10463 23:57:23.818284 <6>[ 0.410089] cpuidle: using governor menu
10464 23:57:23.824825 <6>[ 0.421048] NET: Registered PF_QIPCRTR protocol family
10465 23:57:23.831439 <6>[ 0.426538] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10466 23:57:23.834813 <6>[ 0.433642] ASID allocator initialised with 32768 entries
10467 23:57:23.842218 <6>[ 0.440206] Serial: AMBA PL011 UART driver
10468 23:57:23.851089 <4>[ 0.448962] Trying to register duplicate clock ID: 134
10469 23:57:23.908851 <6>[ 0.510182] KASLR enabled
10470 23:57:23.923416 <6>[ 0.517864] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10471 23:57:23.929719 <6>[ 0.524876] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10472 23:57:23.936286 <6>[ 0.531365] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10473 23:57:23.942731 <6>[ 0.538369] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10474 23:57:23.949805 <6>[ 0.544857] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10475 23:57:23.956235 <6>[ 0.551863] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10476 23:57:23.962744 <6>[ 0.558349] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10477 23:57:23.969787 <6>[ 0.565352] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10478 23:57:23.972662 <6>[ 0.572815] ACPI: Interpreter disabled.
10479 23:57:23.981516 <6>[ 0.579262] iommu: Default domain type: Translated
10480 23:57:23.988107 <6>[ 0.584376] iommu: DMA domain TLB invalidation policy: strict mode
10481 23:57:23.991283 <5>[ 0.591044] SCSI subsystem initialized
10482 23:57:23.998084 <6>[ 0.595289] usbcore: registered new interface driver usbfs
10483 23:57:24.004912 <6>[ 0.601021] usbcore: registered new interface driver hub
10484 23:57:24.008044 <6>[ 0.606575] usbcore: registered new device driver usb
10485 23:57:24.014576 <6>[ 0.612690] pps_core: LinuxPPS API ver. 1 registered
10486 23:57:24.024625 <6>[ 0.617883] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10487 23:57:24.028235 <6>[ 0.627228] PTP clock support registered
10488 23:57:24.031440 <6>[ 0.631467] EDAC MC: Ver: 3.0.0
10489 23:57:24.039445 <6>[ 0.636650] FPGA manager framework
10490 23:57:24.041839 <6>[ 0.640326] Advanced Linux Sound Architecture Driver Initialized.
10491 23:57:24.045774 <6>[ 0.647097] vgaarb: loaded
10492 23:57:24.052459 <6>[ 0.650269] clocksource: Switched to clocksource arch_sys_counter
10493 23:57:24.059273 <5>[ 0.656717] VFS: Disk quotas dquot_6.6.0
10494 23:57:24.065956 <6>[ 0.660905] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10495 23:57:24.068885 <6>[ 0.668097] pnp: PnP ACPI: disabled
10496 23:57:24.076970 <6>[ 0.674716] NET: Registered PF_INET protocol family
10497 23:57:24.086934 <6>[ 0.680305] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10498 23:57:24.097963 <6>[ 0.692633] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10499 23:57:24.108146 <6>[ 0.701448] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10500 23:57:24.114565 <6>[ 0.709419] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10501 23:57:24.121035 <6>[ 0.718118] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10502 23:57:24.133025 <6>[ 0.727865] TCP: Hash tables configured (established 65536 bind 65536)
10503 23:57:24.139340 <6>[ 0.734737] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10504 23:57:24.146263 <6>[ 0.741934] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10505 23:57:24.152971 <6>[ 0.749638] NET: Registered PF_UNIX/PF_LOCAL protocol family
10506 23:57:24.159548 <6>[ 0.755790] RPC: Registered named UNIX socket transport module.
10507 23:57:24.162951 <6>[ 0.761945] RPC: Registered udp transport module.
10508 23:57:24.169464 <6>[ 0.766879] RPC: Registered tcp transport module.
10509 23:57:24.176205 <6>[ 0.771811] RPC: Registered tcp NFSv4.1 backchannel transport module.
10510 23:57:24.179361 <6>[ 0.778477] PCI: CLS 0 bytes, default 64
10511 23:57:24.182588 <6>[ 0.782827] Unpacking initramfs...
10512 23:57:24.200401 <6>[ 0.794848] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10513 23:57:24.210407 <6>[ 0.803487] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10514 23:57:24.213832 <6>[ 0.812328] kvm [1]: IPA Size Limit: 40 bits
10515 23:57:24.219910 <6>[ 0.816858] kvm [1]: GICv3: no GICV resource entry
10516 23:57:24.223669 <6>[ 0.821880] kvm [1]: disabling GICv2 emulation
10517 23:57:24.230030 <6>[ 0.826564] kvm [1]: GIC system register CPU interface enabled
10518 23:57:24.233048 <6>[ 0.832728] kvm [1]: vgic interrupt IRQ18
10519 23:57:24.240061 <6>[ 0.837082] kvm [1]: VHE mode initialized successfully
10520 23:57:24.246664 <5>[ 0.843631] Initialise system trusted keyrings
10521 23:57:24.253113 <6>[ 0.848434] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10522 23:57:24.260662 <6>[ 0.858433] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10523 23:57:24.267476 <5>[ 0.864831] NFS: Registering the id_resolver key type
10524 23:57:24.270297 <5>[ 0.870135] Key type id_resolver registered
10525 23:57:24.276794 <5>[ 0.874548] Key type id_legacy registered
10526 23:57:24.283555 <6>[ 0.878826] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10527 23:57:24.290287 <6>[ 0.885748] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10528 23:57:24.297228 <6>[ 0.893446] 9p: Installing v9fs 9p2000 file system support
10529 23:57:24.333013 <5>[ 0.930875] Key type asymmetric registered
10530 23:57:24.336254 <5>[ 0.935206] Asymmetric key parser 'x509' registered
10531 23:57:24.346492 <6>[ 0.940343] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10532 23:57:24.349402 <6>[ 0.947972] io scheduler mq-deadline registered
10533 23:57:24.353088 <6>[ 0.952753] io scheduler kyber registered
10534 23:57:24.371774 <6>[ 0.969617] EINJ: ACPI disabled.
10535 23:57:24.404295 <4>[ 0.995517] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10536 23:57:24.414397 <4>[ 1.006145] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10537 23:57:24.429289 <6>[ 1.027285] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10538 23:57:24.437547 <6>[ 1.035258] printk: console [ttyS0] disabled
10539 23:57:24.465685 <6>[ 1.059900] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10540 23:57:24.472180 <6>[ 1.069386] printk: console [ttyS0] enabled
10541 23:57:24.475417 <6>[ 1.069386] printk: console [ttyS0] enabled
10542 23:57:24.481763 <6>[ 1.078285] printk: bootconsole [mtk8250] disabled
10543 23:57:24.485062 <6>[ 1.078285] printk: bootconsole [mtk8250] disabled
10544 23:57:24.491822 <6>[ 1.089639] SuperH (H)SCI(F) driver initialized
10545 23:57:24.495497 <6>[ 1.094968] msm_serial: driver initialized
10546 23:57:24.509181 <6>[ 1.103960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10547 23:57:24.519307 <6>[ 1.112521] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10548 23:57:24.525768 <6>[ 1.121063] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10549 23:57:24.536353 <6>[ 1.129689] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10550 23:57:24.542540 <6>[ 1.138398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10551 23:57:24.552642 <6>[ 1.147114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10552 23:57:24.562662 <6>[ 1.155658] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10553 23:57:24.569648 <6>[ 1.164466] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10554 23:57:24.579188 <6>[ 1.173011] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10555 23:57:24.591200 <6>[ 1.188990] loop: module loaded
10556 23:57:24.597586 <6>[ 1.194714] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10557 23:57:24.620197 <4>[ 1.218143] mtk-pmic-keys: Failed to locate of_node [id: -1]
10558 23:57:24.627123 <6>[ 1.225027] megasas: 07.719.03.00-rc1
10559 23:57:24.636829 <6>[ 1.234798] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10560 23:57:24.643738 <6>[ 1.241688] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10561 23:57:24.660215 <6>[ 1.258218] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10562 23:57:24.716361 <6>[ 1.307703] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10563 23:57:24.972916 <6>[ 1.570770] Freeing initrd memory: 18284K
10564 23:57:24.984458 <6>[ 1.582493] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10565 23:57:24.995660 <6>[ 1.593627] tun: Universal TUN/TAP device driver, 1.6
10566 23:57:24.998737 <6>[ 1.599712] thunder_xcv, ver 1.0
10567 23:57:25.002464 <6>[ 1.603217] thunder_bgx, ver 1.0
10568 23:57:25.005153 <6>[ 1.606712] nicpf, ver 1.0
10569 23:57:25.016183 <6>[ 1.610742] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10570 23:57:25.019129 <6>[ 1.618218] hns3: Copyright (c) 2017 Huawei Corporation.
10571 23:57:25.022785 <6>[ 1.623806] hclge is initializing
10572 23:57:25.029576 <6>[ 1.627388] e1000: Intel(R) PRO/1000 Network Driver
10573 23:57:25.035913 <6>[ 1.632517] e1000: Copyright (c) 1999-2006 Intel Corporation.
10574 23:57:25.039628 <6>[ 1.638532] e1000e: Intel(R) PRO/1000 Network Driver
10575 23:57:25.046569 <6>[ 1.643748] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10576 23:57:25.052692 <6>[ 1.649938] igb: Intel(R) Gigabit Ethernet Network Driver
10577 23:57:25.059540 <6>[ 1.655587] igb: Copyright (c) 2007-2014 Intel Corporation.
10578 23:57:25.066236 <6>[ 1.661426] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10579 23:57:25.069394 <6>[ 1.667944] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10580 23:57:25.076433 <6>[ 1.674415] sky2: driver version 1.30
10581 23:57:25.083347 <6>[ 1.679336] usbcore: registered new device driver r8152-cfgselector
10582 23:57:25.089554 <6>[ 1.685871] usbcore: registered new interface driver r8152
10583 23:57:25.092703 <6>[ 1.691691] VFIO - User Level meta-driver version: 0.3
10584 23:57:25.102007 <6>[ 1.699935] usbcore: registered new interface driver usb-storage
10585 23:57:25.108855 <6>[ 1.706386] usbcore: registered new device driver onboard-usb-hub
10586 23:57:25.117632 <6>[ 1.715619] mt6397-rtc mt6359-rtc: registered as rtc0
10587 23:57:25.127595 <6>[ 1.721089] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:52:45 UTC (1717026765)
10588 23:57:25.131014 <6>[ 1.730703] i2c_dev: i2c /dev entries driver
10589 23:57:25.148058 <6>[ 1.742590] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10590 23:57:25.154537 <4>[ 1.751320] cpu cpu0: supply cpu not found, using dummy regulator
10591 23:57:25.161106 <4>[ 1.757747] cpu cpu1: supply cpu not found, using dummy regulator
10592 23:57:25.167908 <4>[ 1.764153] cpu cpu2: supply cpu not found, using dummy regulator
10593 23:57:25.174855 <4>[ 1.770571] cpu cpu3: supply cpu not found, using dummy regulator
10594 23:57:25.181320 <4>[ 1.776966] cpu cpu4: supply cpu not found, using dummy regulator
10595 23:57:25.188128 <4>[ 1.783363] cpu cpu5: supply cpu not found, using dummy regulator
10596 23:57:25.194600 <4>[ 1.789763] cpu cpu6: supply cpu not found, using dummy regulator
10597 23:57:25.198016 <4>[ 1.796157] cpu cpu7: supply cpu not found, using dummy regulator
10598 23:57:25.219126 <6>[ 1.816810] cpu cpu0: EM: created perf domain
10599 23:57:25.222367 <6>[ 1.821756] cpu cpu4: EM: created perf domain
10600 23:57:25.229109 <6>[ 1.827372] sdhci: Secure Digital Host Controller Interface driver
10601 23:57:25.236089 <6>[ 1.833807] sdhci: Copyright(c) Pierre Ossman
10602 23:57:25.242397 <6>[ 1.838764] Synopsys Designware Multimedia Card Interface Driver
10603 23:57:25.249171 <6>[ 1.845399] sdhci-pltfm: SDHCI platform and OF driver helper
10604 23:57:25.252938 <6>[ 1.845429] mmc0: CQHCI version 5.10
10605 23:57:25.259209 <6>[ 1.855544] ledtrig-cpu: registered to indicate activity on CPUs
10606 23:57:25.265770 <6>[ 1.862685] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10607 23:57:25.273018 <6>[ 1.869736] usbcore: registered new interface driver usbhid
10608 23:57:25.276059 <6>[ 1.875569] usbhid: USB HID core driver
10609 23:57:25.282554 <6>[ 1.879767] spi_master spi0: will run message pump with realtime priority
10610 23:57:25.326930 <6>[ 1.918347] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10611 23:57:25.345957 <6>[ 1.933381] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10612 23:57:25.348968 <6>[ 1.947248] mmc0: Command Queue Engine enabled
10613 23:57:25.356527 <6>[ 1.948202] cros-ec-spi spi0.0: Chrome EC device registered
10614 23:57:25.359482 <6>[ 1.951990] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10615 23:57:25.367069 <6>[ 1.965036] mmcblk0: mmc0:0001 DA4128 116 GiB
10616 23:57:25.377463 <6>[ 1.971256] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10617 23:57:25.383941 <6>[ 1.974817] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10618 23:57:25.386896 <6>[ 1.981551] NET: Registered PF_PACKET protocol family
10619 23:57:25.393582 <6>[ 1.987409] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10620 23:57:25.397473 <6>[ 1.991914] 9pnet: Installing 9P2000 support
10621 23:57:25.404271 <6>[ 1.997635] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10622 23:57:25.407660 <5>[ 2.001633] Key type dns_resolver registered
10623 23:57:25.414334 <6>[ 2.007404] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10624 23:57:25.421192 <6>[ 2.011884] registered taskstats version 1
10625 23:57:25.423647 <5>[ 2.022286] Loading compiled-in X.509 certificates
10626 23:57:25.453660 <4>[ 2.044809] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 23:57:25.463167 <4>[ 2.055517] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10628 23:57:25.478018 <6>[ 2.076281] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10629 23:57:25.485249 <6>[ 2.083217] xhci-mtk 11200000.usb: xHCI Host Controller
10630 23:57:25.491619 <6>[ 2.088719] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10631 23:57:25.502045 <6>[ 2.096590] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10632 23:57:25.508757 <6>[ 2.106045] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10633 23:57:25.515339 <6>[ 2.112143] xhci-mtk 11200000.usb: xHCI Host Controller
10634 23:57:25.521631 <6>[ 2.117727] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10635 23:57:25.528441 <6>[ 2.125396] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10636 23:57:25.535232 <6>[ 2.133222] hub 1-0:1.0: USB hub found
10637 23:57:25.538552 <6>[ 2.137270] hub 1-0:1.0: 1 port detected
10638 23:57:25.545371 <6>[ 2.141572] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10639 23:57:25.552572 <6>[ 2.150397] hub 2-0:1.0: USB hub found
10640 23:57:25.555463 <6>[ 2.154420] hub 2-0:1.0: 1 port detected
10641 23:57:25.563943 <6>[ 2.161709] mtk-msdc 11f70000.mmc: Got CD GPIO
10642 23:57:25.581183 <6>[ 2.175715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10643 23:57:25.587577 <6>[ 2.183772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10644 23:57:25.597552 <4>[ 2.191695] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10645 23:57:25.607743 <6>[ 2.201255] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10646 23:57:25.614155 <6>[ 2.209336] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10647 23:57:25.621021 <6>[ 2.217357] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10648 23:57:25.631063 <6>[ 2.225284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10649 23:57:25.637452 <6>[ 2.233102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10650 23:57:25.647514 <6>[ 2.240917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10651 23:57:25.657870 <6>[ 2.251327] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10652 23:57:25.664537 <6>[ 2.259705] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10653 23:57:25.674440 <6>[ 2.268054] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10654 23:57:25.681259 <6>[ 2.276392] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10655 23:57:25.690850 <6>[ 2.284730] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10656 23:57:25.697507 <6>[ 2.293068] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10657 23:57:25.707400 <6>[ 2.301406] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10658 23:57:25.714074 <6>[ 2.309743] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10659 23:57:25.724157 <6>[ 2.318081] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10660 23:57:25.730546 <6>[ 2.326421] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10661 23:57:25.740916 <6>[ 2.334759] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10662 23:57:25.747299 <6>[ 2.343097] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10663 23:57:25.757242 <6>[ 2.351436] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10664 23:57:25.763682 <6>[ 2.359774] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10665 23:57:25.773648 <6>[ 2.368113] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10666 23:57:25.780278 <6>[ 2.376844] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10667 23:57:25.786955 <6>[ 2.383972] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10668 23:57:25.793568 <6>[ 2.390736] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10669 23:57:25.800494 <6>[ 2.397501] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10670 23:57:25.806807 <6>[ 2.404437] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10671 23:57:25.816521 <6>[ 2.411305] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10672 23:57:25.826918 <6>[ 2.420434] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10673 23:57:25.836547 <6>[ 2.429554] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10674 23:57:25.846331 <6>[ 2.438847] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10675 23:57:25.853487 <6>[ 2.448315] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10676 23:57:25.862833 <6>[ 2.457781] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10677 23:57:25.872765 <6>[ 2.466901] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10678 23:57:25.882789 <6>[ 2.476370] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10679 23:57:25.892710 <6>[ 2.485489] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10680 23:57:25.902771 <6>[ 2.494784] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10681 23:57:25.912875 <6>[ 2.504948] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10682 23:57:25.922518 <6>[ 2.517214] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10683 23:57:25.929059 <6>[ 2.526743] Trying to probe devices needed for running init ...
10684 23:57:25.967692 <6>[ 2.562543] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10685 23:57:26.122228 <6>[ 2.720319] hub 1-1:1.0: USB hub found
10686 23:57:26.125443 <6>[ 2.724839] hub 1-1:1.0: 4 ports detected
10687 23:57:26.135467 <6>[ 2.733514] hub 1-1:1.0: USB hub found
10688 23:57:26.138818 <6>[ 2.737889] hub 1-1:1.0: 4 ports detected
10689 23:57:26.248169 <6>[ 2.842839] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10690 23:57:26.273404 <6>[ 2.871623] hub 2-1:1.0: USB hub found
10691 23:57:26.276570 <6>[ 2.876092] hub 2-1:1.0: 3 ports detected
10692 23:57:26.285019 <6>[ 2.883223] hub 2-1:1.0: USB hub found
10693 23:57:26.288199 <6>[ 2.887704] hub 2-1:1.0: 3 ports detected
10694 23:57:26.463268 <6>[ 3.058586] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10695 23:57:26.595571 <6>[ 3.193848] hub 1-1.4:1.0: USB hub found
10696 23:57:26.598700 <6>[ 3.198449] hub 1-1.4:1.0: 2 ports detected
10697 23:57:26.608211 <6>[ 3.206130] hub 1-1.4:1.0: USB hub found
10698 23:57:26.611097 <6>[ 3.210901] hub 1-1.4:1.0: 2 ports detected
10699 23:57:26.675448 <6>[ 3.270598] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10700 23:57:26.784198 <6>[ 3.378958] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10701 23:57:26.816090 <4>[ 3.411066] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10702 23:57:26.826647 <4>[ 3.420252] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10703 23:57:26.865591 <6>[ 3.463548] r8152 2-1.3:1.0 eth0: v1.12.13
10704 23:57:26.911873 <6>[ 3.506588] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10705 23:57:27.103706 <6>[ 3.698588] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10706 23:57:28.482728 <6>[ 5.081032] r8152 2-1.3:1.0 eth0: carrier on
10707 23:57:30.799948 <5>[ 5.102395] Sending DHCP requests .., OK
10708 23:57:30.806148 <6>[ 7.402740] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10709 23:57:30.809988 <6>[ 7.411034] IP-Config: Complete:
10710 23:57:30.822829 <6>[ 7.414563] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10711 23:57:30.829851 <6>[ 7.425274] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10712 23:57:30.836180 <6>[ 7.433892] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10713 23:57:30.842705 <6>[ 7.433901] nameserver0=192.168.201.1
10714 23:57:30.845983 <6>[ 7.446068] clk: Disabling unused clocks
10715 23:57:30.849673 <6>[ 7.451785] ALSA device list:
10716 23:57:30.856404 <6>[ 7.455026] No soundcards found.
10717 23:57:30.863616 <6>[ 7.462532] Freeing unused kernel memory: 8512K
10718 23:57:30.867224 <6>[ 7.467485] Run /init as init process
10719 23:57:30.876582 Loading, please wait...
10720 23:57:30.904986 Starting systemd-udevd version 252.22-1~deb12u1
10721 23:57:31.146298 <6>[ 7.741417] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10722 23:57:31.153059 <3>[ 7.742848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 23:57:31.162722 <3>[ 7.757088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 23:57:31.169238 <3>[ 7.765197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 23:57:31.176282 <6>[ 7.768085] remoteproc remoteproc0: scp is available
10726 23:57:31.182669 <6>[ 7.768689] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10727 23:57:31.192681 <6>[ 7.768709] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10728 23:57:31.199632 <6>[ 7.768715] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10729 23:57:31.205966 <6>[ 7.804063] remoteproc remoteproc0: powering up scp
10730 23:57:31.212478 <3>[ 7.804147] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 23:57:31.222215 <6>[ 7.809239] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10732 23:57:31.229220 <6>[ 7.812638] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10733 23:57:31.239051 <3>[ 7.817325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 23:57:31.242001 <6>[ 7.826199] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10735 23:57:31.251847 <3>[ 7.833396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 23:57:31.259620 <3>[ 7.833407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 23:57:31.269774 <4>[ 7.836472] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10738 23:57:31.272936 <4>[ 7.836472] Fallback method does not support PEC.
10739 23:57:31.279769 <4>[ 7.860494] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10740 23:57:31.289940 <3>[ 7.865416] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 23:57:31.296462 <3>[ 7.877902] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10742 23:57:31.306844 <4>[ 7.878664] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10743 23:57:31.310190 <6>[ 7.880673] mc: Linux media interface: v0.10
10744 23:57:31.316726 <3>[ 7.884682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 23:57:31.323635 <6>[ 7.888356] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10746 23:57:31.330245 <6>[ 7.888368] pci_bus 0000:00: root bus resource [bus 00-ff]
10747 23:57:31.336775 <6>[ 7.888374] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10748 23:57:31.346360 <6>[ 7.888377] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10749 23:57:31.353160 <6>[ 7.888415] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10750 23:57:31.359971 <6>[ 7.888430] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10751 23:57:31.366622 <6>[ 7.888507] pci 0000:00:00.0: supports D1 D2
10752 23:57:31.373358 <6>[ 7.888509] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10753 23:57:31.379670 <6>[ 7.889913] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10754 23:57:31.386623 <6>[ 7.890030] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10755 23:57:31.392862 <6>[ 7.890056] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10756 23:57:31.403342 <6>[ 7.890074] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10757 23:57:31.409686 <6>[ 7.890089] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10758 23:57:31.412867 <6>[ 7.890201] pci 0000:01:00.0: supports D1 D2
10759 23:57:31.422680 <6>[ 7.890203] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10760 23:57:31.429414 <6>[ 7.902682] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10761 23:57:31.436042 <3>[ 7.908805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 23:57:31.442442 <6>[ 7.913288] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10763 23:57:31.453056 <3>[ 7.915708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10764 23:57:31.462790 <3>[ 7.921329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 23:57:31.469620 <3>[ 7.921332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 23:57:31.476470 <6>[ 7.928199] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10767 23:57:31.486404 <3>[ 7.933973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 23:57:31.492821 <6>[ 7.941066] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10769 23:57:31.502275 <6>[ 7.943720] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10770 23:57:31.512415 <6>[ 7.944010] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10771 23:57:31.519129 <3>[ 7.950950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 23:57:31.529288 <3>[ 7.950953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 23:57:31.535939 <3>[ 7.950958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 23:57:31.545410 <6>[ 7.957305] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10775 23:57:31.552548 <3>[ 7.964678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 23:57:31.562182 <3>[ 7.964699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 23:57:31.569201 <6>[ 7.968373] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10778 23:57:31.575681 <6>[ 7.968426] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10779 23:57:31.582192 <6>[ 7.968433] remoteproc remoteproc0: remote processor scp is now up
10780 23:57:31.592084 <6>[ 7.969230] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10781 23:57:31.598735 <6>[ 7.977712] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10782 23:57:31.605226 <6>[ 7.984884] pci 0000:00:00.0: PCI bridge to [bus 01]
10783 23:57:31.615402 <6>[ 7.987031] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10784 23:57:31.618509 <6>[ 8.007293] videodev: Linux video capture interface: v2.00
10785 23:57:31.628664 <6>[ 8.007345] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10786 23:57:31.635558 <6>[ 8.013426] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10787 23:57:31.642062 <6>[ 8.014212] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10788 23:57:31.645785 <6>[ 8.025486] Bluetooth: Core ver 2.22
10789 23:57:31.651901 <6>[ 8.032838] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10790 23:57:31.658481 <6>[ 8.040038] NET: Registered PF_BLUETOOTH protocol family
10791 23:57:31.662017 <6>[ 8.048775] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10792 23:57:31.668588 <6>[ 8.057150] Bluetooth: HCI device and connection manager initialized
10793 23:57:31.678408 <6>[ 8.074408] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10794 23:57:31.682221 <6>[ 8.081150] Bluetooth: HCI socket layer initialized
10795 23:57:31.692065 <5>[ 8.084609] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10796 23:57:31.701793 <6>[ 8.090910] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10797 23:57:31.708125 <6>[ 8.097206] Bluetooth: L2CAP socket layer initialized
10798 23:57:31.711944 <6>[ 8.097226] Bluetooth: SCO socket layer initialized
10799 23:57:31.721371 <5>[ 8.102031] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10800 23:57:31.724528 <6>[ 8.107952] usbcore: registered new interface driver uvcvideo
10801 23:57:31.731557 <6>[ 8.108751] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10802 23:57:31.741590 <5>[ 8.117076] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10803 23:57:31.747968 <6>[ 8.141333] usbcore: registered new interface driver btusb
10804 23:57:31.757857 <4>[ 8.141818] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10805 23:57:31.764917 <3>[ 8.141825] Bluetooth: hci0: Failed to load firmware file (-2)
10806 23:57:31.768044 <3>[ 8.141827] Bluetooth: hci0: Failed to set up firmware (-2)
10807 23:57:31.778119 <4>[ 8.141828] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10808 23:57:31.787996 <4>[ 8.148776] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10809 23:57:31.794747 <6>[ 8.229875] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10810 23:57:31.801118 <6>[ 8.231649] cfg80211: failed to load regulatory.db
10811 23:57:31.807521 <6>[ 8.239722] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10812 23:57:31.831827 <6>[ 8.431009] mt7921e 0000:01:00.0: ASIC revision: 79610010
10813 23:57:31.935393 <6>[ 8.530894] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10814 23:57:31.938580 <6>[ 8.530894]
10815 23:57:31.942340 Begin: Loading essential drivers ... done.
10816 23:57:31.945258 Begin: Running /scripts/init-premount ... done.
10817 23:57:31.952498 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10818 23:57:31.961890 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10819 23:57:31.965785 Device /sys/class/net/eth0 found
10820 23:57:31.965887 done.
10821 23:57:31.972225 Begin: Waiting up to 180 secs for any network device to become available ... done.
10822 23:57:32.011995 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10823 23:57:32.018603 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10824 23:57:32.025031 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10825 23:57:32.031738 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10826 23:57:32.037974 host : mt8192-asurada-spherion-r0-cbg-0
10827 23:57:32.044924 domain : lava-rack
10828 23:57:32.048149 rootserver: 192.168.201.1 rootpath:
10829 23:57:32.048233 filename :
10830 23:57:32.205548 <6>[ 8.800938] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10831 23:57:32.230543 done.
10832 23:57:32.237392 Begin: Running /scripts/nfs-bottom ... done.
10833 23:57:32.252069 Begin: Running /scripts/init-bottom ... done.
10834 23:57:33.545319 <6>[ 10.144126] NET: Registered PF_INET6 protocol family
10835 23:57:33.552563 <6>[ 10.151692] Segment Routing with IPv6
10836 23:57:33.555663 <6>[ 10.155691] In-situ OAM (IOAM) with IPv6
10837 23:57:33.748172 <30>[ 10.320461] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10838 23:57:33.754917 <30>[ 10.353727] systemd[1]: Detected architecture arm64.
10839 23:57:33.772244
10840 23:57:33.775317 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10841 23:57:33.775401
10842 23:57:33.800432 <30>[ 10.399288] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10843 23:57:34.693663 <30>[ 11.289517] systemd[1]: Queued start job for default target graphical.target.
10844 23:57:34.740293 <30>[ 11.335739] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10845 23:57:34.746610 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10846 23:57:34.768729 <30>[ 11.364356] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10847 23:57:34.778430 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10848 23:57:34.796326 <30>[ 11.392357] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10849 23:57:34.806375 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10850 23:57:34.824100 <30>[ 11.419948] systemd[1]: Created slice user.slice - User and Session Slice.
10851 23:57:34.830563 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10852 23:57:34.854911 <30>[ 11.447336] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10853 23:57:34.864463 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10854 23:57:34.882329 <30>[ 11.474810] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10855 23:57:34.888803 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10856 23:57:34.917348 <30>[ 11.503243] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10857 23:57:34.927385 <30>[ 11.523142] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10858 23:57:34.933941 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10859 23:57:34.951171 <30>[ 11.546936] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10860 23:57:34.958183 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10861 23:57:34.978963 <30>[ 11.574983] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10862 23:57:34.988782 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10863 23:57:35.003829 <30>[ 11.602661] systemd[1]: Reached target paths.target - Path Units.
10864 23:57:35.013615 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10865 23:57:35.031152 <30>[ 11.627028] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10866 23:57:35.037942 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10867 23:57:35.051395 <30>[ 11.650565] systemd[1]: Reached target slices.target - Slice Units.
10868 23:57:35.061630 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10869 23:57:35.076111 <30>[ 11.675048] systemd[1]: Reached target swap.target - Swaps.
10870 23:57:35.082230 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10871 23:57:35.103592 <30>[ 11.699063] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10872 23:57:35.113211 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10873 23:57:35.131681 <30>[ 11.727535] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10874 23:57:35.141719 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10875 23:57:35.161853 <30>[ 11.757464] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10876 23:57:35.171672 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10877 23:57:35.187954 <30>[ 11.783924] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10878 23:57:35.198259 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10879 23:57:35.215581 <30>[ 11.811233] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10880 23:57:35.221947 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10881 23:57:35.239990 <30>[ 11.835849] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10882 23:57:35.249982 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10883 23:57:35.269881 <30>[ 11.865402] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10884 23:57:35.279228 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10885 23:57:35.296376 <30>[ 11.891758] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10886 23:57:35.305869 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10887 23:57:35.359271 <30>[ 11.954798] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10888 23:57:35.365684 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10889 23:57:35.387353 <30>[ 11.982965] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10890 23:57:35.393686 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10891 23:57:35.451189 <30>[ 12.046988] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10892 23:57:35.457999 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10893 23:57:35.485949 <30>[ 12.075124] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10894 23:57:35.500533 <30>[ 12.096556] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10895 23:57:35.510463 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10896 23:57:35.532552 <30>[ 12.128244] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10897 23:57:35.538723 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10898 23:57:35.583047 <30>[ 12.178919] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10899 23:57:35.589560 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10900 23:57:35.617154 <30>[ 12.213104] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10901 23:57:35.623718 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10902 23:57:35.638270 <6>[ 12.234150] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10903 23:57:35.671483 <30>[ 12.267068] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10904 23:57:35.681126 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10905 23:57:35.704866 <30>[ 12.300804] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10906 23:57:35.711496 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10907 23:57:35.737719 <30>[ 12.333765] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10908 23:57:35.744511 Starting [0;1;39mmodpr<6>[ 12.344944] fuse: init (API version 7.37)
10909 23:57:35.750780 obe@loop.ser…e[0m - Load Kernel Module loop...
10910 23:57:35.773829 <30>[ 12.369866] systemd[1]: Starting systemd-journald.service - Journal Service...
10911 23:57:35.780780 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10912 23:57:35.804367 <30>[ 12.400000] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10913 23:57:35.811090 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10914 23:57:35.863359 <30>[ 12.455567] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10915 23:57:35.869452 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10916 23:57:35.893056 <30>[ 12.488988] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10917 23:57:35.902948 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10918 23:57:35.923335 <3>[ 12.519171] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 23:57:35.960487 <3>[ 12.556422] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 23:57:35.970781 <30>[ 12.559078] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10921 23:57:35.977266 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10922 23:57:36.003672 <30>[ 12.599586] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10923 23:57:36.013394 <3>[ 12.607280] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 23:57:36.020141 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10925 23:57:36.039060 <30>[ 12.634874] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10926 23:57:36.048884 [[0;32m OK [<3>[ 12.643471] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 23:57:36.054988 0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10928 23:57:36.075808 <30>[ 12.670981] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10929 23:57:36.082218 <3>[ 12.673059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 23:57:36.091754 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10931 23:57:36.112479 <30>[ 12.707690] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10932 23:57:36.122519 <3>[ 12.707998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 23:57:36.128942 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10934 23:57:36.147709 <30>[ 12.743390] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10935 23:57:36.154736 <3>[ 12.745863] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 23:57:36.164453 <30>[ 12.751242] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10937 23:57:36.171613 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10938 23:57:36.185322 <3>[ 12.781340] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 23:57:36.196110 <30>[ 12.791981] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10940 23:57:36.203121 <30>[ 12.800028] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10941 23:57:36.213418 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10942 23:57:36.228863 <30>[ 12.827467] systemd[1]: modprobe@drm.service: Deactivated successfully.
10943 23:57:36.239111 <30>[ 12.835226] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10944 23:57:36.246123 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10945 23:57:36.263367 <30>[ 12.859265] systemd[1]: Started systemd-journald.service - Journal Service.
10946 23:57:36.270075 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10947 23:57:36.289731 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10948 23:57:36.309201 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10949 23:57:36.333563 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10950 23:57:36.352875 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10951 23:57:36.373331 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10952 23:57:36.380094 <4>[ 12.977672] power_supply_show_property: 2 callbacks suppressed
10953 23:57:36.390018 <3>[ 12.977690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 23:57:36.403764 <4>[ 12.992591] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10955 23:57:36.413941 <3>[ 13.006090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 23:57:36.420075 <3>[ 13.008224] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10957 23:57:36.430058 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10958 23:57:36.452723 [[0;32m OK [0m] Finished [0;1;39msystemd-ud<3>[ 13.048240] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 23:57:36.459065 ev-trig…e[0m - Coldplug All udev Devices.
10960 23:57:36.476783 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10961 23:57:36.486590 <3>[ 13.081541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 23:57:36.517082 <3>[ 13.112938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 23:57:36.531361 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10964 23:57:36.547415 <3>[ 13.143114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 23:57:36.560763 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10966 23:57:36.577012 <3>[ 13.172364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 23:57:36.609185 <3>[ 13.205049] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 23:57:36.619019 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10969 23:57:36.641106 Starting [0;1;39msyste<3>[ 13.235210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 23:57:36.644694 md-random-se…ice[0m - Load/Save Random Seed...
10971 23:57:36.670075 <3>[ 13.265778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 23:57:36.676536 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10973 23:57:36.701901 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10974 23:57:36.723478 <46>[ 13.319361] systemd-journald[313]: Received client request to flush runtime journal.
10975 23:57:36.730654 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10976 23:57:36.755139 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10977 23:57:36.771501 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10978 23:57:36.792255 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10979 23:57:37.486998 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10980 23:57:37.548093 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10981 23:57:38.124921 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10982 23:57:38.161374 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10983 23:57:38.178712 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10984 23:57:38.198888 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10985 23:57:38.267153 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10986 23:57:38.291210 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10987 23:57:38.537546 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10988 23:57:38.605749 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10989 23:57:38.642321 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10990 23:57:38.674495 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10991 23:57:38.847863 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10992 23:57:38.880064 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10993 23:57:39.007358 <6>[ 15.606871] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10994 23:57:39.045704 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10995 23:57:39.094905 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10996 23:57:39.157638 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10997 23:57:39.188455 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10998 23:57:39.228605 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10999 23:57:39.250987 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11000 23:57:39.271820 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11001 23:57:39.277688 <46>[ 15.874692] systemd-journald[313]: Time jumped backwards, rotating.
11002 23:57:39.299239 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11003 23:57:39.318536 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11004 23:57:39.339501 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11005 23:57:39.358839 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11006 23:57:40.073159 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11007 23:57:40.401786 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11008 23:57:40.418199 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11009 23:57:40.769226 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11010 23:57:40.789981 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11011 23:57:40.806455 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11012 23:57:40.824012 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11013 23:57:40.841979 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11014 23:57:40.858705 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11015 23:57:40.874556 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11016 23:57:40.931470 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11017 23:57:40.959775 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11018 23:57:41.071542 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11019 23:57:41.098339 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11020 23:57:41.119007 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11021 23:57:41.291000 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11022 23:57:41.347013 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11023 23:57:41.373933 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11024 23:57:41.390560 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11025 23:57:41.407110 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11026 23:57:41.430775 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11027 23:57:41.468075 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11028 23:57:41.493164 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11029 23:57:41.512081 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11030 23:57:41.531824 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11031 23:57:41.577649 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11032 23:57:41.627228 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11033 23:57:41.705789
11034 23:57:41.708869 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11035 23:57:41.708960
11036 23:57:41.712674 debian-bookworm-arm64 login: root (automatic login)
11037 23:57:41.712821
11038 23:57:42.003622 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11039 23:57:42.003764
11040 23:57:42.009981 The programs included with the Debian GNU/Linux system are free software;
11041 23:57:42.017071 the exact distribution terms for each program are described in the
11042 23:57:42.020132 individual files in /usr/share/doc/*/copyright.
11043 23:57:42.020214
11044 23:57:42.026689 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11045 23:57:42.030089 permitted by applicable law.
11046 23:57:42.966691 Matched prompt #10: / #
11048 23:57:42.967055 Setting prompt string to ['/ #']
11049 23:57:42.967177 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11051 23:57:42.967476 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11052 23:57:42.967595 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11053 23:57:42.967695 Setting prompt string to ['/ #']
11054 23:57:42.967782 Forcing a shell prompt, looking for ['/ #']
11056 23:57:43.018053 / #
11057 23:57:43.018169 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11058 23:57:43.018243 Waiting using forced prompt support (timeout 00:02:30)
11059 23:57:43.023146
11060 23:57:43.023422 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11061 23:57:43.023517 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11063 23:57:43.123836 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo'
11064 23:57:43.129370 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084344/extract-nfsrootfs-8v3tt5zo'
11066 23:57:43.229870 / # export NFS_SERVER_IP='192.168.201.1'
11067 23:57:43.235428 export NFS_SERVER_IP='192.168.201.1'
11068 23:57:43.235718 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11069 23:57:43.235816 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11070 23:57:43.235905 end: 2 depthcharge-action (duration 00:01:24) [common]
11071 23:57:43.236052 start: 3 lava-test-retry (timeout 00:07:54) [common]
11072 23:57:43.236198 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
11073 23:57:43.236306 Using namespace: common
11075 23:57:43.336724 / # #
11076 23:57:43.336877 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11077 23:57:43.341836 #
11078 23:57:43.342099 Using /lava-14084344
11080 23:57:43.442430 / # export SHELL=/bin/bash
11081 23:57:43.447311 export SHELL=/bin/bash
11083 23:57:43.547890 / # . /lava-14084344/environment
11084 23:57:43.553452 . /lava-14084344/environment
11086 23:57:43.659156 / # /lava-14084344/bin/lava-test-runner /lava-14084344/0
11087 23:57:43.659355 Test shell timeout: 10s (minimum of the action and connection timeout)
11088 23:57:43.664911 /lava-14084344/bin/lava-test-runner /lava-14084344/0
11089 23:57:43.895325 + export TESTRUN_ID=0_timesync-off
11090 23:57:43.898319 + TESTRUN_ID=0_timesync-off
11091 23:57:43.901557 + cd /lava-14084344/0/tests/0_timesync-off
11092 23:57:43.904666 ++ cat uuid
11093 23:57:43.907758 + UUID=14084344_1.6.2.3.1
11094 23:57:43.907868 + set +x
11095 23:57:43.914801 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14084344_1.6.2.3.1>
11096 23:57:43.915064 Received signal: <STARTRUN> 0_timesync-off 14084344_1.6.2.3.1
11097 23:57:43.915141 Starting test lava.0_timesync-off (14084344_1.6.2.3.1)
11098 23:57:43.915241 Skipping test definition patterns.
11099 23:57:43.918049 + systemctl stop systemd-timesyncd
11100 23:57:43.972630 + set +x
11101 23:57:43.975665 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14084344_1.6.2.3.1>
11102 23:57:43.975925 Received signal: <ENDRUN> 0_timesync-off 14084344_1.6.2.3.1
11103 23:57:43.976010 Ending use of test pattern.
11104 23:57:43.976072 Ending test lava.0_timesync-off (14084344_1.6.2.3.1), duration 0.06
11106 23:57:44.028930 + export TESTRUN_ID=1_kselftest-tpm2
11107 23:57:44.032394 + TESTRUN_ID=1_kselftest-tpm2
11108 23:57:44.035405 + cd /lava-14084344/0/tests/1_kselftest-tpm2
11109 23:57:44.038906 ++ cat uuid
11110 23:57:44.042097 + UUID=14084344_1.6.2.3.5
11111 23:57:44.042226 + set +x
11112 23:57:44.045334 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14084344_1.6.2.3.5>
11113 23:57:44.045589 Received signal: <STARTRUN> 1_kselftest-tpm2 14084344_1.6.2.3.5
11114 23:57:44.045676 Starting test lava.1_kselftest-tpm2 (14084344_1.6.2.3.5)
11115 23:57:44.045802 Skipping test definition patterns.
11116 23:57:44.048692 + cd ./automated/linux/kselftest/
11117 23:57:44.078178 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11118 23:57:44.102171 INFO: install_deps skipped
11119 23:57:44.590037 --2024-05-29 23:53:03-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11120 23:57:44.596636 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11121 23:57:44.721990 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11122 23:57:44.855082 HTTP request sent, awaiting response... 200 OK
11123 23:57:44.857914 Length: 1642292 (1.6M) [application/octet-stream]
11124 23:57:44.861694 Saving to: 'kselftest_armhf.tar.gz'
11125 23:57:44.861779
11126 23:57:44.861844
11127 23:57:45.122593 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11128 23:57:45.387679 kselftest_armhf.tar 2%[ ] 47.81K 179KB/s
11129 23:57:45.699592 kselftest_armhf.tar 13%[=> ] 217.50K 408KB/s
11130 23:57:46.096304 kselftest_armhf.tar 51%[=========> ] 821.30K 973KB/s
11131 23:57:46.102582 kselftest_armhf.tar 84%[===============> ] 1.32M 1.06MB/s
11132 23:57:46.109176 kselftest_armhf.tar 100%[===================>] 1.57M 1.26MB/s in 1.2s
11133 23:57:46.109306
11134 23:57:46.251077 2024-05-29 23:53:05 (1.26 MB/s) - 'kselftest_armhf.tar.gz' saved [1642292/1642292]
11135 23:57:46.251228
11136 23:57:50.068723 skiplist:
11137 23:57:50.071815 ========================================
11138 23:57:50.074928 ========================================
11139 23:57:50.116743 tpm2:test_smoke.sh
11140 23:57:50.119751 tpm2:test_space.sh
11141 23:57:50.136249 ============== Tests to run ===============
11142 23:57:50.136435 tpm2:test_smoke.sh
11143 23:57:50.138841 tpm2:test_space.sh
11144 23:57:50.142498 ===========End Tests to run ===============
11145 23:57:50.142587 shardfile-tpm2 pass
11146 23:57:50.242933 <12>[ 26.844175] kselftest: Running tests in tpm2
11147 23:57:50.251952 TAP version 13
11148 23:57:50.264586 1..2
11149 23:57:50.287185 # selftests: tpm2: test_smoke.sh
11150 23:57:52.067697 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11151 23:57:52.074034 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11152 23:57:52.080853 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11153 23:57:52.084065 # Traceback (most recent call last):
11154 23:57:52.093894 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11155 23:57:52.094071 # if self.tpm:
11156 23:57:52.097960 # ^^^^^^^^
11157 23:57:52.100953 # AttributeError: 'Client' object has no attribute 'tpm'
11158 23:57:52.107243 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11159 23:57:52.113970 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11160 23:57:52.117967 # Traceback (most recent call last):
11161 23:57:52.127970 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11162 23:57:52.128128 # if self.tpm:
11163 23:57:52.130747 # ^^^^^^^^
11164 23:57:52.133902 # AttributeError: 'Client' object has no attribute 'tpm'
11165 23:57:52.140632 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11166 23:57:52.147356 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11167 23:57:52.150896 # Traceback (most recent call last):
11168 23:57:52.160978 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11169 23:57:52.164025 # if self.tpm:
11170 23:57:52.164160 # ^^^^^^^^
11171 23:57:52.170922 # AttributeError: 'Client' object has no attribute 'tpm'
11172 23:57:52.177483 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11173 23:57:52.183799 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11174 23:57:52.187252 # Traceback (most recent call last):
11175 23:57:52.197328 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11176 23:57:52.197504 # if self.tpm:
11177 23:57:52.200368 # ^^^^^^^^
11178 23:57:52.204351 # AttributeError: 'Client' object has no attribute 'tpm'
11179 23:57:52.210730 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11180 23:57:52.217379 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11181 23:57:52.220458 # Traceback (most recent call last):
11182 23:57:52.230530 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11183 23:57:52.233717 # if self.tpm:
11184 23:57:52.233846 # ^^^^^^^^
11185 23:57:52.240807 # AttributeError: 'Client' object has no attribute 'tpm'
11186 23:57:52.247547 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11187 23:57:52.250582 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11188 23:57:52.254020 # Traceback (most recent call last):
11189 23:57:52.263915 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11190 23:57:52.267465 # if self.tpm:
11191 23:57:52.267603 # ^^^^^^^^
11192 23:57:52.273781 # AttributeError: 'Client' object has no attribute 'tpm'
11193 23:57:52.280677 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11194 23:57:52.286882 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11195 23:57:52.290682 # Traceback (most recent call last):
11196 23:57:52.300434 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11197 23:57:52.300614 # if self.tpm:
11198 23:57:52.304124 # ^^^^^^^^
11199 23:57:52.307454 # AttributeError: 'Client' object has no attribute 'tpm'
11200 23:57:52.317761 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11201 23:57:52.324015 # Exception ignored in: <function Client.__del__ at 0xffffb6c7ccc0>
11202 23:57:52.331398 # Traceback (most recent call last):
11203 23:57:52.334949 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11204 23:57:52.338259 # if self.tpm:
11205 23:57:52.338378 # ^^^^^^^^
11206 23:57:52.345345 # AttributeError: 'Client' object has no attribute 'tpm'
11207 23:57:52.345439 #
11208 23:57:52.352137 # ======================================================================
11209 23:57:52.358508 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11210 23:57:52.365373 # ----------------------------------------------------------------------
11211 23:57:52.368246 # Traceback (most recent call last):
11212 23:57:52.378537 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11213 23:57:52.385376 # self.root_key = self.client.create_root_key()
11214 23:57:52.388603 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11215 23:57:52.398606 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11216 23:57:52.405363 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11217 23:57:52.408746 # ^^^^^^^^^^^^^^^^^^
11218 23:57:52.418386 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11219 23:57:52.421766 # raise ProtocolError(cc, rc)
11220 23:57:52.429038 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11221 23:57:52.429139 #
11222 23:57:52.435509 # ======================================================================
11223 23:57:52.441830 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11224 23:57:52.448942 # ----------------------------------------------------------------------
11225 23:57:52.452063 # Traceback (most recent call last):
11226 23:57:52.462115 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11227 23:57:52.465324 # self.client = tpm2.Client()
11228 23:57:52.469060 # ^^^^^^^^^^^^^
11229 23:57:52.479044 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11230 23:57:52.482245 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11231 23:57:52.485414 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11232 23:57:52.492357 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11233 23:57:52.492568 #
11234 23:57:52.498787 # ======================================================================
11235 23:57:52.505151 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11236 23:57:52.512657 # ----------------------------------------------------------------------
11237 23:57:52.515635 # Traceback (most recent call last):
11238 23:57:52.525330 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11239 23:57:52.528826 # self.client = tpm2.Client()
11240 23:57:52.531694 # ^^^^^^^^^^^^^
11241 23:57:52.541823 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11242 23:57:52.545133 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11243 23:57:52.552255 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11244 23:57:52.555577 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11245 23:57:52.555699 #
11246 23:57:52.562058 # ======================================================================
11247 23:57:52.568964 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11248 23:57:52.575267 # ----------------------------------------------------------------------
11249 23:57:52.579201 # Traceback (most recent call last):
11250 23:57:52.589362 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11251 23:57:52.592111 # self.client = tpm2.Client()
11252 23:57:52.595815 # ^^^^^^^^^^^^^
11253 23:57:52.605266 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11254 23:57:52.609036 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11255 23:57:52.615730 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11256 23:57:52.618728 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11257 23:57:52.622311 #
11258 23:57:52.625642 # ======================================================================
11259 23:57:52.638620 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11260 23:57:52.641698 # ----------------------------------------------------------------------
11261 23:57:52.645247 # Traceback (most recent call last):
11262 23:57:52.655612 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11263 23:57:52.659271 # self.client = tpm2.Client()
11264 23:57:52.662447 # ^^^^^^^^^^^^^
11265 23:57:52.670269 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11266 23:57:52.678326 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11267 23:57:52.681461 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11268 23:57:52.685155 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11269 23:57:52.685277 #
11270 23:57:52.692062 # ======================================================================
11271 23:57:52.702642 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11272 23:57:52.706033 # ----------------------------------------------------------------------
11273 23:57:52.709806 # Traceback (most recent call last):
11274 23:57:52.719683 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11275 23:57:52.722576 # self.client = tpm2.Client()
11276 23:57:52.726390 # ^^^^^^^^^^^^^
11277 23:57:52.736013 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11278 23:57:52.739289 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11279 23:57:52.742498 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11280 23:57:52.749115 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11281 23:57:52.749252 #
11282 23:57:52.756058 # ======================================================================
11283 23:57:52.762484 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11284 23:57:52.769336 # ----------------------------------------------------------------------
11285 23:57:52.772661 # Traceback (most recent call last):
11286 23:57:52.782659 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11287 23:57:52.785900 # self.client = tpm2.Client()
11288 23:57:52.789291 # ^^^^^^^^^^^^^
11289 23:57:52.799092 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11290 23:57:52.802236 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11291 23:57:52.808950 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11292 23:57:52.812273 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11293 23:57:52.812419 #
11294 23:57:52.818703 # ======================================================================
11295 23:57:52.828851 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11296 23:57:52.835802 # ----------------------------------------------------------------------
11297 23:57:52.838608 # Traceback (most recent call last):
11298 23:57:52.848927 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11299 23:57:52.849024 # self.client = tpm2.Client()
11300 23:57:52.852108 # ^^^^^^^^^^^^^
11301 23:57:52.862092 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11302 23:57:52.869097 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11303 23:57:52.872099 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11304 23:57:52.878918 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11305 23:57:52.879046 #
11306 23:57:52.885581 # ======================================================================
11307 23:57:52.892484 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11308 23:57:52.899033 # ----------------------------------------------------------------------
11309 23:57:52.902509 # Traceback (most recent call last):
11310 23:57:52.912365 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11311 23:57:52.915800 # self.client = tpm2.Client()
11312 23:57:52.918771 # ^^^^^^^^^^^^^
11313 23:57:52.929054 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11314 23:57:52.932283 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11315 23:57:52.938959 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11316 23:57:52.942395 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11317 23:57:52.942522 #
11318 23:57:52.948800 # ----------------------------------------------------------------------
11319 23:57:52.952491 # Ran 9 tests in 0.047s
11320 23:57:52.952617 #
11321 23:57:52.955642 # FAILED (errors=9)
11322 23:57:52.958748 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11323 23:57:52.965724 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11324 23:57:52.968782 #
11325 23:57:52.972552 # ----------------------------------------------------------------------
11326 23:57:52.975829 # Ran 2 tests in 0.024s
11327 23:57:52.975949 #
11328 23:57:52.976060 # OK
11329 23:57:52.979099 ok 1 selftests: tpm2: test_smoke.sh
11330 23:57:52.982465 # selftests: tpm2: test_space.sh
11331 23:57:52.989190 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11332 23:57:52.995495 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11333 23:57:53.002261 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11334 23:57:53.008792 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11335 23:57:53.008882 #
11336 23:57:53.015484 # ======================================================================
11337 23:57:53.022357 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11338 23:57:53.028905 # ----------------------------------------------------------------------
11339 23:57:53.032235 # Traceback (most recent call last):
11340 23:57:53.042228 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11341 23:57:53.045889 # root1 = space1.create_root_key()
11342 23:57:53.048547 # ^^^^^^^^^^^^^^^^^^^^^^^^
11343 23:57:53.058890 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11344 23:57:53.065926 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11345 23:57:53.069073 # ^^^^^^^^^^^^^^^^^^
11346 23:57:53.078731 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11347 23:57:53.082453 # raise ProtocolError(cc, rc)
11348 23:57:53.088490 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11349 23:57:53.088613 #
11350 23:57:53.095449 # ======================================================================
11351 23:57:53.102345 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11352 23:57:53.109053 # ----------------------------------------------------------------------
11353 23:57:53.111913 # Traceback (most recent call last):
11354 23:57:53.122126 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11355 23:57:53.125258 # space1.create_root_key()
11356 23:57:53.135269 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11357 23:57:53.142246 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11358 23:57:53.145512 # ^^^^^^^^^^^^^^^^^^
11359 23:57:53.155693 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11360 23:57:53.158560 # raise ProtocolError(cc, rc)
11361 23:57:53.165543 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11362 23:57:53.165655 #
11363 23:57:53.171845 # ======================================================================
11364 23:57:53.175691 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11365 23:57:53.181961 # ----------------------------------------------------------------------
11366 23:57:53.185070 # Traceback (most recent call last):
11367 23:57:53.198855 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11368 23:57:53.201848 # root1 = space1.create_root_key()
11369 23:57:53.205542 # ^^^^^^^^^^^^^^^^^^^^^^^^
11370 23:57:53.215479 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11371 23:57:53.222078 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11372 23:57:53.225389 # ^^^^^^^^^^^^^^^^^^
11373 23:57:53.235028 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11374 23:57:53.238250 # raise ProtocolError(cc, rc)
11375 23:57:53.245387 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11376 23:57:53.245561 #
11377 23:57:53.251741 # ======================================================================
11378 23:57:53.258746 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11379 23:57:53.264980 # ----------------------------------------------------------------------
11380 23:57:53.268723 # Traceback (most recent call last):
11381 23:57:53.278092 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11382 23:57:53.281518 # root1 = space1.create_root_key()
11383 23:57:53.285251 # ^^^^^^^^^^^^^^^^^^^^^^^^
11384 23:57:53.294924 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11385 23:57:53.302239 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11386 23:57:53.305115 # ^^^^^^^^^^^^^^^^^^
11387 23:57:53.315397 # File "/lava-14084344/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11388 23:57:53.318703 # raise ProtocolError(cc, rc)
11389 23:57:53.325437 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11390 23:57:53.325546 #
11391 23:57:53.331805 # ----------------------------------------------------------------------
11392 23:57:53.334836 # Ran 4 tests in 0.083s
11393 23:57:53.334966 #
11394 23:57:53.335079 # FAILED (errors=4)
11395 23:57:53.341534 not ok 2 selftests: tpm2: test_space.sh # exit=1
11396 23:57:53.508556 tpm2_test_smoke_sh pass
11397 23:57:53.511615 tpm2_test_space_sh fail
11398 23:57:53.578563 + ../../utils/send-to-lava.sh ./output/result.txt
11399 23:57:53.632893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11400 23:57:53.633367 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11402 23:57:53.664619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11403 23:57:53.665059 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11405 23:57:53.695972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11406 23:57:53.696380 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11408 23:57:53.699590 + set +x
11409 23:57:53.702651 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14084344_1.6.2.3.5>
11410 23:57:53.703034 Received signal: <ENDRUN> 1_kselftest-tpm2 14084344_1.6.2.3.5
11411 23:57:53.703163 Ending use of test pattern.
11412 23:57:53.703278 Ending test lava.1_kselftest-tpm2 (14084344_1.6.2.3.5), duration 9.66
11414 23:57:53.705588 <LAVA_TEST_RUNNER EXIT>
11415 23:57:53.705898 ok: lava_test_shell seems to have completed
11416 23:57:53.706089 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11417 23:57:53.706242 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11418 23:57:53.706391 end: 3 lava-test-retry (duration 00:00:10) [common]
11419 23:57:53.706537 start: 4 finalize (timeout 00:07:44) [common]
11420 23:57:53.706692 start: 4.1 power-off (timeout 00:00:30) [common]
11421 23:57:53.706975 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11422 23:57:53.787817 >> Command sent successfully.
11423 23:57:53.791097 Returned 0 in 0 seconds
11424 23:57:53.891508 end: 4.1 power-off (duration 00:00:00) [common]
11426 23:57:53.891850 start: 4.2 read-feedback (timeout 00:07:43) [common]
11427 23:57:53.892113 Listened to connection for namespace 'common' for up to 1s
11428 23:57:54.892411 Finalising connection for namespace 'common'
11429 23:57:54.892599 Disconnecting from shell: Finalise
11430 23:57:54.892702 / #
11431 23:57:54.993058 end: 4.2 read-feedback (duration 00:00:01) [common]
11432 23:57:54.993257 end: 4 finalize (duration 00:00:01) [common]
11433 23:57:54.993403 Cleaning after the job
11434 23:57:54.993519 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/ramdisk
11435 23:57:55.014734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/kernel
11436 23:57:55.029487 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/dtb
11437 23:57:55.029829 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/nfsrootfs
11438 23:57:55.119133 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084344/tftp-deploy-o2txuo6c/modules
11439 23:57:55.126932 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084344
11440 23:57:55.760824 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084344
11441 23:57:55.761003 Job finished correctly