Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 23:51:53.342681 lava-dispatcher, installed at version: 2024.03
2 23:51:53.342921 start: 0 validate
3 23:51:53.343092 Start time: 2024-05-29 23:51:53.343083+00:00 (UTC)
4 23:51:53.343249 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:51:53.343431 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:51:53.624344 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:51:53.624896 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:51:53.886658 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:51:53.887341 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:51:54.157782 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:51:54.158424 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:51:54.419591 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:51:54.419779 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:51:54.678324 validate duration: 1.34
16 23:51:54.678617 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:51:54.678726 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:51:54.678842 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:51:54.678990 Not decompressing ramdisk as can be used compressed.
20 23:51:54.679110 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 23:51:54.679203 saving as /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/ramdisk/initrd.cpio.gz
22 23:51:54.679296 total size: 5628151 (5 MB)
23 23:51:54.680651 progress 0 % (0 MB)
24 23:51:54.682347 progress 5 % (0 MB)
25 23:51:54.683976 progress 10 % (0 MB)
26 23:51:54.685438 progress 15 % (0 MB)
27 23:51:54.687014 progress 20 % (1 MB)
28 23:51:54.688441 progress 25 % (1 MB)
29 23:51:54.690107 progress 30 % (1 MB)
30 23:51:54.691746 progress 35 % (1 MB)
31 23:51:54.693135 progress 40 % (2 MB)
32 23:51:54.694736 progress 45 % (2 MB)
33 23:51:54.696180 progress 50 % (2 MB)
34 23:51:54.697733 progress 55 % (2 MB)
35 23:51:54.699279 progress 60 % (3 MB)
36 23:51:54.700681 progress 65 % (3 MB)
37 23:51:54.702248 progress 70 % (3 MB)
38 23:51:54.703644 progress 75 % (4 MB)
39 23:51:54.705242 progress 80 % (4 MB)
40 23:51:54.706625 progress 85 % (4 MB)
41 23:51:54.708179 progress 90 % (4 MB)
42 23:51:54.709748 progress 95 % (5 MB)
43 23:51:54.711214 progress 100 % (5 MB)
44 23:51:54.711427 5 MB downloaded in 0.03 s (167.05 MB/s)
45 23:51:54.711622 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:51:54.711908 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:51:54.711994 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:51:54.712081 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:51:54.712219 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:51:54.712288 saving as /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/kernel/Image
52 23:51:54.712347 total size: 54682112 (52 MB)
53 23:51:54.712408 No compression specified
54 23:51:54.713575 progress 0 % (0 MB)
55 23:51:54.727813 progress 5 % (2 MB)
56 23:51:54.742178 progress 10 % (5 MB)
57 23:51:54.757449 progress 15 % (7 MB)
58 23:51:54.772399 progress 20 % (10 MB)
59 23:51:54.787605 progress 25 % (13 MB)
60 23:51:54.802035 progress 30 % (15 MB)
61 23:51:54.816454 progress 35 % (18 MB)
62 23:51:54.830490 progress 40 % (20 MB)
63 23:51:54.844907 progress 45 % (23 MB)
64 23:51:54.859918 progress 50 % (26 MB)
65 23:51:54.874334 progress 55 % (28 MB)
66 23:51:54.888453 progress 60 % (31 MB)
67 23:51:54.902409 progress 65 % (33 MB)
68 23:51:54.917160 progress 70 % (36 MB)
69 23:51:54.931816 progress 75 % (39 MB)
70 23:51:54.946811 progress 80 % (41 MB)
71 23:51:54.960973 progress 85 % (44 MB)
72 23:51:54.975019 progress 90 % (46 MB)
73 23:51:54.988986 progress 95 % (49 MB)
74 23:51:55.002661 progress 100 % (52 MB)
75 23:51:55.002885 52 MB downloaded in 0.29 s (179.49 MB/s)
76 23:51:55.003038 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:51:55.003274 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:51:55.003364 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:51:55.003480 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:51:55.003649 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:51:55.003750 saving as /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/dtb/mt8192-asurada-spherion-r0.dtb
83 23:51:55.003838 total size: 47258 (0 MB)
84 23:51:55.003926 No compression specified
85 23:51:55.005328 progress 69 % (0 MB)
86 23:51:55.005622 progress 100 % (0 MB)
87 23:51:55.005781 0 MB downloaded in 0.00 s (23.23 MB/s)
88 23:51:55.005906 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:51:55.006124 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:51:55.006207 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:51:55.006297 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:51:55.006409 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 23:51:55.006474 saving as /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/nfsrootfs/full.rootfs.tar
95 23:51:55.006534 total size: 69067788 (65 MB)
96 23:51:55.006594 Using unxz to decompress xz
97 23:51:55.010940 progress 0 % (0 MB)
98 23:51:55.201343 progress 5 % (3 MB)
99 23:51:55.400125 progress 10 % (6 MB)
100 23:51:55.601314 progress 15 % (9 MB)
101 23:51:55.764327 progress 20 % (13 MB)
102 23:51:55.941014 progress 25 % (16 MB)
103 23:51:56.139833 progress 30 % (19 MB)
104 23:51:56.257122 progress 35 % (23 MB)
105 23:51:56.353047 progress 40 % (26 MB)
106 23:51:56.551154 progress 45 % (29 MB)
107 23:51:56.759695 progress 50 % (32 MB)
108 23:51:56.966664 progress 55 % (36 MB)
109 23:51:57.186768 progress 60 % (39 MB)
110 23:51:57.373553 progress 65 % (42 MB)
111 23:51:57.565927 progress 70 % (46 MB)
112 23:51:57.756153 progress 75 % (49 MB)
113 23:51:57.967061 progress 80 % (52 MB)
114 23:51:58.141931 progress 85 % (56 MB)
115 23:51:58.331181 progress 90 % (59 MB)
116 23:51:58.531814 progress 95 % (62 MB)
117 23:51:58.730712 progress 100 % (65 MB)
118 23:51:58.736687 65 MB downloaded in 3.73 s (17.66 MB/s)
119 23:51:58.736957 end: 1.4.1 http-download (duration 00:00:04) [common]
121 23:51:58.737264 end: 1.4 download-retry (duration 00:00:04) [common]
122 23:51:58.737395 start: 1.5 download-retry (timeout 00:09:56) [common]
123 23:51:58.737520 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 23:51:58.737720 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:51:58.737797 saving as /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/modules/modules.tar
126 23:51:58.737880 total size: 8601444 (8 MB)
127 23:51:58.737959 Using unxz to decompress xz
128 23:51:58.742004 progress 0 % (0 MB)
129 23:51:58.761689 progress 5 % (0 MB)
130 23:51:58.785797 progress 10 % (0 MB)
131 23:51:58.810859 progress 15 % (1 MB)
132 23:51:58.835107 progress 20 % (1 MB)
133 23:51:58.860429 progress 25 % (2 MB)
134 23:51:58.884968 progress 30 % (2 MB)
135 23:51:58.907984 progress 35 % (2 MB)
136 23:51:58.931755 progress 40 % (3 MB)
137 23:51:58.958060 progress 45 % (3 MB)
138 23:51:58.981723 progress 50 % (4 MB)
139 23:51:59.006330 progress 55 % (4 MB)
140 23:51:59.030382 progress 60 % (4 MB)
141 23:51:59.053931 progress 65 % (5 MB)
142 23:51:59.079932 progress 70 % (5 MB)
143 23:51:59.104512 progress 75 % (6 MB)
144 23:51:59.127704 progress 80 % (6 MB)
145 23:51:59.152937 progress 85 % (7 MB)
146 23:51:59.176176 progress 90 % (7 MB)
147 23:51:59.204662 progress 95 % (7 MB)
148 23:51:59.232094 progress 100 % (8 MB)
149 23:51:59.237426 8 MB downloaded in 0.50 s (16.42 MB/s)
150 23:51:59.237683 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:51:59.237981 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:51:59.238091 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 23:51:59.238205 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 23:52:00.834049 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy
156 23:52:00.834252 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:52:00.834350 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 23:52:00.834517 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn
159 23:52:00.834644 makedir: /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin
160 23:52:00.834745 makedir: /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/tests
161 23:52:00.834842 makedir: /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/results
162 23:52:00.834947 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-add-keys
163 23:52:00.835086 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-add-sources
164 23:52:00.835213 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-background-process-start
165 23:52:00.835347 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-background-process-stop
166 23:52:00.835471 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-common-functions
167 23:52:00.835595 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-echo-ipv4
168 23:52:00.835725 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-install-packages
169 23:52:00.835846 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-installed-packages
170 23:52:00.835966 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-os-build
171 23:52:00.836095 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-probe-channel
172 23:52:00.836216 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-probe-ip
173 23:52:00.836337 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-target-ip
174 23:52:00.836465 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-target-mac
175 23:52:00.836766 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-target-storage
176 23:52:00.836896 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-case
177 23:52:00.837021 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-event
178 23:52:00.837149 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-feedback
179 23:52:00.837272 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-raise
180 23:52:00.837393 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-reference
181 23:52:00.837520 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-runner
182 23:52:00.837642 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-set
183 23:52:00.837764 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-test-shell
184 23:52:00.837892 Updating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-install-packages (oe)
185 23:52:00.838041 Updating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/bin/lava-installed-packages (oe)
186 23:52:00.838158 Creating /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/environment
187 23:52:00.838259 LAVA metadata
188 23:52:00.838326 - LAVA_JOB_ID=14084347
189 23:52:00.838386 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:52:00.838482 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 23:52:00.838547 skipped lava-vland-overlay
192 23:52:00.838619 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:52:00.838703 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 23:52:00.838763 skipped lava-multinode-overlay
195 23:52:00.838833 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:52:00.838908 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 23:52:00.838979 Loading test definitions
198 23:52:00.839070 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 23:52:00.839142 Using /lava-14084347 at stage 0
200 23:52:00.839441 uuid=14084347_1.6.2.3.1 testdef=None
201 23:52:00.839528 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:52:00.839612 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 23:52:00.840093 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:52:00.840316 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 23:52:00.840953 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:52:00.841183 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 23:52:00.841765 runner path: /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/0/tests/0_lc-compliance test_uuid 14084347_1.6.2.3.1
210 23:52:00.841920 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:52:00.842126 Creating lava-test-runner.conf files
213 23:52:00.842188 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084347/lava-overlay-7g1qorfn/lava-14084347/0 for stage 0
214 23:52:00.842274 - 0_lc-compliance
215 23:52:00.842370 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:52:00.842452 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 23:52:00.848370 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:52:00.848475 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 23:52:00.848562 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:52:00.848679 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:52:00.848767 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 23:52:01.012098 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:52:01.012461 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 23:52:01.012611 extracting modules file /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy
225 23:52:01.226831 extracting modules file /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084347/extract-overlay-ramdisk-pyplqdbe/ramdisk
226 23:52:01.446289 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:52:01.446455 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 23:52:01.446548 [common] Applying overlay to NFS
229 23:52:01.446618 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084347/compress-overlay-601w5zm0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy
230 23:52:01.453223 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:52:01.453340 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 23:52:01.453432 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:52:01.453521 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 23:52:01.453599 Building ramdisk /var/lib/lava/dispatcher/tmp/14084347/extract-overlay-ramdisk-pyplqdbe/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084347/extract-overlay-ramdisk-pyplqdbe/ramdisk
235 23:52:01.793093 >> 130335 blocks
236 23:52:03.909593 rename /var/lib/lava/dispatcher/tmp/14084347/extract-overlay-ramdisk-pyplqdbe/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/ramdisk/ramdisk.cpio.gz
237 23:52:03.910040 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:52:03.910165 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 23:52:03.910266 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 23:52:03.910371 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/kernel/Image']
241 23:52:16.952446 Returned 0 in 13 seconds
242 23:52:17.053158 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/kernel/image.itb
243 23:52:17.426167 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:52:17.426526 output: Created: Thu May 30 00:52:17 2024
245 23:52:17.426598 output: Image 0 (kernel-1)
246 23:52:17.426659 output: Description:
247 23:52:17.426719 output: Created: Thu May 30 00:52:17 2024
248 23:52:17.426779 output: Type: Kernel Image
249 23:52:17.426836 output: Compression: lzma compressed
250 23:52:17.426893 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
251 23:52:17.426951 output: Architecture: AArch64
252 23:52:17.427010 output: OS: Linux
253 23:52:17.427069 output: Load Address: 0x00000000
254 23:52:17.427126 output: Entry Point: 0x00000000
255 23:52:17.427184 output: Hash algo: crc32
256 23:52:17.427238 output: Hash value: 907bf91d
257 23:52:17.427296 output: Image 1 (fdt-1)
258 23:52:17.427353 output: Description: mt8192-asurada-spherion-r0
259 23:52:17.427407 output: Created: Thu May 30 00:52:17 2024
260 23:52:17.427464 output: Type: Flat Device Tree
261 23:52:17.427518 output: Compression: uncompressed
262 23:52:17.427570 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 23:52:17.427622 output: Architecture: AArch64
264 23:52:17.427674 output: Hash algo: crc32
265 23:52:17.427726 output: Hash value: 0f8e4d2e
266 23:52:17.427778 output: Image 2 (ramdisk-1)
267 23:52:17.427830 output: Description: unavailable
268 23:52:17.427882 output: Created: Thu May 30 00:52:17 2024
269 23:52:17.427934 output: Type: RAMDisk Image
270 23:52:17.427986 output: Compression: Unknown Compression
271 23:52:17.428038 output: Data Size: 18727384 Bytes = 18288.46 KiB = 17.86 MiB
272 23:52:17.428090 output: Architecture: AArch64
273 23:52:17.428142 output: OS: Linux
274 23:52:17.428194 output: Load Address: unavailable
275 23:52:17.428246 output: Entry Point: unavailable
276 23:52:17.428297 output: Hash algo: crc32
277 23:52:17.428349 output: Hash value: 8a77ef82
278 23:52:17.428422 output: Default Configuration: 'conf-1'
279 23:52:17.428504 output: Configuration 0 (conf-1)
280 23:52:17.428620 output: Description: mt8192-asurada-spherion-r0
281 23:52:17.428675 output: Kernel: kernel-1
282 23:52:17.428728 output: Init Ramdisk: ramdisk-1
283 23:52:17.428780 output: FDT: fdt-1
284 23:52:17.428833 output: Loadables: kernel-1
285 23:52:17.428885 output:
286 23:52:17.429103 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 23:52:17.429203 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 23:52:17.429309 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 23:52:17.429404 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 23:52:17.429480 No LXC device requested
291 23:52:17.429558 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:52:17.429640 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 23:52:17.429716 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:52:17.429782 Checking files for TFTP limit of 4294967296 bytes.
295 23:52:17.430289 end: 1 tftp-deploy (duration 00:00:23) [common]
296 23:52:17.430398 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:52:17.430532 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:52:17.430665 substitutions:
299 23:52:17.430731 - {DTB}: 14084347/tftp-deploy-zua2va7t/dtb/mt8192-asurada-spherion-r0.dtb
300 23:52:17.430797 - {INITRD}: 14084347/tftp-deploy-zua2va7t/ramdisk/ramdisk.cpio.gz
301 23:52:17.430855 - {KERNEL}: 14084347/tftp-deploy-zua2va7t/kernel/Image
302 23:52:17.430913 - {LAVA_MAC}: None
303 23:52:17.430968 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy
304 23:52:17.431055 - {NFS_SERVER_IP}: 192.168.201.1
305 23:52:17.431141 - {PRESEED_CONFIG}: None
306 23:52:17.431228 - {PRESEED_LOCAL}: None
307 23:52:17.431310 - {RAMDISK}: 14084347/tftp-deploy-zua2va7t/ramdisk/ramdisk.cpio.gz
308 23:52:17.431392 - {ROOT_PART}: None
309 23:52:17.431473 - {ROOT}: None
310 23:52:17.431531 - {SERVER_IP}: 192.168.201.1
311 23:52:17.431589 - {TEE}: None
312 23:52:17.431643 Parsed boot commands:
313 23:52:17.431695 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:52:17.431876 Parsed boot commands: tftpboot 192.168.201.1 14084347/tftp-deploy-zua2va7t/kernel/image.itb 14084347/tftp-deploy-zua2va7t/kernel/cmdline
315 23:52:17.431965 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:52:17.432053 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:52:17.432141 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:52:17.432226 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:52:17.432297 Not connected, no need to disconnect.
320 23:52:17.432370 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:52:17.432451 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:52:17.432523 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 23:52:17.436257 Setting prompt string to ['lava-test: # ']
324 23:52:17.436724 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:52:17.436875 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:52:17.436989 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:52:17.437077 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:52:17.437296 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
329 23:52:22.587387 >> Command sent successfully.
330 23:52:22.597836 Returned 0 in 5 seconds
331 23:52:22.699053 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 23:52:22.700499 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 23:52:22.701305 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 23:52:22.701984 Setting prompt string to 'Starting depthcharge on Spherion...'
336 23:52:22.702438 Changing prompt to 'Starting depthcharge on Spherion...'
337 23:52:22.702812 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 23:52:22.704923 [Enter `^Ec?' for help]
339 23:52:22.861322
340 23:52:22.861845
341 23:52:22.862235 F0: 102B 0000
342 23:52:22.862592
343 23:52:22.862936 F3: 1001 0000 [0200]
344 23:52:22.863249
345 23:52:22.864847 F3: 1001 0000
346 23:52:22.865302
347 23:52:22.865639 F7: 102D 0000
348 23:52:22.865982
349 23:52:22.866309 F1: 0000 0000
350 23:52:22.868523
351 23:52:22.869021 V0: 0000 0000 [0001]
352 23:52:22.869428
353 23:52:22.869770 00: 0007 8000
354 23:52:22.870159
355 23:52:22.872637 01: 0000 0000
356 23:52:22.873106
357 23:52:22.873478 BP: 0C00 0209 [0000]
358 23:52:22.873829
359 23:52:22.876272 G0: 1182 0000
360 23:52:22.876741
361 23:52:22.877108 EC: 0000 0021 [4000]
362 23:52:22.877451
363 23:52:22.879781 S7: 0000 0000 [0000]
364 23:52:22.880226
365 23:52:22.880592 CC: 0000 0000 [0001]
366 23:52:22.880949
367 23:52:22.882950 T0: 0000 0040 [010F]
368 23:52:22.883439
369 23:52:22.883776 Jump to BL
370 23:52:22.884122
371 23:52:22.908081
372 23:52:22.908534
373 23:52:22.915730 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
374 23:52:22.918795 ARM64: Exception handlers installed.
375 23:52:22.922551 ARM64: Testing exception
376 23:52:22.925697 ARM64: Done test exception
377 23:52:22.933258 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
378 23:52:22.944323 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
379 23:52:22.950664 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
380 23:52:22.960696 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
381 23:52:22.967414 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
382 23:52:22.974158 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
383 23:52:22.984733 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
384 23:52:22.991445 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
385 23:52:23.011114 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
386 23:52:23.014325 WDT: Last reset was cold boot
387 23:52:23.017452 SPI1(PAD0) initialized at 2873684 Hz
388 23:52:23.021131 SPI5(PAD0) initialized at 992727 Hz
389 23:52:23.024411 VBOOT: Loading verstage.
390 23:52:23.030843 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
391 23:52:23.034358 FMAP: Found "FLASH" version 1.1 at 0x20000.
392 23:52:23.037411 FMAP: base = 0x0 size = 0x800000 #areas = 25
393 23:52:23.040920 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
394 23:52:23.048427 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
395 23:52:23.055159 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
396 23:52:23.065926 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
397 23:52:23.066383
398 23:52:23.066752
399 23:52:23.076415 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
400 23:52:23.079692 ARM64: Exception handlers installed.
401 23:52:23.082862 ARM64: Testing exception
402 23:52:23.083342 ARM64: Done test exception
403 23:52:23.089649 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
404 23:52:23.093123 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 23:52:23.107447 Probing TPM: . done!
406 23:52:23.107872 TPM ready after 0 ms
407 23:52:23.113425 Connected to device vid:did:rid of 1ae0:0028:00
408 23:52:23.161801 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
409 23:52:23.162265 Initialized TPM device CR50 revision 0
410 23:52:23.173649 tlcl_send_startup: Startup return code is 0
411 23:52:23.174114 TPM: setup succeeded
412 23:52:23.184666 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
413 23:52:23.193970 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
414 23:52:23.205612 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
415 23:52:23.214468 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
416 23:52:23.217590 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
417 23:52:23.221804 in-header: 03 07 00 00 08 00 00 00
418 23:52:23.225724 in-data: aa e4 47 04 13 02 00 00
419 23:52:23.228775 Chrome EC: UHEPI supported
420 23:52:23.235410 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
421 23:52:23.239381 in-header: 03 9d 00 00 08 00 00 00
422 23:52:23.243236 in-data: 10 20 20 08 00 00 00 00
423 23:52:23.243667 Phase 1
424 23:52:23.250244 FMAP: area GBB found @ 3f5000 (12032 bytes)
425 23:52:23.254290 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
426 23:52:23.262336 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
427 23:52:23.262860 Recovery requested (1009000e)
428 23:52:23.270585 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 23:52:23.276300 tlcl_extend: response is 0
430 23:52:23.284224 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 23:52:23.289869 tlcl_extend: response is 0
432 23:52:23.296246 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 23:52:23.317319 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
434 23:52:23.324625 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 23:52:23.325051
436 23:52:23.325479
437 23:52:23.331589 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 23:52:23.335483 ARM64: Exception handlers installed.
439 23:52:23.338827 ARM64: Testing exception
440 23:52:23.342504 ARM64: Done test exception
441 23:52:23.362847 pmic_efuse_setting: Set efuses in 11 msecs
442 23:52:23.366547 pmwrap_interface_init: Select PMIF_VLD_RDY
443 23:52:23.370286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 23:52:23.377984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 23:52:23.381376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 23:52:23.385115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 23:52:23.392468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 23:52:23.396116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 23:52:23.399635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 23:52:23.406446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 23:52:23.410303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 23:52:23.413589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 23:52:23.419897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 23:52:23.423749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 23:52:23.426555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 23:52:23.433930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 23:52:23.440441 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 23:52:23.446882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 23:52:23.450159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 23:52:23.456796 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 23:52:23.464113 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 23:52:23.467512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 23:52:23.474600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 23:52:23.478518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 23:52:23.485165 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 23:52:23.492065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 23:52:23.495761 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 23:52:23.502554 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 23:52:23.505556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 23:52:23.512536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 23:52:23.515871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 23:52:23.519487 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 23:52:23.526679 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 23:52:23.530397 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 23:52:23.538058 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 23:52:23.541774 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 23:52:23.545348 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 23:52:23.552643 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 23:52:23.556711 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 23:52:23.559357 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 23:52:23.566386 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 23:52:23.569612 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 23:52:23.572897 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 23:52:23.579810 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 23:52:23.583142 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 23:52:23.586577 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 23:52:23.592896 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 23:52:23.596441 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 23:52:23.599566 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 23:52:23.605874 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 23:52:23.609426 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 23:52:23.612937 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 23:52:23.616040 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 23:52:23.625971 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 23:52:23.632875 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 23:52:23.639179 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 23:52:23.646476 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 23:52:23.656613 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 23:52:23.659168 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 23:52:23.662796 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 23:52:23.669292 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:52:23.676177 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x23
503 23:52:23.679350 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 23:52:23.686503 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
505 23:52:23.689924 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 23:52:23.699608 [RTC]rtc_get_frequency_meter,154: input=15, output=794
507 23:52:23.702966 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
508 23:52:23.709690 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
509 23:52:23.712537 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
510 23:52:23.716277 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
511 23:52:23.719424 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
512 23:52:23.722771 ADC[4]: Raw value=897780 ID=7
513 23:52:23.726029 ADC[3]: Raw value=213440 ID=1
514 23:52:23.726448 RAM Code: 0x71
515 23:52:23.732536 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
516 23:52:23.735786 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
517 23:52:23.745759 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
518 23:52:23.753737 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
519 23:52:23.756322 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
520 23:52:23.760198 in-header: 03 07 00 00 08 00 00 00
521 23:52:23.763253 in-data: aa e4 47 04 13 02 00 00
522 23:52:23.766741 Chrome EC: UHEPI supported
523 23:52:23.769808 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
524 23:52:23.773809 in-header: 03 d5 00 00 08 00 00 00
525 23:52:23.777678 in-data: 98 20 60 08 00 00 00 00
526 23:52:23.781493 MRC: failed to locate region type 0.
527 23:52:23.788427 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
528 23:52:23.792126 DRAM-K: Running full calibration
529 23:52:23.799019 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
530 23:52:23.799439 header.status = 0x0
531 23:52:23.802123 header.version = 0x6 (expected: 0x6)
532 23:52:23.805637 header.size = 0xd00 (expected: 0xd00)
533 23:52:23.809327 header.flags = 0x0
534 23:52:23.812612 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
535 23:52:23.831497 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
536 23:52:23.838079 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
537 23:52:23.841685 dram_init: ddr_geometry: 2
538 23:52:23.842104 [EMI] MDL number = 2
539 23:52:23.845314 [EMI] Get MDL freq = 0
540 23:52:23.848919 dram_init: ddr_type: 0
541 23:52:23.849350 is_discrete_lpddr4: 1
542 23:52:23.852546 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
543 23:52:23.853017
544 23:52:23.853381
545 23:52:23.855904 [Bian_co] ETT version 0.0.0.1
546 23:52:23.859500 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
547 23:52:23.859941
548 23:52:23.863199 dramc_set_vcore_voltage set vcore to 650000
549 23:52:23.866792 Read voltage for 800, 4
550 23:52:23.867208 Vio18 = 0
551 23:52:23.867540 Vcore = 650000
552 23:52:23.870942 Vdram = 0
553 23:52:23.871360 Vddq = 0
554 23:52:23.871690 Vmddr = 0
555 23:52:23.874683 dram_init: config_dvfs: 1
556 23:52:23.878555 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
557 23:52:23.885199 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
558 23:52:23.889371 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
559 23:52:23.892898 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
560 23:52:23.896826 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
561 23:52:23.900187 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
562 23:52:23.900623 MEM_TYPE=3, freq_sel=18
563 23:52:23.903821 sv_algorithm_assistance_LP4_1600
564 23:52:23.907811 ============ PULL DRAM RESETB DOWN ============
565 23:52:23.911726 ========== PULL DRAM RESETB DOWN end =========
566 23:52:23.918721 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
567 23:52:23.922602 ===================================
568 23:52:23.923020 LPDDR4 DRAM CONFIGURATION
569 23:52:23.926117 ===================================
570 23:52:23.929794 EX_ROW_EN[0] = 0x0
571 23:52:23.930227 EX_ROW_EN[1] = 0x0
572 23:52:23.933105 LP4Y_EN = 0x0
573 23:52:23.933563 WORK_FSP = 0x0
574 23:52:23.936369 WL = 0x2
575 23:52:23.936793 RL = 0x2
576 23:52:23.939787 BL = 0x2
577 23:52:23.940231 RPST = 0x0
578 23:52:23.943221 RD_PRE = 0x0
579 23:52:23.943675 WR_PRE = 0x1
580 23:52:23.946755 WR_PST = 0x0
581 23:52:23.947211 DBI_WR = 0x0
582 23:52:23.949978 DBI_RD = 0x0
583 23:52:23.950433 OTF = 0x1
584 23:52:23.953544 ===================================
585 23:52:23.956924 ===================================
586 23:52:23.960028 ANA top config
587 23:52:23.963158 ===================================
588 23:52:23.963604 DLL_ASYNC_EN = 0
589 23:52:23.966461 ALL_SLAVE_EN = 1
590 23:52:23.970009 NEW_RANK_MODE = 1
591 23:52:23.973161 DLL_IDLE_MODE = 1
592 23:52:23.976526 LP45_APHY_COMB_EN = 1
593 23:52:23.976984 TX_ODT_DIS = 1
594 23:52:23.979995 NEW_8X_MODE = 1
595 23:52:23.983183 ===================================
596 23:52:23.986700 ===================================
597 23:52:23.990405 data_rate = 1600
598 23:52:23.993650 CKR = 1
599 23:52:23.997239 DQ_P2S_RATIO = 8
600 23:52:24.000286 ===================================
601 23:52:24.000821 CA_P2S_RATIO = 8
602 23:52:24.003561 DQ_CA_OPEN = 0
603 23:52:24.006800 DQ_SEMI_OPEN = 0
604 23:52:24.010160 CA_SEMI_OPEN = 0
605 23:52:24.013604 CA_FULL_RATE = 0
606 23:52:24.017068 DQ_CKDIV4_EN = 1
607 23:52:24.017516 CA_CKDIV4_EN = 1
608 23:52:24.020163 CA_PREDIV_EN = 0
609 23:52:24.023618 PH8_DLY = 0
610 23:52:24.026845 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
611 23:52:24.030075 DQ_AAMCK_DIV = 4
612 23:52:24.030522 CA_AAMCK_DIV = 4
613 23:52:24.033405 CA_ADMCK_DIV = 4
614 23:52:24.036837 DQ_TRACK_CA_EN = 0
615 23:52:24.040160 CA_PICK = 800
616 23:52:24.043363 CA_MCKIO = 800
617 23:52:24.046891 MCKIO_SEMI = 0
618 23:52:24.050050 PLL_FREQ = 3068
619 23:52:24.050528 DQ_UI_PI_RATIO = 32
620 23:52:24.053268 CA_UI_PI_RATIO = 0
621 23:52:24.057028 ===================================
622 23:52:24.060028 ===================================
623 23:52:24.063484 memory_type:LPDDR4
624 23:52:24.067218 GP_NUM : 10
625 23:52:24.067697 SRAM_EN : 1
626 23:52:24.070230 MD32_EN : 0
627 23:52:24.073292 ===================================
628 23:52:24.076779 [ANA_INIT] >>>>>>>>>>>>>>
629 23:52:24.077242 <<<<<< [CONFIGURE PHASE]: ANA_TX
630 23:52:24.080089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
631 23:52:24.083275 ===================================
632 23:52:24.086637 data_rate = 1600,PCW = 0X7600
633 23:52:24.090287 ===================================
634 23:52:24.093148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
635 23:52:24.099912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
636 23:52:24.106775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 23:52:24.109747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
638 23:52:24.113864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
639 23:52:24.116977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
640 23:52:24.120903 [ANA_INIT] flow start
641 23:52:24.121334 [ANA_INIT] PLL >>>>>>>>
642 23:52:24.124492 [ANA_INIT] PLL <<<<<<<<
643 23:52:24.124963 [ANA_INIT] MIDPI >>>>>>>>
644 23:52:24.128334 [ANA_INIT] MIDPI <<<<<<<<
645 23:52:24.132176 [ANA_INIT] DLL >>>>>>>>
646 23:52:24.132628 [ANA_INIT] flow end
647 23:52:24.135608 ============ LP4 DIFF to SE enter ============
648 23:52:24.139431 ============ LP4 DIFF to SE exit ============
649 23:52:24.143336 [ANA_INIT] <<<<<<<<<<<<<
650 23:52:24.146989 [Flow] Enable top DCM control >>>>>
651 23:52:24.150077 [Flow] Enable top DCM control <<<<<
652 23:52:24.154020 Enable DLL master slave shuffle
653 23:52:24.157720 ==============================================================
654 23:52:24.161200 Gating Mode config
655 23:52:24.164425 ==============================================================
656 23:52:24.167573 Config description:
657 23:52:24.177797 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
658 23:52:24.184384 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
659 23:52:24.187702 SELPH_MODE 0: By rank 1: By Phase
660 23:52:24.194806 ==============================================================
661 23:52:24.197750 GAT_TRACK_EN = 1
662 23:52:24.201388 RX_GATING_MODE = 2
663 23:52:24.201820 RX_GATING_TRACK_MODE = 2
664 23:52:24.204633 SELPH_MODE = 1
665 23:52:24.207729 PICG_EARLY_EN = 1
666 23:52:24.211392 VALID_LAT_VALUE = 1
667 23:52:24.217780 ==============================================================
668 23:52:24.221112 Enter into Gating configuration >>>>
669 23:52:24.224635 Exit from Gating configuration <<<<
670 23:52:24.227675 Enter into DVFS_PRE_config >>>>>
671 23:52:24.237797 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
672 23:52:24.241750 Exit from DVFS_PRE_config <<<<<
673 23:52:24.245002 Enter into PICG configuration >>>>
674 23:52:24.248600 Exit from PICG configuration <<<<
675 23:52:24.252332 [RX_INPUT] configuration >>>>>
676 23:52:24.252796 [RX_INPUT] configuration <<<<<
677 23:52:24.259544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
678 23:52:24.262859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
679 23:52:24.270004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
680 23:52:24.277093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
681 23:52:24.280976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
682 23:52:24.287734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
683 23:52:24.291107 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
684 23:52:24.295123 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
685 23:52:24.301983 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
686 23:52:24.306106 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
687 23:52:24.309487 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
688 23:52:24.312679 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
689 23:52:24.317073 ===================================
690 23:52:24.320643 LPDDR4 DRAM CONFIGURATION
691 23:52:24.321065 ===================================
692 23:52:24.324199 EX_ROW_EN[0] = 0x0
693 23:52:24.328170 EX_ROW_EN[1] = 0x0
694 23:52:24.328620 LP4Y_EN = 0x0
695 23:52:24.328966 WORK_FSP = 0x0
696 23:52:24.331353 WL = 0x2
697 23:52:24.331887 RL = 0x2
698 23:52:24.335293 BL = 0x2
699 23:52:24.335722 RPST = 0x0
700 23:52:24.338964 RD_PRE = 0x0
701 23:52:24.339378 WR_PRE = 0x1
702 23:52:24.342579 WR_PST = 0x0
703 23:52:24.342994 DBI_WR = 0x0
704 23:52:24.346206 DBI_RD = 0x0
705 23:52:24.346621 OTF = 0x1
706 23:52:24.349788 ===================================
707 23:52:24.353760 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
708 23:52:24.357731 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
709 23:52:24.361265 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
710 23:52:24.364987 ===================================
711 23:52:24.368594 LPDDR4 DRAM CONFIGURATION
712 23:52:24.372066 ===================================
713 23:52:24.375301 EX_ROW_EN[0] = 0x10
714 23:52:24.375775 EX_ROW_EN[1] = 0x0
715 23:52:24.378844 LP4Y_EN = 0x0
716 23:52:24.379277 WORK_FSP = 0x0
717 23:52:24.383273 WL = 0x2
718 23:52:24.383711 RL = 0x2
719 23:52:24.384156 BL = 0x2
720 23:52:24.386973 RPST = 0x0
721 23:52:24.387410 RD_PRE = 0x0
722 23:52:24.391209 WR_PRE = 0x1
723 23:52:24.391731 WR_PST = 0x0
724 23:52:24.394386 DBI_WR = 0x0
725 23:52:24.394850 DBI_RD = 0x0
726 23:52:24.398006 OTF = 0x1
727 23:52:24.401902 ===================================
728 23:52:24.404881 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
729 23:52:24.410137 nWR fixed to 40
730 23:52:24.413432 [ModeRegInit_LP4] CH0 RK0
731 23:52:24.413928 [ModeRegInit_LP4] CH0 RK1
732 23:52:24.416893 [ModeRegInit_LP4] CH1 RK0
733 23:52:24.420855 [ModeRegInit_LP4] CH1 RK1
734 23:52:24.421324 match AC timing 13
735 23:52:24.424218 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
736 23:52:24.427425 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
737 23:52:24.435332 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
738 23:52:24.438916 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
739 23:52:24.442888 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
740 23:52:24.446302 [EMI DOE] emi_dcm 0
741 23:52:24.450182 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
742 23:52:24.450677 ==
743 23:52:24.453783 Dram Type= 6, Freq= 0, CH_0, rank 0
744 23:52:24.457619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
745 23:52:24.458085 ==
746 23:52:24.461064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
747 23:52:24.468191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
748 23:52:24.477795 [CA 0] Center 38 (7~69) winsize 63
749 23:52:24.481851 [CA 1] Center 37 (7~68) winsize 62
750 23:52:24.485794 [CA 2] Center 35 (5~66) winsize 62
751 23:52:24.489237 [CA 3] Center 35 (5~66) winsize 62
752 23:52:24.493454 [CA 4] Center 34 (4~65) winsize 62
753 23:52:24.493954 [CA 5] Center 34 (4~65) winsize 62
754 23:52:24.494317
755 23:52:24.496617 [CmdBusTrainingLP45] Vref(ca) range 1: 32
756 23:52:24.497114
757 23:52:24.500606 [CATrainingPosCal] consider 1 rank data
758 23:52:24.503906 u2DelayCellTimex100 = 270/100 ps
759 23:52:24.508067 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
760 23:52:24.511733 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
761 23:52:24.515450 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
762 23:52:24.519304 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
763 23:52:24.522917 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
764 23:52:24.526990 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
765 23:52:24.527419
766 23:52:24.530468 CA PerBit enable=1, Macro0, CA PI delay=34
767 23:52:24.530892
768 23:52:24.534148 [CBTSetCACLKResult] CA Dly = 34
769 23:52:24.534574 CS Dly: 5 (0~36)
770 23:52:24.534909 ==
771 23:52:24.537606 Dram Type= 6, Freq= 0, CH_0, rank 1
772 23:52:24.541442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:52:24.544601 ==
774 23:52:24.548355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
775 23:52:24.554589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
776 23:52:24.563530 [CA 0] Center 38 (7~69) winsize 63
777 23:52:24.567133 [CA 1] Center 38 (7~69) winsize 63
778 23:52:24.569971 [CA 2] Center 35 (5~66) winsize 62
779 23:52:24.573602 [CA 3] Center 35 (5~66) winsize 62
780 23:52:24.576746 [CA 4] Center 34 (4~65) winsize 62
781 23:52:24.580633 [CA 5] Center 34 (4~65) winsize 62
782 23:52:24.581123
783 23:52:24.583809 [CmdBusTrainingLP45] Vref(ca) range 1: 30
784 23:52:24.584224
785 23:52:24.587266 [CATrainingPosCal] consider 2 rank data
786 23:52:24.590293 u2DelayCellTimex100 = 270/100 ps
787 23:52:24.593851 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
788 23:52:24.597373 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
789 23:52:24.600505 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
790 23:52:24.607325 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
791 23:52:24.610629 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
792 23:52:24.613852 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
793 23:52:24.614349
794 23:52:24.616863 CA PerBit enable=1, Macro0, CA PI delay=34
795 23:52:24.617312
796 23:52:24.620681 [CBTSetCACLKResult] CA Dly = 34
797 23:52:24.621175 CS Dly: 5 (0~37)
798 23:52:24.621523
799 23:52:24.623244 ----->DramcWriteLeveling(PI) begin...
800 23:52:24.626780 ==
801 23:52:24.627268 Dram Type= 6, Freq= 0, CH_0, rank 0
802 23:52:24.633493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
803 23:52:24.633966 ==
804 23:52:24.637379 Write leveling (Byte 0): 32 => 32
805 23:52:24.640264 Write leveling (Byte 1): 28 => 28
806 23:52:24.641102 DramcWriteLeveling(PI) end<-----
807 23:52:24.643647
808 23:52:24.644058 ==
809 23:52:24.647048 Dram Type= 6, Freq= 0, CH_0, rank 0
810 23:52:24.650375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:52:24.650794 ==
812 23:52:24.653396 [Gating] SW mode calibration
813 23:52:24.660748 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
814 23:52:24.663586 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
815 23:52:24.670102 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
816 23:52:24.673748 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 23:52:24.676883 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
818 23:52:24.683670 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
819 23:52:24.687172 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 23:52:24.690401 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 23:52:24.697279 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:52:24.700331 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:52:24.704133 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:52:24.707950 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:52:24.711945 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:52:24.718968 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:52:24.722179 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:52:24.725543 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:52:24.733188 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:52:24.736647 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:52:24.739282 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:52:24.742942 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:52:24.749392 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
834 23:52:24.752709 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:52:24.756287 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:52:24.762708 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:52:24.765977 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:52:24.769706 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:52:24.776150 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:52:24.779530 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:52:24.783207 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:52:24.789690 0 9 12 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
843 23:52:24.792831 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
844 23:52:24.796162 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 23:52:24.799701 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 23:52:24.806162 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 23:52:24.809604 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 23:52:24.812996 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 23:52:24.819610 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
850 23:52:24.823024 0 10 12 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
851 23:52:24.826770 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
852 23:52:24.832880 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 23:52:24.836505 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 23:52:24.839748 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:52:24.846563 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:52:24.849493 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:52:24.853097 0 11 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
858 23:52:24.859716 0 11 12 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
859 23:52:24.862947 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 23:52:24.866370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 23:52:24.872803 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 23:52:24.876296 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 23:52:24.879639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 23:52:24.883251 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 23:52:24.889798 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
866 23:52:24.892880 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
867 23:52:24.896479 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 23:52:24.902849 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 23:52:24.906311 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 23:52:24.909786 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 23:52:24.916555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 23:52:24.919503 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 23:52:24.922854 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 23:52:24.929493 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:52:24.933161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:52:24.936393 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:52:24.942891 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:52:24.946211 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:52:24.949615 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:52:24.956159 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:52:24.959424 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
882 23:52:24.962815 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
883 23:52:24.966002 Total UI for P1: 0, mck2ui 16
884 23:52:24.969814 best dqsien dly found for B0: ( 0, 14, 8)
885 23:52:24.976591 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 23:52:24.977014 Total UI for P1: 0, mck2ui 16
887 23:52:24.979541 best dqsien dly found for B1: ( 0, 14, 12)
888 23:52:24.982884 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
889 23:52:24.989790 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
890 23:52:24.990208
891 23:52:24.992821 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
892 23:52:24.996101 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
893 23:52:24.999431 [Gating] SW calibration Done
894 23:52:24.999848 ==
895 23:52:25.002672 Dram Type= 6, Freq= 0, CH_0, rank 0
896 23:52:25.006304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
897 23:52:25.006729 ==
898 23:52:25.009586 RX Vref Scan: 0
899 23:52:25.010052
900 23:52:25.010398 RX Vref 0 -> 0, step: 1
901 23:52:25.010782
902 23:52:25.012673 RX Delay -130 -> 252, step: 16
903 23:52:25.016246 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
904 23:52:25.019759 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
905 23:52:25.026025 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
906 23:52:25.029344 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
907 23:52:25.032990 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
908 23:52:25.036136 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
909 23:52:25.039480 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
910 23:52:25.046271 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
911 23:52:25.049555 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
912 23:52:25.052874 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
913 23:52:25.056324 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
914 23:52:25.059620 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
915 23:52:25.066316 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
916 23:52:25.069997 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
917 23:52:25.073054 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
918 23:52:25.076478 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
919 23:52:25.076926 ==
920 23:52:25.079630 Dram Type= 6, Freq= 0, CH_0, rank 0
921 23:52:25.086064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 23:52:25.086500 ==
923 23:52:25.086840 DQS Delay:
924 23:52:25.089507 DQS0 = 0, DQS1 = 0
925 23:52:25.089929 DQM Delay:
926 23:52:25.090264 DQM0 = 79, DQM1 = 69
927 23:52:25.092853 DQ Delay:
928 23:52:25.096595 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
929 23:52:25.099815 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
930 23:52:25.100238 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
931 23:52:25.106637 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
932 23:52:25.107060
933 23:52:25.107397
934 23:52:25.107706 ==
935 23:52:25.109980 Dram Type= 6, Freq= 0, CH_0, rank 0
936 23:52:25.113844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 23:52:25.114298 ==
938 23:52:25.114639
939 23:52:25.114956
940 23:52:25.115255 TX Vref Scan disable
941 23:52:25.117816 == TX Byte 0 ==
942 23:52:25.121192 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
943 23:52:25.124399 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
944 23:52:25.127858 == TX Byte 1 ==
945 23:52:25.130797 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 23:52:25.134407 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 23:52:25.137530 ==
948 23:52:25.140867 Dram Type= 6, Freq= 0, CH_0, rank 0
949 23:52:25.144675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 23:52:25.145121 ==
951 23:52:25.157056 TX Vref=22, minBit 11, minWin=26, winSum=439
952 23:52:25.160328 TX Vref=24, minBit 0, minWin=27, winSum=444
953 23:52:25.164065 TX Vref=26, minBit 5, minWin=27, winSum=444
954 23:52:25.167318 TX Vref=28, minBit 15, minWin=27, winSum=450
955 23:52:25.170498 TX Vref=30, minBit 4, minWin=27, winSum=443
956 23:52:25.176971 TX Vref=32, minBit 10, minWin=27, winSum=445
957 23:52:25.180695 [TxChooseVref] Worse bit 15, Min win 27, Win sum 450, Final Vref 28
958 23:52:25.181067
959 23:52:25.183683 Final TX Range 1 Vref 28
960 23:52:25.184066
961 23:52:25.184405 ==
962 23:52:25.187443 Dram Type= 6, Freq= 0, CH_0, rank 0
963 23:52:25.190530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 23:52:25.193727 ==
965 23:52:25.194144
966 23:52:25.194477
967 23:52:25.194789 TX Vref Scan disable
968 23:52:25.197450 == TX Byte 0 ==
969 23:52:25.200802 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
970 23:52:25.204144 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
971 23:52:25.207160 == TX Byte 1 ==
972 23:52:25.210620 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 23:52:25.213978 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 23:52:25.217418
975 23:52:25.217832 [DATLAT]
976 23:52:25.218166 Freq=800, CH0 RK0
977 23:52:25.218480
978 23:52:25.220723 DATLAT Default: 0xa
979 23:52:25.221140 0, 0xFFFF, sum = 0
980 23:52:25.224299 1, 0xFFFF, sum = 0
981 23:52:25.224769 2, 0xFFFF, sum = 0
982 23:52:25.227692 3, 0xFFFF, sum = 0
983 23:52:25.228118 4, 0xFFFF, sum = 0
984 23:52:25.230927 5, 0xFFFF, sum = 0
985 23:52:25.231356 6, 0xFFFF, sum = 0
986 23:52:25.234234 7, 0xFFFF, sum = 0
987 23:52:25.237290 8, 0xFFFF, sum = 0
988 23:52:25.237714 9, 0x0, sum = 1
989 23:52:25.238060 10, 0x0, sum = 2
990 23:52:25.240825 11, 0x0, sum = 3
991 23:52:25.241253 12, 0x0, sum = 4
992 23:52:25.244094 best_step = 10
993 23:52:25.244514
994 23:52:25.244962 ==
995 23:52:25.247555 Dram Type= 6, Freq= 0, CH_0, rank 0
996 23:52:25.250468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 23:52:25.250898 ==
998 23:52:25.253956 RX Vref Scan: 1
999 23:52:25.254373
1000 23:52:25.254707 Set Vref Range= 32 -> 127
1001 23:52:25.257133
1002 23:52:25.257551 RX Vref 32 -> 127, step: 1
1003 23:52:25.257887
1004 23:52:25.261021 RX Delay -111 -> 252, step: 8
1005 23:52:25.261455
1006 23:52:25.263839 Set Vref, RX VrefLevel [Byte0]: 32
1007 23:52:25.267357 [Byte1]: 32
1008 23:52:25.267774
1009 23:52:25.270647 Set Vref, RX VrefLevel [Byte0]: 33
1010 23:52:25.273847 [Byte1]: 33
1011 23:52:25.277875
1012 23:52:25.278294 Set Vref, RX VrefLevel [Byte0]: 34
1013 23:52:25.281067 [Byte1]: 34
1014 23:52:25.285343
1015 23:52:25.285761 Set Vref, RX VrefLevel [Byte0]: 35
1016 23:52:25.288907 [Byte1]: 35
1017 23:52:25.293001
1018 23:52:25.293420 Set Vref, RX VrefLevel [Byte0]: 36
1019 23:52:25.296876 [Byte1]: 36
1020 23:52:25.301130
1021 23:52:25.301547 Set Vref, RX VrefLevel [Byte0]: 37
1022 23:52:25.304065 [Byte1]: 37
1023 23:52:25.308236
1024 23:52:25.308680 Set Vref, RX VrefLevel [Byte0]: 38
1025 23:52:25.312114 [Byte1]: 38
1026 23:52:25.316147
1027 23:52:25.316580 Set Vref, RX VrefLevel [Byte0]: 39
1028 23:52:25.319532 [Byte1]: 39
1029 23:52:25.324182
1030 23:52:25.324637 Set Vref, RX VrefLevel [Byte0]: 40
1031 23:52:25.327358 [Byte1]: 40
1032 23:52:25.331191
1033 23:52:25.331598 Set Vref, RX VrefLevel [Byte0]: 41
1034 23:52:25.335031 [Byte1]: 41
1035 23:52:25.339483
1036 23:52:25.339891 Set Vref, RX VrefLevel [Byte0]: 42
1037 23:52:25.342462 [Byte1]: 42
1038 23:52:25.346870
1039 23:52:25.347277 Set Vref, RX VrefLevel [Byte0]: 43
1040 23:52:25.350237 [Byte1]: 43
1041 23:52:25.354283
1042 23:52:25.354693 Set Vref, RX VrefLevel [Byte0]: 44
1043 23:52:25.357437 [Byte1]: 44
1044 23:52:25.361959
1045 23:52:25.362472 Set Vref, RX VrefLevel [Byte0]: 45
1046 23:52:25.365371 [Byte1]: 45
1047 23:52:25.369702
1048 23:52:25.370080 Set Vref, RX VrefLevel [Byte0]: 46
1049 23:52:25.373141 [Byte1]: 46
1050 23:52:25.377690
1051 23:52:25.378067 Set Vref, RX VrefLevel [Byte0]: 47
1052 23:52:25.380673 [Byte1]: 47
1053 23:52:25.384942
1054 23:52:25.388139 Set Vref, RX VrefLevel [Byte0]: 48
1055 23:52:25.388582 [Byte1]: 48
1056 23:52:25.393199
1057 23:52:25.393610 Set Vref, RX VrefLevel [Byte0]: 49
1058 23:52:25.396394 [Byte1]: 49
1059 23:52:25.400915
1060 23:52:25.401338 Set Vref, RX VrefLevel [Byte0]: 50
1061 23:52:25.403585 [Byte1]: 50
1062 23:52:25.408332
1063 23:52:25.408773 Set Vref, RX VrefLevel [Byte0]: 51
1064 23:52:25.411193 [Byte1]: 51
1065 23:52:25.415548
1066 23:52:25.415960 Set Vref, RX VrefLevel [Byte0]: 52
1067 23:52:25.418642 [Byte1]: 52
1068 23:52:25.423457
1069 23:52:25.423864 Set Vref, RX VrefLevel [Byte0]: 53
1070 23:52:25.426386 [Byte1]: 53
1071 23:52:25.430878
1072 23:52:25.431287 Set Vref, RX VrefLevel [Byte0]: 54
1073 23:52:25.433921 [Byte1]: 54
1074 23:52:25.438136
1075 23:52:25.438547 Set Vref, RX VrefLevel [Byte0]: 55
1076 23:52:25.441689 [Byte1]: 55
1077 23:52:25.446180
1078 23:52:25.446590 Set Vref, RX VrefLevel [Byte0]: 56
1079 23:52:25.449195 [Byte1]: 56
1080 23:52:25.454067
1081 23:52:25.454492 Set Vref, RX VrefLevel [Byte0]: 57
1082 23:52:25.456842 [Byte1]: 57
1083 23:52:25.461322
1084 23:52:25.461734 Set Vref, RX VrefLevel [Byte0]: 58
1085 23:52:25.464439 [Byte1]: 58
1086 23:52:25.469327
1087 23:52:25.469753 Set Vref, RX VrefLevel [Byte0]: 59
1088 23:52:25.472226 [Byte1]: 59
1089 23:52:25.476669
1090 23:52:25.477104 Set Vref, RX VrefLevel [Byte0]: 60
1091 23:52:25.479902 [Byte1]: 60
1092 23:52:25.484324
1093 23:52:25.484784 Set Vref, RX VrefLevel [Byte0]: 61
1094 23:52:25.487597 [Byte1]: 61
1095 23:52:25.491931
1096 23:52:25.492373 Set Vref, RX VrefLevel [Byte0]: 62
1097 23:52:25.495129 [Byte1]: 62
1098 23:52:25.499579
1099 23:52:25.499987 Set Vref, RX VrefLevel [Byte0]: 63
1100 23:52:25.502841 [Byte1]: 63
1101 23:52:25.506967
1102 23:52:25.507381 Set Vref, RX VrefLevel [Byte0]: 64
1103 23:52:25.513748 [Byte1]: 64
1104 23:52:25.514369
1105 23:52:25.517345 Set Vref, RX VrefLevel [Byte0]: 65
1106 23:52:25.520582 [Byte1]: 65
1107 23:52:25.521003
1108 23:52:25.523820 Set Vref, RX VrefLevel [Byte0]: 66
1109 23:52:25.527042 [Byte1]: 66
1110 23:52:25.527454
1111 23:52:25.530100 Set Vref, RX VrefLevel [Byte0]: 67
1112 23:52:25.534009 [Byte1]: 67
1113 23:52:25.537986
1114 23:52:25.538458 Set Vref, RX VrefLevel [Byte0]: 68
1115 23:52:25.541029 [Byte1]: 68
1116 23:52:25.545792
1117 23:52:25.546201 Set Vref, RX VrefLevel [Byte0]: 69
1118 23:52:25.548723 [Byte1]: 69
1119 23:52:25.553230
1120 23:52:25.553640 Set Vref, RX VrefLevel [Byte0]: 70
1121 23:52:25.556111 [Byte1]: 70
1122 23:52:25.560711
1123 23:52:25.561120 Set Vref, RX VrefLevel [Byte0]: 71
1124 23:52:25.563938 [Byte1]: 71
1125 23:52:25.568409
1126 23:52:25.568840 Set Vref, RX VrefLevel [Byte0]: 72
1127 23:52:25.571989 [Byte1]: 72
1128 23:52:25.576117
1129 23:52:25.576527 Set Vref, RX VrefLevel [Byte0]: 73
1130 23:52:25.579503 [Byte1]: 73
1131 23:52:25.583932
1132 23:52:25.584342 Set Vref, RX VrefLevel [Byte0]: 74
1133 23:52:25.586795 [Byte1]: 74
1134 23:52:25.591447
1135 23:52:25.591993 Set Vref, RX VrefLevel [Byte0]: 75
1136 23:52:25.594668 [Byte1]: 75
1137 23:52:25.598953
1138 23:52:25.599376 Set Vref, RX VrefLevel [Byte0]: 76
1139 23:52:25.602372 [Byte1]: 76
1140 23:52:25.606775
1141 23:52:25.607166 Set Vref, RX VrefLevel [Byte0]: 77
1142 23:52:25.610010 [Byte1]: 77
1143 23:52:25.614022
1144 23:52:25.614615 Set Vref, RX VrefLevel [Byte0]: 78
1145 23:52:25.617398 [Byte1]: 78
1146 23:52:25.621902
1147 23:52:25.622326 Set Vref, RX VrefLevel [Byte0]: 79
1148 23:52:25.625110 [Byte1]: 79
1149 23:52:25.629313
1150 23:52:25.629750 Final RX Vref Byte 0 = 55 to rank0
1151 23:52:25.633113 Final RX Vref Byte 1 = 62 to rank0
1152 23:52:25.636452 Final RX Vref Byte 0 = 55 to rank1
1153 23:52:25.639497 Final RX Vref Byte 1 = 62 to rank1==
1154 23:52:25.642641 Dram Type= 6, Freq= 0, CH_0, rank 0
1155 23:52:25.649522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 23:52:25.649965 ==
1157 23:52:25.650313 DQS Delay:
1158 23:52:25.650756 DQS0 = 0, DQS1 = 0
1159 23:52:25.652675 DQM Delay:
1160 23:52:25.653102 DQM0 = 82, DQM1 = 68
1161 23:52:25.655999 DQ Delay:
1162 23:52:25.659652 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1163 23:52:25.663109 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1164 23:52:25.663535 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1165 23:52:25.669670 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1166 23:52:25.670098
1167 23:52:25.670450
1168 23:52:25.676028 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1169 23:52:25.679608 CH0 RK0: MR19=606, MR18=2726
1170 23:52:25.686607 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1171 23:52:25.687123
1172 23:52:25.690171 ----->DramcWriteLeveling(PI) begin...
1173 23:52:25.690794 ==
1174 23:52:25.692874 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 23:52:25.696828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 23:52:25.697316 ==
1177 23:52:25.699778 Write leveling (Byte 0): 31 => 31
1178 23:52:25.702898 Write leveling (Byte 1): 29 => 29
1179 23:52:25.706013 DramcWriteLeveling(PI) end<-----
1180 23:52:25.706418
1181 23:52:25.706816 ==
1182 23:52:25.709813 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 23:52:25.713304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 23:52:25.713711 ==
1185 23:52:25.716423 [Gating] SW mode calibration
1186 23:52:25.722925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1187 23:52:25.729183 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1188 23:52:25.732726 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1189 23:52:25.736100 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 23:52:25.743246 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1191 23:52:25.746239 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:52:25.749580 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:52:25.756332 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:52:25.759607 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:52:25.762690 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:52:25.769944 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:52:25.773006 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:52:25.776472 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:52:25.779681 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:52:25.786230 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:52:25.830219 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:52:25.831086 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:52:25.831536 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:52:25.831952 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:52:25.832343 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1206 23:52:25.832866 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1207 23:52:25.833307 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:52:25.833701 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:52:25.834098 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 23:52:25.834496 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 23:52:25.871191 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:52:25.872149 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:52:25.872524 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:52:25.872896 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1215 23:52:25.873267 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1216 23:52:25.873578 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 23:52:25.873872 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 23:52:25.874170 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 23:52:25.874451 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 23:52:25.876212 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 23:52:25.880080 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)
1222 23:52:25.883058 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
1223 23:52:25.886161 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1224 23:52:25.889836 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:52:25.896169 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:52:25.899376 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:52:25.902668 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:52:25.909185 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:52:25.912890 0 11 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
1230 23:52:25.916362 0 11 8 | B1->B0 | 3737 3b3b | 0 0 | (0 0) (0 0)
1231 23:52:25.922820 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1232 23:52:25.926013 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 23:52:25.929508 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 23:52:25.936065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 23:52:25.939328 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 23:52:25.943161 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 23:52:25.946571 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 23:52:25.954062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1239 23:52:25.958084 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 23:52:25.961250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 23:52:25.964527 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 23:52:25.971611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 23:52:25.975124 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 23:52:25.978538 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 23:52:25.981633 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 23:52:25.988474 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 23:52:25.991510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 23:52:25.995373 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 23:52:26.001995 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 23:52:26.005186 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 23:52:26.008501 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 23:52:26.015260 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 23:52:26.018514 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1254 23:52:26.021646 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1255 23:52:26.025101 Total UI for P1: 0, mck2ui 16
1256 23:52:26.028521 best dqsien dly found for B0: ( 0, 14, 4)
1257 23:52:26.034996 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:52:26.035445 Total UI for P1: 0, mck2ui 16
1259 23:52:26.041413 best dqsien dly found for B1: ( 0, 14, 8)
1260 23:52:26.045132 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1261 23:52:26.048055 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1262 23:52:26.048467
1263 23:52:26.051940 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1264 23:52:26.055011 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1265 23:52:26.058053 [Gating] SW calibration Done
1266 23:52:26.058467 ==
1267 23:52:26.061722 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 23:52:26.064778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 23:52:26.065195 ==
1270 23:52:26.068077 RX Vref Scan: 0
1271 23:52:26.068487
1272 23:52:26.068912 RX Vref 0 -> 0, step: 1
1273 23:52:26.069232
1274 23:52:26.071413 RX Delay -130 -> 252, step: 16
1275 23:52:26.075398 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1276 23:52:26.081863 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1277 23:52:26.085002 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1278 23:52:26.087986 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1279 23:52:26.091578 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1280 23:52:26.095048 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1281 23:52:26.101236 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1282 23:52:26.104767 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1283 23:52:26.108020 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1284 23:52:26.111394 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1285 23:52:26.114553 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1286 23:52:26.121293 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1287 23:52:26.124947 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1288 23:52:26.128078 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1289 23:52:26.131363 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1290 23:52:26.135034 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1291 23:52:26.138409 ==
1292 23:52:26.139080 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 23:52:26.144598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 23:52:26.145204 ==
1295 23:52:26.145679 DQS Delay:
1296 23:52:26.148275 DQS0 = 0, DQS1 = 0
1297 23:52:26.148930 DQM Delay:
1298 23:52:26.151452 DQM0 = 75, DQM1 = 69
1299 23:52:26.151964 DQ Delay:
1300 23:52:26.154706 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1301 23:52:26.158122 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1302 23:52:26.161444 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1303 23:52:26.165078 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1304 23:52:26.165675
1305 23:52:26.166162
1306 23:52:26.166654 ==
1307 23:52:26.168149 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 23:52:26.171658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 23:52:26.172083 ==
1310 23:52:26.172616
1311 23:52:26.173103
1312 23:52:26.174971 TX Vref Scan disable
1313 23:52:26.178149 == TX Byte 0 ==
1314 23:52:26.181390 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1315 23:52:26.184683 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1316 23:52:26.187912 == TX Byte 1 ==
1317 23:52:26.191458 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1318 23:52:26.195210 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1319 23:52:26.195638 ==
1320 23:52:26.198282 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 23:52:26.201234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 23:52:26.201656 ==
1323 23:52:26.216079 TX Vref=22, minBit 1, minWin=27, winSum=438
1324 23:52:26.218979 TX Vref=24, minBit 1, minWin=27, winSum=441
1325 23:52:26.222500 TX Vref=26, minBit 1, minWin=27, winSum=440
1326 23:52:26.226003 TX Vref=28, minBit 1, minWin=27, winSum=447
1327 23:52:26.229108 TX Vref=30, minBit 1, minWin=27, winSum=445
1328 23:52:26.232206 TX Vref=32, minBit 9, minWin=27, winSum=444
1329 23:52:26.239529 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1330 23:52:26.239942
1331 23:52:26.242887 Final TX Range 1 Vref 28
1332 23:52:26.243300
1333 23:52:26.243624 ==
1334 23:52:26.246421 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 23:52:26.249389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 23:52:26.249801 ==
1337 23:52:26.250126
1338 23:52:26.250427
1339 23:52:26.252867 TX Vref Scan disable
1340 23:52:26.255833 == TX Byte 0 ==
1341 23:52:26.259158 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1342 23:52:26.262383 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1343 23:52:26.265453 == TX Byte 1 ==
1344 23:52:26.268611 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1345 23:52:26.275288 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1346 23:52:26.275466
1347 23:52:26.275585 [DATLAT]
1348 23:52:26.275695 Freq=800, CH0 RK1
1349 23:52:26.275801
1350 23:52:26.278712 DATLAT Default: 0xa
1351 23:52:26.278860 0, 0xFFFF, sum = 0
1352 23:52:26.281916 1, 0xFFFF, sum = 0
1353 23:52:26.282065 2, 0xFFFF, sum = 0
1354 23:52:26.285309 3, 0xFFFF, sum = 0
1355 23:52:26.288555 4, 0xFFFF, sum = 0
1356 23:52:26.288720 5, 0xFFFF, sum = 0
1357 23:52:26.292158 6, 0xFFFF, sum = 0
1358 23:52:26.292309 7, 0xFFFF, sum = 0
1359 23:52:26.295336 8, 0xFFFF, sum = 0
1360 23:52:26.295487 9, 0x0, sum = 1
1361 23:52:26.295607 10, 0x0, sum = 2
1362 23:52:26.298694 11, 0x0, sum = 3
1363 23:52:26.298844 12, 0x0, sum = 4
1364 23:52:26.301852 best_step = 10
1365 23:52:26.302020
1366 23:52:26.302152 ==
1367 23:52:26.305405 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 23:52:26.308614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 23:52:26.308812 ==
1370 23:52:26.312116 RX Vref Scan: 0
1371 23:52:26.312349
1372 23:52:26.312535 RX Vref 0 -> 0, step: 1
1373 23:52:26.312739
1374 23:52:26.315332 RX Delay -111 -> 252, step: 8
1375 23:52:26.322443 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1376 23:52:26.325669 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1377 23:52:26.328984 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1378 23:52:26.332807 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1379 23:52:26.335664 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1380 23:52:26.342446 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1381 23:52:26.346204 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1382 23:52:26.349427 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1383 23:52:26.352642 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1384 23:52:26.355901 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1385 23:52:26.363064 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1386 23:52:26.365958 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1387 23:52:26.369418 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1388 23:52:26.372646 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1389 23:52:26.376205 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1390 23:52:26.382366 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1391 23:52:26.382788 ==
1392 23:52:26.385988 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 23:52:26.389218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 23:52:26.389668 ==
1395 23:52:26.390026 DQS Delay:
1396 23:52:26.392520 DQS0 = 0, DQS1 = 0
1397 23:52:26.392974 DQM Delay:
1398 23:52:26.395744 DQM0 = 79, DQM1 = 69
1399 23:52:26.396163 DQ Delay:
1400 23:52:26.398992 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1401 23:52:26.402847 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1402 23:52:26.405962 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1403 23:52:26.409522 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1404 23:52:26.409933
1405 23:52:26.410276
1406 23:52:26.415955 [DQSOSCAuto] RK1, (LSB)MR18= 0x441f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1407 23:52:26.418995 CH0 RK1: MR19=606, MR18=441F
1408 23:52:26.425691 CH0_RK1: MR19=0x606, MR18=0x441F, DQSOSC=392, MR23=63, INC=96, DEC=64
1409 23:52:26.429383 [RxdqsGatingPostProcess] freq 800
1410 23:52:26.435653 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1411 23:52:26.439450 Pre-setting of DQS Precalculation
1412 23:52:26.442703 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1413 23:52:26.443128 ==
1414 23:52:26.445810 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 23:52:26.449021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 23:52:26.449456 ==
1417 23:52:26.455613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 23:52:26.462372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 23:52:26.471001 [CA 0] Center 36 (6~66) winsize 61
1420 23:52:26.474626 [CA 1] Center 36 (6~67) winsize 62
1421 23:52:26.477594 [CA 2] Center 34 (5~64) winsize 60
1422 23:52:26.480749 [CA 3] Center 34 (4~64) winsize 61
1423 23:52:26.484330 [CA 4] Center 34 (4~65) winsize 62
1424 23:52:26.487290 [CA 5] Center 34 (4~64) winsize 61
1425 23:52:26.487741
1426 23:52:26.490515 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1427 23:52:26.490975
1428 23:52:26.494190 [CATrainingPosCal] consider 1 rank data
1429 23:52:26.497474 u2DelayCellTimex100 = 270/100 ps
1430 23:52:26.500551 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1431 23:52:26.506998 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 23:52:26.511028 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1433 23:52:26.513878 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1434 23:52:26.517418 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 23:52:26.520393 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1436 23:52:26.520864
1437 23:52:26.524293 CA PerBit enable=1, Macro0, CA PI delay=34
1438 23:52:26.524820
1439 23:52:26.527044 [CBTSetCACLKResult] CA Dly = 34
1440 23:52:26.527473 CS Dly: 5 (0~36)
1441 23:52:26.530461 ==
1442 23:52:26.530898 Dram Type= 6, Freq= 0, CH_1, rank 1
1443 23:52:26.537377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 23:52:26.537805 ==
1445 23:52:26.540636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 23:52:26.547264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 23:52:26.556809 [CA 0] Center 37 (7~67) winsize 61
1448 23:52:26.560534 [CA 1] Center 36 (6~67) winsize 62
1449 23:52:26.563811 [CA 2] Center 35 (5~65) winsize 61
1450 23:52:26.566949 [CA 3] Center 34 (4~64) winsize 61
1451 23:52:26.570422 [CA 4] Center 34 (4~65) winsize 62
1452 23:52:26.573816 [CA 5] Center 33 (3~64) winsize 62
1453 23:52:26.574259
1454 23:52:26.577212 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1455 23:52:26.577659
1456 23:52:26.580340 [CATrainingPosCal] consider 2 rank data
1457 23:52:26.584058 u2DelayCellTimex100 = 270/100 ps
1458 23:52:26.587258 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1459 23:52:26.590466 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 23:52:26.596785 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1461 23:52:26.600264 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1462 23:52:26.604091 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 23:52:26.607788 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 23:52:26.608340
1465 23:52:26.611727 CA PerBit enable=1, Macro0, CA PI delay=34
1466 23:52:26.612148
1467 23:52:26.614877 [CBTSetCACLKResult] CA Dly = 34
1468 23:52:26.615322 CS Dly: 6 (0~38)
1469 23:52:26.615667
1470 23:52:26.618713 ----->DramcWriteLeveling(PI) begin...
1471 23:52:26.619175 ==
1472 23:52:26.622200 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 23:52:26.626467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 23:52:26.626951 ==
1475 23:52:26.629728 Write leveling (Byte 0): 26 => 26
1476 23:52:26.633384 Write leveling (Byte 1): 30 => 30
1477 23:52:26.637208 DramcWriteLeveling(PI) end<-----
1478 23:52:26.637629
1479 23:52:26.637960 ==
1480 23:52:26.640320 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 23:52:26.643597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 23:52:26.644123 ==
1483 23:52:26.647277 [Gating] SW mode calibration
1484 23:52:26.653562 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1485 23:52:26.657470 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1486 23:52:26.663738 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1487 23:52:26.667327 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1488 23:52:26.670019 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1489 23:52:26.677484 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:52:26.680088 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:52:26.684165 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:52:26.690589 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:52:26.693773 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:52:26.697007 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:52:26.703682 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:52:26.707386 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:52:26.710677 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:52:26.717017 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:52:26.720379 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1500 23:52:26.723503 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:52:26.726923 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:52:26.733772 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:52:26.737207 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1504 23:52:26.740395 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:52:26.747251 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:52:26.750370 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:52:26.753428 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:52:26.760355 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:52:26.763581 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:52:26.766962 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:52:26.773776 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:52:26.777048 0 9 8 | B1->B0 | 2b2b 2c2c | 1 0 | (1 1) (0 0)
1513 23:52:26.780200 0 9 12 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1514 23:52:26.787087 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 23:52:26.790272 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 23:52:26.793728 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 23:52:26.800342 0 9 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1518 23:52:26.803822 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 23:52:26.806981 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
1520 23:52:26.813990 0 10 8 | B1->B0 | 2e2e 2f2f | 0 1 | (1 0) (1 0)
1521 23:52:26.817236 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:52:26.820452 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:52:26.824068 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:52:26.830468 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:52:26.833640 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:52:26.837398 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:52:26.843748 0 11 4 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1528 23:52:26.847268 0 11 8 | B1->B0 | 3737 3737 | 0 0 | (1 1) (0 0)
1529 23:52:26.850549 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 23:52:26.857305 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 23:52:26.860466 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 23:52:26.863841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 23:52:26.870795 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 23:52:26.873795 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 23:52:26.877139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 23:52:26.883963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 23:52:26.887365 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1538 23:52:26.890547 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 23:52:26.894107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 23:52:26.900813 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 23:52:26.904349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 23:52:26.907539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 23:52:26.914321 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 23:52:26.917724 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 23:52:26.920479 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 23:52:26.927736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 23:52:26.930813 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 23:52:26.934104 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 23:52:26.940895 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 23:52:26.944415 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 23:52:26.947783 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1552 23:52:26.953746 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1553 23:52:26.954157 Total UI for P1: 0, mck2ui 16
1554 23:52:26.960769 best dqsien dly found for B0: ( 0, 14, 4)
1555 23:52:26.963840 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:52:26.967482 Total UI for P1: 0, mck2ui 16
1557 23:52:26.970802 best dqsien dly found for B1: ( 0, 14, 8)
1558 23:52:26.974056 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1559 23:52:26.977214 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1560 23:52:26.977627
1561 23:52:26.980775 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1562 23:52:26.984246 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1563 23:52:26.987413 [Gating] SW calibration Done
1564 23:52:26.987864 ==
1565 23:52:26.991237 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 23:52:26.993762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 23:52:26.994221 ==
1568 23:52:26.997390 RX Vref Scan: 0
1569 23:52:26.997842
1570 23:52:27.000651 RX Vref 0 -> 0, step: 1
1571 23:52:27.001105
1572 23:52:27.001464 RX Delay -130 -> 252, step: 16
1573 23:52:27.007321 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1574 23:52:27.010719 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1575 23:52:27.013677 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1576 23:52:27.017606 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1577 23:52:27.020366 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1578 23:52:27.027395 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1579 23:52:27.030973 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1580 23:52:27.033900 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1581 23:52:27.037090 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1582 23:52:27.040283 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1583 23:52:27.047256 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1584 23:52:27.050436 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1585 23:52:27.053664 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1586 23:52:27.056912 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1587 23:52:27.060584 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1588 23:52:27.067020 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1589 23:52:27.067527 ==
1590 23:52:27.070792 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 23:52:27.073799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 23:52:27.074252 ==
1593 23:52:27.074618 DQS Delay:
1594 23:52:27.076997 DQS0 = 0, DQS1 = 0
1595 23:52:27.077409 DQM Delay:
1596 23:52:27.080258 DQM0 = 81, DQM1 = 70
1597 23:52:27.080698 DQ Delay:
1598 23:52:27.083566 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1599 23:52:27.087134 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1600 23:52:27.090534 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1601 23:52:27.094004 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1602 23:52:27.094421
1603 23:52:27.094748
1604 23:52:27.095050 ==
1605 23:52:27.097340 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 23:52:27.100283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 23:52:27.100734 ==
1608 23:52:27.103652
1609 23:52:27.104061
1610 23:52:27.104386 TX Vref Scan disable
1611 23:52:27.107028 == TX Byte 0 ==
1612 23:52:27.110365 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1613 23:52:27.113985 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1614 23:52:27.116859 == TX Byte 1 ==
1615 23:52:27.120305 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1616 23:52:27.123915 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1617 23:52:27.124328 ==
1618 23:52:27.127557 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 23:52:27.133588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 23:52:27.134136 ==
1621 23:52:27.145783 TX Vref=22, minBit 11, minWin=26, winSum=441
1622 23:52:27.149136 TX Vref=24, minBit 5, minWin=27, winSum=446
1623 23:52:27.152918 TX Vref=26, minBit 5, minWin=27, winSum=449
1624 23:52:27.155814 TX Vref=28, minBit 5, minWin=27, winSum=448
1625 23:52:27.159156 TX Vref=30, minBit 1, minWin=27, winSum=451
1626 23:52:27.162582 TX Vref=32, minBit 5, minWin=27, winSum=452
1627 23:52:27.169063 [TxChooseVref] Worse bit 5, Min win 27, Win sum 452, Final Vref 32
1628 23:52:27.169478
1629 23:52:27.172617 Final TX Range 1 Vref 32
1630 23:52:27.173029
1631 23:52:27.173354 ==
1632 23:52:27.176103 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 23:52:27.179215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 23:52:27.179629 ==
1635 23:52:27.180017
1636 23:52:27.183130
1637 23:52:27.183540 TX Vref Scan disable
1638 23:52:27.186720 == TX Byte 0 ==
1639 23:52:27.190098 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1640 23:52:27.193811 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1641 23:52:27.196958 == TX Byte 1 ==
1642 23:52:27.200604 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1643 23:52:27.203746 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1644 23:52:27.204158
1645 23:52:27.204483 [DATLAT]
1646 23:52:27.207137 Freq=800, CH1 RK0
1647 23:52:27.207548
1648 23:52:27.210230 DATLAT Default: 0xa
1649 23:52:27.210726 0, 0xFFFF, sum = 0
1650 23:52:27.213727 1, 0xFFFF, sum = 0
1651 23:52:27.214144 2, 0xFFFF, sum = 0
1652 23:52:27.217082 3, 0xFFFF, sum = 0
1653 23:52:27.217500 4, 0xFFFF, sum = 0
1654 23:52:27.220214 5, 0xFFFF, sum = 0
1655 23:52:27.220671 6, 0xFFFF, sum = 0
1656 23:52:27.223587 7, 0xFFFF, sum = 0
1657 23:52:27.224033 8, 0xFFFF, sum = 0
1658 23:52:27.226688 9, 0x0, sum = 1
1659 23:52:27.227106 10, 0x0, sum = 2
1660 23:52:27.230030 11, 0x0, sum = 3
1661 23:52:27.230445 12, 0x0, sum = 4
1662 23:52:27.230787 best_step = 10
1663 23:52:27.233266
1664 23:52:27.233694 ==
1665 23:52:27.237161 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 23:52:27.240288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 23:52:27.240764 ==
1668 23:52:27.241115 RX Vref Scan: 1
1669 23:52:27.241427
1670 23:52:27.243524 Set Vref Range= 32 -> 127
1671 23:52:27.244018
1672 23:52:27.247104 RX Vref 32 -> 127, step: 1
1673 23:52:27.247531
1674 23:52:27.250129 RX Delay -111 -> 252, step: 8
1675 23:52:27.250630
1676 23:52:27.253908 Set Vref, RX VrefLevel [Byte0]: 32
1677 23:52:27.257129 [Byte1]: 32
1678 23:52:27.257558
1679 23:52:27.260020 Set Vref, RX VrefLevel [Byte0]: 33
1680 23:52:27.263833 [Byte1]: 33
1681 23:52:27.264245
1682 23:52:27.266561 Set Vref, RX VrefLevel [Byte0]: 34
1683 23:52:27.269988 [Byte1]: 34
1684 23:52:27.273908
1685 23:52:27.274440 Set Vref, RX VrefLevel [Byte0]: 35
1686 23:52:27.277003 [Byte1]: 35
1687 23:52:27.281514
1688 23:52:27.281940 Set Vref, RX VrefLevel [Byte0]: 36
1689 23:52:27.285161 [Byte1]: 36
1690 23:52:27.289422
1691 23:52:27.290033 Set Vref, RX VrefLevel [Byte0]: 37
1692 23:52:27.292876 [Byte1]: 37
1693 23:52:27.296680
1694 23:52:27.297166 Set Vref, RX VrefLevel [Byte0]: 38
1695 23:52:27.300452 [Byte1]: 38
1696 23:52:27.304447
1697 23:52:27.304923 Set Vref, RX VrefLevel [Byte0]: 39
1698 23:52:27.307913 [Byte1]: 39
1699 23:52:27.312673
1700 23:52:27.313093 Set Vref, RX VrefLevel [Byte0]: 40
1701 23:52:27.315683 [Byte1]: 40
1702 23:52:27.319926
1703 23:52:27.320353 Set Vref, RX VrefLevel [Byte0]: 41
1704 23:52:27.323215 [Byte1]: 41
1705 23:52:27.327617
1706 23:52:27.328044 Set Vref, RX VrefLevel [Byte0]: 42
1707 23:52:27.330846 [Byte1]: 42
1708 23:52:27.334780
1709 23:52:27.335204 Set Vref, RX VrefLevel [Byte0]: 43
1710 23:52:27.338140 [Byte1]: 43
1711 23:52:27.342836
1712 23:52:27.343259 Set Vref, RX VrefLevel [Byte0]: 44
1713 23:52:27.346338 [Byte1]: 44
1714 23:52:27.350445
1715 23:52:27.350872 Set Vref, RX VrefLevel [Byte0]: 45
1716 23:52:27.353821 [Byte1]: 45
1717 23:52:27.357893
1718 23:52:27.358330 Set Vref, RX VrefLevel [Byte0]: 46
1719 23:52:27.361278 [Byte1]: 46
1720 23:52:27.365566
1721 23:52:27.366111 Set Vref, RX VrefLevel [Byte0]: 47
1722 23:52:27.369649 [Byte1]: 47
1723 23:52:27.373872
1724 23:52:27.374419 Set Vref, RX VrefLevel [Byte0]: 48
1725 23:52:27.377024 [Byte1]: 48
1726 23:52:27.380816
1727 23:52:27.381253 Set Vref, RX VrefLevel [Byte0]: 49
1728 23:52:27.384496 [Byte1]: 49
1729 23:52:27.388457
1730 23:52:27.388921 Set Vref, RX VrefLevel [Byte0]: 50
1731 23:52:27.391818 [Byte1]: 50
1732 23:52:27.396083
1733 23:52:27.396593 Set Vref, RX VrefLevel [Byte0]: 51
1734 23:52:27.399819 [Byte1]: 51
1735 23:52:27.403823
1736 23:52:27.404242 Set Vref, RX VrefLevel [Byte0]: 52
1737 23:52:27.407116 [Byte1]: 52
1738 23:52:27.411534
1739 23:52:27.412071 Set Vref, RX VrefLevel [Byte0]: 53
1740 23:52:27.414775 [Byte1]: 53
1741 23:52:27.419536
1742 23:52:27.420037 Set Vref, RX VrefLevel [Byte0]: 54
1743 23:52:27.422396 [Byte1]: 54
1744 23:52:27.426874
1745 23:52:27.427285 Set Vref, RX VrefLevel [Byte0]: 55
1746 23:52:27.430469 [Byte1]: 55
1747 23:52:27.434603
1748 23:52:27.435161 Set Vref, RX VrefLevel [Byte0]: 56
1749 23:52:27.437581 [Byte1]: 56
1750 23:52:27.442069
1751 23:52:27.442502 Set Vref, RX VrefLevel [Byte0]: 57
1752 23:52:27.445844 [Byte1]: 57
1753 23:52:27.449611
1754 23:52:27.450175 Set Vref, RX VrefLevel [Byte0]: 58
1755 23:52:27.453160 [Byte1]: 58
1756 23:52:27.457447
1757 23:52:27.457868 Set Vref, RX VrefLevel [Byte0]: 59
1758 23:52:27.460766 [Byte1]: 59
1759 23:52:27.464961
1760 23:52:27.465383 Set Vref, RX VrefLevel [Byte0]: 60
1761 23:52:27.468275 [Byte1]: 60
1762 23:52:27.472813
1763 23:52:27.473397 Set Vref, RX VrefLevel [Byte0]: 61
1764 23:52:27.476008 [Byte1]: 61
1765 23:52:27.480287
1766 23:52:27.480829 Set Vref, RX VrefLevel [Byte0]: 62
1767 23:52:27.484017 [Byte1]: 62
1768 23:52:27.488157
1769 23:52:27.491364 Set Vref, RX VrefLevel [Byte0]: 63
1770 23:52:27.491787 [Byte1]: 63
1771 23:52:27.495879
1772 23:52:27.496458 Set Vref, RX VrefLevel [Byte0]: 64
1773 23:52:27.498956 [Byte1]: 64
1774 23:52:27.503357
1775 23:52:27.503786 Set Vref, RX VrefLevel [Byte0]: 65
1776 23:52:27.506979 [Byte1]: 65
1777 23:52:27.511138
1778 23:52:27.511557 Set Vref, RX VrefLevel [Byte0]: 66
1779 23:52:27.514575 [Byte1]: 66
1780 23:52:27.518628
1781 23:52:27.519049 Set Vref, RX VrefLevel [Byte0]: 67
1782 23:52:27.521887 [Byte1]: 67
1783 23:52:27.526293
1784 23:52:27.526848 Set Vref, RX VrefLevel [Byte0]: 68
1785 23:52:27.529793 [Byte1]: 68
1786 23:52:27.534002
1787 23:52:27.534563 Set Vref, RX VrefLevel [Byte0]: 69
1788 23:52:27.537273 [Byte1]: 69
1789 23:52:27.541814
1790 23:52:27.542338 Set Vref, RX VrefLevel [Byte0]: 70
1791 23:52:27.545039 [Byte1]: 70
1792 23:52:27.549239
1793 23:52:27.549739 Set Vref, RX VrefLevel [Byte0]: 71
1794 23:52:27.552534 [Byte1]: 71
1795 23:52:27.556918
1796 23:52:27.557437 Set Vref, RX VrefLevel [Byte0]: 72
1797 23:52:27.560372 [Byte1]: 72
1798 23:52:27.564758
1799 23:52:27.565187 Set Vref, RX VrefLevel [Byte0]: 73
1800 23:52:27.567794 [Byte1]: 73
1801 23:52:27.572348
1802 23:52:27.572904 Set Vref, RX VrefLevel [Byte0]: 74
1803 23:52:27.575169 [Byte1]: 74
1804 23:52:27.579983
1805 23:52:27.580417 Final RX Vref Byte 0 = 61 to rank0
1806 23:52:27.583073 Final RX Vref Byte 1 = 55 to rank0
1807 23:52:27.586613 Final RX Vref Byte 0 = 61 to rank1
1808 23:52:27.589624 Final RX Vref Byte 1 = 55 to rank1==
1809 23:52:27.593167 Dram Type= 6, Freq= 0, CH_1, rank 0
1810 23:52:27.599873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 23:52:27.600385 ==
1812 23:52:27.600842 DQS Delay:
1813 23:52:27.601165 DQS0 = 0, DQS1 = 0
1814 23:52:27.603016 DQM Delay:
1815 23:52:27.603506 DQM0 = 81, DQM1 = 72
1816 23:52:27.606278 DQ Delay:
1817 23:52:27.609626 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1818 23:52:27.613368 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1819 23:52:27.613748 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1820 23:52:27.619803 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1821 23:52:27.620167
1822 23:52:27.620471
1823 23:52:27.626438 [DQSOSCAuto] RK0, (LSB)MR18= 0x1620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1824 23:52:27.629945 CH1 RK0: MR19=606, MR18=1620
1825 23:52:27.636501 CH1_RK0: MR19=0x606, MR18=0x1620, DQSOSC=401, MR23=63, INC=91, DEC=61
1826 23:52:27.636920
1827 23:52:27.639573 ----->DramcWriteLeveling(PI) begin...
1828 23:52:27.640077 ==
1829 23:52:27.642720 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 23:52:27.645974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 23:52:27.646338 ==
1832 23:52:27.649471 Write leveling (Byte 0): 27 => 27
1833 23:52:27.652622 Write leveling (Byte 1): 28 => 28
1834 23:52:27.655734 DramcWriteLeveling(PI) end<-----
1835 23:52:27.656095
1836 23:52:27.656412 ==
1837 23:52:27.659196 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 23:52:27.662401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 23:52:27.662779 ==
1840 23:52:27.665756 [Gating] SW mode calibration
1841 23:52:27.672297 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1842 23:52:27.679485 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1843 23:52:27.682521 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1844 23:52:27.689028 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1845 23:52:27.692225 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:52:27.695838 0 6 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1847 23:52:27.702585 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:52:27.705482 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:52:27.709099 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:52:27.712394 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:52:27.719207 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:52:27.722505 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:52:27.726003 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:52:27.732038 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:52:27.735499 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:52:27.739215 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:52:27.745883 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:52:27.749237 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:52:27.752383 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:52:27.758829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1861 23:52:27.762321 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:52:27.765886 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:52:27.772298 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:52:27.775610 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:52:27.779041 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:52:27.785781 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:52:27.789208 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:52:27.792238 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
1869 23:52:27.795709 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1870 23:52:27.802739 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 23:52:27.805491 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 23:52:27.808998 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 23:52:27.815858 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 23:52:27.819102 0 9 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1875 23:52:27.822326 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 23:52:27.829232 0 10 4 | B1->B0 | 3030 2f2f | 1 0 | (1 1) (0 0)
1877 23:52:27.832490 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
1878 23:52:27.835743 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:52:27.842263 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:52:27.845646 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:52:27.849220 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:52:27.856084 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:52:27.858968 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:52:27.862739 0 11 4 | B1->B0 | 2424 3737 | 0 0 | (1 1) (0 0)
1885 23:52:27.869401 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1886 23:52:27.872324 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 23:52:27.875707 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 23:52:27.882464 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 23:52:27.885674 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 23:52:27.888970 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 23:52:27.892144 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 23:52:27.898758 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1893 23:52:27.902126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 23:52:27.905149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 23:52:27.912116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 23:52:27.915800 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 23:52:27.918899 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 23:52:27.925544 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 23:52:27.928695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 23:52:27.932305 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 23:52:27.938807 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 23:52:27.942145 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 23:52:27.945292 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 23:52:27.951992 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 23:52:27.955236 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 23:52:27.958605 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 23:52:27.965436 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 23:52:27.968619 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1909 23:52:27.972064 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 23:52:27.975622 Total UI for P1: 0, mck2ui 16
1911 23:52:27.978570 best dqsien dly found for B0: ( 0, 14, 4)
1912 23:52:27.982045 Total UI for P1: 0, mck2ui 16
1913 23:52:27.985293 best dqsien dly found for B1: ( 0, 14, 4)
1914 23:52:27.988292 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1915 23:52:27.991613 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1916 23:52:27.991693
1917 23:52:27.995175 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1918 23:52:28.002332 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1919 23:52:28.002415 [Gating] SW calibration Done
1920 23:52:28.002479 ==
1921 23:52:28.005592 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 23:52:28.012129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 23:52:28.012211 ==
1924 23:52:28.012276 RX Vref Scan: 0
1925 23:52:28.012358
1926 23:52:28.015200 RX Vref 0 -> 0, step: 1
1927 23:52:28.015281
1928 23:52:28.018958 RX Delay -130 -> 252, step: 16
1929 23:52:28.021956 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1930 23:52:28.025160 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1931 23:52:28.028924 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1932 23:52:28.032114 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1933 23:52:28.039015 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1934 23:52:28.042364 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1935 23:52:28.045826 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1936 23:52:28.049342 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1937 23:52:28.052499 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1938 23:52:28.059216 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1939 23:52:28.062303 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1940 23:52:28.065793 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1941 23:52:28.069069 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1942 23:52:28.072151 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1943 23:52:28.078747 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1944 23:52:28.082584 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1945 23:52:28.082665 ==
1946 23:52:28.085618 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 23:52:28.089095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 23:52:28.089176 ==
1949 23:52:28.092158 DQS Delay:
1950 23:52:28.092238 DQS0 = 0, DQS1 = 0
1951 23:52:28.092301 DQM Delay:
1952 23:52:28.095505 DQM0 = 77, DQM1 = 71
1953 23:52:28.095585 DQ Delay:
1954 23:52:28.098877 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1955 23:52:28.102108 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1956 23:52:28.105541 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1957 23:52:28.109497 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1958 23:52:28.109577
1959 23:52:28.109640
1960 23:52:28.109699 ==
1961 23:52:28.112280 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 23:52:28.115580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 23:52:28.119176 ==
1964 23:52:28.119259
1965 23:52:28.119321
1966 23:52:28.119380 TX Vref Scan disable
1967 23:52:28.122710 == TX Byte 0 ==
1968 23:52:28.125885 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1969 23:52:28.129490 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1970 23:52:28.132597 == TX Byte 1 ==
1971 23:52:28.135478 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1972 23:52:28.138840 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1973 23:52:28.141968 ==
1974 23:52:28.145365 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 23:52:28.149014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 23:52:28.149095 ==
1977 23:52:28.161915 TX Vref=22, minBit 6, minWin=27, winSum=450
1978 23:52:28.164932 TX Vref=24, minBit 1, minWin=28, winSum=452
1979 23:52:28.167832 TX Vref=26, minBit 0, minWin=28, winSum=456
1980 23:52:28.171035 TX Vref=28, minBit 1, minWin=28, winSum=460
1981 23:52:28.174723 TX Vref=30, minBit 1, minWin=28, winSum=463
1982 23:52:28.177787 TX Vref=32, minBit 5, minWin=27, winSum=458
1983 23:52:28.184472 [TxChooseVref] Worse bit 1, Min win 28, Win sum 463, Final Vref 30
1984 23:52:28.184582
1985 23:52:28.188252 Final TX Range 1 Vref 30
1986 23:52:28.188332
1987 23:52:28.188395 ==
1988 23:52:28.191778 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 23:52:28.194650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 23:52:28.194730 ==
1991 23:52:28.194793
1992 23:52:28.194852
1993 23:52:28.198454 TX Vref Scan disable
1994 23:52:28.201713 == TX Byte 0 ==
1995 23:52:28.204465 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1996 23:52:28.208253 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1997 23:52:28.211161 == TX Byte 1 ==
1998 23:52:28.214934 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1999 23:52:28.218163 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2000 23:52:28.218243
2001 23:52:28.221714 [DATLAT]
2002 23:52:28.221793 Freq=800, CH1 RK1
2003 23:52:28.221857
2004 23:52:28.224532 DATLAT Default: 0xa
2005 23:52:28.224624 0, 0xFFFF, sum = 0
2006 23:52:28.227908 1, 0xFFFF, sum = 0
2007 23:52:28.227989 2, 0xFFFF, sum = 0
2008 23:52:28.231793 3, 0xFFFF, sum = 0
2009 23:52:28.231873 4, 0xFFFF, sum = 0
2010 23:52:28.234921 5, 0xFFFF, sum = 0
2011 23:52:28.235002 6, 0xFFFF, sum = 0
2012 23:52:28.238072 7, 0xFFFF, sum = 0
2013 23:52:28.238153 8, 0xFFFF, sum = 0
2014 23:52:28.241239 9, 0x0, sum = 1
2015 23:52:28.241320 10, 0x0, sum = 2
2016 23:52:28.244795 11, 0x0, sum = 3
2017 23:52:28.244876 12, 0x0, sum = 4
2018 23:52:28.248235 best_step = 10
2019 23:52:28.248315
2020 23:52:28.248378 ==
2021 23:52:28.251354 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 23:52:28.255135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 23:52:28.255216 ==
2024 23:52:28.258250 RX Vref Scan: 0
2025 23:52:28.258330
2026 23:52:28.258393 RX Vref 0 -> 0, step: 1
2027 23:52:28.258452
2028 23:52:28.261427 RX Delay -111 -> 252, step: 8
2029 23:52:28.267957 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2030 23:52:28.271800 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2031 23:52:28.275049 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2032 23:52:28.278296 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2033 23:52:28.281558 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
2034 23:52:28.287956 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2035 23:52:28.291424 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2036 23:52:28.295050 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2037 23:52:28.298092 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2038 23:52:28.301704 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2039 23:52:28.308364 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2040 23:52:28.311555 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2041 23:52:28.314999 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2042 23:52:28.318174 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2043 23:52:28.321938 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2044 23:52:28.328138 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2045 23:52:28.328218 ==
2046 23:52:28.331273 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 23:52:28.334657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 23:52:28.334737 ==
2049 23:52:28.334801 DQS Delay:
2050 23:52:28.338472 DQS0 = 0, DQS1 = 0
2051 23:52:28.338551 DQM Delay:
2052 23:52:28.341628 DQM0 = 77, DQM1 = 75
2053 23:52:28.341708 DQ Delay:
2054 23:52:28.345299 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2055 23:52:28.348408 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2056 23:52:28.351388 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2057 23:52:28.355175 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
2058 23:52:28.355255
2059 23:52:28.355319
2060 23:52:28.361590 [DQSOSCAuto] RK1, (LSB)MR18= 0x243c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2061 23:52:28.364894 CH1 RK1: MR19=606, MR18=243C
2062 23:52:28.371340 CH1_RK1: MR19=0x606, MR18=0x243C, DQSOSC=394, MR23=63, INC=95, DEC=63
2063 23:52:28.375153 [RxdqsGatingPostProcess] freq 800
2064 23:52:28.381896 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2065 23:52:28.381978 Pre-setting of DQS Precalculation
2066 23:52:28.388094 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2067 23:52:28.394847 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2068 23:52:28.401523 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2069 23:52:28.401603
2070 23:52:28.401667
2071 23:52:28.404940 [Calibration Summary] 1600 Mbps
2072 23:52:28.408273 CH 0, Rank 0
2073 23:52:28.408353 SW Impedance : PASS
2074 23:52:28.411286 DUTY Scan : NO K
2075 23:52:28.415027 ZQ Calibration : PASS
2076 23:52:28.415107 Jitter Meter : NO K
2077 23:52:28.417946 CBT Training : PASS
2078 23:52:28.421177 Write leveling : PASS
2079 23:52:28.421257 RX DQS gating : PASS
2080 23:52:28.424761 RX DQ/DQS(RDDQC) : PASS
2081 23:52:28.424841 TX DQ/DQS : PASS
2082 23:52:28.428082 RX DATLAT : PASS
2083 23:52:28.431670 RX DQ/DQS(Engine): PASS
2084 23:52:28.431750 TX OE : NO K
2085 23:52:28.434654 All Pass.
2086 23:52:28.434733
2087 23:52:28.434796 CH 0, Rank 1
2088 23:52:28.438116 SW Impedance : PASS
2089 23:52:28.438199 DUTY Scan : NO K
2090 23:52:28.441608 ZQ Calibration : PASS
2091 23:52:28.444738 Jitter Meter : NO K
2092 23:52:28.444818 CBT Training : PASS
2093 23:52:28.447945 Write leveling : PASS
2094 23:52:28.451500 RX DQS gating : PASS
2095 23:52:28.451580 RX DQ/DQS(RDDQC) : PASS
2096 23:52:28.455145 TX DQ/DQS : PASS
2097 23:52:28.458188 RX DATLAT : PASS
2098 23:52:28.458289 RX DQ/DQS(Engine): PASS
2099 23:52:28.461415 TX OE : NO K
2100 23:52:28.461512 All Pass.
2101 23:52:28.461610
2102 23:52:28.464515 CH 1, Rank 0
2103 23:52:28.464652 SW Impedance : PASS
2104 23:52:28.467954 DUTY Scan : NO K
2105 23:52:28.468042 ZQ Calibration : PASS
2106 23:52:28.471422 Jitter Meter : NO K
2107 23:52:28.474358 CBT Training : PASS
2108 23:52:28.474439 Write leveling : PASS
2109 23:52:28.477805 RX DQS gating : PASS
2110 23:52:28.481428 RX DQ/DQS(RDDQC) : PASS
2111 23:52:28.481507 TX DQ/DQS : PASS
2112 23:52:28.484458 RX DATLAT : PASS
2113 23:52:28.487601 RX DQ/DQS(Engine): PASS
2114 23:52:28.487699 TX OE : NO K
2115 23:52:28.490896 All Pass.
2116 23:52:28.490969
2117 23:52:28.491049 CH 1, Rank 1
2118 23:52:28.494656 SW Impedance : PASS
2119 23:52:28.494729 DUTY Scan : NO K
2120 23:52:28.497969 ZQ Calibration : PASS
2121 23:52:28.501587 Jitter Meter : NO K
2122 23:52:28.501675 CBT Training : PASS
2123 23:52:28.504363 Write leveling : PASS
2124 23:52:28.507465 RX DQS gating : PASS
2125 23:52:28.507546 RX DQ/DQS(RDDQC) : PASS
2126 23:52:28.510724 TX DQ/DQS : PASS
2127 23:52:28.514653 RX DATLAT : PASS
2128 23:52:28.514732 RX DQ/DQS(Engine): PASS
2129 23:52:28.517436 TX OE : NO K
2130 23:52:28.517515 All Pass.
2131 23:52:28.517579
2132 23:52:28.521120 DramC Write-DBI off
2133 23:52:28.524204 PER_BANK_REFRESH: Hybrid Mode
2134 23:52:28.524284 TX_TRACKING: ON
2135 23:52:28.527602 [GetDramInforAfterCalByMRR] Vendor 6.
2136 23:52:28.530675 [GetDramInforAfterCalByMRR] Revision 606.
2137 23:52:28.534513 [GetDramInforAfterCalByMRR] Revision 2 0.
2138 23:52:28.537652 MR0 0x3b3b
2139 23:52:28.537732 MR8 0x5151
2140 23:52:28.540524 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 23:52:28.540652
2142 23:52:28.540716 MR0 0x3b3b
2143 23:52:28.543766 MR8 0x5151
2144 23:52:28.547106 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 23:52:28.547186
2146 23:52:28.557291 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2147 23:52:28.560291 [FAST_K] Save calibration result to emmc
2148 23:52:28.563999 [FAST_K] Save calibration result to emmc
2149 23:52:28.564080 dram_init: config_dvfs: 1
2150 23:52:28.570550 dramc_set_vcore_voltage set vcore to 662500
2151 23:52:28.570630 Read voltage for 1200, 2
2152 23:52:28.573959 Vio18 = 0
2153 23:52:28.574039 Vcore = 662500
2154 23:52:28.574102 Vdram = 0
2155 23:52:28.574163 Vddq = 0
2156 23:52:28.577570 Vmddr = 0
2157 23:52:28.580497 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2158 23:52:28.587274 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2159 23:52:28.590560 MEM_TYPE=3, freq_sel=15
2160 23:52:28.590662 sv_algorithm_assistance_LP4_1600
2161 23:52:28.597116 ============ PULL DRAM RESETB DOWN ============
2162 23:52:28.600409 ========== PULL DRAM RESETB DOWN end =========
2163 23:52:28.604394 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 23:52:28.607626 ===================================
2165 23:52:28.610497 LPDDR4 DRAM CONFIGURATION
2166 23:52:28.614078 ===================================
2167 23:52:28.617283 EX_ROW_EN[0] = 0x0
2168 23:52:28.617358 EX_ROW_EN[1] = 0x0
2169 23:52:28.621117 LP4Y_EN = 0x0
2170 23:52:28.621189 WORK_FSP = 0x0
2171 23:52:28.623969 WL = 0x4
2172 23:52:28.624077 RL = 0x4
2173 23:52:28.627401 BL = 0x2
2174 23:52:28.627501 RPST = 0x0
2175 23:52:28.630675 RD_PRE = 0x0
2176 23:52:28.630770 WR_PRE = 0x1
2177 23:52:28.633958 WR_PST = 0x0
2178 23:52:28.634042 DBI_WR = 0x0
2179 23:52:28.637497 DBI_RD = 0x0
2180 23:52:28.637579 OTF = 0x1
2181 23:52:28.640464 ===================================
2182 23:52:28.644110 ===================================
2183 23:52:28.647335 ANA top config
2184 23:52:28.650367 ===================================
2185 23:52:28.654110 DLL_ASYNC_EN = 0
2186 23:52:28.654193 ALL_SLAVE_EN = 0
2187 23:52:28.657373 NEW_RANK_MODE = 1
2188 23:52:28.660719 DLL_IDLE_MODE = 1
2189 23:52:28.664095 LP45_APHY_COMB_EN = 1
2190 23:52:28.664181 TX_ODT_DIS = 1
2191 23:52:28.667608 NEW_8X_MODE = 1
2192 23:52:28.670701 ===================================
2193 23:52:28.674144 ===================================
2194 23:52:28.677223 data_rate = 2400
2195 23:52:28.680514 CKR = 1
2196 23:52:28.684377 DQ_P2S_RATIO = 8
2197 23:52:28.687057 ===================================
2198 23:52:28.690859 CA_P2S_RATIO = 8
2199 23:52:28.690959 DQ_CA_OPEN = 0
2200 23:52:28.694107 DQ_SEMI_OPEN = 0
2201 23:52:28.697150 CA_SEMI_OPEN = 0
2202 23:52:28.700418 CA_FULL_RATE = 0
2203 23:52:28.703814 DQ_CKDIV4_EN = 0
2204 23:52:28.703909 CA_CKDIV4_EN = 0
2205 23:52:28.707014 CA_PREDIV_EN = 0
2206 23:52:28.710793 PH8_DLY = 17
2207 23:52:28.714197 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 23:52:28.717249 DQ_AAMCK_DIV = 4
2209 23:52:28.720515 CA_AAMCK_DIV = 4
2210 23:52:28.720648 CA_ADMCK_DIV = 4
2211 23:52:28.723783 DQ_TRACK_CA_EN = 0
2212 23:52:28.727437 CA_PICK = 1200
2213 23:52:28.730385 CA_MCKIO = 1200
2214 23:52:28.733979 MCKIO_SEMI = 0
2215 23:52:28.737359 PLL_FREQ = 2366
2216 23:52:28.741180 DQ_UI_PI_RATIO = 32
2217 23:52:28.741254 CA_UI_PI_RATIO = 0
2218 23:52:28.744163 ===================================
2219 23:52:28.747540 ===================================
2220 23:52:28.750555 memory_type:LPDDR4
2221 23:52:28.753851 GP_NUM : 10
2222 23:52:28.753924 SRAM_EN : 1
2223 23:52:28.757191 MD32_EN : 0
2224 23:52:28.761166 ===================================
2225 23:52:28.763821 [ANA_INIT] >>>>>>>>>>>>>>
2226 23:52:28.767387 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 23:52:28.771286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 23:52:28.774570 ===================================
2229 23:52:28.774670 data_rate = 2400,PCW = 0X5b00
2230 23:52:28.777821 ===================================
2231 23:52:28.781327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 23:52:28.787742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 23:52:28.794636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 23:52:28.797728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 23:52:28.800841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 23:52:28.804199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 23:52:28.807301 [ANA_INIT] flow start
2238 23:52:28.807374 [ANA_INIT] PLL >>>>>>>>
2239 23:52:28.810963 [ANA_INIT] PLL <<<<<<<<
2240 23:52:28.814563 [ANA_INIT] MIDPI >>>>>>>>
2241 23:52:28.817523 [ANA_INIT] MIDPI <<<<<<<<
2242 23:52:28.817597 [ANA_INIT] DLL >>>>>>>>
2243 23:52:28.820862 [ANA_INIT] DLL <<<<<<<<
2244 23:52:28.820950 [ANA_INIT] flow end
2245 23:52:28.827736 ============ LP4 DIFF to SE enter ============
2246 23:52:28.831115 ============ LP4 DIFF to SE exit ============
2247 23:52:28.834589 [ANA_INIT] <<<<<<<<<<<<<
2248 23:52:28.837875 [Flow] Enable top DCM control >>>>>
2249 23:52:28.841523 [Flow] Enable top DCM control <<<<<
2250 23:52:28.842081 Enable DLL master slave shuffle
2251 23:52:28.847744 ==============================================================
2252 23:52:28.851354 Gating Mode config
2253 23:52:28.854398 ==============================================================
2254 23:52:28.858193 Config description:
2255 23:52:28.867931 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 23:52:28.874497 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 23:52:28.877688 SELPH_MODE 0: By rank 1: By Phase
2258 23:52:28.884627 ==============================================================
2259 23:52:28.887508 GAT_TRACK_EN = 1
2260 23:52:28.890734 RX_GATING_MODE = 2
2261 23:52:28.894440 RX_GATING_TRACK_MODE = 2
2262 23:52:28.897422 SELPH_MODE = 1
2263 23:52:28.900910 PICG_EARLY_EN = 1
2264 23:52:28.901345 VALID_LAT_VALUE = 1
2265 23:52:28.907790 ==============================================================
2266 23:52:28.911305 Enter into Gating configuration >>>>
2267 23:52:28.914255 Exit from Gating configuration <<<<
2268 23:52:28.917506 Enter into DVFS_PRE_config >>>>>
2269 23:52:28.927462 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 23:52:28.930977 Exit from DVFS_PRE_config <<<<<
2271 23:52:28.933811 Enter into PICG configuration >>>>
2272 23:52:28.937307 Exit from PICG configuration <<<<
2273 23:52:28.940244 [RX_INPUT] configuration >>>>>
2274 23:52:28.943814 [RX_INPUT] configuration <<<<<
2275 23:52:28.950643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 23:52:28.953697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 23:52:28.960483 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 23:52:28.967649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 23:52:28.974090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 23:52:28.980481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 23:52:28.983898 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 23:52:28.987400 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 23:52:28.990727 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 23:52:28.993793 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 23:52:29.000525 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2286 23:52:29.003802 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 23:52:29.007445 ===================================
2288 23:52:29.010445 LPDDR4 DRAM CONFIGURATION
2289 23:52:29.014198 ===================================
2290 23:52:29.014639 EX_ROW_EN[0] = 0x0
2291 23:52:29.017235 EX_ROW_EN[1] = 0x0
2292 23:52:29.017821 LP4Y_EN = 0x0
2293 23:52:29.020295 WORK_FSP = 0x0
2294 23:52:29.020770 WL = 0x4
2295 23:52:29.023726 RL = 0x4
2296 23:52:29.024161 BL = 0x2
2297 23:52:29.026975 RPST = 0x0
2298 23:52:29.027394 RD_PRE = 0x0
2299 23:52:29.030854 WR_PRE = 0x1
2300 23:52:29.031458 WR_PST = 0x0
2301 23:52:29.034405 DBI_WR = 0x0
2302 23:52:29.037375 DBI_RD = 0x0
2303 23:52:29.037840 OTF = 0x1
2304 23:52:29.040660 ===================================
2305 23:52:29.044209 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2306 23:52:29.046924 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2307 23:52:29.053905 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 23:52:29.056981 ===================================
2309 23:52:29.060419 LPDDR4 DRAM CONFIGURATION
2310 23:52:29.063719 ===================================
2311 23:52:29.064133 EX_ROW_EN[0] = 0x10
2312 23:52:29.067328 EX_ROW_EN[1] = 0x0
2313 23:52:29.067737 LP4Y_EN = 0x0
2314 23:52:29.070615 WORK_FSP = 0x0
2315 23:52:29.071022 WL = 0x4
2316 23:52:29.073622 RL = 0x4
2317 23:52:29.074030 BL = 0x2
2318 23:52:29.076864 RPST = 0x0
2319 23:52:29.077274 RD_PRE = 0x0
2320 23:52:29.080811 WR_PRE = 0x1
2321 23:52:29.081221 WR_PST = 0x0
2322 23:52:29.083874 DBI_WR = 0x0
2323 23:52:29.084284 DBI_RD = 0x0
2324 23:52:29.086812 OTF = 0x1
2325 23:52:29.090087 ===================================
2326 23:52:29.097382 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2327 23:52:29.097797 ==
2328 23:52:29.100659 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 23:52:29.103643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2330 23:52:29.104054 ==
2331 23:52:29.106812 [Duty_Offset_Calibration]
2332 23:52:29.107223 B0:2 B1:0 CA:3
2333 23:52:29.107545
2334 23:52:29.110468 [DutyScan_Calibration_Flow] k_type=0
2335 23:52:29.121154
2336 23:52:29.121573 ==CLK 0==
2337 23:52:29.124074 Final CLK duty delay cell = 0
2338 23:52:29.127119 [0] MAX Duty = 5062%(X100), DQS PI = 12
2339 23:52:29.130618 [0] MIN Duty = 4906%(X100), DQS PI = 54
2340 23:52:29.130700 [0] AVG Duty = 4984%(X100)
2341 23:52:29.134142
2342 23:52:29.137360 CH0 CLK Duty spec in!! Max-Min= 156%
2343 23:52:29.140553 [DutyScan_Calibration_Flow] ====Done====
2344 23:52:29.140672
2345 23:52:29.144111 [DutyScan_Calibration_Flow] k_type=1
2346 23:52:29.158922
2347 23:52:29.159013 ==DQS 0 ==
2348 23:52:29.162106 Final DQS duty delay cell = 0
2349 23:52:29.165996 [0] MAX Duty = 5062%(X100), DQS PI = 12
2350 23:52:29.169169 [0] MIN Duty = 4907%(X100), DQS PI = 2
2351 23:52:29.169278 [0] AVG Duty = 4984%(X100)
2352 23:52:29.172504
2353 23:52:29.172635 ==DQS 1 ==
2354 23:52:29.175631 Final DQS duty delay cell = -4
2355 23:52:29.179200 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2356 23:52:29.182796 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2357 23:52:29.185615 [-4] AVG Duty = 4937%(X100)
2358 23:52:29.185783
2359 23:52:29.188952 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2360 23:52:29.189121
2361 23:52:29.192499 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2362 23:52:29.195998 [DutyScan_Calibration_Flow] ====Done====
2363 23:52:29.196231
2364 23:52:29.199119 [DutyScan_Calibration_Flow] k_type=3
2365 23:52:29.217265
2366 23:52:29.217670 ==DQM 0 ==
2367 23:52:29.220550 Final DQM duty delay cell = 0
2368 23:52:29.223668 [0] MAX Duty = 5124%(X100), DQS PI = 28
2369 23:52:29.226765 [0] MIN Duty = 4907%(X100), DQS PI = 0
2370 23:52:29.227214 [0] AVG Duty = 5015%(X100)
2371 23:52:29.230227
2372 23:52:29.230650 ==DQM 1 ==
2373 23:52:29.233311 Final DQM duty delay cell = 4
2374 23:52:29.237105 [4] MAX Duty = 5124%(X100), DQS PI = 52
2375 23:52:29.240332 [4] MIN Duty = 5000%(X100), DQS PI = 14
2376 23:52:29.240779 [4] AVG Duty = 5062%(X100)
2377 23:52:29.243731
2378 23:52:29.247189 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2379 23:52:29.247598
2380 23:52:29.250450 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2381 23:52:29.253581 [DutyScan_Calibration_Flow] ====Done====
2382 23:52:29.254055
2383 23:52:29.256775 [DutyScan_Calibration_Flow] k_type=2
2384 23:52:29.271168
2385 23:52:29.271247 ==DQ 0 ==
2386 23:52:29.274481 Final DQ duty delay cell = -4
2387 23:52:29.277881 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2388 23:52:29.281548 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2389 23:52:29.284742 [-4] AVG Duty = 4969%(X100)
2390 23:52:29.284821
2391 23:52:29.284885 ==DQ 1 ==
2392 23:52:29.287976 Final DQ duty delay cell = -4
2393 23:52:29.291336 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2394 23:52:29.294491 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2395 23:52:29.298434 [-4] AVG Duty = 4938%(X100)
2396 23:52:29.298514
2397 23:52:29.301315 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2398 23:52:29.301395
2399 23:52:29.304722 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2400 23:52:29.307979 [DutyScan_Calibration_Flow] ====Done====
2401 23:52:29.308058 ==
2402 23:52:29.311088 Dram Type= 6, Freq= 0, CH_1, rank 0
2403 23:52:29.314517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2404 23:52:29.314598 ==
2405 23:52:29.318180 [Duty_Offset_Calibration]
2406 23:52:29.318343 B0:1 B1:-2 CA:1
2407 23:52:29.318436
2408 23:52:29.321276 [DutyScan_Calibration_Flow] k_type=0
2409 23:52:29.331936
2410 23:52:29.332045 ==CLK 0==
2411 23:52:29.335616 Final CLK duty delay cell = 0
2412 23:52:29.338826 [0] MAX Duty = 5031%(X100), DQS PI = 16
2413 23:52:29.342145 [0] MIN Duty = 4875%(X100), DQS PI = 2
2414 23:52:29.342278 [0] AVG Duty = 4953%(X100)
2415 23:52:29.345423
2416 23:52:29.349019 CH1 CLK Duty spec in!! Max-Min= 156%
2417 23:52:29.352192 [DutyScan_Calibration_Flow] ====Done====
2418 23:52:29.352361
2419 23:52:29.355359 [DutyScan_Calibration_Flow] k_type=1
2420 23:52:29.370541
2421 23:52:29.370918 ==DQS 0 ==
2422 23:52:29.374069 Final DQS duty delay cell = -4
2423 23:52:29.377945 [-4] MAX Duty = 4969%(X100), DQS PI = 8
2424 23:52:29.381253 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2425 23:52:29.384053 [-4] AVG Duty = 4922%(X100)
2426 23:52:29.384465
2427 23:52:29.384843 ==DQS 1 ==
2428 23:52:29.387661 Final DQS duty delay cell = 0
2429 23:52:29.390823 [0] MAX Duty = 5062%(X100), DQS PI = 0
2430 23:52:29.394242 [0] MIN Duty = 4844%(X100), DQS PI = 26
2431 23:52:29.397461 [0] AVG Duty = 4953%(X100)
2432 23:52:29.397875
2433 23:52:29.400968 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2434 23:52:29.401379
2435 23:52:29.404085 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2436 23:52:29.407849 [DutyScan_Calibration_Flow] ====Done====
2437 23:52:29.408259
2438 23:52:29.410511 [DutyScan_Calibration_Flow] k_type=3
2439 23:52:29.427305
2440 23:52:29.427792 ==DQM 0 ==
2441 23:52:29.431309 Final DQM duty delay cell = 0
2442 23:52:29.434631 [0] MAX Duty = 5000%(X100), DQS PI = 22
2443 23:52:29.437393 [0] MIN Duty = 4876%(X100), DQS PI = 4
2444 23:52:29.437824 [0] AVG Duty = 4938%(X100)
2445 23:52:29.440767
2446 23:52:29.441220 ==DQM 1 ==
2447 23:52:29.444437 Final DQM duty delay cell = 0
2448 23:52:29.447772 [0] MAX Duty = 5031%(X100), DQS PI = 36
2449 23:52:29.450611 [0] MIN Duty = 4907%(X100), DQS PI = 2
2450 23:52:29.451021 [0] AVG Duty = 4969%(X100)
2451 23:52:29.454333
2452 23:52:29.457755 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2453 23:52:29.458167
2454 23:52:29.461031 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2455 23:52:29.463985 [DutyScan_Calibration_Flow] ====Done====
2456 23:52:29.464397
2457 23:52:29.467343 [DutyScan_Calibration_Flow] k_type=2
2458 23:52:29.483645
2459 23:52:29.484101 ==DQ 0 ==
2460 23:52:29.487465 Final DQ duty delay cell = 0
2461 23:52:29.490203 [0] MAX Duty = 5093%(X100), DQS PI = 28
2462 23:52:29.494024 [0] MIN Duty = 4938%(X100), DQS PI = 56
2463 23:52:29.494438 [0] AVG Duty = 5015%(X100)
2464 23:52:29.497336
2465 23:52:29.497745 ==DQ 1 ==
2466 23:52:29.500665 Final DQ duty delay cell = 0
2467 23:52:29.503506 [0] MAX Duty = 5125%(X100), DQS PI = 36
2468 23:52:29.507250 [0] MIN Duty = 4969%(X100), DQS PI = 26
2469 23:52:29.507663 [0] AVG Duty = 5047%(X100)
2470 23:52:29.507990
2471 23:52:29.510264 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2472 23:52:29.513438
2473 23:52:29.517397 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2474 23:52:29.520336 [DutyScan_Calibration_Flow] ====Done====
2475 23:52:29.524220 nWR fixed to 30
2476 23:52:29.524668 [ModeRegInit_LP4] CH0 RK0
2477 23:52:29.526881 [ModeRegInit_LP4] CH0 RK1
2478 23:52:29.530244 [ModeRegInit_LP4] CH1 RK0
2479 23:52:29.533400 [ModeRegInit_LP4] CH1 RK1
2480 23:52:29.533828 match AC timing 7
2481 23:52:29.537177 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2482 23:52:29.543944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2483 23:52:29.546856 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2484 23:52:29.550134 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2485 23:52:29.557490 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2486 23:52:29.557901 ==
2487 23:52:29.560106 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 23:52:29.563583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 23:52:29.563999 ==
2490 23:52:29.570219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 23:52:29.573846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 23:52:29.583870 [CA 0] Center 40 (10~71) winsize 62
2493 23:52:29.587115 [CA 1] Center 40 (10~70) winsize 61
2494 23:52:29.590211 [CA 2] Center 36 (6~66) winsize 61
2495 23:52:29.593700 [CA 3] Center 35 (5~66) winsize 62
2496 23:52:29.597351 [CA 4] Center 34 (4~65) winsize 62
2497 23:52:29.600642 [CA 5] Center 33 (3~64) winsize 62
2498 23:52:29.601057
2499 23:52:29.603521 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 23:52:29.603935
2501 23:52:29.607099 [CATrainingPosCal] consider 1 rank data
2502 23:52:29.610364 u2DelayCellTimex100 = 270/100 ps
2503 23:52:29.613701 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2504 23:52:29.620254 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2505 23:52:29.623562 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2506 23:52:29.627521 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 23:52:29.630681 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2508 23:52:29.633654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2509 23:52:29.634066
2510 23:52:29.637245 CA PerBit enable=1, Macro0, CA PI delay=33
2511 23:52:29.637739
2512 23:52:29.640336 [CBTSetCACLKResult] CA Dly = 33
2513 23:52:29.640792 CS Dly: 7 (0~38)
2514 23:52:29.643852 ==
2515 23:52:29.647305 Dram Type= 6, Freq= 0, CH_0, rank 1
2516 23:52:29.650880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:52:29.651312 ==
2518 23:52:29.653638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 23:52:29.660312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2520 23:52:29.670464 [CA 0] Center 40 (10~71) winsize 62
2521 23:52:29.673602 [CA 1] Center 40 (10~70) winsize 61
2522 23:52:29.676415 [CA 2] Center 35 (5~66) winsize 62
2523 23:52:29.680207 [CA 3] Center 35 (5~66) winsize 62
2524 23:52:29.683343 [CA 4] Center 34 (4~65) winsize 62
2525 23:52:29.686440 [CA 5] Center 33 (3~63) winsize 61
2526 23:52:29.686938
2527 23:52:29.690488 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2528 23:52:29.690898
2529 23:52:29.693261 [CATrainingPosCal] consider 2 rank data
2530 23:52:29.696636 u2DelayCellTimex100 = 270/100 ps
2531 23:52:29.700388 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2532 23:52:29.706529 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2533 23:52:29.709822 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2534 23:52:29.713199 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 23:52:29.716479 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 23:52:29.720409 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2537 23:52:29.720898
2538 23:52:29.723338 CA PerBit enable=1, Macro0, CA PI delay=33
2539 23:52:29.723730
2540 23:52:29.726716 [CBTSetCACLKResult] CA Dly = 33
2541 23:52:29.727092 CS Dly: 7 (0~39)
2542 23:52:29.730012
2543 23:52:29.733641 ----->DramcWriteLeveling(PI) begin...
2544 23:52:29.734038 ==
2545 23:52:29.736847 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 23:52:29.740155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 23:52:29.740513 ==
2548 23:52:29.743276 Write leveling (Byte 0): 35 => 35
2549 23:52:29.747152 Write leveling (Byte 1): 29 => 29
2550 23:52:29.750180 DramcWriteLeveling(PI) end<-----
2551 23:52:29.750542
2552 23:52:29.750854 ==
2553 23:52:29.753409 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 23:52:29.756643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 23:52:29.757018 ==
2556 23:52:29.760059 [Gating] SW mode calibration
2557 23:52:29.766670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2558 23:52:29.773481 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2559 23:52:29.776970 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
2560 23:52:29.779952 0 15 4 | B1->B0 | 2b2b 3434 | 1 0 | (0 0) (0 0)
2561 23:52:29.783137 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 23:52:29.790278 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 23:52:29.793431 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 23:52:29.796729 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 23:52:29.803638 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 23:52:29.806880 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2567 23:52:29.810401 1 0 0 | B1->B0 | 3030 2525 | 0 0 | (0 0) (1 0)
2568 23:52:29.817098 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2569 23:52:29.820101 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 23:52:29.823305 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 23:52:29.830141 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 23:52:29.833580 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 23:52:29.836531 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 23:52:29.843607 1 0 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
2575 23:52:29.846723 1 1 0 | B1->B0 | 2626 3232 | 0 1 | (0 0) (0 0)
2576 23:52:29.849963 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2577 23:52:29.856612 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 23:52:29.860136 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 23:52:29.863664 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 23:52:29.870280 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 23:52:29.873533 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 23:52:29.876966 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 23:52:29.880224 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2584 23:52:29.887018 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2585 23:52:29.890101 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 23:52:29.893515 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 23:52:29.900009 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 23:52:29.903170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 23:52:29.906561 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 23:52:29.913397 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 23:52:29.916808 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 23:52:29.920242 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 23:52:29.926378 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 23:52:29.929657 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 23:52:29.933009 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 23:52:29.939805 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 23:52:29.942948 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 23:52:29.946309 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 23:52:29.952727 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2600 23:52:29.955965 Total UI for P1: 0, mck2ui 16
2601 23:52:29.959284 best dqsien dly found for B0: ( 1, 3, 28)
2602 23:52:29.962428 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2603 23:52:29.966236 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 23:52:29.969402 Total UI for P1: 0, mck2ui 16
2605 23:52:29.972765 best dqsien dly found for B1: ( 1, 4, 2)
2606 23:52:29.976008 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2607 23:52:29.979247 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2608 23:52:29.982390
2609 23:52:29.986094 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2610 23:52:29.989253 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2611 23:52:29.992550 [Gating] SW calibration Done
2612 23:52:29.993019 ==
2613 23:52:29.995615 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 23:52:29.999224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 23:52:29.999637 ==
2616 23:52:29.999962 RX Vref Scan: 0
2617 23:52:30.000271
2618 23:52:30.002451 RX Vref 0 -> 0, step: 1
2619 23:52:30.002864
2620 23:52:30.005690 RX Delay -40 -> 252, step: 8
2621 23:52:30.009400 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2622 23:52:30.012368 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2623 23:52:30.019642 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2624 23:52:30.022706 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2625 23:52:30.026059 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2626 23:52:30.028871 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2627 23:52:30.032589 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2628 23:52:30.039479 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2629 23:52:30.042039 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2630 23:52:30.045698 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2631 23:52:30.048974 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2632 23:52:30.052257 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2633 23:52:30.055651 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2634 23:52:30.062182 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2635 23:52:30.065646 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2636 23:52:30.068870 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2637 23:52:30.069287 ==
2638 23:52:30.072234 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 23:52:30.075539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 23:52:30.075954 ==
2641 23:52:30.078855 DQS Delay:
2642 23:52:30.079266 DQS0 = 0, DQS1 = 0
2643 23:52:30.082066 DQM Delay:
2644 23:52:30.082475 DQM0 = 112, DQM1 = 101
2645 23:52:30.085412 DQ Delay:
2646 23:52:30.088649 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2647 23:52:30.092478 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2648 23:52:30.095682 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2649 23:52:30.098851 DQ12 =103, DQ13 =107, DQ14 =111, DQ15 =111
2650 23:52:30.099291
2651 23:52:30.099791
2652 23:52:30.100115 ==
2653 23:52:30.102433 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 23:52:30.105960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 23:52:30.106390 ==
2656 23:52:30.106795
2657 23:52:30.107107
2658 23:52:30.108876 TX Vref Scan disable
2659 23:52:30.112001 == TX Byte 0 ==
2660 23:52:30.115709 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2661 23:52:30.119079 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2662 23:52:30.122647 == TX Byte 1 ==
2663 23:52:30.125653 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2664 23:52:30.128978 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2665 23:52:30.129393 ==
2666 23:52:30.132025 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 23:52:30.135377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 23:52:30.138716 ==
2669 23:52:30.149102 TX Vref=22, minBit 1, minWin=25, winSum=412
2670 23:52:30.152416 TX Vref=24, minBit 0, minWin=25, winSum=414
2671 23:52:30.156036 TX Vref=26, minBit 7, minWin=25, winSum=425
2672 23:52:30.159401 TX Vref=28, minBit 4, minWin=26, winSum=429
2673 23:52:30.162616 TX Vref=30, minBit 1, minWin=26, winSum=427
2674 23:52:30.165927 TX Vref=32, minBit 10, minWin=25, winSum=425
2675 23:52:30.172545 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 28
2676 23:52:30.172994
2677 23:52:30.176005 Final TX Range 1 Vref 28
2678 23:52:30.176418
2679 23:52:30.176779 ==
2680 23:52:30.179048 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 23:52:30.182547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 23:52:30.182953 ==
2683 23:52:30.183273
2684 23:52:30.185978
2685 23:52:30.186381 TX Vref Scan disable
2686 23:52:30.189591 == TX Byte 0 ==
2687 23:52:30.192488 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2688 23:52:30.196302 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2689 23:52:30.199435 == TX Byte 1 ==
2690 23:52:30.202628 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2691 23:52:30.205842 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2692 23:52:30.206247
2693 23:52:30.209293 [DATLAT]
2694 23:52:30.209694 Freq=1200, CH0 RK0
2695 23:52:30.210017
2696 23:52:30.212666 DATLAT Default: 0xd
2697 23:52:30.213071 0, 0xFFFF, sum = 0
2698 23:52:30.215831 1, 0xFFFF, sum = 0
2699 23:52:30.216238 2, 0xFFFF, sum = 0
2700 23:52:30.219060 3, 0xFFFF, sum = 0
2701 23:52:30.219468 4, 0xFFFF, sum = 0
2702 23:52:30.222963 5, 0xFFFF, sum = 0
2703 23:52:30.223376 6, 0xFFFF, sum = 0
2704 23:52:30.225929 7, 0xFFFF, sum = 0
2705 23:52:30.226336 8, 0xFFFF, sum = 0
2706 23:52:30.230039 9, 0xFFFF, sum = 0
2707 23:52:30.233428 10, 0xFFFF, sum = 0
2708 23:52:30.233855 11, 0xFFFF, sum = 0
2709 23:52:30.235960 12, 0x0, sum = 1
2710 23:52:30.236379 13, 0x0, sum = 2
2711 23:52:30.236760 14, 0x0, sum = 3
2712 23:52:30.239602 15, 0x0, sum = 4
2713 23:52:30.240063 best_step = 13
2714 23:52:30.240393
2715 23:52:30.240755 ==
2716 23:52:30.242968 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 23:52:30.249552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 23:52:30.249969 ==
2719 23:52:30.250299 RX Vref Scan: 1
2720 23:52:30.250605
2721 23:52:30.252837 Set Vref Range= 32 -> 127
2722 23:52:30.253260
2723 23:52:30.256689 RX Vref 32 -> 127, step: 1
2724 23:52:30.257100
2725 23:52:30.259441 RX Delay -37 -> 252, step: 4
2726 23:52:30.259850
2727 23:52:30.262669 Set Vref, RX VrefLevel [Byte0]: 32
2728 23:52:30.263080 [Byte1]: 32
2729 23:52:30.267536
2730 23:52:30.267945 Set Vref, RX VrefLevel [Byte0]: 33
2731 23:52:30.270974 [Byte1]: 33
2732 23:52:30.275838
2733 23:52:30.276263 Set Vref, RX VrefLevel [Byte0]: 34
2734 23:52:30.278914 [Byte1]: 34
2735 23:52:30.284052
2736 23:52:30.284536 Set Vref, RX VrefLevel [Byte0]: 35
2737 23:52:30.286810 [Byte1]: 35
2738 23:52:30.291472
2739 23:52:30.291880 Set Vref, RX VrefLevel [Byte0]: 36
2740 23:52:30.295021 [Byte1]: 36
2741 23:52:30.299643
2742 23:52:30.300052 Set Vref, RX VrefLevel [Byte0]: 37
2743 23:52:30.302765 [Byte1]: 37
2744 23:52:30.307772
2745 23:52:30.308216 Set Vref, RX VrefLevel [Byte0]: 38
2746 23:52:30.310996 [Byte1]: 38
2747 23:52:30.315433
2748 23:52:30.315833 Set Vref, RX VrefLevel [Byte0]: 39
2749 23:52:30.318969 [Byte1]: 39
2750 23:52:30.323910
2751 23:52:30.324320 Set Vref, RX VrefLevel [Byte0]: 40
2752 23:52:30.326783 [Byte1]: 40
2753 23:52:30.331621
2754 23:52:30.332051 Set Vref, RX VrefLevel [Byte0]: 41
2755 23:52:30.335090 [Byte1]: 41
2756 23:52:30.340200
2757 23:52:30.340639 Set Vref, RX VrefLevel [Byte0]: 42
2758 23:52:30.343236 [Byte1]: 42
2759 23:52:30.347841
2760 23:52:30.348250 Set Vref, RX VrefLevel [Byte0]: 43
2761 23:52:30.350827 [Byte1]: 43
2762 23:52:30.355869
2763 23:52:30.356278 Set Vref, RX VrefLevel [Byte0]: 44
2764 23:52:30.359244 [Byte1]: 44
2765 23:52:30.364014
2766 23:52:30.364443 Set Vref, RX VrefLevel [Byte0]: 45
2767 23:52:30.366859 [Byte1]: 45
2768 23:52:30.372063
2769 23:52:30.372474 Set Vref, RX VrefLevel [Byte0]: 46
2770 23:52:30.375028 [Byte1]: 46
2771 23:52:30.379970
2772 23:52:30.380380 Set Vref, RX VrefLevel [Byte0]: 47
2773 23:52:30.383393 [Byte1]: 47
2774 23:52:30.387640
2775 23:52:30.388048 Set Vref, RX VrefLevel [Byte0]: 48
2776 23:52:30.391330 [Byte1]: 48
2777 23:52:30.395437
2778 23:52:30.395847 Set Vref, RX VrefLevel [Byte0]: 49
2779 23:52:30.399090 [Byte1]: 49
2780 23:52:30.403639
2781 23:52:30.404050 Set Vref, RX VrefLevel [Byte0]: 50
2782 23:52:30.407389 [Byte1]: 50
2783 23:52:30.411837
2784 23:52:30.412269 Set Vref, RX VrefLevel [Byte0]: 51
2785 23:52:30.415207 [Byte1]: 51
2786 23:52:30.419580
2787 23:52:30.419964 Set Vref, RX VrefLevel [Byte0]: 52
2788 23:52:30.422920 [Byte1]: 52
2789 23:52:30.427524
2790 23:52:30.427908 Set Vref, RX VrefLevel [Byte0]: 53
2791 23:52:30.430765 [Byte1]: 53
2792 23:52:30.435697
2793 23:52:30.436123 Set Vref, RX VrefLevel [Byte0]: 54
2794 23:52:30.439144 [Byte1]: 54
2795 23:52:30.443770
2796 23:52:30.444207 Set Vref, RX VrefLevel [Byte0]: 55
2797 23:52:30.447202 [Byte1]: 55
2798 23:52:30.451897
2799 23:52:30.452324 Set Vref, RX VrefLevel [Byte0]: 56
2800 23:52:30.454850 [Byte1]: 56
2801 23:52:30.460013
2802 23:52:30.460441 Set Vref, RX VrefLevel [Byte0]: 57
2803 23:52:30.463400 [Byte1]: 57
2804 23:52:30.467990
2805 23:52:30.468438 Set Vref, RX VrefLevel [Byte0]: 58
2806 23:52:30.471335 [Byte1]: 58
2807 23:52:30.475632
2808 23:52:30.476135 Set Vref, RX VrefLevel [Byte0]: 59
2809 23:52:30.479038 [Byte1]: 59
2810 23:52:30.483842
2811 23:52:30.484254 Set Vref, RX VrefLevel [Byte0]: 60
2812 23:52:30.487220 [Byte1]: 60
2813 23:52:30.492147
2814 23:52:30.492581 Set Vref, RX VrefLevel [Byte0]: 61
2815 23:52:30.495164 [Byte1]: 61
2816 23:52:30.500052
2817 23:52:30.500461 Set Vref, RX VrefLevel [Byte0]: 62
2818 23:52:30.502849 [Byte1]: 62
2819 23:52:30.507732
2820 23:52:30.508156 Set Vref, RX VrefLevel [Byte0]: 63
2821 23:52:30.511342 [Byte1]: 63
2822 23:52:30.516402
2823 23:52:30.516900 Set Vref, RX VrefLevel [Byte0]: 64
2824 23:52:30.518801 [Byte1]: 64
2825 23:52:30.523639
2826 23:52:30.524066 Set Vref, RX VrefLevel [Byte0]: 65
2827 23:52:30.526953 [Byte1]: 65
2828 23:52:30.532007
2829 23:52:30.532439 Set Vref, RX VrefLevel [Byte0]: 66
2830 23:52:30.534826 [Byte1]: 66
2831 23:52:30.539936
2832 23:52:30.540366 Set Vref, RX VrefLevel [Byte0]: 67
2833 23:52:30.543474 [Byte1]: 67
2834 23:52:30.547580
2835 23:52:30.548009 Set Vref, RX VrefLevel [Byte0]: 68
2836 23:52:30.551013 [Byte1]: 68
2837 23:52:30.555767
2838 23:52:30.556204 Set Vref, RX VrefLevel [Byte0]: 69
2839 23:52:30.559351 [Byte1]: 69
2840 23:52:30.563634
2841 23:52:30.564225 Set Vref, RX VrefLevel [Byte0]: 70
2842 23:52:30.567323 [Byte1]: 70
2843 23:52:30.571785
2844 23:52:30.572194 Set Vref, RX VrefLevel [Byte0]: 71
2845 23:52:30.575090 [Byte1]: 71
2846 23:52:30.579674
2847 23:52:30.580101 Set Vref, RX VrefLevel [Byte0]: 72
2848 23:52:30.583281 [Byte1]: 72
2849 23:52:30.587769
2850 23:52:30.588178 Set Vref, RX VrefLevel [Byte0]: 73
2851 23:52:30.591132 [Byte1]: 73
2852 23:52:30.595609
2853 23:52:30.596021 Final RX Vref Byte 0 = 63 to rank0
2854 23:52:30.599463 Final RX Vref Byte 1 = 47 to rank0
2855 23:52:30.602558 Final RX Vref Byte 0 = 63 to rank1
2856 23:52:30.606098 Final RX Vref Byte 1 = 47 to rank1==
2857 23:52:30.608847 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 23:52:30.615632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 23:52:30.616206 ==
2860 23:52:30.616664 DQS Delay:
2861 23:52:30.617004 DQS0 = 0, DQS1 = 0
2862 23:52:30.619031 DQM Delay:
2863 23:52:30.619461 DQM0 = 112, DQM1 = 98
2864 23:52:30.622124 DQ Delay:
2865 23:52:30.625607 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2866 23:52:30.629000 DQ4 =114, DQ5 =104, DQ6 =118, DQ7 =120
2867 23:52:30.632257 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2868 23:52:30.635652 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2869 23:52:30.636080
2870 23:52:30.636406
2871 23:52:30.642330 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2872 23:52:30.645573 CH0 RK0: MR19=303, MR18=FBFA
2873 23:52:30.652014 CH0_RK0: MR19=0x303, MR18=0xFBFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2874 23:52:30.652605
2875 23:52:30.655272 ----->DramcWriteLeveling(PI) begin...
2876 23:52:30.655711 ==
2877 23:52:30.659118 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 23:52:30.662283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 23:52:30.665234 ==
2880 23:52:30.665665 Write leveling (Byte 0): 34 => 34
2881 23:52:30.669238 Write leveling (Byte 1): 32 => 32
2882 23:52:30.671864 DramcWriteLeveling(PI) end<-----
2883 23:52:30.672293
2884 23:52:30.672689 ==
2885 23:52:30.675444 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 23:52:30.681907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 23:52:30.682506 ==
2888 23:52:30.682984 [Gating] SW mode calibration
2889 23:52:30.691891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 23:52:30.695498 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 23:52:30.699117 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2892 23:52:30.705136 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 23:52:30.708828 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 23:52:30.712065 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 23:52:30.718780 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 23:52:30.722138 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 23:52:30.725608 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2898 23:52:30.731939 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2899 23:52:30.735367 1 0 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
2900 23:52:30.738638 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 23:52:30.745284 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 23:52:30.748851 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 23:52:30.752271 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 23:52:30.758883 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 23:52:30.762470 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2906 23:52:30.765368 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2907 23:52:30.772117 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2908 23:52:30.775543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 23:52:30.778836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 23:52:30.782812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 23:52:30.789053 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 23:52:30.792482 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:52:30.795909 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:52:30.802318 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2915 23:52:30.805480 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 23:52:30.809805 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 23:52:30.815728 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 23:52:30.819220 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 23:52:30.822542 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 23:52:30.829096 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 23:52:30.832595 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:52:30.835898 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:52:30.842097 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:52:30.845618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:52:30.849234 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:52:30.855714 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:52:30.859538 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:52:30.862554 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:52:30.865715 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:52:30.872040 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2931 23:52:30.875821 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2932 23:52:30.878738 Total UI for P1: 0, mck2ui 16
2933 23:52:30.882101 best dqsien dly found for B0: ( 1, 3, 28)
2934 23:52:30.886076 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 23:52:30.889038 Total UI for P1: 0, mck2ui 16
2936 23:52:30.892370 best dqsien dly found for B1: ( 1, 4, 0)
2937 23:52:30.895549 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2938 23:52:30.898653 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2939 23:52:30.899101
2940 23:52:30.905701 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2941 23:52:30.909172 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2942 23:52:30.912047 [Gating] SW calibration Done
2943 23:52:30.912479 ==
2944 23:52:30.916018 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 23:52:30.918926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 23:52:30.919361 ==
2947 23:52:30.919692 RX Vref Scan: 0
2948 23:52:30.920000
2949 23:52:30.922481 RX Vref 0 -> 0, step: 1
2950 23:52:30.923003
2951 23:52:30.926975 RX Delay -40 -> 252, step: 8
2952 23:52:30.929002 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2953 23:52:30.932601 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2954 23:52:30.935765 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2955 23:52:30.942388 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2956 23:52:30.945642 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2957 23:52:30.948898 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2958 23:52:30.952250 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2959 23:52:30.955632 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2960 23:52:30.962341 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2961 23:52:30.965726 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2962 23:52:30.969246 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2963 23:52:30.972478 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2964 23:52:30.975580 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2965 23:52:30.982128 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2966 23:52:30.986163 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2967 23:52:30.988764 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2968 23:52:30.989206 ==
2969 23:52:30.992425 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 23:52:30.995661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 23:52:30.996105 ==
2972 23:52:30.999008 DQS Delay:
2973 23:52:30.999417 DQS0 = 0, DQS1 = 0
2974 23:52:31.002180 DQM Delay:
2975 23:52:31.002660 DQM0 = 111, DQM1 = 100
2976 23:52:31.002994 DQ Delay:
2977 23:52:31.006017 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2978 23:52:31.009200 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2979 23:52:31.012396 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =91
2980 23:52:31.019196 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2981 23:52:31.019613
2982 23:52:31.019940
2983 23:52:31.020243 ==
2984 23:52:31.022542 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 23:52:31.025964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 23:52:31.026378 ==
2987 23:52:31.026706
2988 23:52:31.027006
2989 23:52:31.029040 TX Vref Scan disable
2990 23:52:31.029449 == TX Byte 0 ==
2991 23:52:31.036019 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2992 23:52:31.039317 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2993 23:52:31.039782 == TX Byte 1 ==
2994 23:52:31.046075 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2995 23:52:31.049223 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2996 23:52:31.049641 ==
2997 23:52:31.052270 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 23:52:31.055581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 23:52:31.055997 ==
3000 23:52:31.068341 TX Vref=22, minBit 1, minWin=25, winSum=426
3001 23:52:31.071596 TX Vref=24, minBit 12, minWin=26, winSum=432
3002 23:52:31.074605 TX Vref=26, minBit 2, minWin=26, winSum=433
3003 23:52:31.078062 TX Vref=28, minBit 7, minWin=26, winSum=438
3004 23:52:31.081462 TX Vref=30, minBit 13, minWin=26, winSum=438
3005 23:52:31.088487 TX Vref=32, minBit 13, minWin=26, winSum=437
3006 23:52:31.091646 [TxChooseVref] Worse bit 7, Min win 26, Win sum 438, Final Vref 28
3007 23:52:31.091727
3008 23:52:31.094940 Final TX Range 1 Vref 28
3009 23:52:31.095020
3010 23:52:31.095084 ==
3011 23:52:31.098217 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 23:52:31.101672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 23:52:31.101753 ==
3014 23:52:31.105038
3015 23:52:31.105117
3016 23:52:31.105180 TX Vref Scan disable
3017 23:52:31.108260 == TX Byte 0 ==
3018 23:52:31.111898 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3019 23:52:31.115354 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3020 23:52:31.118655 == TX Byte 1 ==
3021 23:52:31.121605 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3022 23:52:31.125361 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3023 23:52:31.127972
3024 23:52:31.128051 [DATLAT]
3025 23:52:31.128114 Freq=1200, CH0 RK1
3026 23:52:31.128173
3027 23:52:31.131611 DATLAT Default: 0xd
3028 23:52:31.131690 0, 0xFFFF, sum = 0
3029 23:52:31.134875 1, 0xFFFF, sum = 0
3030 23:52:31.134957 2, 0xFFFF, sum = 0
3031 23:52:31.138293 3, 0xFFFF, sum = 0
3032 23:52:31.138410 4, 0xFFFF, sum = 0
3033 23:52:31.141777 5, 0xFFFF, sum = 0
3034 23:52:31.141858 6, 0xFFFF, sum = 0
3035 23:52:31.144937 7, 0xFFFF, sum = 0
3036 23:52:31.148550 8, 0xFFFF, sum = 0
3037 23:52:31.148640 9, 0xFFFF, sum = 0
3038 23:52:31.151857 10, 0xFFFF, sum = 0
3039 23:52:31.151937 11, 0xFFFF, sum = 0
3040 23:52:31.154892 12, 0x0, sum = 1
3041 23:52:31.154972 13, 0x0, sum = 2
3042 23:52:31.159064 14, 0x0, sum = 3
3043 23:52:31.159145 15, 0x0, sum = 4
3044 23:52:31.159210 best_step = 13
3045 23:52:31.159268
3046 23:52:31.161867 ==
3047 23:52:31.165108 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 23:52:31.168240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 23:52:31.168327 ==
3050 23:52:31.168394 RX Vref Scan: 0
3051 23:52:31.168464
3052 23:52:31.171735 RX Vref 0 -> 0, step: 1
3053 23:52:31.171815
3054 23:52:31.174828 RX Delay -37 -> 252, step: 4
3055 23:52:31.178175 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3056 23:52:31.185213 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3057 23:52:31.188253 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3058 23:52:31.191392 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3059 23:52:31.195702 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3060 23:52:31.198476 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3061 23:52:31.201686 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3062 23:52:31.208396 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3063 23:52:31.211690 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3064 23:52:31.215098 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3065 23:52:31.218561 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3066 23:52:31.221729 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3067 23:52:31.228274 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3068 23:52:31.231791 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3069 23:52:31.234978 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3070 23:52:31.238328 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3071 23:52:31.238411 ==
3072 23:52:31.241756 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 23:52:31.244872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 23:52:31.248401 ==
3075 23:52:31.248497 DQS Delay:
3076 23:52:31.248591 DQS0 = 0, DQS1 = 0
3077 23:52:31.251654 DQM Delay:
3078 23:52:31.251727 DQM0 = 111, DQM1 = 99
3079 23:52:31.255447 DQ Delay:
3080 23:52:31.258530 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3081 23:52:31.261774 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3082 23:52:31.264933 DQ8 =88, DQ9 =82, DQ10 =100, DQ11 =90
3083 23:52:31.268552 DQ12 =108, DQ13 =108, DQ14 =112, DQ15 =108
3084 23:52:31.268677
3085 23:52:31.268741
3086 23:52:31.275073 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3087 23:52:31.278277 CH0 RK1: MR19=403, MR18=15FE
3088 23:52:31.285366 CH0_RK1: MR19=0x403, MR18=0x15FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3089 23:52:31.288180 [RxdqsGatingPostProcess] freq 1200
3090 23:52:31.295320 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 23:52:31.295430 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 23:52:31.298415 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 23:52:31.301844 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 23:52:31.304911 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 23:52:31.308351 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 23:52:31.311814 best DQS1 dly(2T, 0.5T) = (0, 12)
3097 23:52:31.315555 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 23:52:31.318844 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3099 23:52:31.322104 Pre-setting of DQS Precalculation
3100 23:52:31.325035 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 23:52:31.328586 ==
3102 23:52:31.328724 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 23:52:31.335134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 23:52:31.335283 ==
3105 23:52:31.338951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 23:52:31.345107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 23:52:31.354439 [CA 0] Center 37 (8~67) winsize 60
3108 23:52:31.358314 [CA 1] Center 37 (7~68) winsize 62
3109 23:52:31.361406 [CA 2] Center 34 (5~64) winsize 60
3110 23:52:31.364619 [CA 3] Center 33 (3~64) winsize 62
3111 23:52:31.368187 [CA 4] Center 34 (4~64) winsize 61
3112 23:52:31.371236 [CA 5] Center 33 (3~63) winsize 61
3113 23:52:31.371589
3114 23:52:31.374612 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3115 23:52:31.374987
3116 23:52:31.378013 [CATrainingPosCal] consider 1 rank data
3117 23:52:31.381139 u2DelayCellTimex100 = 270/100 ps
3118 23:52:31.384597 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3119 23:52:31.388095 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 23:52:31.394498 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3121 23:52:31.397891 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3122 23:52:31.401336 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 23:52:31.404373 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3124 23:52:31.404867
3125 23:52:31.407738 CA PerBit enable=1, Macro0, CA PI delay=33
3126 23:52:31.408206
3127 23:52:31.411497 [CBTSetCACLKResult] CA Dly = 33
3128 23:52:31.411936 CS Dly: 5 (0~36)
3129 23:52:31.412286 ==
3130 23:52:31.414627 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 23:52:31.421392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 23:52:31.421839 ==
3133 23:52:31.424456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 23:52:31.431321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3135 23:52:31.440366 [CA 0] Center 37 (7~67) winsize 61
3136 23:52:31.443379 [CA 1] Center 37 (7~68) winsize 62
3137 23:52:31.446708 [CA 2] Center 34 (4~65) winsize 62
3138 23:52:31.450410 [CA 3] Center 33 (3~64) winsize 62
3139 23:52:31.453815 [CA 4] Center 34 (4~65) winsize 62
3140 23:52:31.457028 [CA 5] Center 33 (3~63) winsize 61
3141 23:52:31.457491
3142 23:52:31.460309 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 23:52:31.460794
3144 23:52:31.463390 [CATrainingPosCal] consider 2 rank data
3145 23:52:31.467309 u2DelayCellTimex100 = 270/100 ps
3146 23:52:31.470641 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3147 23:52:31.473582 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 23:52:31.480270 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3149 23:52:31.483525 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 23:52:31.486728 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 23:52:31.490552 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3152 23:52:31.490960
3153 23:52:31.493921 CA PerBit enable=1, Macro0, CA PI delay=33
3154 23:52:31.494333
3155 23:52:31.496637 [CBTSetCACLKResult] CA Dly = 33
3156 23:52:31.497049 CS Dly: 7 (0~40)
3157 23:52:31.497374
3158 23:52:31.500074 ----->DramcWriteLeveling(PI) begin...
3159 23:52:31.503544 ==
3160 23:52:31.503954 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 23:52:31.510244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 23:52:31.510660 ==
3163 23:52:31.513453 Write leveling (Byte 0): 25 => 25
3164 23:52:31.516427 Write leveling (Byte 1): 28 => 28
3165 23:52:31.520014 DramcWriteLeveling(PI) end<-----
3166 23:52:31.520487
3167 23:52:31.520846 ==
3168 23:52:31.523134 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 23:52:31.526593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 23:52:31.527025 ==
3171 23:52:31.530170 [Gating] SW mode calibration
3172 23:52:31.536663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 23:52:31.543294 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 23:52:31.546457 0 15 0 | B1->B0 | 2c2c 2726 | 1 1 | (0 0) (0 0)
3175 23:52:31.549794 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 23:52:31.553273 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 23:52:31.559823 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 23:52:31.563425 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 23:52:31.566358 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:52:31.573514 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:52:31.577001 0 15 28 | B1->B0 | 2c2c 2b2b | 0 0 | (0 1) (0 0)
3182 23:52:31.579709 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3183 23:52:31.586800 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 23:52:31.589731 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 23:52:31.593711 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 23:52:31.599586 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 23:52:31.603396 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:52:31.606676 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3189 23:52:31.613165 1 0 28 | B1->B0 | 3d3d 3535 | 1 1 | (0 0) (0 0)
3190 23:52:31.616791 1 1 0 | B1->B0 | 4444 4242 | 1 0 | (0 0) (0 0)
3191 23:52:31.620059 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 23:52:31.626645 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 23:52:31.629712 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 23:52:31.633643 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:52:31.639921 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:52:31.643221 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:52:31.646428 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:52:31.649853 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3199 23:52:31.656374 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 23:52:31.660109 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 23:52:31.663045 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 23:52:31.669871 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:52:31.673426 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:52:31.676400 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:52:31.683211 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:52:31.686582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:52:31.689801 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:52:31.696678 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:52:31.700118 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:52:31.703404 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:52:31.710212 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:52:31.713407 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:52:31.716467 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 23:52:31.723148 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3215 23:52:31.723562 Total UI for P1: 0, mck2ui 16
3216 23:52:31.730369 best dqsien dly found for B1: ( 1, 3, 28)
3217 23:52:31.733085 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 23:52:31.736851 Total UI for P1: 0, mck2ui 16
3219 23:52:31.740045 best dqsien dly found for B0: ( 1, 3, 30)
3220 23:52:31.743305 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3221 23:52:31.746874 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3222 23:52:31.747310
3223 23:52:31.749880 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3224 23:52:31.753221 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3225 23:52:31.756589 [Gating] SW calibration Done
3226 23:52:31.757036 ==
3227 23:52:31.760190 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 23:52:31.763529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 23:52:31.763981 ==
3230 23:52:31.766503 RX Vref Scan: 0
3231 23:52:31.766937
3232 23:52:31.770028 RX Vref 0 -> 0, step: 1
3233 23:52:31.770468
3234 23:52:31.770818 RX Delay -40 -> 252, step: 8
3235 23:52:31.776880 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3236 23:52:31.780019 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3237 23:52:31.783205 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3238 23:52:31.786649 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3239 23:52:31.789944 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3240 23:52:31.796702 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3241 23:52:31.800107 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3242 23:52:31.803436 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3243 23:52:31.807056 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3244 23:52:31.810194 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3245 23:52:31.813483 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3246 23:52:31.820139 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3247 23:52:31.823549 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3248 23:52:31.826672 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3249 23:52:31.830075 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3250 23:52:31.833597 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3251 23:52:31.836545 ==
3252 23:52:31.839798 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 23:52:31.843476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 23:52:31.843881 ==
3255 23:52:31.844201 DQS Delay:
3256 23:52:31.846978 DQS0 = 0, DQS1 = 0
3257 23:52:31.847379 DQM Delay:
3258 23:52:31.849957 DQM0 = 114, DQM1 = 106
3259 23:52:31.850361 DQ Delay:
3260 23:52:31.853640 DQ0 =123, DQ1 =107, DQ2 =99, DQ3 =115
3261 23:52:31.856720 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3262 23:52:31.860365 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3263 23:52:31.863528 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3264 23:52:31.863967
3265 23:52:31.864322
3266 23:52:31.864709 ==
3267 23:52:31.867255 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 23:52:31.870153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 23:52:31.873604 ==
3270 23:52:31.874027
3271 23:52:31.874350
3272 23:52:31.874650 TX Vref Scan disable
3273 23:52:31.877073 == TX Byte 0 ==
3274 23:52:31.880226 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3275 23:52:31.883203 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3276 23:52:31.886431 == TX Byte 1 ==
3277 23:52:31.890785 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3278 23:52:31.893392 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3279 23:52:31.896874 ==
3280 23:52:31.900246 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 23:52:31.903550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 23:52:31.904008 ==
3283 23:52:31.914207 TX Vref=22, minBit 11, minWin=24, winSum=408
3284 23:52:31.918017 TX Vref=24, minBit 11, minWin=24, winSum=410
3285 23:52:31.921127 TX Vref=26, minBit 8, minWin=25, winSum=419
3286 23:52:31.924408 TX Vref=28, minBit 9, minWin=25, winSum=421
3287 23:52:31.927875 TX Vref=30, minBit 9, minWin=25, winSum=423
3288 23:52:31.934349 TX Vref=32, minBit 9, minWin=25, winSum=423
3289 23:52:31.937532 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 30
3290 23:52:31.937970
3291 23:52:31.941424 Final TX Range 1 Vref 30
3292 23:52:31.941834
3293 23:52:31.942184 ==
3294 23:52:31.944249 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 23:52:31.947609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 23:52:31.948024 ==
3297 23:52:31.948350
3298 23:52:31.951399
3299 23:52:31.951806 TX Vref Scan disable
3300 23:52:31.954475 == TX Byte 0 ==
3301 23:52:31.957934 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3302 23:52:31.961116 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3303 23:52:31.964379 == TX Byte 1 ==
3304 23:52:31.968005 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3305 23:52:31.971275 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3306 23:52:31.971688
3307 23:52:31.974540 [DATLAT]
3308 23:52:31.974949 Freq=1200, CH1 RK0
3309 23:52:31.975275
3310 23:52:31.977727 DATLAT Default: 0xd
3311 23:52:31.978139 0, 0xFFFF, sum = 0
3312 23:52:31.981158 1, 0xFFFF, sum = 0
3313 23:52:31.981575 2, 0xFFFF, sum = 0
3314 23:52:31.984424 3, 0xFFFF, sum = 0
3315 23:52:31.984873 4, 0xFFFF, sum = 0
3316 23:52:31.987998 5, 0xFFFF, sum = 0
3317 23:52:31.988413 6, 0xFFFF, sum = 0
3318 23:52:31.991101 7, 0xFFFF, sum = 0
3319 23:52:31.994562 8, 0xFFFF, sum = 0
3320 23:52:31.994982 9, 0xFFFF, sum = 0
3321 23:52:31.997668 10, 0xFFFF, sum = 0
3322 23:52:31.998103 11, 0xFFFF, sum = 0
3323 23:52:32.001247 12, 0x0, sum = 1
3324 23:52:32.001648 13, 0x0, sum = 2
3325 23:52:32.004743 14, 0x0, sum = 3
3326 23:52:32.005154 15, 0x0, sum = 4
3327 23:52:32.005475 best_step = 13
3328 23:52:32.005786
3329 23:52:32.007909 ==
3330 23:52:32.011448 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 23:52:32.014647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 23:52:32.015042 ==
3333 23:52:32.015360 RX Vref Scan: 1
3334 23:52:32.015651
3335 23:52:32.017999 Set Vref Range= 32 -> 127
3336 23:52:32.018440
3337 23:52:32.020957 RX Vref 32 -> 127, step: 1
3338 23:52:32.021366
3339 23:52:32.024529 RX Delay -21 -> 252, step: 4
3340 23:52:32.024990
3341 23:52:32.027710 Set Vref, RX VrefLevel [Byte0]: 32
3342 23:52:32.031018 [Byte1]: 32
3343 23:52:32.031456
3344 23:52:32.034683 Set Vref, RX VrefLevel [Byte0]: 33
3345 23:52:32.037826 [Byte1]: 33
3346 23:52:32.038255
3347 23:52:32.041055 Set Vref, RX VrefLevel [Byte0]: 34
3348 23:52:32.044464 [Byte1]: 34
3349 23:52:32.048847
3350 23:52:32.049280 Set Vref, RX VrefLevel [Byte0]: 35
3351 23:52:32.052130 [Byte1]: 35
3352 23:52:32.056769
3353 23:52:32.057211 Set Vref, RX VrefLevel [Byte0]: 36
3354 23:52:32.060056 [Byte1]: 36
3355 23:52:32.064550
3356 23:52:32.065015 Set Vref, RX VrefLevel [Byte0]: 37
3357 23:52:32.067952 [Byte1]: 37
3358 23:52:32.072154
3359 23:52:32.072590 Set Vref, RX VrefLevel [Byte0]: 38
3360 23:52:32.075689 [Byte1]: 38
3361 23:52:32.080448
3362 23:52:32.080885 Set Vref, RX VrefLevel [Byte0]: 39
3363 23:52:32.084017 [Byte1]: 39
3364 23:52:32.088282
3365 23:52:32.088723 Set Vref, RX VrefLevel [Byte0]: 40
3366 23:52:32.091528 [Byte1]: 40
3367 23:52:32.096381
3368 23:52:32.096814 Set Vref, RX VrefLevel [Byte0]: 41
3369 23:52:32.099901 [Byte1]: 41
3370 23:52:32.104051
3371 23:52:32.104465 Set Vref, RX VrefLevel [Byte0]: 42
3372 23:52:32.107327 [Byte1]: 42
3373 23:52:32.112290
3374 23:52:32.112731 Set Vref, RX VrefLevel [Byte0]: 43
3375 23:52:32.115538 [Byte1]: 43
3376 23:52:32.120335
3377 23:52:32.120839 Set Vref, RX VrefLevel [Byte0]: 44
3378 23:52:32.123016 [Byte1]: 44
3379 23:52:32.128061
3380 23:52:32.128459 Set Vref, RX VrefLevel [Byte0]: 45
3381 23:52:32.130970 [Byte1]: 45
3382 23:52:32.135969
3383 23:52:32.136370 Set Vref, RX VrefLevel [Byte0]: 46
3384 23:52:32.139234 [Byte1]: 46
3385 23:52:32.143703
3386 23:52:32.144116 Set Vref, RX VrefLevel [Byte0]: 47
3387 23:52:32.147100 [Byte1]: 47
3388 23:52:32.151606
3389 23:52:32.152007 Set Vref, RX VrefLevel [Byte0]: 48
3390 23:52:32.154917 [Byte1]: 48
3391 23:52:32.159766
3392 23:52:32.160167 Set Vref, RX VrefLevel [Byte0]: 49
3393 23:52:32.163130 [Byte1]: 49
3394 23:52:32.167560
3395 23:52:32.168013 Set Vref, RX VrefLevel [Byte0]: 50
3396 23:52:32.170710 [Byte1]: 50
3397 23:52:32.175295
3398 23:52:32.175782 Set Vref, RX VrefLevel [Byte0]: 51
3399 23:52:32.178610 [Byte1]: 51
3400 23:52:32.183326
3401 23:52:32.183777 Set Vref, RX VrefLevel [Byte0]: 52
3402 23:52:32.186531 [Byte1]: 52
3403 23:52:32.191520
3404 23:52:32.191982 Set Vref, RX VrefLevel [Byte0]: 53
3405 23:52:32.194756 [Byte1]: 53
3406 23:52:32.199239
3407 23:52:32.199640 Set Vref, RX VrefLevel [Byte0]: 54
3408 23:52:32.202511 [Byte1]: 54
3409 23:52:32.207073
3410 23:52:32.207486 Set Vref, RX VrefLevel [Byte0]: 55
3411 23:52:32.210399 [Byte1]: 55
3412 23:52:32.215005
3413 23:52:32.215406 Set Vref, RX VrefLevel [Byte0]: 56
3414 23:52:32.218087 [Byte1]: 56
3415 23:52:32.223251
3416 23:52:32.223655 Set Vref, RX VrefLevel [Byte0]: 57
3417 23:52:32.226624 [Byte1]: 57
3418 23:52:32.231025
3419 23:52:32.231424 Set Vref, RX VrefLevel [Byte0]: 58
3420 23:52:32.233995 [Byte1]: 58
3421 23:52:32.239155
3422 23:52:32.239555 Set Vref, RX VrefLevel [Byte0]: 59
3423 23:52:32.242134 [Byte1]: 59
3424 23:52:32.246464
3425 23:52:32.246865 Set Vref, RX VrefLevel [Byte0]: 60
3426 23:52:32.250188 [Byte1]: 60
3427 23:52:32.254815
3428 23:52:32.255215 Set Vref, RX VrefLevel [Byte0]: 61
3429 23:52:32.257963 [Byte1]: 61
3430 23:52:32.262524
3431 23:52:32.262926 Set Vref, RX VrefLevel [Byte0]: 62
3432 23:52:32.265643 [Byte1]: 62
3433 23:52:32.270424
3434 23:52:32.270826 Set Vref, RX VrefLevel [Byte0]: 63
3435 23:52:32.273659 [Byte1]: 63
3436 23:52:32.278479
3437 23:52:32.278896 Set Vref, RX VrefLevel [Byte0]: 64
3438 23:52:32.281507 [Byte1]: 64
3439 23:52:32.286461
3440 23:52:32.286863 Set Vref, RX VrefLevel [Byte0]: 65
3441 23:52:32.289551 [Byte1]: 65
3442 23:52:32.294045
3443 23:52:32.294446 Set Vref, RX VrefLevel [Byte0]: 66
3444 23:52:32.297446 [Byte1]: 66
3445 23:52:32.302089
3446 23:52:32.302615 Set Vref, RX VrefLevel [Byte0]: 67
3447 23:52:32.305371 [Byte1]: 67
3448 23:52:32.310042
3449 23:52:32.310446 Final RX Vref Byte 0 = 58 to rank0
3450 23:52:32.313417 Final RX Vref Byte 1 = 52 to rank0
3451 23:52:32.316837 Final RX Vref Byte 0 = 58 to rank1
3452 23:52:32.320319 Final RX Vref Byte 1 = 52 to rank1==
3453 23:52:32.323555 Dram Type= 6, Freq= 0, CH_1, rank 0
3454 23:52:32.329985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 23:52:32.330392 ==
3456 23:52:32.330719 DQS Delay:
3457 23:52:32.331021 DQS0 = 0, DQS1 = 0
3458 23:52:32.333378 DQM Delay:
3459 23:52:32.333782 DQM0 = 113, DQM1 = 105
3460 23:52:32.337319 DQ Delay:
3461 23:52:32.340357 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =108
3462 23:52:32.343705 DQ4 =110, DQ5 =122, DQ6 =128, DQ7 =112
3463 23:52:32.346713 DQ8 =94, DQ9 =96, DQ10 =106, DQ11 =98
3464 23:52:32.349748 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =112
3465 23:52:32.350158
3466 23:52:32.350601
3467 23:52:32.356429 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3468 23:52:32.359801 CH1 RK0: MR19=303, MR18=F1F8
3469 23:52:32.366727 CH1_RK0: MR19=0x303, MR18=0xF1F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3470 23:52:32.367143
3471 23:52:32.369939 ----->DramcWriteLeveling(PI) begin...
3472 23:52:32.370349 ==
3473 23:52:32.373128 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 23:52:32.376666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 23:52:32.379831 ==
3476 23:52:32.382978 Write leveling (Byte 0): 25 => 25
3477 23:52:32.383387 Write leveling (Byte 1): 28 => 28
3478 23:52:32.386323 DramcWriteLeveling(PI) end<-----
3479 23:52:32.386728
3480 23:52:32.387047 ==
3481 23:52:32.389719 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 23:52:32.396351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 23:52:32.396805 ==
3484 23:52:32.399689 [Gating] SW mode calibration
3485 23:52:32.406911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3486 23:52:32.409698 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3487 23:52:32.416537 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 23:52:32.419421 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 23:52:32.423191 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 23:52:32.429800 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 23:52:32.433136 0 15 16 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
3492 23:52:32.436479 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3493 23:52:32.442617 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
3494 23:52:32.445989 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3495 23:52:32.449552 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 23:52:32.453029 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 23:52:32.459322 1 0 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3498 23:52:32.462745 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 23:52:32.466068 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 23:52:32.472766 1 0 20 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
3501 23:52:32.476465 1 0 24 | B1->B0 | 2928 4444 | 1 0 | (0 0) (0 0)
3502 23:52:32.479523 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3503 23:52:32.486161 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 23:52:32.489325 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 23:52:32.493009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 23:52:32.499182 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 23:52:32.502801 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 23:52:32.506177 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3509 23:52:32.512651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3510 23:52:32.515950 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3511 23:52:32.519223 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 23:52:32.526001 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 23:52:32.529601 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 23:52:32.532802 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 23:52:32.539362 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 23:52:32.542664 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:52:32.546017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:52:32.552673 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:52:32.556013 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:52:32.559099 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:52:32.566220 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:52:32.569387 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:52:32.572724 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:52:32.575605 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3525 23:52:32.582742 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3526 23:52:32.585934 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3527 23:52:32.589207 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 23:52:32.592544 Total UI for P1: 0, mck2ui 16
3529 23:52:32.595834 best dqsien dly found for B0: ( 1, 3, 24)
3530 23:52:32.598952 Total UI for P1: 0, mck2ui 16
3531 23:52:32.602132 best dqsien dly found for B1: ( 1, 3, 26)
3532 23:52:32.605559 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3533 23:52:32.611686 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3534 23:52:32.611765
3535 23:52:32.615355 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3536 23:52:32.618319 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3537 23:52:32.621585 [Gating] SW calibration Done
3538 23:52:32.621664 ==
3539 23:52:32.625260 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 23:52:32.628518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 23:52:32.628638 ==
3542 23:52:32.628701 RX Vref Scan: 0
3543 23:52:32.631838
3544 23:52:32.631935 RX Vref 0 -> 0, step: 1
3545 23:52:32.632029
3546 23:52:32.635220 RX Delay -40 -> 252, step: 8
3547 23:52:32.638274 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3548 23:52:32.641695 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3549 23:52:32.648545 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3550 23:52:32.651784 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3551 23:52:32.655098 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3552 23:52:32.658564 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3553 23:52:32.661679 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3554 23:52:32.667852 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3555 23:52:32.671452 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3556 23:52:32.674765 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3557 23:52:32.678144 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3558 23:52:32.681165 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3559 23:52:32.687707 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3560 23:52:32.691080 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3561 23:52:32.694314 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3562 23:52:32.697726 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3563 23:52:32.697796 ==
3564 23:52:32.701109 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 23:52:32.707560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 23:52:32.707640 ==
3567 23:52:32.707701 DQS Delay:
3568 23:52:32.710831 DQS0 = 0, DQS1 = 0
3569 23:52:32.710900 DQM Delay:
3570 23:52:32.714232 DQM0 = 111, DQM1 = 108
3571 23:52:32.714301 DQ Delay:
3572 23:52:32.717633 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =111
3573 23:52:32.720982 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3574 23:52:32.724573 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3575 23:52:32.727490 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =111
3576 23:52:32.727564
3577 23:52:32.727625
3578 23:52:32.727681 ==
3579 23:52:32.730745 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 23:52:32.737243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 23:52:32.737319 ==
3582 23:52:32.737380
3583 23:52:32.737437
3584 23:52:32.737498 TX Vref Scan disable
3585 23:52:32.741104 == TX Byte 0 ==
3586 23:52:32.744240 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3587 23:52:32.747437 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3588 23:52:32.750953 == TX Byte 1 ==
3589 23:52:32.754259 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3590 23:52:32.757254 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3591 23:52:32.761209 ==
3592 23:52:32.764056 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 23:52:32.767248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 23:52:32.767321 ==
3595 23:52:32.778448 TX Vref=22, minBit 9, minWin=25, winSum=420
3596 23:52:32.781754 TX Vref=24, minBit 9, minWin=25, winSum=427
3597 23:52:32.785080 TX Vref=26, minBit 1, minWin=26, winSum=433
3598 23:52:32.788531 TX Vref=28, minBit 9, minWin=26, winSum=436
3599 23:52:32.791728 TX Vref=30, minBit 8, minWin=26, winSum=432
3600 23:52:32.798612 TX Vref=32, minBit 8, minWin=25, winSum=432
3601 23:52:32.801947 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3602 23:52:32.802026
3603 23:52:32.805143 Final TX Range 1 Vref 28
3604 23:52:32.805222
3605 23:52:32.805284 ==
3606 23:52:32.808396 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 23:52:32.811882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 23:52:32.814960 ==
3609 23:52:32.815039
3610 23:52:32.815101
3611 23:52:32.815159 TX Vref Scan disable
3612 23:52:32.818570 == TX Byte 0 ==
3613 23:52:32.821880 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3614 23:52:32.828451 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3615 23:52:32.828530 == TX Byte 1 ==
3616 23:52:32.832314 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3617 23:52:32.838456 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3618 23:52:32.838535
3619 23:52:32.838597 [DATLAT]
3620 23:52:32.838655 Freq=1200, CH1 RK1
3621 23:52:32.838751
3622 23:52:32.841509 DATLAT Default: 0xd
3623 23:52:32.841588 0, 0xFFFF, sum = 0
3624 23:52:32.844828 1, 0xFFFF, sum = 0
3625 23:52:32.847809 2, 0xFFFF, sum = 0
3626 23:52:32.847889 3, 0xFFFF, sum = 0
3627 23:52:32.851425 4, 0xFFFF, sum = 0
3628 23:52:32.851505 5, 0xFFFF, sum = 0
3629 23:52:32.854710 6, 0xFFFF, sum = 0
3630 23:52:32.854819 7, 0xFFFF, sum = 0
3631 23:52:32.858046 8, 0xFFFF, sum = 0
3632 23:52:32.858127 9, 0xFFFF, sum = 0
3633 23:52:32.861415 10, 0xFFFF, sum = 0
3634 23:52:32.861496 11, 0xFFFF, sum = 0
3635 23:52:32.864785 12, 0x0, sum = 1
3636 23:52:32.864866 13, 0x0, sum = 2
3637 23:52:32.868267 14, 0x0, sum = 3
3638 23:52:32.868347 15, 0x0, sum = 4
3639 23:52:32.871060 best_step = 13
3640 23:52:32.871139
3641 23:52:32.871201 ==
3642 23:52:32.874643 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 23:52:32.878446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 23:52:32.878525 ==
3645 23:52:32.878588 RX Vref Scan: 0
3646 23:52:32.878646
3647 23:52:32.881327 RX Vref 0 -> 0, step: 1
3648 23:52:32.881406
3649 23:52:32.884648 RX Delay -21 -> 252, step: 4
3650 23:52:32.891026 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3651 23:52:32.894457 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3652 23:52:32.897735 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3653 23:52:32.901552 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3654 23:52:32.904416 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3655 23:52:32.907710 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3656 23:52:32.914425 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3657 23:52:32.917458 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3658 23:52:32.921415 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3659 23:52:32.924487 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3660 23:52:32.927705 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3661 23:52:32.934641 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3662 23:52:32.937915 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3663 23:52:32.941290 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3664 23:52:32.944490 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3665 23:52:32.950691 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3666 23:52:32.950771 ==
3667 23:52:32.954302 Dram Type= 6, Freq= 0, CH_1, rank 1
3668 23:52:32.957568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3669 23:52:32.957648 ==
3670 23:52:32.957711 DQS Delay:
3671 23:52:32.961007 DQS0 = 0, DQS1 = 0
3672 23:52:32.961086 DQM Delay:
3673 23:52:32.964015 DQM0 = 111, DQM1 = 111
3674 23:52:32.964094 DQ Delay:
3675 23:52:32.967231 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3676 23:52:32.971263 DQ4 =108, DQ5 =120, DQ6 =122, DQ7 =108
3677 23:52:32.973963 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =104
3678 23:52:32.977267 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3679 23:52:32.977346
3680 23:52:32.977408
3681 23:52:32.987312 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3682 23:52:32.990607 CH1 RK1: MR19=304, MR18=FC0C
3683 23:52:32.997095 CH1_RK1: MR19=0x304, MR18=0xFC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3684 23:52:32.997175 [RxdqsGatingPostProcess] freq 1200
3685 23:52:33.004284 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3686 23:52:33.007429 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 23:52:33.010566 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 23:52:33.013816 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 23:52:33.017403 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 23:52:33.020529 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 23:52:33.023836 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 23:52:33.027192 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 23:52:33.030563 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 23:52:33.034116 Pre-setting of DQS Precalculation
3695 23:52:33.037291 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3696 23:52:33.043716 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3697 23:52:33.050554 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3698 23:52:33.053837
3699 23:52:33.053954
3700 23:52:33.054046 [Calibration Summary] 2400 Mbps
3701 23:52:33.057468 CH 0, Rank 0
3702 23:52:33.057598 SW Impedance : PASS
3703 23:52:33.060711 DUTY Scan : NO K
3704 23:52:33.063768 ZQ Calibration : PASS
3705 23:52:33.063914 Jitter Meter : NO K
3706 23:52:33.067325 CBT Training : PASS
3707 23:52:33.070525 Write leveling : PASS
3708 23:52:33.070726 RX DQS gating : PASS
3709 23:52:33.073464 RX DQ/DQS(RDDQC) : PASS
3710 23:52:33.077287 TX DQ/DQS : PASS
3711 23:52:33.077534 RX DATLAT : PASS
3712 23:52:33.080499 RX DQ/DQS(Engine): PASS
3713 23:52:33.083495 TX OE : NO K
3714 23:52:33.083748 All Pass.
3715 23:52:33.083983
3716 23:52:33.084200 CH 0, Rank 1
3717 23:52:33.087022 SW Impedance : PASS
3718 23:52:33.090446 DUTY Scan : NO K
3719 23:52:33.090824 ZQ Calibration : PASS
3720 23:52:33.093581 Jitter Meter : NO K
3721 23:52:33.096782 CBT Training : PASS
3722 23:52:33.097147 Write leveling : PASS
3723 23:52:33.100422 RX DQS gating : PASS
3724 23:52:33.103758 RX DQ/DQS(RDDQC) : PASS
3725 23:52:33.104226 TX DQ/DQS : PASS
3726 23:52:33.106794 RX DATLAT : PASS
3727 23:52:33.110591 RX DQ/DQS(Engine): PASS
3728 23:52:33.111017 TX OE : NO K
3729 23:52:33.111377 All Pass.
3730 23:52:33.113451
3731 23:52:33.113896 CH 1, Rank 0
3732 23:52:33.116975 SW Impedance : PASS
3733 23:52:33.117426 DUTY Scan : NO K
3734 23:52:33.120226 ZQ Calibration : PASS
3735 23:52:33.120717 Jitter Meter : NO K
3736 23:52:33.123568 CBT Training : PASS
3737 23:52:33.126245 Write leveling : PASS
3738 23:52:33.126328 RX DQS gating : PASS
3739 23:52:33.129871 RX DQ/DQS(RDDQC) : PASS
3740 23:52:33.133094 TX DQ/DQS : PASS
3741 23:52:33.133182 RX DATLAT : PASS
3742 23:52:33.136323 RX DQ/DQS(Engine): PASS
3743 23:52:33.139606 TX OE : NO K
3744 23:52:33.139688 All Pass.
3745 23:52:33.139751
3746 23:52:33.139809 CH 1, Rank 1
3747 23:52:33.142737 SW Impedance : PASS
3748 23:52:33.146406 DUTY Scan : NO K
3749 23:52:33.146496 ZQ Calibration : PASS
3750 23:52:33.149617 Jitter Meter : NO K
3751 23:52:33.153083 CBT Training : PASS
3752 23:52:33.153196 Write leveling : PASS
3753 23:52:33.156274 RX DQS gating : PASS
3754 23:52:33.159444 RX DQ/DQS(RDDQC) : PASS
3755 23:52:33.159520 TX DQ/DQS : PASS
3756 23:52:33.163064 RX DATLAT : PASS
3757 23:52:33.165917 RX DQ/DQS(Engine): PASS
3758 23:52:33.166001 TX OE : NO K
3759 23:52:33.166062 All Pass.
3760 23:52:33.169557
3761 23:52:33.169632 DramC Write-DBI off
3762 23:52:33.172819 PER_BANK_REFRESH: Hybrid Mode
3763 23:52:33.172893 TX_TRACKING: ON
3764 23:52:33.183145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3765 23:52:33.185771 [FAST_K] Save calibration result to emmc
3766 23:52:33.189404 dramc_set_vcore_voltage set vcore to 650000
3767 23:52:33.192763 Read voltage for 600, 5
3768 23:52:33.192842 Vio18 = 0
3769 23:52:33.195919 Vcore = 650000
3770 23:52:33.195993 Vdram = 0
3771 23:52:33.196053 Vddq = 0
3772 23:52:33.196109 Vmddr = 0
3773 23:52:33.202625 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3774 23:52:33.209402 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3775 23:52:33.209500 MEM_TYPE=3, freq_sel=19
3776 23:52:33.212742 sv_algorithm_assistance_LP4_1600
3777 23:52:33.215577 ============ PULL DRAM RESETB DOWN ============
3778 23:52:33.222989 ========== PULL DRAM RESETB DOWN end =========
3779 23:52:33.225552 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3780 23:52:33.229624 ===================================
3781 23:52:33.232203 LPDDR4 DRAM CONFIGURATION
3782 23:52:33.235578 ===================================
3783 23:52:33.235662 EX_ROW_EN[0] = 0x0
3784 23:52:33.239076 EX_ROW_EN[1] = 0x0
3785 23:52:33.241944 LP4Y_EN = 0x0
3786 23:52:33.242038 WORK_FSP = 0x0
3787 23:52:33.245497 WL = 0x2
3788 23:52:33.245589 RL = 0x2
3789 23:52:33.248928 BL = 0x2
3790 23:52:33.249015 RPST = 0x0
3791 23:52:33.251966 RD_PRE = 0x0
3792 23:52:33.252093 WR_PRE = 0x1
3793 23:52:33.255305 WR_PST = 0x0
3794 23:52:33.255445 DBI_WR = 0x0
3795 23:52:33.259320 DBI_RD = 0x0
3796 23:52:33.259439 OTF = 0x1
3797 23:52:33.262071 ===================================
3798 23:52:33.265516 ===================================
3799 23:52:33.268729 ANA top config
3800 23:52:33.271826 ===================================
3801 23:52:33.272016 DLL_ASYNC_EN = 0
3802 23:52:33.275335 ALL_SLAVE_EN = 1
3803 23:52:33.278376 NEW_RANK_MODE = 1
3804 23:52:33.281872 DLL_IDLE_MODE = 1
3805 23:52:33.285118 LP45_APHY_COMB_EN = 1
3806 23:52:33.285253 TX_ODT_DIS = 1
3807 23:52:33.288188 NEW_8X_MODE = 1
3808 23:52:33.291544 ===================================
3809 23:52:33.295024 ===================================
3810 23:52:33.298265 data_rate = 1200
3811 23:52:33.302126 CKR = 1
3812 23:52:33.305266 DQ_P2S_RATIO = 8
3813 23:52:33.308343 ===================================
3814 23:52:33.308544 CA_P2S_RATIO = 8
3815 23:52:33.311913 DQ_CA_OPEN = 0
3816 23:52:33.314743 DQ_SEMI_OPEN = 0
3817 23:52:33.318519 CA_SEMI_OPEN = 0
3818 23:52:33.321487 CA_FULL_RATE = 0
3819 23:52:33.324786 DQ_CKDIV4_EN = 1
3820 23:52:33.324906 CA_CKDIV4_EN = 1
3821 23:52:33.328613 CA_PREDIV_EN = 0
3822 23:52:33.331339 PH8_DLY = 0
3823 23:52:33.334792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3824 23:52:33.338190 DQ_AAMCK_DIV = 4
3825 23:52:33.341759 CA_AAMCK_DIV = 4
3826 23:52:33.341909 CA_ADMCK_DIV = 4
3827 23:52:33.345122 DQ_TRACK_CA_EN = 0
3828 23:52:33.347974 CA_PICK = 600
3829 23:52:33.351390 CA_MCKIO = 600
3830 23:52:33.354848 MCKIO_SEMI = 0
3831 23:52:33.358087 PLL_FREQ = 2288
3832 23:52:33.361432 DQ_UI_PI_RATIO = 32
3833 23:52:33.361525 CA_UI_PI_RATIO = 0
3834 23:52:33.364475 ===================================
3835 23:52:33.368233 ===================================
3836 23:52:33.371211 memory_type:LPDDR4
3837 23:52:33.374664 GP_NUM : 10
3838 23:52:33.374757 SRAM_EN : 1
3839 23:52:33.377716 MD32_EN : 0
3840 23:52:33.381075 ===================================
3841 23:52:33.384348 [ANA_INIT] >>>>>>>>>>>>>>
3842 23:52:33.387818 <<<<<< [CONFIGURE PHASE]: ANA_TX
3843 23:52:33.390965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3844 23:52:33.394779 ===================================
3845 23:52:33.394881 data_rate = 1200,PCW = 0X5800
3846 23:52:33.398008 ===================================
3847 23:52:33.404612 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3848 23:52:33.408013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3849 23:52:33.414080 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3850 23:52:33.417283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3851 23:52:33.420878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3852 23:52:33.424248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3853 23:52:33.427732 [ANA_INIT] flow start
3854 23:52:33.430697 [ANA_INIT] PLL >>>>>>>>
3855 23:52:33.430819 [ANA_INIT] PLL <<<<<<<<
3856 23:52:33.433887 [ANA_INIT] MIDPI >>>>>>>>
3857 23:52:33.437277 [ANA_INIT] MIDPI <<<<<<<<
3858 23:52:33.437442 [ANA_INIT] DLL >>>>>>>>
3859 23:52:33.440427 [ANA_INIT] flow end
3860 23:52:33.443898 ============ LP4 DIFF to SE enter ============
3861 23:52:33.450490 ============ LP4 DIFF to SE exit ============
3862 23:52:33.450671 [ANA_INIT] <<<<<<<<<<<<<
3863 23:52:33.453690 [Flow] Enable top DCM control >>>>>
3864 23:52:33.457304 [Flow] Enable top DCM control <<<<<
3865 23:52:33.460474 Enable DLL master slave shuffle
3866 23:52:33.467261 ==============================================================
3867 23:52:33.467401 Gating Mode config
3868 23:52:33.473597 ==============================================================
3869 23:52:33.477403 Config description:
3870 23:52:33.484229 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3871 23:52:33.490255 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3872 23:52:33.497392 SELPH_MODE 0: By rank 1: By Phase
3873 23:52:33.503414 ==============================================================
3874 23:52:33.503529 GAT_TRACK_EN = 1
3875 23:52:33.506751 RX_GATING_MODE = 2
3876 23:52:33.510191 RX_GATING_TRACK_MODE = 2
3877 23:52:33.513534 SELPH_MODE = 1
3878 23:52:33.516884 PICG_EARLY_EN = 1
3879 23:52:33.519959 VALID_LAT_VALUE = 1
3880 23:52:33.527079 ==============================================================
3881 23:52:33.530123 Enter into Gating configuration >>>>
3882 23:52:33.533633 Exit from Gating configuration <<<<
3883 23:52:33.536775 Enter into DVFS_PRE_config >>>>>
3884 23:52:33.546762 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3885 23:52:33.550300 Exit from DVFS_PRE_config <<<<<
3886 23:52:33.553508 Enter into PICG configuration >>>>
3887 23:52:33.556876 Exit from PICG configuration <<<<
3888 23:52:33.559761 [RX_INPUT] configuration >>>>>
3889 23:52:33.563504 [RX_INPUT] configuration <<<<<
3890 23:52:33.566276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3891 23:52:33.573570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3892 23:52:33.579859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3893 23:52:33.583462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3894 23:52:33.589892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3895 23:52:33.596618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3896 23:52:33.599891 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3897 23:52:33.603344 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3898 23:52:33.609706 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3899 23:52:33.613052 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3900 23:52:33.616379 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3901 23:52:33.622890 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3902 23:52:33.626254 ===================================
3903 23:52:33.626336 LPDDR4 DRAM CONFIGURATION
3904 23:52:33.629624 ===================================
3905 23:52:33.632896 EX_ROW_EN[0] = 0x0
3906 23:52:33.636304 EX_ROW_EN[1] = 0x0
3907 23:52:33.636424 LP4Y_EN = 0x0
3908 23:52:33.639491 WORK_FSP = 0x0
3909 23:52:33.639582 WL = 0x2
3910 23:52:33.642761 RL = 0x2
3911 23:52:33.642859 BL = 0x2
3912 23:52:33.646178 RPST = 0x0
3913 23:52:33.646285 RD_PRE = 0x0
3914 23:52:33.649475 WR_PRE = 0x1
3915 23:52:33.649582 WR_PST = 0x0
3916 23:52:33.652672 DBI_WR = 0x0
3917 23:52:33.652790 DBI_RD = 0x0
3918 23:52:33.656413 OTF = 0x1
3919 23:52:33.659231 ===================================
3920 23:52:33.663169 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3921 23:52:33.665802 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3922 23:52:33.672795 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3923 23:52:33.675863 ===================================
3924 23:52:33.676094 LPDDR4 DRAM CONFIGURATION
3925 23:52:33.679727 ===================================
3926 23:52:33.683062 EX_ROW_EN[0] = 0x10
3927 23:52:33.686323 EX_ROW_EN[1] = 0x0
3928 23:52:33.686690 LP4Y_EN = 0x0
3929 23:52:33.689367 WORK_FSP = 0x0
3930 23:52:33.689739 WL = 0x2
3931 23:52:33.693041 RL = 0x2
3932 23:52:33.693486 BL = 0x2
3933 23:52:33.696505 RPST = 0x0
3934 23:52:33.696998 RD_PRE = 0x0
3935 23:52:33.699807 WR_PRE = 0x1
3936 23:52:33.700315 WR_PST = 0x0
3937 23:52:33.702611 DBI_WR = 0x0
3938 23:52:33.703069 DBI_RD = 0x0
3939 23:52:33.706284 OTF = 0x1
3940 23:52:33.709322 ===================================
3941 23:52:33.716063 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3942 23:52:33.719620 nWR fixed to 30
3943 23:52:33.720070 [ModeRegInit_LP4] CH0 RK0
3944 23:52:33.722772 [ModeRegInit_LP4] CH0 RK1
3945 23:52:33.726024 [ModeRegInit_LP4] CH1 RK0
3946 23:52:33.729366 [ModeRegInit_LP4] CH1 RK1
3947 23:52:33.729813 match AC timing 17
3948 23:52:33.732614 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3949 23:52:33.739154 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3950 23:52:33.742201 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3951 23:52:33.748898 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3952 23:52:33.752649 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3953 23:52:33.753053 ==
3954 23:52:33.755604 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 23:52:33.758872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 23:52:33.759278 ==
3957 23:52:33.765426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 23:52:33.772193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3959 23:52:33.775327 [CA 0] Center 37 (7~67) winsize 61
3960 23:52:33.779003 [CA 1] Center 36 (6~67) winsize 62
3961 23:52:33.782364 [CA 2] Center 35 (5~65) winsize 61
3962 23:52:33.785601 [CA 3] Center 34 (4~65) winsize 62
3963 23:52:33.788906 [CA 4] Center 34 (4~65) winsize 62
3964 23:52:33.792444 [CA 5] Center 34 (4~64) winsize 61
3965 23:52:33.792886
3966 23:52:33.795428 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3967 23:52:33.795834
3968 23:52:33.798780 [CATrainingPosCal] consider 1 rank data
3969 23:52:33.802085 u2DelayCellTimex100 = 270/100 ps
3970 23:52:33.804980 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3971 23:52:33.808530 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3972 23:52:33.812226 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3973 23:52:33.815600 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3974 23:52:33.818537 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3975 23:52:33.821859 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3976 23:52:33.822263
3977 23:52:33.829253 CA PerBit enable=1, Macro0, CA PI delay=34
3978 23:52:33.829657
3979 23:52:33.831777 [CBTSetCACLKResult] CA Dly = 34
3980 23:52:33.832182 CS Dly: 5 (0~36)
3981 23:52:33.832499 ==
3982 23:52:33.835164 Dram Type= 6, Freq= 0, CH_0, rank 1
3983 23:52:33.838856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 23:52:33.839409 ==
3985 23:52:33.845130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3986 23:52:33.851628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3987 23:52:33.855352 [CA 0] Center 37 (7~67) winsize 61
3988 23:52:33.858748 [CA 1] Center 37 (7~67) winsize 61
3989 23:52:33.862085 [CA 2] Center 35 (5~65) winsize 61
3990 23:52:33.865158 [CA 3] Center 35 (5~65) winsize 61
3991 23:52:33.868411 [CA 4] Center 34 (4~65) winsize 62
3992 23:52:33.871539 [CA 5] Center 33 (3~64) winsize 62
3993 23:52:33.871942
3994 23:52:33.874758 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3995 23:52:33.875164
3996 23:52:33.878414 [CATrainingPosCal] consider 2 rank data
3997 23:52:33.881441 u2DelayCellTimex100 = 270/100 ps
3998 23:52:33.884676 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3999 23:52:33.888424 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4000 23:52:33.891779 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4001 23:52:33.894992 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4002 23:52:33.898146 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4003 23:52:33.904791 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4004 23:52:33.905213
4005 23:52:33.908369 CA PerBit enable=1, Macro0, CA PI delay=34
4006 23:52:33.908819
4007 23:52:33.911572 [CBTSetCACLKResult] CA Dly = 34
4008 23:52:33.911973 CS Dly: 5 (0~36)
4009 23:52:33.912292
4010 23:52:33.915163 ----->DramcWriteLeveling(PI) begin...
4011 23:52:33.915572 ==
4012 23:52:33.918130 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 23:52:33.924894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 23:52:33.925302 ==
4015 23:52:33.928159 Write leveling (Byte 0): 35 => 35
4016 23:52:33.928743 Write leveling (Byte 1): 31 => 31
4017 23:52:33.931339 DramcWriteLeveling(PI) end<-----
4018 23:52:33.931762
4019 23:52:33.932079 ==
4020 23:52:33.934947 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 23:52:33.941546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 23:52:33.941955 ==
4023 23:52:33.944736 [Gating] SW mode calibration
4024 23:52:33.951148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4025 23:52:33.954851 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4026 23:52:33.961012 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 23:52:33.964635 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 23:52:33.968155 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 23:52:33.974443 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4030 23:52:33.977981 0 9 16 | B1->B0 | 3030 2c2c | 0 0 | (1 1) (0 0)
4031 23:52:33.981187 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 23:52:33.984504 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 23:52:33.991244 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 23:52:33.994380 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 23:52:33.998020 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 23:52:34.004554 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 23:52:34.007999 0 10 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4038 23:52:34.011385 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
4039 23:52:34.017729 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 23:52:34.021034 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 23:52:34.024370 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 23:52:34.030939 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 23:52:34.034474 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 23:52:34.037668 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 23:52:34.044215 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 23:52:34.047479 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4047 23:52:34.050988 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:52:34.057438 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 23:52:34.060642 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 23:52:34.063934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 23:52:34.071068 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:52:34.073884 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:52:34.077343 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:52:34.083898 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:52:34.087348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:52:34.090342 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:52:34.096743 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:52:34.100278 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:52:34.103318 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:52:34.110203 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4061 23:52:34.114008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4062 23:52:34.117052 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4063 23:52:34.120338 Total UI for P1: 0, mck2ui 16
4064 23:52:34.123118 best dqsien dly found for B0: ( 0, 13, 10)
4065 23:52:34.129837 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 23:52:34.130309 Total UI for P1: 0, mck2ui 16
4067 23:52:34.136455 best dqsien dly found for B1: ( 0, 13, 18)
4068 23:52:34.140197 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4069 23:52:34.143336 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4070 23:52:34.143771
4071 23:52:34.146642 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4072 23:52:34.149659 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4073 23:52:34.153046 [Gating] SW calibration Done
4074 23:52:34.153480 ==
4075 23:52:34.156315 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 23:52:34.160133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 23:52:34.160624 ==
4078 23:52:34.163149 RX Vref Scan: 0
4079 23:52:34.163641
4080 23:52:34.164063 RX Vref 0 -> 0, step: 1
4081 23:52:34.166333
4082 23:52:34.166787 RX Delay -230 -> 252, step: 16
4083 23:52:34.173040 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4084 23:52:34.176475 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4085 23:52:34.180079 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4086 23:52:34.183200 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4087 23:52:34.189636 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4088 23:52:34.192869 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4089 23:52:34.196121 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4090 23:52:34.199100 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4091 23:52:34.205622 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4092 23:52:34.209008 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4093 23:52:34.212482 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4094 23:52:34.215461 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4095 23:52:34.222395 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4096 23:52:34.225508 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4097 23:52:34.228844 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4098 23:52:34.232150 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4099 23:52:34.232635 ==
4100 23:52:34.235691 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 23:52:34.242561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 23:52:34.243013 ==
4103 23:52:34.243369 DQS Delay:
4104 23:52:34.243701 DQS0 = 0, DQS1 = 0
4105 23:52:34.245751 DQM Delay:
4106 23:52:34.246275 DQM0 = 40, DQM1 = 31
4107 23:52:34.248746 DQ Delay:
4108 23:52:34.252231 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4109 23:52:34.255570 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4110 23:52:34.258458 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4111 23:52:34.261862 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4112 23:52:34.262296
4113 23:52:34.262674
4114 23:52:34.263019 ==
4115 23:52:34.265294 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 23:52:34.268637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 23:52:34.269088 ==
4118 23:52:34.269449
4119 23:52:34.269777
4120 23:52:34.272122 TX Vref Scan disable
4121 23:52:34.275609 == TX Byte 0 ==
4122 23:52:34.278733 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4123 23:52:34.282203 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4124 23:52:34.284973 == TX Byte 1 ==
4125 23:52:34.288875 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4126 23:52:34.291839 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4127 23:52:34.292274 ==
4128 23:52:34.295280 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 23:52:34.298059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 23:52:34.301583 ==
4131 23:52:34.302024
4132 23:52:34.302371
4133 23:52:34.302746 TX Vref Scan disable
4134 23:52:34.305406 == TX Byte 0 ==
4135 23:52:34.308774 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4136 23:52:34.312248 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4137 23:52:34.315916 == TX Byte 1 ==
4138 23:52:34.318847 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4139 23:52:34.325672 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4140 23:52:34.326119
4141 23:52:34.326473 [DATLAT]
4142 23:52:34.326803 Freq=600, CH0 RK0
4143 23:52:34.327123
4144 23:52:34.329012 DATLAT Default: 0x9
4145 23:52:34.329420 0, 0xFFFF, sum = 0
4146 23:52:34.331781 1, 0xFFFF, sum = 0
4147 23:52:34.332231 2, 0xFFFF, sum = 0
4148 23:52:34.335171 3, 0xFFFF, sum = 0
4149 23:52:34.338766 4, 0xFFFF, sum = 0
4150 23:52:34.339204 5, 0xFFFF, sum = 0
4151 23:52:34.341643 6, 0xFFFF, sum = 0
4152 23:52:34.342122 7, 0xFFFF, sum = 0
4153 23:52:34.345217 8, 0x0, sum = 1
4154 23:52:34.345298 9, 0x0, sum = 2
4155 23:52:34.345371 10, 0x0, sum = 3
4156 23:52:34.348493 11, 0x0, sum = 4
4157 23:52:34.348612 best_step = 9
4158 23:52:34.348710
4159 23:52:34.348808 ==
4160 23:52:34.351610 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 23:52:34.358303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 23:52:34.358382 ==
4163 23:52:34.358445 RX Vref Scan: 1
4164 23:52:34.358503
4165 23:52:34.361571 RX Vref 0 -> 0, step: 1
4166 23:52:34.361640
4167 23:52:34.364411 RX Delay -195 -> 252, step: 8
4168 23:52:34.364479
4169 23:52:34.368310 Set Vref, RX VrefLevel [Byte0]: 63
4170 23:52:34.371341 [Byte1]: 47
4171 23:52:34.371409
4172 23:52:34.374443 Final RX Vref Byte 0 = 63 to rank0
4173 23:52:34.378288 Final RX Vref Byte 1 = 47 to rank0
4174 23:52:34.381121 Final RX Vref Byte 0 = 63 to rank1
4175 23:52:34.384447 Final RX Vref Byte 1 = 47 to rank1==
4176 23:52:34.388066 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 23:52:34.390758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 23:52:34.394216 ==
4179 23:52:34.394294 DQS Delay:
4180 23:52:34.394356 DQS0 = 0, DQS1 = 0
4181 23:52:34.397774 DQM Delay:
4182 23:52:34.397852 DQM0 = 35, DQM1 = 29
4183 23:52:34.400967 DQ Delay:
4184 23:52:34.401044 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4185 23:52:34.404115 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4186 23:52:34.407410 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4187 23:52:34.410943 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4188 23:52:34.411022
4189 23:52:34.414158
4190 23:52:34.420845 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4191 23:52:34.424109 CH0 RK0: MR19=808, MR18=3F3D
4192 23:52:34.431321 CH0_RK0: MR19=0x808, MR18=0x3F3D, DQSOSC=397, MR23=63, INC=166, DEC=110
4193 23:52:34.431399
4194 23:52:34.434057 ----->DramcWriteLeveling(PI) begin...
4195 23:52:34.434136 ==
4196 23:52:34.437355 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 23:52:34.440893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 23:52:34.440972 ==
4199 23:52:34.443657 Write leveling (Byte 0): 32 => 32
4200 23:52:34.447227 Write leveling (Byte 1): 32 => 32
4201 23:52:34.450440 DramcWriteLeveling(PI) end<-----
4202 23:52:34.450526
4203 23:52:34.450588 ==
4204 23:52:34.453593 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 23:52:34.457335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 23:52:34.457417 ==
4207 23:52:34.460805 [Gating] SW mode calibration
4208 23:52:34.467261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4209 23:52:34.473918 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4210 23:52:34.477305 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 23:52:34.480216 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 23:52:34.486761 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 23:52:34.490261 0 9 12 | B1->B0 | 3333 3030 | 1 0 | (0 0) (0 1)
4214 23:52:34.493568 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4215 23:52:34.500347 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 23:52:34.503868 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 23:52:34.507122 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 23:52:34.513790 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 23:52:34.516951 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 23:52:34.520456 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4221 23:52:34.527161 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4222 23:52:34.530416 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
4223 23:52:34.534290 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 23:52:34.539828 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 23:52:34.543210 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 23:52:34.547000 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 23:52:34.553009 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 23:52:34.556401 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 23:52:34.559855 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4230 23:52:34.566684 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4231 23:52:34.569662 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 23:52:34.572962 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 23:52:34.579633 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 23:52:34.582937 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 23:52:34.586327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:52:34.592812 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:52:34.596286 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:52:34.599292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:52:34.606155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:52:34.609736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:52:34.612862 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:52:34.619612 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:52:34.623104 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:52:34.626415 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:52:34.632903 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4246 23:52:34.636488 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:52:34.639426 Total UI for P1: 0, mck2ui 16
4248 23:52:34.642612 best dqsien dly found for B0: ( 0, 13, 12)
4249 23:52:34.646063 Total UI for P1: 0, mck2ui 16
4250 23:52:34.649184 best dqsien dly found for B1: ( 0, 13, 14)
4251 23:52:34.652376 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4252 23:52:34.655935 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4253 23:52:34.656015
4254 23:52:34.659108 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4255 23:52:34.662285 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4256 23:52:34.665625 [Gating] SW calibration Done
4257 23:52:34.665725 ==
4258 23:52:34.669460 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 23:52:34.672424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 23:52:34.672543 ==
4261 23:52:34.675650 RX Vref Scan: 0
4262 23:52:34.675755
4263 23:52:34.679262 RX Vref 0 -> 0, step: 1
4264 23:52:34.679338
4265 23:52:34.682304 RX Delay -230 -> 252, step: 16
4266 23:52:34.685583 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4267 23:52:34.688900 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4268 23:52:34.692176 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4269 23:52:34.698955 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4270 23:52:34.701999 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4271 23:52:34.705706 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4272 23:52:34.708998 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4273 23:52:34.712390 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4274 23:52:34.718982 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4275 23:52:34.722078 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4276 23:52:34.725596 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4277 23:52:34.728709 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4278 23:52:34.735198 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4279 23:52:34.738494 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4280 23:52:34.741952 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4281 23:52:34.745127 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4282 23:52:34.745216 ==
4283 23:52:34.748387 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 23:52:34.754801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 23:52:34.754905 ==
4286 23:52:34.755042 DQS Delay:
4287 23:52:34.758755 DQS0 = 0, DQS1 = 0
4288 23:52:34.758851 DQM Delay:
4289 23:52:34.758939 DQM0 = 40, DQM1 = 31
4290 23:52:34.761608 DQ Delay:
4291 23:52:34.765144 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4292 23:52:34.768310 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4293 23:52:34.771878 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4294 23:52:34.775245 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4295 23:52:34.775327
4296 23:52:34.775390
4297 23:52:34.775465 ==
4298 23:52:34.778240 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 23:52:34.782012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 23:52:34.782110 ==
4301 23:52:34.782205
4302 23:52:34.782278
4303 23:52:34.785004 TX Vref Scan disable
4304 23:52:34.785084 == TX Byte 0 ==
4305 23:52:34.791732 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4306 23:52:34.794908 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4307 23:52:34.798150 == TX Byte 1 ==
4308 23:52:34.801856 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4309 23:52:34.804910 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4310 23:52:34.804990 ==
4311 23:52:34.808195 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 23:52:34.811880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 23:52:34.811962 ==
4314 23:52:34.812025
4315 23:52:34.814691
4316 23:52:34.814788 TX Vref Scan disable
4317 23:52:34.818260 == TX Byte 0 ==
4318 23:52:34.821668 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4319 23:52:34.828445 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4320 23:52:34.828528 == TX Byte 1 ==
4321 23:52:34.831743 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4322 23:52:34.838382 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4323 23:52:34.838463
4324 23:52:34.838526 [DATLAT]
4325 23:52:34.838605 Freq=600, CH0 RK1
4326 23:52:34.838675
4327 23:52:34.841945 DATLAT Default: 0x9
4328 23:52:34.842025 0, 0xFFFF, sum = 0
4329 23:52:34.844982 1, 0xFFFF, sum = 0
4330 23:52:34.848257 2, 0xFFFF, sum = 0
4331 23:52:34.848347 3, 0xFFFF, sum = 0
4332 23:52:34.851287 4, 0xFFFF, sum = 0
4333 23:52:34.851469 5, 0xFFFF, sum = 0
4334 23:52:34.854906 6, 0xFFFF, sum = 0
4335 23:52:34.854990 7, 0xFFFF, sum = 0
4336 23:52:34.858134 8, 0x0, sum = 1
4337 23:52:34.858210 9, 0x0, sum = 2
4338 23:52:34.858278 10, 0x0, sum = 3
4339 23:52:34.861335 11, 0x0, sum = 4
4340 23:52:34.861407 best_step = 9
4341 23:52:34.861466
4342 23:52:34.861523 ==
4343 23:52:34.864529 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 23:52:34.871106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 23:52:34.871189 ==
4346 23:52:34.871252 RX Vref Scan: 0
4347 23:52:34.871310
4348 23:52:34.874847 RX Vref 0 -> 0, step: 1
4349 23:52:34.874920
4350 23:52:34.877900 RX Delay -195 -> 252, step: 8
4351 23:52:34.880960 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4352 23:52:34.887676 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4353 23:52:34.891149 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4354 23:52:34.894603 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4355 23:52:34.897695 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4356 23:52:34.904456 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4357 23:52:34.907394 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4358 23:52:34.911051 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4359 23:52:34.914246 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4360 23:52:34.917543 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4361 23:52:34.924103 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4362 23:52:34.927507 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4363 23:52:34.930579 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4364 23:52:34.934225 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4365 23:52:34.941105 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4366 23:52:34.944159 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4367 23:52:34.944245 ==
4368 23:52:34.947555 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 23:52:34.950708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 23:52:34.950801 ==
4371 23:52:34.954123 DQS Delay:
4372 23:52:34.954205 DQS0 = 0, DQS1 = 0
4373 23:52:34.957726 DQM Delay:
4374 23:52:34.957807 DQM0 = 33, DQM1 = 27
4375 23:52:34.957871 DQ Delay:
4376 23:52:34.960851 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4377 23:52:34.964173 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4378 23:52:34.967423 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4379 23:52:34.970382 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4380 23:52:34.970463
4381 23:52:34.970527
4382 23:52:34.980539 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4383 23:52:34.983849 CH0 RK1: MR19=808, MR18=6C3A
4384 23:52:34.990472 CH0_RK1: MR19=0x808, MR18=0x6C3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4385 23:52:34.990561 [RxdqsGatingPostProcess] freq 600
4386 23:52:34.996792 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4387 23:52:35.000358 Pre-setting of DQS Precalculation
4388 23:52:35.003526 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4389 23:52:35.006838 ==
4390 23:52:35.010587 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 23:52:35.013452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 23:52:35.013534 ==
4393 23:52:35.017377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 23:52:35.023672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4395 23:52:35.027652 [CA 0] Center 35 (5~66) winsize 62
4396 23:52:35.030468 [CA 1] Center 35 (5~66) winsize 62
4397 23:52:35.033751 [CA 2] Center 34 (4~65) winsize 62
4398 23:52:35.037529 [CA 3] Center 34 (4~65) winsize 62
4399 23:52:35.040443 [CA 4] Center 34 (4~65) winsize 62
4400 23:52:35.044160 [CA 5] Center 34 (4~64) winsize 61
4401 23:52:35.044241
4402 23:52:35.047218 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4403 23:52:35.047298
4404 23:52:35.050742 [CATrainingPosCal] consider 1 rank data
4405 23:52:35.053746 u2DelayCellTimex100 = 270/100 ps
4406 23:52:35.057240 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4407 23:52:35.060434 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4408 23:52:35.067087 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4409 23:52:35.070458 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4410 23:52:35.073713 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4411 23:52:35.077034 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4412 23:52:35.077134
4413 23:52:35.080637 CA PerBit enable=1, Macro0, CA PI delay=34
4414 23:52:35.080718
4415 23:52:35.083551 [CBTSetCACLKResult] CA Dly = 34
4416 23:52:35.083622 CS Dly: 4 (0~35)
4417 23:52:35.086811 ==
4418 23:52:35.090264 Dram Type= 6, Freq= 0, CH_1, rank 1
4419 23:52:35.093472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 23:52:35.093553 ==
4421 23:52:35.096862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 23:52:35.103477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4423 23:52:35.106986 [CA 0] Center 36 (6~66) winsize 61
4424 23:52:35.110579 [CA 1] Center 36 (6~66) winsize 61
4425 23:52:35.113854 [CA 2] Center 34 (4~65) winsize 62
4426 23:52:35.117175 [CA 3] Center 34 (3~65) winsize 63
4427 23:52:35.120764 [CA 4] Center 34 (4~65) winsize 62
4428 23:52:35.123832 [CA 5] Center 34 (3~65) winsize 63
4429 23:52:35.123912
4430 23:52:35.127217 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4431 23:52:35.127301
4432 23:52:35.130116 [CATrainingPosCal] consider 2 rank data
4433 23:52:35.134063 u2DelayCellTimex100 = 270/100 ps
4434 23:52:35.137296 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4435 23:52:35.143769 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4436 23:52:35.146855 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4437 23:52:35.150491 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4438 23:52:35.153746 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4439 23:52:35.156733 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4440 23:52:35.156813
4441 23:52:35.160082 CA PerBit enable=1, Macro0, CA PI delay=34
4442 23:52:35.160164
4443 23:52:35.164035 [CBTSetCACLKResult] CA Dly = 34
4444 23:52:35.164117 CS Dly: 5 (0~37)
4445 23:52:35.166848
4446 23:52:35.170023 ----->DramcWriteLeveling(PI) begin...
4447 23:52:35.170104 ==
4448 23:52:35.173298 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 23:52:35.176805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 23:52:35.176924 ==
4451 23:52:35.179995 Write leveling (Byte 0): 28 => 28
4452 23:52:35.183458 Write leveling (Byte 1): 29 => 29
4453 23:52:35.186999 DramcWriteLeveling(PI) end<-----
4454 23:52:35.187081
4455 23:52:35.187145 ==
4456 23:52:35.190535 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 23:52:35.193446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 23:52:35.193518 ==
4459 23:52:35.196713 [Gating] SW mode calibration
4460 23:52:35.203652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 23:52:35.210120 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4462 23:52:35.212985 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 23:52:35.216572 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 23:52:35.222929 0 9 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
4465 23:52:35.226319 0 9 12 | B1->B0 | 3232 3131 | 0 1 | (0 0) (1 1)
4466 23:52:35.229626 0 9 16 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
4467 23:52:35.236258 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 23:52:35.239610 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 23:52:35.242925 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 23:52:35.249636 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 23:52:35.252897 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 23:52:35.256188 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 23:52:35.262929 0 10 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
4474 23:52:35.266015 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4475 23:52:35.269634 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 23:52:35.276107 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 23:52:35.279615 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 23:52:35.282764 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 23:52:35.289655 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 23:52:35.292845 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 23:52:35.296076 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4482 23:52:35.302587 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:52:35.305865 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 23:52:35.309432 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 23:52:35.312496 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:52:35.319323 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:52:35.322403 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:52:35.326314 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:52:35.332761 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:52:35.335957 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:52:35.339198 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:52:35.345593 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:52:35.348797 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:52:35.352235 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:52:35.359341 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:52:35.362153 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:52:35.365632 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4498 23:52:35.372550 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 23:52:35.372684 Total UI for P1: 0, mck2ui 16
4500 23:52:35.378788 best dqsien dly found for B0: ( 0, 13, 12)
4501 23:52:35.378890 Total UI for P1: 0, mck2ui 16
4502 23:52:35.385355 best dqsien dly found for B1: ( 0, 13, 14)
4503 23:52:35.388792 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4504 23:52:35.392172 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4505 23:52:35.392267
4506 23:52:35.395276 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4507 23:52:35.398802 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4508 23:52:35.402328 [Gating] SW calibration Done
4509 23:52:35.402410 ==
4510 23:52:35.405449 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 23:52:35.408991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 23:52:35.409069 ==
4513 23:52:35.412038 RX Vref Scan: 0
4514 23:52:35.412116
4515 23:52:35.412196 RX Vref 0 -> 0, step: 1
4516 23:52:35.412272
4517 23:52:35.415551 RX Delay -230 -> 252, step: 16
4518 23:52:35.422040 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4519 23:52:35.425226 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4520 23:52:35.428686 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4521 23:52:35.431976 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4522 23:52:35.435282 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4523 23:52:35.442195 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4524 23:52:35.445080 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4525 23:52:35.448719 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4526 23:52:35.451789 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4527 23:52:35.458481 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4528 23:52:35.461515 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4529 23:52:35.464930 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4530 23:52:35.468682 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4531 23:52:35.475122 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4532 23:52:35.478082 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4533 23:52:35.481921 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4534 23:52:35.481998 ==
4535 23:52:35.485264 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 23:52:35.488543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 23:52:35.488665 ==
4538 23:52:35.491432 DQS Delay:
4539 23:52:35.491506 DQS0 = 0, DQS1 = 0
4540 23:52:35.495085 DQM Delay:
4541 23:52:35.495164 DQM0 = 38, DQM1 = 30
4542 23:52:35.495234 DQ Delay:
4543 23:52:35.498256 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4544 23:52:35.501440 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4545 23:52:35.505073 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4546 23:52:35.508128 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4547 23:52:35.508199
4548 23:52:35.508258
4549 23:52:35.511600 ==
4550 23:52:35.514993 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 23:52:35.518264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 23:52:35.518340 ==
4553 23:52:35.518403
4554 23:52:35.518461
4555 23:52:35.521196 TX Vref Scan disable
4556 23:52:35.521266 == TX Byte 0 ==
4557 23:52:35.528123 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4558 23:52:35.531623 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4559 23:52:35.531706 == TX Byte 1 ==
4560 23:52:35.538299 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 23:52:35.541363 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 23:52:35.541447 ==
4563 23:52:35.544564 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 23:52:35.547569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 23:52:35.547642 ==
4566 23:52:35.547703
4567 23:52:35.547762
4568 23:52:35.551259 TX Vref Scan disable
4569 23:52:35.554470 == TX Byte 0 ==
4570 23:52:35.557974 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 23:52:35.561550 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 23:52:35.564419 == TX Byte 1 ==
4573 23:52:35.567701 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 23:52:35.570870 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 23:52:35.570945
4576 23:52:35.574117 [DATLAT]
4577 23:52:35.574187 Freq=600, CH1 RK0
4578 23:52:35.574247
4579 23:52:35.577799 DATLAT Default: 0x9
4580 23:52:35.577869 0, 0xFFFF, sum = 0
4581 23:52:35.581476 1, 0xFFFF, sum = 0
4582 23:52:35.581551 2, 0xFFFF, sum = 0
4583 23:52:35.584024 3, 0xFFFF, sum = 0
4584 23:52:35.584101 4, 0xFFFF, sum = 0
4585 23:52:35.587809 5, 0xFFFF, sum = 0
4586 23:52:35.591347 6, 0xFFFF, sum = 0
4587 23:52:35.591419 7, 0xFFFF, sum = 0
4588 23:52:35.591480 8, 0x0, sum = 1
4589 23:52:35.594044 9, 0x0, sum = 2
4590 23:52:35.594114 10, 0x0, sum = 3
4591 23:52:35.597277 11, 0x0, sum = 4
4592 23:52:35.597347 best_step = 9
4593 23:52:35.597406
4594 23:52:35.597463 ==
4595 23:52:35.600571 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 23:52:35.607492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 23:52:35.607614 ==
4598 23:52:35.607681 RX Vref Scan: 1
4599 23:52:35.607739
4600 23:52:35.610710 RX Vref 0 -> 0, step: 1
4601 23:52:35.610779
4602 23:52:35.613831 RX Delay -195 -> 252, step: 8
4603 23:52:35.613902
4604 23:52:35.617276 Set Vref, RX VrefLevel [Byte0]: 58
4605 23:52:35.620744 [Byte1]: 52
4606 23:52:35.620817
4607 23:52:35.623540 Final RX Vref Byte 0 = 58 to rank0
4608 23:52:35.626845 Final RX Vref Byte 1 = 52 to rank0
4609 23:52:35.630873 Final RX Vref Byte 0 = 58 to rank1
4610 23:52:35.633486 Final RX Vref Byte 1 = 52 to rank1==
4611 23:52:35.636835 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 23:52:35.639970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 23:52:35.640052 ==
4614 23:52:35.643550 DQS Delay:
4615 23:52:35.643641 DQS0 = 0, DQS1 = 0
4616 23:52:35.646639 DQM Delay:
4617 23:52:35.646715 DQM0 = 38, DQM1 = 27
4618 23:52:35.646776 DQ Delay:
4619 23:52:35.649908 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4620 23:52:35.653870 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4621 23:52:35.657184 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4622 23:52:35.660226 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4623 23:52:35.660309
4624 23:52:35.660371
4625 23:52:35.669880 [DQSOSCAuto] RK0, (LSB)MR18= 0x2532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4626 23:52:35.673340 CH1 RK0: MR19=808, MR18=2532
4627 23:52:35.680204 CH1_RK0: MR19=0x808, MR18=0x2532, DQSOSC=400, MR23=63, INC=163, DEC=109
4628 23:52:35.680286
4629 23:52:35.682977 ----->DramcWriteLeveling(PI) begin...
4630 23:52:35.683056 ==
4631 23:52:35.686700 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 23:52:35.690087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 23:52:35.690192 ==
4634 23:52:35.693499 Write leveling (Byte 0): 31 => 31
4635 23:52:35.696431 Write leveling (Byte 1): 31 => 31
4636 23:52:35.699911 DramcWriteLeveling(PI) end<-----
4637 23:52:35.699983
4638 23:52:35.700049 ==
4639 23:52:35.703155 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 23:52:35.706709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 23:52:35.706783 ==
4642 23:52:35.709607 [Gating] SW mode calibration
4643 23:52:35.716001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4644 23:52:35.722713 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4645 23:52:35.726197 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 23:52:35.729349 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 23:52:35.736248 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4648 23:52:35.739536 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 1)
4649 23:52:35.742585 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 23:52:35.749244 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 23:52:35.752292 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 23:52:35.755518 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 23:52:35.762415 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 23:52:35.765708 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 23:52:35.768847 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4656 23:52:35.775331 0 10 12 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
4657 23:52:35.778879 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 23:52:35.782228 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 23:52:35.788743 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 23:52:35.792137 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 23:52:35.795252 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 23:52:35.801784 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 23:52:35.805226 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 23:52:35.808538 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:52:35.815000 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 23:52:35.818938 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 23:52:35.821487 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 23:52:35.828552 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 23:52:35.831742 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 23:52:35.834807 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 23:52:35.841609 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:52:35.844595 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:52:35.848423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:52:35.854872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:52:35.857922 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:52:35.861269 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:52:35.867927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:52:35.871149 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:52:35.874727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:52:35.881452 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4681 23:52:35.884476 Total UI for P1: 0, mck2ui 16
4682 23:52:35.887763 best dqsien dly found for B0: ( 0, 13, 10)
4683 23:52:35.891200 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4684 23:52:35.894462 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 23:52:35.897644 Total UI for P1: 0, mck2ui 16
4686 23:52:35.900869 best dqsien dly found for B1: ( 0, 13, 14)
4687 23:52:35.904373 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4688 23:52:35.907896 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4689 23:52:35.911310
4690 23:52:35.914619 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4691 23:52:35.917913 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4692 23:52:35.921265 [Gating] SW calibration Done
4693 23:52:35.921360 ==
4694 23:52:35.924409 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 23:52:35.927724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 23:52:35.927816 ==
4697 23:52:35.927878 RX Vref Scan: 0
4698 23:52:35.930747
4699 23:52:35.930825 RX Vref 0 -> 0, step: 1
4700 23:52:35.930885
4701 23:52:35.934099 RX Delay -230 -> 252, step: 16
4702 23:52:35.937388 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4703 23:52:35.944007 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4704 23:52:35.947112 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4705 23:52:35.950325 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4706 23:52:35.953665 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4707 23:52:35.957326 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4708 23:52:35.964040 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4709 23:52:35.966924 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4710 23:52:35.970154 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4711 23:52:35.973582 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4712 23:52:35.980225 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4713 23:52:35.983305 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4714 23:52:35.986701 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4715 23:52:35.990550 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4716 23:52:35.996956 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4717 23:52:36.000457 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4718 23:52:36.000540 ==
4719 23:52:36.003428 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 23:52:36.006704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 23:52:36.006806 ==
4722 23:52:36.009934 DQS Delay:
4723 23:52:36.010013 DQS0 = 0, DQS1 = 0
4724 23:52:36.013301 DQM Delay:
4725 23:52:36.013376 DQM0 = 36, DQM1 = 29
4726 23:52:36.013447 DQ Delay:
4727 23:52:36.016475 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4728 23:52:36.019858 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4729 23:52:36.023025 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4730 23:52:36.026849 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4731 23:52:36.026928
4732 23:52:36.026991
4733 23:52:36.027083 ==
4734 23:52:36.030030 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 23:52:36.036455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 23:52:36.036541 ==
4737 23:52:36.036623
4738 23:52:36.036693
4739 23:52:36.039811 TX Vref Scan disable
4740 23:52:36.039887 == TX Byte 0 ==
4741 23:52:36.043312 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4742 23:52:36.049716 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4743 23:52:36.049808 == TX Byte 1 ==
4744 23:52:36.052555 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4745 23:52:36.059430 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4746 23:52:36.059518 ==
4747 23:52:36.062559 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 23:52:36.065932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 23:52:36.066007 ==
4750 23:52:36.066069
4751 23:52:36.066127
4752 23:52:36.069594 TX Vref Scan disable
4753 23:52:36.072533 == TX Byte 0 ==
4754 23:52:36.075841 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4755 23:52:36.079349 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4756 23:52:36.082776 == TX Byte 1 ==
4757 23:52:36.085838 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4758 23:52:36.088979 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4759 23:52:36.089063
4760 23:52:36.092819 [DATLAT]
4761 23:52:36.092899 Freq=600, CH1 RK1
4762 23:52:36.092965
4763 23:52:36.096313 DATLAT Default: 0x9
4764 23:52:36.096388 0, 0xFFFF, sum = 0
4765 23:52:36.099519 1, 0xFFFF, sum = 0
4766 23:52:36.099597 2, 0xFFFF, sum = 0
4767 23:52:36.102315 3, 0xFFFF, sum = 0
4768 23:52:36.102390 4, 0xFFFF, sum = 0
4769 23:52:36.105541 5, 0xFFFF, sum = 0
4770 23:52:36.105645 6, 0xFFFF, sum = 0
4771 23:52:36.109304 7, 0xFFFF, sum = 0
4772 23:52:36.109386 8, 0x0, sum = 1
4773 23:52:36.112756 9, 0x0, sum = 2
4774 23:52:36.112835 10, 0x0, sum = 3
4775 23:52:36.116086 11, 0x0, sum = 4
4776 23:52:36.116191 best_step = 9
4777 23:52:36.116264
4778 23:52:36.116324 ==
4779 23:52:36.118955 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 23:52:36.122300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 23:52:36.125600 ==
4782 23:52:36.125683 RX Vref Scan: 0
4783 23:52:36.125747
4784 23:52:36.129221 RX Vref 0 -> 0, step: 1
4785 23:52:36.129299
4786 23:52:36.132383 RX Delay -195 -> 252, step: 8
4787 23:52:36.135442 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4788 23:52:36.142335 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4789 23:52:36.145465 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4790 23:52:36.148663 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4791 23:52:36.152044 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4792 23:52:36.155135 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4793 23:52:36.161733 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4794 23:52:36.165428 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4795 23:52:36.168377 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4796 23:52:36.171407 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4797 23:52:36.178390 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4798 23:52:36.181776 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4799 23:52:36.185128 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4800 23:52:36.188743 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4801 23:52:36.194967 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4802 23:52:36.198210 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4803 23:52:36.198301 ==
4804 23:52:36.201358 Dram Type= 6, Freq= 0, CH_1, rank 1
4805 23:52:36.204737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4806 23:52:36.204822 ==
4807 23:52:36.208121 DQS Delay:
4808 23:52:36.208231 DQS0 = 0, DQS1 = 0
4809 23:52:36.208325 DQM Delay:
4810 23:52:36.211536 DQM0 = 35, DQM1 = 29
4811 23:52:36.211619 DQ Delay:
4812 23:52:36.214768 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4813 23:52:36.218048 DQ4 =32, DQ5 =44, DQ6 =44, DQ7 =36
4814 23:52:36.221775 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =24
4815 23:52:36.224745 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4816 23:52:36.224831
4817 23:52:36.224896
4818 23:52:36.234298 [DQSOSCAuto] RK1, (LSB)MR18= 0x3959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4819 23:52:36.237575 CH1 RK1: MR19=808, MR18=3959
4820 23:52:36.240771 CH1_RK1: MR19=0x808, MR18=0x3959, DQSOSC=393, MR23=63, INC=169, DEC=113
4821 23:52:36.244496 [RxdqsGatingPostProcess] freq 600
4822 23:52:36.251117 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4823 23:52:36.253968 Pre-setting of DQS Precalculation
4824 23:52:36.257928 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4825 23:52:36.267613 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4826 23:52:36.273868 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4827 23:52:36.273961
4828 23:52:36.274033
4829 23:52:36.277505 [Calibration Summary] 1200 Mbps
4830 23:52:36.277582 CH 0, Rank 0
4831 23:52:36.280937 SW Impedance : PASS
4832 23:52:36.281014 DUTY Scan : NO K
4833 23:52:36.284060 ZQ Calibration : PASS
4834 23:52:36.287506 Jitter Meter : NO K
4835 23:52:36.287585 CBT Training : PASS
4836 23:52:36.290817 Write leveling : PASS
4837 23:52:36.293909 RX DQS gating : PASS
4838 23:52:36.293986 RX DQ/DQS(RDDQC) : PASS
4839 23:52:36.297179 TX DQ/DQS : PASS
4840 23:52:36.301070 RX DATLAT : PASS
4841 23:52:36.301143 RX DQ/DQS(Engine): PASS
4842 23:52:36.303751 TX OE : NO K
4843 23:52:36.303819 All Pass.
4844 23:52:36.303883
4845 23:52:36.307329 CH 0, Rank 1
4846 23:52:36.307396 SW Impedance : PASS
4847 23:52:36.311105 DUTY Scan : NO K
4848 23:52:36.311188 ZQ Calibration : PASS
4849 23:52:36.314111 Jitter Meter : NO K
4850 23:52:36.317666 CBT Training : PASS
4851 23:52:36.317752 Write leveling : PASS
4852 23:52:36.320925 RX DQS gating : PASS
4853 23:52:36.324164 RX DQ/DQS(RDDQC) : PASS
4854 23:52:36.324267 TX DQ/DQS : PASS
4855 23:52:36.327504 RX DATLAT : PASS
4856 23:52:36.330709 RX DQ/DQS(Engine): PASS
4857 23:52:36.330793 TX OE : NO K
4858 23:52:36.333940 All Pass.
4859 23:52:36.334027
4860 23:52:36.334092 CH 1, Rank 0
4861 23:52:36.337567 SW Impedance : PASS
4862 23:52:36.337649 DUTY Scan : NO K
4863 23:52:36.340540 ZQ Calibration : PASS
4864 23:52:36.344190 Jitter Meter : NO K
4865 23:52:36.344262 CBT Training : PASS
4866 23:52:36.347413 Write leveling : PASS
4867 23:52:36.350338 RX DQS gating : PASS
4868 23:52:36.350422 RX DQ/DQS(RDDQC) : PASS
4869 23:52:36.353934 TX DQ/DQS : PASS
4870 23:52:36.356876 RX DATLAT : PASS
4871 23:52:36.356959 RX DQ/DQS(Engine): PASS
4872 23:52:36.360515 TX OE : NO K
4873 23:52:36.360617 All Pass.
4874 23:52:36.360683
4875 23:52:36.363985 CH 1, Rank 1
4876 23:52:36.364067 SW Impedance : PASS
4877 23:52:36.366957 DUTY Scan : NO K
4878 23:52:36.370188 ZQ Calibration : PASS
4879 23:52:36.370296 Jitter Meter : NO K
4880 23:52:36.373324 CBT Training : PASS
4881 23:52:36.373399 Write leveling : PASS
4882 23:52:36.376903 RX DQS gating : PASS
4883 23:52:36.380249 RX DQ/DQS(RDDQC) : PASS
4884 23:52:36.380349 TX DQ/DQS : PASS
4885 23:52:36.383123 RX DATLAT : PASS
4886 23:52:36.386473 RX DQ/DQS(Engine): PASS
4887 23:52:36.386583 TX OE : NO K
4888 23:52:36.390114 All Pass.
4889 23:52:36.390214
4890 23:52:36.390307 DramC Write-DBI off
4891 23:52:36.393307 PER_BANK_REFRESH: Hybrid Mode
4892 23:52:36.396632 TX_TRACKING: ON
4893 23:52:36.403005 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4894 23:52:36.406462 [FAST_K] Save calibration result to emmc
4895 23:52:36.410269 dramc_set_vcore_voltage set vcore to 662500
4896 23:52:36.413422 Read voltage for 933, 3
4897 23:52:36.413502 Vio18 = 0
4898 23:52:36.416338 Vcore = 662500
4899 23:52:36.416442 Vdram = 0
4900 23:52:36.416533 Vddq = 0
4901 23:52:36.419623 Vmddr = 0
4902 23:52:36.423140 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4903 23:52:36.429783 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4904 23:52:36.429879 MEM_TYPE=3, freq_sel=17
4905 23:52:36.433087 sv_algorithm_assistance_LP4_1600
4906 23:52:36.439757 ============ PULL DRAM RESETB DOWN ============
4907 23:52:36.442970 ========== PULL DRAM RESETB DOWN end =========
4908 23:52:36.446307 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4909 23:52:36.449918 ===================================
4910 23:52:36.452946 LPDDR4 DRAM CONFIGURATION
4911 23:52:36.456324 ===================================
4912 23:52:36.459440 EX_ROW_EN[0] = 0x0
4913 23:52:36.459592 EX_ROW_EN[1] = 0x0
4914 23:52:36.462805 LP4Y_EN = 0x0
4915 23:52:36.462900 WORK_FSP = 0x0
4916 23:52:36.466409 WL = 0x3
4917 23:52:36.466540 RL = 0x3
4918 23:52:36.469572 BL = 0x2
4919 23:52:36.469683 RPST = 0x0
4920 23:52:36.473043 RD_PRE = 0x0
4921 23:52:36.473160 WR_PRE = 0x1
4922 23:52:36.476201 WR_PST = 0x0
4923 23:52:36.476352 DBI_WR = 0x0
4924 23:52:36.479332 DBI_RD = 0x0
4925 23:52:36.479442 OTF = 0x1
4926 23:52:36.482480 ===================================
4927 23:52:36.485999 ===================================
4928 23:52:36.489195 ANA top config
4929 23:52:36.492492 ===================================
4930 23:52:36.495980 DLL_ASYNC_EN = 0
4931 23:52:36.496061 ALL_SLAVE_EN = 1
4932 23:52:36.499232 NEW_RANK_MODE = 1
4933 23:52:36.502587 DLL_IDLE_MODE = 1
4934 23:52:36.506264 LP45_APHY_COMB_EN = 1
4935 23:52:36.506373 TX_ODT_DIS = 1
4936 23:52:36.509449 NEW_8X_MODE = 1
4937 23:52:36.512571 ===================================
4938 23:52:36.516052 ===================================
4939 23:52:36.519425 data_rate = 1866
4940 23:52:36.522826 CKR = 1
4941 23:52:36.526277 DQ_P2S_RATIO = 8
4942 23:52:36.529163 ===================================
4943 23:52:36.532742 CA_P2S_RATIO = 8
4944 23:52:36.532824 DQ_CA_OPEN = 0
4945 23:52:36.535679 DQ_SEMI_OPEN = 0
4946 23:52:36.538994 CA_SEMI_OPEN = 0
4947 23:52:36.542261 CA_FULL_RATE = 0
4948 23:52:36.546033 DQ_CKDIV4_EN = 1
4949 23:52:36.549272 CA_CKDIV4_EN = 1
4950 23:52:36.549354 CA_PREDIV_EN = 0
4951 23:52:36.552567 PH8_DLY = 0
4952 23:52:36.555820 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4953 23:52:36.559019 DQ_AAMCK_DIV = 4
4954 23:52:36.562191 CA_AAMCK_DIV = 4
4955 23:52:36.566184 CA_ADMCK_DIV = 4
4956 23:52:36.566266 DQ_TRACK_CA_EN = 0
4957 23:52:36.568940 CA_PICK = 933
4958 23:52:36.572457 CA_MCKIO = 933
4959 23:52:36.576104 MCKIO_SEMI = 0
4960 23:52:36.579081 PLL_FREQ = 3732
4961 23:52:36.582521 DQ_UI_PI_RATIO = 32
4962 23:52:36.585656 CA_UI_PI_RATIO = 0
4963 23:52:36.588790 ===================================
4964 23:52:36.592172 ===================================
4965 23:52:36.592255 memory_type:LPDDR4
4966 23:52:36.595499 GP_NUM : 10
4967 23:52:36.598880 SRAM_EN : 1
4968 23:52:36.598961 MD32_EN : 0
4969 23:52:36.602472 ===================================
4970 23:52:36.605405 [ANA_INIT] >>>>>>>>>>>>>>
4971 23:52:36.609091 <<<<<< [CONFIGURE PHASE]: ANA_TX
4972 23:52:36.612247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4973 23:52:36.615165 ===================================
4974 23:52:36.618573 data_rate = 1866,PCW = 0X8f00
4975 23:52:36.621992 ===================================
4976 23:52:36.625153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4977 23:52:36.628699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4978 23:52:36.635267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4979 23:52:36.638749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4980 23:52:36.641717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4981 23:52:36.644890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4982 23:52:36.648308 [ANA_INIT] flow start
4983 23:52:36.651680 [ANA_INIT] PLL >>>>>>>>
4984 23:52:36.651813 [ANA_INIT] PLL <<<<<<<<
4985 23:52:36.654911 [ANA_INIT] MIDPI >>>>>>>>
4986 23:52:36.658300 [ANA_INIT] MIDPI <<<<<<<<
4987 23:52:36.661542 [ANA_INIT] DLL >>>>>>>>
4988 23:52:36.661648 [ANA_INIT] flow end
4989 23:52:36.664858 ============ LP4 DIFF to SE enter ============
4990 23:52:36.671490 ============ LP4 DIFF to SE exit ============
4991 23:52:36.671593 [ANA_INIT] <<<<<<<<<<<<<
4992 23:52:36.675170 [Flow] Enable top DCM control >>>>>
4993 23:52:36.678690 [Flow] Enable top DCM control <<<<<
4994 23:52:36.681812 Enable DLL master slave shuffle
4995 23:52:36.688332 ==============================================================
4996 23:52:36.688429 Gating Mode config
4997 23:52:36.694882 ==============================================================
4998 23:52:36.698216 Config description:
4999 23:52:36.707852 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5000 23:52:36.711409 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5001 23:52:36.717981 SELPH_MODE 0: By rank 1: By Phase
5002 23:52:36.725032 ==============================================================
5003 23:52:36.728445 GAT_TRACK_EN = 1
5004 23:52:36.728545 RX_GATING_MODE = 2
5005 23:52:36.731173 RX_GATING_TRACK_MODE = 2
5006 23:52:36.734578 SELPH_MODE = 1
5007 23:52:36.738112 PICG_EARLY_EN = 1
5008 23:52:36.741226 VALID_LAT_VALUE = 1
5009 23:52:36.747974 ==============================================================
5010 23:52:36.751304 Enter into Gating configuration >>>>
5011 23:52:36.754816 Exit from Gating configuration <<<<
5012 23:52:36.757775 Enter into DVFS_PRE_config >>>>>
5013 23:52:36.768165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5014 23:52:36.771017 Exit from DVFS_PRE_config <<<<<
5015 23:52:36.774942 Enter into PICG configuration >>>>
5016 23:52:36.778282 Exit from PICG configuration <<<<
5017 23:52:36.780925 [RX_INPUT] configuration >>>>>
5018 23:52:36.784298 [RX_INPUT] configuration <<<<<
5019 23:52:36.787720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5020 23:52:36.794798 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5021 23:52:36.801102 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 23:52:36.804511 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 23:52:36.810973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5024 23:52:36.817562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5025 23:52:36.821128 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5026 23:52:36.827660 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5027 23:52:36.830738 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5028 23:52:36.834261 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5029 23:52:36.837629 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5030 23:52:36.843921 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 23:52:36.847709 ===================================
5032 23:52:36.847788 LPDDR4 DRAM CONFIGURATION
5033 23:52:36.850714 ===================================
5034 23:52:36.854248 EX_ROW_EN[0] = 0x0
5035 23:52:36.857591 EX_ROW_EN[1] = 0x0
5036 23:52:36.857673 LP4Y_EN = 0x0
5037 23:52:36.860519 WORK_FSP = 0x0
5038 23:52:36.860628 WL = 0x3
5039 23:52:36.864040 RL = 0x3
5040 23:52:36.864116 BL = 0x2
5041 23:52:36.867449 RPST = 0x0
5042 23:52:36.867566 RD_PRE = 0x0
5043 23:52:36.871012 WR_PRE = 0x1
5044 23:52:36.871116 WR_PST = 0x0
5045 23:52:36.873854 DBI_WR = 0x0
5046 23:52:36.873951 DBI_RD = 0x0
5047 23:52:36.877087 OTF = 0x1
5048 23:52:36.880367 ===================================
5049 23:52:36.883621 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5050 23:52:36.886884 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5051 23:52:36.894336 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5052 23:52:36.897085 ===================================
5053 23:52:36.897162 LPDDR4 DRAM CONFIGURATION
5054 23:52:36.900349 ===================================
5055 23:52:36.903557 EX_ROW_EN[0] = 0x10
5056 23:52:36.906850 EX_ROW_EN[1] = 0x0
5057 23:52:36.906924 LP4Y_EN = 0x0
5058 23:52:36.910750 WORK_FSP = 0x0
5059 23:52:36.910825 WL = 0x3
5060 23:52:36.913386 RL = 0x3
5061 23:52:36.913457 BL = 0x2
5062 23:52:36.916790 RPST = 0x0
5063 23:52:36.916858 RD_PRE = 0x0
5064 23:52:36.920323 WR_PRE = 0x1
5065 23:52:36.920398 WR_PST = 0x0
5066 23:52:36.923916 DBI_WR = 0x0
5067 23:52:36.924007 DBI_RD = 0x0
5068 23:52:36.926920 OTF = 0x1
5069 23:52:36.930384 ===================================
5070 23:52:36.936656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5071 23:52:36.940002 nWR fixed to 30
5072 23:52:36.940108 [ModeRegInit_LP4] CH0 RK0
5073 23:52:36.943202 [ModeRegInit_LP4] CH0 RK1
5074 23:52:36.946734 [ModeRegInit_LP4] CH1 RK0
5075 23:52:36.950243 [ModeRegInit_LP4] CH1 RK1
5076 23:52:36.950349 match AC timing 9
5077 23:52:36.953401 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5078 23:52:36.960369 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5079 23:52:36.963065 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5080 23:52:36.970086 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5081 23:52:36.973221 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5082 23:52:36.973325 ==
5083 23:52:36.976708 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 23:52:36.979585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 23:52:36.979684 ==
5086 23:52:36.986520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 23:52:36.993238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5088 23:52:36.996702 [CA 0] Center 38 (8~69) winsize 62
5089 23:52:36.999699 [CA 1] Center 38 (8~69) winsize 62
5090 23:52:37.002984 [CA 2] Center 35 (5~65) winsize 61
5091 23:52:37.006327 [CA 3] Center 35 (5~65) winsize 61
5092 23:52:37.009665 [CA 4] Center 34 (4~65) winsize 62
5093 23:52:37.012929 [CA 5] Center 33 (3~64) winsize 62
5094 23:52:37.013097
5095 23:52:37.016388 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5096 23:52:37.016462
5097 23:52:37.019662 [CATrainingPosCal] consider 1 rank data
5098 23:52:37.023100 u2DelayCellTimex100 = 270/100 ps
5099 23:52:37.026278 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5100 23:52:37.029573 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5101 23:52:37.032776 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5102 23:52:37.035987 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5103 23:52:37.039808 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5104 23:52:37.042497 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5105 23:52:37.042575
5106 23:52:37.049252 CA PerBit enable=1, Macro0, CA PI delay=33
5107 23:52:37.049355
5108 23:52:37.052463 [CBTSetCACLKResult] CA Dly = 33
5109 23:52:37.052543 CS Dly: 7 (0~38)
5110 23:52:37.052650 ==
5111 23:52:37.055683 Dram Type= 6, Freq= 0, CH_0, rank 1
5112 23:52:37.059197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 23:52:37.059301 ==
5114 23:52:37.066056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5115 23:52:37.072766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5116 23:52:37.076052 [CA 0] Center 38 (8~69) winsize 62
5117 23:52:37.078845 [CA 1] Center 38 (8~69) winsize 62
5118 23:52:37.082444 [CA 2] Center 35 (5~66) winsize 62
5119 23:52:37.085365 [CA 3] Center 35 (5~66) winsize 62
5120 23:52:37.088881 [CA 4] Center 34 (4~65) winsize 62
5121 23:52:37.092230 [CA 5] Center 33 (3~64) winsize 62
5122 23:52:37.092307
5123 23:52:37.095816 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5124 23:52:37.095889
5125 23:52:37.098596 [CATrainingPosCal] consider 2 rank data
5126 23:52:37.101887 u2DelayCellTimex100 = 270/100 ps
5127 23:52:37.105105 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5128 23:52:37.108432 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 23:52:37.111966 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5130 23:52:37.118730 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5131 23:52:37.122017 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5132 23:52:37.125515 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 23:52:37.125592
5134 23:52:37.128326 CA PerBit enable=1, Macro0, CA PI delay=33
5135 23:52:37.128400
5136 23:52:37.131854 [CBTSetCACLKResult] CA Dly = 33
5137 23:52:37.131925 CS Dly: 7 (0~39)
5138 23:52:37.131984
5139 23:52:37.135729 ----->DramcWriteLeveling(PI) begin...
5140 23:52:37.135806 ==
5141 23:52:37.138297 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 23:52:37.144865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 23:52:37.144948 ==
5144 23:52:37.148678 Write leveling (Byte 0): 32 => 32
5145 23:52:37.151894 Write leveling (Byte 1): 29 => 29
5146 23:52:37.151975 DramcWriteLeveling(PI) end<-----
5147 23:52:37.155159
5148 23:52:37.155233 ==
5149 23:52:37.158115 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 23:52:37.161713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 23:52:37.161812 ==
5152 23:52:37.164860 [Gating] SW mode calibration
5153 23:52:37.171773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5154 23:52:37.175308 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5155 23:52:37.181594 0 14 0 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
5156 23:52:37.184917 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5157 23:52:37.188512 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 23:52:37.194911 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 23:52:37.198052 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 23:52:37.201446 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 23:52:37.208026 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:52:37.211410 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5163 23:52:37.214650 0 15 0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5164 23:52:37.221614 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5165 23:52:37.224285 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 23:52:37.227828 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 23:52:37.234628 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 23:52:37.237424 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 23:52:37.241012 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:52:37.247399 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 23:52:37.250770 1 0 0 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (0 0)
5172 23:52:37.253897 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
5173 23:52:37.260575 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 23:52:37.263707 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 23:52:37.267074 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 23:52:37.273788 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 23:52:37.277302 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:52:37.280465 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 23:52:37.287184 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5180 23:52:37.290477 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5181 23:52:37.293718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 23:52:37.300595 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 23:52:37.303892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:52:37.307127 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:52:37.313509 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:52:37.316813 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:52:37.320041 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:52:37.326458 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:52:37.330188 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:52:37.333458 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:52:37.339941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:52:37.343492 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:52:37.346842 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:52:37.353062 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5195 23:52:37.356428 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5196 23:52:37.359699 Total UI for P1: 0, mck2ui 16
5197 23:52:37.363446 best dqsien dly found for B0: ( 1, 2, 28)
5198 23:52:37.366828 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 23:52:37.369962 Total UI for P1: 0, mck2ui 16
5200 23:52:37.373096 best dqsien dly found for B1: ( 1, 3, 2)
5201 23:52:37.376172 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5202 23:52:37.379846 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5203 23:52:37.379951
5204 23:52:37.385921 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5205 23:52:37.389806 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5206 23:52:37.389913 [Gating] SW calibration Done
5207 23:52:37.393168 ==
5208 23:52:37.393245 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 23:52:37.399885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 23:52:37.399991 ==
5211 23:52:37.400082 RX Vref Scan: 0
5212 23:52:37.400173
5213 23:52:37.402988 RX Vref 0 -> 0, step: 1
5214 23:52:37.403103
5215 23:52:37.405837 RX Delay -80 -> 252, step: 8
5216 23:52:37.409619 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5217 23:52:37.412676 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5218 23:52:37.416120 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5219 23:52:37.422637 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5220 23:52:37.426014 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5221 23:52:37.429089 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5222 23:52:37.432108 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5223 23:52:37.435460 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5224 23:52:37.439034 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5225 23:52:37.445500 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5226 23:52:37.448683 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5227 23:52:37.452505 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5228 23:52:37.455724 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5229 23:52:37.461814 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5230 23:52:37.465527 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5231 23:52:37.468745 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5232 23:52:37.468844 ==
5233 23:52:37.472029 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 23:52:37.475070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 23:52:37.475179 ==
5236 23:52:37.478877 DQS Delay:
5237 23:52:37.478978 DQS0 = 0, DQS1 = 0
5238 23:52:37.481926 DQM Delay:
5239 23:52:37.482004 DQM0 = 93, DQM1 = 83
5240 23:52:37.482068 DQ Delay:
5241 23:52:37.485037 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5242 23:52:37.488387 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5243 23:52:37.492171 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5244 23:52:37.495472 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5245 23:52:37.495552
5246 23:52:37.498376
5247 23:52:37.498449 ==
5248 23:52:37.502033 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 23:52:37.504926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 23:52:37.505003 ==
5251 23:52:37.505066
5252 23:52:37.505124
5253 23:52:37.508466 TX Vref Scan disable
5254 23:52:37.508542 == TX Byte 0 ==
5255 23:52:37.514946 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5256 23:52:37.518046 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5257 23:52:37.518149 == TX Byte 1 ==
5258 23:52:37.525078 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5259 23:52:37.527987 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5260 23:52:37.528066 ==
5261 23:52:37.531454 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 23:52:37.534784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 23:52:37.534860 ==
5264 23:52:37.534923
5265 23:52:37.534986
5266 23:52:37.538138 TX Vref Scan disable
5267 23:52:37.541690 == TX Byte 0 ==
5268 23:52:37.544768 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5269 23:52:37.548424 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5270 23:52:37.551141 == TX Byte 1 ==
5271 23:52:37.554824 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5272 23:52:37.557907 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5273 23:52:37.558014
5274 23:52:37.561048 [DATLAT]
5275 23:52:37.561150 Freq=933, CH0 RK0
5276 23:52:37.561241
5277 23:52:37.564793 DATLAT Default: 0xd
5278 23:52:37.564893 0, 0xFFFF, sum = 0
5279 23:52:37.567962 1, 0xFFFF, sum = 0
5280 23:52:37.568062 2, 0xFFFF, sum = 0
5281 23:52:37.571489 3, 0xFFFF, sum = 0
5282 23:52:37.571563 4, 0xFFFF, sum = 0
5283 23:52:37.574578 5, 0xFFFF, sum = 0
5284 23:52:37.574682 6, 0xFFFF, sum = 0
5285 23:52:37.577592 7, 0xFFFF, sum = 0
5286 23:52:37.577693 8, 0xFFFF, sum = 0
5287 23:52:37.581152 9, 0xFFFF, sum = 0
5288 23:52:37.581229 10, 0x0, sum = 1
5289 23:52:37.584134 11, 0x0, sum = 2
5290 23:52:37.584231 12, 0x0, sum = 3
5291 23:52:37.587864 13, 0x0, sum = 4
5292 23:52:37.587966 best_step = 11
5293 23:52:37.588057
5294 23:52:37.588146 ==
5295 23:52:37.590953 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 23:52:37.597860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 23:52:37.597953 ==
5298 23:52:37.598020 RX Vref Scan: 1
5299 23:52:37.598084
5300 23:52:37.600617 RX Vref 0 -> 0, step: 1
5301 23:52:37.600689
5302 23:52:37.604290 RX Delay -69 -> 252, step: 4
5303 23:52:37.604364
5304 23:52:37.607597 Set Vref, RX VrefLevel [Byte0]: 63
5305 23:52:37.610900 [Byte1]: 47
5306 23:52:37.611003
5307 23:52:37.614171 Final RX Vref Byte 0 = 63 to rank0
5308 23:52:37.617616 Final RX Vref Byte 1 = 47 to rank0
5309 23:52:37.620592 Final RX Vref Byte 0 = 63 to rank1
5310 23:52:37.623973 Final RX Vref Byte 1 = 47 to rank1==
5311 23:52:37.627385 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 23:52:37.630724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 23:52:37.630835 ==
5314 23:52:37.633803 DQS Delay:
5315 23:52:37.633903 DQS0 = 0, DQS1 = 0
5316 23:52:37.637237 DQM Delay:
5317 23:52:37.637312 DQM0 = 96, DQM1 = 83
5318 23:52:37.637374 DQ Delay:
5319 23:52:37.640425 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5320 23:52:37.643834 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =110
5321 23:52:37.647440 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =76
5322 23:52:37.650359 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5323 23:52:37.650441
5324 23:52:37.653607
5325 23:52:37.660236 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5326 23:52:37.663642 CH0 RK0: MR19=505, MR18=1716
5327 23:52:37.670483 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5328 23:52:37.670581
5329 23:52:37.673608 ----->DramcWriteLeveling(PI) begin...
5330 23:52:37.673690 ==
5331 23:52:37.676998 Dram Type= 6, Freq= 0, CH_0, rank 1
5332 23:52:37.680054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 23:52:37.680161 ==
5334 23:52:37.683465 Write leveling (Byte 0): 33 => 33
5335 23:52:37.686818 Write leveling (Byte 1): 33 => 33
5336 23:52:37.690037 DramcWriteLeveling(PI) end<-----
5337 23:52:37.690119
5338 23:52:37.690183 ==
5339 23:52:37.693767 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 23:52:37.696747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 23:52:37.696823 ==
5342 23:52:37.699957 [Gating] SW mode calibration
5343 23:52:37.706357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5344 23:52:37.712966 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5345 23:52:37.716262 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
5346 23:52:37.720109 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5347 23:52:37.726572 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 23:52:37.729997 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 23:52:37.733325 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 23:52:37.739601 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 23:52:37.743021 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5352 23:52:37.746304 0 14 28 | B1->B0 | 3333 2626 | 0 0 | (0 0) (1 0)
5353 23:52:37.752938 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5354 23:52:37.756255 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 23:52:37.759272 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 23:52:37.765917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 23:52:37.769490 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 23:52:37.772514 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 23:52:37.779340 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:52:37.782669 0 15 28 | B1->B0 | 2525 3535 | 0 1 | (0 0) (0 0)
5361 23:52:37.785878 1 0 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5362 23:52:37.792861 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 23:52:37.795952 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 23:52:37.799293 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 23:52:37.805841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 23:52:37.809055 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:52:37.812220 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:52:37.818790 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5369 23:52:37.822165 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5370 23:52:37.826076 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:52:37.832552 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:52:37.835706 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:52:37.838799 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:52:37.845485 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:52:37.848799 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:52:37.852229 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:52:37.858462 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:52:37.862261 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:52:37.865656 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:52:37.872110 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:52:37.875505 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:52:37.878511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:52:37.884960 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:52:37.888532 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5385 23:52:37.891677 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 23:52:37.895397 Total UI for P1: 0, mck2ui 16
5387 23:52:37.898952 best dqsien dly found for B0: ( 1, 2, 28)
5388 23:52:37.901798 Total UI for P1: 0, mck2ui 16
5389 23:52:37.905374 best dqsien dly found for B1: ( 1, 2, 30)
5390 23:52:37.908588 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5391 23:52:37.911950 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5392 23:52:37.912055
5393 23:52:37.915412 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5394 23:52:37.922174 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5395 23:52:37.922284 [Gating] SW calibration Done
5396 23:52:37.922380 ==
5397 23:52:37.925038 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 23:52:37.931972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 23:52:37.932081 ==
5400 23:52:37.932172 RX Vref Scan: 0
5401 23:52:37.932235
5402 23:52:37.935075 RX Vref 0 -> 0, step: 1
5403 23:52:37.935148
5404 23:52:37.938498 RX Delay -80 -> 252, step: 8
5405 23:52:37.941822 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5406 23:52:37.944989 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5407 23:52:37.948295 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5408 23:52:37.954858 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5409 23:52:37.958211 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5410 23:52:37.961444 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5411 23:52:37.965048 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5412 23:52:37.968275 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5413 23:52:37.971419 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5414 23:52:37.978030 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5415 23:52:37.981186 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5416 23:52:37.984883 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5417 23:52:37.988177 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5418 23:52:37.991481 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5419 23:52:37.998184 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5420 23:52:38.000993 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5421 23:52:38.001098 ==
5422 23:52:38.004900 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 23:52:38.007824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 23:52:38.007925 ==
5425 23:52:38.010983 DQS Delay:
5426 23:52:38.011084 DQS0 = 0, DQS1 = 0
5427 23:52:38.011179 DQM Delay:
5428 23:52:38.014679 DQM0 = 92, DQM1 = 80
5429 23:52:38.014757 DQ Delay:
5430 23:52:38.017479 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5431 23:52:38.021450 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =107
5432 23:52:38.024268 DQ8 =71, DQ9 =63, DQ10 =83, DQ11 =71
5433 23:52:38.027662 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5434 23:52:38.027747
5435 23:52:38.027813
5436 23:52:38.027874 ==
5437 23:52:38.030956 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 23:52:38.037448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 23:52:38.037530 ==
5440 23:52:38.037598
5441 23:52:38.037658
5442 23:52:38.041127 TX Vref Scan disable
5443 23:52:38.041229 == TX Byte 0 ==
5444 23:52:38.044007 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5445 23:52:38.050531 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5446 23:52:38.050643 == TX Byte 1 ==
5447 23:52:38.054610 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5448 23:52:38.060440 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5449 23:52:38.060551 ==
5450 23:52:38.064382 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 23:52:38.067769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 23:52:38.067846 ==
5453 23:52:38.067909
5454 23:52:38.068002
5455 23:52:38.070815 TX Vref Scan disable
5456 23:52:38.073901 == TX Byte 0 ==
5457 23:52:38.077468 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5458 23:52:38.081029 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5459 23:52:38.084103 == TX Byte 1 ==
5460 23:52:38.086955 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5461 23:52:38.090782 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5462 23:52:38.090883
5463 23:52:38.090976 [DATLAT]
5464 23:52:38.093775 Freq=933, CH0 RK1
5465 23:52:38.093883
5466 23:52:38.097157 DATLAT Default: 0xb
5467 23:52:38.097255 0, 0xFFFF, sum = 0
5468 23:52:38.100279 1, 0xFFFF, sum = 0
5469 23:52:38.100383 2, 0xFFFF, sum = 0
5470 23:52:38.103872 3, 0xFFFF, sum = 0
5471 23:52:38.103977 4, 0xFFFF, sum = 0
5472 23:52:38.107135 5, 0xFFFF, sum = 0
5473 23:52:38.107239 6, 0xFFFF, sum = 0
5474 23:52:38.110400 7, 0xFFFF, sum = 0
5475 23:52:38.110477 8, 0xFFFF, sum = 0
5476 23:52:38.113856 9, 0xFFFF, sum = 0
5477 23:52:38.113962 10, 0x0, sum = 1
5478 23:52:38.116831 11, 0x0, sum = 2
5479 23:52:38.116911 12, 0x0, sum = 3
5480 23:52:38.120017 13, 0x0, sum = 4
5481 23:52:38.120130 best_step = 11
5482 23:52:38.120224
5483 23:52:38.120308 ==
5484 23:52:38.123821 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 23:52:38.127039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 23:52:38.130023 ==
5487 23:52:38.130101 RX Vref Scan: 0
5488 23:52:38.130164
5489 23:52:38.133439 RX Vref 0 -> 0, step: 1
5490 23:52:38.133513
5491 23:52:38.137035 RX Delay -77 -> 252, step: 4
5492 23:52:38.139983 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5493 23:52:38.143475 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5494 23:52:38.146706 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5495 23:52:38.153405 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5496 23:52:38.156523 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5497 23:52:38.160031 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5498 23:52:38.163446 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5499 23:52:38.166609 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5500 23:52:38.173220 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5501 23:52:38.176564 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5502 23:52:38.179884 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5503 23:52:38.183150 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5504 23:52:38.186611 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5505 23:52:38.193024 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5506 23:52:38.196396 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5507 23:52:38.199512 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5508 23:52:38.199617 ==
5509 23:52:38.202798 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 23:52:38.206325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 23:52:38.206427 ==
5512 23:52:38.209994 DQS Delay:
5513 23:52:38.210071 DQS0 = 0, DQS1 = 0
5514 23:52:38.213205 DQM Delay:
5515 23:52:38.213300 DQM0 = 92, DQM1 = 83
5516 23:52:38.213389 DQ Delay:
5517 23:52:38.216296 DQ0 =90, DQ1 =96, DQ2 =88, DQ3 =88
5518 23:52:38.219546 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5519 23:52:38.223039 DQ8 =76, DQ9 =66, DQ10 =86, DQ11 =76
5520 23:52:38.226211 DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =92
5521 23:52:38.226284
5522 23:52:38.226346
5523 23:52:38.236108 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5524 23:52:38.239669 CH0 RK1: MR19=505, MR18=2F11
5525 23:52:38.242860 CH0_RK1: MR19=0x505, MR18=0x2F11, DQSOSC=407, MR23=63, INC=65, DEC=43
5526 23:52:38.246429 [RxdqsGatingPostProcess] freq 933
5527 23:52:38.252585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5528 23:52:38.256113 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 23:52:38.259579 best DQS1 dly(2T, 0.5T) = (0, 11)
5530 23:52:38.263257 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 23:52:38.266236 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5532 23:52:38.269392 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 23:52:38.272652 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 23:52:38.276218 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 23:52:38.279340 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 23:52:38.282859 Pre-setting of DQS Precalculation
5537 23:52:38.286485 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5538 23:52:38.286564 ==
5539 23:52:38.289252 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 23:52:38.293190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 23:52:38.293298 ==
5542 23:52:38.299093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 23:52:38.305698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5544 23:52:38.309373 [CA 0] Center 37 (7~68) winsize 62
5545 23:52:38.312524 [CA 1] Center 37 (7~68) winsize 62
5546 23:52:38.315878 [CA 2] Center 35 (5~65) winsize 61
5547 23:52:38.319178 [CA 3] Center 35 (5~65) winsize 61
5548 23:52:38.322594 [CA 4] Center 35 (5~65) winsize 61
5549 23:52:38.325812 [CA 5] Center 33 (4~63) winsize 60
5550 23:52:38.325888
5551 23:52:38.329097 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5552 23:52:38.329172
5553 23:52:38.332167 [CATrainingPosCal] consider 1 rank data
5554 23:52:38.335788 u2DelayCellTimex100 = 270/100 ps
5555 23:52:38.338870 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5556 23:52:38.342155 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5557 23:52:38.345908 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5558 23:52:38.349238 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5559 23:52:38.355537 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5560 23:52:38.359448 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5561 23:52:38.359566
5562 23:52:38.362302 CA PerBit enable=1, Macro0, CA PI delay=33
5563 23:52:38.362374
5564 23:52:38.365300 [CBTSetCACLKResult] CA Dly = 33
5565 23:52:38.365384 CS Dly: 6 (0~37)
5566 23:52:38.365448 ==
5567 23:52:38.368898 Dram Type= 6, Freq= 0, CH_1, rank 1
5568 23:52:38.375534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 23:52:38.375626 ==
5570 23:52:38.378837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 23:52:38.385485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5572 23:52:38.388756 [CA 0] Center 38 (8~68) winsize 61
5573 23:52:38.392295 [CA 1] Center 37 (7~68) winsize 62
5574 23:52:38.395500 [CA 2] Center 35 (5~65) winsize 61
5575 23:52:38.398603 [CA 3] Center 34 (4~64) winsize 61
5576 23:52:38.401912 [CA 4] Center 35 (5~65) winsize 61
5577 23:52:38.405356 [CA 5] Center 34 (4~64) winsize 61
5578 23:52:38.405456
5579 23:52:38.408452 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5580 23:52:38.408566
5581 23:52:38.411958 [CATrainingPosCal] consider 2 rank data
5582 23:52:38.415451 u2DelayCellTimex100 = 270/100 ps
5583 23:52:38.418988 CA0 delay=38 (8~68),Diff = 5 PI (31 cell)
5584 23:52:38.422105 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5585 23:52:38.428271 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5586 23:52:38.431660 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5587 23:52:38.434991 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5588 23:52:38.438390 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5589 23:52:38.438465
5590 23:52:38.442106 CA PerBit enable=1, Macro0, CA PI delay=33
5591 23:52:38.442193
5592 23:52:38.444812 [CBTSetCACLKResult] CA Dly = 33
5593 23:52:38.444889 CS Dly: 7 (0~39)
5594 23:52:38.448442
5595 23:52:38.451712 ----->DramcWriteLeveling(PI) begin...
5596 23:52:38.451802 ==
5597 23:52:38.455066 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 23:52:38.458306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 23:52:38.458388 ==
5600 23:52:38.461323 Write leveling (Byte 0): 26 => 26
5601 23:52:38.464769 Write leveling (Byte 1): 27 => 27
5602 23:52:38.468129 DramcWriteLeveling(PI) end<-----
5603 23:52:38.468205
5604 23:52:38.468279 ==
5605 23:52:38.471493 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 23:52:38.474798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 23:52:38.474872 ==
5608 23:52:38.478209 [Gating] SW mode calibration
5609 23:52:38.485034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 23:52:38.491286 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5611 23:52:38.494954 0 14 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5612 23:52:38.498180 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 23:52:38.504850 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 23:52:38.507864 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 23:52:38.511053 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 23:52:38.518025 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 23:52:38.520992 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 23:52:38.524353 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
5619 23:52:38.530932 0 15 0 | B1->B0 | 2929 2b2b | 0 0 | (0 0) (0 0)
5620 23:52:38.534216 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 23:52:38.537425 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 23:52:38.544327 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 23:52:38.547784 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 23:52:38.551292 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 23:52:38.557594 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 23:52:38.561072 0 15 28 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
5627 23:52:38.563944 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5628 23:52:38.570851 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 23:52:38.574151 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 23:52:38.577941 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 23:52:38.580921 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 23:52:38.587592 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 23:52:38.590896 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5634 23:52:38.594455 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5635 23:52:38.600579 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:52:38.603822 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:52:38.607194 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 23:52:38.613916 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:52:38.617176 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:52:38.620387 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:52:38.626926 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:52:38.630255 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:52:38.633565 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:52:38.640317 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:52:38.643725 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:52:38.646852 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:52:38.653429 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:52:38.656759 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:52:38.660172 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:52:38.666828 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5651 23:52:38.670210 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5652 23:52:38.673411 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 23:52:38.676484 Total UI for P1: 0, mck2ui 16
5654 23:52:38.679957 best dqsien dly found for B0: ( 1, 2, 30)
5655 23:52:38.683324 Total UI for P1: 0, mck2ui 16
5656 23:52:38.686560 best dqsien dly found for B1: ( 1, 2, 30)
5657 23:52:38.689847 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5658 23:52:38.693123 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5659 23:52:38.696527
5660 23:52:38.699642 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5661 23:52:38.702877 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5662 23:52:38.706217 [Gating] SW calibration Done
5663 23:52:38.706303 ==
5664 23:52:38.709421 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 23:52:38.712709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 23:52:38.712789 ==
5667 23:52:38.712853 RX Vref Scan: 0
5668 23:52:38.716505
5669 23:52:38.716589 RX Vref 0 -> 0, step: 1
5670 23:52:38.716652
5671 23:52:38.719947 RX Delay -80 -> 252, step: 8
5672 23:52:38.722778 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5673 23:52:38.726528 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5674 23:52:38.732532 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5675 23:52:38.736339 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5676 23:52:38.739896 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5677 23:52:38.742548 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5678 23:52:38.745898 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5679 23:52:38.749144 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5680 23:52:38.756218 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5681 23:52:38.759325 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5682 23:52:38.762631 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5683 23:52:38.765993 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5684 23:52:38.769386 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5685 23:52:38.775658 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5686 23:52:38.778944 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5687 23:52:38.782441 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5688 23:52:38.782553 ==
5689 23:52:38.785405 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 23:52:38.788893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 23:52:38.788972 ==
5692 23:52:38.792480 DQS Delay:
5693 23:52:38.792594 DQS0 = 0, DQS1 = 0
5694 23:52:38.795802 DQM Delay:
5695 23:52:38.795903 DQM0 = 94, DQM1 = 87
5696 23:52:38.795995 DQ Delay:
5697 23:52:38.798912 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5698 23:52:38.802356 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5699 23:52:38.805384 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5700 23:52:38.808534 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5701 23:52:38.812019
5702 23:52:38.812129
5703 23:52:38.812225 ==
5704 23:52:38.815226 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 23:52:38.819115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 23:52:38.819218 ==
5707 23:52:38.819308
5708 23:52:38.819406
5709 23:52:38.822074 TX Vref Scan disable
5710 23:52:38.822171 == TX Byte 0 ==
5711 23:52:38.828553 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5712 23:52:38.832077 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5713 23:52:38.832176 == TX Byte 1 ==
5714 23:52:38.838656 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5715 23:52:38.841477 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5716 23:52:38.841549 ==
5717 23:52:38.844895 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 23:52:38.848167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 23:52:38.848266 ==
5720 23:52:38.848359
5721 23:52:38.848446
5722 23:52:38.851557 TX Vref Scan disable
5723 23:52:38.854668 == TX Byte 0 ==
5724 23:52:38.858364 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5725 23:52:38.861252 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5726 23:52:38.864954 == TX Byte 1 ==
5727 23:52:38.867742 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5728 23:52:38.871220 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5729 23:52:38.874554
5730 23:52:38.874655 [DATLAT]
5731 23:52:38.874747 Freq=933, CH1 RK0
5732 23:52:38.874838
5733 23:52:38.877833 DATLAT Default: 0xd
5734 23:52:38.877945 0, 0xFFFF, sum = 0
5735 23:52:38.881162 1, 0xFFFF, sum = 0
5736 23:52:38.881261 2, 0xFFFF, sum = 0
5737 23:52:38.884633 3, 0xFFFF, sum = 0
5738 23:52:38.884713 4, 0xFFFF, sum = 0
5739 23:52:38.887728 5, 0xFFFF, sum = 0
5740 23:52:38.887815 6, 0xFFFF, sum = 0
5741 23:52:38.891332 7, 0xFFFF, sum = 0
5742 23:52:38.894642 8, 0xFFFF, sum = 0
5743 23:52:38.894744 9, 0xFFFF, sum = 0
5744 23:52:38.897886 10, 0x0, sum = 1
5745 23:52:38.897991 11, 0x0, sum = 2
5746 23:52:38.898085 12, 0x0, sum = 3
5747 23:52:38.901286 13, 0x0, sum = 4
5748 23:52:38.901375 best_step = 11
5749 23:52:38.901455
5750 23:52:38.904646 ==
5751 23:52:38.907732 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 23:52:38.910652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 23:52:38.910763 ==
5754 23:52:38.910858 RX Vref Scan: 1
5755 23:52:38.910957
5756 23:52:38.913982 RX Vref 0 -> 0, step: 1
5757 23:52:38.914090
5758 23:52:38.917836 RX Delay -69 -> 252, step: 4
5759 23:52:38.917945
5760 23:52:38.920973 Set Vref, RX VrefLevel [Byte0]: 58
5761 23:52:38.924059 [Byte1]: 52
5762 23:52:38.924168
5763 23:52:38.927710 Final RX Vref Byte 0 = 58 to rank0
5764 23:52:38.931013 Final RX Vref Byte 1 = 52 to rank0
5765 23:52:38.934492 Final RX Vref Byte 0 = 58 to rank1
5766 23:52:38.937251 Final RX Vref Byte 1 = 52 to rank1==
5767 23:52:38.940497 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 23:52:38.943880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 23:52:38.947310 ==
5770 23:52:38.947390 DQS Delay:
5771 23:52:38.947454 DQS0 = 0, DQS1 = 0
5772 23:52:38.950509 DQM Delay:
5773 23:52:38.950589 DQM0 = 96, DQM1 = 88
5774 23:52:38.954163 DQ Delay:
5775 23:52:38.957305 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =92
5776 23:52:38.957434 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5777 23:52:38.960889 DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =82
5778 23:52:38.967817 DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =94
5779 23:52:38.967945
5780 23:52:38.968043
5781 23:52:38.973803 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5782 23:52:38.977596 CH1 RK0: MR19=405, MR18=FF08
5783 23:52:38.983766 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5784 23:52:38.983855
5785 23:52:38.987320 ----->DramcWriteLeveling(PI) begin...
5786 23:52:38.987408 ==
5787 23:52:38.990695 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 23:52:38.993855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 23:52:38.993959 ==
5790 23:52:38.997465 Write leveling (Byte 0): 26 => 26
5791 23:52:39.000477 Write leveling (Byte 1): 27 => 27
5792 23:52:39.003876 DramcWriteLeveling(PI) end<-----
5793 23:52:39.003954
5794 23:52:39.004041 ==
5795 23:52:39.006858 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 23:52:39.010363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 23:52:39.010446 ==
5798 23:52:39.013646 [Gating] SW mode calibration
5799 23:52:39.020380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5800 23:52:39.026965 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5801 23:52:39.030233 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5802 23:52:39.037221 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 23:52:39.040247 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 23:52:39.043575 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 23:52:39.046445 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 23:52:39.053225 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5807 23:52:39.056658 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
5808 23:52:39.059928 0 14 28 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
5809 23:52:39.067152 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 23:52:39.070109 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 23:52:39.073456 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 23:52:39.080363 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 23:52:39.083299 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 23:52:39.086678 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 23:52:39.093047 0 15 24 | B1->B0 | 2828 3737 | 0 0 | (0 0) (0 0)
5816 23:52:39.096859 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5817 23:52:39.099901 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 23:52:39.106349 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 23:52:39.109696 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 23:52:39.113082 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 23:52:39.119770 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 23:52:39.123170 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 23:52:39.126335 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5824 23:52:39.132535 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5825 23:52:39.136024 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 23:52:39.139137 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 23:52:39.146269 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:52:39.149209 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:52:39.152821 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:52:39.159528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:52:39.162818 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:52:39.166046 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:52:39.172513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:52:39.175850 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:52:39.179430 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:52:39.185861 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:52:39.189190 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:52:39.192408 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:52:39.199327 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5840 23:52:39.202516 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5841 23:52:39.205911 Total UI for P1: 0, mck2ui 16
5842 23:52:39.209129 best dqsien dly found for B0: ( 1, 2, 24)
5843 23:52:39.212467 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 23:52:39.215808 Total UI for P1: 0, mck2ui 16
5845 23:52:39.219148 best dqsien dly found for B1: ( 1, 2, 26)
5846 23:52:39.222209 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5847 23:52:39.225688 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5848 23:52:39.225793
5849 23:52:39.232117 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5850 23:52:39.235318 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5851 23:52:39.235394 [Gating] SW calibration Done
5852 23:52:39.238654 ==
5853 23:52:39.238727 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 23:52:39.245413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 23:52:39.245496 ==
5856 23:52:39.245609 RX Vref Scan: 0
5857 23:52:39.245697
5858 23:52:39.248835 RX Vref 0 -> 0, step: 1
5859 23:52:39.248931
5860 23:52:39.252003 RX Delay -80 -> 252, step: 8
5861 23:52:39.255191 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5862 23:52:39.258535 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5863 23:52:39.261677 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5864 23:52:39.268553 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5865 23:52:39.271900 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5866 23:52:39.275229 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5867 23:52:39.278535 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5868 23:52:39.282093 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5869 23:52:39.284940 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5870 23:52:39.291858 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5871 23:52:39.295169 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5872 23:52:39.298849 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5873 23:52:39.301731 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5874 23:52:39.305219 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5875 23:52:39.311451 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5876 23:52:39.314840 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5877 23:52:39.314943 ==
5878 23:52:39.318549 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 23:52:39.321915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 23:52:39.321989 ==
5881 23:52:39.322051 DQS Delay:
5882 23:52:39.324838 DQS0 = 0, DQS1 = 0
5883 23:52:39.324937 DQM Delay:
5884 23:52:39.328209 DQM0 = 93, DQM1 = 88
5885 23:52:39.328307 DQ Delay:
5886 23:52:39.331988 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5887 23:52:39.335013 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5888 23:52:39.338370 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5889 23:52:39.341676 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5890 23:52:39.341754
5891 23:52:39.341816
5892 23:52:39.341874 ==
5893 23:52:39.344800 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 23:52:39.348267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 23:52:39.352049 ==
5896 23:52:39.352181
5897 23:52:39.352286
5898 23:52:39.352372 TX Vref Scan disable
5899 23:52:39.354758 == TX Byte 0 ==
5900 23:52:39.358313 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5901 23:52:39.361487 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5902 23:52:39.365188 == TX Byte 1 ==
5903 23:52:39.367863 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 23:52:39.371763 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 23:52:39.374899 ==
5906 23:52:39.378099 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 23:52:39.381410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 23:52:39.381490 ==
5909 23:52:39.381553
5910 23:52:39.381612
5911 23:52:39.384620 TX Vref Scan disable
5912 23:52:39.384692 == TX Byte 0 ==
5913 23:52:39.391065 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5914 23:52:39.394700 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5915 23:52:39.394783 == TX Byte 1 ==
5916 23:52:39.401258 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5917 23:52:39.404570 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5918 23:52:39.404684
5919 23:52:39.404772 [DATLAT]
5920 23:52:39.407581 Freq=933, CH1 RK1
5921 23:52:39.407650
5922 23:52:39.407709 DATLAT Default: 0xb
5923 23:52:39.411774 0, 0xFFFF, sum = 0
5924 23:52:39.411852 1, 0xFFFF, sum = 0
5925 23:52:39.414403 2, 0xFFFF, sum = 0
5926 23:52:39.414475 3, 0xFFFF, sum = 0
5927 23:52:39.417560 4, 0xFFFF, sum = 0
5928 23:52:39.417631 5, 0xFFFF, sum = 0
5929 23:52:39.421496 6, 0xFFFF, sum = 0
5930 23:52:39.424340 7, 0xFFFF, sum = 0
5931 23:52:39.424419 8, 0xFFFF, sum = 0
5932 23:52:39.427832 9, 0xFFFF, sum = 0
5933 23:52:39.427938 10, 0x0, sum = 1
5934 23:52:39.431046 11, 0x0, sum = 2
5935 23:52:39.431117 12, 0x0, sum = 3
5936 23:52:39.431181 13, 0x0, sum = 4
5937 23:52:39.434555 best_step = 11
5938 23:52:39.434630
5939 23:52:39.434691 ==
5940 23:52:39.437549 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 23:52:39.440947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 23:52:39.441025 ==
5943 23:52:39.444188 RX Vref Scan: 0
5944 23:52:39.444263
5945 23:52:39.444324 RX Vref 0 -> 0, step: 1
5946 23:52:39.447589
5947 23:52:39.447658 RX Delay -69 -> 252, step: 4
5948 23:52:39.455298 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5949 23:52:39.458478 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5950 23:52:39.462138 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5951 23:52:39.465412 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5952 23:52:39.468799 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5953 23:52:39.471791 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5954 23:52:39.478735 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5955 23:52:39.481702 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5956 23:52:39.485740 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5957 23:52:39.488332 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5958 23:52:39.492005 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5959 23:52:39.498365 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5960 23:52:39.501641 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5961 23:52:39.504835 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5962 23:52:39.508204 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5963 23:52:39.511782 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5964 23:52:39.515219 ==
5965 23:52:39.515301 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 23:52:39.521442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 23:52:39.521578 ==
5968 23:52:39.521666 DQS Delay:
5969 23:52:39.525239 DQS0 = 0, DQS1 = 0
5970 23:52:39.525352 DQM Delay:
5971 23:52:39.528069 DQM0 = 91, DQM1 = 90
5972 23:52:39.528149 DQ Delay:
5973 23:52:39.531355 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
5974 23:52:39.534452 DQ4 =88, DQ5 =100, DQ6 =102, DQ7 =88
5975 23:52:39.538377 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
5976 23:52:39.541419 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
5977 23:52:39.541499
5978 23:52:39.541563
5979 23:52:39.547858 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5980 23:52:39.551142 CH1 RK1: MR19=505, MR18=D21
5981 23:52:39.557467 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
5982 23:52:39.560942 [RxdqsGatingPostProcess] freq 933
5983 23:52:39.567687 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5984 23:52:39.570742 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 23:52:39.570827 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 23:52:39.574100 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 23:52:39.577370 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 23:52:39.580802 best DQS0 dly(2T, 0.5T) = (0, 10)
5989 23:52:39.584308 best DQS1 dly(2T, 0.5T) = (0, 10)
5990 23:52:39.587617 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5991 23:52:39.591003 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5992 23:52:39.594235 Pre-setting of DQS Precalculation
5993 23:52:39.600872 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5994 23:52:39.607151 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5995 23:52:39.613899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5996 23:52:39.613986
5997 23:52:39.614049
5998 23:52:39.617181 [Calibration Summary] 1866 Mbps
5999 23:52:39.617261 CH 0, Rank 0
6000 23:52:39.620549 SW Impedance : PASS
6001 23:52:39.623996 DUTY Scan : NO K
6002 23:52:39.624076 ZQ Calibration : PASS
6003 23:52:39.627004 Jitter Meter : NO K
6004 23:52:39.630349 CBT Training : PASS
6005 23:52:39.630429 Write leveling : PASS
6006 23:52:39.633925 RX DQS gating : PASS
6007 23:52:39.636999 RX DQ/DQS(RDDQC) : PASS
6008 23:52:39.637079 TX DQ/DQS : PASS
6009 23:52:39.640219 RX DATLAT : PASS
6010 23:52:39.640299 RX DQ/DQS(Engine): PASS
6011 23:52:39.643611 TX OE : NO K
6012 23:52:39.643691 All Pass.
6013 23:52:39.643754
6014 23:52:39.646820 CH 0, Rank 1
6015 23:52:39.646899 SW Impedance : PASS
6016 23:52:39.650238 DUTY Scan : NO K
6017 23:52:39.653494 ZQ Calibration : PASS
6018 23:52:39.653573 Jitter Meter : NO K
6019 23:52:39.657188 CBT Training : PASS
6020 23:52:39.660113 Write leveling : PASS
6021 23:52:39.660195 RX DQS gating : PASS
6022 23:52:39.663501 RX DQ/DQS(RDDQC) : PASS
6023 23:52:39.666350 TX DQ/DQS : PASS
6024 23:52:39.666434 RX DATLAT : PASS
6025 23:52:39.670024 RX DQ/DQS(Engine): PASS
6026 23:52:39.673140 TX OE : NO K
6027 23:52:39.673221 All Pass.
6028 23:52:39.673285
6029 23:52:39.673345 CH 1, Rank 0
6030 23:52:39.676466 SW Impedance : PASS
6031 23:52:39.679958 DUTY Scan : NO K
6032 23:52:39.680039 ZQ Calibration : PASS
6033 23:52:39.683123 Jitter Meter : NO K
6034 23:52:39.686766 CBT Training : PASS
6035 23:52:39.686848 Write leveling : PASS
6036 23:52:39.689753 RX DQS gating : PASS
6037 23:52:39.693351 RX DQ/DQS(RDDQC) : PASS
6038 23:52:39.693433 TX DQ/DQS : PASS
6039 23:52:39.696449 RX DATLAT : PASS
6040 23:52:39.699505 RX DQ/DQS(Engine): PASS
6041 23:52:39.699587 TX OE : NO K
6042 23:52:39.702686 All Pass.
6043 23:52:39.702791
6044 23:52:39.702884 CH 1, Rank 1
6045 23:52:39.706171 SW Impedance : PASS
6046 23:52:39.706269 DUTY Scan : NO K
6047 23:52:39.709754 ZQ Calibration : PASS
6048 23:52:39.713161 Jitter Meter : NO K
6049 23:52:39.713263 CBT Training : PASS
6050 23:52:39.715999 Write leveling : PASS
6051 23:52:39.716066 RX DQS gating : PASS
6052 23:52:39.719308 RX DQ/DQS(RDDQC) : PASS
6053 23:52:39.722637 TX DQ/DQS : PASS
6054 23:52:39.722721 RX DATLAT : PASS
6055 23:52:39.726169 RX DQ/DQS(Engine): PASS
6056 23:52:39.729209 TX OE : NO K
6057 23:52:39.729307 All Pass.
6058 23:52:39.729403
6059 23:52:39.732540 DramC Write-DBI off
6060 23:52:39.732644 PER_BANK_REFRESH: Hybrid Mode
6061 23:52:39.735860 TX_TRACKING: ON
6062 23:52:39.745684 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6063 23:52:39.749060 [FAST_K] Save calibration result to emmc
6064 23:52:39.752776 dramc_set_vcore_voltage set vcore to 650000
6065 23:52:39.752865 Read voltage for 400, 6
6066 23:52:39.756145 Vio18 = 0
6067 23:52:39.756227 Vcore = 650000
6068 23:52:39.756291 Vdram = 0
6069 23:52:39.759223 Vddq = 0
6070 23:52:39.759305 Vmddr = 0
6071 23:52:39.765878 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6072 23:52:39.769033 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6073 23:52:39.772542 MEM_TYPE=3, freq_sel=20
6074 23:52:39.775629 sv_algorithm_assistance_LP4_800
6075 23:52:39.778842 ============ PULL DRAM RESETB DOWN ============
6076 23:52:39.782283 ========== PULL DRAM RESETB DOWN end =========
6077 23:52:39.788593 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6078 23:52:39.792141 ===================================
6079 23:52:39.792311 LPDDR4 DRAM CONFIGURATION
6080 23:52:39.795619 ===================================
6081 23:52:39.798744 EX_ROW_EN[0] = 0x0
6082 23:52:39.802130 EX_ROW_EN[1] = 0x0
6083 23:52:39.802214 LP4Y_EN = 0x0
6084 23:52:39.805202 WORK_FSP = 0x0
6085 23:52:39.805284 WL = 0x2
6086 23:52:39.808810 RL = 0x2
6087 23:52:39.808891 BL = 0x2
6088 23:52:39.811890 RPST = 0x0
6089 23:52:39.811973 RD_PRE = 0x0
6090 23:52:39.815288 WR_PRE = 0x1
6091 23:52:39.815415 WR_PST = 0x0
6092 23:52:39.818976 DBI_WR = 0x0
6093 23:52:39.819059 DBI_RD = 0x0
6094 23:52:39.822153 OTF = 0x1
6095 23:52:39.825474 ===================================
6096 23:52:39.828815 ===================================
6097 23:52:39.828895 ANA top config
6098 23:52:39.831710 ===================================
6099 23:52:39.835270 DLL_ASYNC_EN = 0
6100 23:52:39.838450 ALL_SLAVE_EN = 1
6101 23:52:39.838551 NEW_RANK_MODE = 1
6102 23:52:39.842258 DLL_IDLE_MODE = 1
6103 23:52:39.845674 LP45_APHY_COMB_EN = 1
6104 23:52:39.848828 TX_ODT_DIS = 1
6105 23:52:39.851859 NEW_8X_MODE = 1
6106 23:52:39.855176 ===================================
6107 23:52:39.858528 ===================================
6108 23:52:39.858613 data_rate = 800
6109 23:52:39.861934 CKR = 1
6110 23:52:39.865254 DQ_P2S_RATIO = 4
6111 23:52:39.868475 ===================================
6112 23:52:39.872241 CA_P2S_RATIO = 4
6113 23:52:39.875277 DQ_CA_OPEN = 0
6114 23:52:39.878495 DQ_SEMI_OPEN = 1
6115 23:52:39.878602 CA_SEMI_OPEN = 1
6116 23:52:39.881852 CA_FULL_RATE = 0
6117 23:52:39.885364 DQ_CKDIV4_EN = 0
6118 23:52:39.888582 CA_CKDIV4_EN = 1
6119 23:52:39.891835 CA_PREDIV_EN = 0
6120 23:52:39.894995 PH8_DLY = 0
6121 23:52:39.895070 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6122 23:52:39.898646 DQ_AAMCK_DIV = 0
6123 23:52:39.901740 CA_AAMCK_DIV = 0
6124 23:52:39.904847 CA_ADMCK_DIV = 4
6125 23:52:39.908346 DQ_TRACK_CA_EN = 0
6126 23:52:39.911539 CA_PICK = 800
6127 23:52:39.914898 CA_MCKIO = 400
6128 23:52:39.914978 MCKIO_SEMI = 400
6129 23:52:39.917829 PLL_FREQ = 3016
6130 23:52:39.921529 DQ_UI_PI_RATIO = 32
6131 23:52:39.924514 CA_UI_PI_RATIO = 32
6132 23:52:39.928209 ===================================
6133 23:52:39.931251 ===================================
6134 23:52:39.934938 memory_type:LPDDR4
6135 23:52:39.935036 GP_NUM : 10
6136 23:52:39.937909 SRAM_EN : 1
6137 23:52:39.941260 MD32_EN : 0
6138 23:52:39.944692 ===================================
6139 23:52:39.944776 [ANA_INIT] >>>>>>>>>>>>>>
6140 23:52:39.947842 <<<<<< [CONFIGURE PHASE]: ANA_TX
6141 23:52:39.950938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6142 23:52:39.954652 ===================================
6143 23:52:39.958153 data_rate = 800,PCW = 0X7400
6144 23:52:39.961130 ===================================
6145 23:52:39.964165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6146 23:52:39.971278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 23:52:39.980813 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 23:52:39.987625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6149 23:52:39.990805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6150 23:52:39.993920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6151 23:52:39.994025 [ANA_INIT] flow start
6152 23:52:39.997684 [ANA_INIT] PLL >>>>>>>>
6153 23:52:40.000814 [ANA_INIT] PLL <<<<<<<<
6154 23:52:40.000890 [ANA_INIT] MIDPI >>>>>>>>
6155 23:52:40.004005 [ANA_INIT] MIDPI <<<<<<<<
6156 23:52:40.007889 [ANA_INIT] DLL >>>>>>>>
6157 23:52:40.007989 [ANA_INIT] flow end
6158 23:52:40.013822 ============ LP4 DIFF to SE enter ============
6159 23:52:40.017275 ============ LP4 DIFF to SE exit ============
6160 23:52:40.020310 [ANA_INIT] <<<<<<<<<<<<<
6161 23:52:40.024205 [Flow] Enable top DCM control >>>>>
6162 23:52:40.026895 [Flow] Enable top DCM control <<<<<
6163 23:52:40.026970 Enable DLL master slave shuffle
6164 23:52:40.034072 ==============================================================
6165 23:52:40.037056 Gating Mode config
6166 23:52:40.040393 ==============================================================
6167 23:52:40.044045 Config description:
6168 23:52:40.053697 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6169 23:52:40.060209 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6170 23:52:40.064000 SELPH_MODE 0: By rank 1: By Phase
6171 23:52:40.070158 ==============================================================
6172 23:52:40.073321 GAT_TRACK_EN = 0
6173 23:52:40.076712 RX_GATING_MODE = 2
6174 23:52:40.079984 RX_GATING_TRACK_MODE = 2
6175 23:52:40.083947 SELPH_MODE = 1
6176 23:52:40.087000 PICG_EARLY_EN = 1
6177 23:52:40.087081 VALID_LAT_VALUE = 1
6178 23:52:40.093485 ==============================================================
6179 23:52:40.096489 Enter into Gating configuration >>>>
6180 23:52:40.099827 Exit from Gating configuration <<<<
6181 23:52:40.103274 Enter into DVFS_PRE_config >>>>>
6182 23:52:40.113313 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6183 23:52:40.116816 Exit from DVFS_PRE_config <<<<<
6184 23:52:40.119992 Enter into PICG configuration >>>>
6185 23:52:40.123401 Exit from PICG configuration <<<<
6186 23:52:40.126443 [RX_INPUT] configuration >>>>>
6187 23:52:40.129884 [RX_INPUT] configuration <<<<<
6188 23:52:40.133123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6189 23:52:40.140183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6190 23:52:40.146306 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 23:52:40.153330 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 23:52:40.159970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 23:52:40.166355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 23:52:40.169997 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6195 23:52:40.173180 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6196 23:52:40.176529 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6197 23:52:40.183285 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6198 23:52:40.186042 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6199 23:52:40.189296 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 23:52:40.193332 ===================================
6201 23:52:40.195915 LPDDR4 DRAM CONFIGURATION
6202 23:52:40.199851 ===================================
6203 23:52:40.199921 EX_ROW_EN[0] = 0x0
6204 23:52:40.202797 EX_ROW_EN[1] = 0x0
6205 23:52:40.202865 LP4Y_EN = 0x0
6206 23:52:40.205972 WORK_FSP = 0x0
6207 23:52:40.209584 WL = 0x2
6208 23:52:40.209664 RL = 0x2
6209 23:52:40.212782 BL = 0x2
6210 23:52:40.212855 RPST = 0x0
6211 23:52:40.216203 RD_PRE = 0x0
6212 23:52:40.216278 WR_PRE = 0x1
6213 23:52:40.219491 WR_PST = 0x0
6214 23:52:40.219588 DBI_WR = 0x0
6215 23:52:40.222750 DBI_RD = 0x0
6216 23:52:40.222848 OTF = 0x1
6217 23:52:40.226328 ===================================
6218 23:52:40.229276 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6219 23:52:40.235971 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6220 23:52:40.238908 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 23:52:40.242323 ===================================
6222 23:52:40.245769 LPDDR4 DRAM CONFIGURATION
6223 23:52:40.249054 ===================================
6224 23:52:40.249134 EX_ROW_EN[0] = 0x10
6225 23:52:40.252061 EX_ROW_EN[1] = 0x0
6226 23:52:40.252141 LP4Y_EN = 0x0
6227 23:52:40.255508 WORK_FSP = 0x0
6228 23:52:40.258793 WL = 0x2
6229 23:52:40.258895 RL = 0x2
6230 23:52:40.262289 BL = 0x2
6231 23:52:40.262361 RPST = 0x0
6232 23:52:40.265514 RD_PRE = 0x0
6233 23:52:40.265584 WR_PRE = 0x1
6234 23:52:40.268841 WR_PST = 0x0
6235 23:52:40.268928 DBI_WR = 0x0
6236 23:52:40.272342 DBI_RD = 0x0
6237 23:52:40.272448 OTF = 0x1
6238 23:52:40.275436 ===================================
6239 23:52:40.282071 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6240 23:52:40.286228 nWR fixed to 30
6241 23:52:40.289441 [ModeRegInit_LP4] CH0 RK0
6242 23:52:40.289515 [ModeRegInit_LP4] CH0 RK1
6243 23:52:40.292646 [ModeRegInit_LP4] CH1 RK0
6244 23:52:40.295923 [ModeRegInit_LP4] CH1 RK1
6245 23:52:40.296000 match AC timing 19
6246 23:52:40.302622 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6247 23:52:40.305852 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6248 23:52:40.309539 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6249 23:52:40.316083 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6250 23:52:40.319428 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6251 23:52:40.319533 ==
6252 23:52:40.322864 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 23:52:40.325712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 23:52:40.325827 ==
6255 23:52:40.332485 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 23:52:40.338936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6257 23:52:40.342361 [CA 0] Center 36 (8~64) winsize 57
6258 23:52:40.345933 [CA 1] Center 36 (8~64) winsize 57
6259 23:52:40.349349 [CA 2] Center 36 (8~64) winsize 57
6260 23:52:40.352722 [CA 3] Center 36 (8~64) winsize 57
6261 23:52:40.352817 [CA 4] Center 36 (8~64) winsize 57
6262 23:52:40.355970 [CA 5] Center 36 (8~64) winsize 57
6263 23:52:40.356077
6264 23:52:40.362420 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6265 23:52:40.362533
6266 23:52:40.365753 [CATrainingPosCal] consider 1 rank data
6267 23:52:40.369588 u2DelayCellTimex100 = 270/100 ps
6268 23:52:40.372147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:52:40.375644 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:52:40.378932 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:52:40.382774 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:52:40.385786 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:52:40.389195 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:52:40.389298
6275 23:52:40.392471 CA PerBit enable=1, Macro0, CA PI delay=36
6276 23:52:40.392599
6277 23:52:40.395552 [CBTSetCACLKResult] CA Dly = 36
6278 23:52:40.398965 CS Dly: 1 (0~32)
6279 23:52:40.399070 ==
6280 23:52:40.402592 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 23:52:40.405517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 23:52:40.405592 ==
6283 23:52:40.412082 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 23:52:40.415333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6285 23:52:40.419014 [CA 0] Center 36 (8~64) winsize 57
6286 23:52:40.422381 [CA 1] Center 36 (8~64) winsize 57
6287 23:52:40.425534 [CA 2] Center 36 (8~64) winsize 57
6288 23:52:40.428518 [CA 3] Center 36 (8~64) winsize 57
6289 23:52:40.432294 [CA 4] Center 36 (8~64) winsize 57
6290 23:52:40.435460 [CA 5] Center 36 (8~64) winsize 57
6291 23:52:40.435553
6292 23:52:40.438607 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6293 23:52:40.438710
6294 23:52:40.442358 [CATrainingPosCal] consider 2 rank data
6295 23:52:40.445228 u2DelayCellTimex100 = 270/100 ps
6296 23:52:40.449098 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 23:52:40.451926 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:52:40.458362 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:52:40.461996 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:52:40.464950 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:52:40.468801 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:52:40.468890
6303 23:52:40.471662 CA PerBit enable=1, Macro0, CA PI delay=36
6304 23:52:40.471739
6305 23:52:40.475162 [CBTSetCACLKResult] CA Dly = 36
6306 23:52:40.475277 CS Dly: 1 (0~32)
6307 23:52:40.475368
6308 23:52:40.478438 ----->DramcWriteLeveling(PI) begin...
6309 23:52:40.481597 ==
6310 23:52:40.485195 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 23:52:40.488373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 23:52:40.488475 ==
6313 23:52:40.491865 Write leveling (Byte 0): 40 => 8
6314 23:52:40.494822 Write leveling (Byte 1): 40 => 8
6315 23:52:40.498049 DramcWriteLeveling(PI) end<-----
6316 23:52:40.498150
6317 23:52:40.498240 ==
6318 23:52:40.501475 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 23:52:40.504882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 23:52:40.504984 ==
6321 23:52:40.508328 [Gating] SW mode calibration
6322 23:52:40.514833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6323 23:52:40.521563 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6324 23:52:40.524526 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 23:52:40.527714 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 23:52:40.534427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 23:52:40.537612 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 23:52:40.541115 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 23:52:40.547672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 23:52:40.551311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 23:52:40.554484 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 23:52:40.560934 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 23:52:40.561033 Total UI for P1: 0, mck2ui 16
6334 23:52:40.567532 best dqsien dly found for B0: ( 0, 14, 24)
6335 23:52:40.567618 Total UI for P1: 0, mck2ui 16
6336 23:52:40.570959 best dqsien dly found for B1: ( 0, 14, 24)
6337 23:52:40.577346 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6338 23:52:40.580863 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6339 23:52:40.580941
6340 23:52:40.583883 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 23:52:40.587725 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 23:52:40.590702 [Gating] SW calibration Done
6343 23:52:40.590804 ==
6344 23:52:40.593736 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 23:52:40.597810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 23:52:40.597896 ==
6347 23:52:40.600458 RX Vref Scan: 0
6348 23:52:40.600539
6349 23:52:40.600629 RX Vref 0 -> 0, step: 1
6350 23:52:40.600690
6351 23:52:40.603938 RX Delay -410 -> 252, step: 16
6352 23:52:40.610459 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6353 23:52:40.613717 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6354 23:52:40.617057 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6355 23:52:40.620400 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6356 23:52:40.627206 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6357 23:52:40.630796 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6358 23:52:40.633946 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6359 23:52:40.637395 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6360 23:52:40.643698 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6361 23:52:40.647025 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6362 23:52:40.650295 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6363 23:52:40.653717 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6364 23:52:40.660313 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6365 23:52:40.663668 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6366 23:52:40.667106 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6367 23:52:40.670269 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6368 23:52:40.673743 ==
6369 23:52:40.676490 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 23:52:40.679911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 23:52:40.679989 ==
6372 23:52:40.680050 DQS Delay:
6373 23:52:40.683213 DQS0 = 59, DQS1 = 59
6374 23:52:40.683311 DQM Delay:
6375 23:52:40.686233 DQM0 = 18, DQM1 = 10
6376 23:52:40.686316 DQ Delay:
6377 23:52:40.689563 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6378 23:52:40.692968 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6379 23:52:40.696640 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6380 23:52:40.699573 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6381 23:52:40.699651
6382 23:52:40.699712
6383 23:52:40.699769 ==
6384 23:52:40.703274 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 23:52:40.706487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 23:52:40.706582 ==
6387 23:52:40.706643
6388 23:52:40.706699
6389 23:52:40.709613 TX Vref Scan disable
6390 23:52:40.709700 == TX Byte 0 ==
6391 23:52:40.716782 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 23:52:40.720001 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 23:52:40.720084 == TX Byte 1 ==
6394 23:52:40.726640 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 23:52:40.729818 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 23:52:40.729895 ==
6397 23:52:40.733106 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 23:52:40.736006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 23:52:40.736080 ==
6400 23:52:40.736140
6401 23:52:40.736201
6402 23:52:40.739771 TX Vref Scan disable
6403 23:52:40.743076 == TX Byte 0 ==
6404 23:52:40.745843 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 23:52:40.749832 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 23:52:40.753179 == TX Byte 1 ==
6407 23:52:40.755869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 23:52:40.759538 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 23:52:40.759649
6410 23:52:40.759750 [DATLAT]
6411 23:52:40.762497 Freq=400, CH0 RK0
6412 23:52:40.762595
6413 23:52:40.762682 DATLAT Default: 0xf
6414 23:52:40.766149 0, 0xFFFF, sum = 0
6415 23:52:40.766252 1, 0xFFFF, sum = 0
6416 23:52:40.769410 2, 0xFFFF, sum = 0
6417 23:52:40.772287 3, 0xFFFF, sum = 0
6418 23:52:40.772389 4, 0xFFFF, sum = 0
6419 23:52:40.776073 5, 0xFFFF, sum = 0
6420 23:52:40.776146 6, 0xFFFF, sum = 0
6421 23:52:40.778856 7, 0xFFFF, sum = 0
6422 23:52:40.778934 8, 0xFFFF, sum = 0
6423 23:52:40.782635 9, 0xFFFF, sum = 0
6424 23:52:40.782745 10, 0xFFFF, sum = 0
6425 23:52:40.786135 11, 0xFFFF, sum = 0
6426 23:52:40.786222 12, 0xFFFF, sum = 0
6427 23:52:40.789336 13, 0x0, sum = 1
6428 23:52:40.789417 14, 0x0, sum = 2
6429 23:52:40.792787 15, 0x0, sum = 3
6430 23:52:40.792897 16, 0x0, sum = 4
6431 23:52:40.796033 best_step = 14
6432 23:52:40.796115
6433 23:52:40.796175 ==
6434 23:52:40.799325 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 23:52:40.802397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 23:52:40.802486 ==
6437 23:52:40.802551 RX Vref Scan: 1
6438 23:52:40.805479
6439 23:52:40.805583 RX Vref 0 -> 0, step: 1
6440 23:52:40.805648
6441 23:52:40.808888 RX Delay -359 -> 252, step: 8
6442 23:52:40.808978
6443 23:52:40.812357 Set Vref, RX VrefLevel [Byte0]: 63
6444 23:52:40.815419 [Byte1]: 47
6445 23:52:40.819993
6446 23:52:40.820097 Final RX Vref Byte 0 = 63 to rank0
6447 23:52:40.823035 Final RX Vref Byte 1 = 47 to rank0
6448 23:52:40.826387 Final RX Vref Byte 0 = 63 to rank1
6449 23:52:40.829901 Final RX Vref Byte 1 = 47 to rank1==
6450 23:52:40.833222 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 23:52:40.839650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 23:52:40.839769 ==
6453 23:52:40.839840 DQS Delay:
6454 23:52:40.842896 DQS0 = 60, DQS1 = 68
6455 23:52:40.842964 DQM Delay:
6456 23:52:40.843023 DQM0 = 15, DQM1 = 14
6457 23:52:40.846471 DQ Delay:
6458 23:52:40.849645 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6459 23:52:40.852871 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6460 23:52:40.852947 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6461 23:52:40.856343 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6462 23:52:40.859495
6463 23:52:40.859615
6464 23:52:40.866076 [DQSOSCAuto] RK0, (LSB)MR18= 0x8583, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6465 23:52:40.869998 CH0 RK0: MR19=C0C, MR18=8583
6466 23:52:40.876409 CH0_RK0: MR19=0xC0C, MR18=0x8583, DQSOSC=393, MR23=63, INC=382, DEC=254
6467 23:52:40.876573 ==
6468 23:52:40.879520 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 23:52:40.883143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 23:52:40.883232 ==
6471 23:52:40.886107 [Gating] SW mode calibration
6472 23:52:40.892686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6473 23:52:40.899374 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6474 23:52:40.902491 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 23:52:40.905706 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 23:52:40.912570 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 23:52:40.915748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 23:52:40.919169 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 23:52:40.926182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 23:52:40.929455 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 23:52:40.932446 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 23:52:40.939368 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 23:52:40.939526 Total UI for P1: 0, mck2ui 16
6484 23:52:40.945569 best dqsien dly found for B0: ( 0, 14, 24)
6485 23:52:40.945697 Total UI for P1: 0, mck2ui 16
6486 23:52:40.949115 best dqsien dly found for B1: ( 0, 14, 24)
6487 23:52:40.955674 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6488 23:52:40.959082 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6489 23:52:40.959191
6490 23:52:40.962367 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 23:52:40.965780 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 23:52:40.969021 [Gating] SW calibration Done
6493 23:52:40.969106 ==
6494 23:52:40.972425 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 23:52:40.975621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 23:52:40.975705 ==
6497 23:52:40.978659 RX Vref Scan: 0
6498 23:52:40.978760
6499 23:52:40.978849 RX Vref 0 -> 0, step: 1
6500 23:52:40.978935
6501 23:52:40.982469 RX Delay -410 -> 252, step: 16
6502 23:52:40.989160 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6503 23:52:40.992165 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6504 23:52:40.995499 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6505 23:52:40.998806 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6506 23:52:41.005170 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6507 23:52:41.008469 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6508 23:52:41.012196 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6509 23:52:41.015468 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6510 23:52:41.022011 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6511 23:52:41.025232 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6512 23:52:41.028307 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6513 23:52:41.031701 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6514 23:52:41.038240 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6515 23:52:41.041894 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6516 23:52:41.044920 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6517 23:52:41.048124 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6518 23:52:41.051834 ==
6519 23:52:41.054880 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 23:52:41.058320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 23:52:41.058443 ==
6522 23:52:41.058544 DQS Delay:
6523 23:52:41.061435 DQS0 = 59, DQS1 = 59
6524 23:52:41.061518 DQM Delay:
6525 23:52:41.064872 DQM0 = 16, DQM1 = 10
6526 23:52:41.064955 DQ Delay:
6527 23:52:41.068178 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6528 23:52:41.071216 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6529 23:52:41.074519 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6530 23:52:41.078319 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6531 23:52:41.078431
6532 23:52:41.078526
6533 23:52:41.078615 ==
6534 23:52:41.081186 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 23:52:41.084447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 23:52:41.084575 ==
6537 23:52:41.084647
6538 23:52:41.084708
6539 23:52:41.087820 TX Vref Scan disable
6540 23:52:41.091015 == TX Byte 0 ==
6541 23:52:41.094806 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6542 23:52:41.097682 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6543 23:52:41.097866 == TX Byte 1 ==
6544 23:52:41.104414 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 23:52:41.107718 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 23:52:41.107828 ==
6547 23:52:41.111386 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 23:52:41.114455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 23:52:41.114566 ==
6550 23:52:41.114633
6551 23:52:41.117691
6552 23:52:41.117779 TX Vref Scan disable
6553 23:52:41.121286 == TX Byte 0 ==
6554 23:52:41.123933 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6555 23:52:41.127566 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6556 23:52:41.131246 == TX Byte 1 ==
6557 23:52:41.134162 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6558 23:52:41.137221 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6559 23:52:41.137332
6560 23:52:41.137402 [DATLAT]
6561 23:52:41.140786 Freq=400, CH0 RK1
6562 23:52:41.140870
6563 23:52:41.140934 DATLAT Default: 0xe
6564 23:52:41.143997 0, 0xFFFF, sum = 0
6565 23:52:41.144086 1, 0xFFFF, sum = 0
6566 23:52:41.147260 2, 0xFFFF, sum = 0
6567 23:52:41.150700 3, 0xFFFF, sum = 0
6568 23:52:41.150813 4, 0xFFFF, sum = 0
6569 23:52:41.154128 5, 0xFFFF, sum = 0
6570 23:52:41.154212 6, 0xFFFF, sum = 0
6571 23:52:41.157298 7, 0xFFFF, sum = 0
6572 23:52:41.157373 8, 0xFFFF, sum = 0
6573 23:52:41.160635 9, 0xFFFF, sum = 0
6574 23:52:41.160724 10, 0xFFFF, sum = 0
6575 23:52:41.163970 11, 0xFFFF, sum = 0
6576 23:52:41.164047 12, 0xFFFF, sum = 0
6577 23:52:41.167233 13, 0x0, sum = 1
6578 23:52:41.167327 14, 0x0, sum = 2
6579 23:52:41.170832 15, 0x0, sum = 3
6580 23:52:41.170909 16, 0x0, sum = 4
6581 23:52:41.174182 best_step = 14
6582 23:52:41.174259
6583 23:52:41.174322 ==
6584 23:52:41.177075 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 23:52:41.180527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 23:52:41.180620 ==
6587 23:52:41.180685 RX Vref Scan: 0
6588 23:52:41.184210
6589 23:52:41.184295 RX Vref 0 -> 0, step: 1
6590 23:52:41.184360
6591 23:52:41.186987 RX Delay -359 -> 252, step: 8
6592 23:52:41.194782 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6593 23:52:41.197876 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6594 23:52:41.201221 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6595 23:52:41.208326 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6596 23:52:41.211507 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6597 23:52:41.214264 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6598 23:52:41.217774 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6599 23:52:41.224406 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6600 23:52:41.227510 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6601 23:52:41.231215 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6602 23:52:41.234203 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6603 23:52:41.240954 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6604 23:52:41.244276 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6605 23:52:41.247645 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6606 23:52:41.251121 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6607 23:52:41.257289 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6608 23:52:41.257399 ==
6609 23:52:41.260814 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 23:52:41.264078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 23:52:41.264184 ==
6612 23:52:41.264275 DQS Delay:
6613 23:52:41.267336 DQS0 = 60, DQS1 = 72
6614 23:52:41.267410 DQM Delay:
6615 23:52:41.270801 DQM0 = 11, DQM1 = 17
6616 23:52:41.270881 DQ Delay:
6617 23:52:41.273983 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6618 23:52:41.277589 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6619 23:52:41.281210 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6620 23:52:41.284375 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6621 23:52:41.284485
6622 23:52:41.284600
6623 23:52:41.290703 [DQSOSCAuto] RK1, (LSB)MR18= 0xc37a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6624 23:52:41.294052 CH0 RK1: MR19=C0C, MR18=C37A
6625 23:52:41.300698 CH0_RK1: MR19=0xC0C, MR18=0xC37A, DQSOSC=385, MR23=63, INC=398, DEC=265
6626 23:52:41.304111 [RxdqsGatingPostProcess] freq 400
6627 23:52:41.310446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6628 23:52:41.313484 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 23:52:41.317209 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 23:52:41.320188 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 23:52:41.323662 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 23:52:41.323745 best DQS0 dly(2T, 0.5T) = (0, 10)
6633 23:52:41.327021 best DQS1 dly(2T, 0.5T) = (0, 10)
6634 23:52:41.330215 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6635 23:52:41.333493 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6636 23:52:41.336535 Pre-setting of DQS Precalculation
6637 23:52:41.343670 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6638 23:52:41.343758 ==
6639 23:52:41.347118 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 23:52:41.350406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 23:52:41.350535 ==
6642 23:52:41.356809 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 23:52:41.363234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6644 23:52:41.366352 [CA 0] Center 36 (8~64) winsize 57
6645 23:52:41.366435 [CA 1] Center 36 (8~64) winsize 57
6646 23:52:41.369847 [CA 2] Center 36 (8~64) winsize 57
6647 23:52:41.373135 [CA 3] Center 36 (8~64) winsize 57
6648 23:52:41.376360 [CA 4] Center 36 (8~64) winsize 57
6649 23:52:41.379549 [CA 5] Center 36 (8~64) winsize 57
6650 23:52:41.379622
6651 23:52:41.383365 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6652 23:52:41.383465
6653 23:52:41.390242 [CATrainingPosCal] consider 1 rank data
6654 23:52:41.390320 u2DelayCellTimex100 = 270/100 ps
6655 23:52:41.392909 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:52:41.400083 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:52:41.403060 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:52:41.406468 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:52:41.409658 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:52:41.412933 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:52:41.413018
6662 23:52:41.415914 CA PerBit enable=1, Macro0, CA PI delay=36
6663 23:52:41.416020
6664 23:52:41.419303 [CBTSetCACLKResult] CA Dly = 36
6665 23:52:41.422608 CS Dly: 1 (0~32)
6666 23:52:41.422681 ==
6667 23:52:41.425987 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 23:52:41.429239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 23:52:41.429340 ==
6670 23:52:41.435686 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 23:52:41.439302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6672 23:52:41.442300 [CA 0] Center 36 (8~64) winsize 57
6673 23:52:41.445627 [CA 1] Center 36 (8~64) winsize 57
6674 23:52:41.448843 [CA 2] Center 36 (8~64) winsize 57
6675 23:52:41.452371 [CA 3] Center 36 (8~64) winsize 57
6676 23:52:41.455431 [CA 4] Center 36 (8~64) winsize 57
6677 23:52:41.459052 [CA 5] Center 36 (8~64) winsize 57
6678 23:52:41.459138
6679 23:52:41.462446 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6680 23:52:41.462534
6681 23:52:41.465877 [CATrainingPosCal] consider 2 rank data
6682 23:52:41.468673 u2DelayCellTimex100 = 270/100 ps
6683 23:52:41.472212 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 23:52:41.475999 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:52:41.482424 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:52:41.485633 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:52:41.488711 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:52:41.492339 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:52:41.492440
6690 23:52:41.495247 CA PerBit enable=1, Macro0, CA PI delay=36
6691 23:52:41.495335
6692 23:52:41.498418 [CBTSetCACLKResult] CA Dly = 36
6693 23:52:41.498501 CS Dly: 1 (0~32)
6694 23:52:41.498565
6695 23:52:41.502275 ----->DramcWriteLeveling(PI) begin...
6696 23:52:41.505568 ==
6697 23:52:41.508480 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 23:52:41.511874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 23:52:41.511969 ==
6700 23:52:41.515169 Write leveling (Byte 0): 40 => 8
6701 23:52:41.518547 Write leveling (Byte 1): 40 => 8
6702 23:52:41.522201 DramcWriteLeveling(PI) end<-----
6703 23:52:41.522296
6704 23:52:41.522362 ==
6705 23:52:41.525383 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 23:52:41.528875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 23:52:41.528998 ==
6708 23:52:41.532137 [Gating] SW mode calibration
6709 23:52:41.538198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6710 23:52:41.542022 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6711 23:52:41.548170 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 23:52:41.551678 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 23:52:41.558824 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 23:52:41.561388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 23:52:41.565099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 23:52:41.568128 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 23:52:41.574819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 23:52:41.578245 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 23:52:41.581275 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 23:52:41.584849 Total UI for P1: 0, mck2ui 16
6721 23:52:41.588093 best dqsien dly found for B0: ( 0, 14, 24)
6722 23:52:41.591688 Total UI for P1: 0, mck2ui 16
6723 23:52:41.594608 best dqsien dly found for B1: ( 0, 14, 24)
6724 23:52:41.598171 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6725 23:52:41.604476 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6726 23:52:41.604616
6727 23:52:41.607606 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 23:52:41.610973 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 23:52:41.614616 [Gating] SW calibration Done
6730 23:52:41.614699 ==
6731 23:52:41.617859 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 23:52:41.621077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 23:52:41.621159 ==
6734 23:52:41.624412 RX Vref Scan: 0
6735 23:52:41.624495
6736 23:52:41.624621 RX Vref 0 -> 0, step: 1
6737 23:52:41.624709
6738 23:52:41.627465 RX Delay -410 -> 252, step: 16
6739 23:52:41.630708 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6740 23:52:41.637592 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6741 23:52:41.640803 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6742 23:52:41.643852 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6743 23:52:41.650547 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6744 23:52:41.653752 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6745 23:52:41.657550 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6746 23:52:41.660741 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6747 23:52:41.667620 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6748 23:52:41.670366 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6749 23:52:41.673933 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6750 23:52:41.677513 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6751 23:52:41.683764 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6752 23:52:41.687046 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6753 23:52:41.690633 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6754 23:52:41.694052 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6755 23:52:41.697198 ==
6756 23:52:41.697289 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 23:52:41.703813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 23:52:41.703908 ==
6759 23:52:41.703974 DQS Delay:
6760 23:52:41.706925 DQS0 = 51, DQS1 = 67
6761 23:52:41.707008 DQM Delay:
6762 23:52:41.710371 DQM0 = 13, DQM1 = 19
6763 23:52:41.710473 DQ Delay:
6764 23:52:41.713628 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6765 23:52:41.716900 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6766 23:52:41.720109 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6767 23:52:41.723864 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6768 23:52:41.723955
6769 23:52:41.724021
6770 23:52:41.724080 ==
6771 23:52:41.727130 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 23:52:41.730472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 23:52:41.730563 ==
6774 23:52:41.730627
6775 23:52:41.730687
6776 23:52:41.733628 TX Vref Scan disable
6777 23:52:41.733712 == TX Byte 0 ==
6778 23:52:41.740190 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 23:52:41.743526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 23:52:41.743632 == TX Byte 1 ==
6781 23:52:41.750104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 23:52:41.753482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 23:52:41.753575 ==
6784 23:52:41.757051 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 23:52:41.760007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 23:52:41.760101 ==
6787 23:52:41.760167
6788 23:52:41.760226
6789 23:52:41.763238 TX Vref Scan disable
6790 23:52:41.763343 == TX Byte 0 ==
6791 23:52:41.770329 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 23:52:41.773035 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 23:52:41.773127 == TX Byte 1 ==
6794 23:52:41.780176 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 23:52:41.783075 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 23:52:41.783186
6797 23:52:41.783250 [DATLAT]
6798 23:52:41.786562 Freq=400, CH1 RK0
6799 23:52:41.786663
6800 23:52:41.786742 DATLAT Default: 0xf
6801 23:52:41.789949 0, 0xFFFF, sum = 0
6802 23:52:41.790032 1, 0xFFFF, sum = 0
6803 23:52:41.792915 2, 0xFFFF, sum = 0
6804 23:52:41.793031 3, 0xFFFF, sum = 0
6805 23:52:41.796696 4, 0xFFFF, sum = 0
6806 23:52:41.796779 5, 0xFFFF, sum = 0
6807 23:52:41.799890 6, 0xFFFF, sum = 0
6808 23:52:41.799975 7, 0xFFFF, sum = 0
6809 23:52:41.802974 8, 0xFFFF, sum = 0
6810 23:52:41.803073 9, 0xFFFF, sum = 0
6811 23:52:41.806268 10, 0xFFFF, sum = 0
6812 23:52:41.810148 11, 0xFFFF, sum = 0
6813 23:52:41.810271 12, 0xFFFF, sum = 0
6814 23:52:41.813046 13, 0x0, sum = 1
6815 23:52:41.813131 14, 0x0, sum = 2
6816 23:52:41.816581 15, 0x0, sum = 3
6817 23:52:41.816677 16, 0x0, sum = 4
6818 23:52:41.816743 best_step = 14
6819 23:52:41.816802
6820 23:52:41.819531 ==
6821 23:52:41.822748 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 23:52:41.826175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 23:52:41.826258 ==
6824 23:52:41.826323 RX Vref Scan: 1
6825 23:52:41.826383
6826 23:52:41.829711 RX Vref 0 -> 0, step: 1
6827 23:52:41.829792
6828 23:52:41.833199 RX Delay -375 -> 252, step: 8
6829 23:52:41.833280
6830 23:52:41.836412 Set Vref, RX VrefLevel [Byte0]: 58
6831 23:52:41.839550 [Byte1]: 52
6832 23:52:41.843697
6833 23:52:41.843778 Final RX Vref Byte 0 = 58 to rank0
6834 23:52:41.846375 Final RX Vref Byte 1 = 52 to rank0
6835 23:52:41.849818 Final RX Vref Byte 0 = 58 to rank1
6836 23:52:41.853532 Final RX Vref Byte 1 = 52 to rank1==
6837 23:52:41.856265 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 23:52:41.862908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 23:52:41.863007 ==
6840 23:52:41.863073 DQS Delay:
6841 23:52:41.866127 DQS0 = 56, DQS1 = 64
6842 23:52:41.866208 DQM Delay:
6843 23:52:41.866298 DQM0 = 13, DQM1 = 10
6844 23:52:41.869859 DQ Delay:
6845 23:52:41.873019 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6846 23:52:41.876498 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6847 23:52:41.876647 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6848 23:52:41.879969 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6849 23:52:41.883067
6850 23:52:41.883175
6851 23:52:41.889866 [DQSOSCAuto] RK0, (LSB)MR18= 0x5568, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6852 23:52:41.893083 CH1 RK0: MR19=C0C, MR18=5568
6853 23:52:41.899889 CH1_RK0: MR19=0xC0C, MR18=0x5568, DQSOSC=396, MR23=63, INC=376, DEC=251
6854 23:52:41.899979 ==
6855 23:52:41.902851 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 23:52:41.906080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 23:52:41.906162 ==
6858 23:52:41.909903 [Gating] SW mode calibration
6859 23:52:41.916038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6860 23:52:41.923216 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6861 23:52:41.926319 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 23:52:41.929374 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 23:52:41.935848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 23:52:41.939120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 23:52:41.942846 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 23:52:41.949376 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 23:52:41.952210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 23:52:41.955731 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 23:52:41.962314 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 23:52:41.962408 Total UI for P1: 0, mck2ui 16
6871 23:52:41.965787 best dqsien dly found for B0: ( 0, 14, 24)
6872 23:52:41.968906 Total UI for P1: 0, mck2ui 16
6873 23:52:41.972201 best dqsien dly found for B1: ( 0, 14, 24)
6874 23:52:41.978676 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6875 23:52:41.982042 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6876 23:52:41.982125
6877 23:52:41.985766 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 23:52:41.989131 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 23:52:41.992277 [Gating] SW calibration Done
6880 23:52:41.992360 ==
6881 23:52:41.995658 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 23:52:41.998766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 23:52:41.998849 ==
6884 23:52:42.002220 RX Vref Scan: 0
6885 23:52:42.002302
6886 23:52:42.002366 RX Vref 0 -> 0, step: 1
6887 23:52:42.002426
6888 23:52:42.005597 RX Delay -410 -> 252, step: 16
6889 23:52:42.012238 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6890 23:52:42.015830 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6891 23:52:42.018670 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6892 23:52:42.022060 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6893 23:52:42.028523 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6894 23:52:42.031730 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6895 23:52:42.035273 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6896 23:52:42.038944 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6897 23:52:42.045309 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6898 23:52:42.048518 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6899 23:52:42.051750 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6900 23:52:42.055150 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6901 23:52:42.061897 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6902 23:52:42.064736 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6903 23:52:42.068486 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6904 23:52:42.071741 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6905 23:52:42.075127 ==
6906 23:52:42.078108 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 23:52:42.081445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 23:52:42.081534 ==
6909 23:52:42.081599 DQS Delay:
6910 23:52:42.084819 DQS0 = 59, DQS1 = 59
6911 23:52:42.084899 DQM Delay:
6912 23:52:42.088041 DQM0 = 19, DQM1 = 13
6913 23:52:42.088120 DQ Delay:
6914 23:52:42.091473 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6915 23:52:42.094959 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6916 23:52:42.098351 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6917 23:52:42.101532 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6918 23:52:42.101614
6919 23:52:42.101677
6920 23:52:42.101735 ==
6921 23:52:42.104876 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 23:52:42.107982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 23:52:42.108066 ==
6924 23:52:42.108129
6925 23:52:42.108189
6926 23:52:42.111632 TX Vref Scan disable
6927 23:52:42.111712 == TX Byte 0 ==
6928 23:52:42.117931 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6929 23:52:42.121488 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6930 23:52:42.121591 == TX Byte 1 ==
6931 23:52:42.128013 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 23:52:42.131593 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 23:52:42.131677 ==
6934 23:52:42.134852 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 23:52:42.137933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 23:52:42.138015 ==
6937 23:52:42.138080
6938 23:52:42.138139
6939 23:52:42.141510 TX Vref Scan disable
6940 23:52:42.141590 == TX Byte 0 ==
6941 23:52:42.147919 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6942 23:52:42.151496 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6943 23:52:42.151583 == TX Byte 1 ==
6944 23:52:42.157731 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 23:52:42.161547 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 23:52:42.161636
6947 23:52:42.161701 [DATLAT]
6948 23:52:42.164530 Freq=400, CH1 RK1
6949 23:52:42.164635
6950 23:52:42.164699 DATLAT Default: 0xe
6951 23:52:42.168263 0, 0xFFFF, sum = 0
6952 23:52:42.168343 1, 0xFFFF, sum = 0
6953 23:52:42.170980 2, 0xFFFF, sum = 0
6954 23:52:42.171061 3, 0xFFFF, sum = 0
6955 23:52:42.174318 4, 0xFFFF, sum = 0
6956 23:52:42.174399 5, 0xFFFF, sum = 0
6957 23:52:42.177557 6, 0xFFFF, sum = 0
6958 23:52:42.177673 7, 0xFFFF, sum = 0
6959 23:52:42.181137 8, 0xFFFF, sum = 0
6960 23:52:42.181220 9, 0xFFFF, sum = 0
6961 23:52:42.184517 10, 0xFFFF, sum = 0
6962 23:52:42.187717 11, 0xFFFF, sum = 0
6963 23:52:42.187797 12, 0xFFFF, sum = 0
6964 23:52:42.190938 13, 0x0, sum = 1
6965 23:52:42.191019 14, 0x0, sum = 2
6966 23:52:42.191083 15, 0x0, sum = 3
6967 23:52:42.194289 16, 0x0, sum = 4
6968 23:52:42.194369 best_step = 14
6969 23:52:42.194431
6970 23:52:42.197719 ==
6971 23:52:42.197798 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 23:52:42.204488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 23:52:42.204614 ==
6974 23:52:42.204679 RX Vref Scan: 0
6975 23:52:42.204739
6976 23:52:42.207978 RX Vref 0 -> 0, step: 1
6977 23:52:42.208056
6978 23:52:42.210717 RX Delay -359 -> 252, step: 8
6979 23:52:42.217799 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6980 23:52:42.221309 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6981 23:52:42.224301 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6982 23:52:42.227860 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6983 23:52:42.234110 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6984 23:52:42.237481 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6985 23:52:42.240546 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6986 23:52:42.247798 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6987 23:52:42.250996 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6988 23:52:42.253884 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6989 23:52:42.257675 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6990 23:52:42.263690 iDelay=217, Bit 11, Center -64 (-319 ~ 192) 512
6991 23:52:42.267136 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6992 23:52:42.270913 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6993 23:52:42.274214 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6994 23:52:42.280486 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6995 23:52:42.280610 ==
6996 23:52:42.284238 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 23:52:42.286999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 23:52:42.287078 ==
6999 23:52:42.287140 DQS Delay:
7000 23:52:42.290597 DQS0 = 60, DQS1 = 64
7001 23:52:42.290677 DQM Delay:
7002 23:52:42.293699 DQM0 = 13, DQM1 = 10
7003 23:52:42.293811 DQ Delay:
7004 23:52:42.296863 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7005 23:52:42.300666 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7006 23:52:42.303803 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
7007 23:52:42.307367 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7008 23:52:42.307446
7009 23:52:42.307509
7010 23:52:42.314059 [DQSOSCAuto] RK1, (LSB)MR18= 0x78a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7011 23:52:42.317270 CH1 RK1: MR19=C0C, MR18=78A8
7012 23:52:42.323836 CH1_RK1: MR19=0xC0C, MR18=0x78A8, DQSOSC=388, MR23=63, INC=392, DEC=261
7013 23:52:42.327049 [RxdqsGatingPostProcess] freq 400
7014 23:52:42.333964 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7015 23:52:42.337240 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 23:52:42.337318 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 23:52:42.340511 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 23:52:42.343667 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 23:52:42.347194 best DQS0 dly(2T, 0.5T) = (0, 10)
7020 23:52:42.351385 best DQS1 dly(2T, 0.5T) = (0, 10)
7021 23:52:42.353810 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7022 23:52:42.357144 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7023 23:52:42.360451 Pre-setting of DQS Precalculation
7024 23:52:42.366782 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7025 23:52:42.373389 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7026 23:52:42.380080 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7027 23:52:42.380182
7028 23:52:42.380245
7029 23:52:42.383394 [Calibration Summary] 800 Mbps
7030 23:52:42.383482 CH 0, Rank 0
7031 23:52:42.386759 SW Impedance : PASS
7032 23:52:42.390088 DUTY Scan : NO K
7033 23:52:42.390222 ZQ Calibration : PASS
7034 23:52:42.393386 Jitter Meter : NO K
7035 23:52:42.397038 CBT Training : PASS
7036 23:52:42.397137 Write leveling : PASS
7037 23:52:42.400161 RX DQS gating : PASS
7038 23:52:42.400228 RX DQ/DQS(RDDQC) : PASS
7039 23:52:42.403371 TX DQ/DQS : PASS
7040 23:52:42.406740 RX DATLAT : PASS
7041 23:52:42.406824 RX DQ/DQS(Engine): PASS
7042 23:52:42.409813 TX OE : NO K
7043 23:52:42.409932 All Pass.
7044 23:52:42.410021
7045 23:52:42.413563 CH 0, Rank 1
7046 23:52:42.413643 SW Impedance : PASS
7047 23:52:42.416649 DUTY Scan : NO K
7048 23:52:42.419685 ZQ Calibration : PASS
7049 23:52:42.419765 Jitter Meter : NO K
7050 23:52:42.423219 CBT Training : PASS
7051 23:52:42.426367 Write leveling : NO K
7052 23:52:42.426467 RX DQS gating : PASS
7053 23:52:42.429788 RX DQ/DQS(RDDQC) : PASS
7054 23:52:42.433218 TX DQ/DQS : PASS
7055 23:52:42.433304 RX DATLAT : PASS
7056 23:52:42.436325 RX DQ/DQS(Engine): PASS
7057 23:52:42.439521 TX OE : NO K
7058 23:52:42.439629 All Pass.
7059 23:52:42.439722
7060 23:52:42.439807 CH 1, Rank 0
7061 23:52:42.443324 SW Impedance : PASS
7062 23:52:42.446360 DUTY Scan : NO K
7063 23:52:42.446443 ZQ Calibration : PASS
7064 23:52:42.450244 Jitter Meter : NO K
7065 23:52:42.453200 CBT Training : PASS
7066 23:52:42.453305 Write leveling : PASS
7067 23:52:42.456358 RX DQS gating : PASS
7068 23:52:42.456457 RX DQ/DQS(RDDQC) : PASS
7069 23:52:42.459601 TX DQ/DQS : PASS
7070 23:52:42.462753 RX DATLAT : PASS
7071 23:52:42.462862 RX DQ/DQS(Engine): PASS
7072 23:52:42.466385 TX OE : NO K
7073 23:52:42.466492 All Pass.
7074 23:52:42.466585
7075 23:52:42.469569 CH 1, Rank 1
7076 23:52:42.469678 SW Impedance : PASS
7077 23:52:42.472799 DUTY Scan : NO K
7078 23:52:42.476141 ZQ Calibration : PASS
7079 23:52:42.476242 Jitter Meter : NO K
7080 23:52:42.479485 CBT Training : PASS
7081 23:52:42.482522 Write leveling : NO K
7082 23:52:42.482626 RX DQS gating : PASS
7083 23:52:42.486342 RX DQ/DQS(RDDQC) : PASS
7084 23:52:42.489678 TX DQ/DQS : PASS
7085 23:52:42.489777 RX DATLAT : PASS
7086 23:52:42.492862 RX DQ/DQS(Engine): PASS
7087 23:52:42.496397 TX OE : NO K
7088 23:52:42.496495 All Pass.
7089 23:52:42.496593
7090 23:52:42.496685 DramC Write-DBI off
7091 23:52:42.499437 PER_BANK_REFRESH: Hybrid Mode
7092 23:52:42.502786 TX_TRACKING: ON
7093 23:52:42.509465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7094 23:52:42.513062 [FAST_K] Save calibration result to emmc
7095 23:52:42.519366 dramc_set_vcore_voltage set vcore to 725000
7096 23:52:42.519472 Read voltage for 1600, 0
7097 23:52:42.522414 Vio18 = 0
7098 23:52:42.522489 Vcore = 725000
7099 23:52:42.522552 Vdram = 0
7100 23:52:42.525909 Vddq = 0
7101 23:52:42.525992 Vmddr = 0
7102 23:52:42.529559 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7103 23:52:42.535834 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7104 23:52:42.539353 MEM_TYPE=3, freq_sel=13
7105 23:52:42.542460 sv_algorithm_assistance_LP4_3733
7106 23:52:42.546160 ============ PULL DRAM RESETB DOWN ============
7107 23:52:42.549238 ========== PULL DRAM RESETB DOWN end =========
7108 23:52:42.552370 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7109 23:52:42.555612 ===================================
7110 23:52:42.559058 LPDDR4 DRAM CONFIGURATION
7111 23:52:42.562630 ===================================
7112 23:52:42.565561 EX_ROW_EN[0] = 0x0
7113 23:52:42.565646 EX_ROW_EN[1] = 0x0
7114 23:52:42.569213 LP4Y_EN = 0x0
7115 23:52:42.569295 WORK_FSP = 0x1
7116 23:52:42.572432 WL = 0x5
7117 23:52:42.572539 RL = 0x5
7118 23:52:42.575664 BL = 0x2
7119 23:52:42.575745 RPST = 0x0
7120 23:52:42.579072 RD_PRE = 0x0
7121 23:52:42.582626 WR_PRE = 0x1
7122 23:52:42.582705 WR_PST = 0x1
7123 23:52:42.585896 DBI_WR = 0x0
7124 23:52:42.585971 DBI_RD = 0x0
7125 23:52:42.589015 OTF = 0x1
7126 23:52:42.592602 ===================================
7127 23:52:42.595293 ===================================
7128 23:52:42.595367 ANA top config
7129 23:52:42.598983 ===================================
7130 23:52:42.602352 DLL_ASYNC_EN = 0
7131 23:52:42.605534 ALL_SLAVE_EN = 0
7132 23:52:42.605607 NEW_RANK_MODE = 1
7133 23:52:42.609027 DLL_IDLE_MODE = 1
7134 23:52:42.612229 LP45_APHY_COMB_EN = 1
7135 23:52:42.615515 TX_ODT_DIS = 0
7136 23:52:42.615623 NEW_8X_MODE = 1
7137 23:52:42.618596 ===================================
7138 23:52:42.622171 ===================================
7139 23:52:42.625269 data_rate = 3200
7140 23:52:42.628499 CKR = 1
7141 23:52:42.631800 DQ_P2S_RATIO = 8
7142 23:52:42.635620 ===================================
7143 23:52:42.638752 CA_P2S_RATIO = 8
7144 23:52:42.642210 DQ_CA_OPEN = 0
7145 23:52:42.645356 DQ_SEMI_OPEN = 0
7146 23:52:42.645439 CA_SEMI_OPEN = 0
7147 23:52:42.648473 CA_FULL_RATE = 0
7148 23:52:42.652119 DQ_CKDIV4_EN = 0
7149 23:52:42.655673 CA_CKDIV4_EN = 0
7150 23:52:42.658254 CA_PREDIV_EN = 0
7151 23:52:42.661553 PH8_DLY = 12
7152 23:52:42.661637 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7153 23:52:42.665299 DQ_AAMCK_DIV = 4
7154 23:52:42.668771 CA_AAMCK_DIV = 4
7155 23:52:42.671687 CA_ADMCK_DIV = 4
7156 23:52:42.675661 DQ_TRACK_CA_EN = 0
7157 23:52:42.678929 CA_PICK = 1600
7158 23:52:42.681835 CA_MCKIO = 1600
7159 23:52:42.681917 MCKIO_SEMI = 0
7160 23:52:42.684918 PLL_FREQ = 3068
7161 23:52:42.688321 DQ_UI_PI_RATIO = 32
7162 23:52:42.691725 CA_UI_PI_RATIO = 0
7163 23:52:42.695121 ===================================
7164 23:52:42.698210 ===================================
7165 23:52:42.701834 memory_type:LPDDR4
7166 23:52:42.701916 GP_NUM : 10
7167 23:52:42.704880 SRAM_EN : 1
7168 23:52:42.708133 MD32_EN : 0
7169 23:52:42.711633 ===================================
7170 23:52:42.711714 [ANA_INIT] >>>>>>>>>>>>>>
7171 23:52:42.714833 <<<<<< [CONFIGURE PHASE]: ANA_TX
7172 23:52:42.718089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7173 23:52:42.721870 ===================================
7174 23:52:42.724495 data_rate = 3200,PCW = 0X7600
7175 23:52:42.728093 ===================================
7176 23:52:42.731349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7177 23:52:42.737828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 23:52:42.741075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 23:52:42.748098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7180 23:52:42.751026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7181 23:52:42.754492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7182 23:52:42.754589 [ANA_INIT] flow start
7183 23:52:42.757704 [ANA_INIT] PLL >>>>>>>>
7184 23:52:42.760914 [ANA_INIT] PLL <<<<<<<<
7185 23:52:42.760994 [ANA_INIT] MIDPI >>>>>>>>
7186 23:52:42.764493 [ANA_INIT] MIDPI <<<<<<<<
7187 23:52:42.767939 [ANA_INIT] DLL >>>>>>>>
7188 23:52:42.771147 [ANA_INIT] DLL <<<<<<<<
7189 23:52:42.771227 [ANA_INIT] flow end
7190 23:52:42.774524 ============ LP4 DIFF to SE enter ============
7191 23:52:42.780938 ============ LP4 DIFF to SE exit ============
7192 23:52:42.781022 [ANA_INIT] <<<<<<<<<<<<<
7193 23:52:42.784363 [Flow] Enable top DCM control >>>>>
7194 23:52:42.787757 [Flow] Enable top DCM control <<<<<
7195 23:52:42.791094 Enable DLL master slave shuffle
7196 23:52:42.797491 ==============================================================
7197 23:52:42.797571 Gating Mode config
7198 23:52:42.804129 ==============================================================
7199 23:52:42.807487 Config description:
7200 23:52:42.817408 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7201 23:52:42.824181 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7202 23:52:42.827395 SELPH_MODE 0: By rank 1: By Phase
7203 23:52:42.834092 ==============================================================
7204 23:52:42.837481 GAT_TRACK_EN = 1
7205 23:52:42.837560 RX_GATING_MODE = 2
7206 23:52:42.840554 RX_GATING_TRACK_MODE = 2
7207 23:52:42.843920 SELPH_MODE = 1
7208 23:52:42.847769 PICG_EARLY_EN = 1
7209 23:52:42.850501 VALID_LAT_VALUE = 1
7210 23:52:42.857351 ==============================================================
7211 23:52:42.860464 Enter into Gating configuration >>>>
7212 23:52:42.863492 Exit from Gating configuration <<<<
7213 23:52:42.867113 Enter into DVFS_PRE_config >>>>>
7214 23:52:42.877137 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7215 23:52:42.880378 Exit from DVFS_PRE_config <<<<<
7216 23:52:42.883689 Enter into PICG configuration >>>>
7217 23:52:42.886894 Exit from PICG configuration <<<<
7218 23:52:42.890448 [RX_INPUT] configuration >>>>>
7219 23:52:42.893688 [RX_INPUT] configuration <<<<<
7220 23:52:42.897312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7221 23:52:42.903468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7222 23:52:42.910442 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 23:52:42.916733 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 23:52:42.920340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 23:52:42.927114 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 23:52:42.930464 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7227 23:52:42.936693 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7228 23:52:42.939697 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7229 23:52:42.943081 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7230 23:52:42.946258 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7231 23:52:42.952719 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 23:52:42.956367 ===================================
7233 23:52:42.959592 LPDDR4 DRAM CONFIGURATION
7234 23:52:42.963291 ===================================
7235 23:52:42.963370 EX_ROW_EN[0] = 0x0
7236 23:52:42.966506 EX_ROW_EN[1] = 0x0
7237 23:52:42.966585 LP4Y_EN = 0x0
7238 23:52:42.969451 WORK_FSP = 0x1
7239 23:52:42.969531 WL = 0x5
7240 23:52:42.973057 RL = 0x5
7241 23:52:42.973136 BL = 0x2
7242 23:52:42.976415 RPST = 0x0
7243 23:52:42.976494 RD_PRE = 0x0
7244 23:52:42.979558 WR_PRE = 0x1
7245 23:52:42.979636 WR_PST = 0x1
7246 23:52:42.982849 DBI_WR = 0x0
7247 23:52:42.982928 DBI_RD = 0x0
7248 23:52:42.986206 OTF = 0x1
7249 23:52:42.989702 ===================================
7250 23:52:42.992768 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7251 23:52:42.996045 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7252 23:52:43.002655 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 23:52:43.006078 ===================================
7254 23:52:43.006157 LPDDR4 DRAM CONFIGURATION
7255 23:52:43.009541 ===================================
7256 23:52:43.012513 EX_ROW_EN[0] = 0x10
7257 23:52:43.016343 EX_ROW_EN[1] = 0x0
7258 23:52:43.016421 LP4Y_EN = 0x0
7259 23:52:43.019370 WORK_FSP = 0x1
7260 23:52:43.019450 WL = 0x5
7261 23:52:43.022871 RL = 0x5
7262 23:52:43.022950 BL = 0x2
7263 23:52:43.025721 RPST = 0x0
7264 23:52:43.025800 RD_PRE = 0x0
7265 23:52:43.029141 WR_PRE = 0x1
7266 23:52:43.029219 WR_PST = 0x1
7267 23:52:43.032201 DBI_WR = 0x0
7268 23:52:43.032279 DBI_RD = 0x0
7269 23:52:43.035721 OTF = 0x1
7270 23:52:43.038984 ===================================
7271 23:52:43.045811 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7272 23:52:43.045890 ==
7273 23:52:43.048878 Dram Type= 6, Freq= 0, CH_0, rank 0
7274 23:52:43.052280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 23:52:43.052359 ==
7276 23:52:43.055762 [Duty_Offset_Calibration]
7277 23:52:43.055841 B0:2 B1:0 CA:3
7278 23:52:43.055904
7279 23:52:43.059078 [DutyScan_Calibration_Flow] k_type=0
7280 23:52:43.070190
7281 23:52:43.070271 ==CLK 0==
7282 23:52:43.073344 Final CLK duty delay cell = 0
7283 23:52:43.076485 [0] MAX Duty = 5031%(X100), DQS PI = 12
7284 23:52:43.079829 [0] MIN Duty = 4875%(X100), DQS PI = 54
7285 23:52:43.079908 [0] AVG Duty = 4953%(X100)
7286 23:52:43.083349
7287 23:52:43.086802 CH0 CLK Duty spec in!! Max-Min= 156%
7288 23:52:43.089964 [DutyScan_Calibration_Flow] ====Done====
7289 23:52:43.090044
7290 23:52:43.093257 [DutyScan_Calibration_Flow] k_type=1
7291 23:52:43.110327
7292 23:52:43.110407 ==DQS 0 ==
7293 23:52:43.113869 Final DQS duty delay cell = 0
7294 23:52:43.116697 [0] MAX Duty = 5125%(X100), DQS PI = 30
7295 23:52:43.120285 [0] MIN Duty = 4875%(X100), DQS PI = 48
7296 23:52:43.123823 [0] AVG Duty = 5000%(X100)
7297 23:52:43.123902
7298 23:52:43.123964 ==DQS 1 ==
7299 23:52:43.126366 Final DQS duty delay cell = 0
7300 23:52:43.129888 [0] MAX Duty = 5156%(X100), DQS PI = 32
7301 23:52:43.133494 [0] MIN Duty = 5031%(X100), DQS PI = 14
7302 23:52:43.136485 [0] AVG Duty = 5093%(X100)
7303 23:52:43.136586
7304 23:52:43.139735 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7305 23:52:43.139814
7306 23:52:43.143235 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7307 23:52:43.146714 [DutyScan_Calibration_Flow] ====Done====
7308 23:52:43.146794
7309 23:52:43.149760 [DutyScan_Calibration_Flow] k_type=3
7310 23:52:43.168064
7311 23:52:43.168211 ==DQM 0 ==
7312 23:52:43.171347 Final DQM duty delay cell = 0
7313 23:52:43.174412 [0] MAX Duty = 5156%(X100), DQS PI = 30
7314 23:52:43.177921 [0] MIN Duty = 4875%(X100), DQS PI = 0
7315 23:52:43.181104 [0] AVG Duty = 5015%(X100)
7316 23:52:43.181184
7317 23:52:43.181247 ==DQM 1 ==
7318 23:52:43.184477 Final DQM duty delay cell = 4
7319 23:52:43.187825 [4] MAX Duty = 5187%(X100), DQS PI = 62
7320 23:52:43.191155 [4] MIN Duty = 5031%(X100), DQS PI = 12
7321 23:52:43.194609 [4] AVG Duty = 5109%(X100)
7322 23:52:43.194689
7323 23:52:43.198023 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7324 23:52:43.198102
7325 23:52:43.201256 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7326 23:52:43.204577 [DutyScan_Calibration_Flow] ====Done====
7327 23:52:43.204671
7328 23:52:43.207712 [DutyScan_Calibration_Flow] k_type=2
7329 23:52:43.224480
7330 23:52:43.224585 ==DQ 0 ==
7331 23:52:43.227654 Final DQ duty delay cell = -4
7332 23:52:43.231282 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7333 23:52:43.234512 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7334 23:52:43.238115 [-4] AVG Duty = 4938%(X100)
7335 23:52:43.238194
7336 23:52:43.238257 ==DQ 1 ==
7337 23:52:43.241039 Final DQ duty delay cell = 0
7338 23:52:43.244185 [0] MAX Duty = 5156%(X100), DQS PI = 60
7339 23:52:43.247859 [0] MIN Duty = 5000%(X100), DQS PI = 14
7340 23:52:43.250770 [0] AVG Duty = 5078%(X100)
7341 23:52:43.250849
7342 23:52:43.254286 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7343 23:52:43.254365
7344 23:52:43.257384 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7345 23:52:43.260701 [DutyScan_Calibration_Flow] ====Done====
7346 23:52:43.260807 ==
7347 23:52:43.264037 Dram Type= 6, Freq= 0, CH_1, rank 0
7348 23:52:43.267393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7349 23:52:43.267474 ==
7350 23:52:43.270793 [Duty_Offset_Calibration]
7351 23:52:43.270878 B0:0 B1:-2 CA:1
7352 23:52:43.270982
7353 23:52:43.274192 [DutyScan_Calibration_Flow] k_type=0
7354 23:52:43.284977
7355 23:52:43.285056 ==CLK 0==
7356 23:52:43.288554 Final CLK duty delay cell = 0
7357 23:52:43.291721 [0] MAX Duty = 5062%(X100), DQS PI = 20
7358 23:52:43.295132 [0] MIN Duty = 4844%(X100), DQS PI = 58
7359 23:52:43.298394 [0] AVG Duty = 4953%(X100)
7360 23:52:43.298474
7361 23:52:43.301853 CH1 CLK Duty spec in!! Max-Min= 218%
7362 23:52:43.305612 [DutyScan_Calibration_Flow] ====Done====
7363 23:52:43.305717
7364 23:52:43.307813 [DutyScan_Calibration_Flow] k_type=1
7365 23:52:43.324344
7366 23:52:43.324428 ==DQS 0 ==
7367 23:52:43.327627 Final DQS duty delay cell = -4
7368 23:52:43.330778 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7369 23:52:43.333929 [-4] MIN Duty = 4813%(X100), DQS PI = 52
7370 23:52:43.337083 [-4] AVG Duty = 4906%(X100)
7371 23:52:43.337163
7372 23:52:43.337225 ==DQS 1 ==
7373 23:52:43.340504 Final DQS duty delay cell = 0
7374 23:52:43.343864 [0] MAX Duty = 5093%(X100), DQS PI = 58
7375 23:52:43.347222 [0] MIN Duty = 4844%(X100), DQS PI = 26
7376 23:52:43.350474 [0] AVG Duty = 4968%(X100)
7377 23:52:43.350553
7378 23:52:43.353727 CH1 DQS 0 Duty spec in!! Max-Min= 187%
7379 23:52:43.353806
7380 23:52:43.357254 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7381 23:52:43.360429 [DutyScan_Calibration_Flow] ====Done====
7382 23:52:43.360508
7383 23:52:43.363863 [DutyScan_Calibration_Flow] k_type=3
7384 23:52:43.381265
7385 23:52:43.381389 ==DQM 0 ==
7386 23:52:43.384498 Final DQM duty delay cell = 0
7387 23:52:43.387874 [0] MAX Duty = 5031%(X100), DQS PI = 24
7388 23:52:43.391178 [0] MIN Duty = 4782%(X100), DQS PI = 58
7389 23:52:43.394392 [0] AVG Duty = 4906%(X100)
7390 23:52:43.394471
7391 23:52:43.394534 ==DQM 1 ==
7392 23:52:43.397860 Final DQM duty delay cell = 0
7393 23:52:43.401156 [0] MAX Duty = 5093%(X100), DQS PI = 36
7394 23:52:43.404417 [0] MIN Duty = 4875%(X100), DQS PI = 24
7395 23:52:43.407937 [0] AVG Duty = 4984%(X100)
7396 23:52:43.408016
7397 23:52:43.410983 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7398 23:52:43.411062
7399 23:52:43.414389 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7400 23:52:43.417469 [DutyScan_Calibration_Flow] ====Done====
7401 23:52:43.417547
7402 23:52:43.421004 [DutyScan_Calibration_Flow] k_type=2
7403 23:52:43.438083
7404 23:52:43.438162 ==DQ 0 ==
7405 23:52:43.441792 Final DQ duty delay cell = 0
7406 23:52:43.444602 [0] MAX Duty = 5093%(X100), DQS PI = 20
7407 23:52:43.448328 [0] MIN Duty = 4907%(X100), DQS PI = 56
7408 23:52:43.448407 [0] AVG Duty = 5000%(X100)
7409 23:52:43.451501
7410 23:52:43.451579 ==DQ 1 ==
7411 23:52:43.455116 Final DQ duty delay cell = 0
7412 23:52:43.458373 [0] MAX Duty = 5125%(X100), DQS PI = 34
7413 23:52:43.461508 [0] MIN Duty = 4938%(X100), DQS PI = 24
7414 23:52:43.461587 [0] AVG Duty = 5031%(X100)
7415 23:52:43.461650
7416 23:52:43.468154 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7417 23:52:43.468233
7418 23:52:43.471116 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7419 23:52:43.474463 [DutyScan_Calibration_Flow] ====Done====
7420 23:52:43.477874 nWR fixed to 30
7421 23:52:43.477954 [ModeRegInit_LP4] CH0 RK0
7422 23:52:43.481220 [ModeRegInit_LP4] CH0 RK1
7423 23:52:43.484506 [ModeRegInit_LP4] CH1 RK0
7424 23:52:43.487648 [ModeRegInit_LP4] CH1 RK1
7425 23:52:43.487728 match AC timing 5
7426 23:52:43.494447 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7427 23:52:43.497651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7428 23:52:43.501047 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7429 23:52:43.507593 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7430 23:52:43.510862 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7431 23:52:43.510940 [MiockJmeterHQA]
7432 23:52:43.511002
7433 23:52:43.514200 [DramcMiockJmeter] u1RxGatingPI = 0
7434 23:52:43.517887 0 : 4363, 4137
7435 23:52:43.517966 4 : 4252, 4027
7436 23:52:43.520977 8 : 4252, 4027
7437 23:52:43.521056 12 : 4253, 4027
7438 23:52:43.521119 16 : 4252, 4027
7439 23:52:43.524392 20 : 4363, 4137
7440 23:52:43.524471 24 : 4253, 4027
7441 23:52:43.527862 28 : 4363, 4138
7442 23:52:43.527941 32 : 4252, 4027
7443 23:52:43.531328 36 : 4252, 4027
7444 23:52:43.531408 40 : 4253, 4027
7445 23:52:43.534326 44 : 4254, 4029
7446 23:52:43.534406 48 : 4363, 4137
7447 23:52:43.534469 52 : 4252, 4027
7448 23:52:43.537423 56 : 4363, 4137
7449 23:52:43.537503 60 : 4250, 4027
7450 23:52:43.541137 64 : 4250, 4026
7451 23:52:43.541217 68 : 4250, 4026
7452 23:52:43.544669 72 : 4361, 4137
7453 23:52:43.544748 76 : 4250, 4027
7454 23:52:43.544811 80 : 4361, 4137
7455 23:52:43.547558 84 : 4250, 4027
7456 23:52:43.547638 88 : 4250, 4026
7457 23:52:43.550848 92 : 4250, 4027
7458 23:52:43.550927 96 : 4252, 4029
7459 23:52:43.554031 100 : 4361, 4137
7460 23:52:43.554111 104 : 4250, 3593
7461 23:52:43.557356 108 : 4250, 5
7462 23:52:43.557436 112 : 4250, 0
7463 23:52:43.557500 116 : 4250, 0
7464 23:52:43.560933 120 : 4252, 0
7465 23:52:43.561012 124 : 4252, 0
7466 23:52:43.564004 128 : 4250, 0
7467 23:52:43.564084 132 : 4253, 0
7468 23:52:43.564148 136 : 4252, 0
7469 23:52:43.567693 140 : 4250, 0
7470 23:52:43.567772 144 : 4253, 0
7471 23:52:43.570975 148 : 4363, 0
7472 23:52:43.571057 152 : 4361, 0
7473 23:52:43.571157 156 : 4363, 0
7474 23:52:43.573791 160 : 4252, 0
7475 23:52:43.573884 164 : 4361, 0
7476 23:52:43.573948 168 : 4250, 0
7477 23:52:43.577509 172 : 4252, 0
7478 23:52:43.577588 176 : 4252, 0
7479 23:52:43.580895 180 : 4250, 0
7480 23:52:43.580975 184 : 4252, 0
7481 23:52:43.581038 188 : 4252, 0
7482 23:52:43.583828 192 : 4250, 0
7483 23:52:43.583907 196 : 4252, 0
7484 23:52:43.587399 200 : 4363, 0
7485 23:52:43.587514 204 : 4361, 0
7486 23:52:43.587579 208 : 4363, 0
7487 23:52:43.590587 212 : 4252, 0
7488 23:52:43.590667 216 : 4361, 0
7489 23:52:43.594219 220 : 4250, 0
7490 23:52:43.594299 224 : 4252, 0
7491 23:52:43.594362 228 : 4252, 0
7492 23:52:43.597242 232 : 4250, 0
7493 23:52:43.597348 236 : 4252, 1081
7494 23:52:43.600351 240 : 4250, 4027
7495 23:52:43.600449 244 : 4360, 4137
7496 23:52:43.603470 248 : 4361, 4137
7497 23:52:43.603586 252 : 4248, 4025
7498 23:52:43.607315 256 : 4363, 4139
7499 23:52:43.607395 260 : 4250, 4027
7500 23:52:43.607459 264 : 4250, 4027
7501 23:52:43.610552 268 : 4250, 4027
7502 23:52:43.610666 272 : 4253, 4029
7503 23:52:43.613635 276 : 4250, 4027
7504 23:52:43.613715 280 : 4249, 4027
7505 23:52:43.616933 284 : 4250, 4027
7506 23:52:43.617013 288 : 4252, 4029
7507 23:52:43.620033 292 : 4250, 4027
7508 23:52:43.620112 296 : 4360, 4138
7509 23:52:43.623454 300 : 4361, 4137
7510 23:52:43.623602 304 : 4250, 4026
7511 23:52:43.627153 308 : 4363, 4139
7512 23:52:43.627262 312 : 4250, 4027
7513 23:52:43.630475 316 : 4250, 4027
7514 23:52:43.630555 320 : 4250, 4027
7515 23:52:43.630618 324 : 4252, 4029
7516 23:52:43.633917 328 : 4250, 4027
7517 23:52:43.633997 332 : 4250, 4027
7518 23:52:43.637404 336 : 4250, 4027
7519 23:52:43.637484 340 : 4252, 4030
7520 23:52:43.640356 344 : 4250, 4027
7521 23:52:43.640435 348 : 4360, 4138
7522 23:52:43.643541 352 : 4361, 4105
7523 23:52:43.643620 356 : 4250, 2864
7524 23:52:43.646918 360 : 4363, 2
7525 23:52:43.646998
7526 23:52:43.647060 MIOCK jitter meter ch=0
7527 23:52:43.647118
7528 23:52:43.650098 1T = (360-108) = 252 dly cells
7529 23:52:43.656522 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7530 23:52:43.656646 ==
7531 23:52:43.659936 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 23:52:43.663106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 23:52:43.663207 ==
7534 23:52:43.670188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 23:52:43.673520 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 23:52:43.677084 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 23:52:43.683393 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 23:52:43.693157 [CA 0] Center 44 (14~75) winsize 62
7539 23:52:43.696702 [CA 1] Center 43 (13~74) winsize 62
7540 23:52:43.699923 [CA 2] Center 40 (11~69) winsize 59
7541 23:52:43.703355 [CA 3] Center 39 (10~68) winsize 59
7542 23:52:43.706197 [CA 4] Center 37 (8~67) winsize 60
7543 23:52:43.709503 [CA 5] Center 37 (7~67) winsize 61
7544 23:52:43.709607
7545 23:52:43.712739 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 23:52:43.712818
7547 23:52:43.719812 [CATrainingPosCal] consider 1 rank data
7548 23:52:43.719891 u2DelayCellTimex100 = 258/100 ps
7549 23:52:43.726280 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7550 23:52:43.729495 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7551 23:52:43.733277 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7552 23:52:43.736212 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7553 23:52:43.739364 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7554 23:52:43.743030 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7555 23:52:43.743110
7556 23:52:43.746247 CA PerBit enable=1, Macro0, CA PI delay=37
7557 23:52:43.746326
7558 23:52:43.749495 [CBTSetCACLKResult] CA Dly = 37
7559 23:52:43.752989 CS Dly: 11 (0~42)
7560 23:52:43.756148 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 23:52:43.759592 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 23:52:43.759671 ==
7563 23:52:43.762763 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 23:52:43.769479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 23:52:43.769561 ==
7566 23:52:43.772534 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 23:52:43.779653 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 23:52:43.782763 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 23:52:43.789205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 23:52:43.796900 [CA 0] Center 44 (14~75) winsize 62
7571 23:52:43.800397 [CA 1] Center 43 (13~74) winsize 62
7572 23:52:43.803788 [CA 2] Center 39 (10~69) winsize 60
7573 23:52:43.807283 [CA 3] Center 38 (9~68) winsize 60
7574 23:52:43.810730 [CA 4] Center 37 (8~67) winsize 60
7575 23:52:43.813849 [CA 5] Center 36 (7~66) winsize 60
7576 23:52:43.813928
7577 23:52:43.816728 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 23:52:43.816807
7579 23:52:43.820644 [CATrainingPosCal] consider 2 rank data
7580 23:52:43.823915 u2DelayCellTimex100 = 258/100 ps
7581 23:52:43.827279 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7582 23:52:43.833578 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7583 23:52:43.836763 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7584 23:52:43.840039 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7585 23:52:43.843299 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7586 23:52:43.846826 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7587 23:52:43.846905
7588 23:52:43.850285 CA PerBit enable=1, Macro0, CA PI delay=36
7589 23:52:43.850363
7590 23:52:43.853375 [CBTSetCACLKResult] CA Dly = 36
7591 23:52:43.856909 CS Dly: 11 (0~43)
7592 23:52:43.860134 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 23:52:43.863420 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 23:52:43.863499
7595 23:52:43.866618 ----->DramcWriteLeveling(PI) begin...
7596 23:52:43.866693 ==
7597 23:52:43.869869 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 23:52:43.876895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 23:52:43.876975 ==
7600 23:52:43.879948 Write leveling (Byte 0): 39 => 39
7601 23:52:43.883218 Write leveling (Byte 1): 29 => 29
7602 23:52:43.883323 DramcWriteLeveling(PI) end<-----
7603 23:52:43.883412
7604 23:52:43.886241 ==
7605 23:52:43.889973 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 23:52:43.892896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 23:52:43.892976 ==
7608 23:52:43.896732 [Gating] SW mode calibration
7609 23:52:43.902902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 23:52:43.906359 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 23:52:43.912863 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 23:52:43.916316 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 23:52:43.919418 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 23:52:43.926096 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 23:52:43.929368 1 4 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7616 23:52:43.932719 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7617 23:52:43.939361 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7618 23:52:43.942582 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 23:52:43.946450 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 23:52:43.952844 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 23:52:43.956335 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 23:52:43.959122 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7623 23:52:43.965912 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7624 23:52:43.969242 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7625 23:52:43.972424 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7626 23:52:43.978867 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 23:52:43.982092 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 23:52:43.985844 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 23:52:43.992013 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 23:52:43.995217 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7631 23:52:43.998731 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7632 23:52:44.005403 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7633 23:52:44.008737 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7634 23:52:44.012307 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 23:52:44.018501 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 23:52:44.022006 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 23:52:44.024894 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 23:52:44.031744 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 23:52:44.035280 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7640 23:52:44.038377 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7641 23:52:44.045406 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7642 23:52:44.048575 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:52:44.051846 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:52:44.058832 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:52:44.061487 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:52:44.065420 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:52:44.071457 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:52:44.075309 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:52:44.078138 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:52:44.084718 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:52:44.088181 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:52:44.091451 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:52:44.098284 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 23:52:44.101477 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 23:52:44.104961 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7656 23:52:44.108464 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7657 23:52:44.111737 Total UI for P1: 0, mck2ui 16
7658 23:52:44.114748 best dqsien dly found for B0: ( 1, 9, 14)
7659 23:52:44.121582 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7660 23:52:44.125063 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 23:52:44.128222 Total UI for P1: 0, mck2ui 16
7662 23:52:44.131255 best dqsien dly found for B1: ( 1, 9, 22)
7663 23:52:44.134851 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7664 23:52:44.138188 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7665 23:52:44.138296
7666 23:52:44.141100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7667 23:52:44.148222 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7668 23:52:44.148303 [Gating] SW calibration Done
7669 23:52:44.148367 ==
7670 23:52:44.151560 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 23:52:44.158343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 23:52:44.158424 ==
7673 23:52:44.158486 RX Vref Scan: 0
7674 23:52:44.158544
7675 23:52:44.161473 RX Vref 0 -> 0, step: 1
7676 23:52:44.161552
7677 23:52:44.164479 RX Delay 0 -> 252, step: 8
7678 23:52:44.167896 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7679 23:52:44.171179 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7680 23:52:44.174551 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7681 23:52:44.181140 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7682 23:52:44.184667 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7683 23:52:44.187683 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7684 23:52:44.190933 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7685 23:52:44.194627 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7686 23:52:44.197761 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7687 23:52:44.204391 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7688 23:52:44.207577 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7689 23:52:44.211024 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7690 23:52:44.214413 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7691 23:52:44.220941 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7692 23:52:44.224038 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7693 23:52:44.227511 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7694 23:52:44.227594 ==
7695 23:52:44.230823 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 23:52:44.234179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 23:52:44.234261 ==
7698 23:52:44.237330 DQS Delay:
7699 23:52:44.237411 DQS0 = 0, DQS1 = 0
7700 23:52:44.240729 DQM Delay:
7701 23:52:44.240810 DQM0 = 128, DQM1 = 124
7702 23:52:44.243829 DQ Delay:
7703 23:52:44.248034 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7704 23:52:44.250387 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7705 23:52:44.254309 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7706 23:52:44.257200 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7707 23:52:44.257289
7708 23:52:44.257352
7709 23:52:44.257410 ==
7710 23:52:44.260553 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 23:52:44.263633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 23:52:44.263714 ==
7713 23:52:44.263778
7714 23:52:44.263836
7715 23:52:44.267066 TX Vref Scan disable
7716 23:52:44.270324 == TX Byte 0 ==
7717 23:52:44.273691 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
7718 23:52:44.277050 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
7719 23:52:44.280303 == TX Byte 1 ==
7720 23:52:44.283793 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7721 23:52:44.287018 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7722 23:52:44.287100 ==
7723 23:52:44.290353 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 23:52:44.296662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 23:52:44.296751 ==
7726 23:52:44.309714
7727 23:52:44.312874 TX Vref early break, caculate TX vref
7728 23:52:44.316404 TX Vref=16, minBit 8, minWin=22, winSum=371
7729 23:52:44.319317 TX Vref=18, minBit 8, minWin=22, winSum=378
7730 23:52:44.322765 TX Vref=20, minBit 8, minWin=23, winSum=382
7731 23:52:44.325996 TX Vref=22, minBit 7, minWin=24, winSum=393
7732 23:52:44.329429 TX Vref=24, minBit 8, minWin=24, winSum=407
7733 23:52:44.336228 TX Vref=26, minBit 1, minWin=25, winSum=410
7734 23:52:44.339160 TX Vref=28, minBit 3, minWin=25, winSum=411
7735 23:52:44.342829 TX Vref=30, minBit 9, minWin=23, winSum=400
7736 23:52:44.345784 TX Vref=32, minBit 12, minWin=23, winSum=395
7737 23:52:44.349255 TX Vref=34, minBit 8, minWin=22, winSum=384
7738 23:52:44.355855 [TxChooseVref] Worse bit 3, Min win 25, Win sum 411, Final Vref 28
7739 23:52:44.355954
7740 23:52:44.359119 Final TX Range 0 Vref 28
7741 23:52:44.359229
7742 23:52:44.359320 ==
7743 23:52:44.362810 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 23:52:44.366043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 23:52:44.366134 ==
7746 23:52:44.366198
7747 23:52:44.366257
7748 23:52:44.369171 TX Vref Scan disable
7749 23:52:44.375826 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7750 23:52:44.375923 == TX Byte 0 ==
7751 23:52:44.379273 u2DelayCellOfst[0]=7 cells (2 PI)
7752 23:52:44.382406 u2DelayCellOfst[1]=11 cells (3 PI)
7753 23:52:44.386137 u2DelayCellOfst[2]=7 cells (2 PI)
7754 23:52:44.388896 u2DelayCellOfst[3]=7 cells (2 PI)
7755 23:52:44.392321 u2DelayCellOfst[4]=3 cells (1 PI)
7756 23:52:44.395912 u2DelayCellOfst[5]=0 cells (0 PI)
7757 23:52:44.398904 u2DelayCellOfst[6]=15 cells (4 PI)
7758 23:52:44.402395 u2DelayCellOfst[7]=11 cells (3 PI)
7759 23:52:44.405507 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7760 23:52:44.408730 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
7761 23:52:44.412295 == TX Byte 1 ==
7762 23:52:44.412380 u2DelayCellOfst[8]=0 cells (0 PI)
7763 23:52:44.415423 u2DelayCellOfst[9]=0 cells (0 PI)
7764 23:52:44.419008 u2DelayCellOfst[10]=7 cells (2 PI)
7765 23:52:44.422280 u2DelayCellOfst[11]=3 cells (1 PI)
7766 23:52:44.425574 u2DelayCellOfst[12]=11 cells (3 PI)
7767 23:52:44.428991 u2DelayCellOfst[13]=11 cells (3 PI)
7768 23:52:44.432293 u2DelayCellOfst[14]=18 cells (5 PI)
7769 23:52:44.436075 u2DelayCellOfst[15]=11 cells (3 PI)
7770 23:52:44.438923 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7771 23:52:44.445566 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7772 23:52:44.445668 DramC Write-DBI on
7773 23:52:44.445733 ==
7774 23:52:44.448735 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 23:52:44.452021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 23:52:44.455417 ==
7777 23:52:44.455516
7778 23:52:44.455579
7779 23:52:44.455638 TX Vref Scan disable
7780 23:52:44.458823 == TX Byte 0 ==
7781 23:52:44.462027 Update DQM dly =740 (2 ,6, 36) DQM OEN =(3 ,3)
7782 23:52:44.465566 == TX Byte 1 ==
7783 23:52:44.468980 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7784 23:52:44.472183 DramC Write-DBI off
7785 23:52:44.472273
7786 23:52:44.472337 [DATLAT]
7787 23:52:44.472396 Freq=1600, CH0 RK0
7788 23:52:44.472453
7789 23:52:44.475414 DATLAT Default: 0xf
7790 23:52:44.475502 0, 0xFFFF, sum = 0
7791 23:52:44.478650 1, 0xFFFF, sum = 0
7792 23:52:44.482097 2, 0xFFFF, sum = 0
7793 23:52:44.482185 3, 0xFFFF, sum = 0
7794 23:52:44.485729 4, 0xFFFF, sum = 0
7795 23:52:44.485827 5, 0xFFFF, sum = 0
7796 23:52:44.488971 6, 0xFFFF, sum = 0
7797 23:52:44.489062 7, 0xFFFF, sum = 0
7798 23:52:44.492608 8, 0xFFFF, sum = 0
7799 23:52:44.492695 9, 0xFFFF, sum = 0
7800 23:52:44.495673 10, 0xFFFF, sum = 0
7801 23:52:44.495757 11, 0xFFFF, sum = 0
7802 23:52:44.498556 12, 0xFFFF, sum = 0
7803 23:52:44.498640 13, 0xFFFF, sum = 0
7804 23:52:44.501975 14, 0x0, sum = 1
7805 23:52:44.502066 15, 0x0, sum = 2
7806 23:52:44.505321 16, 0x0, sum = 3
7807 23:52:44.505406 17, 0x0, sum = 4
7808 23:52:44.508563 best_step = 15
7809 23:52:44.508648
7810 23:52:44.508712 ==
7811 23:52:44.512090 Dram Type= 6, Freq= 0, CH_0, rank 0
7812 23:52:44.515574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7813 23:52:44.515663 ==
7814 23:52:44.518405 RX Vref Scan: 1
7815 23:52:44.518489
7816 23:52:44.518553 Set Vref Range= 24 -> 127
7817 23:52:44.518612
7818 23:52:44.521958 RX Vref 24 -> 127, step: 1
7819 23:52:44.522041
7820 23:52:44.525188 RX Delay 11 -> 252, step: 4
7821 23:52:44.525272
7822 23:52:44.528736 Set Vref, RX VrefLevel [Byte0]: 24
7823 23:52:44.531977 [Byte1]: 24
7824 23:52:44.532064
7825 23:52:44.535579 Set Vref, RX VrefLevel [Byte0]: 25
7826 23:52:44.538830 [Byte1]: 25
7827 23:52:44.542161
7828 23:52:44.542251 Set Vref, RX VrefLevel [Byte0]: 26
7829 23:52:44.544845 [Byte1]: 26
7830 23:52:44.549370
7831 23:52:44.549461 Set Vref, RX VrefLevel [Byte0]: 27
7832 23:52:44.552342 [Byte1]: 27
7833 23:52:44.557253
7834 23:52:44.557349 Set Vref, RX VrefLevel [Byte0]: 28
7835 23:52:44.560110 [Byte1]: 28
7836 23:52:44.564405
7837 23:52:44.564497 Set Vref, RX VrefLevel [Byte0]: 29
7838 23:52:44.567940 [Byte1]: 29
7839 23:52:44.572230
7840 23:52:44.572321 Set Vref, RX VrefLevel [Byte0]: 30
7841 23:52:44.575463 [Byte1]: 30
7842 23:52:44.579980
7843 23:52:44.583203 Set Vref, RX VrefLevel [Byte0]: 31
7844 23:52:44.586492 [Byte1]: 31
7845 23:52:44.586579
7846 23:52:44.589448 Set Vref, RX VrefLevel [Byte0]: 32
7847 23:52:44.593063 [Byte1]: 32
7848 23:52:44.593149
7849 23:52:44.596235 Set Vref, RX VrefLevel [Byte0]: 33
7850 23:52:44.599582 [Byte1]: 33
7851 23:52:44.599668
7852 23:52:44.602918 Set Vref, RX VrefLevel [Byte0]: 34
7853 23:52:44.606362 [Byte1]: 34
7854 23:52:44.610366
7855 23:52:44.610461 Set Vref, RX VrefLevel [Byte0]: 35
7856 23:52:44.613725 [Byte1]: 35
7857 23:52:44.617831
7858 23:52:44.617921 Set Vref, RX VrefLevel [Byte0]: 36
7859 23:52:44.621269 [Byte1]: 36
7860 23:52:44.625516
7861 23:52:44.625605 Set Vref, RX VrefLevel [Byte0]: 37
7862 23:52:44.628877 [Byte1]: 37
7863 23:52:44.633200
7864 23:52:44.633290 Set Vref, RX VrefLevel [Byte0]: 38
7865 23:52:44.636611 [Byte1]: 38
7866 23:52:44.640791
7867 23:52:44.640920 Set Vref, RX VrefLevel [Byte0]: 39
7868 23:52:44.644002 [Byte1]: 39
7869 23:52:44.648275
7870 23:52:44.648364 Set Vref, RX VrefLevel [Byte0]: 40
7871 23:52:44.651314 [Byte1]: 40
7872 23:52:44.655829
7873 23:52:44.655921 Set Vref, RX VrefLevel [Byte0]: 41
7874 23:52:44.658962 [Byte1]: 41
7875 23:52:44.663444
7876 23:52:44.663535 Set Vref, RX VrefLevel [Byte0]: 42
7877 23:52:44.666865 [Byte1]: 42
7878 23:52:44.671107
7879 23:52:44.671207 Set Vref, RX VrefLevel [Byte0]: 43
7880 23:52:44.674599 [Byte1]: 43
7881 23:52:44.678898
7882 23:52:44.679001 Set Vref, RX VrefLevel [Byte0]: 44
7883 23:52:44.682035 [Byte1]: 44
7884 23:52:44.686508
7885 23:52:44.686598 Set Vref, RX VrefLevel [Byte0]: 45
7886 23:52:44.689677 [Byte1]: 45
7887 23:52:44.694037
7888 23:52:44.694129 Set Vref, RX VrefLevel [Byte0]: 46
7889 23:52:44.697472 [Byte1]: 46
7890 23:52:44.701425
7891 23:52:44.701515 Set Vref, RX VrefLevel [Byte0]: 47
7892 23:52:44.704734 [Byte1]: 47
7893 23:52:44.709123
7894 23:52:44.709212 Set Vref, RX VrefLevel [Byte0]: 48
7895 23:52:44.712711 [Byte1]: 48
7896 23:52:44.717166
7897 23:52:44.717259 Set Vref, RX VrefLevel [Byte0]: 49
7898 23:52:44.720272 [Byte1]: 49
7899 23:52:44.724229
7900 23:52:44.724315 Set Vref, RX VrefLevel [Byte0]: 50
7901 23:52:44.727917 [Byte1]: 50
7902 23:52:44.732223
7903 23:52:44.732319 Set Vref, RX VrefLevel [Byte0]: 51
7904 23:52:44.735048 [Byte1]: 51
7905 23:52:44.739908
7906 23:52:44.740003 Set Vref, RX VrefLevel [Byte0]: 52
7907 23:52:44.743389 [Byte1]: 52
7908 23:52:44.747152
7909 23:52:44.747240 Set Vref, RX VrefLevel [Byte0]: 53
7910 23:52:44.750281 [Byte1]: 53
7911 23:52:44.754873
7912 23:52:44.754965 Set Vref, RX VrefLevel [Byte0]: 54
7913 23:52:44.758152 [Byte1]: 54
7914 23:52:44.762446
7915 23:52:44.762543 Set Vref, RX VrefLevel [Byte0]: 55
7916 23:52:44.765694 [Byte1]: 55
7917 23:52:44.770247
7918 23:52:44.770349 Set Vref, RX VrefLevel [Byte0]: 56
7919 23:52:44.773530 [Byte1]: 56
7920 23:52:44.777638
7921 23:52:44.777739 Set Vref, RX VrefLevel [Byte0]: 57
7922 23:52:44.781129 [Byte1]: 57
7923 23:52:44.785866
7924 23:52:44.785966 Set Vref, RX VrefLevel [Byte0]: 58
7925 23:52:44.788732 [Byte1]: 58
7926 23:52:44.792988
7927 23:52:44.793088 Set Vref, RX VrefLevel [Byte0]: 59
7928 23:52:44.796198 [Byte1]: 59
7929 23:52:44.800486
7930 23:52:44.800639 Set Vref, RX VrefLevel [Byte0]: 60
7931 23:52:44.803987 [Byte1]: 60
7932 23:52:44.808417
7933 23:52:44.808523 Set Vref, RX VrefLevel [Byte0]: 61
7934 23:52:44.811764 [Byte1]: 61
7935 23:52:44.815633
7936 23:52:44.815732 Set Vref, RX VrefLevel [Byte0]: 62
7937 23:52:44.819044 [Byte1]: 62
7938 23:52:44.823345
7939 23:52:44.823451 Set Vref, RX VrefLevel [Byte0]: 63
7940 23:52:44.826734 [Byte1]: 63
7941 23:52:44.831034
7942 23:52:44.831139 Set Vref, RX VrefLevel [Byte0]: 64
7943 23:52:44.834504 [Byte1]: 64
7944 23:52:44.838667
7945 23:52:44.838773 Set Vref, RX VrefLevel [Byte0]: 65
7946 23:52:44.842876 [Byte1]: 65
7947 23:52:44.846947
7948 23:52:44.847066 Set Vref, RX VrefLevel [Byte0]: 66
7949 23:52:44.849694 [Byte1]: 66
7950 23:52:44.853968
7951 23:52:44.854080 Set Vref, RX VrefLevel [Byte0]: 67
7952 23:52:44.857165 [Byte1]: 67
7953 23:52:44.861455
7954 23:52:44.861567 Set Vref, RX VrefLevel [Byte0]: 68
7955 23:52:44.864897 [Byte1]: 68
7956 23:52:44.868905
7957 23:52:44.869030 Set Vref, RX VrefLevel [Byte0]: 69
7958 23:52:44.872738 [Byte1]: 69
7959 23:52:44.876680
7960 23:52:44.876815 Set Vref, RX VrefLevel [Byte0]: 70
7961 23:52:44.880002 [Byte1]: 70
7962 23:52:44.884170
7963 23:52:44.884281 Set Vref, RX VrefLevel [Byte0]: 71
7964 23:52:44.887689 [Byte1]: 71
7965 23:52:44.891627
7966 23:52:44.891740 Set Vref, RX VrefLevel [Byte0]: 72
7967 23:52:44.895472 [Byte1]: 72
7968 23:52:44.899309
7969 23:52:44.899441 Set Vref, RX VrefLevel [Byte0]: 73
7970 23:52:44.903023 [Byte1]: 73
7971 23:52:44.906913
7972 23:52:44.907019 Set Vref, RX VrefLevel [Byte0]: 74
7973 23:52:44.910312 [Byte1]: 74
7974 23:52:44.914992
7975 23:52:44.915110 Set Vref, RX VrefLevel [Byte0]: 75
7976 23:52:44.918105 [Byte1]: 75
7977 23:52:44.922464
7978 23:52:44.922577 Set Vref, RX VrefLevel [Byte0]: 76
7979 23:52:44.925568 [Byte1]: 76
7980 23:52:44.930023
7981 23:52:44.930135 Final RX Vref Byte 0 = 64 to rank0
7982 23:52:44.933562 Final RX Vref Byte 1 = 59 to rank0
7983 23:52:44.936847 Final RX Vref Byte 0 = 64 to rank1
7984 23:52:44.940094 Final RX Vref Byte 1 = 59 to rank1==
7985 23:52:44.943585 Dram Type= 6, Freq= 0, CH_0, rank 0
7986 23:52:44.949709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 23:52:44.949824 ==
7988 23:52:44.949891 DQS Delay:
7989 23:52:44.949950 DQS0 = 0, DQS1 = 0
7990 23:52:44.952916 DQM Delay:
7991 23:52:44.953001 DQM0 = 126, DQM1 = 120
7992 23:52:44.956228 DQ Delay:
7993 23:52:44.959900 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7994 23:52:44.963174 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7995 23:52:44.966368 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7996 23:52:44.971417 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7997 23:52:44.971527
7998 23:52:44.971590
7999 23:52:44.971650
8000 23:52:44.973340 [DramC_TX_OE_Calibration] TA2
8001 23:52:44.976169 Original DQ_B0 (3 6) =30, OEN = 27
8002 23:52:44.979597 Original DQ_B1 (3 6) =30, OEN = 27
8003 23:52:44.982930 24, 0x0, End_B0=24 End_B1=24
8004 23:52:44.983033 25, 0x0, End_B0=25 End_B1=25
8005 23:52:44.986549 26, 0x0, End_B0=26 End_B1=26
8006 23:52:44.989897 27, 0x0, End_B0=27 End_B1=27
8007 23:52:44.993029 28, 0x0, End_B0=28 End_B1=28
8008 23:52:44.996441 29, 0x0, End_B0=29 End_B1=29
8009 23:52:44.996540 30, 0x0, End_B0=30 End_B1=30
8010 23:52:44.999883 31, 0x4101, End_B0=30 End_B1=30
8011 23:52:45.003216 Byte0 end_step=30 best_step=27
8012 23:52:45.006435 Byte1 end_step=30 best_step=27
8013 23:52:45.009727 Byte0 TX OE(2T, 0.5T) = (3, 3)
8014 23:52:45.013052 Byte1 TX OE(2T, 0.5T) = (3, 3)
8015 23:52:45.013144
8016 23:52:45.013208
8017 23:52:45.019477 [DQSOSCAuto] RK0, (LSB)MR18= 0x1313, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8018 23:52:45.022684 CH0 RK0: MR19=303, MR18=1313
8019 23:52:45.029670 CH0_RK0: MR19=0x303, MR18=0x1313, DQSOSC=400, MR23=63, INC=23, DEC=15
8020 23:52:45.029808
8021 23:52:45.032483 ----->DramcWriteLeveling(PI) begin...
8022 23:52:45.032593 ==
8023 23:52:45.036042 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:52:45.039522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 23:52:45.039622 ==
8026 23:52:45.042575 Write leveling (Byte 0): 34 => 34
8027 23:52:45.045646 Write leveling (Byte 1): 28 => 28
8028 23:52:45.049782 DramcWriteLeveling(PI) end<-----
8029 23:52:45.049879
8030 23:52:45.049941 ==
8031 23:52:45.052529 Dram Type= 6, Freq= 0, CH_0, rank 1
8032 23:52:45.055957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8033 23:52:45.056048 ==
8034 23:52:45.059108 [Gating] SW mode calibration
8035 23:52:45.065627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8036 23:52:45.072366 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8037 23:52:45.075545 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 23:52:45.082355 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 23:52:45.085715 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 23:52:45.088928 1 4 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
8041 23:52:45.095438 1 4 16 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
8042 23:52:45.098895 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8043 23:52:45.101941 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8044 23:52:45.108951 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 23:52:45.112740 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 23:52:45.115828 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 23:52:45.118785 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
8048 23:52:45.125904 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8049 23:52:45.128749 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8050 23:52:45.132302 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
8051 23:52:45.138618 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 23:52:45.141859 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 23:52:45.145256 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 23:52:45.151793 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 23:52:45.155906 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8056 23:52:45.158812 1 6 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8057 23:52:45.165153 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8058 23:52:45.168540 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8059 23:52:45.171677 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 23:52:45.178855 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 23:52:45.181751 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 23:52:45.185016 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8063 23:52:45.191528 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 23:52:45.195245 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8065 23:52:45.198376 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8066 23:52:45.204680 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 23:52:45.208841 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:52:45.211701 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:52:45.218392 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:52:45.221406 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:52:45.224996 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:52:45.231235 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:52:45.234952 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:52:45.238068 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:52:45.244872 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:52:45.248248 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:52:45.251606 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:52:45.258058 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:52:45.261626 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8080 23:52:45.265059 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 23:52:45.271482 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8082 23:52:45.271671 Total UI for P1: 0, mck2ui 16
8083 23:52:45.274783 best dqsien dly found for B0: ( 1, 9, 10)
8084 23:52:45.281399 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 23:52:45.284806 Total UI for P1: 0, mck2ui 16
8086 23:52:45.288160 best dqsien dly found for B1: ( 1, 9, 16)
8087 23:52:45.291574 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8088 23:52:45.294721 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8089 23:52:45.294862
8090 23:52:45.297954 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8091 23:52:45.301249 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8092 23:52:45.304977 [Gating] SW calibration Done
8093 23:52:45.305107 ==
8094 23:52:45.308283 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 23:52:45.311718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 23:52:45.311851 ==
8097 23:52:45.314950 RX Vref Scan: 0
8098 23:52:45.315093
8099 23:52:45.317963 RX Vref 0 -> 0, step: 1
8100 23:52:45.318094
8101 23:52:45.318189 RX Delay 0 -> 252, step: 8
8102 23:52:45.324545 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8103 23:52:45.327602 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8104 23:52:45.331371 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8105 23:52:45.334158 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8106 23:52:45.337786 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8107 23:52:45.344576 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8108 23:52:45.347509 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8109 23:52:45.351614 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8110 23:52:45.354390 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8111 23:52:45.357906 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8112 23:52:45.363967 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8113 23:52:45.367460 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8114 23:52:45.370804 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8115 23:52:45.373884 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8116 23:52:45.380475 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8117 23:52:45.383970 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8118 23:52:45.384187 ==
8119 23:52:45.387169 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 23:52:45.390545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 23:52:45.390669 ==
8122 23:52:45.390798 DQS Delay:
8123 23:52:45.393949 DQS0 = 0, DQS1 = 0
8124 23:52:45.394062 DQM Delay:
8125 23:52:45.397232 DQM0 = 128, DQM1 = 121
8126 23:52:45.397344 DQ Delay:
8127 23:52:45.400731 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8128 23:52:45.403554 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8129 23:52:45.407151 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8130 23:52:45.413768 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8131 23:52:45.413912
8132 23:52:45.414012
8133 23:52:45.414104 ==
8134 23:52:45.417241 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 23:52:45.420392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 23:52:45.420536 ==
8137 23:52:45.420651
8138 23:52:45.420741
8139 23:52:45.423537 TX Vref Scan disable
8140 23:52:45.423652 == TX Byte 0 ==
8141 23:52:45.430336 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8142 23:52:45.433776 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8143 23:52:45.433911 == TX Byte 1 ==
8144 23:52:45.440649 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8145 23:52:45.443160 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8146 23:52:45.443288 ==
8147 23:52:45.446999 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 23:52:45.450143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 23:52:45.450283 ==
8150 23:52:45.464382
8151 23:52:45.467603 TX Vref early break, caculate TX vref
8152 23:52:45.471332 TX Vref=16, minBit 1, minWin=22, winSum=366
8153 23:52:45.474270 TX Vref=18, minBit 9, minWin=22, winSum=374
8154 23:52:45.478093 TX Vref=20, minBit 8, minWin=22, winSum=383
8155 23:52:45.481093 TX Vref=22, minBit 8, minWin=23, winSum=389
8156 23:52:45.484338 TX Vref=24, minBit 8, minWin=23, winSum=397
8157 23:52:45.490878 TX Vref=26, minBit 0, minWin=24, winSum=401
8158 23:52:45.494208 TX Vref=28, minBit 8, minWin=24, winSum=409
8159 23:52:45.497617 TX Vref=30, minBit 11, minWin=23, winSum=405
8160 23:52:45.501299 TX Vref=32, minBit 8, minWin=24, winSum=397
8161 23:52:45.504964 TX Vref=34, minBit 8, minWin=22, winSum=386
8162 23:52:45.510902 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 28
8163 23:52:45.511021
8164 23:52:45.513820 Final TX Range 0 Vref 28
8165 23:52:45.513911
8166 23:52:45.513977 ==
8167 23:52:45.517718 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 23:52:45.520993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 23:52:45.521106 ==
8170 23:52:45.521174
8171 23:52:45.521236
8172 23:52:45.524180 TX Vref Scan disable
8173 23:52:45.530587 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8174 23:52:45.530701 == TX Byte 0 ==
8175 23:52:45.534080 u2DelayCellOfst[0]=18 cells (5 PI)
8176 23:52:45.537323 u2DelayCellOfst[1]=18 cells (5 PI)
8177 23:52:45.540591 u2DelayCellOfst[2]=15 cells (4 PI)
8178 23:52:45.543690 u2DelayCellOfst[3]=15 cells (4 PI)
8179 23:52:45.547029 u2DelayCellOfst[4]=11 cells (3 PI)
8180 23:52:45.550411 u2DelayCellOfst[5]=0 cells (0 PI)
8181 23:52:45.554087 u2DelayCellOfst[6]=22 cells (6 PI)
8182 23:52:45.556972 u2DelayCellOfst[7]=18 cells (5 PI)
8183 23:52:45.560938 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8184 23:52:45.563778 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8185 23:52:45.566815 == TX Byte 1 ==
8186 23:52:45.569997 u2DelayCellOfst[8]=0 cells (0 PI)
8187 23:52:45.573338 u2DelayCellOfst[9]=0 cells (0 PI)
8188 23:52:45.577014 u2DelayCellOfst[10]=11 cells (3 PI)
8189 23:52:45.577182 u2DelayCellOfst[11]=7 cells (2 PI)
8190 23:52:45.580149 u2DelayCellOfst[12]=15 cells (4 PI)
8191 23:52:45.583528 u2DelayCellOfst[13]=11 cells (3 PI)
8192 23:52:45.586784 u2DelayCellOfst[14]=15 cells (4 PI)
8193 23:52:45.590175 u2DelayCellOfst[15]=11 cells (3 PI)
8194 23:52:45.597198 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8195 23:52:45.600363 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8196 23:52:45.600489 DramC Write-DBI on
8197 23:52:45.600595 ==
8198 23:52:45.603743 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 23:52:45.609870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 23:52:45.610005 ==
8201 23:52:45.610104
8202 23:52:45.610196
8203 23:52:45.610286 TX Vref Scan disable
8204 23:52:45.613974 == TX Byte 0 ==
8205 23:52:45.617479 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8206 23:52:45.620853 == TX Byte 1 ==
8207 23:52:45.623905 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8208 23:52:45.627162 DramC Write-DBI off
8209 23:52:45.627281
8210 23:52:45.627375 [DATLAT]
8211 23:52:45.627466 Freq=1600, CH0 RK1
8212 23:52:45.627555
8213 23:52:45.630973 DATLAT Default: 0xf
8214 23:52:45.631084 0, 0xFFFF, sum = 0
8215 23:52:45.634181 1, 0xFFFF, sum = 0
8216 23:52:45.638342 2, 0xFFFF, sum = 0
8217 23:52:45.638464 3, 0xFFFF, sum = 0
8218 23:52:45.640537 4, 0xFFFF, sum = 0
8219 23:52:45.640744 5, 0xFFFF, sum = 0
8220 23:52:45.643942 6, 0xFFFF, sum = 0
8221 23:52:45.644022 7, 0xFFFF, sum = 0
8222 23:52:45.647394 8, 0xFFFF, sum = 0
8223 23:52:45.647469 9, 0xFFFF, sum = 0
8224 23:52:45.650626 10, 0xFFFF, sum = 0
8225 23:52:45.650716 11, 0xFFFF, sum = 0
8226 23:52:45.654370 12, 0xFFFF, sum = 0
8227 23:52:45.654461 13, 0xCFFF, sum = 0
8228 23:52:45.657555 14, 0x0, sum = 1
8229 23:52:45.657648 15, 0x0, sum = 2
8230 23:52:45.660554 16, 0x0, sum = 3
8231 23:52:45.660669 17, 0x0, sum = 4
8232 23:52:45.663655 best_step = 15
8233 23:52:45.663746
8234 23:52:45.663812 ==
8235 23:52:45.667311 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 23:52:45.670248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 23:52:45.670396 ==
8238 23:52:45.673685 RX Vref Scan: 0
8239 23:52:45.673797
8240 23:52:45.673862 RX Vref 0 -> 0, step: 1
8241 23:52:45.673922
8242 23:52:45.677368 RX Delay 3 -> 252, step: 4
8243 23:52:45.680384 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8244 23:52:45.686987 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8245 23:52:45.690551 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8246 23:52:45.694113 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8247 23:52:45.696830 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8248 23:52:45.700523 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8249 23:52:45.707672 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8250 23:52:45.710508 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8251 23:52:45.714003 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8252 23:52:45.717338 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8253 23:52:45.720392 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8254 23:52:45.727070 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8255 23:52:45.730350 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8256 23:52:45.733798 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8257 23:52:45.736944 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8258 23:52:45.743711 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8259 23:52:45.743827 ==
8260 23:52:45.746669 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 23:52:45.750264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 23:52:45.750359 ==
8263 23:52:45.750445 DQS Delay:
8264 23:52:45.753100 DQS0 = 0, DQS1 = 0
8265 23:52:45.753184 DQM Delay:
8266 23:52:45.756805 DQM0 = 124, DQM1 = 118
8267 23:52:45.756908 DQ Delay:
8268 23:52:45.759695 DQ0 =122, DQ1 =126, DQ2 =120, DQ3 =122
8269 23:52:45.763331 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8270 23:52:45.766827 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8271 23:52:45.770051 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8272 23:52:45.770143
8273 23:52:45.770208
8274 23:52:45.773061
8275 23:52:45.773144 [DramC_TX_OE_Calibration] TA2
8276 23:52:45.776547 Original DQ_B0 (3 6) =30, OEN = 27
8277 23:52:45.780085 Original DQ_B1 (3 6) =30, OEN = 27
8278 23:52:45.783160 24, 0x0, End_B0=24 End_B1=24
8279 23:52:45.786503 25, 0x0, End_B0=25 End_B1=25
8280 23:52:45.789778 26, 0x0, End_B0=26 End_B1=26
8281 23:52:45.789863 27, 0x0, End_B0=27 End_B1=27
8282 23:52:45.793072 28, 0x0, End_B0=28 End_B1=28
8283 23:52:45.796305 29, 0x0, End_B0=29 End_B1=29
8284 23:52:45.799787 30, 0x0, End_B0=30 End_B1=30
8285 23:52:45.802951 31, 0x5151, End_B0=30 End_B1=30
8286 23:52:45.803043 Byte0 end_step=30 best_step=27
8287 23:52:45.806410 Byte1 end_step=30 best_step=27
8288 23:52:45.809600 Byte0 TX OE(2T, 0.5T) = (3, 3)
8289 23:52:45.812892 Byte1 TX OE(2T, 0.5T) = (3, 3)
8290 23:52:45.812974
8291 23:52:45.813039
8292 23:52:45.819292 [DQSOSCAuto] RK1, (LSB)MR18= 0x2714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
8293 23:52:45.823023 CH0 RK1: MR19=303, MR18=2714
8294 23:52:45.829153 CH0_RK1: MR19=0x303, MR18=0x2714, DQSOSC=390, MR23=63, INC=24, DEC=16
8295 23:52:45.832361 [RxdqsGatingPostProcess] freq 1600
8296 23:52:45.839074 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8297 23:52:45.842704 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 23:52:45.845808 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 23:52:45.849169 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 23:52:45.849258 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 23:52:45.852467 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 23:52:45.856350 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 23:52:45.859324 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 23:52:45.862452 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 23:52:45.865714 Pre-setting of DQS Precalculation
8306 23:52:45.872175 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8307 23:52:45.872284 ==
8308 23:52:45.875513 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 23:52:45.878865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 23:52:45.878954 ==
8311 23:52:45.885389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 23:52:45.888896 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 23:52:45.892042 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 23:52:45.899116 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 23:52:45.907187 [CA 0] Center 42 (13~71) winsize 59
8316 23:52:45.910379 [CA 1] Center 42 (12~72) winsize 61
8317 23:52:45.913826 [CA 2] Center 37 (9~66) winsize 58
8318 23:52:45.917133 [CA 3] Center 37 (8~66) winsize 59
8319 23:52:45.920472 [CA 4] Center 37 (8~66) winsize 59
8320 23:52:45.923850 [CA 5] Center 36 (7~66) winsize 60
8321 23:52:45.923951
8322 23:52:45.927212 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8323 23:52:45.927295
8324 23:52:45.930624 [CATrainingPosCal] consider 1 rank data
8325 23:52:45.933594 u2DelayCellTimex100 = 258/100 ps
8326 23:52:45.940472 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8327 23:52:45.943728 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8328 23:52:45.946994 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8329 23:52:45.950381 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8330 23:52:45.953368 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 23:52:45.957224 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8332 23:52:45.957376
8333 23:52:45.960288 CA PerBit enable=1, Macro0, CA PI delay=36
8334 23:52:45.960377
8335 23:52:45.963311 [CBTSetCACLKResult] CA Dly = 36
8336 23:52:45.966587 CS Dly: 10 (0~41)
8337 23:52:45.970050 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 23:52:45.973327 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 23:52:45.973420 ==
8340 23:52:45.976513 Dram Type= 6, Freq= 0, CH_1, rank 1
8341 23:52:45.979890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 23:52:45.983553 ==
8343 23:52:45.986526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8344 23:52:45.989809 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8345 23:52:45.996395 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8346 23:52:46.003374 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8347 23:52:46.010707 [CA 0] Center 42 (13~71) winsize 59
8348 23:52:46.013899 [CA 1] Center 42 (12~72) winsize 61
8349 23:52:46.017231 [CA 2] Center 37 (8~67) winsize 60
8350 23:52:46.020653 [CA 3] Center 36 (7~66) winsize 60
8351 23:52:46.023379 [CA 4] Center 37 (7~67) winsize 61
8352 23:52:46.026766 [CA 5] Center 36 (6~66) winsize 61
8353 23:52:46.026892
8354 23:52:46.030345 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8355 23:52:46.030471
8356 23:52:46.034179 [CATrainingPosCal] consider 2 rank data
8357 23:52:46.037304 u2DelayCellTimex100 = 258/100 ps
8358 23:52:46.040365 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8359 23:52:46.047224 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8360 23:52:46.050210 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8361 23:52:46.053300 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8362 23:52:46.056871 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8363 23:52:46.060056 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8364 23:52:46.060143
8365 23:52:46.063221 CA PerBit enable=1, Macro0, CA PI delay=36
8366 23:52:46.063324
8367 23:52:46.066893 [CBTSetCACLKResult] CA Dly = 36
8368 23:52:46.069764 CS Dly: 11 (0~44)
8369 23:52:46.073390 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8370 23:52:46.077416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8371 23:52:46.077511
8372 23:52:46.079789 ----->DramcWriteLeveling(PI) begin...
8373 23:52:46.079870 ==
8374 23:52:46.083124 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 23:52:46.089906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 23:52:46.089997 ==
8377 23:52:46.093542 Write leveling (Byte 0): 24 => 24
8378 23:52:46.093627 Write leveling (Byte 1): 30 => 30
8379 23:52:46.096972 DramcWriteLeveling(PI) end<-----
8380 23:52:46.097056
8381 23:52:46.099613 ==
8382 23:52:46.103581 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 23:52:46.106092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 23:52:46.106192 ==
8385 23:52:46.109408 [Gating] SW mode calibration
8386 23:52:46.116403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8387 23:52:46.120008 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8388 23:52:46.126172 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 23:52:46.129855 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 23:52:46.132936 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 23:52:46.139573 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 23:52:46.143042 1 4 16 | B1->B0 | 3131 3030 | 0 0 | (1 1) (0 0)
8393 23:52:46.146032 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 23:52:46.152953 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 23:52:46.156268 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 23:52:46.159374 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 23:52:46.165888 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 23:52:46.169264 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 23:52:46.172386 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 23:52:46.178958 1 5 16 | B1->B0 | 2626 2525 | 1 1 | (1 0) (1 0)
8401 23:52:46.182465 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 23:52:46.186068 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 23:52:46.192470 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 23:52:46.195833 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 23:52:46.198554 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 23:52:46.205865 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 23:52:46.208480 1 6 12 | B1->B0 | 2424 2424 | 1 0 | (0 0) (0 0)
8408 23:52:46.212374 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8409 23:52:46.218318 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 23:52:46.221883 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 23:52:46.225391 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 23:52:46.231913 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 23:52:46.235104 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 23:52:46.238316 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 23:52:46.244785 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8416 23:52:46.248421 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8417 23:52:46.251846 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8418 23:52:46.258360 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:52:46.261561 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:52:46.264955 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:52:46.271888 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:52:46.275078 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:52:46.277849 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:52:46.284798 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:52:46.287778 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:52:46.291310 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:52:46.297853 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:52:46.301519 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:52:46.304520 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:52:46.310974 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:52:46.314502 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8432 23:52:46.317958 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8433 23:52:46.324518 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 23:52:46.324656 Total UI for P1: 0, mck2ui 16
8435 23:52:46.327835 best dqsien dly found for B0: ( 1, 9, 14)
8436 23:52:46.331350 Total UI for P1: 0, mck2ui 16
8437 23:52:46.334674 best dqsien dly found for B1: ( 1, 9, 14)
8438 23:52:46.340883 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8439 23:52:46.344464 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8440 23:52:46.344594
8441 23:52:46.347434 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8442 23:52:46.350842 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8443 23:52:46.354122 [Gating] SW calibration Done
8444 23:52:46.354238 ==
8445 23:52:46.357961 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 23:52:46.361223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 23:52:46.361314 ==
8448 23:52:46.364225 RX Vref Scan: 0
8449 23:52:46.364340
8450 23:52:46.364437 RX Vref 0 -> 0, step: 1
8451 23:52:46.364528
8452 23:52:46.367182 RX Delay 0 -> 252, step: 8
8453 23:52:46.370848 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8454 23:52:46.377284 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8455 23:52:46.380721 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8456 23:52:46.384059 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8457 23:52:46.387410 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8458 23:52:46.390881 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8459 23:52:46.397176 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8460 23:52:46.400450 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8461 23:52:46.404077 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8462 23:52:46.406938 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8463 23:52:46.410388 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8464 23:52:46.416848 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8465 23:52:46.420202 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8466 23:52:46.423658 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8467 23:52:46.426715 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8468 23:52:46.433489 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8469 23:52:46.433647 ==
8470 23:52:46.436956 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 23:52:46.440153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 23:52:46.440246 ==
8473 23:52:46.440311 DQS Delay:
8474 23:52:46.443025 DQS0 = 0, DQS1 = 0
8475 23:52:46.443110 DQM Delay:
8476 23:52:46.446589 DQM0 = 132, DQM1 = 126
8477 23:52:46.446676 DQ Delay:
8478 23:52:46.449663 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =131
8479 23:52:46.453181 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8480 23:52:46.456476 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8481 23:52:46.459798 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8482 23:52:46.459887
8483 23:52:46.459952
8484 23:52:46.463082 ==
8485 23:52:46.466254 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 23:52:46.469490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 23:52:46.469592 ==
8488 23:52:46.469660
8489 23:52:46.469721
8490 23:52:46.473277 TX Vref Scan disable
8491 23:52:46.473368 == TX Byte 0 ==
8492 23:52:46.479450 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8493 23:52:46.482877 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8494 23:52:46.483024 == TX Byte 1 ==
8495 23:52:46.489803 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8496 23:52:46.492999 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8497 23:52:46.493117 ==
8498 23:52:46.496052 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 23:52:46.499017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 23:52:46.499112 ==
8501 23:52:46.514338
8502 23:52:46.517217 TX Vref early break, caculate TX vref
8503 23:52:46.520859 TX Vref=16, minBit 9, minWin=20, winSum=357
8504 23:52:46.524334 TX Vref=18, minBit 9, minWin=21, winSum=362
8505 23:52:46.527658 TX Vref=20, minBit 11, minWin=21, winSum=377
8506 23:52:46.531446 TX Vref=22, minBit 8, minWin=22, winSum=381
8507 23:52:46.533751 TX Vref=24, minBit 8, minWin=23, winSum=393
8508 23:52:46.540345 TX Vref=26, minBit 8, minWin=24, winSum=407
8509 23:52:46.543756 TX Vref=28, minBit 11, minWin=23, winSum=404
8510 23:52:46.547215 TX Vref=30, minBit 6, minWin=24, winSum=408
8511 23:52:46.550720 TX Vref=32, minBit 9, minWin=23, winSum=396
8512 23:52:46.554068 TX Vref=34, minBit 0, minWin=23, winSum=388
8513 23:52:46.557148 TX Vref=36, minBit 1, minWin=22, winSum=381
8514 23:52:46.563482 [TxChooseVref] Worse bit 6, Min win 24, Win sum 408, Final Vref 30
8515 23:52:46.563612
8516 23:52:46.566873 Final TX Range 0 Vref 30
8517 23:52:46.566977
8518 23:52:46.567066 ==
8519 23:52:46.570194 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 23:52:46.573516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 23:52:46.573640 ==
8522 23:52:46.576694
8523 23:52:46.576779
8524 23:52:46.576846 TX Vref Scan disable
8525 23:52:46.583517 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8526 23:52:46.583635 == TX Byte 0 ==
8527 23:52:46.586699 u2DelayCellOfst[0]=22 cells (6 PI)
8528 23:52:46.590431 u2DelayCellOfst[1]=15 cells (4 PI)
8529 23:52:46.593613 u2DelayCellOfst[2]=0 cells (0 PI)
8530 23:52:46.596590 u2DelayCellOfst[3]=11 cells (3 PI)
8531 23:52:46.600090 u2DelayCellOfst[4]=11 cells (3 PI)
8532 23:52:46.603297 u2DelayCellOfst[5]=22 cells (6 PI)
8533 23:52:46.606855 u2DelayCellOfst[6]=22 cells (6 PI)
8534 23:52:46.609765 u2DelayCellOfst[7]=7 cells (2 PI)
8535 23:52:46.613173 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8536 23:52:46.616369 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8537 23:52:46.620018 == TX Byte 1 ==
8538 23:52:46.623147 u2DelayCellOfst[8]=0 cells (0 PI)
8539 23:52:46.626455 u2DelayCellOfst[9]=7 cells (2 PI)
8540 23:52:46.630051 u2DelayCellOfst[10]=15 cells (4 PI)
8541 23:52:46.633595 u2DelayCellOfst[11]=7 cells (2 PI)
8542 23:52:46.636445 u2DelayCellOfst[12]=15 cells (4 PI)
8543 23:52:46.636580 u2DelayCellOfst[13]=18 cells (5 PI)
8544 23:52:46.640125 u2DelayCellOfst[14]=18 cells (5 PI)
8545 23:52:46.643404 u2DelayCellOfst[15]=18 cells (5 PI)
8546 23:52:46.650127 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8547 23:52:46.653592 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8548 23:52:46.653724 DramC Write-DBI on
8549 23:52:46.656209 ==
8550 23:52:46.659545 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 23:52:46.663243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 23:52:46.663355 ==
8553 23:52:46.663446
8554 23:52:46.663538
8555 23:52:46.666075 TX Vref Scan disable
8556 23:52:46.666179 == TX Byte 0 ==
8557 23:52:46.672844 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8558 23:52:46.672971 == TX Byte 1 ==
8559 23:52:46.676508 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8560 23:52:46.679530 DramC Write-DBI off
8561 23:52:46.679642
8562 23:52:46.679743 [DATLAT]
8563 23:52:46.682653 Freq=1600, CH1 RK0
8564 23:52:46.682767
8565 23:52:46.682863 DATLAT Default: 0xf
8566 23:52:46.686283 0, 0xFFFF, sum = 0
8567 23:52:46.686392 1, 0xFFFF, sum = 0
8568 23:52:46.689245 2, 0xFFFF, sum = 0
8569 23:52:46.689351 3, 0xFFFF, sum = 0
8570 23:52:46.693052 4, 0xFFFF, sum = 0
8571 23:52:46.693169 5, 0xFFFF, sum = 0
8572 23:52:46.695954 6, 0xFFFF, sum = 0
8573 23:52:46.699313 7, 0xFFFF, sum = 0
8574 23:52:46.699431 8, 0xFFFF, sum = 0
8575 23:52:46.702953 9, 0xFFFF, sum = 0
8576 23:52:46.703073 10, 0xFFFF, sum = 0
8577 23:52:46.706119 11, 0xFFFF, sum = 0
8578 23:52:46.706229 12, 0xFFFF, sum = 0
8579 23:52:46.709115 13, 0x8FFF, sum = 0
8580 23:52:46.709206 14, 0x0, sum = 1
8581 23:52:46.712625 15, 0x0, sum = 2
8582 23:52:46.712738 16, 0x0, sum = 3
8583 23:52:46.716395 17, 0x0, sum = 4
8584 23:52:46.716505 best_step = 15
8585 23:52:46.716601
8586 23:52:46.716667 ==
8587 23:52:46.719359 Dram Type= 6, Freq= 0, CH_1, rank 0
8588 23:52:46.722345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8589 23:52:46.725846 ==
8590 23:52:46.725936 RX Vref Scan: 1
8591 23:52:46.726002
8592 23:52:46.729176 Set Vref Range= 24 -> 127
8593 23:52:46.729262
8594 23:52:46.729326 RX Vref 24 -> 127, step: 1
8595 23:52:46.732387
8596 23:52:46.732491 RX Delay 11 -> 252, step: 4
8597 23:52:46.732592
8598 23:52:46.735843 Set Vref, RX VrefLevel [Byte0]: 24
8599 23:52:46.738844 [Byte1]: 24
8600 23:52:46.742897
8601 23:52:46.743018 Set Vref, RX VrefLevel [Byte0]: 25
8602 23:52:46.745805 [Byte1]: 25
8603 23:52:46.750499
8604 23:52:46.750633 Set Vref, RX VrefLevel [Byte0]: 26
8605 23:52:46.753828 [Byte1]: 26
8606 23:52:46.757820
8607 23:52:46.757936 Set Vref, RX VrefLevel [Byte0]: 27
8608 23:52:46.761188 [Byte1]: 27
8609 23:52:46.765453
8610 23:52:46.765551 Set Vref, RX VrefLevel [Byte0]: 28
8611 23:52:46.768915 [Byte1]: 28
8612 23:52:46.772905
8613 23:52:46.773021 Set Vref, RX VrefLevel [Byte0]: 29
8614 23:52:46.776229 [Byte1]: 29
8615 23:52:46.780653
8616 23:52:46.780777 Set Vref, RX VrefLevel [Byte0]: 30
8617 23:52:46.784208 [Byte1]: 30
8618 23:52:46.788754
8619 23:52:46.788850 Set Vref, RX VrefLevel [Byte0]: 31
8620 23:52:46.791502 [Byte1]: 31
8621 23:52:46.795915
8622 23:52:46.796050 Set Vref, RX VrefLevel [Byte0]: 32
8623 23:52:46.799417 [Byte1]: 32
8624 23:52:46.803892
8625 23:52:46.803985 Set Vref, RX VrefLevel [Byte0]: 33
8626 23:52:46.806863 [Byte1]: 33
8627 23:52:46.811243
8628 23:52:46.811333 Set Vref, RX VrefLevel [Byte0]: 34
8629 23:52:46.814551 [Byte1]: 34
8630 23:52:46.818957
8631 23:52:46.819070 Set Vref, RX VrefLevel [Byte0]: 35
8632 23:52:46.825452 [Byte1]: 35
8633 23:52:46.825581
8634 23:52:46.828454 Set Vref, RX VrefLevel [Byte0]: 36
8635 23:52:46.831899 [Byte1]: 36
8636 23:52:46.832010
8637 23:52:46.835459 Set Vref, RX VrefLevel [Byte0]: 37
8638 23:52:46.838613 [Byte1]: 37
8639 23:52:46.841959
8640 23:52:46.842081 Set Vref, RX VrefLevel [Byte0]: 38
8641 23:52:46.845104 [Byte1]: 38
8642 23:52:46.849314
8643 23:52:46.849405 Set Vref, RX VrefLevel [Byte0]: 39
8644 23:52:46.852445 [Byte1]: 39
8645 23:52:46.856780
8646 23:52:46.856910 Set Vref, RX VrefLevel [Byte0]: 40
8647 23:52:46.860418 [Byte1]: 40
8648 23:52:46.864273
8649 23:52:46.864395 Set Vref, RX VrefLevel [Byte0]: 41
8650 23:52:46.867965 [Byte1]: 41
8651 23:52:46.872154
8652 23:52:46.872271 Set Vref, RX VrefLevel [Byte0]: 42
8653 23:52:46.875406 [Byte1]: 42
8654 23:52:46.879963
8655 23:52:46.880063 Set Vref, RX VrefLevel [Byte0]: 43
8656 23:52:46.882903 [Byte1]: 43
8657 23:52:46.887695
8658 23:52:46.887821 Set Vref, RX VrefLevel [Byte0]: 44
8659 23:52:46.890465 [Byte1]: 44
8660 23:52:46.894955
8661 23:52:46.895043 Set Vref, RX VrefLevel [Byte0]: 45
8662 23:52:46.898197 [Byte1]: 45
8663 23:52:46.902461
8664 23:52:46.902561 Set Vref, RX VrefLevel [Byte0]: 46
8665 23:52:46.905617 [Byte1]: 46
8666 23:52:46.910136
8667 23:52:46.910225 Set Vref, RX VrefLevel [Byte0]: 47
8668 23:52:46.913786 [Byte1]: 47
8669 23:52:46.918075
8670 23:52:46.918214 Set Vref, RX VrefLevel [Byte0]: 48
8671 23:52:46.920817 [Byte1]: 48
8672 23:52:46.925236
8673 23:52:46.925339 Set Vref, RX VrefLevel [Byte0]: 49
8674 23:52:46.928840 [Byte1]: 49
8675 23:52:46.933255
8676 23:52:46.933358 Set Vref, RX VrefLevel [Byte0]: 50
8677 23:52:46.936165 [Byte1]: 50
8678 23:52:46.940944
8679 23:52:46.941038 Set Vref, RX VrefLevel [Byte0]: 51
8680 23:52:46.944057 [Byte1]: 51
8681 23:52:46.948167
8682 23:52:46.948264 Set Vref, RX VrefLevel [Byte0]: 52
8683 23:52:46.951706 [Byte1]: 52
8684 23:52:46.956212
8685 23:52:46.956302 Set Vref, RX VrefLevel [Byte0]: 53
8686 23:52:46.959306 [Byte1]: 53
8687 23:52:46.963726
8688 23:52:46.963820 Set Vref, RX VrefLevel [Byte0]: 54
8689 23:52:46.966801 [Byte1]: 54
8690 23:52:46.971162
8691 23:52:46.971270 Set Vref, RX VrefLevel [Byte0]: 55
8692 23:52:46.974543 [Byte1]: 55
8693 23:52:46.978691
8694 23:52:46.978798 Set Vref, RX VrefLevel [Byte0]: 56
8695 23:52:46.982173 [Byte1]: 56
8696 23:52:46.986613
8697 23:52:46.986717 Set Vref, RX VrefLevel [Byte0]: 57
8698 23:52:46.989655 [Byte1]: 57
8699 23:52:46.994059
8700 23:52:46.994153 Set Vref, RX VrefLevel [Byte0]: 58
8701 23:52:46.997473 [Byte1]: 58
8702 23:52:47.001807
8703 23:52:47.001902 Set Vref, RX VrefLevel [Byte0]: 59
8704 23:52:47.005089 [Byte1]: 59
8705 23:52:47.009161
8706 23:52:47.009262 Set Vref, RX VrefLevel [Byte0]: 60
8707 23:52:47.012332 [Byte1]: 60
8708 23:52:47.016740
8709 23:52:47.016840 Set Vref, RX VrefLevel [Byte0]: 61
8710 23:52:47.019940 [Byte1]: 61
8711 23:52:47.024531
8712 23:52:47.024647 Set Vref, RX VrefLevel [Byte0]: 62
8713 23:52:47.027384 [Byte1]: 62
8714 23:52:47.031978
8715 23:52:47.032104 Set Vref, RX VrefLevel [Byte0]: 63
8716 23:52:47.035610 [Byte1]: 63
8717 23:52:47.039522
8718 23:52:47.039634 Set Vref, RX VrefLevel [Byte0]: 64
8719 23:52:47.042909 [Byte1]: 64
8720 23:52:47.047086
8721 23:52:47.047206 Set Vref, RX VrefLevel [Byte0]: 65
8722 23:52:47.050609 [Byte1]: 65
8723 23:52:47.054712
8724 23:52:47.054824 Set Vref, RX VrefLevel [Byte0]: 66
8725 23:52:47.058335 [Byte1]: 66
8726 23:52:47.062346
8727 23:52:47.062467 Set Vref, RX VrefLevel [Byte0]: 67
8728 23:52:47.065717 [Byte1]: 67
8729 23:52:47.070257
8730 23:52:47.070359 Set Vref, RX VrefLevel [Byte0]: 68
8731 23:52:47.073850 [Byte1]: 68
8732 23:52:47.077471
8733 23:52:47.077569 Set Vref, RX VrefLevel [Byte0]: 69
8734 23:52:47.080938 [Byte1]: 69
8735 23:52:47.085258
8736 23:52:47.085344 Set Vref, RX VrefLevel [Byte0]: 70
8737 23:52:47.088540 [Byte1]: 70
8738 23:52:47.092643
8739 23:52:47.092725 Final RX Vref Byte 0 = 56 to rank0
8740 23:52:47.096260 Final RX Vref Byte 1 = 58 to rank0
8741 23:52:47.099269 Final RX Vref Byte 0 = 56 to rank1
8742 23:52:47.103086 Final RX Vref Byte 1 = 58 to rank1==
8743 23:52:47.105951 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 23:52:47.113144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 23:52:47.113293 ==
8746 23:52:47.113397 DQS Delay:
8747 23:52:47.115875 DQS0 = 0, DQS1 = 0
8748 23:52:47.115985 DQM Delay:
8749 23:52:47.116086 DQM0 = 131, DQM1 = 123
8750 23:52:47.119132 DQ Delay:
8751 23:52:47.122536 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8752 23:52:47.125660 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8753 23:52:47.129037 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =116
8754 23:52:47.132294 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8755 23:52:47.132392
8756 23:52:47.132492
8757 23:52:47.132586
8758 23:52:47.135484 [DramC_TX_OE_Calibration] TA2
8759 23:52:47.138790 Original DQ_B0 (3 6) =30, OEN = 27
8760 23:52:47.142020 Original DQ_B1 (3 6) =30, OEN = 27
8761 23:52:47.145420 24, 0x0, End_B0=24 End_B1=24
8762 23:52:47.148901 25, 0x0, End_B0=25 End_B1=25
8763 23:52:47.148988 26, 0x0, End_B0=26 End_B1=26
8764 23:52:47.151805 27, 0x0, End_B0=27 End_B1=27
8765 23:52:47.155427 28, 0x0, End_B0=28 End_B1=28
8766 23:52:47.158516 29, 0x0, End_B0=29 End_B1=29
8767 23:52:47.158608 30, 0x0, End_B0=30 End_B1=30
8768 23:52:47.161816 31, 0x5151, End_B0=30 End_B1=30
8769 23:52:47.165100 Byte0 end_step=30 best_step=27
8770 23:52:47.168471 Byte1 end_step=30 best_step=27
8771 23:52:47.171905 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 23:52:47.175186 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 23:52:47.175273
8774 23:52:47.175339
8775 23:52:47.181788 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8776 23:52:47.185094 CH1 RK0: MR19=303, MR18=90E
8777 23:52:47.191888 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8778 23:52:47.191990
8779 23:52:47.194941 ----->DramcWriteLeveling(PI) begin...
8780 23:52:47.195034 ==
8781 23:52:47.198633 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 23:52:47.201604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 23:52:47.201716 ==
8784 23:52:47.205346 Write leveling (Byte 0): 24 => 24
8785 23:52:47.208148 Write leveling (Byte 1): 28 => 28
8786 23:52:47.211414 DramcWriteLeveling(PI) end<-----
8787 23:52:47.211551
8788 23:52:47.211664 ==
8789 23:52:47.214724 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 23:52:47.218162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 23:52:47.221227 ==
8792 23:52:47.221353 [Gating] SW mode calibration
8793 23:52:47.231398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 23:52:47.234770 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 23:52:47.237857 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:52:47.244492 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:52:47.248356 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8798 23:52:47.251742 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 23:52:47.257764 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 23:52:47.261794 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 23:52:47.264592 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 23:52:47.271132 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 23:52:47.274649 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 23:52:47.278025 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8805 23:52:47.284543 1 5 8 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
8806 23:52:47.288092 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
8807 23:52:47.291224 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8808 23:52:47.297927 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 23:52:47.301268 1 5 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8810 23:52:47.304666 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 23:52:47.310953 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 23:52:47.314533 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8813 23:52:47.318141 1 6 8 | B1->B0 | 2525 4444 | 0 0 | (0 0) (0 0)
8814 23:52:47.320928 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8815 23:52:47.327647 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:52:47.330713 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:52:47.334267 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 23:52:47.340751 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 23:52:47.344178 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 23:52:47.347641 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 23:52:47.354256 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8822 23:52:47.357583 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8823 23:52:47.360904 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8824 23:52:47.367781 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:52:47.371171 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:52:47.374168 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:52:47.381195 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:52:47.384126 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:52:47.387440 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:52:47.394318 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:52:47.397676 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:52:47.401094 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:52:47.407106 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:52:47.410442 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:52:47.414146 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:52:47.420527 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:52:47.424341 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8838 23:52:47.427319 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8839 23:52:47.434140 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 23:52:47.434280 Total UI for P1: 0, mck2ui 16
8841 23:52:47.440486 best dqsien dly found for B0: ( 1, 9, 10)
8842 23:52:47.440641 Total UI for P1: 0, mck2ui 16
8843 23:52:47.447641 best dqsien dly found for B1: ( 1, 9, 10)
8844 23:52:47.450631 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8845 23:52:47.454102 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8846 23:52:47.454199
8847 23:52:47.457100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8848 23:52:47.460196 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8849 23:52:47.463772 [Gating] SW calibration Done
8850 23:52:47.463865 ==
8851 23:52:47.466868 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 23:52:47.470473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 23:52:47.470621 ==
8854 23:52:47.473774 RX Vref Scan: 0
8855 23:52:47.473866
8856 23:52:47.473932 RX Vref 0 -> 0, step: 1
8857 23:52:47.473992
8858 23:52:47.477098 RX Delay 0 -> 252, step: 8
8859 23:52:47.480381 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8860 23:52:47.487000 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8861 23:52:47.490354 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8862 23:52:47.493604 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8863 23:52:47.496975 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8864 23:52:47.500392 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8865 23:52:47.506953 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8866 23:52:47.510446 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8867 23:52:47.513147 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8868 23:52:47.517318 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8869 23:52:47.520492 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8870 23:52:47.526558 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8871 23:52:47.529895 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8872 23:52:47.533031 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8873 23:52:47.536543 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8874 23:52:47.539806 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8875 23:52:47.543331 ==
8876 23:52:47.546682 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 23:52:47.550281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 23:52:47.550377 ==
8879 23:52:47.550443 DQS Delay:
8880 23:52:47.553204 DQS0 = 0, DQS1 = 0
8881 23:52:47.553291 DQM Delay:
8882 23:52:47.556480 DQM0 = 132, DQM1 = 128
8883 23:52:47.556594 DQ Delay:
8884 23:52:47.559674 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8885 23:52:47.563095 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8886 23:52:47.566421 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8887 23:52:47.569958 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8888 23:52:47.570079
8889 23:52:47.570172
8890 23:52:47.570260 ==
8891 23:52:47.573036 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 23:52:47.579924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 23:52:47.580038 ==
8894 23:52:47.580106
8895 23:52:47.580165
8896 23:52:47.582962 TX Vref Scan disable
8897 23:52:47.583046 == TX Byte 0 ==
8898 23:52:47.586438 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8899 23:52:47.593119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8900 23:52:47.593241 == TX Byte 1 ==
8901 23:52:47.596070 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8902 23:52:47.602645 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8903 23:52:47.602770 ==
8904 23:52:47.605970 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 23:52:47.609429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 23:52:47.609528 ==
8907 23:52:47.623778
8908 23:52:47.626925 TX Vref early break, caculate TX vref
8909 23:52:47.630264 TX Vref=16, minBit 0, minWin=23, winSum=383
8910 23:52:47.633434 TX Vref=18, minBit 0, minWin=22, winSum=392
8911 23:52:47.636972 TX Vref=20, minBit 0, minWin=24, winSum=399
8912 23:52:47.640333 TX Vref=22, minBit 0, minWin=24, winSum=404
8913 23:52:47.643610 TX Vref=24, minBit 0, minWin=24, winSum=415
8914 23:52:47.649851 TX Vref=26, minBit 0, minWin=25, winSum=422
8915 23:52:47.653329 TX Vref=28, minBit 5, minWin=25, winSum=421
8916 23:52:47.656584 TX Vref=30, minBit 1, minWin=25, winSum=420
8917 23:52:47.660174 TX Vref=32, minBit 5, minWin=24, winSum=410
8918 23:52:47.663473 TX Vref=34, minBit 1, minWin=24, winSum=405
8919 23:52:47.666379 TX Vref=36, minBit 1, minWin=22, winSum=393
8920 23:52:47.673541 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8921 23:52:47.673685
8922 23:52:47.676471 Final TX Range 0 Vref 26
8923 23:52:47.676580
8924 23:52:47.676661 ==
8925 23:52:47.680312 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 23:52:47.682933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 23:52:47.683020 ==
8928 23:52:47.683084
8929 23:52:47.686682
8930 23:52:47.686766 TX Vref Scan disable
8931 23:52:47.693175 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8932 23:52:47.693278 == TX Byte 0 ==
8933 23:52:47.696242 u2DelayCellOfst[0]=15 cells (4 PI)
8934 23:52:47.699729 u2DelayCellOfst[1]=11 cells (3 PI)
8935 23:52:47.702796 u2DelayCellOfst[2]=0 cells (0 PI)
8936 23:52:47.706176 u2DelayCellOfst[3]=3 cells (1 PI)
8937 23:52:47.709416 u2DelayCellOfst[4]=7 cells (2 PI)
8938 23:52:47.712986 u2DelayCellOfst[5]=22 cells (6 PI)
8939 23:52:47.716214 u2DelayCellOfst[6]=18 cells (5 PI)
8940 23:52:47.719831 u2DelayCellOfst[7]=3 cells (1 PI)
8941 23:52:47.722549 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8942 23:52:47.726083 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8943 23:52:47.729212 == TX Byte 1 ==
8944 23:52:47.732821 u2DelayCellOfst[8]=0 cells (0 PI)
8945 23:52:47.735946 u2DelayCellOfst[9]=7 cells (2 PI)
8946 23:52:47.739307 u2DelayCellOfst[10]=15 cells (4 PI)
8947 23:52:47.739394 u2DelayCellOfst[11]=7 cells (2 PI)
8948 23:52:47.742974 u2DelayCellOfst[12]=18 cells (5 PI)
8949 23:52:47.745839 u2DelayCellOfst[13]=18 cells (5 PI)
8950 23:52:47.749394 u2DelayCellOfst[14]=18 cells (5 PI)
8951 23:52:47.752458 u2DelayCellOfst[15]=18 cells (5 PI)
8952 23:52:47.759100 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8953 23:52:47.762484 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8954 23:52:47.762577 DramC Write-DBI on
8955 23:52:47.762641 ==
8956 23:52:47.766036 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 23:52:47.772502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 23:52:47.772652 ==
8959 23:52:47.772719
8960 23:52:47.772779
8961 23:52:47.772835 TX Vref Scan disable
8962 23:52:47.776788 == TX Byte 0 ==
8963 23:52:47.780178 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8964 23:52:47.783682 == TX Byte 1 ==
8965 23:52:47.786406 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8966 23:52:47.790003 DramC Write-DBI off
8967 23:52:47.790091
8968 23:52:47.790156 [DATLAT]
8969 23:52:47.790216 Freq=1600, CH1 RK1
8970 23:52:47.790274
8971 23:52:47.793306 DATLAT Default: 0xf
8972 23:52:47.793389 0, 0xFFFF, sum = 0
8973 23:52:47.796746 1, 0xFFFF, sum = 0
8974 23:52:47.799953 2, 0xFFFF, sum = 0
8975 23:52:47.800039 3, 0xFFFF, sum = 0
8976 23:52:47.803015 4, 0xFFFF, sum = 0
8977 23:52:47.803101 5, 0xFFFF, sum = 0
8978 23:52:47.806175 6, 0xFFFF, sum = 0
8979 23:52:47.806259 7, 0xFFFF, sum = 0
8980 23:52:47.809499 8, 0xFFFF, sum = 0
8981 23:52:47.809584 9, 0xFFFF, sum = 0
8982 23:52:47.812886 10, 0xFFFF, sum = 0
8983 23:52:47.812978 11, 0xFFFF, sum = 0
8984 23:52:47.816894 12, 0xFFFF, sum = 0
8985 23:52:47.817027 13, 0x8FFF, sum = 0
8986 23:52:47.819894 14, 0x0, sum = 1
8987 23:52:47.819981 15, 0x0, sum = 2
8988 23:52:47.823340 16, 0x0, sum = 3
8989 23:52:47.823430 17, 0x0, sum = 4
8990 23:52:47.826158 best_step = 15
8991 23:52:47.826242
8992 23:52:47.826307 ==
8993 23:52:47.829583 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 23:52:47.832753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 23:52:47.832843 ==
8996 23:52:47.836064 RX Vref Scan: 0
8997 23:52:47.836151
8998 23:52:47.836216 RX Vref 0 -> 0, step: 1
8999 23:52:47.836275
9000 23:52:47.839255 RX Delay 11 -> 252, step: 4
9001 23:52:47.846263 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9002 23:52:47.849712 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9003 23:52:47.853140 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9004 23:52:47.856010 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9005 23:52:47.859454 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9006 23:52:47.862847 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9007 23:52:47.869377 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9008 23:52:47.872704 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9009 23:52:47.876285 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9010 23:52:47.879559 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9011 23:52:47.885686 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9012 23:52:47.889268 iDelay=195, Bit 11, Center 122 (67 ~ 178) 112
9013 23:52:47.892378 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
9014 23:52:47.896134 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9015 23:52:47.899159 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
9016 23:52:47.905618 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9017 23:52:47.905732 ==
9018 23:52:47.909291 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 23:52:47.912786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 23:52:47.912878 ==
9021 23:52:47.912945 DQS Delay:
9022 23:52:47.915608 DQS0 = 0, DQS1 = 0
9023 23:52:47.915690 DQM Delay:
9024 23:52:47.918914 DQM0 = 129, DQM1 = 126
9025 23:52:47.918998 DQ Delay:
9026 23:52:47.922277 DQ0 =132, DQ1 =128, DQ2 =118, DQ3 =126
9027 23:52:47.925691 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =124
9028 23:52:47.928857 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =122
9029 23:52:47.932004 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =136
9030 23:52:47.932091
9031 23:52:47.935413
9032 23:52:47.935497
9033 23:52:47.935562 [DramC_TX_OE_Calibration] TA2
9034 23:52:47.938838 Original DQ_B0 (3 6) =30, OEN = 27
9035 23:52:47.942406 Original DQ_B1 (3 6) =30, OEN = 27
9036 23:52:47.945283 24, 0x0, End_B0=24 End_B1=24
9037 23:52:47.948775 25, 0x0, End_B0=25 End_B1=25
9038 23:52:47.951975 26, 0x0, End_B0=26 End_B1=26
9039 23:52:47.952067 27, 0x0, End_B0=27 End_B1=27
9040 23:52:47.955427 28, 0x0, End_B0=28 End_B1=28
9041 23:52:47.958638 29, 0x0, End_B0=29 End_B1=29
9042 23:52:47.961879 30, 0x0, End_B0=30 End_B1=30
9043 23:52:47.965307 31, 0x4141, End_B0=30 End_B1=30
9044 23:52:47.965405 Byte0 end_step=30 best_step=27
9045 23:52:47.968956 Byte1 end_step=30 best_step=27
9046 23:52:47.971794 Byte0 TX OE(2T, 0.5T) = (3, 3)
9047 23:52:47.975077 Byte1 TX OE(2T, 0.5T) = (3, 3)
9048 23:52:47.975163
9049 23:52:47.975226
9050 23:52:47.985177 [DQSOSCAuto] RK1, (LSB)MR18= 0x131e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9051 23:52:47.985304 CH1 RK1: MR19=303, MR18=131E
9052 23:52:47.991824 CH1_RK1: MR19=0x303, MR18=0x131E, DQSOSC=394, MR23=63, INC=23, DEC=15
9053 23:52:47.995290 [RxdqsGatingPostProcess] freq 1600
9054 23:52:48.001439 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9055 23:52:48.004997 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 23:52:48.008058 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 23:52:48.011995 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 23:52:48.015069 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 23:52:48.015158 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 23:52:48.018222 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 23:52:48.021710 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 23:52:48.024947 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 23:52:48.028131 Pre-setting of DQS Precalculation
9064 23:52:48.034762 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9065 23:52:48.041181 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9066 23:52:48.048409 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 23:52:48.048532
9068 23:52:48.048631
9069 23:52:48.051217 [Calibration Summary] 3200 Mbps
9070 23:52:48.051300 CH 0, Rank 0
9071 23:52:48.055477 SW Impedance : PASS
9072 23:52:48.058190 DUTY Scan : NO K
9073 23:52:48.058277 ZQ Calibration : PASS
9074 23:52:48.061382 Jitter Meter : NO K
9075 23:52:48.064412 CBT Training : PASS
9076 23:52:48.064501 Write leveling : PASS
9077 23:52:48.067713 RX DQS gating : PASS
9078 23:52:48.067798 RX DQ/DQS(RDDQC) : PASS
9079 23:52:48.071422 TX DQ/DQS : PASS
9080 23:52:48.074457 RX DATLAT : PASS
9081 23:52:48.074549 RX DQ/DQS(Engine): PASS
9082 23:52:48.077934 TX OE : PASS
9083 23:52:48.078023 All Pass.
9084 23:52:48.078087
9085 23:52:48.081580 CH 0, Rank 1
9086 23:52:48.081666 SW Impedance : PASS
9087 23:52:48.084965 DUTY Scan : NO K
9088 23:52:48.087923 ZQ Calibration : PASS
9089 23:52:48.088007 Jitter Meter : NO K
9090 23:52:48.091239 CBT Training : PASS
9091 23:52:48.094347 Write leveling : PASS
9092 23:52:48.094434 RX DQS gating : PASS
9093 23:52:48.097609 RX DQ/DQS(RDDQC) : PASS
9094 23:52:48.100937 TX DQ/DQS : PASS
9095 23:52:48.101023 RX DATLAT : PASS
9096 23:52:48.104634 RX DQ/DQS(Engine): PASS
9097 23:52:48.107781 TX OE : PASS
9098 23:52:48.107911 All Pass.
9099 23:52:48.107996
9100 23:52:48.108074 CH 1, Rank 0
9101 23:52:48.110893 SW Impedance : PASS
9102 23:52:48.114677 DUTY Scan : NO K
9103 23:52:48.114764 ZQ Calibration : PASS
9104 23:52:48.117859 Jitter Meter : NO K
9105 23:52:48.121120 CBT Training : PASS
9106 23:52:48.121210 Write leveling : PASS
9107 23:52:48.124255 RX DQS gating : PASS
9108 23:52:48.127699 RX DQ/DQS(RDDQC) : PASS
9109 23:52:48.127791 TX DQ/DQS : PASS
9110 23:52:48.131113 RX DATLAT : PASS
9111 23:52:48.131199 RX DQ/DQS(Engine): PASS
9112 23:52:48.134631 TX OE : PASS
9113 23:52:48.134716 All Pass.
9114 23:52:48.134799
9115 23:52:48.137509 CH 1, Rank 1
9116 23:52:48.137591 SW Impedance : PASS
9117 23:52:48.141076 DUTY Scan : NO K
9118 23:52:48.143966 ZQ Calibration : PASS
9119 23:52:48.144052 Jitter Meter : NO K
9120 23:52:48.147675 CBT Training : PASS
9121 23:52:48.150891 Write leveling : PASS
9122 23:52:48.150978 RX DQS gating : PASS
9123 23:52:48.154366 RX DQ/DQS(RDDQC) : PASS
9124 23:52:48.157206 TX DQ/DQS : PASS
9125 23:52:48.157294 RX DATLAT : PASS
9126 23:52:48.160849 RX DQ/DQS(Engine): PASS
9127 23:52:48.164881 TX OE : PASS
9128 23:52:48.164973 All Pass.
9129 23:52:48.165058
9130 23:52:48.165136 DramC Write-DBI on
9131 23:52:48.167243 PER_BANK_REFRESH: Hybrid Mode
9132 23:52:48.170833 TX_TRACKING: ON
9133 23:52:48.177061 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9134 23:52:48.187268 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9135 23:52:48.193976 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9136 23:52:48.197090 [FAST_K] Save calibration result to emmc
9137 23:52:48.200821 sync common calibartion params.
9138 23:52:48.204141 sync cbt_mode0:1, 1:1
9139 23:52:48.204241 dram_init: ddr_geometry: 2
9140 23:52:48.206819 dram_init: ddr_geometry: 2
9141 23:52:48.210491 dram_init: ddr_geometry: 2
9142 23:52:48.210578 0:dram_rank_size:100000000
9143 23:52:48.213647 1:dram_rank_size:100000000
9144 23:52:48.220142 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9145 23:52:48.224132 DFS_SHUFFLE_HW_MODE: ON
9146 23:52:48.226856 dramc_set_vcore_voltage set vcore to 725000
9147 23:52:48.226951 Read voltage for 1600, 0
9148 23:52:48.230260 Vio18 = 0
9149 23:52:48.230346 Vcore = 725000
9150 23:52:48.230411 Vdram = 0
9151 23:52:48.233861 Vddq = 0
9152 23:52:48.233944 Vmddr = 0
9153 23:52:48.236839 switch to 3200 Mbps bootup
9154 23:52:48.236924 [DramcRunTimeConfig]
9155 23:52:48.236988 PHYPLL
9156 23:52:48.240236 DPM_CONTROL_AFTERK: ON
9157 23:52:48.243601 PER_BANK_REFRESH: ON
9158 23:52:48.243686 REFRESH_OVERHEAD_REDUCTION: ON
9159 23:52:48.246669 CMD_PICG_NEW_MODE: OFF
9160 23:52:48.250122 XRTWTW_NEW_MODE: ON
9161 23:52:48.250207 XRTRTR_NEW_MODE: ON
9162 23:52:48.253361 TX_TRACKING: ON
9163 23:52:48.253445 RDSEL_TRACKING: OFF
9164 23:52:48.256672 DQS Precalculation for DVFS: ON
9165 23:52:48.260319 RX_TRACKING: OFF
9166 23:52:48.260406 HW_GATING DBG: ON
9167 23:52:48.263402 ZQCS_ENABLE_LP4: ON
9168 23:52:48.263488 RX_PICG_NEW_MODE: ON
9169 23:52:48.266717 TX_PICG_NEW_MODE: ON
9170 23:52:48.266802 ENABLE_RX_DCM_DPHY: ON
9171 23:52:48.269981 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9172 23:52:48.273335 DUMMY_READ_FOR_TRACKING: OFF
9173 23:52:48.276703 !!! SPM_CONTROL_AFTERK: OFF
9174 23:52:48.280342 !!! SPM could not control APHY
9175 23:52:48.280440 IMPEDANCE_TRACKING: ON
9176 23:52:48.282981 TEMP_SENSOR: ON
9177 23:52:48.283067 HW_SAVE_FOR_SR: OFF
9178 23:52:48.286726 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9179 23:52:48.289746 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9180 23:52:48.293332 Read ODT Tracking: ON
9181 23:52:48.296147 Refresh Rate DeBounce: ON
9182 23:52:48.296260 DFS_NO_QUEUE_FLUSH: ON
9183 23:52:48.299792 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9184 23:52:48.302811 ENABLE_DFS_RUNTIME_MRW: OFF
9185 23:52:48.306505 DDR_RESERVE_NEW_MODE: ON
9186 23:52:48.306597 MR_CBT_SWITCH_FREQ: ON
9187 23:52:48.309894 =========================
9188 23:52:48.328584 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9189 23:52:48.331442 dram_init: ddr_geometry: 2
9190 23:52:48.350054 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9191 23:52:48.353215 dram_init: dram init end (result: 0)
9192 23:52:48.360014 DRAM-K: Full calibration passed in 24557 msecs
9193 23:52:48.362815 MRC: failed to locate region type 0.
9194 23:52:48.362906 DRAM rank0 size:0x100000000,
9195 23:52:48.366249 DRAM rank1 size=0x100000000
9196 23:52:48.376727 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9197 23:52:48.383018 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9198 23:52:48.389665 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9199 23:52:48.395831 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9200 23:52:48.399347 DRAM rank0 size:0x100000000,
9201 23:52:48.402443 DRAM rank1 size=0x100000000
9202 23:52:48.402530 CBMEM:
9203 23:52:48.405874 IMD: root @ 0xfffff000 254 entries.
9204 23:52:48.409451 IMD: root @ 0xffffec00 62 entries.
9205 23:52:48.412702 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9206 23:52:48.419102 WARNING: RO_VPD is uninitialized or empty.
9207 23:52:48.422503 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9208 23:52:48.430041 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9209 23:52:48.442712 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9210 23:52:48.454159 BS: romstage times (exec / console): total (unknown) / 24023 ms
9211 23:52:48.454299
9212 23:52:48.454364
9213 23:52:48.463951 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9214 23:52:48.467320 ARM64: Exception handlers installed.
9215 23:52:48.471102 ARM64: Testing exception
9216 23:52:48.473683 ARM64: Done test exception
9217 23:52:48.473780 Enumerating buses...
9218 23:52:48.477463 Show all devs... Before device enumeration.
9219 23:52:48.480657 Root Device: enabled 1
9220 23:52:48.483771 CPU_CLUSTER: 0: enabled 1
9221 23:52:48.483858 CPU: 00: enabled 1
9222 23:52:48.487046 Compare with tree...
9223 23:52:48.487129 Root Device: enabled 1
9224 23:52:48.490227 CPU_CLUSTER: 0: enabled 1
9225 23:52:48.493581 CPU: 00: enabled 1
9226 23:52:48.493668 Root Device scanning...
9227 23:52:48.497677 scan_static_bus for Root Device
9228 23:52:48.500302 CPU_CLUSTER: 0 enabled
9229 23:52:48.503459 scan_static_bus for Root Device done
9230 23:52:48.507477 scan_bus: bus Root Device finished in 8 msecs
9231 23:52:48.507574 done
9232 23:52:48.513427 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9233 23:52:48.516688 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9234 23:52:48.523267 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9235 23:52:48.527154 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9236 23:52:48.530095 Allocating resources...
9237 23:52:48.533598 Reading resources...
9238 23:52:48.536663 Root Device read_resources bus 0 link: 0
9239 23:52:48.536835 DRAM rank0 size:0x100000000,
9240 23:52:48.539844 DRAM rank1 size=0x100000000
9241 23:52:48.543716 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9242 23:52:48.546836 CPU: 00 missing read_resources
9243 23:52:48.549972 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9244 23:52:48.556382 Root Device read_resources bus 0 link: 0 done
9245 23:52:48.556518 Done reading resources.
9246 23:52:48.563502 Show resources in subtree (Root Device)...After reading.
9247 23:52:48.566375 Root Device child on link 0 CPU_CLUSTER: 0
9248 23:52:48.569727 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 23:52:48.579866 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 23:52:48.580007 CPU: 00
9251 23:52:48.582982 Root Device assign_resources, bus 0 link: 0
9252 23:52:48.586450 CPU_CLUSTER: 0 missing set_resources
9253 23:52:48.592994 Root Device assign_resources, bus 0 link: 0 done
9254 23:52:48.593130 Done setting resources.
9255 23:52:48.599912 Show resources in subtree (Root Device)...After assigning values.
9256 23:52:48.603447 Root Device child on link 0 CPU_CLUSTER: 0
9257 23:52:48.606426 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 23:52:48.616553 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 23:52:48.616743 CPU: 00
9260 23:52:48.620010 Done allocating resources.
9261 23:52:48.623023 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9262 23:52:48.626444 Enabling resources...
9263 23:52:48.626557 done.
9264 23:52:48.633127 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9265 23:52:48.633254 Initializing devices...
9266 23:52:48.636369 Root Device init
9267 23:52:48.636476 init hardware done!
9268 23:52:48.639600 0x00000018: ctrlr->caps
9269 23:52:48.643304 52.000 MHz: ctrlr->f_max
9270 23:52:48.643417 0.400 MHz: ctrlr->f_min
9271 23:52:48.646349 0x40ff8080: ctrlr->voltages
9272 23:52:48.649595 sclk: 390625
9273 23:52:48.649703 Bus Width = 1
9274 23:52:48.649795 sclk: 390625
9275 23:52:48.652765 Bus Width = 1
9276 23:52:48.652869 Early init status = 3
9277 23:52:48.659557 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9278 23:52:48.662835 in-header: 03 fc 00 00 01 00 00 00
9279 23:52:48.666397 in-data: 00
9280 23:52:48.668982 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9281 23:52:48.674606 in-header: 03 fd 00 00 00 00 00 00
9282 23:52:48.677962 in-data:
9283 23:52:48.681333 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9284 23:52:48.685765 in-header: 03 fc 00 00 01 00 00 00
9285 23:52:48.688673 in-data: 00
9286 23:52:48.692186 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9287 23:52:48.697828 in-header: 03 fd 00 00 00 00 00 00
9288 23:52:48.700948 in-data:
9289 23:52:48.704257 [SSUSB] Setting up USB HOST controller...
9290 23:52:48.707665 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9291 23:52:48.710935 [SSUSB] phy power-on done.
9292 23:52:48.714257 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9293 23:52:48.720869 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9294 23:52:48.724250 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9295 23:52:48.730958 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9296 23:52:48.737529 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9297 23:52:48.743898 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9298 23:52:48.750800 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9299 23:52:48.757474 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9300 23:52:48.760628 SPM: binary array size = 0x9dc
9301 23:52:48.763763 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9302 23:52:48.770364 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9303 23:52:48.776995 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9304 23:52:48.783757 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9305 23:52:48.786933 configure_display: Starting display init
9306 23:52:48.821018 anx7625_power_on_init: Init interface.
9307 23:52:48.824011 anx7625_disable_pd_protocol: Disabled PD feature.
9308 23:52:48.827362 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9309 23:52:48.855419 anx7625_start_dp_work: Secure OCM version=00
9310 23:52:48.858618 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9311 23:52:48.873415 sp_tx_get_edid_block: EDID Block = 1
9312 23:52:48.976308 Extracted contents:
9313 23:52:48.979154 header: 00 ff ff ff ff ff ff 00
9314 23:52:48.982469 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9315 23:52:48.985702 version: 01 04
9316 23:52:48.989185 basic params: 95 1f 11 78 0a
9317 23:52:48.992816 chroma info: 76 90 94 55 54 90 27 21 50 54
9318 23:52:48.995755 established: 00 00 00
9319 23:52:49.002316 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9320 23:52:49.008667 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9321 23:52:49.012323 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9322 23:52:49.018722 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9323 23:52:49.025389 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9324 23:52:49.028953 extensions: 00
9325 23:52:49.029083 checksum: fb
9326 23:52:49.029174
9327 23:52:49.035328 Manufacturer: IVO Model 57d Serial Number 0
9328 23:52:49.035428 Made week 0 of 2020
9329 23:52:49.038375 EDID version: 1.4
9330 23:52:49.038466 Digital display
9331 23:52:49.041685 6 bits per primary color channel
9332 23:52:49.041772 DisplayPort interface
9333 23:52:49.045072 Maximum image size: 31 cm x 17 cm
9334 23:52:49.048470 Gamma: 220%
9335 23:52:49.048555 Check DPMS levels
9336 23:52:49.055455 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9337 23:52:49.058681 First detailed timing is preferred timing
9338 23:52:49.058771 Established timings supported:
9339 23:52:49.061877 Standard timings supported:
9340 23:52:49.065051 Detailed timings
9341 23:52:49.068231 Hex of detail: 383680a07038204018303c0035ae10000019
9342 23:52:49.075360 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9343 23:52:49.078231 0780 0798 07c8 0820 hborder 0
9344 23:52:49.081783 0438 043b 0447 0458 vborder 0
9345 23:52:49.085008 -hsync -vsync
9346 23:52:49.085113 Did detailed timing
9347 23:52:49.091463 Hex of detail: 000000000000000000000000000000000000
9348 23:52:49.094732 Manufacturer-specified data, tag 0
9349 23:52:49.098074 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9350 23:52:49.101215 ASCII string: InfoVision
9351 23:52:49.104659 Hex of detail: 000000fe00523134304e574635205248200a
9352 23:52:49.107830 ASCII string: R140NWF5 RH
9353 23:52:49.107922 Checksum
9354 23:52:49.111236 Checksum: 0xfb (valid)
9355 23:52:49.114609 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9356 23:52:49.117753 DSI data_rate: 832800000 bps
9357 23:52:49.124211 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9358 23:52:49.127472 anx7625_parse_edid: pixelclock(138800).
9359 23:52:49.131409 hactive(1920), hsync(48), hfp(24), hbp(88)
9360 23:52:49.134421 vactive(1080), vsync(12), vfp(3), vbp(17)
9361 23:52:49.137523 anx7625_dsi_config: config dsi.
9362 23:52:49.144290 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9363 23:52:49.157968 anx7625_dsi_config: success to config DSI
9364 23:52:49.161228 anx7625_dp_start: MIPI phy setup OK.
9365 23:52:49.164870 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9366 23:52:49.168081 mtk_ddp_mode_set invalid vrefresh 60
9367 23:52:49.171368 main_disp_path_setup
9368 23:52:49.171456 ovl_layer_smi_id_en
9369 23:52:49.174465 ovl_layer_smi_id_en
9370 23:52:49.174553 ccorr_config
9371 23:52:49.174617 aal_config
9372 23:52:49.177843 gamma_config
9373 23:52:49.177925 postmask_config
9374 23:52:49.181173 dither_config
9375 23:52:49.184388 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9376 23:52:49.191106 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9377 23:52:49.194807 Root Device init finished in 555 msecs
9378 23:52:49.198044 CPU_CLUSTER: 0 init
9379 23:52:49.204867 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9380 23:52:49.207833 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9381 23:52:49.210832 APU_MBOX 0x190000b0 = 0x10001
9382 23:52:49.214664 APU_MBOX 0x190001b0 = 0x10001
9383 23:52:49.217787 APU_MBOX 0x190005b0 = 0x10001
9384 23:52:49.221090 APU_MBOX 0x190006b0 = 0x10001
9385 23:52:49.224346 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9386 23:52:49.237134 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9387 23:52:49.249604 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9388 23:52:49.256192 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9389 23:52:49.267665 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9390 23:52:49.276988 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9391 23:52:49.280059 CPU_CLUSTER: 0 init finished in 81 msecs
9392 23:52:49.283467 Devices initialized
9393 23:52:49.286968 Show all devs... After init.
9394 23:52:49.287060 Root Device: enabled 1
9395 23:52:49.289837 CPU_CLUSTER: 0: enabled 1
9396 23:52:49.293274 CPU: 00: enabled 1
9397 23:52:49.297060 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9398 23:52:49.300280 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9399 23:52:49.303110 ELOG: NV offset 0x57f000 size 0x1000
9400 23:52:49.309992 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9401 23:52:49.316314 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9402 23:52:49.319805 ELOG: Event(17) added with size 13 at 2024-05-29 23:52:49 UTC
9403 23:52:49.326398 out: cmd=0x121: 03 db 21 01 00 00 00 00
9404 23:52:49.329585 in-header: 03 6f 00 00 2c 00 00 00
9405 23:52:49.339713 in-data: f0 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9406 23:52:49.345894 ELOG: Event(A1) added with size 10 at 2024-05-29 23:52:49 UTC
9407 23:52:49.352796 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9408 23:52:49.359516 ELOG: Event(A0) added with size 9 at 2024-05-29 23:52:49 UTC
9409 23:52:49.362611 elog_add_boot_reason: Logged dev mode boot
9410 23:52:49.369172 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9411 23:52:49.369322 Finalize devices...
9412 23:52:49.372500 Devices finalized
9413 23:52:49.376184 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9414 23:52:49.379281 Writing coreboot table at 0xffe64000
9415 23:52:49.382423 0. 000000000010a000-0000000000113fff: RAMSTAGE
9416 23:52:49.388828 1. 0000000040000000-00000000400fffff: RAM
9417 23:52:49.392252 2. 0000000040100000-000000004032afff: RAMSTAGE
9418 23:52:49.395762 3. 000000004032b000-00000000545fffff: RAM
9419 23:52:49.399206 4. 0000000054600000-000000005465ffff: BL31
9420 23:52:49.402379 5. 0000000054660000-00000000ffe63fff: RAM
9421 23:52:49.409050 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9422 23:52:49.412511 7. 0000000100000000-000000023fffffff: RAM
9423 23:52:49.415880 Passing 5 GPIOs to payload:
9424 23:52:49.419359 NAME | PORT | POLARITY | VALUE
9425 23:52:49.425609 EC in RW | 0x000000aa | low | undefined
9426 23:52:49.428734 EC interrupt | 0x00000005 | low | undefined
9427 23:52:49.432029 TPM interrupt | 0x000000ab | high | undefined
9428 23:52:49.438944 SD card detect | 0x00000011 | high | undefined
9429 23:52:49.442238 speaker enable | 0x00000093 | high | undefined
9430 23:52:49.445522 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9431 23:52:49.449117 in-header: 03 f9 00 00 02 00 00 00
9432 23:52:49.451896 in-data: 02 00
9433 23:52:49.455718 ADC[4]: Raw value=892971 ID=7
9434 23:52:49.455813 ADC[3]: Raw value=212700 ID=1
9435 23:52:49.458979 RAM Code: 0x71
9436 23:52:49.461793 ADC[6]: Raw value=74722 ID=0
9437 23:52:49.465144 ADC[5]: Raw value=211590 ID=1
9438 23:52:49.465259 SKU Code: 0x1
9439 23:52:49.472273 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f5e
9440 23:52:49.472403 coreboot table: 964 bytes.
9441 23:52:49.475198 IMD ROOT 0. 0xfffff000 0x00001000
9442 23:52:49.478539 IMD SMALL 1. 0xffffe000 0x00001000
9443 23:52:49.482040 RO MCACHE 2. 0xffffc000 0x00001104
9444 23:52:49.485497 CONSOLE 3. 0xfff7c000 0x00080000
9445 23:52:49.488584 FMAP 4. 0xfff7b000 0x00000452
9446 23:52:49.492005 TIME STAMP 5. 0xfff7a000 0x00000910
9447 23:52:49.495148 VBOOT WORK 6. 0xfff66000 0x00014000
9448 23:52:49.498393 RAMOOPS 7. 0xffe66000 0x00100000
9449 23:52:49.501570 COREBOOT 8. 0xffe64000 0x00002000
9450 23:52:49.505035 IMD small region:
9451 23:52:49.508695 IMD ROOT 0. 0xffffec00 0x00000400
9452 23:52:49.511623 VPD 1. 0xffffeb80 0x0000006c
9453 23:52:49.515034 MMC STATUS 2. 0xffffeb60 0x00000004
9454 23:52:49.518494 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9455 23:52:49.521783 Probing TPM: done!
9456 23:52:49.525305 Connected to device vid:did:rid of 1ae0:0028:00
9457 23:52:49.536129 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9458 23:52:49.539583 Initialized TPM device CR50 revision 0
9459 23:52:49.543284 Checking cr50 for pending updates
9460 23:52:49.546571 Reading cr50 TPM mode
9461 23:52:49.555723 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9462 23:52:49.562299 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9463 23:52:49.601841 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9464 23:52:49.605843 Checking segment from ROM address 0x40100000
9465 23:52:49.608729 Checking segment from ROM address 0x4010001c
9466 23:52:49.615559 Loading segment from ROM address 0x40100000
9467 23:52:49.615703 code (compression=0)
9468 23:52:49.626087 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9469 23:52:49.632116 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9470 23:52:49.632283 it's not compressed!
9471 23:52:49.638847 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9472 23:52:49.642154 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9473 23:52:49.662853 Loading segment from ROM address 0x4010001c
9474 23:52:49.663026 Entry Point 0x80000000
9475 23:52:49.666034 Loaded segments
9476 23:52:49.669419 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9477 23:52:49.676068 Jumping to boot code at 0x80000000(0xffe64000)
9478 23:52:49.682835 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9479 23:52:49.688971 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9480 23:52:49.697103 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9481 23:52:49.700375 Checking segment from ROM address 0x40100000
9482 23:52:49.703474 Checking segment from ROM address 0x4010001c
9483 23:52:49.710642 Loading segment from ROM address 0x40100000
9484 23:52:49.710792 code (compression=1)
9485 23:52:49.717341 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9486 23:52:49.726993 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9487 23:52:49.727154 using LZMA
9488 23:52:49.735239 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9489 23:52:49.742664 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9490 23:52:49.745084 Loading segment from ROM address 0x4010001c
9491 23:52:49.745210 Entry Point 0x54601000
9492 23:52:49.748436 Loaded segments
9493 23:52:49.751576 NOTICE: MT8192 bl31_setup
9494 23:52:49.758956 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9495 23:52:49.761969 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9496 23:52:49.765767 WARNING: region 0:
9497 23:52:49.768845 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 23:52:49.768944 WARNING: region 1:
9499 23:52:49.775478 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9500 23:52:49.778614 WARNING: region 2:
9501 23:52:49.782622 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9502 23:52:49.785644 WARNING: region 3:
9503 23:52:49.788577 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 23:52:49.792423 WARNING: region 4:
9505 23:52:49.798746 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 23:52:49.798883 WARNING: region 5:
9507 23:52:49.802063 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 23:52:49.806252 WARNING: region 6:
9509 23:52:49.809006 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 23:52:49.812253 WARNING: region 7:
9511 23:52:49.815538 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 23:52:49.822102 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9513 23:52:49.825578 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9514 23:52:49.828731 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9515 23:52:49.835500 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9516 23:52:49.838987 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9517 23:52:49.842263 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9518 23:52:49.848796 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9519 23:52:49.852397 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9520 23:52:49.858817 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9521 23:52:49.861910 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9522 23:52:49.865831 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9523 23:52:49.872238 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9524 23:52:49.875449 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9525 23:52:49.878437 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9526 23:52:49.885310 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9527 23:52:49.888410 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9528 23:52:49.895847 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9529 23:52:49.899127 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9530 23:52:49.902010 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9531 23:52:49.908671 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9532 23:52:49.911899 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9533 23:52:49.915293 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9534 23:52:49.922060 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9535 23:52:49.925461 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9536 23:52:49.932135 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9537 23:52:49.935451 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9538 23:52:49.938542 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9539 23:52:49.945343 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9540 23:52:49.948627 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9541 23:52:49.955118 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9542 23:52:49.958989 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9543 23:52:49.962053 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9544 23:52:49.968712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9545 23:52:49.972050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9546 23:52:49.975158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9547 23:52:49.979038 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9548 23:52:49.985553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9549 23:52:49.988524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9550 23:52:49.992198 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9551 23:52:49.995300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9552 23:52:50.001885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9553 23:52:50.005283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9554 23:52:50.008971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9555 23:52:50.012327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9556 23:52:50.018834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9557 23:52:50.022049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9558 23:52:50.025262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9559 23:52:50.028505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9560 23:52:50.035539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9561 23:52:50.039154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9562 23:52:50.045608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9563 23:52:50.048655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9564 23:52:50.052086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9565 23:52:50.058737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9566 23:52:50.062236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9567 23:52:50.068707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9568 23:52:50.071930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9569 23:52:50.078513 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9570 23:52:50.081879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9571 23:52:50.085130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9572 23:52:50.091847 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9573 23:52:50.095738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9574 23:52:50.102093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9575 23:52:50.105378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9576 23:52:50.111876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9577 23:52:50.115445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9578 23:52:50.121997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9579 23:52:50.125425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9580 23:52:50.128555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9581 23:52:50.135326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9582 23:52:50.138609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9583 23:52:50.145189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9584 23:52:50.148676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9585 23:52:50.155500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9586 23:52:50.158679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9587 23:52:50.162025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9588 23:52:50.168698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9589 23:52:50.171928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9590 23:52:50.178381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9591 23:52:50.181660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9592 23:52:50.188605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9593 23:52:50.191730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9594 23:52:50.198365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9595 23:52:50.202106 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9596 23:52:50.205593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9597 23:52:50.212210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9598 23:52:50.215457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9599 23:52:50.221946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9600 23:52:50.225120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9601 23:52:50.228494 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9602 23:52:50.235161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9603 23:52:50.238719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9604 23:52:50.245539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9605 23:52:50.248572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9606 23:52:50.255223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9607 23:52:50.258479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9608 23:52:50.261634 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9609 23:52:50.269042 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9610 23:52:50.271647 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9611 23:52:50.275075 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9612 23:52:50.278581 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9613 23:52:50.285425 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9614 23:52:50.288480 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9615 23:52:50.295054 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9616 23:52:50.298582 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9617 23:52:50.301890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9618 23:52:50.308679 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9619 23:52:50.311786 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9620 23:52:50.318720 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9621 23:52:50.322121 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9622 23:52:50.325366 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9623 23:52:50.331765 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9624 23:52:50.335324 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9625 23:52:50.342176 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9626 23:52:50.344913 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9627 23:52:50.348579 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9628 23:52:50.352012 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9629 23:52:50.358287 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9630 23:52:50.361647 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9631 23:52:50.364980 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9632 23:52:50.372040 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9633 23:52:50.375523 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9634 23:52:50.378242 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9635 23:52:50.381476 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9636 23:52:50.388182 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9637 23:52:50.391353 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9638 23:52:50.398513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9639 23:52:50.401829 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9640 23:52:50.405228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9641 23:52:50.411648 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9642 23:52:50.414817 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9643 23:52:50.421466 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9644 23:52:50.424842 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9645 23:52:50.428107 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9646 23:52:50.435384 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9647 23:52:50.438158 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9648 23:52:50.444757 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9649 23:52:50.448174 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9650 23:52:50.451653 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9651 23:52:50.458257 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9652 23:52:50.461383 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9653 23:52:50.465027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9654 23:52:50.471356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9655 23:52:50.474869 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9656 23:52:50.481515 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9657 23:52:50.484915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9658 23:52:50.488169 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9659 23:52:50.495228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9660 23:52:50.498237 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9661 23:52:50.505031 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9662 23:52:50.508125 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9663 23:52:50.511621 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9664 23:52:50.518228 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9665 23:52:50.521878 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9666 23:52:50.525532 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9667 23:52:50.531514 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9668 23:52:50.534852 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9669 23:52:50.541630 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9670 23:52:50.544595 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9671 23:52:50.548128 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9672 23:52:50.554758 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9673 23:52:50.558302 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9674 23:52:50.564834 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9675 23:52:50.568056 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9676 23:52:50.571733 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9677 23:52:50.577992 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9678 23:52:50.581129 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9679 23:52:50.584870 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9680 23:52:50.591300 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9681 23:52:50.594909 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9682 23:52:50.600816 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9683 23:52:50.604873 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9684 23:52:50.607864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9685 23:52:50.614336 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9686 23:52:50.617546 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9687 23:52:50.624430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9688 23:52:50.627347 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9689 23:52:50.634426 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9690 23:52:50.637706 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9691 23:52:50.640846 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9692 23:52:50.647677 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9693 23:52:50.650659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9694 23:52:50.653811 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9695 23:52:50.660458 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9696 23:52:50.664235 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9697 23:52:50.671032 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9698 23:52:50.673820 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9699 23:52:50.677154 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9700 23:52:50.683914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9701 23:52:50.687115 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9702 23:52:50.694216 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9703 23:52:50.697452 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9704 23:52:50.703912 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9705 23:52:50.706997 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9706 23:52:50.710354 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9707 23:52:50.717854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9708 23:52:50.720121 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9709 23:52:50.727156 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9710 23:52:50.730386 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9711 23:52:50.736726 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9712 23:52:50.740208 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9713 23:52:50.743834 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9714 23:52:50.750555 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9715 23:52:50.753369 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9716 23:52:50.760176 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9717 23:52:50.763258 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9718 23:52:50.766909 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9719 23:52:50.773423 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9720 23:52:50.776710 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9721 23:52:50.783391 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9722 23:52:50.786564 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9723 23:52:50.790055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9724 23:52:50.796602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9725 23:52:50.799751 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9726 23:52:50.806593 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9727 23:52:50.809911 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9728 23:52:50.816242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9729 23:52:50.820004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9730 23:52:50.822980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9731 23:52:50.829517 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9732 23:52:50.832978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9733 23:52:50.839383 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9734 23:52:50.843048 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9735 23:52:50.846474 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9736 23:52:50.852913 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9737 23:52:50.856129 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9738 23:52:50.863308 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9739 23:52:50.866111 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9740 23:52:50.872713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9741 23:52:50.876148 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9742 23:52:50.879392 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9743 23:52:50.882572 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9744 23:52:50.886546 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9745 23:52:50.892486 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9746 23:52:50.895976 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9747 23:52:50.899315 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9748 23:52:50.906179 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9749 23:52:50.909125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9750 23:52:50.916016 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9751 23:52:50.919350 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9752 23:52:50.922402 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9753 23:52:50.929140 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9754 23:52:50.932430 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9755 23:52:50.935899 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9756 23:52:50.942731 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9757 23:52:50.946141 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9758 23:52:50.952518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9759 23:52:50.955744 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9760 23:52:50.959265 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9761 23:52:50.965694 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9762 23:52:50.968818 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9763 23:52:50.972062 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9764 23:52:50.978833 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9765 23:52:50.982017 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9766 23:52:50.985266 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9767 23:52:50.992019 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9768 23:52:50.995309 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9769 23:52:51.001930 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9770 23:52:51.005384 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9771 23:52:51.008490 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9772 23:52:51.015139 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9773 23:52:51.018646 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9774 23:52:51.025253 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9775 23:52:51.028461 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9776 23:52:51.031639 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9777 23:52:51.038439 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9778 23:52:51.041860 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9779 23:52:51.044896 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9780 23:52:51.051616 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9781 23:52:51.054894 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9782 23:52:51.058304 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9783 23:52:51.061526 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9784 23:52:51.065197 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9785 23:52:51.071772 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9786 23:52:51.074828 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9787 23:52:51.078380 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9788 23:52:51.081985 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9789 23:52:51.088458 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9790 23:52:51.091866 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9791 23:52:51.095147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9792 23:52:51.101421 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9793 23:52:51.104591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9794 23:52:51.107913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9795 23:52:51.114779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9796 23:52:51.118145 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9797 23:52:51.121403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9798 23:52:51.128289 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9799 23:52:51.131852 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9800 23:52:51.138021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9801 23:52:51.141167 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9802 23:52:51.144880 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9803 23:52:51.151454 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9804 23:52:51.154572 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9805 23:52:51.161280 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9806 23:52:51.164529 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9807 23:52:51.170829 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9808 23:52:51.174884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9809 23:52:51.177440 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9810 23:52:51.184267 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9811 23:52:51.188003 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9812 23:52:51.194188 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9813 23:52:51.197705 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9814 23:52:51.200971 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9815 23:52:51.207634 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9816 23:52:51.210934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9817 23:52:51.217626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9818 23:52:51.220970 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9819 23:52:51.224252 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9820 23:52:51.230647 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9821 23:52:51.234189 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9822 23:52:51.240836 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9823 23:52:51.243913 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9824 23:52:51.250677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9825 23:52:51.253974 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9826 23:52:51.257377 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9827 23:52:51.263611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9828 23:52:51.266992 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9829 23:52:51.273715 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9830 23:52:51.276988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9831 23:52:51.283637 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9832 23:52:51.287120 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9833 23:52:51.290383 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9834 23:52:51.296728 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9835 23:52:51.299966 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9836 23:52:51.306884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9837 23:52:51.310304 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9838 23:52:51.313539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9839 23:52:51.320465 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9840 23:52:51.323886 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9841 23:52:51.329984 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9842 23:52:51.333337 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9843 23:52:51.336390 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9844 23:52:51.343588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9845 23:52:51.346909 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9846 23:52:51.353205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9847 23:52:51.356490 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9848 23:52:51.363312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9849 23:52:51.366729 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9850 23:52:51.369794 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9851 23:52:51.376676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9852 23:52:51.379669 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9853 23:52:51.386332 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9854 23:52:51.389874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9855 23:52:51.392997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9856 23:52:51.399549 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9857 23:52:51.402899 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9858 23:52:51.409551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9859 23:52:51.412798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9860 23:52:51.416046 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9861 23:52:51.422583 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9862 23:52:51.425877 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9863 23:52:51.432543 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9864 23:52:51.435779 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9865 23:52:51.439167 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9866 23:52:51.445875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9867 23:52:51.449099 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9868 23:52:51.455957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9869 23:52:51.459108 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9870 23:52:51.466176 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9871 23:52:51.469382 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9872 23:52:51.475704 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9873 23:52:51.479052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9874 23:52:51.482474 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9875 23:52:51.488782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9876 23:52:51.492316 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9877 23:52:51.499053 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9878 23:52:51.502175 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9879 23:52:51.508937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9880 23:52:51.512343 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9881 23:52:51.515617 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9882 23:52:51.522063 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9883 23:52:51.525842 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9884 23:52:51.531919 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9885 23:52:51.535411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9886 23:52:51.541967 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9887 23:52:51.545191 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9888 23:52:51.552189 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9889 23:52:51.555044 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9890 23:52:51.558345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9891 23:52:51.564977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9892 23:52:51.568501 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9893 23:52:51.574995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9894 23:52:51.578213 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9895 23:52:51.585184 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9896 23:52:51.588155 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9897 23:52:51.591504 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9898 23:52:51.598521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9899 23:52:51.601434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9900 23:52:51.608280 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9901 23:52:51.611710 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9902 23:52:51.618327 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9903 23:52:51.621577 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9904 23:52:51.628466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9905 23:52:51.631705 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9906 23:52:51.635057 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9907 23:52:51.641534 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9908 23:52:51.644519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9909 23:52:51.651251 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9910 23:52:51.654447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9911 23:52:51.661251 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9912 23:52:51.664163 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9913 23:52:51.667804 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9914 23:52:51.674369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9915 23:52:51.677674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9916 23:52:51.684252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9917 23:52:51.687481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9918 23:52:51.694053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9919 23:52:51.697893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9920 23:52:51.704493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9921 23:52:51.707663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9922 23:52:51.714324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9923 23:52:51.717475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9924 23:52:51.724163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9925 23:52:51.727310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9926 23:52:51.733952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9927 23:52:51.737534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9928 23:52:51.740397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9929 23:52:51.747367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9930 23:52:51.750837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9931 23:52:51.756955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9932 23:52:51.760518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9933 23:52:51.767368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9934 23:52:51.770780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9935 23:52:51.777215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9936 23:52:51.780394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9937 23:52:51.786801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9938 23:52:51.789893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9939 23:52:51.797069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9940 23:52:51.800470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9941 23:52:51.806767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9942 23:52:51.810408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9943 23:52:51.817237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9944 23:52:51.819807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9945 23:52:51.826450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9946 23:52:51.830366 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9947 23:52:51.833460 INFO: [APUAPC] vio 0
9948 23:52:51.836660 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9949 23:52:51.843145 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9950 23:52:51.846482 INFO: [APUAPC] D0_APC_0: 0x400510
9951 23:52:51.850302 INFO: [APUAPC] D0_APC_1: 0x0
9952 23:52:51.853026 INFO: [APUAPC] D0_APC_2: 0x1540
9953 23:52:51.853110 INFO: [APUAPC] D0_APC_3: 0x0
9954 23:52:51.856518 INFO: [APUAPC] D1_APC_0: 0xffffffff
9955 23:52:51.859643 INFO: [APUAPC] D1_APC_1: 0xffffffff
9956 23:52:51.863150 INFO: [APUAPC] D1_APC_2: 0x3fffff
9957 23:52:51.866374 INFO: [APUAPC] D1_APC_3: 0x0
9958 23:52:51.870228 INFO: [APUAPC] D2_APC_0: 0xffffffff
9959 23:52:51.872729 INFO: [APUAPC] D2_APC_1: 0xffffffff
9960 23:52:51.876466 INFO: [APUAPC] D2_APC_2: 0x3fffff
9961 23:52:51.879764 INFO: [APUAPC] D2_APC_3: 0x0
9962 23:52:51.883325 INFO: [APUAPC] D3_APC_0: 0xffffffff
9963 23:52:51.886709 INFO: [APUAPC] D3_APC_1: 0xffffffff
9964 23:52:51.889380 INFO: [APUAPC] D3_APC_2: 0x3fffff
9965 23:52:51.893218 INFO: [APUAPC] D3_APC_3: 0x0
9966 23:52:51.896293 INFO: [APUAPC] D4_APC_0: 0xffffffff
9967 23:52:51.899599 INFO: [APUAPC] D4_APC_1: 0xffffffff
9968 23:52:51.903203 INFO: [APUAPC] D4_APC_2: 0x3fffff
9969 23:52:51.906154 INFO: [APUAPC] D4_APC_3: 0x0
9970 23:52:51.909481 INFO: [APUAPC] D5_APC_0: 0xffffffff
9971 23:52:51.913054 INFO: [APUAPC] D5_APC_1: 0xffffffff
9972 23:52:51.915978 INFO: [APUAPC] D5_APC_2: 0x3fffff
9973 23:52:51.919199 INFO: [APUAPC] D5_APC_3: 0x0
9974 23:52:51.922440 INFO: [APUAPC] D6_APC_0: 0xffffffff
9975 23:52:51.926210 INFO: [APUAPC] D6_APC_1: 0xffffffff
9976 23:52:51.929624 INFO: [APUAPC] D6_APC_2: 0x3fffff
9977 23:52:51.932367 INFO: [APUAPC] D6_APC_3: 0x0
9978 23:52:51.935821 INFO: [APUAPC] D7_APC_0: 0xffffffff
9979 23:52:51.939092 INFO: [APUAPC] D7_APC_1: 0xffffffff
9980 23:52:51.942579 INFO: [APUAPC] D7_APC_2: 0x3fffff
9981 23:52:51.945480 INFO: [APUAPC] D7_APC_3: 0x0
9982 23:52:51.949129 INFO: [APUAPC] D8_APC_0: 0xffffffff
9983 23:52:51.952508 INFO: [APUAPC] D8_APC_1: 0xffffffff
9984 23:52:51.955446 INFO: [APUAPC] D8_APC_2: 0x3fffff
9985 23:52:51.958668 INFO: [APUAPC] D8_APC_3: 0x0
9986 23:52:51.962552 INFO: [APUAPC] D9_APC_0: 0xffffffff
9987 23:52:51.965385 INFO: [APUAPC] D9_APC_1: 0xffffffff
9988 23:52:51.969027 INFO: [APUAPC] D9_APC_2: 0x3fffff
9989 23:52:51.972138 INFO: [APUAPC] D9_APC_3: 0x0
9990 23:52:51.975317 INFO: [APUAPC] D10_APC_0: 0xffffffff
9991 23:52:51.978783 INFO: [APUAPC] D10_APC_1: 0xffffffff
9992 23:52:51.982112 INFO: [APUAPC] D10_APC_2: 0x3fffff
9993 23:52:51.985269 INFO: [APUAPC] D10_APC_3: 0x0
9994 23:52:51.988710 INFO: [APUAPC] D11_APC_0: 0xffffffff
9995 23:52:51.992278 INFO: [APUAPC] D11_APC_1: 0xffffffff
9996 23:52:51.995574 INFO: [APUAPC] D11_APC_2: 0x3fffff
9997 23:52:51.998612 INFO: [APUAPC] D11_APC_3: 0x0
9998 23:52:52.001731 INFO: [APUAPC] D12_APC_0: 0xffffffff
9999 23:52:52.005356 INFO: [APUAPC] D12_APC_1: 0xffffffff
10000 23:52:52.008595 INFO: [APUAPC] D12_APC_2: 0x3fffff
10001 23:52:52.011807 INFO: [APUAPC] D12_APC_3: 0x0
10002 23:52:52.015035 INFO: [APUAPC] D13_APC_0: 0xffffffff
10003 23:52:52.018291 INFO: [APUAPC] D13_APC_1: 0xffffffff
10004 23:52:52.021978 INFO: [APUAPC] D13_APC_2: 0x3fffff
10005 23:52:52.025119 INFO: [APUAPC] D13_APC_3: 0x0
10006 23:52:52.028523 INFO: [APUAPC] D14_APC_0: 0xffffffff
10007 23:52:52.032064 INFO: [APUAPC] D14_APC_1: 0xffffffff
10008 23:52:52.034625 INFO: [APUAPC] D14_APC_2: 0x3fffff
10009 23:52:52.037987 INFO: [APUAPC] D14_APC_3: 0x0
10010 23:52:52.041418 INFO: [APUAPC] D15_APC_0: 0xffffffff
10011 23:52:52.044735 INFO: [APUAPC] D15_APC_1: 0xffffffff
10012 23:52:52.047861 INFO: [APUAPC] D15_APC_2: 0x3fffff
10013 23:52:52.051330 INFO: [APUAPC] D15_APC_3: 0x0
10014 23:52:52.054889 INFO: [APUAPC] APC_CON: 0x4
10015 23:52:52.057941 INFO: [NOCDAPC] D0_APC_0: 0x0
10016 23:52:52.061630 INFO: [NOCDAPC] D0_APC_1: 0x0
10017 23:52:52.064550 INFO: [NOCDAPC] D1_APC_0: 0x0
10018 23:52:52.067682 INFO: [NOCDAPC] D1_APC_1: 0xfff
10019 23:52:52.067764 INFO: [NOCDAPC] D2_APC_0: 0x0
10020 23:52:52.071566 INFO: [NOCDAPC] D2_APC_1: 0xfff
10021 23:52:52.074240 INFO: [NOCDAPC] D3_APC_0: 0x0
10022 23:52:52.077852 INFO: [NOCDAPC] D3_APC_1: 0xfff
10023 23:52:52.081191 INFO: [NOCDAPC] D4_APC_0: 0x0
10024 23:52:52.084469 INFO: [NOCDAPC] D4_APC_1: 0xfff
10025 23:52:52.087522 INFO: [NOCDAPC] D5_APC_0: 0x0
10026 23:52:52.091183 INFO: [NOCDAPC] D5_APC_1: 0xfff
10027 23:52:52.094472 INFO: [NOCDAPC] D6_APC_0: 0x0
10028 23:52:52.098110 INFO: [NOCDAPC] D6_APC_1: 0xfff
10029 23:52:52.100985 INFO: [NOCDAPC] D7_APC_0: 0x0
10030 23:52:52.104479 INFO: [NOCDAPC] D7_APC_1: 0xfff
10031 23:52:52.104624 INFO: [NOCDAPC] D8_APC_0: 0x0
10032 23:52:52.107506 INFO: [NOCDAPC] D8_APC_1: 0xfff
10033 23:52:52.110592 INFO: [NOCDAPC] D9_APC_0: 0x0
10034 23:52:52.114419 INFO: [NOCDAPC] D9_APC_1: 0xfff
10035 23:52:52.117273 INFO: [NOCDAPC] D10_APC_0: 0x0
10036 23:52:52.120476 INFO: [NOCDAPC] D10_APC_1: 0xfff
10037 23:52:52.123882 INFO: [NOCDAPC] D11_APC_0: 0x0
10038 23:52:52.127533 INFO: [NOCDAPC] D11_APC_1: 0xfff
10039 23:52:52.130741 INFO: [NOCDAPC] D12_APC_0: 0x0
10040 23:52:52.134163 INFO: [NOCDAPC] D12_APC_1: 0xfff
10041 23:52:52.137161 INFO: [NOCDAPC] D13_APC_0: 0x0
10042 23:52:52.140327 INFO: [NOCDAPC] D13_APC_1: 0xfff
10043 23:52:52.143670 INFO: [NOCDAPC] D14_APC_0: 0x0
10044 23:52:52.147037 INFO: [NOCDAPC] D14_APC_1: 0xfff
10045 23:52:52.147120 INFO: [NOCDAPC] D15_APC_0: 0x0
10046 23:52:52.150285 INFO: [NOCDAPC] D15_APC_1: 0xfff
10047 23:52:52.153679 INFO: [NOCDAPC] APC_CON: 0x4
10048 23:52:52.157314 INFO: [APUAPC] set_apusys_apc done
10049 23:52:52.160716 INFO: [DEVAPC] devapc_init done
10050 23:52:52.163639 INFO: GICv3 without legacy support detected.
10051 23:52:52.170353 INFO: ARM GICv3 driver initialized in EL3
10052 23:52:52.174155 INFO: Maximum SPI INTID supported: 639
10053 23:52:52.177037 INFO: BL31: Initializing runtime services
10054 23:52:52.183811 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10055 23:52:52.187088 INFO: SPM: enable CPC mode
10056 23:52:52.190263 INFO: mcdi ready for mcusys-off-idle and system suspend
10057 23:52:52.197159 INFO: BL31: Preparing for EL3 exit to normal world
10058 23:52:52.200184 INFO: Entry point address = 0x80000000
10059 23:52:52.200279 INFO: SPSR = 0x8
10060 23:52:52.206769
10061 23:52:52.206879
10062 23:52:52.206946
10063 23:52:52.209884 Starting depthcharge on Spherion...
10064 23:52:52.209972
10065 23:52:52.210036 Wipe memory regions:
10066 23:52:52.210095
10067 23:52:52.210757 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10068 23:52:52.210858 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10069 23:52:52.210943 Setting prompt string to ['asurada:']
10070 23:52:52.211025 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10071 23:52:52.213440 [0x00000040000000, 0x00000054600000)
10072 23:52:52.336087
10073 23:52:52.336245 [0x00000054660000, 0x00000080000000)
10074 23:52:52.596339
10075 23:52:52.596495 [0x000000821a7280, 0x000000ffe64000)
10076 23:52:53.340542
10077 23:52:53.340689 [0x00000100000000, 0x00000240000000)
10078 23:52:55.229658
10079 23:52:55.233021 Initializing XHCI USB controller at 0x11200000.
10080 23:52:56.270573
10081 23:52:56.273964 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10082 23:52:56.274055
10083 23:52:56.274119
10084 23:52:56.274398 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 23:52:56.374785 asurada: tftpboot 192.168.201.1 14084347/tftp-deploy-zua2va7t/kernel/image.itb 14084347/tftp-deploy-zua2va7t/kernel/cmdline
10087 23:52:56.375220 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 23:52:56.375305 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10089 23:52:56.379684 tftpboot 192.168.201.1 14084347/tftp-deploy-zua2va7t/kernel/image.itp-deploy-zua2va7t/kernel/cmdline
10090 23:52:56.379769
10091 23:52:56.379833 Waiting for link
10092 23:52:56.540085
10093 23:52:56.540215 R8152: Initializing
10094 23:52:56.540283
10095 23:52:56.543260 Version 6 (ocp_data = 5c30)
10096 23:52:56.543343
10097 23:52:56.546876 R8152: Done initializing
10098 23:52:56.546958
10099 23:52:56.547022 Adding net device
10100 23:52:58.638964
10101 23:52:58.639119 done.
10102 23:52:58.639212
10103 23:52:58.639299 MAC: 00:24:32:30:78:ff
10104 23:52:58.639384
10105 23:52:58.641965 Sending DHCP discover... done.
10106 23:52:58.642049
10107 23:53:01.921466 Waiting for reply... done.
10108 23:53:01.921607
10109 23:53:01.921674 Sending DHCP request... done.
10110 23:53:01.924902
10111 23:53:01.924987 Waiting for reply... done.
10112 23:53:01.925052
10113 23:53:01.928250 My ip is 192.168.201.21
10114 23:53:01.928332
10115 23:53:01.931338 The DHCP server ip is 192.168.201.1
10116 23:53:01.931429
10117 23:53:01.935326 TFTP server IP predefined by user: 192.168.201.1
10118 23:53:01.935410
10119 23:53:01.941761 Bootfile predefined by user: 14084347/tftp-deploy-zua2va7t/kernel/image.itb
10120 23:53:01.941848
10121 23:53:01.944687 Sending tftp read request... done.
10122 23:53:01.944770
10123 23:53:01.948006 Waiting for the transfer...
10124 23:53:01.948093
10125 23:53:02.497816 00000000 ################################################################
10126 23:53:02.498004
10127 23:53:03.049599 00080000 ################################################################
10128 23:53:03.049773
10129 23:53:03.586829 00100000 ################################################################
10130 23:53:03.586968
10131 23:53:04.157372 00180000 ################################################################
10132 23:53:04.157509
10133 23:53:04.704848 00200000 ################################################################
10134 23:53:04.705019
10135 23:53:05.256055 00280000 ################################################################
10136 23:53:05.256227
10137 23:53:05.798761 00300000 ################################################################
10138 23:53:05.798900
10139 23:53:06.366138 00380000 ################################################################
10140 23:53:06.366325
10141 23:53:06.933667 00400000 ################################################################
10142 23:53:06.933858
10143 23:53:07.485668 00480000 ################################################################
10144 23:53:07.485853
10145 23:53:08.058309 00500000 ################################################################
10146 23:53:08.058502
10147 23:53:08.623986 00580000 ################################################################
10148 23:53:08.624179
10149 23:53:09.184761 00600000 ################################################################
10150 23:53:09.184896
10151 23:53:09.726570 00680000 ################################################################
10152 23:53:09.726772
10153 23:53:10.288524 00700000 ################################################################
10154 23:53:10.288674
10155 23:53:10.873998 00780000 ################################################################
10156 23:53:10.874148
10157 23:53:11.464935 00800000 ################################################################
10158 23:53:11.465087
10159 23:53:12.034471 00880000 ################################################################
10160 23:53:12.034624
10161 23:53:12.594810 00900000 ################################################################
10162 23:53:12.594963
10163 23:53:13.165301 00980000 ################################################################
10164 23:53:13.165441
10165 23:53:13.763882 00a00000 ################################################################
10166 23:53:13.764075
10167 23:53:14.367049 00a80000 ################################################################
10168 23:53:14.367181
10169 23:53:14.912203 00b00000 ################################################################
10170 23:53:14.912375
10171 23:53:15.436706 00b80000 ################################################################
10172 23:53:15.436839
10173 23:53:15.952643 00c00000 ################################################################
10174 23:53:15.952817
10175 23:53:16.480763 00c80000 ################################################################
10176 23:53:16.480936
10177 23:53:17.000187 00d00000 ################################################################
10178 23:53:17.000323
10179 23:53:17.525477 00d80000 ################################################################
10180 23:53:17.525609
10181 23:53:18.057970 00e00000 ################################################################
10182 23:53:18.058108
10183 23:53:18.592310 00e80000 ################################################################
10184 23:53:18.592465
10185 23:53:19.120785 00f00000 ################################################################
10186 23:53:19.120957
10187 23:53:19.649731 00f80000 ################################################################
10188 23:53:19.649875
10189 23:53:20.175997 01000000 ################################################################
10190 23:53:20.176170
10191 23:53:20.706882 01080000 ################################################################
10192 23:53:20.707098
10193 23:53:21.237252 01100000 ################################################################
10194 23:53:21.237399
10195 23:53:21.778703 01180000 ################################################################
10196 23:53:21.778865
10197 23:53:22.309106 01200000 ################################################################
10198 23:53:22.309274
10199 23:53:22.842023 01280000 ################################################################
10200 23:53:22.842162
10201 23:53:23.378340 01300000 ################################################################
10202 23:53:23.378490
10203 23:53:23.909200 01380000 ################################################################
10204 23:53:23.909379
10205 23:53:24.439480 01400000 ################################################################
10206 23:53:24.439696
10207 23:53:24.964881 01480000 ################################################################
10208 23:53:24.965055
10209 23:53:25.491354 01500000 ################################################################
10210 23:53:25.491521
10211 23:53:26.015585 01580000 ################################################################
10212 23:53:26.015718
10213 23:53:26.547507 01600000 ################################################################
10214 23:53:26.547668
10215 23:53:27.080967 01680000 ################################################################
10216 23:53:27.081101
10217 23:53:27.608236 01700000 ################################################################
10218 23:53:27.608400
10219 23:53:28.140324 01780000 ################################################################
10220 23:53:28.140489
10221 23:53:28.674301 01800000 ################################################################
10222 23:53:28.674458
10223 23:53:29.204077 01880000 ################################################################
10224 23:53:29.204208
10225 23:53:29.734849 01900000 ################################################################
10226 23:53:29.734984
10227 23:53:30.295040 01980000 ################################################################
10228 23:53:30.295184
10229 23:53:30.845204 01a00000 ################################################################
10230 23:53:30.845377
10231 23:53:31.394051 01a80000 ################################################################
10232 23:53:31.394225
10233 23:53:31.925540 01b00000 ################################################################
10234 23:53:31.925682
10235 23:53:32.455192 01b80000 ################################################################
10236 23:53:32.455353
10237 23:53:32.998315 01c00000 ################################################################
10238 23:53:32.998485
10239 23:53:33.535784 01c80000 ################################################################
10240 23:53:33.535919
10241 23:53:34.077163 01d00000 ################################################################
10242 23:53:34.077338
10243 23:53:34.630649 01d80000 ################################################################
10244 23:53:34.630822
10245 23:53:35.051568 01e00000 ############################################### done.
10246 23:53:35.051711
10247 23:53:35.055432 The bootfile was 31840162 bytes long.
10248 23:53:35.055515
10249 23:53:35.058488 Sending tftp read request... done.
10250 23:53:35.058569
10251 23:53:35.058632 Waiting for the transfer...
10252 23:53:35.058691
10253 23:53:35.062031 00000000 # done.
10254 23:53:35.062114
10255 23:53:35.068748 Command line loaded dynamically from TFTP file: 14084347/tftp-deploy-zua2va7t/kernel/cmdline
10256 23:53:35.068833
10257 23:53:35.091604 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10258 23:53:35.091695
10259 23:53:35.091761 Loading FIT.
10260 23:53:35.091821
10261 23:53:35.094802 Image ramdisk-1 has 18727384 bytes.
10262 23:53:35.094873
10263 23:53:35.097879 Image fdt-1 has 47258 bytes.
10264 23:53:35.097951
10265 23:53:35.101536 Image kernel-1 has 13063488 bytes.
10266 23:53:35.101615
10267 23:53:35.111732 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 23:53:35.111815
10269 23:53:35.127751 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 23:53:35.127836
10271 23:53:35.134664 Choosing best match conf-1 for compat google,spherion-rev2.
10272 23:53:35.134744
10273 23:53:35.142465 Connected to device vid:did:rid of 1ae0:0028:00
10274 23:53:35.150354
10275 23:53:35.153945 tpm_get_response: command 0x17b, return code 0x0
10276 23:53:35.154025
10277 23:53:35.157050 ec_init: CrosEC protocol v3 supported (256, 248)
10278 23:53:35.160880
10279 23:53:35.164434 tpm_cleanup: add release locality here.
10280 23:53:35.164516
10281 23:53:35.164615 Shutting down all USB controllers.
10282 23:53:35.167917
10283 23:53:35.167996 Removing current net device
10284 23:53:35.168059
10285 23:53:35.174549 Exiting depthcharge with code 4 at timestamp: 72262956
10286 23:53:35.174629
10287 23:53:35.177670 LZMA decompressing kernel-1 to 0x821a6718
10288 23:53:35.177750
10289 23:53:35.180617 LZMA decompressing kernel-1 to 0x40000000
10290 23:53:36.791840
10291 23:53:36.791975 jumping to kernel
10292 23:53:36.792436 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10293 23:53:36.792549 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10294 23:53:36.792648 Setting prompt string to ['Linux version [0-9]']
10295 23:53:36.792726 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 23:53:36.792800 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 23:53:36.874364
10298 23:53:36.877627 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 23:53:36.881079 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10300 23:53:36.881199 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 23:53:36.881301 Setting prompt string to []
10302 23:53:36.881434 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10303 23:53:36.881535 Using line separator: #'\n'#
10304 23:53:36.881630 No login prompt set.
10305 23:53:36.881742 Parsing kernel messages
10306 23:53:36.881845 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10307 23:53:36.882090 [login-action] Waiting for messages, (timeout 00:03:41)
10308 23:53:36.882250 Waiting using forced prompt support (timeout 00:01:50)
10309 23:53:36.900895 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10310 23:53:36.904719 [ 0.000000] random: crng init done
10311 23:53:36.910871 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 23:53:36.914457 [ 0.000000] efi: UEFI not found.
10313 23:53:36.920609 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 23:53:36.930737 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 23:53:36.937231 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 23:53:36.947098 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 23:53:36.954055 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 23:53:36.960255 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 23:53:36.967022 [ 0.000000] NUMA: No NUMA configuration found
10320 23:53:36.973468 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 23:53:36.980224 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10322 23:53:36.980311 [ 0.000000] Zone ranges:
10323 23:53:36.986509 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 23:53:36.990011 [ 0.000000] DMA32 empty
10325 23:53:36.996483 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 23:53:37.000017 [ 0.000000] Movable zone start for each node
10327 23:53:37.003281 [ 0.000000] Early memory node ranges
10328 23:53:37.010037 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 23:53:37.016262 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 23:53:37.023133 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 23:53:37.029778 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 23:53:37.036205 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 23:53:37.042882 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 23:53:37.099183 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 23:53:37.105378 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 23:53:37.112269 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 23:53:37.115675 [ 0.000000] psci: probing for conduit method from DT.
10338 23:53:37.121852 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 23:53:37.125007 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 23:53:37.131736 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 23:53:37.135379 [ 0.000000] psci: SMC Calling Convention v1.2
10342 23:53:37.141749 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10343 23:53:37.144939 [ 0.000000] Detected VIPT I-cache on CPU0
10344 23:53:37.151848 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 23:53:37.158635 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 23:53:37.164619 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 23:53:37.171743 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 23:53:37.181629 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 23:53:37.188541 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 23:53:37.191566 [ 0.000000] alternatives: applying boot alternatives
10351 23:53:37.198501 [ 0.000000] Fallback order for Node 0: 0
10352 23:53:37.204619 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 23:53:37.207802 [ 0.000000] Policy zone: Normal
10354 23:53:37.231557 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10355 23:53:37.241458 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 23:53:37.252067 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 23:53:37.262269 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 23:53:37.268418 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 23:53:37.271931 <6>[ 0.000000] software IO TLB: area num 8.
10360 23:53:37.328439 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 23:53:37.477697 <6>[ 0.000000] Memory: 7945900K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406868K reserved, 32768K cma-reserved)
10362 23:53:37.484197 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 23:53:37.490510 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 23:53:37.493593 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 23:53:37.500437 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 23:53:37.507219 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 23:53:37.510085 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 23:53:37.520281 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 23:53:37.527175 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 23:53:37.533320 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 23:53:37.540180 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 23:53:37.543314 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 23:53:37.546432 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 23:53:37.553656 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 23:53:37.556719 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 23:53:37.563393 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 23:53:37.576597 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 23:53:37.589769 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 23:53:37.596164 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 23:53:37.603901 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 23:53:37.617207 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 23:53:37.624121 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 23:53:37.630229 <6>[ 0.009233] Console: colour dummy device 80x25
10384 23:53:37.640437 <6>[ 0.013962] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 23:53:37.646764 <6>[ 0.024404] pid_max: default: 32768 minimum: 301
10386 23:53:37.650244 <6>[ 0.029306] LSM: Security Framework initializing
10387 23:53:37.657243 <6>[ 0.034240] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 23:53:37.667061 <6>[ 0.042103] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 23:53:37.673426 <6>[ 0.051525] cblist_init_generic: Setting adjustable number of callback queues.
10390 23:53:37.680113 <6>[ 0.058969] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 23:53:37.690122 <6>[ 0.065309] cblist_init_generic: Setting adjustable number of callback queues.
10392 23:53:37.696473 <6>[ 0.072735] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 23:53:37.699822 <6>[ 0.079137] rcu: Hierarchical SRCU implementation.
10394 23:53:37.706766 <6>[ 0.084153] rcu: Max phase no-delay instances is 1000.
10395 23:53:37.713241 <6>[ 0.091189] EFI services will not be available.
10396 23:53:37.716689 <6>[ 0.096146] smp: Bringing up secondary CPUs ...
10397 23:53:37.724581 <6>[ 0.101196] Detected VIPT I-cache on CPU1
10398 23:53:37.731404 <6>[ 0.101269] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10399 23:53:37.738029 <6>[ 0.101298] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10400 23:53:37.741299 <6>[ 0.101634] Detected VIPT I-cache on CPU2
10401 23:53:37.748346 <6>[ 0.101686] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10402 23:53:37.754857 <6>[ 0.101704] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10403 23:53:37.761072 <6>[ 0.101962] Detected VIPT I-cache on CPU3
10404 23:53:37.767805 <6>[ 0.102007] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10405 23:53:37.774826 <6>[ 0.102022] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10406 23:53:37.777750 <6>[ 0.102326] CPU features: detected: Spectre-v4
10407 23:53:37.784714 <6>[ 0.102332] CPU features: detected: Spectre-BHB
10408 23:53:37.787816 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10409 23:53:37.794649 <6>[ 0.102396] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10410 23:53:37.800836 <6>[ 0.102412] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10411 23:53:37.807436 <6>[ 0.102704] Detected PIPT I-cache on CPU5
10412 23:53:37.814367 <6>[ 0.102765] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10413 23:53:37.820695 <6>[ 0.102781] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10414 23:53:37.824145 <6>[ 0.103061] Detected PIPT I-cache on CPU6
10415 23:53:37.830939 <6>[ 0.103125] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10416 23:53:37.837299 <6>[ 0.103142] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10417 23:53:37.843760 <6>[ 0.103436] Detected PIPT I-cache on CPU7
10418 23:53:37.851012 <6>[ 0.103500] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10419 23:53:37.857483 <6>[ 0.103515] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10420 23:53:37.860499 <6>[ 0.103563] smp: Brought up 1 node, 8 CPUs
10421 23:53:37.867000 <6>[ 0.244890] SMP: Total of 8 processors activated.
10422 23:53:37.870513 <6>[ 0.249841] CPU features: detected: 32-bit EL0 Support
10423 23:53:37.880433 <6>[ 0.255204] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10424 23:53:37.886730 <6>[ 0.264059] CPU features: detected: Common not Private translations
10425 23:53:37.893910 <6>[ 0.270576] CPU features: detected: CRC32 instructions
10426 23:53:37.896944 <6>[ 0.275927] CPU features: detected: RCpc load-acquire (LDAPR)
10427 23:53:37.903618 <6>[ 0.281887] CPU features: detected: LSE atomic instructions
10428 23:53:37.909934 <6>[ 0.287704] CPU features: detected: Privileged Access Never
10429 23:53:37.916891 <6>[ 0.293520] CPU features: detected: RAS Extension Support
10430 23:53:37.923459 <6>[ 0.299128] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10431 23:53:37.926401 <6>[ 0.306350] CPU: All CPU(s) started at EL2
10432 23:53:37.933322 <6>[ 0.310667] alternatives: applying system-wide alternatives
10433 23:53:37.942624 <6>[ 0.321520] devtmpfs: initialized
10434 23:53:37.954966 <6>[ 0.330466] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10435 23:53:37.965007 <6>[ 0.340425] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10436 23:53:37.971618 <6>[ 0.348440] pinctrl core: initialized pinctrl subsystem
10437 23:53:37.975069 <6>[ 0.355091] DMI not present or invalid.
10438 23:53:37.981621 <6>[ 0.359504] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10439 23:53:37.991031 <6>[ 0.366326] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10440 23:53:37.997976 <6>[ 0.373914] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10441 23:53:38.007893 <6>[ 0.382129] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10442 23:53:38.011193 <6>[ 0.390373] audit: initializing netlink subsys (disabled)
10443 23:53:38.021155 <5>[ 0.396064] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10444 23:53:38.027373 <6>[ 0.396762] thermal_sys: Registered thermal governor 'step_wise'
10445 23:53:38.034125 <6>[ 0.404031] thermal_sys: Registered thermal governor 'power_allocator'
10446 23:53:38.037773 <6>[ 0.410286] cpuidle: using governor menu
10447 23:53:38.044269 <6>[ 0.421246] NET: Registered PF_QIPCRTR protocol family
10448 23:53:38.051016 <6>[ 0.426732] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10449 23:53:38.054275 <6>[ 0.433833] ASID allocator initialised with 32768 entries
10450 23:53:38.061759 <6>[ 0.440406] Serial: AMBA PL011 UART driver
10451 23:53:38.070342 <4>[ 0.449150] Trying to register duplicate clock ID: 134
10452 23:53:38.129869 <6>[ 0.511937] KASLR enabled
10453 23:53:38.144490 <6>[ 0.519818] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 23:53:38.150614 <6>[ 0.526831] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 23:53:38.157494 <6>[ 0.533320] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 23:53:38.163596 <6>[ 0.540326] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 23:53:38.170560 <6>[ 0.546815] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 23:53:38.176886 <6>[ 0.553818] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 23:53:38.183458 <6>[ 0.560304] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 23:53:38.190092 <6>[ 0.567308] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 23:53:38.193239 <6>[ 0.574831] ACPI: Interpreter disabled.
10462 23:53:38.202502 <6>[ 0.581262] iommu: Default domain type: Translated
10463 23:53:38.209047 <6>[ 0.586371] iommu: DMA domain TLB invalidation policy: strict mode
10464 23:53:38.212125 <5>[ 0.593032] SCSI subsystem initialized
10465 23:53:38.219101 <6>[ 0.597197] usbcore: registered new interface driver usbfs
10466 23:53:38.225330 <6>[ 0.602932] usbcore: registered new interface driver hub
10467 23:53:38.229065 <6>[ 0.608483] usbcore: registered new device driver usb
10468 23:53:38.235935 <6>[ 0.614585] pps_core: LinuxPPS API ver. 1 registered
10469 23:53:38.245633 <6>[ 0.619778] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10470 23:53:38.248810 <6>[ 0.629123] PTP clock support registered
10471 23:53:38.252549 <6>[ 0.633363] EDAC MC: Ver: 3.0.0
10472 23:53:38.259558 <6>[ 0.638516] FPGA manager framework
10473 23:53:38.266119 <6>[ 0.642203] Advanced Linux Sound Architecture Driver Initialized.
10474 23:53:38.269604 <6>[ 0.648987] vgaarb: loaded
10475 23:53:38.276315 <6>[ 0.652154] clocksource: Switched to clocksource arch_sys_counter
10476 23:53:38.279556 <5>[ 0.658598] VFS: Disk quotas dquot_6.6.0
10477 23:53:38.285765 <6>[ 0.662784] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10478 23:53:38.289451 <6>[ 0.669973] pnp: PnP ACPI: disabled
10479 23:53:38.297899 <6>[ 0.676631] NET: Registered PF_INET protocol family
10480 23:53:38.307338 <6>[ 0.682219] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10481 23:53:38.318840 <6>[ 0.694550] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10482 23:53:38.328902 <6>[ 0.703364] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10483 23:53:38.335174 <6>[ 0.711333] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10484 23:53:38.345292 <6>[ 0.720031] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10485 23:53:38.352397 <6>[ 0.729781] TCP: Hash tables configured (established 65536 bind 65536)
10486 23:53:38.358610 <6>[ 0.736648] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 23:53:38.368551 <6>[ 0.743847] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 23:53:38.374956 <6>[ 0.751548] NET: Registered PF_UNIX/PF_LOCAL protocol family
10489 23:53:38.378277 <6>[ 0.757696] RPC: Registered named UNIX socket transport module.
10490 23:53:38.385351 <6>[ 0.763851] RPC: Registered udp transport module.
10491 23:53:38.388262 <6>[ 0.768784] RPC: Registered tcp transport module.
10492 23:53:38.398211 <6>[ 0.773714] RPC: Registered tcp NFSv4.1 backchannel transport module.
10493 23:53:38.401788 <6>[ 0.780378] PCI: CLS 0 bytes, default 64
10494 23:53:38.404711 <6>[ 0.784610] Unpacking initramfs...
10495 23:53:38.414189 <6>[ 0.788674] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10496 23:53:38.421092 <6>[ 0.797296] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10497 23:53:38.427853 <6>[ 0.806115] kvm [1]: IPA Size Limit: 40 bits
10498 23:53:38.430743 <6>[ 0.810640] kvm [1]: GICv3: no GICV resource entry
10499 23:53:38.437618 <6>[ 0.815662] kvm [1]: disabling GICv2 emulation
10500 23:53:38.444076 <6>[ 0.820350] kvm [1]: GIC system register CPU interface enabled
10501 23:53:38.447379 <6>[ 0.826501] kvm [1]: vgic interrupt IRQ18
10502 23:53:38.450898 <6>[ 0.830851] kvm [1]: VHE mode initialized successfully
10503 23:53:38.458402 <5>[ 0.837274] Initialise system trusted keyrings
10504 23:53:38.465243 <6>[ 0.842059] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10505 23:53:38.473235 <6>[ 0.852027] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10506 23:53:38.479374 <5>[ 0.858419] NFS: Registering the id_resolver key type
10507 23:53:38.483192 <5>[ 0.863722] Key type id_resolver registered
10508 23:53:38.489403 <5>[ 0.868138] Key type id_legacy registered
10509 23:53:38.496231 <6>[ 0.872418] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10510 23:53:38.502821 <6>[ 0.879342] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10511 23:53:38.509286 <6>[ 0.887044] 9p: Installing v9fs 9p2000 file system support
10512 23:53:38.546259 <5>[ 0.925302] Key type asymmetric registered
10513 23:53:38.549858 <5>[ 0.929635] Asymmetric key parser 'x509' registered
10514 23:53:38.559905 <6>[ 0.934782] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10515 23:53:38.562684 <6>[ 0.942399] io scheduler mq-deadline registered
10516 23:53:38.566315 <6>[ 0.947159] io scheduler kyber registered
10517 23:53:38.585453 <6>[ 0.964178] EINJ: ACPI disabled.
10518 23:53:38.618342 <4>[ 0.990497] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 23:53:38.628129 <4>[ 1.001148] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 23:53:38.643306 <6>[ 1.022251] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10521 23:53:38.651222 <6>[ 1.030314] printk: console [ttyS0] disabled
10522 23:53:38.679410 <6>[ 1.054956] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10523 23:53:38.686259 <6>[ 1.064428] printk: console [ttyS0] enabled
10524 23:53:38.689336 <6>[ 1.064428] printk: console [ttyS0] enabled
10525 23:53:38.695663 <6>[ 1.073325] printk: bootconsole [mtk8250] disabled
10526 23:53:38.699397 <6>[ 1.073325] printk: bootconsole [mtk8250] disabled
10527 23:53:38.705640 <6>[ 1.084512] SuperH (H)SCI(F) driver initialized
10528 23:53:38.708826 <6>[ 1.089778] msm_serial: driver initialized
10529 23:53:38.723180 <6>[ 1.098709] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10530 23:53:38.733180 <6>[ 1.107255] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10531 23:53:38.739696 <6>[ 1.115796] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10532 23:53:38.749511 <6>[ 1.124423] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10533 23:53:38.759661 <6>[ 1.133129] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10534 23:53:38.766500 <6>[ 1.141841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10535 23:53:38.776129 <6>[ 1.150381] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10536 23:53:38.782654 <6>[ 1.159188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10537 23:53:38.792541 <6>[ 1.167729] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10538 23:53:38.803996 <6>[ 1.183268] loop: module loaded
10539 23:53:38.810653 <6>[ 1.189271] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10540 23:53:38.833637 <4>[ 1.212437] mtk-pmic-keys: Failed to locate of_node [id: -1]
10541 23:53:38.840338 <6>[ 1.219225] megasas: 07.719.03.00-rc1
10542 23:53:38.850159 <6>[ 1.228986] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10543 23:53:38.856567 <6>[ 1.235538] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10544 23:53:38.873264 <6>[ 1.252131] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10545 23:53:38.928896 <6>[ 1.301428] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10546 23:53:39.233242 <6>[ 1.611972] Freeing initrd memory: 18284K
10547 23:53:39.245152 <6>[ 1.623597] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10548 23:53:39.256149 <6>[ 1.634567] tun: Universal TUN/TAP device driver, 1.6
10549 23:53:39.259313 <6>[ 1.640642] thunder_xcv, ver 1.0
10550 23:53:39.262411 <6>[ 1.644136] thunder_bgx, ver 1.0
10551 23:53:39.265807 <6>[ 1.647633] nicpf, ver 1.0
10552 23:53:39.276535 <6>[ 1.651648] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10553 23:53:39.280044 <6>[ 1.659123] hns3: Copyright (c) 2017 Huawei Corporation.
10554 23:53:39.283362 <6>[ 1.664713] hclge is initializing
10555 23:53:39.289991 <6>[ 1.668288] e1000: Intel(R) PRO/1000 Network Driver
10556 23:53:39.296451 <6>[ 1.673417] e1000: Copyright (c) 1999-2006 Intel Corporation.
10557 23:53:39.299526 <6>[ 1.679433] e1000e: Intel(R) PRO/1000 Network Driver
10558 23:53:39.306199 <6>[ 1.684649] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10559 23:53:39.312811 <6>[ 1.690836] igb: Intel(R) Gigabit Ethernet Network Driver
10560 23:53:39.319680 <6>[ 1.696485] igb: Copyright (c) 2007-2014 Intel Corporation.
10561 23:53:39.326454 <6>[ 1.702326] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 23:53:39.329597 <6>[ 1.708845] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 23:53:39.336684 <6>[ 1.715305] sky2: driver version 1.30
10564 23:53:39.343600 <6>[ 1.720233] usbcore: registered new device driver r8152-cfgselector
10565 23:53:39.349860 <6>[ 1.726765] usbcore: registered new interface driver r8152
10566 23:53:39.353025 <6>[ 1.732582] VFIO - User Level meta-driver version: 0.3
10567 23:53:39.362183 <6>[ 1.740805] usbcore: registered new interface driver usb-storage
10568 23:53:39.368431 <6>[ 1.747250] usbcore: registered new device driver onboard-usb-hub
10569 23:53:39.377817 <6>[ 1.756365] mt6397-rtc mt6359-rtc: registered as rtc0
10570 23:53:39.387314 <6>[ 1.761823] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:53:39 UTC (1717026819)
10571 23:53:39.391077 <6>[ 1.771392] i2c_dev: i2c /dev entries driver
10572 23:53:39.408145 <6>[ 1.783274] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10573 23:53:39.414551 <4>[ 1.791996] cpu cpu0: supply cpu not found, using dummy regulator
10574 23:53:39.420938 <4>[ 1.798422] cpu cpu1: supply cpu not found, using dummy regulator
10575 23:53:39.427899 <4>[ 1.804835] cpu cpu2: supply cpu not found, using dummy regulator
10576 23:53:39.434800 <4>[ 1.811251] cpu cpu3: supply cpu not found, using dummy regulator
10577 23:53:39.441111 <4>[ 1.817647] cpu cpu4: supply cpu not found, using dummy regulator
10578 23:53:39.448061 <4>[ 1.824043] cpu cpu5: supply cpu not found, using dummy regulator
10579 23:53:39.454361 <4>[ 1.830442] cpu cpu6: supply cpu not found, using dummy regulator
10580 23:53:39.458162 <4>[ 1.836841] cpu cpu7: supply cpu not found, using dummy regulator
10581 23:53:39.479773 <6>[ 1.858520] cpu cpu0: EM: created perf domain
10582 23:53:39.483247 <6>[ 1.863461] cpu cpu4: EM: created perf domain
10583 23:53:39.490593 <6>[ 1.869094] sdhci: Secure Digital Host Controller Interface driver
10584 23:53:39.496876 <6>[ 1.875527] sdhci: Copyright(c) Pierre Ossman
10585 23:53:39.503557 <6>[ 1.880492] Synopsys Designware Multimedia Card Interface Driver
10586 23:53:39.510014 <6>[ 1.887145] sdhci-pltfm: SDHCI platform and OF driver helper
10587 23:53:39.513906 <6>[ 1.887178] mmc0: CQHCI version 5.10
10588 23:53:39.520648 <6>[ 1.897145] ledtrig-cpu: registered to indicate activity on CPUs
10589 23:53:39.526722 <6>[ 1.904235] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10590 23:53:39.533223 <6>[ 1.911291] usbcore: registered new interface driver usbhid
10591 23:53:39.536618 <6>[ 1.917113] usbhid: USB HID core driver
10592 23:53:39.543588 <6>[ 1.921315] spi_master spi0: will run message pump with realtime priority
10593 23:53:39.587506 <6>[ 1.959817] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10594 23:53:39.607064 <6>[ 1.975713] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10595 23:53:39.610505 <6>[ 1.990295] mmc0: Command Queue Engine enabled
10596 23:53:39.617309 <6>[ 1.990304] cros-ec-spi spi0.0: Chrome EC device registered
10597 23:53:39.623791 <6>[ 1.990322] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10598 23:53:39.630708 <6>[ 2.007954] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 23:53:39.636987 <6>[ 2.008913] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10600 23:53:39.644066 <6>[ 2.018123] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10601 23:53:39.650244 <6>[ 2.023055] NET: Registered PF_PACKET protocol family
10602 23:53:39.654085 <6>[ 2.029569] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10603 23:53:39.660537 <6>[ 2.033251] 9pnet: Installing 9P2000 support
10604 23:53:39.663860 <6>[ 2.039092] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10605 23:53:39.670425 <5>[ 2.042956] Key type dns_resolver registered
10606 23:53:39.676799 <6>[ 2.048813] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 23:53:39.680361 <6>[ 2.053108] registered taskstats version 1
10608 23:53:39.683690 <5>[ 2.063556] Loading compiled-in X.509 certificates
10609 23:53:39.713526 <4>[ 2.085162] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 23:53:39.723177 <4>[ 2.095865] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 23:53:39.736314 <6>[ 2.115302] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10612 23:53:39.743472 <6>[ 2.122252] xhci-mtk 11200000.usb: xHCI Host Controller
10613 23:53:39.749940 <6>[ 2.127780] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10614 23:53:39.760311 <6>[ 2.135637] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10615 23:53:39.766953 <6>[ 2.145072] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10616 23:53:39.774060 <6>[ 2.151155] xhci-mtk 11200000.usb: xHCI Host Controller
10617 23:53:39.780123 <6>[ 2.156643] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10618 23:53:39.786986 <6>[ 2.164294] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10619 23:53:39.793794 <6>[ 2.171934] hub 1-0:1.0: USB hub found
10620 23:53:39.797089 <6>[ 2.175946] hub 1-0:1.0: 1 port detected
10621 23:53:39.803680 <6>[ 2.180239] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10622 23:53:39.810330 <6>[ 2.188764] hub 2-0:1.0: USB hub found
10623 23:53:39.813244 <6>[ 2.192771] hub 2-0:1.0: 1 port detected
10624 23:53:39.821242 <6>[ 2.199752] mtk-msdc 11f70000.mmc: Got CD GPIO
10625 23:53:39.836705 <6>[ 2.212283] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10626 23:53:39.843204 <6>[ 2.220301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10627 23:53:39.853190 <4>[ 2.228263] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10628 23:53:39.863226 <6>[ 2.237803] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10629 23:53:39.870216 <6>[ 2.245880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10630 23:53:39.876716 <6>[ 2.253894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10631 23:53:39.886160 <6>[ 2.261810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10632 23:53:39.893265 <6>[ 2.269627] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10633 23:53:39.902719 <6>[ 2.277443] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10634 23:53:39.912877 <6>[ 2.287867] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10635 23:53:39.919160 <6>[ 2.296226] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10636 23:53:39.929220 <6>[ 2.304575] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10637 23:53:39.935781 <6>[ 2.312914] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10638 23:53:39.945991 <6>[ 2.321252] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10639 23:53:39.953057 <6>[ 2.329589] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10640 23:53:39.963051 <6>[ 2.337927] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10641 23:53:39.968975 <6>[ 2.346264] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10642 23:53:39.979177 <6>[ 2.354602] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10643 23:53:39.985795 <6>[ 2.362939] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10644 23:53:39.995786 <6>[ 2.371278] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10645 23:53:40.005667 <6>[ 2.379616] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10646 23:53:40.012413 <6>[ 2.387954] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10647 23:53:40.019269 <6>[ 2.396292] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10648 23:53:40.029494 <6>[ 2.404630] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10649 23:53:40.035534 <6>[ 2.413371] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10650 23:53:40.041982 <6>[ 2.420550] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10651 23:53:40.048762 <6>[ 2.427316] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10652 23:53:40.055134 <6>[ 2.434080] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10653 23:53:40.064965 <6>[ 2.441009] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10654 23:53:40.072035 <6>[ 2.447876] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10655 23:53:40.081813 <6>[ 2.457016] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10656 23:53:40.091849 <6>[ 2.466136] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10657 23:53:40.101692 <6>[ 2.475430] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10658 23:53:40.111752 <6>[ 2.484898] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10659 23:53:40.117964 <6>[ 2.494366] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10660 23:53:40.127933 <6>[ 2.503486] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10661 23:53:40.137842 <6>[ 2.512953] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10662 23:53:40.147904 <6>[ 2.522071] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10663 23:53:40.157942 <6>[ 2.531367] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10664 23:53:40.167666 <6>[ 2.541527] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10665 23:53:40.177787 <6>[ 2.553433] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10666 23:53:40.184155 <6>[ 2.563148] Trying to probe devices needed for running init ...
10667 23:53:40.224550 <6>[ 2.600430] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10668 23:53:40.379745 <6>[ 2.758517] hub 1-1:1.0: USB hub found
10669 23:53:40.382927 <6>[ 2.763023] hub 1-1:1.0: 4 ports detected
10670 23:53:40.392483 <6>[ 2.771789] hub 1-1:1.0: USB hub found
10671 23:53:40.395769 <6>[ 2.776291] hub 1-1:1.0: 4 ports detected
10672 23:53:40.505134 <6>[ 2.880460] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10673 23:53:40.530542 <6>[ 2.909485] hub 2-1:1.0: USB hub found
10674 23:53:40.533841 <6>[ 2.913924] hub 2-1:1.0: 3 ports detected
10675 23:53:40.542896 <6>[ 2.921249] hub 2-1:1.0: USB hub found
10676 23:53:40.545949 <6>[ 2.925623] hub 2-1:1.0: 3 ports detected
10677 23:53:40.720328 <6>[ 3.096281] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10678 23:53:40.853281 <6>[ 3.232329] hub 1-1.4:1.0: USB hub found
10679 23:53:40.857040 <6>[ 3.236992] hub 1-1.4:1.0: 2 ports detected
10680 23:53:40.866507 <6>[ 3.245453] hub 1-1.4:1.0: USB hub found
10681 23:53:40.869820 <6>[ 3.250076] hub 1-1.4:1.0: 2 ports detected
10682 23:53:40.936875 <6>[ 3.312677] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10683 23:53:41.045264 <6>[ 3.421093] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10684 23:53:41.082270 <4>[ 3.458242] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10685 23:53:41.092526 <4>[ 3.467380] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10686 23:53:41.130705 <6>[ 3.510049] r8152 2-1.3:1.0 eth0: v1.12.13
10687 23:53:41.168279 <6>[ 3.544409] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10688 23:53:41.356539 <6>[ 3.732314] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10689 23:53:42.754961 <6>[ 5.134371] r8152 2-1.3:1.0 eth0: carrier on
10690 23:53:43.265220 <5>[ 5.164279] Sending DHCP requests .
10691 23:53:43.271560 <3>[ 5.644406] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[4272d07f]
10692 23:53:43.305172 <3>[ 5.681635] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[4272d07f]
10693 23:53:44.087818 <3>[ 6.464029] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[59c7c7a5]
10694 23:53:44.094376 <3>[ 6.470902] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[59c7c7a5]
10695 23:53:45.165229 <4>[ 7.532484] ., OK
10696 23:53:45.175109 <6>[ 7.550530] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10697 23:53:45.178277 <6>[ 7.558825] IP-Config: Complete:
10698 23:53:45.188596 <6>[ 7.562317] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10699 23:53:45.198736 <6>[ 7.573028] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10700 23:53:45.204966 <6>[ 7.581644] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10701 23:53:45.208253 <6>[ 7.581653] nameserver0=192.168.201.1
10702 23:53:45.212043 <6>[ 7.593828] clk: Disabling unused clocks
10703 23:53:45.216705 <6>[ 7.599345] ALSA device list:
10704 23:53:45.223228 <6>[ 7.602624] No soundcards found.
10705 23:53:45.230456 <6>[ 7.610152] Freeing unused kernel memory: 8512K
10706 23:53:45.233690 <6>[ 7.615097] Run /init as init process
10707 23:53:45.244158 Loading, please wait...
10708 23:53:45.273180 Starting systemd-udevd version 252.22-1~deb12u1
10709 23:53:45.551208 <6>[ 7.927402] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10710 23:53:45.561315 <6>[ 7.936699] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10711 23:53:45.567560 <6>[ 7.938307] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10712 23:53:45.577577 <6>[ 7.945703] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10713 23:53:45.584977 <6>[ 7.964737] remoteproc remoteproc0: scp is available
10714 23:53:45.591521 <6>[ 7.970166] remoteproc remoteproc0: powering up scp
10715 23:53:45.599043 <6>[ 7.975319] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10716 23:53:45.605004 <6>[ 7.983795] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10717 23:53:45.618011 <6>[ 7.997302] mc: Linux media interface: v0.10
10718 23:53:45.624311 <3>[ 7.999800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 23:53:45.634352 <4>[ 8.002326] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10720 23:53:45.640541 <3>[ 8.010080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 23:53:45.650445 <3>[ 8.010117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:53:45.657632 <3>[ 8.018591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 23:53:45.663682 <6>[ 8.021037] videodev: Linux video capture interface: v2.00
10724 23:53:45.670351 <6>[ 8.021305] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10725 23:53:45.677009 <4>[ 8.026637] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10726 23:53:45.687240 <3>[ 8.034325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 23:53:45.694242 <3>[ 8.034341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 23:53:45.704675 <3>[ 8.034357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 23:53:45.710903 <3>[ 8.034365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 23:53:45.720447 <3>[ 8.034748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 23:53:45.727576 <4>[ 8.053504] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10732 23:53:45.731362 <4>[ 8.053504] Fallback method does not support PEC.
10733 23:53:45.741156 <3>[ 8.056373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 23:53:45.751047 <3>[ 8.080491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10735 23:53:45.757564 <6>[ 8.085555] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10736 23:53:45.760873 <6>[ 8.085560] pci_bus 0000:00: root bus resource [bus 00-ff]
10737 23:53:45.771105 <6>[ 8.085564] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10738 23:53:45.780927 <6>[ 8.085567] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10739 23:53:45.784125 <6>[ 8.085593] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10740 23:53:45.793963 <6>[ 8.085606] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10741 23:53:45.797675 <6>[ 8.085669] pci 0000:00:00.0: supports D1 D2
10742 23:53:45.804082 <6>[ 8.085670] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 23:53:45.814223 <6>[ 8.086582] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10744 23:53:45.820553 <6>[ 8.086673] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10745 23:53:45.827249 <6>[ 8.086699] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10746 23:53:45.833983 <6>[ 8.086715] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10747 23:53:45.840103 <6>[ 8.086729] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10748 23:53:45.847124 <6>[ 8.086835] pci 0000:01:00.0: supports D1 D2
10749 23:53:45.853712 <6>[ 8.086836] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10750 23:53:45.860597 <3>[ 8.087672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 23:53:45.870505 <3>[ 8.087677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 23:53:45.876935 <3>[ 8.087732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 23:53:45.883870 <6>[ 8.096185] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10754 23:53:45.893853 <3>[ 8.103842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 23:53:45.900412 <3>[ 8.103846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 23:53:45.910439 <6>[ 8.115892] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10757 23:53:45.916809 <6>[ 8.115900] remoteproc remoteproc0: remote processor scp is now up
10758 23:53:45.923324 <6>[ 8.115901] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10759 23:53:45.929910 <6>[ 8.117505] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10760 23:53:45.940275 <3>[ 8.125557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 23:53:45.946633 <6>[ 8.134326] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10762 23:53:45.956384 <3>[ 8.134872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10763 23:53:45.963208 <6>[ 8.135373] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10764 23:53:45.973095 <6>[ 8.136568] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10765 23:53:45.982523 <6>[ 8.137427] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10766 23:53:45.992739 <6>[ 8.137860] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10767 23:53:45.999499 <3>[ 8.141189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 23:53:46.006147 <6>[ 8.146926] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10769 23:53:46.016163 <3>[ 8.154052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 23:53:46.025705 <6>[ 8.160963] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10771 23:53:46.032712 <6>[ 8.164805] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10772 23:53:46.036060 <6>[ 8.178330] Bluetooth: Core ver 2.22
10773 23:53:46.045806 <6>[ 8.182555] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10774 23:53:46.048976 <6>[ 8.189385] NET: Registered PF_BLUETOOTH protocol family
10775 23:53:46.056123 <6>[ 8.197526] pci 0000:00:00.0: PCI bridge to [bus 01]
10776 23:53:46.062271 <6>[ 8.203764] Bluetooth: HCI device and connection manager initialized
10777 23:53:46.069010 <6>[ 8.204844] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10778 23:53:46.082235 <6>[ 8.206034] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10779 23:53:46.085562 <6>[ 8.206126] usbcore: registered new interface driver uvcvideo
10780 23:53:46.095236 <6>[ 8.211239] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10781 23:53:46.102140 <6>[ 8.211478] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10782 23:53:46.105228 <6>[ 8.218864] Bluetooth: HCI socket layer initialized
10783 23:53:46.112257 <6>[ 8.226842] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10784 23:53:46.118337 <6>[ 8.230808] Bluetooth: L2CAP socket layer initialized
10785 23:53:46.121956 <6>[ 8.230836] Bluetooth: SCO socket layer initialized
10786 23:53:46.128282 <6>[ 8.231317] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10787 23:53:46.135054 <6>[ 8.238238] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10788 23:53:46.142108 <6>[ 8.300349] usbcore: registered new interface driver btusb
10789 23:53:46.151406 <4>[ 8.301332] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10790 23:53:46.158050 <3>[ 8.301347] Bluetooth: hci0: Failed to load firmware file (-2)
10791 23:53:46.164581 <3>[ 8.301354] Bluetooth: hci0: Failed to set up firmware (-2)
10792 23:53:46.174696 <4>[ 8.301361] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10793 23:53:46.181105 <5>[ 8.324821] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10794 23:53:46.204274 <5>[ 8.580182] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10795 23:53:46.210816 <5>[ 8.587247] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10796 23:53:46.221035 <4>[ 8.595678] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10797 23:53:46.223929 <6>[ 8.604556] cfg80211: failed to load regulatory.db
10798 23:53:46.264616 <6>[ 8.641073] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10799 23:53:46.271181 <6>[ 8.648575] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10800 23:53:46.292698 <6>[ 8.672480] mt7921e 0000:01:00.0: ASIC revision: 79610010
10801 23:53:46.396455 <6>[ 8.772722] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10802 23:53:46.399854 <6>[ 8.772722]
10803 23:53:46.402753 Begin: Loading essential drivers ... done.
10804 23:53:46.406243 Begin: Running /scripts/init-premount ... done.
10805 23:53:46.412694 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10806 23:53:46.422611 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10807 23:53:46.425835 Device /sys/class/net/eth0 found
10808 23:53:46.425913 done.
10809 23:53:46.432346 Begin: Waiting up to 180 secs for any network device to become available ... done.
10810 23:53:46.472550 IP-Config: eth0 hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10811 23:53:46.479133 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10812 23:53:46.486270 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10813 23:53:46.492314 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10814 23:53:46.499248 host : mt8192-asurada-spherion-r0-cbg-8
10815 23:53:46.505695 domain : lava-rack
10816 23:53:46.508793 rootserver: 192.168.201.1 rootpath:
10817 23:53:46.512235 filename :
10818 23:53:46.664806 <6>[ 9.041578] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10819 23:53:46.673797 done.
10820 23:53:46.681667 Begin: Running /scripts/nfs-bottom ... done.
10821 23:53:46.695472 Begin: Running /scripts/init-bottom ... done.
10822 23:53:48.048694 <6>[ 10.428732] NET: Registered PF_INET6 protocol family
10823 23:53:48.056518 <6>[ 10.436395] Segment Routing with IPv6
10824 23:53:48.059883 <6>[ 10.440341] In-situ OAM (IOAM) with IPv6
10825 23:53:48.226190 <30>[ 10.579759] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10826 23:53:48.232550 <30>[ 10.612888] systemd[1]: Detected architecture arm64.
10827 23:53:48.241501
10828 23:53:48.244706 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10829 23:53:48.244786
10830 23:53:48.273737 <30>[ 10.653635] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10831 23:53:49.414355 <30>[ 11.791465] systemd[1]: Queued start job for default target graphical.target.
10832 23:53:49.445122 <30>[ 11.821709] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10833 23:53:49.451503 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10834 23:53:49.473430 <30>[ 11.850250] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10835 23:53:49.483035 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10836 23:53:49.501543 <30>[ 11.878195] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10837 23:53:49.511134 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10838 23:53:49.530190 <30>[ 11.906651] systemd[1]: Created slice user.slice - User and Session Slice.
10839 23:53:49.536379 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10840 23:53:49.563528 <30>[ 11.936790] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10841 23:53:49.573094 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10842 23:53:49.594806 <30>[ 11.968710] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10843 23:53:49.601923 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10844 23:53:49.629320 <30>[ 11.996658] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10845 23:53:49.639330 <30>[ 12.016507] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10846 23:53:49.646113 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10847 23:53:49.663297 <30>[ 12.040424] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10848 23:53:49.670429 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10849 23:53:49.687698 <30>[ 12.064545] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10850 23:53:49.697501 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10851 23:53:49.712751 <30>[ 12.092981] systemd[1]: Reached target paths.target - Path Units.
10852 23:53:49.722933 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10853 23:53:49.740939 <30>[ 12.117409] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10854 23:53:49.747153 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10855 23:53:49.763995 <30>[ 12.144441] systemd[1]: Reached target slices.target - Slice Units.
10856 23:53:49.774208 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10857 23:53:49.788159 <30>[ 12.168488] systemd[1]: Reached target swap.target - Swaps.
10858 23:53:49.794538 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10859 23:53:49.815685 <30>[ 12.192521] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10860 23:53:49.825686 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10861 23:53:49.844209 <30>[ 12.221396] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10862 23:53:49.854256 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10863 23:53:49.875482 <30>[ 12.252341] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10864 23:53:49.885058 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10865 23:53:49.904832 <30>[ 12.282004] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10866 23:53:49.914832 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10867 23:53:49.932330 <30>[ 12.309201] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10868 23:53:49.938899 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10869 23:53:49.957324 <30>[ 12.333945] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10870 23:53:49.967065 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10871 23:53:49.986513 <30>[ 12.363426] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10872 23:53:49.996594 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10873 23:53:50.012090 <30>[ 12.388934] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10874 23:53:50.021920 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10875 23:53:50.079905 <30>[ 12.456644] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10876 23:53:50.086150 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10877 23:53:50.108307 <30>[ 12.485130] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10878 23:53:50.114708 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10879 23:53:50.140241 <30>[ 12.517438] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10880 23:53:50.146904 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10881 23:53:50.174979 <30>[ 12.545174] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10882 23:53:50.208632 <30>[ 12.585397] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10883 23:53:50.218075 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10884 23:53:50.241159 <30>[ 12.618108] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10885 23:53:50.248022 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10886 23:53:50.271272 <30>[ 12.648552] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10887 23:53:50.278212 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10888 23:53:50.305383 <30>[ 12.682200] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10889 23:53:50.315310 Startin<6>[ 12.691413] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10890 23:53:50.321507 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10891 23:53:50.345418 <30>[ 12.722370] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10892 23:53:50.355033 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10893 23:53:50.392409 <30>[ 12.769364] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10894 23:53:50.398726 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10895 23:53:50.425854 <30>[ 12.802598] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10896 23:53:50.435835 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 12.814424] fuse: init (API version 7.37)
10897 23:53:50.435963 [0m - Load Kernel Module loop...
10898 23:53:50.492118 <30>[ 12.869047] systemd[1]: Starting systemd-journald.service - Journal Service...
10899 23:53:50.498889 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10900 23:53:50.523916 <30>[ 12.900713] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10901 23:53:50.530263 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10902 23:53:50.580055 <30>[ 12.953492] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10903 23:53:50.586669 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10904 23:53:50.608799 <30>[ 12.986064] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10905 23:53:50.619022 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10906 23:53:50.641498 <30>[ 13.018339] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10907 23:53:50.648056 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10908 23:53:50.674490 <30>[ 13.051653] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10909 23:53:50.680907 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10910 23:53:50.696426 <3>[ 13.073498] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 23:53:50.706586 <30>[ 13.083194] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10912 23:53:50.713174 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10913 23:53:50.732190 <30>[ 13.108756] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10914 23:53:50.738757 <3>[ 13.110943] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 23:53:50.748553 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10916 23:53:50.769231 <30>[ 13.146109] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10917 23:53:50.779388 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10918 23:53:50.789478 <3>[ 13.165412] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 23:53:50.799479 <30>[ 13.176095] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10920 23:53:50.808881 <30>[ 13.184452] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10921 23:53:50.815837 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10922 23:53:50.833801 <3>[ 13.210560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 23:53:50.844570 <30>[ 13.221407] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10924 23:53:50.851181 <30>[ 13.229658] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10925 23:53:50.865221 [[0;32m OK [0m] Finished [0<3>[ 13.240719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 23:53:50.871976 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10927 23:53:50.885676 <30>[ 13.265573] systemd[1]: modprobe@drm.service: Deactivated successfully.
10928 23:53:50.896012 <3>[ 13.271136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 23:53:50.902375 <30>[ 13.273416] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10930 23:53:50.912527 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10931 23:53:50.926476 <3>[ 13.303861] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 23:53:50.937324 <30>[ 13.314151] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10933 23:53:50.947166 <30>[ 13.322843] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10934 23:53:50.960827 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Lo<3>[ 13.336563] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 23:53:50.964553 ad Kernel Module efi_pstore.
10936 23:53:50.980855 <30>[ 13.357278] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10937 23:53:50.987461 <30>[ 13.364671] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10938 23:53:50.997425 <3>[ 13.368162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 23:53:51.003665 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10940 23:53:51.024834 <30>[ 13.401355] systemd[1]: modprobe@loop.service: Deactivated successfully.
10941 23:53:51.030934 <3>[ 13.405633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 23:53:51.040872 <30>[ 13.408868] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10943 23:53:51.047570 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10944 23:53:51.068509 <30>[ 13.445244] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10945 23:53:51.082189 [[0;32m OK [0m] Finished [0;1;39msystemd-mo<3>[ 13.457208] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 23:53:51.096571 <4>[ 13.466413] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10947 23:53:51.102968 <3>[ 13.482047] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10948 23:53:51.109417 dules-l…service[0m - Load Kernel Modules.
10949 23:53:51.133864 <30>[ 13.507771] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10950 23:53:51.140773 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10951 23:53:51.159753 <30>[ 13.536930] systemd[1]: Started systemd-journald.service - Journal Service.
10952 23:53:51.166492 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10953 23:53:51.185837 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10954 23:53:51.204770 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10955 23:53:51.226964 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10956 23:53:51.288257 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10957 23:53:51.310800 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10958 23:53:51.332905 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10959 23:53:51.361224 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10960 23:53:51.392093 Starting [0;1;39msystemd-sysctl.se…c<46>[ 13.769624] systemd-journald[307]: Received client request to flush runtime journal.
10961 23:53:51.395437 e[0m - Apply Kernel Variables...
10962 23:53:51.426026 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10963 23:53:51.718678 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10964 23:53:51.736093 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10965 23:53:51.756662 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10966 23:53:52.161956 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10967 23:53:52.524903 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10968 23:53:52.572362 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10969 23:53:52.806198 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10970 23:53:52.914195 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10971 23:53:52.931880 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10972 23:53:52.951502 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10973 23:53:52.996101 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10974 23:53:53.023127 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10975 23:53:53.261399 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10976 23:53:53.321760 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10977 23:53:53.378191 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10978 23:53:53.579549 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10979 23:53:53.608429 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10980 23:53:53.640377 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10981 23:53:53.706450 <6>[ 16.087186] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10982 23:53:53.742451 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10983 23:53:53.796870 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10984 23:53:53.849000 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10985 23:53:53.876215 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10986 23:53:53.912001 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10987 23:53:53.956707 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10988 23:53:53.980484 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10989 23:53:53.999876 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10990 23:53:54.024625 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10991 23:53:54.055380 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10992 23:53:54.072519 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10993 23:53:54.095025 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10994 23:53:54.115601 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10995 23:53:54.131259 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10996 23:53:54.155135 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10997 23:53:54.203079 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10998 23:53:54.219693 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10999 23:53:54.242929 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11000 23:53:54.263138 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11001 23:53:54.279208 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11002 23:53:54.297217 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11003 23:53:54.315086 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11004 23:53:54.331699 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11005 23:53:54.376517 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11006 23:53:54.411651 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11007 23:53:54.503807 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11008 23:53:54.529594 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11009 23:53:54.594552 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11010 23:53:54.646276 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11011 23:53:54.670811 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11012 23:53:54.687424 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11013 23:53:54.707788 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11014 23:53:54.736134 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11015 23:53:54.885606 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11016 23:53:54.908166 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11017 23:53:54.924479 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11018 23:53:54.976217 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11019 23:53:55.018420 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11020 23:53:55.105729
11021 23:53:55.108860 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11022 23:53:55.108983
11023 23:53:55.112130 debian-bookworm-arm64 login: root (automatic login)
11024 23:53:55.112234
11025 23:53:55.354562 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11026 23:53:55.354719
11027 23:53:55.361454 The programs included with the Debian GNU/Linux system are free software;
11028 23:53:55.367887 the exact distribution terms for each program are described in the
11029 23:53:55.370974 individual files in /usr/share/doc/*/copyright.
11030 23:53:55.371088
11031 23:53:55.377606 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11032 23:53:55.381430 permitted by applicable law.
11033 23:53:55.471240 Matched prompt #10: / #
11035 23:53:55.471616 Setting prompt string to ['/ #']
11036 23:53:55.471747 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11038 23:53:55.472075 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11039 23:53:55.472206 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
11040 23:53:55.472307 Setting prompt string to ['/ #']
11041 23:53:55.472406 Forcing a shell prompt, looking for ['/ #']
11043 23:53:55.522671 / #
11044 23:53:55.522841 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11045 23:53:55.522945 Waiting using forced prompt support (timeout 00:02:30)
11046 23:53:55.528098
11047 23:53:55.528402 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11048 23:53:55.528533 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
11050 23:53:55.628910 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy'
11051 23:53:55.634025 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14084347/extract-nfsrootfs-soh7uwmy'
11053 23:53:55.734566 / # export NFS_SERVER_IP='192.168.201.1'
11054 23:53:55.739282 export NFS_SERVER_IP='192.168.201.1'
11055 23:53:55.739596 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11056 23:53:55.739727 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11057 23:53:55.739848 end: 2 depthcharge-action (duration 00:01:38) [common]
11058 23:53:55.739982 start: 3 lava-test-retry (timeout 00:30:00) [common]
11059 23:53:55.740103 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11060 23:53:55.740219 Using namespace: common
11062 23:53:55.840586 / # #
11063 23:53:55.840769 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11064 23:53:55.845531 #
11065 23:53:55.845833 Using /lava-14084347
11067 23:53:55.946175 / # export SHELL=/bin/sh
11068 23:53:55.951718 export SHELL=/bin/sh
11070 23:53:56.052257 / # . /lava-14084347/environment
11071 23:53:56.057275 . /lava-14084347/environment
11073 23:53:56.163518 / # /lava-14084347/bin/lava-test-runner /lava-14084347/0
11074 23:53:56.163685 Test shell timeout: 10s (minimum of the action and connection timeout)
11075 23:53:56.169140 /lava-14084347/bin/lava-test-runner /lava-14084347/0
11076 23:53:56.408025 + export TESTRUN_ID=0_lc-compliance
11077 23:53:56.414149 + cd /lava-14084347/0/tests/0_lc-compliance
11078 23:53:56.414276 + cat uuid
11079 23:53:56.421371 + UUID=14084347_1.6.2.3.1
11080 23:53:56.421477 + set +x
11081 23:53:56.427888 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14084347_1.6.2.3.1>
11082 23:53:56.428183 Received signal: <STARTRUN> 0_lc-compliance 14084347_1.6.2.3.1
11083 23:53:56.428285 Starting test lava.0_lc-compliance (14084347_1.6.2.3.1)
11084 23:53:56.428403 Skipping test definition patterns.
11085 23:53:56.431017 + /usr/bin/lc-compliance-parser.sh
11086 23:53:58.072789 [0:00:20.286663559] [414] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11087 23:53:58.076444 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11088 23:53:58.090112 [0:00:20.304164345] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11089 23:53:58.152572 [0:00:20.365817637] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11090 23:53:58.163082 [==========] Running 120 tests from 1 test suite.
11091 23:53:58.209516 [0:00:20.421933507] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11092 23:53:58.232755 [----------] Global test environment set-up.
11093 23:53:58.263437 [0:00:20.475408854] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11094 23:53:58.319796 [----------] 120 tests from CaptureTests/SingleStream
11095 23:53:58.402655 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11096 23:53:58.466444 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11097 23:53:58.466771 Received signal: <TESTSET> START CaptureTests/SingleStream
11098 23:53:58.466875 Starting test_set CaptureTests/SingleStream
11099 23:53:58.469036 Camera needs 4 requests, can't test only 1
11100 23:53:58.543148 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11101 23:53:58.618838
11102 23:53:58.693269 [0:00:20.900301639] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 23:53:58.703814 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (62 ms)
11104 23:53:58.793843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11105 23:53:58.794178 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11107 23:53:58.811540 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11108 23:53:58.863444 Camera needs 4 requests, can't test only 2
11109 23:53:58.943814 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11110 23:53:59.022327
11111 23:53:59.108894 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (55 ms)
11112 23:53:59.201090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11113 23:53:59.201418 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11115 23:53:59.216992 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11116 23:53:59.271151 Camera needs 4 requests, can't test only 3
11117 23:53:59.351844 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11118 23:53:59.387500 [0:00:21.588334992] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11119 23:53:59.434561
11120 23:53:59.518678 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
11121 23:53:59.629341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11122 23:53:59.629675 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11124 23:53:59.646299 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11125 23:53:59.698002 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (424 ms)
11126 23:53:59.789269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11127 23:53:59.789673 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11129 23:53:59.806393 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11130 23:53:59.859652 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (689 ms)
11131 23:53:59.951685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11132 23:53:59.952006 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11134 23:53:59.967403 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11135 23:54:00.634469 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1243 ms)
11136 23:54:00.644305 [0:00:22.833552457] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 23:54:00.737502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11138 23:54:00.737832 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11140 23:54:00.754055 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11141 23:54:02.450839 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1804 ms)
11142 23:54:02.461353 [0:00:24.638370622] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11143 23:54:02.554495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11144 23:54:02.554798 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11146 23:54:02.570278 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11147 23:54:05.179410 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2714 ms)
11148 23:54:05.189607 [0:00:27.352286392] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 23:54:05.281324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11150 23:54:05.281618 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11152 23:54:05.298525 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11153 23:54:09.377533 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4184 ms)
11154 23:54:09.387462 [0:00:31.536728495] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11155 23:54:09.481726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11156 23:54:09.482017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11158 23:54:09.497938 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11159 23:54:15.706993 <6>[ 38.093515] vpu: disabling
11160 23:54:15.710212 <6>[ 38.096616] vproc2: disabling
11161 23:54:15.714014 <6>[ 38.099936] vproc1: disabling
11162 23:54:15.717247 <6>[ 38.103263] vaud18: disabling
11163 23:54:15.723437 <6>[ 38.106777] vsram_others: disabling
11164 23:54:15.727099 <6>[ 38.110772] va09: disabling
11165 23:54:15.730165 <6>[ 38.113937] vsram_md: disabling
11166 23:54:15.733612 <6>[ 38.117499] Vgpu: disabling
11167 23:54:15.955971 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6567 ms)
11168 23:54:15.965544 [0:00:38.104882218] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11169 23:54:16.021113 [0:00:38.160119665] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11170 23:54:16.060103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11171 23:54:16.060388 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11173 23:54:16.077246 [0:00:38.215616342] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11174 23:54:16.080403 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11175 23:54:16.134728 [0:00:38.273537512] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11176 23:54:16.137931 Camera needs 4 requests, can't test only 1
11177 23:54:16.222920 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11178 23:54:16.302246
11179 23:54:16.389321 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11180 23:54:16.486032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11181 23:54:16.486334 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11183 23:54:16.503908 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11184 23:54:16.556284 Camera needs 4 requests, can't test only 2
11185 23:54:16.635999 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11186 23:54:16.718367
11187 23:54:16.812091 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
11188 23:54:16.829490 [0:00:38.967584758] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11189 23:54:16.911101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11190 23:54:16.911399 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11192 23:54:16.927710 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11193 23:54:16.982433 Camera needs 4 requests, can't test only 3
11194 23:54:17.058480 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11195 23:54:17.133615
11196 23:54:17.215512 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (56 ms)
11197 23:54:17.328721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11198 23:54:17.329042 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11200 23:54:17.348520 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11201 23:54:17.412743 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (694 ms)
11202 23:54:17.525412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11203 23:54:17.525735 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11205 23:54:17.546545 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11206 23:54:17.727876 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (905 ms)
11207 23:54:17.740884 [0:00:39.875389634] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11208 23:54:17.844104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11209 23:54:17.844434 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11211 23:54:17.863585 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11212 23:54:18.984964 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1256 ms)
11213 23:54:18.998306 [0:00:41.131686951] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 23:54:19.088931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11215 23:54:19.089226 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11217 23:54:19.106381 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11218 23:54:20.803808 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1817 ms)
11219 23:54:20.817451 [0:00:42.949309815] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11220 23:54:20.906216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11221 23:54:20.906521 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11223 23:54:20.924175 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11224 23:54:23.533432 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2728 ms)
11225 23:54:23.546468 [0:00:45.678014628] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 23:54:23.634974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11227 23:54:23.635281 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11229 23:54:23.652094 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11230 23:54:27.731003 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4196 ms)
11231 23:54:27.743832 [0:00:49.874798761] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 23:54:27.855799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11233 23:54:27.856128 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11235 23:54:27.876397 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11236 23:54:34.308830 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6577 ms)
11237 23:54:34.321541 [0:00:56.452483472] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11238 23:54:34.375240 [0:00:56.508763692] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11239 23:54:34.421161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11240 23:54:34.421451 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11242 23:54:34.434580 [0:00:56.566362720] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 23:54:34.442109 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11244 23:54:34.487343 [0:00:56.621302981] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11245 23:54:34.503280 Camera needs 4 requests, can't test only 1
11246 23:54:34.589329 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11247 23:54:34.673638
11248 23:54:34.762527 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (57 ms)
11249 23:54:34.864490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11250 23:54:34.864826 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11252 23:54:34.881453 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11253 23:54:34.939609 Camera needs 4 requests, can't test only 2
11254 23:54:35.028223 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11255 23:54:35.113681
11256 23:54:35.180731 [0:00:57.315190563] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11257 23:54:35.201229 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (56 ms)
11258 23:54:35.302665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11259 23:54:35.302957 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11261 23:54:35.323253 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11262 23:54:35.379292 Camera needs 4 requests, can't test only 3
11263 23:54:35.470732 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11264 23:54:35.557072
11265 23:54:35.647548 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
11266 23:54:35.752377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11267 23:54:35.752679 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11269 23:54:35.769964 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11270 23:54:35.826424 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (694 ms)
11271 23:54:35.937413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11272 23:54:35.937702 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11274 23:54:35.954696 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11275 23:54:36.078904 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (905 ms)
11276 23:54:36.091762 [0:00:58.222445500] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11277 23:54:36.187139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11278 23:54:36.187446 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11280 23:54:36.205604 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11281 23:54:37.336287 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11282 23:54:37.349713 [0:00:59.480307470] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11283 23:54:37.441776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11284 23:54:37.442076 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11286 23:54:37.459002 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11287 23:54:39.157681 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1818 ms)
11288 23:54:39.167704 [0:01:01.297911855] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 23:54:39.284369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11290 23:54:39.285312 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11292 23:54:39.306676 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11293 23:54:41.886899 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11294 23:54:41.897100 [0:01:04.027580059] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 23:54:42.009458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11296 23:54:42.009835 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11298 23:54:42.028748 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11299 23:54:46.080945 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4197 ms)
11300 23:54:46.094426 [0:01:08.225705462] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 23:54:46.180665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11302 23:54:46.180974 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11304 23:54:46.198834 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11305 23:54:52.658971 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6578 ms)
11306 23:54:52.672021 [0:01:14.804174606] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11307 23:54:52.726069 [0:01:14.861287615] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11308 23:54:52.761173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11309 23:54:52.761476 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11311 23:54:52.781479 [0:01:14.916952174] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 23:54:52.785079 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11313 23:54:52.838847 [0:01:14.974505564] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11314 23:54:52.842581 Camera needs 4 requests, can't test only 1
11315 23:54:52.928535 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11316 23:54:53.028101
11317 23:54:53.129915 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11318 23:54:53.246747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11319 23:54:53.247062 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11321 23:54:53.263873 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11322 23:54:53.319079 Camera needs 4 requests, can't test only 2
11323 23:54:53.398440 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11324 23:54:53.487868
11325 23:54:53.533325 [0:01:15.668729268] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11326 23:54:53.576997 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (55 ms)
11327 23:54:53.682298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11328 23:54:53.682612 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11330 23:54:53.702573 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11331 23:54:53.769338 Camera needs 4 requests, can't test only 3
11332 23:54:53.867007 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11333 23:54:53.960052
11334 23:54:54.070755 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (58 ms)
11335 23:54:54.196902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11336 23:54:54.197747 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11338 23:54:54.218995 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11339 23:54:54.279063 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11340 23:54:54.373653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11341 23:54:54.373954 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11343 23:54:54.390592 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11344 23:54:54.440379 [0:01:16.575995115] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11345 23:54:54.452172 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (906 ms)
11346 23:54:54.548516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11347 23:54:54.548835 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11349 23:54:54.565815 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11350 23:54:55.686786 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1254 ms)
11351 23:54:55.699890 [0:01:17.831835167] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 23:54:55.807726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11353 23:54:55.808555 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11355 23:54:55.826826 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11356 23:54:57.504009 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1818 ms)
11357 23:54:57.517436 [0:01:19.650083572] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 23:54:57.612776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11359 23:54:57.613145 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11361 23:54:57.633413 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11362 23:55:00.232298 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11363 23:55:00.245533 [0:01:22.378031561] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 23:55:00.332902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11365 23:55:00.333225 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11367 23:55:00.351038 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11368 23:55:04.430081 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4198 ms)
11369 23:55:04.443587 [0:01:26.576698564] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 23:55:04.556546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11371 23:55:04.557386 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11373 23:55:04.580103 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11374 23:55:11.007571 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6578 ms)
11375 23:55:11.021160 [0:01:33.154713412] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 23:55:11.075280 [0:01:33.212494376] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11377 23:55:11.108773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11378 23:55:11.109099 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11380 23:55:11.130833 [0:01:33.268173957] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 23:55:11.133899 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11382 23:55:11.186902 [0:01:33.324580691] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11383 23:55:11.190555 Camera needs 4 requests, can't test only 1
11384 23:55:11.265393 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11385 23:55:11.341354
11386 23:55:11.430914 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (58 ms)
11387 23:55:11.528663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11388 23:55:11.528967 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11390 23:55:11.545053 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11391 23:55:11.597899 Camera needs 4 requests, can't test only 2
11392 23:55:11.677355 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11393 23:55:11.761087
11394 23:55:11.838904 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11395 23:55:11.940864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11396 23:55:11.941182 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11398 23:55:11.958428 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11399 23:55:12.011963 Camera needs 4 requests, can't test only 3
11400 23:55:12.092489 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11401 23:55:12.168265
11402 23:55:12.251466 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (57 ms)
11403 23:55:12.340827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11404 23:55:12.341137 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11406 23:55:12.357191 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11407 23:55:13.260983 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2081 ms)
11408 23:55:13.273841 [0:01:35.408180655] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11409 23:55:13.364860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11410 23:55:13.365215 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11412 23:55:13.382372 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11413 23:55:15.977595 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2717 ms)
11414 23:55:15.990859 [0:01:38.125604674] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 23:55:16.078666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11416 23:55:16.078984 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11418 23:55:16.097481 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11419 23:55:19.739900 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3762 ms)
11420 23:55:19.753222 [0:01:41.888159889] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11421 23:55:19.842990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11422 23:55:19.843316 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11424 23:55:19.859774 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11425 23:55:25.181153 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5441 ms)
11426 23:55:25.194257 [0:01:47.330174081] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 23:55:25.284056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11428 23:55:25.284358 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11430 23:55:25.300288 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11431 23:55:33.355611 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8174 ms)
11432 23:55:33.368613 [0:01:55.505205195] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 23:55:33.495453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11434 23:55:33.496257 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11436 23:55:33.514180 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11437 23:55:45.937107 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12583 ms)
11438 23:55:45.950793 [0:02:08.088651912] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 23:55:46.046390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11440 23:55:46.046689 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11442 23:55:46.065249 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11443 23:56:05.659522 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19724 ms)
11444 23:56:05.672891 [0:02:27.813452485] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11445 23:56:05.728380 [0:02:27.871746793] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11446 23:56:05.757363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11447 23:56:05.757643 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11449 23:56:05.773653 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11450 23:56:05.786660 [0:02:27.926953946] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 23:56:05.826271 Camera needs 4 requests, can't test only 1
11452 23:56:05.840418 [0:02:27.984111562] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11453 23:56:05.907016 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11454 23:56:05.982997
11455 23:56:06.067452 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (58 ms)
11456 23:56:06.167803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11457 23:56:06.168119 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11459 23:56:06.180832 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11460 23:56:06.236128 Camera needs 4 requests, can't test only 2
11461 23:56:06.310843 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11462 23:56:06.389178
11463 23:56:06.479156 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (55 ms)
11464 23:56:06.570076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11465 23:56:06.570379 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11467 23:56:06.587540 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11468 23:56:06.642498 Camera needs 4 requests, can't test only 3
11469 23:56:06.723438 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11470 23:56:06.804723
11471 23:56:06.895737 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (57 ms)
11472 23:56:06.984982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11473 23:56:06.985288 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11475 23:56:06.998517 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11476 23:56:07.915292 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2079 ms)
11477 23:56:07.924894 [0:02:30.065632407] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 23:56:08.010967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11479 23:56:08.011293 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11481 23:56:08.022070 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11482 23:56:10.627192 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11483 23:56:10.636884 [0:02:32.778084176] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 23:56:10.726223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11485 23:56:10.726510 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11487 23:56:10.740830 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11488 23:56:14.388338 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3761 ms)
11489 23:56:14.398133 [0:02:36.539479022] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 23:56:14.484834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11491 23:56:14.485181 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11493 23:56:14.498041 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11494 23:56:19.829599 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5441 ms)
11495 23:56:19.839344 [0:02:41.981555483] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 23:56:19.929655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11497 23:56:19.929952 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11499 23:56:19.944040 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11500 23:56:28.003621 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8174 ms)
11501 23:56:28.013307 [0:02:50.156448945] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 23:56:28.110009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11503 23:56:28.110315 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11505 23:56:28.124433 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11506 23:56:40.585655 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12583 ms)
11507 23:56:40.595140 [0:03:02.739661714] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 23:56:40.699960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11509 23:56:40.700266 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11511 23:56:40.714663 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11512 23:57:00.308418 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19724 ms)
11513 23:57:00.318525 [0:03:22.464444023] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 23:57:00.369961 [0:03:22.519578485] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11515 23:57:00.426505 [0:03:22.576384100] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11516 23:57:00.432953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11517 23:57:00.433222 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11519 23:57:00.442013 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11520 23:57:00.483536 [0:03:22.633572792] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 23:57:00.499396 Camera needs 4 requests, can't test only 1
11522 23:57:00.582051 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11523 23:57:00.660467
11524 23:57:00.753522 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (55 ms)
11525 23:57:00.848382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11526 23:57:00.848680 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11528 23:57:00.862489 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11529 23:57:00.918585 Camera needs 4 requests, can't test only 2
11530 23:57:01.011544 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11531 23:57:01.086542
11532 23:57:01.183123 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11533 23:57:01.283139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11534 23:57:01.283435 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11536 23:57:01.296801 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11537 23:57:01.348068 Camera needs 4 requests, can't test only 3
11538 23:57:01.430736 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11539 23:57:01.509662
11540 23:57:01.597561 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (58 ms)
11541 23:57:01.692971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11542 23:57:01.693270 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11544 23:57:01.708389 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11545 23:57:02.558397 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2079 ms)
11546 23:57:02.568549 [0:03:24.715202793] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 23:57:02.673388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11548 23:57:02.674162 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11550 23:57:02.690489 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11551 23:57:05.271082 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11552 23:57:05.281447 [0:03:27.427887331] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 23:57:05.383855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11554 23:57:05.384764 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11556 23:57:05.402520 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11557 23:57:09.032425 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3761 ms)
11558 23:57:09.041881 [0:03:31.189335024] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 23:57:09.157252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11560 23:57:09.158024 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11562 23:57:09.176879 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11563 23:57:14.473434 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5441 ms)
11564 23:57:14.482911 [0:03:36.631158255] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 23:57:14.597543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11566 23:57:14.598296 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11568 23:57:14.615834 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11569 23:57:22.647808 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8175 ms)
11570 23:57:22.657708 [0:03:44.806232409] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 23:57:22.765455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11572 23:57:22.766222 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11574 23:57:22.782167 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11575 23:57:35.226088 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12579 ms)
11576 23:57:35.235922 [0:03:57.386087564] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 23:57:35.329998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11578 23:57:35.330337 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11580 23:57:35.345032 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11581 23:57:54.948529 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19724 ms)
11582 23:57:54.957949 [0:04:17.110972026] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11583 23:57:55.010589 [0:04:17.166871334] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11584 23:57:55.065424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11585 23:57:55.065760 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11587 23:57:55.075356 [0:04:17.225255257] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 23:57:55.082513 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11589 23:57:55.124410 [0:04:17.280440103] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11590 23:57:55.142404 Camera needs 4 requests, can't test only 1
11591 23:57:55.223920 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11592 23:57:55.295182
11593 23:57:55.380535 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11594 23:57:55.477879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11595 23:57:55.478234 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11597 23:57:55.490863 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11598 23:57:55.544530 Camera needs 4 requests, can't test only 2
11599 23:57:55.626336 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11600 23:57:55.704379
11601 23:57:55.796028 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (58 ms)
11602 23:57:55.912430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11603 23:57:55.912799 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11605 23:57:55.930217 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11606 23:57:55.982815 Camera needs 4 requests, can't test only 3
11607 23:57:56.076175 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11608 23:57:56.164341
11609 23:57:56.260369 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (56 ms)
11610 23:57:56.358242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11611 23:57:56.358556 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11613 23:57:56.371965 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11614 23:57:57.199335 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2079 ms)
11615 23:57:57.209101 [0:04:19.362019334] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11616 23:57:57.310671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11617 23:57:57.310974 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11619 23:57:57.327074 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11620 23:57:59.912193 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2712 ms)
11621 23:57:59.922271 [0:04:22.075128258] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11622 23:58:00.040416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11623 23:58:00.041238 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11625 23:58:00.059311 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11626 23:58:03.674360 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3761 ms)
11627 23:58:03.683745 [0:04:25.837023258] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11628 23:58:03.814430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11629 23:58:03.815156 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11631 23:58:03.833986 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11632 23:58:09.114968 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5441 ms)
11633 23:58:09.124243 [0:04:31.278224258] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11634 23:58:09.237943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11635 23:58:09.238674 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11637 23:58:09.256601 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11638 23:58:17.288628 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8174 ms)
11639 23:58:17.298386 [0:04:39.453020412] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11640 23:58:17.416744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11641 23:58:17.417549 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11643 23:58:17.436475 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11644 23:58:29.870720 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12583 ms)
11645 23:58:29.880255 [0:04:52.037003644] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11646 23:58:29.986682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11647 23:58:29.987500 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11649 23:58:30.003780 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11650 23:58:49.592396 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19724 ms)
11651 23:58:49.602175 [0:05:11.761482260] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11652 23:58:49.691903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11653 23:58:49.692203 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11655 23:58:49.705403 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11656 23:58:50.006718 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (417 ms)
11657 23:58:50.020147 [0:05:12.179143030] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11658 23:58:50.107902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11659 23:58:50.108188 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11661 23:58:50.125772 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11662 23:58:50.496706 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (489 ms)
11663 23:58:50.509785 [0:05:12.668936261] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11664 23:58:50.601714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11665 23:58:50.602014 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11667 23:58:50.620321 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11668 23:58:51.054218 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (557 ms)
11669 23:58:51.067355 [0:05:13.226629414] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11670 23:58:51.153468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11671 23:58:51.153766 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11673 23:58:51.168934 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11674 23:58:51.751835 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (697 ms)
11675 23:58:51.764922 [0:05:13.923922261] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11676 23:58:51.870606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11677 23:58:51.871268 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11679 23:58:51.889273 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11680 23:58:52.660329 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (908 ms)
11681 23:58:52.673698 [0:05:14.832614953] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11682 23:58:52.783701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11683 23:58:52.784442 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11685 23:58:52.804621 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11686 23:58:53.918387 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1258 ms)
11687 23:58:53.931650 [0:05:16.090831568] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11688 23:58:54.039103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11689 23:58:54.039828 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11691 23:58:54.061187 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11692 23:58:55.736045 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1817 ms)
11693 23:58:55.749329 [0:05:17.908862569] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11694 23:58:55.851435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11695 23:58:55.851757 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11697 23:58:55.869996 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11698 23:58:58.464849 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2728 ms)
11699 23:58:58.477533 [0:05:20.637436338] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11700 23:58:58.573380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11701 23:58:58.573684 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11703 23:58:58.591282 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11704 23:59:02.662675 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4198 ms)
11705 23:59:02.675252 [0:05:24.836115261] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11706 23:59:02.768317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11707 23:59:02.768586 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11709 23:59:02.784752 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11710 23:59:09.241064 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6579 ms)
11711 23:59:09.253964 [0:05:31.415292646] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11712 23:59:09.348679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11713 23:59:09.349031 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11715 23:59:09.365810 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11716 23:59:09.661585 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (417 ms)
11717 23:59:09.670853 [0:05:31.832600108] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11718 23:59:09.765380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11719 23:59:09.765728 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11721 23:59:09.778640 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11722 23:59:10.149931 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (488 ms)
11723 23:59:10.159524 [0:05:32.320807185] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11724 23:59:10.249363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11725 23:59:10.249705 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11727 23:59:10.263473 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11728 23:59:10.707308 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (557 ms)
11729 23:59:10.717451 [0:05:32.878940569] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11730 23:59:10.810511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11731 23:59:10.810826 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11733 23:59:10.823322 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11734 23:59:11.405809 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (697 ms)
11735 23:59:11.415427 [0:05:33.576958800] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11736 23:59:11.512540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11737 23:59:11.512907 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11739 23:59:11.525741 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11740 23:59:12.315038 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (909 ms)
11741 23:59:12.325053 [0:05:34.486812108] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11742 23:59:12.418667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11743 23:59:12.419030 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11745 23:59:12.433275 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11746 23:59:13.573091 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1257 ms)
11747 23:59:13.582754 [0:05:35.744701185] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11748 23:59:13.666218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11749 23:59:13.666528 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11751 23:59:13.678844 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11752 23:59:15.390894 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1818 ms)
11753 23:59:15.401139 [0:05:37.563110877] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11754 23:59:15.494425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11755 23:59:15.494741 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11757 23:59:15.509559 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11758 23:59:18.121160 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2730 ms)
11759 23:59:18.131426 [0:05:40.293539647] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11760 23:59:18.222388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11761 23:59:18.222745 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11763 23:59:18.236566 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11764 23:59:22.319407 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4198 ms)
11765 23:59:22.329357 [0:05:44.492272570] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11766 23:59:22.418697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11767 23:59:22.419071 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11769 23:59:22.430400 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11770 23:59:28.897584 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6578 ms)
11771 23:59:28.907753 [0:05:51.071143571] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11772 23:59:29.000807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11773 23:59:29.001122 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11775 23:59:29.016994 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11776 23:59:29.315704 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (417 ms)
11777 23:59:29.325867 [0:05:51.488381571] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11778 23:59:29.414472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11779 23:59:29.414825 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11781 23:59:29.427732 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11782 23:59:29.803568 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (487 ms)
11783 23:59:29.813597 [0:05:51.976501571] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11784 23:59:29.905189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11785 23:59:29.905525 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11787 23:59:29.920495 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11788 23:59:30.361246 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (557 ms)
11789 23:59:30.370993 [0:05:52.534513955] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11790 23:59:30.465595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11791 23:59:30.465998 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11793 23:59:30.481782 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11794 23:59:31.058958 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (697 ms)
11795 23:59:31.069269 [0:05:53.232651340] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11796 23:59:31.159900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11797 23:59:31.160228 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11799 23:59:31.174004 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11800 23:59:31.968502 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (909 ms)
11801 23:59:31.978336 [0:05:54.141941340] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11802 23:59:32.070085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11803 23:59:32.070393 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11805 23:59:32.083221 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11806 23:59:33.226017 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1257 ms)
11807 23:59:33.235794 [0:05:55.399811571] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11808 23:59:33.333478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11809 23:59:33.333830 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11811 23:59:33.348937 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11812 23:59:35.044260 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1818 ms)
11813 23:59:35.053828 [0:05:57.218250417] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11814 23:59:35.147725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11815 23:59:35.148058 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11817 23:59:35.162346 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11818 23:59:37.772184 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2728 ms)
11819 23:59:37.782342 [0:05:59.946116571] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11820 23:59:37.877898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11821 23:59:37.878240 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11823 23:59:37.892264 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11824 23:59:41.970147 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4198 ms)
11825 23:59:41.980250 [0:06:04.144967417] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11826 23:59:42.076657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11827 23:59:42.077061 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11829 23:59:42.091627 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11830 23:59:48.548053 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6578 ms)
11831 23:59:48.558022 [0:06:10.723997649] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11832 23:59:48.651522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11833 23:59:48.651825 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11835 23:59:48.665900 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11836 23:59:48.965769 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (417 ms)
11837 23:59:48.975503 [0:06:11.141098187] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11838 23:59:49.063192 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11840 23:59:49.066396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11841 23:59:49.082621 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11842 23:59:49.453451 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (487 ms)
11843 23:59:49.463073 [0:06:11.629002726] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11844 23:59:49.558143 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11846 23:59:49.561145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11847 23:59:49.577464 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11848 23:59:50.011342 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (557 ms)
11849 23:59:50.020916 [0:06:12.187115187] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11850 23:59:50.109262 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11852 23:59:50.112093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11853 23:59:50.127354 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11854 23:59:50.709360 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (697 ms)
11855 23:59:50.718799 [0:06:12.884881187] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11856 23:59:50.806870 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11858 23:59:50.809838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11859 23:59:50.823017 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11860 23:59:51.617314 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (907 ms)
11861 23:59:51.626990 [0:06:13.793206495] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11862 23:59:51.709560 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11864 23:59:51.712422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11865 23:59:51.725240 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11866 23:59:52.874329 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1257 ms)
11867 23:59:52.884578 [0:06:15.050683187] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11868 23:59:52.975071 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11870 23:59:52.978020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11871 23:59:52.993106 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11872 23:59:54.691893 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1817 ms)
11873 23:59:54.701918 [0:06:16.868508034] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11874 23:59:54.793648 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11876 23:59:54.796657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11877 23:59:54.811917 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11878 23:59:57.421106 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2728 ms)
11879 23:59:57.430566 [0:06:19.597322495] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11880 23:59:57.532116 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11882 23:59:57.535087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11883 23:59:57.549727 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11884 00:00:01.618857 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4198 ms)
11885 00:00:01.628795 [0:06:23.795929034] [414] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11886 00:00:01.718696 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11888 00:00:01.721617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11889 00:00:01.735233 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11890 00:00:08.196102 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6578 ms)
11891 00:00:08.290222 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11893 00:00:08.293510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11894 00:00:08.306837 [----------] 120 tests from CaptureTests/SingleStream (370069 ms total)
11895 00:00:08.389011
11896 00:00:08.473342 [----------] Global test environment tear-down
11897 00:00:08.552612 [==========] 120 tests from 1 test suite ran. (370069 ms total)
11898 00:00:08.638665 <LAVA_SIGNAL_TESTSET STOP>
11899 00:00:08.638984 Received signal: <TESTSET> STOP
11900 00:00:08.639059 Closing test_set CaptureTests/SingleStream
11901 00:00:08.642129 + set +x
11902 00:00:08.645392 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14084347_1.6.2.3.1>
11903 00:00:08.645645 Received signal: <ENDRUN> 0_lc-compliance 14084347_1.6.2.3.1
11904 00:00:08.645726 Ending use of test pattern.
11905 00:00:08.645814 Ending test lava.0_lc-compliance (14084347_1.6.2.3.1), duration 372.22
11907 00:00:08.648596 <LAVA_TEST_RUNNER EXIT>
11908 00:00:08.648862 ok: lava_test_shell seems to have completed
11909 00:00:08.650709 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11910 00:00:08.650896 end: 3.1 lava-test-shell (duration 00:06:13) [common]
11911 00:00:08.651002 end: 3 lava-test-retry (duration 00:06:13) [common]
11912 00:00:08.651107 start: 4 finalize (timeout 00:10:00) [common]
11913 00:00:08.651194 start: 4.1 power-off (timeout 00:00:30) [common]
11914 00:00:08.651349 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11915 00:00:08.728788 >> Command sent successfully.
11916 00:00:08.731342 Returned 0 in 0 seconds
11917 00:00:08.831734 end: 4.1 power-off (duration 00:00:00) [common]
11919 00:00:08.832071 start: 4.2 read-feedback (timeout 00:10:00) [common]
11920 00:00:08.832344 Listened to connection for namespace 'common' for up to 1s
11921 00:00:09.832656 Finalising connection for namespace 'common'
11922 00:00:09.832811 Disconnecting from shell: Finalise
11923 00:00:09.832886 / #
11924 00:00:09.933281 end: 4.2 read-feedback (duration 00:00:01) [common]
11925 00:00:09.933435 end: 4 finalize (duration 00:00:01) [common]
11926 00:00:09.933546 Cleaning after the job
11927 00:00:09.933641 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/ramdisk
11928 00:00:09.935765 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/kernel
11929 00:00:09.946514 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/dtb
11930 00:00:09.946685 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/nfsrootfs
11931 00:00:09.987506 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084347/tftp-deploy-zua2va7t/modules
11932 00:00:09.993161 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084347
11933 00:00:10.254216 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084347
11934 00:00:10.254406 Job finished correctly