Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:52:54.853809 lava-dispatcher, installed at version: 2024.03
2 23:52:54.854042 start: 0 validate
3 23:52:54.854183 Start time: 2024-05-29 23:52:54.854175+00:00 (UTC)
4 23:52:54.854334 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:52:54.854515 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:52:55.113698 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:52:55.113884 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:52:55.372578 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:52:55.372759 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:52:55.632346 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:52:55.632506 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:52:55.899268 validate duration: 1.05
14 23:52:55.899556 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:52:55.899683 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:52:55.899820 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:52:55.899981 Not decompressing ramdisk as can be used compressed.
18 23:52:55.900094 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 23:52:55.900186 saving as /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/ramdisk/rootfs.cpio.gz
20 23:52:55.900280 total size: 28105535 (26 MB)
21 23:52:55.901757 progress 0 % (0 MB)
22 23:52:55.909482 progress 5 % (1 MB)
23 23:52:55.916803 progress 10 % (2 MB)
24 23:52:55.924120 progress 15 % (4 MB)
25 23:52:55.931369 progress 20 % (5 MB)
26 23:52:55.938911 progress 25 % (6 MB)
27 23:52:55.946581 progress 30 % (8 MB)
28 23:52:55.954587 progress 35 % (9 MB)
29 23:52:55.962261 progress 40 % (10 MB)
30 23:52:55.969606 progress 45 % (12 MB)
31 23:52:55.977359 progress 50 % (13 MB)
32 23:52:55.984787 progress 55 % (14 MB)
33 23:52:55.992221 progress 60 % (16 MB)
34 23:52:55.999582 progress 65 % (17 MB)
35 23:52:56.006979 progress 70 % (18 MB)
36 23:52:56.014384 progress 75 % (20 MB)
37 23:52:56.021782 progress 80 % (21 MB)
38 23:52:56.029051 progress 85 % (22 MB)
39 23:52:56.036101 progress 90 % (24 MB)
40 23:52:56.043368 progress 95 % (25 MB)
41 23:52:56.050617 progress 100 % (26 MB)
42 23:52:56.050845 26 MB downloaded in 0.15 s (178.02 MB/s)
43 23:52:56.050997 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:52:56.051237 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:52:56.051323 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:52:56.051406 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:52:56.051539 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:52:56.051607 saving as /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/kernel/Image
50 23:52:56.051671 total size: 54682112 (52 MB)
51 23:52:56.051732 No compression specified
52 23:52:56.052876 progress 0 % (0 MB)
53 23:52:56.067206 progress 5 % (2 MB)
54 23:52:56.081477 progress 10 % (5 MB)
55 23:52:56.095748 progress 15 % (7 MB)
56 23:52:56.109858 progress 20 % (10 MB)
57 23:52:56.124077 progress 25 % (13 MB)
58 23:52:56.138242 progress 30 % (15 MB)
59 23:52:56.152473 progress 35 % (18 MB)
60 23:52:56.166807 progress 40 % (20 MB)
61 23:52:56.180953 progress 45 % (23 MB)
62 23:52:56.195310 progress 50 % (26 MB)
63 23:52:56.209591 progress 55 % (28 MB)
64 23:52:56.223829 progress 60 % (31 MB)
65 23:52:56.238121 progress 65 % (33 MB)
66 23:52:56.252472 progress 70 % (36 MB)
67 23:52:56.266704 progress 75 % (39 MB)
68 23:52:56.281063 progress 80 % (41 MB)
69 23:52:56.294982 progress 85 % (44 MB)
70 23:52:56.309309 progress 90 % (46 MB)
71 23:52:56.323462 progress 95 % (49 MB)
72 23:52:56.337212 progress 100 % (52 MB)
73 23:52:56.337509 52 MB downloaded in 0.29 s (182.44 MB/s)
74 23:52:56.337685 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:52:56.337960 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:52:56.338079 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:52:56.338204 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:52:56.338342 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:52:56.338417 saving as /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/dtb/mt8192-asurada-spherion-r0.dtb
81 23:52:56.338506 total size: 47258 (0 MB)
82 23:52:56.338567 No compression specified
83 23:52:56.339700 progress 69 % (0 MB)
84 23:52:56.339971 progress 100 % (0 MB)
85 23:52:56.340142 0 MB downloaded in 0.00 s (27.35 MB/s)
86 23:52:56.340388 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:52:56.340671 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:52:56.340803 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:52:56.340897 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:52:56.341013 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:52:56.341080 saving as /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/modules/modules.tar
93 23:52:56.341140 total size: 8601444 (8 MB)
94 23:52:56.341202 Using unxz to decompress xz
95 23:52:56.345524 progress 0 % (0 MB)
96 23:52:56.366487 progress 5 % (0 MB)
97 23:52:56.392022 progress 10 % (0 MB)
98 23:52:56.418056 progress 15 % (1 MB)
99 23:52:56.443331 progress 20 % (1 MB)
100 23:52:56.469576 progress 25 % (2 MB)
101 23:52:56.495137 progress 30 % (2 MB)
102 23:52:56.519112 progress 35 % (2 MB)
103 23:52:56.543873 progress 40 % (3 MB)
104 23:52:56.571077 progress 45 % (3 MB)
105 23:52:56.595782 progress 50 % (4 MB)
106 23:52:56.621197 progress 55 % (4 MB)
107 23:52:56.646124 progress 60 % (4 MB)
108 23:52:56.670445 progress 65 % (5 MB)
109 23:52:56.697269 progress 70 % (5 MB)
110 23:52:56.722811 progress 75 % (6 MB)
111 23:52:56.746614 progress 80 % (6 MB)
112 23:52:56.772485 progress 85 % (7 MB)
113 23:52:56.796661 progress 90 % (7 MB)
114 23:52:56.826357 progress 95 % (7 MB)
115 23:52:56.854745 progress 100 % (8 MB)
116 23:52:56.860196 8 MB downloaded in 0.52 s (15.80 MB/s)
117 23:52:56.860461 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:52:56.860736 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:52:56.860877 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:52:56.861009 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:52:56.861123 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:52:56.861242 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:52:56.861486 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4
125 23:52:56.861621 makedir: /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin
126 23:52:56.861725 makedir: /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/tests
127 23:52:56.861822 makedir: /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/results
128 23:52:56.861940 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-add-keys
129 23:52:56.862087 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-add-sources
130 23:52:56.862220 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-background-process-start
131 23:52:56.862351 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-background-process-stop
132 23:52:56.862477 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-common-functions
133 23:52:56.862602 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-echo-ipv4
134 23:52:56.862731 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-install-packages
135 23:52:56.862905 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-installed-packages
136 23:52:56.863051 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-os-build
137 23:52:56.863179 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-probe-channel
138 23:52:56.863304 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-probe-ip
139 23:52:56.863429 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-target-ip
140 23:52:56.863551 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-target-mac
141 23:52:56.863673 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-target-storage
142 23:52:56.863800 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-case
143 23:52:56.863924 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-event
144 23:52:56.864051 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-feedback
145 23:52:56.864175 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-raise
146 23:52:56.864296 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-reference
147 23:52:56.864432 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-runner
148 23:52:56.864558 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-set
149 23:52:56.864695 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-test-shell
150 23:52:56.864859 Updating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-install-packages (oe)
151 23:52:56.865043 Updating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/bin/lava-installed-packages (oe)
152 23:52:56.865195 Creating /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/environment
153 23:52:56.865325 LAVA metadata
154 23:52:56.865399 - LAVA_JOB_ID=14084359
155 23:52:56.865465 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:52:56.865569 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:52:56.865638 skipped lava-vland-overlay
158 23:52:56.865713 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:52:56.865797 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:52:56.865870 skipped lava-multinode-overlay
161 23:52:56.865943 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:52:56.866027 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:52:56.866105 Loading test definitions
164 23:52:56.866198 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:52:56.866272 Using /lava-14084359 at stage 0
166 23:52:56.866592 uuid=14084359_1.5.2.3.1 testdef=None
167 23:52:56.866681 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:52:56.866766 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:52:56.867291 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:52:56.867518 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:52:56.868255 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:52:56.868576 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:52:56.869285 runner path: /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14084359_1.5.2.3.1
176 23:52:56.869446 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:52:56.869656 Creating lava-test-runner.conf files
179 23:52:56.869720 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084359/lava-overlay-qusdsp_4/lava-14084359/0 for stage 0
180 23:52:56.869831 - 0_v4l2-compliance-mtk-vcodec-enc
181 23:52:56.869931 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:52:56.870026 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:52:56.877592 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:52:56.877715 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:52:56.877803 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:52:56.877888 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:52:56.877972 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:52:57.797806 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:52:57.798176 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:52:57.798290 extracting modules file /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084359/extract-overlay-ramdisk-qk56p9op/ramdisk
191 23:52:58.026447 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:52:58.026647 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:52:58.026797 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084359/compress-overlay-sg1f_bw4/overlay-1.5.2.4.tar.gz to ramdisk
194 23:52:58.026926 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084359/compress-overlay-sg1f_bw4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084359/extract-overlay-ramdisk-qk56p9op/ramdisk
195 23:52:58.034208 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:52:58.034343 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:52:58.034463 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:52:58.034582 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:52:58.034694 Building ramdisk /var/lib/lava/dispatcher/tmp/14084359/extract-overlay-ramdisk-qk56p9op/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084359/extract-overlay-ramdisk-qk56p9op/ramdisk
200 23:52:58.808015 >> 275882 blocks
201 23:53:02.954462 rename /var/lib/lava/dispatcher/tmp/14084359/extract-overlay-ramdisk-qk56p9op/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/ramdisk/ramdisk.cpio.gz
202 23:53:02.954952 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:53:02.955082 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 23:53:02.955190 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 23:53:02.955300 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/kernel/Image']
206 23:53:17.178753 Returned 0 in 14 seconds
207 23:53:17.279420 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/kernel/image.itb
208 23:53:17.932735 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:53:17.933144 output: Created: Thu May 30 00:53:17 2024
210 23:53:17.933245 output: Image 0 (kernel-1)
211 23:53:17.933356 output: Description:
212 23:53:17.933441 output: Created: Thu May 30 00:53:17 2024
213 23:53:17.933509 output: Type: Kernel Image
214 23:53:17.933572 output: Compression: lzma compressed
215 23:53:17.933691 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
216 23:53:17.933786 output: Architecture: AArch64
217 23:53:17.933852 output: OS: Linux
218 23:53:17.933912 output: Load Address: 0x00000000
219 23:53:17.933990 output: Entry Point: 0x00000000
220 23:53:17.934049 output: Hash algo: crc32
221 23:53:17.934107 output: Hash value: 907bf91d
222 23:53:17.934165 output: Image 1 (fdt-1)
223 23:53:17.934221 output: Description: mt8192-asurada-spherion-r0
224 23:53:17.934277 output: Created: Thu May 30 00:53:17 2024
225 23:53:17.934339 output: Type: Flat Device Tree
226 23:53:17.934393 output: Compression: uncompressed
227 23:53:17.934446 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:53:17.934500 output: Architecture: AArch64
229 23:53:17.934552 output: Hash algo: crc32
230 23:53:17.934605 output: Hash value: 0f8e4d2e
231 23:53:17.934657 output: Image 2 (ramdisk-1)
232 23:53:17.934710 output: Description: unavailable
233 23:53:17.934762 output: Created: Thu May 30 00:53:17 2024
234 23:53:17.934815 output: Type: RAMDisk Image
235 23:53:17.934868 output: Compression: Unknown Compression
236 23:53:17.934921 output: Data Size: 41202613 Bytes = 40236.93 KiB = 39.29 MiB
237 23:53:17.934974 output: Architecture: AArch64
238 23:53:17.935027 output: OS: Linux
239 23:53:17.935080 output: Load Address: unavailable
240 23:53:17.935132 output: Entry Point: unavailable
241 23:53:17.935185 output: Hash algo: crc32
242 23:53:17.935238 output: Hash value: 2303f8a4
243 23:53:17.935322 output: Default Configuration: 'conf-1'
244 23:53:17.935402 output: Configuration 0 (conf-1)
245 23:53:17.935479 output: Description: mt8192-asurada-spherion-r0
246 23:53:17.935542 output: Kernel: kernel-1
247 23:53:17.935595 output: Init Ramdisk: ramdisk-1
248 23:53:17.935648 output: FDT: fdt-1
249 23:53:17.935701 output: Loadables: kernel-1
250 23:53:17.935754 output:
251 23:53:17.935972 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 23:53:17.936095 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 23:53:17.936234 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 23:53:17.936359 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 23:53:17.936442 No LXC device requested
256 23:53:17.936526 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:53:17.936613 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 23:53:17.936692 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:53:17.936760 Checking files for TFTP limit of 4294967296 bytes.
260 23:53:17.937265 end: 1 tftp-deploy (duration 00:00:22) [common]
261 23:53:17.937429 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:53:17.937553 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:53:17.937688 substitutions:
264 23:53:17.937755 - {DTB}: 14084359/tftp-deploy-z1crv513/dtb/mt8192-asurada-spherion-r0.dtb
265 23:53:17.937827 - {INITRD}: 14084359/tftp-deploy-z1crv513/ramdisk/ramdisk.cpio.gz
266 23:53:17.937888 - {KERNEL}: 14084359/tftp-deploy-z1crv513/kernel/Image
267 23:53:17.937946 - {LAVA_MAC}: None
268 23:53:17.938002 - {PRESEED_CONFIG}: None
269 23:53:17.938058 - {PRESEED_LOCAL}: None
270 23:53:17.938112 - {RAMDISK}: 14084359/tftp-deploy-z1crv513/ramdisk/ramdisk.cpio.gz
271 23:53:17.938167 - {ROOT_PART}: None
272 23:53:17.938222 - {ROOT}: None
273 23:53:17.938280 - {SERVER_IP}: 192.168.201.1
274 23:53:17.938338 - {TEE}: None
275 23:53:17.938392 Parsed boot commands:
276 23:53:17.938447 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:53:17.938621 Parsed boot commands: tftpboot 192.168.201.1 14084359/tftp-deploy-z1crv513/kernel/image.itb 14084359/tftp-deploy-z1crv513/kernel/cmdline
278 23:53:17.938709 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:53:17.938798 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:53:17.938890 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:53:17.939017 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:53:17.939106 Not connected, no need to disconnect.
283 23:53:17.939218 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:53:17.939370 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:53:17.939477 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 23:53:17.943513 Setting prompt string to ['lava-test: # ']
287 23:53:17.944098 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:53:17.944291 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:53:17.944476 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:53:17.944606 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:53:17.944806 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
292 23:53:31.965353 Returned 0 in 14 seconds
293 23:53:32.066008 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 23:53:32.066741 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 23:53:32.066874 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 23:53:32.066969 Setting prompt string to 'Starting depthcharge on Spherion...'
298 23:53:32.067051 Changing prompt to 'Starting depthcharge on Spherion...'
299 23:53:32.067122 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 23:53:32.067714 [Enter `^Ec?' for help]
301 23:53:32.067877
302 23:53:32.068016
303 23:53:32.068086 F0: 102B 0000
304 23:53:32.068148
305 23:53:32.068210 F3: 1001 0000 [0200]
306 23:53:32.068271
307 23:53:32.068328 F3: 1001 0000
308 23:53:32.068388
309 23:53:32.068446 F7: 102D 0000
310 23:53:32.068503
311 23:53:32.068559 F1: 0000 0000
312 23:53:32.068615
313 23:53:32.068670 V0: 0000 0000 [0001]
314 23:53:32.068725
315 23:53:32.068779 00: 0007 8000
316 23:53:32.068838
317 23:53:32.068892 01: 0000 0000
318 23:53:32.068948
319 23:53:32.069002 BP: 0C00 0209 [0000]
320 23:53:32.069057
321 23:53:32.069112 G0: 1182 0000
322 23:53:32.069166
323 23:53:32.069220 EC: 0000 0021 [4000]
324 23:53:32.069282
325 23:53:32.069337 S7: 0000 0000 [0000]
326 23:53:32.069392
327 23:53:32.069446 CC: 0000 0000 [0001]
328 23:53:32.069500
329 23:53:32.069554 T0: 0000 0040 [010F]
330 23:53:32.069611
331 23:53:32.069665 Jump to BL
332 23:53:32.069720
333 23:53:32.069774
334 23:53:32.069828
335 23:53:32.069883 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 23:53:32.069940 ARM64: Exception handlers installed.
337 23:53:32.069996 ARM64: Testing exception
338 23:53:32.070051 ARM64: Done test exception
339 23:53:32.070105 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 23:53:32.070161 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 23:53:32.070216 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 23:53:32.070271 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 23:53:32.070327 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 23:53:32.070382 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 23:53:32.070437 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 23:53:32.070493 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 23:53:32.070548 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 23:53:32.070604 WDT: Last reset was cold boot
349 23:53:32.070680 SPI1(PAD0) initialized at 2873684 Hz
350 23:53:32.070737 SPI5(PAD0) initialized at 992727 Hz
351 23:53:32.070792 VBOOT: Loading verstage.
352 23:53:32.070847 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 23:53:32.070921 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 23:53:32.070979 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 23:53:32.071034 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 23:53:32.071090 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 23:53:32.071164 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 23:53:32.071221 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
359 23:53:32.071276
360 23:53:32.071330
361 23:53:32.071402 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 23:53:32.071460 ARM64: Exception handlers installed.
363 23:53:32.071515 ARM64: Testing exception
364 23:53:32.071569 ARM64: Done test exception
365 23:53:32.071651 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 23:53:32.071739 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 23:53:32.071825 Probing TPM: . done!
368 23:53:32.071920 TPM ready after 0 ms
369 23:53:32.072006 Connected to device vid:did:rid of 1ae0:0028:00
370 23:53:32.072100 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
371 23:53:32.072162 Initialized TPM device CR50 revision 0
372 23:53:32.072218 tlcl_send_startup: Startup return code is 0
373 23:53:32.072273 TPM: setup succeeded
374 23:53:32.072337 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 23:53:32.072428 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 23:53:32.072514 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 23:53:32.072609 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:53:32.072696 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 23:53:32.072782 in-header: 03 07 00 00 08 00 00 00
380 23:53:32.072876 in-data: aa e4 47 04 13 02 00 00
381 23:53:32.072962 Chrome EC: UHEPI supported
382 23:53:32.073049 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 23:53:32.073144 in-header: 03 a9 00 00 08 00 00 00
384 23:53:32.073230 in-data: 84 60 60 08 00 00 00 00
385 23:53:32.073329 Phase 1
386 23:53:32.073389 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 23:53:32.073445 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 23:53:32.073501 VB2:vb2_check_recovery() Recovery was requested manually
389 23:53:32.073568 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 23:53:32.073627 Recovery requested (1009000e)
391 23:53:32.073682 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:53:32.073738 tlcl_extend: response is 0
393 23:53:32.073805 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:53:32.073864 tlcl_extend: response is 0
395 23:53:32.073920 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:53:32.073975 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
397 23:53:32.074042 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:53:32.074100
399 23:53:32.074155
400 23:53:32.074209 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:53:32.074277 ARM64: Exception handlers installed.
402 23:53:32.074334 ARM64: Testing exception
403 23:53:32.074389 ARM64: Done test exception
404 23:53:32.074443 pmic_efuse_setting: Set efuses in 11 msecs
405 23:53:32.074498 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:53:32.074552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:53:32.074620 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:53:32.074880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:53:32.075017 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:53:32.075150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:53:32.075281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:53:32.075415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:53:32.075505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:53:32.075564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:53:32.075620 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:53:32.075676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:53:32.075731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:53:32.075787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:53:32.075841 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:53:32.075897 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:53:32.075952 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:53:32.076007 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:53:32.076061 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:53:32.076115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:53:32.076170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:53:32.076224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:53:32.076279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:53:32.076334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:53:32.076388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:53:32.076443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:53:32.076497 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:53:32.076552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:53:32.076606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:53:32.076660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:53:32.076715 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:53:32.076769 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:53:32.076824 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:53:32.076878 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:53:32.076933 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:53:32.076987 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:53:32.077041 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:53:32.077096 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:53:32.077151 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:53:32.077205 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:53:32.077268 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:53:32.077326 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:53:32.077380 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:53:32.077435 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:53:32.077489 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:53:32.077544 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:53:32.077599 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:53:32.077653 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:53:32.077708 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:53:32.077762 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:53:32.077816 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:53:32.077870 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:53:32.077925 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 23:53:32.077980 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:53:32.078036 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:53:32.078091 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:53:32.078146 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:53:32.078201 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:53:32.078256 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:53:32.078310 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:53:32.078364 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x1
466 23:53:32.078418 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:53:32.078473 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 23:53:32.078527 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:53:32.078582 [RTC]rtc_get_frequency_meter,154: input=15, output=853
470 23:53:32.078637 [RTC]rtc_get_frequency_meter,154: input=7, output=723
471 23:53:32.078691 [RTC]rtc_get_frequency_meter,154: input=11, output=788
472 23:53:32.078746 [RTC]rtc_get_frequency_meter,154: input=13, output=822
473 23:53:32.078801 [RTC]rtc_get_frequency_meter,154: input=12, output=805
474 23:53:32.078855 [RTC]rtc_get_frequency_meter,154: input=11, output=789
475 23:53:32.078909 [RTC]rtc_get_frequency_meter,154: input=12, output=805
476 23:53:32.078965 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 23:53:32.079019 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 23:53:32.079268 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:53:32.079408 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 23:53:32.079542 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:53:32.079669 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 23:53:32.079801 ADC[4]: Raw value=904064 ID=7
483 23:53:32.079911 ADC[3]: Raw value=213546 ID=1
484 23:53:32.079970 RAM Code: 0x71
485 23:53:32.080027 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:53:32.080084 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:53:32.080141 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:53:32.080198 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:53:32.080253 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:53:32.080309 in-header: 03 07 00 00 08 00 00 00
491 23:53:32.080363 in-data: aa e4 47 04 13 02 00 00
492 23:53:32.080418 Chrome EC: UHEPI supported
493 23:53:32.080472 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:53:32.080527 in-header: 03 a9 00 00 08 00 00 00
495 23:53:32.080581 in-data: 84 60 60 08 00 00 00 00
496 23:53:32.080636 MRC: failed to locate region type 0.
497 23:53:32.080690 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:53:32.080745 DRAM-K: Running full calibration
499 23:53:32.080800 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:53:32.080855 header.status = 0x0
501 23:53:32.080909 header.version = 0x6 (expected: 0x6)
502 23:53:32.080964 header.size = 0xd00 (expected: 0xd00)
503 23:53:32.081018 header.flags = 0x0
504 23:53:32.081073 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:53:32.081128 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
506 23:53:32.081183 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:53:32.081237 dram_init: ddr_geometry: 2
508 23:53:32.081303 [EMI] MDL number = 2
509 23:53:32.081358 [EMI] Get MDL freq = 0
510 23:53:32.081412 dram_init: ddr_type: 0
511 23:53:32.081467 is_discrete_lpddr4: 1
512 23:53:32.081521 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:53:32.081576
514 23:53:32.081631
515 23:53:32.081685 [Bian_co] ETT version 0.0.0.1
516 23:53:32.081740 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:53:32.081794
518 23:53:32.081849 dramc_set_vcore_voltage set vcore to 650000
519 23:53:32.081903 Read voltage for 800, 4
520 23:53:32.081958 Vio18 = 0
521 23:53:32.082012 Vcore = 650000
522 23:53:32.082067 Vdram = 0
523 23:53:32.082122 Vddq = 0
524 23:53:32.082177 Vmddr = 0
525 23:53:32.082231 dram_init: config_dvfs: 1
526 23:53:32.082286 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:53:32.082341 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:53:32.082395 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 23:53:32.082450 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 23:53:32.082505 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 23:53:32.082560 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 23:53:32.082614 MEM_TYPE=3, freq_sel=18
533 23:53:32.082668 sv_algorithm_assistance_LP4_1600
534 23:53:32.082723 ============ PULL DRAM RESETB DOWN ============
535 23:53:32.082780 ========== PULL DRAM RESETB DOWN end =========
536 23:53:32.082834 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:53:32.082889 ===================================
538 23:53:32.082943 LPDDR4 DRAM CONFIGURATION
539 23:53:32.082998 ===================================
540 23:53:32.083053 EX_ROW_EN[0] = 0x0
541 23:53:32.083107 EX_ROW_EN[1] = 0x0
542 23:53:32.083161 LP4Y_EN = 0x0
543 23:53:32.083215 WORK_FSP = 0x0
544 23:53:32.083269 WL = 0x2
545 23:53:32.083323 RL = 0x2
546 23:53:32.083377 BL = 0x2
547 23:53:32.083431 RPST = 0x0
548 23:53:32.083484 RD_PRE = 0x0
549 23:53:32.083537 WR_PRE = 0x1
550 23:53:32.083591 WR_PST = 0x0
551 23:53:32.083645 DBI_WR = 0x0
552 23:53:32.083698 DBI_RD = 0x0
553 23:53:32.083752 OTF = 0x1
554 23:53:32.083806 ===================================
555 23:53:32.083861 ===================================
556 23:53:32.083914 ANA top config
557 23:53:32.083968 ===================================
558 23:53:32.084023 DLL_ASYNC_EN = 0
559 23:53:32.084077 ALL_SLAVE_EN = 1
560 23:53:32.084131 NEW_RANK_MODE = 1
561 23:53:32.084186 DLL_IDLE_MODE = 1
562 23:53:32.084240 LP45_APHY_COMB_EN = 1
563 23:53:32.084294 TX_ODT_DIS = 1
564 23:53:32.084348 NEW_8X_MODE = 1
565 23:53:32.084402 ===================================
566 23:53:32.084457 ===================================
567 23:53:32.084511 data_rate = 1600
568 23:53:32.084564 CKR = 1
569 23:53:32.084619 DQ_P2S_RATIO = 8
570 23:53:32.084673 ===================================
571 23:53:32.084728 CA_P2S_RATIO = 8
572 23:53:32.084782 DQ_CA_OPEN = 0
573 23:53:32.084836 DQ_SEMI_OPEN = 0
574 23:53:32.084891 CA_SEMI_OPEN = 0
575 23:53:32.084945 CA_FULL_RATE = 0
576 23:53:32.084998 DQ_CKDIV4_EN = 1
577 23:53:32.085053 CA_CKDIV4_EN = 1
578 23:53:32.085107 CA_PREDIV_EN = 0
579 23:53:32.085161 PH8_DLY = 0
580 23:53:32.085215 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:53:32.085276 DQ_AAMCK_DIV = 4
582 23:53:32.085333 CA_AAMCK_DIV = 4
583 23:53:32.085387 CA_ADMCK_DIV = 4
584 23:53:32.085441 DQ_TRACK_CA_EN = 0
585 23:53:32.085494 CA_PICK = 800
586 23:53:32.085548 CA_MCKIO = 800
587 23:53:32.085603 MCKIO_SEMI = 0
588 23:53:32.085657 PLL_FREQ = 3068
589 23:53:32.085711 DQ_UI_PI_RATIO = 32
590 23:53:32.085765 CA_UI_PI_RATIO = 0
591 23:53:32.085820 ===================================
592 23:53:32.085875 ===================================
593 23:53:32.085929 memory_type:LPDDR4
594 23:53:32.085983 GP_NUM : 10
595 23:53:32.086037 SRAM_EN : 1
596 23:53:32.086091 MD32_EN : 0
597 23:53:32.086146 ===================================
598 23:53:32.086413 [ANA_INIT] >>>>>>>>>>>>>>
599 23:53:32.086548 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:53:32.086700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:53:32.086830 ===================================
602 23:53:32.086957 data_rate = 1600,PCW = 0X7600
603 23:53:32.087055 ===================================
604 23:53:32.087114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:53:32.087171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:53:32.087227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:53:32.087283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:53:32.087356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:53:32.087411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:53:32.087467 [ANA_INIT] flow start
611 23:53:32.087522 [ANA_INIT] PLL >>>>>>>>
612 23:53:32.087590 [ANA_INIT] PLL <<<<<<<<
613 23:53:32.087643 [ANA_INIT] MIDPI >>>>>>>>
614 23:53:32.087696 [ANA_INIT] MIDPI <<<<<<<<
615 23:53:32.087749 [ANA_INIT] DLL >>>>>>>>
616 23:53:32.087802 [ANA_INIT] flow end
617 23:53:32.087855 ============ LP4 DIFF to SE enter ============
618 23:53:32.087909 ============ LP4 DIFF to SE exit ============
619 23:53:32.087963 [ANA_INIT] <<<<<<<<<<<<<
620 23:53:32.088016 [Flow] Enable top DCM control >>>>>
621 23:53:32.088069 [Flow] Enable top DCM control <<<<<
622 23:53:32.088122 Enable DLL master slave shuffle
623 23:53:32.088176 ==============================================================
624 23:53:32.088230 Gating Mode config
625 23:53:32.088283 ==============================================================
626 23:53:32.088337 Config description:
627 23:53:32.088401 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:53:32.088494 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:53:32.088557 SELPH_MODE 0: By rank 1: By Phase
630 23:53:32.088612 ==============================================================
631 23:53:32.088667 GAT_TRACK_EN = 1
632 23:53:32.088738 RX_GATING_MODE = 2
633 23:53:32.088806 RX_GATING_TRACK_MODE = 2
634 23:53:32.088860 SELPH_MODE = 1
635 23:53:32.088913 PICG_EARLY_EN = 1
636 23:53:32.088967 VALID_LAT_VALUE = 1
637 23:53:32.089020 ==============================================================
638 23:53:32.089074 Enter into Gating configuration >>>>
639 23:53:32.089127 Exit from Gating configuration <<<<
640 23:53:32.089181 Enter into DVFS_PRE_config >>>>>
641 23:53:32.089234 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:53:32.089334 Exit from DVFS_PRE_config <<<<<
643 23:53:32.089389 Enter into PICG configuration >>>>
644 23:53:32.089442 Exit from PICG configuration <<<<
645 23:53:32.089513 [RX_INPUT] configuration >>>>>
646 23:53:32.089567 [RX_INPUT] configuration <<<<<
647 23:53:32.089622 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:53:32.089677 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:53:32.089732 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:53:32.089801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:53:32.089855 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:53:32.089908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:53:32.089962 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:53:32.090015 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:53:32.090068 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:53:32.090121 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:53:32.090175 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:53:32.090228 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:53:32.090281 ===================================
660 23:53:32.090334 LPDDR4 DRAM CONFIGURATION
661 23:53:32.090387 ===================================
662 23:53:32.090441 EX_ROW_EN[0] = 0x0
663 23:53:32.090494 EX_ROW_EN[1] = 0x0
664 23:53:32.090547 LP4Y_EN = 0x0
665 23:53:32.090618 WORK_FSP = 0x0
666 23:53:32.090672 WL = 0x2
667 23:53:32.090726 RL = 0x2
668 23:53:32.090780 BL = 0x2
669 23:53:32.090847 RPST = 0x0
670 23:53:32.090900 RD_PRE = 0x0
671 23:53:32.090953 WR_PRE = 0x1
672 23:53:32.091006 WR_PST = 0x0
673 23:53:32.091058 DBI_WR = 0x0
674 23:53:32.091111 DBI_RD = 0x0
675 23:53:32.091163 OTF = 0x1
676 23:53:32.091217 ===================================
677 23:53:32.091270 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:53:32.091323 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:53:32.091377 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:53:32.091430 ===================================
681 23:53:32.091483 LPDDR4 DRAM CONFIGURATION
682 23:53:32.091536 ===================================
683 23:53:32.091589 EX_ROW_EN[0] = 0x10
684 23:53:32.091642 EX_ROW_EN[1] = 0x0
685 23:53:32.091695 LP4Y_EN = 0x0
686 23:53:32.091747 WORK_FSP = 0x0
687 23:53:32.091800 WL = 0x2
688 23:53:32.091853 RL = 0x2
689 23:53:32.091906 BL = 0x2
690 23:53:32.091959 RPST = 0x0
691 23:53:32.092012 RD_PRE = 0x0
692 23:53:32.092065 WR_PRE = 0x1
693 23:53:32.092118 WR_PST = 0x0
694 23:53:32.092171 DBI_WR = 0x0
695 23:53:32.092223 DBI_RD = 0x0
696 23:53:32.092293 OTF = 0x1
697 23:53:32.092348 ===================================
698 23:53:32.092435 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:53:32.092504 nWR fixed to 40
700 23:53:32.092577 [ModeRegInit_LP4] CH0 RK0
701 23:53:32.092664 [ModeRegInit_LP4] CH0 RK1
702 23:53:32.092749 [ModeRegInit_LP4] CH1 RK0
703 23:53:32.092803 [ModeRegInit_LP4] CH1 RK1
704 23:53:32.092857 match AC timing 13
705 23:53:32.092911 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:53:32.093163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:53:32.093339 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:53:32.093501 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:53:32.093663 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:53:32.093797 [EMI DOE] emi_dcm 0
711 23:53:32.093878 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:53:32.093937 ==
713 23:53:32.093994 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:53:32.094051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:53:32.094106 ==
716 23:53:32.094162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:53:32.094217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:53:32.094273 [CA 0] Center 37 (7~68) winsize 62
719 23:53:32.094328 [CA 1] Center 37 (7~68) winsize 62
720 23:53:32.094382 [CA 2] Center 34 (4~65) winsize 62
721 23:53:32.094437 [CA 3] Center 35 (4~66) winsize 63
722 23:53:32.094491 [CA 4] Center 34 (3~65) winsize 63
723 23:53:32.094546 [CA 5] Center 33 (3~64) winsize 62
724 23:53:32.094614
725 23:53:32.094668 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:53:32.094721
727 23:53:32.094774 [CATrainingPosCal] consider 1 rank data
728 23:53:32.094828 u2DelayCellTimex100 = 270/100 ps
729 23:53:32.094881 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 23:53:32.094934 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 23:53:32.094988 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 23:53:32.095041 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
733 23:53:32.095094 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 23:53:32.095147 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:53:32.095200
736 23:53:32.095253 CA PerBit enable=1, Macro0, CA PI delay=33
737 23:53:32.095307
738 23:53:32.095360 [CBTSetCACLKResult] CA Dly = 33
739 23:53:32.095413 CS Dly: 6 (0~37)
740 23:53:32.095466 ==
741 23:53:32.095520 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:53:32.095574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:53:32.095627 ==
744 23:53:32.095680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:53:32.095734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:53:32.095788 [CA 0] Center 38 (7~69) winsize 63
747 23:53:32.095841 [CA 1] Center 37 (7~68) winsize 62
748 23:53:32.095894 [CA 2] Center 35 (4~66) winsize 63
749 23:53:32.095947 [CA 3] Center 34 (4~65) winsize 62
750 23:53:32.096000 [CA 4] Center 34 (3~65) winsize 63
751 23:53:32.096053 [CA 5] Center 33 (3~64) winsize 62
752 23:53:32.096106
753 23:53:32.096160 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:53:32.096213
755 23:53:32.096266 [CATrainingPosCal] consider 2 rank data
756 23:53:32.096319 u2DelayCellTimex100 = 270/100 ps
757 23:53:32.096390 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 23:53:32.096445 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:53:32.096499 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 23:53:32.096566 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 23:53:32.096619 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
762 23:53:32.096672 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:53:32.096758
764 23:53:32.096811 CA PerBit enable=1, Macro0, CA PI delay=33
765 23:53:32.096865
766 23:53:32.096918 [CBTSetCACLKResult] CA Dly = 33
767 23:53:32.096971 CS Dly: 6 (0~38)
768 23:53:32.097024
769 23:53:32.097077 ----->DramcWriteLeveling(PI) begin...
770 23:53:32.097152 ==
771 23:53:32.097206 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:53:32.097267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:53:32.097357 ==
774 23:53:32.097412 Write leveling (Byte 0): 30 => 30
775 23:53:32.097466 Write leveling (Byte 1): 25 => 25
776 23:53:32.097520 DramcWriteLeveling(PI) end<-----
777 23:53:32.097575
778 23:53:32.097629 ==
779 23:53:32.097697 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:53:32.097750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:53:32.097804 ==
782 23:53:32.097858 [Gating] SW mode calibration
783 23:53:32.097912 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:53:32.097966 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:53:32.098021 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:53:32.098075 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:53:32.098145 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
788 23:53:32.098215 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:53:32.098269 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:53:32.098322 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:53:32.098375 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:53:32.098429 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:53:32.098482 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:53:32.098535 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:53:32.098588 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:53:32.098641 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:53:32.098711 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:53:32.098780 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:53:32.098833 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:53:32.098887 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:53:32.098940 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:53:32.098994 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
803 23:53:32.099046 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
804 23:53:32.099100 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:53:32.099153 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:53:32.099206 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:53:32.099259 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:53:32.099313 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:53:32.099366 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:53:32.099419 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:53:32.099472 0 9 8 | B1->B0 | 2322 3333 | 1 0 | (1 1) (0 0)
812 23:53:32.099524 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
813 23:53:32.099577 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:53:32.099842 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:53:32.099988 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:53:32.100118 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:53:32.100270 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:53:32.100452 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
819 23:53:32.100599 0 10 8 | B1->B0 | 3131 2525 | 1 0 | (1 1) (0 0)
820 23:53:32.100660 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
821 23:53:32.100717 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:53:32.100773 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:53:32.100834 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:53:32.100899 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:53:32.100966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:53:32.101030 0 11 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
827 23:53:32.101094 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
828 23:53:32.101156 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
829 23:53:32.101219 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 23:53:32.101294 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:53:32.101357 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:53:32.101415 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:53:32.101472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:53:32.101529 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 23:53:32.101584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 23:53:32.101639 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 23:53:32.101694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:53:32.101749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:53:32.101804 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:53:32.101859 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:53:32.101914 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:53:32.101969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:53:32.102024 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:53:32.102078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:53:32.102133 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:53:32.102188 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:53:32.102242 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:53:32.102297 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:53:32.102351 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:53:32.102405 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:53:32.102459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 23:53:32.102514 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 23:53:32.102568 Total UI for P1: 0, mck2ui 16
854 23:53:32.102623 best dqsien dly found for B0: ( 0, 14, 8)
855 23:53:32.102678 Total UI for P1: 0, mck2ui 16
856 23:53:32.102732 best dqsien dly found for B1: ( 0, 14, 10)
857 23:53:32.102787 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 23:53:32.102841 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 23:53:32.102896
860 23:53:32.102954 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 23:53:32.103009 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 23:53:32.103064 [Gating] SW calibration Done
863 23:53:32.103118 ==
864 23:53:32.103172 Dram Type= 6, Freq= 0, CH_0, rank 0
865 23:53:32.103227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 23:53:32.103296 ==
867 23:53:32.103382 RX Vref Scan: 0
868 23:53:32.103435
869 23:53:32.103489 RX Vref 0 -> 0, step: 1
870 23:53:32.103541
871 23:53:32.103611 RX Delay -130 -> 252, step: 16
872 23:53:32.103679 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 23:53:32.103733 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 23:53:32.103815 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 23:53:32.103884 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 23:53:32.103938 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 23:53:32.103993 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 23:53:32.104048 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 23:53:32.104103 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 23:53:32.104158 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
881 23:53:32.104212 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 23:53:32.104266 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 23:53:32.104351 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 23:53:32.104436 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 23:53:32.104504 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 23:53:32.104557 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 23:53:32.104610 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 23:53:32.104664 ==
889 23:53:32.104718 Dram Type= 6, Freq= 0, CH_0, rank 0
890 23:53:32.104772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 23:53:32.104826 ==
892 23:53:32.104897 DQS Delay:
893 23:53:32.104967 DQS0 = 0, DQS1 = 0
894 23:53:32.105026 DQM Delay:
895 23:53:32.105080 DQM0 = 88, DQM1 = 75
896 23:53:32.105134 DQ Delay:
897 23:53:32.105187 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 23:53:32.105241 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 23:53:32.105346 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
900 23:53:32.105400 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 23:53:32.105471
902 23:53:32.105540
903 23:53:32.105592 ==
904 23:53:32.105646 Dram Type= 6, Freq= 0, CH_0, rank 0
905 23:53:32.105700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 23:53:32.105754 ==
907 23:53:32.105807
908 23:53:32.105861
909 23:53:32.105914 TX Vref Scan disable
910 23:53:32.105967 == TX Byte 0 ==
911 23:53:32.106021 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 23:53:32.106074 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 23:53:32.106128 == TX Byte 1 ==
914 23:53:32.106181 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
915 23:53:32.106235 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
916 23:53:32.106288 ==
917 23:53:32.106341 Dram Type= 6, Freq= 0, CH_0, rank 0
918 23:53:32.106395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 23:53:32.106449 ==
920 23:53:32.106502 TX Vref=22, minBit 5, minWin=26, winSum=437
921 23:53:32.106556 TX Vref=24, minBit 1, minWin=26, winSum=438
922 23:53:32.106807 TX Vref=26, minBit 0, minWin=27, winSum=444
923 23:53:32.106944 TX Vref=28, minBit 1, minWin=27, winSum=446
924 23:53:32.107077 TX Vref=30, minBit 1, minWin=28, winSum=453
925 23:53:32.107228 TX Vref=32, minBit 2, minWin=27, winSum=449
926 23:53:32.107360 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 30
927 23:53:32.107472
928 23:53:32.107531 Final TX Range 1 Vref 30
929 23:53:32.107588
930 23:53:32.107643 ==
931 23:53:32.107697 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:53:32.107751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:53:32.107806 ==
934 23:53:32.107877
935 23:53:32.107945
936 23:53:32.107998 TX Vref Scan disable
937 23:53:32.108052 == TX Byte 0 ==
938 23:53:32.108105 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 23:53:32.108159 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 23:53:32.108212 == TX Byte 1 ==
941 23:53:32.108266 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
942 23:53:32.108319 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
943 23:53:32.108394
944 23:53:32.108463 [DATLAT]
945 23:53:32.108533 Freq=800, CH0 RK0
946 23:53:32.108602
947 23:53:32.108673 DATLAT Default: 0xa
948 23:53:32.108727 0, 0xFFFF, sum = 0
949 23:53:32.108813 1, 0xFFFF, sum = 0
950 23:53:32.108899 2, 0xFFFF, sum = 0
951 23:53:32.108985 3, 0xFFFF, sum = 0
952 23:53:32.109040 4, 0xFFFF, sum = 0
953 23:53:32.109128 5, 0xFFFF, sum = 0
954 23:53:32.109183 6, 0xFFFF, sum = 0
955 23:53:32.109238 7, 0xFFFF, sum = 0
956 23:53:32.109323 8, 0xFFFF, sum = 0
957 23:53:32.109410 9, 0x0, sum = 1
958 23:53:32.109470 10, 0x0, sum = 2
959 23:53:32.109526 11, 0x0, sum = 3
960 23:53:32.109581 12, 0x0, sum = 4
961 23:53:32.109636 best_step = 10
962 23:53:32.109690
963 23:53:32.109745 ==
964 23:53:32.109800 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:53:32.109854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 23:53:32.109909 ==
967 23:53:32.109963 RX Vref Scan: 1
968 23:53:32.110018
969 23:53:32.110071 Set Vref Range= 32 -> 127
970 23:53:32.110126
971 23:53:32.110179 RX Vref 32 -> 127, step: 1
972 23:53:32.110234
973 23:53:32.110288 RX Delay -111 -> 252, step: 8
974 23:53:32.110343
975 23:53:32.110396 Set Vref, RX VrefLevel [Byte0]: 32
976 23:53:32.110450 [Byte1]: 32
977 23:53:32.110505
978 23:53:32.110559 Set Vref, RX VrefLevel [Byte0]: 33
979 23:53:32.110613 [Byte1]: 33
980 23:53:32.110668
981 23:53:32.110721 Set Vref, RX VrefLevel [Byte0]: 34
982 23:53:32.110776 [Byte1]: 34
983 23:53:32.110830
984 23:53:32.110884 Set Vref, RX VrefLevel [Byte0]: 35
985 23:53:32.110938 [Byte1]: 35
986 23:53:32.110993
987 23:53:32.111050 Set Vref, RX VrefLevel [Byte0]: 36
988 23:53:32.111113 [Byte1]: 36
989 23:53:32.111175
990 23:53:32.111237 Set Vref, RX VrefLevel [Byte0]: 37
991 23:53:32.111299 [Byte1]: 37
992 23:53:32.111361
993 23:53:32.111422 Set Vref, RX VrefLevel [Byte0]: 38
994 23:53:32.111484 [Byte1]: 38
995 23:53:32.111545
996 23:53:32.111605 Set Vref, RX VrefLevel [Byte0]: 39
997 23:53:32.111666 [Byte1]: 39
998 23:53:32.111727
999 23:53:32.111786 Set Vref, RX VrefLevel [Byte0]: 40
1000 23:53:32.111848 [Byte1]: 40
1001 23:53:32.111908
1002 23:53:32.111968 Set Vref, RX VrefLevel [Byte0]: 41
1003 23:53:32.112028 [Byte1]: 41
1004 23:53:32.112088
1005 23:53:32.112148 Set Vref, RX VrefLevel [Byte0]: 42
1006 23:53:32.112208 [Byte1]: 42
1007 23:53:32.112268
1008 23:53:32.112328 Set Vref, RX VrefLevel [Byte0]: 43
1009 23:53:32.112389 [Byte1]: 43
1010 23:53:32.112450
1011 23:53:32.112510 Set Vref, RX VrefLevel [Byte0]: 44
1012 23:53:32.112571 [Byte1]: 44
1013 23:53:32.112631
1014 23:53:32.112691 Set Vref, RX VrefLevel [Byte0]: 45
1015 23:53:32.112751 [Byte1]: 45
1016 23:53:32.112812
1017 23:53:32.112873 Set Vref, RX VrefLevel [Byte0]: 46
1018 23:53:32.112933 [Byte1]: 46
1019 23:53:32.112993
1020 23:53:32.113053 Set Vref, RX VrefLevel [Byte0]: 47
1021 23:53:32.113123 [Byte1]: 47
1022 23:53:32.113215
1023 23:53:32.113298 Set Vref, RX VrefLevel [Byte0]: 48
1024 23:53:32.113357 [Byte1]: 48
1025 23:53:32.113419
1026 23:53:32.113477 Set Vref, RX VrefLevel [Byte0]: 49
1027 23:53:32.113533 [Byte1]: 49
1028 23:53:32.113589
1029 23:53:32.113643 Set Vref, RX VrefLevel [Byte0]: 50
1030 23:53:32.113698 [Byte1]: 50
1031 23:53:32.113752
1032 23:53:32.113806 Set Vref, RX VrefLevel [Byte0]: 51
1033 23:53:32.113860 [Byte1]: 51
1034 23:53:32.113914
1035 23:53:32.113967 Set Vref, RX VrefLevel [Byte0]: 52
1036 23:53:32.114021 [Byte1]: 52
1037 23:53:32.114075
1038 23:53:32.114129 Set Vref, RX VrefLevel [Byte0]: 53
1039 23:53:32.114183 [Byte1]: 53
1040 23:53:32.114237
1041 23:53:32.114291 Set Vref, RX VrefLevel [Byte0]: 54
1042 23:53:32.114375 [Byte1]: 54
1043 23:53:32.114429
1044 23:53:32.114483 Set Vref, RX VrefLevel [Byte0]: 55
1045 23:53:32.114537 [Byte1]: 55
1046 23:53:32.114592
1047 23:53:32.114675 Set Vref, RX VrefLevel [Byte0]: 56
1048 23:53:32.114743 [Byte1]: 56
1049 23:53:32.114795
1050 23:53:32.114847 Set Vref, RX VrefLevel [Byte0]: 57
1051 23:53:32.114898 [Byte1]: 57
1052 23:53:32.114950
1053 23:53:32.115002 Set Vref, RX VrefLevel [Byte0]: 58
1054 23:53:32.115055 [Byte1]: 58
1055 23:53:32.115108
1056 23:53:32.115160 Set Vref, RX VrefLevel [Byte0]: 59
1057 23:53:32.115212 [Byte1]: 59
1058 23:53:32.115295
1059 23:53:32.115347 Set Vref, RX VrefLevel [Byte0]: 60
1060 23:53:32.115400 [Byte1]: 60
1061 23:53:32.115452
1062 23:53:32.115504 Set Vref, RX VrefLevel [Byte0]: 61
1063 23:53:32.115556 [Byte1]: 61
1064 23:53:32.115608
1065 23:53:32.115660 Set Vref, RX VrefLevel [Byte0]: 62
1066 23:53:32.115712 [Byte1]: 62
1067 23:53:32.115789
1068 23:53:32.115856 Set Vref, RX VrefLevel [Byte0]: 63
1069 23:53:32.115908 [Byte1]: 63
1070 23:53:32.115961
1071 23:53:32.116013 Set Vref, RX VrefLevel [Byte0]: 64
1072 23:53:32.116065 [Byte1]: 64
1073 23:53:32.116118
1074 23:53:32.116169 Set Vref, RX VrefLevel [Byte0]: 65
1075 23:53:32.116222 [Byte1]: 65
1076 23:53:32.116274
1077 23:53:32.116356 Set Vref, RX VrefLevel [Byte0]: 66
1078 23:53:32.116408 [Byte1]: 66
1079 23:53:32.116460
1080 23:53:32.116512 Set Vref, RX VrefLevel [Byte0]: 67
1081 23:53:32.116565 [Byte1]: 67
1082 23:53:32.116641
1083 23:53:32.116708 Set Vref, RX VrefLevel [Byte0]: 68
1084 23:53:32.116761 [Byte1]: 68
1085 23:53:32.116813
1086 23:53:32.116880 Set Vref, RX VrefLevel [Byte0]: 69
1087 23:53:32.116947 [Byte1]: 69
1088 23:53:32.116999
1089 23:53:32.117050 Set Vref, RX VrefLevel [Byte0]: 70
1090 23:53:32.117321 [Byte1]: 70
1091 23:53:32.117483
1092 23:53:32.117644 Set Vref, RX VrefLevel [Byte0]: 71
1093 23:53:32.117820 [Byte1]: 71
1094 23:53:32.117994
1095 23:53:32.118166 Set Vref, RX VrefLevel [Byte0]: 72
1096 23:53:32.118260 [Byte1]: 72
1097 23:53:32.118317
1098 23:53:32.118372 Set Vref, RX VrefLevel [Byte0]: 73
1099 23:53:32.118428 [Byte1]: 73
1100 23:53:32.118483
1101 23:53:32.118537 Set Vref, RX VrefLevel [Byte0]: 74
1102 23:53:32.118592 [Byte1]: 74
1103 23:53:32.118646
1104 23:53:32.118700 Set Vref, RX VrefLevel [Byte0]: 75
1105 23:53:32.118767 [Byte1]: 75
1106 23:53:32.118820
1107 23:53:32.118873 Set Vref, RX VrefLevel [Byte0]: 76
1108 23:53:32.118940 [Byte1]: 76
1109 23:53:32.119008
1110 23:53:32.119060 Final RX Vref Byte 0 = 58 to rank0
1111 23:53:32.119114 Final RX Vref Byte 1 = 59 to rank0
1112 23:53:32.119167 Final RX Vref Byte 0 = 58 to rank1
1113 23:53:32.119235 Final RX Vref Byte 1 = 59 to rank1==
1114 23:53:32.119302 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 23:53:32.119355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 23:53:32.119409 ==
1117 23:53:32.119478 DQS Delay:
1118 23:53:32.119544 DQS0 = 0, DQS1 = 0
1119 23:53:32.119596 DQM Delay:
1120 23:53:32.119649 DQM0 = 88, DQM1 = 75
1121 23:53:32.119718 DQ Delay:
1122 23:53:32.119785 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1123 23:53:32.119837 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1124 23:53:32.119890 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1125 23:53:32.119957 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1126 23:53:32.120011
1127 23:53:32.120064
1128 23:53:32.120117 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1129 23:53:32.120173 CH0 RK0: MR19=606, MR18=2D27
1130 23:53:32.120227 CH0_RK0: MR19=0x606, MR18=0x2D27, DQSOSC=398, MR23=63, INC=93, DEC=62
1131 23:53:32.120282
1132 23:53:32.120335 ----->DramcWriteLeveling(PI) begin...
1133 23:53:32.120391 ==
1134 23:53:32.120458 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 23:53:32.120512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 23:53:32.120565 ==
1137 23:53:32.120618 Write leveling (Byte 0): 30 => 30
1138 23:53:32.120671 Write leveling (Byte 1): 29 => 29
1139 23:53:32.120724 DramcWriteLeveling(PI) end<-----
1140 23:53:32.120777
1141 23:53:32.120829 ==
1142 23:53:32.120881 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:53:32.120953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:53:32.121020 ==
1145 23:53:32.121073 [Gating] SW mode calibration
1146 23:53:32.121126 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 23:53:32.121195 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 23:53:32.121249 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 23:53:32.121333 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1150 23:53:32.121387 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 23:53:32.121473 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 23:53:32.121525 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 23:53:32.121578 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:53:32.121632 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:53:32.121702 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:53:32.121769 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:53:32.121822 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:53:32.121875 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:53:32.121945 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:53:32.122014 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:53:32.122067 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:53:32.122120 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:53:32.122189 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:53:32.122257 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:53:32.122310 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1166 23:53:32.122363 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:53:32.122415 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:53:32.122501 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:53:32.122553 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:53:32.122607 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:53:32.122659 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:53:32.122712 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:53:32.122797 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:53:32.122850 0 9 8 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
1175 23:53:32.122903 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1176 23:53:32.122956 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 23:53:32.123024 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:53:32.123091 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:53:32.123144 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:53:32.123197 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:53:32.123250 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
1182 23:53:32.123333 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1183 23:53:32.123387 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:53:32.123440 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:53:32.123492 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:53:32.123576 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:53:32.123629 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:53:32.123681 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:53:32.123734 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1190 23:53:32.123803 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1191 23:53:32.123857 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 23:53:32.123911 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:53:32.123965 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:53:32.124019 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:53:32.124087 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:53:32.124352 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:53:32.124481 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:53:32.124669 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 23:53:32.124812 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:53:32.124942 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:53:32.125078 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:53:32.125139 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:53:32.125195 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:53:32.125250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:53:32.125330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:53:32.125384 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:53:32.125438 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:53:32.125491 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:53:32.125544 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:53:32.125630 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:53:32.125683 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:53:32.125736 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:53:32.125788 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 23:53:32.125857 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 23:53:32.125923 Total UI for P1: 0, mck2ui 16
1216 23:53:32.125977 best dqsien dly found for B0: ( 0, 14, 4)
1217 23:53:32.126031 Total UI for P1: 0, mck2ui 16
1218 23:53:32.126099 best dqsien dly found for B1: ( 0, 14, 6)
1219 23:53:32.126167 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1220 23:53:32.126221 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1221 23:53:32.126273
1222 23:53:32.126326 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1223 23:53:32.126410 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 23:53:32.126463 [Gating] SW calibration Done
1225 23:53:32.126515 ==
1226 23:53:32.126569 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 23:53:32.126622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 23:53:32.126704 ==
1229 23:53:32.126757 RX Vref Scan: 0
1230 23:53:32.126810
1231 23:53:32.126862 RX Vref 0 -> 0, step: 1
1232 23:53:32.126929
1233 23:53:32.127011 RX Delay -130 -> 252, step: 16
1234 23:53:32.127078 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1235 23:53:32.127132 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1236 23:53:32.127185 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1237 23:53:32.127238 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1238 23:53:32.127291 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1239 23:53:32.127344 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1240 23:53:32.127397 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1241 23:53:32.127450 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1242 23:53:32.127502 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1243 23:53:32.127555 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1244 23:53:32.127607 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1245 23:53:32.127660 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1246 23:53:32.127743 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1247 23:53:32.127797 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1248 23:53:32.127850 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1249 23:53:32.127918 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1250 23:53:32.127972 ==
1251 23:53:32.128026 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 23:53:32.128081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 23:53:32.128135 ==
1254 23:53:32.128190 DQS Delay:
1255 23:53:32.128243 DQS0 = 0, DQS1 = 0
1256 23:53:32.128297 DQM Delay:
1257 23:53:32.128351 DQM0 = 89, DQM1 = 77
1258 23:53:32.128405 DQ Delay:
1259 23:53:32.128473 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1260 23:53:32.128526 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1261 23:53:32.128578 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
1262 23:53:32.128631 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1263 23:53:32.128712
1264 23:53:32.128764
1265 23:53:32.128816 ==
1266 23:53:32.128868 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 23:53:32.128951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 23:53:32.129004 ==
1269 23:53:32.129057
1270 23:53:32.129109
1271 23:53:32.129176 TX Vref Scan disable
1272 23:53:32.129230 == TX Byte 0 ==
1273 23:53:32.129303 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1274 23:53:32.129357 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1275 23:53:32.129410 == TX Byte 1 ==
1276 23:53:32.129463 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1277 23:53:32.129516 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1278 23:53:32.129568 ==
1279 23:53:32.129621 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 23:53:32.129674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 23:53:32.129763 ==
1282 23:53:32.129815 TX Vref=22, minBit 0, minWin=27, winSum=442
1283 23:53:32.129869 TX Vref=24, minBit 0, minWin=27, winSum=443
1284 23:53:32.129922 TX Vref=26, minBit 1, minWin=27, winSum=444
1285 23:53:32.129975 TX Vref=28, minBit 7, minWin=27, winSum=451
1286 23:53:32.130029 TX Vref=30, minBit 2, minWin=27, winSum=449
1287 23:53:32.130082 TX Vref=32, minBit 1, minWin=27, winSum=447
1288 23:53:32.130135 [TxChooseVref] Worse bit 7, Min win 27, Win sum 451, Final Vref 28
1289 23:53:32.130188
1290 23:53:32.130241 Final TX Range 1 Vref 28
1291 23:53:32.130294
1292 23:53:32.130346 ==
1293 23:53:32.130399 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 23:53:32.130452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 23:53:32.130504 ==
1296 23:53:32.130556
1297 23:53:32.130608
1298 23:53:32.130660 TX Vref Scan disable
1299 23:53:32.130712 == TX Byte 0 ==
1300 23:53:32.130833 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1301 23:53:32.130886 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1302 23:53:32.130938 == TX Byte 1 ==
1303 23:53:32.130990 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1304 23:53:32.131042 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1305 23:53:32.131094
1306 23:53:32.131145 [DATLAT]
1307 23:53:32.131197 Freq=800, CH0 RK1
1308 23:53:32.131249
1309 23:53:32.131301 DATLAT Default: 0xa
1310 23:53:32.131353 0, 0xFFFF, sum = 0
1311 23:53:32.131421 1, 0xFFFF, sum = 0
1312 23:53:32.131490 2, 0xFFFF, sum = 0
1313 23:53:32.131544 3, 0xFFFF, sum = 0
1314 23:53:32.131597 4, 0xFFFF, sum = 0
1315 23:53:32.131650 5, 0xFFFF, sum = 0
1316 23:53:32.131703 6, 0xFFFF, sum = 0
1317 23:53:32.131756 7, 0xFFFF, sum = 0
1318 23:53:32.131809 8, 0xFFFF, sum = 0
1319 23:53:32.131862 9, 0x0, sum = 1
1320 23:53:32.131915 10, 0x0, sum = 2
1321 23:53:32.131968 11, 0x0, sum = 3
1322 23:53:32.132022 12, 0x0, sum = 4
1323 23:53:32.132075 best_step = 10
1324 23:53:32.132127
1325 23:53:32.132211 ==
1326 23:53:32.132263 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 23:53:32.132516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 23:53:32.132670 ==
1329 23:53:32.132841 RX Vref Scan: 0
1330 23:53:32.132967
1331 23:53:32.133111 RX Vref 0 -> 0, step: 1
1332 23:53:32.133213
1333 23:53:32.133310 RX Delay -111 -> 252, step: 8
1334 23:53:32.133367 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1335 23:53:32.133422 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1336 23:53:32.133476 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1337 23:53:32.133529 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1338 23:53:32.133583 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1339 23:53:32.133635 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1340 23:53:32.133738 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1341 23:53:32.133804 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1342 23:53:32.133856 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1343 23:53:32.133909 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1344 23:53:32.133962 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1345 23:53:32.134014 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1346 23:53:32.134066 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1347 23:53:32.134136 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1348 23:53:32.134204 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1349 23:53:32.134256 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1350 23:53:32.134308 ==
1351 23:53:32.134359 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 23:53:32.134444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 23:53:32.134497 ==
1354 23:53:32.134549 DQS Delay:
1355 23:53:32.134600 DQS0 = 0, DQS1 = 0
1356 23:53:32.134653 DQM Delay:
1357 23:53:32.134705 DQM0 = 86, DQM1 = 76
1358 23:53:32.134794 DQ Delay:
1359 23:53:32.134846 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1360 23:53:32.134898 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1361 23:53:32.134955 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1362 23:53:32.135008 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1363 23:53:32.135060
1364 23:53:32.135111
1365 23:53:32.135208 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1366 23:53:32.135276 CH0 RK1: MR19=606, MR18=2E2B
1367 23:53:32.135329 CH0_RK1: MR19=0x606, MR18=0x2E2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1368 23:53:32.135381 [RxdqsGatingPostProcess] freq 800
1369 23:53:32.135433 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1370 23:53:32.135486 Pre-setting of DQS Precalculation
1371 23:53:32.135538 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1372 23:53:32.135590 ==
1373 23:53:32.135642 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 23:53:32.135694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 23:53:32.135784 ==
1376 23:53:32.135867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1377 23:53:32.135919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1378 23:53:32.135972 [CA 0] Center 37 (6~68) winsize 63
1379 23:53:32.136024 [CA 1] Center 37 (6~68) winsize 63
1380 23:53:32.136076 [CA 2] Center 35 (5~65) winsize 61
1381 23:53:32.136127 [CA 3] Center 34 (4~65) winsize 62
1382 23:53:32.136179 [CA 4] Center 34 (4~65) winsize 62
1383 23:53:32.136231 [CA 5] Center 33 (3~64) winsize 62
1384 23:53:32.136283
1385 23:53:32.136334 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1386 23:53:32.136386
1387 23:53:32.136438 [CATrainingPosCal] consider 1 rank data
1388 23:53:32.136490 u2DelayCellTimex100 = 270/100 ps
1389 23:53:32.136541 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1390 23:53:32.136594 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1391 23:53:32.136646 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1392 23:53:32.136698 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 23:53:32.136750 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 23:53:32.136802 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 23:53:32.136898
1396 23:53:32.136964 CA PerBit enable=1, Macro0, CA PI delay=33
1397 23:53:32.137016
1398 23:53:32.137067 [CBTSetCACLKResult] CA Dly = 33
1399 23:53:32.137134 CS Dly: 4 (0~35)
1400 23:53:32.137223 ==
1401 23:53:32.137335 Dram Type= 6, Freq= 0, CH_1, rank 1
1402 23:53:32.137452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 23:53:32.137508 ==
1404 23:53:32.137576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 23:53:32.137630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 23:53:32.137684 [CA 0] Center 36 (6~67) winsize 62
1407 23:53:32.137738 [CA 1] Center 37 (6~68) winsize 63
1408 23:53:32.137792 [CA 2] Center 34 (4~65) winsize 62
1409 23:53:32.137846 [CA 3] Center 34 (3~65) winsize 63
1410 23:53:32.137913 [CA 4] Center 34 (4~65) winsize 62
1411 23:53:32.137965 [CA 5] Center 34 (3~65) winsize 63
1412 23:53:32.138017
1413 23:53:32.138069 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1414 23:53:32.138164
1415 23:53:32.138230 [CATrainingPosCal] consider 2 rank data
1416 23:53:32.138284 u2DelayCellTimex100 = 270/100 ps
1417 23:53:32.138336 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1418 23:53:32.138389 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1419 23:53:32.138441 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1420 23:53:32.138493 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1421 23:53:32.138545 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1422 23:53:32.138597 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 23:53:32.138649
1424 23:53:32.138701 CA PerBit enable=1, Macro0, CA PI delay=33
1425 23:53:32.138753
1426 23:53:32.138806 [CBTSetCACLKResult] CA Dly = 33
1427 23:53:32.138858 CS Dly: 5 (0~37)
1428 23:53:32.138909
1429 23:53:32.138961 ----->DramcWriteLeveling(PI) begin...
1430 23:53:32.139050 ==
1431 23:53:32.139102 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 23:53:32.139154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 23:53:32.139206 ==
1434 23:53:32.139258 Write leveling (Byte 0): 28 => 28
1435 23:53:32.139311 Write leveling (Byte 1): 28 => 28
1436 23:53:32.139363 DramcWriteLeveling(PI) end<-----
1437 23:53:32.139415
1438 23:53:32.139466 ==
1439 23:53:32.139518 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 23:53:32.139608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 23:53:32.139660 ==
1442 23:53:32.139712 [Gating] SW mode calibration
1443 23:53:32.139764 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1444 23:53:32.139817 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1445 23:53:32.139907 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 23:53:32.139960 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1447 23:53:32.140013 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1448 23:53:32.140265 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 23:53:32.140325 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 23:53:32.140410 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:53:32.140463 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:53:32.140515 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:53:32.140567 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:53:32.140620 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:53:32.140695 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:53:32.140792 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:53:32.140859 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:53:32.140940 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:53:32.141022 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:53:32.141135 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:53:32.141219 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:53:32.141313 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1463 23:53:32.141367 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1464 23:53:32.141420 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:53:32.141503 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:53:32.141555 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:53:32.141608 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:53:32.141660 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:53:32.141729 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:53:32.141809 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1471 23:53:32.141877 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1472 23:53:32.141928 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 23:53:32.142010 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 23:53:32.142077 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 23:53:32.142143 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:53:32.142195 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:53:32.142277 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1478 23:53:32.142329 0 10 4 | B1->B0 | 3333 3131 | 1 0 | (1 0) (1 0)
1479 23:53:32.142381 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1480 23:53:32.142434 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:53:32.142516 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:53:32.142568 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:53:32.142620 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:53:32.142673 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:53:32.142741 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:53:32.142808 0 11 4 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
1487 23:53:32.142861 0 11 8 | B1->B0 | 3d3d 4545 | 0 1 | (0 0) (0 0)
1488 23:53:32.142914 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 23:53:32.142966 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 23:53:32.143047 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:53:32.143098 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:53:32.143150 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:53:32.143202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:53:32.143284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1495 23:53:32.143336 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1496 23:53:32.143388 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 23:53:32.143439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 23:53:32.143506 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:53:32.143574 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:53:32.143626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:53:32.143678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:53:32.143730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:53:32.143812 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:53:32.143865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:53:32.143917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:53:32.143969 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:53:32.144052 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:53:32.144105 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:53:32.144157 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1510 23:53:32.144209 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1511 23:53:32.144277 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1512 23:53:32.144359 Total UI for P1: 0, mck2ui 16
1513 23:53:32.144414 best dqsien dly found for B0: ( 0, 14, 2)
1514 23:53:32.144471 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 23:53:32.144532 Total UI for P1: 0, mck2ui 16
1516 23:53:32.144586 best dqsien dly found for B1: ( 0, 14, 8)
1517 23:53:32.144640 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1518 23:53:32.144708 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1519 23:53:32.144774
1520 23:53:32.144858 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1521 23:53:32.144926 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1522 23:53:32.144978 [Gating] SW calibration Done
1523 23:53:32.145029 ==
1524 23:53:32.145081 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 23:53:32.145133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 23:53:32.145186 ==
1527 23:53:32.145253 RX Vref Scan: 0
1528 23:53:32.145327
1529 23:53:32.145379 RX Vref 0 -> 0, step: 1
1530 23:53:32.145431
1531 23:53:32.145504 RX Delay -130 -> 252, step: 16
1532 23:53:32.145571 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1533 23:53:32.145623 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1534 23:53:32.145675 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1535 23:53:32.145727 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1536 23:53:32.145779 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1537 23:53:32.145831 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1538 23:53:32.146114 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1539 23:53:32.146242 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1540 23:53:32.146371 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1541 23:53:32.146498 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1542 23:53:32.146646 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1543 23:53:32.146785 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1544 23:53:32.146937 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1545 23:53:32.147078 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1546 23:53:32.147244 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1547 23:53:32.147387 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1548 23:53:32.147462 ==
1549 23:53:32.147518 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 23:53:32.147574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 23:53:32.147629 ==
1552 23:53:32.147696 DQS Delay:
1553 23:53:32.147748 DQS0 = 0, DQS1 = 0
1554 23:53:32.147800 DQM Delay:
1555 23:53:32.147852 DQM0 = 88, DQM1 = 80
1556 23:53:32.147905 DQ Delay:
1557 23:53:32.147957 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1558 23:53:32.148009 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1559 23:53:32.148061 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1560 23:53:32.148114 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 23:53:32.148166
1562 23:53:32.148218
1563 23:53:32.148269 ==
1564 23:53:32.148321 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 23:53:32.148374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 23:53:32.148427 ==
1567 23:53:32.148478
1568 23:53:32.148530
1569 23:53:32.148581 TX Vref Scan disable
1570 23:53:32.148633 == TX Byte 0 ==
1571 23:53:32.148685 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1572 23:53:32.148737 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1573 23:53:32.148789 == TX Byte 1 ==
1574 23:53:32.148841 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 23:53:32.148893 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 23:53:32.148959 ==
1577 23:53:32.149046 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 23:53:32.149101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 23:53:32.149156 ==
1580 23:53:32.149209 TX Vref=22, minBit 5, minWin=26, winSum=442
1581 23:53:32.149273 TX Vref=24, minBit 1, minWin=27, winSum=448
1582 23:53:32.149360 TX Vref=26, minBit 1, minWin=27, winSum=453
1583 23:53:32.149415 TX Vref=28, minBit 1, minWin=27, winSum=453
1584 23:53:32.149482 TX Vref=30, minBit 6, minWin=27, winSum=454
1585 23:53:32.149535 TX Vref=32, minBit 0, minWin=27, winSum=449
1586 23:53:32.149588 [TxChooseVref] Worse bit 6, Min win 27, Win sum 454, Final Vref 30
1587 23:53:32.149641
1588 23:53:32.149692 Final TX Range 1 Vref 30
1589 23:53:32.149745
1590 23:53:32.149797 ==
1591 23:53:32.149849 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 23:53:32.149901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 23:53:32.149953 ==
1594 23:53:32.150005
1595 23:53:32.150057
1596 23:53:32.150109 TX Vref Scan disable
1597 23:53:32.150161 == TX Byte 0 ==
1598 23:53:32.150213 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 23:53:32.150265 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 23:53:32.150318 == TX Byte 1 ==
1601 23:53:32.150369 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 23:53:32.150422 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 23:53:32.150475
1604 23:53:32.150526 [DATLAT]
1605 23:53:32.150577 Freq=800, CH1 RK0
1606 23:53:32.150629
1607 23:53:32.150681 DATLAT Default: 0xa
1608 23:53:32.150761 0, 0xFFFF, sum = 0
1609 23:53:32.150830 1, 0xFFFF, sum = 0
1610 23:53:32.150898 2, 0xFFFF, sum = 0
1611 23:53:32.150951 3, 0xFFFF, sum = 0
1612 23:53:32.151034 4, 0xFFFF, sum = 0
1613 23:53:32.151116 5, 0xFFFF, sum = 0
1614 23:53:32.151168 6, 0xFFFF, sum = 0
1615 23:53:32.151221 7, 0xFFFF, sum = 0
1616 23:53:32.151274 8, 0xFFFF, sum = 0
1617 23:53:32.151327 9, 0x0, sum = 1
1618 23:53:32.151379 10, 0x0, sum = 2
1619 23:53:32.151432 11, 0x0, sum = 3
1620 23:53:32.151484 12, 0x0, sum = 4
1621 23:53:32.151537 best_step = 10
1622 23:53:32.151588
1623 23:53:32.151639 ==
1624 23:53:32.151691 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 23:53:32.151743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 23:53:32.151795 ==
1627 23:53:32.151847 RX Vref Scan: 1
1628 23:53:32.151899
1629 23:53:32.151950 Set Vref Range= 32 -> 127
1630 23:53:32.152001
1631 23:53:32.152053 RX Vref 32 -> 127, step: 1
1632 23:53:32.152104
1633 23:53:32.152155 RX Delay -95 -> 252, step: 8
1634 23:53:32.152207
1635 23:53:32.152258 Set Vref, RX VrefLevel [Byte0]: 32
1636 23:53:32.152310 [Byte1]: 32
1637 23:53:32.152370
1638 23:53:32.152465 Set Vref, RX VrefLevel [Byte0]: 33
1639 23:53:32.152517 [Byte1]: 33
1640 23:53:32.152569
1641 23:53:32.152621 Set Vref, RX VrefLevel [Byte0]: 34
1642 23:53:32.152673 [Byte1]: 34
1643 23:53:32.152725
1644 23:53:32.152776 Set Vref, RX VrefLevel [Byte0]: 35
1645 23:53:32.152828 [Byte1]: 35
1646 23:53:32.152880
1647 23:53:32.152933 Set Vref, RX VrefLevel [Byte0]: 36
1648 23:53:32.152985 [Byte1]: 36
1649 23:53:32.153037
1650 23:53:32.153088 Set Vref, RX VrefLevel [Byte0]: 37
1651 23:53:32.153140 [Byte1]: 37
1652 23:53:32.153192
1653 23:53:32.153243 Set Vref, RX VrefLevel [Byte0]: 38
1654 23:53:32.153337 [Byte1]: 38
1655 23:53:32.153389
1656 23:53:32.153442 Set Vref, RX VrefLevel [Byte0]: 39
1657 23:53:32.153494 [Byte1]: 39
1658 23:53:32.153546
1659 23:53:32.153598 Set Vref, RX VrefLevel [Byte0]: 40
1660 23:53:32.153650 [Byte1]: 40
1661 23:53:32.153701
1662 23:53:32.153752 Set Vref, RX VrefLevel [Byte0]: 41
1663 23:53:32.153804 [Byte1]: 41
1664 23:53:32.153855
1665 23:53:32.153907 Set Vref, RX VrefLevel [Byte0]: 42
1666 23:53:32.153959 [Byte1]: 42
1667 23:53:32.154011
1668 23:53:32.154062 Set Vref, RX VrefLevel [Byte0]: 43
1669 23:53:32.154114 [Byte1]: 43
1670 23:53:32.154188
1671 23:53:32.154256 Set Vref, RX VrefLevel [Byte0]: 44
1672 23:53:32.154308 [Byte1]: 44
1673 23:53:32.154359
1674 23:53:32.154411 Set Vref, RX VrefLevel [Byte0]: 45
1675 23:53:32.154463 [Byte1]: 45
1676 23:53:32.154545
1677 23:53:32.154619 Set Vref, RX VrefLevel [Byte0]: 46
1678 23:53:32.154686 [Byte1]: 46
1679 23:53:32.154737
1680 23:53:32.154789 Set Vref, RX VrefLevel [Byte0]: 47
1681 23:53:32.154841 [Byte1]: 47
1682 23:53:32.154893
1683 23:53:32.154944 Set Vref, RX VrefLevel [Byte0]: 48
1684 23:53:32.154996 [Byte1]: 48
1685 23:53:32.155048
1686 23:53:32.155100 Set Vref, RX VrefLevel [Byte0]: 49
1687 23:53:32.155177 [Byte1]: 49
1688 23:53:32.155245
1689 23:53:32.155299 Set Vref, RX VrefLevel [Byte0]: 50
1690 23:53:32.155381 [Byte1]: 50
1691 23:53:32.155433
1692 23:53:32.155484 Set Vref, RX VrefLevel [Byte0]: 51
1693 23:53:32.155536 [Byte1]: 51
1694 23:53:32.155587
1695 23:53:32.155639 Set Vref, RX VrefLevel [Byte0]: 52
1696 23:53:32.155707 [Byte1]: 52
1697 23:53:32.155789
1698 23:53:32.156077 Set Vref, RX VrefLevel [Byte0]: 53
1699 23:53:32.156214 [Byte1]: 53
1700 23:53:32.156371
1701 23:53:32.156513 Set Vref, RX VrefLevel [Byte0]: 54
1702 23:53:32.156655 [Byte1]: 54
1703 23:53:32.156740
1704 23:53:32.156826 Set Vref, RX VrefLevel [Byte0]: 55
1705 23:53:32.156880 [Byte1]: 55
1706 23:53:32.156933
1707 23:53:32.157014 Set Vref, RX VrefLevel [Byte0]: 56
1708 23:53:32.157131 [Byte1]: 56
1709 23:53:32.157214
1710 23:53:32.157319 Set Vref, RX VrefLevel [Byte0]: 57
1711 23:53:32.157376 [Byte1]: 57
1712 23:53:32.157458
1713 23:53:32.157526 Set Vref, RX VrefLevel [Byte0]: 58
1714 23:53:32.157594 [Byte1]: 58
1715 23:53:32.157661
1716 23:53:32.157743 Set Vref, RX VrefLevel [Byte0]: 59
1717 23:53:32.157825 [Byte1]: 59
1718 23:53:32.157907
1719 23:53:32.157988 Set Vref, RX VrefLevel [Byte0]: 60
1720 23:53:32.158079 [Byte1]: 60
1721 23:53:32.158136
1722 23:53:32.158189 Set Vref, RX VrefLevel [Byte0]: 61
1723 23:53:32.158242 [Byte1]: 61
1724 23:53:32.158295
1725 23:53:32.158347 Set Vref, RX VrefLevel [Byte0]: 62
1726 23:53:32.158401 [Byte1]: 62
1727 23:53:32.158455
1728 23:53:32.158508 Set Vref, RX VrefLevel [Byte0]: 63
1729 23:53:32.158564 [Byte1]: 63
1730 23:53:32.158617
1731 23:53:32.158671 Set Vref, RX VrefLevel [Byte0]: 64
1732 23:53:32.158725 [Byte1]: 64
1733 23:53:32.158778
1734 23:53:32.158830 Set Vref, RX VrefLevel [Byte0]: 65
1735 23:53:32.158883 [Byte1]: 65
1736 23:53:32.158936
1737 23:53:32.158988 Set Vref, RX VrefLevel [Byte0]: 66
1738 23:53:32.159041 [Byte1]: 66
1739 23:53:32.159094
1740 23:53:32.159146 Set Vref, RX VrefLevel [Byte0]: 67
1741 23:53:32.159199 [Byte1]: 67
1742 23:53:32.159252
1743 23:53:32.159304 Set Vref, RX VrefLevel [Byte0]: 68
1744 23:53:32.159357 [Byte1]: 68
1745 23:53:32.159409
1746 23:53:32.159462 Set Vref, RX VrefLevel [Byte0]: 69
1747 23:53:32.159514 [Byte1]: 69
1748 23:53:32.159567
1749 23:53:32.159619 Set Vref, RX VrefLevel [Byte0]: 70
1750 23:53:32.159673 [Byte1]: 70
1751 23:53:32.159725
1752 23:53:32.159778 Set Vref, RX VrefLevel [Byte0]: 71
1753 23:53:32.159831 [Byte1]: 71
1754 23:53:32.159883
1755 23:53:32.159936 Set Vref, RX VrefLevel [Byte0]: 72
1756 23:53:32.159989 [Byte1]: 72
1757 23:53:32.160042
1758 23:53:32.160095 Set Vref, RX VrefLevel [Byte0]: 73
1759 23:53:32.160148 [Byte1]: 73
1760 23:53:32.160201
1761 23:53:32.160253 Set Vref, RX VrefLevel [Byte0]: 74
1762 23:53:32.160306 [Byte1]: 74
1763 23:53:32.160359
1764 23:53:32.160411 Set Vref, RX VrefLevel [Byte0]: 75
1765 23:53:32.160464 [Byte1]: 75
1766 23:53:32.160517
1767 23:53:32.160570 Final RX Vref Byte 0 = 55 to rank0
1768 23:53:32.160623 Final RX Vref Byte 1 = 54 to rank0
1769 23:53:32.160676 Final RX Vref Byte 0 = 55 to rank1
1770 23:53:32.160730 Final RX Vref Byte 1 = 54 to rank1==
1771 23:53:32.160784 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 23:53:32.160837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 23:53:32.160890 ==
1774 23:53:32.160944 DQS Delay:
1775 23:53:32.160998 DQS0 = 0, DQS1 = 0
1776 23:53:32.161051 DQM Delay:
1777 23:53:32.161104 DQM0 = 84, DQM1 = 80
1778 23:53:32.161157 DQ Delay:
1779 23:53:32.161210 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1780 23:53:32.161271 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1781 23:53:32.161327 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1782 23:53:32.161380 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1783 23:53:32.161433
1784 23:53:32.161486
1785 23:53:32.161539 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1786 23:53:32.161593 CH1 RK0: MR19=606, MR18=1C2F
1787 23:53:32.161647 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1788 23:53:32.161700
1789 23:53:32.161754 ----->DramcWriteLeveling(PI) begin...
1790 23:53:32.161808 ==
1791 23:53:32.161861 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 23:53:32.161914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 23:53:32.161968 ==
1794 23:53:32.162021 Write leveling (Byte 0): 26 => 26
1795 23:53:32.162074 Write leveling (Byte 1): 27 => 27
1796 23:53:32.162127 DramcWriteLeveling(PI) end<-----
1797 23:53:32.162180
1798 23:53:32.162233 ==
1799 23:53:32.162285 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 23:53:32.162339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 23:53:32.162393 ==
1802 23:53:32.162446 [Gating] SW mode calibration
1803 23:53:32.162498 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 23:53:32.162551 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 23:53:32.162605 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 23:53:32.162659 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1807 23:53:32.162712 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1808 23:53:32.162768 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:53:32.162832 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:53:32.162887 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:53:32.162940 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:53:32.163012 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:53:32.163106 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:53:32.163164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:53:32.163219 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:53:32.163273 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:53:32.163327 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:53:32.163380 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:53:32.163434 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:53:32.163488 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:53:32.163541 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1822 23:53:32.163594 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 23:53:32.163647 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:53:32.163701 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:53:32.163754 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:53:32.163808 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:53:32.163861 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:53:32.164116 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:53:32.164248 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:53:32.164377 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1831 23:53:32.164505 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1832 23:53:32.164633 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 23:53:32.164695 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 23:53:32.164751 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 23:53:32.164805 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 23:53:32.164859 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 23:53:32.164913 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1838 23:53:32.164966 0 10 4 | B1->B0 | 3333 2828 | 1 0 | (0 0) (0 0)
1839 23:53:32.165019 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1840 23:53:32.165072 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:53:32.165125 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:53:32.165179 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:53:32.165231 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:53:32.165296 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:53:32.165350 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1846 23:53:32.165405 0 11 4 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
1847 23:53:32.165459 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
1848 23:53:32.165512 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 23:53:32.165565 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 23:53:32.165618 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 23:53:32.165672 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 23:53:32.165725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 23:53:32.165778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 23:53:32.165832 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1855 23:53:32.165885 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:53:32.165939 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:53:32.165993 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:53:32.166046 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:53:32.166099 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:53:32.166152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:53:32.166205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 23:53:32.166258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 23:53:32.166311 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:53:32.166363 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:53:32.166417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:53:32.166470 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:53:32.166523 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:53:32.166576 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:53:32.166629 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:53:32.166683 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1871 23:53:32.166736 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 23:53:32.166789 Total UI for P1: 0, mck2ui 16
1873 23:53:32.166842 best dqsien dly found for B0: ( 0, 14, 4)
1874 23:53:32.166901 Total UI for P1: 0, mck2ui 16
1875 23:53:32.166966 best dqsien dly found for B1: ( 0, 14, 6)
1876 23:53:32.167021 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1877 23:53:32.167075 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1878 23:53:32.167128
1879 23:53:32.167181 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1880 23:53:32.167237 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1881 23:53:32.167291 [Gating] SW calibration Done
1882 23:53:32.167344 ==
1883 23:53:32.167397 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 23:53:32.167450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 23:53:32.167503 ==
1886 23:53:32.167557 RX Vref Scan: 0
1887 23:53:32.167610
1888 23:53:32.167663 RX Vref 0 -> 0, step: 1
1889 23:53:32.167715
1890 23:53:32.167769 RX Delay -130 -> 252, step: 16
1891 23:53:32.167822 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1892 23:53:32.167875 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1893 23:53:32.167928 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1894 23:53:32.167982 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1895 23:53:32.168035 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1896 23:53:32.168089 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1897 23:53:32.168142 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1898 23:53:32.168195 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1899 23:53:32.168248 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1900 23:53:32.168301 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1901 23:53:32.168354 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1902 23:53:32.168408 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1903 23:53:32.168461 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1904 23:53:32.168515 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1905 23:53:32.168568 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1906 23:53:32.168621 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1907 23:53:32.168675 ==
1908 23:53:32.168728 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 23:53:32.168782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1910 23:53:32.168836 ==
1911 23:53:32.168889 DQS Delay:
1912 23:53:32.168942 DQS0 = 0, DQS1 = 0
1913 23:53:32.168995 DQM Delay:
1914 23:53:32.169048 DQM0 = 82, DQM1 = 79
1915 23:53:32.169100 DQ Delay:
1916 23:53:32.169154 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1917 23:53:32.169207 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1918 23:53:32.169268 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1919 23:53:32.327746 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1920 23:53:32.327871
1921 23:53:32.327936
1922 23:53:32.327997 ==
1923 23:53:32.328056 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 23:53:32.328145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 23:53:32.328233 ==
1926 23:53:32.328322
1927 23:53:32.328406
1928 23:53:32.328472 TX Vref Scan disable
1929 23:53:32.328530 == TX Byte 0 ==
1930 23:53:32.328586 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1931 23:53:32.328642 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1932 23:53:32.328696 == TX Byte 1 ==
1933 23:53:32.328963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1934 23:53:32.329098 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1935 23:53:32.329228 ==
1936 23:53:32.329369 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 23:53:32.329502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 23:53:32.329589 ==
1939 23:53:32.329647 TX Vref=22, minBit 1, minWin=27, winSum=443
1940 23:53:32.329704 TX Vref=24, minBit 3, minWin=27, winSum=452
1941 23:53:32.329759 TX Vref=26, minBit 4, minWin=27, winSum=451
1942 23:53:32.329814 TX Vref=28, minBit 0, minWin=28, winSum=456
1943 23:53:32.329869 TX Vref=30, minBit 2, minWin=27, winSum=454
1944 23:53:32.329922 TX Vref=32, minBit 5, minWin=27, winSum=453
1945 23:53:32.329977 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1946 23:53:32.330032
1947 23:53:32.330086 Final TX Range 1 Vref 28
1948 23:53:32.330139
1949 23:53:32.330193 ==
1950 23:53:32.330246 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 23:53:32.330300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 23:53:32.330353 ==
1953 23:53:32.330406
1954 23:53:32.330459
1955 23:53:32.330511 TX Vref Scan disable
1956 23:53:32.330565 == TX Byte 0 ==
1957 23:53:32.330617 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1958 23:53:32.330671 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1959 23:53:32.330724 == TX Byte 1 ==
1960 23:53:32.330777 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1961 23:53:32.330831 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1962 23:53:32.330884
1963 23:53:32.330936 [DATLAT]
1964 23:53:32.330989 Freq=800, CH1 RK1
1965 23:53:32.331042
1966 23:53:32.331105 DATLAT Default: 0xa
1967 23:53:32.331181 0, 0xFFFF, sum = 0
1968 23:53:32.331243 1, 0xFFFF, sum = 0
1969 23:53:32.331300 2, 0xFFFF, sum = 0
1970 23:53:32.331355 3, 0xFFFF, sum = 0
1971 23:53:32.331410 4, 0xFFFF, sum = 0
1972 23:53:32.331464 5, 0xFFFF, sum = 0
1973 23:53:32.331526 6, 0xFFFF, sum = 0
1974 23:53:32.331620 7, 0xFFFF, sum = 0
1975 23:53:32.331717 8, 0xFFFF, sum = 0
1976 23:53:32.331806 9, 0x0, sum = 1
1977 23:53:32.331890 10, 0x0, sum = 2
1978 23:53:32.331957 11, 0x0, sum = 3
1979 23:53:32.332015 12, 0x0, sum = 4
1980 23:53:32.332070 best_step = 10
1981 23:53:32.332125
1982 23:53:32.332178 ==
1983 23:53:32.332232 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 23:53:32.332286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 23:53:32.332340 ==
1986 23:53:32.332394 RX Vref Scan: 0
1987 23:53:32.332454
1988 23:53:32.332520 RX Vref 0 -> 0, step: 1
1989 23:53:32.332583
1990 23:53:32.332646 RX Delay -95 -> 252, step: 8
1991 23:53:32.332700 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1992 23:53:32.332754 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1993 23:53:32.332808 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1994 23:53:32.332862 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1995 23:53:32.332915 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1996 23:53:32.332969 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1997 23:53:32.333024 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1998 23:53:32.333092 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1999 23:53:32.333179 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2000 23:53:32.333267 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2001 23:53:32.333325 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2002 23:53:32.333379 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2003 23:53:32.333432 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2004 23:53:32.333486 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2005 23:53:32.333539 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2006 23:53:32.333625 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2007 23:53:32.333679 ==
2008 23:53:32.333764 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 23:53:32.333850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 23:53:32.333905 ==
2011 23:53:32.333990 DQS Delay:
2012 23:53:32.334043 DQS0 = 0, DQS1 = 0
2013 23:53:32.334097 DQM Delay:
2014 23:53:32.334151 DQM0 = 86, DQM1 = 81
2015 23:53:32.334204 DQ Delay:
2016 23:53:32.334258 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2017 23:53:32.334312 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2018 23:53:32.334366 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2019 23:53:32.334420 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2020 23:53:32.334474
2021 23:53:32.334527
2022 23:53:32.334580 [DQSOSCAuto] RK1, (LSB)MR18= 0x213d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2023 23:53:32.334635 CH1 RK1: MR19=606, MR18=213D
2024 23:53:32.334690 CH1_RK1: MR19=0x606, MR18=0x213D, DQSOSC=394, MR23=63, INC=95, DEC=63
2025 23:53:32.334752 [RxdqsGatingPostProcess] freq 800
2026 23:53:32.334817 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2027 23:53:32.334872 Pre-setting of DQS Precalculation
2028 23:53:32.334926 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2029 23:53:32.334980 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2030 23:53:32.335035 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2031 23:53:32.335089
2032 23:53:32.335166
2033 23:53:32.335259 [Calibration Summary] 1600 Mbps
2034 23:53:32.335347 CH 0, Rank 0
2035 23:53:32.335437 SW Impedance : PASS
2036 23:53:32.335519 DUTY Scan : NO K
2037 23:53:32.335601 ZQ Calibration : PASS
2038 23:53:32.335661 Jitter Meter : NO K
2039 23:53:32.335716 CBT Training : PASS
2040 23:53:32.335771 Write leveling : PASS
2041 23:53:32.335825 RX DQS gating : PASS
2042 23:53:32.335879 RX DQ/DQS(RDDQC) : PASS
2043 23:53:32.335933 TX DQ/DQS : PASS
2044 23:53:32.336009 RX DATLAT : PASS
2045 23:53:32.336065 RX DQ/DQS(Engine): PASS
2046 23:53:32.336139 TX OE : NO K
2047 23:53:32.336197 All Pass.
2048 23:53:32.336251
2049 23:53:32.336305 CH 0, Rank 1
2050 23:53:32.336359 SW Impedance : PASS
2051 23:53:32.336414 DUTY Scan : NO K
2052 23:53:32.336467 ZQ Calibration : PASS
2053 23:53:32.336527 Jitter Meter : NO K
2054 23:53:32.336617 CBT Training : PASS
2055 23:53:32.336701 Write leveling : PASS
2056 23:53:32.336784 RX DQS gating : PASS
2057 23:53:32.336868 RX DQ/DQS(RDDQC) : PASS
2058 23:53:32.336951 TX DQ/DQS : PASS
2059 23:53:32.337034 RX DATLAT : PASS
2060 23:53:32.337117 RX DQ/DQS(Engine): PASS
2061 23:53:32.337200 TX OE : NO K
2062 23:53:32.337294 All Pass.
2063 23:53:32.337350
2064 23:53:32.337404 CH 1, Rank 0
2065 23:53:32.337458 SW Impedance : PASS
2066 23:53:32.337514 DUTY Scan : NO K
2067 23:53:32.337567 ZQ Calibration : PASS
2068 23:53:32.337621 Jitter Meter : NO K
2069 23:53:32.337681 CBT Training : PASS
2070 23:53:32.337746 Write leveling : PASS
2071 23:53:32.337801 RX DQS gating : PASS
2072 23:53:32.337855 RX DQ/DQS(RDDQC) : PASS
2073 23:53:32.337933 TX DQ/DQS : PASS
2074 23:53:32.337989 RX DATLAT : PASS
2075 23:53:32.338043 RX DQ/DQS(Engine): PASS
2076 23:53:32.338098 TX OE : NO K
2077 23:53:32.338152 All Pass.
2078 23:53:32.338206
2079 23:53:32.338259 CH 1, Rank 1
2080 23:53:32.338313 SW Impedance : PASS
2081 23:53:32.338367 DUTY Scan : NO K
2082 23:53:32.338648 ZQ Calibration : PASS
2083 23:53:32.338786 Jitter Meter : NO K
2084 23:53:32.338917 CBT Training : PASS
2085 23:53:32.339047 Write leveling : PASS
2086 23:53:32.339235 RX DQS gating : PASS
2087 23:53:32.339337 RX DQ/DQS(RDDQC) : PASS
2088 23:53:32.339424 TX DQ/DQS : PASS
2089 23:53:32.339494 RX DATLAT : PASS
2090 23:53:32.339565 RX DQ/DQS(Engine): PASS
2091 23:53:32.339650 TX OE : NO K
2092 23:53:32.339705 All Pass.
2093 23:53:32.339758
2094 23:53:32.339813 DramC Write-DBI off
2095 23:53:32.339867 PER_BANK_REFRESH: Hybrid Mode
2096 23:53:32.339921 TX_TRACKING: ON
2097 23:53:32.339975 [GetDramInforAfterCalByMRR] Vendor 6.
2098 23:53:32.340030 [GetDramInforAfterCalByMRR] Revision 606.
2099 23:53:32.340084 [GetDramInforAfterCalByMRR] Revision 2 0.
2100 23:53:32.340138 MR0 0x3b3b
2101 23:53:32.340191 MR8 0x5151
2102 23:53:32.340245 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 23:53:32.340299
2104 23:53:32.340352 MR0 0x3b3b
2105 23:53:32.340405 MR8 0x5151
2106 23:53:32.340459 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 23:53:32.340512
2108 23:53:32.340565 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2109 23:53:32.340621 [FAST_K] Save calibration result to emmc
2110 23:53:32.340675 [FAST_K] Save calibration result to emmc
2111 23:53:32.340728 dram_init: config_dvfs: 1
2112 23:53:32.340781 dramc_set_vcore_voltage set vcore to 662500
2113 23:53:32.340835 Read voltage for 1200, 2
2114 23:53:32.340889 Vio18 = 0
2115 23:53:32.340942 Vcore = 662500
2116 23:53:32.340996 Vdram = 0
2117 23:53:32.341049 Vddq = 0
2118 23:53:32.341102 Vmddr = 0
2119 23:53:32.341155 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2120 23:53:32.341209 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2121 23:53:32.341275 MEM_TYPE=3, freq_sel=15
2122 23:53:32.341341 sv_algorithm_assistance_LP4_1600
2123 23:53:32.341396 ============ PULL DRAM RESETB DOWN ============
2124 23:53:32.341451 ========== PULL DRAM RESETB DOWN end =========
2125 23:53:32.341506 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 23:53:32.341561 ===================================
2127 23:53:32.341615 LPDDR4 DRAM CONFIGURATION
2128 23:53:32.341669 ===================================
2129 23:53:32.341722 EX_ROW_EN[0] = 0x0
2130 23:53:32.341790 EX_ROW_EN[1] = 0x0
2131 23:53:32.341842 LP4Y_EN = 0x0
2132 23:53:32.341895 WORK_FSP = 0x0
2133 23:53:32.341946 WL = 0x4
2134 23:53:32.342030 RL = 0x4
2135 23:53:32.342100 BL = 0x2
2136 23:53:32.342183 RPST = 0x0
2137 23:53:32.342250 RD_PRE = 0x0
2138 23:53:32.342319 WR_PRE = 0x1
2139 23:53:32.342387 WR_PST = 0x0
2140 23:53:32.342439 DBI_WR = 0x0
2141 23:53:32.342508 DBI_RD = 0x0
2142 23:53:32.342576 OTF = 0x1
2143 23:53:32.342628 ===================================
2144 23:53:32.342682 ===================================
2145 23:53:32.342734 ANA top config
2146 23:53:32.342787 ===================================
2147 23:53:32.342872 DLL_ASYNC_EN = 0
2148 23:53:32.342957 ALL_SLAVE_EN = 0
2149 23:53:32.343027 NEW_RANK_MODE = 1
2150 23:53:32.343095 DLL_IDLE_MODE = 1
2151 23:53:32.343147 LP45_APHY_COMB_EN = 1
2152 23:53:32.343200 TX_ODT_DIS = 1
2153 23:53:32.343252 NEW_8X_MODE = 1
2154 23:53:32.343306 ===================================
2155 23:53:32.343358 ===================================
2156 23:53:32.343410 data_rate = 2400
2157 23:53:32.343463 CKR = 1
2158 23:53:32.343515 DQ_P2S_RATIO = 8
2159 23:53:32.343617 ===================================
2160 23:53:32.343684 CA_P2S_RATIO = 8
2161 23:53:32.343736 DQ_CA_OPEN = 0
2162 23:53:32.343789 DQ_SEMI_OPEN = 0
2163 23:53:32.343841 CA_SEMI_OPEN = 0
2164 23:53:32.343924 CA_FULL_RATE = 0
2165 23:53:32.344008 DQ_CKDIV4_EN = 0
2166 23:53:32.344061 CA_CKDIV4_EN = 0
2167 23:53:32.344131 CA_PREDIV_EN = 0
2168 23:53:32.344213 PH8_DLY = 17
2169 23:53:32.344296 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2170 23:53:32.344364 DQ_AAMCK_DIV = 4
2171 23:53:32.344417 CA_AAMCK_DIV = 4
2172 23:53:32.344468 CA_ADMCK_DIV = 4
2173 23:53:32.344521 DQ_TRACK_CA_EN = 0
2174 23:53:32.344573 CA_PICK = 1200
2175 23:53:32.344641 CA_MCKIO = 1200
2176 23:53:32.344709 MCKIO_SEMI = 0
2177 23:53:32.344775 PLL_FREQ = 2366
2178 23:53:32.344829 DQ_UI_PI_RATIO = 32
2179 23:53:32.344882 CA_UI_PI_RATIO = 0
2180 23:53:32.344951 ===================================
2181 23:53:32.345047 ===================================
2182 23:53:32.345100 memory_type:LPDDR4
2183 23:53:32.345169 GP_NUM : 10
2184 23:53:32.345223 SRAM_EN : 1
2185 23:53:32.345298 MD32_EN : 0
2186 23:53:32.345353 ===================================
2187 23:53:32.345406 [ANA_INIT] >>>>>>>>>>>>>>
2188 23:53:32.345459 <<<<<< [CONFIGURE PHASE]: ANA_TX
2189 23:53:32.345512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2190 23:53:32.345580 ===================================
2191 23:53:32.345647 data_rate = 2400,PCW = 0X5b00
2192 23:53:32.345715 ===================================
2193 23:53:32.345799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2194 23:53:32.345866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 23:53:32.345919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 23:53:32.346001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2197 23:53:32.346085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2198 23:53:32.346137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2199 23:53:32.346190 [ANA_INIT] flow start
2200 23:53:32.346258 [ANA_INIT] PLL >>>>>>>>
2201 23:53:32.346340 [ANA_INIT] PLL <<<<<<<<
2202 23:53:32.346393 [ANA_INIT] MIDPI >>>>>>>>
2203 23:53:32.346447 [ANA_INIT] MIDPI <<<<<<<<
2204 23:53:32.346500 [ANA_INIT] DLL >>>>>>>>
2205 23:53:32.346553 [ANA_INIT] DLL <<<<<<<<
2206 23:53:32.346606 [ANA_INIT] flow end
2207 23:53:32.346660 ============ LP4 DIFF to SE enter ============
2208 23:53:32.346714 ============ LP4 DIFF to SE exit ============
2209 23:53:32.346767 [ANA_INIT] <<<<<<<<<<<<<
2210 23:53:32.346821 [Flow] Enable top DCM control >>>>>
2211 23:53:32.346875 [Flow] Enable top DCM control <<<<<
2212 23:53:32.346928 Enable DLL master slave shuffle
2213 23:53:32.346982 ==============================================================
2214 23:53:32.347237 Gating Mode config
2215 23:53:32.347370 ==============================================================
2216 23:53:32.347502 Config description:
2217 23:53:32.347633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2218 23:53:32.347766 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2219 23:53:32.347879 SELPH_MODE 0: By rank 1: By Phase
2220 23:53:32.347939 ==============================================================
2221 23:53:32.347995 GAT_TRACK_EN = 1
2222 23:53:32.348049 RX_GATING_MODE = 2
2223 23:53:32.348103 RX_GATING_TRACK_MODE = 2
2224 23:53:32.348157 SELPH_MODE = 1
2225 23:53:32.348211 PICG_EARLY_EN = 1
2226 23:53:32.348265 VALID_LAT_VALUE = 1
2227 23:53:32.348319 ==============================================================
2228 23:53:32.348374 Enter into Gating configuration >>>>
2229 23:53:32.348428 Exit from Gating configuration <<<<
2230 23:53:32.348482 Enter into DVFS_PRE_config >>>>>
2231 23:53:32.348535 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2232 23:53:32.348591 Exit from DVFS_PRE_config <<<<<
2233 23:53:32.348645 Enter into PICG configuration >>>>
2234 23:53:32.348698 Exit from PICG configuration <<<<
2235 23:53:32.348752 [RX_INPUT] configuration >>>>>
2236 23:53:32.348805 [RX_INPUT] configuration <<<<<
2237 23:53:32.348858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2238 23:53:32.348913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2239 23:53:32.348967 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 23:53:32.349022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 23:53:32.349076 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 23:53:32.349130 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 23:53:32.349184 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2244 23:53:32.349238 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2245 23:53:32.349302 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2246 23:53:32.349358 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2247 23:53:32.349412 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2248 23:53:32.349466 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2249 23:53:32.349520 ===================================
2250 23:53:32.349575 LPDDR4 DRAM CONFIGURATION
2251 23:53:32.349629 ===================================
2252 23:53:32.349683 EX_ROW_EN[0] = 0x0
2253 23:53:32.349736 EX_ROW_EN[1] = 0x0
2254 23:53:32.349789 LP4Y_EN = 0x0
2255 23:53:32.349842 WORK_FSP = 0x0
2256 23:53:32.349896 WL = 0x4
2257 23:53:32.349949 RL = 0x4
2258 23:53:32.350002 BL = 0x2
2259 23:53:32.350056 RPST = 0x0
2260 23:53:32.350109 RD_PRE = 0x0
2261 23:53:32.350163 WR_PRE = 0x1
2262 23:53:32.350216 WR_PST = 0x0
2263 23:53:32.350269 DBI_WR = 0x0
2264 23:53:32.350322 DBI_RD = 0x0
2265 23:53:32.350375 OTF = 0x1
2266 23:53:32.350428 ===================================
2267 23:53:32.350482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2268 23:53:32.350536 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2269 23:53:32.350589 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 23:53:32.350643 ===================================
2271 23:53:32.350697 LPDDR4 DRAM CONFIGURATION
2272 23:53:32.350751 ===================================
2273 23:53:32.350805 EX_ROW_EN[0] = 0x10
2274 23:53:32.350858 EX_ROW_EN[1] = 0x0
2275 23:53:32.350911 LP4Y_EN = 0x0
2276 23:53:32.350964 WORK_FSP = 0x0
2277 23:53:32.351018 WL = 0x4
2278 23:53:32.351071 RL = 0x4
2279 23:53:32.351123 BL = 0x2
2280 23:53:32.351176 RPST = 0x0
2281 23:53:32.351229 RD_PRE = 0x0
2282 23:53:32.351283 WR_PRE = 0x1
2283 23:53:32.351336 WR_PST = 0x0
2284 23:53:32.351389 DBI_WR = 0x0
2285 23:53:32.351442 DBI_RD = 0x0
2286 23:53:32.351495 OTF = 0x1
2287 23:53:32.351549 ===================================
2288 23:53:32.351603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2289 23:53:32.351657 ==
2290 23:53:32.351711 Dram Type= 6, Freq= 0, CH_0, rank 0
2291 23:53:32.351764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2292 23:53:32.351818 ==
2293 23:53:32.351872 [Duty_Offset_Calibration]
2294 23:53:32.351925 B0:2 B1:0 CA:4
2295 23:53:32.351978
2296 23:53:32.352031 [DutyScan_Calibration_Flow] k_type=0
2297 23:53:32.352084
2298 23:53:32.352137 ==CLK 0==
2299 23:53:32.352190 Final CLK duty delay cell = -4
2300 23:53:32.352244 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2301 23:53:32.352296 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2302 23:53:32.352349 [-4] AVG Duty = 4937%(X100)
2303 23:53:32.352402
2304 23:53:32.352454 CH0 CLK Duty spec in!! Max-Min= 187%
2305 23:53:32.352507 [DutyScan_Calibration_Flow] ====Done====
2306 23:53:32.352560
2307 23:53:32.352612 [DutyScan_Calibration_Flow] k_type=1
2308 23:53:32.352665
2309 23:53:32.352717 ==DQS 0 ==
2310 23:53:32.352770 Final DQS duty delay cell = 0
2311 23:53:32.352823 [0] MAX Duty = 5156%(X100), DQS PI = 18
2312 23:53:32.352876 [0] MIN Duty = 5093%(X100), DQS PI = 0
2313 23:53:32.352929 [0] AVG Duty = 5124%(X100)
2314 23:53:32.352982
2315 23:53:32.353034 ==DQS 1 ==
2316 23:53:32.353087 Final DQS duty delay cell = 0
2317 23:53:32.353141 [0] MAX Duty = 5125%(X100), DQS PI = 54
2318 23:53:32.353194 [0] MIN Duty = 5000%(X100), DQS PI = 0
2319 23:53:32.353247 [0] AVG Duty = 5062%(X100)
2320 23:53:32.353315
2321 23:53:32.353369 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2322 23:53:32.353423
2323 23:53:32.353475 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2324 23:53:32.353528 [DutyScan_Calibration_Flow] ====Done====
2325 23:53:32.353581
2326 23:53:32.353633 [DutyScan_Calibration_Flow] k_type=3
2327 23:53:32.353686
2328 23:53:32.353738 ==DQM 0 ==
2329 23:53:32.353791 Final DQM duty delay cell = 0
2330 23:53:32.353845 [0] MAX Duty = 5125%(X100), DQS PI = 20
2331 23:53:32.353898 [0] MIN Duty = 4844%(X100), DQS PI = 52
2332 23:53:32.353951 [0] AVG Duty = 4984%(X100)
2333 23:53:32.354003
2334 23:53:32.354055 ==DQM 1 ==
2335 23:53:32.354108 Final DQM duty delay cell = 0
2336 23:53:32.354162 [0] MAX Duty = 4969%(X100), DQS PI = 2
2337 23:53:32.354217 [0] MIN Duty = 4875%(X100), DQS PI = 14
2338 23:53:32.354471 [0] AVG Duty = 4922%(X100)
2339 23:53:32.354603
2340 23:53:32.354731 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2341 23:53:32.354859
2342 23:53:32.354988 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2343 23:53:32.355080 [DutyScan_Calibration_Flow] ====Done====
2344 23:53:32.355138
2345 23:53:32.355193 [DutyScan_Calibration_Flow] k_type=2
2346 23:53:32.355248
2347 23:53:32.355302 ==DQ 0 ==
2348 23:53:32.355356 Final DQ duty delay cell = 0
2349 23:53:32.355410 [0] MAX Duty = 5125%(X100), DQS PI = 18
2350 23:53:32.355465 [0] MIN Duty = 4969%(X100), DQS PI = 52
2351 23:53:32.355519 [0] AVG Duty = 5047%(X100)
2352 23:53:32.355573
2353 23:53:32.355625 ==DQ 1 ==
2354 23:53:32.355679 Final DQ duty delay cell = 0
2355 23:53:32.355733 [0] MAX Duty = 5125%(X100), DQS PI = 6
2356 23:53:32.355787 [0] MIN Duty = 4938%(X100), DQS PI = 16
2357 23:53:32.355840 [0] AVG Duty = 5031%(X100)
2358 23:53:32.355893
2359 23:53:32.355946 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2360 23:53:32.356000
2361 23:53:32.356052 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2362 23:53:32.356105 [DutyScan_Calibration_Flow] ====Done====
2363 23:53:32.356158 ==
2364 23:53:32.356212 Dram Type= 6, Freq= 0, CH_1, rank 0
2365 23:53:32.356266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 23:53:32.356320 ==
2367 23:53:32.356373 [Duty_Offset_Calibration]
2368 23:53:32.356426 B0:0 B1:-1 CA:3
2369 23:53:32.356479
2370 23:53:32.356532 [DutyScan_Calibration_Flow] k_type=0
2371 23:53:32.356585
2372 23:53:32.356638 ==CLK 0==
2373 23:53:32.356691 Final CLK duty delay cell = -4
2374 23:53:32.356745 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2375 23:53:32.356798 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2376 23:53:32.356852 [-4] AVG Duty = 4938%(X100)
2377 23:53:32.356905
2378 23:53:32.356958 CH1 CLK Duty spec in!! Max-Min= 124%
2379 23:53:32.357011 [DutyScan_Calibration_Flow] ====Done====
2380 23:53:32.357066
2381 23:53:32.357119 [DutyScan_Calibration_Flow] k_type=1
2382 23:53:32.357172
2383 23:53:32.357225 ==DQS 0 ==
2384 23:53:32.357295 Final DQS duty delay cell = 0
2385 23:53:32.357380 [0] MAX Duty = 5187%(X100), DQS PI = 18
2386 23:53:32.357464 [0] MIN Duty = 4938%(X100), DQS PI = 38
2387 23:53:32.357521 [0] AVG Duty = 5062%(X100)
2388 23:53:32.357574
2389 23:53:32.357628 ==DQS 1 ==
2390 23:53:32.357682 Final DQS duty delay cell = 0
2391 23:53:32.357735 [0] MAX Duty = 5156%(X100), DQS PI = 12
2392 23:53:32.357788 [0] MIN Duty = 5031%(X100), DQS PI = 18
2393 23:53:32.357842 [0] AVG Duty = 5093%(X100)
2394 23:53:32.357896
2395 23:53:32.357948 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2396 23:53:32.358002
2397 23:53:32.358055 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2398 23:53:32.358109 [DutyScan_Calibration_Flow] ====Done====
2399 23:53:32.358162
2400 23:53:32.358215 [DutyScan_Calibration_Flow] k_type=3
2401 23:53:32.358269
2402 23:53:32.358326 ==DQM 0 ==
2403 23:53:32.358386 Final DQM duty delay cell = 0
2404 23:53:32.358440 [0] MAX Duty = 5031%(X100), DQS PI = 28
2405 23:53:32.358494 [0] MIN Duty = 4813%(X100), DQS PI = 36
2406 23:53:32.358547 [0] AVG Duty = 4922%(X100)
2407 23:53:32.358601
2408 23:53:32.358653 ==DQM 1 ==
2409 23:53:32.358706 Final DQM duty delay cell = 0
2410 23:53:32.358760 [0] MAX Duty = 5000%(X100), DQS PI = 34
2411 23:53:32.358813 [0] MIN Duty = 4844%(X100), DQS PI = 0
2412 23:53:32.358867 [0] AVG Duty = 4922%(X100)
2413 23:53:32.358919
2414 23:53:32.358972 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2415 23:53:32.359025
2416 23:53:32.359078 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2417 23:53:32.359131 [DutyScan_Calibration_Flow] ====Done====
2418 23:53:32.359183
2419 23:53:32.359236 [DutyScan_Calibration_Flow] k_type=2
2420 23:53:32.359289
2421 23:53:32.359342 ==DQ 0 ==
2422 23:53:32.359395 Final DQ duty delay cell = -4
2423 23:53:32.359449 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2424 23:53:32.359503 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2425 23:53:32.359556 [-4] AVG Duty = 4937%(X100)
2426 23:53:32.359609
2427 23:53:32.359662 ==DQ 1 ==
2428 23:53:32.359715 Final DQ duty delay cell = 4
2429 23:53:32.359768 [4] MAX Duty = 5156%(X100), DQS PI = 26
2430 23:53:32.359822 [4] MIN Duty = 5031%(X100), DQS PI = 62
2431 23:53:32.359875 [4] AVG Duty = 5093%(X100)
2432 23:53:32.359927
2433 23:53:32.359980 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2434 23:53:32.360033
2435 23:53:32.360086 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2436 23:53:32.360139 [DutyScan_Calibration_Flow] ====Done====
2437 23:53:32.360192 nWR fixed to 30
2438 23:53:32.360246 [ModeRegInit_LP4] CH0 RK0
2439 23:53:32.360299 [ModeRegInit_LP4] CH0 RK1
2440 23:53:32.360351 [ModeRegInit_LP4] CH1 RK0
2441 23:53:32.360404 [ModeRegInit_LP4] CH1 RK1
2442 23:53:32.360457 match AC timing 7
2443 23:53:32.360509 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2444 23:53:32.360563 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2445 23:53:32.360616 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2446 23:53:32.360670 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2447 23:53:32.360724 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2448 23:53:32.360777 ==
2449 23:53:32.360830 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 23:53:32.360883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 23:53:32.360937 ==
2452 23:53:32.360989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2453 23:53:32.361043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2454 23:53:32.361097 [CA 0] Center 39 (9~70) winsize 62
2455 23:53:32.361150 [CA 1] Center 39 (9~69) winsize 61
2456 23:53:32.361203 [CA 2] Center 35 (5~66) winsize 62
2457 23:53:32.361262 [CA 3] Center 35 (5~66) winsize 62
2458 23:53:32.361319 [CA 4] Center 33 (3~64) winsize 62
2459 23:53:32.361373 [CA 5] Center 33 (3~63) winsize 61
2460 23:53:32.361426
2461 23:53:32.361479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2462 23:53:32.361533
2463 23:53:32.361586 [CATrainingPosCal] consider 1 rank data
2464 23:53:32.361639 u2DelayCellTimex100 = 270/100 ps
2465 23:53:32.361692 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2466 23:53:32.361746 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2467 23:53:32.361800 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2468 23:53:32.361853 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2469 23:53:32.361906 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2470 23:53:32.361960 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2471 23:53:32.362013
2472 23:53:32.362066 CA PerBit enable=1, Macro0, CA PI delay=33
2473 23:53:32.362119
2474 23:53:32.362171 [CBTSetCACLKResult] CA Dly = 33
2475 23:53:32.362224 CS Dly: 7 (0~38)
2476 23:53:32.362278 ==
2477 23:53:32.362331 Dram Type= 6, Freq= 0, CH_0, rank 1
2478 23:53:32.362385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2479 23:53:32.362438 ==
2480 23:53:32.362491 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2481 23:53:32.362545 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2482 23:53:32.362598 [CA 0] Center 39 (9~70) winsize 62
2483 23:53:32.362651 [CA 1] Center 39 (9~70) winsize 62
2484 23:53:32.362704 [CA 2] Center 35 (5~66) winsize 62
2485 23:53:32.362959 [CA 3] Center 35 (5~66) winsize 62
2486 23:53:32.363092 [CA 4] Center 34 (4~65) winsize 62
2487 23:53:32.363221 [CA 5] Center 33 (3~64) winsize 62
2488 23:53:32.363348
2489 23:53:32.363475 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2490 23:53:32.363555
2491 23:53:32.363612 [CATrainingPosCal] consider 2 rank data
2492 23:53:32.363666 u2DelayCellTimex100 = 270/100 ps
2493 23:53:32.363721 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2494 23:53:32.363775 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2495 23:53:32.363829 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2496 23:53:32.363884 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 23:53:32.363938 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2498 23:53:32.363991 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2499 23:53:32.364044
2500 23:53:32.364097 CA PerBit enable=1, Macro0, CA PI delay=33
2501 23:53:32.364152
2502 23:53:32.364204 [CBTSetCACLKResult] CA Dly = 33
2503 23:53:32.364257 CS Dly: 8 (0~41)
2504 23:53:32.364310
2505 23:53:32.364363 ----->DramcWriteLeveling(PI) begin...
2506 23:53:32.364418 ==
2507 23:53:32.364471 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 23:53:32.364525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 23:53:32.364579 ==
2510 23:53:32.364633 Write leveling (Byte 0): 30 => 30
2511 23:53:32.364686 Write leveling (Byte 1): 27 => 27
2512 23:53:32.364739 DramcWriteLeveling(PI) end<-----
2513 23:53:32.364792
2514 23:53:32.364845 ==
2515 23:53:32.364898 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 23:53:32.364952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:53:32.365006 ==
2518 23:53:32.365058 [Gating] SW mode calibration
2519 23:53:32.365111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2520 23:53:32.365165 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2521 23:53:32.365219 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2522 23:53:32.365297 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2523 23:53:32.365352 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 23:53:32.365404 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 23:53:32.365456 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 23:53:32.365526 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 23:53:32.365612 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 23:53:32.365695 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2529 23:53:32.365749 1 0 0 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2530 23:53:32.365802 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 23:53:32.365856 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 23:53:32.365909 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 23:53:32.365962 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 23:53:32.366047 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 23:53:32.366146 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2536 23:53:32.366198 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2537 23:53:32.366250 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2538 23:53:32.366303 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2539 23:53:32.366356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 23:53:32.366408 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 23:53:32.366460 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 23:53:32.366544 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 23:53:32.366595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 23:53:32.366665 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2545 23:53:32.366732 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2546 23:53:32.366784 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 23:53:32.366836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:53:32.366888 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:53:32.366958 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:53:32.367011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:53:32.367064 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:53:32.367117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 23:53:32.367192 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:53:32.367263 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:53:32.367315 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:53:32.367368 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:53:32.367419 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:53:32.367504 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:53:32.367557 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:53:32.367609 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2561 23:53:32.367662 Total UI for P1: 0, mck2ui 16
2562 23:53:32.367715 best dqsien dly found for B0: ( 1, 3, 26)
2563 23:53:32.367768 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 23:53:32.367820 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 23:53:32.367872 Total UI for P1: 0, mck2ui 16
2566 23:53:32.367925 best dqsien dly found for B1: ( 1, 4, 0)
2567 23:53:32.368026 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2568 23:53:32.368093 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2569 23:53:32.368145
2570 23:53:32.368197 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2571 23:53:32.368249 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2572 23:53:32.368301 [Gating] SW calibration Done
2573 23:53:32.368354 ==
2574 23:53:32.368406 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 23:53:32.368490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 23:53:32.368543 ==
2577 23:53:32.368595 RX Vref Scan: 0
2578 23:53:32.368646
2579 23:53:32.368713 RX Vref 0 -> 0, step: 1
2580 23:53:32.368796
2581 23:53:32.368849 RX Delay -40 -> 252, step: 8
2582 23:53:32.368903 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2583 23:53:32.368956 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2584 23:53:32.369010 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2585 23:53:32.369063 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2586 23:53:32.369131 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2587 23:53:32.369183 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2588 23:53:32.369235 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2589 23:53:32.369536 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2590 23:53:32.369668 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2591 23:53:32.369809 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2592 23:53:32.369938 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2593 23:53:32.370067 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2594 23:53:32.370153 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2595 23:53:32.370209 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2596 23:53:32.370264 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2597 23:53:32.370319 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2598 23:53:32.370372 ==
2599 23:53:32.370426 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 23:53:32.370494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 23:53:32.370564 ==
2602 23:53:32.370617 DQS Delay:
2603 23:53:32.370670 DQS0 = 0, DQS1 = 0
2604 23:53:32.370723 DQM Delay:
2605 23:53:32.370776 DQM0 = 118, DQM1 = 107
2606 23:53:32.370830 DQ Delay:
2607 23:53:32.370897 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2608 23:53:32.370965 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2609 23:53:32.371018 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2610 23:53:32.371072 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2611 23:53:32.371125
2612 23:53:32.371178
2613 23:53:32.371245 ==
2614 23:53:32.371298 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 23:53:32.371350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 23:53:32.371402 ==
2617 23:53:32.371486
2618 23:53:32.371537
2619 23:53:32.371589 TX Vref Scan disable
2620 23:53:32.371640 == TX Byte 0 ==
2621 23:53:32.371692 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2622 23:53:32.371745 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2623 23:53:32.371797 == TX Byte 1 ==
2624 23:53:32.371849 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2625 23:53:32.371902 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2626 23:53:32.372002 ==
2627 23:53:32.372070 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 23:53:32.372122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 23:53:32.372175 ==
2630 23:53:32.372227 TX Vref=22, minBit 0, minWin=25, winSum=410
2631 23:53:32.372280 TX Vref=24, minBit 3, minWin=25, winSum=415
2632 23:53:32.372332 TX Vref=26, minBit 1, minWin=26, winSum=423
2633 23:53:32.372385 TX Vref=28, minBit 3, minWin=25, winSum=425
2634 23:53:32.372455 TX Vref=30, minBit 4, minWin=26, winSum=427
2635 23:53:32.372539 TX Vref=32, minBit 0, minWin=26, winSum=428
2636 23:53:32.372624 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 32
2637 23:53:32.372677
2638 23:53:32.372730 Final TX Range 1 Vref 32
2639 23:53:32.372784
2640 23:53:32.372837 ==
2641 23:53:32.372890 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 23:53:32.372943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 23:53:32.372996 ==
2644 23:53:32.373049
2645 23:53:32.373102
2646 23:53:32.373154 TX Vref Scan disable
2647 23:53:32.373208 == TX Byte 0 ==
2648 23:53:32.373268 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2649 23:53:32.373338 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2650 23:53:32.373390 == TX Byte 1 ==
2651 23:53:32.373442 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2652 23:53:32.373512 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2653 23:53:32.373579
2654 23:53:32.373631 [DATLAT]
2655 23:53:32.373683 Freq=1200, CH0 RK0
2656 23:53:32.373736
2657 23:53:32.373787 DATLAT Default: 0xd
2658 23:53:32.373840 0, 0xFFFF, sum = 0
2659 23:53:32.373893 1, 0xFFFF, sum = 0
2660 23:53:32.373947 2, 0xFFFF, sum = 0
2661 23:53:32.374016 3, 0xFFFF, sum = 0
2662 23:53:32.374117 4, 0xFFFF, sum = 0
2663 23:53:32.374188 5, 0xFFFF, sum = 0
2664 23:53:32.374242 6, 0xFFFF, sum = 0
2665 23:53:32.374296 7, 0xFFFF, sum = 0
2666 23:53:32.374350 8, 0xFFFF, sum = 0
2667 23:53:32.374404 9, 0xFFFF, sum = 0
2668 23:53:32.374472 10, 0xFFFF, sum = 0
2669 23:53:32.374556 11, 0xFFFF, sum = 0
2670 23:53:32.374609 12, 0x0, sum = 1
2671 23:53:32.374662 13, 0x0, sum = 2
2672 23:53:32.374714 14, 0x0, sum = 3
2673 23:53:32.374767 15, 0x0, sum = 4
2674 23:53:32.374819 best_step = 13
2675 23:53:32.374870
2676 23:53:32.374922 ==
2677 23:53:32.374973 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 23:53:32.375070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 23:53:32.375137 ==
2680 23:53:32.375189 RX Vref Scan: 1
2681 23:53:32.375256
2682 23:53:32.375327 Set Vref Range= 32 -> 127
2683 23:53:32.375402
2684 23:53:32.375489 RX Vref 32 -> 127, step: 1
2685 23:53:32.375547
2686 23:53:32.375601 RX Delay -21 -> 252, step: 4
2687 23:53:32.375669
2688 23:53:32.375722 Set Vref, RX VrefLevel [Byte0]: 32
2689 23:53:32.375774 [Byte1]: 32
2690 23:53:32.375827
2691 23:53:32.375879 Set Vref, RX VrefLevel [Byte0]: 33
2692 23:53:32.375931 [Byte1]: 33
2693 23:53:32.376014
2694 23:53:32.376095 Set Vref, RX VrefLevel [Byte0]: 34
2695 23:53:32.376148 [Byte1]: 34
2696 23:53:32.376200
2697 23:53:32.376252 Set Vref, RX VrefLevel [Byte0]: 35
2698 23:53:32.376304 [Byte1]: 35
2699 23:53:32.376358
2700 23:53:32.376410 Set Vref, RX VrefLevel [Byte0]: 36
2701 23:53:32.376492 [Byte1]: 36
2702 23:53:32.376543
2703 23:53:32.376595 Set Vref, RX VrefLevel [Byte0]: 37
2704 23:53:32.376647 [Byte1]: 37
2705 23:53:32.376698
2706 23:53:32.376750 Set Vref, RX VrefLevel [Byte0]: 38
2707 23:53:32.376802 [Byte1]: 38
2708 23:53:32.376854
2709 23:53:32.376906 Set Vref, RX VrefLevel [Byte0]: 39
2710 23:53:32.377002 [Byte1]: 39
2711 23:53:32.377070
2712 23:53:32.377122 Set Vref, RX VrefLevel [Byte0]: 40
2713 23:53:32.377174 [Byte1]: 40
2714 23:53:32.377226
2715 23:53:32.377300 Set Vref, RX VrefLevel [Byte0]: 41
2716 23:53:32.377390 [Byte1]: 41
2717 23:53:32.377487
2718 23:53:32.377539 Set Vref, RX VrefLevel [Byte0]: 42
2719 23:53:32.377592 [Byte1]: 42
2720 23:53:32.377644
2721 23:53:32.377695 Set Vref, RX VrefLevel [Byte0]: 43
2722 23:53:32.377747 [Byte1]: 43
2723 23:53:32.377799
2724 23:53:32.377851 Set Vref, RX VrefLevel [Byte0]: 44
2725 23:53:32.377902 [Byte1]: 44
2726 23:53:32.377998
2727 23:53:32.378065 Set Vref, RX VrefLevel [Byte0]: 45
2728 23:53:32.378117 [Byte1]: 45
2729 23:53:32.378169
2730 23:53:32.378221 Set Vref, RX VrefLevel [Byte0]: 46
2731 23:53:32.378272 [Byte1]: 46
2732 23:53:32.378324
2733 23:53:32.378375 Set Vref, RX VrefLevel [Byte0]: 47
2734 23:53:32.378457 [Byte1]: 47
2735 23:53:32.378525
2736 23:53:32.378579 Set Vref, RX VrefLevel [Byte0]: 48
2737 23:53:32.378632 [Byte1]: 48
2738 23:53:32.378685
2739 23:53:32.378737 Set Vref, RX VrefLevel [Byte0]: 49
2740 23:53:32.378805 [Byte1]: 49
2741 23:53:32.378858
2742 23:53:32.378940 Set Vref, RX VrefLevel [Byte0]: 50
2743 23:53:32.379037 [Byte1]: 50
2744 23:53:32.379091
2745 23:53:32.379144 Set Vref, RX VrefLevel [Byte0]: 51
2746 23:53:32.379197 [Byte1]: 51
2747 23:53:32.379250
2748 23:53:32.379302 Set Vref, RX VrefLevel [Byte0]: 52
2749 23:53:32.379371 [Byte1]: 52
2750 23:53:32.379428
2751 23:53:32.379679 Set Vref, RX VrefLevel [Byte0]: 53
2752 23:53:32.379812 [Byte1]: 53
2753 23:53:32.379941
2754 23:53:32.380069 Set Vref, RX VrefLevel [Byte0]: 54
2755 23:53:32.380197 [Byte1]: 54
2756 23:53:32.380274
2757 23:53:32.380331 Set Vref, RX VrefLevel [Byte0]: 55
2758 23:53:32.380386 [Byte1]: 55
2759 23:53:32.380453
2760 23:53:32.380507 Set Vref, RX VrefLevel [Byte0]: 56
2761 23:53:32.380559 [Byte1]: 56
2762 23:53:32.380612
2763 23:53:32.380664 Set Vref, RX VrefLevel [Byte0]: 57
2764 23:53:32.380716 [Byte1]: 57
2765 23:53:32.380768
2766 23:53:32.380820 Set Vref, RX VrefLevel [Byte0]: 58
2767 23:53:32.380888 [Byte1]: 58
2768 23:53:32.380941
2769 23:53:32.381007 Set Vref, RX VrefLevel [Byte0]: 59
2770 23:53:32.381059 [Byte1]: 59
2771 23:53:32.381111
2772 23:53:32.381164 Set Vref, RX VrefLevel [Byte0]: 60
2773 23:53:32.381216 [Byte1]: 60
2774 23:53:32.381295
2775 23:53:32.381401 Set Vref, RX VrefLevel [Byte0]: 61
2776 23:53:32.381484 [Byte1]: 61
2777 23:53:32.381537
2778 23:53:32.381589 Set Vref, RX VrefLevel [Byte0]: 62
2779 23:53:32.381641 [Byte1]: 62
2780 23:53:32.381694
2781 23:53:32.381746 Set Vref, RX VrefLevel [Byte0]: 63
2782 23:53:32.381798 [Byte1]: 63
2783 23:53:32.381868
2784 23:53:32.381920 Set Vref, RX VrefLevel [Byte0]: 64
2785 23:53:32.381974 [Byte1]: 64
2786 23:53:32.382027
2787 23:53:32.382080 Set Vref, RX VrefLevel [Byte0]: 65
2788 23:53:32.382148 [Byte1]: 65
2789 23:53:32.382200
2790 23:53:32.382252 Set Vref, RX VrefLevel [Byte0]: 66
2791 23:53:32.382320 [Byte1]: 66
2792 23:53:32.382373
2793 23:53:32.382426 Set Vref, RX VrefLevel [Byte0]: 67
2794 23:53:32.382479 [Byte1]: 67
2795 23:53:32.382531
2796 23:53:32.382584 Set Vref, RX VrefLevel [Byte0]: 68
2797 23:53:32.382652 [Byte1]: 68
2798 23:53:32.382704
2799 23:53:32.382755 Final RX Vref Byte 0 = 51 to rank0
2800 23:53:32.382809 Final RX Vref Byte 1 = 59 to rank0
2801 23:53:32.382861 Final RX Vref Byte 0 = 51 to rank1
2802 23:53:32.382913 Final RX Vref Byte 1 = 59 to rank1==
2803 23:53:32.382995 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 23:53:32.383063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 23:53:32.383117 ==
2806 23:53:32.383171 DQS Delay:
2807 23:53:32.383239 DQS0 = 0, DQS1 = 0
2808 23:53:32.383291 DQM Delay:
2809 23:53:32.383361 DQM0 = 116, DQM1 = 105
2810 23:53:32.383417 DQ Delay:
2811 23:53:32.383486 DQ0 =118, DQ1 =116, DQ2 =112, DQ3 =114
2812 23:53:32.383539 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2813 23:53:32.383591 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2814 23:53:32.383643 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2815 23:53:32.383695
2816 23:53:32.383747
2817 23:53:32.383799 [DQSOSCAuto] RK0, (LSB)MR18= 0x4ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2818 23:53:32.383852 CH0 RK0: MR19=403, MR18=4FF
2819 23:53:32.383905 CH0_RK0: MR19=0x403, MR18=0x4FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2820 23:53:32.383973
2821 23:53:32.384069 ----->DramcWriteLeveling(PI) begin...
2822 23:53:32.384122 ==
2823 23:53:32.384174 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 23:53:32.384227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 23:53:32.384280 ==
2826 23:53:32.384332 Write leveling (Byte 0): 33 => 33
2827 23:53:32.384384 Write leveling (Byte 1): 27 => 27
2828 23:53:32.384451 DramcWriteLeveling(PI) end<-----
2829 23:53:32.384518
2830 23:53:32.384569 ==
2831 23:53:32.384621 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 23:53:32.384673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 23:53:32.384725 ==
2834 23:53:32.384777 [Gating] SW mode calibration
2835 23:53:32.384829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 23:53:32.384882 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 23:53:32.384949 0 15 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2838 23:53:32.385045 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 23:53:32.385098 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 23:53:32.385151 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 23:53:32.385203 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 23:53:32.385255 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 23:53:32.385356 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2844 23:53:32.385472 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2845 23:53:32.385536 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2846 23:53:32.385590 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 23:53:32.385643 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 23:53:32.385695 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 23:53:32.385764 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 23:53:32.385818 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 23:53:32.385872 1 0 24 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
2852 23:53:32.385925 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
2853 23:53:32.385978 1 1 0 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2854 23:53:32.386032 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 23:53:32.386099 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 23:53:32.386151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 23:53:32.386203 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 23:53:32.386256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2859 23:53:32.386308 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2860 23:53:32.386361 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2861 23:53:32.386443 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 23:53:32.386495 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 23:53:32.386547 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 23:53:32.386599 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 23:53:32.386666 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 23:53:32.386719 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 23:53:32.386773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 23:53:32.386826 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 23:53:32.386879 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 23:53:32.387131 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 23:53:32.387265 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 23:53:32.387394 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 23:53:32.387525 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 23:53:32.387655 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2875 23:53:32.387770 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2876 23:53:32.387829 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2877 23:53:32.387883 Total UI for P1: 0, mck2ui 16
2878 23:53:32.387939 best dqsien dly found for B0: ( 1, 3, 22)
2879 23:53:32.387994 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 23:53:32.388048 Total UI for P1: 0, mck2ui 16
2881 23:53:32.388103 best dqsien dly found for B1: ( 1, 3, 28)
2882 23:53:32.388156 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2883 23:53:32.388210 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2884 23:53:32.388264
2885 23:53:32.388317 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2886 23:53:32.388372 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2887 23:53:32.388425 [Gating] SW calibration Done
2888 23:53:32.388478 ==
2889 23:53:32.388532 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 23:53:32.388586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 23:53:32.388640 ==
2892 23:53:32.388693 RX Vref Scan: 0
2893 23:53:32.388746
2894 23:53:32.388799 RX Vref 0 -> 0, step: 1
2895 23:53:32.388853
2896 23:53:32.388907 RX Delay -40 -> 252, step: 8
2897 23:53:32.388960 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2898 23:53:32.389014 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2899 23:53:32.389067 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2900 23:53:32.389121 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2901 23:53:32.389174 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2902 23:53:32.389227 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2903 23:53:32.389290 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2904 23:53:32.389345 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2905 23:53:32.389398 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2906 23:53:32.389452 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2907 23:53:32.389505 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2908 23:53:32.389559 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2909 23:53:32.389612 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2910 23:53:32.389665 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2911 23:53:32.389719 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2912 23:53:32.389772 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2913 23:53:32.389825 ==
2914 23:53:32.389878 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 23:53:32.389932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 23:53:32.389986 ==
2917 23:53:32.390039 DQS Delay:
2918 23:53:32.390092 DQS0 = 0, DQS1 = 0
2919 23:53:32.390145 DQM Delay:
2920 23:53:32.390198 DQM0 = 115, DQM1 = 108
2921 23:53:32.390252 DQ Delay:
2922 23:53:32.390305 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2923 23:53:32.390358 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2924 23:53:32.390412 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2925 23:53:32.390465 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2926 23:53:32.390519
2927 23:53:32.390572
2928 23:53:32.390625 ==
2929 23:53:32.390678 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 23:53:32.390731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 23:53:32.390785 ==
2932 23:53:32.390838
2933 23:53:32.390891
2934 23:53:32.390944 TX Vref Scan disable
2935 23:53:32.618012 == TX Byte 0 ==
2936 23:53:32.618139 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2937 23:53:32.618205 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2938 23:53:32.618264 == TX Byte 1 ==
2939 23:53:32.618322 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2940 23:53:32.618378 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2941 23:53:32.618434 ==
2942 23:53:32.618504 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 23:53:32.618572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 23:53:32.618626 ==
2945 23:53:32.618678 TX Vref=22, minBit 12, minWin=25, winSum=418
2946 23:53:32.618733 TX Vref=24, minBit 8, minWin=25, winSum=419
2947 23:53:32.618786 TX Vref=26, minBit 1, minWin=26, winSum=423
2948 23:53:32.618839 TX Vref=28, minBit 12, minWin=26, winSum=429
2949 23:53:32.618892 TX Vref=30, minBit 12, minWin=26, winSum=429
2950 23:53:32.618945 TX Vref=32, minBit 5, minWin=26, winSum=428
2951 23:53:32.618997 [TxChooseVref] Worse bit 12, Min win 26, Win sum 429, Final Vref 28
2952 23:53:32.619065
2953 23:53:32.619118 Final TX Range 1 Vref 28
2954 23:53:32.619184
2955 23:53:32.619234 ==
2956 23:53:32.619286 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:53:32.619338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:53:32.619390 ==
2959 23:53:32.619442
2960 23:53:32.619493
2961 23:53:32.619544 TX Vref Scan disable
2962 23:53:32.619610 == TX Byte 0 ==
2963 23:53:32.619674 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2964 23:53:32.619726 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2965 23:53:32.619778 == TX Byte 1 ==
2966 23:53:32.619829 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2967 23:53:32.619933 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2968 23:53:32.620021
2969 23:53:32.620106 [DATLAT]
2970 23:53:32.620196 Freq=1200, CH0 RK1
2971 23:53:32.620260
2972 23:53:32.620314 DATLAT Default: 0xd
2973 23:53:32.620368 0, 0xFFFF, sum = 0
2974 23:53:32.620422 1, 0xFFFF, sum = 0
2975 23:53:32.620475 2, 0xFFFF, sum = 0
2976 23:53:32.620529 3, 0xFFFF, sum = 0
2977 23:53:32.620582 4, 0xFFFF, sum = 0
2978 23:53:32.620635 5, 0xFFFF, sum = 0
2979 23:53:32.620687 6, 0xFFFF, sum = 0
2980 23:53:32.620740 7, 0xFFFF, sum = 0
2981 23:53:32.620793 8, 0xFFFF, sum = 0
2982 23:53:32.620844 9, 0xFFFF, sum = 0
2983 23:53:32.620897 10, 0xFFFF, sum = 0
2984 23:53:32.620949 11, 0xFFFF, sum = 0
2985 23:53:32.621001 12, 0x0, sum = 1
2986 23:53:32.621053 13, 0x0, sum = 2
2987 23:53:32.621105 14, 0x0, sum = 3
2988 23:53:32.621157 15, 0x0, sum = 4
2989 23:53:32.621210 best_step = 13
2990 23:53:32.621269
2991 23:53:32.621356 ==
2992 23:53:32.621407 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 23:53:32.621459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 23:53:32.621511 ==
2995 23:53:32.621563 RX Vref Scan: 0
2996 23:53:32.621652
2997 23:53:32.621705 RX Vref 0 -> 0, step: 1
2998 23:53:32.621756
2999 23:53:32.621807 RX Delay -21 -> 252, step: 4
3000 23:53:32.621859 iDelay=191, Bit 0, Center 114 (51 ~ 178) 128
3001 23:53:32.621911 iDelay=191, Bit 1, Center 116 (47 ~ 186) 140
3002 23:53:32.621962 iDelay=191, Bit 2, Center 110 (43 ~ 178) 136
3003 23:53:32.622014 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3004 23:53:32.622066 iDelay=191, Bit 4, Center 118 (51 ~ 186) 136
3005 23:53:32.622117 iDelay=191, Bit 5, Center 108 (43 ~ 174) 132
3006 23:53:32.622169 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3007 23:53:32.622220 iDelay=191, Bit 7, Center 120 (55 ~ 186) 132
3008 23:53:32.622476 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3009 23:53:32.622561 iDelay=191, Bit 9, Center 92 (27 ~ 158) 132
3010 23:53:32.622615 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3011 23:53:32.622669 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3012 23:53:32.622722 iDelay=191, Bit 12, Center 112 (47 ~ 178) 132
3013 23:53:32.622775 iDelay=191, Bit 13, Center 110 (43 ~ 178) 136
3014 23:53:32.622842 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3015 23:53:32.622894 iDelay=191, Bit 15, Center 112 (47 ~ 178) 132
3016 23:53:32.622946 ==
3017 23:53:32.622998 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 23:53:32.623050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 23:53:32.623142 ==
3020 23:53:32.623226 DQS Delay:
3021 23:53:32.623313 DQS0 = 0, DQS1 = 0
3022 23:53:32.623372 DQM Delay:
3023 23:53:32.623425 DQM0 = 115, DQM1 = 106
3024 23:53:32.623477 DQ Delay:
3025 23:53:32.623529 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3026 23:53:32.623581 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
3027 23:53:32.623633 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3028 23:53:32.623684 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3029 23:53:32.623766
3030 23:53:32.623817
3031 23:53:32.623868 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3032 23:53:32.623921 CH0 RK1: MR19=303, MR18=FDFA
3033 23:53:32.624001 CH0_RK1: MR19=0x303, MR18=0xFDFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3034 23:53:32.624053 [RxdqsGatingPostProcess] freq 1200
3035 23:53:32.624105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 23:53:32.624157 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 23:53:32.624209 best DQS1 dly(2T, 0.5T) = (0, 12)
3038 23:53:32.624261 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 23:53:32.624312 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3040 23:53:32.624363 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 23:53:32.624414 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 23:53:32.624466 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 23:53:32.624517 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 23:53:32.624568 Pre-setting of DQS Precalculation
3045 23:53:32.624620 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 23:53:32.624672 ==
3047 23:53:32.624724 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 23:53:32.624776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 23:53:32.624828 ==
3050 23:53:32.624880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 23:53:32.624933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3052 23:53:32.624985 [CA 0] Center 38 (8~68) winsize 61
3053 23:53:32.625037 [CA 1] Center 37 (7~68) winsize 62
3054 23:53:32.625088 [CA 2] Center 35 (5~65) winsize 61
3055 23:53:32.625140 [CA 3] Center 34 (4~64) winsize 61
3056 23:53:32.625191 [CA 4] Center 35 (5~65) winsize 61
3057 23:53:32.625242 [CA 5] Center 33 (3~64) winsize 62
3058 23:53:32.625337
3059 23:53:32.625389 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3060 23:53:32.625441
3061 23:53:32.625492 [CATrainingPosCal] consider 1 rank data
3062 23:53:32.625543 u2DelayCellTimex100 = 270/100 ps
3063 23:53:32.625594 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3064 23:53:32.625646 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 23:53:32.625697 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 23:53:32.625748 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3067 23:53:32.625800 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3068 23:53:32.625851 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3069 23:53:32.625902
3070 23:53:32.625954 CA PerBit enable=1, Macro0, CA PI delay=33
3071 23:53:32.626006
3072 23:53:32.626058 [CBTSetCACLKResult] CA Dly = 33
3073 23:53:32.626109 CS Dly: 5 (0~36)
3074 23:53:32.626177 ==
3075 23:53:32.626274 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 23:53:32.626364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 23:53:32.626481 ==
3078 23:53:32.626566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 23:53:32.626667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 23:53:32.626739 [CA 0] Center 38 (8~68) winsize 61
3081 23:53:32.626794 [CA 1] Center 38 (7~69) winsize 63
3082 23:53:32.626846 [CA 2] Center 35 (5~65) winsize 61
3083 23:53:32.626898 [CA 3] Center 33 (4~63) winsize 60
3084 23:53:32.626950 [CA 4] Center 34 (4~64) winsize 61
3085 23:53:32.627002 [CA 5] Center 33 (3~64) winsize 62
3086 23:53:32.627054
3087 23:53:32.627106 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3088 23:53:32.627158
3089 23:53:32.627210 [CATrainingPosCal] consider 2 rank data
3090 23:53:32.627262 u2DelayCellTimex100 = 270/100 ps
3091 23:53:32.627315 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3092 23:53:32.627367 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 23:53:32.627419 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 23:53:32.627471 CA3 delay=33 (4~63),Diff = 0 PI (0 cell)
3095 23:53:32.627560 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3096 23:53:32.627612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3097 23:53:32.627664
3098 23:53:32.627715 CA PerBit enable=1, Macro0, CA PI delay=33
3099 23:53:32.627767
3100 23:53:32.627846 [CBTSetCACLKResult] CA Dly = 33
3101 23:53:32.627898 CS Dly: 6 (0~39)
3102 23:53:32.627950
3103 23:53:32.628001 ----->DramcWriteLeveling(PI) begin...
3104 23:53:32.628055 ==
3105 23:53:32.628107 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 23:53:32.628159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 23:53:32.628212 ==
3108 23:53:32.628263 Write leveling (Byte 0): 27 => 27
3109 23:53:32.628316 Write leveling (Byte 1): 27 => 27
3110 23:53:32.628368 DramcWriteLeveling(PI) end<-----
3111 23:53:32.628420
3112 23:53:32.628471 ==
3113 23:53:32.628523 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 23:53:32.628575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 23:53:32.628627 ==
3116 23:53:32.628679 [Gating] SW mode calibration
3117 23:53:32.628731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 23:53:32.628784 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 23:53:32.628837 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3120 23:53:32.628890 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 23:53:32.628942 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 23:53:32.628994 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 23:53:32.629046 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 23:53:32.629098 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 23:53:32.629149 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
3126 23:53:32.629399 0 15 28 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (1 0)
3127 23:53:32.629459 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 23:53:32.629512 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 23:53:32.629565 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 23:53:32.629618 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 23:53:32.629670 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 23:53:32.629722 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 23:53:32.629775 1 0 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
3134 23:53:32.629827 1 0 28 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3135 23:53:32.629913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 23:53:32.630033 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 23:53:32.630118 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 23:53:32.630198 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 23:53:32.630253 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 23:53:32.630307 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 23:53:32.630388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 23:53:32.630440 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3143 23:53:32.630492 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 23:53:32.630544 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 23:53:32.630596 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 23:53:32.630648 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 23:53:32.630700 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 23:53:32.630752 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 23:53:32.630804 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 23:53:32.630856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 23:53:32.630908 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 23:53:32.630960 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 23:53:32.631012 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 23:53:32.631063 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 23:53:32.631115 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 23:53:32.631167 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 23:53:32.631219 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3158 23:53:32.631271 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3159 23:53:32.631322 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 23:53:32.631374 Total UI for P1: 0, mck2ui 16
3161 23:53:32.631427 best dqsien dly found for B0: ( 1, 3, 28)
3162 23:53:32.631479 Total UI for P1: 0, mck2ui 16
3163 23:53:32.631559 best dqsien dly found for B1: ( 1, 3, 26)
3164 23:53:32.631611 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3165 23:53:32.631663 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3166 23:53:32.631715
3167 23:53:32.631767 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3168 23:53:32.631833 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 23:53:32.631899 [Gating] SW calibration Done
3170 23:53:32.631951 ==
3171 23:53:32.632003 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 23:53:32.632055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 23:53:32.632121 ==
3174 23:53:32.632187 RX Vref Scan: 0
3175 23:53:32.632238
3176 23:53:32.632289 RX Vref 0 -> 0, step: 1
3177 23:53:32.632341
3178 23:53:32.632393 RX Delay -40 -> 252, step: 8
3179 23:53:32.632445 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3180 23:53:32.632498 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3181 23:53:32.632549 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3182 23:53:32.632601 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3183 23:53:32.632653 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3184 23:53:32.632704 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3185 23:53:32.632756 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3186 23:53:32.632808 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3187 23:53:32.632861 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3188 23:53:32.632925 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3189 23:53:32.633010 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3190 23:53:32.633100 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3191 23:53:32.633186 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 23:53:32.633313 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3193 23:53:32.633370 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3194 23:53:32.633424 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3195 23:53:32.633476 ==
3196 23:53:32.633529 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 23:53:32.633582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 23:53:32.633635 ==
3199 23:53:32.633688 DQS Delay:
3200 23:53:32.633740 DQS0 = 0, DQS1 = 0
3201 23:53:32.633793 DQM Delay:
3202 23:53:32.633844 DQM0 = 115, DQM1 = 112
3203 23:53:32.633897 DQ Delay:
3204 23:53:32.633949 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3205 23:53:32.634002 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3206 23:53:32.634054 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3207 23:53:32.634107 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3208 23:53:32.634159
3209 23:53:32.634211
3210 23:53:32.634263 ==
3211 23:53:32.634314 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 23:53:32.634393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 23:53:32.634446 ==
3214 23:53:32.634498
3215 23:53:32.634550
3216 23:53:32.634602 TX Vref Scan disable
3217 23:53:32.634654 == TX Byte 0 ==
3218 23:53:32.634706 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3219 23:53:32.634759 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3220 23:53:32.634812 == TX Byte 1 ==
3221 23:53:32.634864 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3222 23:53:32.634916 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3223 23:53:32.634968 ==
3224 23:53:32.635020 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 23:53:32.635073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 23:53:32.635125 ==
3227 23:53:32.635178 TX Vref=22, minBit 9, minWin=24, winSum=409
3228 23:53:32.635230 TX Vref=24, minBit 8, minWin=25, winSum=419
3229 23:53:32.635282 TX Vref=26, minBit 10, minWin=25, winSum=423
3230 23:53:32.635335 TX Vref=28, minBit 11, minWin=25, winSum=426
3231 23:53:32.635387 TX Vref=30, minBit 2, minWin=26, winSum=427
3232 23:53:32.635439 TX Vref=32, minBit 8, minWin=26, winSum=428
3233 23:53:32.635683 [TxChooseVref] Worse bit 8, Min win 26, Win sum 428, Final Vref 32
3234 23:53:32.635743
3235 23:53:32.635798 Final TX Range 1 Vref 32
3236 23:53:32.635851
3237 23:53:32.635904 ==
3238 23:53:32.635956 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:53:32.636009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:53:32.636061 ==
3241 23:53:32.636113
3242 23:53:32.636164
3243 23:53:32.636216 TX Vref Scan disable
3244 23:53:32.636268 == TX Byte 0 ==
3245 23:53:32.636320 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3246 23:53:32.636374 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3247 23:53:32.636426 == TX Byte 1 ==
3248 23:53:32.636478 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3249 23:53:32.636530 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3250 23:53:32.636582
3251 23:53:32.636634 [DATLAT]
3252 23:53:32.636685 Freq=1200, CH1 RK0
3253 23:53:32.636738
3254 23:53:32.636790 DATLAT Default: 0xd
3255 23:53:32.636849 0, 0xFFFF, sum = 0
3256 23:53:32.636969 1, 0xFFFF, sum = 0
3257 23:53:32.637060 2, 0xFFFF, sum = 0
3258 23:53:32.637149 3, 0xFFFF, sum = 0
3259 23:53:32.637242 4, 0xFFFF, sum = 0
3260 23:53:32.637340 5, 0xFFFF, sum = 0
3261 23:53:32.637395 6, 0xFFFF, sum = 0
3262 23:53:32.637463 7, 0xFFFF, sum = 0
3263 23:53:32.637531 8, 0xFFFF, sum = 0
3264 23:53:32.637584 9, 0xFFFF, sum = 0
3265 23:53:32.637637 10, 0xFFFF, sum = 0
3266 23:53:32.637690 11, 0xFFFF, sum = 0
3267 23:53:32.637757 12, 0x0, sum = 1
3268 23:53:32.637823 13, 0x0, sum = 2
3269 23:53:32.637876 14, 0x0, sum = 3
3270 23:53:32.637929 15, 0x0, sum = 4
3271 23:53:32.637982 best_step = 13
3272 23:53:32.638033
3273 23:53:32.638085 ==
3274 23:53:32.638138 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 23:53:32.638190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 23:53:32.638243 ==
3277 23:53:32.638295 RX Vref Scan: 1
3278 23:53:32.638347
3279 23:53:32.638399 Set Vref Range= 32 -> 127
3280 23:53:32.638451
3281 23:53:32.638502 RX Vref 32 -> 127, step: 1
3282 23:53:32.638554
3283 23:53:32.638605 RX Delay -13 -> 252, step: 4
3284 23:53:32.638657
3285 23:53:32.638708 Set Vref, RX VrefLevel [Byte0]: 32
3286 23:53:32.638761 [Byte1]: 32
3287 23:53:32.638812
3288 23:53:32.638864 Set Vref, RX VrefLevel [Byte0]: 33
3289 23:53:32.638916 [Byte1]: 33
3290 23:53:32.638968
3291 23:53:32.639018 Set Vref, RX VrefLevel [Byte0]: 34
3292 23:53:32.639070 [Byte1]: 34
3293 23:53:32.639146
3294 23:53:32.639240 Set Vref, RX VrefLevel [Byte0]: 35
3295 23:53:32.639291 [Byte1]: 35
3296 23:53:32.639342
3297 23:53:32.639393 Set Vref, RX VrefLevel [Byte0]: 36
3298 23:53:32.639445 [Byte1]: 36
3299 23:53:32.639496
3300 23:53:32.639547 Set Vref, RX VrefLevel [Byte0]: 37
3301 23:53:32.639599 [Byte1]: 37
3302 23:53:32.639650
3303 23:53:32.639701 Set Vref, RX VrefLevel [Byte0]: 38
3304 23:53:32.639752 [Byte1]: 38
3305 23:53:32.639803
3306 23:53:32.639854 Set Vref, RX VrefLevel [Byte0]: 39
3307 23:53:32.639906 [Byte1]: 39
3308 23:53:32.640010
3309 23:53:32.640091 Set Vref, RX VrefLevel [Byte0]: 40
3310 23:53:32.640178 [Byte1]: 40
3311 23:53:32.640264
3312 23:53:32.640335 Set Vref, RX VrefLevel [Byte0]: 41
3313 23:53:32.640389 [Byte1]: 41
3314 23:53:32.640442
3315 23:53:32.640494 Set Vref, RX VrefLevel [Byte0]: 42
3316 23:53:32.640547 [Byte1]: 42
3317 23:53:32.640599
3318 23:53:32.640650 Set Vref, RX VrefLevel [Byte0]: 43
3319 23:53:32.640702 [Byte1]: 43
3320 23:53:32.640753
3321 23:53:32.640805 Set Vref, RX VrefLevel [Byte0]: 44
3322 23:53:32.640856 [Byte1]: 44
3323 23:53:32.640907
3324 23:53:32.640958 Set Vref, RX VrefLevel [Byte0]: 45
3325 23:53:32.641009 [Byte1]: 45
3326 23:53:32.641061
3327 23:53:32.641112 Set Vref, RX VrefLevel [Byte0]: 46
3328 23:53:32.641164 [Byte1]: 46
3329 23:53:32.641215
3330 23:53:32.641293 Set Vref, RX VrefLevel [Byte0]: 47
3331 23:53:32.641384 [Byte1]: 47
3332 23:53:32.641451
3333 23:53:32.641501 Set Vref, RX VrefLevel [Byte0]: 48
3334 23:53:32.641553 [Byte1]: 48
3335 23:53:32.641649
3336 23:53:32.641715 Set Vref, RX VrefLevel [Byte0]: 49
3337 23:53:32.641782 [Byte1]: 49
3338 23:53:32.641875
3339 23:53:32.641932 Set Vref, RX VrefLevel [Byte0]: 50
3340 23:53:32.641985 [Byte1]: 50
3341 23:53:32.642037
3342 23:53:32.642089 Set Vref, RX VrefLevel [Byte0]: 51
3343 23:53:32.642140 [Byte1]: 51
3344 23:53:32.642192
3345 23:53:32.642243 Set Vref, RX VrefLevel [Byte0]: 52
3346 23:53:32.642295 [Byte1]: 52
3347 23:53:32.642347
3348 23:53:32.642398 Set Vref, RX VrefLevel [Byte0]: 53
3349 23:53:32.642449 [Byte1]: 53
3350 23:53:32.642501
3351 23:53:32.642553 Set Vref, RX VrefLevel [Byte0]: 54
3352 23:53:32.642604 [Byte1]: 54
3353 23:53:32.642655
3354 23:53:32.642706 Set Vref, RX VrefLevel [Byte0]: 55
3355 23:53:32.642758 [Byte1]: 55
3356 23:53:32.642824
3357 23:53:32.642889 Set Vref, RX VrefLevel [Byte0]: 56
3358 23:53:32.642940 [Byte1]: 56
3359 23:53:32.642991
3360 23:53:32.643051 Set Vref, RX VrefLevel [Byte0]: 57
3361 23:53:32.643140 [Byte1]: 57
3362 23:53:32.643228
3363 23:53:32.643314 Set Vref, RX VrefLevel [Byte0]: 58
3364 23:53:32.643387 [Byte1]: 58
3365 23:53:32.643442
3366 23:53:32.643494 Set Vref, RX VrefLevel [Byte0]: 59
3367 23:53:32.643547 [Byte1]: 59
3368 23:53:32.643600
3369 23:53:32.643651 Set Vref, RX VrefLevel [Byte0]: 60
3370 23:53:32.643704 [Byte1]: 60
3371 23:53:32.643756
3372 23:53:32.643807 Set Vref, RX VrefLevel [Byte0]: 61
3373 23:53:32.643858 [Byte1]: 61
3374 23:53:32.643910
3375 23:53:32.643961 Set Vref, RX VrefLevel [Byte0]: 62
3376 23:53:32.644013 [Byte1]: 62
3377 23:53:32.644065
3378 23:53:32.644116 Set Vref, RX VrefLevel [Byte0]: 63
3379 23:53:32.644168 [Byte1]: 63
3380 23:53:32.644220
3381 23:53:32.644271 Set Vref, RX VrefLevel [Byte0]: 64
3382 23:53:32.644322 [Byte1]: 64
3383 23:53:32.644373
3384 23:53:32.644424 Set Vref, RX VrefLevel [Byte0]: 65
3385 23:53:32.644475 [Byte1]: 65
3386 23:53:32.644526
3387 23:53:32.644578 Final RX Vref Byte 0 = 49 to rank0
3388 23:53:32.644630 Final RX Vref Byte 1 = 52 to rank0
3389 23:53:32.644682 Final RX Vref Byte 0 = 49 to rank1
3390 23:53:32.644772 Final RX Vref Byte 1 = 52 to rank1==
3391 23:53:32.644824 Dram Type= 6, Freq= 0, CH_1, rank 0
3392 23:53:32.644875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3393 23:53:32.644928 ==
3394 23:53:32.644979 DQS Delay:
3395 23:53:32.645031 DQS0 = 0, DQS1 = 0
3396 23:53:32.645083 DQM Delay:
3397 23:53:32.645145 DQM0 = 115, DQM1 = 112
3398 23:53:32.645227 DQ Delay:
3399 23:53:32.645314 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3400 23:53:32.645382 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3401 23:53:32.645433 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3402 23:53:32.645485 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3403 23:53:32.645536
3404 23:53:32.645588
3405 23:53:32.645836 [DQSOSCAuto] RK0, (LSB)MR18= 0xf401, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
3406 23:53:32.645899 CH1 RK0: MR19=304, MR18=F401
3407 23:53:32.645969 CH1_RK0: MR19=0x304, MR18=0xF401, DQSOSC=409, MR23=63, INC=39, DEC=26
3408 23:53:32.646036
3409 23:53:32.646087 ----->DramcWriteLeveling(PI) begin...
3410 23:53:32.646140 ==
3411 23:53:32.646192 Dram Type= 6, Freq= 0, CH_1, rank 1
3412 23:53:32.646244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 23:53:32.646296 ==
3414 23:53:32.646348 Write leveling (Byte 0): 24 => 24
3415 23:53:32.646430 Write leveling (Byte 1): 28 => 28
3416 23:53:32.646482 DramcWriteLeveling(PI) end<-----
3417 23:53:32.646534
3418 23:53:32.646585 ==
3419 23:53:32.646651 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 23:53:32.646706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 23:53:32.646801 ==
3422 23:53:32.646888 [Gating] SW mode calibration
3423 23:53:32.646973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3424 23:53:32.647064 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3425 23:53:32.647124 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 23:53:32.647179 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 23:53:32.647232 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 23:53:32.647284 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 23:53:32.647336 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 23:53:32.647389 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3431 23:53:32.647441 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
3432 23:53:32.647492 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
3433 23:53:32.647544 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 23:53:32.647596 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 23:53:32.647647 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 23:53:32.647700 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 23:53:32.647751 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 23:53:32.647803 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3439 23:53:32.647854 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3440 23:53:32.647906 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
3441 23:53:32.647957 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 23:53:32.648009 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 23:53:32.648060 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 23:53:32.648112 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 23:53:32.648163 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 23:53:32.648215 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3447 23:53:32.648266 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3448 23:53:32.648318 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3449 23:53:32.648369 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 23:53:32.648420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 23:53:32.648471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 23:53:32.648523 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 23:53:32.648574 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 23:53:32.648626 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 23:53:32.648678 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 23:53:32.648730 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 23:53:32.648782 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 23:53:32.648833 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 23:53:32.648884 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 23:53:32.648935 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:53:32.648986 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:53:32.649037 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3463 23:53:32.649089 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3464 23:53:32.649140 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3465 23:53:32.649192 Total UI for P1: 0, mck2ui 16
3466 23:53:32.649244 best dqsien dly found for B0: ( 1, 3, 22)
3467 23:53:32.649334 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 23:53:32.649386 Total UI for P1: 0, mck2ui 16
3469 23:53:32.649439 best dqsien dly found for B1: ( 1, 3, 28)
3470 23:53:32.649491 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3471 23:53:32.649542 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3472 23:53:32.649608
3473 23:53:32.649689 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3474 23:53:32.649771 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3475 23:53:32.649837 [Gating] SW calibration Done
3476 23:53:32.649893 ==
3477 23:53:32.649981 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 23:53:32.650074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 23:53:32.650158 ==
3480 23:53:32.650264 RX Vref Scan: 0
3481 23:53:32.650318
3482 23:53:32.650371 RX Vref 0 -> 0, step: 1
3483 23:53:32.650423
3484 23:53:32.650475 RX Delay -40 -> 252, step: 8
3485 23:53:32.650527 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3486 23:53:32.650579 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3487 23:53:32.650631 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3488 23:53:32.650683 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3489 23:53:32.650734 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3490 23:53:32.650803 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3491 23:53:32.650870 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3492 23:53:32.650923 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3493 23:53:32.650974 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3494 23:53:32.651026 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3495 23:53:32.651078 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3496 23:53:32.651130 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3497 23:53:32.651181 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3498 23:53:32.651232 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3499 23:53:32.651284 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3500 23:53:32.651335 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3501 23:53:32.651387 ==
3502 23:53:32.651438 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 23:53:32.651686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 23:53:32.651745 ==
3505 23:53:32.651797 DQS Delay:
3506 23:53:32.651850 DQS0 = 0, DQS1 = 0
3507 23:53:32.651902 DQM Delay:
3508 23:53:32.651953 DQM0 = 114, DQM1 = 111
3509 23:53:32.652004 DQ Delay:
3510 23:53:32.652056 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3511 23:53:32.652108 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3512 23:53:32.652159 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3513 23:53:32.652211 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3514 23:53:32.652262
3515 23:53:32.652313
3516 23:53:32.652363 ==
3517 23:53:32.652415 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 23:53:32.652466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 23:53:32.652518 ==
3520 23:53:32.652570
3521 23:53:32.652621
3522 23:53:32.652671 TX Vref Scan disable
3523 23:53:32.652722 == TX Byte 0 ==
3524 23:53:32.652773 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3525 23:53:32.652825 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3526 23:53:32.652876 == TX Byte 1 ==
3527 23:53:32.652927 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3528 23:53:32.652978 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3529 23:53:32.653030 ==
3530 23:53:32.653102 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 23:53:32.653189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 23:53:32.653315 ==
3533 23:53:32.653405 TX Vref=22, minBit 3, minWin=25, winSum=421
3534 23:53:32.653493 TX Vref=24, minBit 1, minWin=26, winSum=425
3535 23:53:32.653562 TX Vref=26, minBit 3, minWin=25, winSum=426
3536 23:53:32.653618 TX Vref=28, minBit 3, minWin=26, winSum=430
3537 23:53:32.653672 TX Vref=30, minBit 1, minWin=26, winSum=436
3538 23:53:32.653725 TX Vref=32, minBit 10, minWin=26, winSum=434
3539 23:53:32.653778 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 30
3540 23:53:32.653831
3541 23:53:32.653883 Final TX Range 1 Vref 30
3542 23:53:32.653935
3543 23:53:32.653987 ==
3544 23:53:32.654039 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 23:53:32.654091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 23:53:32.654143 ==
3547 23:53:32.654194
3548 23:53:32.654245
3549 23:53:32.654296 TX Vref Scan disable
3550 23:53:32.654348 == TX Byte 0 ==
3551 23:53:32.654399 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3552 23:53:32.654451 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3553 23:53:32.654502 == TX Byte 1 ==
3554 23:53:32.654554 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 23:53:32.654606 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 23:53:32.654658
3557 23:53:32.654709 [DATLAT]
3558 23:53:32.654760 Freq=1200, CH1 RK1
3559 23:53:32.654812
3560 23:53:32.654864 DATLAT Default: 0xd
3561 23:53:32.654916 0, 0xFFFF, sum = 0
3562 23:53:32.654969 1, 0xFFFF, sum = 0
3563 23:53:32.655021 2, 0xFFFF, sum = 0
3564 23:53:32.655073 3, 0xFFFF, sum = 0
3565 23:53:32.655141 4, 0xFFFF, sum = 0
3566 23:53:32.655207 5, 0xFFFF, sum = 0
3567 23:53:32.655279 6, 0xFFFF, sum = 0
3568 23:53:32.655345 7, 0xFFFF, sum = 0
3569 23:53:32.655398 8, 0xFFFF, sum = 0
3570 23:53:32.655450 9, 0xFFFF, sum = 0
3571 23:53:32.655502 10, 0xFFFF, sum = 0
3572 23:53:32.655555 11, 0xFFFF, sum = 0
3573 23:53:32.655607 12, 0x0, sum = 1
3574 23:53:32.655682 13, 0x0, sum = 2
3575 23:53:32.655748 14, 0x0, sum = 3
3576 23:53:32.655800 15, 0x0, sum = 4
3577 23:53:32.655852 best_step = 13
3578 23:53:32.655903
3579 23:53:32.655953 ==
3580 23:53:32.656005 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 23:53:32.656056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 23:53:32.656108 ==
3583 23:53:32.656159 RX Vref Scan: 0
3584 23:53:32.656210
3585 23:53:32.656261 RX Vref 0 -> 0, step: 1
3586 23:53:32.656313
3587 23:53:32.656364 RX Delay -13 -> 252, step: 4
3588 23:53:32.656415 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3589 23:53:32.656467 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3590 23:53:32.656518 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3591 23:53:32.656570 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3592 23:53:32.656621 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3593 23:53:32.656672 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3594 23:53:32.656723 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3595 23:53:32.656774 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3596 23:53:32.656825 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3597 23:53:32.656877 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3598 23:53:32.656928 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3599 23:53:32.657002 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3600 23:53:32.657067 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3601 23:53:32.657119 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3602 23:53:32.657170 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3603 23:53:32.657222 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3604 23:53:32.657302 ==
3605 23:53:32.657368 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 23:53:32.657420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 23:53:32.657472 ==
3608 23:53:32.657524 DQS Delay:
3609 23:53:32.657575 DQS0 = 0, DQS1 = 0
3610 23:53:32.657626 DQM Delay:
3611 23:53:32.657686 DQM0 = 114, DQM1 = 112
3612 23:53:32.657738 DQ Delay:
3613 23:53:32.657790 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3614 23:53:32.657843 DQ4 =114, DQ5 =122, DQ6 =120, DQ7 =110
3615 23:53:32.657895 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3616 23:53:32.657946 DQ12 =120, DQ13 =116, DQ14 =114, DQ15 =122
3617 23:53:32.657997
3618 23:53:32.658048
3619 23:53:32.658100 [DQSOSCAuto] RK1, (LSB)MR18= 0xf508, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3620 23:53:32.658153 CH1 RK1: MR19=304, MR18=F508
3621 23:53:32.658205 CH1_RK1: MR19=0x304, MR18=0xF508, DQSOSC=406, MR23=63, INC=39, DEC=26
3622 23:53:32.658256 [RxdqsGatingPostProcess] freq 1200
3623 23:53:32.658308 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3624 23:53:32.658360 best DQS0 dly(2T, 0.5T) = (0, 11)
3625 23:53:32.658414 best DQS1 dly(2T, 0.5T) = (0, 11)
3626 23:53:32.658466 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3627 23:53:32.658517 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3628 23:53:32.658568 best DQS0 dly(2T, 0.5T) = (0, 11)
3629 23:53:32.658620 best DQS1 dly(2T, 0.5T) = (0, 11)
3630 23:53:32.658671 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3631 23:53:32.658722 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3632 23:53:32.658773 Pre-setting of DQS Precalculation
3633 23:53:32.658825 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3634 23:53:32.658877 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3635 23:53:32.658929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3636 23:53:32.658981
3637 23:53:32.659032
3638 23:53:32.659083 [Calibration Summary] 2400 Mbps
3639 23:53:32.659135 CH 0, Rank 0
3640 23:53:32.659223 SW Impedance : PASS
3641 23:53:32.659306 DUTY Scan : NO K
3642 23:53:32.659384 ZQ Calibration : PASS
3643 23:53:32.659439 Jitter Meter : NO K
3644 23:53:32.659697 CBT Training : PASS
3645 23:53:32.659831 Write leveling : PASS
3646 23:53:32.659893 RX DQS gating : PASS
3647 23:53:32.659948 RX DQ/DQS(RDDQC) : PASS
3648 23:53:32.660000 TX DQ/DQS : PASS
3649 23:53:32.660052 RX DATLAT : PASS
3650 23:53:32.660104 RX DQ/DQS(Engine): PASS
3651 23:53:32.660170 TX OE : NO K
3652 23:53:32.660236 All Pass.
3653 23:53:32.660289
3654 23:53:32.660349 CH 0, Rank 1
3655 23:53:32.660408 SW Impedance : PASS
3656 23:53:32.660492 DUTY Scan : NO K
3657 23:53:32.660575 ZQ Calibration : PASS
3658 23:53:32.660662 Jitter Meter : NO K
3659 23:53:32.660745 CBT Training : PASS
3660 23:53:32.660830 Write leveling : PASS
3661 23:53:32.660911 RX DQS gating : PASS
3662 23:53:32.660997 RX DQ/DQS(RDDQC) : PASS
3663 23:53:32.661082 TX DQ/DQS : PASS
3664 23:53:32.661166 RX DATLAT : PASS
3665 23:53:32.661251 RX DQ/DQS(Engine): PASS
3666 23:53:32.661373 TX OE : NO K
3667 23:53:32.661455 All Pass.
3668 23:53:32.661538
3669 23:53:32.661619 CH 1, Rank 0
3670 23:53:32.661704 SW Impedance : PASS
3671 23:53:32.661786 DUTY Scan : NO K
3672 23:53:32.661849 ZQ Calibration : PASS
3673 23:53:32.661905 Jitter Meter : NO K
3674 23:53:32.661958 CBT Training : PASS
3675 23:53:32.662010 Write leveling : PASS
3676 23:53:32.662062 RX DQS gating : PASS
3677 23:53:32.662149 RX DQ/DQS(RDDQC) : PASS
3678 23:53:32.662237 TX DQ/DQS : PASS
3679 23:53:32.662326 RX DATLAT : PASS
3680 23:53:32.662415 RX DQ/DQS(Engine): PASS
3681 23:53:32.662484 TX OE : NO K
3682 23:53:32.662548 All Pass.
3683 23:53:32.662630
3684 23:53:32.662700 CH 1, Rank 1
3685 23:53:32.662759 SW Impedance : PASS
3686 23:53:32.662842 DUTY Scan : NO K
3687 23:53:32.662912 ZQ Calibration : PASS
3688 23:53:32.662999 Jitter Meter : NO K
3689 23:53:32.663085 CBT Training : PASS
3690 23:53:32.663208 Write leveling : PASS
3691 23:53:32.663335 RX DQS gating : PASS
3692 23:53:32.663417 RX DQ/DQS(RDDQC) : PASS
3693 23:53:32.663511 TX DQ/DQS : PASS
3694 23:53:32.663621 RX DATLAT : PASS
3695 23:53:32.663739 RX DQ/DQS(Engine): PASS
3696 23:53:32.663823 TX OE : NO K
3697 23:53:32.663904 All Pass.
3698 23:53:32.663983
3699 23:53:32.664063 DramC Write-DBI off
3700 23:53:32.664144 PER_BANK_REFRESH: Hybrid Mode
3701 23:53:32.664224 TX_TRACKING: ON
3702 23:53:32.664307 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3703 23:53:32.664389 [FAST_K] Save calibration result to emmc
3704 23:53:32.664470 dramc_set_vcore_voltage set vcore to 650000
3705 23:53:32.664550 Read voltage for 600, 5
3706 23:53:32.664630 Vio18 = 0
3707 23:53:32.664710 Vcore = 650000
3708 23:53:32.664790 Vdram = 0
3709 23:53:32.664870 Vddq = 0
3710 23:53:32.664949 Vmddr = 0
3711 23:53:32.665030 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3712 23:53:32.665112 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3713 23:53:32.665192 MEM_TYPE=3, freq_sel=19
3714 23:53:32.665308 sv_algorithm_assistance_LP4_1600
3715 23:53:32.665391 ============ PULL DRAM RESETB DOWN ============
3716 23:53:32.665472 ========== PULL DRAM RESETB DOWN end =========
3717 23:53:32.665554 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3718 23:53:32.665635 ===================================
3719 23:53:32.665716 LPDDR4 DRAM CONFIGURATION
3720 23:53:32.665797 ===================================
3721 23:53:32.665877 EX_ROW_EN[0] = 0x0
3722 23:53:32.665957 EX_ROW_EN[1] = 0x0
3723 23:53:32.666037 LP4Y_EN = 0x0
3724 23:53:32.666118 WORK_FSP = 0x0
3725 23:53:32.666199 WL = 0x2
3726 23:53:32.666287 RL = 0x2
3727 23:53:32.666378 BL = 0x2
3728 23:53:32.666460 RPST = 0x0
3729 23:53:32.666539 RD_PRE = 0x0
3730 23:53:32.666594 WR_PRE = 0x1
3731 23:53:32.666646 WR_PST = 0x0
3732 23:53:32.666698 DBI_WR = 0x0
3733 23:53:32.666750 DBI_RD = 0x0
3734 23:53:32.666802 OTF = 0x1
3735 23:53:32.666854 ===================================
3736 23:53:32.666906 ===================================
3737 23:53:32.666959 ANA top config
3738 23:53:32.667012 ===================================
3739 23:53:32.667064 DLL_ASYNC_EN = 0
3740 23:53:32.667115 ALL_SLAVE_EN = 1
3741 23:53:32.667167 NEW_RANK_MODE = 1
3742 23:53:32.667219 DLL_IDLE_MODE = 1
3743 23:53:32.667270 LP45_APHY_COMB_EN = 1
3744 23:53:32.667320 TX_ODT_DIS = 1
3745 23:53:32.667372 NEW_8X_MODE = 1
3746 23:53:32.667424 ===================================
3747 23:53:32.667475 ===================================
3748 23:53:32.667526 data_rate = 1200
3749 23:53:32.667578 CKR = 1
3750 23:53:32.667629 DQ_P2S_RATIO = 8
3751 23:53:32.667681 ===================================
3752 23:53:32.667732 CA_P2S_RATIO = 8
3753 23:53:32.667783 DQ_CA_OPEN = 0
3754 23:53:32.667834 DQ_SEMI_OPEN = 0
3755 23:53:32.667946 CA_SEMI_OPEN = 0
3756 23:53:32.667997 CA_FULL_RATE = 0
3757 23:53:32.668048 DQ_CKDIV4_EN = 1
3758 23:53:32.668100 CA_CKDIV4_EN = 1
3759 23:53:32.668150 CA_PREDIV_EN = 0
3760 23:53:32.668201 PH8_DLY = 0
3761 23:53:32.668252 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3762 23:53:32.668303 DQ_AAMCK_DIV = 4
3763 23:53:32.668355 CA_AAMCK_DIV = 4
3764 23:53:32.668406 CA_ADMCK_DIV = 4
3765 23:53:32.668457 DQ_TRACK_CA_EN = 0
3766 23:53:32.668508 CA_PICK = 600
3767 23:53:32.668559 CA_MCKIO = 600
3768 23:53:32.668611 MCKIO_SEMI = 0
3769 23:53:32.668662 PLL_FREQ = 2288
3770 23:53:32.668713 DQ_UI_PI_RATIO = 32
3771 23:53:32.668764 CA_UI_PI_RATIO = 0
3772 23:53:32.668827 ===================================
3773 23:53:32.668914 ===================================
3774 23:53:32.669003 memory_type:LPDDR4
3775 23:53:32.669088 GP_NUM : 10
3776 23:53:32.669179 SRAM_EN : 1
3777 23:53:32.669283 MD32_EN : 0
3778 23:53:32.669354 ===================================
3779 23:53:32.669408 [ANA_INIT] >>>>>>>>>>>>>>
3780 23:53:32.669459 <<<<<< [CONFIGURE PHASE]: ANA_TX
3781 23:53:32.669512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3782 23:53:32.669564 ===================================
3783 23:53:32.669616 data_rate = 1200,PCW = 0X5800
3784 23:53:32.669697 ===================================
3785 23:53:32.669749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3786 23:53:32.669802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3787 23:53:32.669854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 23:53:32.669906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3789 23:53:32.670152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3790 23:53:32.670211 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3791 23:53:32.670265 [ANA_INIT] flow start
3792 23:53:32.670316 [ANA_INIT] PLL >>>>>>>>
3793 23:53:32.670368 [ANA_INIT] PLL <<<<<<<<
3794 23:53:32.670419 [ANA_INIT] MIDPI >>>>>>>>
3795 23:53:32.670470 [ANA_INIT] MIDPI <<<<<<<<
3796 23:53:32.670522 [ANA_INIT] DLL >>>>>>>>
3797 23:53:32.670573 [ANA_INIT] flow end
3798 23:53:32.670623 ============ LP4 DIFF to SE enter ============
3799 23:53:32.670675 ============ LP4 DIFF to SE exit ============
3800 23:53:32.670727 [ANA_INIT] <<<<<<<<<<<<<
3801 23:53:32.670778 [Flow] Enable top DCM control >>>>>
3802 23:53:32.670842 [Flow] Enable top DCM control <<<<<
3803 23:53:32.670935 Enable DLL master slave shuffle
3804 23:53:32.670986 ==============================================================
3805 23:53:32.671038 Gating Mode config
3806 23:53:32.671089 ==============================================================
3807 23:53:32.671140 Config description:
3808 23:53:32.671191 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3809 23:53:32.671243 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3810 23:53:32.671295 SELPH_MODE 0: By rank 1: By Phase
3811 23:53:32.671346 ==============================================================
3812 23:53:32.671397 GAT_TRACK_EN = 1
3813 23:53:32.671449 RX_GATING_MODE = 2
3814 23:53:32.671500 RX_GATING_TRACK_MODE = 2
3815 23:53:32.671551 SELPH_MODE = 1
3816 23:53:32.671601 PICG_EARLY_EN = 1
3817 23:53:32.671652 VALID_LAT_VALUE = 1
3818 23:53:32.671703 ==============================================================
3819 23:53:32.671754 Enter into Gating configuration >>>>
3820 23:53:32.671805 Exit from Gating configuration <<<<
3821 23:53:32.671856 Enter into DVFS_PRE_config >>>>>
3822 23:53:32.671936 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3823 23:53:32.672017 Exit from DVFS_PRE_config <<<<<
3824 23:53:32.672069 Enter into PICG configuration >>>>
3825 23:53:32.672120 Exit from PICG configuration <<<<
3826 23:53:32.672171 [RX_INPUT] configuration >>>>>
3827 23:53:32.672222 [RX_INPUT] configuration <<<<<
3828 23:53:32.673468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3829 23:53:32.676649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3830 23:53:32.683027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3831 23:53:32.689880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3832 23:53:32.696201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3833 23:53:32.702377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3834 23:53:32.706057 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3835 23:53:32.708966 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3836 23:53:32.712608 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3837 23:53:32.718854 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3838 23:53:32.722627 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3839 23:53:32.725656 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 23:53:32.728986 ===================================
3841 23:53:32.732311 LPDDR4 DRAM CONFIGURATION
3842 23:53:32.735215 ===================================
3843 23:53:32.739097 EX_ROW_EN[0] = 0x0
3844 23:53:32.739179 EX_ROW_EN[1] = 0x0
3845 23:53:32.742103 LP4Y_EN = 0x0
3846 23:53:32.742187 WORK_FSP = 0x0
3847 23:53:32.745408 WL = 0x2
3848 23:53:32.745508 RL = 0x2
3849 23:53:32.748524 BL = 0x2
3850 23:53:32.748605 RPST = 0x0
3851 23:53:32.752216 RD_PRE = 0x0
3852 23:53:32.752317 WR_PRE = 0x1
3853 23:53:32.755354 WR_PST = 0x0
3854 23:53:32.755435 DBI_WR = 0x0
3855 23:53:32.758354 DBI_RD = 0x0
3856 23:53:32.762183 OTF = 0x1
3857 23:53:32.765163 ===================================
3858 23:53:32.768199 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3859 23:53:32.772148 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3860 23:53:32.774975 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 23:53:32.778109 ===================================
3862 23:53:32.781760 LPDDR4 DRAM CONFIGURATION
3863 23:53:32.784697 ===================================
3864 23:53:32.787817 EX_ROW_EN[0] = 0x10
3865 23:53:32.787890 EX_ROW_EN[1] = 0x0
3866 23:53:32.791605 LP4Y_EN = 0x0
3867 23:53:32.791687 WORK_FSP = 0x0
3868 23:53:32.794539 WL = 0x2
3869 23:53:32.794671 RL = 0x2
3870 23:53:32.797734 BL = 0x2
3871 23:53:32.797815 RPST = 0x0
3872 23:53:32.801717 RD_PRE = 0x0
3873 23:53:32.801800 WR_PRE = 0x1
3874 23:53:32.804856 WR_PST = 0x0
3875 23:53:32.807916 DBI_WR = 0x0
3876 23:53:32.807990 DBI_RD = 0x0
3877 23:53:32.811264 OTF = 0x1
3878 23:53:32.814470 ===================================
3879 23:53:32.818229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3880 23:53:32.823044 nWR fixed to 30
3881 23:53:32.826550 [ModeRegInit_LP4] CH0 RK0
3882 23:53:32.826622 [ModeRegInit_LP4] CH0 RK1
3883 23:53:32.829774 [ModeRegInit_LP4] CH1 RK0
3884 23:53:32.833104 [ModeRegInit_LP4] CH1 RK1
3885 23:53:32.833186 match AC timing 17
3886 23:53:32.839594 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3887 23:53:32.842716 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3888 23:53:32.846418 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3889 23:53:32.852825 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3890 23:53:32.855830 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3891 23:53:32.855956 ==
3892 23:53:32.859127 Dram Type= 6, Freq= 0, CH_0, rank 0
3893 23:53:32.862790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3894 23:53:32.862872 ==
3895 23:53:32.869729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3896 23:53:32.875571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3897 23:53:32.878971 [CA 0] Center 36 (6~67) winsize 62
3898 23:53:32.882658 [CA 1] Center 36 (5~67) winsize 63
3899 23:53:32.885684 [CA 2] Center 34 (4~65) winsize 62
3900 23:53:32.889408 [CA 3] Center 34 (3~65) winsize 63
3901 23:53:32.892565 [CA 4] Center 33 (3~64) winsize 62
3902 23:53:32.895901 [CA 5] Center 33 (3~64) winsize 62
3903 23:53:32.895982
3904 23:53:32.898873 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3905 23:53:32.898983
3906 23:53:32.902067 [CATrainingPosCal] consider 1 rank data
3907 23:53:32.905361 u2DelayCellTimex100 = 270/100 ps
3908 23:53:32.909057 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3909 23:53:32.912111 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3910 23:53:32.915277 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3911 23:53:32.921969 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3912 23:53:32.925636 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3913 23:53:32.928578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3914 23:53:32.928660
3915 23:53:32.931814 CA PerBit enable=1, Macro0, CA PI delay=33
3916 23:53:32.931897
3917 23:53:32.935576 [CBTSetCACLKResult] CA Dly = 33
3918 23:53:32.935657 CS Dly: 4 (0~35)
3919 23:53:32.935722 ==
3920 23:53:32.938774 Dram Type= 6, Freq= 0, CH_0, rank 1
3921 23:53:32.945370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3922 23:53:32.945467 ==
3923 23:53:32.948246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3924 23:53:32.954911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3925 23:53:32.958864 [CA 0] Center 36 (6~67) winsize 62
3926 23:53:32.962020 [CA 1] Center 36 (6~67) winsize 62
3927 23:53:32.965035 [CA 2] Center 34 (4~65) winsize 62
3928 23:53:32.968013 [CA 3] Center 34 (4~65) winsize 62
3929 23:53:32.971851 [CA 4] Center 34 (3~65) winsize 63
3930 23:53:32.974685 [CA 5] Center 33 (3~64) winsize 62
3931 23:53:32.974768
3932 23:53:32.978360 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3933 23:53:32.978443
3934 23:53:32.981598 [CATrainingPosCal] consider 2 rank data
3935 23:53:32.984637 u2DelayCellTimex100 = 270/100 ps
3936 23:53:32.987939 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 23:53:32.994934 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 23:53:32.998073 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 23:53:33.000943 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 23:53:33.004621 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 23:53:33.007873 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 23:53:33.007956
3943 23:53:33.010936 CA PerBit enable=1, Macro0, CA PI delay=33
3944 23:53:33.011018
3945 23:53:33.014143 [CBTSetCACLKResult] CA Dly = 33
3946 23:53:33.017991 CS Dly: 5 (0~38)
3947 23:53:33.018074
3948 23:53:33.021040 ----->DramcWriteLeveling(PI) begin...
3949 23:53:33.021140 ==
3950 23:53:33.024254 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 23:53:33.027290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 23:53:33.027372 ==
3953 23:53:33.030920 Write leveling (Byte 0): 34 => 34
3954 23:53:33.033821 Write leveling (Byte 1): 30 => 30
3955 23:53:33.037556 DramcWriteLeveling(PI) end<-----
3956 23:53:33.037654
3957 23:53:33.037718 ==
3958 23:53:33.040626 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 23:53:33.043795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 23:53:33.043908 ==
3961 23:53:33.047471 [Gating] SW mode calibration
3962 23:53:33.053833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3963 23:53:33.060083 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3964 23:53:33.063620 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 23:53:33.070072 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 23:53:33.073839 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 23:53:33.077003 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3968 23:53:33.083417 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
3969 23:53:33.087060 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 23:53:33.090224 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 23:53:33.096503 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 23:53:33.099562 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 23:53:33.103187 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 23:53:33.109932 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 23:53:33.113207 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3976 23:53:33.116330 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
3977 23:53:33.123084 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 23:53:33.126192 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 23:53:33.129340 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 23:53:33.135699 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 23:53:33.139414 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 23:53:33.142665 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 23:53:33.149400 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 23:53:33.152581 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3985 23:53:33.155841 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 23:53:33.162120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 23:53:33.165773 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 23:53:33.168816 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 23:53:33.175538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 23:53:33.178519 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 23:53:33.182473 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 23:53:33.188520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 23:53:33.192417 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:53:33.195812 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:53:33.202066 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:53:33.205207 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:53:33.208378 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:53:33.215167 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:53:33.218798 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4000 23:53:33.221420 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 23:53:33.224945 Total UI for P1: 0, mck2ui 16
4002 23:53:33.227951 best dqsien dly found for B0: ( 0, 13, 12)
4003 23:53:33.231727 Total UI for P1: 0, mck2ui 16
4004 23:53:33.235110 best dqsien dly found for B1: ( 0, 13, 14)
4005 23:53:33.238120 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4006 23:53:33.241486 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4007 23:53:33.241567
4008 23:53:33.248456 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4009 23:53:33.251385 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4010 23:53:33.254699 [Gating] SW calibration Done
4011 23:53:33.254780 ==
4012 23:53:33.257728 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 23:53:33.260894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 23:53:33.260975 ==
4015 23:53:33.261038 RX Vref Scan: 0
4016 23:53:33.261098
4017 23:53:33.264624 RX Vref 0 -> 0, step: 1
4018 23:53:33.264705
4019 23:53:33.267791 RX Delay -230 -> 252, step: 16
4020 23:53:33.271105 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4021 23:53:33.274272 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4022 23:53:33.280928 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4023 23:53:33.284474 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4024 23:53:33.287381 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4025 23:53:33.290528 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4026 23:53:33.297766 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4027 23:53:33.300862 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4028 23:53:33.303951 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4029 23:53:33.307170 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4030 23:53:33.313650 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4031 23:53:33.316827 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4032 23:53:33.320632 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4033 23:53:33.323321 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4034 23:53:33.330732 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4035 23:53:33.333504 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4036 23:53:33.333586 ==
4037 23:53:33.336944 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 23:53:33.340152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 23:53:33.340235 ==
4040 23:53:33.343304 DQS Delay:
4041 23:53:33.343384 DQS0 = 0, DQS1 = 0
4042 23:53:33.343448 DQM Delay:
4043 23:53:33.346609 DQM0 = 42, DQM1 = 33
4044 23:53:33.346690 DQ Delay:
4045 23:53:33.349802 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4046 23:53:33.353505 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4047 23:53:33.356810 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4048 23:53:33.360116 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4049 23:53:33.360197
4050 23:53:33.360261
4051 23:53:33.360356 ==
4052 23:53:33.363167 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 23:53:33.369749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 23:53:33.369832 ==
4055 23:53:33.369896
4056 23:53:33.369955
4057 23:53:33.372784 TX Vref Scan disable
4058 23:53:33.372865 == TX Byte 0 ==
4059 23:53:33.376029 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4060 23:53:33.382991 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4061 23:53:33.383073 == TX Byte 1 ==
4062 23:53:33.389187 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4063 23:53:33.393067 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4064 23:53:33.393149 ==
4065 23:53:33.396017 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 23:53:33.399236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 23:53:33.399337 ==
4068 23:53:33.399401
4069 23:53:33.399461
4070 23:53:33.402655 TX Vref Scan disable
4071 23:53:33.406216 == TX Byte 0 ==
4072 23:53:33.409328 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4073 23:53:33.412593 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4074 23:53:33.415807 == TX Byte 1 ==
4075 23:53:33.419083 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4076 23:53:33.422363 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4077 23:53:33.422461
4078 23:53:33.426093 [DATLAT]
4079 23:53:33.426174 Freq=600, CH0 RK0
4080 23:53:33.426238
4081 23:53:33.429057 DATLAT Default: 0x9
4082 23:53:33.429168 0, 0xFFFF, sum = 0
4083 23:53:33.432609 1, 0xFFFF, sum = 0
4084 23:53:33.432751 2, 0xFFFF, sum = 0
4085 23:53:33.435601 3, 0xFFFF, sum = 0
4086 23:53:33.435695 4, 0xFFFF, sum = 0
4087 23:53:33.438962 5, 0xFFFF, sum = 0
4088 23:53:33.442535 6, 0xFFFF, sum = 0
4089 23:53:33.442652 7, 0xFFFF, sum = 0
4090 23:53:33.442735 8, 0x0, sum = 1
4091 23:53:33.445733 9, 0x0, sum = 2
4092 23:53:33.445816 10, 0x0, sum = 3
4093 23:53:33.448790 11, 0x0, sum = 4
4094 23:53:33.448897 best_step = 9
4095 23:53:33.448975
4096 23:53:33.449116 ==
4097 23:53:33.452092 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 23:53:33.458407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 23:53:33.458498 ==
4100 23:53:33.458566 RX Vref Scan: 1
4101 23:53:33.458625
4102 23:53:33.462310 RX Vref 0 -> 0, step: 1
4103 23:53:33.462421
4104 23:53:33.465421 RX Delay -195 -> 252, step: 8
4105 23:53:33.465505
4106 23:53:33.468621 Set Vref, RX VrefLevel [Byte0]: 51
4107 23:53:33.472012 [Byte1]: 59
4108 23:53:33.472100
4109 23:53:33.475079 Final RX Vref Byte 0 = 51 to rank0
4110 23:53:33.478310 Final RX Vref Byte 1 = 59 to rank0
4111 23:53:33.481784 Final RX Vref Byte 0 = 51 to rank1
4112 23:53:33.485103 Final RX Vref Byte 1 = 59 to rank1==
4113 23:53:33.488245 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 23:53:33.491280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 23:53:33.491361 ==
4116 23:53:33.494861 DQS Delay:
4117 23:53:33.494942 DQS0 = 0, DQS1 = 0
4118 23:53:33.498023 DQM Delay:
4119 23:53:33.498141 DQM0 = 41, DQM1 = 32
4120 23:53:33.501186 DQ Delay:
4121 23:53:33.501287 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4122 23:53:33.504860 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4123 23:53:33.508110 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4124 23:53:33.511258 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4125 23:53:33.514427
4126 23:53:33.514508
4127 23:53:33.521275 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4128 23:53:33.524252 CH0 RK0: MR19=808, MR18=4D45
4129 23:53:33.530871 CH0_RK0: MR19=0x808, MR18=0x4D45, DQSOSC=395, MR23=63, INC=168, DEC=112
4130 23:53:33.530955
4131 23:53:33.534679 ----->DramcWriteLeveling(PI) begin...
4132 23:53:33.534761 ==
4133 23:53:33.537555 Dram Type= 6, Freq= 0, CH_0, rank 1
4134 23:53:33.540644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 23:53:33.540742 ==
4136 23:53:33.544611 Write leveling (Byte 0): 33 => 33
4137 23:53:33.547671 Write leveling (Byte 1): 31 => 31
4138 23:53:33.550576 DramcWriteLeveling(PI) end<-----
4139 23:53:33.550657
4140 23:53:33.550722 ==
4141 23:53:33.554327 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 23:53:33.557183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 23:53:33.557287 ==
4144 23:53:33.560346 [Gating] SW mode calibration
4145 23:53:33.567341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4146 23:53:33.573872 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4147 23:53:33.577001 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 23:53:33.583907 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 23:53:33.587259 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 23:53:33.589902 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
4151 23:53:33.596468 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
4152 23:53:33.600272 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 23:53:33.603540 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 23:53:33.609890 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 23:53:33.612995 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 23:53:33.616216 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 23:53:33.623229 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 23:53:33.626229 0 10 12 | B1->B0 | 2828 3636 | 0 0 | (1 1) (0 0)
4159 23:53:33.629735 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
4160 23:53:33.635999 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 23:53:33.639414 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 23:53:33.642996 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 23:53:33.649630 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 23:53:33.652827 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 23:53:33.655833 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 23:53:33.662876 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4167 23:53:33.666121 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 23:53:33.669362 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 23:53:33.675578 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 23:53:33.679234 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 23:53:33.682253 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 23:53:33.688966 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 23:53:33.692283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 23:53:33.695541 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 23:53:33.702376 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 23:53:33.705617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 23:53:33.708713 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 23:53:33.715132 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 23:53:33.718282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 23:53:33.722077 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:53:33.728281 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4182 23:53:33.731663 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:53:33.735113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4184 23:53:33.741721 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 23:53:33.741803 Total UI for P1: 0, mck2ui 16
4186 23:53:33.748380 best dqsien dly found for B0: ( 0, 13, 16)
4187 23:53:33.748465 Total UI for P1: 0, mck2ui 16
4188 23:53:33.754788 best dqsien dly found for B1: ( 0, 13, 16)
4189 23:53:33.757894 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4190 23:53:33.761187 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4191 23:53:33.761279
4192 23:53:33.764803 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4193 23:53:33.767963 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4194 23:53:33.771000 [Gating] SW calibration Done
4195 23:53:33.771107 ==
4196 23:53:33.774608 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 23:53:33.777703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 23:53:33.777784 ==
4199 23:53:33.780840 RX Vref Scan: 0
4200 23:53:33.780951
4201 23:53:33.784688 RX Vref 0 -> 0, step: 1
4202 23:53:33.784783
4203 23:53:33.784846 RX Delay -230 -> 252, step: 16
4204 23:53:33.790780 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4205 23:53:33.794164 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4206 23:53:33.797522 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4207 23:53:33.800613 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4208 23:53:33.807446 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4209 23:53:33.810475 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4210 23:53:33.813909 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4211 23:53:33.817100 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4212 23:53:33.823935 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4213 23:53:33.827134 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4214 23:53:33.830443 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4215 23:53:33.833646 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4216 23:53:33.839911 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4217 23:53:33.843556 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4218 23:53:33.850700 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4219 23:53:33.850824 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4220 23:53:33.850910 ==
4221 23:53:33.853462 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 23:53:33.859626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 23:53:33.859718 ==
4224 23:53:33.859783 DQS Delay:
4225 23:53:33.863010 DQS0 = 0, DQS1 = 0
4226 23:53:33.863091 DQM Delay:
4227 23:53:33.866524 DQM0 = 40, DQM1 = 33
4228 23:53:33.866631 DQ Delay:
4229 23:53:33.869966 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4230 23:53:33.872836 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =41
4231 23:53:33.876879 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4232 23:53:33.879773 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4233 23:53:33.879855
4234 23:53:33.879919
4235 23:53:33.879978 ==
4236 23:53:33.882971 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 23:53:33.886060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 23:53:33.886146 ==
4239 23:53:33.886210
4240 23:53:33.886269
4241 23:53:33.889790 TX Vref Scan disable
4242 23:53:33.893005 == TX Byte 0 ==
4243 23:53:33.896080 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4244 23:53:33.899147 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4245 23:53:33.902641 == TX Byte 1 ==
4246 23:53:33.905731 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4247 23:53:33.909556 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4248 23:53:33.909639 ==
4249 23:53:33.912382 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 23:53:33.918900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 23:53:33.919024 ==
4252 23:53:33.919159
4253 23:53:33.919290
4254 23:53:33.919453 TX Vref Scan disable
4255 23:53:33.923423 == TX Byte 0 ==
4256 23:53:33.926812 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4257 23:53:33.933484 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4258 23:53:33.933596 == TX Byte 1 ==
4259 23:53:33.936864 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4260 23:53:33.943260 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4261 23:53:33.943345
4262 23:53:33.943408 [DATLAT]
4263 23:53:33.943476 Freq=600, CH0 RK1
4264 23:53:33.943578
4265 23:53:33.946441 DATLAT Default: 0x9
4266 23:53:33.949702 0, 0xFFFF, sum = 0
4267 23:53:33.949786 1, 0xFFFF, sum = 0
4268 23:53:33.953310 2, 0xFFFF, sum = 0
4269 23:53:33.953420 3, 0xFFFF, sum = 0
4270 23:53:33.956332 4, 0xFFFF, sum = 0
4271 23:53:33.956441 5, 0xFFFF, sum = 0
4272 23:53:33.959569 6, 0xFFFF, sum = 0
4273 23:53:33.959652 7, 0xFFFF, sum = 0
4274 23:53:33.962761 8, 0x0, sum = 1
4275 23:53:33.962844 9, 0x0, sum = 2
4276 23:53:33.966164 10, 0x0, sum = 3
4277 23:53:33.966263 11, 0x0, sum = 4
4278 23:53:33.966342 best_step = 9
4279 23:53:33.966418
4280 23:53:33.969632 ==
4281 23:53:33.972473 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 23:53:33.976015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 23:53:33.976124 ==
4284 23:53:33.976216 RX Vref Scan: 0
4285 23:53:33.976304
4286 23:53:33.979292 RX Vref 0 -> 0, step: 1
4287 23:53:33.979373
4288 23:53:33.982833 RX Delay -195 -> 252, step: 8
4289 23:53:33.989408 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4290 23:53:33.992372 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4291 23:53:33.995716 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4292 23:53:33.999301 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4293 23:53:34.002480 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4294 23:53:34.009081 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4295 23:53:34.012275 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4296 23:53:34.015846 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4297 23:53:34.019044 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4298 23:53:34.025496 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4299 23:53:34.028695 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4300 23:53:34.032073 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4301 23:53:34.035330 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4302 23:53:34.041549 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4303 23:53:34.045240 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4304 23:53:34.048604 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4305 23:53:34.048728 ==
4306 23:53:34.051931 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 23:53:34.058199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 23:53:34.058311 ==
4309 23:53:34.058404 DQS Delay:
4310 23:53:34.058493 DQS0 = 0, DQS1 = 0
4311 23:53:34.061637 DQM Delay:
4312 23:53:34.061742 DQM0 = 41, DQM1 = 33
4313 23:53:34.064543 DQ Delay:
4314 23:53:34.068355 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4315 23:53:34.071833 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4316 23:53:34.074586 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4317 23:53:34.077948 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4318 23:53:34.078058
4319 23:53:34.078148
4320 23:53:34.084523 [DQSOSCAuto] RK1, (LSB)MR18= 0x4945, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4321 23:53:34.088108 CH0 RK1: MR19=808, MR18=4945
4322 23:53:34.094927 CH0_RK1: MR19=0x808, MR18=0x4945, DQSOSC=396, MR23=63, INC=167, DEC=111
4323 23:53:34.097766 [RxdqsGatingPostProcess] freq 600
4324 23:53:34.101413 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4325 23:53:34.104481 Pre-setting of DQS Precalculation
4326 23:53:34.110746 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4327 23:53:34.110875 ==
4328 23:53:34.114142 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 23:53:34.117484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 23:53:34.117582 ==
4331 23:53:34.124060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4332 23:53:34.130546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4333 23:53:34.134405 [CA 0] Center 36 (6~66) winsize 61
4334 23:53:34.137684 [CA 1] Center 35 (5~66) winsize 62
4335 23:53:34.140847 [CA 2] Center 34 (4~65) winsize 62
4336 23:53:34.144001 [CA 3] Center 34 (3~65) winsize 63
4337 23:53:34.147223 [CA 4] Center 34 (4~65) winsize 62
4338 23:53:34.150296 [CA 5] Center 34 (3~65) winsize 63
4339 23:53:34.150427
4340 23:53:34.154161 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4341 23:53:34.154263
4342 23:53:34.157442 [CATrainingPosCal] consider 1 rank data
4343 23:53:34.160732 u2DelayCellTimex100 = 270/100 ps
4344 23:53:34.163992 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4345 23:53:34.166889 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4346 23:53:34.170174 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4347 23:53:34.173399 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4348 23:53:34.177245 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4349 23:53:34.180721 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4350 23:53:34.180840
4351 23:53:34.186979 CA PerBit enable=1, Macro0, CA PI delay=34
4352 23:53:34.187071
4353 23:53:34.187137 [CBTSetCACLKResult] CA Dly = 34
4354 23:53:34.190218 CS Dly: 4 (0~35)
4355 23:53:34.190328 ==
4356 23:53:34.193343 Dram Type= 6, Freq= 0, CH_1, rank 1
4357 23:53:34.196894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 23:53:34.197005 ==
4359 23:53:34.203678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 23:53:34.210134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4361 23:53:34.213112 [CA 0] Center 35 (5~66) winsize 62
4362 23:53:34.216679 [CA 1] Center 35 (5~66) winsize 62
4363 23:53:34.219660 [CA 2] Center 34 (4~65) winsize 62
4364 23:53:34.223129 [CA 3] Center 33 (3~64) winsize 62
4365 23:53:34.226675 [CA 4] Center 34 (4~64) winsize 61
4366 23:53:34.229557 [CA 5] Center 34 (3~65) winsize 63
4367 23:53:34.229689
4368 23:53:34.233404 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4369 23:53:34.233507
4370 23:53:34.236211 [CATrainingPosCal] consider 2 rank data
4371 23:53:34.239636 u2DelayCellTimex100 = 270/100 ps
4372 23:53:34.242614 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4373 23:53:34.246276 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 23:53:34.249455 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 23:53:34.252707 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 23:53:34.259271 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4377 23:53:34.262735 CA5 delay=34 (3~65),Diff = 1 PI (9 cell)
4378 23:53:34.262856
4379 23:53:34.265967 CA PerBit enable=1, Macro0, CA PI delay=33
4380 23:53:34.266074
4381 23:53:34.269146 [CBTSetCACLKResult] CA Dly = 33
4382 23:53:34.269251 CS Dly: 4 (0~36)
4383 23:53:34.269347
4384 23:53:34.272857 ----->DramcWriteLeveling(PI) begin...
4385 23:53:34.272965 ==
4386 23:53:34.275760 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 23:53:34.282493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 23:53:34.282607 ==
4389 23:53:34.285759 Write leveling (Byte 0): 30 => 30
4390 23:53:34.288847 Write leveling (Byte 1): 29 => 29
4391 23:53:34.292077 DramcWriteLeveling(PI) end<-----
4392 23:53:34.292184
4393 23:53:34.292277 ==
4394 23:53:34.295955 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 23:53:34.299267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 23:53:34.299356 ==
4397 23:53:34.302269 [Gating] SW mode calibration
4398 23:53:34.309079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 23:53:34.314975 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4400 23:53:34.318724 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 23:53:34.321806 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 23:53:34.328445 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 23:53:34.331964 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
4404 23:53:34.335060 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 23:53:34.342069 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 23:53:34.344757 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 23:53:34.348272 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 23:53:34.354518 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 23:53:34.357725 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 23:53:34.361536 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4411 23:53:34.368239 0 10 12 | B1->B0 | 3232 3939 | 1 0 | (0 0) (0 0)
4412 23:53:34.371127 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 23:53:34.374334 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 23:53:34.381211 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 23:53:34.384267 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 23:53:34.387804 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 23:53:34.394073 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 23:53:34.397399 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 23:53:34.400844 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4420 23:53:34.407319 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 23:53:34.411092 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 23:53:34.413866 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 23:53:34.420636 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 23:53:34.423656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 23:53:34.427237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 23:53:34.433770 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 23:53:34.437180 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:53:34.440272 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:53:34.446765 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:53:34.450581 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:53:34.453376 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:53:34.459778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:53:34.463357 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:53:34.466251 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4435 23:53:34.473314 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 23:53:34.473399 Total UI for P1: 0, mck2ui 16
4437 23:53:34.479684 best dqsien dly found for B0: ( 0, 13, 8)
4438 23:53:34.479767 Total UI for P1: 0, mck2ui 16
4439 23:53:34.485965 best dqsien dly found for B1: ( 0, 13, 10)
4440 23:53:34.489147 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4441 23:53:34.492971 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4442 23:53:34.493067
4443 23:53:34.496090 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4444 23:53:34.499135 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4445 23:53:34.502778 [Gating] SW calibration Done
4446 23:53:34.502859 ==
4447 23:53:34.505644 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 23:53:34.509507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 23:53:34.509637 ==
4450 23:53:34.512556 RX Vref Scan: 0
4451 23:53:34.512652
4452 23:53:34.512746 RX Vref 0 -> 0, step: 1
4453 23:53:34.512820
4454 23:53:34.515912 RX Delay -230 -> 252, step: 16
4455 23:53:34.522526 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4456 23:53:34.525681 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4457 23:53:34.528918 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4458 23:53:34.532316 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4459 23:53:34.535916 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4460 23:53:34.542457 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4461 23:53:34.545501 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4462 23:53:34.548709 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4463 23:53:34.552156 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4464 23:53:34.559129 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4465 23:53:34.562262 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4466 23:53:34.565197 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4467 23:53:34.568403 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4468 23:53:34.575026 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4469 23:53:34.578208 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4470 23:53:34.582036 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4471 23:53:34.582118 ==
4472 23:53:34.585253 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 23:53:34.591664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 23:53:34.591770 ==
4475 23:53:34.591867 DQS Delay:
4476 23:53:34.591957 DQS0 = 0, DQS1 = 0
4477 23:53:34.594730 DQM Delay:
4478 23:53:34.594824 DQM0 = 44, DQM1 = 38
4479 23:53:34.598540 DQ Delay:
4480 23:53:34.601643 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4481 23:53:34.604944 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4482 23:53:34.608166 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4483 23:53:34.611427 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4484 23:53:34.611523
4485 23:53:34.611587
4486 23:53:34.611647 ==
4487 23:53:34.614325 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 23:53:34.617946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 23:53:34.618027 ==
4490 23:53:34.618091
4491 23:53:34.618166
4492 23:53:34.621382 TX Vref Scan disable
4493 23:53:34.621484 == TX Byte 0 ==
4494 23:53:34.627593 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4495 23:53:34.631167 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4496 23:53:34.631279 == TX Byte 1 ==
4497 23:53:34.638116 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4498 23:53:34.641217 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4499 23:53:34.641338 ==
4500 23:53:34.644629 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 23:53:34.647620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 23:53:34.647727 ==
4503 23:53:34.650721
4504 23:53:34.650822
4505 23:53:34.650913 TX Vref Scan disable
4506 23:53:34.654481 == TX Byte 0 ==
4507 23:53:34.658100 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 23:53:34.664459 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 23:53:34.664555 == TX Byte 1 ==
4510 23:53:34.668311 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 23:53:34.674543 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 23:53:34.674627
4513 23:53:34.674689 [DATLAT]
4514 23:53:34.674749 Freq=600, CH1 RK0
4515 23:53:34.674806
4516 23:53:34.678119 DATLAT Default: 0x9
4517 23:53:34.678200 0, 0xFFFF, sum = 0
4518 23:53:34.681372 1, 0xFFFF, sum = 0
4519 23:53:34.684491 2, 0xFFFF, sum = 0
4520 23:53:34.684573 3, 0xFFFF, sum = 0
4521 23:53:34.687855 4, 0xFFFF, sum = 0
4522 23:53:34.687942 5, 0xFFFF, sum = 0
4523 23:53:34.691050 6, 0xFFFF, sum = 0
4524 23:53:34.691177 7, 0xFFFF, sum = 0
4525 23:53:34.694346 8, 0x0, sum = 1
4526 23:53:34.694481 9, 0x0, sum = 2
4527 23:53:34.697289 10, 0x0, sum = 3
4528 23:53:34.697405 11, 0x0, sum = 4
4529 23:53:34.697480 best_step = 9
4530 23:53:34.697547
4531 23:53:34.700741 ==
4532 23:53:34.703973 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 23:53:34.707156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 23:53:34.707308 ==
4535 23:53:34.707406 RX Vref Scan: 1
4536 23:53:34.707501
4537 23:53:34.710287 RX Vref 0 -> 0, step: 1
4538 23:53:34.710404
4539 23:53:34.713788 RX Delay -179 -> 252, step: 8
4540 23:53:34.713936
4541 23:53:34.716865 Set Vref, RX VrefLevel [Byte0]: 49
4542 23:53:34.720707 [Byte1]: 52
4543 23:53:34.720788
4544 23:53:34.724029 Final RX Vref Byte 0 = 49 to rank0
4545 23:53:34.726976 Final RX Vref Byte 1 = 52 to rank0
4546 23:53:34.730030 Final RX Vref Byte 0 = 49 to rank1
4547 23:53:34.733588 Final RX Vref Byte 1 = 52 to rank1==
4548 23:53:34.736716 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 23:53:34.743473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 23:53:34.743564 ==
4551 23:53:34.743659 DQS Delay:
4552 23:53:34.743751 DQS0 = 0, DQS1 = 0
4553 23:53:34.746793 DQM Delay:
4554 23:53:34.746876 DQM0 = 40, DQM1 = 34
4555 23:53:34.750112 DQ Delay:
4556 23:53:34.752999 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4557 23:53:34.756665 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4558 23:53:34.759596 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4559 23:53:34.763206 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4560 23:53:34.763290
4561 23:53:34.763355
4562 23:53:34.769683 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b45, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4563 23:53:34.772794 CH1 RK0: MR19=808, MR18=2B45
4564 23:53:34.779826 CH1_RK0: MR19=0x808, MR18=0x2B45, DQSOSC=396, MR23=63, INC=167, DEC=111
4565 23:53:34.779912
4566 23:53:34.783234 ----->DramcWriteLeveling(PI) begin...
4567 23:53:34.783318 ==
4568 23:53:34.786311 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 23:53:34.789419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 23:53:34.789503 ==
4571 23:53:34.792647 Write leveling (Byte 0): 28 => 28
4572 23:53:34.795823 Write leveling (Byte 1): 31 => 31
4573 23:53:34.799002 DramcWriteLeveling(PI) end<-----
4574 23:53:34.799084
4575 23:53:34.799158 ==
4576 23:53:34.802716 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 23:53:34.805869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 23:53:34.809030 ==
4579 23:53:34.809112 [Gating] SW mode calibration
4580 23:53:34.819349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4581 23:53:34.822593 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4582 23:53:34.825825 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4583 23:53:34.832292 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 23:53:34.835291 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 23:53:34.838364 0 9 12 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
4586 23:53:34.845451 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4587 23:53:34.848415 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 23:53:34.851865 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 23:53:34.858432 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 23:53:34.861282 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 23:53:34.864844 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 23:53:34.871353 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4593 23:53:34.874587 0 10 12 | B1->B0 | 2f2f 3939 | 1 0 | (0 0) (0 0)
4594 23:53:34.878389 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4595 23:53:34.884553 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 23:53:34.887827 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 23:53:34.891322 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 23:53:34.898142 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 23:53:34.901224 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 23:53:34.904460 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 23:53:34.910936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4602 23:53:34.914678 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 23:53:34.917938 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 23:53:34.924031 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 23:53:34.927336 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 23:53:34.931212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 23:53:34.937558 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 23:53:34.940790 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 23:53:34.947165 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 23:53:34.950219 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 23:53:34.953466 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 23:53:34.960456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 23:53:34.963525 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 23:53:34.967013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 23:53:34.973726 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:53:34.976787 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:53:34.980209 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4618 23:53:34.983405 Total UI for P1: 0, mck2ui 16
4619 23:53:34.986931 best dqsien dly found for B0: ( 0, 13, 10)
4620 23:53:34.993107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 23:53:34.993234 Total UI for P1: 0, mck2ui 16
4622 23:53:34.996247 best dqsien dly found for B1: ( 0, 13, 12)
4623 23:53:35.002912 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4624 23:53:35.006358 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4625 23:53:35.006476
4626 23:53:35.009484 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4627 23:53:35.012909 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4628 23:53:35.015946 [Gating] SW calibration Done
4629 23:53:35.016062 ==
4630 23:53:35.019551 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 23:53:35.022733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 23:53:35.022850 ==
4633 23:53:35.025944 RX Vref Scan: 0
4634 23:53:35.026052
4635 23:53:35.026150 RX Vref 0 -> 0, step: 1
4636 23:53:35.026239
4637 23:53:35.029216 RX Delay -230 -> 252, step: 16
4638 23:53:35.035987 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4639 23:53:35.039369 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4640 23:53:35.042843 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4641 23:53:35.045790 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4642 23:53:35.049544 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4643 23:53:35.055848 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4644 23:53:35.059139 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4645 23:53:35.062376 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4646 23:53:35.065501 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4647 23:53:35.072249 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4648 23:53:35.075498 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4649 23:53:35.078690 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4650 23:53:35.082215 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4651 23:53:35.088609 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4652 23:53:35.091926 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4653 23:53:35.095397 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4654 23:53:35.095480 ==
4655 23:53:35.098557 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 23:53:35.102226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 23:53:35.105506 ==
4658 23:53:35.105623 DQS Delay:
4659 23:53:35.105717 DQS0 = 0, DQS1 = 0
4660 23:53:35.108462 DQM Delay:
4661 23:53:35.108562 DQM0 = 41, DQM1 = 39
4662 23:53:35.111963 DQ Delay:
4663 23:53:35.114787 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4664 23:53:35.114870 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4665 23:53:35.118368 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4666 23:53:35.124811 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4667 23:53:35.124895
4668 23:53:35.124958
4669 23:53:35.125038 ==
4670 23:53:35.128085 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 23:53:35.131982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 23:53:35.132141 ==
4673 23:53:35.132248
4674 23:53:35.132338
4675 23:53:35.134605 TX Vref Scan disable
4676 23:53:35.134712 == TX Byte 0 ==
4677 23:53:35.141229 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4678 23:53:35.145044 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4679 23:53:35.145153 == TX Byte 1 ==
4680 23:53:35.151540 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4681 23:53:35.154742 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4682 23:53:35.154843 ==
4683 23:53:35.157769 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 23:53:35.161063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 23:53:35.161196 ==
4686 23:53:35.164184
4687 23:53:35.164291
4688 23:53:35.164382 TX Vref Scan disable
4689 23:53:35.167950 == TX Byte 0 ==
4690 23:53:35.171095 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4691 23:53:35.177971 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4692 23:53:35.178054 == TX Byte 1 ==
4693 23:53:35.181221 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4694 23:53:35.187637 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4695 23:53:35.187759
4696 23:53:35.187850 [DATLAT]
4697 23:53:35.187936 Freq=600, CH1 RK1
4698 23:53:35.188029
4699 23:53:35.191352 DATLAT Default: 0x9
4700 23:53:35.194325 0, 0xFFFF, sum = 0
4701 23:53:35.194434 1, 0xFFFF, sum = 0
4702 23:53:35.197779 2, 0xFFFF, sum = 0
4703 23:53:35.197886 3, 0xFFFF, sum = 0
4704 23:53:35.200708 4, 0xFFFF, sum = 0
4705 23:53:35.200782 5, 0xFFFF, sum = 0
4706 23:53:35.204260 6, 0xFFFF, sum = 0
4707 23:53:35.204344 7, 0xFFFF, sum = 0
4708 23:53:35.207581 8, 0x0, sum = 1
4709 23:53:35.207667 9, 0x0, sum = 2
4710 23:53:35.210767 10, 0x0, sum = 3
4711 23:53:35.210868 11, 0x0, sum = 4
4712 23:53:35.210933 best_step = 9
4713 23:53:35.211024
4714 23:53:35.214040 ==
4715 23:53:35.217108 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 23:53:35.220824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 23:53:35.220905 ==
4718 23:53:35.220968 RX Vref Scan: 0
4719 23:53:35.221028
4720 23:53:35.224172 RX Vref 0 -> 0, step: 1
4721 23:53:35.224271
4722 23:53:35.227098 RX Delay -179 -> 252, step: 8
4723 23:53:35.233680 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4724 23:53:35.237350 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4725 23:53:35.240335 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4726 23:53:35.243606 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4727 23:53:35.250449 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4728 23:53:35.253212 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4729 23:53:35.256529 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4730 23:53:35.260283 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4731 23:53:35.263531 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4732 23:53:35.269881 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4733 23:53:35.273055 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4734 23:53:35.276246 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4735 23:53:35.279864 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4736 23:53:35.286230 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4737 23:53:35.289918 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4738 23:53:35.293084 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4739 23:53:35.293189 ==
4740 23:53:35.296256 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 23:53:35.302798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 23:53:35.302890 ==
4743 23:53:35.302964 DQS Delay:
4744 23:53:35.305930 DQS0 = 0, DQS1 = 0
4745 23:53:35.306019 DQM Delay:
4746 23:53:35.306087 DQM0 = 37, DQM1 = 35
4747 23:53:35.309148 DQ Delay:
4748 23:53:35.312476 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4749 23:53:35.316031 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4750 23:53:35.319178 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4751 23:53:35.322458 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4752 23:53:35.322545
4753 23:53:35.322629
4754 23:53:35.329172 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4755 23:53:35.332659 CH1 RK1: MR19=808, MR18=3A60
4756 23:53:35.338954 CH1_RK1: MR19=0x808, MR18=0x3A60, DQSOSC=391, MR23=63, INC=171, DEC=114
4757 23:53:35.342602 [RxdqsGatingPostProcess] freq 600
4758 23:53:35.345887 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4759 23:53:35.348960 Pre-setting of DQS Precalculation
4760 23:53:35.355884 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4761 23:53:35.361894 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4762 23:53:35.368722 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4763 23:53:35.368828
4764 23:53:35.368940
4765 23:53:35.371897 [Calibration Summary] 1200 Mbps
4766 23:53:35.371974 CH 0, Rank 0
4767 23:53:35.375187 SW Impedance : PASS
4768 23:53:35.378915 DUTY Scan : NO K
4769 23:53:35.379025 ZQ Calibration : PASS
4770 23:53:35.382306 Jitter Meter : NO K
4771 23:53:35.385403 CBT Training : PASS
4772 23:53:35.385484 Write leveling : PASS
4773 23:53:35.388588 RX DQS gating : PASS
4774 23:53:35.391943 RX DQ/DQS(RDDQC) : PASS
4775 23:53:35.392022 TX DQ/DQS : PASS
4776 23:53:35.394996 RX DATLAT : PASS
4777 23:53:35.398178 RX DQ/DQS(Engine): PASS
4778 23:53:35.398280 TX OE : NO K
4779 23:53:35.402073 All Pass.
4780 23:53:35.402176
4781 23:53:35.402280 CH 0, Rank 1
4782 23:53:35.405127 SW Impedance : PASS
4783 23:53:35.405226 DUTY Scan : NO K
4784 23:53:35.408151 ZQ Calibration : PASS
4785 23:53:35.411884 Jitter Meter : NO K
4786 23:53:35.411964 CBT Training : PASS
4787 23:53:35.415140 Write leveling : PASS
4788 23:53:35.418247 RX DQS gating : PASS
4789 23:53:35.418346 RX DQ/DQS(RDDQC) : PASS
4790 23:53:35.421741 TX DQ/DQS : PASS
4791 23:53:35.424679 RX DATLAT : PASS
4792 23:53:35.424754 RX DQ/DQS(Engine): PASS
4793 23:53:35.428294 TX OE : NO K
4794 23:53:35.428375 All Pass.
4795 23:53:35.428477
4796 23:53:35.431569 CH 1, Rank 0
4797 23:53:35.431649 SW Impedance : PASS
4798 23:53:35.434923 DUTY Scan : NO K
4799 23:53:35.438016 ZQ Calibration : PASS
4800 23:53:35.438096 Jitter Meter : NO K
4801 23:53:35.441554 CBT Training : PASS
4802 23:53:35.441632 Write leveling : PASS
4803 23:53:35.444842 RX DQS gating : PASS
4804 23:53:35.448180 RX DQ/DQS(RDDQC) : PASS
4805 23:53:35.448254 TX DQ/DQS : PASS
4806 23:53:35.451120 RX DATLAT : PASS
4807 23:53:35.454645 RX DQ/DQS(Engine): PASS
4808 23:53:35.454724 TX OE : NO K
4809 23:53:35.458036 All Pass.
4810 23:53:35.458142
4811 23:53:35.458248 CH 1, Rank 1
4812 23:53:35.461306 SW Impedance : PASS
4813 23:53:35.461380 DUTY Scan : NO K
4814 23:53:35.464427 ZQ Calibration : PASS
4815 23:53:35.467397 Jitter Meter : NO K
4816 23:53:35.467478 CBT Training : PASS
4817 23:53:35.471101 Write leveling : PASS
4818 23:53:35.474450 RX DQS gating : PASS
4819 23:53:35.474528 RX DQ/DQS(RDDQC) : PASS
4820 23:53:35.477690 TX DQ/DQS : PASS
4821 23:53:35.480667 RX DATLAT : PASS
4822 23:53:35.480741 RX DQ/DQS(Engine): PASS
4823 23:53:35.483947 TX OE : NO K
4824 23:53:35.484050 All Pass.
4825 23:53:35.484148
4826 23:53:35.487232 DramC Write-DBI off
4827 23:53:35.490971 PER_BANK_REFRESH: Hybrid Mode
4828 23:53:35.491046 TX_TRACKING: ON
4829 23:53:35.500490 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4830 23:53:35.503651 [FAST_K] Save calibration result to emmc
4831 23:53:35.506725 dramc_set_vcore_voltage set vcore to 662500
4832 23:53:35.510701 Read voltage for 933, 3
4833 23:53:35.510780 Vio18 = 0
4834 23:53:35.510860 Vcore = 662500
4835 23:53:35.513594 Vdram = 0
4836 23:53:35.513670 Vddq = 0
4837 23:53:35.513750 Vmddr = 0
4838 23:53:35.520034 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4839 23:53:35.523206 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4840 23:53:35.526937 MEM_TYPE=3, freq_sel=17
4841 23:53:35.530157 sv_algorithm_assistance_LP4_1600
4842 23:53:35.533365 ============ PULL DRAM RESETB DOWN ============
4843 23:53:35.539985 ========== PULL DRAM RESETB DOWN end =========
4844 23:53:35.543294 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 23:53:35.546283 ===================================
4846 23:53:35.549596 LPDDR4 DRAM CONFIGURATION
4847 23:53:35.553098 ===================================
4848 23:53:35.553199 EX_ROW_EN[0] = 0x0
4849 23:53:35.556058 EX_ROW_EN[1] = 0x0
4850 23:53:35.556156 LP4Y_EN = 0x0
4851 23:53:35.559312 WORK_FSP = 0x0
4852 23:53:35.559426 WL = 0x3
4853 23:53:35.562627 RL = 0x3
4854 23:53:35.566079 BL = 0x2
4855 23:53:35.566164 RPST = 0x0
4856 23:53:35.569660 RD_PRE = 0x0
4857 23:53:35.569737 WR_PRE = 0x1
4858 23:53:35.572923 WR_PST = 0x0
4859 23:53:35.573003 DBI_WR = 0x0
4860 23:53:35.576171 DBI_RD = 0x0
4861 23:53:35.576244 OTF = 0x1
4862 23:53:35.579520 ===================================
4863 23:53:35.582908 ===================================
4864 23:53:35.586212 ANA top config
4865 23:53:35.589090 ===================================
4866 23:53:35.589168 DLL_ASYNC_EN = 0
4867 23:53:35.592437 ALL_SLAVE_EN = 1
4868 23:53:35.595742 NEW_RANK_MODE = 1
4869 23:53:35.599396 DLL_IDLE_MODE = 1
4870 23:53:35.602624 LP45_APHY_COMB_EN = 1
4871 23:53:35.602716 TX_ODT_DIS = 1
4872 23:53:35.605793 NEW_8X_MODE = 1
4873 23:53:35.609198 ===================================
4874 23:53:35.612121 ===================================
4875 23:53:35.615752 data_rate = 1866
4876 23:53:35.618924 CKR = 1
4877 23:53:35.621983 DQ_P2S_RATIO = 8
4878 23:53:35.625759 ===================================
4879 23:53:35.625840 CA_P2S_RATIO = 8
4880 23:53:35.629006 DQ_CA_OPEN = 0
4881 23:53:35.632031 DQ_SEMI_OPEN = 0
4882 23:53:35.635309 CA_SEMI_OPEN = 0
4883 23:53:35.639053 CA_FULL_RATE = 0
4884 23:53:35.642332 DQ_CKDIV4_EN = 1
4885 23:53:35.642432 CA_CKDIV4_EN = 1
4886 23:53:35.645214 CA_PREDIV_EN = 0
4887 23:53:35.648873 PH8_DLY = 0
4888 23:53:35.652113 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4889 23:53:35.655053 DQ_AAMCK_DIV = 4
4890 23:53:35.658575 CA_AAMCK_DIV = 4
4891 23:53:35.658691 CA_ADMCK_DIV = 4
4892 23:53:35.661726 DQ_TRACK_CA_EN = 0
4893 23:53:35.665251 CA_PICK = 933
4894 23:53:35.668199 CA_MCKIO = 933
4895 23:53:35.671634 MCKIO_SEMI = 0
4896 23:53:35.675035 PLL_FREQ = 3732
4897 23:53:35.678439 DQ_UI_PI_RATIO = 32
4898 23:53:35.681853 CA_UI_PI_RATIO = 0
4899 23:53:35.684827 ===================================
4900 23:53:35.688716 ===================================
4901 23:53:35.688791 memory_type:LPDDR4
4902 23:53:35.691549 GP_NUM : 10
4903 23:53:35.694704 SRAM_EN : 1
4904 23:53:35.694799 MD32_EN : 0
4905 23:53:35.698279 ===================================
4906 23:53:35.701566 [ANA_INIT] >>>>>>>>>>>>>>
4907 23:53:35.704503 <<<<<< [CONFIGURE PHASE]: ANA_TX
4908 23:53:35.708302 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4909 23:53:35.711051 ===================================
4910 23:53:35.714684 data_rate = 1866,PCW = 0X8f00
4911 23:53:35.717711 ===================================
4912 23:53:35.720923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4913 23:53:35.724519 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4914 23:53:35.730918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 23:53:35.734012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4916 23:53:35.737282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4917 23:53:35.744154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4918 23:53:35.744230 [ANA_INIT] flow start
4919 23:53:35.747368 [ANA_INIT] PLL >>>>>>>>
4920 23:53:35.747442 [ANA_INIT] PLL <<<<<<<<
4921 23:53:35.750466 [ANA_INIT] MIDPI >>>>>>>>
4922 23:53:35.754204 [ANA_INIT] MIDPI <<<<<<<<
4923 23:53:35.757367 [ANA_INIT] DLL >>>>>>>>
4924 23:53:35.757443 [ANA_INIT] flow end
4925 23:53:35.760551 ============ LP4 DIFF to SE enter ============
4926 23:53:35.766892 ============ LP4 DIFF to SE exit ============
4927 23:53:35.766972 [ANA_INIT] <<<<<<<<<<<<<
4928 23:53:35.770149 [Flow] Enable top DCM control >>>>>
4929 23:53:35.773876 [Flow] Enable top DCM control <<<<<
4930 23:53:35.776844 Enable DLL master slave shuffle
4931 23:53:35.783356 ==============================================================
4932 23:53:35.786519 Gating Mode config
4933 23:53:35.789794 ==============================================================
4934 23:53:35.793167 Config description:
4935 23:53:35.803334 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4936 23:53:35.809841 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4937 23:53:35.813255 SELPH_MODE 0: By rank 1: By Phase
4938 23:53:35.819953 ==============================================================
4939 23:53:35.823156 GAT_TRACK_EN = 1
4940 23:53:35.826258 RX_GATING_MODE = 2
4941 23:53:35.829921 RX_GATING_TRACK_MODE = 2
4942 23:53:35.833012 SELPH_MODE = 1
4943 23:53:35.833087 PICG_EARLY_EN = 1
4944 23:53:35.836345 VALID_LAT_VALUE = 1
4945 23:53:35.842572 ==============================================================
4946 23:53:35.846414 Enter into Gating configuration >>>>
4947 23:53:35.849575 Exit from Gating configuration <<<<
4948 23:53:35.852660 Enter into DVFS_PRE_config >>>>>
4949 23:53:35.862712 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4950 23:53:35.865754 Exit from DVFS_PRE_config <<<<<
4951 23:53:35.869459 Enter into PICG configuration >>>>
4952 23:53:35.872933 Exit from PICG configuration <<<<
4953 23:53:35.876016 [RX_INPUT] configuration >>>>>
4954 23:53:35.879196 [RX_INPUT] configuration <<<<<
4955 23:53:35.882269 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4956 23:53:35.889383 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4957 23:53:35.895782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 23:53:35.902015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 23:53:35.908388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 23:53:35.915257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 23:53:35.918515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4962 23:53:35.921603 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4963 23:53:35.924915 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4964 23:53:35.931750 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4965 23:53:35.934975 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4966 23:53:35.938108 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 23:53:35.941845 ===================================
4968 23:53:35.945079 LPDDR4 DRAM CONFIGURATION
4969 23:53:35.948207 ===================================
4970 23:53:35.951359 EX_ROW_EN[0] = 0x0
4971 23:53:35.951429 EX_ROW_EN[1] = 0x0
4972 23:53:35.954507 LP4Y_EN = 0x0
4973 23:53:35.954576 WORK_FSP = 0x0
4974 23:53:35.958559 WL = 0x3
4975 23:53:35.958660 RL = 0x3
4976 23:53:35.961362 BL = 0x2
4977 23:53:35.961436 RPST = 0x0
4978 23:53:35.964550 RD_PRE = 0x0
4979 23:53:35.964625 WR_PRE = 0x1
4980 23:53:35.968342 WR_PST = 0x0
4981 23:53:35.968446 DBI_WR = 0x0
4982 23:53:35.971425 DBI_RD = 0x0
4983 23:53:35.971504 OTF = 0x1
4984 23:53:35.974477 ===================================
4985 23:53:35.981221 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4986 23:53:35.984229 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4987 23:53:35.987994 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 23:53:35.991237 ===================================
4989 23:53:35.994463 LPDDR4 DRAM CONFIGURATION
4990 23:53:35.997706 ===================================
4991 23:53:36.000933 EX_ROW_EN[0] = 0x10
4992 23:53:36.001033 EX_ROW_EN[1] = 0x0
4993 23:53:36.003994 LP4Y_EN = 0x0
4994 23:53:36.004074 WORK_FSP = 0x0
4995 23:53:36.007454 WL = 0x3
4996 23:53:36.007536 RL = 0x3
4997 23:53:36.011072 BL = 0x2
4998 23:53:36.011177 RPST = 0x0
4999 23:53:36.014269 RD_PRE = 0x0
5000 23:53:36.014349 WR_PRE = 0x1
5001 23:53:36.017813 WR_PST = 0x0
5002 23:53:36.017897 DBI_WR = 0x0
5003 23:53:36.021147 DBI_RD = 0x0
5004 23:53:36.021251 OTF = 0x1
5005 23:53:36.024234 ===================================
5006 23:53:36.030397 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5007 23:53:36.035391 nWR fixed to 30
5008 23:53:36.038506 [ModeRegInit_LP4] CH0 RK0
5009 23:53:36.038582 [ModeRegInit_LP4] CH0 RK1
5010 23:53:36.042199 [ModeRegInit_LP4] CH1 RK0
5011 23:53:36.045599 [ModeRegInit_LP4] CH1 RK1
5012 23:53:36.045676 match AC timing 9
5013 23:53:36.051711 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5014 23:53:36.055308 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5015 23:53:36.058471 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5016 23:53:36.065284 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5017 23:53:36.068497 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5018 23:53:36.068571 ==
5019 23:53:36.071507 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 23:53:36.075475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5021 23:53:36.075545 ==
5022 23:53:36.081618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5023 23:53:36.088047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5024 23:53:36.091525 [CA 0] Center 37 (7~68) winsize 62
5025 23:53:36.094701 [CA 1] Center 37 (7~68) winsize 62
5026 23:53:36.097749 [CA 2] Center 34 (4~65) winsize 62
5027 23:53:36.101485 [CA 3] Center 34 (4~65) winsize 62
5028 23:53:36.104664 [CA 4] Center 33 (3~63) winsize 61
5029 23:53:36.107768 [CA 5] Center 33 (3~63) winsize 61
5030 23:53:36.107844
5031 23:53:36.111028 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5032 23:53:36.111113
5033 23:53:36.114881 [CATrainingPosCal] consider 1 rank data
5034 23:53:36.117689 u2DelayCellTimex100 = 270/100 ps
5035 23:53:36.121276 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5036 23:53:36.124770 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5037 23:53:36.127671 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5038 23:53:36.130853 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5039 23:53:36.137678 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5040 23:53:36.140887 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5041 23:53:36.140970
5042 23:53:36.144043 CA PerBit enable=1, Macro0, CA PI delay=33
5043 23:53:36.144117
5044 23:53:36.147174 [CBTSetCACLKResult] CA Dly = 33
5045 23:53:36.147253 CS Dly: 5 (0~36)
5046 23:53:36.147317 ==
5047 23:53:36.150839 Dram Type= 6, Freq= 0, CH_0, rank 1
5048 23:53:36.157250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 23:53:36.157337 ==
5050 23:53:36.160789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 23:53:36.167378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 23:53:36.170653 [CA 0] Center 37 (7~68) winsize 62
5053 23:53:36.173991 [CA 1] Center 37 (7~68) winsize 62
5054 23:53:36.177392 [CA 2] Center 35 (5~65) winsize 61
5055 23:53:36.180275 [CA 3] Center 34 (4~65) winsize 62
5056 23:53:36.183888 [CA 4] Center 33 (3~64) winsize 62
5057 23:53:36.186962 [CA 5] Center 32 (2~63) winsize 62
5058 23:53:36.187038
5059 23:53:36.190232 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 23:53:36.190303
5061 23:53:36.193841 [CATrainingPosCal] consider 2 rank data
5062 23:53:36.196948 u2DelayCellTimex100 = 270/100 ps
5063 23:53:36.200277 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5064 23:53:36.204068 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5065 23:53:36.210597 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5066 23:53:36.213684 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5067 23:53:36.216874 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5068 23:53:36.220016 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5069 23:53:36.220097
5070 23:53:36.223754 CA PerBit enable=1, Macro0, CA PI delay=33
5071 23:53:36.223835
5072 23:53:36.226887 [CBTSetCACLKResult] CA Dly = 33
5073 23:53:36.226967 CS Dly: 6 (0~39)
5074 23:53:36.230041
5075 23:53:36.233143 ----->DramcWriteLeveling(PI) begin...
5076 23:53:36.233255 ==
5077 23:53:36.236600 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 23:53:36.240107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 23:53:36.240188 ==
5080 23:53:36.243318 Write leveling (Byte 0): 29 => 29
5081 23:53:36.246923 Write leveling (Byte 1): 28 => 28
5082 23:53:36.249877 DramcWriteLeveling(PI) end<-----
5083 23:53:36.249958
5084 23:53:36.250020 ==
5085 23:53:36.253171 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 23:53:36.256200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 23:53:36.256281 ==
5088 23:53:36.259594 [Gating] SW mode calibration
5089 23:53:36.266324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 23:53:36.272708 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5091 23:53:36.276564 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5092 23:53:36.279520 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 23:53:36.286385 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 23:53:36.289625 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 23:53:36.292919 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 23:53:36.299026 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 23:53:36.302314 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5098 23:53:36.306072 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5099 23:53:36.312354 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5100 23:53:36.315666 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 23:53:36.318862 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 23:53:36.325854 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 23:53:36.329017 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 23:53:36.332407 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 23:53:36.338863 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5106 23:53:36.342489 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5107 23:53:36.345630 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5108 23:53:36.352481 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 23:53:36.355066 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 23:53:36.359105 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 23:53:36.365216 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 23:53:36.368432 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 23:53:36.372274 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 23:53:36.378490 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5115 23:53:36.381766 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5116 23:53:36.387546 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5117 23:53:36.391699 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 23:53:36.394809 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 23:53:36.398011 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 23:53:36.404791 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 23:53:36.408014 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 23:53:36.411163 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 23:53:36.418101 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 23:53:36.421410 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:53:36.424558 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:53:36.430752 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:53:36.434502 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:53:36.437520 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:53:36.444122 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5130 23:53:36.447198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5131 23:53:36.451050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5132 23:53:36.454097 Total UI for P1: 0, mck2ui 16
5133 23:53:36.457166 best dqsien dly found for B0: ( 1, 2, 26)
5134 23:53:36.463690 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 23:53:36.467332 Total UI for P1: 0, mck2ui 16
5136 23:53:36.470573 best dqsien dly found for B1: ( 1, 2, 30)
5137 23:53:36.473511 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5138 23:53:36.476660 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5139 23:53:36.476789
5140 23:53:36.480321 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5141 23:53:36.483617 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5142 23:53:36.486607 [Gating] SW calibration Done
5143 23:53:36.486693 ==
5144 23:53:36.490468 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 23:53:36.493568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 23:53:36.493655 ==
5147 23:53:36.496594 RX Vref Scan: 0
5148 23:53:36.496679
5149 23:53:36.499775 RX Vref 0 -> 0, step: 1
5150 23:53:36.499863
5151 23:53:36.499950 RX Delay -80 -> 252, step: 8
5152 23:53:36.506701 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5153 23:53:36.509938 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5154 23:53:36.513056 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5155 23:53:36.516709 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5156 23:53:36.519736 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5157 23:53:36.526343 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5158 23:53:36.529433 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5159 23:53:36.532791 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5160 23:53:36.536246 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5161 23:53:36.539302 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5162 23:53:36.545950 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5163 23:53:36.549098 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5164 23:53:36.552820 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5165 23:53:36.555939 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5166 23:53:36.559219 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5167 23:53:36.562371 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5168 23:53:36.566049 ==
5169 23:53:36.566132 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 23:53:36.572669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 23:53:36.572759 ==
5172 23:53:36.572846 DQS Delay:
5173 23:53:36.575943 DQS0 = 0, DQS1 = 0
5174 23:53:36.576029 DQM Delay:
5175 23:53:36.579074 DQM0 = 100, DQM1 = 88
5176 23:53:36.579160 DQ Delay:
5177 23:53:36.582241 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5178 23:53:36.585912 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5179 23:53:36.589112 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5180 23:53:36.592292 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5181 23:53:36.592363
5182 23:53:36.592425
5183 23:53:36.592483 ==
5184 23:53:36.595473 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 23:53:36.599282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 23:53:36.599365 ==
5187 23:53:36.602385
5188 23:53:36.602470
5189 23:53:36.602534 TX Vref Scan disable
5190 23:53:36.605585 == TX Byte 0 ==
5191 23:53:36.608744 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5192 23:53:36.612266 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5193 23:53:36.615192 == TX Byte 1 ==
5194 23:53:36.619190 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5195 23:53:36.622079 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5196 23:53:36.622163 ==
5197 23:53:36.625162 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 23:53:36.632014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 23:53:36.632097 ==
5200 23:53:36.632163
5201 23:53:36.632223
5202 23:53:36.634974 TX Vref Scan disable
5203 23:53:36.635056 == TX Byte 0 ==
5204 23:53:36.641668 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5205 23:53:36.644916 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5206 23:53:36.645000 == TX Byte 1 ==
5207 23:53:36.651370 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 23:53:36.654783 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 23:53:36.654866
5210 23:53:36.654931 [DATLAT]
5211 23:53:36.658064 Freq=933, CH0 RK0
5212 23:53:36.658147
5213 23:53:36.658212 DATLAT Default: 0xd
5214 23:53:36.661425 0, 0xFFFF, sum = 0
5215 23:53:36.661509 1, 0xFFFF, sum = 0
5216 23:53:36.664539 2, 0xFFFF, sum = 0
5217 23:53:36.664622 3, 0xFFFF, sum = 0
5218 23:53:36.667677 4, 0xFFFF, sum = 0
5219 23:53:36.667760 5, 0xFFFF, sum = 0
5220 23:53:36.671564 6, 0xFFFF, sum = 0
5221 23:53:36.674664 7, 0xFFFF, sum = 0
5222 23:53:36.674748 8, 0xFFFF, sum = 0
5223 23:53:36.677677 9, 0xFFFF, sum = 0
5224 23:53:36.677760 10, 0x0, sum = 1
5225 23:53:36.681117 11, 0x0, sum = 2
5226 23:53:36.681200 12, 0x0, sum = 3
5227 23:53:36.681274 13, 0x0, sum = 4
5228 23:53:36.684681 best_step = 11
5229 23:53:36.684758
5230 23:53:36.684824 ==
5231 23:53:36.687901 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 23:53:36.690982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 23:53:36.691054 ==
5234 23:53:36.694654 RX Vref Scan: 1
5235 23:53:36.694724
5236 23:53:36.694783 RX Vref 0 -> 0, step: 1
5237 23:53:36.697800
5238 23:53:36.697868 RX Delay -61 -> 252, step: 4
5239 23:53:36.697946
5240 23:53:36.701016 Set Vref, RX VrefLevel [Byte0]: 51
5241 23:53:36.704453 [Byte1]: 59
5242 23:53:36.709146
5243 23:53:36.709250 Final RX Vref Byte 0 = 51 to rank0
5244 23:53:36.712046 Final RX Vref Byte 1 = 59 to rank0
5245 23:53:36.715327 Final RX Vref Byte 0 = 51 to rank1
5246 23:53:36.718413 Final RX Vref Byte 1 = 59 to rank1==
5247 23:53:36.722210 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 23:53:36.728458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 23:53:36.728535 ==
5250 23:53:36.728597 DQS Delay:
5251 23:53:36.731651 DQS0 = 0, DQS1 = 0
5252 23:53:36.731736 DQM Delay:
5253 23:53:36.731824 DQM0 = 99, DQM1 = 87
5254 23:53:36.735405 DQ Delay:
5255 23:53:36.738544 DQ0 =100, DQ1 =98, DQ2 =96, DQ3 =94
5256 23:53:36.741787 DQ4 =100, DQ5 =92, DQ6 =108, DQ7 =106
5257 23:53:36.745051 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5258 23:53:36.748532 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =94
5259 23:53:36.748608
5260 23:53:36.748669
5261 23:53:36.754797 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5262 23:53:36.758323 CH0 RK0: MR19=505, MR18=1D17
5263 23:53:36.765214 CH0_RK0: MR19=0x505, MR18=0x1D17, DQSOSC=412, MR23=63, INC=63, DEC=42
5264 23:53:36.765340
5265 23:53:36.767960 ----->DramcWriteLeveling(PI) begin...
5266 23:53:36.768083 ==
5267 23:53:36.771389 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 23:53:36.774564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 23:53:36.774670 ==
5270 23:53:36.778372 Write leveling (Byte 0): 30 => 30
5271 23:53:36.781500 Write leveling (Byte 1): 27 => 27
5272 23:53:36.784587 DramcWriteLeveling(PI) end<-----
5273 23:53:36.784710
5274 23:53:36.784772 ==
5275 23:53:36.788134 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 23:53:36.794538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 23:53:36.794621 ==
5278 23:53:36.794713 [Gating] SW mode calibration
5279 23:53:36.804129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5280 23:53:36.807863 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5281 23:53:36.811024 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5282 23:53:36.817365 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 23:53:36.821093 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 23:53:36.827507 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 23:53:36.830726 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 23:53:36.833785 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 23:53:36.837644 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5288 23:53:36.844109 0 14 28 | B1->B0 | 3030 2626 | 1 0 | (1 0) (1 0)
5289 23:53:36.847278 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5290 23:53:36.850404 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 23:53:36.857403 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 23:53:36.860371 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 23:53:36.863433 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 23:53:36.870646 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 23:53:36.873231 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5296 23:53:36.880286 0 15 28 | B1->B0 | 3232 3b3b | 0 1 | (0 0) (0 0)
5297 23:53:36.883476 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5298 23:53:36.886620 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 23:53:36.893685 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 23:53:36.896586 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 23:53:36.900096 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 23:53:36.906387 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 23:53:36.909716 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5304 23:53:36.913014 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5305 23:53:36.919576 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 23:53:36.923260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 23:53:36.926252 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 23:53:36.932701 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 23:53:36.936030 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 23:53:36.939122 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 23:53:36.946091 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 23:53:36.949106 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 23:53:36.952380 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 23:53:36.959306 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 23:53:36.962382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 23:53:36.965550 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 23:53:36.972579 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 23:53:36.975513 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:53:36.978982 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:53:36.985493 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5321 23:53:36.985597 Total UI for P1: 0, mck2ui 16
5322 23:53:36.992354 best dqsien dly found for B0: ( 1, 2, 26)
5323 23:53:36.995263 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5324 23:53:36.998617 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 23:53:37.001633 Total UI for P1: 0, mck2ui 16
5326 23:53:37.005157 best dqsien dly found for B1: ( 1, 2, 30)
5327 23:53:37.008389 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5328 23:53:37.011723 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5329 23:53:37.011803
5330 23:53:37.018256 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5331 23:53:37.021829 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5332 23:53:37.021960 [Gating] SW calibration Done
5333 23:53:37.024842 ==
5334 23:53:37.028007 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 23:53:37.031799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 23:53:37.031881 ==
5337 23:53:37.031944 RX Vref Scan: 0
5338 23:53:37.032003
5339 23:53:37.034996 RX Vref 0 -> 0, step: 1
5340 23:53:37.035077
5341 23:53:37.038118 RX Delay -80 -> 252, step: 8
5342 23:53:37.041246 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5343 23:53:37.045063 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5344 23:53:37.048153 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5345 23:53:37.054511 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5346 23:53:37.058310 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5347 23:53:37.061497 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5348 23:53:37.064685 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5349 23:53:37.067617 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5350 23:53:37.071388 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5351 23:53:37.077687 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5352 23:53:37.080875 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5353 23:53:37.084493 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5354 23:53:37.087527 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5355 23:53:37.090689 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5356 23:53:37.097194 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5357 23:53:37.100876 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5358 23:53:37.100956 ==
5359 23:53:37.104029 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 23:53:37.107246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 23:53:37.107328 ==
5362 23:53:37.107416 DQS Delay:
5363 23:53:37.110817 DQS0 = 0, DQS1 = 0
5364 23:53:37.110898 DQM Delay:
5365 23:53:37.114233 DQM0 = 98, DQM1 = 89
5366 23:53:37.114315 DQ Delay:
5367 23:53:37.117416 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5368 23:53:37.120444 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5369 23:53:37.123796 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5370 23:53:37.127122 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5371 23:53:37.127203
5372 23:53:37.127265
5373 23:53:37.127359 ==
5374 23:53:37.130748 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 23:53:37.136579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 23:53:37.136661 ==
5377 23:53:37.136729
5378 23:53:37.136820
5379 23:53:37.136892 TX Vref Scan disable
5380 23:53:37.140668 == TX Byte 0 ==
5381 23:53:37.143826 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5382 23:53:37.150150 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5383 23:53:37.150266 == TX Byte 1 ==
5384 23:53:37.153857 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5385 23:53:37.160181 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5386 23:53:37.160292 ==
5387 23:53:37.163359 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 23:53:37.167175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 23:53:37.167274 ==
5390 23:53:37.167362
5391 23:53:37.167447
5392 23:53:37.170252 TX Vref Scan disable
5393 23:53:37.170343 == TX Byte 0 ==
5394 23:53:37.177371 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5395 23:53:37.180139 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5396 23:53:37.183248 == TX Byte 1 ==
5397 23:53:37.186371 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5398 23:53:37.190238 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5399 23:53:37.190323
5400 23:53:37.190407 [DATLAT]
5401 23:53:37.193654 Freq=933, CH0 RK1
5402 23:53:37.193734
5403 23:53:37.193831 DATLAT Default: 0xb
5404 23:53:37.196700 0, 0xFFFF, sum = 0
5405 23:53:37.199727 1, 0xFFFF, sum = 0
5406 23:53:37.199812 2, 0xFFFF, sum = 0
5407 23:53:37.203430 3, 0xFFFF, sum = 0
5408 23:53:37.203507 4, 0xFFFF, sum = 0
5409 23:53:37.206538 5, 0xFFFF, sum = 0
5410 23:53:37.206619 6, 0xFFFF, sum = 0
5411 23:53:37.209639 7, 0xFFFF, sum = 0
5412 23:53:37.209745 8, 0xFFFF, sum = 0
5413 23:53:37.213175 9, 0xFFFF, sum = 0
5414 23:53:37.213328 10, 0x0, sum = 1
5415 23:53:37.216166 11, 0x0, sum = 2
5416 23:53:37.216272 12, 0x0, sum = 3
5417 23:53:37.219647 13, 0x0, sum = 4
5418 23:53:37.219750 best_step = 11
5419 23:53:37.219851
5420 23:53:37.219947 ==
5421 23:53:37.223169 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 23:53:37.226050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 23:53:37.226163 ==
5424 23:53:37.229961 RX Vref Scan: 0
5425 23:53:37.230035
5426 23:53:37.233126 RX Vref 0 -> 0, step: 1
5427 23:53:37.233199
5428 23:53:37.233323 RX Delay -53 -> 252, step: 4
5429 23:53:37.240944 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5430 23:53:37.244105 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5431 23:53:37.247389 iDelay=195, Bit 2, Center 92 (-1 ~ 186) 188
5432 23:53:37.250946 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5433 23:53:37.254130 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5434 23:53:37.260506 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5435 23:53:37.263674 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5436 23:53:37.266913 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5437 23:53:37.270090 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5438 23:53:37.273878 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5439 23:53:37.280336 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5440 23:53:37.283753 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5441 23:53:37.286987 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5442 23:53:37.290098 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5443 23:53:37.293249 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5444 23:53:37.299961 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5445 23:53:37.300040 ==
5446 23:53:37.303088 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 23:53:37.306567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 23:53:37.306646 ==
5449 23:53:37.306734 DQS Delay:
5450 23:53:37.309656 DQS0 = 0, DQS1 = 0
5451 23:53:37.309734 DQM Delay:
5452 23:53:37.312812 DQM0 = 97, DQM1 = 89
5453 23:53:37.312912 DQ Delay:
5454 23:53:37.316474 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5455 23:53:37.319691 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =104
5456 23:53:37.322799 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5457 23:53:37.326008 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5458 23:53:37.326114
5459 23:53:37.326219
5460 23:53:37.336483 [DQSOSCAuto] RK1, (LSB)MR18= 0x1714, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5461 23:53:37.336640 CH0 RK1: MR19=505, MR18=1714
5462 23:53:37.342755 CH0_RK1: MR19=0x505, MR18=0x1714, DQSOSC=414, MR23=63, INC=63, DEC=42
5463 23:53:37.345811 [RxdqsGatingPostProcess] freq 933
5464 23:53:37.352929 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5465 23:53:37.356025 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 23:53:37.359096 best DQS1 dly(2T, 0.5T) = (0, 10)
5467 23:53:37.362779 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 23:53:37.365782 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5469 23:53:37.368845 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 23:53:37.368950 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 23:53:37.372031 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 23:53:37.375759 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 23:53:37.378747 Pre-setting of DQS Precalculation
5474 23:53:37.385357 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5475 23:53:37.385443 ==
5476 23:53:37.388546 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 23:53:37.392140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 23:53:37.392243 ==
5479 23:53:37.398587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5480 23:53:37.405326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5481 23:53:37.408471 [CA 0] Center 36 (6~67) winsize 62
5482 23:53:37.411594 [CA 1] Center 36 (6~67) winsize 62
5483 23:53:37.415241 [CA 2] Center 34 (4~65) winsize 62
5484 23:53:37.418268 [CA 3] Center 34 (4~64) winsize 61
5485 23:53:37.421304 [CA 4] Center 34 (4~64) winsize 61
5486 23:53:37.425117 [CA 5] Center 33 (3~64) winsize 62
5487 23:53:37.425220
5488 23:53:37.428183 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5489 23:53:37.428264
5490 23:53:37.431650 [CATrainingPosCal] consider 1 rank data
5491 23:53:37.434763 u2DelayCellTimex100 = 270/100 ps
5492 23:53:37.438186 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 23:53:37.441074 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 23:53:37.444657 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 23:53:37.447708 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5496 23:53:37.454481 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5497 23:53:37.457528 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5498 23:53:37.457612
5499 23:53:37.460996 CA PerBit enable=1, Macro0, CA PI delay=33
5500 23:53:37.461097
5501 23:53:37.464294 [CBTSetCACLKResult] CA Dly = 33
5502 23:53:37.464372 CS Dly: 5 (0~36)
5503 23:53:37.464452 ==
5504 23:53:37.467510 Dram Type= 6, Freq= 0, CH_1, rank 1
5505 23:53:37.471237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 23:53:37.474136 ==
5507 23:53:37.477406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 23:53:37.484411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5509 23:53:37.487700 [CA 0] Center 36 (6~66) winsize 61
5510 23:53:37.490477 [CA 1] Center 36 (6~67) winsize 62
5511 23:53:37.494161 [CA 2] Center 34 (4~64) winsize 61
5512 23:53:37.497299 [CA 3] Center 33 (3~64) winsize 62
5513 23:53:37.500606 [CA 4] Center 33 (3~64) winsize 62
5514 23:53:37.503794 [CA 5] Center 33 (3~64) winsize 62
5515 23:53:37.503901
5516 23:53:37.507155 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5517 23:53:37.507235
5518 23:53:37.510440 [CATrainingPosCal] consider 2 rank data
5519 23:53:37.513666 u2DelayCellTimex100 = 270/100 ps
5520 23:53:37.517425 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5521 23:53:37.520314 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 23:53:37.527062 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 23:53:37.530364 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 23:53:37.533339 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 23:53:37.537128 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5526 23:53:37.537252
5527 23:53:37.540283 CA PerBit enable=1, Macro0, CA PI delay=33
5528 23:53:37.540386
5529 23:53:37.543444 [CBTSetCACLKResult] CA Dly = 33
5530 23:53:37.543521 CS Dly: 6 (0~38)
5531 23:53:37.543601
5532 23:53:37.550151 ----->DramcWriteLeveling(PI) begin...
5533 23:53:37.550243 ==
5534 23:53:37.553474 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 23:53:37.556951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 23:53:37.557073 ==
5537 23:53:37.560330 Write leveling (Byte 0): 28 => 28
5538 23:53:37.563125 Write leveling (Byte 1): 29 => 29
5539 23:53:37.566567 DramcWriteLeveling(PI) end<-----
5540 23:53:37.566653
5541 23:53:37.566736 ==
5542 23:53:37.569722 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 23:53:37.572963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 23:53:37.573059 ==
5545 23:53:37.576609 [Gating] SW mode calibration
5546 23:53:37.582990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5547 23:53:37.589855 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5548 23:53:37.593231 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 23:53:37.596300 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 23:53:37.603229 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 23:53:37.606272 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 23:53:37.609644 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 23:53:37.616061 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 23:53:37.619281 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
5555 23:53:37.623015 0 14 28 | B1->B0 | 2a2a 2525 | 0 0 | (1 0) (0 1)
5556 23:53:37.629044 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 23:53:37.632646 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 23:53:37.635903 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 23:53:37.642225 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 23:53:37.646055 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 23:53:37.649107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 23:53:37.655410 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 23:53:37.659056 0 15 28 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
5564 23:53:37.662482 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 23:53:37.669143 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 23:53:37.672013 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 23:53:37.675204 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 23:53:37.682362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 23:53:37.685352 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 23:53:37.688543 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5571 23:53:37.695502 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5572 23:53:37.698513 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5573 23:53:37.701707 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 23:53:37.708436 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 23:53:37.711612 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 23:53:37.714929 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 23:53:37.721232 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 23:53:37.725040 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 23:53:37.728164 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 23:53:37.734798 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:53:37.737835 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:53:37.741654 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:53:37.747899 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:53:37.751216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:53:37.754433 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:53:37.760720 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5587 23:53:37.763943 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5588 23:53:37.767769 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 23:53:37.770795 Total UI for P1: 0, mck2ui 16
5590 23:53:37.774310 best dqsien dly found for B0: ( 1, 2, 28)
5591 23:53:37.777252 Total UI for P1: 0, mck2ui 16
5592 23:53:37.781059 best dqsien dly found for B1: ( 1, 2, 26)
5593 23:53:37.783987 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5594 23:53:37.787561 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5595 23:53:37.787651
5596 23:53:37.794367 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5597 23:53:37.797501 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5598 23:53:37.797589 [Gating] SW calibration Done
5599 23:53:37.800614 ==
5600 23:53:37.803716 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 23:53:37.807616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 23:53:37.807705 ==
5603 23:53:37.807771 RX Vref Scan: 0
5604 23:53:37.807832
5605 23:53:37.810878 RX Vref 0 -> 0, step: 1
5606 23:53:37.810961
5607 23:53:37.813851 RX Delay -80 -> 252, step: 8
5608 23:53:37.817003 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5609 23:53:37.820807 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5610 23:53:37.823958 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5611 23:53:37.830150 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5612 23:53:37.833881 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5613 23:53:37.837187 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5614 23:53:37.840088 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5615 23:53:37.843435 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5616 23:53:37.847093 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5617 23:53:37.853376 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5618 23:53:37.856350 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5619 23:53:37.860118 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5620 23:53:37.863391 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5621 23:53:37.866487 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5622 23:53:37.872947 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5623 23:53:37.876500 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5624 23:53:37.876582 ==
5625 23:53:37.880094 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 23:53:37.882941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 23:53:37.883023 ==
5628 23:53:37.886357 DQS Delay:
5629 23:53:37.886442 DQS0 = 0, DQS1 = 0
5630 23:53:37.886529 DQM Delay:
5631 23:53:37.889687 DQM0 = 100, DQM1 = 95
5632 23:53:37.889789 DQ Delay:
5633 23:53:37.892805 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5634 23:53:37.896548 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5635 23:53:37.899539 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5636 23:53:37.902702 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5637 23:53:37.902815
5638 23:53:37.902919
5639 23:53:37.905977 ==
5640 23:53:37.909130 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 23:53:37.913124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 23:53:37.913238 ==
5643 23:53:37.913356
5644 23:53:37.913464
5645 23:53:37.916101 TX Vref Scan disable
5646 23:53:37.916189 == TX Byte 0 ==
5647 23:53:37.922303 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5648 23:53:37.926098 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5649 23:53:37.926179 == TX Byte 1 ==
5650 23:53:37.932487 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5651 23:53:37.935481 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5652 23:53:37.935564 ==
5653 23:53:37.939012 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 23:53:37.942406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 23:53:37.942491 ==
5656 23:53:37.942556
5657 23:53:37.942616
5658 23:53:37.945347 TX Vref Scan disable
5659 23:53:37.948758 == TX Byte 0 ==
5660 23:53:37.951789 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5661 23:53:37.955028 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5662 23:53:37.958456 == TX Byte 1 ==
5663 23:53:37.961716 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5664 23:53:37.965432 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5665 23:53:37.965513
5666 23:53:37.968579 [DATLAT]
5667 23:53:37.968655 Freq=933, CH1 RK0
5668 23:53:37.968739
5669 23:53:37.971737 DATLAT Default: 0xd
5670 23:53:37.971850 0, 0xFFFF, sum = 0
5671 23:53:37.974831 1, 0xFFFF, sum = 0
5672 23:53:37.974921 2, 0xFFFF, sum = 0
5673 23:53:37.978095 3, 0xFFFF, sum = 0
5674 23:53:37.978177 4, 0xFFFF, sum = 0
5675 23:53:37.981937 5, 0xFFFF, sum = 0
5676 23:53:37.982026 6, 0xFFFF, sum = 0
5677 23:53:37.985054 7, 0xFFFF, sum = 0
5678 23:53:37.988196 8, 0xFFFF, sum = 0
5679 23:53:37.988278 9, 0xFFFF, sum = 0
5680 23:53:37.988370 10, 0x0, sum = 1
5681 23:53:37.991944 11, 0x0, sum = 2
5682 23:53:37.992035 12, 0x0, sum = 3
5683 23:53:37.994769 13, 0x0, sum = 4
5684 23:53:37.994858 best_step = 11
5685 23:53:37.994943
5686 23:53:37.995030 ==
5687 23:53:37.998080 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 23:53:38.004651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 23:53:38.004797 ==
5690 23:53:38.004871 RX Vref Scan: 1
5691 23:53:38.004932
5692 23:53:38.008182 RX Vref 0 -> 0, step: 1
5693 23:53:38.008308
5694 23:53:38.011239 RX Delay -53 -> 252, step: 4
5695 23:53:38.011362
5696 23:53:38.014664 Set Vref, RX VrefLevel [Byte0]: 49
5697 23:53:38.017467 [Byte1]: 52
5698 23:53:38.017579
5699 23:53:38.021462 Final RX Vref Byte 0 = 49 to rank0
5700 23:53:38.024573 Final RX Vref Byte 1 = 52 to rank0
5701 23:53:38.027614 Final RX Vref Byte 0 = 49 to rank1
5702 23:53:38.030737 Final RX Vref Byte 1 = 52 to rank1==
5703 23:53:38.034368 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 23:53:38.037394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 23:53:38.040616 ==
5706 23:53:38.040690 DQS Delay:
5707 23:53:38.040752 DQS0 = 0, DQS1 = 0
5708 23:53:38.043922 DQM Delay:
5709 23:53:38.044035 DQM0 = 98, DQM1 = 94
5710 23:53:38.047622 DQ Delay:
5711 23:53:38.050833 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =98
5712 23:53:38.053997 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5713 23:53:38.057243 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5714 23:53:38.060662 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5715 23:53:38.060745
5716 23:53:38.060849
5717 23:53:38.067227 [DQSOSCAuto] RK0, (LSB)MR18= 0x616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 420 ps
5718 23:53:38.070339 CH1 RK0: MR19=505, MR18=616
5719 23:53:38.077132 CH1_RK0: MR19=0x505, MR18=0x616, DQSOSC=414, MR23=63, INC=63, DEC=42
5720 23:53:38.077244
5721 23:53:38.080341 ----->DramcWriteLeveling(PI) begin...
5722 23:53:38.080424 ==
5723 23:53:38.083695 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 23:53:38.086694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 23:53:38.086782 ==
5726 23:53:38.090414 Write leveling (Byte 0): 25 => 25
5727 23:53:38.093465 Write leveling (Byte 1): 26 => 26
5728 23:53:38.096635 DramcWriteLeveling(PI) end<-----
5729 23:53:38.096717
5730 23:53:38.096822 ==
5731 23:53:38.100603 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 23:53:38.103635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 23:53:38.106642 ==
5734 23:53:38.106719 [Gating] SW mode calibration
5735 23:53:38.113286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5736 23:53:38.119813 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5737 23:53:38.123389 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5738 23:53:38.130021 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 23:53:38.133021 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 23:53:38.136250 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 23:53:38.143013 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 23:53:38.146143 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 23:53:38.149912 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
5744 23:53:38.156315 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5745 23:53:38.159517 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5746 23:53:38.162857 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 23:53:38.169322 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 23:53:38.172348 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 23:53:38.175653 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 23:53:38.182567 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 23:53:38.186003 0 15 24 | B1->B0 | 2727 3737 | 1 0 | (0 0) (0 0)
5752 23:53:38.189182 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5753 23:53:38.195623 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 23:53:38.199077 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 23:53:38.202160 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 23:53:38.208410 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 23:53:38.212211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 23:53:38.215247 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 23:53:38.221992 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 23:53:38.225087 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 23:53:38.228513 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 23:53:38.235029 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 23:53:38.238335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 23:53:38.241471 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 23:53:38.248404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 23:53:38.251480 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 23:53:38.254537 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 23:53:38.261610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 23:53:38.264788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 23:53:38.268041 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 23:53:38.274891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 23:53:38.278295 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 23:53:38.281253 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 23:53:38.287579 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:53:38.290924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5776 23:53:38.294161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 23:53:38.297358 Total UI for P1: 0, mck2ui 16
5778 23:53:38.300761 best dqsien dly found for B0: ( 1, 2, 24)
5779 23:53:38.304531 Total UI for P1: 0, mck2ui 16
5780 23:53:38.307224 best dqsien dly found for B1: ( 1, 2, 24)
5781 23:53:38.310996 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5782 23:53:38.317080 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5783 23:53:38.317192
5784 23:53:38.320932 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5785 23:53:38.324254 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5786 23:53:38.327330 [Gating] SW calibration Done
5787 23:53:38.327409 ==
5788 23:53:38.330547 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 23:53:38.334012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 23:53:38.334101 ==
5791 23:53:38.337072 RX Vref Scan: 0
5792 23:53:38.337180
5793 23:53:38.337279 RX Vref 0 -> 0, step: 1
5794 23:53:38.337351
5795 23:53:38.340174 RX Delay -80 -> 252, step: 8
5796 23:53:38.343890 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5797 23:53:38.349989 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5798 23:53:38.353123 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5799 23:53:38.356923 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5800 23:53:38.360174 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5801 23:53:38.363308 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5802 23:53:38.366393 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5803 23:53:38.373352 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5804 23:53:38.376465 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5805 23:53:38.379767 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5806 23:53:38.383343 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5807 23:53:38.386556 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5808 23:53:38.389591 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5809 23:53:38.396387 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5810 23:53:38.399970 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5811 23:53:38.403085 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5812 23:53:38.403168 ==
5813 23:53:38.406673 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 23:53:38.409654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 23:53:38.409751 ==
5816 23:53:38.412722 DQS Delay:
5817 23:53:38.412803 DQS0 = 0, DQS1 = 0
5818 23:53:38.416414 DQM Delay:
5819 23:53:38.416522 DQM0 = 97, DQM1 = 94
5820 23:53:38.416613 DQ Delay:
5821 23:53:38.419571 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5822 23:53:38.423062 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5823 23:53:38.426063 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5824 23:53:38.432610 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5825 23:53:38.432707
5826 23:53:38.432770
5827 23:53:38.432843 ==
5828 23:53:38.435872 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 23:53:38.439367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 23:53:38.439452 ==
5831 23:53:38.439518
5832 23:53:38.439579
5833 23:53:38.442533 TX Vref Scan disable
5834 23:53:38.442616 == TX Byte 0 ==
5835 23:53:38.448882 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5836 23:53:38.452047 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5837 23:53:38.452188 == TX Byte 1 ==
5838 23:53:38.458624 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5839 23:53:38.462604 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5840 23:53:38.462689 ==
5841 23:53:38.465795 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 23:53:38.468875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 23:53:38.468970 ==
5844 23:53:38.469034
5845 23:53:38.471970
5846 23:53:38.472051 TX Vref Scan disable
5847 23:53:38.475896 == TX Byte 0 ==
5848 23:53:38.478961 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5849 23:53:38.482246 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5850 23:53:38.485264 == TX Byte 1 ==
5851 23:53:38.488443 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5852 23:53:38.495364 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5853 23:53:38.495444
5854 23:53:38.495515 [DATLAT]
5855 23:53:38.495575 Freq=933, CH1 RK1
5856 23:53:38.495650
5857 23:53:38.498414 DATLAT Default: 0xb
5858 23:53:38.498488 0, 0xFFFF, sum = 0
5859 23:53:38.501494 1, 0xFFFF, sum = 0
5860 23:53:38.505187 2, 0xFFFF, sum = 0
5861 23:53:38.505306 3, 0xFFFF, sum = 0
5862 23:53:38.508259 4, 0xFFFF, sum = 0
5863 23:53:38.508342 5, 0xFFFF, sum = 0
5864 23:53:38.511438 6, 0xFFFF, sum = 0
5865 23:53:38.511522 7, 0xFFFF, sum = 0
5866 23:53:38.514932 8, 0xFFFF, sum = 0
5867 23:53:38.515017 9, 0xFFFF, sum = 0
5868 23:53:38.517840 10, 0x0, sum = 1
5869 23:53:38.517924 11, 0x0, sum = 2
5870 23:53:38.521589 12, 0x0, sum = 3
5871 23:53:38.521673 13, 0x0, sum = 4
5872 23:53:38.524827 best_step = 11
5873 23:53:38.524947
5874 23:53:38.525041 ==
5875 23:53:38.528075 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 23:53:38.531037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 23:53:38.531114 ==
5878 23:53:38.531183 RX Vref Scan: 0
5879 23:53:38.534815
5880 23:53:38.534890 RX Vref 0 -> 0, step: 1
5881 23:53:38.534952
5882 23:53:38.537861 RX Delay -53 -> 252, step: 4
5883 23:53:38.544292 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5884 23:53:38.547417 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5885 23:53:38.550774 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5886 23:53:38.554062 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5887 23:53:38.557892 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5888 23:53:38.564365 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5889 23:53:38.567536 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5890 23:53:38.570846 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5891 23:53:38.574152 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5892 23:53:38.577352 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5893 23:53:38.580351 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5894 23:53:38.587336 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5895 23:53:38.590465 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5896 23:53:38.593588 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5897 23:53:38.597230 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5898 23:53:38.600439 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5899 23:53:38.603536 ==
5900 23:53:38.607142 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 23:53:38.610397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 23:53:38.610480 ==
5903 23:53:38.610545 DQS Delay:
5904 23:53:38.613472 DQS0 = 0, DQS1 = 0
5905 23:53:38.613555 DQM Delay:
5906 23:53:38.616629 DQM0 = 97, DQM1 = 92
5907 23:53:38.616711 DQ Delay:
5908 23:53:38.620349 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5909 23:53:38.623080 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5910 23:53:38.626746 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5911 23:53:38.630131 DQ12 =100, DQ13 =98, DQ14 =96, DQ15 =102
5912 23:53:38.630213
5913 23:53:38.630278
5914 23:53:38.639901 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5915 23:53:38.639987 CH1 RK1: MR19=505, MR18=B22
5916 23:53:38.646221 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5917 23:53:38.649361 [RxdqsGatingPostProcess] freq 933
5918 23:53:38.656303 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5919 23:53:38.659305 best DQS0 dly(2T, 0.5T) = (0, 10)
5920 23:53:38.662603 best DQS1 dly(2T, 0.5T) = (0, 10)
5921 23:53:38.666025 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5922 23:53:38.669109 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5923 23:53:38.669193 best DQS0 dly(2T, 0.5T) = (0, 10)
5924 23:53:38.672593 best DQS1 dly(2T, 0.5T) = (0, 10)
5925 23:53:38.675998 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5926 23:53:38.679042 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5927 23:53:38.682830 Pre-setting of DQS Precalculation
5928 23:53:38.689020 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5929 23:53:38.695928 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5930 23:53:38.702236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5931 23:53:38.702322
5932 23:53:38.702388
5933 23:53:38.706063 [Calibration Summary] 1866 Mbps
5934 23:53:38.708987 CH 0, Rank 0
5935 23:53:38.709089 SW Impedance : PASS
5936 23:53:38.712084 DUTY Scan : NO K
5937 23:53:38.712163 ZQ Calibration : PASS
5938 23:53:38.715203 Jitter Meter : NO K
5939 23:53:38.718940 CBT Training : PASS
5940 23:53:38.719020 Write leveling : PASS
5941 23:53:38.722034 RX DQS gating : PASS
5942 23:53:38.725153 RX DQ/DQS(RDDQC) : PASS
5943 23:53:38.725274 TX DQ/DQS : PASS
5944 23:53:38.728758 RX DATLAT : PASS
5945 23:53:38.732214 RX DQ/DQS(Engine): PASS
5946 23:53:38.732291 TX OE : NO K
5947 23:53:38.735421 All Pass.
5948 23:53:38.735501
5949 23:53:38.735570 CH 0, Rank 1
5950 23:53:38.738797 SW Impedance : PASS
5951 23:53:38.738881 DUTY Scan : NO K
5952 23:53:38.741808 ZQ Calibration : PASS
5953 23:53:38.744857 Jitter Meter : NO K
5954 23:53:38.744935 CBT Training : PASS
5955 23:53:38.748599 Write leveling : PASS
5956 23:53:38.751602 RX DQS gating : PASS
5957 23:53:38.751688 RX DQ/DQS(RDDQC) : PASS
5958 23:53:38.754880 TX DQ/DQS : PASS
5959 23:53:38.758092 RX DATLAT : PASS
5960 23:53:38.758167 RX DQ/DQS(Engine): PASS
5961 23:53:38.761759 TX OE : NO K
5962 23:53:38.761833 All Pass.
5963 23:53:38.761893
5964 23:53:38.764918 CH 1, Rank 0
5965 23:53:38.765015 SW Impedance : PASS
5966 23:53:38.768100 DUTY Scan : NO K
5967 23:53:38.771385 ZQ Calibration : PASS
5968 23:53:38.771502 Jitter Meter : NO K
5969 23:53:38.774679 CBT Training : PASS
5970 23:53:38.778294 Write leveling : PASS
5971 23:53:38.778374 RX DQS gating : PASS
5972 23:53:38.781033 RX DQ/DQS(RDDQC) : PASS
5973 23:53:38.784577 TX DQ/DQS : PASS
5974 23:53:38.784662 RX DATLAT : PASS
5975 23:53:38.788151 RX DQ/DQS(Engine): PASS
5976 23:53:38.788251 TX OE : NO K
5977 23:53:38.791049 All Pass.
5978 23:53:38.791132
5979 23:53:38.791202 CH 1, Rank 1
5980 23:53:38.794672 SW Impedance : PASS
5981 23:53:38.794757 DUTY Scan : NO K
5982 23:53:38.797974 ZQ Calibration : PASS
5983 23:53:38.801097 Jitter Meter : NO K
5984 23:53:38.801208 CBT Training : PASS
5985 23:53:38.804994 Write leveling : PASS
5986 23:53:38.807995 RX DQS gating : PASS
5987 23:53:38.808075 RX DQ/DQS(RDDQC) : PASS
5988 23:53:38.811045 TX DQ/DQS : PASS
5989 23:53:38.814274 RX DATLAT : PASS
5990 23:53:38.814353 RX DQ/DQS(Engine): PASS
5991 23:53:38.817510 TX OE : NO K
5992 23:53:38.817589 All Pass.
5993 23:53:38.817653
5994 23:53:38.820832 DramC Write-DBI off
5995 23:53:38.823989 PER_BANK_REFRESH: Hybrid Mode
5996 23:53:38.824068 TX_TRACKING: ON
5997 23:53:38.834219 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5998 23:53:38.837205 [FAST_K] Save calibration result to emmc
5999 23:53:38.840848 dramc_set_vcore_voltage set vcore to 650000
6000 23:53:38.844173 Read voltage for 400, 6
6001 23:53:38.844275 Vio18 = 0
6002 23:53:38.844369 Vcore = 650000
6003 23:53:38.847247 Vdram = 0
6004 23:53:38.847321 Vddq = 0
6005 23:53:38.847396 Vmddr = 0
6006 23:53:38.854008 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6007 23:53:38.857138 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6008 23:53:38.860377 MEM_TYPE=3, freq_sel=20
6009 23:53:38.864176 sv_algorithm_assistance_LP4_800
6010 23:53:38.867552 ============ PULL DRAM RESETB DOWN ============
6011 23:53:38.873632 ========== PULL DRAM RESETB DOWN end =========
6012 23:53:38.876830 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 23:53:38.880602 ===================================
6014 23:53:38.883614 LPDDR4 DRAM CONFIGURATION
6015 23:53:38.886588 ===================================
6016 23:53:38.886661 EX_ROW_EN[0] = 0x0
6017 23:53:38.890324 EX_ROW_EN[1] = 0x0
6018 23:53:38.890401 LP4Y_EN = 0x0
6019 23:53:38.893449 WORK_FSP = 0x0
6020 23:53:38.893528 WL = 0x2
6021 23:53:38.896493 RL = 0x2
6022 23:53:38.900155 BL = 0x2
6023 23:53:38.900232 RPST = 0x0
6024 23:53:38.903020 RD_PRE = 0x0
6025 23:53:38.903092 WR_PRE = 0x1
6026 23:53:38.906522 WR_PST = 0x0
6027 23:53:38.906620 DBI_WR = 0x0
6028 23:53:38.909945 DBI_RD = 0x0
6029 23:53:38.910019 OTF = 0x1
6030 23:53:38.913276 ===================================
6031 23:53:38.916277 ===================================
6032 23:53:38.919725 ANA top config
6033 23:53:38.922854 ===================================
6034 23:53:38.922937 DLL_ASYNC_EN = 0
6035 23:53:38.926104 ALL_SLAVE_EN = 1
6036 23:53:38.929764 NEW_RANK_MODE = 1
6037 23:53:38.933266 DLL_IDLE_MODE = 1
6038 23:53:38.933349 LP45_APHY_COMB_EN = 1
6039 23:53:38.936347 TX_ODT_DIS = 1
6040 23:53:38.939562 NEW_8X_MODE = 1
6041 23:53:38.942707 ===================================
6042 23:53:38.945999 ===================================
6043 23:53:38.949456 data_rate = 800
6044 23:53:38.952376 CKR = 1
6045 23:53:38.956078 DQ_P2S_RATIO = 4
6046 23:53:38.959176 ===================================
6047 23:53:38.959260 CA_P2S_RATIO = 4
6048 23:53:38.962564 DQ_CA_OPEN = 0
6049 23:53:38.965632 DQ_SEMI_OPEN = 1
6050 23:53:38.968809 CA_SEMI_OPEN = 1
6051 23:53:38.972057 CA_FULL_RATE = 0
6052 23:53:38.975637 DQ_CKDIV4_EN = 0
6053 23:53:38.978975 CA_CKDIV4_EN = 1
6054 23:53:38.979051 CA_PREDIV_EN = 0
6055 23:53:38.982307 PH8_DLY = 0
6056 23:53:38.985426 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6057 23:53:38.988755 DQ_AAMCK_DIV = 0
6058 23:53:38.992342 CA_AAMCK_DIV = 0
6059 23:53:38.995262 CA_ADMCK_DIV = 4
6060 23:53:38.995345 DQ_TRACK_CA_EN = 0
6061 23:53:38.998871 CA_PICK = 800
6062 23:53:39.002099 CA_MCKIO = 400
6063 23:53:39.005204 MCKIO_SEMI = 400
6064 23:53:39.008928 PLL_FREQ = 3016
6065 23:53:39.012012 DQ_UI_PI_RATIO = 32
6066 23:53:39.015076 CA_UI_PI_RATIO = 32
6067 23:53:39.018733 ===================================
6068 23:53:39.021892 ===================================
6069 23:53:39.021967 memory_type:LPDDR4
6070 23:53:39.025185 GP_NUM : 10
6071 23:53:39.028571 SRAM_EN : 1
6072 23:53:39.028647 MD32_EN : 0
6073 23:53:39.031450 ===================================
6074 23:53:39.035118 [ANA_INIT] >>>>>>>>>>>>>>
6075 23:53:39.038031 <<<<<< [CONFIGURE PHASE]: ANA_TX
6076 23:53:39.041459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6077 23:53:39.044755 ===================================
6078 23:53:39.048327 data_rate = 800,PCW = 0X7400
6079 23:53:39.051146 ===================================
6080 23:53:39.054703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6081 23:53:39.058225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 23:53:39.071298 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 23:53:39.074475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6084 23:53:39.077515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6085 23:53:39.081312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6086 23:53:39.084557 [ANA_INIT] flow start
6087 23:53:39.087520 [ANA_INIT] PLL >>>>>>>>
6088 23:53:39.087597 [ANA_INIT] PLL <<<<<<<<
6089 23:53:39.090758 [ANA_INIT] MIDPI >>>>>>>>
6090 23:53:39.094415 [ANA_INIT] MIDPI <<<<<<<<
6091 23:53:39.094487 [ANA_INIT] DLL >>>>>>>>
6092 23:53:39.097343 [ANA_INIT] flow end
6093 23:53:39.100827 ============ LP4 DIFF to SE enter ============
6094 23:53:39.107182 ============ LP4 DIFF to SE exit ============
6095 23:53:39.107258 [ANA_INIT] <<<<<<<<<<<<<
6096 23:53:39.110990 [Flow] Enable top DCM control >>>>>
6097 23:53:39.114134 [Flow] Enable top DCM control <<<<<
6098 23:53:39.117362 Enable DLL master slave shuffle
6099 23:53:39.123577 ==============================================================
6100 23:53:39.123652 Gating Mode config
6101 23:53:39.130654 ==============================================================
6102 23:53:39.133588 Config description:
6103 23:53:39.143608 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6104 23:53:39.150175 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6105 23:53:39.153385 SELPH_MODE 0: By rank 1: By Phase
6106 23:53:39.159818 ==============================================================
6107 23:53:39.163157 GAT_TRACK_EN = 0
6108 23:53:39.166755 RX_GATING_MODE = 2
6109 23:53:39.166836 RX_GATING_TRACK_MODE = 2
6110 23:53:39.169944 SELPH_MODE = 1
6111 23:53:39.173294 PICG_EARLY_EN = 1
6112 23:53:39.176231 VALID_LAT_VALUE = 1
6113 23:53:39.183313 ==============================================================
6114 23:53:39.186543 Enter into Gating configuration >>>>
6115 23:53:39.189552 Exit from Gating configuration <<<<
6116 23:53:39.192706 Enter into DVFS_PRE_config >>>>>
6117 23:53:39.202763 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6118 23:53:39.206287 Exit from DVFS_PRE_config <<<<<
6119 23:53:39.209449 Enter into PICG configuration >>>>
6120 23:53:39.212715 Exit from PICG configuration <<<<
6121 23:53:39.216268 [RX_INPUT] configuration >>>>>
6122 23:53:39.219385 [RX_INPUT] configuration <<<<<
6123 23:53:39.222527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6124 23:53:39.229233 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6125 23:53:39.236025 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6126 23:53:39.242546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6127 23:53:39.249437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6128 23:53:39.252675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6129 23:53:39.258672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6130 23:53:39.262181 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6131 23:53:39.265253 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6132 23:53:39.268803 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6133 23:53:39.275365 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6134 23:53:39.278528 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6135 23:53:39.282203 ===================================
6136 23:53:39.285084 LPDDR4 DRAM CONFIGURATION
6137 23:53:39.288256 ===================================
6138 23:53:39.288339 EX_ROW_EN[0] = 0x0
6139 23:53:39.291980 EX_ROW_EN[1] = 0x0
6140 23:53:39.294704 LP4Y_EN = 0x0
6141 23:53:39.294781 WORK_FSP = 0x0
6142 23:53:39.298549 WL = 0x2
6143 23:53:39.298621 RL = 0x2
6144 23:53:39.301818 BL = 0x2
6145 23:53:39.301917 RPST = 0x0
6146 23:53:39.304959 RD_PRE = 0x0
6147 23:53:39.305030 WR_PRE = 0x1
6148 23:53:39.307896 WR_PST = 0x0
6149 23:53:39.307966 DBI_WR = 0x0
6150 23:53:39.311676 DBI_RD = 0x0
6151 23:53:39.311749 OTF = 0x1
6152 23:53:39.314773 ===================================
6153 23:53:39.317829 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6154 23:53:39.324348 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6155 23:53:39.328100 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 23:53:39.331045 ===================================
6157 23:53:39.334267 LPDDR4 DRAM CONFIGURATION
6158 23:53:39.337390 ===================================
6159 23:53:39.337471 EX_ROW_EN[0] = 0x10
6160 23:53:39.341171 EX_ROW_EN[1] = 0x0
6161 23:53:39.344453 LP4Y_EN = 0x0
6162 23:53:39.344534 WORK_FSP = 0x0
6163 23:53:39.347709 WL = 0x2
6164 23:53:39.347790 RL = 0x2
6165 23:53:39.350871 BL = 0x2
6166 23:53:39.350951 RPST = 0x0
6167 23:53:39.354125 RD_PRE = 0x0
6168 23:53:39.354206 WR_PRE = 0x1
6169 23:53:39.357295 WR_PST = 0x0
6170 23:53:39.357390 DBI_WR = 0x0
6171 23:53:39.360959 DBI_RD = 0x0
6172 23:53:39.361037 OTF = 0x1
6173 23:53:39.364156 ===================================
6174 23:53:39.370469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6175 23:53:39.374961 nWR fixed to 30
6176 23:53:39.378126 [ModeRegInit_LP4] CH0 RK0
6177 23:53:39.378204 [ModeRegInit_LP4] CH0 RK1
6178 23:53:39.381703 [ModeRegInit_LP4] CH1 RK0
6179 23:53:39.385359 [ModeRegInit_LP4] CH1 RK1
6180 23:53:39.385428 match AC timing 19
6181 23:53:39.391384 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6182 23:53:39.395163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6183 23:53:39.398056 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6184 23:53:39.404772 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6185 23:53:39.407800 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6186 23:53:39.407883 ==
6187 23:53:39.411700 Dram Type= 6, Freq= 0, CH_0, rank 0
6188 23:53:39.414648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6189 23:53:39.414732 ==
6190 23:53:39.421107 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6191 23:53:39.427522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6192 23:53:39.431287 [CA 0] Center 36 (8~64) winsize 57
6193 23:53:39.434623 [CA 1] Center 36 (8~64) winsize 57
6194 23:53:39.437574 [CA 2] Center 36 (8~64) winsize 57
6195 23:53:39.441354 [CA 3] Center 36 (8~64) winsize 57
6196 23:53:39.444406 [CA 4] Center 36 (8~64) winsize 57
6197 23:53:39.447679 [CA 5] Center 36 (8~64) winsize 57
6198 23:53:39.447754
6199 23:53:39.451296 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6200 23:53:39.451378
6201 23:53:39.454732 [CATrainingPosCal] consider 1 rank data
6202 23:53:39.457754 u2DelayCellTimex100 = 270/100 ps
6203 23:53:39.460916 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 23:53:39.464174 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 23:53:39.467359 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 23:53:39.471135 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 23:53:39.474167 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 23:53:39.477511 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 23:53:39.477584
6210 23:53:39.480420 CA PerBit enable=1, Macro0, CA PI delay=36
6211 23:53:39.484334
6212 23:53:39.484463 [CBTSetCACLKResult] CA Dly = 36
6213 23:53:39.487406 CS Dly: 1 (0~32)
6214 23:53:39.487479 ==
6215 23:53:39.490481 Dram Type= 6, Freq= 0, CH_0, rank 1
6216 23:53:39.493723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6217 23:53:39.493804 ==
6218 23:53:39.500654 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6219 23:53:39.507003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6220 23:53:39.510319 [CA 0] Center 36 (8~64) winsize 57
6221 23:53:39.513393 [CA 1] Center 36 (8~64) winsize 57
6222 23:53:39.517038 [CA 2] Center 36 (8~64) winsize 57
6223 23:53:39.520031 [CA 3] Center 36 (8~64) winsize 57
6224 23:53:39.520112 [CA 4] Center 36 (8~64) winsize 57
6225 23:53:39.523351 [CA 5] Center 36 (8~64) winsize 57
6226 23:53:39.523433
6227 23:53:39.529939 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6228 23:53:39.530021
6229 23:53:39.533706 [CATrainingPosCal] consider 2 rank data
6230 23:53:39.536802 u2DelayCellTimex100 = 270/100 ps
6231 23:53:39.540152 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 23:53:39.543586 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 23:53:39.546730 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 23:53:39.549831 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 23:53:39.553137 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 23:53:39.556203 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 23:53:39.556285
6238 23:53:39.559770 CA PerBit enable=1, Macro0, CA PI delay=36
6239 23:53:39.559852
6240 23:53:39.563174 [CBTSetCACLKResult] CA Dly = 36
6241 23:53:39.566186 CS Dly: 1 (0~32)
6242 23:53:39.566266
6243 23:53:39.569424 ----->DramcWriteLeveling(PI) begin...
6244 23:53:39.569522 ==
6245 23:53:39.573277 Dram Type= 6, Freq= 0, CH_0, rank 0
6246 23:53:39.576448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 23:53:39.576529 ==
6248 23:53:39.579417 Write leveling (Byte 0): 40 => 8
6249 23:53:39.582908 Write leveling (Byte 1): 40 => 8
6250 23:53:39.585972 DramcWriteLeveling(PI) end<-----
6251 23:53:39.586052
6252 23:53:39.586115 ==
6253 23:53:39.589104 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 23:53:39.592856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 23:53:39.592971 ==
6256 23:53:39.595756 [Gating] SW mode calibration
6257 23:53:39.602565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6258 23:53:39.609477 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6259 23:53:39.612697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 23:53:39.618792 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 23:53:39.622232 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 23:53:39.625224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 23:53:39.632320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 23:53:39.635506 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 23:53:39.638596 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 23:53:39.645107 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 23:53:39.648690 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 23:53:39.652052 Total UI for P1: 0, mck2ui 16
6269 23:53:39.655196 best dqsien dly found for B0: ( 0, 14, 24)
6270 23:53:39.658357 Total UI for P1: 0, mck2ui 16
6271 23:53:39.661470 best dqsien dly found for B1: ( 0, 14, 24)
6272 23:53:39.664859 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6273 23:53:39.668644 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6274 23:53:39.668725
6275 23:53:39.671875 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 23:53:39.674988 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 23:53:39.678244 [Gating] SW calibration Done
6278 23:53:39.678325 ==
6279 23:53:39.681479 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 23:53:39.688403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 23:53:39.688482 ==
6282 23:53:39.688545 RX Vref Scan: 0
6283 23:53:39.688603
6284 23:53:39.691626 RX Vref 0 -> 0, step: 1
6285 23:53:39.691700
6286 23:53:39.694682 RX Delay -410 -> 252, step: 16
6287 23:53:39.698277 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6288 23:53:39.701036 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6289 23:53:39.707957 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6290 23:53:39.711393 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6291 23:53:39.714741 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6292 23:53:39.717929 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6293 23:53:39.724704 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6294 23:53:39.728026 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6295 23:53:39.731071 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6296 23:53:39.734063 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6297 23:53:39.740800 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6298 23:53:39.744267 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6299 23:53:39.747619 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6300 23:53:39.750450 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6301 23:53:39.757746 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6302 23:53:39.760494 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6303 23:53:39.760590 ==
6304 23:53:39.764066 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 23:53:39.767211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 23:53:39.767293 ==
6307 23:53:39.770400 DQS Delay:
6308 23:53:39.770480 DQS0 = 35, DQS1 = 51
6309 23:53:39.773773 DQM Delay:
6310 23:53:39.773867 DQM0 = 4, DQM1 = 10
6311 23:53:39.776907 DQ Delay:
6312 23:53:39.776988 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6313 23:53:39.780880 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6314 23:53:39.783834 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6315 23:53:39.787050 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6316 23:53:39.787131
6317 23:53:39.787194
6318 23:53:39.787254 ==
6319 23:53:39.790269 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 23:53:39.796546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 23:53:39.796628 ==
6322 23:53:39.796692
6323 23:53:39.796751
6324 23:53:39.796808 TX Vref Scan disable
6325 23:53:39.800367 == TX Byte 0 ==
6326 23:53:39.803580 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6327 23:53:39.806664 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6328 23:53:39.810037 == TX Byte 1 ==
6329 23:53:39.812969 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6330 23:53:39.816281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6331 23:53:39.819853 ==
6332 23:53:39.823042 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 23:53:39.826185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 23:53:39.826352 ==
6335 23:53:39.826419
6336 23:53:39.826499
6337 23:53:39.829381 TX Vref Scan disable
6338 23:53:39.829461 == TX Byte 0 ==
6339 23:53:39.833242 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 23:53:39.839446 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 23:53:39.839566 == TX Byte 1 ==
6342 23:53:39.843108 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 23:53:39.849620 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 23:53:39.849706
6345 23:53:39.849770 [DATLAT]
6346 23:53:39.849830 Freq=400, CH0 RK0
6347 23:53:39.849888
6348 23:53:39.852642 DATLAT Default: 0xf
6349 23:53:39.856099 0, 0xFFFF, sum = 0
6350 23:53:39.856183 1, 0xFFFF, sum = 0
6351 23:53:39.858943 2, 0xFFFF, sum = 0
6352 23:53:39.859024 3, 0xFFFF, sum = 0
6353 23:53:39.862525 4, 0xFFFF, sum = 0
6354 23:53:39.862678 5, 0xFFFF, sum = 0
6355 23:53:39.865510 6, 0xFFFF, sum = 0
6356 23:53:39.865592 7, 0xFFFF, sum = 0
6357 23:53:39.869102 8, 0xFFFF, sum = 0
6358 23:53:39.869185 9, 0xFFFF, sum = 0
6359 23:53:39.872521 10, 0xFFFF, sum = 0
6360 23:53:39.872605 11, 0xFFFF, sum = 0
6361 23:53:39.875790 12, 0xFFFF, sum = 0
6362 23:53:39.875867 13, 0x0, sum = 1
6363 23:53:39.879065 14, 0x0, sum = 2
6364 23:53:39.879177 15, 0x0, sum = 3
6365 23:53:39.882105 16, 0x0, sum = 4
6366 23:53:39.882188 best_step = 14
6367 23:53:39.882251
6368 23:53:39.882310 ==
6369 23:53:39.885326 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 23:53:39.892196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 23:53:39.892282 ==
6372 23:53:39.892349 RX Vref Scan: 1
6373 23:53:39.892409
6374 23:53:39.895294 RX Vref 0 -> 0, step: 1
6375 23:53:39.895380
6376 23:53:39.898477 RX Delay -343 -> 252, step: 8
6377 23:53:39.898558
6378 23:53:39.901767 Set Vref, RX VrefLevel [Byte0]: 51
6379 23:53:39.905548 [Byte1]: 59
6380 23:53:39.908756
6381 23:53:39.908899 Final RX Vref Byte 0 = 51 to rank0
6382 23:53:39.911982 Final RX Vref Byte 1 = 59 to rank0
6383 23:53:39.915098 Final RX Vref Byte 0 = 51 to rank1
6384 23:53:39.918195 Final RX Vref Byte 1 = 59 to rank1==
6385 23:53:39.921549 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 23:53:39.928286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 23:53:39.928373 ==
6388 23:53:39.928438 DQS Delay:
6389 23:53:39.931340 DQS0 = 44, DQS1 = 60
6390 23:53:39.931410 DQM Delay:
6391 23:53:39.931468 DQM0 = 10, DQM1 = 16
6392 23:53:39.934480 DQ Delay:
6393 23:53:39.938219 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6394 23:53:39.941502 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6395 23:53:39.941579 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6396 23:53:39.947783 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6397 23:53:39.947887
6398 23:53:39.947977
6399 23:53:39.954445 [DQSOSCAuto] RK0, (LSB)MR18= 0x988c, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6400 23:53:39.957919 CH0 RK0: MR19=C0C, MR18=988C
6401 23:53:39.964283 CH0_RK0: MR19=0xC0C, MR18=0x988C, DQSOSC=390, MR23=63, INC=388, DEC=258
6402 23:53:39.964368 ==
6403 23:53:39.967807 Dram Type= 6, Freq= 0, CH_0, rank 1
6404 23:53:39.970905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 23:53:39.971009 ==
6406 23:53:39.974384 [Gating] SW mode calibration
6407 23:53:39.980808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6408 23:53:39.987283 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6409 23:53:39.990414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 23:53:39.994304 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 23:53:40.000464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 23:53:40.003822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 23:53:40.007502 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 23:53:40.014029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 23:53:40.017052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 23:53:40.020317 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 23:53:40.027044 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 23:53:40.030025 Total UI for P1: 0, mck2ui 16
6419 23:53:40.033421 best dqsien dly found for B0: ( 0, 14, 24)
6420 23:53:40.036953 Total UI for P1: 0, mck2ui 16
6421 23:53:40.039977 best dqsien dly found for B1: ( 0, 14, 24)
6422 23:53:40.043586 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6423 23:53:40.046902 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6424 23:53:40.046984
6425 23:53:40.050093 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 23:53:40.053213 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 23:53:40.056361 [Gating] SW calibration Done
6428 23:53:40.056439 ==
6429 23:53:40.060025 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 23:53:40.063234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 23:53:40.063311 ==
6432 23:53:40.066370 RX Vref Scan: 0
6433 23:53:40.066444
6434 23:53:40.069854 RX Vref 0 -> 0, step: 1
6435 23:53:40.069936
6436 23:53:40.072812 RX Delay -410 -> 252, step: 16
6437 23:53:40.075939 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6438 23:53:40.079419 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6439 23:53:40.082843 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6440 23:53:40.089658 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6441 23:53:40.092559 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6442 23:53:40.095839 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6443 23:53:40.099579 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6444 23:53:40.106002 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6445 23:53:40.109201 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6446 23:53:40.112391 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6447 23:53:40.115625 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6448 23:53:40.122744 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6449 23:53:40.125810 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6450 23:53:40.129137 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6451 23:53:40.135247 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6452 23:53:40.138727 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6453 23:53:40.138810 ==
6454 23:53:40.141725 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 23:53:40.145549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 23:53:40.145632 ==
6457 23:53:40.148483 DQS Delay:
6458 23:53:40.148566 DQS0 = 35, DQS1 = 51
6459 23:53:40.152133 DQM Delay:
6460 23:53:40.152215 DQM0 = 6, DQM1 = 9
6461 23:53:40.152280 DQ Delay:
6462 23:53:40.155172 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6463 23:53:40.158639 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6464 23:53:40.161515 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6465 23:53:40.165233 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6466 23:53:40.165383
6467 23:53:40.165477
6468 23:53:40.165565 ==
6469 23:53:40.168436 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 23:53:40.171649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 23:53:40.174782 ==
6472 23:53:40.174870
6473 23:53:40.174934
6474 23:53:40.174994 TX Vref Scan disable
6475 23:53:40.178356 == TX Byte 0 ==
6476 23:53:40.182021 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6477 23:53:40.185038 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6478 23:53:40.188202 == TX Byte 1 ==
6479 23:53:40.191950 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6480 23:53:40.194861 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6481 23:53:40.194943 ==
6482 23:53:40.198219 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 23:53:40.201453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 23:53:40.204788 ==
6485 23:53:40.204895
6486 23:53:40.205014
6487 23:53:40.205101 TX Vref Scan disable
6488 23:53:40.207762 == TX Byte 0 ==
6489 23:53:40.211172 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6490 23:53:40.214358 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6491 23:53:40.218133 == TX Byte 1 ==
6492 23:53:40.221195 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6493 23:53:40.224555 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6494 23:53:40.224662
6495 23:53:40.227643 [DATLAT]
6496 23:53:40.227726 Freq=400, CH0 RK1
6497 23:53:40.227791
6498 23:53:40.230948 DATLAT Default: 0xe
6499 23:53:40.231030 0, 0xFFFF, sum = 0
6500 23:53:40.234123 1, 0xFFFF, sum = 0
6501 23:53:40.234206 2, 0xFFFF, sum = 0
6502 23:53:40.237979 3, 0xFFFF, sum = 0
6503 23:53:40.238080 4, 0xFFFF, sum = 0
6504 23:53:40.241091 5, 0xFFFF, sum = 0
6505 23:53:40.241173 6, 0xFFFF, sum = 0
6506 23:53:40.244071 7, 0xFFFF, sum = 0
6507 23:53:40.244183 8, 0xFFFF, sum = 0
6508 23:53:40.247642 9, 0xFFFF, sum = 0
6509 23:53:40.247727 10, 0xFFFF, sum = 0
6510 23:53:40.250790 11, 0xFFFF, sum = 0
6511 23:53:40.253814 12, 0xFFFF, sum = 0
6512 23:53:40.253925 13, 0x0, sum = 1
6513 23:53:40.257486 14, 0x0, sum = 2
6514 23:53:40.257569 15, 0x0, sum = 3
6515 23:53:40.257635 16, 0x0, sum = 4
6516 23:53:40.260527 best_step = 14
6517 23:53:40.260636
6518 23:53:40.260731 ==
6519 23:53:40.263644 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 23:53:40.266947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 23:53:40.267030 ==
6522 23:53:40.270527 RX Vref Scan: 0
6523 23:53:40.270637
6524 23:53:40.273941 RX Vref 0 -> 0, step: 1
6525 23:53:40.274022
6526 23:53:40.274086 RX Delay -343 -> 252, step: 8
6527 23:53:40.282505 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6528 23:53:40.285781 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6529 23:53:40.289315 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6530 23:53:40.295743 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6531 23:53:40.298928 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6532 23:53:40.302135 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6533 23:53:40.305720 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6534 23:53:40.311865 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6535 23:53:40.315445 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6536 23:53:40.318762 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6537 23:53:40.321825 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6538 23:53:40.328260 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6539 23:53:40.332042 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6540 23:53:40.335156 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6541 23:53:40.338359 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6542 23:53:40.345334 iDelay=209, Bit 15, Center -40 (-287 ~ 208) 496
6543 23:53:40.345437 ==
6544 23:53:40.348313 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 23:53:40.351463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 23:53:40.351542 ==
6547 23:53:40.351605 DQS Delay:
6548 23:53:40.354899 DQS0 = 44, DQS1 = 60
6549 23:53:40.354979 DQM Delay:
6550 23:53:40.357892 DQM0 = 9, DQM1 = 15
6551 23:53:40.357970 DQ Delay:
6552 23:53:40.361559 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6553 23:53:40.364598 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6554 23:53:40.368392 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6555 23:53:40.371657 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =20
6556 23:53:40.371742
6557 23:53:40.371822
6558 23:53:40.377996 [DQSOSCAuto] RK1, (LSB)MR18= 0x8681, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6559 23:53:40.381133 CH0 RK1: MR19=C0C, MR18=8681
6560 23:53:40.387825 CH0_RK1: MR19=0xC0C, MR18=0x8681, DQSOSC=393, MR23=63, INC=382, DEC=254
6561 23:53:40.391337 [RxdqsGatingPostProcess] freq 400
6562 23:53:40.397489 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6563 23:53:40.401359 best DQS0 dly(2T, 0.5T) = (0, 10)
6564 23:53:40.404489 best DQS1 dly(2T, 0.5T) = (0, 10)
6565 23:53:40.407731 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6566 23:53:40.410893 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6567 23:53:40.414675 best DQS0 dly(2T, 0.5T) = (0, 10)
6568 23:53:40.414758 best DQS1 dly(2T, 0.5T) = (0, 10)
6569 23:53:40.417354 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6570 23:53:40.421049 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6571 23:53:40.424140 Pre-setting of DQS Precalculation
6572 23:53:40.430525 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6573 23:53:40.430610 ==
6574 23:53:40.434369 Dram Type= 6, Freq= 0, CH_1, rank 0
6575 23:53:40.437399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 23:53:40.437530 ==
6577 23:53:40.443853 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6578 23:53:40.450669 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6579 23:53:40.453849 [CA 0] Center 36 (8~64) winsize 57
6580 23:53:40.457452 [CA 1] Center 36 (8~64) winsize 57
6581 23:53:40.457535 [CA 2] Center 36 (8~64) winsize 57
6582 23:53:40.460520 [CA 3] Center 36 (8~64) winsize 57
6583 23:53:40.463706 [CA 4] Center 36 (8~64) winsize 57
6584 23:53:40.467186 [CA 5] Center 36 (8~64) winsize 57
6585 23:53:40.467268
6586 23:53:40.470700 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6587 23:53:40.473818
6588 23:53:40.476922 [CATrainingPosCal] consider 1 rank data
6589 23:53:40.477019 u2DelayCellTimex100 = 270/100 ps
6590 23:53:40.483848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 23:53:40.487357 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 23:53:40.490401 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 23:53:40.493529 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 23:53:40.497060 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 23:53:40.499975 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 23:53:40.500057
6597 23:53:40.503576 CA PerBit enable=1, Macro0, CA PI delay=36
6598 23:53:40.503705
6599 23:53:40.506935 [CBTSetCACLKResult] CA Dly = 36
6600 23:53:40.510076 CS Dly: 1 (0~32)
6601 23:53:40.510157 ==
6602 23:53:40.513449 Dram Type= 6, Freq= 0, CH_1, rank 1
6603 23:53:40.516294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 23:53:40.516376 ==
6605 23:53:40.523502 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6606 23:53:40.529568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6607 23:53:40.529655 [CA 0] Center 36 (8~64) winsize 57
6608 23:53:40.533269 [CA 1] Center 36 (8~64) winsize 57
6609 23:53:40.536205 [CA 2] Center 36 (8~64) winsize 57
6610 23:53:40.539381 [CA 3] Center 36 (8~64) winsize 57
6611 23:53:40.542962 [CA 4] Center 36 (8~64) winsize 57
6612 23:53:40.546077 [CA 5] Center 36 (8~64) winsize 57
6613 23:53:40.546186
6614 23:53:40.549144 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6615 23:53:40.549229
6616 23:53:40.556294 [CATrainingPosCal] consider 2 rank data
6617 23:53:40.556373 u2DelayCellTimex100 = 270/100 ps
6618 23:53:40.559571 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 23:53:40.565752 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 23:53:40.569425 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 23:53:40.572798 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 23:53:40.576026 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 23:53:40.578988 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 23:53:40.579063
6625 23:53:40.582405 CA PerBit enable=1, Macro0, CA PI delay=36
6626 23:53:40.582480
6627 23:53:40.585598 [CBTSetCACLKResult] CA Dly = 36
6628 23:53:40.588633 CS Dly: 1 (0~32)
6629 23:53:40.588736
6630 23:53:40.591903 ----->DramcWriteLeveling(PI) begin...
6631 23:53:40.592004 ==
6632 23:53:40.595741 Dram Type= 6, Freq= 0, CH_1, rank 0
6633 23:53:40.598976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 23:53:40.599052 ==
6635 23:53:40.602188 Write leveling (Byte 0): 40 => 8
6636 23:53:40.605189 Write leveling (Byte 1): 40 => 8
6637 23:53:40.608648 DramcWriteLeveling(PI) end<-----
6638 23:53:40.608723
6639 23:53:40.608817 ==
6640 23:53:40.611724 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 23:53:40.615605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:53:40.615714 ==
6643 23:53:40.618816 [Gating] SW mode calibration
6644 23:53:40.625109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6645 23:53:40.631553 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6646 23:53:40.634808 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 23:53:40.638474 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 23:53:40.644740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 23:53:40.648520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 23:53:40.651748 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 23:53:40.657975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 23:53:40.661266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 23:53:40.665033 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 23:53:40.671201 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 23:53:40.674241 Total UI for P1: 0, mck2ui 16
6656 23:53:40.677952 best dqsien dly found for B0: ( 0, 14, 24)
6657 23:53:40.681163 Total UI for P1: 0, mck2ui 16
6658 23:53:40.684359 best dqsien dly found for B1: ( 0, 14, 24)
6659 23:53:40.687555 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6660 23:53:40.691291 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6661 23:53:40.691374
6662 23:53:40.694018 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 23:53:40.697542 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 23:53:40.700688 [Gating] SW calibration Done
6665 23:53:40.700785 ==
6666 23:53:40.703799 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 23:53:40.707449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 23:53:40.710704 ==
6669 23:53:40.710800 RX Vref Scan: 0
6670 23:53:40.710879
6671 23:53:40.713634 RX Vref 0 -> 0, step: 1
6672 23:53:40.713716
6673 23:53:40.716876 RX Delay -410 -> 252, step: 16
6674 23:53:40.720529 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6675 23:53:40.723818 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6676 23:53:40.727059 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6677 23:53:40.733820 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6678 23:53:40.736840 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6679 23:53:40.739997 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6680 23:53:40.743388 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6681 23:53:40.750261 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6682 23:53:40.753299 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6683 23:53:40.756649 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6684 23:53:40.763027 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6685 23:53:40.766684 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6686 23:53:40.769815 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6687 23:53:40.772819 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6688 23:53:40.779449 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6689 23:53:40.783143 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6690 23:53:40.783263 ==
6691 23:53:40.786338 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 23:53:40.789498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 23:53:40.789581 ==
6694 23:53:40.793047 DQS Delay:
6695 23:53:40.793154 DQS0 = 43, DQS1 = 51
6696 23:53:40.796149 DQM Delay:
6697 23:53:40.796230 DQM0 = 13, DQM1 = 13
6698 23:53:40.796294 DQ Delay:
6699 23:53:40.799296 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6700 23:53:40.802412 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6701 23:53:40.806140 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6702 23:53:40.809446 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6703 23:53:40.809528
6704 23:53:40.809591
6705 23:53:40.809651 ==
6706 23:53:40.812789 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 23:53:40.818851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 23:53:40.818938 ==
6709 23:53:40.819002
6710 23:53:40.819062
6711 23:53:40.819119 TX Vref Scan disable
6712 23:53:40.822521 == TX Byte 0 ==
6713 23:53:40.825718 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6714 23:53:40.828899 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6715 23:53:40.832223 == TX Byte 1 ==
6716 23:53:40.835416 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6717 23:53:40.839018 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6718 23:53:40.841987 ==
6719 23:53:40.842076 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 23:53:40.848747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 23:53:40.848830 ==
6722 23:53:40.848896
6723 23:53:40.848999
6724 23:53:40.851865 TX Vref Scan disable
6725 23:53:40.851948 == TX Byte 0 ==
6726 23:53:40.855410 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 23:53:40.861958 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 23:53:40.862044 == TX Byte 1 ==
6729 23:53:40.865185 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 23:53:40.872181 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 23:53:40.872264
6732 23:53:40.872328 [DATLAT]
6733 23:53:40.872388 Freq=400, CH1 RK0
6734 23:53:40.872446
6735 23:53:40.875304 DATLAT Default: 0xf
6736 23:53:40.875386 0, 0xFFFF, sum = 0
6737 23:53:40.878525 1, 0xFFFF, sum = 0
6738 23:53:40.881512 2, 0xFFFF, sum = 0
6739 23:53:40.881595 3, 0xFFFF, sum = 0
6740 23:53:40.885183 4, 0xFFFF, sum = 0
6741 23:53:40.885311 5, 0xFFFF, sum = 0
6742 23:53:40.888173 6, 0xFFFF, sum = 0
6743 23:53:40.888276 7, 0xFFFF, sum = 0
6744 23:53:40.891835 8, 0xFFFF, sum = 0
6745 23:53:40.891909 9, 0xFFFF, sum = 0
6746 23:53:40.895192 10, 0xFFFF, sum = 0
6747 23:53:40.895265 11, 0xFFFF, sum = 0
6748 23:53:40.898252 12, 0xFFFF, sum = 0
6749 23:53:40.898322 13, 0x0, sum = 1
6750 23:53:40.901485 14, 0x0, sum = 2
6751 23:53:40.901597 15, 0x0, sum = 3
6752 23:53:40.905017 16, 0x0, sum = 4
6753 23:53:40.905097 best_step = 14
6754 23:53:40.905187
6755 23:53:40.905297 ==
6756 23:53:40.908280 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 23:53:40.911470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 23:53:40.914701 ==
6759 23:53:40.914784 RX Vref Scan: 1
6760 23:53:40.914849
6761 23:53:40.917820 RX Vref 0 -> 0, step: 1
6762 23:53:40.917900
6763 23:53:40.921058 RX Delay -343 -> 252, step: 8
6764 23:53:40.921140
6765 23:53:40.924622 Set Vref, RX VrefLevel [Byte0]: 49
6766 23:53:40.927931 [Byte1]: 52
6767 23:53:40.928038
6768 23:53:40.931049 Final RX Vref Byte 0 = 49 to rank0
6769 23:53:40.934276 Final RX Vref Byte 1 = 52 to rank0
6770 23:53:40.938125 Final RX Vref Byte 0 = 49 to rank1
6771 23:53:40.941148 Final RX Vref Byte 1 = 52 to rank1==
6772 23:53:40.944106 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 23:53:40.947794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 23:53:40.950756 ==
6775 23:53:40.950866 DQS Delay:
6776 23:53:40.950956 DQS0 = 44, DQS1 = 52
6777 23:53:40.954121 DQM Delay:
6778 23:53:40.954197 DQM0 = 11, DQM1 = 11
6779 23:53:40.957205 DQ Delay:
6780 23:53:40.960858 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6781 23:53:40.960940 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6782 23:53:40.963883 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6783 23:53:40.966982 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6784 23:53:40.967121
6785 23:53:40.967212
6786 23:53:40.977026 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d94, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6787 23:53:40.980267 CH1 RK0: MR19=C0C, MR18=6D94
6788 23:53:40.987067 CH1_RK0: MR19=0xC0C, MR18=0x6D94, DQSOSC=391, MR23=63, INC=386, DEC=257
6789 23:53:40.987211 ==
6790 23:53:40.990122 Dram Type= 6, Freq= 0, CH_1, rank 1
6791 23:53:40.993818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 23:53:40.993918 ==
6793 23:53:40.996652 [Gating] SW mode calibration
6794 23:53:41.003765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6795 23:53:41.009750 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6796 23:53:41.013128 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 23:53:41.016789 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 23:53:41.022935 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 23:53:41.026591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 23:53:41.029854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 23:53:41.036335 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 23:53:41.039930 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 23:53:41.043072 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 23:53:41.049870 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 23:53:41.049960 Total UI for P1: 0, mck2ui 16
6806 23:53:41.056473 best dqsien dly found for B0: ( 0, 14, 24)
6807 23:53:41.056560 Total UI for P1: 0, mck2ui 16
6808 23:53:41.059581 best dqsien dly found for B1: ( 0, 14, 24)
6809 23:53:41.065930 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6810 23:53:41.069078 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6811 23:53:41.069190
6812 23:53:41.072829 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 23:53:41.075927 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 23:53:41.079079 [Gating] SW calibration Done
6815 23:53:41.079163 ==
6816 23:53:41.082902 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 23:53:41.086213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 23:53:41.086296 ==
6819 23:53:41.089372 RX Vref Scan: 0
6820 23:53:41.089455
6821 23:53:41.089519 RX Vref 0 -> 0, step: 1
6822 23:53:41.089579
6823 23:53:41.092404 RX Delay -410 -> 252, step: 16
6824 23:53:41.098968 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6825 23:53:41.102067 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6826 23:53:41.105563 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6827 23:53:41.108734 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6828 23:53:41.115580 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6829 23:53:41.118799 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6830 23:53:41.122152 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6831 23:53:41.125150 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6832 23:53:41.131983 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6833 23:53:41.135597 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6834 23:53:41.138763 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6835 23:53:41.141685 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6836 23:53:41.148694 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6837 23:53:41.151729 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6838 23:53:41.154959 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6839 23:53:41.161826 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6840 23:53:41.161968 ==
6841 23:53:41.165038 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 23:53:41.168361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 23:53:41.168450 ==
6844 23:53:41.168515 DQS Delay:
6845 23:53:41.171778 DQS0 = 43, DQS1 = 51
6846 23:53:41.171886 DQM Delay:
6847 23:53:41.174726 DQM0 = 9, DQM1 = 14
6848 23:53:41.174807 DQ Delay:
6849 23:53:41.177869 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6850 23:53:41.181141 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6851 23:53:41.184484 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6852 23:53:41.187679 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6853 23:53:41.187777
6854 23:53:41.187870
6855 23:53:41.187961 ==
6856 23:53:41.191137 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 23:53:41.194306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 23:53:41.194404 ==
6859 23:53:41.194496
6860 23:53:41.194572
6861 23:53:41.197541 TX Vref Scan disable
6862 23:53:41.200799 == TX Byte 0 ==
6863 23:53:41.204283 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6864 23:53:41.207408 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6865 23:53:41.210512 == TX Byte 1 ==
6866 23:53:41.213781 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6867 23:53:41.217798 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6868 23:53:41.217917 ==
6869 23:53:41.220731 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 23:53:41.224033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 23:53:41.227103 ==
6872 23:53:41.227186
6873 23:53:41.227249
6874 23:53:41.227308 TX Vref Scan disable
6875 23:53:41.230976 == TX Byte 0 ==
6876 23:53:41.234069 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6877 23:53:41.237308 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6878 23:53:41.240508 == TX Byte 1 ==
6879 23:53:41.243851 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6880 23:53:41.247085 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6881 23:53:41.247172
6882 23:53:41.250263 [DATLAT]
6883 23:53:41.250366 Freq=400, CH1 RK1
6884 23:53:41.250451
6885 23:53:41.253169 DATLAT Default: 0xe
6886 23:53:41.253285 0, 0xFFFF, sum = 0
6887 23:53:41.256645 1, 0xFFFF, sum = 0
6888 23:53:41.256734 2, 0xFFFF, sum = 0
6889 23:53:41.260364 3, 0xFFFF, sum = 0
6890 23:53:41.260470 4, 0xFFFF, sum = 0
6891 23:53:41.263305 5, 0xFFFF, sum = 0
6892 23:53:41.263419 6, 0xFFFF, sum = 0
6893 23:53:41.266844 7, 0xFFFF, sum = 0
6894 23:53:41.266934 8, 0xFFFF, sum = 0
6895 23:53:41.269891 9, 0xFFFF, sum = 0
6896 23:53:41.270026 10, 0xFFFF, sum = 0
6897 23:53:41.273267 11, 0xFFFF, sum = 0
6898 23:53:41.273387 12, 0xFFFF, sum = 0
6899 23:53:41.276787 13, 0x0, sum = 1
6900 23:53:41.276904 14, 0x0, sum = 2
6901 23:53:41.279694 15, 0x0, sum = 3
6902 23:53:41.279776 16, 0x0, sum = 4
6903 23:53:41.283586 best_step = 14
6904 23:53:41.283661
6905 23:53:41.283723 ==
6906 23:53:41.286666 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 23:53:41.289915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 23:53:41.289999 ==
6909 23:53:41.293141 RX Vref Scan: 0
6910 23:53:41.293216
6911 23:53:41.293289 RX Vref 0 -> 0, step: 1
6912 23:53:41.293349
6913 23:53:41.296451 RX Delay -343 -> 252, step: 8
6914 23:53:41.304617 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6915 23:53:41.307962 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6916 23:53:41.310922 iDelay=217, Bit 2, Center -44 (-287 ~ 200) 488
6917 23:53:41.317964 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6918 23:53:41.320842 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6919 23:53:41.324232 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6920 23:53:41.327437 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6921 23:53:41.333928 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6922 23:53:41.337300 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6923 23:53:41.341212 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6924 23:53:41.344318 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6925 23:53:41.350744 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6926 23:53:41.353970 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6927 23:53:41.357094 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6928 23:53:41.360352 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6929 23:53:41.367526 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6930 23:53:41.367616 ==
6931 23:53:41.370405 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 23:53:41.374004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 23:53:41.374106 ==
6934 23:53:41.374172 DQS Delay:
6935 23:53:41.377383 DQS0 = 44, DQS1 = 52
6936 23:53:41.377492 DQM Delay:
6937 23:53:41.380442 DQM0 = 7, DQM1 = 10
6938 23:53:41.380546 DQ Delay:
6939 23:53:41.383388 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =4
6940 23:53:41.386727 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6941 23:53:41.390376 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6942 23:53:41.393734 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6943 23:53:41.393817
6944 23:53:41.393885
6945 23:53:41.399860 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eb6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6946 23:53:41.403565 CH1 RK1: MR19=C0C, MR18=7EB6
6947 23:53:41.409976 CH1_RK1: MR19=0xC0C, MR18=0x7EB6, DQSOSC=387, MR23=63, INC=394, DEC=262
6948 23:53:41.413271 [RxdqsGatingPostProcess] freq 400
6949 23:53:41.419874 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6950 23:53:41.423404 best DQS0 dly(2T, 0.5T) = (0, 10)
6951 23:53:41.426581 best DQS1 dly(2T, 0.5T) = (0, 10)
6952 23:53:41.429897 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6953 23:53:41.432897 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6954 23:53:41.433009 best DQS0 dly(2T, 0.5T) = (0, 10)
6955 23:53:41.436211 best DQS1 dly(2T, 0.5T) = (0, 10)
6956 23:53:41.439459 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6957 23:53:41.443123 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6958 23:53:41.446320 Pre-setting of DQS Precalculation
6959 23:53:41.453453 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6960 23:53:41.459673 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6961 23:53:41.466193 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6962 23:53:41.466281
6963 23:53:41.466347
6964 23:53:41.469029 [Calibration Summary] 800 Mbps
6965 23:53:41.469141 CH 0, Rank 0
6966 23:53:41.472611 SW Impedance : PASS
6967 23:53:41.476065 DUTY Scan : NO K
6968 23:53:41.476148 ZQ Calibration : PASS
6969 23:53:41.479237 Jitter Meter : NO K
6970 23:53:41.482245 CBT Training : PASS
6971 23:53:41.482328 Write leveling : PASS
6972 23:53:41.485355 RX DQS gating : PASS
6973 23:53:41.488663 RX DQ/DQS(RDDQC) : PASS
6974 23:53:41.488743 TX DQ/DQS : PASS
6975 23:53:41.492222 RX DATLAT : PASS
6976 23:53:41.495519 RX DQ/DQS(Engine): PASS
6977 23:53:41.495603 TX OE : NO K
6978 23:53:41.498756 All Pass.
6979 23:53:41.498831
6980 23:53:41.498893 CH 0, Rank 1
6981 23:53:41.502338 SW Impedance : PASS
6982 23:53:41.502410 DUTY Scan : NO K
6983 23:53:41.505110 ZQ Calibration : PASS
6984 23:53:41.508716 Jitter Meter : NO K
6985 23:53:41.508792 CBT Training : PASS
6986 23:53:41.511973 Write leveling : NO K
6987 23:53:41.515435 RX DQS gating : PASS
6988 23:53:41.515514 RX DQ/DQS(RDDQC) : PASS
6989 23:53:41.518475 TX DQ/DQS : PASS
6990 23:53:41.522061 RX DATLAT : PASS
6991 23:53:41.522140 RX DQ/DQS(Engine): PASS
6992 23:53:41.525075 TX OE : NO K
6993 23:53:41.525186 All Pass.
6994 23:53:41.525287
6995 23:53:41.528771 CH 1, Rank 0
6996 23:53:41.528877 SW Impedance : PASS
6997 23:53:41.532181 DUTY Scan : NO K
6998 23:53:41.535463 ZQ Calibration : PASS
6999 23:53:41.535544 Jitter Meter : NO K
7000 23:53:41.538223 CBT Training : PASS
7001 23:53:41.541457 Write leveling : PASS
7002 23:53:41.541532 RX DQS gating : PASS
7003 23:53:41.544676 RX DQ/DQS(RDDQC) : PASS
7004 23:53:41.548009 TX DQ/DQS : PASS
7005 23:53:41.548086 RX DATLAT : PASS
7006 23:53:41.551256 RX DQ/DQS(Engine): PASS
7007 23:53:41.555148 TX OE : NO K
7008 23:53:41.555227 All Pass.
7009 23:53:41.555291
7010 23:53:41.555352 CH 1, Rank 1
7011 23:53:41.557775 SW Impedance : PASS
7012 23:53:41.561112 DUTY Scan : NO K
7013 23:53:41.561215 ZQ Calibration : PASS
7014 23:53:41.564355 Jitter Meter : NO K
7015 23:53:41.568110 CBT Training : PASS
7016 23:53:41.568213 Write leveling : NO K
7017 23:53:41.571390 RX DQS gating : PASS
7018 23:53:41.571464 RX DQ/DQS(RDDQC) : PASS
7019 23:53:41.574466 TX DQ/DQS : PASS
7020 23:53:41.578130 RX DATLAT : PASS
7021 23:53:41.578240 RX DQ/DQS(Engine): PASS
7022 23:53:41.581331 TX OE : NO K
7023 23:53:41.581415 All Pass.
7024 23:53:41.581479
7025 23:53:41.584313 DramC Write-DBI off
7026 23:53:41.587665 PER_BANK_REFRESH: Hybrid Mode
7027 23:53:41.587742 TX_TRACKING: ON
7028 23:53:41.597448 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7029 23:53:41.601242 [FAST_K] Save calibration result to emmc
7030 23:53:41.604311 dramc_set_vcore_voltage set vcore to 725000
7031 23:53:41.607455 Read voltage for 1600, 0
7032 23:53:41.607540 Vio18 = 0
7033 23:53:41.610709 Vcore = 725000
7034 23:53:41.610792 Vdram = 0
7035 23:53:41.610856 Vddq = 0
7036 23:53:41.610916 Vmddr = 0
7037 23:53:41.617101 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7038 23:53:41.623773 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7039 23:53:41.623880 MEM_TYPE=3, freq_sel=13
7040 23:53:41.627350 sv_algorithm_assistance_LP4_3733
7041 23:53:41.630713 ============ PULL DRAM RESETB DOWN ============
7042 23:53:41.637331 ========== PULL DRAM RESETB DOWN end =========
7043 23:53:41.640579 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7044 23:53:41.643710 ===================================
7045 23:53:41.647062 LPDDR4 DRAM CONFIGURATION
7046 23:53:41.650143 ===================================
7047 23:53:41.650254 EX_ROW_EN[0] = 0x0
7048 23:53:41.653225 EX_ROW_EN[1] = 0x0
7049 23:53:41.657177 LP4Y_EN = 0x0
7050 23:53:41.657285 WORK_FSP = 0x1
7051 23:53:41.660335 WL = 0x5
7052 23:53:41.660445 RL = 0x5
7053 23:53:41.663775 BL = 0x2
7054 23:53:41.663850 RPST = 0x0
7055 23:53:41.666795 RD_PRE = 0x0
7056 23:53:41.666871 WR_PRE = 0x1
7057 23:53:41.669997 WR_PST = 0x1
7058 23:53:41.670071 DBI_WR = 0x0
7059 23:53:41.673417 DBI_RD = 0x0
7060 23:53:41.673515 OTF = 0x1
7061 23:53:41.676672 ===================================
7062 23:53:41.679797 ===================================
7063 23:53:41.683011 ANA top config
7064 23:53:41.686773 ===================================
7065 23:53:41.686852 DLL_ASYNC_EN = 0
7066 23:53:41.690072 ALL_SLAVE_EN = 0
7067 23:53:41.693240 NEW_RANK_MODE = 1
7068 23:53:41.696518 DLL_IDLE_MODE = 1
7069 23:53:41.699570 LP45_APHY_COMB_EN = 1
7070 23:53:41.699645 TX_ODT_DIS = 0
7071 23:53:41.702759 NEW_8X_MODE = 1
7072 23:53:41.706161 ===================================
7073 23:53:41.709411 ===================================
7074 23:53:41.712764 data_rate = 3200
7075 23:53:41.716567 CKR = 1
7076 23:53:41.719565 DQ_P2S_RATIO = 8
7077 23:53:41.722571 ===================================
7078 23:53:41.726283 CA_P2S_RATIO = 8
7079 23:53:41.726368 DQ_CA_OPEN = 0
7080 23:53:41.729647 DQ_SEMI_OPEN = 0
7081 23:53:41.732354 CA_SEMI_OPEN = 0
7082 23:53:41.736122 CA_FULL_RATE = 0
7083 23:53:41.739225 DQ_CKDIV4_EN = 0
7084 23:53:41.742380 CA_CKDIV4_EN = 0
7085 23:53:41.742466 CA_PREDIV_EN = 0
7086 23:53:41.745840 PH8_DLY = 12
7087 23:53:41.749292 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7088 23:53:41.752611 DQ_AAMCK_DIV = 4
7089 23:53:41.755219 CA_AAMCK_DIV = 4
7090 23:53:41.758859 CA_ADMCK_DIV = 4
7091 23:53:41.758965 DQ_TRACK_CA_EN = 0
7092 23:53:41.762218 CA_PICK = 1600
7093 23:53:41.765307 CA_MCKIO = 1600
7094 23:53:41.768652 MCKIO_SEMI = 0
7095 23:53:41.771863 PLL_FREQ = 3068
7096 23:53:41.775613 DQ_UI_PI_RATIO = 32
7097 23:53:41.778342 CA_UI_PI_RATIO = 0
7098 23:53:41.781655 ===================================
7099 23:53:41.784883 ===================================
7100 23:53:41.788449 memory_type:LPDDR4
7101 23:53:41.788557 GP_NUM : 10
7102 23:53:41.791624 SRAM_EN : 1
7103 23:53:41.791727 MD32_EN : 0
7104 23:53:41.794825 ===================================
7105 23:53:41.798239 [ANA_INIT] >>>>>>>>>>>>>>
7106 23:53:41.801519 <<<<<< [CONFIGURE PHASE]: ANA_TX
7107 23:53:41.805000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7108 23:53:41.808339 ===================================
7109 23:53:41.811398 data_rate = 3200,PCW = 0X7600
7110 23:53:41.814672 ===================================
7111 23:53:41.817914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7112 23:53:41.824562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 23:53:41.827870 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 23:53:41.834569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7115 23:53:41.837784 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7116 23:53:41.841118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7117 23:53:41.841224 [ANA_INIT] flow start
7118 23:53:41.844272 [ANA_INIT] PLL >>>>>>>>
7119 23:53:41.847567 [ANA_INIT] PLL <<<<<<<<
7120 23:53:41.847673 [ANA_INIT] MIDPI >>>>>>>>
7121 23:53:41.851046 [ANA_INIT] MIDPI <<<<<<<<
7122 23:53:41.854074 [ANA_INIT] DLL >>>>>>>>
7123 23:53:41.857760 [ANA_INIT] DLL <<<<<<<<
7124 23:53:41.857865 [ANA_INIT] flow end
7125 23:53:41.860672 ============ LP4 DIFF to SE enter ============
7126 23:53:41.867761 ============ LP4 DIFF to SE exit ============
7127 23:53:41.867846 [ANA_INIT] <<<<<<<<<<<<<
7128 23:53:41.870743 [Flow] Enable top DCM control >>>>>
7129 23:53:41.873715 [Flow] Enable top DCM control <<<<<
7130 23:53:41.877666 Enable DLL master slave shuffle
7131 23:53:41.883571 ==============================================================
7132 23:53:41.883655 Gating Mode config
7133 23:53:41.890695 ==============================================================
7134 23:53:41.893849 Config description:
7135 23:53:41.904173 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7136 23:53:41.910602 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7137 23:53:41.913749 SELPH_MODE 0: By rank 1: By Phase
7138 23:53:41.920153 ==============================================================
7139 23:53:41.923958 GAT_TRACK_EN = 1
7140 23:53:41.926644 RX_GATING_MODE = 2
7141 23:53:41.926726 RX_GATING_TRACK_MODE = 2
7142 23:53:41.929859 SELPH_MODE = 1
7143 23:53:41.933702 PICG_EARLY_EN = 1
7144 23:53:41.936745 VALID_LAT_VALUE = 1
7145 23:53:41.943612 ==============================================================
7146 23:53:41.946909 Enter into Gating configuration >>>>
7147 23:53:41.950242 Exit from Gating configuration <<<<
7148 23:53:41.953323 Enter into DVFS_PRE_config >>>>>
7149 23:53:41.963122 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7150 23:53:41.966091 Exit from DVFS_PRE_config <<<<<
7151 23:53:41.969934 Enter into PICG configuration >>>>
7152 23:53:41.972633 Exit from PICG configuration <<<<
7153 23:53:41.976184 [RX_INPUT] configuration >>>>>
7154 23:53:41.979432 [RX_INPUT] configuration <<<<<
7155 23:53:41.982508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7156 23:53:41.989047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7157 23:53:41.995684 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7158 23:53:42.002759 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7159 23:53:42.008993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7160 23:53:42.015953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7161 23:53:42.019032 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7162 23:53:42.022359 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7163 23:53:42.025707 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7164 23:53:42.031938 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7165 23:53:42.035146 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7166 23:53:42.038406 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7167 23:53:42.041971 ===================================
7168 23:53:42.045165 LPDDR4 DRAM CONFIGURATION
7169 23:53:42.048235 ===================================
7170 23:53:42.048320 EX_ROW_EN[0] = 0x0
7171 23:53:42.051572 EX_ROW_EN[1] = 0x0
7172 23:53:42.055206 LP4Y_EN = 0x0
7173 23:53:42.055311 WORK_FSP = 0x1
7174 23:53:42.058476 WL = 0x5
7175 23:53:42.058581 RL = 0x5
7176 23:53:42.061689 BL = 0x2
7177 23:53:42.061772 RPST = 0x0
7178 23:53:42.064940 RD_PRE = 0x0
7179 23:53:42.065046 WR_PRE = 0x1
7180 23:53:42.068127 WR_PST = 0x1
7181 23:53:42.068212 DBI_WR = 0x0
7182 23:53:42.071385 DBI_RD = 0x0
7183 23:53:42.071468 OTF = 0x1
7184 23:53:42.074665 ===================================
7185 23:53:42.077837 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7186 23:53:42.084547 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7187 23:53:42.088205 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 23:53:42.091111 ===================================
7189 23:53:42.094371 LPDDR4 DRAM CONFIGURATION
7190 23:53:42.097557 ===================================
7191 23:53:42.101335 EX_ROW_EN[0] = 0x10
7192 23:53:42.101419 EX_ROW_EN[1] = 0x0
7193 23:53:42.104497 LP4Y_EN = 0x0
7194 23:53:42.104590 WORK_FSP = 0x1
7195 23:53:42.107699 WL = 0x5
7196 23:53:42.107784 RL = 0x5
7197 23:53:42.110951 BL = 0x2
7198 23:53:42.111040 RPST = 0x0
7199 23:53:42.114364 RD_PRE = 0x0
7200 23:53:42.114447 WR_PRE = 0x1
7201 23:53:42.117673 WR_PST = 0x1
7202 23:53:42.117768 DBI_WR = 0x0
7203 23:53:42.120997 DBI_RD = 0x0
7204 23:53:42.121075 OTF = 0x1
7205 23:53:42.124493 ===================================
7206 23:53:42.131021 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7207 23:53:42.131111 ==
7208 23:53:42.134130 Dram Type= 6, Freq= 0, CH_0, rank 0
7209 23:53:42.140649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7210 23:53:42.140736 ==
7211 23:53:42.140802 [Duty_Offset_Calibration]
7212 23:53:42.143822 B0:2 B1:0 CA:4
7213 23:53:42.143905
7214 23:53:42.147107 [DutyScan_Calibration_Flow] k_type=0
7215 23:53:42.155920
7216 23:53:42.156021 ==CLK 0==
7217 23:53:42.159150 Final CLK duty delay cell = -4
7218 23:53:42.162327 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7219 23:53:42.165969 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7220 23:53:42.168821 [-4] AVG Duty = 4922%(X100)
7221 23:53:42.168930
7222 23:53:42.172066 CH0 CLK Duty spec in!! Max-Min= 218%
7223 23:53:42.175778 [DutyScan_Calibration_Flow] ====Done====
7224 23:53:42.175888
7225 23:53:42.179186 [DutyScan_Calibration_Flow] k_type=1
7226 23:53:42.196249
7227 23:53:42.196368 ==DQS 0 ==
7228 23:53:42.199211 Final DQS duty delay cell = 0
7229 23:53:42.202755 [0] MAX Duty = 5218%(X100), DQS PI = 38
7230 23:53:42.205946 [0] MIN Duty = 5093%(X100), DQS PI = 10
7231 23:53:42.209268 [0] AVG Duty = 5155%(X100)
7232 23:53:42.209380
7233 23:53:42.209473 ==DQS 1 ==
7234 23:53:42.212363 Final DQS duty delay cell = 0
7235 23:53:42.215548 [0] MAX Duty = 5187%(X100), DQS PI = 2
7236 23:53:42.219018 [0] MIN Duty = 4969%(X100), DQS PI = 10
7237 23:53:42.222819 [0] AVG Duty = 5078%(X100)
7238 23:53:42.222905
7239 23:53:42.225770 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7240 23:53:42.225854
7241 23:53:42.229069 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7242 23:53:42.232430 [DutyScan_Calibration_Flow] ====Done====
7243 23:53:42.232517
7244 23:53:42.235486 [DutyScan_Calibration_Flow] k_type=3
7245 23:53:42.253460
7246 23:53:42.253587 ==DQM 0 ==
7247 23:53:42.256403 Final DQM duty delay cell = 0
7248 23:53:42.259628 [0] MAX Duty = 5093%(X100), DQS PI = 22
7249 23:53:42.262954 [0] MIN Duty = 4844%(X100), DQS PI = 56
7250 23:53:42.266058 [0] AVG Duty = 4968%(X100)
7251 23:53:42.266170
7252 23:53:42.266264 ==DQM 1 ==
7253 23:53:42.269498 Final DQM duty delay cell = 0
7254 23:53:42.273097 [0] MAX Duty = 4969%(X100), DQS PI = 0
7255 23:53:42.276150 [0] MIN Duty = 4844%(X100), DQS PI = 10
7256 23:53:42.279462 [0] AVG Duty = 4906%(X100)
7257 23:53:42.279547
7258 23:53:42.282685 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7259 23:53:42.282769
7260 23:53:42.285940 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7261 23:53:42.289082 [DutyScan_Calibration_Flow] ====Done====
7262 23:53:42.289192
7263 23:53:42.292138 [DutyScan_Calibration_Flow] k_type=2
7264 23:53:42.310066
7265 23:53:42.310188 ==DQ 0 ==
7266 23:53:42.313548 Final DQ duty delay cell = 0
7267 23:53:42.316708 [0] MAX Duty = 5124%(X100), DQS PI = 20
7268 23:53:42.320154 [0] MIN Duty = 4938%(X100), DQS PI = 12
7269 23:53:42.320268 [0] AVG Duty = 5031%(X100)
7270 23:53:42.323751
7271 23:53:42.323862 ==DQ 1 ==
7272 23:53:42.326770 Final DQ duty delay cell = 0
7273 23:53:42.330137 [0] MAX Duty = 5187%(X100), DQS PI = 2
7274 23:53:42.333637 [0] MIN Duty = 4907%(X100), DQS PI = 32
7275 23:53:42.333724 [0] AVG Duty = 5047%(X100)
7276 23:53:42.333791
7277 23:53:42.340054 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7278 23:53:42.340167
7279 23:53:42.343351 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7280 23:53:42.346743 [DutyScan_Calibration_Flow] ====Done====
7281 23:53:42.346828 ==
7282 23:53:42.349853 Dram Type= 6, Freq= 0, CH_1, rank 0
7283 23:53:42.353093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 23:53:42.353217 ==
7285 23:53:42.356628 [Duty_Offset_Calibration]
7286 23:53:42.356739 B0:0 B1:-1 CA:3
7287 23:53:42.356836
7288 23:53:42.359804 [DutyScan_Calibration_Flow] k_type=0
7289 23:53:42.370897
7290 23:53:42.370997 ==CLK 0==
7291 23:53:42.373664 Final CLK duty delay cell = 0
7292 23:53:42.377064 [0] MAX Duty = 5187%(X100), DQS PI = 4
7293 23:53:42.380354 [0] MIN Duty = 5000%(X100), DQS PI = 54
7294 23:53:42.383422 [0] AVG Duty = 5093%(X100)
7295 23:53:42.383545
7296 23:53:42.386753 CH1 CLK Duty spec in!! Max-Min= 187%
7297 23:53:42.390041 [DutyScan_Calibration_Flow] ====Done====
7298 23:53:42.390119
7299 23:53:42.393207 [DutyScan_Calibration_Flow] k_type=1
7300 23:53:42.409534
7301 23:53:42.409626 ==DQS 0 ==
7302 23:53:42.412791 Final DQS duty delay cell = 0
7303 23:53:42.415959 [0] MAX Duty = 5218%(X100), DQS PI = 20
7304 23:53:42.419190 [0] MIN Duty = 4907%(X100), DQS PI = 58
7305 23:53:42.422263 [0] AVG Duty = 5062%(X100)
7306 23:53:42.422348
7307 23:53:42.422412 ==DQS 1 ==
7308 23:53:42.425883 Final DQS duty delay cell = -4
7309 23:53:42.428924 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7310 23:53:42.432437 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7311 23:53:42.435802 [-4] AVG Duty = 4906%(X100)
7312 23:53:42.435912
7313 23:53:42.439234 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7314 23:53:42.439318
7315 23:53:42.442659 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7316 23:53:42.445639 [DutyScan_Calibration_Flow] ====Done====
7317 23:53:42.445746
7318 23:53:42.449114 [DutyScan_Calibration_Flow] k_type=3
7319 23:53:42.466389
7320 23:53:42.466482 ==DQM 0 ==
7321 23:53:42.469680 Final DQM duty delay cell = 0
7322 23:53:42.473093 [0] MAX Duty = 5031%(X100), DQS PI = 30
7323 23:53:42.476541 [0] MIN Duty = 4750%(X100), DQS PI = 40
7324 23:53:42.480021 [0] AVG Duty = 4890%(X100)
7325 23:53:42.480105
7326 23:53:42.480171 ==DQM 1 ==
7327 23:53:42.482665 Final DQM duty delay cell = 0
7328 23:53:42.486643 [0] MAX Duty = 4969%(X100), DQS PI = 30
7329 23:53:42.489680 [0] MIN Duty = 4813%(X100), DQS PI = 60
7330 23:53:42.492820 [0] AVG Duty = 4891%(X100)
7331 23:53:42.492903
7332 23:53:42.496345 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7333 23:53:42.496430
7334 23:53:42.499404 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7335 23:53:42.502793 [DutyScan_Calibration_Flow] ====Done====
7336 23:53:42.502878
7337 23:53:42.505992 [DutyScan_Calibration_Flow] k_type=2
7338 23:53:42.522919
7339 23:53:42.523007 ==DQ 0 ==
7340 23:53:42.526007 Final DQ duty delay cell = -4
7341 23:53:42.529239 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7342 23:53:42.532381 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7343 23:53:42.535745 [-4] AVG Duty = 4875%(X100)
7344 23:53:42.535831
7345 23:53:42.535895 ==DQ 1 ==
7346 23:53:42.539165 Final DQ duty delay cell = 0
7347 23:53:42.542131 [0] MAX Duty = 5062%(X100), DQS PI = 32
7348 23:53:42.545512 [0] MIN Duty = 4875%(X100), DQS PI = 0
7349 23:53:42.549313 [0] AVG Duty = 4968%(X100)
7350 23:53:42.549397
7351 23:53:42.552223 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7352 23:53:42.552309
7353 23:53:42.555571 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7354 23:53:42.558979 [DutyScan_Calibration_Flow] ====Done====
7355 23:53:42.562630 nWR fixed to 30
7356 23:53:42.565453 [ModeRegInit_LP4] CH0 RK0
7357 23:53:42.565538 [ModeRegInit_LP4] CH0 RK1
7358 23:53:42.568522 [ModeRegInit_LP4] CH1 RK0
7359 23:53:42.572268 [ModeRegInit_LP4] CH1 RK1
7360 23:53:42.572352 match AC timing 5
7361 23:53:42.578724 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7362 23:53:42.581827 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7363 23:53:42.584953 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7364 23:53:42.592133 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7365 23:53:42.595040 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7366 23:53:42.595126 [MiockJmeterHQA]
7367 23:53:42.598444
7368 23:53:42.598528 [DramcMiockJmeter] u1RxGatingPI = 0
7369 23:53:42.601771 0 : 4257, 4030
7370 23:53:42.601860 4 : 4363, 4137
7371 23:53:42.604932 8 : 4252, 4027
7372 23:53:42.605017 12 : 4362, 4137
7373 23:53:42.608097 16 : 4258, 4029
7374 23:53:42.608181 20 : 4252, 4027
7375 23:53:42.611535 24 : 4253, 4027
7376 23:53:42.611620 28 : 4362, 4137
7377 23:53:42.611686 32 : 4363, 4137
7378 23:53:42.614768 36 : 4363, 4137
7379 23:53:42.614853 40 : 4255, 4029
7380 23:53:42.618023 44 : 4255, 4029
7381 23:53:42.618110 48 : 4253, 4027
7382 23:53:42.621248 52 : 4255, 4029
7383 23:53:42.621342 56 : 4366, 4140
7384 23:53:42.624995 60 : 4252, 4027
7385 23:53:42.625107 64 : 4253, 4027
7386 23:53:42.625202 68 : 4252, 4029
7387 23:53:42.628375 72 : 4249, 4027
7388 23:53:42.628460 76 : 4250, 4027
7389 23:53:42.631434 80 : 4363, 4140
7390 23:53:42.631520 84 : 4361, 4137
7391 23:53:42.634475 88 : 4361, 4137
7392 23:53:42.634560 92 : 4249, 4027
7393 23:53:42.638268 96 : 4250, 2811
7394 23:53:42.638353 100 : 4250, 0
7395 23:53:42.638419 104 : 4250, 0
7396 23:53:42.641525 108 : 4255, 0
7397 23:53:42.641609 112 : 4361, 0
7398 23:53:42.641676 116 : 4252, 0
7399 23:53:42.644699 120 : 4250, 0
7400 23:53:42.644784 124 : 4361, 0
7401 23:53:42.647684 128 : 4360, 0
7402 23:53:42.647769 132 : 4363, 0
7403 23:53:42.647835 136 : 4250, 0
7404 23:53:42.651320 140 : 4250, 0
7405 23:53:42.651432 144 : 4250, 0
7406 23:53:42.654638 148 : 4250, 0
7407 23:53:42.654718 152 : 4252, 0
7408 23:53:42.654783 156 : 4250, 0
7409 23:53:42.657962 160 : 4363, 0
7410 23:53:42.658058 164 : 4252, 0
7411 23:53:42.661145 168 : 4250, 0
7412 23:53:42.661223 172 : 4255, 0
7413 23:53:42.661298 176 : 4361, 0
7414 23:53:42.664152 180 : 4250, 0
7415 23:53:42.664227 184 : 4360, 0
7416 23:53:42.667783 188 : 4250, 0
7417 23:53:42.667862 192 : 4250, 0
7418 23:53:42.667926 196 : 4250, 0
7419 23:53:42.670701 200 : 4249, 0
7420 23:53:42.670777 204 : 4250, 0
7421 23:53:42.670852 208 : 4250, 0
7422 23:53:42.674088 212 : 4252, 0
7423 23:53:42.674164 216 : 4250, 0
7424 23:53:42.677702 220 : 4250, 645
7425 23:53:42.677783 224 : 4252, 4018
7426 23:53:42.680574 228 : 4250, 4027
7427 23:53:42.680652 232 : 4250, 4027
7428 23:53:42.684204 236 : 4363, 4140
7429 23:53:42.684284 240 : 4360, 4137
7430 23:53:42.687443 244 : 4249, 4027
7431 23:53:42.687522 248 : 4360, 4138
7432 23:53:42.687585 252 : 4252, 4029
7433 23:53:42.691099 256 : 4249, 4027
7434 23:53:42.691184 260 : 4252, 4030
7435 23:53:42.694191 264 : 4361, 4137
7436 23:53:42.694276 268 : 4250, 4027
7437 23:53:42.697281 272 : 4250, 4027
7438 23:53:42.697366 276 : 4360, 4138
7439 23:53:42.700534 280 : 4250, 4026
7440 23:53:42.700619 284 : 4252, 4029
7441 23:53:42.703890 288 : 4360, 4138
7442 23:53:42.703975 292 : 4363, 4137
7443 23:53:42.707090 296 : 4250, 4026
7444 23:53:42.707175 300 : 4255, 4029
7445 23:53:42.711124 304 : 4252, 4030
7446 23:53:42.711209 308 : 4250, 4027
7447 23:53:42.711276 312 : 4252, 4030
7448 23:53:42.714072 316 : 4365, 4140
7449 23:53:42.714157 320 : 4252, 4029
7450 23:53:42.717453 324 : 4250, 4027
7451 23:53:42.717538 328 : 4361, 4137
7452 23:53:42.720281 332 : 4250, 3886
7453 23:53:42.720365 336 : 4252, 1667
7454 23:53:42.720432
7455 23:53:42.723644 MIOCK jitter meter ch=0
7456 23:53:42.723734
7457 23:53:42.727292 1T = (336-100) = 236 dly cells
7458 23:53:42.733823 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7459 23:53:42.733913 ==
7460 23:53:42.736987 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 23:53:42.740191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 23:53:42.740275 ==
7463 23:53:42.746687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 23:53:42.749959 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 23:53:42.753507 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 23:53:42.760445 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 23:53:42.768905 [CA 0] Center 44 (14~74) winsize 61
7468 23:53:42.772217 [CA 1] Center 43 (13~74) winsize 62
7469 23:53:42.776007 [CA 2] Center 39 (10~68) winsize 59
7470 23:53:42.779014 [CA 3] Center 38 (9~68) winsize 60
7471 23:53:42.782114 [CA 4] Center 36 (7~66) winsize 60
7472 23:53:42.785625 [CA 5] Center 36 (6~66) winsize 61
7473 23:53:42.785702
7474 23:53:42.788731 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 23:53:42.788805
7476 23:53:42.792067 [CATrainingPosCal] consider 1 rank data
7477 23:53:42.795961 u2DelayCellTimex100 = 275/100 ps
7478 23:53:42.801931 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7479 23:53:42.805868 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7480 23:53:42.808800 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7481 23:53:42.812045 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7482 23:53:42.815072 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7483 23:53:42.818979 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7484 23:53:42.819064
7485 23:53:42.822199 CA PerBit enable=1, Macro0, CA PI delay=36
7486 23:53:42.822283
7487 23:53:42.825280 [CBTSetCACLKResult] CA Dly = 36
7488 23:53:42.828197 CS Dly: 11 (0~42)
7489 23:53:42.831697 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 23:53:42.834865 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 23:53:42.834964 ==
7492 23:53:42.838102 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 23:53:42.844710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 23:53:42.844801 ==
7495 23:53:42.847977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 23:53:42.854409 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 23:53:42.858278 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 23:53:42.864318 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 23:53:42.872743 [CA 0] Center 44 (14~75) winsize 62
7500 23:53:42.875908 [CA 1] Center 44 (14~74) winsize 61
7501 23:53:42.879753 [CA 2] Center 39 (10~69) winsize 60
7502 23:53:42.882844 [CA 3] Center 39 (10~68) winsize 59
7503 23:53:42.886110 [CA 4] Center 37 (7~67) winsize 61
7504 23:53:42.889171 [CA 5] Center 36 (6~66) winsize 61
7505 23:53:42.889263
7506 23:53:42.892392 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7507 23:53:42.892500
7508 23:53:42.899322 [CATrainingPosCal] consider 2 rank data
7509 23:53:42.899404 u2DelayCellTimex100 = 275/100 ps
7510 23:53:42.906017 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7511 23:53:42.909197 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7512 23:53:42.912545 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7513 23:53:42.915327 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7514 23:53:42.919024 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7515 23:53:42.922074 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7516 23:53:42.922159
7517 23:53:42.925367 CA PerBit enable=1, Macro0, CA PI delay=36
7518 23:53:42.925448
7519 23:53:42.928544 [CBTSetCACLKResult] CA Dly = 36
7520 23:53:42.932470 CS Dly: 11 (0~43)
7521 23:53:42.935640 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 23:53:42.938836 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 23:53:42.938918
7524 23:53:42.941748 ----->DramcWriteLeveling(PI) begin...
7525 23:53:42.945323 ==
7526 23:53:42.948745 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 23:53:42.951989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 23:53:42.952071 ==
7529 23:53:42.955132 Write leveling (Byte 0): 33 => 33
7530 23:53:42.958524 Write leveling (Byte 1): 24 => 24
7531 23:53:42.962259 DramcWriteLeveling(PI) end<-----
7532 23:53:42.962337
7533 23:53:42.962399 ==
7534 23:53:42.965463 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 23:53:42.968447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 23:53:42.968530 ==
7537 23:53:42.971583 [Gating] SW mode calibration
7538 23:53:42.978558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 23:53:42.985008 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 23:53:42.988162 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 23:53:42.991933 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 23:53:42.998111 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 23:53:43.001340 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7544 23:53:43.004545 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7545 23:53:43.011377 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7546 23:53:43.014831 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 23:53:43.018256 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 23:53:43.024615 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 23:53:43.027459 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 23:53:43.031028 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7551 23:53:43.037564 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7552 23:53:43.040792 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7553 23:53:43.043903 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7554 23:53:43.051093 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 23:53:43.054235 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 23:53:43.057280 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 23:53:43.063762 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 23:53:43.067036 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7559 23:53:43.070522 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7560 23:53:43.076917 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7561 23:53:43.080547 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7562 23:53:43.083822 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 23:53:43.090267 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 23:53:43.093508 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 23:53:43.096706 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 23:53:43.103156 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7567 23:53:43.106911 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 23:53:43.110206 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7569 23:53:43.116649 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7570 23:53:43.119988 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 23:53:43.123028 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 23:53:43.129564 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 23:53:43.132866 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 23:53:43.136018 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 23:53:43.142556 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 23:53:43.146069 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 23:53:43.149838 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 23:53:43.155812 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 23:53:43.158941 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 23:53:43.162602 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 23:53:43.169216 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 23:53:43.172463 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 23:53:43.175338 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 23:53:43.182121 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 23:53:43.185562 Total UI for P1: 0, mck2ui 16
7586 23:53:43.188466 best dqsien dly found for B0: ( 1, 9, 10)
7587 23:53:43.191704 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 23:53:43.195212 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 23:53:43.198478 Total UI for P1: 0, mck2ui 16
7590 23:53:43.202214 best dqsien dly found for B1: ( 1, 9, 20)
7591 23:53:43.204958 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7592 23:53:43.211884 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 23:53:43.211969
7594 23:53:43.214709 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7595 23:53:43.218184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 23:53:43.221543 [Gating] SW calibration Done
7597 23:53:43.221627 ==
7598 23:53:43.224768 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 23:53:43.228161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 23:53:43.228246 ==
7601 23:53:43.231804 RX Vref Scan: 0
7602 23:53:43.231899
7603 23:53:43.231965 RX Vref 0 -> 0, step: 1
7604 23:53:43.232026
7605 23:53:43.234996 RX Delay 0 -> 252, step: 8
7606 23:53:43.238103 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7607 23:53:43.244399 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7608 23:53:43.248314 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7609 23:53:43.251563 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7610 23:53:43.254590 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7611 23:53:43.257572 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7612 23:53:43.264650 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7613 23:53:43.268036 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7614 23:53:43.270793 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7615 23:53:43.274647 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7616 23:53:43.277671 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7617 23:53:43.284418 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7618 23:53:43.287512 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7619 23:53:43.290775 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7620 23:53:43.293917 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7621 23:53:43.301029 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7622 23:53:43.301119 ==
7623 23:53:43.304137 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 23:53:43.307135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 23:53:43.307220 ==
7626 23:53:43.307291 DQS Delay:
7627 23:53:43.310897 DQS0 = 0, DQS1 = 0
7628 23:53:43.310978 DQM Delay:
7629 23:53:43.314259 DQM0 = 131, DQM1 = 127
7630 23:53:43.314365 DQ Delay:
7631 23:53:43.317326 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7632 23:53:43.320649 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7633 23:53:43.323742 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7634 23:53:43.326982 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7635 23:53:43.327066
7636 23:53:43.327130
7637 23:53:43.330265 ==
7638 23:53:43.333463 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 23:53:43.336685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 23:53:43.336763 ==
7641 23:53:43.336830
7642 23:53:43.336890
7643 23:53:43.340133 TX Vref Scan disable
7644 23:53:43.340208 == TX Byte 0 ==
7645 23:53:43.346779 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7646 23:53:43.350152 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7647 23:53:43.350229 == TX Byte 1 ==
7648 23:53:43.356354 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7649 23:53:43.360231 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7650 23:53:43.360342 ==
7651 23:53:43.363540 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 23:53:43.366240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 23:53:43.366321 ==
7654 23:53:43.380798
7655 23:53:43.383745 TX Vref early break, caculate TX vref
7656 23:53:43.387544 TX Vref=16, minBit 1, minWin=22, winSum=369
7657 23:53:43.390282 TX Vref=18, minBit 8, minWin=22, winSum=379
7658 23:53:43.393720 TX Vref=20, minBit 8, minWin=23, winSum=388
7659 23:53:43.397580 TX Vref=22, minBit 7, minWin=23, winSum=391
7660 23:53:43.400773 TX Vref=24, minBit 7, minWin=24, winSum=406
7661 23:53:43.407348 TX Vref=26, minBit 1, minWin=25, winSum=412
7662 23:53:43.410521 TX Vref=28, minBit 0, minWin=26, winSum=421
7663 23:53:43.413527 TX Vref=30, minBit 2, minWin=25, winSum=414
7664 23:53:43.417133 TX Vref=32, minBit 0, minWin=25, winSum=406
7665 23:53:43.420660 TX Vref=34, minBit 0, minWin=24, winSum=394
7666 23:53:43.427110 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
7667 23:53:43.427215
7668 23:53:43.430417 Final TX Range 0 Vref 28
7669 23:53:43.430529
7670 23:53:43.430619 ==
7671 23:53:43.433640 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 23:53:43.436871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 23:53:43.436987 ==
7674 23:53:43.437090
7675 23:53:43.437190
7676 23:53:43.440245 TX Vref Scan disable
7677 23:53:43.446683 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7678 23:53:43.446769 == TX Byte 0 ==
7679 23:53:43.449899 u2DelayCellOfst[0]=14 cells (4 PI)
7680 23:53:43.453574 u2DelayCellOfst[1]=17 cells (5 PI)
7681 23:53:43.456830 u2DelayCellOfst[2]=14 cells (4 PI)
7682 23:53:43.460140 u2DelayCellOfst[3]=14 cells (4 PI)
7683 23:53:43.463075 u2DelayCellOfst[4]=10 cells (3 PI)
7684 23:53:43.466216 u2DelayCellOfst[5]=0 cells (0 PI)
7685 23:53:43.469432 u2DelayCellOfst[6]=17 cells (5 PI)
7686 23:53:43.473495 u2DelayCellOfst[7]=17 cells (5 PI)
7687 23:53:43.476720 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7688 23:53:43.479936 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7689 23:53:43.482956 == TX Byte 1 ==
7690 23:53:43.486192 u2DelayCellOfst[8]=0 cells (0 PI)
7691 23:53:43.489192 u2DelayCellOfst[9]=3 cells (1 PI)
7692 23:53:43.492650 u2DelayCellOfst[10]=7 cells (2 PI)
7693 23:53:43.492767 u2DelayCellOfst[11]=3 cells (1 PI)
7694 23:53:43.496265 u2DelayCellOfst[12]=10 cells (3 PI)
7695 23:53:43.499378 u2DelayCellOfst[13]=10 cells (3 PI)
7696 23:53:43.502961 u2DelayCellOfst[14]=14 cells (4 PI)
7697 23:53:43.506080 u2DelayCellOfst[15]=10 cells (3 PI)
7698 23:53:43.512266 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7699 23:53:43.515589 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7700 23:53:43.515676 DramC Write-DBI on
7701 23:53:43.519292 ==
7702 23:53:43.522456 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 23:53:43.525646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 23:53:43.525730 ==
7705 23:53:43.525796
7706 23:53:43.525857
7707 23:53:43.529239 TX Vref Scan disable
7708 23:53:43.529354 == TX Byte 0 ==
7709 23:53:43.536002 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7710 23:53:43.536108 == TX Byte 1 ==
7711 23:53:43.538713 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7712 23:53:43.542192 DramC Write-DBI off
7713 23:53:43.542265
7714 23:53:43.542347 [DATLAT]
7715 23:53:43.545572 Freq=1600, CH0 RK0
7716 23:53:43.545650
7717 23:53:43.545731 DATLAT Default: 0xf
7718 23:53:43.548553 0, 0xFFFF, sum = 0
7719 23:53:43.548647 1, 0xFFFF, sum = 0
7720 23:53:43.551956 2, 0xFFFF, sum = 0
7721 23:53:43.555615 3, 0xFFFF, sum = 0
7722 23:53:43.555707 4, 0xFFFF, sum = 0
7723 23:53:43.558299 5, 0xFFFF, sum = 0
7724 23:53:43.558406 6, 0xFFFF, sum = 0
7725 23:53:43.561939 7, 0xFFFF, sum = 0
7726 23:53:43.562018 8, 0xFFFF, sum = 0
7727 23:53:43.565058 9, 0xFFFF, sum = 0
7728 23:53:43.565131 10, 0xFFFF, sum = 0
7729 23:53:43.568217 11, 0xFFFF, sum = 0
7730 23:53:43.568309 12, 0xFFFF, sum = 0
7731 23:53:43.571471 13, 0xFFFF, sum = 0
7732 23:53:43.571577 14, 0x0, sum = 1
7733 23:53:43.575319 15, 0x0, sum = 2
7734 23:53:43.575432 16, 0x0, sum = 3
7735 23:53:43.578445 17, 0x0, sum = 4
7736 23:53:43.578529 best_step = 15
7737 23:53:43.578594
7738 23:53:43.578655 ==
7739 23:53:43.581669 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 23:53:43.584860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 23:53:43.588580 ==
7742 23:53:43.588663 RX Vref Scan: 1
7743 23:53:43.588728
7744 23:53:43.591598 Set Vref Range= 24 -> 127
7745 23:53:43.591680
7746 23:53:43.594666 RX Vref 24 -> 127, step: 1
7747 23:53:43.594748
7748 23:53:43.594813 RX Delay 19 -> 252, step: 4
7749 23:53:43.594874
7750 23:53:43.597945 Set Vref, RX VrefLevel [Byte0]: 24
7751 23:53:43.601131 [Byte1]: 24
7752 23:53:43.605546
7753 23:53:43.605636 Set Vref, RX VrefLevel [Byte0]: 25
7754 23:53:43.608855 [Byte1]: 25
7755 23:53:43.613124
7756 23:53:43.613232 Set Vref, RX VrefLevel [Byte0]: 26
7757 23:53:43.616626 [Byte1]: 26
7758 23:53:43.620510
7759 23:53:43.620593 Set Vref, RX VrefLevel [Byte0]: 27
7760 23:53:43.623959 [Byte1]: 27
7761 23:53:43.628373
7762 23:53:43.628461 Set Vref, RX VrefLevel [Byte0]: 28
7763 23:53:43.631464 [Byte1]: 28
7764 23:53:43.635983
7765 23:53:43.636065 Set Vref, RX VrefLevel [Byte0]: 29
7766 23:53:43.639178 [Byte1]: 29
7767 23:53:43.643546
7768 23:53:43.643628 Set Vref, RX VrefLevel [Byte0]: 30
7769 23:53:43.646341 [Byte1]: 30
7770 23:53:43.650874
7771 23:53:43.650956 Set Vref, RX VrefLevel [Byte0]: 31
7772 23:53:43.654202 [Byte1]: 31
7773 23:53:43.658608
7774 23:53:43.658698 Set Vref, RX VrefLevel [Byte0]: 32
7775 23:53:43.661704 [Byte1]: 32
7776 23:53:43.665944
7777 23:53:43.666028 Set Vref, RX VrefLevel [Byte0]: 33
7778 23:53:43.669154 [Byte1]: 33
7779 23:53:43.673565
7780 23:53:43.673671 Set Vref, RX VrefLevel [Byte0]: 34
7781 23:53:43.676916 [Byte1]: 34
7782 23:53:43.680974
7783 23:53:43.681057 Set Vref, RX VrefLevel [Byte0]: 35
7784 23:53:43.684622 [Byte1]: 35
7785 23:53:43.688975
7786 23:53:43.689056 Set Vref, RX VrefLevel [Byte0]: 36
7787 23:53:43.692265 [Byte1]: 36
7788 23:53:43.696528
7789 23:53:43.696632 Set Vref, RX VrefLevel [Byte0]: 37
7790 23:53:43.699652 [Byte1]: 37
7791 23:53:43.704118
7792 23:53:43.704204 Set Vref, RX VrefLevel [Byte0]: 38
7793 23:53:43.707315 [Byte1]: 38
7794 23:53:43.711311
7795 23:53:43.711391 Set Vref, RX VrefLevel [Byte0]: 39
7796 23:53:43.714693 [Byte1]: 39
7797 23:53:43.718902
7798 23:53:43.718984 Set Vref, RX VrefLevel [Byte0]: 40
7799 23:53:43.722160 [Byte1]: 40
7800 23:53:43.726654
7801 23:53:43.726729 Set Vref, RX VrefLevel [Byte0]: 41
7802 23:53:43.729866 [Byte1]: 41
7803 23:53:43.734122
7804 23:53:43.734197 Set Vref, RX VrefLevel [Byte0]: 42
7805 23:53:43.737433 [Byte1]: 42
7806 23:53:43.741992
7807 23:53:43.742066 Set Vref, RX VrefLevel [Byte0]: 43
7808 23:53:43.745171 [Byte1]: 43
7809 23:53:43.749716
7810 23:53:43.749788 Set Vref, RX VrefLevel [Byte0]: 44
7811 23:53:43.752557 [Byte1]: 44
7812 23:53:43.756787
7813 23:53:43.756896 Set Vref, RX VrefLevel [Byte0]: 45
7814 23:53:43.760004 [Byte1]: 45
7815 23:53:43.764455
7816 23:53:43.764534 Set Vref, RX VrefLevel [Byte0]: 46
7817 23:53:43.768133 [Byte1]: 46
7818 23:53:43.771966
7819 23:53:43.772069 Set Vref, RX VrefLevel [Byte0]: 47
7820 23:53:43.775072 [Byte1]: 47
7821 23:53:43.779319
7822 23:53:43.779422 Set Vref, RX VrefLevel [Byte0]: 48
7823 23:53:43.782708 [Byte1]: 48
7824 23:53:43.787191
7825 23:53:43.787295 Set Vref, RX VrefLevel [Byte0]: 49
7826 23:53:43.790325 [Byte1]: 49
7827 23:53:43.794795
7828 23:53:43.794867 Set Vref, RX VrefLevel [Byte0]: 50
7829 23:53:43.798045 [Byte1]: 50
7830 23:53:43.802278
7831 23:53:43.802379 Set Vref, RX VrefLevel [Byte0]: 51
7832 23:53:43.805917 [Byte1]: 51
7833 23:53:43.809640
7834 23:53:43.809754 Set Vref, RX VrefLevel [Byte0]: 52
7835 23:53:43.813470 [Byte1]: 52
7836 23:53:43.817337
7837 23:53:43.817435 Set Vref, RX VrefLevel [Byte0]: 53
7838 23:53:43.820950 [Byte1]: 53
7839 23:53:43.824703
7840 23:53:43.824804 Set Vref, RX VrefLevel [Byte0]: 54
7841 23:53:43.828315 [Byte1]: 54
7842 23:53:43.833112
7843 23:53:43.833213 Set Vref, RX VrefLevel [Byte0]: 55
7844 23:53:43.835666 [Byte1]: 55
7845 23:53:43.840254
7846 23:53:43.840353 Set Vref, RX VrefLevel [Byte0]: 56
7847 23:53:43.843512 [Byte1]: 56
7848 23:53:43.847752
7849 23:53:43.847853 Set Vref, RX VrefLevel [Byte0]: 57
7850 23:53:43.850944 [Byte1]: 57
7851 23:53:43.855084
7852 23:53:43.855195 Set Vref, RX VrefLevel [Byte0]: 58
7853 23:53:43.858817 [Byte1]: 58
7854 23:53:43.862802
7855 23:53:43.862881 Set Vref, RX VrefLevel [Byte0]: 59
7856 23:53:43.865942 [Byte1]: 59
7857 23:53:43.870355
7858 23:53:43.870427 Set Vref, RX VrefLevel [Byte0]: 60
7859 23:53:43.874250 [Byte1]: 60
7860 23:53:43.877801
7861 23:53:43.877878 Set Vref, RX VrefLevel [Byte0]: 61
7862 23:53:43.881305 [Byte1]: 61
7863 23:53:43.885350
7864 23:53:43.885423 Set Vref, RX VrefLevel [Byte0]: 62
7865 23:53:43.888890 [Byte1]: 62
7866 23:53:43.893153
7867 23:53:43.893304 Set Vref, RX VrefLevel [Byte0]: 63
7868 23:53:43.896323 [Byte1]: 63
7869 23:53:43.900961
7870 23:53:43.901063 Set Vref, RX VrefLevel [Byte0]: 64
7871 23:53:43.904112 [Byte1]: 64
7872 23:53:43.908536
7873 23:53:43.908644 Set Vref, RX VrefLevel [Byte0]: 65
7874 23:53:43.911476 [Byte1]: 65
7875 23:53:43.916001
7876 23:53:43.916089 Set Vref, RX VrefLevel [Byte0]: 66
7877 23:53:43.919099 [Byte1]: 66
7878 23:53:43.923456
7879 23:53:43.923528 Set Vref, RX VrefLevel [Byte0]: 67
7880 23:53:43.926724 [Byte1]: 67
7881 23:53:43.931328
7882 23:53:43.931401 Set Vref, RX VrefLevel [Byte0]: 68
7883 23:53:43.934375 [Byte1]: 68
7884 23:53:43.938762
7885 23:53:43.938834 Set Vref, RX VrefLevel [Byte0]: 69
7886 23:53:43.945222 [Byte1]: 69
7887 23:53:43.945340
7888 23:53:43.948750 Set Vref, RX VrefLevel [Byte0]: 70
7889 23:53:43.951968 [Byte1]: 70
7890 23:53:43.952076
7891 23:53:43.954962 Set Vref, RX VrefLevel [Byte0]: 71
7892 23:53:43.958384 [Byte1]: 71
7893 23:53:43.958468
7894 23:53:43.961459 Set Vref, RX VrefLevel [Byte0]: 72
7895 23:53:43.965012 [Byte1]: 72
7896 23:53:43.968851
7897 23:53:43.968954 Set Vref, RX VrefLevel [Byte0]: 73
7898 23:53:43.972014 [Byte1]: 73
7899 23:53:43.976672
7900 23:53:43.976752 Set Vref, RX VrefLevel [Byte0]: 74
7901 23:53:43.979667 [Byte1]: 74
7902 23:53:43.984120
7903 23:53:43.984198 Set Vref, RX VrefLevel [Byte0]: 75
7904 23:53:43.987199 [Byte1]: 75
7905 23:53:43.991684
7906 23:53:43.991783 Set Vref, RX VrefLevel [Byte0]: 76
7907 23:53:43.994803 [Byte1]: 76
7908 23:53:43.999185
7909 23:53:43.999293 Final RX Vref Byte 0 = 57 to rank0
7910 23:53:44.002720 Final RX Vref Byte 1 = 60 to rank0
7911 23:53:44.005940 Final RX Vref Byte 0 = 57 to rank1
7912 23:53:44.008721 Final RX Vref Byte 1 = 60 to rank1==
7913 23:53:44.012589 Dram Type= 6, Freq= 0, CH_0, rank 0
7914 23:53:44.019221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7915 23:53:44.019339 ==
7916 23:53:44.019445 DQS Delay:
7917 23:53:44.022615 DQS0 = 0, DQS1 = 0
7918 23:53:44.022731 DQM Delay:
7919 23:53:44.022797 DQM0 = 129, DQM1 = 124
7920 23:53:44.025788 DQ Delay:
7921 23:53:44.028905 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7922 23:53:44.032249 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =134
7923 23:53:44.035437 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7924 23:53:44.038460 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =130
7925 23:53:44.038549
7926 23:53:44.038614
7927 23:53:44.038673
7928 23:53:44.041839 [DramC_TX_OE_Calibration] TA2
7929 23:53:44.045598 Original DQ_B0 (3 6) =30, OEN = 27
7930 23:53:44.048743 Original DQ_B1 (3 6) =30, OEN = 27
7931 23:53:44.051994 24, 0x0, End_B0=24 End_B1=24
7932 23:53:44.052077 25, 0x0, End_B0=25 End_B1=25
7933 23:53:44.055237 26, 0x0, End_B0=26 End_B1=26
7934 23:53:44.058777 27, 0x0, End_B0=27 End_B1=27
7935 23:53:44.061848 28, 0x0, End_B0=28 End_B1=28
7936 23:53:44.065285 29, 0x0, End_B0=29 End_B1=29
7937 23:53:44.065376 30, 0x0, End_B0=30 End_B1=30
7938 23:53:44.068603 31, 0x5151, End_B0=30 End_B1=30
7939 23:53:44.071420 Byte0 end_step=30 best_step=27
7940 23:53:44.074714 Byte1 end_step=30 best_step=27
7941 23:53:44.077931 Byte0 TX OE(2T, 0.5T) = (3, 3)
7942 23:53:44.081353 Byte1 TX OE(2T, 0.5T) = (3, 3)
7943 23:53:44.081454
7944 23:53:44.081543
7945 23:53:44.088372 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7946 23:53:44.091605 CH0 RK0: MR19=303, MR18=1A17
7947 23:53:44.098071 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7948 23:53:44.098179
7949 23:53:44.101365 ----->DramcWriteLeveling(PI) begin...
7950 23:53:44.101446 ==
7951 23:53:44.104880 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 23:53:44.108272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 23:53:44.108374 ==
7954 23:53:44.111451 Write leveling (Byte 0): 34 => 34
7955 23:53:44.114576 Write leveling (Byte 1): 25 => 25
7956 23:53:44.117907 DramcWriteLeveling(PI) end<-----
7957 23:53:44.117992
7958 23:53:44.118057 ==
7959 23:53:44.121121 Dram Type= 6, Freq= 0, CH_0, rank 1
7960 23:53:44.127798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 23:53:44.127907 ==
7962 23:53:44.128000 [Gating] SW mode calibration
7963 23:53:44.137729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7964 23:53:44.140898 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7965 23:53:44.144216 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 23:53:44.150535 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 23:53:44.153692 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7968 23:53:44.157815 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7969 23:53:44.164120 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7970 23:53:44.167042 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7971 23:53:44.170838 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 23:53:44.176982 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 23:53:44.179940 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 23:53:44.186893 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7975 23:53:44.190220 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7976 23:53:44.193814 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7977 23:53:44.196944 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7978 23:53:44.203227 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7979 23:53:44.206580 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 23:53:44.213039 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 23:53:44.216171 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 23:53:44.219552 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 23:53:44.226129 1 6 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7984 23:53:44.229997 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7985 23:53:44.233139 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
7986 23:53:44.239816 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 23:53:44.243162 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 23:53:44.245988 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 23:53:44.252483 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 23:53:44.256036 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7991 23:53:44.259146 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7992 23:53:44.265882 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7993 23:53:44.269031 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7994 23:53:44.272604 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7995 23:53:44.278804 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7996 23:53:44.282570 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 23:53:44.285550 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 23:53:44.292077 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 23:53:44.295788 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 23:53:44.298811 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 23:53:44.305820 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 23:53:44.308988 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 23:53:44.312106 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 23:53:44.318933 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 23:53:44.321973 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 23:53:44.325138 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8007 23:53:44.331611 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8008 23:53:44.335111 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 23:53:44.338510 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8010 23:53:44.341496 Total UI for P1: 0, mck2ui 16
8011 23:53:44.344771 best dqsien dly found for B0: ( 1, 9, 8)
8012 23:53:44.352002 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8013 23:53:44.355158 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 23:53:44.358186 Total UI for P1: 0, mck2ui 16
8015 23:53:44.361510 best dqsien dly found for B1: ( 1, 9, 20)
8016 23:53:44.364927 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8017 23:53:44.368042 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8018 23:53:44.368151
8019 23:53:44.371569 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8020 23:53:44.374716 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8021 23:53:44.377973 [Gating] SW calibration Done
8022 23:53:44.378052 ==
8023 23:53:44.381349 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:53:44.384739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 23:53:44.384815 ==
8026 23:53:44.387495 RX Vref Scan: 0
8027 23:53:44.387593
8028 23:53:44.390797 RX Vref 0 -> 0, step: 1
8029 23:53:44.390898
8030 23:53:44.390993 RX Delay 0 -> 252, step: 8
8031 23:53:44.397979 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8032 23:53:44.400702 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8033 23:53:44.404386 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8034 23:53:44.407549 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8035 23:53:44.410803 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8036 23:53:44.417513 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8037 23:53:44.420702 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8038 23:53:44.423914 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8039 23:53:44.427853 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8040 23:53:44.430975 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8041 23:53:44.437119 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8042 23:53:44.440284 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8043 23:53:44.443734 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8044 23:53:44.447635 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8045 23:53:44.453904 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8046 23:53:44.457233 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8047 23:53:44.457342 ==
8048 23:53:44.460316 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 23:53:44.463713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 23:53:44.463835 ==
8051 23:53:44.467094 DQS Delay:
8052 23:53:44.467247 DQS0 = 0, DQS1 = 0
8053 23:53:44.467355 DQM Delay:
8054 23:53:44.470061 DQM0 = 131, DQM1 = 127
8055 23:53:44.470135 DQ Delay:
8056 23:53:44.473505 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8057 23:53:44.476790 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8058 23:53:44.483444 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8059 23:53:44.486512 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8060 23:53:44.486599
8061 23:53:44.486665
8062 23:53:44.486728 ==
8063 23:53:44.490112 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 23:53:44.493246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 23:53:44.493328 ==
8066 23:53:44.493389
8067 23:53:44.493447
8068 23:53:44.496348 TX Vref Scan disable
8069 23:53:44.499798 == TX Byte 0 ==
8070 23:53:44.503144 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8071 23:53:44.505970 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8072 23:53:44.509461 == TX Byte 1 ==
8073 23:53:44.512904 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8074 23:53:44.516333 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8075 23:53:44.516458 ==
8076 23:53:44.519335 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 23:53:44.525955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 23:53:44.526066 ==
8079 23:53:44.538114
8080 23:53:44.541396 TX Vref early break, caculate TX vref
8081 23:53:44.545087 TX Vref=16, minBit 1, minWin=23, winSum=379
8082 23:53:44.548323 TX Vref=18, minBit 8, minWin=23, winSum=386
8083 23:53:44.551340 TX Vref=20, minBit 0, minWin=24, winSum=395
8084 23:53:44.554557 TX Vref=22, minBit 10, minWin=24, winSum=401
8085 23:53:44.558413 TX Vref=24, minBit 13, minWin=24, winSum=406
8086 23:53:44.564689 TX Vref=26, minBit 1, minWin=25, winSum=412
8087 23:53:44.567934 TX Vref=28, minBit 0, minWin=25, winSum=417
8088 23:53:44.571245 TX Vref=30, minBit 2, minWin=25, winSum=410
8089 23:53:44.574909 TX Vref=32, minBit 0, minWin=25, winSum=405
8090 23:53:44.578171 TX Vref=34, minBit 0, minWin=24, winSum=392
8091 23:53:44.584502 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8092 23:53:44.584614
8093 23:53:44.587480 Final TX Range 0 Vref 28
8094 23:53:44.587578
8095 23:53:44.587645 ==
8096 23:53:44.591133 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 23:53:44.594016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 23:53:44.594126 ==
8099 23:53:44.594195
8100 23:53:44.597575
8101 23:53:44.597659 TX Vref Scan disable
8102 23:53:44.604238 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8103 23:53:44.604328 == TX Byte 0 ==
8104 23:53:44.607354 u2DelayCellOfst[0]=14 cells (4 PI)
8105 23:53:44.610931 u2DelayCellOfst[1]=17 cells (5 PI)
8106 23:53:44.613912 u2DelayCellOfst[2]=10 cells (3 PI)
8107 23:53:44.616855 u2DelayCellOfst[3]=14 cells (4 PI)
8108 23:53:44.620189 u2DelayCellOfst[4]=10 cells (3 PI)
8109 23:53:44.623563 u2DelayCellOfst[5]=0 cells (0 PI)
8110 23:53:44.627139 u2DelayCellOfst[6]=17 cells (5 PI)
8111 23:53:44.630046 u2DelayCellOfst[7]=17 cells (5 PI)
8112 23:53:44.633690 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8113 23:53:44.636773 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8114 23:53:44.639988 == TX Byte 1 ==
8115 23:53:44.643199 u2DelayCellOfst[8]=0 cells (0 PI)
8116 23:53:44.646948 u2DelayCellOfst[9]=0 cells (0 PI)
8117 23:53:44.650180 u2DelayCellOfst[10]=3 cells (1 PI)
8118 23:53:44.653201 u2DelayCellOfst[11]=0 cells (0 PI)
8119 23:53:44.656955 u2DelayCellOfst[12]=7 cells (2 PI)
8120 23:53:44.660193 u2DelayCellOfst[13]=7 cells (2 PI)
8121 23:53:44.663222 u2DelayCellOfst[14]=14 cells (4 PI)
8122 23:53:44.663315 u2DelayCellOfst[15]=7 cells (2 PI)
8123 23:53:44.669696 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8124 23:53:44.673446 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8125 23:53:44.676573 DramC Write-DBI on
8126 23:53:44.676735 ==
8127 23:53:44.679917 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 23:53:44.683165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 23:53:44.683254 ==
8130 23:53:44.683318
8131 23:53:44.683396
8132 23:53:44.686062 TX Vref Scan disable
8133 23:53:44.686163 == TX Byte 0 ==
8134 23:53:44.693018 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8135 23:53:44.693108 == TX Byte 1 ==
8136 23:53:44.699689 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8137 23:53:44.699771 DramC Write-DBI off
8138 23:53:44.699835
8139 23:53:44.699921 [DATLAT]
8140 23:53:44.702792 Freq=1600, CH0 RK1
8141 23:53:44.702892
8142 23:53:44.703007 DATLAT Default: 0xf
8143 23:53:44.706335 0, 0xFFFF, sum = 0
8144 23:53:44.709341 1, 0xFFFF, sum = 0
8145 23:53:44.709454 2, 0xFFFF, sum = 0
8146 23:53:44.712434 3, 0xFFFF, sum = 0
8147 23:53:44.712522 4, 0xFFFF, sum = 0
8148 23:53:44.716116 5, 0xFFFF, sum = 0
8149 23:53:44.716238 6, 0xFFFF, sum = 0
8150 23:53:44.719083 7, 0xFFFF, sum = 0
8151 23:53:44.719165 8, 0xFFFF, sum = 0
8152 23:53:44.722257 9, 0xFFFF, sum = 0
8153 23:53:44.722337 10, 0xFFFF, sum = 0
8154 23:53:44.725653 11, 0xFFFF, sum = 0
8155 23:53:44.725728 12, 0xFFFF, sum = 0
8156 23:53:44.729138 13, 0xFFFF, sum = 0
8157 23:53:44.729240 14, 0x0, sum = 1
8158 23:53:44.732184 15, 0x0, sum = 2
8159 23:53:44.732258 16, 0x0, sum = 3
8160 23:53:44.735703 17, 0x0, sum = 4
8161 23:53:44.735811 best_step = 15
8162 23:53:44.735924
8163 23:53:44.735988 ==
8164 23:53:44.738724 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 23:53:44.745559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 23:53:44.745655 ==
8167 23:53:44.745725 RX Vref Scan: 0
8168 23:53:44.745785
8169 23:53:44.748624 RX Vref 0 -> 0, step: 1
8170 23:53:44.748696
8171 23:53:44.751784 RX Delay 11 -> 252, step: 4
8172 23:53:44.755139 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8173 23:53:44.758645 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8174 23:53:44.764990 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8175 23:53:44.768240 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8176 23:53:44.772030 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8177 23:53:44.775280 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8178 23:53:44.778472 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8179 23:53:44.784771 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8180 23:53:44.788165 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8181 23:53:44.791671 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8182 23:53:44.794680 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8183 23:53:44.797856 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8184 23:53:44.804879 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8185 23:53:44.807907 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8186 23:53:44.811616 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8187 23:53:44.814486 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8188 23:53:44.814576 ==
8189 23:53:44.817932 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 23:53:44.824313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 23:53:44.824401 ==
8192 23:53:44.824469 DQS Delay:
8193 23:53:44.827879 DQS0 = 0, DQS1 = 0
8194 23:53:44.827962 DQM Delay:
8195 23:53:44.830942 DQM0 = 128, DQM1 = 124
8196 23:53:44.831026 DQ Delay:
8197 23:53:44.834000 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8198 23:53:44.837661 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
8199 23:53:44.841221 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8200 23:53:44.844132 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8201 23:53:44.844215
8202 23:53:44.844296
8203 23:53:44.844357
8204 23:53:44.847114 [DramC_TX_OE_Calibration] TA2
8205 23:53:44.850822 Original DQ_B0 (3 6) =30, OEN = 27
8206 23:53:44.853975 Original DQ_B1 (3 6) =30, OEN = 27
8207 23:53:44.857210 24, 0x0, End_B0=24 End_B1=24
8208 23:53:44.860888 25, 0x0, End_B0=25 End_B1=25
8209 23:53:44.861013 26, 0x0, End_B0=26 End_B1=26
8210 23:53:44.864152 27, 0x0, End_B0=27 End_B1=27
8211 23:53:44.867143 28, 0x0, End_B0=28 End_B1=28
8212 23:53:44.870369 29, 0x0, End_B0=29 End_B1=29
8213 23:53:44.874048 30, 0x0, End_B0=30 End_B1=30
8214 23:53:44.874149 31, 0x5151, End_B0=30 End_B1=30
8215 23:53:44.877403 Byte0 end_step=30 best_step=27
8216 23:53:44.880695 Byte1 end_step=30 best_step=27
8217 23:53:44.883904 Byte0 TX OE(2T, 0.5T) = (3, 3)
8218 23:53:44.886861 Byte1 TX OE(2T, 0.5T) = (3, 3)
8219 23:53:44.886972
8220 23:53:44.887087
8221 23:53:44.893247 [DQSOSCAuto] RK1, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
8222 23:53:44.897132 CH0 RK1: MR19=303, MR18=1815
8223 23:53:44.903270 CH0_RK1: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
8224 23:53:44.906494 [RxdqsGatingPostProcess] freq 1600
8225 23:53:44.913490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8226 23:53:44.916545 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 23:53:44.916630 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 23:53:44.920045 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 23:53:44.923192 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 23:53:44.926938 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 23:53:44.929716 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 23:53:44.933117 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 23:53:44.936103 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 23:53:44.939406 Pre-setting of DQS Precalculation
8235 23:53:44.942983 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8236 23:53:44.946256 ==
8237 23:53:44.949367 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 23:53:44.952796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 23:53:44.952903 ==
8240 23:53:44.956459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8241 23:53:44.962744 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8242 23:53:44.965928 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8243 23:53:44.972363 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8244 23:53:44.981357 [CA 0] Center 42 (13~72) winsize 60
8245 23:53:44.984433 [CA 1] Center 43 (13~73) winsize 61
8246 23:53:44.987651 [CA 2] Center 38 (9~68) winsize 60
8247 23:53:44.991342 [CA 3] Center 38 (8~68) winsize 61
8248 23:53:44.994419 [CA 4] Center 38 (8~69) winsize 62
8249 23:53:44.997700 [CA 5] Center 37 (7~67) winsize 61
8250 23:53:44.997772
8251 23:53:45.000754 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8252 23:53:45.000824
8253 23:53:45.004548 [CATrainingPosCal] consider 1 rank data
8254 23:53:45.007611 u2DelayCellTimex100 = 275/100 ps
8255 23:53:45.010661 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8256 23:53:45.017246 CA1 delay=43 (13~73),Diff = 6 PI (21 cell)
8257 23:53:45.021014 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8258 23:53:45.024220 CA3 delay=38 (8~68),Diff = 1 PI (3 cell)
8259 23:53:45.027217 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8260 23:53:45.030998 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8261 23:53:45.031091
8262 23:53:45.034106 CA PerBit enable=1, Macro0, CA PI delay=37
8263 23:53:45.034190
8264 23:53:45.037046 [CBTSetCACLKResult] CA Dly = 37
8265 23:53:45.040503 CS Dly: 8 (0~39)
8266 23:53:45.043700 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8267 23:53:45.046924 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8268 23:53:45.047002 ==
8269 23:53:45.050513 Dram Type= 6, Freq= 0, CH_1, rank 1
8270 23:53:45.056947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 23:53:45.057024 ==
8272 23:53:45.060330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8273 23:53:45.063618 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8274 23:53:45.069948 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8275 23:53:45.076425 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8276 23:53:45.084182 [CA 0] Center 42 (13~72) winsize 60
8277 23:53:45.087187 [CA 1] Center 43 (14~72) winsize 59
8278 23:53:45.090912 [CA 2] Center 38 (9~68) winsize 60
8279 23:53:45.094225 [CA 3] Center 37 (8~67) winsize 60
8280 23:53:45.097223 [CA 4] Center 38 (8~68) winsize 61
8281 23:53:45.100936 [CA 5] Center 37 (8~67) winsize 60
8282 23:53:45.101016
8283 23:53:45.104204 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8284 23:53:45.104284
8285 23:53:45.110417 [CATrainingPosCal] consider 2 rank data
8286 23:53:45.110498 u2DelayCellTimex100 = 275/100 ps
8287 23:53:45.116753 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8288 23:53:45.120580 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8289 23:53:45.123660 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 23:53:45.126814 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8291 23:53:45.129955 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8292 23:53:45.133492 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8293 23:53:45.133562
8294 23:53:45.136538 CA PerBit enable=1, Macro0, CA PI delay=37
8295 23:53:45.136632
8296 23:53:45.139867 [CBTSetCACLKResult] CA Dly = 37
8297 23:53:45.143006 CS Dly: 9 (0~42)
8298 23:53:45.146684 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8299 23:53:45.149651 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8300 23:53:45.149731
8301 23:53:45.153047 ----->DramcWriteLeveling(PI) begin...
8302 23:53:45.153128 ==
8303 23:53:45.156520 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 23:53:45.162745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 23:53:45.162828 ==
8306 23:53:45.166499 Write leveling (Byte 0): 25 => 25
8307 23:53:45.169749 Write leveling (Byte 1): 25 => 25
8308 23:53:45.173241 DramcWriteLeveling(PI) end<-----
8309 23:53:45.173365
8310 23:53:45.173430 ==
8311 23:53:45.176319 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 23:53:45.179790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 23:53:45.179896 ==
8314 23:53:45.182817 [Gating] SW mode calibration
8315 23:53:45.189474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8316 23:53:45.192642 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8317 23:53:45.199609 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 23:53:45.202703 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 23:53:45.209308 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 23:53:45.212695 1 4 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
8321 23:53:45.215860 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8322 23:53:45.222196 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 23:53:45.225847 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 23:53:45.229044 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 23:53:45.235318 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 23:53:45.238795 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 23:53:45.242009 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8328 23:53:45.248464 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 1)
8329 23:53:45.251715 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 23:53:45.255510 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 23:53:45.261630 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 23:53:45.265246 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 23:53:45.268328 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 23:53:45.274635 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 23:53:45.278359 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8336 23:53:45.281676 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8337 23:53:45.288251 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8338 23:53:45.291797 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 23:53:45.294585 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 23:53:45.301421 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 23:53:45.304450 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 23:53:45.307727 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 23:53:45.314878 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8344 23:53:45.318057 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 23:53:45.321032 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8346 23:53:45.327391 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 23:53:45.331194 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 23:53:45.334407 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 23:53:45.340647 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 23:53:45.344280 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 23:53:45.347219 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 23:53:45.354164 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 23:53:45.357105 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 23:53:45.360527 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 23:53:45.367269 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 23:53:45.370330 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 23:53:45.373589 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 23:53:45.380345 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 23:53:45.384074 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8360 23:53:45.386759 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 23:53:45.393357 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 23:53:45.393438 Total UI for P1: 0, mck2ui 16
8363 23:53:45.400201 best dqsien dly found for B0: ( 1, 9, 10)
8364 23:53:45.400306 Total UI for P1: 0, mck2ui 16
8365 23:53:45.406953 best dqsien dly found for B1: ( 1, 9, 12)
8366 23:53:45.410142 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8367 23:53:45.413165 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8368 23:53:45.413277
8369 23:53:45.416727 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 23:53:45.419883 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8371 23:53:45.422951 [Gating] SW calibration Done
8372 23:53:45.423052 ==
8373 23:53:45.426135 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 23:53:45.429204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 23:53:45.429338 ==
8376 23:53:45.433083 RX Vref Scan: 0
8377 23:53:45.433157
8378 23:53:45.433217 RX Vref 0 -> 0, step: 1
8379 23:53:45.436263
8380 23:53:45.436337 RX Delay 0 -> 252, step: 8
8381 23:53:45.439457 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8382 23:53:45.446319 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8383 23:53:45.449408 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8384 23:53:45.452337 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8385 23:53:45.456198 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8386 23:53:45.462333 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8387 23:53:45.465428 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8388 23:53:45.469271 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8389 23:53:45.472203 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8390 23:53:45.475511 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8391 23:53:45.482051 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8392 23:53:45.485832 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8393 23:53:45.488997 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8394 23:53:45.492193 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8395 23:53:45.495786 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8396 23:53:45.502461 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8397 23:53:45.502544 ==
8398 23:53:45.505414 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 23:53:45.508953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 23:53:45.509028 ==
8401 23:53:45.509089 DQS Delay:
8402 23:53:45.511842 DQS0 = 0, DQS1 = 0
8403 23:53:45.511914 DQM Delay:
8404 23:53:45.515189 DQM0 = 135, DQM1 = 130
8405 23:53:45.515312 DQ Delay:
8406 23:53:45.518547 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8407 23:53:45.521807 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8408 23:53:45.525505 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8409 23:53:45.531855 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8410 23:53:45.531938
8411 23:53:45.532001
8412 23:53:45.532060 ==
8413 23:53:45.535009 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 23:53:45.538557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 23:53:45.538640 ==
8416 23:53:45.538704
8417 23:53:45.538763
8418 23:53:45.541888 TX Vref Scan disable
8419 23:53:45.541968 == TX Byte 0 ==
8420 23:53:45.548097 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8421 23:53:45.551204 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8422 23:53:45.551304 == TX Byte 1 ==
8423 23:53:45.558317 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8424 23:53:45.561370 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8425 23:53:45.561446 ==
8426 23:53:45.564703 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 23:53:45.567803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 23:53:45.567906 ==
8429 23:53:45.581428
8430 23:53:45.584604 TX Vref early break, caculate TX vref
8431 23:53:45.588429 TX Vref=16, minBit 8, minWin=22, winSum=367
8432 23:53:45.591795 TX Vref=18, minBit 9, minWin=21, winSum=375
8433 23:53:45.594965 TX Vref=20, minBit 8, minWin=23, winSum=389
8434 23:53:45.598068 TX Vref=22, minBit 5, minWin=24, winSum=397
8435 23:53:45.601208 TX Vref=24, minBit 6, minWin=24, winSum=408
8436 23:53:45.607752 TX Vref=26, minBit 3, minWin=25, winSum=412
8437 23:53:45.611018 TX Vref=28, minBit 3, minWin=25, winSum=421
8438 23:53:45.614757 TX Vref=30, minBit 0, minWin=25, winSum=416
8439 23:53:45.617797 TX Vref=32, minBit 11, minWin=24, winSum=404
8440 23:53:45.621179 TX Vref=34, minBit 0, minWin=23, winSum=398
8441 23:53:45.627494 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 28
8442 23:53:45.627600
8443 23:53:45.631336 Final TX Range 0 Vref 28
8444 23:53:45.631433
8445 23:53:45.631519 ==
8446 23:53:45.634336 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 23:53:45.637182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 23:53:45.637316 ==
8449 23:53:45.637381
8450 23:53:45.637445
8451 23:53:45.640656 TX Vref Scan disable
8452 23:53:45.647239 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8453 23:53:45.647342 == TX Byte 0 ==
8454 23:53:45.650869 u2DelayCellOfst[0]=17 cells (5 PI)
8455 23:53:45.654002 u2DelayCellOfst[1]=10 cells (3 PI)
8456 23:53:45.657243 u2DelayCellOfst[2]=0 cells (0 PI)
8457 23:53:45.660893 u2DelayCellOfst[3]=7 cells (2 PI)
8458 23:53:45.663972 u2DelayCellOfst[4]=7 cells (2 PI)
8459 23:53:45.667637 u2DelayCellOfst[5]=17 cells (5 PI)
8460 23:53:45.670737 u2DelayCellOfst[6]=14 cells (4 PI)
8461 23:53:45.673998 u2DelayCellOfst[7]=7 cells (2 PI)
8462 23:53:45.676936 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8463 23:53:45.680526 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 23:53:45.683743 == TX Byte 1 ==
8465 23:53:45.687141 u2DelayCellOfst[8]=0 cells (0 PI)
8466 23:53:45.687262 u2DelayCellOfst[9]=7 cells (2 PI)
8467 23:53:45.690389 u2DelayCellOfst[10]=14 cells (4 PI)
8468 23:53:45.693463 u2DelayCellOfst[11]=7 cells (2 PI)
8469 23:53:45.696808 u2DelayCellOfst[12]=17 cells (5 PI)
8470 23:53:45.700521 u2DelayCellOfst[13]=17 cells (5 PI)
8471 23:53:45.703844 u2DelayCellOfst[14]=21 cells (6 PI)
8472 23:53:45.707057 u2DelayCellOfst[15]=21 cells (6 PI)
8473 23:53:45.713414 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8474 23:53:45.717025 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8475 23:53:45.717132 DramC Write-DBI on
8476 23:53:45.717222 ==
8477 23:53:45.720015 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 23:53:45.726382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 23:53:45.726483 ==
8480 23:53:45.726572
8481 23:53:45.726660
8482 23:53:45.730055 TX Vref Scan disable
8483 23:53:45.730157 == TX Byte 0 ==
8484 23:53:45.736480 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8485 23:53:45.736588 == TX Byte 1 ==
8486 23:53:45.739710 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8487 23:53:45.743161 DramC Write-DBI off
8488 23:53:45.743241
8489 23:53:45.743305 [DATLAT]
8490 23:53:45.746641 Freq=1600, CH1 RK0
8491 23:53:45.746725
8492 23:53:45.746846 DATLAT Default: 0xf
8493 23:53:45.749553 0, 0xFFFF, sum = 0
8494 23:53:45.749631 1, 0xFFFF, sum = 0
8495 23:53:45.752964 2, 0xFFFF, sum = 0
8496 23:53:45.753037 3, 0xFFFF, sum = 0
8497 23:53:45.756317 4, 0xFFFF, sum = 0
8498 23:53:45.756418 5, 0xFFFF, sum = 0
8499 23:53:45.759284 6, 0xFFFF, sum = 0
8500 23:53:45.759385 7, 0xFFFF, sum = 0
8501 23:53:45.762744 8, 0xFFFF, sum = 0
8502 23:53:45.765800 9, 0xFFFF, sum = 0
8503 23:53:45.765880 10, 0xFFFF, sum = 0
8504 23:53:45.769382 11, 0xFFFF, sum = 0
8505 23:53:45.769488 12, 0xFFFF, sum = 0
8506 23:53:45.772714 13, 0xFFFF, sum = 0
8507 23:53:45.772870 14, 0x0, sum = 1
8508 23:53:45.775903 15, 0x0, sum = 2
8509 23:53:45.776021 16, 0x0, sum = 3
8510 23:53:45.778951 17, 0x0, sum = 4
8511 23:53:45.779114 best_step = 15
8512 23:53:45.779204
8513 23:53:45.779290 ==
8514 23:53:45.782750 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 23:53:45.785595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 23:53:45.788833 ==
8517 23:53:45.788936 RX Vref Scan: 1
8518 23:53:45.789028
8519 23:53:45.791941 Set Vref Range= 24 -> 127
8520 23:53:45.792042
8521 23:53:45.796102 RX Vref 24 -> 127, step: 1
8522 23:53:45.796203
8523 23:53:45.796294 RX Delay 19 -> 252, step: 4
8524 23:53:45.796380
8525 23:53:45.799075 Set Vref, RX VrefLevel [Byte0]: 24
8526 23:53:45.802032 [Byte1]: 24
8527 23:53:45.805821
8528 23:53:45.805893 Set Vref, RX VrefLevel [Byte0]: 25
8529 23:53:45.809011 [Byte1]: 25
8530 23:53:45.813355
8531 23:53:45.813452 Set Vref, RX VrefLevel [Byte0]: 26
8532 23:53:45.816952 [Byte1]: 26
8533 23:53:45.821172
8534 23:53:45.821275 Set Vref, RX VrefLevel [Byte0]: 27
8535 23:53:45.824106 [Byte1]: 27
8536 23:53:45.828635
8537 23:53:45.828711 Set Vref, RX VrefLevel [Byte0]: 28
8538 23:53:45.831734 [Byte1]: 28
8539 23:53:45.835982
8540 23:53:45.836086 Set Vref, RX VrefLevel [Byte0]: 29
8541 23:53:45.839828 [Byte1]: 29
8542 23:53:45.844108
8543 23:53:45.844209 Set Vref, RX VrefLevel [Byte0]: 30
8544 23:53:45.847332 [Byte1]: 30
8545 23:53:45.851449
8546 23:53:45.851548 Set Vref, RX VrefLevel [Byte0]: 31
8547 23:53:45.854658 [Byte1]: 31
8548 23:53:45.859067
8549 23:53:45.859172 Set Vref, RX VrefLevel [Byte0]: 32
8550 23:53:45.861975 [Byte1]: 32
8551 23:53:45.866898
8552 23:53:45.866967 Set Vref, RX VrefLevel [Byte0]: 33
8553 23:53:45.869949 [Byte1]: 33
8554 23:53:45.874191
8555 23:53:45.874265 Set Vref, RX VrefLevel [Byte0]: 34
8556 23:53:45.877469 [Byte1]: 34
8557 23:53:45.881953
8558 23:53:45.882029 Set Vref, RX VrefLevel [Byte0]: 35
8559 23:53:45.884946 [Byte1]: 35
8560 23:53:45.889615
8561 23:53:45.889690 Set Vref, RX VrefLevel [Byte0]: 36
8562 23:53:45.892498 [Byte1]: 36
8563 23:53:45.896957
8564 23:53:45.897027 Set Vref, RX VrefLevel [Byte0]: 37
8565 23:53:45.900172 [Byte1]: 37
8566 23:53:45.904493
8567 23:53:45.904566 Set Vref, RX VrefLevel [Byte0]: 38
8568 23:53:45.907712 [Byte1]: 38
8569 23:53:45.911910
8570 23:53:45.911983 Set Vref, RX VrefLevel [Byte0]: 39
8571 23:53:45.915117 [Byte1]: 39
8572 23:53:45.919739
8573 23:53:45.919805 Set Vref, RX VrefLevel [Byte0]: 40
8574 23:53:45.922926 [Byte1]: 40
8575 23:53:45.927156
8576 23:53:45.927229 Set Vref, RX VrefLevel [Byte0]: 41
8577 23:53:45.930107 [Byte1]: 41
8578 23:53:45.934447
8579 23:53:45.934540 Set Vref, RX VrefLevel [Byte0]: 42
8580 23:53:45.938244 [Byte1]: 42
8581 23:53:45.942469
8582 23:53:45.942565 Set Vref, RX VrefLevel [Byte0]: 43
8583 23:53:45.945416 [Byte1]: 43
8584 23:53:45.949810
8585 23:53:45.949892 Set Vref, RX VrefLevel [Byte0]: 44
8586 23:53:45.953240 [Byte1]: 44
8587 23:53:45.957276
8588 23:53:45.957367 Set Vref, RX VrefLevel [Byte0]: 45
8589 23:53:45.960436 [Byte1]: 45
8590 23:53:45.964888
8591 23:53:45.964979 Set Vref, RX VrefLevel [Byte0]: 46
8592 23:53:45.968401 [Byte1]: 46
8593 23:53:45.972949
8594 23:53:45.973051 Set Vref, RX VrefLevel [Byte0]: 47
8595 23:53:45.975623 [Byte1]: 47
8596 23:53:45.980286
8597 23:53:45.980381 Set Vref, RX VrefLevel [Byte0]: 48
8598 23:53:45.983759 [Byte1]: 48
8599 23:53:45.987824
8600 23:53:45.987899 Set Vref, RX VrefLevel [Byte0]: 49
8601 23:53:45.990961 [Byte1]: 49
8602 23:53:45.995287
8603 23:53:45.995365 Set Vref, RX VrefLevel [Byte0]: 50
8604 23:53:45.998802 [Byte1]: 50
8605 23:53:46.003044
8606 23:53:46.003123 Set Vref, RX VrefLevel [Byte0]: 51
8607 23:53:46.006046 [Byte1]: 51
8608 23:53:46.010431
8609 23:53:46.010516 Set Vref, RX VrefLevel [Byte0]: 52
8610 23:53:46.013516 [Byte1]: 52
8611 23:53:46.018014
8612 23:53:46.018103 Set Vref, RX VrefLevel [Byte0]: 53
8613 23:53:46.021131 [Byte1]: 53
8614 23:53:46.025680
8615 23:53:46.025766 Set Vref, RX VrefLevel [Byte0]: 54
8616 23:53:46.028852 [Byte1]: 54
8617 23:53:46.033204
8618 23:53:46.033311 Set Vref, RX VrefLevel [Byte0]: 55
8619 23:53:46.036769 [Byte1]: 55
8620 23:53:46.040723
8621 23:53:46.040812 Set Vref, RX VrefLevel [Byte0]: 56
8622 23:53:46.043912 [Byte1]: 56
8623 23:53:46.048388
8624 23:53:46.048477 Set Vref, RX VrefLevel [Byte0]: 57
8625 23:53:46.051438 [Byte1]: 57
8626 23:53:46.056051
8627 23:53:46.056137 Set Vref, RX VrefLevel [Byte0]: 58
8628 23:53:46.059018 [Byte1]: 58
8629 23:53:46.063667
8630 23:53:46.063755 Set Vref, RX VrefLevel [Byte0]: 59
8631 23:53:46.066730 [Byte1]: 59
8632 23:53:46.071321
8633 23:53:46.071407 Set Vref, RX VrefLevel [Byte0]: 60
8634 23:53:46.074448 [Byte1]: 60
8635 23:53:46.078979
8636 23:53:46.079065 Set Vref, RX VrefLevel [Byte0]: 61
8637 23:53:46.082069 [Byte1]: 61
8638 23:53:46.086061
8639 23:53:46.086147 Set Vref, RX VrefLevel [Byte0]: 62
8640 23:53:46.089683 [Byte1]: 62
8641 23:53:46.093546
8642 23:53:46.093652 Set Vref, RX VrefLevel [Byte0]: 63
8643 23:53:46.097422 [Byte1]: 63
8644 23:53:46.101123
8645 23:53:46.101206 Set Vref, RX VrefLevel [Byte0]: 64
8646 23:53:46.104601 [Byte1]: 64
8647 23:53:46.108801
8648 23:53:46.108916 Set Vref, RX VrefLevel [Byte0]: 65
8649 23:53:46.111954 [Byte1]: 65
8650 23:53:46.116536
8651 23:53:46.116615 Set Vref, RX VrefLevel [Byte0]: 66
8652 23:53:46.119793 [Byte1]: 66
8653 23:53:46.124038
8654 23:53:46.124143 Set Vref, RX VrefLevel [Byte0]: 67
8655 23:53:46.127203 [Byte1]: 67
8656 23:53:46.131671
8657 23:53:46.131750 Set Vref, RX VrefLevel [Byte0]: 68
8658 23:53:46.134710 [Byte1]: 68
8659 23:53:46.139204
8660 23:53:46.139307 Set Vref, RX VrefLevel [Byte0]: 69
8661 23:53:46.142554 [Byte1]: 69
8662 23:53:46.146595
8663 23:53:46.146693 Set Vref, RX VrefLevel [Byte0]: 70
8664 23:53:46.150432 [Byte1]: 70
8665 23:53:46.154420
8666 23:53:46.154517 Set Vref, RX VrefLevel [Byte0]: 71
8667 23:53:46.157584 [Byte1]: 71
8668 23:53:46.162299
8669 23:53:46.162397 Set Vref, RX VrefLevel [Byte0]: 72
8670 23:53:46.165247 [Byte1]: 72
8671 23:53:46.169499
8672 23:53:46.169570 Final RX Vref Byte 0 = 58 to rank0
8673 23:53:46.172876 Final RX Vref Byte 1 = 61 to rank0
8674 23:53:46.176320 Final RX Vref Byte 0 = 58 to rank1
8675 23:53:46.179483 Final RX Vref Byte 1 = 61 to rank1==
8676 23:53:46.182617 Dram Type= 6, Freq= 0, CH_1, rank 0
8677 23:53:46.189225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8678 23:53:46.189376 ==
8679 23:53:46.189468 DQS Delay:
8680 23:53:46.192321 DQS0 = 0, DQS1 = 0
8681 23:53:46.192416 DQM Delay:
8682 23:53:46.192501 DQM0 = 132, DQM1 = 128
8683 23:53:46.196369 DQ Delay:
8684 23:53:46.199408 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8685 23:53:46.202277 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8686 23:53:46.205582 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8687 23:53:46.208932 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =136
8688 23:53:46.209034
8689 23:53:46.209133
8690 23:53:46.209219
8691 23:53:46.212269 [DramC_TX_OE_Calibration] TA2
8692 23:53:46.215388 Original DQ_B0 (3 6) =30, OEN = 27
8693 23:53:46.219086 Original DQ_B1 (3 6) =30, OEN = 27
8694 23:53:46.222138 24, 0x0, End_B0=24 End_B1=24
8695 23:53:46.222249 25, 0x0, End_B0=25 End_B1=25
8696 23:53:46.225689 26, 0x0, End_B0=26 End_B1=26
8697 23:53:46.228743 27, 0x0, End_B0=27 End_B1=27
8698 23:53:46.232057 28, 0x0, End_B0=28 End_B1=28
8699 23:53:46.235320 29, 0x0, End_B0=29 End_B1=29
8700 23:53:46.235423 30, 0x0, End_B0=30 End_B1=30
8701 23:53:46.238569 31, 0x5151, End_B0=30 End_B1=30
8702 23:53:46.242263 Byte0 end_step=30 best_step=27
8703 23:53:46.245375 Byte1 end_step=30 best_step=27
8704 23:53:46.248553 Byte0 TX OE(2T, 0.5T) = (3, 3)
8705 23:53:46.251668 Byte1 TX OE(2T, 0.5T) = (3, 3)
8706 23:53:46.251761
8707 23:53:46.251848
8708 23:53:46.258156 [DQSOSCAuto] RK0, (LSB)MR18= 0x1019, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
8709 23:53:46.261403 CH1 RK0: MR19=303, MR18=1019
8710 23:53:46.267969 CH1_RK0: MR19=0x303, MR18=0x1019, DQSOSC=397, MR23=63, INC=23, DEC=15
8711 23:53:46.268096
8712 23:53:46.271635 ----->DramcWriteLeveling(PI) begin...
8713 23:53:46.271736 ==
8714 23:53:46.274598 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 23:53:46.278122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 23:53:46.278208 ==
8717 23:53:46.281223 Write leveling (Byte 0): 23 => 23
8718 23:53:46.284881 Write leveling (Byte 1): 25 => 25
8719 23:53:46.287889 DramcWriteLeveling(PI) end<-----
8720 23:53:46.287966
8721 23:53:46.288046 ==
8722 23:53:46.291180 Dram Type= 6, Freq= 0, CH_1, rank 1
8723 23:53:46.297634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 23:53:46.297714 ==
8725 23:53:46.297795 [Gating] SW mode calibration
8726 23:53:46.307755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8727 23:53:46.310607 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8728 23:53:46.317659 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 23:53:46.320720 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8730 23:53:46.323744 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8731 23:53:46.330771 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8732 23:53:46.333862 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8733 23:53:46.336926 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 23:53:46.343785 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 23:53:46.347280 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 23:53:46.350546 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 23:53:46.356886 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8738 23:53:46.360123 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8739 23:53:46.363538 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8740 23:53:46.369770 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 23:53:46.373489 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 23:53:46.376657 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 23:53:46.382971 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 23:53:46.386450 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 23:53:46.390123 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8746 23:53:46.396394 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8747 23:53:46.399467 1 6 12 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8748 23:53:46.403105 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 23:53:46.409365 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 23:53:46.412427 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 23:53:46.416000 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 23:53:46.422632 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 23:53:46.425865 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 23:53:46.428942 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8755 23:53:46.435379 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8756 23:53:46.439195 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 23:53:46.442427 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 23:53:46.449086 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 23:53:46.452065 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 23:53:46.455454 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 23:53:46.462402 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 23:53:46.465625 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 23:53:46.468725 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 23:53:46.475673 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 23:53:46.478527 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 23:53:46.482340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 23:53:46.488645 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 23:53:46.491666 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 23:53:46.495226 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8770 23:53:46.501861 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8771 23:53:46.504878 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8772 23:53:46.508069 Total UI for P1: 0, mck2ui 16
8773 23:53:46.511292 best dqsien dly found for B0: ( 1, 9, 6)
8774 23:53:46.515144 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 23:53:46.518263 Total UI for P1: 0, mck2ui 16
8776 23:53:46.521554 best dqsien dly found for B1: ( 1, 9, 12)
8777 23:53:46.524783 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8778 23:53:46.527677 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8779 23:53:46.527756
8780 23:53:46.534447 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8781 23:53:46.538081 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8782 23:53:46.541148 [Gating] SW calibration Done
8783 23:53:46.541261 ==
8784 23:53:46.544161 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 23:53:46.547906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 23:53:46.547985 ==
8787 23:53:46.548084 RX Vref Scan: 0
8788 23:53:46.548180
8789 23:53:46.551203 RX Vref 0 -> 0, step: 1
8790 23:53:46.551288
8791 23:53:46.554322 RX Delay 0 -> 252, step: 8
8792 23:53:46.557454 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8793 23:53:46.560575 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8794 23:53:46.567670 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8795 23:53:46.570360 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8796 23:53:46.573655 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8797 23:53:46.577168 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8798 23:53:46.580800 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8799 23:53:46.586917 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8800 23:53:46.590623 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8801 23:53:46.594028 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8802 23:53:46.597339 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8803 23:53:46.600100 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8804 23:53:46.607070 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8805 23:53:46.609988 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8806 23:53:46.613205 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8807 23:53:46.617171 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8808 23:53:46.617296 ==
8809 23:53:46.620343 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 23:53:46.626592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 23:53:46.626676 ==
8812 23:53:46.626757 DQS Delay:
8813 23:53:46.630130 DQS0 = 0, DQS1 = 0
8814 23:53:46.630207 DQM Delay:
8815 23:53:46.633213 DQM0 = 133, DQM1 = 131
8816 23:53:46.633327 DQ Delay:
8817 23:53:46.636288 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =135
8818 23:53:46.640053 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8819 23:53:46.643015 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8820 23:53:46.646609 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =139
8821 23:53:46.646693
8822 23:53:46.646776
8823 23:53:46.646860 ==
8824 23:53:46.649687 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 23:53:46.656149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 23:53:46.656233 ==
8827 23:53:46.656318
8828 23:53:46.656396
8829 23:53:46.656479 TX Vref Scan disable
8830 23:53:46.659964 == TX Byte 0 ==
8831 23:53:46.663137 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8832 23:53:46.670275 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8833 23:53:46.670361 == TX Byte 1 ==
8834 23:53:46.673440 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8835 23:53:46.679963 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8836 23:53:46.680070 ==
8837 23:53:46.682909 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 23:53:46.686190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 23:53:46.686278 ==
8840 23:53:46.700079
8841 23:53:46.703346 TX Vref early break, caculate TX vref
8842 23:53:46.706447 TX Vref=16, minBit 9, minWin=21, winSum=375
8843 23:53:46.709843 TX Vref=18, minBit 9, minWin=23, winSum=388
8844 23:53:46.712677 TX Vref=20, minBit 9, minWin=22, winSum=394
8845 23:53:46.716153 TX Vref=22, minBit 9, minWin=23, winSum=400
8846 23:53:46.719324 TX Vref=24, minBit 9, minWin=24, winSum=409
8847 23:53:46.726275 TX Vref=26, minBit 9, minWin=25, winSum=417
8848 23:53:46.729049 TX Vref=28, minBit 9, minWin=25, winSum=424
8849 23:53:46.732621 TX Vref=30, minBit 0, minWin=25, winSum=414
8850 23:53:46.736044 TX Vref=32, minBit 9, minWin=24, winSum=407
8851 23:53:46.739032 TX Vref=34, minBit 9, minWin=23, winSum=403
8852 23:53:46.746116 TX Vref=36, minBit 8, minWin=23, winSum=397
8853 23:53:46.748862 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
8854 23:53:46.748946
8855 23:53:46.752543 Final TX Range 0 Vref 28
8856 23:53:46.752628
8857 23:53:46.752713 ==
8858 23:53:46.755624 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 23:53:46.758814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 23:53:46.762245 ==
8861 23:53:46.762321
8862 23:53:46.762418
8863 23:53:46.762513 TX Vref Scan disable
8864 23:53:46.769219 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8865 23:53:46.769348 == TX Byte 0 ==
8866 23:53:46.772451 u2DelayCellOfst[0]=14 cells (4 PI)
8867 23:53:46.775745 u2DelayCellOfst[1]=10 cells (3 PI)
8868 23:53:46.778927 u2DelayCellOfst[2]=0 cells (0 PI)
8869 23:53:46.782047 u2DelayCellOfst[3]=7 cells (2 PI)
8870 23:53:46.785267 u2DelayCellOfst[4]=7 cells (2 PI)
8871 23:53:46.789120 u2DelayCellOfst[5]=14 cells (4 PI)
8872 23:53:46.792059 u2DelayCellOfst[6]=14 cells (4 PI)
8873 23:53:46.795790 u2DelayCellOfst[7]=7 cells (2 PI)
8874 23:53:46.798462 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8875 23:53:46.801741 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8876 23:53:46.804954 == TX Byte 1 ==
8877 23:53:46.808418 u2DelayCellOfst[8]=0 cells (0 PI)
8878 23:53:46.811670 u2DelayCellOfst[9]=3 cells (1 PI)
8879 23:53:46.814759 u2DelayCellOfst[10]=14 cells (4 PI)
8880 23:53:46.818446 u2DelayCellOfst[11]=7 cells (2 PI)
8881 23:53:46.821571 u2DelayCellOfst[12]=17 cells (5 PI)
8882 23:53:46.825150 u2DelayCellOfst[13]=17 cells (5 PI)
8883 23:53:46.828029 u2DelayCellOfst[14]=17 cells (5 PI)
8884 23:53:46.831807 u2DelayCellOfst[15]=17 cells (5 PI)
8885 23:53:46.834914 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8886 23:53:46.838219 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8887 23:53:46.841172 DramC Write-DBI on
8888 23:53:46.841298 ==
8889 23:53:46.844963 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 23:53:46.847830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 23:53:46.847932 ==
8892 23:53:46.848022
8893 23:53:46.848107
8894 23:53:46.851113 TX Vref Scan disable
8895 23:53:46.851190 == TX Byte 0 ==
8896 23:53:46.857823 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8897 23:53:46.857907 == TX Byte 1 ==
8898 23:53:46.860868 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8899 23:53:46.864700 DramC Write-DBI off
8900 23:53:46.864781
8901 23:53:46.864844 [DATLAT]
8902 23:53:46.867927 Freq=1600, CH1 RK1
8903 23:53:46.868042
8904 23:53:46.868135 DATLAT Default: 0xf
8905 23:53:46.871101 0, 0xFFFF, sum = 0
8906 23:53:46.874156 1, 0xFFFF, sum = 0
8907 23:53:46.874229 2, 0xFFFF, sum = 0
8908 23:53:46.878009 3, 0xFFFF, sum = 0
8909 23:53:46.878091 4, 0xFFFF, sum = 0
8910 23:53:46.881117 5, 0xFFFF, sum = 0
8911 23:53:46.881199 6, 0xFFFF, sum = 0
8912 23:53:46.884201 7, 0xFFFF, sum = 0
8913 23:53:46.884316 8, 0xFFFF, sum = 0
8914 23:53:46.887230 9, 0xFFFF, sum = 0
8915 23:53:46.887339 10, 0xFFFF, sum = 0
8916 23:53:46.890577 11, 0xFFFF, sum = 0
8917 23:53:46.890659 12, 0xFFFF, sum = 0
8918 23:53:46.893791 13, 0xFFFF, sum = 0
8919 23:53:46.893899 14, 0x0, sum = 1
8920 23:53:46.897312 15, 0x0, sum = 2
8921 23:53:46.897384 16, 0x0, sum = 3
8922 23:53:46.900493 17, 0x0, sum = 4
8923 23:53:46.900575 best_step = 15
8924 23:53:46.900639
8925 23:53:46.900697 ==
8926 23:53:46.903625 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 23:53:46.910670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 23:53:46.910759 ==
8929 23:53:46.910826 RX Vref Scan: 0
8930 23:53:46.910886
8931 23:53:46.914420 RX Vref 0 -> 0, step: 1
8932 23:53:46.914500
8933 23:53:46.916702 RX Delay 11 -> 252, step: 4
8934 23:53:46.920204 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8935 23:53:46.923676 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8936 23:53:46.930269 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8937 23:53:46.933663 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8938 23:53:46.937150 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8939 23:53:46.940270 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8940 23:53:46.943528 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8941 23:53:46.946679 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8942 23:53:46.953705 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8943 23:53:46.956941 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8944 23:53:46.960151 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8945 23:53:46.963082 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8946 23:53:46.970063 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8947 23:53:46.973136 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8948 23:53:46.976963 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8949 23:53:46.980258 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8950 23:53:46.980373 ==
8951 23:53:46.983508 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 23:53:46.989654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 23:53:46.989745 ==
8954 23:53:46.989828 DQS Delay:
8955 23:53:46.992854 DQS0 = 0, DQS1 = 0
8956 23:53:46.992937 DQM Delay:
8957 23:53:46.993020 DQM0 = 130, DQM1 = 128
8958 23:53:46.996784 DQ Delay:
8959 23:53:46.999956 DQ0 =132, DQ1 =128, DQ2 =118, DQ3 =128
8960 23:53:47.002963 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
8961 23:53:47.006226 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8962 23:53:47.009992 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8963 23:53:47.010101
8964 23:53:47.010201
8965 23:53:47.010298
8966 23:53:47.013054 [DramC_TX_OE_Calibration] TA2
8967 23:53:47.016176 Original DQ_B0 (3 6) =30, OEN = 27
8968 23:53:47.019273 Original DQ_B1 (3 6) =30, OEN = 27
8969 23:53:47.022760 24, 0x0, End_B0=24 End_B1=24
8970 23:53:47.022845 25, 0x0, End_B0=25 End_B1=25
8971 23:53:47.026281 26, 0x0, End_B0=26 End_B1=26
8972 23:53:47.029467 27, 0x0, End_B0=27 End_B1=27
8973 23:53:47.032753 28, 0x0, End_B0=28 End_B1=28
8974 23:53:47.036144 29, 0x0, End_B0=29 End_B1=29
8975 23:53:47.036227 30, 0x0, End_B0=30 End_B1=30
8976 23:53:47.039364 31, 0x4141, End_B0=30 End_B1=30
8977 23:53:47.042410 Byte0 end_step=30 best_step=27
8978 23:53:47.045924 Byte1 end_step=30 best_step=27
8979 23:53:47.049059 Byte0 TX OE(2T, 0.5T) = (3, 3)
8980 23:53:47.052353 Byte1 TX OE(2T, 0.5T) = (3, 3)
8981 23:53:47.052435
8982 23:53:47.052499
8983 23:53:47.058993 [DQSOSCAuto] RK1, (LSB)MR18= 0x121f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
8984 23:53:47.061999 CH1 RK1: MR19=303, MR18=121F
8985 23:53:47.068838 CH1_RK1: MR19=0x303, MR18=0x121F, DQSOSC=394, MR23=63, INC=23, DEC=15
8986 23:53:47.071840 [RxdqsGatingPostProcess] freq 1600
8987 23:53:47.078733 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8988 23:53:47.078815 best DQS0 dly(2T, 0.5T) = (1, 1)
8989 23:53:47.081927 best DQS1 dly(2T, 0.5T) = (1, 1)
8990 23:53:47.085151 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8991 23:53:47.088389 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8992 23:53:47.091646 best DQS0 dly(2T, 0.5T) = (1, 1)
8993 23:53:47.094843 best DQS1 dly(2T, 0.5T) = (1, 1)
8994 23:53:47.098194 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8995 23:53:47.101521 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8996 23:53:47.105197 Pre-setting of DQS Precalculation
8997 23:53:47.108281 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8998 23:53:47.118430 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8999 23:53:47.124993 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9000 23:53:47.125077
9001 23:53:47.125141
9002 23:53:47.127831 [Calibration Summary] 3200 Mbps
9003 23:53:47.127913 CH 0, Rank 0
9004 23:53:47.131495 SW Impedance : PASS
9005 23:53:47.131577 DUTY Scan : NO K
9006 23:53:47.134686 ZQ Calibration : PASS
9007 23:53:47.137772 Jitter Meter : NO K
9008 23:53:47.137854 CBT Training : PASS
9009 23:53:47.141130 Write leveling : PASS
9010 23:53:47.144966 RX DQS gating : PASS
9011 23:53:47.145043 RX DQ/DQS(RDDQC) : PASS
9012 23:53:47.147933 TX DQ/DQS : PASS
9013 23:53:47.151029 RX DATLAT : PASS
9014 23:53:47.151127 RX DQ/DQS(Engine): PASS
9015 23:53:47.154284 TX OE : PASS
9016 23:53:47.154378 All Pass.
9017 23:53:47.154443
9018 23:53:47.157788 CH 0, Rank 1
9019 23:53:47.157869 SW Impedance : PASS
9020 23:53:47.160713 DUTY Scan : NO K
9021 23:53:47.164260 ZQ Calibration : PASS
9022 23:53:47.164340 Jitter Meter : NO K
9023 23:53:47.167708 CBT Training : PASS
9024 23:53:47.170756 Write leveling : PASS
9025 23:53:47.170859 RX DQS gating : PASS
9026 23:53:47.174542 RX DQ/DQS(RDDQC) : PASS
9027 23:53:47.177604 TX DQ/DQS : PASS
9028 23:53:47.177686 RX DATLAT : PASS
9029 23:53:47.181198 RX DQ/DQS(Engine): PASS
9030 23:53:47.184327 TX OE : PASS
9031 23:53:47.184408 All Pass.
9032 23:53:47.184472
9033 23:53:47.184531 CH 1, Rank 0
9034 23:53:47.187394 SW Impedance : PASS
9035 23:53:47.190559 DUTY Scan : NO K
9036 23:53:47.190640 ZQ Calibration : PASS
9037 23:53:47.193776 Jitter Meter : NO K
9038 23:53:47.197042 CBT Training : PASS
9039 23:53:47.197123 Write leveling : PASS
9040 23:53:47.200890 RX DQS gating : PASS
9041 23:53:47.203464 RX DQ/DQS(RDDQC) : PASS
9042 23:53:47.203545 TX DQ/DQS : PASS
9043 23:53:47.207054 RX DATLAT : PASS
9044 23:53:47.207135 RX DQ/DQS(Engine): PASS
9045 23:53:47.210209 TX OE : PASS
9046 23:53:47.210290 All Pass.
9047 23:53:47.210354
9048 23:53:47.213845 CH 1, Rank 1
9049 23:53:47.213926 SW Impedance : PASS
9050 23:53:47.216948 DUTY Scan : NO K
9051 23:53:47.220110 ZQ Calibration : PASS
9052 23:53:47.220191 Jitter Meter : NO K
9053 23:53:47.223801 CBT Training : PASS
9054 23:53:47.226969 Write leveling : PASS
9055 23:53:47.227064 RX DQS gating : PASS
9056 23:53:47.230292 RX DQ/DQS(RDDQC) : PASS
9057 23:53:47.233881 TX DQ/DQS : PASS
9058 23:53:47.233962 RX DATLAT : PASS
9059 23:53:47.236968 RX DQ/DQS(Engine): PASS
9060 23:53:47.240053 TX OE : PASS
9061 23:53:47.240133 All Pass.
9062 23:53:47.240196
9063 23:53:47.243572 DramC Write-DBI on
9064 23:53:47.243654 PER_BANK_REFRESH: Hybrid Mode
9065 23:53:47.246904 TX_TRACKING: ON
9066 23:53:47.256626 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9067 23:53:47.263099 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9068 23:53:47.269721 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 23:53:47.273393 [FAST_K] Save calibration result to emmc
9070 23:53:47.276272 sync common calibartion params.
9071 23:53:47.279366 sync cbt_mode0:1, 1:1
9072 23:53:47.279448 dram_init: ddr_geometry: 2
9073 23:53:47.283123 dram_init: ddr_geometry: 2
9074 23:53:47.286268 dram_init: ddr_geometry: 2
9075 23:53:47.289744 0:dram_rank_size:100000000
9076 23:53:47.289827 1:dram_rank_size:100000000
9077 23:53:47.296187 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9078 23:53:47.299260 DFS_SHUFFLE_HW_MODE: ON
9079 23:53:47.302343 dramc_set_vcore_voltage set vcore to 725000
9080 23:53:47.305975 Read voltage for 1600, 0
9081 23:53:47.306056 Vio18 = 0
9082 23:53:47.306120 Vcore = 725000
9083 23:53:47.309315 Vdram = 0
9084 23:53:47.309396 Vddq = 0
9085 23:53:47.309460 Vmddr = 0
9086 23:53:47.312497 switch to 3200 Mbps bootup
9087 23:53:47.312578 [DramcRunTimeConfig]
9088 23:53:47.315999 PHYPLL
9089 23:53:47.316109 DPM_CONTROL_AFTERK: ON
9090 23:53:47.319262 PER_BANK_REFRESH: ON
9091 23:53:47.322351 REFRESH_OVERHEAD_REDUCTION: ON
9092 23:53:47.322432 CMD_PICG_NEW_MODE: OFF
9093 23:53:47.325461 XRTWTW_NEW_MODE: ON
9094 23:53:47.325542 XRTRTR_NEW_MODE: ON
9095 23:53:47.328838 TX_TRACKING: ON
9096 23:53:47.328919 RDSEL_TRACKING: OFF
9097 23:53:47.332543 DQS Precalculation for DVFS: ON
9098 23:53:47.335645 RX_TRACKING: OFF
9099 23:53:47.335727 HW_GATING DBG: ON
9100 23:53:47.338872 ZQCS_ENABLE_LP4: ON
9101 23:53:47.338954 RX_PICG_NEW_MODE: ON
9102 23:53:47.341893 TX_PICG_NEW_MODE: ON
9103 23:53:47.345635 ENABLE_RX_DCM_DPHY: ON
9104 23:53:47.345716 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9105 23:53:47.348782 DUMMY_READ_FOR_TRACKING: OFF
9106 23:53:47.351901 !!! SPM_CONTROL_AFTERK: OFF
9107 23:53:47.355010 !!! SPM could not control APHY
9108 23:53:47.355092 IMPEDANCE_TRACKING: ON
9109 23:53:47.358335 TEMP_SENSOR: ON
9110 23:53:47.358418 HW_SAVE_FOR_SR: OFF
9111 23:53:47.362127 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9112 23:53:47.365140 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9113 23:53:47.368538 Read ODT Tracking: ON
9114 23:53:47.372006 Refresh Rate DeBounce: ON
9115 23:53:47.372114 DFS_NO_QUEUE_FLUSH: ON
9116 23:53:47.375054 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9117 23:53:47.378272 ENABLE_DFS_RUNTIME_MRW: OFF
9118 23:53:47.381507 DDR_RESERVE_NEW_MODE: ON
9119 23:53:47.381588 MR_CBT_SWITCH_FREQ: ON
9120 23:53:47.384920 =========================
9121 23:53:47.404250 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9122 23:53:47.407928 dram_init: ddr_geometry: 2
9123 23:53:47.426398 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9124 23:53:47.429486 dram_init: dram init end (result: 0)
9125 23:53:47.436023 DRAM-K: Full calibration passed in 24430 msecs
9126 23:53:47.439229 MRC: failed to locate region type 0.
9127 23:53:47.439312 DRAM rank0 size:0x100000000,
9128 23:53:47.442400 DRAM rank1 size=0x100000000
9129 23:53:47.452421 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9130 23:53:47.458760 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9131 23:53:47.465579 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9132 23:53:47.475210 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9133 23:53:47.475294 DRAM rank0 size:0x100000000,
9134 23:53:47.478429 DRAM rank1 size=0x100000000
9135 23:53:47.478511 CBMEM:
9136 23:53:47.481721 IMD: root @ 0xfffff000 254 entries.
9137 23:53:47.484969 IMD: root @ 0xffffec00 62 entries.
9138 23:53:47.491929 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9139 23:53:47.495235 WARNING: RO_VPD is uninitialized or empty.
9140 23:53:47.497940 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9141 23:53:47.505982 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9142 23:53:47.518548 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9143 23:53:47.530572 BS: romstage times (exec / console): total (unknown) / 23957 ms
9144 23:53:47.530657
9145 23:53:47.530721
9146 23:53:47.539976 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9147 23:53:47.543153 ARM64: Exception handlers installed.
9148 23:53:47.547072 ARM64: Testing exception
9149 23:53:47.550142 ARM64: Done test exception
9150 23:53:47.550224 Enumerating buses...
9151 23:53:47.553388 Show all devs... Before device enumeration.
9152 23:53:47.556444 Root Device: enabled 1
9153 23:53:47.559524 CPU_CLUSTER: 0: enabled 1
9154 23:53:47.559605 CPU: 00: enabled 1
9155 23:53:47.563509 Compare with tree...
9156 23:53:47.563590 Root Device: enabled 1
9157 23:53:47.566235 CPU_CLUSTER: 0: enabled 1
9158 23:53:47.569849 CPU: 00: enabled 1
9159 23:53:47.569931 Root Device scanning...
9160 23:53:47.573117 scan_static_bus for Root Device
9161 23:53:47.576154 CPU_CLUSTER: 0 enabled
9162 23:53:47.579388 scan_static_bus for Root Device done
9163 23:53:47.582992 scan_bus: bus Root Device finished in 8 msecs
9164 23:53:47.583099 done
9165 23:53:47.589162 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9166 23:53:47.592637 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9167 23:53:47.599461 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9168 23:53:47.606150 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9169 23:53:47.606236 Allocating resources...
9170 23:53:47.609164 Reading resources...
9171 23:53:47.612616 Root Device read_resources bus 0 link: 0
9172 23:53:47.615746 DRAM rank0 size:0x100000000,
9173 23:53:47.615831 DRAM rank1 size=0x100000000
9174 23:53:47.622085 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9175 23:53:47.622171 CPU: 00 missing read_resources
9176 23:53:47.628754 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9177 23:53:47.632205 Root Device read_resources bus 0 link: 0 done
9178 23:53:47.635098 Done reading resources.
9179 23:53:47.638937 Show resources in subtree (Root Device)...After reading.
9180 23:53:47.641997 Root Device child on link 0 CPU_CLUSTER: 0
9181 23:53:47.645224 CPU_CLUSTER: 0 child on link 0 CPU: 00
9182 23:53:47.655328 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9183 23:53:47.655414 CPU: 00
9184 23:53:47.661645 Root Device assign_resources, bus 0 link: 0
9185 23:53:47.664747 CPU_CLUSTER: 0 missing set_resources
9186 23:53:47.668636 Root Device assign_resources, bus 0 link: 0 done
9187 23:53:47.671805 Done setting resources.
9188 23:53:47.674906 Show resources in subtree (Root Device)...After assigning values.
9189 23:53:47.681626 Root Device child on link 0 CPU_CLUSTER: 0
9190 23:53:47.684678 CPU_CLUSTER: 0 child on link 0 CPU: 00
9191 23:53:47.691095 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9192 23:53:47.694123 CPU: 00
9193 23:53:47.694223 Done allocating resources.
9194 23:53:47.701262 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9195 23:53:47.704131 Enabling resources...
9196 23:53:47.704212 done.
9197 23:53:47.707791 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9198 23:53:47.711043 Initializing devices...
9199 23:53:47.711150 Root Device init
9200 23:53:47.714352 init hardware done!
9201 23:53:47.717724 0x00000018: ctrlr->caps
9202 23:53:47.717807 52.000 MHz: ctrlr->f_max
9203 23:53:47.720618 0.400 MHz: ctrlr->f_min
9204 23:53:47.724046 0x40ff8080: ctrlr->voltages
9205 23:53:47.724132 sclk: 390625
9206 23:53:47.724196 Bus Width = 1
9207 23:53:47.727174 sclk: 390625
9208 23:53:47.727256 Bus Width = 1
9209 23:53:47.731172 Early init status = 3
9210 23:53:47.733913 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9211 23:53:47.738902 in-header: 03 fc 00 00 01 00 00 00
9212 23:53:47.742012 in-data: 00
9213 23:53:47.745577 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9214 23:53:47.751103 in-header: 03 fd 00 00 00 00 00 00
9215 23:53:47.754365 in-data:
9216 23:53:47.757383 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9217 23:53:47.761751 in-header: 03 fc 00 00 01 00 00 00
9218 23:53:47.765023 in-data: 00
9219 23:53:47.768630 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9220 23:53:47.774762 in-header: 03 fd 00 00 00 00 00 00
9221 23:53:47.777566 in-data:
9222 23:53:47.781054 [SSUSB] Setting up USB HOST controller...
9223 23:53:47.784324 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9224 23:53:47.787417 [SSUSB] phy power-on done.
9225 23:53:47.790467 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9226 23:53:47.797495 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9227 23:53:47.800656 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9228 23:53:47.807507 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9229 23:53:47.813557 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9230 23:53:47.820241 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9231 23:53:47.827179 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9232 23:53:47.834047 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9233 23:53:47.836594 SPM: binary array size = 0x9dc
9234 23:53:47.840110 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9235 23:53:47.846838 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9236 23:53:47.853238 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9237 23:53:47.859932 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9238 23:53:47.863481 configure_display: Starting display init
9239 23:53:47.897920 anx7625_power_on_init: Init interface.
9240 23:53:47.901050 anx7625_disable_pd_protocol: Disabled PD feature.
9241 23:53:47.904288 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9242 23:53:47.932036 anx7625_start_dp_work: Secure OCM version=00
9243 23:53:47.934941 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9244 23:53:47.949674 sp_tx_get_edid_block: EDID Block = 1
9245 23:53:48.052775 Extracted contents:
9246 23:53:48.056057 header: 00 ff ff ff ff ff ff 00
9247 23:53:48.059053 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9248 23:53:48.062351 version: 01 04
9249 23:53:48.065750 basic params: 95 1f 11 78 0a
9250 23:53:48.069191 chroma info: 76 90 94 55 54 90 27 21 50 54
9251 23:53:48.072274 established: 00 00 00
9252 23:53:48.078598 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9253 23:53:48.085786 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9254 23:53:48.088772 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9255 23:53:48.095803 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9256 23:53:48.101782 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9257 23:53:48.105095 extensions: 00
9258 23:53:48.105171 checksum: fb
9259 23:53:48.105239
9260 23:53:48.112136 Manufacturer: IVO Model 57d Serial Number 0
9261 23:53:48.112225 Made week 0 of 2020
9262 23:53:48.115291 EDID version: 1.4
9263 23:53:48.115374 Digital display
9264 23:53:48.118526 6 bits per primary color channel
9265 23:53:48.121684 DisplayPort interface
9266 23:53:48.121766 Maximum image size: 31 cm x 17 cm
9267 23:53:48.125070 Gamma: 220%
9268 23:53:48.125151 Check DPMS levels
9269 23:53:48.131768 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9270 23:53:48.135021 First detailed timing is preferred timing
9271 23:53:48.138213 Established timings supported:
9272 23:53:48.138296 Standard timings supported:
9273 23:53:48.141238 Detailed timings
9274 23:53:48.145017 Hex of detail: 383680a07038204018303c0035ae10000019
9275 23:53:48.151456 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9276 23:53:48.154489 0780 0798 07c8 0820 hborder 0
9277 23:53:48.158210 0438 043b 0447 0458 vborder 0
9278 23:53:48.161127 -hsync -vsync
9279 23:53:48.161209 Did detailed timing
9280 23:53:48.168080 Hex of detail: 000000000000000000000000000000000000
9281 23:53:48.171062 Manufacturer-specified data, tag 0
9282 23:53:48.174383 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9283 23:53:48.177635 ASCII string: InfoVision
9284 23:53:48.180668 Hex of detail: 000000fe00523134304e574635205248200a
9285 23:53:48.184126 ASCII string: R140NWF5 RH
9286 23:53:48.184234 Checksum
9287 23:53:48.187441 Checksum: 0xfb (valid)
9288 23:53:48.190794 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9289 23:53:48.194210 DSI data_rate: 832800000 bps
9290 23:53:48.200554 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9291 23:53:48.203747 anx7625_parse_edid: pixelclock(138800).
9292 23:53:48.207459 hactive(1920), hsync(48), hfp(24), hbp(88)
9293 23:53:48.210877 vactive(1080), vsync(12), vfp(3), vbp(17)
9294 23:53:48.213697 anx7625_dsi_config: config dsi.
9295 23:53:48.220488 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9296 23:53:48.234505 anx7625_dsi_config: success to config DSI
9297 23:53:48.238286 anx7625_dp_start: MIPI phy setup OK.
9298 23:53:48.241465 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9299 23:53:48.244669 mtk_ddp_mode_set invalid vrefresh 60
9300 23:53:48.247648 main_disp_path_setup
9301 23:53:48.247729 ovl_layer_smi_id_en
9302 23:53:48.250822 ovl_layer_smi_id_en
9303 23:53:48.250903 ccorr_config
9304 23:53:48.250966 aal_config
9305 23:53:48.254543 gamma_config
9306 23:53:48.254624 postmask_config
9307 23:53:48.257775 dither_config
9308 23:53:48.260784 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9309 23:53:48.267573 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9310 23:53:48.270544 Root Device init finished in 555 msecs
9311 23:53:48.274352 CPU_CLUSTER: 0 init
9312 23:53:48.280598 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9313 23:53:48.287394 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9314 23:53:48.287482 APU_MBOX 0x190000b0 = 0x10001
9315 23:53:48.290473 APU_MBOX 0x190001b0 = 0x10001
9316 23:53:48.293950 APU_MBOX 0x190005b0 = 0x10001
9317 23:53:48.297423 APU_MBOX 0x190006b0 = 0x10001
9318 23:53:48.303852 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9319 23:53:48.313645 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9320 23:53:48.325967 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9321 23:53:48.332635 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9322 23:53:48.343922 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9323 23:53:48.353382 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9324 23:53:48.356355 CPU_CLUSTER: 0 init finished in 81 msecs
9325 23:53:48.359786 Devices initialized
9326 23:53:48.363248 Show all devs... After init.
9327 23:53:48.363322 Root Device: enabled 1
9328 23:53:48.366384 CPU_CLUSTER: 0: enabled 1
9329 23:53:48.369662 CPU: 00: enabled 1
9330 23:53:48.372944 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9331 23:53:48.376609 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9332 23:53:48.379845 ELOG: NV offset 0x57f000 size 0x1000
9333 23:53:48.386267 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9334 23:53:48.393075 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9335 23:53:48.396022 ELOG: Event(17) added with size 13 at 2024-05-29 23:53:48 UTC
9336 23:53:48.402660 out: cmd=0x121: 03 db 21 01 00 00 00 00
9337 23:53:48.406117 in-header: 03 d5 00 00 2c 00 00 00
9338 23:53:48.415909 in-data: 68 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9339 23:53:48.422682 ELOG: Event(A1) added with size 10 at 2024-05-29 23:53:48 UTC
9340 23:53:48.428996 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9341 23:53:48.435845 ELOG: Event(A0) added with size 9 at 2024-05-29 23:53:48 UTC
9342 23:53:48.439014 elog_add_boot_reason: Logged dev mode boot
9343 23:53:48.445733 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9344 23:53:48.445817 Finalize devices...
9345 23:53:48.448881 Devices finalized
9346 23:53:48.452090 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9347 23:53:48.455788 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9348 23:53:48.459593 in-header: 03 07 00 00 08 00 00 00
9349 23:53:48.462744 in-data: aa e4 47 04 13 02 00 00
9350 23:53:48.465866 Chrome EC: UHEPI supported
9351 23:53:48.472685 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9352 23:53:48.475879 in-header: 03 a9 00 00 08 00 00 00
9353 23:53:48.479009 in-data: 84 60 60 08 00 00 00 00
9354 23:53:48.485884 ELOG: Event(91) added with size 10 at 2024-05-29 23:53:48 UTC
9355 23:53:48.488942 Chrome EC: clear events_b mask to 0x0000000020004000
9356 23:53:48.495244 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9357 23:53:48.499619 in-header: 03 fd 00 00 00 00 00 00
9358 23:53:48.502777 in-data:
9359 23:53:48.506529 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9360 23:53:48.510270 Writing coreboot table at 0xffe64000
9361 23:53:48.516098 0. 000000000010a000-0000000000113fff: RAMSTAGE
9362 23:53:48.519794 1. 0000000040000000-00000000400fffff: RAM
9363 23:53:48.522956 2. 0000000040100000-000000004032afff: RAMSTAGE
9364 23:53:48.526038 3. 000000004032b000-00000000545fffff: RAM
9365 23:53:48.529282 4. 0000000054600000-000000005465ffff: BL31
9366 23:53:48.532792 5. 0000000054660000-00000000ffe63fff: RAM
9367 23:53:48.539454 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9368 23:53:48.542474 7. 0000000100000000-000000023fffffff: RAM
9369 23:53:48.546090 Passing 5 GPIOs to payload:
9370 23:53:48.549035 NAME | PORT | POLARITY | VALUE
9371 23:53:48.555999 EC in RW | 0x000000aa | low | undefined
9372 23:53:48.559041 EC interrupt | 0x00000005 | low | undefined
9373 23:53:48.566114 TPM interrupt | 0x000000ab | high | undefined
9374 23:53:48.569388 SD card detect | 0x00000011 | high | undefined
9375 23:53:48.572291 speaker enable | 0x00000093 | high | undefined
9376 23:53:48.575701 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9377 23:53:48.578828 in-header: 03 f9 00 00 02 00 00 00
9378 23:53:48.582612 in-data: 02 00
9379 23:53:48.585495 ADC[4]: Raw value=902586 ID=7
9380 23:53:48.589282 ADC[3]: Raw value=213916 ID=1
9381 23:53:48.589377 RAM Code: 0x71
9382 23:53:48.592433 ADC[6]: Raw value=74630 ID=0
9383 23:53:48.595658 ADC[5]: Raw value=213546 ID=1
9384 23:53:48.595740 SKU Code: 0x1
9385 23:53:48.602156 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7d3c
9386 23:53:48.602270 coreboot table: 964 bytes.
9387 23:53:48.605465 IMD ROOT 0. 0xfffff000 0x00001000
9388 23:53:48.609138 IMD SMALL 1. 0xffffe000 0x00001000
9389 23:53:48.612266 RO MCACHE 2. 0xffffc000 0x00001104
9390 23:53:48.615314 CONSOLE 3. 0xfff7c000 0x00080000
9391 23:53:48.618555 FMAP 4. 0xfff7b000 0x00000452
9392 23:53:48.621818 TIME STAMP 5. 0xfff7a000 0x00000910
9393 23:53:48.625172 VBOOT WORK 6. 0xfff66000 0x00014000
9394 23:53:48.628607 RAMOOPS 7. 0xffe66000 0x00100000
9395 23:53:48.631965 COREBOOT 8. 0xffe64000 0x00002000
9396 23:53:48.635104 IMD small region:
9397 23:53:48.638656 IMD ROOT 0. 0xffffec00 0x00000400
9398 23:53:48.641764 VPD 1. 0xffffeb80 0x0000006c
9399 23:53:48.645315 MMC STATUS 2. 0xffffeb60 0x00000004
9400 23:53:48.651392 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9401 23:53:48.658375 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9402 23:53:48.696918 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9403 23:53:48.700142 Checking segment from ROM address 0x40100000
9404 23:53:48.703335 Checking segment from ROM address 0x4010001c
9405 23:53:48.710143 Loading segment from ROM address 0x40100000
9406 23:53:48.710226 code (compression=0)
9407 23:53:48.719597 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9408 23:53:48.726718 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9409 23:53:48.726818 it's not compressed!
9410 23:53:48.732902 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9411 23:53:48.739623 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9412 23:53:48.757079 Loading segment from ROM address 0x4010001c
9413 23:53:48.757188 Entry Point 0x80000000
9414 23:53:48.760277 Loaded segments
9415 23:53:48.763634 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9416 23:53:48.770680 Jumping to boot code at 0x80000000(0xffe64000)
9417 23:53:48.776917 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9418 23:53:48.783493 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9419 23:53:48.791717 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9420 23:53:48.794723 Checking segment from ROM address 0x40100000
9421 23:53:48.798370 Checking segment from ROM address 0x4010001c
9422 23:53:48.805157 Loading segment from ROM address 0x40100000
9423 23:53:48.805266 code (compression=1)
9424 23:53:48.811477 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9425 23:53:48.820951 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9426 23:53:48.821030 using LZMA
9427 23:53:48.829907 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9428 23:53:48.836384 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9429 23:53:48.839561 Loading segment from ROM address 0x4010001c
9430 23:53:48.843082 Entry Point 0x54601000
9431 23:53:48.843180 Loaded segments
9432 23:53:48.846256 NOTICE: MT8192 bl31_setup
9433 23:53:48.853555 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9434 23:53:48.856655 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9435 23:53:48.860148 WARNING: region 0:
9436 23:53:48.863794 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 23:53:48.863869 WARNING: region 1:
9438 23:53:48.870119 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9439 23:53:48.873483 WARNING: region 2:
9440 23:53:48.876664 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9441 23:53:48.880194 WARNING: region 3:
9442 23:53:48.883487 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 23:53:48.886844 WARNING: region 4:
9444 23:53:48.893096 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9445 23:53:48.893174 WARNING: region 5:
9446 23:53:48.896169 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 23:53:48.899872 WARNING: region 6:
9448 23:53:48.902946 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 23:53:48.906547 WARNING: region 7:
9450 23:53:48.909940 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 23:53:48.916023 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9452 23:53:48.919405 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9453 23:53:48.926091 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9454 23:53:48.929424 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9455 23:53:48.932580 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9456 23:53:48.939476 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9457 23:53:48.942721 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9458 23:53:48.945961 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9459 23:53:48.952589 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9460 23:53:48.955599 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9461 23:53:48.962219 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9462 23:53:48.965427 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9463 23:53:48.968610 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9464 23:53:48.975381 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9465 23:53:48.978581 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9466 23:53:48.985107 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9467 23:53:48.988857 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9468 23:53:48.991809 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9469 23:53:48.998420 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9470 23:53:49.001867 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9471 23:53:49.008564 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9472 23:53:49.011729 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9473 23:53:49.014962 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9474 23:53:49.021883 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9475 23:53:49.025029 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9476 23:53:49.031449 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9477 23:53:49.034655 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9478 23:53:49.037945 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9479 23:53:49.044830 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9480 23:53:49.048056 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9481 23:53:49.054817 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9482 23:53:49.057779 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9483 23:53:49.061402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9484 23:53:49.067834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9485 23:53:49.071056 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9486 23:53:49.074620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9487 23:53:49.077833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9488 23:53:49.083969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9489 23:53:49.087686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9490 23:53:49.090792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9491 23:53:49.093806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9492 23:53:49.100887 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9493 23:53:49.103926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9494 23:53:49.107057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9495 23:53:49.110649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9496 23:53:49.117460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9497 23:53:49.120464 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9498 23:53:49.123689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9499 23:53:49.130612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9500 23:53:49.133591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9501 23:53:49.139989 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9502 23:53:49.143329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9503 23:53:49.147026 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9504 23:53:49.153121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9505 23:53:49.156800 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9506 23:53:49.163470 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9507 23:53:49.166687 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9508 23:53:49.172922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9509 23:53:49.176146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9510 23:53:49.182940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9511 23:53:49.186287 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9512 23:53:49.193001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9513 23:53:49.196244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9514 23:53:49.199135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9515 23:53:49.206237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9516 23:53:49.209567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9517 23:53:49.216179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9518 23:53:49.219193 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9519 23:53:49.226044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9520 23:53:49.229164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9521 23:53:49.236060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9522 23:53:49.238857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9523 23:53:49.242060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9524 23:53:49.248876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9525 23:53:49.252408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9526 23:53:49.258486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9527 23:53:49.262184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9528 23:53:49.268550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9529 23:53:49.272145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9530 23:53:49.278265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9531 23:53:49.281493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9532 23:53:49.288344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9533 23:53:49.291577 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9534 23:53:49.294554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9535 23:53:49.301472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9536 23:53:49.304710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9537 23:53:49.311144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9538 23:53:49.314809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9539 23:53:49.321612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9540 23:53:49.324717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9541 23:53:49.331426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9542 23:53:49.334553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9543 23:53:49.337664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9544 23:53:49.343993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9545 23:53:49.347903 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9546 23:53:49.354378 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9547 23:53:49.357425 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9548 23:53:49.360633 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9549 23:53:49.367545 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9550 23:53:49.370714 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9551 23:53:49.373823 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9552 23:53:49.380378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9553 23:53:49.383621 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9554 23:53:49.387227 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9555 23:53:49.394345 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9556 23:53:49.397017 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9557 23:53:49.403963 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9558 23:53:49.406938 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9559 23:53:49.410225 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9560 23:53:49.416854 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9561 23:53:49.420141 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9562 23:53:49.426897 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9563 23:53:49.429924 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9564 23:53:49.436885 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9565 23:53:49.440053 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9566 23:53:49.443225 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9567 23:53:49.446493 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9568 23:53:49.453191 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9569 23:53:49.456461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9570 23:53:49.462948 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9571 23:53:49.466145 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9572 23:53:49.469313 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9573 23:53:49.472545 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9574 23:53:49.479845 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9575 23:53:49.482980 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9576 23:53:49.486622 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9577 23:53:49.492853 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9578 23:53:49.495878 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9579 23:53:49.502776 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9580 23:53:49.506035 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9581 23:53:49.509147 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9582 23:53:49.515731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9583 23:53:49.518967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9584 23:53:49.525407 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9585 23:53:49.529005 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9586 23:53:49.532449 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9587 23:53:49.538894 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9588 23:53:49.541893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9589 23:53:49.545360 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9590 23:53:49.552081 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9591 23:53:49.555340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9592 23:53:49.562234 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9593 23:53:49.565375 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9594 23:53:49.571621 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9595 23:53:49.575371 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9596 23:53:49.578551 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9597 23:53:49.585203 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9598 23:53:49.588226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9599 23:53:49.594761 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9600 23:53:49.597964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9601 23:53:49.601540 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9602 23:53:49.607910 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9603 23:53:49.611623 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9604 23:53:49.617909 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9605 23:53:49.621025 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9606 23:53:49.624718 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9607 23:53:49.631487 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9608 23:53:49.634068 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9609 23:53:49.641117 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9610 23:53:49.644218 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9611 23:53:49.647310 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9612 23:53:49.654346 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9613 23:53:49.657105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9614 23:53:49.663696 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9615 23:53:49.666937 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9616 23:53:49.670477 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9617 23:53:49.676914 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9618 23:53:49.680061 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9619 23:53:49.686853 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9620 23:53:49.689811 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9621 23:53:49.693565 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9622 23:53:49.700227 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9623 23:53:49.703442 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9624 23:53:49.709715 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9625 23:53:49.713318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9626 23:53:49.716429 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9627 23:53:49.722856 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9628 23:53:49.725955 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9629 23:53:49.732881 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9630 23:53:49.735917 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9631 23:53:49.739121 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9632 23:53:49.745964 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9633 23:53:49.749021 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9634 23:53:49.755783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9635 23:53:49.759189 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9636 23:53:49.765692 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9637 23:53:49.768678 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9638 23:53:49.772507 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9639 23:53:49.778978 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9640 23:53:49.782001 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9641 23:53:49.789145 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9642 23:53:49.791933 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9643 23:53:49.795693 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9644 23:53:49.802045 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9645 23:53:49.805029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9646 23:53:49.812039 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9647 23:53:49.815004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9648 23:53:49.821351 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9649 23:53:49.825017 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9650 23:53:49.828187 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9651 23:53:49.835087 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9652 23:53:49.838088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9653 23:53:49.844512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9654 23:53:49.847652 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9655 23:53:49.854617 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9656 23:53:49.857820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9657 23:53:49.861332 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9658 23:53:49.867528 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9659 23:53:49.871247 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9660 23:53:49.877749 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9661 23:53:49.880618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9662 23:53:49.887620 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9663 23:53:49.890801 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9664 23:53:49.894268 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9665 23:53:49.900632 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9666 23:53:49.904277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9667 23:53:49.910566 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9668 23:53:49.914061 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9669 23:53:49.920598 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9670 23:53:49.923874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9671 23:53:49.927184 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9672 23:53:49.933917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9673 23:53:49.936993 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9674 23:53:49.943631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9675 23:53:49.946892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9676 23:53:49.950161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9677 23:53:49.957079 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9678 23:53:49.960161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9679 23:53:49.966555 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9680 23:53:49.970114 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9681 23:53:49.973773 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9682 23:53:49.976761 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9683 23:53:49.983077 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9684 23:53:49.986986 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9685 23:53:49.989955 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9686 23:53:49.996899 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9687 23:53:49.999672 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9688 23:53:50.006261 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9689 23:53:50.009859 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9690 23:53:50.012724 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9691 23:53:50.019496 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9692 23:53:50.022959 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9693 23:53:50.025783 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9694 23:53:50.032748 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9695 23:53:50.035981 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9696 23:53:50.042594 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9697 23:53:50.046156 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9698 23:53:50.049198 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9699 23:53:50.055634 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9700 23:53:50.058855 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9701 23:53:50.062027 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9702 23:53:50.068894 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9703 23:53:50.072120 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9704 23:53:50.075150 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9705 23:53:50.081753 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9706 23:53:50.085357 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9707 23:53:50.091736 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9708 23:53:50.094966 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9709 23:53:50.098275 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9710 23:53:50.105039 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9711 23:53:50.108248 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9712 23:53:50.114712 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9713 23:53:50.118514 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9714 23:53:50.121584 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9715 23:53:50.128230 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9716 23:53:50.132027 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9717 23:53:50.134562 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9718 23:53:50.141153 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9719 23:53:50.145033 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9720 23:53:50.147892 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9721 23:53:50.154543 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9722 23:53:50.157844 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9723 23:53:50.161104 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9724 23:53:50.164371 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9725 23:53:50.168139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9726 23:53:50.174310 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9727 23:53:50.178052 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9728 23:53:50.181205 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9729 23:53:50.184407 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9730 23:53:50.190832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9731 23:53:50.194519 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9732 23:53:50.197751 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9733 23:53:50.204430 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9734 23:53:50.207665 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9735 23:53:50.213922 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9736 23:53:50.217613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9737 23:53:50.224318 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9738 23:53:50.227405 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9739 23:53:50.230610 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9740 23:53:50.237414 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9741 23:53:50.240867 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9742 23:53:50.247372 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9743 23:53:50.250335 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9744 23:53:50.253822 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9745 23:53:50.260462 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9746 23:53:50.263430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9747 23:53:50.270379 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9748 23:53:50.273635 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9749 23:53:50.276711 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9750 23:53:50.283841 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9751 23:53:50.286846 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9752 23:53:50.293154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9753 23:53:50.296673 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9754 23:53:50.303268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9755 23:53:50.306577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9756 23:53:50.309766 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9757 23:53:50.316080 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9758 23:53:50.319434 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9759 23:53:50.325865 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9760 23:53:50.329182 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9761 23:53:50.336172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9762 23:53:50.339198 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9763 23:53:50.342202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9764 23:53:50.348883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9765 23:53:50.352544 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9766 23:53:50.359267 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9767 23:53:50.362090 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9768 23:53:50.365800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9769 23:53:50.372278 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9770 23:53:50.375692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9771 23:53:50.381999 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9772 23:53:50.385754 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9773 23:53:50.391961 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9774 23:53:50.394992 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9775 23:53:50.398911 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9776 23:53:50.404966 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9777 23:53:50.408601 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9778 23:53:50.415331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9779 23:53:50.418613 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9780 23:53:50.421774 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9781 23:53:50.428061 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9782 23:53:50.432056 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9783 23:53:50.438461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9784 23:53:50.441774 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9785 23:53:50.447896 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9786 23:53:50.451029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9787 23:53:50.457859 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9788 23:53:50.460834 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9789 23:53:50.464272 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9790 23:53:50.471194 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9791 23:53:50.474281 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9792 23:53:50.480684 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9793 23:53:50.483829 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9794 23:53:50.487278 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9795 23:53:50.494102 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9796 23:53:50.497146 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9797 23:53:50.504198 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9798 23:53:50.507295 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9799 23:53:50.510292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9800 23:53:50.517295 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9801 23:53:50.520425 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9802 23:53:50.526740 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9803 23:53:50.530458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9804 23:53:50.536914 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9805 23:53:50.540080 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9806 23:53:50.543144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9807 23:53:50.550047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9808 23:53:50.553461 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9809 23:53:50.560194 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9810 23:53:50.563336 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9811 23:53:50.569896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9812 23:53:50.572736 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9813 23:53:50.579797 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9814 23:53:50.582890 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9815 23:53:50.589367 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9816 23:53:50.592727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9817 23:53:50.595745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9818 23:53:50.602994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9819 23:53:50.606145 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9820 23:53:50.612330 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9821 23:53:50.615539 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9822 23:53:50.622224 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9823 23:53:50.625866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9824 23:53:50.632180 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9825 23:53:50.635196 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9826 23:53:50.642194 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9827 23:53:50.645335 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9828 23:53:50.648547 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9829 23:53:50.655239 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9830 23:53:50.658584 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9831 23:53:50.665204 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9832 23:53:50.668498 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9833 23:53:50.675087 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9834 23:53:50.678521 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9835 23:53:50.684786 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9836 23:53:50.688455 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9837 23:53:50.691957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9838 23:53:50.698411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9839 23:53:50.701425 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9840 23:53:50.707719 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9841 23:53:50.711390 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9842 23:53:50.717901 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9843 23:53:50.720927 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9844 23:53:50.724648 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9845 23:53:50.731186 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9846 23:53:50.734279 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9847 23:53:50.740736 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9848 23:53:50.743769 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9849 23:53:50.750923 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9850 23:53:50.754024 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9851 23:53:50.760494 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9852 23:53:50.764213 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9853 23:53:50.767195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9854 23:53:50.774056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9855 23:53:50.777142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9856 23:53:50.783422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9857 23:53:50.786844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9858 23:53:50.793696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9859 23:53:50.797160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9860 23:53:50.803618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9861 23:53:50.806706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9862 23:53:50.813084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9863 23:53:50.816478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9864 23:53:50.823391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9865 23:53:50.826539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9866 23:53:50.832960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9867 23:53:50.836677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9868 23:53:50.843362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9869 23:53:50.846553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9870 23:53:50.852825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9871 23:53:50.856066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9872 23:53:50.862963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9873 23:53:50.866107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9874 23:53:50.872535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9875 23:53:50.876194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9876 23:53:50.882849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9877 23:53:50.885916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9878 23:53:50.892499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9879 23:53:50.895943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9880 23:53:50.901996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9881 23:53:50.905590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9882 23:53:50.912229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9883 23:53:50.915414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9884 23:53:50.922467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9885 23:53:50.925201 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9886 23:53:50.928386 INFO: [APUAPC] vio 0
9887 23:53:50.931578 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9888 23:53:50.938715 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9889 23:53:50.942209 INFO: [APUAPC] D0_APC_0: 0x400510
9890 23:53:50.942324 INFO: [APUAPC] D0_APC_1: 0x0
9891 23:53:50.945069 INFO: [APUAPC] D0_APC_2: 0x1540
9892 23:53:50.948388 INFO: [APUAPC] D0_APC_3: 0x0
9893 23:53:50.951778 INFO: [APUAPC] D1_APC_0: 0xffffffff
9894 23:53:50.954928 INFO: [APUAPC] D1_APC_1: 0xffffffff
9895 23:53:50.958132 INFO: [APUAPC] D1_APC_2: 0x3fffff
9896 23:53:50.962010 INFO: [APUAPC] D1_APC_3: 0x0
9897 23:53:50.965109 INFO: [APUAPC] D2_APC_0: 0xffffffff
9898 23:53:50.968133 INFO: [APUAPC] D2_APC_1: 0xffffffff
9899 23:53:50.971356 INFO: [APUAPC] D2_APC_2: 0x3fffff
9900 23:53:50.974681 INFO: [APUAPC] D2_APC_3: 0x0
9901 23:53:50.977942 INFO: [APUAPC] D3_APC_0: 0xffffffff
9902 23:53:50.981527 INFO: [APUAPC] D3_APC_1: 0xffffffff
9903 23:53:50.984462 INFO: [APUAPC] D3_APC_2: 0x3fffff
9904 23:53:50.987725 INFO: [APUAPC] D3_APC_3: 0x0
9905 23:53:50.991491 INFO: [APUAPC] D4_APC_0: 0xffffffff
9906 23:53:50.994574 INFO: [APUAPC] D4_APC_1: 0xffffffff
9907 23:53:50.997722 INFO: [APUAPC] D4_APC_2: 0x3fffff
9908 23:53:51.000911 INFO: [APUAPC] D4_APC_3: 0x0
9909 23:53:51.004513 INFO: [APUAPC] D5_APC_0: 0xffffffff
9910 23:53:51.007462 INFO: [APUAPC] D5_APC_1: 0xffffffff
9911 23:53:51.010646 INFO: [APUAPC] D5_APC_2: 0x3fffff
9912 23:53:51.014212 INFO: [APUAPC] D5_APC_3: 0x0
9913 23:53:51.017460 INFO: [APUAPC] D6_APC_0: 0xffffffff
9914 23:53:51.020720 INFO: [APUAPC] D6_APC_1: 0xffffffff
9915 23:53:51.023753 INFO: [APUAPC] D6_APC_2: 0x3fffff
9916 23:53:51.027452 INFO: [APUAPC] D6_APC_3: 0x0
9917 23:53:51.030551 INFO: [APUAPC] D7_APC_0: 0xffffffff
9918 23:53:51.033588 INFO: [APUAPC] D7_APC_1: 0xffffffff
9919 23:53:51.037444 INFO: [APUAPC] D7_APC_2: 0x3fffff
9920 23:53:51.040344 INFO: [APUAPC] D7_APC_3: 0x0
9921 23:53:51.043651 INFO: [APUAPC] D8_APC_0: 0xffffffff
9922 23:53:51.046838 INFO: [APUAPC] D8_APC_1: 0xffffffff
9923 23:53:51.050656 INFO: [APUAPC] D8_APC_2: 0x3fffff
9924 23:53:51.053557 INFO: [APUAPC] D8_APC_3: 0x0
9925 23:53:51.056938 INFO: [APUAPC] D9_APC_0: 0xffffffff
9926 23:53:51.060235 INFO: [APUAPC] D9_APC_1: 0xffffffff
9927 23:53:51.063360 INFO: [APUAPC] D9_APC_2: 0x3fffff
9928 23:53:51.066556 INFO: [APUAPC] D9_APC_3: 0x0
9929 23:53:51.070325 INFO: [APUAPC] D10_APC_0: 0xffffffff
9930 23:53:51.073613 INFO: [APUAPC] D10_APC_1: 0xffffffff
9931 23:53:51.076789 INFO: [APUAPC] D10_APC_2: 0x3fffff
9932 23:53:51.079895 INFO: [APUAPC] D10_APC_3: 0x0
9933 23:53:51.083807 INFO: [APUAPC] D11_APC_0: 0xffffffff
9934 23:53:51.086959 INFO: [APUAPC] D11_APC_1: 0xffffffff
9935 23:53:51.090038 INFO: [APUAPC] D11_APC_2: 0x3fffff
9936 23:53:51.093346 INFO: [APUAPC] D11_APC_3: 0x0
9937 23:53:51.096310 INFO: [APUAPC] D12_APC_0: 0xffffffff
9938 23:53:51.099982 INFO: [APUAPC] D12_APC_1: 0xffffffff
9939 23:53:51.102913 INFO: [APUAPC] D12_APC_2: 0x3fffff
9940 23:53:51.106033 INFO: [APUAPC] D12_APC_3: 0x0
9941 23:53:51.109964 INFO: [APUAPC] D13_APC_0: 0xffffffff
9942 23:53:51.113094 INFO: [APUAPC] D13_APC_1: 0xffffffff
9943 23:53:51.116246 INFO: [APUAPC] D13_APC_2: 0x3fffff
9944 23:53:51.119434 INFO: [APUAPC] D13_APC_3: 0x0
9945 23:53:51.123153 INFO: [APUAPC] D14_APC_0: 0xffffffff
9946 23:53:51.126249 INFO: [APUAPC] D14_APC_1: 0xffffffff
9947 23:53:51.129535 INFO: [APUAPC] D14_APC_2: 0x3fffff
9948 23:53:51.132624 INFO: [APUAPC] D14_APC_3: 0x0
9949 23:53:51.136341 INFO: [APUAPC] D15_APC_0: 0xffffffff
9950 23:53:51.139478 INFO: [APUAPC] D15_APC_1: 0xffffffff
9951 23:53:51.142588 INFO: [APUAPC] D15_APC_2: 0x3fffff
9952 23:53:51.146190 INFO: [APUAPC] D15_APC_3: 0x0
9953 23:53:51.149177 INFO: [APUAPC] APC_CON: 0x4
9954 23:53:51.152624 INFO: [NOCDAPC] D0_APC_0: 0x0
9955 23:53:51.155942 INFO: [NOCDAPC] D0_APC_1: 0x0
9956 23:53:51.158991 INFO: [NOCDAPC] D1_APC_0: 0x0
9957 23:53:51.162368 INFO: [NOCDAPC] D1_APC_1: 0xfff
9958 23:53:51.162450 INFO: [NOCDAPC] D2_APC_0: 0x0
9959 23:53:51.165958 INFO: [NOCDAPC] D2_APC_1: 0xfff
9960 23:53:51.168682 INFO: [NOCDAPC] D3_APC_0: 0x0
9961 23:53:51.171981 INFO: [NOCDAPC] D3_APC_1: 0xfff
9962 23:53:51.175686 INFO: [NOCDAPC] D4_APC_0: 0x0
9963 23:53:51.178846 INFO: [NOCDAPC] D4_APC_1: 0xfff
9964 23:53:51.182200 INFO: [NOCDAPC] D5_APC_0: 0x0
9965 23:53:51.185395 INFO: [NOCDAPC] D5_APC_1: 0xfff
9966 23:53:51.189187 INFO: [NOCDAPC] D6_APC_0: 0x0
9967 23:53:51.192364 INFO: [NOCDAPC] D6_APC_1: 0xfff
9968 23:53:51.195180 INFO: [NOCDAPC] D7_APC_0: 0x0
9969 23:53:51.198830 INFO: [NOCDAPC] D7_APC_1: 0xfff
9970 23:53:51.198906 INFO: [NOCDAPC] D8_APC_0: 0x0
9971 23:53:51.201818 INFO: [NOCDAPC] D8_APC_1: 0xfff
9972 23:53:51.205569 INFO: [NOCDAPC] D9_APC_0: 0x0
9973 23:53:51.208573 INFO: [NOCDAPC] D9_APC_1: 0xfff
9974 23:53:51.211676 INFO: [NOCDAPC] D10_APC_0: 0x0
9975 23:53:51.214864 INFO: [NOCDAPC] D10_APC_1: 0xfff
9976 23:53:51.218381 INFO: [NOCDAPC] D11_APC_0: 0x0
9977 23:53:51.221450 INFO: [NOCDAPC] D11_APC_1: 0xfff
9978 23:53:51.224954 INFO: [NOCDAPC] D12_APC_0: 0x0
9979 23:53:51.227988 INFO: [NOCDAPC] D12_APC_1: 0xfff
9980 23:53:51.231603 INFO: [NOCDAPC] D13_APC_0: 0x0
9981 23:53:51.234910 INFO: [NOCDAPC] D13_APC_1: 0xfff
9982 23:53:51.237915 INFO: [NOCDAPC] D14_APC_0: 0x0
9983 23:53:51.241219 INFO: [NOCDAPC] D14_APC_1: 0xfff
9984 23:53:51.244470 INFO: [NOCDAPC] D15_APC_0: 0x0
9985 23:53:51.248198 INFO: [NOCDAPC] D15_APC_1: 0xfff
9986 23:53:51.248281 INFO: [NOCDAPC] APC_CON: 0x4
9987 23:53:51.251395 INFO: [APUAPC] set_apusys_apc done
9988 23:53:51.254596 INFO: [DEVAPC] devapc_init done
9989 23:53:51.260946 INFO: GICv3 without legacy support detected.
9990 23:53:51.264214 INFO: ARM GICv3 driver initialized in EL3
9991 23:53:51.267495 INFO: Maximum SPI INTID supported: 639
9992 23:53:51.271072 INFO: BL31: Initializing runtime services
9993 23:53:51.277599 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9994 23:53:51.281017 INFO: SPM: enable CPC mode
9995 23:53:51.284337 INFO: mcdi ready for mcusys-off-idle and system suspend
9996 23:53:51.290489 INFO: BL31: Preparing for EL3 exit to normal world
9997 23:53:51.294125 INFO: Entry point address = 0x80000000
9998 23:53:51.297475 INFO: SPSR = 0x8
9999 23:53:51.301640
10000 23:53:51.301729
10001 23:53:51.301795
10002 23:53:51.304707 Starting depthcharge on Spherion...
10003 23:53:51.304793
10004 23:53:51.304857 Wipe memory regions:
10005 23:53:51.304917
10006 23:53:51.305522 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10007 23:53:51.305628 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10008 23:53:51.305712 Setting prompt string to ['asurada:']
10009 23:53:51.305789 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10010 23:53:51.308247 [0x00000040000000, 0x00000054600000)
10011 23:53:51.430752
10012 23:53:51.430912 [0x00000054660000, 0x00000080000000)
10013 23:53:51.690993
10014 23:53:51.691125 [0x000000821a7280, 0x000000ffe64000)
10015 23:53:52.435900
10016 23:53:52.436031 [0x00000100000000, 0x00000240000000)
10017 23:53:54.325287
10018 23:53:54.328446 Initializing XHCI USB controller at 0x11200000.
10019 23:53:55.366970
10020 23:53:55.370076 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10021 23:53:55.370176
10022 23:53:55.370243
10023 23:53:55.370534 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 23:53:55.470873 asurada: tftpboot 192.168.201.1 14084359/tftp-deploy-z1crv513/kernel/image.itb 14084359/tftp-deploy-z1crv513/kernel/cmdline
10026 23:53:55.471027 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10027 23:53:55.471121 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10028 23:53:55.475819 tftpboot 192.168.201.1 14084359/tftp-deploy-z1crv513/kernel/image.itp-deploy-z1crv513/kernel/cmdline
10029 23:53:55.475911
10030 23:53:55.475976 Waiting for link
10031 23:53:55.633816
10032 23:53:55.633948 R8152: Initializing
10033 23:53:55.634016
10034 23:53:55.636927 Version 6 (ocp_data = 5c30)
10035 23:53:55.637009
10036 23:53:55.640204 R8152: Done initializing
10037 23:53:55.640278
10038 23:53:55.640340 Adding net device
10039 23:53:57.513761
10040 23:53:57.513927 done.
10041 23:53:57.514031
10042 23:53:57.514123 MAC: 00:24:32:30:7c:7b
10043 23:53:57.514201
10044 23:53:57.516770 Sending DHCP discover... done.
10045 23:53:57.516883
10046 23:53:57.520625 Waiting for reply... done.
10047 23:53:57.520737
10048 23:53:57.523683 Sending DHCP request... done.
10049 23:53:57.523789
10050 23:53:57.534661 Waiting for reply... done.
10051 23:53:57.534751
10052 23:53:57.534820 My ip is 192.168.201.14
10053 23:53:57.534891
10054 23:53:57.537835 The DHCP server ip is 192.168.201.1
10055 23:53:57.537914
10056 23:53:57.544791 TFTP server IP predefined by user: 192.168.201.1
10057 23:53:57.544899
10058 23:53:57.550967 Bootfile predefined by user: 14084359/tftp-deploy-z1crv513/kernel/image.itb
10059 23:53:57.551073
10060 23:53:57.554329 Sending tftp read request... done.
10061 23:53:57.554424
10062 23:53:57.558502 Waiting for the transfer...
10063 23:53:57.558586
10064 23:53:58.084806 00000000 ################################################################
10065 23:53:58.084946
10066 23:53:58.625919 00080000 ################################################################
10067 23:53:58.626066
10068 23:53:59.150148 00100000 ################################################################
10069 23:53:59.150312
10070 23:53:59.681488 00180000 ################################################################
10071 23:53:59.681670
10072 23:54:00.203472 00200000 ################################################################
10073 23:54:00.203633
10074 23:54:00.747061 00280000 ################################################################
10075 23:54:00.747305
10076 23:54:01.282830 00300000 ################################################################
10077 23:54:01.282997
10078 23:54:01.812190 00380000 ################################################################
10079 23:54:01.812345
10080 23:54:02.343696 00400000 ################################################################
10081 23:54:02.343833
10082 23:54:02.876874 00480000 ################################################################
10083 23:54:02.877042
10084 23:54:03.412512 00500000 ################################################################
10085 23:54:03.412682
10086 23:54:03.952522 00580000 ################################################################
10087 23:54:03.952705
10088 23:54:04.499849 00600000 ################################################################
10089 23:54:04.500020
10090 23:54:05.037099 00680000 ################################################################
10091 23:54:05.037276
10092 23:54:05.562452 00700000 ################################################################
10093 23:54:05.562622
10094 23:54:06.105661 00780000 ################################################################
10095 23:54:06.105851
10096 23:54:06.658354 00800000 ################################################################
10097 23:54:06.658513
10098 23:54:07.215811 00880000 ################################################################
10099 23:54:07.215947
10100 23:54:07.762112 00900000 ################################################################
10101 23:54:07.762238
10102 23:54:08.315156 00980000 ################################################################
10103 23:54:08.315288
10104 23:54:08.853307 00a00000 ################################################################
10105 23:54:08.853442
10106 23:54:09.406403 00a80000 ################################################################
10107 23:54:09.406533
10108 23:54:09.979273 00b00000 ################################################################
10109 23:54:09.979434
10110 23:54:10.542584 00b80000 ################################################################
10111 23:54:10.542719
10112 23:54:11.123935 00c00000 ################################################################
10113 23:54:11.124068
10114 23:54:11.705653 00c80000 ################################################################
10115 23:54:11.705783
10116 23:54:12.262024 00d00000 ################################################################
10117 23:54:12.262157
10118 23:54:12.807749 00d80000 ################################################################
10119 23:54:12.807909
10120 23:54:13.374488 00e00000 ################################################################
10121 23:54:13.374622
10122 23:54:13.926504 00e80000 ################################################################
10123 23:54:13.926639
10124 23:54:14.495847 00f00000 ################################################################
10125 23:54:14.495983
10126 23:54:15.082418 00f80000 ################################################################
10127 23:54:15.082560
10128 23:54:15.692138 01000000 ################################################################
10129 23:54:15.692272
10130 23:54:16.271904 01080000 ################################################################
10131 23:54:16.272065
10132 23:54:16.835099 01100000 ################################################################
10133 23:54:16.835275
10134 23:54:17.393780 01180000 ################################################################
10135 23:54:17.393931
10136 23:54:17.951422 01200000 ################################################################
10137 23:54:17.951554
10138 23:54:18.509949 01280000 ################################################################
10139 23:54:18.510105
10140 23:54:19.113908 01300000 ################################################################
10141 23:54:19.114056
10142 23:54:19.700548 01380000 ################################################################
10143 23:54:19.700685
10144 23:54:20.258675 01400000 ################################################################
10145 23:54:20.258806
10146 23:54:20.832420 01480000 ################################################################
10147 23:54:20.832554
10148 23:54:21.413573 01500000 ################################################################
10149 23:54:21.413722
10150 23:54:21.958632 01580000 ################################################################
10151 23:54:21.958783
10152 23:54:22.482398 01600000 ################################################################
10153 23:54:22.482565
10154 23:54:23.029138 01680000 ################################################################
10155 23:54:23.029329
10156 23:54:23.614196 01700000 ################################################################
10157 23:54:23.614359
10158 23:54:24.276805 01780000 ################################################################
10159 23:54:24.276963
10160 23:54:24.923378 01800000 ################################################################
10161 23:54:24.923551
10162 23:54:25.475588 01880000 ################################################################
10163 23:54:25.475758
10164 23:54:26.014063 01900000 ################################################################
10165 23:54:26.014224
10166 23:54:26.562585 01980000 ################################################################
10167 23:54:26.562760
10168 23:54:27.103132 01a00000 ################################################################
10169 23:54:27.103261
10170 23:54:27.653237 01a80000 ################################################################
10171 23:54:27.653407
10172 23:54:28.216712 01b00000 ################################################################
10173 23:54:28.216847
10174 23:54:28.783099 01b80000 ################################################################
10175 23:54:28.783232
10176 23:54:29.340715 01c00000 ################################################################
10177 23:54:29.340850
10178 23:54:29.898228 01c80000 ################################################################
10179 23:54:29.898372
10180 23:54:30.444376 01d00000 ################################################################
10181 23:54:30.444523
10182 23:54:30.989474 01d80000 ################################################################
10183 23:54:30.989622
10184 23:54:31.552191 01e00000 ################################################################
10185 23:54:31.552360
10186 23:54:32.112925 01e80000 ################################################################
10187 23:54:32.113085
10188 23:54:32.666305 01f00000 ################################################################
10189 23:54:32.666440
10190 23:54:33.230205 01f80000 ################################################################
10191 23:54:33.230365
10192 23:54:33.804583 02000000 ################################################################
10193 23:54:33.804719
10194 23:54:34.395761 02080000 ################################################################
10195 23:54:34.395893
10196 23:54:34.978138 02100000 ################################################################
10197 23:54:34.978300
10198 23:54:35.630381 02180000 ################################################################
10199 23:54:35.630883
10200 23:54:36.260543 02200000 ################################################################
10201 23:54:36.260679
10202 23:54:36.821439 02280000 ################################################################
10203 23:54:36.821577
10204 23:54:37.364177 02300000 ################################################################
10205 23:54:37.364328
10206 23:54:37.926999 02380000 ################################################################
10207 23:54:37.927152
10208 23:54:38.489137 02400000 ################################################################
10209 23:54:38.489327
10210 23:54:39.034824 02480000 ################################################################
10211 23:54:39.034963
10212 23:54:39.583618 02500000 ################################################################
10213 23:54:39.583764
10214 23:54:40.113531 02580000 ################################################################
10215 23:54:40.113677
10216 23:54:40.645479 02600000 ################################################################
10217 23:54:40.645616
10218 23:54:41.177277 02680000 ################################################################
10219 23:54:41.177422
10220 23:54:41.722400 02700000 ################################################################
10221 23:54:41.722559
10222 23:54:42.275952 02780000 ################################################################
10223 23:54:42.276187
10224 23:54:42.848517 02800000 ################################################################
10225 23:54:42.848655
10226 23:54:43.412864 02880000 ################################################################
10227 23:54:43.412999
10228 23:54:43.975568 02900000 ################################################################
10229 23:54:43.975742
10230 23:54:44.530621 02980000 ################################################################
10231 23:54:44.530770
10232 23:54:45.102255 02a00000 ################################################################
10233 23:54:45.102403
10234 23:54:45.680652 02a80000 ################################################################
10235 23:54:45.680802
10236 23:54:46.260245 02b00000 ################################################################
10237 23:54:46.260398
10238 23:54:46.826668 02b80000 ################################################################
10239 23:54:46.826834
10240 23:54:47.363021 02c00000 ################################################################
10241 23:54:47.363160
10242 23:54:47.915115 02c80000 ################################################################
10243 23:54:47.915290
10244 23:54:48.519640 02d00000 ################################################################
10245 23:54:48.519771
10246 23:54:49.121480 02d80000 ################################################################
10247 23:54:49.121625
10248 23:54:49.686830 02e00000 ################################################################
10249 23:54:49.687020
10250 23:54:50.251367 02e80000 ################################################################
10251 23:54:50.251522
10252 23:54:50.820538 02f00000 ################################################################
10253 23:54:50.820669
10254 23:54:51.370395 02f80000 ################################################################
10255 23:54:51.370529
10256 23:54:51.927702 03000000 ################################################################
10257 23:54:51.927835
10258 23:54:52.477779 03080000 ################################################################
10259 23:54:52.477914
10260 23:54:53.025986 03100000 ################################################################
10261 23:54:53.026121
10262 23:54:53.575479 03180000 ################################################################
10263 23:54:53.575617
10264 23:54:54.121178 03200000 ################################################################
10265 23:54:54.121342
10266 23:54:54.666437 03280000 ################################################################
10267 23:54:54.666608
10268 23:54:55.212149 03300000 ################################################################
10269 23:54:55.212282
10270 23:54:55.533751 03380000 ####################################### done.
10271 23:54:55.533881
10272 23:54:55.536845 The bootfile was 54315394 bytes long.
10273 23:54:55.536925
10274 23:54:55.540045 Sending tftp read request... done.
10275 23:54:55.540152
10276 23:54:55.543522 Waiting for the transfer...
10277 23:54:55.543629
10278 23:54:55.547529 00000000 # done.
10279 23:54:55.547609
10280 23:54:55.553847 Command line loaded dynamically from TFTP file: 14084359/tftp-deploy-z1crv513/kernel/cmdline
10281 23:54:55.553929
10282 23:54:55.566815 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10283 23:54:55.566910
10284 23:54:55.566979 Loading FIT.
10285 23:54:55.567042
10286 23:54:55.570139 Image ramdisk-1 has 41202613 bytes.
10287 23:54:55.570216
10288 23:54:55.573867 Image fdt-1 has 47258 bytes.
10289 23:54:55.573942
10290 23:54:55.576806 Image kernel-1 has 13063488 bytes.
10291 23:54:55.576889
10292 23:54:55.587181 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10293 23:54:55.587263
10294 23:54:55.603167 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10295 23:54:55.603273
10296 23:54:55.610085 Choosing best match conf-1 for compat google,spherion-rev2.
10297 23:54:55.610168
10298 23:54:55.617441 Connected to device vid:did:rid of 1ae0:0028:00
10299 23:54:55.625824
10300 23:54:55.629500 tpm_get_response: command 0x17b, return code 0x0
10301 23:54:55.629584
10302 23:54:55.632318 ec_init: CrosEC protocol v3 supported (256, 248)
10303 23:54:55.636760
10304 23:54:55.639797 tpm_cleanup: add release locality here.
10305 23:54:55.639878
10306 23:54:55.639963 Shutting down all USB controllers.
10307 23:54:55.640027
10308 23:54:55.642913 Removing current net device
10309 23:54:55.642994
10310 23:54:55.649908 Exiting depthcharge with code 4 at timestamp: 93595815
10311 23:54:55.649990
10312 23:54:55.652980 LZMA decompressing kernel-1 to 0x821a6718
10313 23:54:55.653062
10314 23:54:55.656604 LZMA decompressing kernel-1 to 0x40000000
10315 23:54:57.267257
10316 23:54:57.267393 jumping to kernel
10317 23:54:57.267903 end: 2.2.4 bootloader-commands (duration 00:01:06) [common]
10318 23:54:57.268001 start: 2.2.5 auto-login-action (timeout 00:03:21) [common]
10319 23:54:57.268076 Setting prompt string to ['Linux version [0-9]']
10320 23:54:57.268176 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10321 23:54:57.268245 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10322 23:54:57.350290
10323 23:54:57.353306 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10324 23:54:57.356714 start: 2.2.5.1 login-action (timeout 00:03:21) [common]
10325 23:54:57.356830 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10326 23:54:57.356902 Setting prompt string to []
10327 23:54:57.356994 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10328 23:54:57.357096 Using line separator: #'\n'#
10329 23:54:57.357183 No login prompt set.
10330 23:54:57.357332 Parsing kernel messages
10331 23:54:57.357432 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10332 23:54:57.357538 [login-action] Waiting for messages, (timeout 00:03:21)
10333 23:54:57.357605 Waiting using forced prompt support (timeout 00:01:40)
10334 23:54:57.377213 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10335 23:54:57.379572 [ 0.000000] random: crng init done
10336 23:54:57.386846 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 23:54:57.389692 [ 0.000000] efi: UEFI not found.
10338 23:54:57.396588 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 23:54:57.403407 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 23:54:57.413481 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 23:54:57.422986 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 23:54:57.429708 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 23:54:57.435838 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 23:54:57.442456 [ 0.000000] NUMA: No NUMA configuration found
10345 23:54:57.449425 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 23:54:57.452487 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10347 23:54:57.455780 [ 0.000000] Zone ranges:
10348 23:54:57.462521 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 23:54:57.466014 [ 0.000000] DMA32 empty
10350 23:54:57.472369 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 23:54:57.475686 [ 0.000000] Movable zone start for each node
10352 23:54:57.479188 [ 0.000000] Early memory node ranges
10353 23:54:57.486044 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 23:54:57.492337 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 23:54:57.498897 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 23:54:57.505980 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 23:54:57.509098 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 23:54:57.519041 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 23:54:57.573914 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 23:54:57.580649 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 23:54:57.587163 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 23:54:57.590626 [ 0.000000] psci: probing for conduit method from DT.
10363 23:54:57.597737 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 23:54:57.600550 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 23:54:57.607528 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 23:54:57.610326 [ 0.000000] psci: SMC Calling Convention v1.2
10367 23:54:57.617417 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10368 23:54:57.620469 [ 0.000000] Detected VIPT I-cache on CPU0
10369 23:54:57.626840 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 23:54:57.633438 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 23:54:57.640073 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 23:54:57.646706 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 23:54:57.653790 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 23:54:57.663692 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 23:54:57.666993 [ 0.000000] alternatives: applying boot alternatives
10376 23:54:57.673528 [ 0.000000] Fallback order for Node 0: 0
10377 23:54:57.679932 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 23:54:57.683398 [ 0.000000] Policy zone: Normal
10379 23:54:57.697314 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10380 23:54:57.706635 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 23:54:57.718871 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 23:54:57.728477 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 23:54:57.734896 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10384 23:54:57.738338 <6>[ 0.000000] software IO TLB: area num 8.
10385 23:54:57.794824 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 23:54:57.943727 <6>[ 0.000000] Memory: 7923952K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428816K reserved, 32768K cma-reserved)
10387 23:54:57.951186 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 23:54:57.957054 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 23:54:57.960635 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 23:54:57.967395 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 23:54:57.973499 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 23:54:57.976824 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 23:54:57.986766 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 23:54:57.993220 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 23:54:58.000634 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 23:54:58.006461 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 23:54:58.010456 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 23:54:58.013484 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 23:54:58.019753 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 23:54:58.023419 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 23:54:58.030382 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 23:54:58.043109 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 23:54:58.053110 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 23:54:58.062767 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 23:54:58.070388 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 23:54:58.083717 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 23:54:58.089781 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 23:54:58.097382 <6>[ 0.009179] Console: colour dummy device 80x25
10409 23:54:58.107514 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 23:54:58.113132 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10411 23:54:58.116967 <6>[ 0.029221] LSM: Security Framework initializing
10412 23:54:58.123152 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 23:54:58.134375 <6>[ 0.041971] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 23:54:58.140036 <6>[ 0.051396] cblist_init_generic: Setting adjustable number of callback queues.
10415 23:54:58.146175 <6>[ 0.058884] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 23:54:58.156508 <6>[ 0.065223] cblist_init_generic: Setting adjustable number of callback queues.
10417 23:54:58.163486 <6>[ 0.072649] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 23:54:58.166031 <6>[ 0.079050] rcu: Hierarchical SRCU implementation.
10419 23:54:58.173457 <6>[ 0.084065] rcu: Max phase no-delay instances is 1000.
10420 23:54:58.179794 <6>[ 0.091086] EFI services will not be available.
10421 23:54:58.182801 <6>[ 0.096043] smp: Bringing up secondary CPUs ...
10422 23:54:58.191279 <6>[ 0.101118] Detected VIPT I-cache on CPU1
10423 23:54:58.197744 <6>[ 0.101190] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 23:54:58.204157 <6>[ 0.101222] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 23:54:58.207308 <6>[ 0.101557] Detected VIPT I-cache on CPU2
10426 23:54:58.214422 <6>[ 0.101606] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 23:54:58.221217 <6>[ 0.101622] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 23:54:58.227252 <6>[ 0.101879] Detected VIPT I-cache on CPU3
10429 23:54:58.233880 <6>[ 0.101926] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 23:54:58.240354 <6>[ 0.101940] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 23:54:58.244100 <6>[ 0.102243] CPU features: detected: Spectre-v4
10432 23:54:58.250769 <6>[ 0.102249] CPU features: detected: Spectre-BHB
10433 23:54:58.253862 <6>[ 0.102254] Detected PIPT I-cache on CPU4
10434 23:54:58.261213 <6>[ 0.102314] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 23:54:58.267029 <6>[ 0.102330] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 23:54:58.273266 <6>[ 0.102622] Detected PIPT I-cache on CPU5
10437 23:54:58.280431 <6>[ 0.102682] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 23:54:58.286948 <6>[ 0.102698] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 23:54:58.290065 <6>[ 0.102982] Detected PIPT I-cache on CPU6
10440 23:54:58.296683 <6>[ 0.103046] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 23:54:58.303283 <6>[ 0.103062] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 23:54:58.310191 <6>[ 0.103356] Detected PIPT I-cache on CPU7
10443 23:54:58.317385 <6>[ 0.103420] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 23:54:58.323197 <6>[ 0.103436] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 23:54:58.326705 <6>[ 0.103483] smp: Brought up 1 node, 8 CPUs
10446 23:54:58.333229 <6>[ 0.244791] SMP: Total of 8 processors activated.
10447 23:54:58.336797 <6>[ 0.249712] CPU features: detected: 32-bit EL0 Support
10448 23:54:58.346218 <6>[ 0.255075] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 23:54:58.353041 <6>[ 0.263930] CPU features: detected: Common not Private translations
10450 23:54:58.360020 <6>[ 0.270437] CPU features: detected: CRC32 instructions
10451 23:54:58.362815 <6>[ 0.275788] CPU features: detected: RCpc load-acquire (LDAPR)
10452 23:54:58.369580 <6>[ 0.281748] CPU features: detected: LSE atomic instructions
10453 23:54:58.376463 <6>[ 0.287529] CPU features: detected: Privileged Access Never
10454 23:54:58.382967 <6>[ 0.293309] CPU features: detected: RAS Extension Support
10455 23:54:58.389807 <6>[ 0.298918] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 23:54:58.392735 <6>[ 0.306180] CPU: All CPU(s) started at EL2
10457 23:54:58.399075 <6>[ 0.310497] alternatives: applying system-wide alternatives
10458 23:54:58.409058 <6>[ 0.321379] devtmpfs: initialized
10459 23:54:58.421053 <6>[ 0.330332] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10460 23:54:58.431129 <6>[ 0.340287] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10461 23:54:58.437805 <6>[ 0.348306] pinctrl core: initialized pinctrl subsystem
10462 23:54:58.441048 <6>[ 0.354946] DMI not present or invalid.
10463 23:54:58.448003 <6>[ 0.359354] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10464 23:54:58.457464 <6>[ 0.366212] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10465 23:54:58.463906 <6>[ 0.373798] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10466 23:54:58.474471 <6>[ 0.382019] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10467 23:54:58.477210 <6>[ 0.390263] audit: initializing netlink subsys (disabled)
10468 23:54:58.487454 <5>[ 0.395955] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10469 23:54:58.494052 <6>[ 0.396654] thermal_sys: Registered thermal governor 'step_wise'
10470 23:54:58.500939 <6>[ 0.403920] thermal_sys: Registered thermal governor 'power_allocator'
10471 23:54:58.503905 <6>[ 0.410174] cpuidle: using governor menu
10472 23:54:58.510460 <6>[ 0.421133] NET: Registered PF_QIPCRTR protocol family
10473 23:54:58.517045 <6>[ 0.426608] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10474 23:54:58.520592 <6>[ 0.433707] ASID allocator initialised with 32768 entries
10475 23:54:58.527837 <6>[ 0.440280] Serial: AMBA PL011 UART driver
10476 23:54:58.536316 <4>[ 0.449024] Trying to register duplicate clock ID: 134
10477 23:54:58.594693 <6>[ 0.510466] KASLR enabled
10478 23:54:58.609160 <6>[ 0.518202] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10479 23:54:58.615835 <6>[ 0.525217] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10480 23:54:58.622508 <6>[ 0.531707] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10481 23:54:58.628735 <6>[ 0.538710] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10482 23:54:58.635820 <6>[ 0.545200] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10483 23:54:58.641649 <6>[ 0.552202] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10484 23:54:58.648935 <6>[ 0.558690] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10485 23:54:58.654946 <6>[ 0.565697] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10486 23:54:58.658442 <6>[ 0.573222] ACPI: Interpreter disabled.
10487 23:54:58.666835 <6>[ 0.579668] iommu: Default domain type: Translated
10488 23:54:58.673657 <6>[ 0.584780] iommu: DMA domain TLB invalidation policy: strict mode
10489 23:54:58.676687 <5>[ 0.591442] SCSI subsystem initialized
10490 23:54:58.683611 <6>[ 0.595608] usbcore: registered new interface driver usbfs
10491 23:54:58.690612 <6>[ 0.601340] usbcore: registered new interface driver hub
10492 23:54:58.693514 <6>[ 0.606894] usbcore: registered new device driver usb
10493 23:54:58.700651 <6>[ 0.612990] pps_core: LinuxPPS API ver. 1 registered
10494 23:54:58.710296 <6>[ 0.618183] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10495 23:54:58.713438 <6>[ 0.627529] PTP clock support registered
10496 23:54:58.716755 <6>[ 0.631770] EDAC MC: Ver: 3.0.0
10497 23:54:58.724496 <6>[ 0.636920] FPGA manager framework
10498 23:54:58.730915 <6>[ 0.640608] Advanced Linux Sound Architecture Driver Initialized.
10499 23:54:58.733834 <6>[ 0.647380] vgaarb: loaded
10500 23:54:58.740652 <6>[ 0.650537] clocksource: Switched to clocksource arch_sys_counter
10501 23:54:58.743760 <5>[ 0.656980] VFS: Disk quotas dquot_6.6.0
10502 23:54:58.750568 <6>[ 0.661165] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10503 23:54:58.753601 <6>[ 0.668358] pnp: PnP ACPI: disabled
10504 23:54:58.762481 <6>[ 0.675034] NET: Registered PF_INET protocol family
10505 23:54:58.772212 <6>[ 0.680629] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10506 23:54:58.783334 <6>[ 0.692882] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10507 23:54:58.793240 <6>[ 0.701691] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10508 23:54:58.800169 <6>[ 0.709659] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10509 23:54:58.809875 <6>[ 0.718356] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10510 23:54:58.816309 <6>[ 0.728076] TCP: Hash tables configured (established 65536 bind 65536)
10511 23:54:58.823262 <6>[ 0.734942] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 23:54:58.832720 <6>[ 0.742141] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 23:54:58.839383 <6>[ 0.749840] NET: Registered PF_UNIX/PF_LOCAL protocol family
10514 23:54:58.846395 <6>[ 0.755995] RPC: Registered named UNIX socket transport module.
10515 23:54:58.849585 <6>[ 0.762147] RPC: Registered udp transport module.
10516 23:54:58.855546 <6>[ 0.767077] RPC: Registered tcp transport module.
10517 23:54:58.862676 <6>[ 0.772010] RPC: Registered tcp NFSv4.1 backchannel transport module.
10518 23:54:58.865780 <6>[ 0.778676] PCI: CLS 0 bytes, default 64
10519 23:54:58.869118 <6>[ 0.783007] Unpacking initramfs...
10520 23:54:58.893632 <6>[ 0.802729] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10521 23:54:58.903374 <6>[ 0.811380] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10522 23:54:58.906563 <6>[ 0.820213] kvm [1]: IPA Size Limit: 40 bits
10523 23:54:58.912856 <6>[ 0.824743] kvm [1]: GICv3: no GICV resource entry
10524 23:54:58.916830 <6>[ 0.829764] kvm [1]: disabling GICv2 emulation
10525 23:54:58.923165 <6>[ 0.834450] kvm [1]: GIC system register CPU interface enabled
10526 23:54:58.926435 <6>[ 0.840605] kvm [1]: vgic interrupt IRQ18
10527 23:54:58.933059 <6>[ 0.844949] kvm [1]: VHE mode initialized successfully
10528 23:54:58.939866 <5>[ 0.851376] Initialise system trusted keyrings
10529 23:54:58.945720 <6>[ 0.856217] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10530 23:54:58.953850 <6>[ 0.866230] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10531 23:54:58.960686 <5>[ 0.872624] NFS: Registering the id_resolver key type
10532 23:54:58.963322 <5>[ 0.877920] Key type id_resolver registered
10533 23:54:58.970363 <5>[ 0.882333] Key type id_legacy registered
10534 23:54:58.976804 <6>[ 0.886622] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10535 23:54:58.983780 <6>[ 0.893546] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10536 23:54:58.989795 <6>[ 0.901267] 9p: Installing v9fs 9p2000 file system support
10537 23:54:59.026411 <5>[ 0.939195] Key type asymmetric registered
10538 23:54:59.030524 <5>[ 0.943525] Asymmetric key parser 'x509' registered
10539 23:54:59.039550 <6>[ 0.948712] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10540 23:54:59.043198 <6>[ 0.956331] io scheduler mq-deadline registered
10541 23:54:59.046351 <6>[ 0.961096] io scheduler kyber registered
10542 23:54:59.065142 <6>[ 0.978031] EINJ: ACPI disabled.
10543 23:54:59.097983 <4>[ 1.004135] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 23:54:59.108133 <4>[ 1.014789] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 23:54:59.123252 <6>[ 1.035611] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10546 23:54:59.130988 <6>[ 1.043689] printk: console [ttyS0] disabled
10547 23:54:59.158967 <6>[ 1.068318] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10548 23:54:59.165338 <6>[ 1.077786] printk: console [ttyS0] enabled
10549 23:54:59.169314 <6>[ 1.077786] printk: console [ttyS0] enabled
10550 23:54:59.175523 <6>[ 1.086682] printk: bootconsole [mtk8250] disabled
10551 23:54:59.179115 <6>[ 1.086682] printk: bootconsole [mtk8250] disabled
10552 23:54:59.185671 <6>[ 1.097784] SuperH (H)SCI(F) driver initialized
10553 23:54:59.188864 <6>[ 1.103074] msm_serial: driver initialized
10554 23:54:59.202568 <6>[ 1.111980] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10555 23:54:59.212999 <6>[ 1.120531] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10556 23:54:59.219099 <6>[ 1.129073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10557 23:54:59.229521 <6>[ 1.137700] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10558 23:54:59.239004 <6>[ 1.146407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10559 23:54:59.245606 <6>[ 1.155126] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10560 23:54:59.255344 <6>[ 1.163666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10561 23:54:59.262308 <6>[ 1.172461] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10562 23:54:59.272588 <6>[ 1.181005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10563 23:54:59.283900 <6>[ 1.196752] loop: module loaded
10564 23:54:59.291187 <6>[ 1.202710] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10565 23:54:59.313677 <4>[ 1.226025] mtk-pmic-keys: Failed to locate of_node [id: -1]
10566 23:54:59.320088 <6>[ 1.232835] megasas: 07.719.03.00-rc1
10567 23:54:59.329783 <6>[ 1.242362] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10568 23:54:59.337059 <6>[ 1.249928] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10569 23:54:59.354065 <6>[ 1.266674] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10570 23:54:59.410468 <6>[ 1.316512] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10571 23:55:00.599583 <6>[ 2.512476] Freeing initrd memory: 40232K
10572 23:55:00.611366 <6>[ 2.524211] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10573 23:55:00.622441 <6>[ 2.535110] tun: Universal TUN/TAP device driver, 1.6
10574 23:55:00.625632 <6>[ 2.541154] thunder_xcv, ver 1.0
10575 23:55:00.628619 <6>[ 2.544663] thunder_bgx, ver 1.0
10576 23:55:00.632669 <6>[ 2.548158] nicpf, ver 1.0
10577 23:55:00.642683 <6>[ 2.552160] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10578 23:55:00.645625 <6>[ 2.559637] hns3: Copyright (c) 2017 Huawei Corporation.
10579 23:55:00.653031 <6>[ 2.565223] hclge is initializing
10580 23:55:00.656571 <6>[ 2.568803] e1000: Intel(R) PRO/1000 Network Driver
10581 23:55:00.662238 <6>[ 2.573932] e1000: Copyright (c) 1999-2006 Intel Corporation.
10582 23:55:00.665691 <6>[ 2.579944] e1000e: Intel(R) PRO/1000 Network Driver
10583 23:55:00.672344 <6>[ 2.585159] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10584 23:55:00.679520 <6>[ 2.591343] igb: Intel(R) Gigabit Ethernet Network Driver
10585 23:55:00.685691 <6>[ 2.596992] igb: Copyright (c) 2007-2014 Intel Corporation.
10586 23:55:00.692307 <6>[ 2.602831] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10587 23:55:00.699362 <6>[ 2.609348] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10588 23:55:00.702026 <6>[ 2.615804] sky2: driver version 1.30
10589 23:55:00.708626 <6>[ 2.620722] usbcore: registered new device driver r8152-cfgselector
10590 23:55:00.715998 <6>[ 2.627258] usbcore: registered new interface driver r8152
10591 23:55:00.722039 <6>[ 2.633069] VFIO - User Level meta-driver version: 0.3
10592 23:55:00.729696 <6>[ 2.641299] usbcore: registered new interface driver usb-storage
10593 23:55:00.735506 <6>[ 2.647747] usbcore: registered new device driver onboard-usb-hub
10594 23:55:00.743974 <6>[ 2.656848] mt6397-rtc mt6359-rtc: registered as rtc0
10595 23:55:00.753642 <6>[ 2.662309] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:55:01 UTC (1717026901)
10596 23:55:00.756933 <6>[ 2.671862] i2c_dev: i2c /dev entries driver
10597 23:55:00.773763 <6>[ 2.683578] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10598 23:55:00.780794 <4>[ 2.692304] cpu cpu0: supply cpu not found, using dummy regulator
10599 23:55:00.787779 <4>[ 2.698733] cpu cpu1: supply cpu not found, using dummy regulator
10600 23:55:00.794094 <4>[ 2.705140] cpu cpu2: supply cpu not found, using dummy regulator
10601 23:55:00.800412 <4>[ 2.711555] cpu cpu3: supply cpu not found, using dummy regulator
10602 23:55:00.807112 <4>[ 2.717951] cpu cpu4: supply cpu not found, using dummy regulator
10603 23:55:00.813974 <4>[ 2.724352] cpu cpu5: supply cpu not found, using dummy regulator
10604 23:55:00.820357 <4>[ 2.730746] cpu cpu6: supply cpu not found, using dummy regulator
10605 23:55:00.827280 <4>[ 2.737139] cpu cpu7: supply cpu not found, using dummy regulator
10606 23:55:00.845091 <6>[ 2.757789] cpu cpu0: EM: created perf domain
10607 23:55:00.847850 <6>[ 2.762747] cpu cpu4: EM: created perf domain
10608 23:55:00.855845 <6>[ 2.768328] sdhci: Secure Digital Host Controller Interface driver
10609 23:55:00.861940 <6>[ 2.774763] sdhci: Copyright(c) Pierre Ossman
10610 23:55:00.868566 <6>[ 2.779732] Synopsys Designware Multimedia Card Interface Driver
10611 23:55:00.875402 <6>[ 2.786360] sdhci-pltfm: SDHCI platform and OF driver helper
10612 23:55:00.878989 <6>[ 2.786399] mmc0: CQHCI version 5.10
10613 23:55:00.885047 <6>[ 2.796598] ledtrig-cpu: registered to indicate activity on CPUs
10614 23:55:00.891733 <6>[ 2.803694] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10615 23:55:00.898516 <6>[ 2.810761] usbcore: registered new interface driver usbhid
10616 23:55:00.901943 <6>[ 2.816583] usbhid: USB HID core driver
10617 23:55:00.911950 <6>[ 2.820747] spi_master spi0: will run message pump with realtime priority
10618 23:55:00.951572 <6>[ 2.857974] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10619 23:55:00.970884 <6>[ 2.873125] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10620 23:55:00.977123 <6>[ 2.888173] cros-ec-spi spi0.0: Chrome EC device registered
10621 23:55:00.980895 <6>[ 2.894282] mmc0: Command Queue Engine enabled
10622 23:55:00.987477 <6>[ 2.899046] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10623 23:55:00.993721 <6>[ 2.906650] mmcblk0: mmc0:0001 DA4128 116 GiB
10624 23:55:01.003371 <6>[ 2.915927] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 23:55:01.010435 <6>[ 2.923258] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10626 23:55:01.020213 <6>[ 2.928724] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10627 23:55:01.026950 <6>[ 2.929272] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10628 23:55:01.030237 <6>[ 2.939296] NET: Registered PF_PACKET protocol family
10629 23:55:01.036863 <6>[ 2.943948] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10630 23:55:01.043464 <6>[ 2.948650] 9pnet: Installing 9P2000 support
10631 23:55:01.046705 <5>[ 2.959653] Key type dns_resolver registered
10632 23:55:01.049860 <6>[ 2.964627] registered taskstats version 1
10633 23:55:01.056639 <5>[ 2.969005] Loading compiled-in X.509 certificates
10634 23:55:01.086929 <4>[ 2.993280] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 23:55:01.096786 <4>[ 3.004195] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 23:55:01.111866 <6>[ 3.024653] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 23:55:01.118716 <6>[ 3.031578] xhci-mtk 11200000.usb: xHCI Host Controller
10638 23:55:01.125472 <6>[ 3.037078] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 23:55:01.135169 <6>[ 3.044942] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 23:55:01.142028 <6>[ 3.054377] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 23:55:01.148657 <6>[ 3.060578] xhci-mtk 11200000.usb: xHCI Host Controller
10642 23:55:01.155305 <6>[ 3.066080] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 23:55:01.161954 <6>[ 3.073738] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 23:55:01.169316 <6>[ 3.081580] hub 1-0:1.0: USB hub found
10645 23:55:01.172652 <6>[ 3.085604] hub 1-0:1.0: 1 port detected
10646 23:55:01.182027 <6>[ 3.089910] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 23:55:01.184999 <6>[ 3.098663] hub 2-0:1.0: USB hub found
10648 23:55:01.188777 <6>[ 3.102679] hub 2-0:1.0: 1 port detected
10649 23:55:01.196919 <6>[ 3.109660] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 23:55:01.209482 <6>[ 3.118647] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 23:55:01.216398 <6>[ 3.126670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10652 23:55:01.225607 <4>[ 3.134586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10653 23:55:01.235430 <6>[ 3.144128] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10654 23:55:01.243164 <6>[ 3.152206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10655 23:55:01.248401 <6>[ 3.160222] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10656 23:55:01.259016 <6>[ 3.168142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10657 23:55:01.265220 <6>[ 3.175960] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10658 23:55:01.275462 <6>[ 3.183779] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10659 23:55:01.285100 <6>[ 3.194183] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 23:55:01.292176 <6>[ 3.202544] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 23:55:01.302183 <6>[ 3.210893] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 23:55:01.308027 <6>[ 3.219232] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 23:55:01.318169 <6>[ 3.227570] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 23:55:01.324803 <6>[ 3.235908] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 23:55:01.334639 <6>[ 3.244254] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 23:55:01.344611 <6>[ 3.252592] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 23:55:01.351020 <6>[ 3.260930] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 23:55:01.361230 <6>[ 3.269267] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 23:55:01.367696 <6>[ 3.277605] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 23:55:01.377554 <6>[ 3.285943] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 23:55:01.384367 <6>[ 3.294283] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 23:55:01.394281 <6>[ 3.302621] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 23:55:01.401173 <6>[ 3.310958] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 23:55:01.407144 <6>[ 3.319695] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 23:55:01.414480 <6>[ 3.326880] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 23:55:01.420596 <6>[ 3.333653] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 23:55:01.430893 <6>[ 3.340407] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 23:55:01.437570 <6>[ 3.347343] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 23:55:01.444750 <6>[ 3.354198] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 23:55:01.454089 <6>[ 3.363330] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 23:55:01.463415 <6>[ 3.372449] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 23:55:01.473535 <6>[ 3.381743] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 23:55:01.483427 <6>[ 3.391211] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 23:55:01.493712 <6>[ 3.400678] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 23:55:01.500920 <6>[ 3.409798] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 23:55:01.510144 <6>[ 3.419264] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 23:55:01.520100 <6>[ 3.428382] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 23:55:01.530845 <6>[ 3.437690] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 23:55:01.539608 <6>[ 3.447851] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 23:55:01.550019 <6>[ 3.459811] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 23:55:01.597562 <6>[ 3.506787] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10692 23:55:01.751835 <6>[ 3.664727] hub 1-1:1.0: USB hub found
10693 23:55:01.755131 <6>[ 3.669266] hub 1-1:1.0: 4 ports detected
10694 23:55:01.764845 <6>[ 3.677869] hub 1-1:1.0: USB hub found
10695 23:55:01.768240 <6>[ 3.682179] hub 1-1:1.0: 4 ports detected
10696 23:55:01.877223 <6>[ 3.787156] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10697 23:55:01.903428 <6>[ 3.816555] hub 2-1:1.0: USB hub found
10698 23:55:01.907180 <6>[ 3.821053] hub 2-1:1.0: 3 ports detected
10699 23:55:01.916127 <6>[ 3.829195] hub 2-1:1.0: USB hub found
10700 23:55:01.919469 <6>[ 3.833644] hub 2-1:1.0: 3 ports detected
10701 23:55:02.092877 <6>[ 4.002835] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10702 23:55:02.225097 <6>[ 4.138099] hub 1-1.4:1.0: USB hub found
10703 23:55:02.228697 <6>[ 4.142663] hub 1-1.4:1.0: 2 ports detected
10704 23:55:02.236587 <6>[ 4.149809] hub 1-1.4:1.0: USB hub found
10705 23:55:02.240333 <6>[ 4.154312] hub 1-1.4:1.0: 2 ports detected
10706 23:55:02.310149 <6>[ 4.218963] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 23:55:02.417696 <6>[ 4.327493] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10708 23:55:02.454098 <4>[ 4.363930] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10709 23:55:02.464634 <4>[ 4.373024] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10710 23:55:02.498864 <6>[ 4.411811] r8152 2-1.3:1.0 eth0: v1.12.13
10711 23:55:02.536737 <6>[ 4.446775] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10712 23:55:02.729143 <6>[ 4.638838] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10713 23:55:04.114617 <6>[ 6.027669] r8152 2-1.3:1.0 eth0: carrier on
10714 23:55:06.621395 <5>[ 6.054649] Sending DHCP requests .., OK
10715 23:55:06.628014 <6>[ 8.538941] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10716 23:55:06.631002 <6>[ 8.547230] IP-Config: Complete:
10717 23:55:06.644126 <6>[ 8.550728] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10718 23:55:06.651377 <6>[ 8.561437] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10719 23:55:06.657650 <6>[ 8.570055] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10720 23:55:06.664137 <6>[ 8.570064] nameserver0=192.168.201.1
10721 23:55:06.667364 <6>[ 8.582243] clk: Disabling unused clocks
10722 23:55:06.670698 <6>[ 8.587750] ALSA device list:
10723 23:55:06.677619 <6>[ 8.591006] No soundcards found.
10724 23:55:06.684973 <6>[ 8.598312] Freeing unused kernel memory: 8512K
10725 23:55:06.687898 <6>[ 8.603301] Run /init as init process
10726 23:55:06.718234 <6>[ 8.631649] NET: Registered PF_INET6 protocol family
10727 23:55:06.725176 <6>[ 8.638368] Segment Routing with IPv6
10728 23:55:06.728308 <6>[ 8.642315] In-situ OAM (IOAM) with IPv6
10729 23:55:06.769430 <30>[ 8.656306] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10730 23:55:06.775871 <30>[ 8.689516] systemd[1]: Detected architecture arm64.
10731 23:55:06.776019
10732 23:55:06.782920 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10733 23:55:06.783061
10734 23:55:06.797997 <30>[ 8.710903] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10735 23:55:06.927847 <30>[ 8.837439] systemd[1]: Queued start job for default target graphical.target.
10736 23:55:06.974433 <30>[ 8.884508] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10737 23:55:06.980875 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10738 23:55:07.001503 <30>[ 8.911307] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10739 23:55:07.011271 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10740 23:55:07.030182 <30>[ 8.939669] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10741 23:55:07.040044 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10742 23:55:07.058132 <30>[ 8.968347] systemd[1]: Created slice user.slice - User and Session Slice.
10743 23:55:07.064852 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10744 23:55:07.088450 <30>[ 8.995573] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10745 23:55:07.098496 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10746 23:55:07.116341 <30>[ 9.023007] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10747 23:55:07.122736 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10748 23:55:07.150433 <30>[ 9.051012] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10749 23:55:07.160483 <30>[ 9.070843] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10750 23:55:07.167135 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10751 23:55:07.185779 <30>[ 9.095266] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10752 23:55:07.195761 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10753 23:55:07.213185 <30>[ 9.123298] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10754 23:55:07.222787 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10755 23:55:07.237497 <30>[ 9.151371] systemd[1]: Reached target paths.target - Path Units.
10756 23:55:07.247548 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10757 23:55:07.265082 <30>[ 9.175278] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10758 23:55:07.271963 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10759 23:55:07.285606 <30>[ 9.198952] systemd[1]: Reached target slices.target - Slice Units.
10760 23:55:07.295336 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10761 23:55:07.309539 <30>[ 9.222908] systemd[1]: Reached target swap.target - Swaps.
10762 23:55:07.316010 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10763 23:55:07.337055 <30>[ 9.247350] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10764 23:55:07.347913 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10765 23:55:07.365152 <30>[ 9.275783] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10766 23:55:07.375362 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10767 23:55:07.394395 <30>[ 9.304847] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10768 23:55:07.404580 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10769 23:55:07.421206 <30>[ 9.331481] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10770 23:55:07.431644 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10771 23:55:07.449062 <30>[ 9.359480] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10772 23:55:07.455637 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10773 23:55:07.473127 <30>[ 9.383497] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10774 23:55:07.482768 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10775 23:55:07.501861 <30>[ 9.412252] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10776 23:55:07.511585 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10777 23:55:07.529730 <30>[ 9.439939] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10778 23:55:07.539507 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10779 23:55:07.588786 <30>[ 9.499033] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10780 23:55:07.595484 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10781 23:55:07.616803 <30>[ 9.527021] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10782 23:55:07.623152 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10783 23:55:07.644985 <30>[ 9.555177] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10784 23:55:07.651905 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10785 23:55:07.680024 <30>[ 9.583333] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10786 23:55:07.712658 <30>[ 9.623063] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10787 23:55:07.722242 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10788 23:55:07.746042 <30>[ 9.655904] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10789 23:55:07.752505 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10790 23:55:07.777335 <30>[ 9.687447] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10791 23:55:07.790337 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 9.701056] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10792 23:55:07.793687 Module dm_mod...
10793 23:55:07.817000 <30>[ 9.727333] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10794 23:55:07.823356 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10795 23:55:07.845483 <30>[ 9.755605] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10796 23:55:07.855266 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10797 23:55:07.878007 <30>[ 9.788132] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10798 23:55:07.884157 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10799 23:55:07.913770 <30>[ 9.823694] systemd[1]: Starting systemd-journald.service - Journal Service...
10800 23:55:07.920060 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10801 23:55:07.939451 <30>[ 9.849566] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10802 23:55:07.945908 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10803 23:55:07.970984 <30>[ 9.877868] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10804 23:55:07.977221 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10805 23:55:08.000553 <30>[ 9.911074] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10806 23:55:08.010661 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10807 23:55:08.031588 <30>[ 9.941809] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10808 23:55:08.037930 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10809 23:55:08.061595 <30>[ 9.971948] systemd[1]: Started systemd-journald.service - Journal Service.
10810 23:55:08.068823 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10811 23:55:08.087637 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10812 23:55:08.105332 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10813 23:55:08.125606 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10814 23:55:08.145996 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10815 23:55:08.166465 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10816 23:55:08.186722 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10817 23:55:08.207033 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10818 23:55:08.231303 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10819 23:55:08.253835 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10820 23:55:08.274453 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10821 23:55:08.293808 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10822 23:55:08.314777 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10823 23:55:08.329458 See 'systemctl status systemd-remount-fs.service' for details.
10824 23:55:08.339758 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10825 23:55:08.359235 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10826 23:55:08.429113 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10827 23:55:08.453868 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10828 23:55:08.464819 <46>[ 10.375553] systemd-journald[197]: Received client request to flush runtime journal.
10829 23:55:08.479354 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10830 23:55:08.502427 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10831 23:55:08.525896 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10832 23:55:08.559206 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10833 23:55:08.581775 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10834 23:55:08.606030 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10835 23:55:08.625576 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10836 23:55:08.645739 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10837 23:55:08.705744 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10838 23:55:08.731165 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10839 23:55:08.748996 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10840 23:55:08.768644 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10841 23:55:08.790060 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10842 23:55:08.814679 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10843 23:55:08.839226 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10844 23:55:08.872281 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10845 23:55:08.901937 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10846 23:55:08.923485 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10847 23:55:08.993754 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10848 23:55:09.016394 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10849 23:55:09.026404 <46>[ 10.939630] systemd-journald[197]: Time jumped backwards, rotating.
10850 23:55:09.042910 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10851 23:55:09.148307 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10852 23:55:09.165668 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10853 23:55:09.184848 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10854 23:55:09.206058 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10855 23:55:09.224776 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10856 23:55:09.236507 <6>[ 11.147190] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10857 23:55:09.246504 <6>[ 11.155210] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10858 23:55:09.253150 <6>[ 11.159314] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10859 23:55:09.259568 <6>[ 11.164211] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10860 23:55:09.270154 <3>[ 11.177986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10861 23:55:09.276151 <6>[ 11.188625] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10862 23:55:09.283254 [[0;32m OK [<6>[ 11.189131] remoteproc remoteproc0: scp is available
10863 23:55:09.292758 0m] Listening on<4>[ 11.189380] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10864 23:55:09.299686 <4>[ 11.189522] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10865 23:55:09.309395 [0;1;39mdbus.s<3>[ 11.189627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10866 23:55:09.320269 <3>[ 11.189638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 23:55:09.325650 ocket[…- D-Bu<3>[ 11.189687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10868 23:55:09.335881 <3>[ 11.189690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 23:55:09.342405 <3>[ 11.189694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 23:55:09.352137 <3>[ 11.189699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 23:55:09.359675 s System Message<3>[ 11.189701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 23:55:09.362959 Bus Socket.
10873 23:55:09.370585 <3>[ 11.189722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 23:55:09.379752 <3>[ 11.189755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 23:55:09.386296 <3>[ 11.189758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 23:55:09.393052 <3>[ 11.189761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 23:55:09.403179 <3>[ 11.189783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10878 23:55:09.409556 <3>[ 11.189787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10879 23:55:09.419285 <3>[ 11.189789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 23:55:09.427173 <3>[ 11.189792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 23:55:09.435818 <3>[ 11.189795] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 23:55:09.442432 <3>[ 11.190318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 23:55:09.452493 <4>[ 11.253177] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10884 23:55:09.456057 <4>[ 11.253177] Fallback method does not support PEC.
10885 23:55:09.462672 <6>[ 11.254672] remoteproc remoteproc0: powering up scp
10886 23:55:09.469301 <3>[ 11.277898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 23:55:09.478997 <6>[ 11.280346] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10888 23:55:09.489303 <3>[ 11.312382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 23:55:09.492317 <6>[ 11.313492] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10890 23:55:09.498806 <6>[ 11.332493] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10891 23:55:09.506034 <6>[ 11.357673] mc: Linux media interface: v0.10
10892 23:55:09.515517 <6>[ 11.358613] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10893 23:55:09.518809 <6>[ 11.362102] pci_bus 0000:00: root bus resource [bus 00-ff]
10894 23:55:09.525237 <6>[ 11.408865] videodev: Linux video capture interface: v2.00
10895 23:55:09.532950 <6>[ 11.412714] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10896 23:55:09.542758 <6>[ 11.421451] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10897 23:55:09.552909 <6>[ 11.424097] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10898 23:55:09.559175 <6>[ 11.424151] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10899 23:55:09.569146 <6>[ 11.439420] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10900 23:55:09.576334 <6>[ 11.445565] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10901 23:55:09.585656 <3>[ 11.460696] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 23:55:09.588802 <6>[ 11.462274] pci 0000:00:00.0: supports D1 D2
10903 23:55:09.600008 <6>[ 11.463298] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10904 23:55:09.606542 <6>[ 11.463303] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10905 23:55:09.609881 <6>[ 11.463306] remoteproc remoteproc0: remote processor scp is now up
10906 23:55:09.619719 <6>[ 11.510279] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10907 23:55:09.626670 <6>[ 11.516622] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10908 23:55:09.633505 <6>[ 11.518024] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10909 23:55:09.644252 <3>[ 11.523065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 23:55:09.650765 <3>[ 11.523826] power_supply sbs-5-000b: driver failed to report `health' property: -6
10911 23:55:09.655099 <6>[ 11.524485] Bluetooth: Core ver 2.22
10912 23:55:09.660959 <6>[ 11.524593] NET: Registered PF_BLUETOOTH protocol family
10913 23:55:09.668033 <6>[ 11.524596] Bluetooth: HCI device and connection manager initialized
10914 23:55:09.674990 <6>[ 11.524634] Bluetooth: HCI socket layer initialized
10915 23:55:09.677588 <6>[ 11.524663] Bluetooth: L2CAP socket layer initialized
10916 23:55:09.684881 <6>[ 11.524701] Bluetooth: SCO socket layer initialized
10917 23:55:09.687897 <6>[ 11.530433] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10918 23:55:09.697983 <6>[ 11.539632] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10919 23:55:09.704468 <6>[ 11.545415] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10920 23:55:09.711259 <6>[ 11.554711] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10921 23:55:09.724477 <6>[ 11.555142] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10922 23:55:09.731568 <6>[ 11.555308] usbcore: registered new interface driver uvcvideo
10923 23:55:09.737986 <3>[ 11.556587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 23:55:09.748278 <6>[ 11.562451] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10925 23:55:09.755277 <6>[ 11.562471] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10926 23:55:09.761421 <3>[ 11.573043] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 23:55:09.768602 <6>[ 11.574224] pci 0000:01:00.0: supports D1 D2
10928 23:55:09.775386 <6>[ 11.575348] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10929 23:55:09.778429 <6>[ 11.586885] usbcore: registered new interface driver btusb
10930 23:55:09.788784 <4>[ 11.587887] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10931 23:55:09.795289 <3>[ 11.587894] Bluetooth: hci0: Failed to load firmware file (-2)
10932 23:55:09.802982 <3>[ 11.587897] Bluetooth: hci0: Failed to set up firmware (-2)
10933 23:55:09.812914 <4>[ 11.587899] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10934 23:55:09.819422 <6>[ 11.591385] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10935 23:55:09.830288 <3>[ 11.601491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 23:55:09.836109 <6>[ 11.610701] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10937 23:55:09.843382 <3>[ 11.636052] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 23:55:09.850522 <6>[ 11.643363] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10939 23:55:09.860268 <3>[ 11.671300] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 23:55:09.870691 <6>[ 11.673055] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10941 23:55:09.876703 <6>[ 11.787515] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10942 23:55:09.883323 <6>[ 11.787528] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10943 23:55:09.893077 <6>[ 11.787541] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10944 23:55:09.896484 <6>[ 11.787553] pci 0000:00:00.0: PCI bridge to [bus 01]
10945 23:55:09.906450 <6>[ 11.787557] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10946 23:55:09.913088 <6>[ 11.787708] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10947 23:55:09.920384 [[0;32m OK [<6>[ 11.831733] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10948 23:55:09.926148 0m] Reached targ<6>[ 11.839499] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10949 23:55:09.932817 et [0;1;39msockets.target[0m - Socket Units.
10950 23:55:09.950682 <5>[ 11.860765] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10951 23:55:09.969064 <5>[ 11.879745] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10952 23:55:09.979160 Startin<5>[ 11.887243] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10953 23:55:09.988630 g [0;1;39msyste<4>[ 11.896870] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10954 23:55:09.995662 md-networkd.…i<6>[ 11.907063] cfg80211: failed to load regulatory.db
10955 23:55:09.998911 ce[0m - Network Configuration...
10956 23:55:10.016829 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10957 23:55:10.051686 <6>[ 11.961954] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10958 23:55:10.057713 <6>[ 11.969526] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10959 23:55:10.070507 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10960 23:55:10.082175 <6>[ 11.996284] mt7921e 0000:01:00.0: ASIC revision: 79610010
10961 23:55:10.106336 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10962 23:55:10.125780 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10963 23:55:10.145010 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10964 23:55:10.191237 <6>[ 12.102131] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10965 23:55:10.194582 <6>[ 12.102131]
10966 23:55:10.213919 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10967 23:55:10.235014 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10968 23:55:10.252771 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10969 23:55:10.266265 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10970 23:55:10.289670 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10971 23:55:10.346040 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10972 23:55:10.370598 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10973 23:55:10.394425 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10974 23:55:10.415733 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10975 23:55:10.466383 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10976 23:55:10.476267 <6>[ 12.385355] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10977 23:55:10.510281 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10978 23:55:10.529581 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10979 23:55:10.544922 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10980 23:55:10.565557 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10981 23:55:10.610439 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10982 23:55:10.635187 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10983 23:55:10.657292 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10984 23:55:10.698147 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10985 23:55:10.734070
10986 23:55:10.737548 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10987 23:55:10.737647
10988 23:55:10.740530 debian-bookworm-arm64 login: root (automatic login)
10989 23:55:10.740616
10990 23:55:10.752999 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
10991 23:55:10.753140
10992 23:55:10.759686 The programs included with the Debian GNU/Linux system are free software;
10993 23:55:10.766235 the exact distribution terms for each program are described in the
10994 23:55:10.769247 individual files in /usr/share/doc/*/copyright.
10995 23:55:10.769417
10996 23:55:10.775819 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10997 23:55:10.779016 permitted by applicable law.
10998 23:55:10.779524 Matched prompt #10: / #
11000 23:55:10.779734 Setting prompt string to ['/ #']
11001 23:55:10.779827 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11003 23:55:10.780057 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11004 23:55:10.780148 start: 2.2.6 expect-shell-connection (timeout 00:03:07) [common]
11005 23:55:10.780220 Setting prompt string to ['/ #']
11006 23:55:10.780280 Forcing a shell prompt, looking for ['/ #']
11008 23:55:10.830518 / #
11009 23:55:10.830699 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11010 23:55:10.830787 Waiting using forced prompt support (timeout 00:02:30)
11011 23:55:10.836191
11012 23:55:10.836491 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11013 23:55:10.836593 start: 2.2.7 export-device-env (timeout 00:03:07) [common]
11014 23:55:10.836684 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11015 23:55:10.836773 end: 2.2 depthcharge-retry (duration 00:01:53) [common]
11016 23:55:10.836861 end: 2 depthcharge-action (duration 00:01:53) [common]
11017 23:55:10.836948 start: 3 lava-test-retry (timeout 00:07:45) [common]
11018 23:55:10.837032 start: 3.1 lava-test-shell (timeout 00:07:45) [common]
11019 23:55:10.837108 Using namespace: common
11021 23:55:10.937486 / # #
11022 23:55:10.937667 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11023 23:55:10.942797 #
11024 23:55:10.943081 Using /lava-14084359
11026 23:55:11.043488 / # export SHELL=/bin/sh
11027 23:55:11.048927 export SHELL=/bin/sh
11029 23:55:11.149527 / # . /lava-14084359/environment
11030 23:55:11.155018 . /lava-14084359/environment
11032 23:55:11.255596 / # /lava-14084359/bin/lava-test-runner /lava-14084359/0
11033 23:55:11.255772 Test shell timeout: 10s (minimum of the action and connection timeout)
11034 23:55:11.261328 /lava-14084359/bin/lava-test-runner /lava-14084359/0
11035 23:55:11.283586 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11036 23:55:11.289681 + cd /lava-14084359/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11037 23:55:11.289799 + cat uuid
11038 23:55:11.292849 + UUID=14084359_1.5.2.3.1
11039 23:55:11.292933 + set +x
11040 23:55:11.299346 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14084359_1.5.2.3.1>
11041 23:55:11.299662 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14084359_1.5.2.3.1
11042 23:55:11.299774 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14084359_1.5.2.3.1)
11043 23:55:11.299891 Skipping test definition patterns.
11044 23:55:11.302387 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11045 23:55:11.309097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11046 23:55:11.309224 device: /dev/video2
11047 23:55:11.309539 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11049 23:55:11.321628 <4>[ 13.232261] use of bytesused == 0 is deprecated and will be removed in the future,
11050 23:55:11.325026 <4>[ 13.240117] use the actual size instead.
11051 23:55:11.331374 <6>[ 13.242884] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11052 23:55:11.340866 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11053 23:55:11.350323 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11054 23:55:11.357088
11055 23:55:11.371224 Compliance test for mtk-vcodec-enc device /dev/video2:
11056 23:55:11.377875
11057 23:55:11.388088 Driver Info:
11058 23:55:11.399405 Driver name : mtk-vcodec-enc
11059 23:55:11.412939 Card type : MT8192 video encoder
11060 23:55:11.421239 Bus info : platform:17020000.vcodec
11061 23:55:11.432236 Driver version : 6.1.91
11062 23:55:11.441507 Capabilities : 0x84204000
11063 23:55:11.451296 Video Memory-to-Memory Multiplanar
11064 23:55:11.461483 Streaming
11065 23:55:11.471406 Extended Pix Format
11066 23:55:11.481634 Device Capabilities
11067 23:55:11.491807 Device Caps : 0x04204000
11068 23:55:11.506756 Video Memory-to-Memory Multiplanar
11069 23:55:11.518273 Streaming
11070 23:55:11.527922 Extended Pix Format
11071 23:55:11.538226 Detected Stateful Encoder
11072 23:55:11.549452
11073 23:55:11.559177 Required ioctls:
11074 23:55:11.577949 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11075 23:55:11.578137 test VIDIOC_QUERYCAP: OK
11076 23:55:11.578425 Received signal: <TESTSET> START Required-ioctls
11077 23:55:11.578531 Starting test_set Required-ioctls
11078 23:55:11.601670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11079 23:55:11.602041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11081 23:55:11.605160 test invalid ioctls: OK
11082 23:55:11.625658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11083 23:55:11.625844
11084 23:55:11.626125 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11086 23:55:11.639402 Allow for multiple opens:
11087 23:55:11.646441 <LAVA_SIGNAL_TESTSET STOP>
11088 23:55:11.646783 Received signal: <TESTSET> STOP
11089 23:55:11.646895 Closing test_set Required-ioctls
11090 23:55:11.655584 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11091 23:55:11.655916 Received signal: <TESTSET> START Allow-for-multiple-opens
11092 23:55:11.656026 Starting test_set Allow-for-multiple-opens
11093 23:55:11.659014 test second /dev/video2 open: OK
11094 23:55:11.680456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11095 23:55:11.680828 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11097 23:55:11.683216 test VIDIOC_QUERYCAP: OK
11098 23:55:11.705048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11099 23:55:11.705420 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11101 23:55:11.707998 test VIDIOC_G/S_PRIORITY: OK
11102 23:55:11.728214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11103 23:55:11.728581 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11105 23:55:11.731256 test for unlimited opens: OK
11106 23:55:11.752262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11107 23:55:11.752451
11108 23:55:11.752734 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11110 23:55:11.763621 Debug ioctls:
11111 23:55:11.776060 <LAVA_SIGNAL_TESTSET STOP>
11112 23:55:11.776439 Received signal: <TESTSET> STOP
11113 23:55:11.776549 Closing test_set Allow-for-multiple-opens
11114 23:55:11.784382 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11115 23:55:11.784698 Received signal: <TESTSET> START Debug-ioctls
11116 23:55:11.784804 Starting test_set Debug-ioctls
11117 23:55:11.787879 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11118 23:55:11.809668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11119 23:55:11.810039 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11121 23:55:11.816118 test VIDIOC_LOG_STATUS: OK (Not Supported)
11122 23:55:11.834821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11123 23:55:11.835008
11124 23:55:11.835291 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11126 23:55:11.849853 Input ioctls:
11127 23:55:11.857014 <LAVA_SIGNAL_TESTSET STOP>
11128 23:55:11.857362 Received signal: <TESTSET> STOP
11129 23:55:11.857472 Closing test_set Debug-ioctls
11130 23:55:11.866140 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11131 23:55:11.866489 Received signal: <TESTSET> START Input-ioctls
11132 23:55:11.866602 Starting test_set Input-ioctls
11133 23:55:11.869280 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11134 23:55:11.894943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11135 23:55:11.895317 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11137 23:55:11.898085 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11138 23:55:11.916887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11139 23:55:11.917248 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11141 23:55:11.923777 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11142 23:55:11.946049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11143 23:55:11.946416 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11145 23:55:11.951931 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11146 23:55:11.969630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11147 23:55:11.969996 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11149 23:55:11.972666 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11150 23:55:11.995284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11151 23:55:11.995653 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11153 23:55:11.998787 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11154 23:55:12.019245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11155 23:55:12.019608 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11157 23:55:12.022403 Inputs: 0 Audio Inputs: 0 Tuners: 0
11158 23:55:12.034077
11159 23:55:12.054477 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11160 23:55:12.076971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11161 23:55:12.077329 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11163 23:55:12.083555 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11164 23:55:12.106646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11165 23:55:12.107013 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11167 23:55:12.112875 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11168 23:55:12.130034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11169 23:55:12.130398 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11171 23:55:12.136529 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11172 23:55:12.153747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11173 23:55:12.154108 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11175 23:55:12.160276 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11176 23:55:12.179035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11177 23:55:12.179207
11178 23:55:12.179488 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11180 23:55:12.200963 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11181 23:55:12.225963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11182 23:55:12.226327 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11184 23:55:12.232278 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11185 23:55:12.253367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11186 23:55:12.253715 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11188 23:55:12.256080 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11189 23:55:12.276181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11190 23:55:12.276530 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11192 23:55:12.278928 test VIDIOC_G/S_EDID: OK (Not Supported)
11193 23:55:12.305190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11194 23:55:12.305403
11195 23:55:12.305684 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11197 23:55:12.315643 Control ioctls:
11198 23:55:12.322384 <LAVA_SIGNAL_TESTSET STOP>
11199 23:55:12.322698 Received signal: <TESTSET> STOP
11200 23:55:12.322803 Closing test_set Input-ioctls
11201 23:55:12.332050 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11202 23:55:12.332354 Received signal: <TESTSET> START Control-ioctls
11203 23:55:12.332460 Starting test_set Control-ioctls
11204 23:55:12.335108 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11205 23:55:12.362662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11206 23:55:12.362836 test VIDIOC_QUERYCTRL: OK
11207 23:55:12.363114 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11209 23:55:12.384108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11210 23:55:12.384472 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11212 23:55:12.387731 test VIDIOC_G/S_CTRL: OK
11213 23:55:12.407980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11214 23:55:12.408343 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11216 23:55:12.411672 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11217 23:55:12.431862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11218 23:55:12.432225 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11220 23:55:12.438003 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11221 23:55:12.446123 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11222 23:55:12.474660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11223 23:55:12.475034 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11225 23:55:12.478464 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11226 23:55:12.497147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11227 23:55:12.497532 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11229 23:55:12.500797 Standard Controls: 16 Private Controls: 0
11230 23:55:12.507538
11231 23:55:12.518379 Format ioctls:
11232 23:55:12.525870 <LAVA_SIGNAL_TESTSET STOP>
11233 23:55:12.526154 Received signal: <TESTSET> STOP
11234 23:55:12.526227 Closing test_set Control-ioctls
11235 23:55:12.534994 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11236 23:55:12.535257 Received signal: <TESTSET> START Format-ioctls
11237 23:55:12.535326 Starting test_set Format-ioctls
11238 23:55:12.538262 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11239 23:55:12.562173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11240 23:55:12.562488 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11242 23:55:12.565135 test VIDIOC_G/S_PARM: OK
11243 23:55:12.583496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11244 23:55:12.583849 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11246 23:55:12.586226 test VIDIOC_G_FBUF: OK (Not Supported)
11247 23:55:12.607456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11248 23:55:12.607815 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11250 23:55:12.611387 test VIDIOC_G_FMT: OK
11251 23:55:12.631816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11252 23:55:12.632174 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11254 23:55:12.634716 test VIDIOC_TRY_FMT: OK
11255 23:55:12.655290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11256 23:55:12.655617 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11258 23:55:12.662267 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11259 23:55:12.667574 test VIDIOC_S_FMT: FAIL
11260 23:55:12.696063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11261 23:55:12.696429 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11263 23:55:12.698921 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11264 23:55:12.725634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11265 23:55:12.726072 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11267 23:55:12.728933 test Cropping: OK
11268 23:55:12.748637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11269 23:55:12.748989 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11271 23:55:12.752006 test Composing: OK (Not Supported)
11272 23:55:12.774151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11273 23:55:12.774510 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11275 23:55:12.776998 test Scaling: OK (Not Supported)
11276 23:55:12.805996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11277 23:55:12.806181
11278 23:55:12.806462 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11280 23:55:12.815847 Codec ioctls:
11281 23:55:12.823534 <LAVA_SIGNAL_TESTSET STOP>
11282 23:55:12.823857 Received signal: <TESTSET> STOP
11283 23:55:12.823963 Closing test_set Format-ioctls
11284 23:55:12.832785 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11285 23:55:12.833095 Received signal: <TESTSET> START Codec-ioctls
11286 23:55:12.833198 Starting test_set Codec-ioctls
11287 23:55:12.836162 test VIDIOC_(TRY_)ENCODER_CMD: OK
11288 23:55:12.858321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11289 23:55:12.858676 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11291 23:55:12.865432 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11292 23:55:12.883857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11293 23:55:12.884212 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11295 23:55:12.890011 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11296 23:55:12.907436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11297 23:55:12.907598
11298 23:55:12.907873 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11300 23:55:12.918906 Buffer ioctls:
11301 23:55:12.926871 <LAVA_SIGNAL_TESTSET STOP>
11302 23:55:12.927180 Received signal: <TESTSET> STOP
11303 23:55:12.927282 Closing test_set Codec-ioctls
11304 23:55:12.936281 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11305 23:55:12.936602 Received signal: <TESTSET> START Buffer-ioctls
11306 23:55:12.936705 Starting test_set Buffer-ioctls
11307 23:55:12.939949 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11308 23:55:12.967075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11309 23:55:12.967475 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11311 23:55:12.970172 test CREATE_BUFS maximum buffers: OK
11312 23:55:12.989716 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11314 23:55:12.992813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11315 23:55:12.992924 test VIDIOC_EXPBUF: OK
11316 23:55:13.014223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11317 23:55:13.014582 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11319 23:55:13.017840 test Requests: OK (Not Supported)
11320 23:55:13.038373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11321 23:55:13.038557
11322 23:55:13.038840 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11324 23:55:13.053090 Test input 0:
11325 23:55:13.068185
11326 23:55:13.078986 Streaming ioctls:
11327 23:55:13.088508 <LAVA_SIGNAL_TESTSET STOP>
11328 23:55:13.088864 Received signal: <TESTSET> STOP
11329 23:55:13.088973 Closing test_set Buffer-ioctls
11330 23:55:13.098955 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11331 23:55:13.099277 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11332 23:55:13.099383 Starting test_set Streaming-ioctls_Test-input-0
11333 23:55:13.102788 test read/write: OK (Not Supported)
11334 23:55:13.124857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11335 23:55:13.125225 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11337 23:55:13.132037 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11338 23:55:13.138226 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11339 23:55:13.146510 test blocking wait: FAIL
11340 23:55:13.171121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11341 23:55:13.171491 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11343 23:55:13.177400 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11344 23:55:13.183418 test MMAP (select): FAIL
11345 23:55:13.211113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11346 23:55:13.211475 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11348 23:55:13.217570 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11349 23:55:13.221749 test MMAP (epoll): FAIL
11350 23:55:13.246416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11351 23:55:13.246777 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11353 23:55:13.252683 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11354 23:55:13.260414 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11355 23:55:13.284659 test USERPTR (select): FAIL
11356 23:55:13.311069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11357 23:55:13.311430 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11359 23:55:13.317704 test DMABUF: Cannot test, specify --expbuf-device
11360 23:55:13.322340
11361 23:55:13.340233 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11362 23:55:13.343716 <LAVA_TEST_RUNNER EXIT>
11363 23:55:13.344024 ok: lava_test_shell seems to have completed
11364 23:55:13.344133 Marking unfinished test run as failed
11366 23:55:13.345724 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11367 23:55:13.345908 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11368 23:55:13.346032 end: 3 lava-test-retry (duration 00:00:03) [common]
11369 23:55:13.346155 start: 4 finalize (timeout 00:07:43) [common]
11370 23:55:13.346282 start: 4.1 power-off (timeout 00:00:30) [common]
11371 23:55:13.346524 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11372 23:55:13.546290 >> Command sent successfully.
11373 23:55:13.548598 Returned 0 in 0 seconds
11374 23:55:13.649094 end: 4.1 power-off (duration 00:00:00) [common]
11376 23:55:13.649589 start: 4.2 read-feedback (timeout 00:07:42) [common]
11377 23:55:13.649921 Listened to connection for namespace 'common' for up to 1s
11378 23:55:14.650857 Finalising connection for namespace 'common'
11379 23:55:14.651047 Disconnecting from shell: Finalise
11380 23:55:14.651124 / #
11381 23:55:14.751479 end: 4.2 read-feedback (duration 00:00:01) [common]
11382 23:55:14.751659 end: 4 finalize (duration 00:00:01) [common]
11383 23:55:14.751773 Cleaning after the job
11384 23:55:14.751874 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/ramdisk
11385 23:55:14.756428 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/kernel
11386 23:55:14.769556 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/dtb
11387 23:55:14.769984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084359/tftp-deploy-z1crv513/modules
11388 23:55:14.775419 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084359
11389 23:55:14.837054 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084359
11390 23:55:14.837236 Job finished correctly