Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 23:54:13.936809 lava-dispatcher, installed at version: 2024.03
2 23:54:13.937030 start: 0 validate
3 23:54:13.937170 Start time: 2024-05-29 23:54:13.937163+00:00 (UTC)
4 23:54:13.937295 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:54:13.937431 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:54:14.210704 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:54:14.210874 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:54:14.471442 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:54:14.471795 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:54:14.730297 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:54:14.730451 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.91-cip21-33-g9433716496158%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:54:14.997108 validate duration: 1.06
14 23:54:14.997389 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:54:14.997505 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:54:14.997613 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:54:14.997744 Not decompressing ramdisk as can be used compressed.
18 23:54:14.997827 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 23:54:14.997890 saving as /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/ramdisk/rootfs.cpio.gz
20 23:54:14.997954 total size: 28105535 (26 MB)
21 23:54:14.999082 progress 0 % (0 MB)
22 23:54:15.006869 progress 5 % (1 MB)
23 23:54:15.014279 progress 10 % (2 MB)
24 23:54:15.021786 progress 15 % (4 MB)
25 23:54:15.029739 progress 20 % (5 MB)
26 23:54:15.037517 progress 25 % (6 MB)
27 23:54:15.045669 progress 30 % (8 MB)
28 23:54:15.053264 progress 35 % (9 MB)
29 23:54:15.060883 progress 40 % (10 MB)
30 23:54:15.068214 progress 45 % (12 MB)
31 23:54:15.075878 progress 50 % (13 MB)
32 23:54:15.083689 progress 55 % (14 MB)
33 23:54:15.091177 progress 60 % (16 MB)
34 23:54:15.098622 progress 65 % (17 MB)
35 23:54:15.106091 progress 70 % (18 MB)
36 23:54:15.113540 progress 75 % (20 MB)
37 23:54:15.121132 progress 80 % (21 MB)
38 23:54:15.128686 progress 85 % (22 MB)
39 23:54:15.135823 progress 90 % (24 MB)
40 23:54:15.143385 progress 95 % (25 MB)
41 23:54:15.150760 progress 100 % (26 MB)
42 23:54:15.150990 26 MB downloaded in 0.15 s (175.15 MB/s)
43 23:54:15.151145 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:54:15.151389 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:54:15.151476 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:54:15.151561 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:54:15.151713 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:54:15.151785 saving as /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/kernel/Image
50 23:54:15.151850 total size: 54682112 (52 MB)
51 23:54:15.151913 No compression specified
52 23:54:15.153158 progress 0 % (0 MB)
53 23:54:15.167489 progress 5 % (2 MB)
54 23:54:15.181732 progress 10 % (5 MB)
55 23:54:15.196414 progress 15 % (7 MB)
56 23:54:15.210821 progress 20 % (10 MB)
57 23:54:15.225163 progress 25 % (13 MB)
58 23:54:15.239779 progress 30 % (15 MB)
59 23:54:15.254206 progress 35 % (18 MB)
60 23:54:15.268273 progress 40 % (20 MB)
61 23:54:15.282357 progress 45 % (23 MB)
62 23:54:15.296550 progress 50 % (26 MB)
63 23:54:15.310744 progress 55 % (28 MB)
64 23:54:15.325133 progress 60 % (31 MB)
65 23:54:15.339058 progress 65 % (33 MB)
66 23:54:15.353451 progress 70 % (36 MB)
67 23:54:15.367486 progress 75 % (39 MB)
68 23:54:15.381560 progress 80 % (41 MB)
69 23:54:15.395483 progress 85 % (44 MB)
70 23:54:15.409283 progress 90 % (46 MB)
71 23:54:15.423066 progress 95 % (49 MB)
72 23:54:15.436843 progress 100 % (52 MB)
73 23:54:15.437119 52 MB downloaded in 0.29 s (182.81 MB/s)
74 23:54:15.437271 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:54:15.437508 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:54:15.437597 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:54:15.437681 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:54:15.437818 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:54:15.437916 saving as /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/dtb/mt8192-asurada-spherion-r0.dtb
81 23:54:15.437993 total size: 47258 (0 MB)
82 23:54:15.438055 No compression specified
83 23:54:15.439465 progress 69 % (0 MB)
84 23:54:15.439828 progress 100 % (0 MB)
85 23:54:15.439987 0 MB downloaded in 0.00 s (22.64 MB/s)
86 23:54:15.440111 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:54:15.440331 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:54:15.440416 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:54:15.440498 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:54:15.440613 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.91-cip21-33-g9433716496158/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:54:15.440679 saving as /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/modules/modules.tar
93 23:54:15.440738 total size: 8601444 (8 MB)
94 23:54:15.440799 Using unxz to decompress xz
95 23:54:15.445087 progress 0 % (0 MB)
96 23:54:15.464887 progress 5 % (0 MB)
97 23:54:15.488923 progress 10 % (0 MB)
98 23:54:15.514234 progress 15 % (1 MB)
99 23:54:15.538966 progress 20 % (1 MB)
100 23:54:15.564775 progress 25 % (2 MB)
101 23:54:15.590496 progress 30 % (2 MB)
102 23:54:15.614201 progress 35 % (2 MB)
103 23:54:15.638589 progress 40 % (3 MB)
104 23:54:15.665383 progress 45 % (3 MB)
105 23:54:15.689612 progress 50 % (4 MB)
106 23:54:15.714881 progress 55 % (4 MB)
107 23:54:15.739616 progress 60 % (4 MB)
108 23:54:15.763786 progress 65 % (5 MB)
109 23:54:15.790085 progress 70 % (5 MB)
110 23:54:15.815232 progress 75 % (6 MB)
111 23:54:15.839657 progress 80 % (6 MB)
112 23:54:15.865457 progress 85 % (7 MB)
113 23:54:15.889097 progress 90 % (7 MB)
114 23:54:15.918685 progress 95 % (7 MB)
115 23:54:15.947245 progress 100 % (8 MB)
116 23:54:15.952812 8 MB downloaded in 0.51 s (16.02 MB/s)
117 23:54:15.953122 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:54:15.953416 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:54:15.953525 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:54:15.953632 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:54:15.953727 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:54:15.953861 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:54:15.954137 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm
125 23:54:15.954309 makedir: /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin
126 23:54:15.954451 makedir: /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/tests
127 23:54:15.954563 makedir: /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/results
128 23:54:15.954690 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-add-keys
129 23:54:15.954848 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-add-sources
130 23:54:15.954996 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-background-process-start
131 23:54:15.955172 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-background-process-stop
132 23:54:15.955314 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-common-functions
133 23:54:15.955458 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-echo-ipv4
134 23:54:15.955627 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-install-packages
135 23:54:15.955793 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-installed-packages
136 23:54:15.955933 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-os-build
137 23:54:15.956074 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-probe-channel
138 23:54:15.956213 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-probe-ip
139 23:54:15.956356 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-target-ip
140 23:54:15.956523 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-target-mac
141 23:54:15.956694 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-target-storage
142 23:54:15.956867 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-case
143 23:54:15.957079 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-event
144 23:54:15.957247 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-feedback
145 23:54:15.957414 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-raise
146 23:54:15.957580 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-reference
147 23:54:15.957747 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-runner
148 23:54:15.957914 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-set
149 23:54:15.958086 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-test-shell
150 23:54:15.958258 Updating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-install-packages (oe)
151 23:54:15.958456 Updating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/bin/lava-installed-packages (oe)
152 23:54:15.958623 Creating /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/environment
153 23:54:15.958765 LAVA metadata
154 23:54:15.958872 - LAVA_JOB_ID=14084372
155 23:54:15.958973 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:54:15.959125 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:54:15.959225 skipped lava-vland-overlay
158 23:54:15.959343 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:54:15.959467 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:54:15.959573 skipped lava-multinode-overlay
161 23:54:15.959690 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:54:15.959816 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:54:15.959928 Loading test definitions
164 23:54:15.960063 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:54:15.960174 Using /lava-14084372 at stage 0
166 23:54:15.960592 uuid=14084372_1.5.2.3.1 testdef=None
167 23:54:15.960748 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:54:15.960875 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:54:15.961628 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:54:15.961994 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:54:15.962885 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:54:15.963266 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:54:15.964116 runner path: /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/0/tests/0_v4l2-compliance-uvc test_uuid 14084372_1.5.2.3.1
176 23:54:15.964311 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:54:15.964633 Creating lava-test-runner.conf files
179 23:54:15.964734 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14084372/lava-overlay-zd62a_jm/lava-14084372/0 for stage 0
180 23:54:15.964868 - 0_v4l2-compliance-uvc
181 23:54:15.965038 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:54:15.965164 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:54:15.973072 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:54:15.973219 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:54:15.973336 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:54:15.973437 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:54:15.973536 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:54:16.875811 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:54:16.876196 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:54:16.876321 extracting modules file /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14084372/extract-overlay-ramdisk-9su5lkn0/ramdisk
191 23:54:17.098116 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:54:17.098283 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:54:17.098396 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084372/compress-overlay-jqqvmt83/overlay-1.5.2.4.tar.gz to ramdisk
194 23:54:17.098474 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14084372/compress-overlay-jqqvmt83/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14084372/extract-overlay-ramdisk-9su5lkn0/ramdisk
195 23:54:17.104964 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:54:17.105224 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:54:17.105328 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:54:17.105435 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:54:17.105527 Building ramdisk /var/lib/lava/dispatcher/tmp/14084372/extract-overlay-ramdisk-9su5lkn0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14084372/extract-overlay-ramdisk-9su5lkn0/ramdisk
200 23:54:17.765368 >> 275882 blocks
201 23:54:21.900927 rename /var/lib/lava/dispatcher/tmp/14084372/extract-overlay-ramdisk-9su5lkn0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/ramdisk/ramdisk.cpio.gz
202 23:54:21.901487 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:54:21.901694 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 23:54:21.901843 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 23:54:21.902014 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/kernel/Image']
206 23:54:35.561715 Returned 0 in 13 seconds
207 23:54:35.662386 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/kernel/image.itb
208 23:54:36.290348 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:54:36.290713 output: Created: Thu May 30 00:54:36 2024
210 23:54:36.290813 output: Image 0 (kernel-1)
211 23:54:36.290900 output: Description:
212 23:54:36.290981 output: Created: Thu May 30 00:54:36 2024
213 23:54:36.291062 output: Type: Kernel Image
214 23:54:36.291146 output: Compression: lzma compressed
215 23:54:36.291231 output: Data Size: 13063488 Bytes = 12757.31 KiB = 12.46 MiB
216 23:54:36.291330 output: Architecture: AArch64
217 23:54:36.291432 output: OS: Linux
218 23:54:36.291533 output: Load Address: 0x00000000
219 23:54:36.291634 output: Entry Point: 0x00000000
220 23:54:36.291733 output: Hash algo: crc32
221 23:54:36.291828 output: Hash value: 907bf91d
222 23:54:36.291924 output: Image 1 (fdt-1)
223 23:54:36.292017 output: Description: mt8192-asurada-spherion-r0
224 23:54:36.292113 output: Created: Thu May 30 00:54:36 2024
225 23:54:36.292206 output: Type: Flat Device Tree
226 23:54:36.292302 output: Compression: uncompressed
227 23:54:36.292396 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:54:36.292489 output: Architecture: AArch64
229 23:54:36.292582 output: Hash algo: crc32
230 23:54:36.292675 output: Hash value: 0f8e4d2e
231 23:54:36.292767 output: Image 2 (ramdisk-1)
232 23:54:36.292860 output: Description: unavailable
233 23:54:36.292952 output: Created: Thu May 30 00:54:36 2024
234 23:54:36.293085 output: Type: RAMDisk Image
235 23:54:36.293179 output: Compression: Unknown Compression
236 23:54:36.293271 output: Data Size: 41211737 Bytes = 40245.84 KiB = 39.30 MiB
237 23:54:36.293364 output: Architecture: AArch64
238 23:54:36.293455 output: OS: Linux
239 23:54:36.293547 output: Load Address: unavailable
240 23:54:36.293639 output: Entry Point: unavailable
241 23:54:36.293730 output: Hash algo: crc32
242 23:54:36.293820 output: Hash value: 44db620c
243 23:54:36.293912 output: Default Configuration: 'conf-1'
244 23:54:36.294003 output: Configuration 0 (conf-1)
245 23:54:36.294094 output: Description: mt8192-asurada-spherion-r0
246 23:54:36.294186 output: Kernel: kernel-1
247 23:54:36.294277 output: Init Ramdisk: ramdisk-1
248 23:54:36.294368 output: FDT: fdt-1
249 23:54:36.294460 output: Loadables: kernel-1
250 23:54:36.294551 output:
251 23:54:36.294801 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:54:36.294938 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:54:36.295088 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 23:54:36.295230 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 23:54:36.295353 No LXC device requested
256 23:54:36.295479 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:54:36.295609 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 23:54:36.295730 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:54:36.295836 Checking files for TFTP limit of 4294967296 bytes.
260 23:54:36.296503 end: 1 tftp-deploy (duration 00:00:21) [common]
261 23:54:36.296644 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:54:36.296780 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:54:36.296954 substitutions:
264 23:54:36.297101 - {DTB}: 14084372/tftp-deploy-pcqix4nj/dtb/mt8192-asurada-spherion-r0.dtb
265 23:54:36.297203 - {INITRD}: 14084372/tftp-deploy-pcqix4nj/ramdisk/ramdisk.cpio.gz
266 23:54:36.297302 - {KERNEL}: 14084372/tftp-deploy-pcqix4nj/kernel/Image
267 23:54:36.297401 - {LAVA_MAC}: None
268 23:54:36.297498 - {PRESEED_CONFIG}: None
269 23:54:36.297599 - {PRESEED_LOCAL}: None
270 23:54:36.297700 - {RAMDISK}: 14084372/tftp-deploy-pcqix4nj/ramdisk/ramdisk.cpio.gz
271 23:54:36.297792 - {ROOT_PART}: None
272 23:54:36.297879 - {ROOT}: None
273 23:54:36.297965 - {SERVER_IP}: 192.168.201.1
274 23:54:36.298050 - {TEE}: None
275 23:54:36.298135 Parsed boot commands:
276 23:54:36.298218 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:54:36.298467 Parsed boot commands: tftpboot 192.168.201.1 14084372/tftp-deploy-pcqix4nj/kernel/image.itb 14084372/tftp-deploy-pcqix4nj/kernel/cmdline
278 23:54:36.298585 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:54:36.298706 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:54:36.298831 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:54:36.298946 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:54:36.299047 Not connected, no need to disconnect.
283 23:54:36.299152 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:54:36.299264 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:54:36.299361 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 23:54:36.303188 Setting prompt string to ['lava-test: # ']
287 23:54:36.303587 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:54:36.303726 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:54:36.303871 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:54:36.303984 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:54:36.304222 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 23:54:41.447501 >> Command sent successfully.
293 23:54:41.456724 Returned 0 in 5 seconds
294 23:54:41.557849 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:54:41.559079 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:54:41.559537 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:54:41.559924 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:54:41.560237 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:54:41.560553 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:54:41.562257 [Enter `^Ec?' for help]
302 23:54:41.727210
303 23:54:41.727678
304 23:54:41.728021 F0: 102B 0000
305 23:54:41.728332
306 23:54:41.728641 F3: 1001 0000 [0200]
307 23:54:41.730294
308 23:54:41.730711 F3: 1001 0000
309 23:54:41.731030
310 23:54:41.731326 F7: 102D 0000
311 23:54:41.731712
312 23:54:41.733426 F1: 0000 0000
313 23:54:41.733861
314 23:54:41.734260 V0: 0000 0000 [0001]
315 23:54:41.734726
316 23:54:41.737086 00: 0007 8000
317 23:54:41.737498
318 23:54:41.737808 01: 0000 0000
319 23:54:41.738103
320 23:54:41.740845 BP: 0C00 0209 [0000]
321 23:54:41.741275
322 23:54:41.741589 G0: 1182 0000
323 23:54:41.741879
324 23:54:41.744089 EC: 0000 0021 [4000]
325 23:54:41.744474
326 23:54:41.744931 S7: 0000 0000 [0000]
327 23:54:41.745293
328 23:54:41.747487 CC: 0000 0000 [0001]
329 23:54:41.747874
330 23:54:41.748188 T0: 0000 0040 [010F]
331 23:54:41.748481
332 23:54:41.748762 Jump to BL
333 23:54:41.749088
334 23:54:41.773798
335 23:54:41.774196
336 23:54:41.781097 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:54:41.785162 ARM64: Exception handlers installed.
338 23:54:41.788637 ARM64: Testing exception
339 23:54:41.791828 ARM64: Done test exception
340 23:54:41.798298 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:54:41.808825 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:54:41.815920 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:54:41.826095 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:54:41.832613 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:54:41.839399 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:54:41.850634 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:54:41.857553 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:54:41.876878 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:54:41.880346 WDT: Last reset was cold boot
350 23:54:41.883408 SPI1(PAD0) initialized at 2873684 Hz
351 23:54:41.886616 SPI5(PAD0) initialized at 992727 Hz
352 23:54:41.890331 VBOOT: Loading verstage.
353 23:54:41.897124 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:54:41.900032 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:54:41.903892 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:54:41.906873 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:54:41.914160 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:54:41.920829 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:54:41.931772 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 23:54:41.932214
361 23:54:41.932551
362 23:54:41.942364 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:54:41.945485 ARM64: Exception handlers installed.
364 23:54:41.948866 ARM64: Testing exception
365 23:54:41.949443 ARM64: Done test exception
366 23:54:41.955751 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:54:41.958876 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:54:41.973977 Probing TPM: . done!
369 23:54:41.974592 TPM ready after 0 ms
370 23:54:41.981811 Connected to device vid:did:rid of 1ae0:0028:00
371 23:54:41.988152 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:54:42.045510 Initialized TPM device CR50 revision 0
373 23:54:42.057309 tlcl_send_startup: Startup return code is 0
374 23:54:42.057756 TPM: setup succeeded
375 23:54:42.068661 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:54:42.077152 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:54:42.088756 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:54:42.098867 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:54:42.102243 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:54:42.107408 in-header: 03 07 00 00 08 00 00 00
381 23:54:42.111436 in-data: aa e4 47 04 13 02 00 00
382 23:54:42.114823 Chrome EC: UHEPI supported
383 23:54:42.121799 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:54:42.125467 in-header: 03 ad 00 00 08 00 00 00
385 23:54:42.129326 in-data: 00 20 20 08 00 00 00 00
386 23:54:42.129442 Phase 1
387 23:54:42.133711 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:54:42.140259 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:54:42.144301 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:54:42.148085 Recovery requested (1009000e)
391 23:54:42.157396 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:54:42.163013 tlcl_extend: response is 0
393 23:54:42.171854 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:54:42.177104 tlcl_extend: response is 0
395 23:54:42.184286 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:54:42.204468 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 23:54:42.210945 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:54:42.211344
399 23:54:42.211661
400 23:54:42.221731 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:54:42.226152 ARM64: Exception handlers installed.
402 23:54:42.226679 ARM64: Testing exception
403 23:54:42.229303 ARM64: Done test exception
404 23:54:42.249647 pmic_efuse_setting: Set efuses in 11 msecs
405 23:54:42.253916 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:54:42.260065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:54:42.263031 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:54:42.270235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:54:42.273946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:54:42.277874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:54:42.281818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:54:42.288776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:54:42.292714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:54:42.296678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:54:42.303819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:54:42.307878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:54:42.311690 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:54:42.315046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:54:42.322074 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:54:42.329143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:54:42.333252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:54:42.340417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:54:42.343741 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:54:42.351158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:54:42.354947 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:54:42.363049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:54:42.365825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:54:42.373100 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:54:42.376833 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:54:42.384197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:54:42.387526 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:54:42.395505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:54:42.398737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:54:42.402304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:54:42.409676 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:54:42.413355 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:54:42.421112 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:54:42.424158 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:54:42.427994 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:54:42.435027 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:54:42.438669 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:54:42.442874 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:54:42.449379 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:54:42.453596 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:54:42.457391 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:54:42.460814 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:54:42.464447 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:54:42.472006 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:54:42.475616 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:54:42.478984 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:54:42.482994 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:54:42.486312 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:54:42.490406 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:54:42.497256 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:54:42.500944 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:54:42.504910 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:54:42.512273 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:54:42.519880 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:54:42.527379 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:54:42.534747 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:54:42.542164 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:54:42.546311 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:54:42.550008 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:54:42.557596 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:54:42.560968 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 23:54:42.568271 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:54:42.572946 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 23:54:42.578741 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:54:42.587829 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 23:54:42.597007 [RTC]rtc_get_frequency_meter,154: input=23, output=977
471 23:54:42.606920 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 23:54:42.615585 [RTC]rtc_get_frequency_meter,154: input=17, output=836
473 23:54:42.625087 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 23:54:42.634937 [RTC]rtc_get_frequency_meter,154: input=15, output=789
475 23:54:42.645059 [RTC]rtc_get_frequency_meter,154: input=16, output=812
476 23:54:42.648661 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 23:54:42.652248 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 23:54:42.656452 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:54:42.663320 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 23:54:42.667056 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:54:42.670794 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 23:54:42.674736 ADC[4]: Raw value=901328 ID=7
483 23:54:42.675186 ADC[3]: Raw value=213336 ID=1
484 23:54:42.677992 RAM Code: 0x71
485 23:54:42.681740 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:54:42.685442 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:54:42.697141 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:54:42.700440 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:54:42.704521 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:54:42.709027 in-header: 03 07 00 00 08 00 00 00
491 23:54:42.713544 in-data: aa e4 47 04 13 02 00 00
492 23:54:42.716821 Chrome EC: UHEPI supported
493 23:54:42.724732 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:54:42.727643 in-header: 03 ed 00 00 08 00 00 00
495 23:54:42.728082 in-data: 80 20 60 08 00 00 00 00
496 23:54:42.731471 MRC: failed to locate region type 0.
497 23:54:42.739263 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:54:42.743098 DRAM-K: Running full calibration
499 23:54:42.750192 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:54:42.750714 header.status = 0x0
501 23:54:42.754121 header.version = 0x6 (expected: 0x6)
502 23:54:42.758220 header.size = 0xd00 (expected: 0xd00)
503 23:54:42.758815 header.flags = 0x0
504 23:54:42.765486 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:54:42.783379 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 23:54:42.791206 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:54:42.791691 dram_init: ddr_geometry: 2
508 23:54:42.794764 [EMI] MDL number = 2
509 23:54:42.795195 [EMI] Get MDL freq = 0
510 23:54:42.799021 dram_init: ddr_type: 0
511 23:54:42.799449 is_discrete_lpddr4: 1
512 23:54:42.803124 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:54:42.803552
514 23:54:42.803893
515 23:54:42.806045 [Bian_co] ETT version 0.0.0.1
516 23:54:42.809462 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:54:42.809964
518 23:54:42.816315 dramc_set_vcore_voltage set vcore to 650000
519 23:54:42.816902 Read voltage for 800, 4
520 23:54:42.819821 Vio18 = 0
521 23:54:42.820254 Vcore = 650000
522 23:54:42.820595 Vdram = 0
523 23:54:42.820912 Vddq = 0
524 23:54:42.823292 Vmddr = 0
525 23:54:42.823719 dram_init: config_dvfs: 1
526 23:54:42.829818 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:54:42.836336 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:54:42.839811 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 23:54:42.843516 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 23:54:42.847015 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 23:54:42.850525 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 23:54:42.853072 MEM_TYPE=3, freq_sel=18
533 23:54:42.856867 sv_algorithm_assistance_LP4_1600
534 23:54:42.860291 ============ PULL DRAM RESETB DOWN ============
535 23:54:42.863416 ========== PULL DRAM RESETB DOWN end =========
536 23:54:42.869905 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:54:42.870509 ===================================
538 23:54:42.873148 LPDDR4 DRAM CONFIGURATION
539 23:54:42.876797 ===================================
540 23:54:42.880318 EX_ROW_EN[0] = 0x0
541 23:54:42.880810 EX_ROW_EN[1] = 0x0
542 23:54:42.883720 LP4Y_EN = 0x0
543 23:54:42.884150 WORK_FSP = 0x0
544 23:54:42.886729 WL = 0x2
545 23:54:42.887095 RL = 0x2
546 23:54:42.890164 BL = 0x2
547 23:54:42.890693 RPST = 0x0
548 23:54:42.893989 RD_PRE = 0x0
549 23:54:42.894651 WR_PRE = 0x1
550 23:54:42.896905 WR_PST = 0x0
551 23:54:42.897396 DBI_WR = 0x0
552 23:54:42.900161 DBI_RD = 0x0
553 23:54:42.900611 OTF = 0x1
554 23:54:42.903900 ===================================
555 23:54:42.907199 ===================================
556 23:54:42.910541 ANA top config
557 23:54:42.914083 ===================================
558 23:54:42.917031 DLL_ASYNC_EN = 0
559 23:54:42.917488 ALL_SLAVE_EN = 1
560 23:54:42.920516 NEW_RANK_MODE = 1
561 23:54:42.924076 DLL_IDLE_MODE = 1
562 23:54:42.927266 LP45_APHY_COMB_EN = 1
563 23:54:42.927724 TX_ODT_DIS = 1
564 23:54:42.930655 NEW_8X_MODE = 1
565 23:54:42.934231 ===================================
566 23:54:42.937064 ===================================
567 23:54:42.940546 data_rate = 1600
568 23:54:42.944099 CKR = 1
569 23:54:42.947251 DQ_P2S_RATIO = 8
570 23:54:42.950617 ===================================
571 23:54:42.951277 CA_P2S_RATIO = 8
572 23:54:42.954259 DQ_CA_OPEN = 0
573 23:54:42.956883 DQ_SEMI_OPEN = 0
574 23:54:42.960187 CA_SEMI_OPEN = 0
575 23:54:42.963834 CA_FULL_RATE = 0
576 23:54:42.967125 DQ_CKDIV4_EN = 1
577 23:54:42.967242 CA_CKDIV4_EN = 1
578 23:54:42.970650 CA_PREDIV_EN = 0
579 23:54:42.973650 PH8_DLY = 0
580 23:54:42.977367 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:54:42.980585 DQ_AAMCK_DIV = 4
582 23:54:42.984099 CA_AAMCK_DIV = 4
583 23:54:42.984216 CA_ADMCK_DIV = 4
584 23:54:42.987075 DQ_TRACK_CA_EN = 0
585 23:54:42.990603 CA_PICK = 800
586 23:54:42.993890 CA_MCKIO = 800
587 23:54:42.997352 MCKIO_SEMI = 0
588 23:54:43.001137 PLL_FREQ = 3068
589 23:54:43.001218 DQ_UI_PI_RATIO = 32
590 23:54:43.004699 CA_UI_PI_RATIO = 0
591 23:54:43.009340 ===================================
592 23:54:43.012698 ===================================
593 23:54:43.012797 memory_type:LPDDR4
594 23:54:43.016194 GP_NUM : 10
595 23:54:43.019931 SRAM_EN : 1
596 23:54:43.020031 MD32_EN : 0
597 23:54:43.023744 ===================================
598 23:54:43.027826 [ANA_INIT] >>>>>>>>>>>>>>
599 23:54:43.027928 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:54:43.031355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:54:43.034813 ===================================
602 23:54:43.038528 data_rate = 1600,PCW = 0X7600
603 23:54:43.041622 ===================================
604 23:54:43.045033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:54:43.051374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:54:43.054642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:54:43.061757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:54:43.064748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:54:43.068550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:54:43.068653 [ANA_INIT] flow start
611 23:54:43.071416 [ANA_INIT] PLL >>>>>>>>
612 23:54:43.074875 [ANA_INIT] PLL <<<<<<<<
613 23:54:43.074992 [ANA_INIT] MIDPI >>>>>>>>
614 23:54:43.078582 [ANA_INIT] MIDPI <<<<<<<<
615 23:54:43.081666 [ANA_INIT] DLL >>>>>>>>
616 23:54:43.081767 [ANA_INIT] flow end
617 23:54:43.088562 ============ LP4 DIFF to SE enter ============
618 23:54:43.091550 ============ LP4 DIFF to SE exit ============
619 23:54:43.095027 [ANA_INIT] <<<<<<<<<<<<<
620 23:54:43.095137 [Flow] Enable top DCM control >>>>>
621 23:54:43.098468 [Flow] Enable top DCM control <<<<<
622 23:54:43.101706 Enable DLL master slave shuffle
623 23:54:43.108664 ==============================================================
624 23:54:43.112384 Gating Mode config
625 23:54:43.115344 ==============================================================
626 23:54:43.119369 Config description:
627 23:54:43.128704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:54:43.135279 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:54:43.139165 SELPH_MODE 0: By rank 1: By Phase
630 23:54:43.145724 ==============================================================
631 23:54:43.149059 GAT_TRACK_EN = 1
632 23:54:43.149139 RX_GATING_MODE = 2
633 23:54:43.152577 RX_GATING_TRACK_MODE = 2
634 23:54:43.155771 SELPH_MODE = 1
635 23:54:43.158792 PICG_EARLY_EN = 1
636 23:54:43.162104 VALID_LAT_VALUE = 1
637 23:54:43.169181 ==============================================================
638 23:54:43.172720 Enter into Gating configuration >>>>
639 23:54:43.175528 Exit from Gating configuration <<<<
640 23:54:43.179359 Enter into DVFS_PRE_config >>>>>
641 23:54:43.189313 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:54:43.192855 Exit from DVFS_PRE_config <<<<<
643 23:54:43.195682 Enter into PICG configuration >>>>
644 23:54:43.199520 Exit from PICG configuration <<<<
645 23:54:43.202745 [RX_INPUT] configuration >>>>>
646 23:54:43.202828 [RX_INPUT] configuration <<<<<
647 23:54:43.213249 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:54:43.216026 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:54:43.219593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:54:43.226458 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:54:43.233321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:54:43.240089 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:54:43.243320 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:54:43.246727 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:54:43.249730 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:54:43.256433 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:54:43.259965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:54:43.263109 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:54:43.266372 ===================================
660 23:54:43.270072 LPDDR4 DRAM CONFIGURATION
661 23:54:43.273337 ===================================
662 23:54:43.273438 EX_ROW_EN[0] = 0x0
663 23:54:43.276499 EX_ROW_EN[1] = 0x0
664 23:54:43.279817 LP4Y_EN = 0x0
665 23:54:43.279917 WORK_FSP = 0x0
666 23:54:43.283191 WL = 0x2
667 23:54:43.283309 RL = 0x2
668 23:54:43.286355 BL = 0x2
669 23:54:43.286438 RPST = 0x0
670 23:54:43.290077 RD_PRE = 0x0
671 23:54:43.290161 WR_PRE = 0x1
672 23:54:43.293498 WR_PST = 0x0
673 23:54:43.293582 DBI_WR = 0x0
674 23:54:43.296790 DBI_RD = 0x0
675 23:54:43.296900 OTF = 0x1
676 23:54:43.299929 ===================================
677 23:54:43.303499 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:54:43.310198 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:54:43.313506 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:54:43.317125 ===================================
681 23:54:43.320452 LPDDR4 DRAM CONFIGURATION
682 23:54:43.323856 ===================================
683 23:54:43.323940 EX_ROW_EN[0] = 0x10
684 23:54:43.327042 EX_ROW_EN[1] = 0x0
685 23:54:43.327126 LP4Y_EN = 0x0
686 23:54:43.330300 WORK_FSP = 0x0
687 23:54:43.330383 WL = 0x2
688 23:54:43.333980 RL = 0x2
689 23:54:43.334063 BL = 0x2
690 23:54:43.337124 RPST = 0x0
691 23:54:43.337207 RD_PRE = 0x0
692 23:54:43.340143 WR_PRE = 0x1
693 23:54:43.340226 WR_PST = 0x0
694 23:54:43.343625 DBI_WR = 0x0
695 23:54:43.343709 DBI_RD = 0x0
696 23:54:43.347106 OTF = 0x1
697 23:54:43.351163 ===================================
698 23:54:43.357106 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:54:43.360477 nWR fixed to 40
700 23:54:43.364236 [ModeRegInit_LP4] CH0 RK0
701 23:54:43.364321 [ModeRegInit_LP4] CH0 RK1
702 23:54:43.367633 [ModeRegInit_LP4] CH1 RK0
703 23:54:43.370403 [ModeRegInit_LP4] CH1 RK1
704 23:54:43.370487 match AC timing 13
705 23:54:43.377342 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:54:43.380813 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:54:43.384330 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:54:43.390934 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:54:43.394402 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:54:43.394510 [EMI DOE] emi_dcm 0
711 23:54:43.400910 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:54:43.401055 ==
713 23:54:43.404091 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:54:43.407517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:54:43.407628 ==
716 23:54:43.414122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:54:43.417465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:54:43.427696 [CA 0] Center 37 (7~68) winsize 62
719 23:54:43.430960 [CA 1] Center 37 (6~68) winsize 63
720 23:54:43.434801 [CA 2] Center 35 (5~66) winsize 62
721 23:54:43.438037 [CA 3] Center 35 (5~65) winsize 61
722 23:54:43.441431 [CA 4] Center 34 (3~65) winsize 63
723 23:54:43.444573 [CA 5] Center 33 (3~64) winsize 62
724 23:54:43.444656
725 23:54:43.448574 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:54:43.448659
727 23:54:43.451447 [CATrainingPosCal] consider 1 rank data
728 23:54:43.454576 u2DelayCellTimex100 = 270/100 ps
729 23:54:43.458368 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 23:54:43.461245 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 23:54:43.464575 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 23:54:43.471782 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
733 23:54:43.474813 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 23:54:43.478617 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:54:43.478701
736 23:54:43.482067 CA PerBit enable=1, Macro0, CA PI delay=33
737 23:54:43.482180
738 23:54:43.485368 [CBTSetCACLKResult] CA Dly = 33
739 23:54:43.485481 CS Dly: 4 (0~35)
740 23:54:43.485583 ==
741 23:54:43.488816 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:54:43.492037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:54:43.495285 ==
744 23:54:43.498783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:54:43.505143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:54:43.514010 [CA 0] Center 37 (6~68) winsize 63
747 23:54:43.517412 [CA 1] Center 37 (6~68) winsize 63
748 23:54:43.520756 [CA 2] Center 35 (4~66) winsize 63
749 23:54:43.524057 [CA 3] Center 35 (4~66) winsize 63
750 23:54:43.527376 [CA 4] Center 34 (3~65) winsize 63
751 23:54:43.530906 [CA 5] Center 33 (3~64) winsize 62
752 23:54:43.531020
753 23:54:43.534189 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:54:43.534286
755 23:54:43.538005 [CATrainingPosCal] consider 2 rank data
756 23:54:43.541312 u2DelayCellTimex100 = 270/100 ps
757 23:54:43.544478 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 23:54:43.547676 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
759 23:54:43.551236 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 23:54:43.558498 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
761 23:54:43.561295 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
762 23:54:43.564584 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:54:43.564683
764 23:54:43.567877 CA PerBit enable=1, Macro0, CA PI delay=33
765 23:54:43.567973
766 23:54:43.571443 [CBTSetCACLKResult] CA Dly = 33
767 23:54:43.571539 CS Dly: 5 (0~38)
768 23:54:43.571631
769 23:54:43.574577 ----->DramcWriteLeveling(PI) begin...
770 23:54:43.577628 ==
771 23:54:43.577705 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:54:43.584791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:54:43.584872 ==
774 23:54:43.588530 Write leveling (Byte 0): 33 => 33
775 23:54:43.588615 Write leveling (Byte 1): 29 => 29
776 23:54:43.591822 DramcWriteLeveling(PI) end<-----
777 23:54:43.591934
778 23:54:43.592025 ==
779 23:54:43.596116 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:54:43.599693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:54:43.599797 ==
782 23:54:43.602739 [Gating] SW mode calibration
783 23:54:43.609425 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:54:43.617192 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:54:43.620180 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:54:43.623673 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:54:43.630055 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 23:54:43.633744 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 23:54:43.637090 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:54:43.643859 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:54:43.647132 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:54:43.650322 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:54:43.654180 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:54:43.660277 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:54:43.663666 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:54:43.667384 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:54:43.673835 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:54:43.677235 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:54:43.680488 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:54:43.686847 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:54:43.690515 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:54:43.693660 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:54:43.700362 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 23:54:43.703797 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 23:54:43.707404 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:54:43.714494 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:54:43.718004 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:54:43.720565 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:54:43.723779 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:54:43.730611 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:54:43.734434 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:54:43.737688 0 9 12 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
813 23:54:43.744306 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:54:43.747534 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:54:43.750993 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:54:43.757616 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:54:43.760910 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:54:43.764276 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:54:43.770968 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
820 23:54:43.774892 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
821 23:54:43.777849 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:54:43.781301 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:54:43.787540 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:54:43.790820 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:54:43.794440 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:54:43.801162 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:54:43.804535 0 11 8 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
828 23:54:43.807520 0 11 12 | B1->B0 | 3636 4040 | 1 1 | (0 0) (0 0)
829 23:54:43.814723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 23:54:43.817969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:54:43.821472 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:54:43.828035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:54:43.831524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:54:43.834800 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:54:43.837959 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 23:54:43.844676 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 23:54:43.848117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:54:43.851541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:54:43.858450 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:54:43.861691 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:54:43.865036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:54:43.871620 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:54:43.875555 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:54:43.878681 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:54:43.885026 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:54:43.888613 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:54:43.892174 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:54:43.895451 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:54:43.901839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:54:43.905163 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:54:43.908736 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 23:54:43.915736 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 23:54:43.918806 Total UI for P1: 0, mck2ui 16
854 23:54:43.922004 best dqsien dly found for B0: ( 0, 14, 8)
855 23:54:43.922091 Total UI for P1: 0, mck2ui 16
856 23:54:43.928509 best dqsien dly found for B1: ( 0, 14, 10)
857 23:54:43.932366 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 23:54:43.935770 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 23:54:43.935856
860 23:54:43.938635 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 23:54:43.942201 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 23:54:43.945530 [Gating] SW calibration Done
863 23:54:43.945616 ==
864 23:54:43.949156 Dram Type= 6, Freq= 0, CH_0, rank 0
865 23:54:43.952493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 23:54:43.952580 ==
867 23:54:43.955299 RX Vref Scan: 0
868 23:54:43.955385
869 23:54:43.955471 RX Vref 0 -> 0, step: 1
870 23:54:43.955553
871 23:54:43.958804 RX Delay -130 -> 252, step: 16
872 23:54:43.962480 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 23:54:43.968736 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 23:54:43.972214 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 23:54:43.975484 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 23:54:43.979419 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 23:54:43.982494 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 23:54:43.985963 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 23:54:43.992625 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 23:54:43.996554 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 23:54:43.999882 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 23:54:44.003365 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 23:54:44.007103 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 23:54:44.012823 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 23:54:44.016222 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
886 23:54:44.019793 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
887 23:54:44.022819 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 23:54:44.023063 ==
889 23:54:44.026122 Dram Type= 6, Freq= 0, CH_0, rank 0
890 23:54:44.033409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 23:54:44.033752 ==
892 23:54:44.034029 DQS Delay:
893 23:54:44.034275 DQS0 = 0, DQS1 = 0
894 23:54:44.036632 DQM Delay:
895 23:54:44.036947 DQM0 = 86, DQM1 = 78
896 23:54:44.039626 DQ Delay:
897 23:54:44.043067 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 23:54:44.046939 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
899 23:54:44.047478 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
900 23:54:44.053414 DQ12 =85, DQ13 =77, DQ14 =93, DQ15 =85
901 23:54:44.053844
902 23:54:44.054182
903 23:54:44.054498 ==
904 23:54:44.056709 Dram Type= 6, Freq= 0, CH_0, rank 0
905 23:54:44.059841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 23:54:44.060270 ==
907 23:54:44.060667
908 23:54:44.061040
909 23:54:44.063134 TX Vref Scan disable
910 23:54:44.063561 == TX Byte 0 ==
911 23:54:44.069944 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
912 23:54:44.073085 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
913 23:54:44.073517 == TX Byte 1 ==
914 23:54:44.080234 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
915 23:54:44.083407 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
916 23:54:44.083521 ==
917 23:54:44.086780 Dram Type= 6, Freq= 0, CH_0, rank 0
918 23:54:44.089802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 23:54:44.089890 ==
920 23:54:44.104044 TX Vref=22, minBit 6, minWin=27, winSum=440
921 23:54:44.107496 TX Vref=24, minBit 7, minWin=27, winSum=445
922 23:54:44.110577 TX Vref=26, minBit 12, minWin=27, winSum=449
923 23:54:44.113558 TX Vref=28, minBit 12, minWin=27, winSum=452
924 23:54:44.117281 TX Vref=30, minBit 3, minWin=28, winSum=456
925 23:54:44.123725 TX Vref=32, minBit 12, minWin=27, winSum=453
926 23:54:44.127420 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 30
927 23:54:44.127504
928 23:54:44.130673 Final TX Range 1 Vref 30
929 23:54:44.130757
930 23:54:44.130823 ==
931 23:54:44.133823 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:54:44.137756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:54:44.137840 ==
934 23:54:44.137907
935 23:54:44.140675
936 23:54:44.140757 TX Vref Scan disable
937 23:54:44.143809 == TX Byte 0 ==
938 23:54:44.147249 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
939 23:54:44.151097 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
940 23:54:44.153926 == TX Byte 1 ==
941 23:54:44.157463 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 23:54:44.161102 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 23:54:44.164238
944 23:54:44.164320 [DATLAT]
945 23:54:44.164385 Freq=800, CH0 RK0
946 23:54:44.164447
947 23:54:44.167261 DATLAT Default: 0xa
948 23:54:44.167343 0, 0xFFFF, sum = 0
949 23:54:44.170909 1, 0xFFFF, sum = 0
950 23:54:44.170993 2, 0xFFFF, sum = 0
951 23:54:44.174259 3, 0xFFFF, sum = 0
952 23:54:44.174343 4, 0xFFFF, sum = 0
953 23:54:44.177459 5, 0xFFFF, sum = 0
954 23:54:44.177544 6, 0xFFFF, sum = 0
955 23:54:44.180714 7, 0xFFFF, sum = 0
956 23:54:44.180797 8, 0xFFFF, sum = 0
957 23:54:44.184190 9, 0x0, sum = 1
958 23:54:44.184274 10, 0x0, sum = 2
959 23:54:44.187433 11, 0x0, sum = 3
960 23:54:44.187516 12, 0x0, sum = 4
961 23:54:44.191310 best_step = 10
962 23:54:44.191392
963 23:54:44.191457 ==
964 23:54:44.194527 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:54:44.197514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 23:54:44.197600 ==
967 23:54:44.201158 RX Vref Scan: 1
968 23:54:44.201240
969 23:54:44.201305 Set Vref Range= 32 -> 127
970 23:54:44.201366
971 23:54:44.204225 RX Vref 32 -> 127, step: 1
972 23:54:44.204307
973 23:54:44.207684 RX Delay -95 -> 252, step: 8
974 23:54:44.207766
975 23:54:44.211184 Set Vref, RX VrefLevel [Byte0]: 32
976 23:54:44.214718 [Byte1]: 32
977 23:54:44.214801
978 23:54:44.218390 Set Vref, RX VrefLevel [Byte0]: 33
979 23:54:44.221362 [Byte1]: 33
980 23:54:44.221444
981 23:54:44.225228 Set Vref, RX VrefLevel [Byte0]: 34
982 23:54:44.228530 [Byte1]: 34
983 23:54:44.231665
984 23:54:44.231747 Set Vref, RX VrefLevel [Byte0]: 35
985 23:54:44.235405 [Byte1]: 35
986 23:54:44.239216
987 23:54:44.239298 Set Vref, RX VrefLevel [Byte0]: 36
988 23:54:44.242964 [Byte1]: 36
989 23:54:44.246917
990 23:54:44.246999 Set Vref, RX VrefLevel [Byte0]: 37
991 23:54:44.250585 [Byte1]: 37
992 23:54:44.255093
993 23:54:44.255174 Set Vref, RX VrefLevel [Byte0]: 38
994 23:54:44.258424 [Byte1]: 38
995 23:54:44.262971
996 23:54:44.263052 Set Vref, RX VrefLevel [Byte0]: 39
997 23:54:44.266449 [Byte1]: 39
998 23:54:44.270342
999 23:54:44.270425 Set Vref, RX VrefLevel [Byte0]: 40
1000 23:54:44.272947 [Byte1]: 40
1001 23:54:44.277872
1002 23:54:44.277954 Set Vref, RX VrefLevel [Byte0]: 41
1003 23:54:44.281320 [Byte1]: 41
1004 23:54:44.284750
1005 23:54:44.288129 Set Vref, RX VrefLevel [Byte0]: 42
1006 23:54:44.291774 [Byte1]: 42
1007 23:54:44.291857
1008 23:54:44.294976 Set Vref, RX VrefLevel [Byte0]: 43
1009 23:54:44.298541 [Byte1]: 43
1010 23:54:44.298623
1011 23:54:44.301851 Set Vref, RX VrefLevel [Byte0]: 44
1012 23:54:44.305024 [Byte1]: 44
1013 23:54:44.305107
1014 23:54:44.308614 Set Vref, RX VrefLevel [Byte0]: 45
1015 23:54:44.311657 [Byte1]: 45
1016 23:54:44.315359
1017 23:54:44.315442 Set Vref, RX VrefLevel [Byte0]: 46
1018 23:54:44.318817 [Byte1]: 46
1019 23:54:44.323435
1020 23:54:44.323523 Set Vref, RX VrefLevel [Byte0]: 47
1021 23:54:44.326651 [Byte1]: 47
1022 23:54:44.330660
1023 23:54:44.330804 Set Vref, RX VrefLevel [Byte0]: 48
1024 23:54:44.333922 [Byte1]: 48
1025 23:54:44.338287
1026 23:54:44.338398 Set Vref, RX VrefLevel [Byte0]: 49
1027 23:54:44.341873 [Byte1]: 49
1028 23:54:44.345985
1029 23:54:44.346105 Set Vref, RX VrefLevel [Byte0]: 50
1030 23:54:44.349614 [Byte1]: 50
1031 23:54:44.353788
1032 23:54:44.353870 Set Vref, RX VrefLevel [Byte0]: 51
1033 23:54:44.356783 [Byte1]: 51
1034 23:54:44.361451
1035 23:54:44.361532 Set Vref, RX VrefLevel [Byte0]: 52
1036 23:54:44.364224 [Byte1]: 52
1037 23:54:44.369264
1038 23:54:44.369346 Set Vref, RX VrefLevel [Byte0]: 53
1039 23:54:44.372683 [Byte1]: 53
1040 23:54:44.376535
1041 23:54:44.376949 Set Vref, RX VrefLevel [Byte0]: 54
1042 23:54:44.380161 [Byte1]: 54
1043 23:54:44.384253
1044 23:54:44.384774 Set Vref, RX VrefLevel [Byte0]: 55
1045 23:54:44.387541 [Byte1]: 55
1046 23:54:44.391786
1047 23:54:44.392208 Set Vref, RX VrefLevel [Byte0]: 56
1048 23:54:44.395191 [Byte1]: 56
1049 23:54:44.400215
1050 23:54:44.400630 Set Vref, RX VrefLevel [Byte0]: 57
1051 23:54:44.405962 [Byte1]: 57
1052 23:54:44.406386
1053 23:54:44.409535 Set Vref, RX VrefLevel [Byte0]: 58
1054 23:54:44.412692 [Byte1]: 58
1055 23:54:44.413139
1056 23:54:44.416518 Set Vref, RX VrefLevel [Byte0]: 59
1057 23:54:44.419749 [Byte1]: 59
1058 23:54:44.420266
1059 23:54:44.422910 Set Vref, RX VrefLevel [Byte0]: 60
1060 23:54:44.425632 [Byte1]: 60
1061 23:54:44.429437
1062 23:54:44.429967 Set Vref, RX VrefLevel [Byte0]: 61
1063 23:54:44.432889 [Byte1]: 61
1064 23:54:44.437303
1065 23:54:44.437718 Set Vref, RX VrefLevel [Byte0]: 62
1066 23:54:44.440573 [Byte1]: 62
1067 23:54:44.444951
1068 23:54:44.445407 Set Vref, RX VrefLevel [Byte0]: 63
1069 23:54:44.448417 [Byte1]: 63
1070 23:54:44.452822
1071 23:54:44.453293 Set Vref, RX VrefLevel [Byte0]: 64
1072 23:54:44.456183 [Byte1]: 64
1073 23:54:44.460039
1074 23:54:44.460455 Set Vref, RX VrefLevel [Byte0]: 65
1075 23:54:44.463431 [Byte1]: 65
1076 23:54:44.468027
1077 23:54:44.468445 Set Vref, RX VrefLevel [Byte0]: 66
1078 23:54:44.471470 [Byte1]: 66
1079 23:54:44.475170
1080 23:54:44.475586 Set Vref, RX VrefLevel [Byte0]: 67
1081 23:54:44.478892 [Byte1]: 67
1082 23:54:44.483114
1083 23:54:44.483531 Set Vref, RX VrefLevel [Byte0]: 68
1084 23:54:44.486226 [Byte1]: 68
1085 23:54:44.490516
1086 23:54:44.491028 Set Vref, RX VrefLevel [Byte0]: 69
1087 23:54:44.494177 [Byte1]: 69
1088 23:54:44.498181
1089 23:54:44.498662 Set Vref, RX VrefLevel [Byte0]: 70
1090 23:54:44.501545 [Byte1]: 70
1091 23:54:44.505899
1092 23:54:44.506345 Set Vref, RX VrefLevel [Byte0]: 71
1093 23:54:44.509210 [Byte1]: 71
1094 23:54:44.513531
1095 23:54:44.514050 Set Vref, RX VrefLevel [Byte0]: 72
1096 23:54:44.516869 [Byte1]: 72
1097 23:54:44.520966
1098 23:54:44.521424 Set Vref, RX VrefLevel [Byte0]: 73
1099 23:54:44.524356 [Byte1]: 73
1100 23:54:44.528509
1101 23:54:44.528923 Set Vref, RX VrefLevel [Byte0]: 74
1102 23:54:44.531863 [Byte1]: 74
1103 23:54:44.535997
1104 23:54:44.536411 Set Vref, RX VrefLevel [Byte0]: 75
1105 23:54:44.539287 [Byte1]: 75
1106 23:54:44.544009
1107 23:54:44.544426 Set Vref, RX VrefLevel [Byte0]: 76
1108 23:54:44.547000 [Byte1]: 76
1109 23:54:44.551267
1110 23:54:44.551904 Final RX Vref Byte 0 = 62 to rank0
1111 23:54:44.554709 Final RX Vref Byte 1 = 58 to rank0
1112 23:54:44.557706 Final RX Vref Byte 0 = 62 to rank1
1113 23:54:44.561633 Final RX Vref Byte 1 = 58 to rank1==
1114 23:54:44.564666 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 23:54:44.568075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 23:54:44.571495 ==
1117 23:54:44.572042 DQS Delay:
1118 23:54:44.572401 DQS0 = 0, DQS1 = 0
1119 23:54:44.574450 DQM Delay:
1120 23:54:44.574867 DQM0 = 87, DQM1 = 80
1121 23:54:44.578415 DQ Delay:
1122 23:54:44.581406 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1123 23:54:44.581825 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1124 23:54:44.584912 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1125 23:54:44.587967 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1126 23:54:44.588346
1127 23:54:44.591700
1128 23:54:44.598708 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1129 23:54:44.601508 CH0 RK0: MR19=606, MR18=260D
1130 23:54:44.608223 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1131 23:54:44.608649
1132 23:54:44.612043 ----->DramcWriteLeveling(PI) begin...
1133 23:54:44.612468 ==
1134 23:54:44.614978 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 23:54:44.618125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 23:54:44.618549 ==
1137 23:54:44.621396 Write leveling (Byte 0): 32 => 32
1138 23:54:44.624741 Write leveling (Byte 1): 29 => 29
1139 23:54:44.628160 DramcWriteLeveling(PI) end<-----
1140 23:54:44.628579
1141 23:54:44.628913 ==
1142 23:54:44.631867 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:54:44.634791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:54:44.635265 ==
1145 23:54:44.638762 [Gating] SW mode calibration
1146 23:54:44.645411 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 23:54:44.651857 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 23:54:44.655297 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 23:54:44.659137 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1150 23:54:44.702599 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1151 23:54:44.703169 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 23:54:44.703978 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 23:54:44.704337 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:54:44.704648 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:54:44.705171 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:54:44.705517 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:54:44.705897 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:54:44.706357 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:54:44.706840 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:54:44.717602 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:54:44.718355 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:54:44.720868 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:54:44.721328 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:54:44.723946 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:54:44.730720 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 23:54:44.734056 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1167 23:54:44.737083 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:54:44.744081 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:54:44.747030 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:54:44.750188 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:54:44.757095 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:54:44.760418 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:54:44.763691 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:54:44.767085 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1175 23:54:44.773616 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1176 23:54:44.776776 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 23:54:44.780274 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:54:44.786851 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:54:44.790321 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:54:44.794126 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1181 23:54:44.800391 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1182 23:54:44.803860 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
1183 23:54:44.807238 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1184 23:54:44.814043 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:54:44.817529 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:54:44.820883 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:54:44.823927 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:54:44.831416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:54:44.834745 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1190 23:54:44.838841 0 11 8 | B1->B0 | 2a2a 4141 | 0 0 | (0 0) (0 0)
1191 23:54:44.842739 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1192 23:54:44.846373 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:54:44.853511 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:54:44.856405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:54:44.860593 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:54:44.864463 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:54:44.871177 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:54:44.874492 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1199 23:54:44.877655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:54:44.884296 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:54:44.887808 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:54:44.891141 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:54:44.897836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:54:44.901395 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:54:44.904435 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:54:44.908290 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:54:44.914830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:54:44.917912 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:54:44.921345 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:54:44.927844 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:54:44.931566 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:54:44.934480 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1213 23:54:44.941891 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 23:54:44.944711 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1215 23:54:44.948390 Total UI for P1: 0, mck2ui 16
1216 23:54:44.951446 best dqsien dly found for B0: ( 0, 14, 2)
1217 23:54:44.954922 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 23:54:44.958618 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 23:54:44.962113 Total UI for P1: 0, mck2ui 16
1220 23:54:44.964786 best dqsien dly found for B1: ( 0, 14, 12)
1221 23:54:44.968072 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1222 23:54:44.975096 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1223 23:54:44.975515
1224 23:54:44.978141 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1225 23:54:44.981801 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1226 23:54:44.985162 [Gating] SW calibration Done
1227 23:54:44.985581 ==
1228 23:54:44.988329 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 23:54:44.991884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 23:54:44.992306 ==
1231 23:54:44.992639 RX Vref Scan: 0
1232 23:54:44.992954
1233 23:54:44.995059 RX Vref 0 -> 0, step: 1
1234 23:54:44.995476
1235 23:54:44.998641 RX Delay -130 -> 252, step: 16
1236 23:54:45.001807 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 23:54:45.005171 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 23:54:45.011987 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 23:54:45.015827 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 23:54:45.018716 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 23:54:45.022325 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 23:54:45.025690 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 23:54:45.028928 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 23:54:45.035894 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 23:54:45.039381 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 23:54:45.042417 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 23:54:45.045895 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 23:54:45.049158 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1249 23:54:45.055478 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 23:54:45.059234 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 23:54:45.062756 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1252 23:54:45.063171 ==
1253 23:54:45.065486 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 23:54:45.069275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 23:54:45.069692 ==
1256 23:54:45.072229 DQS Delay:
1257 23:54:45.072685 DQS0 = 0, DQS1 = 0
1258 23:54:45.075650 DQM Delay:
1259 23:54:45.076063 DQM0 = 86, DQM1 = 76
1260 23:54:45.076392 DQ Delay:
1261 23:54:45.079346 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1262 23:54:45.082214 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1263 23:54:45.085662 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1264 23:54:45.088930 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1265 23:54:45.089394
1266 23:54:45.089726
1267 23:54:45.092271 ==
1268 23:54:45.095721 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 23:54:45.099418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 23:54:45.099501 ==
1271 23:54:45.099565
1272 23:54:45.099625
1273 23:54:45.101776 TX Vref Scan disable
1274 23:54:45.101856 == TX Byte 0 ==
1275 23:54:45.105257 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1276 23:54:45.111763 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1277 23:54:45.111844 == TX Byte 1 ==
1278 23:54:45.115466 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1279 23:54:45.122197 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1280 23:54:45.122285 ==
1281 23:54:45.125323 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 23:54:45.128631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 23:54:45.128720 ==
1284 23:54:45.142396 TX Vref=22, minBit 9, minWin=27, winSum=446
1285 23:54:45.145605 TX Vref=24, minBit 3, minWin=27, winSum=446
1286 23:54:45.148886 TX Vref=26, minBit 9, minWin=27, winSum=450
1287 23:54:45.152346 TX Vref=28, minBit 9, minWin=27, winSum=456
1288 23:54:45.155505 TX Vref=30, minBit 4, minWin=28, winSum=457
1289 23:54:45.159306 TX Vref=32, minBit 4, minWin=28, winSum=457
1290 23:54:45.165523 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 30
1291 23:54:45.165605
1292 23:54:45.168884 Final TX Range 1 Vref 30
1293 23:54:45.169026
1294 23:54:45.169094 ==
1295 23:54:45.172611 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 23:54:45.175832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 23:54:45.175913 ==
1298 23:54:45.175977
1299 23:54:45.176036
1300 23:54:45.179062 TX Vref Scan disable
1301 23:54:45.182288 == TX Byte 0 ==
1302 23:54:45.185938 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1303 23:54:45.189051 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1304 23:54:45.192343 == TX Byte 1 ==
1305 23:54:45.195638 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 23:54:45.199635 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 23:54:45.199736
1308 23:54:45.202613 [DATLAT]
1309 23:54:45.202721 Freq=800, CH0 RK1
1310 23:54:45.202810
1311 23:54:45.205719 DATLAT Default: 0xa
1312 23:54:45.205788 0, 0xFFFF, sum = 0
1313 23:54:45.209127 1, 0xFFFF, sum = 0
1314 23:54:45.209195 2, 0xFFFF, sum = 0
1315 23:54:45.212545 3, 0xFFFF, sum = 0
1316 23:54:45.212625 4, 0xFFFF, sum = 0
1317 23:54:45.216610 5, 0xFFFF, sum = 0
1318 23:54:45.216714 6, 0xFFFF, sum = 0
1319 23:54:45.219139 7, 0xFFFF, sum = 0
1320 23:54:45.219233 8, 0xFFFF, sum = 0
1321 23:54:45.222633 9, 0x0, sum = 1
1322 23:54:45.222742 10, 0x0, sum = 2
1323 23:54:45.226308 11, 0x0, sum = 3
1324 23:54:45.226411 12, 0x0, sum = 4
1325 23:54:45.229942 best_step = 10
1326 23:54:45.230037
1327 23:54:45.230115 ==
1328 23:54:45.232754 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 23:54:45.236240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 23:54:45.236311 ==
1331 23:54:45.239251 RX Vref Scan: 0
1332 23:54:45.239349
1333 23:54:45.239437 RX Vref 0 -> 0, step: 1
1334 23:54:45.239525
1335 23:54:45.242691 RX Delay -95 -> 252, step: 8
1336 23:54:45.245871 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1337 23:54:45.252944 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 23:54:45.256670 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 23:54:45.259506 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 23:54:45.263180 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 23:54:45.266084 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 23:54:45.273571 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 23:54:45.276772 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 23:54:45.279505 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 23:54:45.283388 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 23:54:45.286384 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 23:54:45.293317 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 23:54:45.296811 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1349 23:54:45.300105 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 23:54:45.303570 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 23:54:45.306329 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 23:54:45.306409 ==
1353 23:54:45.309656 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 23:54:45.316617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 23:54:45.316698 ==
1356 23:54:45.316761 DQS Delay:
1357 23:54:45.320417 DQS0 = 0, DQS1 = 0
1358 23:54:45.320497 DQM Delay:
1359 23:54:45.320561 DQM0 = 87, DQM1 = 78
1360 23:54:45.323400 DQ Delay:
1361 23:54:45.326624 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1362 23:54:45.330026 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 23:54:45.333428 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 23:54:45.337592 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1365 23:54:45.337672
1366 23:54:45.337735
1367 23:54:45.343766 [DQSOSCAuto] RK1, (LSB)MR18= 0x311c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1368 23:54:45.346531 CH0 RK1: MR19=606, MR18=311C
1369 23:54:45.353644 CH0_RK1: MR19=0x606, MR18=0x311C, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 23:54:45.357054 [RxdqsGatingPostProcess] freq 800
1371 23:54:45.359958 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 23:54:45.363996 Pre-setting of DQS Precalculation
1373 23:54:45.370595 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 23:54:45.370676 ==
1375 23:54:45.373803 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 23:54:45.376821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 23:54:45.376902 ==
1378 23:54:45.384048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 23:54:45.387264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 23:54:45.396911 [CA 0] Center 37 (7~67) winsize 61
1381 23:54:45.400308 [CA 1] Center 36 (6~66) winsize 61
1382 23:54:45.403816 [CA 2] Center 34 (5~64) winsize 60
1383 23:54:45.406899 [CA 3] Center 33 (3~64) winsize 62
1384 23:54:45.410212 [CA 4] Center 34 (4~65) winsize 62
1385 23:54:45.413845 [CA 5] Center 33 (3~64) winsize 62
1386 23:54:45.413927
1387 23:54:45.417104 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 23:54:45.417185
1389 23:54:45.420343 [CATrainingPosCal] consider 1 rank data
1390 23:54:45.423519 u2DelayCellTimex100 = 270/100 ps
1391 23:54:45.427381 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1392 23:54:45.430549 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 23:54:45.433763 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1394 23:54:45.440352 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 23:54:45.444058 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 23:54:45.447148 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 23:54:45.447229
1398 23:54:45.450692 CA PerBit enable=1, Macro0, CA PI delay=33
1399 23:54:45.450773
1400 23:54:45.453857 [CBTSetCACLKResult] CA Dly = 33
1401 23:54:45.453939 CS Dly: 5 (0~36)
1402 23:54:45.454003 ==
1403 23:54:45.457667 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 23:54:45.464445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 23:54:45.464531 ==
1406 23:54:45.467889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 23:54:45.473940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 23:54:45.483317 [CA 0] Center 36 (6~66) winsize 61
1409 23:54:45.486655 [CA 1] Center 36 (6~66) winsize 61
1410 23:54:45.490340 [CA 2] Center 34 (3~65) winsize 63
1411 23:54:45.493746 [CA 3] Center 33 (3~64) winsize 62
1412 23:54:45.496785 [CA 4] Center 34 (4~65) winsize 62
1413 23:54:45.500616 [CA 5] Center 33 (3~64) winsize 62
1414 23:54:45.501079
1415 23:54:45.504018 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 23:54:45.504436
1417 23:54:45.507738 [CATrainingPosCal] consider 2 rank data
1418 23:54:45.511705 u2DelayCellTimex100 = 270/100 ps
1419 23:54:45.515513 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1420 23:54:45.519093 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 23:54:45.522868 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1422 23:54:45.526435 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 23:54:45.530154 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 23:54:45.534170 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 23:54:45.534589
1426 23:54:45.537839 CA PerBit enable=1, Macro0, CA PI delay=33
1427 23:54:45.538259
1428 23:54:45.540591 [CBTSetCACLKResult] CA Dly = 33
1429 23:54:45.541048 CS Dly: 5 (0~37)
1430 23:54:45.541392
1431 23:54:45.544194 ----->DramcWriteLeveling(PI) begin...
1432 23:54:45.544614 ==
1433 23:54:45.547459 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 23:54:45.551282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 23:54:45.554200 ==
1436 23:54:45.554618 Write leveling (Byte 0): 27 => 27
1437 23:54:45.557457 Write leveling (Byte 1): 27 => 27
1438 23:54:45.560822 DramcWriteLeveling(PI) end<-----
1439 23:54:45.561297
1440 23:54:45.561631 ==
1441 23:54:45.564258 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 23:54:45.571536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 23:54:45.571957 ==
1444 23:54:45.572290 [Gating] SW mode calibration
1445 23:54:45.581117 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 23:54:45.584817 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 23:54:45.587976 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 23:54:45.594802 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 23:54:45.597998 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 23:54:45.601624 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:54:45.607981 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:54:45.611645 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:54:45.614934 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:54:45.621854 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:54:45.624776 0 7 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1456 23:54:45.628275 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:54:45.632155 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:54:45.638309 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1459 23:54:45.641796 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:54:45.645236 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1461 23:54:45.651700 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:54:45.655298 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1463 23:54:45.658905 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1464 23:54:45.665084 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1465 23:54:45.668518 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
1466 23:54:45.671804 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1467 23:54:45.678469 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:54:45.682307 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1469 23:54:45.685587 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:54:45.691887 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:54:45.695737 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1472 23:54:45.698309 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:54:45.702225 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:54:45.709070 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 23:54:45.712178 0 9 16 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
1476 23:54:45.715311 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:54:45.722010 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1478 23:54:45.725130 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1479 23:54:45.728753 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:54:45.735659 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:54:45.738640 0 10 8 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 0)
1482 23:54:45.742319 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1483 23:54:45.748911 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:54:45.752182 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:54:45.755585 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1486 23:54:45.762217 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:54:45.765420 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:54:45.768889 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 23:54:45.772281 0 11 8 | B1->B0 | 3838 3030 | 0 0 | (0 0) (0 0)
1490 23:54:45.779085 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:54:45.782059 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:54:45.785463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:54:45.792879 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:54:45.795639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:54:45.799301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:54:45.805406 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:54:45.808818 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1498 23:54:45.812749 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:54:45.819296 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:54:45.822741 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:54:45.826072 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:54:45.828962 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:54:45.836144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:54:45.839414 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:54:45.842741 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:54:45.849483 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:54:45.852624 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:54:45.856111 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:54:45.862677 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:54:45.865945 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:54:45.869171 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:54:45.875909 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 23:54:45.879480 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1514 23:54:45.883047 Total UI for P1: 0, mck2ui 16
1515 23:54:45.886175 best dqsien dly found for B0: ( 0, 14, 4)
1516 23:54:45.889700 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 23:54:45.892757 Total UI for P1: 0, mck2ui 16
1518 23:54:45.896256 best dqsien dly found for B1: ( 0, 14, 6)
1519 23:54:45.899857 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1520 23:54:45.903041 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 23:54:45.903499
1522 23:54:45.906169 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 23:54:45.909780 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 23:54:45.913283 [Gating] SW calibration Done
1525 23:54:45.913698 ==
1526 23:54:45.916290 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 23:54:45.923017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 23:54:45.923435 ==
1529 23:54:45.923763 RX Vref Scan: 0
1530 23:54:45.924070
1531 23:54:45.926392 RX Vref 0 -> 0, step: 1
1532 23:54:45.926809
1533 23:54:45.929674 RX Delay -130 -> 252, step: 16
1534 23:54:45.932725 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1535 23:54:45.936759 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1536 23:54:45.939779 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1537 23:54:45.942882 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 23:54:45.949629 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1539 23:54:45.952779 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1540 23:54:45.956329 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 23:54:45.959289 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1542 23:54:45.962909 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1543 23:54:45.969349 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1544 23:54:45.972759 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1545 23:54:45.975938 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 23:54:45.979372 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 23:54:45.982863 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 23:54:45.989292 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 23:54:45.992695 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1550 23:54:45.992776 ==
1551 23:54:45.996189 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 23:54:45.999270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 23:54:45.999352 ==
1554 23:54:46.002724 DQS Delay:
1555 23:54:46.002806 DQS0 = 0, DQS1 = 0
1556 23:54:46.002870 DQM Delay:
1557 23:54:46.006183 DQM0 = 83, DQM1 = 76
1558 23:54:46.006264 DQ Delay:
1559 23:54:46.009851 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1560 23:54:46.012988 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1561 23:54:46.016137 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1562 23:54:46.020022 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 23:54:46.020115
1564 23:54:46.020189
1565 23:54:46.020257 ==
1566 23:54:46.023254 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 23:54:46.026617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 23:54:46.029953 ==
1569 23:54:46.030061
1570 23:54:46.030148
1571 23:54:46.030229 TX Vref Scan disable
1572 23:54:46.032835 == TX Byte 0 ==
1573 23:54:46.036232 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 23:54:46.040167 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 23:54:46.043154 == TX Byte 1 ==
1576 23:54:46.046392 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 23:54:46.050235 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 23:54:46.050406 ==
1579 23:54:46.053328 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 23:54:46.059904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 23:54:46.060253 ==
1582 23:54:46.072386 TX Vref=22, minBit 0, minWin=27, winSum=439
1583 23:54:46.075536 TX Vref=24, minBit 8, minWin=27, winSum=443
1584 23:54:46.078345 TX Vref=26, minBit 8, minWin=27, winSum=447
1585 23:54:46.082368 TX Vref=28, minBit 15, minWin=27, winSum=450
1586 23:54:46.086052 TX Vref=30, minBit 13, minWin=27, winSum=450
1587 23:54:46.089328 TX Vref=32, minBit 11, minWin=27, winSum=455
1588 23:54:46.096485 [TxChooseVref] Worse bit 11, Min win 27, Win sum 455, Final Vref 32
1589 23:54:46.096948
1590 23:54:46.099707 Final TX Range 1 Vref 32
1591 23:54:46.100114
1592 23:54:46.100434 ==
1593 23:54:46.103654 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 23:54:46.106185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 23:54:46.106634 ==
1596 23:54:46.106964
1597 23:54:46.107294
1598 23:54:46.109345 TX Vref Scan disable
1599 23:54:46.112688 == TX Byte 0 ==
1600 23:54:46.116525 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 23:54:46.119855 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 23:54:46.123381 == TX Byte 1 ==
1603 23:54:46.126179 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 23:54:46.130009 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 23:54:46.130549
1606 23:54:46.132897 [DATLAT]
1607 23:54:46.133339 Freq=800, CH1 RK0
1608 23:54:46.133666
1609 23:54:46.136157 DATLAT Default: 0xa
1610 23:54:46.136562 0, 0xFFFF, sum = 0
1611 23:54:46.140276 1, 0xFFFF, sum = 0
1612 23:54:46.140692 2, 0xFFFF, sum = 0
1613 23:54:46.143047 3, 0xFFFF, sum = 0
1614 23:54:46.143459 4, 0xFFFF, sum = 0
1615 23:54:46.146530 5, 0xFFFF, sum = 0
1616 23:54:46.147089 6, 0xFFFF, sum = 0
1617 23:54:46.149772 7, 0xFFFF, sum = 0
1618 23:54:46.150197 8, 0xFFFF, sum = 0
1619 23:54:46.153420 9, 0x0, sum = 1
1620 23:54:46.153852 10, 0x0, sum = 2
1621 23:54:46.156380 11, 0x0, sum = 3
1622 23:54:46.156814 12, 0x0, sum = 4
1623 23:54:46.157172 best_step = 10
1624 23:54:46.159992
1625 23:54:46.160398 ==
1626 23:54:46.163772 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:54:46.166574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:54:46.167012 ==
1629 23:54:46.167382 RX Vref Scan: 1
1630 23:54:46.167690
1631 23:54:46.170278 Set Vref Range= 32 -> 127
1632 23:54:46.170803
1633 23:54:46.173421 RX Vref 32 -> 127, step: 1
1634 23:54:46.173830
1635 23:54:46.176765 RX Delay -95 -> 252, step: 8
1636 23:54:46.177253
1637 23:54:46.180306 Set Vref, RX VrefLevel [Byte0]: 32
1638 23:54:46.183484 [Byte1]: 32
1639 23:54:46.183895
1640 23:54:46.187551 Set Vref, RX VrefLevel [Byte0]: 33
1641 23:54:46.190356 [Byte1]: 33
1642 23:54:46.190768
1643 23:54:46.193433 Set Vref, RX VrefLevel [Byte0]: 34
1644 23:54:46.197083 [Byte1]: 34
1645 23:54:46.200152
1646 23:54:46.200679 Set Vref, RX VrefLevel [Byte0]: 35
1647 23:54:46.203405 [Byte1]: 35
1648 23:54:46.208357
1649 23:54:46.208869 Set Vref, RX VrefLevel [Byte0]: 36
1650 23:54:46.211534 [Byte1]: 36
1651 23:54:46.215954
1652 23:54:46.216458 Set Vref, RX VrefLevel [Byte0]: 37
1653 23:54:46.218485 [Byte1]: 37
1654 23:54:46.223364
1655 23:54:46.223866 Set Vref, RX VrefLevel [Byte0]: 38
1656 23:54:46.226375 [Byte1]: 38
1657 23:54:46.231019
1658 23:54:46.231428 Set Vref, RX VrefLevel [Byte0]: 39
1659 23:54:46.234148 [Byte1]: 39
1660 23:54:46.237947
1661 23:54:46.238396 Set Vref, RX VrefLevel [Byte0]: 40
1662 23:54:46.241907 [Byte1]: 40
1663 23:54:46.245605
1664 23:54:46.246012 Set Vref, RX VrefLevel [Byte0]: 41
1665 23:54:46.249034 [Byte1]: 41
1666 23:54:46.253332
1667 23:54:46.253742 Set Vref, RX VrefLevel [Byte0]: 42
1668 23:54:46.257111 [Byte1]: 42
1669 23:54:46.261105
1670 23:54:46.261680 Set Vref, RX VrefLevel [Byte0]: 43
1671 23:54:46.264320 [Byte1]: 43
1672 23:54:46.268206
1673 23:54:46.268745 Set Vref, RX VrefLevel [Byte0]: 44
1674 23:54:46.271968 [Byte1]: 44
1675 23:54:46.276248
1676 23:54:46.276657 Set Vref, RX VrefLevel [Byte0]: 45
1677 23:54:46.279350 [Byte1]: 45
1678 23:54:46.283405
1679 23:54:46.284089 Set Vref, RX VrefLevel [Byte0]: 46
1680 23:54:46.287157 [Byte1]: 46
1681 23:54:46.291589
1682 23:54:46.292181 Set Vref, RX VrefLevel [Byte0]: 47
1683 23:54:46.294923 [Byte1]: 47
1684 23:54:46.299257
1685 23:54:46.299660 Set Vref, RX VrefLevel [Byte0]: 48
1686 23:54:46.302752 [Byte1]: 48
1687 23:54:46.306381
1688 23:54:46.306792 Set Vref, RX VrefLevel [Byte0]: 49
1689 23:54:46.309754 [Byte1]: 49
1690 23:54:46.314064
1691 23:54:46.314474 Set Vref, RX VrefLevel [Byte0]: 50
1692 23:54:46.317944 [Byte1]: 50
1693 23:54:46.322119
1694 23:54:46.322526 Set Vref, RX VrefLevel [Byte0]: 51
1695 23:54:46.325049 [Byte1]: 51
1696 23:54:46.329449
1697 23:54:46.329876 Set Vref, RX VrefLevel [Byte0]: 52
1698 23:54:46.332744 [Byte1]: 52
1699 23:54:46.337094
1700 23:54:46.337507 Set Vref, RX VrefLevel [Byte0]: 53
1701 23:54:46.339824 [Byte1]: 53
1702 23:54:46.344720
1703 23:54:46.345340 Set Vref, RX VrefLevel [Byte0]: 54
1704 23:54:46.348144 [Byte1]: 54
1705 23:54:46.352178
1706 23:54:46.352604 Set Vref, RX VrefLevel [Byte0]: 55
1707 23:54:46.355248 [Byte1]: 55
1708 23:54:46.359798
1709 23:54:46.360207 Set Vref, RX VrefLevel [Byte0]: 56
1710 23:54:46.363065 [Byte1]: 56
1711 23:54:46.367095
1712 23:54:46.367613 Set Vref, RX VrefLevel [Byte0]: 57
1713 23:54:46.370975 [Byte1]: 57
1714 23:54:46.375005
1715 23:54:46.375413 Set Vref, RX VrefLevel [Byte0]: 58
1716 23:54:46.378346 [Byte1]: 58
1717 23:54:46.382219
1718 23:54:46.382648 Set Vref, RX VrefLevel [Byte0]: 59
1719 23:54:46.386270 [Byte1]: 59
1720 23:54:46.390063
1721 23:54:46.390142 Set Vref, RX VrefLevel [Byte0]: 60
1722 23:54:46.393281 [Byte1]: 60
1723 23:54:46.397421
1724 23:54:46.397852 Set Vref, RX VrefLevel [Byte0]: 61
1725 23:54:46.401012 [Byte1]: 61
1726 23:54:46.405244
1727 23:54:46.405657 Set Vref, RX VrefLevel [Byte0]: 62
1728 23:54:46.408379 [Byte1]: 62
1729 23:54:46.412593
1730 23:54:46.413050 Set Vref, RX VrefLevel [Byte0]: 63
1731 23:54:46.416269 [Byte1]: 63
1732 23:54:46.420260
1733 23:54:46.420670 Set Vref, RX VrefLevel [Byte0]: 64
1734 23:54:46.423603 [Byte1]: 64
1735 23:54:46.427979
1736 23:54:46.428386 Set Vref, RX VrefLevel [Byte0]: 65
1737 23:54:46.431616 [Byte1]: 65
1738 23:54:46.435663
1739 23:54:46.436069 Set Vref, RX VrefLevel [Byte0]: 66
1740 23:54:46.438713 [Byte1]: 66
1741 23:54:46.443022
1742 23:54:46.443432 Set Vref, RX VrefLevel [Byte0]: 67
1743 23:54:46.446819 [Byte1]: 67
1744 23:54:46.450615
1745 23:54:46.451025 Set Vref, RX VrefLevel [Byte0]: 68
1746 23:54:46.454067 [Byte1]: 68
1747 23:54:46.458135
1748 23:54:46.458558 Set Vref, RX VrefLevel [Byte0]: 69
1749 23:54:46.461668 [Byte1]: 69
1750 23:54:46.466250
1751 23:54:46.466769 Set Vref, RX VrefLevel [Byte0]: 70
1752 23:54:46.469402 [Byte1]: 70
1753 23:54:46.473598
1754 23:54:46.474004 Set Vref, RX VrefLevel [Byte0]: 71
1755 23:54:46.476887 [Byte1]: 71
1756 23:54:46.481179
1757 23:54:46.481658 Set Vref, RX VrefLevel [Byte0]: 72
1758 23:54:46.484432 [Byte1]: 72
1759 23:54:46.488688
1760 23:54:46.489266 Set Vref, RX VrefLevel [Byte0]: 73
1761 23:54:46.492346 [Byte1]: 73
1762 23:54:46.496299
1763 23:54:46.496690 Set Vref, RX VrefLevel [Byte0]: 74
1764 23:54:46.499610 [Byte1]: 74
1765 23:54:46.504002
1766 23:54:46.504413 Set Vref, RX VrefLevel [Byte0]: 75
1767 23:54:46.507248 [Byte1]: 75
1768 23:54:46.511412
1769 23:54:46.511839 Set Vref, RX VrefLevel [Byte0]: 76
1770 23:54:46.514824 [Byte1]: 76
1771 23:54:46.519449
1772 23:54:46.519856 Set Vref, RX VrefLevel [Byte0]: 77
1773 23:54:46.522420 [Byte1]: 77
1774 23:54:46.527066
1775 23:54:46.527489 Set Vref, RX VrefLevel [Byte0]: 78
1776 23:54:46.529860 [Byte1]: 78
1777 23:54:46.534636
1778 23:54:46.535045 Final RX Vref Byte 0 = 61 to rank0
1779 23:54:46.537616 Final RX Vref Byte 1 = 59 to rank0
1780 23:54:46.541380 Final RX Vref Byte 0 = 61 to rank1
1781 23:54:46.544339 Final RX Vref Byte 1 = 59 to rank1==
1782 23:54:46.547678 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 23:54:46.551105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 23:54:46.554449 ==
1785 23:54:46.554862 DQS Delay:
1786 23:54:46.555192 DQS0 = 0, DQS1 = 0
1787 23:54:46.558157 DQM Delay:
1788 23:54:46.558596 DQM0 = 83, DQM1 = 74
1789 23:54:46.560938 DQ Delay:
1790 23:54:46.564093 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1791 23:54:46.564200 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1792 23:54:46.567679 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1793 23:54:46.570920 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1794 23:54:46.571000
1795 23:54:46.571063
1796 23:54:46.581343 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1797 23:54:46.585191 CH1 RK0: MR19=606, MR18=2C02
1798 23:54:46.587749 CH1_RK0: MR19=0x606, MR18=0x2C02, DQSOSC=398, MR23=63, INC=93, DEC=62
1799 23:54:46.591360
1800 23:54:46.594507 ----->DramcWriteLeveling(PI) begin...
1801 23:54:46.594589 ==
1802 23:54:46.597857 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 23:54:46.601527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 23:54:46.601613 ==
1805 23:54:46.605012 Write leveling (Byte 0): 29 => 29
1806 23:54:46.608334 Write leveling (Byte 1): 28 => 28
1807 23:54:46.611541 DramcWriteLeveling(PI) end<-----
1808 23:54:46.611641
1809 23:54:46.611719 ==
1810 23:54:46.615119 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 23:54:46.617828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 23:54:46.617938 ==
1813 23:54:46.621369 [Gating] SW mode calibration
1814 23:54:46.628066 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 23:54:46.631567 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 23:54:46.637978 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1817 23:54:46.641817 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1818 23:54:46.645114 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:54:46.651984 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:54:46.655348 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:54:46.658559 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:54:46.665310 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:54:46.668937 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:54:46.672265 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:54:46.678938 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:54:46.682256 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:54:46.685451 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1828 23:54:46.688806 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:54:46.695377 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1830 23:54:46.698798 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1831 23:54:46.702016 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1832 23:54:46.708959 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1833 23:54:46.711831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1834 23:54:46.715503 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1835 23:54:46.722362 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:54:46.726154 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:54:46.729476 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:54:46.735859 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:54:46.739421 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:54:46.742880 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:54:46.745742 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
1842 23:54:46.752761 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1843 23:54:46.755816 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1844 23:54:46.759663 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:54:46.766345 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 23:54:46.769636 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 23:54:46.773191 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 23:54:46.779578 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 23:54:46.783271 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 1)
1850 23:54:46.785973 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1851 23:54:46.793395 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:54:46.796519 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:54:46.799881 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:54:46.803065 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:54:46.809880 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:54:46.813317 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:54:46.816672 0 11 4 | B1->B0 | 2a2a 3535 | 0 0 | (0 0) (0 0)
1858 23:54:46.823079 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1859 23:54:46.826526 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:54:46.829956 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:54:46.836637 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:54:46.839723 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 23:54:46.843445 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 23:54:46.850074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 23:54:46.853645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1866 23:54:46.856698 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1867 23:54:46.863123 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:54:46.866687 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:54:46.870373 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:54:46.873213 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:54:46.880052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:54:46.883595 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:54:46.886939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:54:46.893514 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:54:46.897023 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:54:46.900879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:54:46.907093 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:54:46.910690 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:54:46.913513 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:54:46.920460 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:54:46.923769 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1882 23:54:46.927386 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 23:54:46.930725 Total UI for P1: 0, mck2ui 16
1884 23:54:46.933941 best dqsien dly found for B0: ( 0, 14, 4)
1885 23:54:46.937560 Total UI for P1: 0, mck2ui 16
1886 23:54:46.940812 best dqsien dly found for B1: ( 0, 14, 4)
1887 23:54:46.944266 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1888 23:54:46.947809 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1889 23:54:46.948271
1890 23:54:46.950993 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 23:54:46.954265 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1892 23:54:46.957847 [Gating] SW calibration Done
1893 23:54:46.958399 ==
1894 23:54:46.960798 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 23:54:46.964595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 23:54:46.967484 ==
1897 23:54:46.967973 RX Vref Scan: 0
1898 23:54:46.968491
1899 23:54:46.970792 RX Vref 0 -> 0, step: 1
1900 23:54:46.971260
1901 23:54:46.974356 RX Delay -130 -> 252, step: 16
1902 23:54:46.977671 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1903 23:54:46.981012 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1904 23:54:46.983908 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1905 23:54:46.987511 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1906 23:54:46.991171 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1907 23:54:46.998061 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1908 23:54:47.001478 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1909 23:54:47.004662 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1910 23:54:47.007987 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1911 23:54:47.011368 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1912 23:54:47.017643 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1913 23:54:47.021150 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1914 23:54:47.024806 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1915 23:54:47.028236 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1916 23:54:47.031670 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1917 23:54:47.037904 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1918 23:54:47.038356 ==
1919 23:54:47.040850 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 23:54:47.044601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 23:54:47.045117 ==
1922 23:54:47.045554 DQS Delay:
1923 23:54:47.047848 DQS0 = 0, DQS1 = 0
1924 23:54:47.048265 DQM Delay:
1925 23:54:47.051315 DQM0 = 81, DQM1 = 77
1926 23:54:47.051727 DQ Delay:
1927 23:54:47.054630 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1928 23:54:47.057938 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1929 23:54:47.060942 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1930 23:54:47.064571 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1931 23:54:47.065009
1932 23:54:47.065343
1933 23:54:47.065650 ==
1934 23:54:47.067848 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 23:54:47.071416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 23:54:47.071833 ==
1937 23:54:47.072160
1938 23:54:47.074763
1939 23:54:47.075179 TX Vref Scan disable
1940 23:54:47.077883 == TX Byte 0 ==
1941 23:54:47.081583 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 23:54:47.084836 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 23:54:47.088139 == TX Byte 1 ==
1944 23:54:47.091049 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1945 23:54:47.094956 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1946 23:54:47.095370 ==
1947 23:54:47.097849 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 23:54:47.104969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 23:54:47.105641 ==
1950 23:54:47.116199 TX Vref=22, minBit 1, minWin=27, winSum=442
1951 23:54:47.119423 TX Vref=24, minBit 1, minWin=27, winSum=443
1952 23:54:47.122746 TX Vref=26, minBit 1, minWin=27, winSum=445
1953 23:54:47.126077 TX Vref=28, minBit 12, minWin=27, winSum=448
1954 23:54:47.129457 TX Vref=30, minBit 0, minWin=28, winSum=452
1955 23:54:47.132942 TX Vref=32, minBit 0, minWin=28, winSum=449
1956 23:54:47.140048 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1957 23:54:47.140550
1958 23:54:47.143323 Final TX Range 1 Vref 30
1959 23:54:47.143744
1960 23:54:47.144064 ==
1961 23:54:47.146508 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 23:54:47.149931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 23:54:47.150397 ==
1964 23:54:47.150737
1965 23:54:47.151043
1966 23:54:47.153194 TX Vref Scan disable
1967 23:54:47.156635 == TX Byte 0 ==
1968 23:54:47.160201 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 23:54:47.163432 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 23:54:47.166593 == TX Byte 1 ==
1971 23:54:47.170048 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1972 23:54:47.173303 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1973 23:54:47.173712
1974 23:54:47.176827 [DATLAT]
1975 23:54:47.177340 Freq=800, CH1 RK1
1976 23:54:47.177682
1977 23:54:47.179879 DATLAT Default: 0xa
1978 23:54:47.180299 0, 0xFFFF, sum = 0
1979 23:54:47.183292 1, 0xFFFF, sum = 0
1980 23:54:47.183721 2, 0xFFFF, sum = 0
1981 23:54:47.186841 3, 0xFFFF, sum = 0
1982 23:54:47.187253 4, 0xFFFF, sum = 0
1983 23:54:47.189752 5, 0xFFFF, sum = 0
1984 23:54:47.190177 6, 0xFFFF, sum = 0
1985 23:54:47.193238 7, 0xFFFF, sum = 0
1986 23:54:47.193654 8, 0xFFFF, sum = 0
1987 23:54:47.196892 9, 0x0, sum = 1
1988 23:54:47.197417 10, 0x0, sum = 2
1989 23:54:47.200059 11, 0x0, sum = 3
1990 23:54:47.200459 12, 0x0, sum = 4
1991 23:54:47.203569 best_step = 10
1992 23:54:47.203982
1993 23:54:47.204510 ==
1994 23:54:47.207280 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 23:54:47.210192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 23:54:47.210642 ==
1997 23:54:47.211224 RX Vref Scan: 0
1998 23:54:47.211833
1999 23:54:47.213570 RX Vref 0 -> 0, step: 1
2000 23:54:47.213993
2001 23:54:47.217439 RX Delay -95 -> 252, step: 8
2002 23:54:47.220280 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2003 23:54:47.227149 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2004 23:54:47.230685 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2005 23:54:47.233368 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2006 23:54:47.237102 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
2007 23:54:47.240202 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2008 23:54:47.246778 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2009 23:54:47.250406 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2010 23:54:47.254361 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2011 23:54:47.257163 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2012 23:54:47.260283 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2013 23:54:47.266892 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2014 23:54:47.271186 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2015 23:54:47.273853 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2016 23:54:47.276763 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2017 23:54:47.280752 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2018 23:54:47.281228 ==
2019 23:54:47.283542 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 23:54:47.290406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 23:54:47.290879 ==
2022 23:54:47.291341 DQS Delay:
2023 23:54:47.293756 DQS0 = 0, DQS1 = 0
2024 23:54:47.294180 DQM Delay:
2025 23:54:47.294648 DQM0 = 79, DQM1 = 75
2026 23:54:47.297345 DQ Delay:
2027 23:54:47.300841 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2028 23:54:47.303787 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
2029 23:54:47.307490 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2030 23:54:47.310868 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2031 23:54:47.311295
2032 23:54:47.311757
2033 23:54:47.317628 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2034 23:54:47.320617 CH1 RK1: MR19=606, MR18=1F29
2035 23:54:47.327569 CH1_RK1: MR19=0x606, MR18=0x1F29, DQSOSC=399, MR23=63, INC=92, DEC=61
2036 23:54:47.330653 [RxdqsGatingPostProcess] freq 800
2037 23:54:47.333795 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 23:54:47.337268 Pre-setting of DQS Precalculation
2039 23:54:47.343813 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 23:54:47.350590 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 23:54:47.357196 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 23:54:47.357629
2043 23:54:47.358060
2044 23:54:47.360417 [Calibration Summary] 1600 Mbps
2045 23:54:47.360850 CH 0, Rank 0
2046 23:54:47.364350 SW Impedance : PASS
2047 23:54:47.367563 DUTY Scan : NO K
2048 23:54:47.368083 ZQ Calibration : PASS
2049 23:54:47.370533 Jitter Meter : NO K
2050 23:54:47.373965 CBT Training : PASS
2051 23:54:47.374387 Write leveling : PASS
2052 23:54:47.377490 RX DQS gating : PASS
2053 23:54:47.377913 RX DQ/DQS(RDDQC) : PASS
2054 23:54:47.381341 TX DQ/DQS : PASS
2055 23:54:47.383930 RX DATLAT : PASS
2056 23:54:47.384400 RX DQ/DQS(Engine): PASS
2057 23:54:47.388079 TX OE : NO K
2058 23:54:47.388574 All Pass.
2059 23:54:47.389112
2060 23:54:47.390593 CH 0, Rank 1
2061 23:54:47.391003 SW Impedance : PASS
2062 23:54:47.394115 DUTY Scan : NO K
2063 23:54:47.397518 ZQ Calibration : PASS
2064 23:54:47.397961 Jitter Meter : NO K
2065 23:54:47.400474 CBT Training : PASS
2066 23:54:47.404421 Write leveling : PASS
2067 23:54:47.404829 RX DQS gating : PASS
2068 23:54:47.407765 RX DQ/DQS(RDDQC) : PASS
2069 23:54:47.410812 TX DQ/DQS : PASS
2070 23:54:47.411213 RX DATLAT : PASS
2071 23:54:47.414334 RX DQ/DQS(Engine): PASS
2072 23:54:47.414769 TX OE : NO K
2073 23:54:47.417970 All Pass.
2074 23:54:47.418439
2075 23:54:47.418787 CH 1, Rank 0
2076 23:54:47.420766 SW Impedance : PASS
2077 23:54:47.421229 DUTY Scan : NO K
2078 23:54:47.424118 ZQ Calibration : PASS
2079 23:54:47.427549 Jitter Meter : NO K
2080 23:54:47.427906 CBT Training : PASS
2081 23:54:47.431305 Write leveling : PASS
2082 23:54:47.434394 RX DQS gating : PASS
2083 23:54:47.434827 RX DQ/DQS(RDDQC) : PASS
2084 23:54:47.437316 TX DQ/DQS : PASS
2085 23:54:47.442048 RX DATLAT : PASS
2086 23:54:47.442509 RX DQ/DQS(Engine): PASS
2087 23:54:47.444411 TX OE : NO K
2088 23:54:47.444825 All Pass.
2089 23:54:47.445209
2090 23:54:47.447569 CH 1, Rank 1
2091 23:54:47.448233 SW Impedance : PASS
2092 23:54:47.451537 DUTY Scan : NO K
2093 23:54:47.451950 ZQ Calibration : PASS
2094 23:54:47.454680 Jitter Meter : NO K
2095 23:54:47.458194 CBT Training : PASS
2096 23:54:47.458630 Write leveling : PASS
2097 23:54:47.461285 RX DQS gating : PASS
2098 23:54:47.464220 RX DQ/DQS(RDDQC) : PASS
2099 23:54:47.464626 TX DQ/DQS : PASS
2100 23:54:47.467872 RX DATLAT : PASS
2101 23:54:47.471776 RX DQ/DQS(Engine): PASS
2102 23:54:47.472238 TX OE : NO K
2103 23:54:47.474882 All Pass.
2104 23:54:47.475437
2105 23:54:47.475894 DramC Write-DBI off
2106 23:54:47.477948 PER_BANK_REFRESH: Hybrid Mode
2107 23:54:47.478393 TX_TRACKING: ON
2108 23:54:47.481359 [GetDramInforAfterCalByMRR] Vendor 6.
2109 23:54:47.484646 [GetDramInforAfterCalByMRR] Revision 606.
2110 23:54:47.491158 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 23:54:47.491600 MR0 0x3b3b
2112 23:54:47.492014 MR8 0x5151
2113 23:54:47.494935 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 23:54:47.495473
2115 23:54:47.498273 MR0 0x3b3b
2116 23:54:47.498711 MR8 0x5151
2117 23:54:47.502080 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 23:54:47.502487
2119 23:54:47.512008 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 23:54:47.514614 [FAST_K] Save calibration result to emmc
2121 23:54:47.518213 [FAST_K] Save calibration result to emmc
2122 23:54:47.522108 dram_init: config_dvfs: 1
2123 23:54:47.525027 dramc_set_vcore_voltage set vcore to 662500
2124 23:54:47.525448 Read voltage for 1200, 2
2125 23:54:47.528703 Vio18 = 0
2126 23:54:47.529266 Vcore = 662500
2127 23:54:47.529606 Vdram = 0
2128 23:54:47.531550 Vddq = 0
2129 23:54:47.531957 Vmddr = 0
2130 23:54:47.535340 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 23:54:47.541976 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 23:54:47.544928 MEM_TYPE=3, freq_sel=15
2133 23:54:47.548427 sv_algorithm_assistance_LP4_1600
2134 23:54:47.551904 ============ PULL DRAM RESETB DOWN ============
2135 23:54:47.555123 ========== PULL DRAM RESETB DOWN end =========
2136 23:54:47.558715 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 23:54:47.562662 ===================================
2138 23:54:47.565726 LPDDR4 DRAM CONFIGURATION
2139 23:54:47.568690 ===================================
2140 23:54:47.572073 EX_ROW_EN[0] = 0x0
2141 23:54:47.572588 EX_ROW_EN[1] = 0x0
2142 23:54:47.575169 LP4Y_EN = 0x0
2143 23:54:47.575577 WORK_FSP = 0x0
2144 23:54:47.579061 WL = 0x4
2145 23:54:47.579473 RL = 0x4
2146 23:54:47.581855 BL = 0x2
2147 23:54:47.582263 RPST = 0x0
2148 23:54:47.585474 RD_PRE = 0x0
2149 23:54:47.585909 WR_PRE = 0x1
2150 23:54:47.589265 WR_PST = 0x0
2151 23:54:47.589706 DBI_WR = 0x0
2152 23:54:47.592054 DBI_RD = 0x0
2153 23:54:47.592459 OTF = 0x1
2154 23:54:47.595250 ===================================
2155 23:54:47.599130 ===================================
2156 23:54:47.602331 ANA top config
2157 23:54:47.605531 ===================================
2158 23:54:47.608655 DLL_ASYNC_EN = 0
2159 23:54:47.609168 ALL_SLAVE_EN = 0
2160 23:54:47.611909 NEW_RANK_MODE = 1
2161 23:54:47.615604 DLL_IDLE_MODE = 1
2162 23:54:47.619083 LP45_APHY_COMB_EN = 1
2163 23:54:47.619495 TX_ODT_DIS = 1
2164 23:54:47.622081 NEW_8X_MODE = 1
2165 23:54:47.625700 ===================================
2166 23:54:47.628630 ===================================
2167 23:54:47.632535 data_rate = 2400
2168 23:54:47.635375 CKR = 1
2169 23:54:47.638898 DQ_P2S_RATIO = 8
2170 23:54:47.642712 ===================================
2171 23:54:47.643229 CA_P2S_RATIO = 8
2172 23:54:47.645386 DQ_CA_OPEN = 0
2173 23:54:47.649210 DQ_SEMI_OPEN = 0
2174 23:54:47.652433 CA_SEMI_OPEN = 0
2175 23:54:47.655682 CA_FULL_RATE = 0
2176 23:54:47.659149 DQ_CKDIV4_EN = 0
2177 23:54:47.659556 CA_CKDIV4_EN = 0
2178 23:54:47.662767 CA_PREDIV_EN = 0
2179 23:54:47.665628 PH8_DLY = 17
2180 23:54:47.668910 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 23:54:47.672904 DQ_AAMCK_DIV = 4
2182 23:54:47.675941 CA_AAMCK_DIV = 4
2183 23:54:47.676234 CA_ADMCK_DIV = 4
2184 23:54:47.679192 DQ_TRACK_CA_EN = 0
2185 23:54:47.682550 CA_PICK = 1200
2186 23:54:47.685761 CA_MCKIO = 1200
2187 23:54:47.689203 MCKIO_SEMI = 0
2188 23:54:47.692359 PLL_FREQ = 2366
2189 23:54:47.696178 DQ_UI_PI_RATIO = 32
2190 23:54:47.696306 CA_UI_PI_RATIO = 0
2191 23:54:47.699059 ===================================
2192 23:54:47.702288 ===================================
2193 23:54:47.705482 memory_type:LPDDR4
2194 23:54:47.709129 GP_NUM : 10
2195 23:54:47.709250 SRAM_EN : 1
2196 23:54:47.712381 MD32_EN : 0
2197 23:54:47.715887 ===================================
2198 23:54:47.719545 [ANA_INIT] >>>>>>>>>>>>>>
2199 23:54:47.720030 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 23:54:47.722534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 23:54:47.726375 ===================================
2202 23:54:47.729585 data_rate = 2400,PCW = 0X5b00
2203 23:54:47.732715 ===================================
2204 23:54:47.736066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 23:54:47.742508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 23:54:47.749675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 23:54:47.752918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 23:54:47.755697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 23:54:47.759649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 23:54:47.762640 [ANA_INIT] flow start
2211 23:54:47.762740 [ANA_INIT] PLL >>>>>>>>
2212 23:54:47.766298 [ANA_INIT] PLL <<<<<<<<
2213 23:54:47.769400 [ANA_INIT] MIDPI >>>>>>>>
2214 23:54:47.769499 [ANA_INIT] MIDPI <<<<<<<<
2215 23:54:47.772879 [ANA_INIT] DLL >>>>>>>>
2216 23:54:47.775960 [ANA_INIT] DLL <<<<<<<<
2217 23:54:47.776060 [ANA_INIT] flow end
2218 23:54:47.779245 ============ LP4 DIFF to SE enter ============
2219 23:54:47.786491 ============ LP4 DIFF to SE exit ============
2220 23:54:47.786594 [ANA_INIT] <<<<<<<<<<<<<
2221 23:54:47.789642 [Flow] Enable top DCM control >>>>>
2222 23:54:47.793189 [Flow] Enable top DCM control <<<<<
2223 23:54:47.795988 Enable DLL master slave shuffle
2224 23:54:47.802813 ==============================================================
2225 23:54:47.802914 Gating Mode config
2226 23:54:47.809853 ==============================================================
2227 23:54:47.812990 Config description:
2228 23:54:47.822737 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 23:54:47.829640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 23:54:47.833373 SELPH_MODE 0: By rank 1: By Phase
2231 23:54:47.839764 ==============================================================
2232 23:54:47.839915 GAT_TRACK_EN = 1
2233 23:54:47.843261 RX_GATING_MODE = 2
2234 23:54:47.846345 RX_GATING_TRACK_MODE = 2
2235 23:54:47.850096 SELPH_MODE = 1
2236 23:54:47.853275 PICG_EARLY_EN = 1
2237 23:54:47.856874 VALID_LAT_VALUE = 1
2238 23:54:47.863291 ==============================================================
2239 23:54:47.866654 Enter into Gating configuration >>>>
2240 23:54:47.870077 Exit from Gating configuration <<<<
2241 23:54:47.873606 Enter into DVFS_PRE_config >>>>>
2242 23:54:47.883723 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 23:54:47.887726 Exit from DVFS_PRE_config <<<<<
2244 23:54:47.890288 Enter into PICG configuration >>>>
2245 23:54:47.893830 Exit from PICG configuration <<<<
2246 23:54:47.894239 [RX_INPUT] configuration >>>>>
2247 23:54:47.897132 [RX_INPUT] configuration <<<<<
2248 23:54:47.904206 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 23:54:47.907664 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 23:54:47.914104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 23:54:47.920843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 23:54:47.927634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 23:54:47.934385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 23:54:47.937844 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 23:54:47.941165 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 23:54:47.944367 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 23:54:47.950926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 23:54:47.954152 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 23:54:47.957566 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 23:54:47.961075 ===================================
2261 23:54:47.964414 LPDDR4 DRAM CONFIGURATION
2262 23:54:47.967836 ===================================
2263 23:54:47.968245 EX_ROW_EN[0] = 0x0
2264 23:54:47.970909 EX_ROW_EN[1] = 0x0
2265 23:54:47.974650 LP4Y_EN = 0x0
2266 23:54:47.975194 WORK_FSP = 0x0
2267 23:54:47.977429 WL = 0x4
2268 23:54:47.977808 RL = 0x4
2269 23:54:47.980969 BL = 0x2
2270 23:54:47.981452 RPST = 0x0
2271 23:54:47.984179 RD_PRE = 0x0
2272 23:54:47.984547 WR_PRE = 0x1
2273 23:54:47.987487 WR_PST = 0x0
2274 23:54:47.988060 DBI_WR = 0x0
2275 23:54:47.990846 DBI_RD = 0x0
2276 23:54:47.991310 OTF = 0x1
2277 23:54:47.994416 ===================================
2278 23:54:47.997725 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 23:54:48.004939 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 23:54:48.008194 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 23:54:48.011692 ===================================
2282 23:54:48.014709 LPDDR4 DRAM CONFIGURATION
2283 23:54:48.018185 ===================================
2284 23:54:48.018612 EX_ROW_EN[0] = 0x10
2285 23:54:48.021481 EX_ROW_EN[1] = 0x0
2286 23:54:48.021908 LP4Y_EN = 0x0
2287 23:54:48.025236 WORK_FSP = 0x0
2288 23:54:48.025660 WL = 0x4
2289 23:54:48.028022 RL = 0x4
2290 23:54:48.028448 BL = 0x2
2291 23:54:48.031409 RPST = 0x0
2292 23:54:48.031833 RD_PRE = 0x0
2293 23:54:48.034701 WR_PRE = 0x1
2294 23:54:48.035233 WR_PST = 0x0
2295 23:54:48.038447 DBI_WR = 0x0
2296 23:54:48.038957 DBI_RD = 0x0
2297 23:54:48.041277 OTF = 0x1
2298 23:54:48.044601 ===================================
2299 23:54:48.051511 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 23:54:48.051951 ==
2301 23:54:48.055039 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 23:54:48.058425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 23:54:48.058938 ==
2304 23:54:48.061548 [Duty_Offset_Calibration]
2305 23:54:48.061906 B0:2 B1:-1 CA:1
2306 23:54:48.062139
2307 23:54:48.064916 [DutyScan_Calibration_Flow] k_type=0
2308 23:54:48.074687
2309 23:54:48.075075 ==CLK 0==
2310 23:54:48.078006 Final CLK duty delay cell = -4
2311 23:54:48.081333 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2312 23:54:48.084583 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2313 23:54:48.088214 [-4] AVG Duty = 4953%(X100)
2314 23:54:48.088622
2315 23:54:48.091538 CH0 CLK Duty spec in!! Max-Min= 156%
2316 23:54:48.095072 [DutyScan_Calibration_Flow] ====Done====
2317 23:54:48.095482
2318 23:54:48.098132 [DutyScan_Calibration_Flow] k_type=1
2319 23:54:48.113787
2320 23:54:48.114191 ==DQS 0 ==
2321 23:54:48.117429 Final DQS duty delay cell = 0
2322 23:54:48.120364 [0] MAX Duty = 5125%(X100), DQS PI = 48
2323 23:54:48.124027 [0] MIN Duty = 5000%(X100), DQS PI = 14
2324 23:54:48.124543 [0] AVG Duty = 5062%(X100)
2325 23:54:48.127271
2326 23:54:48.127787 ==DQS 1 ==
2327 23:54:48.130578 Final DQS duty delay cell = -4
2328 23:54:48.133739 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2329 23:54:48.137290 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2330 23:54:48.137702 [-4] AVG Duty = 5046%(X100)
2331 23:54:48.141125
2332 23:54:48.143745 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2333 23:54:48.144156
2334 23:54:48.147498 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2335 23:54:48.150554 [DutyScan_Calibration_Flow] ====Done====
2336 23:54:48.150968
2337 23:54:48.154509 [DutyScan_Calibration_Flow] k_type=3
2338 23:54:48.170698
2339 23:54:48.171109 ==DQM 0 ==
2340 23:54:48.173549 Final DQM duty delay cell = 0
2341 23:54:48.177756 [0] MAX Duty = 5000%(X100), DQS PI = 54
2342 23:54:48.180601 [0] MIN Duty = 4907%(X100), DQS PI = 2
2343 23:54:48.181123 [0] AVG Duty = 4953%(X100)
2344 23:54:48.181459
2345 23:54:48.184046 ==DQM 1 ==
2346 23:54:48.187242 Final DQM duty delay cell = 0
2347 23:54:48.190592 [0] MAX Duty = 5124%(X100), DQS PI = 62
2348 23:54:48.193810 [0] MIN Duty = 4969%(X100), DQS PI = 10
2349 23:54:48.194218 [0] AVG Duty = 5046%(X100)
2350 23:54:48.197444
2351 23:54:48.200693 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2352 23:54:48.201126
2353 23:54:48.203908 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2354 23:54:48.207434 [DutyScan_Calibration_Flow] ====Done====
2355 23:54:48.207845
2356 23:54:48.210418 [DutyScan_Calibration_Flow] k_type=2
2357 23:54:48.225898
2358 23:54:48.226414 ==DQ 0 ==
2359 23:54:48.229404 Final DQ duty delay cell = -4
2360 23:54:48.232756 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2361 23:54:48.236188 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2362 23:54:48.236788 [-4] AVG Duty = 4953%(X100)
2363 23:54:48.239568
2364 23:54:48.239993 ==DQ 1 ==
2365 23:54:48.243077 Final DQ duty delay cell = 0
2366 23:54:48.246429 [0] MAX Duty = 5031%(X100), DQS PI = 16
2367 23:54:48.249214 [0] MIN Duty = 4907%(X100), DQS PI = 46
2368 23:54:48.249640 [0] AVG Duty = 4969%(X100)
2369 23:54:48.250068
2370 23:54:48.252791 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2371 23:54:48.256462
2372 23:54:48.259677 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2373 23:54:48.263390 [DutyScan_Calibration_Flow] ====Done====
2374 23:54:48.263796 ==
2375 23:54:48.266391 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 23:54:48.269572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 23:54:48.269998 ==
2378 23:54:48.273232 [Duty_Offset_Calibration]
2379 23:54:48.273637 B0:1 B1:1 CA:2
2380 23:54:48.273993
2381 23:54:48.276302 [DutyScan_Calibration_Flow] k_type=0
2382 23:54:48.286223
2383 23:54:48.286628 ==CLK 0==
2384 23:54:48.289892 Final CLK duty delay cell = 0
2385 23:54:48.292934 [0] MAX Duty = 5125%(X100), DQS PI = 24
2386 23:54:48.296163 [0] MIN Duty = 4969%(X100), DQS PI = 38
2387 23:54:48.296589 [0] AVG Duty = 5047%(X100)
2388 23:54:48.299617
2389 23:54:48.302911 CH1 CLK Duty spec in!! Max-Min= 156%
2390 23:54:48.306624 [DutyScan_Calibration_Flow] ====Done====
2391 23:54:48.307029
2392 23:54:48.309743 [DutyScan_Calibration_Flow] k_type=1
2393 23:54:48.325469
2394 23:54:48.325950 ==DQS 0 ==
2395 23:54:48.329789 Final DQS duty delay cell = 0
2396 23:54:48.332827 [0] MAX Duty = 5031%(X100), DQS PI = 18
2397 23:54:48.335554 [0] MIN Duty = 4844%(X100), DQS PI = 48
2398 23:54:48.335962 [0] AVG Duty = 4937%(X100)
2399 23:54:48.339425
2400 23:54:48.339828 ==DQS 1 ==
2401 23:54:48.342435 Final DQS duty delay cell = 0
2402 23:54:48.345618 [0] MAX Duty = 5062%(X100), DQS PI = 36
2403 23:54:48.349510 [0] MIN Duty = 4907%(X100), DQS PI = 30
2404 23:54:48.349921 [0] AVG Duty = 4984%(X100)
2405 23:54:48.350246
2406 23:54:48.355859 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2407 23:54:48.356379
2408 23:54:48.358963 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2409 23:54:48.362263 [DutyScan_Calibration_Flow] ====Done====
2410 23:54:48.362669
2411 23:54:48.365748 [DutyScan_Calibration_Flow] k_type=3
2412 23:54:48.382282
2413 23:54:48.382859 ==DQM 0 ==
2414 23:54:48.386708 Final DQM duty delay cell = 0
2415 23:54:48.389060 [0] MAX Duty = 5093%(X100), DQS PI = 18
2416 23:54:48.391942 [0] MIN Duty = 4875%(X100), DQS PI = 50
2417 23:54:48.395470 [0] AVG Duty = 4984%(X100)
2418 23:54:48.396014
2419 23:54:48.396373 ==DQM 1 ==
2420 23:54:48.398794 Final DQM duty delay cell = 0
2421 23:54:48.402056 [0] MAX Duty = 5156%(X100), DQS PI = 62
2422 23:54:48.405532 [0] MIN Duty = 4938%(X100), DQS PI = 22
2423 23:54:48.409377 [0] AVG Duty = 5047%(X100)
2424 23:54:48.409960
2425 23:54:48.412374 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2426 23:54:48.412851
2427 23:54:48.415480 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2428 23:54:48.418693 [DutyScan_Calibration_Flow] ====Done====
2429 23:54:48.419191
2430 23:54:48.422565 [DutyScan_Calibration_Flow] k_type=2
2431 23:54:48.438727
2432 23:54:48.439357 ==DQ 0 ==
2433 23:54:48.442040 Final DQ duty delay cell = 0
2434 23:54:48.445576 [0] MAX Duty = 5156%(X100), DQS PI = 18
2435 23:54:48.448194 [0] MIN Duty = 4938%(X100), DQS PI = 60
2436 23:54:48.448271 [0] AVG Duty = 5047%(X100)
2437 23:54:48.448333
2438 23:54:48.451727 ==DQ 1 ==
2439 23:54:48.455094 Final DQ duty delay cell = 0
2440 23:54:48.458695 [0] MAX Duty = 5093%(X100), DQS PI = 10
2441 23:54:48.461832 [0] MIN Duty = 5031%(X100), DQS PI = 2
2442 23:54:48.461903 [0] AVG Duty = 5062%(X100)
2443 23:54:48.461970
2444 23:54:48.465810 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2445 23:54:48.465881
2446 23:54:48.468763 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2447 23:54:48.471946 [DutyScan_Calibration_Flow] ====Done====
2448 23:54:48.477321 nWR fixed to 30
2449 23:54:48.480942 [ModeRegInit_LP4] CH0 RK0
2450 23:54:48.481058 [ModeRegInit_LP4] CH0 RK1
2451 23:54:48.483939 [ModeRegInit_LP4] CH1 RK0
2452 23:54:48.487311 [ModeRegInit_LP4] CH1 RK1
2453 23:54:48.487396 match AC timing 7
2454 23:54:48.494237 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 23:54:48.497504 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 23:54:48.501144 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 23:54:48.507633 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 23:54:48.511121 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 23:54:48.511230 ==
2460 23:54:48.514524 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 23:54:48.517575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 23:54:48.517661 ==
2463 23:54:48.524057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 23:54:48.530652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2465 23:54:48.538655 [CA 0] Center 40 (10~71) winsize 62
2466 23:54:48.542306 [CA 1] Center 39 (9~70) winsize 62
2467 23:54:48.545864 [CA 2] Center 36 (6~67) winsize 62
2468 23:54:48.548430 [CA 3] Center 36 (6~66) winsize 61
2469 23:54:48.552695 [CA 4] Center 34 (4~65) winsize 62
2470 23:54:48.555648 [CA 5] Center 34 (4~64) winsize 61
2471 23:54:48.556205
2472 23:54:48.559511 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2473 23:54:48.560023
2474 23:54:48.562202 [CATrainingPosCal] consider 1 rank data
2475 23:54:48.565256 u2DelayCellTimex100 = 270/100 ps
2476 23:54:48.569135 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2477 23:54:48.572342 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2478 23:54:48.578830 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2479 23:54:48.582175 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2480 23:54:48.585575 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2481 23:54:48.589009 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2482 23:54:48.589568
2483 23:54:48.592316 CA PerBit enable=1, Macro0, CA PI delay=34
2484 23:54:48.592867
2485 23:54:48.596218 [CBTSetCACLKResult] CA Dly = 34
2486 23:54:48.596821 CS Dly: 7 (0~38)
2487 23:54:48.597376 ==
2488 23:54:48.599211 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 23:54:48.605672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 23:54:48.606126 ==
2491 23:54:48.609015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 23:54:48.615741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2493 23:54:48.625020 [CA 0] Center 39 (9~70) winsize 62
2494 23:54:48.627772 [CA 1] Center 40 (10~70) winsize 61
2495 23:54:48.631920 [CA 2] Center 36 (6~67) winsize 62
2496 23:54:48.634405 [CA 3] Center 36 (5~67) winsize 63
2497 23:54:48.638133 [CA 4] Center 34 (4~65) winsize 62
2498 23:54:48.641371 [CA 5] Center 34 (4~64) winsize 61
2499 23:54:48.641841
2500 23:54:48.644919 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 23:54:48.645425
2502 23:54:48.648770 [CATrainingPosCal] consider 2 rank data
2503 23:54:48.652042 u2DelayCellTimex100 = 270/100 ps
2504 23:54:48.655045 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2505 23:54:48.658294 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2506 23:54:48.664883 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2507 23:54:48.668478 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2508 23:54:48.671479 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2509 23:54:48.675123 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2510 23:54:48.675680
2511 23:54:48.678765 CA PerBit enable=1, Macro0, CA PI delay=34
2512 23:54:48.679218
2513 23:54:48.682010 [CBTSetCACLKResult] CA Dly = 34
2514 23:54:48.682461 CS Dly: 8 (0~41)
2515 23:54:48.682823
2516 23:54:48.685207 ----->DramcWriteLeveling(PI) begin...
2517 23:54:48.688865 ==
2518 23:54:48.689471 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 23:54:48.695086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 23:54:48.695645 ==
2521 23:54:48.698747 Write leveling (Byte 0): 31 => 31
2522 23:54:48.701892 Write leveling (Byte 1): 29 => 29
2523 23:54:48.702449 DramcWriteLeveling(PI) end<-----
2524 23:54:48.704957
2525 23:54:48.705440 ==
2526 23:54:48.708156 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 23:54:48.711956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 23:54:48.712652 ==
2529 23:54:48.715506 [Gating] SW mode calibration
2530 23:54:48.722184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 23:54:48.725149 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 23:54:48.732086 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 23:54:48.736230 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2534 23:54:48.739621 0 15 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2535 23:54:48.745304 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 23:54:48.749079 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 23:54:48.751895 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 23:54:48.758724 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 23:54:48.761950 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 23:54:48.765728 1 0 0 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
2541 23:54:48.768734 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2542 23:54:48.775537 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:54:48.779432 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 23:54:48.782691 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 23:54:48.789543 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 23:54:48.792406 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 23:54:48.795801 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 23:54:48.802375 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2549 23:54:48.806018 1 1 4 | B1->B0 | 3d3d 4545 | 1 0 | (0 0) (0 0)
2550 23:54:48.809288 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:54:48.815706 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 23:54:48.819116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 23:54:48.822468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 23:54:48.829466 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 23:54:48.833025 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 23:54:48.836268 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2557 23:54:48.839195 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 23:54:48.845746 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:54:48.849320 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:54:48.852858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:54:48.859541 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:54:48.862591 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:54:48.866253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:54:48.872692 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:54:48.876357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:54:48.879658 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:54:48.886210 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:54:48.890922 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:54:48.892581 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:54:48.896662 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:54:48.903251 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:54:48.906319 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2573 23:54:48.910052 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 23:54:48.913446 Total UI for P1: 0, mck2ui 16
2575 23:54:48.916317 best dqsien dly found for B0: ( 1, 4, 0)
2576 23:54:48.919688 Total UI for P1: 0, mck2ui 16
2577 23:54:48.923158 best dqsien dly found for B1: ( 1, 4, 0)
2578 23:54:48.926433 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2579 23:54:48.929942 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2580 23:54:48.930504
2581 23:54:48.934201 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2582 23:54:48.939973 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2583 23:54:48.940522 [Gating] SW calibration Done
2584 23:54:48.940892 ==
2585 23:54:48.943494 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 23:54:48.949977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 23:54:48.950568 ==
2588 23:54:48.951054 RX Vref Scan: 0
2589 23:54:48.951501
2590 23:54:48.953316 RX Vref 0 -> 0, step: 1
2591 23:54:48.953785
2592 23:54:48.956424 RX Delay -40 -> 252, step: 8
2593 23:54:48.960144 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2594 23:54:48.963635 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2595 23:54:48.966919 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2596 23:54:48.973393 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2597 23:54:48.976313 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2598 23:54:48.979791 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2599 23:54:48.983208 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2600 23:54:48.986688 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2601 23:54:48.990256 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2602 23:54:48.996626 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2603 23:54:49.000042 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2604 23:54:49.003778 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2605 23:54:49.006960 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2606 23:54:49.009989 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2607 23:54:49.016503 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2608 23:54:49.020411 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2609 23:54:49.020967 ==
2610 23:54:49.024001 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 23:54:49.026594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 23:54:49.027056 ==
2613 23:54:49.029832 DQS Delay:
2614 23:54:49.030295 DQS0 = 0, DQS1 = 0
2615 23:54:49.030664 DQM Delay:
2616 23:54:49.033323 DQM0 = 115, DQM1 = 107
2617 23:54:49.033779 DQ Delay:
2618 23:54:49.036891 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2619 23:54:49.040491 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2620 23:54:49.043193 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2621 23:54:49.047547 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2622 23:54:49.048112
2623 23:54:49.050099
2624 23:54:49.050548 ==
2625 23:54:49.053783 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 23:54:49.057396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 23:54:49.057968 ==
2628 23:54:49.058340
2629 23:54:49.058678
2630 23:54:49.060415 TX Vref Scan disable
2631 23:54:49.060866 == TX Byte 0 ==
2632 23:54:49.063603 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2633 23:54:49.070186 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2634 23:54:49.070782 == TX Byte 1 ==
2635 23:54:49.073781 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2636 23:54:49.080321 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2637 23:54:49.080882 ==
2638 23:54:49.083614 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 23:54:49.087291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 23:54:49.087752 ==
2641 23:54:49.099889 TX Vref=22, minBit 7, minWin=24, winSum=417
2642 23:54:49.102743 TX Vref=24, minBit 1, minWin=25, winSum=426
2643 23:54:49.105792 TX Vref=26, minBit 0, minWin=26, winSum=429
2644 23:54:49.109592 TX Vref=28, minBit 4, minWin=26, winSum=435
2645 23:54:49.112771 TX Vref=30, minBit 4, minWin=26, winSum=437
2646 23:54:49.115681 TX Vref=32, minBit 0, minWin=26, winSum=433
2647 23:54:49.122407 [TxChooseVref] Worse bit 4, Min win 26, Win sum 437, Final Vref 30
2648 23:54:49.122960
2649 23:54:49.125727 Final TX Range 1 Vref 30
2650 23:54:49.126184
2651 23:54:49.126544 ==
2652 23:54:49.129114 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 23:54:49.132631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 23:54:49.133233 ==
2655 23:54:49.133616
2656 23:54:49.133962
2657 23:54:49.136053 TX Vref Scan disable
2658 23:54:49.139365 == TX Byte 0 ==
2659 23:54:49.142652 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2660 23:54:49.146059 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2661 23:54:49.149706 == TX Byte 1 ==
2662 23:54:49.153398 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2663 23:54:49.156452 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2664 23:54:49.157048
2665 23:54:49.159367 [DATLAT]
2666 23:54:49.159825 Freq=1200, CH0 RK0
2667 23:54:49.160188
2668 23:54:49.163068 DATLAT Default: 0xd
2669 23:54:49.163627 0, 0xFFFF, sum = 0
2670 23:54:49.166617 1, 0xFFFF, sum = 0
2671 23:54:49.167184 2, 0xFFFF, sum = 0
2672 23:54:49.169876 3, 0xFFFF, sum = 0
2673 23:54:49.170445 4, 0xFFFF, sum = 0
2674 23:54:49.172997 5, 0xFFFF, sum = 0
2675 23:54:49.173574 6, 0xFFFF, sum = 0
2676 23:54:49.176400 7, 0xFFFF, sum = 0
2677 23:54:49.176965 8, 0xFFFF, sum = 0
2678 23:54:49.179866 9, 0xFFFF, sum = 0
2679 23:54:49.180429 10, 0xFFFF, sum = 0
2680 23:54:49.182971 11, 0xFFFF, sum = 0
2681 23:54:49.183434 12, 0x0, sum = 1
2682 23:54:49.186194 13, 0x0, sum = 2
2683 23:54:49.186659 14, 0x0, sum = 3
2684 23:54:49.189425 15, 0x0, sum = 4
2685 23:54:49.189889 best_step = 13
2686 23:54:49.190255
2687 23:54:49.190599 ==
2688 23:54:49.193396 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 23:54:49.199761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 23:54:49.200222 ==
2691 23:54:49.200592 RX Vref Scan: 1
2692 23:54:49.200938
2693 23:54:49.203378 Set Vref Range= 32 -> 127
2694 23:54:49.203940
2695 23:54:49.206597 RX Vref 32 -> 127, step: 1
2696 23:54:49.207058
2697 23:54:49.207425 RX Delay -21 -> 252, step: 4
2698 23:54:49.207770
2699 23:54:49.209607 Set Vref, RX VrefLevel [Byte0]: 32
2700 23:54:49.212773 [Byte1]: 32
2701 23:54:49.217363
2702 23:54:49.217821 Set Vref, RX VrefLevel [Byte0]: 33
2703 23:54:49.221079 [Byte1]: 33
2704 23:54:49.225343
2705 23:54:49.225902 Set Vref, RX VrefLevel [Byte0]: 34
2706 23:54:49.228422 [Byte1]: 34
2707 23:54:49.233528
2708 23:54:49.234086 Set Vref, RX VrefLevel [Byte0]: 35
2709 23:54:49.236733 [Byte1]: 35
2710 23:54:49.241253
2711 23:54:49.241714 Set Vref, RX VrefLevel [Byte0]: 36
2712 23:54:49.244703 [Byte1]: 36
2713 23:54:49.249022
2714 23:54:49.249485 Set Vref, RX VrefLevel [Byte0]: 37
2715 23:54:49.252270 [Byte1]: 37
2716 23:54:49.256753
2717 23:54:49.257270 Set Vref, RX VrefLevel [Byte0]: 38
2718 23:54:49.260019 [Byte1]: 38
2719 23:54:49.264717
2720 23:54:49.265169 Set Vref, RX VrefLevel [Byte0]: 39
2721 23:54:49.267897 [Byte1]: 39
2722 23:54:49.272809
2723 23:54:49.273264 Set Vref, RX VrefLevel [Byte0]: 40
2724 23:54:49.275950 [Byte1]: 40
2725 23:54:49.280688
2726 23:54:49.281158 Set Vref, RX VrefLevel [Byte0]: 41
2727 23:54:49.284184 [Byte1]: 41
2728 23:54:49.288433
2729 23:54:49.288842 Set Vref, RX VrefLevel [Byte0]: 42
2730 23:54:49.292097 [Byte1]: 42
2731 23:54:49.296123
2732 23:54:49.296532 Set Vref, RX VrefLevel [Byte0]: 43
2733 23:54:49.300033 [Byte1]: 43
2734 23:54:49.304541
2735 23:54:49.304955 Set Vref, RX VrefLevel [Byte0]: 44
2736 23:54:49.307775 [Byte1]: 44
2737 23:54:49.312275
2738 23:54:49.312706 Set Vref, RX VrefLevel [Byte0]: 45
2739 23:54:49.315467 [Byte1]: 45
2740 23:54:49.320036
2741 23:54:49.320448 Set Vref, RX VrefLevel [Byte0]: 46
2742 23:54:49.323840 [Byte1]: 46
2743 23:54:49.328239
2744 23:54:49.328653 Set Vref, RX VrefLevel [Byte0]: 47
2745 23:54:49.331806 [Byte1]: 47
2746 23:54:49.336119
2747 23:54:49.336532 Set Vref, RX VrefLevel [Byte0]: 48
2748 23:54:49.339320 [Byte1]: 48
2749 23:54:49.343985
2750 23:54:49.344458 Set Vref, RX VrefLevel [Byte0]: 49
2751 23:54:49.347421 [Byte1]: 49
2752 23:54:49.352039
2753 23:54:49.352453 Set Vref, RX VrefLevel [Byte0]: 50
2754 23:54:49.355403 [Byte1]: 50
2755 23:54:49.359977
2756 23:54:49.360387 Set Vref, RX VrefLevel [Byte0]: 51
2757 23:54:49.363489 [Byte1]: 51
2758 23:54:49.367646
2759 23:54:49.368055 Set Vref, RX VrefLevel [Byte0]: 52
2760 23:54:49.371150 [Byte1]: 52
2761 23:54:49.375793
2762 23:54:49.376202 Set Vref, RX VrefLevel [Byte0]: 53
2763 23:54:49.379382 [Byte1]: 53
2764 23:54:49.383461
2765 23:54:49.383870 Set Vref, RX VrefLevel [Byte0]: 54
2766 23:54:49.387230 [Byte1]: 54
2767 23:54:49.391286
2768 23:54:49.391694 Set Vref, RX VrefLevel [Byte0]: 55
2769 23:54:49.394681 [Byte1]: 55
2770 23:54:49.399490
2771 23:54:49.399898 Set Vref, RX VrefLevel [Byte0]: 56
2772 23:54:49.403015 [Byte1]: 56
2773 23:54:49.407163
2774 23:54:49.407571 Set Vref, RX VrefLevel [Byte0]: 57
2775 23:54:49.410512 [Byte1]: 57
2776 23:54:49.415107
2777 23:54:49.415517 Set Vref, RX VrefLevel [Byte0]: 58
2778 23:54:49.418476 [Byte1]: 58
2779 23:54:49.423650
2780 23:54:49.424081 Set Vref, RX VrefLevel [Byte0]: 59
2781 23:54:49.426515 [Byte1]: 59
2782 23:54:49.431281
2783 23:54:49.431688 Set Vref, RX VrefLevel [Byte0]: 60
2784 23:54:49.434368 [Byte1]: 60
2785 23:54:49.439043
2786 23:54:49.439474 Set Vref, RX VrefLevel [Byte0]: 61
2787 23:54:49.442433 [Byte1]: 61
2788 23:54:49.446929
2789 23:54:49.447337 Set Vref, RX VrefLevel [Byte0]: 62
2790 23:54:49.450615 [Byte1]: 62
2791 23:54:49.455310
2792 23:54:49.455719 Set Vref, RX VrefLevel [Byte0]: 63
2793 23:54:49.458623 [Byte1]: 63
2794 23:54:49.462681
2795 23:54:49.463093 Set Vref, RX VrefLevel [Byte0]: 64
2796 23:54:49.466545 [Byte1]: 64
2797 23:54:49.470920
2798 23:54:49.471330 Set Vref, RX VrefLevel [Byte0]: 65
2799 23:54:49.474251 [Byte1]: 65
2800 23:54:49.478617
2801 23:54:49.479027 Set Vref, RX VrefLevel [Byte0]: 66
2802 23:54:49.481859 [Byte1]: 66
2803 23:54:49.486599
2804 23:54:49.486956 Set Vref, RX VrefLevel [Byte0]: 67
2805 23:54:49.490082 [Byte1]: 67
2806 23:54:49.494677
2807 23:54:49.495081 Set Vref, RX VrefLevel [Byte0]: 68
2808 23:54:49.498045 [Byte1]: 68
2809 23:54:49.502578
2810 23:54:49.503126 Final RX Vref Byte 0 = 53 to rank0
2811 23:54:49.506058 Final RX Vref Byte 1 = 53 to rank0
2812 23:54:49.509327 Final RX Vref Byte 0 = 53 to rank1
2813 23:54:49.513012 Final RX Vref Byte 1 = 53 to rank1==
2814 23:54:49.515812 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 23:54:49.519453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 23:54:49.522930 ==
2817 23:54:49.523341 DQS Delay:
2818 23:54:49.523666 DQS0 = 0, DQS1 = 0
2819 23:54:49.526210 DQM Delay:
2820 23:54:49.526590 DQM0 = 115, DQM1 = 105
2821 23:54:49.529358 DQ Delay:
2822 23:54:49.532881 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2823 23:54:49.536189 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2824 23:54:49.539842 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2825 23:54:49.543211 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2826 23:54:49.543996
2827 23:54:49.544455
2828 23:54:49.549154 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2829 23:54:49.552272 CH0 RK0: MR19=303, MR18=FCEC
2830 23:54:49.559228 CH0_RK0: MR19=0x303, MR18=0xFCEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2831 23:54:49.559307
2832 23:54:49.562644 ----->DramcWriteLeveling(PI) begin...
2833 23:54:49.562730 ==
2834 23:54:49.566648 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 23:54:49.569253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 23:54:49.569404 ==
2837 23:54:49.572875 Write leveling (Byte 0): 32 => 32
2838 23:54:49.576844 Write leveling (Byte 1): 28 => 28
2839 23:54:49.579412 DramcWriteLeveling(PI) end<-----
2840 23:54:49.579520
2841 23:54:49.579605 ==
2842 23:54:49.582675 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 23:54:49.586155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 23:54:49.586275 ==
2845 23:54:49.590013 [Gating] SW mode calibration
2846 23:54:49.596488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 23:54:49.603017 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 23:54:49.606193 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 23:54:49.613048 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2850 23:54:49.616504 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 23:54:49.619880 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 23:54:49.623366 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 23:54:49.630159 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 23:54:49.633681 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2855 23:54:49.637132 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2856 23:54:49.643986 1 0 0 | B1->B0 | 3030 2525 | 0 0 | (0 0) (1 1)
2857 23:54:49.647086 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2858 23:54:49.649907 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 23:54:49.656858 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 23:54:49.660279 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 23:54:49.663561 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 23:54:49.670151 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2863 23:54:49.673540 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2864 23:54:49.677083 1 1 0 | B1->B0 | 2b2a 3939 | 1 0 | (0 0) (0 0)
2865 23:54:49.680247 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2866 23:54:49.687044 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 23:54:49.690682 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 23:54:49.694161 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 23:54:49.700555 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 23:54:49.703962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 23:54:49.706846 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2872 23:54:49.714001 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2873 23:54:49.717096 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2874 23:54:49.720410 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 23:54:49.727204 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:54:49.731072 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:54:49.734067 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 23:54:49.741028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 23:54:49.743884 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:54:49.746631 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:54:49.750420 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:54:49.756741 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:54:49.760389 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:54:49.763334 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:54:49.770496 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:54:49.774289 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:54:49.777091 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2888 23:54:49.783626 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2889 23:54:49.783774 Total UI for P1: 0, mck2ui 16
2890 23:54:49.790780 best dqsien dly found for B0: ( 1, 3, 28)
2891 23:54:49.793824 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2892 23:54:49.796947 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 23:54:49.800789 Total UI for P1: 0, mck2ui 16
2894 23:54:49.803806 best dqsien dly found for B1: ( 1, 4, 2)
2895 23:54:49.807259 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2896 23:54:49.810448 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2897 23:54:49.810535
2898 23:54:49.814051 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2899 23:54:49.820839 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2900 23:54:49.820943 [Gating] SW calibration Done
2901 23:54:49.821038 ==
2902 23:54:49.824292 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 23:54:49.830864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 23:54:49.830978 ==
2905 23:54:49.831072 RX Vref Scan: 0
2906 23:54:49.831160
2907 23:54:49.834063 RX Vref 0 -> 0, step: 1
2908 23:54:49.834185
2909 23:54:49.837156 RX Delay -40 -> 252, step: 8
2910 23:54:49.840573 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2911 23:54:49.844421 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2912 23:54:49.847738 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2913 23:54:49.851229 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2914 23:54:49.858019 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2915 23:54:49.861050 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2916 23:54:49.864676 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2917 23:54:49.868029 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2918 23:54:49.871399 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2919 23:54:49.874800 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2920 23:54:49.881063 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2921 23:54:49.884480 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2922 23:54:49.887993 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2923 23:54:49.891243 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2924 23:54:49.894457 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2925 23:54:49.901341 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2926 23:54:49.901760 ==
2927 23:54:49.905708 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 23:54:49.908028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 23:54:49.908442 ==
2930 23:54:49.908882 DQS Delay:
2931 23:54:49.911333 DQS0 = 0, DQS1 = 0
2932 23:54:49.911741 DQM Delay:
2933 23:54:49.914843 DQM0 = 115, DQM1 = 106
2934 23:54:49.915254 DQ Delay:
2935 23:54:49.918496 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2936 23:54:49.921765 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2937 23:54:49.924752 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2938 23:54:49.928281 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2939 23:54:49.928693
2940 23:54:49.929064
2941 23:54:49.931481 ==
2942 23:54:49.931932 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 23:54:49.938555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 23:54:49.938970 ==
2945 23:54:49.939305
2946 23:54:49.939612
2947 23:54:49.941493 TX Vref Scan disable
2948 23:54:49.941905 == TX Byte 0 ==
2949 23:54:49.944836 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2950 23:54:49.951759 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2951 23:54:49.952220 == TX Byte 1 ==
2952 23:54:49.955704 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2953 23:54:49.961866 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2954 23:54:49.962280 ==
2955 23:54:49.964930 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 23:54:49.968429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 23:54:49.969102 ==
2958 23:54:49.980194 TX Vref=22, minBit 0, minWin=26, winSum=424
2959 23:54:49.983674 TX Vref=24, minBit 1, minWin=25, winSum=425
2960 23:54:49.986818 TX Vref=26, minBit 0, minWin=26, winSum=431
2961 23:54:49.990243 TX Vref=28, minBit 3, minWin=26, winSum=437
2962 23:54:49.993598 TX Vref=30, minBit 3, minWin=26, winSum=436
2963 23:54:49.996796 TX Vref=32, minBit 3, minWin=26, winSum=437
2964 23:54:50.003958 [TxChooseVref] Worse bit 3, Min win 26, Win sum 437, Final Vref 28
2965 23:54:50.004371
2966 23:54:50.006963 Final TX Range 1 Vref 28
2967 23:54:50.007378
2968 23:54:50.007702 ==
2969 23:54:50.010271 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 23:54:50.013886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 23:54:50.014300 ==
2972 23:54:50.014627
2973 23:54:50.014933
2974 23:54:50.016949 TX Vref Scan disable
2975 23:54:50.020376 == TX Byte 0 ==
2976 23:54:50.024007 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2977 23:54:50.027185 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2978 23:54:50.030548 == TX Byte 1 ==
2979 23:54:50.033646 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2980 23:54:50.037180 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2981 23:54:50.037591
2982 23:54:50.040482 [DATLAT]
2983 23:54:50.040893 Freq=1200, CH0 RK1
2984 23:54:50.041281
2985 23:54:50.043721 DATLAT Default: 0xd
2986 23:54:50.044132 0, 0xFFFF, sum = 0
2987 23:54:50.047349 1, 0xFFFF, sum = 0
2988 23:54:50.047769 2, 0xFFFF, sum = 0
2989 23:54:50.050757 3, 0xFFFF, sum = 0
2990 23:54:50.051173 4, 0xFFFF, sum = 0
2991 23:54:50.053814 5, 0xFFFF, sum = 0
2992 23:54:50.054232 6, 0xFFFF, sum = 0
2993 23:54:50.057269 7, 0xFFFF, sum = 0
2994 23:54:50.057687 8, 0xFFFF, sum = 0
2995 23:54:50.061229 9, 0xFFFF, sum = 0
2996 23:54:50.061649 10, 0xFFFF, sum = 0
2997 23:54:50.064813 11, 0xFFFF, sum = 0
2998 23:54:50.065276 12, 0x0, sum = 1
2999 23:54:50.067429 13, 0x0, sum = 2
3000 23:54:50.067849 14, 0x0, sum = 3
3001 23:54:50.071104 15, 0x0, sum = 4
3002 23:54:50.071524 best_step = 13
3003 23:54:50.071853
3004 23:54:50.072161 ==
3005 23:54:50.074229 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 23:54:50.081242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 23:54:50.081657 ==
3008 23:54:50.081987 RX Vref Scan: 0
3009 23:54:50.082297
3010 23:54:50.084674 RX Vref 0 -> 0, step: 1
3011 23:54:50.085125
3012 23:54:50.087551 RX Delay -21 -> 252, step: 4
3013 23:54:50.091274 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3014 23:54:50.094336 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3015 23:54:50.097877 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3016 23:54:50.104802 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3017 23:54:50.107865 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3018 23:54:50.111310 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3019 23:54:50.114256 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3020 23:54:50.117894 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3021 23:54:50.124674 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3022 23:54:50.128074 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3023 23:54:50.131318 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3024 23:54:50.134785 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3025 23:54:50.138136 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3026 23:54:50.141479 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3027 23:54:50.147971 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3028 23:54:50.151134 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3029 23:54:50.151547 ==
3030 23:54:50.154877 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 23:54:50.157891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 23:54:50.158307 ==
3033 23:54:50.161143 DQS Delay:
3034 23:54:50.161553 DQS0 = 0, DQS1 = 0
3035 23:54:50.161884 DQM Delay:
3036 23:54:50.165280 DQM0 = 113, DQM1 = 105
3037 23:54:50.165692 DQ Delay:
3038 23:54:50.168450 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3039 23:54:50.171736 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3040 23:54:50.175105 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3041 23:54:50.178348 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3042 23:54:50.181808
3043 23:54:50.182216
3044 23:54:50.188144 [DQSOSCAuto] RK1, (LSB)MR18= 0xfeef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
3045 23:54:50.191624 CH0 RK1: MR19=303, MR18=FEEF
3046 23:54:50.198419 CH0_RK1: MR19=0x303, MR18=0xFEEF, DQSOSC=410, MR23=63, INC=39, DEC=26
3047 23:54:50.201682 [RxdqsGatingPostProcess] freq 1200
3048 23:54:50.205174 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 23:54:50.208333 best DQS0 dly(2T, 0.5T) = (0, 12)
3050 23:54:50.211841 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 23:54:50.215109 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3052 23:54:50.218609 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 23:54:50.222010 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 23:54:50.225138 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 23:54:50.228547 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 23:54:50.231919 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 23:54:50.235139 Pre-setting of DQS Precalculation
3058 23:54:50.238411 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 23:54:50.238824 ==
3060 23:54:50.242164 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 23:54:50.245633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 23:54:50.246053 ==
3063 23:54:50.252035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 23:54:50.258475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3065 23:54:50.266318 [CA 0] Center 38 (8~68) winsize 61
3066 23:54:50.269565 [CA 1] Center 38 (8~68) winsize 61
3067 23:54:50.273080 [CA 2] Center 34 (4~65) winsize 62
3068 23:54:50.276567 [CA 3] Center 34 (4~64) winsize 61
3069 23:54:50.279433 [CA 4] Center 34 (4~65) winsize 62
3070 23:54:50.283031 [CA 5] Center 33 (4~63) winsize 60
3071 23:54:50.283500
3072 23:54:50.286403 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3073 23:54:50.286867
3074 23:54:50.289401 [CATrainingPosCal] consider 1 rank data
3075 23:54:50.292807 u2DelayCellTimex100 = 270/100 ps
3076 23:54:50.296034 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3077 23:54:50.299115 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3078 23:54:50.302412 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3079 23:54:50.309243 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 23:54:50.312582 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3081 23:54:50.316440 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3082 23:54:50.316540
3083 23:54:50.319515 CA PerBit enable=1, Macro0, CA PI delay=33
3084 23:54:50.319614
3085 23:54:50.322740 [CBTSetCACLKResult] CA Dly = 33
3086 23:54:50.322849 CS Dly: 6 (0~37)
3087 23:54:50.322938 ==
3088 23:54:50.326384 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 23:54:50.333329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 23:54:50.333541 ==
3091 23:54:50.336701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 23:54:50.343472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 23:54:50.351836 [CA 0] Center 38 (8~68) winsize 61
3094 23:54:50.355348 [CA 1] Center 38 (9~68) winsize 60
3095 23:54:50.358793 [CA 2] Center 34 (4~65) winsize 62
3096 23:54:50.362099 [CA 3] Center 34 (4~65) winsize 62
3097 23:54:50.364954 [CA 4] Center 34 (4~65) winsize 62
3098 23:54:50.368623 [CA 5] Center 33 (3~63) winsize 61
3099 23:54:50.369126
3100 23:54:50.371644 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 23:54:50.372101
3102 23:54:50.375002 [CATrainingPosCal] consider 2 rank data
3103 23:54:50.379221 u2DelayCellTimex100 = 270/100 ps
3104 23:54:50.382285 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3105 23:54:50.385133 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3106 23:54:50.389304 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3107 23:54:50.395087 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 23:54:50.398984 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3109 23:54:50.402192 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3110 23:54:50.402665
3111 23:54:50.405161 CA PerBit enable=1, Macro0, CA PI delay=33
3112 23:54:50.405601
3113 23:54:50.409219 [CBTSetCACLKResult] CA Dly = 33
3114 23:54:50.409779 CS Dly: 8 (0~41)
3115 23:54:50.410150
3116 23:54:50.412554 ----->DramcWriteLeveling(PI) begin...
3117 23:54:50.412915 ==
3118 23:54:50.415459 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 23:54:50.422713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 23:54:50.423259 ==
3121 23:54:50.425753 Write leveling (Byte 0): 27 => 27
3122 23:54:50.428863 Write leveling (Byte 1): 29 => 29
3123 23:54:50.429450 DramcWriteLeveling(PI) end<-----
3124 23:54:50.429966
3125 23:54:50.432536 ==
3126 23:54:50.432951 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 23:54:50.438810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 23:54:50.439226 ==
3129 23:54:50.442169 [Gating] SW mode calibration
3130 23:54:50.449133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 23:54:50.452183 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 23:54:50.459095 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
3133 23:54:50.462676 0 15 4 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
3134 23:54:50.465620 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 23:54:50.472788 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3136 23:54:50.475835 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3137 23:54:50.479439 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 23:54:50.483059 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3139 23:54:50.489264 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3140 23:54:50.492533 1 0 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 0)
3141 23:54:50.496413 1 0 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3142 23:54:50.502761 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 23:54:50.506198 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 23:54:50.509198 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3145 23:54:50.515909 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 23:54:50.519384 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 23:54:50.522740 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 23:54:50.529808 1 1 0 | B1->B0 | 3e3e 2f2f | 0 0 | (0 0) (0 0)
3149 23:54:50.533434 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 23:54:50.536585 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 23:54:50.539993 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 23:54:50.546645 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 23:54:50.549452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 23:54:50.552779 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 23:54:50.559395 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 23:54:50.563032 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3157 23:54:50.566473 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 23:54:50.573530 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:54:50.576342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 23:54:50.579798 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 23:54:50.586472 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 23:54:50.591399 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:54:50.593357 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:54:50.600606 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:54:50.603467 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:54:50.606353 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:54:50.610259 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:54:50.616260 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:54:50.620243 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:54:50.623212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:54:50.629976 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3172 23:54:50.633850 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3173 23:54:50.636557 Total UI for P1: 0, mck2ui 16
3174 23:54:50.640083 best dqsien dly found for B0: ( 1, 3, 28)
3175 23:54:50.643655 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 23:54:50.646365 Total UI for P1: 0, mck2ui 16
3177 23:54:50.650296 best dqsien dly found for B1: ( 1, 4, 0)
3178 23:54:50.653323 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3179 23:54:50.657167 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3180 23:54:50.657716
3181 23:54:50.663609 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3182 23:54:50.666661 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3183 23:54:50.667422 [Gating] SW calibration Done
3184 23:54:50.668106 ==
3185 23:54:50.669779 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 23:54:50.676494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 23:54:50.677229 ==
3188 23:54:50.677895 RX Vref Scan: 0
3189 23:54:50.678433
3190 23:54:50.680672 RX Vref 0 -> 0, step: 1
3191 23:54:50.681291
3192 23:54:50.683508 RX Delay -40 -> 252, step: 8
3193 23:54:50.686705 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3194 23:54:50.689894 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3195 23:54:50.693338 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3196 23:54:50.700333 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3197 23:54:50.703904 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3198 23:54:50.707265 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3199 23:54:50.710410 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3200 23:54:50.713686 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3201 23:54:50.717053 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 23:54:50.723649 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3203 23:54:50.727269 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3204 23:54:50.730346 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 23:54:50.733727 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3206 23:54:50.737042 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3207 23:54:50.744048 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3208 23:54:50.747389 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3209 23:54:50.747963 ==
3210 23:54:50.750461 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 23:54:50.753693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 23:54:50.754226 ==
3213 23:54:50.757209 DQS Delay:
3214 23:54:50.757665 DQS0 = 0, DQS1 = 0
3215 23:54:50.758025 DQM Delay:
3216 23:54:50.760438 DQM0 = 115, DQM1 = 108
3217 23:54:50.760891 DQ Delay:
3218 23:54:50.764243 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3219 23:54:50.767369 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3220 23:54:50.771222 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3221 23:54:50.774683 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3222 23:54:50.775250
3223 23:54:50.778263
3224 23:54:50.778808 ==
3225 23:54:50.781117 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 23:54:50.784391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 23:54:50.784942 ==
3228 23:54:50.785352
3229 23:54:50.785693
3230 23:54:50.787404 TX Vref Scan disable
3231 23:54:50.787858 == TX Byte 0 ==
3232 23:54:50.794480 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3233 23:54:50.797698 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3234 23:54:50.798259 == TX Byte 1 ==
3235 23:54:50.800615 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3236 23:54:50.807469 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3237 23:54:50.807930 ==
3238 23:54:50.811056 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:54:50.814192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:54:50.814652 ==
3241 23:54:50.826165 TX Vref=22, minBit 1, minWin=25, winSum=413
3242 23:54:50.829447 TX Vref=24, minBit 1, minWin=25, winSum=418
3243 23:54:50.833127 TX Vref=26, minBit 0, minWin=26, winSum=424
3244 23:54:50.836408 TX Vref=28, minBit 1, minWin=26, winSum=426
3245 23:54:50.839545 TX Vref=30, minBit 1, minWin=26, winSum=427
3246 23:54:50.842780 TX Vref=32, minBit 15, minWin=25, winSum=429
3247 23:54:50.850367 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3248 23:54:50.850885
3249 23:54:50.853229 Final TX Range 1 Vref 30
3250 23:54:50.853704
3251 23:54:50.854056 ==
3252 23:54:50.856525 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 23:54:50.859811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 23:54:50.860364 ==
3255 23:54:50.860735
3256 23:54:50.861111
3257 23:54:50.863124 TX Vref Scan disable
3258 23:54:50.866338 == TX Byte 0 ==
3259 23:54:50.869653 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3260 23:54:50.873559 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3261 23:54:50.876536 == TX Byte 1 ==
3262 23:54:50.880435 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3263 23:54:50.883485 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3264 23:54:50.884037
3265 23:54:50.886526 [DATLAT]
3266 23:54:50.886980 Freq=1200, CH1 RK0
3267 23:54:50.887345
3268 23:54:50.890280 DATLAT Default: 0xd
3269 23:54:50.890734 0, 0xFFFF, sum = 0
3270 23:54:50.893566 1, 0xFFFF, sum = 0
3271 23:54:50.894128 2, 0xFFFF, sum = 0
3272 23:54:50.897172 3, 0xFFFF, sum = 0
3273 23:54:50.897731 4, 0xFFFF, sum = 0
3274 23:54:50.899995 5, 0xFFFF, sum = 0
3275 23:54:50.900456 6, 0xFFFF, sum = 0
3276 23:54:50.903939 7, 0xFFFF, sum = 0
3277 23:54:50.904503 8, 0xFFFF, sum = 0
3278 23:54:50.906466 9, 0xFFFF, sum = 0
3279 23:54:50.906925 10, 0xFFFF, sum = 0
3280 23:54:50.910833 11, 0xFFFF, sum = 0
3281 23:54:50.911395 12, 0x0, sum = 1
3282 23:54:50.913582 13, 0x0, sum = 2
3283 23:54:50.914044 14, 0x0, sum = 3
3284 23:54:50.916461 15, 0x0, sum = 4
3285 23:54:50.916921 best_step = 13
3286 23:54:50.917308
3287 23:54:50.917647 ==
3288 23:54:50.919950 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 23:54:50.926928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 23:54:50.927384 ==
3291 23:54:50.927745 RX Vref Scan: 1
3292 23:54:50.928117
3293 23:54:50.930003 Set Vref Range= 32 -> 127
3294 23:54:50.930597
3295 23:54:50.933501 RX Vref 32 -> 127, step: 1
3296 23:54:50.934153
3297 23:54:50.934736 RX Delay -21 -> 252, step: 4
3298 23:54:50.935104
3299 23:54:50.936743 Set Vref, RX VrefLevel [Byte0]: 32
3300 23:54:50.940560 [Byte1]: 32
3301 23:54:50.944146
3302 23:54:50.944690 Set Vref, RX VrefLevel [Byte0]: 33
3303 23:54:50.947665 [Byte1]: 33
3304 23:54:50.952601
3305 23:54:50.953040 Set Vref, RX VrefLevel [Byte0]: 34
3306 23:54:50.955289 [Byte1]: 34
3307 23:54:50.960902
3308 23:54:50.961634 Set Vref, RX VrefLevel [Byte0]: 35
3309 23:54:50.963243 [Byte1]: 35
3310 23:54:50.968197
3311 23:54:50.968703 Set Vref, RX VrefLevel [Byte0]: 36
3312 23:54:50.971317 [Byte1]: 36
3313 23:54:50.976363
3314 23:54:50.976920 Set Vref, RX VrefLevel [Byte0]: 37
3315 23:54:50.979662 [Byte1]: 37
3316 23:54:50.984097
3317 23:54:50.984628 Set Vref, RX VrefLevel [Byte0]: 38
3318 23:54:50.987200 [Byte1]: 38
3319 23:54:50.992465
3320 23:54:50.993050 Set Vref, RX VrefLevel [Byte0]: 39
3321 23:54:50.995062 [Byte1]: 39
3322 23:54:51.000137
3323 23:54:51.000795 Set Vref, RX VrefLevel [Byte0]: 40
3324 23:54:51.003599 [Byte1]: 40
3325 23:54:51.008638
3326 23:54:51.009266 Set Vref, RX VrefLevel [Byte0]: 41
3327 23:54:51.011528 [Byte1]: 41
3328 23:54:51.015988
3329 23:54:51.016534 Set Vref, RX VrefLevel [Byte0]: 42
3330 23:54:51.019580 [Byte1]: 42
3331 23:54:51.023840
3332 23:54:51.024388 Set Vref, RX VrefLevel [Byte0]: 43
3333 23:54:51.027171 [Byte1]: 43
3334 23:54:51.031813
3335 23:54:51.032366 Set Vref, RX VrefLevel [Byte0]: 44
3336 23:54:51.035073 [Byte1]: 44
3337 23:54:51.040018
3338 23:54:51.043289 Set Vref, RX VrefLevel [Byte0]: 45
3339 23:54:51.043867 [Byte1]: 45
3340 23:54:51.047925
3341 23:54:51.048562 Set Vref, RX VrefLevel [Byte0]: 46
3342 23:54:51.050255 [Byte1]: 46
3343 23:54:51.055137
3344 23:54:51.055710 Set Vref, RX VrefLevel [Byte0]: 47
3345 23:54:51.058358 [Byte1]: 47
3346 23:54:51.062952
3347 23:54:51.063402 Set Vref, RX VrefLevel [Byte0]: 48
3348 23:54:51.066320 [Byte1]: 48
3349 23:54:51.071083
3350 23:54:51.071633 Set Vref, RX VrefLevel [Byte0]: 49
3351 23:54:51.075001 [Byte1]: 49
3352 23:54:51.079383
3353 23:54:51.079929 Set Vref, RX VrefLevel [Byte0]: 50
3354 23:54:51.082682 [Byte1]: 50
3355 23:54:51.087085
3356 23:54:51.087630 Set Vref, RX VrefLevel [Byte0]: 51
3357 23:54:51.090745 [Byte1]: 51
3358 23:54:51.095029
3359 23:54:51.095642 Set Vref, RX VrefLevel [Byte0]: 52
3360 23:54:51.098104 [Byte1]: 52
3361 23:54:51.103307
3362 23:54:51.103855 Set Vref, RX VrefLevel [Byte0]: 53
3363 23:54:51.106042 [Byte1]: 53
3364 23:54:51.111367
3365 23:54:51.111913 Set Vref, RX VrefLevel [Byte0]: 54
3366 23:54:51.114071 [Byte1]: 54
3367 23:54:51.118582
3368 23:54:51.119033 Set Vref, RX VrefLevel [Byte0]: 55
3369 23:54:51.122170 [Byte1]: 55
3370 23:54:51.126595
3371 23:54:51.127044 Set Vref, RX VrefLevel [Byte0]: 56
3372 23:54:51.129855 [Byte1]: 56
3373 23:54:51.134523
3374 23:54:51.135073 Set Vref, RX VrefLevel [Byte0]: 57
3375 23:54:51.137923 [Byte1]: 57
3376 23:54:51.143141
3377 23:54:51.143698 Set Vref, RX VrefLevel [Byte0]: 58
3378 23:54:51.145850 [Byte1]: 58
3379 23:54:51.150277
3380 23:54:51.150835 Set Vref, RX VrefLevel [Byte0]: 59
3381 23:54:51.153588 [Byte1]: 59
3382 23:54:51.158649
3383 23:54:51.159202 Set Vref, RX VrefLevel [Byte0]: 60
3384 23:54:51.161520 [Byte1]: 60
3385 23:54:51.166646
3386 23:54:51.167208 Set Vref, RX VrefLevel [Byte0]: 61
3387 23:54:51.169451 [Byte1]: 61
3388 23:54:51.174326
3389 23:54:51.174894 Set Vref, RX VrefLevel [Byte0]: 62
3390 23:54:51.177284 [Byte1]: 62
3391 23:54:51.182289
3392 23:54:51.182736 Set Vref, RX VrefLevel [Byte0]: 63
3393 23:54:51.185058 [Byte1]: 63
3394 23:54:51.189768
3395 23:54:51.190218 Set Vref, RX VrefLevel [Byte0]: 64
3396 23:54:51.193081 [Byte1]: 64
3397 23:54:51.197861
3398 23:54:51.198268 Set Vref, RX VrefLevel [Byte0]: 65
3399 23:54:51.201116 [Byte1]: 65
3400 23:54:51.205460
3401 23:54:51.205967 Set Vref, RX VrefLevel [Byte0]: 66
3402 23:54:51.209023 [Byte1]: 66
3403 23:54:51.213677
3404 23:54:51.214084 Set Vref, RX VrefLevel [Byte0]: 67
3405 23:54:51.217143 [Byte1]: 67
3406 23:54:51.222222
3407 23:54:51.222789 Set Vref, RX VrefLevel [Byte0]: 68
3408 23:54:51.224734 [Byte1]: 68
3409 23:54:51.229983
3410 23:54:51.230525 Set Vref, RX VrefLevel [Byte0]: 69
3411 23:54:51.232827 [Byte1]: 69
3412 23:54:51.237585
3413 23:54:51.238132 Set Vref, RX VrefLevel [Byte0]: 70
3414 23:54:51.241407 [Byte1]: 70
3415 23:54:51.245360
3416 23:54:51.245923 Final RX Vref Byte 0 = 57 to rank0
3417 23:54:51.248706 Final RX Vref Byte 1 = 52 to rank0
3418 23:54:51.252264 Final RX Vref Byte 0 = 57 to rank1
3419 23:54:51.255295 Final RX Vref Byte 1 = 52 to rank1==
3420 23:54:51.258820 Dram Type= 6, Freq= 0, CH_1, rank 0
3421 23:54:51.265862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 23:54:51.266421 ==
3423 23:54:51.266834 DQS Delay:
3424 23:54:51.267179 DQS0 = 0, DQS1 = 0
3425 23:54:51.269085 DQM Delay:
3426 23:54:51.269542 DQM0 = 115, DQM1 = 109
3427 23:54:51.272423 DQ Delay:
3428 23:54:51.275296 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114
3429 23:54:51.279256 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3430 23:54:51.282637 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3431 23:54:51.285660 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3432 23:54:51.286112
3433 23:54:51.286470
3434 23:54:51.292440 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3435 23:54:51.296006 CH1 RK0: MR19=303, MR18=FDE2
3436 23:54:51.302335 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3437 23:54:51.302793
3438 23:54:51.305548 ----->DramcWriteLeveling(PI) begin...
3439 23:54:51.306013 ==
3440 23:54:51.309112 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 23:54:51.312528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 23:54:51.313014 ==
3443 23:54:51.315672 Write leveling (Byte 0): 26 => 26
3444 23:54:51.318861 Write leveling (Byte 1): 28 => 28
3445 23:54:51.322074 DramcWriteLeveling(PI) end<-----
3446 23:54:51.322519
3447 23:54:51.322884 ==
3448 23:54:51.325522 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 23:54:51.328853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 23:54:51.332176 ==
3451 23:54:51.332618 [Gating] SW mode calibration
3452 23:54:51.339265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3453 23:54:51.345779 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3454 23:54:51.349052 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3455 23:54:51.355842 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3456 23:54:51.358884 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 23:54:51.362154 0 15 12 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3458 23:54:51.365739 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 23:54:51.372152 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 23:54:51.376067 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
3461 23:54:51.379584 0 15 28 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
3462 23:54:51.385969 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 23:54:51.389151 1 0 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3464 23:54:51.392577 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 23:54:51.399273 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 23:54:51.403092 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3467 23:54:51.405910 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3468 23:54:51.412676 1 0 24 | B1->B0 | 2626 3f3f | 0 0 | (0 0) (0 0)
3469 23:54:51.416140 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3470 23:54:51.419653 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 23:54:51.425939 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 23:54:51.429323 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 23:54:51.432786 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 23:54:51.439644 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 23:54:51.443057 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3476 23:54:51.446218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3477 23:54:51.452897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 23:54:51.456080 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 23:54:51.459490 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 23:54:51.463168 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 23:54:51.469426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 23:54:51.472886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 23:54:51.476402 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 23:54:51.482792 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:54:51.485932 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:54:51.489334 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:54:51.496200 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:54:51.498969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:54:51.502626 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:54:51.508683 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:54:51.512112 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3492 23:54:51.515434 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3493 23:54:51.522392 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3494 23:54:51.522471 Total UI for P1: 0, mck2ui 16
3495 23:54:51.528591 best dqsien dly found for B0: ( 1, 3, 22)
3496 23:54:51.532563 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 23:54:51.536301 Total UI for P1: 0, mck2ui 16
3498 23:54:51.539236 best dqsien dly found for B1: ( 1, 3, 28)
3499 23:54:51.542290 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3500 23:54:51.545683 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3501 23:54:51.545801
3502 23:54:51.548740 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3503 23:54:51.552310 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3504 23:54:51.555880 [Gating] SW calibration Done
3505 23:54:51.555989 ==
3506 23:54:51.559087 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 23:54:51.562203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 23:54:51.562306 ==
3509 23:54:51.565762 RX Vref Scan: 0
3510 23:54:51.565863
3511 23:54:51.568683 RX Vref 0 -> 0, step: 1
3512 23:54:51.568789
3513 23:54:51.568876 RX Delay -40 -> 252, step: 8
3514 23:54:51.575751 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3515 23:54:51.578692 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3516 23:54:51.582000 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3517 23:54:51.585890 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3518 23:54:51.588697 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3519 23:54:51.595721 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3520 23:54:51.598852 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3521 23:54:51.602420 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3522 23:54:51.605599 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3523 23:54:51.608715 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3524 23:54:51.615471 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3525 23:54:51.618767 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3526 23:54:51.622229 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3527 23:54:51.625413 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3528 23:54:51.628951 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3529 23:54:51.636106 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3530 23:54:51.636189 ==
3531 23:54:51.638568 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 23:54:51.642097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 23:54:51.642185 ==
3534 23:54:51.642255 DQS Delay:
3535 23:54:51.644965 DQS0 = 0, DQS1 = 0
3536 23:54:51.645062 DQM Delay:
3537 23:54:51.649086 DQM0 = 113, DQM1 = 110
3538 23:54:51.649535 DQ Delay:
3539 23:54:51.652482 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3540 23:54:51.655761 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3541 23:54:51.659164 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3542 23:54:51.662732 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3543 23:54:51.663149
3544 23:54:51.665591
3545 23:54:51.666014 ==
3546 23:54:51.669191 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 23:54:51.672582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 23:54:51.673037 ==
3549 23:54:51.673380
3550 23:54:51.673692
3551 23:54:51.675685 TX Vref Scan disable
3552 23:54:51.676120 == TX Byte 0 ==
3553 23:54:51.679058 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3554 23:54:51.686014 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3555 23:54:51.686429 == TX Byte 1 ==
3556 23:54:51.689079 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3557 23:54:51.695967 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3558 23:54:51.696380 ==
3559 23:54:51.698880 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 23:54:51.702598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 23:54:51.703019 ==
3562 23:54:51.714097 TX Vref=22, minBit 1, minWin=25, winSum=418
3563 23:54:51.717707 TX Vref=24, minBit 1, minWin=25, winSum=422
3564 23:54:51.720820 TX Vref=26, minBit 0, minWin=26, winSum=427
3565 23:54:51.724385 TX Vref=28, minBit 2, minWin=26, winSum=433
3566 23:54:51.727825 TX Vref=30, minBit 0, minWin=26, winSum=433
3567 23:54:51.730892 TX Vref=32, minBit 2, minWin=26, winSum=432
3568 23:54:51.737510 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 28
3569 23:54:51.737924
3570 23:54:51.740907 Final TX Range 1 Vref 28
3571 23:54:51.741359
3572 23:54:51.741689 ==
3573 23:54:51.744403 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 23:54:51.748089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 23:54:51.748545 ==
3576 23:54:51.748961
3577 23:54:51.749373
3578 23:54:51.751430 TX Vref Scan disable
3579 23:54:51.754902 == TX Byte 0 ==
3580 23:54:51.757719 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3581 23:54:51.760842 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3582 23:54:51.764350 == TX Byte 1 ==
3583 23:54:51.767698 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3584 23:54:51.770766 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3585 23:54:51.770848
3586 23:54:51.774135 [DATLAT]
3587 23:54:51.774215 Freq=1200, CH1 RK1
3588 23:54:51.774280
3589 23:54:51.777497 DATLAT Default: 0xd
3590 23:54:51.777578 0, 0xFFFF, sum = 0
3591 23:54:51.780731 1, 0xFFFF, sum = 0
3592 23:54:51.780813 2, 0xFFFF, sum = 0
3593 23:54:51.783900 3, 0xFFFF, sum = 0
3594 23:54:51.783982 4, 0xFFFF, sum = 0
3595 23:54:51.787414 5, 0xFFFF, sum = 0
3596 23:54:51.787522 6, 0xFFFF, sum = 0
3597 23:54:51.790614 7, 0xFFFF, sum = 0
3598 23:54:51.790696 8, 0xFFFF, sum = 0
3599 23:54:51.794303 9, 0xFFFF, sum = 0
3600 23:54:51.797725 10, 0xFFFF, sum = 0
3601 23:54:51.797807 11, 0xFFFF, sum = 0
3602 23:54:51.800940 12, 0x0, sum = 1
3603 23:54:51.801032 13, 0x0, sum = 2
3604 23:54:51.801098 14, 0x0, sum = 3
3605 23:54:51.804025 15, 0x0, sum = 4
3606 23:54:51.804107 best_step = 13
3607 23:54:51.804171
3608 23:54:51.804231 ==
3609 23:54:51.807409 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 23:54:51.814743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 23:54:51.814824 ==
3612 23:54:51.814888 RX Vref Scan: 0
3613 23:54:51.814948
3614 23:54:51.817839 RX Vref 0 -> 0, step: 1
3615 23:54:51.817920
3616 23:54:51.820764 RX Delay -21 -> 252, step: 4
3617 23:54:51.823955 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3618 23:54:51.827517 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3619 23:54:51.834651 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3620 23:54:51.837563 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3621 23:54:51.841050 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3622 23:54:51.844218 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3623 23:54:51.847818 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3624 23:54:51.853979 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3625 23:54:51.857423 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3626 23:54:51.860566 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3627 23:54:51.864337 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3628 23:54:51.867761 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3629 23:54:51.874048 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3630 23:54:51.877239 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3631 23:54:51.880543 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3632 23:54:51.884130 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3633 23:54:51.884211 ==
3634 23:54:51.887298 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 23:54:51.890889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 23:54:51.893920 ==
3637 23:54:51.894002 DQS Delay:
3638 23:54:51.894067 DQS0 = 0, DQS1 = 0
3639 23:54:51.897373 DQM Delay:
3640 23:54:51.897465 DQM0 = 113, DQM1 = 109
3641 23:54:51.900584 DQ Delay:
3642 23:54:51.904326 DQ0 =112, DQ1 =110, DQ2 =106, DQ3 =112
3643 23:54:51.907683 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3644 23:54:51.910649 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3645 23:54:51.913977 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3646 23:54:51.914058
3647 23:54:51.914123
3648 23:54:51.920675 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa01, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3649 23:54:51.923935 CH1 RK1: MR19=304, MR18=FA01
3650 23:54:51.930575 CH1_RK1: MR19=0x304, MR18=0xFA01, DQSOSC=409, MR23=63, INC=39, DEC=26
3651 23:54:51.934292 [RxdqsGatingPostProcess] freq 1200
3652 23:54:51.940662 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3653 23:54:51.944387 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 23:54:51.944475 best DQS1 dly(2T, 0.5T) = (0, 12)
3655 23:54:51.947454 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 23:54:51.951018 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3657 23:54:51.953723 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 23:54:51.957429 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 23:54:51.960948 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 23:54:51.963890 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 23:54:51.967604 Pre-setting of DQS Precalculation
3662 23:54:51.974256 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3663 23:54:51.980533 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3664 23:54:51.987492 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3665 23:54:51.987574
3666 23:54:51.987639
3667 23:54:51.990465 [Calibration Summary] 2400 Mbps
3668 23:54:51.990547 CH 0, Rank 0
3669 23:54:51.993720 SW Impedance : PASS
3670 23:54:51.997715 DUTY Scan : NO K
3671 23:54:51.998135 ZQ Calibration : PASS
3672 23:54:52.000894 Jitter Meter : NO K
3673 23:54:52.001363 CBT Training : PASS
3674 23:54:52.004143 Write leveling : PASS
3675 23:54:52.007561 RX DQS gating : PASS
3676 23:54:52.007979 RX DQ/DQS(RDDQC) : PASS
3677 23:54:52.011528 TX DQ/DQS : PASS
3678 23:54:52.014936 RX DATLAT : PASS
3679 23:54:52.015353 RX DQ/DQS(Engine): PASS
3680 23:54:52.017596 TX OE : NO K
3681 23:54:52.018177 All Pass.
3682 23:54:52.018561
3683 23:54:52.021203 CH 0, Rank 1
3684 23:54:52.021748 SW Impedance : PASS
3685 23:54:52.024283 DUTY Scan : NO K
3686 23:54:52.027803 ZQ Calibration : PASS
3687 23:54:52.028356 Jitter Meter : NO K
3688 23:54:52.031088 CBT Training : PASS
3689 23:54:52.034246 Write leveling : PASS
3690 23:54:52.034661 RX DQS gating : PASS
3691 23:54:52.037452 RX DQ/DQS(RDDQC) : PASS
3692 23:54:52.037865 TX DQ/DQS : PASS
3693 23:54:52.040904 RX DATLAT : PASS
3694 23:54:52.044584 RX DQ/DQS(Engine): PASS
3695 23:54:52.045037 TX OE : NO K
3696 23:54:52.047492 All Pass.
3697 23:54:52.047916
3698 23:54:52.048307 CH 1, Rank 0
3699 23:54:52.051163 SW Impedance : PASS
3700 23:54:52.051573 DUTY Scan : NO K
3701 23:54:52.054578 ZQ Calibration : PASS
3702 23:54:52.057741 Jitter Meter : NO K
3703 23:54:52.058157 CBT Training : PASS
3704 23:54:52.061439 Write leveling : PASS
3705 23:54:52.064572 RX DQS gating : PASS
3706 23:54:52.065020 RX DQ/DQS(RDDQC) : PASS
3707 23:54:52.068251 TX DQ/DQS : PASS
3708 23:54:52.071196 RX DATLAT : PASS
3709 23:54:52.071609 RX DQ/DQS(Engine): PASS
3710 23:54:52.074542 TX OE : NO K
3711 23:54:52.074956 All Pass.
3712 23:54:52.075285
3713 23:54:52.078926 CH 1, Rank 1
3714 23:54:52.079342 SW Impedance : PASS
3715 23:54:52.081715 DUTY Scan : NO K
3716 23:54:52.082131 ZQ Calibration : PASS
3717 23:54:52.084649 Jitter Meter : NO K
3718 23:54:52.088146 CBT Training : PASS
3719 23:54:52.088559 Write leveling : PASS
3720 23:54:52.091224 RX DQS gating : PASS
3721 23:54:52.094693 RX DQ/DQS(RDDQC) : PASS
3722 23:54:52.095104 TX DQ/DQS : PASS
3723 23:54:52.097609 RX DATLAT : PASS
3724 23:54:52.100615 RX DQ/DQS(Engine): PASS
3725 23:54:52.100695 TX OE : NO K
3726 23:54:52.103908 All Pass.
3727 23:54:52.103988
3728 23:54:52.104051 DramC Write-DBI off
3729 23:54:52.107232 PER_BANK_REFRESH: Hybrid Mode
3730 23:54:52.107312 TX_TRACKING: ON
3731 23:54:52.117345 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3732 23:54:52.121226 [FAST_K] Save calibration result to emmc
3733 23:54:52.124456 dramc_set_vcore_voltage set vcore to 650000
3734 23:54:52.127255 Read voltage for 600, 5
3735 23:54:52.127335 Vio18 = 0
3736 23:54:52.131194 Vcore = 650000
3737 23:54:52.131274 Vdram = 0
3738 23:54:52.131338 Vddq = 0
3739 23:54:52.134264 Vmddr = 0
3740 23:54:52.137502 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3741 23:54:52.144148 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3742 23:54:52.144229 MEM_TYPE=3, freq_sel=19
3743 23:54:52.147564 sv_algorithm_assistance_LP4_1600
3744 23:54:52.150788 ============ PULL DRAM RESETB DOWN ============
3745 23:54:52.157246 ========== PULL DRAM RESETB DOWN end =========
3746 23:54:52.160722 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 23:54:52.164382 ===================================
3748 23:54:52.167135 LPDDR4 DRAM CONFIGURATION
3749 23:54:52.170437 ===================================
3750 23:54:52.170532 EX_ROW_EN[0] = 0x0
3751 23:54:52.174461 EX_ROW_EN[1] = 0x0
3752 23:54:52.174546 LP4Y_EN = 0x0
3753 23:54:52.177101 WORK_FSP = 0x0
3754 23:54:52.180612 WL = 0x2
3755 23:54:52.180704 RL = 0x2
3756 23:54:52.184123 BL = 0x2
3757 23:54:52.184223 RPST = 0x0
3758 23:54:52.187504 RD_PRE = 0x0
3759 23:54:52.187612 WR_PRE = 0x1
3760 23:54:52.190557 WR_PST = 0x0
3761 23:54:52.190665 DBI_WR = 0x0
3762 23:54:52.194363 DBI_RD = 0x0
3763 23:54:52.194443 OTF = 0x1
3764 23:54:52.197499 ===================================
3765 23:54:52.200882 ===================================
3766 23:54:52.204151 ANA top config
3767 23:54:52.207267 ===================================
3768 23:54:52.207367 DLL_ASYNC_EN = 0
3769 23:54:52.210488 ALL_SLAVE_EN = 1
3770 23:54:52.214294 NEW_RANK_MODE = 1
3771 23:54:52.217701 DLL_IDLE_MODE = 1
3772 23:54:52.217821 LP45_APHY_COMB_EN = 1
3773 23:54:52.220666 TX_ODT_DIS = 1
3774 23:54:52.223895 NEW_8X_MODE = 1
3775 23:54:52.227357 ===================================
3776 23:54:52.230687 ===================================
3777 23:54:52.234019 data_rate = 1200
3778 23:54:52.237188 CKR = 1
3779 23:54:52.237387 DQ_P2S_RATIO = 8
3780 23:54:52.240565 ===================================
3781 23:54:52.243945 CA_P2S_RATIO = 8
3782 23:54:52.247475 DQ_CA_OPEN = 0
3783 23:54:52.250575 DQ_SEMI_OPEN = 0
3784 23:54:52.254497 CA_SEMI_OPEN = 0
3785 23:54:52.257672 CA_FULL_RATE = 0
3786 23:54:52.258090 DQ_CKDIV4_EN = 1
3787 23:54:52.260804 CA_CKDIV4_EN = 1
3788 23:54:52.264486 CA_PREDIV_EN = 0
3789 23:54:52.267388 PH8_DLY = 0
3790 23:54:52.270861 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3791 23:54:52.274227 DQ_AAMCK_DIV = 4
3792 23:54:52.274647 CA_AAMCK_DIV = 4
3793 23:54:52.277580 CA_ADMCK_DIV = 4
3794 23:54:52.281062 DQ_TRACK_CA_EN = 0
3795 23:54:52.284214 CA_PICK = 600
3796 23:54:52.288131 CA_MCKIO = 600
3797 23:54:52.291280 MCKIO_SEMI = 0
3798 23:54:52.294656 PLL_FREQ = 2288
3799 23:54:52.295074 DQ_UI_PI_RATIO = 32
3800 23:54:52.297330 CA_UI_PI_RATIO = 0
3801 23:54:52.300863 ===================================
3802 23:54:52.304428 ===================================
3803 23:54:52.307568 memory_type:LPDDR4
3804 23:54:52.310936 GP_NUM : 10
3805 23:54:52.311356 SRAM_EN : 1
3806 23:54:52.314193 MD32_EN : 0
3807 23:54:52.317517 ===================================
3808 23:54:52.317936 [ANA_INIT] >>>>>>>>>>>>>>
3809 23:54:52.321285 <<<<<< [CONFIGURE PHASE]: ANA_TX
3810 23:54:52.324245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3811 23:54:52.327929 ===================================
3812 23:54:52.331054 data_rate = 1200,PCW = 0X5800
3813 23:54:52.334367 ===================================
3814 23:54:52.337907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3815 23:54:52.344442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 23:54:52.347989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 23:54:52.354261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3818 23:54:52.357629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3819 23:54:52.361311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3820 23:54:52.364515 [ANA_INIT] flow start
3821 23:54:52.364930 [ANA_INIT] PLL >>>>>>>>
3822 23:54:52.367753 [ANA_INIT] PLL <<<<<<<<
3823 23:54:52.371397 [ANA_INIT] MIDPI >>>>>>>>
3824 23:54:52.371813 [ANA_INIT] MIDPI <<<<<<<<
3825 23:54:52.374696 [ANA_INIT] DLL >>>>>>>>
3826 23:54:52.377706 [ANA_INIT] flow end
3827 23:54:52.381034 ============ LP4 DIFF to SE enter ============
3828 23:54:52.384379 ============ LP4 DIFF to SE exit ============
3829 23:54:52.387967 [ANA_INIT] <<<<<<<<<<<<<
3830 23:54:52.390676 [Flow] Enable top DCM control >>>>>
3831 23:54:52.394437 [Flow] Enable top DCM control <<<<<
3832 23:54:52.397637 Enable DLL master slave shuffle
3833 23:54:52.400901 ==============================================================
3834 23:54:52.404063 Gating Mode config
3835 23:54:52.411132 ==============================================================
3836 23:54:52.411549 Config description:
3837 23:54:52.421122 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3838 23:54:52.427954 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3839 23:54:52.431018 SELPH_MODE 0: By rank 1: By Phase
3840 23:54:52.437940 ==============================================================
3841 23:54:52.441196 GAT_TRACK_EN = 1
3842 23:54:52.444923 RX_GATING_MODE = 2
3843 23:54:52.447614 RX_GATING_TRACK_MODE = 2
3844 23:54:52.451036 SELPH_MODE = 1
3845 23:54:52.454198 PICG_EARLY_EN = 1
3846 23:54:52.454676 VALID_LAT_VALUE = 1
3847 23:54:52.461156 ==============================================================
3848 23:54:52.464086 Enter into Gating configuration >>>>
3849 23:54:52.467538 Exit from Gating configuration <<<<
3850 23:54:52.471113 Enter into DVFS_PRE_config >>>>>
3851 23:54:52.480718 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3852 23:54:52.484652 Exit from DVFS_PRE_config <<<<<
3853 23:54:52.488018 Enter into PICG configuration >>>>
3854 23:54:52.491648 Exit from PICG configuration <<<<
3855 23:54:52.494419 [RX_INPUT] configuration >>>>>
3856 23:54:52.497933 [RX_INPUT] configuration <<<<<
3857 23:54:52.501011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3858 23:54:52.507775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3859 23:54:52.514421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 23:54:52.521175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 23:54:52.527602 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 23:54:52.531043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 23:54:52.538062 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3864 23:54:52.541279 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3865 23:54:52.544933 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3866 23:54:52.548774 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3867 23:54:52.551586 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3868 23:54:52.557930 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 23:54:52.561137 ===================================
3870 23:54:52.561562 LPDDR4 DRAM CONFIGURATION
3871 23:54:52.564702 ===================================
3872 23:54:52.567839 EX_ROW_EN[0] = 0x0
3873 23:54:52.571337 EX_ROW_EN[1] = 0x0
3874 23:54:52.571753 LP4Y_EN = 0x0
3875 23:54:52.574752 WORK_FSP = 0x0
3876 23:54:52.575171 WL = 0x2
3877 23:54:52.577991 RL = 0x2
3878 23:54:52.578404 BL = 0x2
3879 23:54:52.581717 RPST = 0x0
3880 23:54:52.582134 RD_PRE = 0x0
3881 23:54:52.584434 WR_PRE = 0x1
3882 23:54:52.584849 WR_PST = 0x0
3883 23:54:52.588111 DBI_WR = 0x0
3884 23:54:52.588529 DBI_RD = 0x0
3885 23:54:52.591326 OTF = 0x1
3886 23:54:52.594229 ===================================
3887 23:54:52.598086 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3888 23:54:52.601224 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3889 23:54:52.608159 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 23:54:52.610923 ===================================
3891 23:54:52.611343 LPDDR4 DRAM CONFIGURATION
3892 23:54:52.614646 ===================================
3893 23:54:52.617698 EX_ROW_EN[0] = 0x10
3894 23:54:52.620951 EX_ROW_EN[1] = 0x0
3895 23:54:52.621420 LP4Y_EN = 0x0
3896 23:54:52.624751 WORK_FSP = 0x0
3897 23:54:52.625202 WL = 0x2
3898 23:54:52.627881 RL = 0x2
3899 23:54:52.628296 BL = 0x2
3900 23:54:52.631006 RPST = 0x0
3901 23:54:52.631427 RD_PRE = 0x0
3902 23:54:52.634741 WR_PRE = 0x1
3903 23:54:52.635171 WR_PST = 0x0
3904 23:54:52.638297 DBI_WR = 0x0
3905 23:54:52.638711 DBI_RD = 0x0
3906 23:54:52.641416 OTF = 0x1
3907 23:54:52.644807 ===================================
3908 23:54:52.651278 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3909 23:54:52.654422 nWR fixed to 30
3910 23:54:52.654855 [ModeRegInit_LP4] CH0 RK0
3911 23:54:52.657916 [ModeRegInit_LP4] CH0 RK1
3912 23:54:52.661265 [ModeRegInit_LP4] CH1 RK0
3913 23:54:52.664768 [ModeRegInit_LP4] CH1 RK1
3914 23:54:52.665379 match AC timing 17
3915 23:54:52.667996 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3916 23:54:52.674823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3917 23:54:52.677733 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3918 23:54:52.681388 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3919 23:54:52.688039 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3920 23:54:52.688605 ==
3921 23:54:52.691247 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 23:54:52.694522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 23:54:52.694986 ==
3924 23:54:52.701483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 23:54:52.704853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 23:54:52.708330 [CA 0] Center 36 (6~67) winsize 62
3927 23:54:52.711619 [CA 1] Center 36 (6~66) winsize 61
3928 23:54:52.715465 [CA 2] Center 34 (4~64) winsize 61
3929 23:54:52.718512 [CA 3] Center 34 (4~64) winsize 61
3930 23:54:52.722048 [CA 4] Center 33 (3~64) winsize 62
3931 23:54:52.725237 [CA 5] Center 33 (3~64) winsize 62
3932 23:54:52.725366
3933 23:54:52.728213 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 23:54:52.728294
3935 23:54:52.732021 [CATrainingPosCal] consider 1 rank data
3936 23:54:52.735214 u2DelayCellTimex100 = 270/100 ps
3937 23:54:52.738703 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 23:54:52.741861 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3939 23:54:52.748699 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3940 23:54:52.752024 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3941 23:54:52.755026 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 23:54:52.758549 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 23:54:52.758624
3944 23:54:52.761611 CA PerBit enable=1, Macro0, CA PI delay=33
3945 23:54:52.761683
3946 23:54:52.764961 [CBTSetCACLKResult] CA Dly = 33
3947 23:54:52.765051 CS Dly: 3 (0~34)
3948 23:54:52.765112 ==
3949 23:54:52.768469 Dram Type= 6, Freq= 0, CH_0, rank 1
3950 23:54:52.775073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 23:54:52.775155 ==
3952 23:54:52.778235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 23:54:52.785221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3954 23:54:52.788380 [CA 0] Center 36 (6~66) winsize 61
3955 23:54:52.792181 [CA 1] Center 36 (6~66) winsize 61
3956 23:54:52.795090 [CA 2] Center 34 (4~65) winsize 62
3957 23:54:52.798698 [CA 3] Center 34 (4~65) winsize 62
3958 23:54:52.802063 [CA 4] Center 33 (3~64) winsize 62
3959 23:54:52.805445 [CA 5] Center 33 (3~64) winsize 62
3960 23:54:52.805526
3961 23:54:52.808757 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3962 23:54:52.808837
3963 23:54:52.812239 [CATrainingPosCal] consider 2 rank data
3964 23:54:52.815720 u2DelayCellTimex100 = 270/100 ps
3965 23:54:52.819411 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3966 23:54:52.822175 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 23:54:52.825327 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3968 23:54:52.831985 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3969 23:54:52.835570 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 23:54:52.838863 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 23:54:52.838944
3972 23:54:52.842202 CA PerBit enable=1, Macro0, CA PI delay=33
3973 23:54:52.842283
3974 23:54:52.845765 [CBTSetCACLKResult] CA Dly = 33
3975 23:54:52.845847 CS Dly: 4 (0~37)
3976 23:54:52.845912
3977 23:54:52.849008 ----->DramcWriteLeveling(PI) begin...
3978 23:54:52.849106 ==
3979 23:54:52.852171 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 23:54:52.858577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 23:54:52.858659 ==
3982 23:54:52.861984 Write leveling (Byte 0): 31 => 31
3983 23:54:52.865563 Write leveling (Byte 1): 31 => 31
3984 23:54:52.868706 DramcWriteLeveling(PI) end<-----
3985 23:54:52.868788
3986 23:54:52.868851 ==
3987 23:54:52.871863 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 23:54:52.875648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 23:54:52.875731 ==
3990 23:54:52.879218 [Gating] SW mode calibration
3991 23:54:52.885230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 23:54:52.888460 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3993 23:54:52.895538 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 23:54:52.898538 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 23:54:52.902189 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 23:54:52.908429 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3997 23:54:52.911967 0 9 16 | B1->B0 | 3131 2929 | 0 0 | (0 1) (0 0)
3998 23:54:52.915117 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 23:54:52.922091 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 23:54:52.925044 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 23:54:52.928964 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 23:54:52.935454 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 23:54:52.938455 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 23:54:52.941747 0 10 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4005 23:54:52.948460 0 10 16 | B1->B0 | 3131 3a3a | 0 0 | (1 1) (0 0)
4006 23:54:52.951725 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 23:54:52.955261 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 23:54:52.962184 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 23:54:52.965345 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 23:54:52.968494 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 23:54:52.975189 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 23:54:52.978440 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 23:54:52.981815 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4014 23:54:52.985093 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:54:52.991967 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:54:52.995490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 23:54:52.998755 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 23:54:53.005442 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 23:54:53.008261 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:54:53.012354 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:54:53.018420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:54:53.022406 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:54:53.025061 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:54:53.031979 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:54:53.035380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:54:53.038537 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:54:53.045901 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:54:53.048742 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:54:53.052254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4030 23:54:53.055313 Total UI for P1: 0, mck2ui 16
4031 23:54:53.058561 best dqsien dly found for B0: ( 0, 13, 14)
4032 23:54:53.062133 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 23:54:53.065263 Total UI for P1: 0, mck2ui 16
4034 23:54:53.068454 best dqsien dly found for B1: ( 0, 13, 16)
4035 23:54:53.071764 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4036 23:54:53.078793 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4037 23:54:53.078875
4038 23:54:53.082033 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4039 23:54:53.085515 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4040 23:54:53.088664 [Gating] SW calibration Done
4041 23:54:53.088745 ==
4042 23:54:53.092034 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 23:54:53.095410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 23:54:53.095491 ==
4045 23:54:53.095556 RX Vref Scan: 0
4046 23:54:53.098903
4047 23:54:53.098983 RX Vref 0 -> 0, step: 1
4048 23:54:53.099047
4049 23:54:53.102301 RX Delay -230 -> 252, step: 16
4050 23:54:53.105436 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4051 23:54:53.111977 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4052 23:54:53.115806 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4053 23:54:53.118710 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4054 23:54:53.121966 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4055 23:54:53.125208 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4056 23:54:53.131587 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4057 23:54:53.135684 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4058 23:54:53.138669 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4059 23:54:53.141986 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4060 23:54:53.148697 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4061 23:54:53.151902 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4062 23:54:53.155334 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4063 23:54:53.159132 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4064 23:54:53.162215 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4065 23:54:53.168861 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4066 23:54:53.168971 ==
4067 23:54:53.172145 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 23:54:53.175857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 23:54:53.175938 ==
4070 23:54:53.176002 DQS Delay:
4071 23:54:53.178416 DQS0 = 0, DQS1 = 0
4072 23:54:53.178496 DQM Delay:
4073 23:54:53.182263 DQM0 = 43, DQM1 = 36
4074 23:54:53.182344 DQ Delay:
4075 23:54:53.185376 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4076 23:54:53.188649 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4077 23:54:53.192782 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4078 23:54:53.195674 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4079 23:54:53.196083
4080 23:54:53.196412
4081 23:54:53.196716 ==
4082 23:54:53.199100 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 23:54:53.202623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 23:54:53.203041 ==
4085 23:54:53.205664
4086 23:54:53.206080
4087 23:54:53.206409 TX Vref Scan disable
4088 23:54:53.208690 == TX Byte 0 ==
4089 23:54:53.212451 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4090 23:54:53.215140 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4091 23:54:53.218475 == TX Byte 1 ==
4092 23:54:53.222158 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4093 23:54:53.225417 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4094 23:54:53.225498 ==
4095 23:54:53.228468 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 23:54:53.235113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 23:54:53.235196 ==
4098 23:54:53.235261
4099 23:54:53.235320
4100 23:54:53.235377 TX Vref Scan disable
4101 23:54:53.239765 == TX Byte 0 ==
4102 23:54:53.243685 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4103 23:54:53.246638 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4104 23:54:53.249952 == TX Byte 1 ==
4105 23:54:53.253519 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4106 23:54:53.257157 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4107 23:54:53.260201
4108 23:54:53.260615 [DATLAT]
4109 23:54:53.260945 Freq=600, CH0 RK0
4110 23:54:53.261318
4111 23:54:53.263660 DATLAT Default: 0x9
4112 23:54:53.264076 0, 0xFFFF, sum = 0
4113 23:54:53.266829 1, 0xFFFF, sum = 0
4114 23:54:53.267251 2, 0xFFFF, sum = 0
4115 23:54:53.270785 3, 0xFFFF, sum = 0
4116 23:54:53.271206 4, 0xFFFF, sum = 0
4117 23:54:53.273737 5, 0xFFFF, sum = 0
4118 23:54:53.274278 6, 0xFFFF, sum = 0
4119 23:54:53.276935 7, 0xFFFF, sum = 0
4120 23:54:53.277404 8, 0x0, sum = 1
4121 23:54:53.280610 9, 0x0, sum = 2
4122 23:54:53.281119 10, 0x0, sum = 3
4123 23:54:53.283791 11, 0x0, sum = 4
4124 23:54:53.284263 best_step = 9
4125 23:54:53.284723
4126 23:54:53.285216 ==
4127 23:54:53.286901 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 23:54:53.293586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 23:54:53.294059 ==
4130 23:54:53.294478 RX Vref Scan: 1
4131 23:54:53.294941
4132 23:54:53.297230 RX Vref 0 -> 0, step: 1
4133 23:54:53.297712
4134 23:54:53.300467 RX Delay -179 -> 252, step: 8
4135 23:54:53.300935
4136 23:54:53.303869 Set Vref, RX VrefLevel [Byte0]: 53
4137 23:54:53.307227 [Byte1]: 53
4138 23:54:53.307731
4139 23:54:53.310376 Final RX Vref Byte 0 = 53 to rank0
4140 23:54:53.313629 Final RX Vref Byte 1 = 53 to rank0
4141 23:54:53.317302 Final RX Vref Byte 0 = 53 to rank1
4142 23:54:53.320338 Final RX Vref Byte 1 = 53 to rank1==
4143 23:54:53.323738 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 23:54:53.327045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 23:54:53.327494 ==
4146 23:54:53.330379 DQS Delay:
4147 23:54:53.330823 DQS0 = 0, DQS1 = 0
4148 23:54:53.331157 DQM Delay:
4149 23:54:53.333473 DQM0 = 42, DQM1 = 33
4150 23:54:53.333885 DQ Delay:
4151 23:54:53.337355 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4152 23:54:53.340647 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4153 23:54:53.343841 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4154 23:54:53.347249 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4155 23:54:53.347663
4156 23:54:53.347992
4157 23:54:53.357123 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4158 23:54:53.357542 CH0 RK0: MR19=808, MR18=3E1D
4159 23:54:53.363809 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4160 23:54:53.364224
4161 23:54:53.367091 ----->DramcWriteLeveling(PI) begin...
4162 23:54:53.367510 ==
4163 23:54:53.370259 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 23:54:53.377058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 23:54:53.377439 ==
4166 23:54:53.380356 Write leveling (Byte 0): 31 => 31
4167 23:54:53.380438 Write leveling (Byte 1): 29 => 29
4168 23:54:53.383870 DramcWriteLeveling(PI) end<-----
4169 23:54:53.383951
4170 23:54:53.387239 ==
4171 23:54:53.387321 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 23:54:53.393371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 23:54:53.393453 ==
4174 23:54:53.397200 [Gating] SW mode calibration
4175 23:54:53.403976 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4176 23:54:53.407381 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4177 23:54:53.414035 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 23:54:53.417060 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 23:54:53.420352 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 23:54:53.426792 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
4181 23:54:53.430475 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
4182 23:54:53.433433 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 23:54:53.440168 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 23:54:53.443644 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 23:54:53.447141 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 23:54:53.450030 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 23:54:53.457214 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 23:54:53.460636 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4189 23:54:53.463729 0 10 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
4190 23:54:53.470737 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 23:54:53.473812 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 23:54:53.477442 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 23:54:53.484014 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 23:54:53.487614 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 23:54:53.491039 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 23:54:53.497290 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 23:54:53.500481 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4198 23:54:53.504177 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 23:54:53.511330 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 23:54:53.514282 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 23:54:53.517339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 23:54:53.523967 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:54:53.527315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:54:53.530818 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:54:53.537107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:54:53.540693 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:54:53.544264 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:54:53.547558 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:54:53.553987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:54:53.557249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:54:53.560476 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4212 23:54:53.567260 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4213 23:54:53.570423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4214 23:54:53.573613 Total UI for P1: 0, mck2ui 16
4215 23:54:53.577324 best dqsien dly found for B0: ( 0, 13, 10)
4216 23:54:53.580625 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 23:54:53.583973 Total UI for P1: 0, mck2ui 16
4218 23:54:53.586932 best dqsien dly found for B1: ( 0, 13, 16)
4219 23:54:53.590645 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4220 23:54:53.594003 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4221 23:54:53.594438
4222 23:54:53.601336 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4223 23:54:53.604882 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4224 23:54:53.606985 [Gating] SW calibration Done
4225 23:54:53.607399 ==
4226 23:54:53.610233 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 23:54:53.613640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 23:54:53.614071 ==
4229 23:54:53.614428 RX Vref Scan: 0
4230 23:54:53.614735
4231 23:54:53.617190 RX Vref 0 -> 0, step: 1
4232 23:54:53.617599
4233 23:54:53.620388 RX Delay -230 -> 252, step: 16
4234 23:54:53.623682 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4235 23:54:53.630262 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4236 23:54:53.633891 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4237 23:54:53.636707 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4238 23:54:53.640438 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4239 23:54:53.643634 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4240 23:54:53.650303 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4241 23:54:53.653555 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4242 23:54:53.656772 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4243 23:54:53.660268 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4244 23:54:53.663308 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4245 23:54:53.670345 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4246 23:54:53.673605 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4247 23:54:53.677213 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4248 23:54:53.680376 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4249 23:54:53.686881 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4250 23:54:53.687474 ==
4251 23:54:53.690054 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 23:54:53.693493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 23:54:53.694077 ==
4254 23:54:53.694565 DQS Delay:
4255 23:54:53.696881 DQS0 = 0, DQS1 = 0
4256 23:54:53.697431 DQM Delay:
4257 23:54:53.699902 DQM0 = 38, DQM1 = 30
4258 23:54:53.700426 DQ Delay:
4259 23:54:53.703379 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4260 23:54:53.706584 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4261 23:54:53.710321 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4262 23:54:53.713712 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4263 23:54:53.714256
4264 23:54:53.714738
4265 23:54:53.715248 ==
4266 23:54:53.717024 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 23:54:53.720095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 23:54:53.720642 ==
4269 23:54:53.721193
4270 23:54:53.723715
4271 23:54:53.724220 TX Vref Scan disable
4272 23:54:53.726798 == TX Byte 0 ==
4273 23:54:53.731281 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4274 23:54:53.733529 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4275 23:54:53.737245 == TX Byte 1 ==
4276 23:54:53.740044 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4277 23:54:53.743700 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4278 23:54:53.744262 ==
4279 23:54:53.747191 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 23:54:53.753777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 23:54:53.754198 ==
4282 23:54:53.754557
4283 23:54:53.754872
4284 23:54:53.755167 TX Vref Scan disable
4285 23:54:53.758278 == TX Byte 0 ==
4286 23:54:53.761541 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 23:54:53.765036 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 23:54:53.768155 == TX Byte 1 ==
4289 23:54:53.771549 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4290 23:54:53.774884 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4291 23:54:53.778252
4292 23:54:53.778645 [DATLAT]
4293 23:54:53.779214 Freq=600, CH0 RK1
4294 23:54:53.779727
4295 23:54:53.781329 DATLAT Default: 0x9
4296 23:54:53.781877 0, 0xFFFF, sum = 0
4297 23:54:53.785032 1, 0xFFFF, sum = 0
4298 23:54:53.785560 2, 0xFFFF, sum = 0
4299 23:54:53.787923 3, 0xFFFF, sum = 0
4300 23:54:53.788429 4, 0xFFFF, sum = 0
4301 23:54:53.791410 5, 0xFFFF, sum = 0
4302 23:54:53.794521 6, 0xFFFF, sum = 0
4303 23:54:53.795042 7, 0xFFFF, sum = 0
4304 23:54:53.795509 8, 0x0, sum = 1
4305 23:54:53.798084 9, 0x0, sum = 2
4306 23:54:53.798538 10, 0x0, sum = 3
4307 23:54:53.801517 11, 0x0, sum = 4
4308 23:54:53.801817 best_step = 9
4309 23:54:53.802052
4310 23:54:53.802275 ==
4311 23:54:53.804549 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 23:54:53.811470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 23:54:53.811694 ==
4314 23:54:53.811871 RX Vref Scan: 0
4315 23:54:53.812037
4316 23:54:53.814953 RX Vref 0 -> 0, step: 1
4317 23:54:53.815175
4318 23:54:53.817846 RX Delay -195 -> 252, step: 8
4319 23:54:53.821554 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4320 23:54:53.827975 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4321 23:54:53.831121 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4322 23:54:53.834964 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4323 23:54:53.837816 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4324 23:54:53.841702 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4325 23:54:53.848400 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4326 23:54:53.851636 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4327 23:54:53.855248 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4328 23:54:53.858440 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4329 23:54:53.861839 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4330 23:54:53.868082 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4331 23:54:53.871612 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4332 23:54:53.874914 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4333 23:54:53.878256 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4334 23:54:53.885048 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4335 23:54:53.885444 ==
4336 23:54:53.888380 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 23:54:53.892135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 23:54:53.892711 ==
4339 23:54:53.893221 DQS Delay:
4340 23:54:53.895090 DQS0 = 0, DQS1 = 0
4341 23:54:53.895496 DQM Delay:
4342 23:54:53.898201 DQM0 = 40, DQM1 = 32
4343 23:54:53.898769 DQ Delay:
4344 23:54:53.901386 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4345 23:54:53.905260 DQ4 =36, DQ5 =28, DQ6 =52, DQ7 =48
4346 23:54:53.908257 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4347 23:54:53.911982 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4348 23:54:53.912623
4349 23:54:53.913255
4350 23:54:53.918659 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c2e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 395 ps
4351 23:54:53.921537 CH0 RK1: MR19=808, MR18=4C2E
4352 23:54:53.928459 CH0_RK1: MR19=0x808, MR18=0x4C2E, DQSOSC=395, MR23=63, INC=168, DEC=112
4353 23:54:53.931976 [RxdqsGatingPostProcess] freq 600
4354 23:54:53.938639 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4355 23:54:53.941712 Pre-setting of DQS Precalculation
4356 23:54:53.944836 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4357 23:54:53.945501 ==
4358 23:54:53.948593 Dram Type= 6, Freq= 0, CH_1, rank 0
4359 23:54:53.951504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 23:54:53.951920 ==
4361 23:54:53.958319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 23:54:53.964889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4363 23:54:53.968231 [CA 0] Center 35 (5~66) winsize 62
4364 23:54:53.971799 [CA 1] Center 35 (5~66) winsize 62
4365 23:54:53.974835 [CA 2] Center 34 (4~65) winsize 62
4366 23:54:53.978609 [CA 3] Center 33 (3~64) winsize 62
4367 23:54:53.981547 [CA 4] Center 34 (3~65) winsize 63
4368 23:54:53.985048 [CA 5] Center 33 (2~64) winsize 63
4369 23:54:53.985487
4370 23:54:53.988280 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4371 23:54:53.988793
4372 23:54:53.991904 [CATrainingPosCal] consider 1 rank data
4373 23:54:53.995168 u2DelayCellTimex100 = 270/100 ps
4374 23:54:53.998554 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 23:54:54.001785 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 23:54:54.005229 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 23:54:54.008773 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 23:54:54.012092 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4379 23:54:54.015436 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4380 23:54:54.015851
4381 23:54:54.022001 CA PerBit enable=1, Macro0, CA PI delay=33
4382 23:54:54.022496
4383 23:54:54.022823 [CBTSetCACLKResult] CA Dly = 33
4384 23:54:54.025445 CS Dly: 4 (0~35)
4385 23:54:54.025855 ==
4386 23:54:54.028601 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 23:54:54.032082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 23:54:54.032493 ==
4389 23:54:54.038765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 23:54:54.045110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 23:54:54.048753 [CA 0] Center 35 (5~66) winsize 62
4392 23:54:54.051841 [CA 1] Center 36 (6~66) winsize 61
4393 23:54:54.055277 [CA 2] Center 34 (3~65) winsize 63
4394 23:54:54.058342 [CA 3] Center 34 (3~65) winsize 63
4395 23:54:54.061762 [CA 4] Center 34 (3~65) winsize 63
4396 23:54:54.065429 [CA 5] Center 33 (3~64) winsize 62
4397 23:54:54.065862
4398 23:54:54.068880 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 23:54:54.069358
4400 23:54:54.072087 [CATrainingPosCal] consider 2 rank data
4401 23:54:54.075268 u2DelayCellTimex100 = 270/100 ps
4402 23:54:54.079255 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 23:54:54.082382 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4404 23:54:54.085459 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 23:54:54.088625 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 23:54:54.091695 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4407 23:54:54.095438 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 23:54:54.095861
4409 23:54:54.101925 CA PerBit enable=1, Macro0, CA PI delay=33
4410 23:54:54.102345
4411 23:54:54.102677 [CBTSetCACLKResult] CA Dly = 33
4412 23:54:54.105152 CS Dly: 4 (0~36)
4413 23:54:54.105575
4414 23:54:54.108922 ----->DramcWriteLeveling(PI) begin...
4415 23:54:54.109396 ==
4416 23:54:54.112161 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 23:54:54.115265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 23:54:54.115977 ==
4419 23:54:54.118890 Write leveling (Byte 0): 30 => 30
4420 23:54:54.122680 Write leveling (Byte 1): 30 => 30
4421 23:54:54.125565 DramcWriteLeveling(PI) end<-----
4422 23:54:54.125985
4423 23:54:54.126317 ==
4424 23:54:54.128497 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 23:54:54.132110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 23:54:54.132527 ==
4427 23:54:54.135564 [Gating] SW mode calibration
4428 23:54:54.142181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4429 23:54:54.148734 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4430 23:54:54.151951 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 23:54:54.159076 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4432 23:54:54.162227 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4433 23:54:54.165385 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4434 23:54:54.169036 0 9 16 | B1->B0 | 2525 2828 | 0 1 | (0 0) (1 0)
4435 23:54:54.175190 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 23:54:54.178875 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4437 23:54:54.182020 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 23:54:54.188851 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 23:54:54.191920 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 23:54:54.195741 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 23:54:54.202301 0 10 12 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
4442 23:54:54.205948 0 10 16 | B1->B0 | 3939 3e3e | 0 0 | (0 0) (0 0)
4443 23:54:54.208724 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 23:54:54.215132 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 23:54:54.218543 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 23:54:54.222503 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 23:54:54.228740 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 23:54:54.232306 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:54:54.235219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4450 23:54:54.242215 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4451 23:54:54.245327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 23:54:54.248938 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 23:54:54.255459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 23:54:54.258850 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 23:54:54.262249 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:54:54.268511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 23:54:54.272188 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:54:54.275835 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:54:54.278939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:54:54.285152 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:54:54.288554 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:54:54.292252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:54:54.298876 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:54:54.302540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:54:54.305359 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4466 23:54:54.312110 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 23:54:54.312532 Total UI for P1: 0, mck2ui 16
4468 23:54:54.319305 best dqsien dly found for B0: ( 0, 13, 12)
4469 23:54:54.319743 Total UI for P1: 0, mck2ui 16
4470 23:54:54.325878 best dqsien dly found for B1: ( 0, 13, 12)
4471 23:54:54.329390 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4472 23:54:54.332440 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4473 23:54:54.332858
4474 23:54:54.335472 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4475 23:54:54.338773 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 23:54:54.342541 [Gating] SW calibration Done
4477 23:54:54.343010 ==
4478 23:54:54.345878 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 23:54:54.349053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 23:54:54.349530 ==
4481 23:54:54.351944 RX Vref Scan: 0
4482 23:54:54.352526
4483 23:54:54.352956 RX Vref 0 -> 0, step: 1
4484 23:54:54.353357
4485 23:54:54.355309 RX Delay -230 -> 252, step: 16
4486 23:54:54.359419 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4487 23:54:54.365540 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4488 23:54:54.368957 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4489 23:54:54.372142 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4490 23:54:54.375519 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4491 23:54:54.382841 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4492 23:54:54.385882 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4493 23:54:54.389098 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4494 23:54:54.392226 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4495 23:54:54.395688 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4496 23:54:54.402162 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4497 23:54:54.405312 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4498 23:54:54.409045 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4499 23:54:54.411711 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4500 23:54:54.418554 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4501 23:54:54.422131 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4502 23:54:54.422213 ==
4503 23:54:54.425197 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 23:54:54.428614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 23:54:54.428721 ==
4506 23:54:54.432015 DQS Delay:
4507 23:54:54.432096 DQS0 = 0, DQS1 = 0
4508 23:54:54.432160 DQM Delay:
4509 23:54:54.435107 DQM0 = 45, DQM1 = 37
4510 23:54:54.435187 DQ Delay:
4511 23:54:54.439339 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4512 23:54:54.441948 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4513 23:54:54.445146 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4514 23:54:54.448539 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4515 23:54:54.448631
4516 23:54:54.448696
4517 23:54:54.448755 ==
4518 23:54:54.451972 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 23:54:54.458744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 23:54:54.458825 ==
4521 23:54:54.458890
4522 23:54:54.458949
4523 23:54:54.459007 TX Vref Scan disable
4524 23:54:54.461872 == TX Byte 0 ==
4525 23:54:54.465600 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 23:54:54.471936 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 23:54:54.472015 == TX Byte 1 ==
4528 23:54:54.475392 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 23:54:54.482235 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 23:54:54.482317 ==
4531 23:54:54.485601 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 23:54:54.488443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 23:54:54.488525 ==
4534 23:54:54.488590
4535 23:54:54.488650
4536 23:54:54.492106 TX Vref Scan disable
4537 23:54:54.492187 == TX Byte 0 ==
4538 23:54:54.498640 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4539 23:54:54.501893 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4540 23:54:54.501974 == TX Byte 1 ==
4541 23:54:54.508728 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 23:54:54.511863 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 23:54:54.511944
4544 23:54:54.512009 [DATLAT]
4545 23:54:54.515305 Freq=600, CH1 RK0
4546 23:54:54.515386
4547 23:54:54.515450 DATLAT Default: 0x9
4548 23:54:54.518660 0, 0xFFFF, sum = 0
4549 23:54:54.518758 1, 0xFFFF, sum = 0
4550 23:54:54.522477 2, 0xFFFF, sum = 0
4551 23:54:54.522559 3, 0xFFFF, sum = 0
4552 23:54:54.525654 4, 0xFFFF, sum = 0
4553 23:54:54.525737 5, 0xFFFF, sum = 0
4554 23:54:54.528923 6, 0xFFFF, sum = 0
4555 23:54:54.529013 7, 0xFFFF, sum = 0
4556 23:54:54.532211 8, 0x0, sum = 1
4557 23:54:54.532293 9, 0x0, sum = 2
4558 23:54:54.535951 10, 0x0, sum = 3
4559 23:54:54.536033 11, 0x0, sum = 4
4560 23:54:54.538962 best_step = 9
4561 23:54:54.539043
4562 23:54:54.539106 ==
4563 23:54:54.542077 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 23:54:54.545409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 23:54:54.545491 ==
4566 23:54:54.548608 RX Vref Scan: 1
4567 23:54:54.548689
4568 23:54:54.548753 RX Vref 0 -> 0, step: 1
4569 23:54:54.548813
4570 23:54:54.551995 RX Delay -179 -> 252, step: 8
4571 23:54:54.552076
4572 23:54:54.555674 Set Vref, RX VrefLevel [Byte0]: 57
4573 23:54:54.558550 [Byte1]: 52
4574 23:54:54.562159
4575 23:54:54.562241 Final RX Vref Byte 0 = 57 to rank0
4576 23:54:54.565931 Final RX Vref Byte 1 = 52 to rank0
4577 23:54:54.569179 Final RX Vref Byte 0 = 57 to rank1
4578 23:54:54.572997 Final RX Vref Byte 1 = 52 to rank1==
4579 23:54:54.575748 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 23:54:54.582745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 23:54:54.582835 ==
4582 23:54:54.582900 DQS Delay:
4583 23:54:54.582961 DQS0 = 0, DQS1 = 0
4584 23:54:54.586044 DQM Delay:
4585 23:54:54.586125 DQM0 = 41, DQM1 = 33
4586 23:54:54.589495 DQ Delay:
4587 23:54:54.592414 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4588 23:54:54.592499 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4589 23:54:54.595812 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4590 23:54:54.599012 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4591 23:54:54.602549
4592 23:54:54.602629
4593 23:54:54.609225 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4594 23:54:54.612578 CH1 RK0: MR19=808, MR18=3D04
4595 23:54:54.619388 CH1_RK0: MR19=0x808, MR18=0x3D04, DQSOSC=398, MR23=63, INC=165, DEC=110
4596 23:54:54.619471
4597 23:54:54.622719 ----->DramcWriteLeveling(PI) begin...
4598 23:54:54.622808 ==
4599 23:54:54.626061 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 23:54:54.629481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 23:54:54.629563 ==
4602 23:54:54.632458 Write leveling (Byte 0): 30 => 30
4603 23:54:54.635850 Write leveling (Byte 1): 32 => 32
4604 23:54:54.639361 DramcWriteLeveling(PI) end<-----
4605 23:54:54.639443
4606 23:54:54.639507 ==
4607 23:54:54.642866 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 23:54:54.646033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 23:54:54.646115 ==
4610 23:54:54.649369 [Gating] SW mode calibration
4611 23:54:54.655899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4612 23:54:54.662967 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4613 23:54:54.666202 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 23:54:54.669362 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 23:54:54.675968 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 23:54:54.679332 0 9 12 | B1->B0 | 3131 2d2d | 1 0 | (1 1) (0 0)
4617 23:54:54.682704 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4618 23:54:54.689466 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 23:54:54.693603 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 23:54:54.695919 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 23:54:54.699449 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 23:54:54.706720 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 23:54:54.709437 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4624 23:54:54.712570 0 10 12 | B1->B0 | 3131 3f3f | 0 0 | (0 0) (0 0)
4625 23:54:54.719406 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4626 23:54:54.722698 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 23:54:54.726084 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 23:54:54.732807 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 23:54:54.736118 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 23:54:54.739676 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 23:54:54.746519 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4632 23:54:54.750195 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4633 23:54:54.752965 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 23:54:54.759891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 23:54:54.763036 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 23:54:54.766278 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 23:54:54.769841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:54:54.776497 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:54:54.779685 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 23:54:54.782863 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:54:54.789410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:54:54.793315 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:54:54.796283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:54:54.803020 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:54:54.806767 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:54:54.809473 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:54:54.816442 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4648 23:54:54.819506 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4649 23:54:54.822867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 23:54:54.826622 Total UI for P1: 0, mck2ui 16
4651 23:54:54.829582 best dqsien dly found for B0: ( 0, 13, 10)
4652 23:54:54.832951 Total UI for P1: 0, mck2ui 16
4653 23:54:54.836181 best dqsien dly found for B1: ( 0, 13, 14)
4654 23:54:54.839955 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4655 23:54:54.843143 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4656 23:54:54.843225
4657 23:54:54.849616 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4658 23:54:54.853228 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4659 23:54:54.853309 [Gating] SW calibration Done
4660 23:54:54.856799 ==
4661 23:54:54.859709 Dram Type= 6, Freq= 0, CH_1, rank 1
4662 23:54:54.863055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4663 23:54:54.863137 ==
4664 23:54:54.863203 RX Vref Scan: 0
4665 23:54:54.863263
4666 23:54:54.866486 RX Vref 0 -> 0, step: 1
4667 23:54:54.866568
4668 23:54:54.869642 RX Delay -230 -> 252, step: 16
4669 23:54:54.873048 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4670 23:54:54.876173 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4671 23:54:54.882661 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4672 23:54:54.886389 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4673 23:54:54.889719 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4674 23:54:54.892986 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4675 23:54:54.896136 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4676 23:54:54.902712 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4677 23:54:54.906037 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4678 23:54:54.909971 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4679 23:54:54.913275 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4680 23:54:54.919745 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4681 23:54:54.923181 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4682 23:54:54.926644 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4683 23:54:54.930087 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4684 23:54:54.936537 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4685 23:54:54.936619 ==
4686 23:54:54.939866 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 23:54:54.943222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 23:54:54.943296 ==
4689 23:54:54.943359 DQS Delay:
4690 23:54:54.946647 DQS0 = 0, DQS1 = 0
4691 23:54:54.946728 DQM Delay:
4692 23:54:54.949946 DQM0 = 40, DQM1 = 34
4693 23:54:54.950028 DQ Delay:
4694 23:54:54.953442 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4695 23:54:54.956559 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4696 23:54:54.959870 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4697 23:54:54.962963 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4698 23:54:54.963044
4699 23:54:54.963118
4700 23:54:54.963180 ==
4701 23:54:54.966146 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 23:54:54.970252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 23:54:54.970335 ==
4704 23:54:54.970399
4705 23:54:54.970459
4706 23:54:54.973275 TX Vref Scan disable
4707 23:54:54.976603 == TX Byte 0 ==
4708 23:54:54.980047 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4709 23:54:54.983031 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4710 23:54:54.986509 == TX Byte 1 ==
4711 23:54:54.990026 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4712 23:54:54.993168 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4713 23:54:54.993275 ==
4714 23:54:54.996104 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 23:54:55.000072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 23:54:55.003473 ==
4717 23:54:55.003554
4718 23:54:55.003618
4719 23:54:55.003678 TX Vref Scan disable
4720 23:54:55.006918 == TX Byte 0 ==
4721 23:54:55.010340 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 23:54:55.014018 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 23:54:55.017118 == TX Byte 1 ==
4724 23:54:55.020458 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4725 23:54:55.023652 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4726 23:54:55.027024
4727 23:54:55.027109 [DATLAT]
4728 23:54:55.027210 Freq=600, CH1 RK1
4729 23:54:55.027309
4730 23:54:55.030744 DATLAT Default: 0x9
4731 23:54:55.030824 0, 0xFFFF, sum = 0
4732 23:54:55.033772 1, 0xFFFF, sum = 0
4733 23:54:55.033854 2, 0xFFFF, sum = 0
4734 23:54:55.036892 3, 0xFFFF, sum = 0
4735 23:54:55.037043 4, 0xFFFF, sum = 0
4736 23:54:55.040162 5, 0xFFFF, sum = 0
4737 23:54:55.040244 6, 0xFFFF, sum = 0
4738 23:54:55.043765 7, 0xFFFF, sum = 0
4739 23:54:55.043880 8, 0x0, sum = 1
4740 23:54:55.047153 9, 0x0, sum = 2
4741 23:54:55.047263 10, 0x0, sum = 3
4742 23:54:55.050787 11, 0x0, sum = 4
4743 23:54:55.050900 best_step = 9
4744 23:54:55.050998
4745 23:54:55.051062 ==
4746 23:54:55.054216 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 23:54:55.060713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 23:54:55.060795 ==
4749 23:54:55.060859 RX Vref Scan: 0
4750 23:54:55.060920
4751 23:54:55.064378 RX Vref 0 -> 0, step: 1
4752 23:54:55.064458
4753 23:54:55.067043 RX Delay -195 -> 252, step: 8
4754 23:54:55.071225 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4755 23:54:55.073607 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4756 23:54:55.080683 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4757 23:54:55.083943 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4758 23:54:55.087094 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4759 23:54:55.090752 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4760 23:54:55.094307 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4761 23:54:55.100783 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4762 23:54:55.104159 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4763 23:54:55.107565 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4764 23:54:55.110994 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4765 23:54:55.117474 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4766 23:54:55.120714 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4767 23:54:55.123694 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4768 23:54:55.127463 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4769 23:54:55.133841 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4770 23:54:55.133930 ==
4771 23:54:55.137142 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 23:54:55.140495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 23:54:55.140603 ==
4774 23:54:55.140704 DQS Delay:
4775 23:54:55.144128 DQS0 = 0, DQS1 = 0
4776 23:54:55.144209 DQM Delay:
4777 23:54:55.147776 DQM0 = 38, DQM1 = 33
4778 23:54:55.147856 DQ Delay:
4779 23:54:55.150494 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4780 23:54:55.154120 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4781 23:54:55.157597 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4782 23:54:55.160427 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4783 23:54:55.160507
4784 23:54:55.160571
4785 23:54:55.167979 [DQSOSCAuto] RK1, (LSB)MR18= 0x3140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4786 23:54:55.170862 CH1 RK1: MR19=808, MR18=3140
4787 23:54:55.178059 CH1_RK1: MR19=0x808, MR18=0x3140, DQSOSC=397, MR23=63, INC=166, DEC=110
4788 23:54:55.180473 [RxdqsGatingPostProcess] freq 600
4789 23:54:55.187269 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4790 23:54:55.190563 Pre-setting of DQS Precalculation
4791 23:54:55.193777 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4792 23:54:55.201392 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4793 23:54:55.207574 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4794 23:54:55.207691
4795 23:54:55.207791
4796 23:54:55.210471 [Calibration Summary] 1200 Mbps
4797 23:54:55.214551 CH 0, Rank 0
4798 23:54:55.214661 SW Impedance : PASS
4799 23:54:55.217661 DUTY Scan : NO K
4800 23:54:55.220569 ZQ Calibration : PASS
4801 23:54:55.220675 Jitter Meter : NO K
4802 23:54:55.224375 CBT Training : PASS
4803 23:54:55.224456 Write leveling : PASS
4804 23:54:55.227292 RX DQS gating : PASS
4805 23:54:55.230909 RX DQ/DQS(RDDQC) : PASS
4806 23:54:55.230990 TX DQ/DQS : PASS
4807 23:54:55.233865 RX DATLAT : PASS
4808 23:54:55.237125 RX DQ/DQS(Engine): PASS
4809 23:54:55.237206 TX OE : NO K
4810 23:54:55.240402 All Pass.
4811 23:54:55.240498
4812 23:54:55.240562 CH 0, Rank 1
4813 23:54:55.243896 SW Impedance : PASS
4814 23:54:55.243977 DUTY Scan : NO K
4815 23:54:55.247169 ZQ Calibration : PASS
4816 23:54:55.250630 Jitter Meter : NO K
4817 23:54:55.250712 CBT Training : PASS
4818 23:54:55.254091 Write leveling : PASS
4819 23:54:55.257144 RX DQS gating : PASS
4820 23:54:55.257224 RX DQ/DQS(RDDQC) : PASS
4821 23:54:55.260525 TX DQ/DQS : PASS
4822 23:54:55.260648 RX DATLAT : PASS
4823 23:54:55.264099 RX DQ/DQS(Engine): PASS
4824 23:54:55.267163 TX OE : NO K
4825 23:54:55.267271 All Pass.
4826 23:54:55.267363
4827 23:54:55.267452 CH 1, Rank 0
4828 23:54:55.270510 SW Impedance : PASS
4829 23:54:55.273994 DUTY Scan : NO K
4830 23:54:55.274075 ZQ Calibration : PASS
4831 23:54:55.277763 Jitter Meter : NO K
4832 23:54:55.280858 CBT Training : PASS
4833 23:54:55.280939 Write leveling : PASS
4834 23:54:55.284303 RX DQS gating : PASS
4835 23:54:55.287742 RX DQ/DQS(RDDQC) : PASS
4836 23:54:55.287848 TX DQ/DQS : PASS
4837 23:54:55.290794 RX DATLAT : PASS
4838 23:54:55.294198 RX DQ/DQS(Engine): PASS
4839 23:54:55.294277 TX OE : NO K
4840 23:54:55.294359 All Pass.
4841 23:54:55.297532
4842 23:54:55.297635 CH 1, Rank 1
4843 23:54:55.301317 SW Impedance : PASS
4844 23:54:55.301422 DUTY Scan : NO K
4845 23:54:55.304050 ZQ Calibration : PASS
4846 23:54:55.307537 Jitter Meter : NO K
4847 23:54:55.307637 CBT Training : PASS
4848 23:54:55.310348 Write leveling : PASS
4849 23:54:55.314117 RX DQS gating : PASS
4850 23:54:55.314243 RX DQ/DQS(RDDQC) : PASS
4851 23:54:55.317159 TX DQ/DQS : PASS
4852 23:54:55.317241 RX DATLAT : PASS
4853 23:54:55.320918 RX DQ/DQS(Engine): PASS
4854 23:54:55.324213 TX OE : NO K
4855 23:54:55.324322 All Pass.
4856 23:54:55.324421
4857 23:54:55.327310 DramC Write-DBI off
4858 23:54:55.327392 PER_BANK_REFRESH: Hybrid Mode
4859 23:54:55.330988 TX_TRACKING: ON
4860 23:54:55.340336 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4861 23:54:55.343620 [FAST_K] Save calibration result to emmc
4862 23:54:55.347358 dramc_set_vcore_voltage set vcore to 662500
4863 23:54:55.347440 Read voltage for 933, 3
4864 23:54:55.350844 Vio18 = 0
4865 23:54:55.350926 Vcore = 662500
4866 23:54:55.350990 Vdram = 0
4867 23:54:55.353862 Vddq = 0
4868 23:54:55.353963 Vmddr = 0
4869 23:54:55.357187 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4870 23:54:55.363743 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4871 23:54:55.366684 MEM_TYPE=3, freq_sel=17
4872 23:54:55.370879 sv_algorithm_assistance_LP4_1600
4873 23:54:55.373487 ============ PULL DRAM RESETB DOWN ============
4874 23:54:55.377013 ========== PULL DRAM RESETB DOWN end =========
4875 23:54:55.383569 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4876 23:54:55.387018 ===================================
4877 23:54:55.387100 LPDDR4 DRAM CONFIGURATION
4878 23:54:55.390162 ===================================
4879 23:54:55.393805 EX_ROW_EN[0] = 0x0
4880 23:54:55.393886 EX_ROW_EN[1] = 0x0
4881 23:54:55.397020 LP4Y_EN = 0x0
4882 23:54:55.397100 WORK_FSP = 0x0
4883 23:54:55.401129 WL = 0x3
4884 23:54:55.403437 RL = 0x3
4885 23:54:55.403517 BL = 0x2
4886 23:54:55.407071 RPST = 0x0
4887 23:54:55.407151 RD_PRE = 0x0
4888 23:54:55.410374 WR_PRE = 0x1
4889 23:54:55.410454 WR_PST = 0x0
4890 23:54:55.414147 DBI_WR = 0x0
4891 23:54:55.414232 DBI_RD = 0x0
4892 23:54:55.416389 OTF = 0x1
4893 23:54:55.420427 ===================================
4894 23:54:55.423335 ===================================
4895 23:54:55.423415 ANA top config
4896 23:54:55.426565 ===================================
4897 23:54:55.430158 DLL_ASYNC_EN = 0
4898 23:54:55.433606 ALL_SLAVE_EN = 1
4899 23:54:55.433687 NEW_RANK_MODE = 1
4900 23:54:55.437076 DLL_IDLE_MODE = 1
4901 23:54:55.440062 LP45_APHY_COMB_EN = 1
4902 23:54:55.443274 TX_ODT_DIS = 1
4903 23:54:55.443356 NEW_8X_MODE = 1
4904 23:54:55.446579 ===================================
4905 23:54:55.449876 ===================================
4906 23:54:55.453768 data_rate = 1866
4907 23:54:55.457088 CKR = 1
4908 23:54:55.459823 DQ_P2S_RATIO = 8
4909 23:54:55.463518 ===================================
4910 23:54:55.467049 CA_P2S_RATIO = 8
4911 23:54:55.470047 DQ_CA_OPEN = 0
4912 23:54:55.470128 DQ_SEMI_OPEN = 0
4913 23:54:55.473408 CA_SEMI_OPEN = 0
4914 23:54:55.476665 CA_FULL_RATE = 0
4915 23:54:55.480087 DQ_CKDIV4_EN = 1
4916 23:54:55.483549 CA_CKDIV4_EN = 1
4917 23:54:55.486609 CA_PREDIV_EN = 0
4918 23:54:55.486689 PH8_DLY = 0
4919 23:54:55.489775 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4920 23:54:55.492859 DQ_AAMCK_DIV = 4
4921 23:54:55.496519 CA_AAMCK_DIV = 4
4922 23:54:55.499797 CA_ADMCK_DIV = 4
4923 23:54:55.503274 DQ_TRACK_CA_EN = 0
4924 23:54:55.506524 CA_PICK = 933
4925 23:54:55.506605 CA_MCKIO = 933
4926 23:54:55.509824 MCKIO_SEMI = 0
4927 23:54:55.513276 PLL_FREQ = 3732
4928 23:54:55.516228 DQ_UI_PI_RATIO = 32
4929 23:54:55.519627 CA_UI_PI_RATIO = 0
4930 23:54:55.523288 ===================================
4931 23:54:55.526542 ===================================
4932 23:54:55.529714 memory_type:LPDDR4
4933 23:54:55.529795 GP_NUM : 10
4934 23:54:55.533223 SRAM_EN : 1
4935 23:54:55.533304 MD32_EN : 0
4936 23:54:55.536361 ===================================
4937 23:54:55.539807 [ANA_INIT] >>>>>>>>>>>>>>
4938 23:54:55.542873 <<<<<< [CONFIGURE PHASE]: ANA_TX
4939 23:54:55.546577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4940 23:54:55.549382 ===================================
4941 23:54:55.552872 data_rate = 1866,PCW = 0X8f00
4942 23:54:55.556308 ===================================
4943 23:54:55.560159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4944 23:54:55.563063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4945 23:54:55.569646 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 23:54:55.573203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4947 23:54:55.579661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4948 23:54:55.583137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4949 23:54:55.583236 [ANA_INIT] flow start
4950 23:54:55.586281 [ANA_INIT] PLL >>>>>>>>
4951 23:54:55.589315 [ANA_INIT] PLL <<<<<<<<
4952 23:54:55.589426 [ANA_INIT] MIDPI >>>>>>>>
4953 23:54:55.592919 [ANA_INIT] MIDPI <<<<<<<<
4954 23:54:55.596305 [ANA_INIT] DLL >>>>>>>>
4955 23:54:55.596380 [ANA_INIT] flow end
4956 23:54:55.599401 ============ LP4 DIFF to SE enter ============
4957 23:54:55.606448 ============ LP4 DIFF to SE exit ============
4958 23:54:55.606549 [ANA_INIT] <<<<<<<<<<<<<
4959 23:54:55.609810 [Flow] Enable top DCM control >>>>>
4960 23:54:55.613146 [Flow] Enable top DCM control <<<<<
4961 23:54:55.616447 Enable DLL master slave shuffle
4962 23:54:55.623011 ==============================================================
4963 23:54:55.623109 Gating Mode config
4964 23:54:55.629580 ==============================================================
4965 23:54:55.633065 Config description:
4966 23:54:55.643249 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4967 23:54:55.650009 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4968 23:54:55.653158 SELPH_MODE 0: By rank 1: By Phase
4969 23:54:55.659206 ==============================================================
4970 23:54:55.662591 GAT_TRACK_EN = 1
4971 23:54:55.662666 RX_GATING_MODE = 2
4972 23:54:55.665880 RX_GATING_TRACK_MODE = 2
4973 23:54:55.669796 SELPH_MODE = 1
4974 23:54:55.673169 PICG_EARLY_EN = 1
4975 23:54:55.676028 VALID_LAT_VALUE = 1
4976 23:54:55.683010 ==============================================================
4977 23:54:55.685976 Enter into Gating configuration >>>>
4978 23:54:55.689674 Exit from Gating configuration <<<<
4979 23:54:55.692449 Enter into DVFS_PRE_config >>>>>
4980 23:54:55.702745 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4981 23:54:55.706361 Exit from DVFS_PRE_config <<<<<
4982 23:54:55.709282 Enter into PICG configuration >>>>
4983 23:54:55.712639 Exit from PICG configuration <<<<
4984 23:54:55.716530 [RX_INPUT] configuration >>>>>
4985 23:54:55.716602 [RX_INPUT] configuration <<<<<
4986 23:54:55.722591 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4987 23:54:55.729563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4988 23:54:55.736481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 23:54:55.739478 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 23:54:55.745965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4991 23:54:55.753511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4992 23:54:55.756565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4993 23:54:55.759884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4994 23:54:55.766094 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4995 23:54:55.770098 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4996 23:54:55.772922 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4997 23:54:55.779399 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 23:54:55.783063 ===================================
4999 23:54:55.783144 LPDDR4 DRAM CONFIGURATION
5000 23:54:55.786237 ===================================
5001 23:54:55.789498 EX_ROW_EN[0] = 0x0
5002 23:54:55.789577 EX_ROW_EN[1] = 0x0
5003 23:54:55.793193 LP4Y_EN = 0x0
5004 23:54:55.793298 WORK_FSP = 0x0
5005 23:54:55.796606 WL = 0x3
5006 23:54:55.796686 RL = 0x3
5007 23:54:55.799735 BL = 0x2
5008 23:54:55.799818 RPST = 0x0
5009 23:54:55.802861 RD_PRE = 0x0
5010 23:54:55.802941 WR_PRE = 0x1
5011 23:54:55.806616 WR_PST = 0x0
5012 23:54:55.809746 DBI_WR = 0x0
5013 23:54:55.809825 DBI_RD = 0x0
5014 23:54:55.812999 OTF = 0x1
5015 23:54:55.816317 ===================================
5016 23:54:55.819683 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5017 23:54:55.823013 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5018 23:54:55.826616 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5019 23:54:55.829617 ===================================
5020 23:54:55.832878 LPDDR4 DRAM CONFIGURATION
5021 23:54:55.836563 ===================================
5022 23:54:55.839897 EX_ROW_EN[0] = 0x10
5023 23:54:55.839978 EX_ROW_EN[1] = 0x0
5024 23:54:55.843706 LP4Y_EN = 0x0
5025 23:54:55.843786 WORK_FSP = 0x0
5026 23:54:55.846380 WL = 0x3
5027 23:54:55.846461 RL = 0x3
5028 23:54:55.849867 BL = 0x2
5029 23:54:55.849947 RPST = 0x0
5030 23:54:55.853105 RD_PRE = 0x0
5031 23:54:55.853185 WR_PRE = 0x1
5032 23:54:55.856519 WR_PST = 0x0
5033 23:54:55.856599 DBI_WR = 0x0
5034 23:54:55.859990 DBI_RD = 0x0
5035 23:54:55.860070 OTF = 0x1
5036 23:54:55.863457 ===================================
5037 23:54:55.869824 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5038 23:54:55.875087 nWR fixed to 30
5039 23:54:55.877947 [ModeRegInit_LP4] CH0 RK0
5040 23:54:55.878027 [ModeRegInit_LP4] CH0 RK1
5041 23:54:55.881100 [ModeRegInit_LP4] CH1 RK0
5042 23:54:55.884323 [ModeRegInit_LP4] CH1 RK1
5043 23:54:55.884403 match AC timing 9
5044 23:54:55.891060 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5045 23:54:55.894250 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5046 23:54:55.897659 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5047 23:54:55.904411 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5048 23:54:55.907901 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5049 23:54:55.907982 ==
5050 23:54:55.911209 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 23:54:55.914557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 23:54:55.914637 ==
5053 23:54:55.921266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 23:54:55.928175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5055 23:54:55.931838 [CA 0] Center 38 (8~69) winsize 62
5056 23:54:55.935106 [CA 1] Center 38 (7~69) winsize 63
5057 23:54:55.938634 [CA 2] Center 35 (5~66) winsize 62
5058 23:54:55.941444 [CA 3] Center 34 (4~65) winsize 62
5059 23:54:55.944817 [CA 4] Center 34 (4~64) winsize 61
5060 23:54:55.948365 [CA 5] Center 34 (4~64) winsize 61
5061 23:54:55.948781
5062 23:54:55.951708 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5063 23:54:55.952121
5064 23:54:55.954692 [CATrainingPosCal] consider 1 rank data
5065 23:54:55.958712 u2DelayCellTimex100 = 270/100 ps
5066 23:54:55.961442 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5067 23:54:55.964916 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5068 23:54:55.968017 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5069 23:54:55.971734 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5070 23:54:55.974962 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5071 23:54:55.977957 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5072 23:54:55.978429
5073 23:54:55.984768 CA PerBit enable=1, Macro0, CA PI delay=34
5074 23:54:55.985383
5075 23:54:55.985873 [CBTSetCACLKResult] CA Dly = 34
5076 23:54:55.988288 CS Dly: 6 (0~37)
5077 23:54:55.988701 ==
5078 23:54:55.992022 Dram Type= 6, Freq= 0, CH_0, rank 1
5079 23:54:55.994992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 23:54:55.995514 ==
5081 23:54:56.001675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 23:54:56.008658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 23:54:56.011732 [CA 0] Center 38 (8~69) winsize 62
5084 23:54:56.014477 [CA 1] Center 38 (8~69) winsize 62
5085 23:54:56.017797 [CA 2] Center 35 (5~66) winsize 62
5086 23:54:56.021440 [CA 3] Center 35 (4~66) winsize 63
5087 23:54:56.024807 [CA 4] Center 33 (3~64) winsize 62
5088 23:54:56.027944 [CA 5] Center 33 (3~64) winsize 62
5089 23:54:56.028024
5090 23:54:56.031654 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 23:54:56.031735
5092 23:54:56.034510 [CATrainingPosCal] consider 2 rank data
5093 23:54:56.038220 u2DelayCellTimex100 = 270/100 ps
5094 23:54:56.041509 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5095 23:54:56.044825 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5096 23:54:56.048165 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5097 23:54:56.051143 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5098 23:54:56.054689 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5099 23:54:56.057879 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5100 23:54:56.057959
5101 23:54:56.061181 CA PerBit enable=1, Macro0, CA PI delay=34
5102 23:54:56.061261
5103 23:54:56.064847 [CBTSetCACLKResult] CA Dly = 34
5104 23:54:56.067974 CS Dly: 7 (0~39)
5105 23:54:56.068054
5106 23:54:56.071200 ----->DramcWriteLeveling(PI) begin...
5107 23:54:56.071280 ==
5108 23:54:56.074501 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 23:54:56.078076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 23:54:56.078157 ==
5111 23:54:56.081653 Write leveling (Byte 0): 31 => 31
5112 23:54:56.084919 Write leveling (Byte 1): 29 => 29
5113 23:54:56.088130 DramcWriteLeveling(PI) end<-----
5114 23:54:56.088226
5115 23:54:56.088295 ==
5116 23:54:56.091463 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 23:54:56.095216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 23:54:56.095297 ==
5119 23:54:56.098422 [Gating] SW mode calibration
5120 23:54:56.104650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5121 23:54:56.111471 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5122 23:54:56.114687 0 14 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5123 23:54:56.118438 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5124 23:54:56.124506 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 23:54:56.128175 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 23:54:56.131097 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 23:54:56.137894 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 23:54:56.141271 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 23:54:56.145233 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5130 23:54:56.151513 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
5131 23:54:56.154820 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5132 23:54:56.158125 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 23:54:56.164589 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 23:54:56.167853 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 23:54:56.171706 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 23:54:56.178065 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 23:54:56.181557 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5138 23:54:56.184865 1 0 0 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
5139 23:54:56.191568 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 23:54:56.194569 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 23:54:56.198018 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 23:54:56.204885 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 23:54:56.207790 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 23:54:56.211481 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:54:56.214606 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5146 23:54:56.221471 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5147 23:54:56.224983 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 23:54:56.228069 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 23:54:56.235153 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 23:54:56.238042 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 23:54:56.241618 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 23:54:56.248091 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 23:54:56.251755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 23:54:56.254814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:54:56.261709 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:54:56.264870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:54:56.267889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:54:56.274721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:54:56.277967 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:54:56.281852 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:54:56.288170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5162 23:54:56.291271 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5163 23:54:56.294883 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 23:54:56.298309 Total UI for P1: 0, mck2ui 16
5165 23:54:56.301815 best dqsien dly found for B0: ( 1, 2, 30)
5166 23:54:56.304882 Total UI for P1: 0, mck2ui 16
5167 23:54:56.308458 best dqsien dly found for B1: ( 1, 2, 30)
5168 23:54:56.311908 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5169 23:54:56.315079 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5170 23:54:56.315160
5171 23:54:56.318160 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5172 23:54:56.321443 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5173 23:54:56.325136 [Gating] SW calibration Done
5174 23:54:56.325217 ==
5175 23:54:56.328552 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 23:54:56.335333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 23:54:56.335415 ==
5178 23:54:56.335480 RX Vref Scan: 0
5179 23:54:56.335540
5180 23:54:56.338295 RX Vref 0 -> 0, step: 1
5181 23:54:56.338392
5182 23:54:56.341651 RX Delay -80 -> 252, step: 8
5183 23:54:56.346105 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5184 23:54:56.348459 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5185 23:54:56.351448 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5186 23:54:56.355116 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5187 23:54:56.358650 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5188 23:54:56.365021 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5189 23:54:56.368235 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5190 23:54:56.371547 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5191 23:54:56.375319 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5192 23:54:56.378339 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5193 23:54:56.384937 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5194 23:54:56.388281 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5195 23:54:56.391380 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5196 23:54:56.394884 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5197 23:54:56.398460 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5198 23:54:56.401517 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5199 23:54:56.401599 ==
5200 23:54:56.405162 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 23:54:56.411411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 23:54:56.411493 ==
5203 23:54:56.411559 DQS Delay:
5204 23:54:56.414882 DQS0 = 0, DQS1 = 0
5205 23:54:56.414964 DQM Delay:
5206 23:54:56.418377 DQM0 = 97, DQM1 = 87
5207 23:54:56.418458 DQ Delay:
5208 23:54:56.421336 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5209 23:54:56.424673 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5210 23:54:56.428265 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5211 23:54:56.431914 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5212 23:54:56.431995
5213 23:54:56.432060
5214 23:54:56.432120 ==
5215 23:54:56.434861 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 23:54:56.438114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 23:54:56.438237 ==
5218 23:54:56.438338
5219 23:54:56.438428
5220 23:54:56.441889 TX Vref Scan disable
5221 23:54:56.445095 == TX Byte 0 ==
5222 23:54:56.448150 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5223 23:54:56.451443 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5224 23:54:56.454758 == TX Byte 1 ==
5225 23:54:56.457964 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5226 23:54:56.461323 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5227 23:54:56.461404 ==
5228 23:54:56.464611 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 23:54:56.468649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 23:54:56.471492 ==
5231 23:54:56.471572
5232 23:54:56.471637
5233 23:54:56.471697 TX Vref Scan disable
5234 23:54:56.475459 == TX Byte 0 ==
5235 23:54:56.478639 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5236 23:54:56.481600 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5237 23:54:56.485013 == TX Byte 1 ==
5238 23:54:56.488577 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5239 23:54:56.491459 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5240 23:54:56.494732
5241 23:54:56.494812 [DATLAT]
5242 23:54:56.494878 Freq=933, CH0 RK0
5243 23:54:56.494939
5244 23:54:56.498153 DATLAT Default: 0xd
5245 23:54:56.498234 0, 0xFFFF, sum = 0
5246 23:54:56.501815 1, 0xFFFF, sum = 0
5247 23:54:56.501899 2, 0xFFFF, sum = 0
5248 23:54:56.505227 3, 0xFFFF, sum = 0
5249 23:54:56.505309 4, 0xFFFF, sum = 0
5250 23:54:56.509093 5, 0xFFFF, sum = 0
5251 23:54:56.509180 6, 0xFFFF, sum = 0
5252 23:54:56.511866 7, 0xFFFF, sum = 0
5253 23:54:56.515074 8, 0xFFFF, sum = 0
5254 23:54:56.515161 9, 0xFFFF, sum = 0
5255 23:54:56.515228 10, 0x0, sum = 1
5256 23:54:56.518607 11, 0x0, sum = 2
5257 23:54:56.518690 12, 0x0, sum = 3
5258 23:54:56.522253 13, 0x0, sum = 4
5259 23:54:56.522335 best_step = 11
5260 23:54:56.522399
5261 23:54:56.522458 ==
5262 23:54:56.524924 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 23:54:56.531668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 23:54:56.531749 ==
5265 23:54:56.531815 RX Vref Scan: 1
5266 23:54:56.531876
5267 23:54:56.534967 RX Vref 0 -> 0, step: 1
5268 23:54:56.535048
5269 23:54:56.538075 RX Delay -61 -> 252, step: 4
5270 23:54:56.538156
5271 23:54:56.541861 Set Vref, RX VrefLevel [Byte0]: 53
5272 23:54:56.545177 [Byte1]: 53
5273 23:54:56.545258
5274 23:54:56.548364 Final RX Vref Byte 0 = 53 to rank0
5275 23:54:56.551436 Final RX Vref Byte 1 = 53 to rank0
5276 23:54:56.554983 Final RX Vref Byte 0 = 53 to rank1
5277 23:54:56.558783 Final RX Vref Byte 1 = 53 to rank1==
5278 23:54:56.561489 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:54:56.564875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:54:56.564957 ==
5281 23:54:56.567995 DQS Delay:
5282 23:54:56.568075 DQS0 = 0, DQS1 = 0
5283 23:54:56.571738 DQM Delay:
5284 23:54:56.571819 DQM0 = 97, DQM1 = 89
5285 23:54:56.571883 DQ Delay:
5286 23:54:56.575302 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5287 23:54:56.578255 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =102
5288 23:54:56.581688 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5289 23:54:56.584662 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5290 23:54:56.584744
5291 23:54:56.584808
5292 23:54:56.594610 [DQSOSCAuto] RK0, (LSB)MR18= 0xffb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 417 ps
5293 23:54:56.597979 CH0 RK0: MR19=504, MR18=FFB
5294 23:54:56.604893 CH0_RK0: MR19=0x504, MR18=0xFFB, DQSOSC=417, MR23=63, INC=62, DEC=41
5295 23:54:56.605019
5296 23:54:56.607746 ----->DramcWriteLeveling(PI) begin...
5297 23:54:56.607828 ==
5298 23:54:56.611165 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 23:54:56.615165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 23:54:56.615246 ==
5301 23:54:56.617716 Write leveling (Byte 0): 32 => 32
5302 23:54:56.621505 Write leveling (Byte 1): 31 => 31
5303 23:54:56.624857 DramcWriteLeveling(PI) end<-----
5304 23:54:56.624937
5305 23:54:56.625040 ==
5306 23:54:56.627936 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 23:54:56.631144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 23:54:56.631226 ==
5309 23:54:56.635005 [Gating] SW mode calibration
5310 23:54:56.641360 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5311 23:54:56.648177 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5312 23:54:56.651494 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5313 23:54:56.654897 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 23:54:56.661639 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 23:54:56.664712 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 23:54:56.668252 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 23:54:56.671483 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 23:54:56.677916 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 23:54:56.681597 0 14 28 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
5320 23:54:56.684543 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5321 23:54:56.691365 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 23:54:56.694460 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 23:54:56.698463 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 23:54:56.704901 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 23:54:56.707993 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 23:54:56.711554 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 23:54:56.718057 0 15 28 | B1->B0 | 2626 3232 | 0 0 | (0 0) (1 1)
5328 23:54:56.721158 1 0 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5329 23:54:56.724642 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 23:54:56.731090 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 23:54:56.734755 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 23:54:56.738326 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 23:54:56.744393 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 23:54:56.748254 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5335 23:54:56.751232 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5336 23:54:56.758353 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5337 23:54:56.760953 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 23:54:56.764425 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 23:54:56.771483 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 23:54:56.774476 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 23:54:56.778109 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 23:54:56.781279 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 23:54:56.788102 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 23:54:56.791470 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:54:56.794994 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:54:56.800902 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:54:56.804471 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:54:56.807613 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:54:56.814477 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5350 23:54:56.817649 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5351 23:54:56.821502 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5352 23:54:56.824609 Total UI for P1: 0, mck2ui 16
5353 23:54:56.827833 best dqsien dly found for B0: ( 1, 2, 22)
5354 23:54:56.834598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5355 23:54:56.837891 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 23:54:56.840785 Total UI for P1: 0, mck2ui 16
5357 23:54:56.844184 best dqsien dly found for B1: ( 1, 2, 30)
5358 23:54:56.847913 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5359 23:54:56.851265 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5360 23:54:56.851352
5361 23:54:56.854696 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5362 23:54:56.857837 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5363 23:54:56.861249 [Gating] SW calibration Done
5364 23:54:56.861330 ==
5365 23:54:56.864731 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 23:54:56.867611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 23:54:56.870951 ==
5368 23:54:56.871033 RX Vref Scan: 0
5369 23:54:56.871098
5370 23:54:56.874640 RX Vref 0 -> 0, step: 1
5371 23:54:56.874730
5372 23:54:56.874839 RX Delay -80 -> 252, step: 8
5373 23:54:56.881281 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5374 23:54:56.884719 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5375 23:54:56.888146 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5376 23:54:56.891461 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5377 23:54:56.894968 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5378 23:54:56.897686 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5379 23:54:56.904651 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5380 23:54:56.908067 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5381 23:54:56.911221 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5382 23:54:56.914403 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5383 23:54:56.918012 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5384 23:54:56.924424 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5385 23:54:56.927828 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5386 23:54:56.931437 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5387 23:54:56.934731 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5388 23:54:56.937680 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5389 23:54:56.937764 ==
5390 23:54:56.941213 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 23:54:56.944762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 23:54:56.947841 ==
5393 23:54:56.947923 DQS Delay:
5394 23:54:56.947989 DQS0 = 0, DQS1 = 0
5395 23:54:56.950969 DQM Delay:
5396 23:54:56.951051 DQM0 = 96, DQM1 = 87
5397 23:54:56.954387 DQ Delay:
5398 23:54:56.957599 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5399 23:54:56.961424 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5400 23:54:56.961506 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5401 23:54:56.968099 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5402 23:54:56.968181
5403 23:54:56.968246
5404 23:54:56.968307 ==
5405 23:54:56.971465 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 23:54:56.974681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 23:54:56.974764 ==
5408 23:54:56.974839
5409 23:54:56.974905
5410 23:54:56.977631 TX Vref Scan disable
5411 23:54:56.977713 == TX Byte 0 ==
5412 23:54:56.984139 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5413 23:54:56.987910 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5414 23:54:56.987992 == TX Byte 1 ==
5415 23:54:56.994385 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5416 23:54:56.998083 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5417 23:54:56.998165 ==
5418 23:54:57.001064 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 23:54:57.004426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 23:54:57.004508 ==
5421 23:54:57.004573
5422 23:54:57.004634
5423 23:54:57.007701 TX Vref Scan disable
5424 23:54:57.011503 == TX Byte 0 ==
5425 23:54:57.014125 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5426 23:54:57.017418 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5427 23:54:57.020797 == TX Byte 1 ==
5428 23:54:57.024577 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5429 23:54:57.027510 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5430 23:54:57.027598
5431 23:54:57.030946 [DATLAT]
5432 23:54:57.031026 Freq=933, CH0 RK1
5433 23:54:57.031091
5434 23:54:57.034619 DATLAT Default: 0xb
5435 23:54:57.034737 0, 0xFFFF, sum = 0
5436 23:54:57.037473 1, 0xFFFF, sum = 0
5437 23:54:57.037556 2, 0xFFFF, sum = 0
5438 23:54:57.041034 3, 0xFFFF, sum = 0
5439 23:54:57.041121 4, 0xFFFF, sum = 0
5440 23:54:57.044761 5, 0xFFFF, sum = 0
5441 23:54:57.044844 6, 0xFFFF, sum = 0
5442 23:54:57.047671 7, 0xFFFF, sum = 0
5443 23:54:57.047753 8, 0xFFFF, sum = 0
5444 23:54:57.050962 9, 0xFFFF, sum = 0
5445 23:54:57.051046 10, 0x0, sum = 1
5446 23:54:57.054518 11, 0x0, sum = 2
5447 23:54:57.054600 12, 0x0, sum = 3
5448 23:54:57.058011 13, 0x0, sum = 4
5449 23:54:57.058093 best_step = 11
5450 23:54:57.058158
5451 23:54:57.058218 ==
5452 23:54:57.061145 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 23:54:57.064372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 23:54:57.067660 ==
5455 23:54:57.067758 RX Vref Scan: 0
5456 23:54:57.067822
5457 23:54:57.070945 RX Vref 0 -> 0, step: 1
5458 23:54:57.071026
5459 23:54:57.074632 RX Delay -61 -> 252, step: 4
5460 23:54:57.077731 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5461 23:54:57.081268 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5462 23:54:57.084376 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5463 23:54:57.091438 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5464 23:54:57.094507 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5465 23:54:57.097903 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5466 23:54:57.101278 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5467 23:54:57.104448 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5468 23:54:57.111796 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5469 23:54:57.114617 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5470 23:54:57.117700 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5471 23:54:57.120860 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5472 23:54:57.124274 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5473 23:54:57.128157 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5474 23:54:57.134085 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5475 23:54:57.138016 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5476 23:54:57.138098 ==
5477 23:54:57.141261 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 23:54:57.144423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 23:54:57.144504 ==
5480 23:54:57.144569 DQS Delay:
5481 23:54:57.147513 DQS0 = 0, DQS1 = 0
5482 23:54:57.147593 DQM Delay:
5483 23:54:57.151224 DQM0 = 95, DQM1 = 88
5484 23:54:57.151305 DQ Delay:
5485 23:54:57.154737 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5486 23:54:57.157919 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =102
5487 23:54:57.160637 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5488 23:54:57.164352 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5489 23:54:57.164454
5490 23:54:57.164520
5491 23:54:57.174203 [DQSOSCAuto] RK1, (LSB)MR18= 0x1705, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5492 23:54:57.174285 CH0 RK1: MR19=505, MR18=1705
5493 23:54:57.180949 CH0_RK1: MR19=0x505, MR18=0x1705, DQSOSC=414, MR23=63, INC=63, DEC=42
5494 23:54:57.184244 [RxdqsGatingPostProcess] freq 933
5495 23:54:57.190733 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5496 23:54:57.194304 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 23:54:57.197696 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 23:54:57.200920 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 23:54:57.204436 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 23:54:57.204516 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 23:54:57.207658 best DQS1 dly(2T, 0.5T) = (0, 10)
5502 23:54:57.210677 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 23:54:57.214389 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5504 23:54:57.217466 Pre-setting of DQS Precalculation
5505 23:54:57.224860 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5506 23:54:57.224942 ==
5507 23:54:57.227538 Dram Type= 6, Freq= 0, CH_1, rank 0
5508 23:54:57.230833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 23:54:57.230915 ==
5510 23:54:57.237682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 23:54:57.244336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5512 23:54:57.247618 [CA 0] Center 36 (6~67) winsize 62
5513 23:54:57.251197 [CA 1] Center 36 (6~67) winsize 62
5514 23:54:57.253987 [CA 2] Center 34 (4~64) winsize 61
5515 23:54:57.257708 [CA 3] Center 33 (3~64) winsize 62
5516 23:54:57.257790 [CA 4] Center 34 (4~64) winsize 61
5517 23:54:57.261272 [CA 5] Center 32 (2~63) winsize 62
5518 23:54:57.261352
5519 23:54:57.267411 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5520 23:54:57.267492
5521 23:54:57.270867 [CATrainingPosCal] consider 1 rank data
5522 23:54:57.274011 u2DelayCellTimex100 = 270/100 ps
5523 23:54:57.277674 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5524 23:54:57.281206 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5525 23:54:57.284110 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5526 23:54:57.287683 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5527 23:54:57.290877 CA4 delay=34 (4~64),Diff = 2 PI (12 cell)
5528 23:54:57.294288 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5529 23:54:57.294369
5530 23:54:57.297354 CA PerBit enable=1, Macro0, CA PI delay=32
5531 23:54:57.297435
5532 23:54:57.300844 [CBTSetCACLKResult] CA Dly = 32
5533 23:54:57.303847 CS Dly: 4 (0~35)
5534 23:54:57.303927 ==
5535 23:54:57.307203 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 23:54:57.310695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 23:54:57.310778 ==
5538 23:54:57.317464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 23:54:57.323858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5540 23:54:57.327534 [CA 0] Center 36 (6~67) winsize 62
5541 23:54:57.330699 [CA 1] Center 36 (6~67) winsize 62
5542 23:54:57.333790 [CA 2] Center 33 (3~64) winsize 62
5543 23:54:57.337161 [CA 3] Center 33 (3~64) winsize 62
5544 23:54:57.340838 [CA 4] Center 34 (3~65) winsize 63
5545 23:54:57.344112 [CA 5] Center 33 (2~64) winsize 63
5546 23:54:57.344192
5547 23:54:57.347588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5548 23:54:57.347670
5549 23:54:57.350798 [CATrainingPosCal] consider 2 rank data
5550 23:54:57.353907 u2DelayCellTimex100 = 270/100 ps
5551 23:54:57.357515 CA0 delay=36 (6~67),Diff = 4 PI (24 cell)
5552 23:54:57.360558 CA1 delay=36 (6~67),Diff = 4 PI (24 cell)
5553 23:54:57.364274 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5554 23:54:57.367119 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5555 23:54:57.370580 CA4 delay=34 (4~64),Diff = 2 PI (12 cell)
5556 23:54:57.373873 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5557 23:54:57.373955
5558 23:54:57.377191 CA PerBit enable=1, Macro0, CA PI delay=32
5559 23:54:57.380497
5560 23:54:57.380578 [CBTSetCACLKResult] CA Dly = 32
5561 23:54:57.383961 CS Dly: 5 (0~37)
5562 23:54:57.384042
5563 23:54:57.387410 ----->DramcWriteLeveling(PI) begin...
5564 23:54:57.387493 ==
5565 23:54:57.390651 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 23:54:57.394230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 23:54:57.394311 ==
5568 23:54:57.397482 Write leveling (Byte 0): 29 => 29
5569 23:54:57.400768 Write leveling (Byte 1): 31 => 31
5570 23:54:57.403944 DramcWriteLeveling(PI) end<-----
5571 23:54:57.404025
5572 23:54:57.404089 ==
5573 23:54:57.407204 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 23:54:57.410611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 23:54:57.410693 ==
5576 23:54:57.414235 [Gating] SW mode calibration
5577 23:54:57.421051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5578 23:54:57.427630 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5579 23:54:57.431022 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5580 23:54:57.437318 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5581 23:54:57.440889 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 23:54:57.443962 0 14 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5583 23:54:57.451188 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 23:54:57.453944 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 23:54:57.458055 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 23:54:57.461237 0 14 28 | B1->B0 | 3232 3232 | 0 1 | (0 0) (1 0)
5587 23:54:57.467955 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5588 23:54:57.470962 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5589 23:54:57.474093 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5590 23:54:57.480815 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5591 23:54:57.484235 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5592 23:54:57.487710 0 15 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5593 23:54:57.494545 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 23:54:57.497643 0 15 28 | B1->B0 | 3131 2a2a | 0 0 | (1 1) (0 0)
5595 23:54:57.501471 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5596 23:54:57.508126 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 23:54:57.511310 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 23:54:57.514478 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 23:54:57.521111 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 23:54:57.524442 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 23:54:57.528144 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5602 23:54:57.531572 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5603 23:54:57.537829 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5604 23:54:57.541066 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 23:54:57.544477 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 23:54:57.551269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 23:54:57.554820 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 23:54:57.558088 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 23:54:57.564605 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 23:54:57.567725 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:54:57.571337 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:54:57.578180 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:54:57.581209 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:54:57.584860 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:54:57.591492 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:54:57.594428 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:54:57.597674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:54:57.604400 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5619 23:54:57.608395 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5620 23:54:57.611416 Total UI for P1: 0, mck2ui 16
5621 23:54:57.614727 best dqsien dly found for B1: ( 1, 2, 28)
5622 23:54:57.617873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 23:54:57.621386 Total UI for P1: 0, mck2ui 16
5624 23:54:57.625713 best dqsien dly found for B0: ( 1, 2, 30)
5625 23:54:57.627865 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5626 23:54:57.631247 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5627 23:54:57.631694
5628 23:54:57.635018 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5629 23:54:57.637780 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5630 23:54:57.641436 [Gating] SW calibration Done
5631 23:54:57.641847 ==
5632 23:54:57.644780 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 23:54:57.651350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 23:54:57.651809 ==
5635 23:54:57.652301 RX Vref Scan: 0
5636 23:54:57.652658
5637 23:54:57.654797 RX Vref 0 -> 0, step: 1
5638 23:54:57.655218
5639 23:54:57.658222 RX Delay -80 -> 252, step: 8
5640 23:54:57.661289 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5641 23:54:57.664908 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5642 23:54:57.668086 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5643 23:54:57.671044 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5644 23:54:57.674766 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5645 23:54:57.681243 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5646 23:54:57.685096 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5647 23:54:57.687982 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5648 23:54:57.691330 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5649 23:54:57.694755 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5650 23:54:57.701305 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5651 23:54:57.704577 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5652 23:54:57.708015 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5653 23:54:57.711397 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5654 23:54:57.714846 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5655 23:54:57.718047 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5656 23:54:57.721094 ==
5657 23:54:57.721515 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 23:54:57.728338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 23:54:57.728759 ==
5660 23:54:57.729128 DQS Delay:
5661 23:54:57.731714 DQS0 = 0, DQS1 = 0
5662 23:54:57.732131 DQM Delay:
5663 23:54:57.734969 DQM0 = 96, DQM1 = 88
5664 23:54:57.735563 DQ Delay:
5665 23:54:57.737825 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5666 23:54:57.741261 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5667 23:54:57.744854 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5668 23:54:57.748261 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5669 23:54:57.748737
5670 23:54:57.749220
5671 23:54:57.749576 ==
5672 23:54:57.751485 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 23:54:57.754582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 23:54:57.755153 ==
5675 23:54:57.755673
5676 23:54:57.756137
5677 23:54:57.758265 TX Vref Scan disable
5678 23:54:57.761650 == TX Byte 0 ==
5679 23:54:57.764925 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5680 23:54:57.768319 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5681 23:54:57.771611 == TX Byte 1 ==
5682 23:54:57.774913 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5683 23:54:57.777936 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5684 23:54:57.778502 ==
5685 23:54:57.781238 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 23:54:57.784801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 23:54:57.785426 ==
5688 23:54:57.788381
5689 23:54:57.788829
5690 23:54:57.789276 TX Vref Scan disable
5691 23:54:57.791890 == TX Byte 0 ==
5692 23:54:57.794466 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5693 23:54:57.801127 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5694 23:54:57.801542 == TX Byte 1 ==
5695 23:54:57.804891 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5696 23:54:57.811314 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5697 23:54:57.811864
5698 23:54:57.812355 [DATLAT]
5699 23:54:57.812782 Freq=933, CH1 RK0
5700 23:54:57.813249
5701 23:54:57.814853 DATLAT Default: 0xd
5702 23:54:57.815423 0, 0xFFFF, sum = 0
5703 23:54:57.818143 1, 0xFFFF, sum = 0
5704 23:54:57.818715 2, 0xFFFF, sum = 0
5705 23:54:57.821633 3, 0xFFFF, sum = 0
5706 23:54:57.822074 4, 0xFFFF, sum = 0
5707 23:54:57.824914 5, 0xFFFF, sum = 0
5708 23:54:57.825518 6, 0xFFFF, sum = 0
5709 23:54:57.828615 7, 0xFFFF, sum = 0
5710 23:54:57.829072 8, 0xFFFF, sum = 0
5711 23:54:57.831493 9, 0xFFFF, sum = 0
5712 23:54:57.831949 10, 0x0, sum = 1
5713 23:54:57.835567 11, 0x0, sum = 2
5714 23:54:57.836020 12, 0x0, sum = 3
5715 23:54:57.838181 13, 0x0, sum = 4
5716 23:54:57.838600 best_step = 11
5717 23:54:57.838983
5718 23:54:57.839298 ==
5719 23:54:57.842124 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 23:54:57.847977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 23:54:57.848398 ==
5722 23:54:57.848733 RX Vref Scan: 1
5723 23:54:57.849114
5724 23:54:57.851358 RX Vref 0 -> 0, step: 1
5725 23:54:57.851819
5726 23:54:57.855135 RX Delay -61 -> 252, step: 4
5727 23:54:57.855573
5728 23:54:57.858618 Set Vref, RX VrefLevel [Byte0]: 57
5729 23:54:57.861871 [Byte1]: 52
5730 23:54:57.862360
5731 23:54:57.864686 Final RX Vref Byte 0 = 57 to rank0
5732 23:54:57.868215 Final RX Vref Byte 1 = 52 to rank0
5733 23:54:57.871394 Final RX Vref Byte 0 = 57 to rank1
5734 23:54:57.875000 Final RX Vref Byte 1 = 52 to rank1==
5735 23:54:57.878533 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 23:54:57.881439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 23:54:57.882014 ==
5738 23:54:57.885342 DQS Delay:
5739 23:54:57.885754 DQS0 = 0, DQS1 = 0
5740 23:54:57.886235 DQM Delay:
5741 23:54:57.888434 DQM0 = 97, DQM1 = 90
5742 23:54:57.889060 DQ Delay:
5743 23:54:57.891868 DQ0 =100, DQ1 =90, DQ2 =86, DQ3 =96
5744 23:54:57.894713 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5745 23:54:57.898405 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5746 23:54:57.901950 DQ12 =96, DQ13 =98, DQ14 =94, DQ15 =96
5747 23:54:57.902374
5748 23:54:57.902707
5749 23:54:57.911533 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5750 23:54:57.915006 CH1 RK0: MR19=504, MR18=12EE
5751 23:54:57.918033 CH1_RK0: MR19=0x504, MR18=0x12EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5752 23:54:57.918453
5753 23:54:57.921675 ----->DramcWriteLeveling(PI) begin...
5754 23:54:57.924686 ==
5755 23:54:57.928631 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 23:54:57.931748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 23:54:57.932167 ==
5758 23:54:57.934930 Write leveling (Byte 0): 29 => 29
5759 23:54:57.938387 Write leveling (Byte 1): 31 => 31
5760 23:54:57.941292 DramcWriteLeveling(PI) end<-----
5761 23:54:57.941726
5762 23:54:57.942062 ==
5763 23:54:57.945102 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 23:54:57.947929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 23:54:57.948354 ==
5766 23:54:57.951943 [Gating] SW mode calibration
5767 23:54:57.958405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5768 23:54:57.961699 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5769 23:54:57.968157 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5770 23:54:57.971559 0 14 4 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5771 23:54:57.974873 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5772 23:54:57.981460 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 23:54:57.984949 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 23:54:57.988251 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 23:54:57.994887 0 14 24 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
5776 23:54:57.998295 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5777 23:54:58.001807 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5778 23:54:58.008154 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 23:54:58.011196 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5780 23:54:58.014914 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 23:54:58.021524 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 23:54:58.024397 0 15 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5783 23:54:58.028415 0 15 24 | B1->B0 | 2d2d 3535 | 0 0 | (0 0) (0 0)
5784 23:54:58.034692 0 15 28 | B1->B0 | 3939 4343 | 0 1 | (1 1) (0 0)
5785 23:54:58.037900 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 23:54:58.041564 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 23:54:58.047775 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 23:54:58.051306 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 23:54:58.054939 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 23:54:58.060836 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5791 23:54:58.064678 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5792 23:54:58.067943 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 23:54:58.074127 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 23:54:58.078158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 23:54:58.081213 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 23:54:58.087856 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 23:54:58.091598 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 23:54:58.094768 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 23:54:58.097807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:54:58.104639 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:54:58.107972 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:54:58.111497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:54:58.118377 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:54:58.121233 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:54:58.124718 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:54:58.131128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5807 23:54:58.134996 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5808 23:54:58.137794 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 23:54:58.141603 Total UI for P1: 0, mck2ui 16
5810 23:54:58.144666 best dqsien dly found for B0: ( 1, 2, 22)
5811 23:54:58.147769 Total UI for P1: 0, mck2ui 16
5812 23:54:58.151047 best dqsien dly found for B1: ( 1, 2, 24)
5813 23:54:58.154364 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5814 23:54:58.157786 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5815 23:54:58.158384
5816 23:54:58.164578 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5817 23:54:58.167786 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5818 23:54:58.168347 [Gating] SW calibration Done
5819 23:54:58.171441 ==
5820 23:54:58.171985 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 23:54:58.178392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 23:54:58.179009 ==
5823 23:54:58.179552 RX Vref Scan: 0
5824 23:54:58.180090
5825 23:54:58.181498 RX Vref 0 -> 0, step: 1
5826 23:54:58.181918
5827 23:54:58.184563 RX Delay -80 -> 252, step: 8
5828 23:54:58.188414 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5829 23:54:58.191282 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5830 23:54:58.194668 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5831 23:54:58.198388 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5832 23:54:58.204628 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5833 23:54:58.207871 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5834 23:54:58.211398 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5835 23:54:58.214392 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5836 23:54:58.217622 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5837 23:54:58.224366 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5838 23:54:58.227920 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5839 23:54:58.230849 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5840 23:54:58.234642 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5841 23:54:58.237850 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5842 23:54:58.241035 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5843 23:54:58.247594 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5844 23:54:58.248010 ==
5845 23:54:58.251221 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 23:54:58.254642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 23:54:58.255057 ==
5848 23:54:58.255388 DQS Delay:
5849 23:54:58.257767 DQS0 = 0, DQS1 = 0
5850 23:54:58.258205 DQM Delay:
5851 23:54:58.261202 DQM0 = 94, DQM1 = 89
5852 23:54:58.261617 DQ Delay:
5853 23:54:58.264526 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5854 23:54:58.267605 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5855 23:54:58.270921 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5856 23:54:58.274776 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5857 23:54:58.275266
5858 23:54:58.275604
5859 23:54:58.275912 ==
5860 23:54:58.278202 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 23:54:58.281078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 23:54:58.281498 ==
5863 23:54:58.281830
5864 23:54:58.282137
5865 23:54:58.284725 TX Vref Scan disable
5866 23:54:58.287831 == TX Byte 0 ==
5867 23:54:58.291487 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5868 23:54:58.294927 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5869 23:54:58.298024 == TX Byte 1 ==
5870 23:54:58.301461 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5871 23:54:58.304685 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5872 23:54:58.305255 ==
5873 23:54:58.307880 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 23:54:58.311486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 23:54:58.314710 ==
5876 23:54:58.315129
5877 23:54:58.315460
5878 23:54:58.315772 TX Vref Scan disable
5879 23:54:58.318218 == TX Byte 0 ==
5880 23:54:58.321574 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5881 23:54:58.328435 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5882 23:54:58.328856 == TX Byte 1 ==
5883 23:54:58.331751 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5884 23:54:58.338442 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5885 23:54:58.339008
5886 23:54:58.339377 [DATLAT]
5887 23:54:58.339692 Freq=933, CH1 RK1
5888 23:54:58.339997
5889 23:54:58.341586 DATLAT Default: 0xb
5890 23:54:58.342017 0, 0xFFFF, sum = 0
5891 23:54:58.345113 1, 0xFFFF, sum = 0
5892 23:54:58.345687 2, 0xFFFF, sum = 0
5893 23:54:58.348387 3, 0xFFFF, sum = 0
5894 23:54:58.348826 4, 0xFFFF, sum = 0
5895 23:54:58.351483 5, 0xFFFF, sum = 0
5896 23:54:58.351905 6, 0xFFFF, sum = 0
5897 23:54:58.354988 7, 0xFFFF, sum = 0
5898 23:54:58.358169 8, 0xFFFF, sum = 0
5899 23:54:58.358590 9, 0xFFFF, sum = 0
5900 23:54:58.361582 10, 0x0, sum = 1
5901 23:54:58.362005 11, 0x0, sum = 2
5902 23:54:58.362342 12, 0x0, sum = 3
5903 23:54:58.364851 13, 0x0, sum = 4
5904 23:54:58.365317 best_step = 11
5905 23:54:58.365653
5906 23:54:58.365964 ==
5907 23:54:58.367943 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 23:54:58.374853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 23:54:58.375321 ==
5910 23:54:58.375667 RX Vref Scan: 0
5911 23:54:58.375978
5912 23:54:58.378198 RX Vref 0 -> 0, step: 1
5913 23:54:58.378610
5914 23:54:58.381510 RX Delay -61 -> 252, step: 4
5915 23:54:58.385292 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5916 23:54:58.391208 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5917 23:54:58.395408 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5918 23:54:58.398219 iDelay=195, Bit 3, Center 92 (-1 ~ 186) 188
5919 23:54:58.401411 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5920 23:54:58.404735 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5921 23:54:58.408189 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5922 23:54:58.415125 iDelay=195, Bit 7, Center 88 (-1 ~ 178) 180
5923 23:54:58.417961 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5924 23:54:58.421725 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5925 23:54:58.425257 iDelay=195, Bit 10, Center 90 (-5 ~ 186) 192
5926 23:54:58.427860 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5927 23:54:58.431757 iDelay=195, Bit 12, Center 98 (11 ~ 186) 176
5928 23:54:58.438036 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5929 23:54:58.441950 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5930 23:54:58.444758 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5931 23:54:58.445304 ==
5932 23:54:58.448596 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 23:54:58.451721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 23:54:58.452312 ==
5935 23:54:58.454997 DQS Delay:
5936 23:54:58.455467 DQS0 = 0, DQS1 = 0
5937 23:54:58.456047 DQM Delay:
5938 23:54:58.458552 DQM0 = 94, DQM1 = 90
5939 23:54:58.459005 DQ Delay:
5940 23:54:58.462090 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5941 23:54:58.465077 DQ4 =98, DQ5 =104, DQ6 =102, DQ7 =88
5942 23:54:58.468162 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5943 23:54:58.471330 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5944 23:54:58.471780
5945 23:54:58.472112
5946 23:54:58.481664 [DQSOSCAuto] RK1, (LSB)MR18= 0x1019, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5947 23:54:58.485350 CH1 RK1: MR19=505, MR18=1019
5948 23:54:58.488426 CH1_RK1: MR19=0x505, MR18=0x1019, DQSOSC=413, MR23=63, INC=63, DEC=42
5949 23:54:58.491496 [RxdqsGatingPostProcess] freq 933
5950 23:54:58.498300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5951 23:54:58.501707 best DQS0 dly(2T, 0.5T) = (0, 10)
5952 23:54:58.504825 best DQS1 dly(2T, 0.5T) = (0, 10)
5953 23:54:58.508280 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5954 23:54:58.511832 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5955 23:54:58.515108 best DQS0 dly(2T, 0.5T) = (0, 10)
5956 23:54:58.518114 best DQS1 dly(2T, 0.5T) = (0, 10)
5957 23:54:58.521681 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5958 23:54:58.522096 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5959 23:54:58.525013 Pre-setting of DQS Precalculation
5960 23:54:58.532295 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5961 23:54:58.538474 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5962 23:54:58.545122 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5963 23:54:58.545598
5964 23:54:58.545969
5965 23:54:58.548500 [Calibration Summary] 1866 Mbps
5966 23:54:58.548920 CH 0, Rank 0
5967 23:54:58.551686 SW Impedance : PASS
5968 23:54:58.555339 DUTY Scan : NO K
5969 23:54:58.555861 ZQ Calibration : PASS
5970 23:54:58.558545 Jitter Meter : NO K
5971 23:54:58.561719 CBT Training : PASS
5972 23:54:58.562149 Write leveling : PASS
5973 23:54:58.565346 RX DQS gating : PASS
5974 23:54:58.568710 RX DQ/DQS(RDDQC) : PASS
5975 23:54:58.569349 TX DQ/DQS : PASS
5976 23:54:58.571743 RX DATLAT : PASS
5977 23:54:58.575145 RX DQ/DQS(Engine): PASS
5978 23:54:58.575660 TX OE : NO K
5979 23:54:58.578415 All Pass.
5980 23:54:58.579002
5981 23:54:58.579539 CH 0, Rank 1
5982 23:54:58.582000 SW Impedance : PASS
5983 23:54:58.582437 DUTY Scan : NO K
5984 23:54:58.585130 ZQ Calibration : PASS
5985 23:54:58.588650 Jitter Meter : NO K
5986 23:54:58.589111 CBT Training : PASS
5987 23:54:58.591886 Write leveling : PASS
5988 23:54:58.592299 RX DQS gating : PASS
5989 23:54:58.595322 RX DQ/DQS(RDDQC) : PASS
5990 23:54:58.599002 TX DQ/DQS : PASS
5991 23:54:58.599418 RX DATLAT : PASS
5992 23:54:58.601979 RX DQ/DQS(Engine): PASS
5993 23:54:58.605053 TX OE : NO K
5994 23:54:58.605484 All Pass.
5995 23:54:58.605917
5996 23:54:58.606329 CH 1, Rank 0
5997 23:54:58.608567 SW Impedance : PASS
5998 23:54:58.611599 DUTY Scan : NO K
5999 23:54:58.612051 ZQ Calibration : PASS
6000 23:54:58.615676 Jitter Meter : NO K
6001 23:54:58.619102 CBT Training : PASS
6002 23:54:58.619566 Write leveling : PASS
6003 23:54:58.622110 RX DQS gating : PASS
6004 23:54:58.625325 RX DQ/DQS(RDDQC) : PASS
6005 23:54:58.625772 TX DQ/DQS : PASS
6006 23:54:58.628540 RX DATLAT : PASS
6007 23:54:58.628967 RX DQ/DQS(Engine): PASS
6008 23:54:58.631854 TX OE : NO K
6009 23:54:58.632281 All Pass.
6010 23:54:58.632715
6011 23:54:58.635212 CH 1, Rank 1
6012 23:54:58.635637 SW Impedance : PASS
6013 23:54:58.638905 DUTY Scan : NO K
6014 23:54:58.641937 ZQ Calibration : PASS
6015 23:54:58.642365 Jitter Meter : NO K
6016 23:54:58.645139 CBT Training : PASS
6017 23:54:58.648349 Write leveling : PASS
6018 23:54:58.648813 RX DQS gating : PASS
6019 23:54:58.652154 RX DQ/DQS(RDDQC) : PASS
6020 23:54:58.655388 TX DQ/DQS : PASS
6021 23:54:58.655920 RX DATLAT : PASS
6022 23:54:58.658666 RX DQ/DQS(Engine): PASS
6023 23:54:58.662069 TX OE : NO K
6024 23:54:58.662709 All Pass.
6025 23:54:58.663195
6026 23:54:58.663546 DramC Write-DBI off
6027 23:54:58.665446 PER_BANK_REFRESH: Hybrid Mode
6028 23:54:58.668771 TX_TRACKING: ON
6029 23:54:58.676042 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6030 23:54:58.678933 [FAST_K] Save calibration result to emmc
6031 23:54:58.685794 dramc_set_vcore_voltage set vcore to 650000
6032 23:54:58.686266 Read voltage for 400, 6
6033 23:54:58.686600 Vio18 = 0
6034 23:54:58.688593 Vcore = 650000
6035 23:54:58.689167 Vdram = 0
6036 23:54:58.689688 Vddq = 0
6037 23:54:58.692211 Vmddr = 0
6038 23:54:58.695867 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6039 23:54:58.702149 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6040 23:54:58.702574 MEM_TYPE=3, freq_sel=20
6041 23:54:58.705306 sv_algorithm_assistance_LP4_800
6042 23:54:58.712307 ============ PULL DRAM RESETB DOWN ============
6043 23:54:58.715566 ========== PULL DRAM RESETB DOWN end =========
6044 23:54:58.718772 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6045 23:54:58.722209 ===================================
6046 23:54:58.725717 LPDDR4 DRAM CONFIGURATION
6047 23:54:58.728764 ===================================
6048 23:54:58.732054 EX_ROW_EN[0] = 0x0
6049 23:54:58.732549 EX_ROW_EN[1] = 0x0
6050 23:54:58.735588 LP4Y_EN = 0x0
6051 23:54:58.736143 WORK_FSP = 0x0
6052 23:54:58.738835 WL = 0x2
6053 23:54:58.739344 RL = 0x2
6054 23:54:58.742215 BL = 0x2
6055 23:54:58.742653 RPST = 0x0
6056 23:54:58.745422 RD_PRE = 0x0
6057 23:54:58.746048 WR_PRE = 0x1
6058 23:54:58.748715 WR_PST = 0x0
6059 23:54:58.749288 DBI_WR = 0x0
6060 23:54:58.751980 DBI_RD = 0x0
6061 23:54:58.752405 OTF = 0x1
6062 23:54:58.755376 ===================================
6063 23:54:58.759002 ===================================
6064 23:54:58.762248 ANA top config
6065 23:54:58.765648 ===================================
6066 23:54:58.766181 DLL_ASYNC_EN = 0
6067 23:54:58.768502 ALL_SLAVE_EN = 1
6068 23:54:58.772336 NEW_RANK_MODE = 1
6069 23:54:58.775594 DLL_IDLE_MODE = 1
6070 23:54:58.778853 LP45_APHY_COMB_EN = 1
6071 23:54:58.779416 TX_ODT_DIS = 1
6072 23:54:58.782409 NEW_8X_MODE = 1
6073 23:54:58.785850 ===================================
6074 23:54:58.789251 ===================================
6075 23:54:58.792543 data_rate = 800
6076 23:54:58.795378 CKR = 1
6077 23:54:58.799051 DQ_P2S_RATIO = 4
6078 23:54:58.802722 ===================================
6079 23:54:58.803138 CA_P2S_RATIO = 4
6080 23:54:58.805569 DQ_CA_OPEN = 0
6081 23:54:58.809052 DQ_SEMI_OPEN = 1
6082 23:54:58.812098 CA_SEMI_OPEN = 1
6083 23:54:58.815669 CA_FULL_RATE = 0
6084 23:54:58.818951 DQ_CKDIV4_EN = 0
6085 23:54:58.819362 CA_CKDIV4_EN = 1
6086 23:54:58.822006 CA_PREDIV_EN = 0
6087 23:54:58.825649 PH8_DLY = 0
6088 23:54:58.829175 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6089 23:54:58.831800 DQ_AAMCK_DIV = 0
6090 23:54:58.835487 CA_AAMCK_DIV = 0
6091 23:54:58.835902 CA_ADMCK_DIV = 4
6092 23:54:58.838508 DQ_TRACK_CA_EN = 0
6093 23:54:58.842174 CA_PICK = 800
6094 23:54:58.845281 CA_MCKIO = 400
6095 23:54:58.848320 MCKIO_SEMI = 400
6096 23:54:58.852060 PLL_FREQ = 3016
6097 23:54:58.855594 DQ_UI_PI_RATIO = 32
6098 23:54:58.856083 CA_UI_PI_RATIO = 32
6099 23:54:58.858627 ===================================
6100 23:54:58.862659 ===================================
6101 23:54:58.865352 memory_type:LPDDR4
6102 23:54:58.868403 GP_NUM : 10
6103 23:54:58.868941 SRAM_EN : 1
6104 23:54:58.871905 MD32_EN : 0
6105 23:54:58.875622 ===================================
6106 23:54:58.878546 [ANA_INIT] >>>>>>>>>>>>>>
6107 23:54:58.881628 <<<<<< [CONFIGURE PHASE]: ANA_TX
6108 23:54:58.885152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6109 23:54:58.888744 ===================================
6110 23:54:58.889264 data_rate = 800,PCW = 0X7400
6111 23:54:58.892333 ===================================
6112 23:54:58.895248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6113 23:54:58.901882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6114 23:54:58.915785 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 23:54:58.919208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6116 23:54:58.921678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6117 23:54:58.925033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6118 23:54:58.928532 [ANA_INIT] flow start
6119 23:54:58.929055 [ANA_INIT] PLL >>>>>>>>
6120 23:54:58.931963 [ANA_INIT] PLL <<<<<<<<
6121 23:54:58.934891 [ANA_INIT] MIDPI >>>>>>>>
6122 23:54:58.935330 [ANA_INIT] MIDPI <<<<<<<<
6123 23:54:58.938324 [ANA_INIT] DLL >>>>>>>>
6124 23:54:58.942202 [ANA_INIT] flow end
6125 23:54:58.945420 ============ LP4 DIFF to SE enter ============
6126 23:54:58.948358 ============ LP4 DIFF to SE exit ============
6127 23:54:58.951793 [ANA_INIT] <<<<<<<<<<<<<
6128 23:54:58.955196 [Flow] Enable top DCM control >>>>>
6129 23:54:58.958283 [Flow] Enable top DCM control <<<<<
6130 23:54:58.961896 Enable DLL master slave shuffle
6131 23:54:58.965350 ==============================================================
6132 23:54:58.968649 Gating Mode config
6133 23:54:58.975135 ==============================================================
6134 23:54:58.975549 Config description:
6135 23:54:58.985564 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6136 23:54:58.992115 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6137 23:54:58.995043 SELPH_MODE 0: By rank 1: By Phase
6138 23:54:59.001709 ==============================================================
6139 23:54:59.005357 GAT_TRACK_EN = 0
6140 23:54:59.008184 RX_GATING_MODE = 2
6141 23:54:59.012188 RX_GATING_TRACK_MODE = 2
6142 23:54:59.015648 SELPH_MODE = 1
6143 23:54:59.018603 PICG_EARLY_EN = 1
6144 23:54:59.019039 VALID_LAT_VALUE = 1
6145 23:54:59.025115 ==============================================================
6146 23:54:59.028659 Enter into Gating configuration >>>>
6147 23:54:59.031930 Exit from Gating configuration <<<<
6148 23:54:59.035201 Enter into DVFS_PRE_config >>>>>
6149 23:54:59.044911 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6150 23:54:59.048390 Exit from DVFS_PRE_config <<<<<
6151 23:54:59.051956 Enter into PICG configuration >>>>
6152 23:54:59.055245 Exit from PICG configuration <<<<
6153 23:54:59.058818 [RX_INPUT] configuration >>>>>
6154 23:54:59.061950 [RX_INPUT] configuration <<<<<
6155 23:54:59.065103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6156 23:54:59.071802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6157 23:54:59.078594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6158 23:54:59.085101 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6159 23:54:59.092173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6160 23:54:59.098135 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6161 23:54:59.101470 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6162 23:54:59.104854 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6163 23:54:59.108369 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6164 23:54:59.111536 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6165 23:54:59.118423 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6166 23:54:59.121454 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 23:54:59.125459 ===================================
6168 23:54:59.128547 LPDDR4 DRAM CONFIGURATION
6169 23:54:59.131590 ===================================
6170 23:54:59.132079 EX_ROW_EN[0] = 0x0
6171 23:54:59.135021 EX_ROW_EN[1] = 0x0
6172 23:54:59.135515 LP4Y_EN = 0x0
6173 23:54:59.138291 WORK_FSP = 0x0
6174 23:54:59.138738 WL = 0x2
6175 23:54:59.141419 RL = 0x2
6176 23:54:59.141840 BL = 0x2
6177 23:54:59.145242 RPST = 0x0
6178 23:54:59.145672 RD_PRE = 0x0
6179 23:54:59.148131 WR_PRE = 0x1
6180 23:54:59.151791 WR_PST = 0x0
6181 23:54:59.152237 DBI_WR = 0x0
6182 23:54:59.154741 DBI_RD = 0x0
6183 23:54:59.155155 OTF = 0x1
6184 23:54:59.158409 ===================================
6185 23:54:59.161872 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6186 23:54:59.164959 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6187 23:54:59.171780 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6188 23:54:59.175249 ===================================
6189 23:54:59.178325 LPDDR4 DRAM CONFIGURATION
6190 23:54:59.181780 ===================================
6191 23:54:59.182195 EX_ROW_EN[0] = 0x10
6192 23:54:59.185110 EX_ROW_EN[1] = 0x0
6193 23:54:59.185521 LP4Y_EN = 0x0
6194 23:54:59.188554 WORK_FSP = 0x0
6195 23:54:59.188961 WL = 0x2
6196 23:54:59.191678 RL = 0x2
6197 23:54:59.192084 BL = 0x2
6198 23:54:59.194951 RPST = 0x0
6199 23:54:59.195537 RD_PRE = 0x0
6200 23:54:59.198626 WR_PRE = 0x1
6201 23:54:59.199040 WR_PST = 0x0
6202 23:54:59.202026 DBI_WR = 0x0
6203 23:54:59.202516 DBI_RD = 0x0
6204 23:54:59.205290 OTF = 0x1
6205 23:54:59.208426 ===================================
6206 23:54:59.215220 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6207 23:54:59.218100 nWR fixed to 30
6208 23:54:59.221991 [ModeRegInit_LP4] CH0 RK0
6209 23:54:59.222398 [ModeRegInit_LP4] CH0 RK1
6210 23:54:59.224816 [ModeRegInit_LP4] CH1 RK0
6211 23:54:59.228699 [ModeRegInit_LP4] CH1 RK1
6212 23:54:59.229245 match AC timing 19
6213 23:54:59.235041 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6214 23:54:59.238181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6215 23:54:59.242578 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6216 23:54:59.248215 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6217 23:54:59.251915 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6218 23:54:59.252460 ==
6219 23:54:59.255322 Dram Type= 6, Freq= 0, CH_0, rank 0
6220 23:54:59.258314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6221 23:54:59.258742 ==
6222 23:54:59.265052 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6223 23:54:59.271875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6224 23:54:59.274928 [CA 0] Center 36 (8~64) winsize 57
6225 23:54:59.275437 [CA 1] Center 36 (8~64) winsize 57
6226 23:54:59.278383 [CA 2] Center 36 (8~64) winsize 57
6227 23:54:59.281667 [CA 3] Center 36 (8~64) winsize 57
6228 23:54:59.285021 [CA 4] Center 36 (8~64) winsize 57
6229 23:54:59.288313 [CA 5] Center 36 (8~64) winsize 57
6230 23:54:59.288724
6231 23:54:59.291606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6232 23:54:59.292018
6233 23:54:59.295251 [CATrainingPosCal] consider 1 rank data
6234 23:54:59.298192 u2DelayCellTimex100 = 270/100 ps
6235 23:54:59.301417 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 23:54:59.308442 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 23:54:59.311565 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 23:54:59.315093 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:54:59.318434 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:54:59.321747 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:54:59.322160
6242 23:54:59.325218 CA PerBit enable=1, Macro0, CA PI delay=36
6243 23:54:59.325652
6244 23:54:59.328521 [CBTSetCACLKResult] CA Dly = 36
6245 23:54:59.328939 CS Dly: 1 (0~32)
6246 23:54:59.329305 ==
6247 23:54:59.331663 Dram Type= 6, Freq= 0, CH_0, rank 1
6248 23:54:59.338519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 23:54:59.338946 ==
6250 23:54:59.341675 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6251 23:54:59.349056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6252 23:54:59.351736 [CA 0] Center 36 (8~64) winsize 57
6253 23:54:59.355072 [CA 1] Center 36 (8~64) winsize 57
6254 23:54:59.358122 [CA 2] Center 36 (8~64) winsize 57
6255 23:54:59.361955 [CA 3] Center 36 (8~64) winsize 57
6256 23:54:59.365245 [CA 4] Center 36 (8~64) winsize 57
6257 23:54:59.368360 [CA 5] Center 36 (8~64) winsize 57
6258 23:54:59.368774
6259 23:54:59.371989 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6260 23:54:59.372424
6261 23:54:59.374875 [CATrainingPosCal] consider 2 rank data
6262 23:54:59.378410 u2DelayCellTimex100 = 270/100 ps
6263 23:54:59.381859 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 23:54:59.385233 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 23:54:59.388104 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 23:54:59.391386 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:54:59.395215 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:54:59.401293 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:54:59.401724
6270 23:54:59.404630 CA PerBit enable=1, Macro0, CA PI delay=36
6271 23:54:59.405212
6272 23:54:59.408167 [CBTSetCACLKResult] CA Dly = 36
6273 23:54:59.408581 CS Dly: 1 (0~32)
6274 23:54:59.408910
6275 23:54:59.411839 ----->DramcWriteLeveling(PI) begin...
6276 23:54:59.412256 ==
6277 23:54:59.415315 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 23:54:59.418415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 23:54:59.422129 ==
6280 23:54:59.422539 Write leveling (Byte 0): 40 => 8
6281 23:54:59.424895 Write leveling (Byte 1): 32 => 0
6282 23:54:59.428696 DramcWriteLeveling(PI) end<-----
6283 23:54:59.429182
6284 23:54:59.429529 ==
6285 23:54:59.431293 Dram Type= 6, Freq= 0, CH_0, rank 0
6286 23:54:59.435145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6287 23:54:59.438367 ==
6288 23:54:59.438781 [Gating] SW mode calibration
6289 23:54:59.448518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6290 23:54:59.451984 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6291 23:54:59.454951 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6292 23:54:59.461657 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 23:54:59.464915 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 23:54:59.468395 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 23:54:59.475032 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 23:54:59.478701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 23:54:59.481496 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 23:54:59.488386 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 23:54:59.491374 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 23:54:59.494861 Total UI for P1: 0, mck2ui 16
6301 23:54:59.498250 best dqsien dly found for B0: ( 0, 14, 24)
6302 23:54:59.501737 Total UI for P1: 0, mck2ui 16
6303 23:54:59.504886 best dqsien dly found for B1: ( 0, 14, 24)
6304 23:54:59.508420 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6305 23:54:59.511583 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6306 23:54:59.511974
6307 23:54:59.515266 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6308 23:54:59.518496 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 23:54:59.521863 [Gating] SW calibration Done
6310 23:54:59.522275 ==
6311 23:54:59.525644 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 23:54:59.528780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 23:54:59.529098 ==
6314 23:54:59.531386 RX Vref Scan: 0
6315 23:54:59.531758
6316 23:54:59.535164 RX Vref 0 -> 0, step: 1
6317 23:54:59.535544
6318 23:54:59.535880 RX Delay -410 -> 252, step: 16
6319 23:54:59.541859 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6320 23:54:59.545405 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6321 23:54:59.548204 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6322 23:54:59.551876 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6323 23:54:59.558666 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6324 23:54:59.562000 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6325 23:54:59.565494 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6326 23:54:59.568209 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6327 23:54:59.575056 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6328 23:54:59.578472 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6329 23:54:59.581672 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6330 23:54:59.584941 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6331 23:54:59.591561 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6332 23:54:59.594960 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6333 23:54:59.598692 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6334 23:54:59.605016 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6335 23:54:59.605310 ==
6336 23:54:59.608154 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 23:54:59.611596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 23:54:59.611889 ==
6339 23:54:59.612150 DQS Delay:
6340 23:54:59.614869 DQS0 = 35, DQS1 = 51
6341 23:54:59.615160 DQM Delay:
6342 23:54:59.618661 DQM0 = 6, DQM1 = 10
6343 23:54:59.618947 DQ Delay:
6344 23:54:59.621733 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6345 23:54:59.624885 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6346 23:54:59.628008 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6347 23:54:59.631646 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6348 23:54:59.631936
6349 23:54:59.632168
6350 23:54:59.632414 ==
6351 23:54:59.635458 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 23:54:59.638998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 23:54:59.639290 ==
6354 23:54:59.639524
6355 23:54:59.639770
6356 23:54:59.641623 TX Vref Scan disable
6357 23:54:59.641918 == TX Byte 0 ==
6358 23:54:59.648157 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 23:54:59.651579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 23:54:59.651900 == TX Byte 1 ==
6361 23:54:59.658510 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6362 23:54:59.661701 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6363 23:54:59.662025 ==
6364 23:54:59.665032 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 23:54:59.668466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 23:54:59.668761 ==
6367 23:54:59.669017
6368 23:54:59.669244
6369 23:54:59.671854 TX Vref Scan disable
6370 23:54:59.672144 == TX Byte 0 ==
6371 23:54:59.678096 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 23:54:59.681951 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 23:54:59.682348 == TX Byte 1 ==
6374 23:54:59.689187 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6375 23:54:59.692105 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6376 23:54:59.692460
6377 23:54:59.692856 [DATLAT]
6378 23:54:59.695006 Freq=400, CH0 RK0
6379 23:54:59.695321
6380 23:54:59.695606 DATLAT Default: 0xf
6381 23:54:59.698405 0, 0xFFFF, sum = 0
6382 23:54:59.698819 1, 0xFFFF, sum = 0
6383 23:54:59.701552 2, 0xFFFF, sum = 0
6384 23:54:59.702021 3, 0xFFFF, sum = 0
6385 23:54:59.705018 4, 0xFFFF, sum = 0
6386 23:54:59.705468 5, 0xFFFF, sum = 0
6387 23:54:59.708589 6, 0xFFFF, sum = 0
6388 23:54:59.708909 7, 0xFFFF, sum = 0
6389 23:54:59.711978 8, 0xFFFF, sum = 0
6390 23:54:59.712287 9, 0xFFFF, sum = 0
6391 23:54:59.715121 10, 0xFFFF, sum = 0
6392 23:54:59.715432 11, 0xFFFF, sum = 0
6393 23:54:59.718513 12, 0xFFFF, sum = 0
6394 23:54:59.718821 13, 0x0, sum = 1
6395 23:54:59.722080 14, 0x0, sum = 2
6396 23:54:59.722389 15, 0x0, sum = 3
6397 23:54:59.725397 16, 0x0, sum = 4
6398 23:54:59.725707 best_step = 14
6399 23:54:59.726013
6400 23:54:59.726303 ==
6401 23:54:59.728632 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 23:54:59.735485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 23:54:59.735792 ==
6404 23:54:59.736101 RX Vref Scan: 1
6405 23:54:59.736397
6406 23:54:59.738672 RX Vref 0 -> 0, step: 1
6407 23:54:59.738974
6408 23:54:59.742044 RX Delay -343 -> 252, step: 8
6409 23:54:59.742345
6410 23:54:59.744967 Set Vref, RX VrefLevel [Byte0]: 53
6411 23:54:59.748182 [Byte1]: 53
6412 23:54:59.748498
6413 23:54:59.751638 Final RX Vref Byte 0 = 53 to rank0
6414 23:54:59.755298 Final RX Vref Byte 1 = 53 to rank0
6415 23:54:59.758648 Final RX Vref Byte 0 = 53 to rank1
6416 23:54:59.761858 Final RX Vref Byte 1 = 53 to rank1==
6417 23:54:59.766118 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 23:54:59.768386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 23:54:59.773035 ==
6420 23:54:59.773382 DQS Delay:
6421 23:54:59.773619 DQS0 = 44, DQS1 = 60
6422 23:54:59.774907 DQM Delay:
6423 23:54:59.775210 DQM0 = 11, DQM1 = 14
6424 23:54:59.778839 DQ Delay:
6425 23:54:59.781663 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6426 23:54:59.781956 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6427 23:54:59.785175 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6428 23:54:59.788293 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6429 23:54:59.788589
6430 23:54:59.788825
6431 23:54:59.798357 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f4d, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
6432 23:54:59.801696 CH0 RK0: MR19=C0C, MR18=7F4D
6433 23:54:59.808318 CH0_RK0: MR19=0xC0C, MR18=0x7F4D, DQSOSC=393, MR23=63, INC=382, DEC=254
6434 23:54:59.808612 ==
6435 23:54:59.811396 Dram Type= 6, Freq= 0, CH_0, rank 1
6436 23:54:59.814971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 23:54:59.815347 ==
6438 23:54:59.818222 [Gating] SW mode calibration
6439 23:54:59.825081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6440 23:54:59.831850 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6441 23:54:59.835029 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 23:54:59.838600 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 23:54:59.842237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 23:54:59.848373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 23:54:59.851415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 23:54:59.855173 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 23:54:59.861271 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 23:54:59.865210 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 23:54:59.868355 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 23:54:59.871598 Total UI for P1: 0, mck2ui 16
6451 23:54:59.875610 best dqsien dly found for B0: ( 0, 14, 24)
6452 23:54:59.878125 Total UI for P1: 0, mck2ui 16
6453 23:54:59.882388 best dqsien dly found for B1: ( 0, 14, 24)
6454 23:54:59.885318 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6455 23:54:59.888998 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6456 23:54:59.889393
6457 23:54:59.894842 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6458 23:54:59.898769 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 23:54:59.899225 [Gating] SW calibration Done
6460 23:54:59.901620 ==
6461 23:54:59.905208 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 23:54:59.908421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 23:54:59.908715 ==
6464 23:54:59.908948 RX Vref Scan: 0
6465 23:54:59.909207
6466 23:54:59.911843 RX Vref 0 -> 0, step: 1
6467 23:54:59.912169
6468 23:54:59.915042 RX Delay -410 -> 252, step: 16
6469 23:54:59.918404 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6470 23:54:59.921380 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6471 23:54:59.928080 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6472 23:54:59.931944 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6473 23:54:59.935066 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6474 23:54:59.938682 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6475 23:54:59.944919 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6476 23:54:59.948497 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6477 23:54:59.951744 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6478 23:54:59.955238 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6479 23:54:59.961887 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6480 23:54:59.965384 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6481 23:54:59.968506 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6482 23:54:59.971657 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6483 23:54:59.978473 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6484 23:54:59.982172 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6485 23:54:59.982665 ==
6486 23:54:59.985427 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 23:54:59.988457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 23:54:59.989005 ==
6489 23:54:59.991909 DQS Delay:
6490 23:54:59.992396 DQS0 = 43, DQS1 = 51
6491 23:54:59.995971 DQM Delay:
6492 23:54:59.996541 DQM0 = 11, DQM1 = 10
6493 23:54:59.996910 DQ Delay:
6494 23:54:59.998964 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6495 23:55:00.001853 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6496 23:55:00.005305 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6497 23:55:00.009195 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6498 23:55:00.009653
6499 23:55:00.010018
6500 23:55:00.010353 ==
6501 23:55:00.011974 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 23:55:00.015319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 23:55:00.018788 ==
6504 23:55:00.019304
6505 23:55:00.019636
6506 23:55:00.019947 TX Vref Scan disable
6507 23:55:00.021941 == TX Byte 0 ==
6508 23:55:00.025115 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6509 23:55:00.028853 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6510 23:55:00.031811 == TX Byte 1 ==
6511 23:55:00.035976 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6512 23:55:00.038444 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6513 23:55:00.038857 ==
6514 23:55:00.042127 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 23:55:00.045345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 23:55:00.048684 ==
6517 23:55:00.049198
6518 23:55:00.049567
6519 23:55:00.049901 TX Vref Scan disable
6520 23:55:00.052096 == TX Byte 0 ==
6521 23:55:00.055469 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6522 23:55:00.058942 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6523 23:55:00.061953 == TX Byte 1 ==
6524 23:55:00.065088 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6525 23:55:00.068852 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6526 23:55:00.069315
6527 23:55:00.069641 [DATLAT]
6528 23:55:00.071914 Freq=400, CH0 RK1
6529 23:55:00.072324
6530 23:55:00.075318 DATLAT Default: 0xe
6531 23:55:00.075794 0, 0xFFFF, sum = 0
6532 23:55:00.078597 1, 0xFFFF, sum = 0
6533 23:55:00.079011 2, 0xFFFF, sum = 0
6534 23:55:00.082106 3, 0xFFFF, sum = 0
6535 23:55:00.082522 4, 0xFFFF, sum = 0
6536 23:55:00.085226 5, 0xFFFF, sum = 0
6537 23:55:00.085739 6, 0xFFFF, sum = 0
6538 23:55:00.088609 7, 0xFFFF, sum = 0
6539 23:55:00.089061 8, 0xFFFF, sum = 0
6540 23:55:00.092123 9, 0xFFFF, sum = 0
6541 23:55:00.092541 10, 0xFFFF, sum = 0
6542 23:55:00.095467 11, 0xFFFF, sum = 0
6543 23:55:00.095996 12, 0xFFFF, sum = 0
6544 23:55:00.098627 13, 0x0, sum = 1
6545 23:55:00.099046 14, 0x0, sum = 2
6546 23:55:00.101792 15, 0x0, sum = 3
6547 23:55:00.102247 16, 0x0, sum = 4
6548 23:55:00.105567 best_step = 14
6549 23:55:00.105976
6550 23:55:00.106299 ==
6551 23:55:00.108533 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 23:55:00.111709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 23:55:00.112125 ==
6554 23:55:00.115234 RX Vref Scan: 0
6555 23:55:00.115648
6556 23:55:00.115975 RX Vref 0 -> 0, step: 1
6557 23:55:00.116282
6558 23:55:00.118585 RX Delay -343 -> 252, step: 8
6559 23:55:00.125958 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6560 23:55:00.129692 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6561 23:55:00.132629 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6562 23:55:00.136296 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6563 23:55:00.142533 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6564 23:55:00.146186 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6565 23:55:00.149644 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6566 23:55:00.152636 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6567 23:55:00.159270 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6568 23:55:00.162985 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6569 23:55:00.165699 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6570 23:55:00.169006 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6571 23:55:00.176244 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6572 23:55:00.179472 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6573 23:55:00.183069 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6574 23:55:00.189158 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6575 23:55:00.189747 ==
6576 23:55:00.192470 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 23:55:00.196032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 23:55:00.196527 ==
6579 23:55:00.197009 DQS Delay:
6580 23:55:00.199628 DQS0 = 48, DQS1 = 60
6581 23:55:00.200036 DQM Delay:
6582 23:55:00.202770 DQM0 = 11, DQM1 = 13
6583 23:55:00.203177 DQ Delay:
6584 23:55:00.206072 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6585 23:55:00.209452 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6586 23:55:00.213555 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6587 23:55:00.216348 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6588 23:55:00.216761
6589 23:55:00.217139
6590 23:55:00.223215 [DQSOSCAuto] RK1, (LSB)MR18= 0x956a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6591 23:55:00.226274 CH0 RK1: MR19=C0C, MR18=956A
6592 23:55:00.232968 CH0_RK1: MR19=0xC0C, MR18=0x956A, DQSOSC=391, MR23=63, INC=386, DEC=257
6593 23:55:00.236034 [RxdqsGatingPostProcess] freq 400
6594 23:55:00.239175 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6595 23:55:00.243119 best DQS0 dly(2T, 0.5T) = (0, 10)
6596 23:55:00.245734 best DQS1 dly(2T, 0.5T) = (0, 10)
6597 23:55:00.249216 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6598 23:55:00.252598 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6599 23:55:00.255674 best DQS0 dly(2T, 0.5T) = (0, 10)
6600 23:55:00.259147 best DQS1 dly(2T, 0.5T) = (0, 10)
6601 23:55:00.262721 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6602 23:55:00.266575 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6603 23:55:00.269435 Pre-setting of DQS Precalculation
6604 23:55:00.272779 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6605 23:55:00.273325 ==
6606 23:55:00.276292 Dram Type= 6, Freq= 0, CH_1, rank 0
6607 23:55:00.283178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 23:55:00.283697 ==
6609 23:55:00.286440 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6610 23:55:00.293133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6611 23:55:00.296163 [CA 0] Center 36 (8~64) winsize 57
6612 23:55:00.299973 [CA 1] Center 36 (8~64) winsize 57
6613 23:55:00.303327 [CA 2] Center 36 (8~64) winsize 57
6614 23:55:00.306343 [CA 3] Center 36 (8~64) winsize 57
6615 23:55:00.309727 [CA 4] Center 36 (8~64) winsize 57
6616 23:55:00.312887 [CA 5] Center 36 (8~64) winsize 57
6617 23:55:00.313430
6618 23:55:00.316155 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6619 23:55:00.316565
6620 23:55:00.320105 [CATrainingPosCal] consider 1 rank data
6621 23:55:00.322676 u2DelayCellTimex100 = 270/100 ps
6622 23:55:00.326389 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 23:55:00.329980 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 23:55:00.332799 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 23:55:00.336097 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:55:00.339865 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:55:00.342751 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:55:00.345875
6629 23:55:00.349209 CA PerBit enable=1, Macro0, CA PI delay=36
6630 23:55:00.349673
6631 23:55:00.352611 [CBTSetCACLKResult] CA Dly = 36
6632 23:55:00.353209 CS Dly: 1 (0~32)
6633 23:55:00.353691 ==
6634 23:55:00.355928 Dram Type= 6, Freq= 0, CH_1, rank 1
6635 23:55:00.359489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 23:55:00.359955 ==
6637 23:55:00.366218 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6638 23:55:00.372552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6639 23:55:00.376122 [CA 0] Center 36 (8~64) winsize 57
6640 23:55:00.379737 [CA 1] Center 36 (8~64) winsize 57
6641 23:55:00.382988 [CA 2] Center 36 (8~64) winsize 57
6642 23:55:00.386061 [CA 3] Center 36 (8~64) winsize 57
6643 23:55:00.386619 [CA 4] Center 36 (8~64) winsize 57
6644 23:55:00.389988 [CA 5] Center 36 (8~64) winsize 57
6645 23:55:00.390444
6646 23:55:00.396243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6647 23:55:00.396803
6648 23:55:00.399772 [CATrainingPosCal] consider 2 rank data
6649 23:55:00.403006 u2DelayCellTimex100 = 270/100 ps
6650 23:55:00.406265 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 23:55:00.409461 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 23:55:00.413279 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 23:55:00.416100 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:55:00.419870 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:55:00.423495 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:55:00.424057
6657 23:55:00.426339 CA PerBit enable=1, Macro0, CA PI delay=36
6658 23:55:00.426801
6659 23:55:00.429577 [CBTSetCACLKResult] CA Dly = 36
6660 23:55:00.433104 CS Dly: 1 (0~32)
6661 23:55:00.433674
6662 23:55:00.436518 ----->DramcWriteLeveling(PI) begin...
6663 23:55:00.437125 ==
6664 23:55:00.440405 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 23:55:00.442934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 23:55:00.443398 ==
6667 23:55:00.446513 Write leveling (Byte 0): 40 => 8
6668 23:55:00.449701 Write leveling (Byte 1): 40 => 8
6669 23:55:00.452731 DramcWriteLeveling(PI) end<-----
6670 23:55:00.453366
6671 23:55:00.453744 ==
6672 23:55:00.456349 Dram Type= 6, Freq= 0, CH_1, rank 0
6673 23:55:00.459241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6674 23:55:00.459700 ==
6675 23:55:00.463151 [Gating] SW mode calibration
6676 23:55:00.469571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6677 23:55:00.476138 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6678 23:55:00.479468 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6679 23:55:00.482809 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 23:55:00.489659 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 23:55:00.492801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 23:55:00.496088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 23:55:00.503032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 23:55:00.506437 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 23:55:00.509650 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 23:55:00.516585 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 23:55:00.517180 Total UI for P1: 0, mck2ui 16
6688 23:55:00.519485 best dqsien dly found for B0: ( 0, 14, 24)
6689 23:55:00.523075 Total UI for P1: 0, mck2ui 16
6690 23:55:00.526458 best dqsien dly found for B1: ( 0, 14, 24)
6691 23:55:00.529930 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6692 23:55:00.536234 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6693 23:55:00.536802
6694 23:55:00.540347 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6695 23:55:00.543550 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 23:55:00.546129 [Gating] SW calibration Done
6697 23:55:00.546593 ==
6698 23:55:00.549873 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 23:55:00.553344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 23:55:00.553943 ==
6701 23:55:00.554326 RX Vref Scan: 0
6702 23:55:00.554821
6703 23:55:00.556156 RX Vref 0 -> 0, step: 1
6704 23:55:00.556788
6705 23:55:00.559440 RX Delay -410 -> 252, step: 16
6706 23:55:00.563293 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6707 23:55:00.569618 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6708 23:55:00.573078 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6709 23:55:00.576499 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6710 23:55:00.579773 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6711 23:55:00.586148 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6712 23:55:00.589480 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6713 23:55:00.592625 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6714 23:55:00.596719 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6715 23:55:00.602763 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6716 23:55:00.606750 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6717 23:55:00.609869 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6718 23:55:00.613593 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6719 23:55:00.619508 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6720 23:55:00.623264 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6721 23:55:00.626169 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6722 23:55:00.626620 ==
6723 23:55:00.629400 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 23:55:00.632680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 23:55:00.636333 ==
6726 23:55:00.636848 DQS Delay:
6727 23:55:00.637233 DQS0 = 51, DQS1 = 59
6728 23:55:00.639627 DQM Delay:
6729 23:55:00.640042 DQM0 = 19, DQM1 = 16
6730 23:55:00.642968 DQ Delay:
6731 23:55:00.646086 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6732 23:55:00.646550 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6733 23:55:00.650341 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6734 23:55:00.653504 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6735 23:55:00.653969
6736 23:55:00.654337
6737 23:55:00.656311 ==
6738 23:55:00.659722 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 23:55:00.662934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 23:55:00.663399 ==
6741 23:55:00.663765
6742 23:55:00.664105
6743 23:55:00.666334 TX Vref Scan disable
6744 23:55:00.666796 == TX Byte 0 ==
6745 23:55:00.669578 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 23:55:00.676163 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 23:55:00.676692 == TX Byte 1 ==
6748 23:55:00.679347 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 23:55:00.686246 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 23:55:00.686835 ==
6751 23:55:00.689457 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 23:55:00.692737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 23:55:00.693238 ==
6754 23:55:00.693606
6755 23:55:00.694033
6756 23:55:00.696431 TX Vref Scan disable
6757 23:55:00.696889 == TX Byte 0 ==
6758 23:55:00.699747 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 23:55:00.705963 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 23:55:00.706431 == TX Byte 1 ==
6761 23:55:00.709519 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 23:55:00.716443 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 23:55:00.717042
6764 23:55:00.717421 [DATLAT]
6765 23:55:00.717769 Freq=400, CH1 RK0
6766 23:55:00.718111
6767 23:55:00.719504 DATLAT Default: 0xf
6768 23:55:00.719962 0, 0xFFFF, sum = 0
6769 23:55:00.722716 1, 0xFFFF, sum = 0
6770 23:55:00.726281 2, 0xFFFF, sum = 0
6771 23:55:00.726882 3, 0xFFFF, sum = 0
6772 23:55:00.729449 4, 0xFFFF, sum = 0
6773 23:55:00.729918 5, 0xFFFF, sum = 0
6774 23:55:00.732549 6, 0xFFFF, sum = 0
6775 23:55:00.733045 7, 0xFFFF, sum = 0
6776 23:55:00.736252 8, 0xFFFF, sum = 0
6777 23:55:00.736720 9, 0xFFFF, sum = 0
6778 23:55:00.739471 10, 0xFFFF, sum = 0
6779 23:55:00.739897 11, 0xFFFF, sum = 0
6780 23:55:00.742823 12, 0xFFFF, sum = 0
6781 23:55:00.743247 13, 0x0, sum = 1
6782 23:55:00.746368 14, 0x0, sum = 2
6783 23:55:00.746794 15, 0x0, sum = 3
6784 23:55:00.749691 16, 0x0, sum = 4
6785 23:55:00.750217 best_step = 14
6786 23:55:00.750551
6787 23:55:00.750864 ==
6788 23:55:00.752789 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 23:55:00.755732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 23:55:00.759664 ==
6791 23:55:00.760195 RX Vref Scan: 1
6792 23:55:00.760540
6793 23:55:00.763230 RX Vref 0 -> 0, step: 1
6794 23:55:00.763649
6795 23:55:00.763982 RX Delay -359 -> 252, step: 8
6796 23:55:00.765789
6797 23:55:00.766207 Set Vref, RX VrefLevel [Byte0]: 57
6798 23:55:00.769108 [Byte1]: 52
6799 23:55:00.775056
6800 23:55:00.775578 Final RX Vref Byte 0 = 57 to rank0
6801 23:55:00.778185 Final RX Vref Byte 1 = 52 to rank0
6802 23:55:00.782209 Final RX Vref Byte 0 = 57 to rank1
6803 23:55:00.785658 Final RX Vref Byte 1 = 52 to rank1==
6804 23:55:00.789045 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 23:55:00.792133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 23:55:00.795132 ==
6807 23:55:00.795586 DQS Delay:
6808 23:55:00.795946 DQS0 = 48, DQS1 = 60
6809 23:55:00.799244 DQM Delay:
6810 23:55:00.799800 DQM0 = 12, DQM1 = 13
6811 23:55:00.801620 DQ Delay:
6812 23:55:00.805321 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6813 23:55:00.805777 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6814 23:55:00.808678 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6815 23:55:00.811519 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6816 23:55:00.811974
6817 23:55:00.812330
6818 23:55:00.821947 [DQSOSCAuto] RK0, (LSB)MR18= 0x862e, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6819 23:55:00.824910 CH1 RK0: MR19=C0C, MR18=862E
6820 23:55:00.831771 CH1_RK0: MR19=0xC0C, MR18=0x862E, DQSOSC=393, MR23=63, INC=382, DEC=254
6821 23:55:00.832247 ==
6822 23:55:00.835081 Dram Type= 6, Freq= 0, CH_1, rank 1
6823 23:55:00.838346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 23:55:00.838815 ==
6825 23:55:00.841573 [Gating] SW mode calibration
6826 23:55:00.848372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6827 23:55:00.852464 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6828 23:55:00.858113 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6829 23:55:00.861789 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 23:55:00.865058 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 23:55:00.872829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 23:55:00.875624 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 23:55:00.878680 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 23:55:00.885458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 23:55:00.888724 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 23:55:00.891865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 23:55:00.895180 Total UI for P1: 0, mck2ui 16
6838 23:55:00.898379 best dqsien dly found for B0: ( 0, 14, 24)
6839 23:55:00.902264 Total UI for P1: 0, mck2ui 16
6840 23:55:00.905165 best dqsien dly found for B1: ( 0, 14, 24)
6841 23:55:00.908426 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6842 23:55:00.911802 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6843 23:55:00.912309
6844 23:55:00.918306 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6845 23:55:00.921641 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 23:55:00.922103 [Gating] SW calibration Done
6847 23:55:00.924897 ==
6848 23:55:00.928616 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 23:55:00.931897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 23:55:00.932358 ==
6851 23:55:00.932722 RX Vref Scan: 0
6852 23:55:00.933118
6853 23:55:00.934844 RX Vref 0 -> 0, step: 1
6854 23:55:00.935258
6855 23:55:00.938554 RX Delay -410 -> 252, step: 16
6856 23:55:00.941747 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6857 23:55:00.945390 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6858 23:55:00.951438 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6859 23:55:00.954746 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6860 23:55:00.958171 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6861 23:55:00.961680 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6862 23:55:00.968452 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6863 23:55:00.971978 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6864 23:55:00.975267 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6865 23:55:00.978612 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6866 23:55:00.986598 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6867 23:55:00.989019 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6868 23:55:00.992160 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6869 23:55:00.994905 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6870 23:55:01.002149 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6871 23:55:01.005154 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6872 23:55:01.005610 ==
6873 23:55:01.008825 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 23:55:01.012054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 23:55:01.012582 ==
6876 23:55:01.015139 DQS Delay:
6877 23:55:01.015671 DQS0 = 43, DQS1 = 59
6878 23:55:01.018608 DQM Delay:
6879 23:55:01.019157 DQM0 = 10, DQM1 = 18
6880 23:55:01.019518 DQ Delay:
6881 23:55:01.021664 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6882 23:55:01.025233 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6883 23:55:01.028872 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6884 23:55:01.032067 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6885 23:55:01.032619
6886 23:55:01.033034
6887 23:55:01.033391 ==
6888 23:55:01.035124 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 23:55:01.038351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 23:55:01.041721 ==
6891 23:55:01.042188
6892 23:55:01.042545
6893 23:55:01.042880 TX Vref Scan disable
6894 23:55:01.045095 == TX Byte 0 ==
6895 23:55:01.048472 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6896 23:55:01.051603 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6897 23:55:01.054806 == TX Byte 1 ==
6898 23:55:01.058589 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6899 23:55:01.061647 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6900 23:55:01.062110 ==
6901 23:55:01.065485 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 23:55:01.071511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 23:55:01.072065 ==
6904 23:55:01.072434
6905 23:55:01.072775
6906 23:55:01.073209 TX Vref Scan disable
6907 23:55:01.075526 == TX Byte 0 ==
6908 23:55:01.078503 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6909 23:55:01.081340 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6910 23:55:01.085465 == TX Byte 1 ==
6911 23:55:01.088680 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6912 23:55:01.092055 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6913 23:55:01.092641
6914 23:55:01.094950 [DATLAT]
6915 23:55:01.095533 Freq=400, CH1 RK1
6916 23:55:01.095907
6917 23:55:01.098539 DATLAT Default: 0xe
6918 23:55:01.099151 0, 0xFFFF, sum = 0
6919 23:55:01.102116 1, 0xFFFF, sum = 0
6920 23:55:01.102712 2, 0xFFFF, sum = 0
6921 23:55:01.105121 3, 0xFFFF, sum = 0
6922 23:55:01.105642 4, 0xFFFF, sum = 0
6923 23:55:01.108484 5, 0xFFFF, sum = 0
6924 23:55:01.109039 6, 0xFFFF, sum = 0
6925 23:55:01.111660 7, 0xFFFF, sum = 0
6926 23:55:01.112124 8, 0xFFFF, sum = 0
6927 23:55:01.115161 9, 0xFFFF, sum = 0
6928 23:55:01.115619 10, 0xFFFF, sum = 0
6929 23:55:01.118641 11, 0xFFFF, sum = 0
6930 23:55:01.119170 12, 0xFFFF, sum = 0
6931 23:55:01.121723 13, 0x0, sum = 1
6932 23:55:01.122184 14, 0x0, sum = 2
6933 23:55:01.125040 15, 0x0, sum = 3
6934 23:55:01.125625 16, 0x0, sum = 4
6935 23:55:01.128354 best_step = 14
6936 23:55:01.128899
6937 23:55:01.129321 ==
6938 23:55:01.132114 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 23:55:01.135846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 23:55:01.136398 ==
6941 23:55:01.138316 RX Vref Scan: 0
6942 23:55:01.138767
6943 23:55:01.139128 RX Vref 0 -> 0, step: 1
6944 23:55:01.139466
6945 23:55:01.141496 RX Delay -359 -> 252, step: 8
6946 23:55:01.149551 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6947 23:55:01.152932 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6948 23:55:01.155961 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6949 23:55:01.159405 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6950 23:55:01.166101 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6951 23:55:01.169451 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6952 23:55:01.173193 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6953 23:55:01.175855 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6954 23:55:01.182466 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6955 23:55:01.186204 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6956 23:55:01.189291 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6957 23:55:01.192743 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6958 23:55:01.199379 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6959 23:55:01.202645 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6960 23:55:01.205868 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6961 23:55:01.209231 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6962 23:55:01.213249 ==
6963 23:55:01.215897 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 23:55:01.219481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 23:55:01.219914 ==
6966 23:55:01.220255 DQS Delay:
6967 23:55:01.222436 DQS0 = 52, DQS1 = 60
6968 23:55:01.222930 DQM Delay:
6969 23:55:01.225876 DQM0 = 13, DQM1 = 12
6970 23:55:01.226293 DQ Delay:
6971 23:55:01.229068 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6972 23:55:01.232393 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6973 23:55:01.235728 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6974 23:55:01.239105 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6975 23:55:01.239558
6976 23:55:01.239908
6977 23:55:01.245400 [DQSOSCAuto] RK1, (LSB)MR18= 0x788e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
6978 23:55:01.249381 CH1 RK1: MR19=C0C, MR18=788E
6979 23:55:01.255543 CH1_RK1: MR19=0xC0C, MR18=0x788E, DQSOSC=392, MR23=63, INC=384, DEC=256
6980 23:55:01.258980 [RxdqsGatingPostProcess] freq 400
6981 23:55:01.261956 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6982 23:55:01.265670 best DQS0 dly(2T, 0.5T) = (0, 10)
6983 23:55:01.268867 best DQS1 dly(2T, 0.5T) = (0, 10)
6984 23:55:01.272429 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6985 23:55:01.275664 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6986 23:55:01.279025 best DQS0 dly(2T, 0.5T) = (0, 10)
6987 23:55:01.282581 best DQS1 dly(2T, 0.5T) = (0, 10)
6988 23:55:01.285359 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6989 23:55:01.289343 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6990 23:55:01.292343 Pre-setting of DQS Precalculation
6991 23:55:01.295550 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6992 23:55:01.305902 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6993 23:55:01.312503 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6994 23:55:01.312585
6995 23:55:01.312649
6996 23:55:01.316258 [Calibration Summary] 800 Mbps
6997 23:55:01.316340 CH 0, Rank 0
6998 23:55:01.318655 SW Impedance : PASS
6999 23:55:01.318736 DUTY Scan : NO K
7000 23:55:01.322595 ZQ Calibration : PASS
7001 23:55:01.325207 Jitter Meter : NO K
7002 23:55:01.325288 CBT Training : PASS
7003 23:55:01.328743 Write leveling : PASS
7004 23:55:01.332147 RX DQS gating : PASS
7005 23:55:01.332228 RX DQ/DQS(RDDQC) : PASS
7006 23:55:01.335501 TX DQ/DQS : PASS
7007 23:55:01.335582 RX DATLAT : PASS
7008 23:55:01.338602 RX DQ/DQS(Engine): PASS
7009 23:55:01.342347 TX OE : NO K
7010 23:55:01.342428 All Pass.
7011 23:55:01.342493
7012 23:55:01.342552 CH 0, Rank 1
7013 23:55:01.345607 SW Impedance : PASS
7014 23:55:01.348888 DUTY Scan : NO K
7015 23:55:01.348991 ZQ Calibration : PASS
7016 23:55:01.351942 Jitter Meter : NO K
7017 23:55:01.355168 CBT Training : PASS
7018 23:55:01.355241 Write leveling : NO K
7019 23:55:01.358749 RX DQS gating : PASS
7020 23:55:01.362358 RX DQ/DQS(RDDQC) : PASS
7021 23:55:01.362439 TX DQ/DQS : PASS
7022 23:55:01.365454 RX DATLAT : PASS
7023 23:55:01.368669 RX DQ/DQS(Engine): PASS
7024 23:55:01.368750 TX OE : NO K
7025 23:55:01.368815 All Pass.
7026 23:55:01.372310
7027 23:55:01.372380 CH 1, Rank 0
7028 23:55:01.375501 SW Impedance : PASS
7029 23:55:01.375582 DUTY Scan : NO K
7030 23:55:01.379350 ZQ Calibration : PASS
7031 23:55:01.379430 Jitter Meter : NO K
7032 23:55:01.382301 CBT Training : PASS
7033 23:55:01.385440 Write leveling : PASS
7034 23:55:01.385520 RX DQS gating : PASS
7035 23:55:01.389375 RX DQ/DQS(RDDQC) : PASS
7036 23:55:01.392100 TX DQ/DQS : PASS
7037 23:55:01.392182 RX DATLAT : PASS
7038 23:55:01.395382 RX DQ/DQS(Engine): PASS
7039 23:55:01.398746 TX OE : NO K
7040 23:55:01.398829 All Pass.
7041 23:55:01.398893
7042 23:55:01.398953 CH 1, Rank 1
7043 23:55:01.402182 SW Impedance : PASS
7044 23:55:01.405264 DUTY Scan : NO K
7045 23:55:01.405362 ZQ Calibration : PASS
7046 23:55:01.408596 Jitter Meter : NO K
7047 23:55:01.412436 CBT Training : PASS
7048 23:55:01.412516 Write leveling : NO K
7049 23:55:01.415294 RX DQS gating : PASS
7050 23:55:01.418860 RX DQ/DQS(RDDQC) : PASS
7051 23:55:01.418941 TX DQ/DQS : PASS
7052 23:55:01.422345 RX DATLAT : PASS
7053 23:55:01.422426 RX DQ/DQS(Engine): PASS
7054 23:55:01.425813 TX OE : NO K
7055 23:55:01.425894 All Pass.
7056 23:55:01.425959
7057 23:55:01.428556 DramC Write-DBI off
7058 23:55:01.431817 PER_BANK_REFRESH: Hybrid Mode
7059 23:55:01.431897 TX_TRACKING: ON
7060 23:55:01.441929 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7061 23:55:01.445391 [FAST_K] Save calibration result to emmc
7062 23:55:01.448762 dramc_set_vcore_voltage set vcore to 725000
7063 23:55:01.451970 Read voltage for 1600, 0
7064 23:55:01.452065 Vio18 = 0
7065 23:55:01.455452 Vcore = 725000
7066 23:55:01.455532 Vdram = 0
7067 23:55:01.455596 Vddq = 0
7068 23:55:01.455656 Vmddr = 0
7069 23:55:01.462163 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7070 23:55:01.465654 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7071 23:55:01.468950 MEM_TYPE=3, freq_sel=13
7072 23:55:01.472269 sv_algorithm_assistance_LP4_3733
7073 23:55:01.475747 ============ PULL DRAM RESETB DOWN ============
7074 23:55:01.478974 ========== PULL DRAM RESETB DOWN end =========
7075 23:55:01.485390 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7076 23:55:01.488839 ===================================
7077 23:55:01.492417 LPDDR4 DRAM CONFIGURATION
7078 23:55:01.495713 ===================================
7079 23:55:01.495794 EX_ROW_EN[0] = 0x0
7080 23:55:01.498781 EX_ROW_EN[1] = 0x0
7081 23:55:01.498862 LP4Y_EN = 0x0
7082 23:55:01.502195 WORK_FSP = 0x1
7083 23:55:01.502276 WL = 0x5
7084 23:55:01.505381 RL = 0x5
7085 23:55:01.505471 BL = 0x2
7086 23:55:01.509304 RPST = 0x0
7087 23:55:01.509384 RD_PRE = 0x0
7088 23:55:01.512075 WR_PRE = 0x1
7089 23:55:01.512155 WR_PST = 0x1
7090 23:55:01.515401 DBI_WR = 0x0
7091 23:55:01.515481 DBI_RD = 0x0
7092 23:55:01.519170 OTF = 0x1
7093 23:55:01.522045 ===================================
7094 23:55:01.525720 ===================================
7095 23:55:01.525802 ANA top config
7096 23:55:01.529020 ===================================
7097 23:55:01.532299 DLL_ASYNC_EN = 0
7098 23:55:01.535635 ALL_SLAVE_EN = 0
7099 23:55:01.538592 NEW_RANK_MODE = 1
7100 23:55:01.538674 DLL_IDLE_MODE = 1
7101 23:55:01.542405 LP45_APHY_COMB_EN = 1
7102 23:55:01.546268 TX_ODT_DIS = 0
7103 23:55:01.548675 NEW_8X_MODE = 1
7104 23:55:01.552324 ===================================
7105 23:55:01.555440 ===================================
7106 23:55:01.558888 data_rate = 3200
7107 23:55:01.558969 CKR = 1
7108 23:55:01.562173 DQ_P2S_RATIO = 8
7109 23:55:01.565771 ===================================
7110 23:55:01.568650 CA_P2S_RATIO = 8
7111 23:55:01.572077 DQ_CA_OPEN = 0
7112 23:55:01.575848 DQ_SEMI_OPEN = 0
7113 23:55:01.578577 CA_SEMI_OPEN = 0
7114 23:55:01.578658 CA_FULL_RATE = 0
7115 23:55:01.582086 DQ_CKDIV4_EN = 0
7116 23:55:01.585699 CA_CKDIV4_EN = 0
7117 23:55:01.588905 CA_PREDIV_EN = 0
7118 23:55:01.592284 PH8_DLY = 12
7119 23:55:01.595378 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7120 23:55:01.595459 DQ_AAMCK_DIV = 4
7121 23:55:01.598533 CA_AAMCK_DIV = 4
7122 23:55:01.602195 CA_ADMCK_DIV = 4
7123 23:55:01.605387 DQ_TRACK_CA_EN = 0
7124 23:55:01.608646 CA_PICK = 1600
7125 23:55:01.611973 CA_MCKIO = 1600
7126 23:55:01.615198 MCKIO_SEMI = 0
7127 23:55:01.615279 PLL_FREQ = 3068
7128 23:55:01.618969 DQ_UI_PI_RATIO = 32
7129 23:55:01.621914 CA_UI_PI_RATIO = 0
7130 23:55:01.625250 ===================================
7131 23:55:01.628619 ===================================
7132 23:55:01.631995 memory_type:LPDDR4
7133 23:55:01.632062 GP_NUM : 10
7134 23:55:01.635300 SRAM_EN : 1
7135 23:55:01.638959 MD32_EN : 0
7136 23:55:01.642246 ===================================
7137 23:55:01.642327 [ANA_INIT] >>>>>>>>>>>>>>
7138 23:55:01.645575 <<<<<< [CONFIGURE PHASE]: ANA_TX
7139 23:55:01.648967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7140 23:55:01.651972 ===================================
7141 23:55:01.655370 data_rate = 3200,PCW = 0X7600
7142 23:55:01.659131 ===================================
7143 23:55:01.662292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7144 23:55:01.668841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7145 23:55:01.671973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 23:55:01.678734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7147 23:55:01.682428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7148 23:55:01.685869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7149 23:55:01.685940 [ANA_INIT] flow start
7150 23:55:01.688935 [ANA_INIT] PLL >>>>>>>>
7151 23:55:01.692037 [ANA_INIT] PLL <<<<<<<<
7152 23:55:01.692117 [ANA_INIT] MIDPI >>>>>>>>
7153 23:55:01.695257 [ANA_INIT] MIDPI <<<<<<<<
7154 23:55:01.699167 [ANA_INIT] DLL >>>>>>>>
7155 23:55:01.702257 [ANA_INIT] DLL <<<<<<<<
7156 23:55:01.702337 [ANA_INIT] flow end
7157 23:55:01.705542 ============ LP4 DIFF to SE enter ============
7158 23:55:01.712451 ============ LP4 DIFF to SE exit ============
7159 23:55:01.712533 [ANA_INIT] <<<<<<<<<<<<<
7160 23:55:01.715543 [Flow] Enable top DCM control >>>>>
7161 23:55:01.719382 [Flow] Enable top DCM control <<<<<
7162 23:55:01.722289 Enable DLL master slave shuffle
7163 23:55:01.729202 ==============================================================
7164 23:55:01.729286 Gating Mode config
7165 23:55:01.735999 ==============================================================
7166 23:55:01.739208 Config description:
7167 23:55:01.745462 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7168 23:55:01.752354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7169 23:55:01.758905 SELPH_MODE 0: By rank 1: By Phase
7170 23:55:01.762035 ==============================================================
7171 23:55:01.765537 GAT_TRACK_EN = 1
7172 23:55:01.768834 RX_GATING_MODE = 2
7173 23:55:01.772207 RX_GATING_TRACK_MODE = 2
7174 23:55:01.775594 SELPH_MODE = 1
7175 23:55:01.778910 PICG_EARLY_EN = 1
7176 23:55:01.782716 VALID_LAT_VALUE = 1
7177 23:55:01.788678 ==============================================================
7178 23:55:01.792121 Enter into Gating configuration >>>>
7179 23:55:01.795585 Exit from Gating configuration <<<<
7180 23:55:01.798833 Enter into DVFS_PRE_config >>>>>
7181 23:55:01.808826 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7182 23:55:01.812572 Exit from DVFS_PRE_config <<<<<
7183 23:55:01.815818 Enter into PICG configuration >>>>
7184 23:55:01.819129 Exit from PICG configuration <<<<
7185 23:55:01.819210 [RX_INPUT] configuration >>>>>
7186 23:55:01.822848 [RX_INPUT] configuration <<<<<
7187 23:55:01.829170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7188 23:55:01.832682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7189 23:55:01.839642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7190 23:55:01.845790 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7191 23:55:01.852457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7192 23:55:01.859382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7193 23:55:01.862572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7194 23:55:01.866062 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7195 23:55:01.869435 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7196 23:55:01.876158 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7197 23:55:01.879448 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7198 23:55:01.883203 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 23:55:01.885914 ===================================
7200 23:55:01.889320 LPDDR4 DRAM CONFIGURATION
7201 23:55:01.892584 ===================================
7202 23:55:01.895919 EX_ROW_EN[0] = 0x0
7203 23:55:01.896003 EX_ROW_EN[1] = 0x0
7204 23:55:01.899409 LP4Y_EN = 0x0
7205 23:55:01.899490 WORK_FSP = 0x1
7206 23:55:01.902476 WL = 0x5
7207 23:55:01.902557 RL = 0x5
7208 23:55:01.906422 BL = 0x2
7209 23:55:01.906503 RPST = 0x0
7210 23:55:01.909702 RD_PRE = 0x0
7211 23:55:01.909782 WR_PRE = 0x1
7212 23:55:01.912943 WR_PST = 0x1
7213 23:55:01.913045 DBI_WR = 0x0
7214 23:55:01.916130 DBI_RD = 0x0
7215 23:55:01.916211 OTF = 0x1
7216 23:55:01.919462 ===================================
7217 23:55:01.923100 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7218 23:55:01.929677 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7219 23:55:01.933014 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7220 23:55:01.936008 ===================================
7221 23:55:01.939378 LPDDR4 DRAM CONFIGURATION
7222 23:55:01.942737 ===================================
7223 23:55:01.942818 EX_ROW_EN[0] = 0x10
7224 23:55:01.946116 EX_ROW_EN[1] = 0x0
7225 23:55:01.949328 LP4Y_EN = 0x0
7226 23:55:01.949409 WORK_FSP = 0x1
7227 23:55:01.952479 WL = 0x5
7228 23:55:01.952560 RL = 0x5
7229 23:55:01.956268 BL = 0x2
7230 23:55:01.956349 RPST = 0x0
7231 23:55:01.959115 RD_PRE = 0x0
7232 23:55:01.959196 WR_PRE = 0x1
7233 23:55:01.962460 WR_PST = 0x1
7234 23:55:01.962540 DBI_WR = 0x0
7235 23:55:01.966184 DBI_RD = 0x0
7236 23:55:01.966264 OTF = 0x1
7237 23:55:01.969513 ===================================
7238 23:55:01.976134 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7239 23:55:01.976216 ==
7240 23:55:01.979193 Dram Type= 6, Freq= 0, CH_0, rank 0
7241 23:55:01.982545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7242 23:55:01.982627 ==
7243 23:55:01.985924 [Duty_Offset_Calibration]
7244 23:55:01.989307 B0:2 B1:-1 CA:1
7245 23:55:01.989388
7246 23:55:01.992258 [DutyScan_Calibration_Flow] k_type=0
7247 23:55:02.000312
7248 23:55:02.000393 ==CLK 0==
7249 23:55:02.003773 Final CLK duty delay cell = -4
7250 23:55:02.007013 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7251 23:55:02.010484 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7252 23:55:02.013627 [-4] AVG Duty = 4937%(X100)
7253 23:55:02.013707
7254 23:55:02.016628 CH0 CLK Duty spec in!! Max-Min= 187%
7255 23:55:02.020014 [DutyScan_Calibration_Flow] ====Done====
7256 23:55:02.020096
7257 23:55:02.023490 [DutyScan_Calibration_Flow] k_type=1
7258 23:55:02.039733
7259 23:55:02.039810 ==DQS 0 ==
7260 23:55:02.043126 Final DQS duty delay cell = 0
7261 23:55:02.046973 [0] MAX Duty = 5125%(X100), DQS PI = 20
7262 23:55:02.049893 [0] MIN Duty = 5000%(X100), DQS PI = 14
7263 23:55:02.052944 [0] AVG Duty = 5062%(X100)
7264 23:55:02.053045
7265 23:55:02.053109 ==DQS 1 ==
7266 23:55:02.056485 Final DQS duty delay cell = -4
7267 23:55:02.060297 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7268 23:55:02.063113 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7269 23:55:02.066854 [-4] AVG Duty = 5046%(X100)
7270 23:55:02.066935
7271 23:55:02.070217 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7272 23:55:02.070298
7273 23:55:02.073155 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7274 23:55:02.076601 [DutyScan_Calibration_Flow] ====Done====
7275 23:55:02.076682
7276 23:55:02.079812 [DutyScan_Calibration_Flow] k_type=3
7277 23:55:02.097155
7278 23:55:02.097235 ==DQM 0 ==
7279 23:55:02.100395 Final DQM duty delay cell = 0
7280 23:55:02.103657 [0] MAX Duty = 5000%(X100), DQS PI = 20
7281 23:55:02.106954 [0] MIN Duty = 4875%(X100), DQS PI = 6
7282 23:55:02.107035 [0] AVG Duty = 4937%(X100)
7283 23:55:02.110328
7284 23:55:02.110410 ==DQM 1 ==
7285 23:55:02.113972 Final DQM duty delay cell = 0
7286 23:55:02.117121 [0] MAX Duty = 5218%(X100), DQS PI = 58
7287 23:55:02.120966 [0] MIN Duty = 4969%(X100), DQS PI = 20
7288 23:55:02.121055 [0] AVG Duty = 5093%(X100)
7289 23:55:02.124221
7290 23:55:02.127615 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7291 23:55:02.127696
7292 23:55:02.130917 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7293 23:55:02.133981 [DutyScan_Calibration_Flow] ====Done====
7294 23:55:02.134061
7295 23:55:02.137170 [DutyScan_Calibration_Flow] k_type=2
7296 23:55:02.153587
7297 23:55:02.153668 ==DQ 0 ==
7298 23:55:02.156777 Final DQ duty delay cell = -4
7299 23:55:02.160207 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7300 23:55:02.163731 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7301 23:55:02.163812 [-4] AVG Duty = 4922%(X100)
7302 23:55:02.166911
7303 23:55:02.166991 ==DQ 1 ==
7304 23:55:02.170315 Final DQ duty delay cell = 0
7305 23:55:02.173929 [0] MAX Duty = 5031%(X100), DQS PI = 30
7306 23:55:02.177131 [0] MIN Duty = 4907%(X100), DQS PI = 20
7307 23:55:02.177213 [0] AVG Duty = 4969%(X100)
7308 23:55:02.177277
7309 23:55:02.180254 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7310 23:55:02.183507
7311 23:55:02.187224 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7312 23:55:02.190363 [DutyScan_Calibration_Flow] ====Done====
7313 23:55:02.190443 ==
7314 23:55:02.193573 Dram Type= 6, Freq= 0, CH_1, rank 0
7315 23:55:02.197355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7316 23:55:02.197436 ==
7317 23:55:02.200287 [Duty_Offset_Calibration]
7318 23:55:02.200367 B0:1 B1:1 CA:2
7319 23:55:02.200429
7320 23:55:02.203649 [DutyScan_Calibration_Flow] k_type=0
7321 23:55:02.213904
7322 23:55:02.214009 ==CLK 0==
7323 23:55:02.217247 Final CLK duty delay cell = 0
7324 23:55:02.220875 [0] MAX Duty = 5187%(X100), DQS PI = 24
7325 23:55:02.224058 [0] MIN Duty = 4938%(X100), DQS PI = 48
7326 23:55:02.224138 [0] AVG Duty = 5062%(X100)
7327 23:55:02.227528
7328 23:55:02.230834 CH1 CLK Duty spec in!! Max-Min= 249%
7329 23:55:02.234266 [DutyScan_Calibration_Flow] ====Done====
7330 23:55:02.234346
7331 23:55:02.237655 [DutyScan_Calibration_Flow] k_type=1
7332 23:55:02.254179
7333 23:55:02.254260 ==DQS 0 ==
7334 23:55:02.257165 Final DQS duty delay cell = 0
7335 23:55:02.260706 [0] MAX Duty = 5031%(X100), DQS PI = 20
7336 23:55:02.264421 [0] MIN Duty = 4813%(X100), DQS PI = 50
7337 23:55:02.266951 [0] AVG Duty = 4922%(X100)
7338 23:55:02.267031
7339 23:55:02.267094 ==DQS 1 ==
7340 23:55:02.270248 Final DQS duty delay cell = 0
7341 23:55:02.273895 [0] MAX Duty = 5031%(X100), DQS PI = 34
7342 23:55:02.277180 [0] MIN Duty = 4938%(X100), DQS PI = 14
7343 23:55:02.277259 [0] AVG Duty = 4984%(X100)
7344 23:55:02.280739
7345 23:55:02.284335 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7346 23:55:02.284415
7347 23:55:02.287011 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7348 23:55:02.290402 [DutyScan_Calibration_Flow] ====Done====
7349 23:55:02.290482
7350 23:55:02.293768 [DutyScan_Calibration_Flow] k_type=3
7351 23:55:02.310619
7352 23:55:02.310698 ==DQM 0 ==
7353 23:55:02.314105 Final DQM duty delay cell = 0
7354 23:55:02.317186 [0] MAX Duty = 5156%(X100), DQS PI = 20
7355 23:55:02.320730 [0] MIN Duty = 4813%(X100), DQS PI = 50
7356 23:55:02.320810 [0] AVG Duty = 4984%(X100)
7357 23:55:02.324271
7358 23:55:02.324350 ==DQM 1 ==
7359 23:55:02.327317 Final DQM duty delay cell = 0
7360 23:55:02.330899 [0] MAX Duty = 5125%(X100), DQS PI = 8
7361 23:55:02.333967 [0] MIN Duty = 4875%(X100), DQS PI = 20
7362 23:55:02.334047 [0] AVG Duty = 5000%(X100)
7363 23:55:02.334110
7364 23:55:02.340700 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7365 23:55:02.340780
7366 23:55:02.344202 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7367 23:55:02.347577 [DutyScan_Calibration_Flow] ====Done====
7368 23:55:02.347656
7369 23:55:02.350652 [DutyScan_Calibration_Flow] k_type=2
7370 23:55:02.367620
7371 23:55:02.367703 ==DQ 0 ==
7372 23:55:02.370733 Final DQ duty delay cell = 0
7373 23:55:02.374191 [0] MAX Duty = 5125%(X100), DQS PI = 20
7374 23:55:02.377495 [0] MIN Duty = 4907%(X100), DQS PI = 52
7375 23:55:02.377574 [0] AVG Duty = 5016%(X100)
7376 23:55:02.380892
7377 23:55:02.380972 ==DQ 1 ==
7378 23:55:02.384310 Final DQ duty delay cell = 0
7379 23:55:02.387480 [0] MAX Duty = 5093%(X100), DQS PI = 6
7380 23:55:02.390856 [0] MIN Duty = 5031%(X100), DQS PI = 0
7381 23:55:02.390936 [0] AVG Duty = 5062%(X100)
7382 23:55:02.391000
7383 23:55:02.394179 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7384 23:55:02.394259
7385 23:55:02.397649 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7386 23:55:02.404244 [DutyScan_Calibration_Flow] ====Done====
7387 23:55:02.407664 nWR fixed to 30
7388 23:55:02.407744 [ModeRegInit_LP4] CH0 RK0
7389 23:55:02.410844 [ModeRegInit_LP4] CH0 RK1
7390 23:55:02.414183 [ModeRegInit_LP4] CH1 RK0
7391 23:55:02.414263 [ModeRegInit_LP4] CH1 RK1
7392 23:55:02.417385 match AC timing 5
7393 23:55:02.420808 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7394 23:55:02.424012 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7395 23:55:02.430818 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7396 23:55:02.434374 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7397 23:55:02.441015 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7398 23:55:02.441108 [MiockJmeterHQA]
7399 23:55:02.441173
7400 23:55:02.444518 [DramcMiockJmeter] u1RxGatingPI = 0
7401 23:55:02.444599 0 : 4252, 4026
7402 23:55:02.447610 4 : 4368, 4140
7403 23:55:02.447692 8 : 4257, 4029
7404 23:55:02.450828 12 : 4252, 4026
7405 23:55:02.450910 16 : 4253, 4027
7406 23:55:02.454825 20 : 4253, 4026
7407 23:55:02.454907 24 : 4255, 4030
7408 23:55:02.454972 28 : 4252, 4027
7409 23:55:02.457999 32 : 4252, 4027
7410 23:55:02.458080 36 : 4365, 4140
7411 23:55:02.461186 40 : 4253, 4026
7412 23:55:02.461275 44 : 4255, 4030
7413 23:55:02.464292 48 : 4252, 4027
7414 23:55:02.464373 52 : 4363, 4137
7415 23:55:02.467898 56 : 4252, 4027
7416 23:55:02.467980 60 : 4363, 4137
7417 23:55:02.468046 64 : 4252, 4027
7418 23:55:02.471475 68 : 4249, 4027
7419 23:55:02.471556 72 : 4252, 4026
7420 23:55:02.474395 76 : 4252, 4029
7421 23:55:02.474475 80 : 4249, 4027
7422 23:55:02.478129 84 : 4250, 4027
7423 23:55:02.478237 88 : 4363, 4140
7424 23:55:02.478331 92 : 4250, 4026
7425 23:55:02.481345 96 : 4252, 3316
7426 23:55:02.481444 100 : 4249, 0
7427 23:55:02.484502 104 : 4250, 0
7428 23:55:02.484582 108 : 4250, 0
7429 23:55:02.484647 112 : 4250, 0
7430 23:55:02.487557 116 : 4252, 0
7431 23:55:02.487638 120 : 4250, 0
7432 23:55:02.491353 124 : 4360, 0
7433 23:55:02.491433 128 : 4361, 0
7434 23:55:02.491498 132 : 4252, 0
7435 23:55:02.494611 136 : 4250, 0
7436 23:55:02.494693 140 : 4362, 0
7437 23:55:02.497881 144 : 4250, 0
7438 23:55:02.497962 148 : 4250, 0
7439 23:55:02.498027 152 : 4249, 0
7440 23:55:02.500855 156 : 4252, 0
7441 23:55:02.500936 160 : 4361, 0
7442 23:55:02.504409 164 : 4249, 0
7443 23:55:02.504493 168 : 4250, 0
7444 23:55:02.504557 172 : 4252, 0
7445 23:55:02.507904 176 : 4360, 0
7446 23:55:02.507986 180 : 4360, 0
7447 23:55:02.510952 184 : 4250, 0
7448 23:55:02.511033 188 : 4250, 0
7449 23:55:02.511098 192 : 4249, 0
7450 23:55:02.514295 196 : 4252, 0
7451 23:55:02.514382 200 : 4250, 0
7452 23:55:02.514447 204 : 4249, 0
7453 23:55:02.517432 208 : 4252, 0
7454 23:55:02.517513 212 : 4361, 61
7455 23:55:02.520819 216 : 4249, 3447
7456 23:55:02.520919 220 : 4361, 4137
7457 23:55:02.524320 224 : 4361, 4137
7458 23:55:02.524402 228 : 4247, 4025
7459 23:55:02.527448 232 : 4363, 4140
7460 23:55:02.527529 236 : 4361, 4137
7461 23:55:02.530982 240 : 4250, 4026
7462 23:55:02.531063 244 : 4250, 4027
7463 23:55:02.531129 248 : 4252, 4030
7464 23:55:02.534557 252 : 4249, 4027
7465 23:55:02.534639 256 : 4250, 4026
7466 23:55:02.537359 260 : 4250, 4027
7467 23:55:02.537441 264 : 4252, 4030
7468 23:55:02.541330 268 : 4249, 4027
7469 23:55:02.541411 272 : 4360, 4137
7470 23:55:02.544116 276 : 4361, 4137
7471 23:55:02.544197 280 : 4250, 4027
7472 23:55:02.547616 284 : 4363, 4140
7473 23:55:02.547697 288 : 4249, 4027
7474 23:55:02.550884 292 : 4250, 4026
7475 23:55:02.550966 296 : 4250, 4027
7476 23:55:02.553974 300 : 4252, 4030
7477 23:55:02.554056 304 : 4249, 4027
7478 23:55:02.554122 308 : 4250, 4026
7479 23:55:02.557435 312 : 4250, 4027
7480 23:55:02.557517 316 : 4252, 4030
7481 23:55:02.560878 320 : 4249, 4027
7482 23:55:02.560959 324 : 4360, 4137
7483 23:55:02.564827 328 : 4361, 4137
7484 23:55:02.564908 332 : 4250, 3091
7485 23:55:02.567657 336 : 4363, 170
7486 23:55:02.567739
7487 23:55:02.567803 MIOCK jitter meter ch=0
7488 23:55:02.567863
7489 23:55:02.571089 1T = (336-100) = 236 dly cells
7490 23:55:02.577196 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7491 23:55:02.577277 ==
7492 23:55:02.581016 Dram Type= 6, Freq= 0, CH_0, rank 0
7493 23:55:02.584305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 23:55:02.584386 ==
7495 23:55:02.590763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 23:55:02.593935 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 23:55:02.600336 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 23:55:02.604399 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 23:55:02.614001 [CA 0] Center 44 (14~75) winsize 62
7500 23:55:02.617597 [CA 1] Center 44 (14~74) winsize 61
7501 23:55:02.620517 [CA 2] Center 39 (10~68) winsize 59
7502 23:55:02.623955 [CA 3] Center 39 (10~68) winsize 59
7503 23:55:02.627159 [CA 4] Center 37 (7~67) winsize 61
7504 23:55:02.630572 [CA 5] Center 37 (7~67) winsize 61
7505 23:55:02.630653
7506 23:55:02.634089 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7507 23:55:02.634169
7508 23:55:02.637277 [CATrainingPosCal] consider 1 rank data
7509 23:55:02.640676 u2DelayCellTimex100 = 275/100 ps
7510 23:55:02.644189 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7511 23:55:02.650941 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7512 23:55:02.654148 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7513 23:55:02.657467 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7514 23:55:02.660801 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7515 23:55:02.664134 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7516 23:55:02.664218
7517 23:55:02.667454 CA PerBit enable=1, Macro0, CA PI delay=37
7518 23:55:02.667535
7519 23:55:02.670500 [CBTSetCACLKResult] CA Dly = 37
7520 23:55:02.673836 CS Dly: 10 (0~41)
7521 23:55:02.677491 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 23:55:02.680735 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 23:55:02.680816 ==
7524 23:55:02.684318 Dram Type= 6, Freq= 0, CH_0, rank 1
7525 23:55:02.687532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 23:55:02.690421 ==
7527 23:55:02.694219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7528 23:55:02.697318 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7529 23:55:02.704000 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7530 23:55:02.707107 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7531 23:55:02.717513 [CA 0] Center 43 (13~74) winsize 62
7532 23:55:02.720920 [CA 1] Center 43 (13~74) winsize 62
7533 23:55:02.724305 [CA 2] Center 39 (10~69) winsize 60
7534 23:55:02.727975 [CA 3] Center 38 (9~68) winsize 60
7535 23:55:02.730820 [CA 4] Center 37 (7~67) winsize 61
7536 23:55:02.734117 [CA 5] Center 37 (7~67) winsize 61
7537 23:55:02.734225
7538 23:55:02.737531 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7539 23:55:02.737611
7540 23:55:02.740869 [CATrainingPosCal] consider 2 rank data
7541 23:55:02.744626 u2DelayCellTimex100 = 275/100 ps
7542 23:55:02.747521 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7543 23:55:02.754283 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7544 23:55:02.757512 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7545 23:55:02.760923 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7546 23:55:02.764500 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7547 23:55:02.767967 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7548 23:55:02.768048
7549 23:55:02.771045 CA PerBit enable=1, Macro0, CA PI delay=37
7550 23:55:02.771126
7551 23:55:02.774197 [CBTSetCACLKResult] CA Dly = 37
7552 23:55:02.777425 CS Dly: 11 (0~44)
7553 23:55:02.780756 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7554 23:55:02.784401 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7555 23:55:02.784482
7556 23:55:02.787768 ----->DramcWriteLeveling(PI) begin...
7557 23:55:02.787850 ==
7558 23:55:02.791265 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 23:55:02.794506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 23:55:02.797808 ==
7561 23:55:02.797889 Write leveling (Byte 0): 32 => 32
7562 23:55:02.801355 Write leveling (Byte 1): 29 => 29
7563 23:55:02.804222 DramcWriteLeveling(PI) end<-----
7564 23:55:02.804303
7565 23:55:02.804367 ==
7566 23:55:02.807627 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 23:55:02.814822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 23:55:02.814902 ==
7569 23:55:02.814967 [Gating] SW mode calibration
7570 23:55:02.824521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7571 23:55:02.827594 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7572 23:55:02.831432 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 23:55:02.837751 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 23:55:02.840873 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 23:55:02.844679 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 23:55:02.851555 1 4 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7577 23:55:02.855057 1 4 20 | B1->B0 | 2323 3231 | 1 1 | (1 1) (0 0)
7578 23:55:02.858253 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7579 23:55:02.864428 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 23:55:02.868158 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 23:55:02.871664 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 23:55:02.878027 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 23:55:02.881373 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7584 23:55:02.884579 1 5 16 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7585 23:55:02.891343 1 5 20 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
7586 23:55:02.894622 1 5 24 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7587 23:55:02.898420 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 23:55:02.901618 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 23:55:02.908636 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 23:55:02.911755 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 23:55:02.914981 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 23:55:02.921776 1 6 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7593 23:55:02.925098 1 6 20 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
7594 23:55:02.927975 1 6 24 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
7595 23:55:02.934718 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 23:55:02.938126 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 23:55:02.941377 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 23:55:02.947867 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 23:55:02.951362 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7600 23:55:02.954710 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7601 23:55:02.961709 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7602 23:55:02.964614 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7603 23:55:02.967937 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 23:55:02.974922 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 23:55:02.978402 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 23:55:02.981480 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 23:55:02.987822 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 23:55:02.991363 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 23:55:02.994851 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 23:55:02.997960 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 23:55:03.004458 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:55:03.008208 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:55:03.011851 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:55:03.018002 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:55:03.021194 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7616 23:55:03.024756 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 23:55:03.031265 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7618 23:55:03.034413 Total UI for P1: 0, mck2ui 16
7619 23:55:03.037805 best dqsien dly found for B0: ( 1, 9, 14)
7620 23:55:03.041567 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 23:55:03.044316 Total UI for P1: 0, mck2ui 16
7622 23:55:03.047922 best dqsien dly found for B1: ( 1, 9, 20)
7623 23:55:03.051320 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7624 23:55:03.055344 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7625 23:55:03.055425
7626 23:55:03.058019 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7627 23:55:03.061100 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7628 23:55:03.064788 [Gating] SW calibration Done
7629 23:55:03.064869 ==
7630 23:55:03.067819 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 23:55:03.071584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 23:55:03.075010 ==
7633 23:55:03.075091 RX Vref Scan: 0
7634 23:55:03.075155
7635 23:55:03.078813 RX Vref 0 -> 0, step: 1
7636 23:55:03.078894
7637 23:55:03.081250 RX Delay 0 -> 252, step: 8
7638 23:55:03.084576 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7639 23:55:03.088184 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7640 23:55:03.091444 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7641 23:55:03.095091 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7642 23:55:03.098389 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7643 23:55:03.104822 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7644 23:55:03.108575 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7645 23:55:03.111405 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7646 23:55:03.114746 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7647 23:55:03.118145 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7648 23:55:03.124943 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7649 23:55:03.128420 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7650 23:55:03.131255 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7651 23:55:03.134674 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7652 23:55:03.137913 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7653 23:55:03.144787 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7654 23:55:03.144892 ==
7655 23:55:03.147719 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 23:55:03.151034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 23:55:03.151115 ==
7658 23:55:03.151179 DQS Delay:
7659 23:55:03.155015 DQS0 = 0, DQS1 = 0
7660 23:55:03.155120 DQM Delay:
7661 23:55:03.157893 DQM0 = 132, DQM1 = 124
7662 23:55:03.157990 DQ Delay:
7663 23:55:03.161382 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7664 23:55:03.164848 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7665 23:55:03.168010 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7666 23:55:03.171432 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7667 23:55:03.171513
7668 23:55:03.175290
7669 23:55:03.175369 ==
7670 23:55:03.178062 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 23:55:03.181912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 23:55:03.181992 ==
7673 23:55:03.182057
7674 23:55:03.182116
7675 23:55:03.184649 TX Vref Scan disable
7676 23:55:03.184729 == TX Byte 0 ==
7677 23:55:03.191410 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7678 23:55:03.194942 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7679 23:55:03.195022 == TX Byte 1 ==
7680 23:55:03.198307 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7681 23:55:03.204958 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7682 23:55:03.205100 ==
7683 23:55:03.208549 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 23:55:03.211690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 23:55:03.211771 ==
7686 23:55:03.226155
7687 23:55:03.229241 TX Vref early break, caculate TX vref
7688 23:55:03.232578 TX Vref=16, minBit 1, minWin=21, winSum=363
7689 23:55:03.235948 TX Vref=18, minBit 1, minWin=21, winSum=373
7690 23:55:03.239104 TX Vref=20, minBit 1, minWin=22, winSum=379
7691 23:55:03.242703 TX Vref=22, minBit 7, minWin=21, winSum=387
7692 23:55:03.245786 TX Vref=24, minBit 0, minWin=23, winSum=402
7693 23:55:03.252849 TX Vref=26, minBit 1, minWin=24, winSum=412
7694 23:55:03.256081 TX Vref=28, minBit 0, minWin=25, winSum=420
7695 23:55:03.259305 TX Vref=30, minBit 0, minWin=25, winSum=419
7696 23:55:03.262607 TX Vref=32, minBit 0, minWin=24, winSum=412
7697 23:55:03.266005 TX Vref=34, minBit 0, minWin=24, winSum=402
7698 23:55:03.269611 TX Vref=36, minBit 0, minWin=23, winSum=393
7699 23:55:03.275989 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
7700 23:55:03.276070
7701 23:55:03.279878 Final TX Range 0 Vref 28
7702 23:55:03.279958
7703 23:55:03.280022 ==
7704 23:55:03.283022 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 23:55:03.286514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 23:55:03.286595 ==
7707 23:55:03.286659
7708 23:55:03.286718
7709 23:55:03.289666 TX Vref Scan disable
7710 23:55:03.296115 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7711 23:55:03.296196 == TX Byte 0 ==
7712 23:55:03.299589 u2DelayCellOfst[0]=17 cells (5 PI)
7713 23:55:03.302917 u2DelayCellOfst[1]=21 cells (6 PI)
7714 23:55:03.306066 u2DelayCellOfst[2]=14 cells (4 PI)
7715 23:55:03.309714 u2DelayCellOfst[3]=17 cells (5 PI)
7716 23:55:03.313002 u2DelayCellOfst[4]=10 cells (3 PI)
7717 23:55:03.316188 u2DelayCellOfst[5]=0 cells (0 PI)
7718 23:55:03.319493 u2DelayCellOfst[6]=21 cells (6 PI)
7719 23:55:03.322845 u2DelayCellOfst[7]=21 cells (6 PI)
7720 23:55:03.326513 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7721 23:55:03.329535 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7722 23:55:03.333073 == TX Byte 1 ==
7723 23:55:03.333153 u2DelayCellOfst[8]=0 cells (0 PI)
7724 23:55:03.336018 u2DelayCellOfst[9]=0 cells (0 PI)
7725 23:55:03.339785 u2DelayCellOfst[10]=7 cells (2 PI)
7726 23:55:03.343048 u2DelayCellOfst[11]=0 cells (0 PI)
7727 23:55:03.346417 u2DelayCellOfst[12]=10 cells (3 PI)
7728 23:55:03.349596 u2DelayCellOfst[13]=10 cells (3 PI)
7729 23:55:03.353180 u2DelayCellOfst[14]=14 cells (4 PI)
7730 23:55:03.356546 u2DelayCellOfst[15]=7 cells (2 PI)
7731 23:55:03.359688 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7732 23:55:03.366442 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7733 23:55:03.366529 DramC Write-DBI on
7734 23:55:03.366594 ==
7735 23:55:03.369465 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 23:55:03.373415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 23:55:03.373496 ==
7738 23:55:03.373560
7739 23:55:03.376419
7740 23:55:03.376498 TX Vref Scan disable
7741 23:55:03.379466 == TX Byte 0 ==
7742 23:55:03.382789 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7743 23:55:03.386553 == TX Byte 1 ==
7744 23:55:03.389505 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7745 23:55:03.389586 DramC Write-DBI off
7746 23:55:03.389650
7747 23:55:03.393224 [DATLAT]
7748 23:55:03.393304 Freq=1600, CH0 RK0
7749 23:55:03.393368
7750 23:55:03.396735 DATLAT Default: 0xf
7751 23:55:03.396815 0, 0xFFFF, sum = 0
7752 23:55:03.400105 1, 0xFFFF, sum = 0
7753 23:55:03.400187 2, 0xFFFF, sum = 0
7754 23:55:03.403036 3, 0xFFFF, sum = 0
7755 23:55:03.403119 4, 0xFFFF, sum = 0
7756 23:55:03.406177 5, 0xFFFF, sum = 0
7757 23:55:03.406259 6, 0xFFFF, sum = 0
7758 23:55:03.409508 7, 0xFFFF, sum = 0
7759 23:55:03.409589 8, 0xFFFF, sum = 0
7760 23:55:03.413148 9, 0xFFFF, sum = 0
7761 23:55:03.416323 10, 0xFFFF, sum = 0
7762 23:55:03.416405 11, 0xFFFF, sum = 0
7763 23:55:03.419579 12, 0xFFFF, sum = 0
7764 23:55:03.419661 13, 0xFFFF, sum = 0
7765 23:55:03.422765 14, 0x0, sum = 1
7766 23:55:03.422847 15, 0x0, sum = 2
7767 23:55:03.426075 16, 0x0, sum = 3
7768 23:55:03.426157 17, 0x0, sum = 4
7769 23:55:03.426222 best_step = 15
7770 23:55:03.429907
7771 23:55:03.429988 ==
7772 23:55:03.433201 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 23:55:03.436434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 23:55:03.436517 ==
7775 23:55:03.436611 RX Vref Scan: 1
7776 23:55:03.436699
7777 23:55:03.439539 Set Vref Range= 24 -> 127
7778 23:55:03.439620
7779 23:55:03.442964 RX Vref 24 -> 127, step: 1
7780 23:55:03.443044
7781 23:55:03.446412 RX Delay 11 -> 252, step: 4
7782 23:55:03.446492
7783 23:55:03.450048 Set Vref, RX VrefLevel [Byte0]: 24
7784 23:55:03.453725 [Byte1]: 24
7785 23:55:03.453806
7786 23:55:03.456575 Set Vref, RX VrefLevel [Byte0]: 25
7787 23:55:03.460062 [Byte1]: 25
7788 23:55:03.460143
7789 23:55:03.463107 Set Vref, RX VrefLevel [Byte0]: 26
7790 23:55:03.466508 [Byte1]: 26
7791 23:55:03.470024
7792 23:55:03.470104 Set Vref, RX VrefLevel [Byte0]: 27
7793 23:55:03.473222 [Byte1]: 27
7794 23:55:03.477544
7795 23:55:03.477623 Set Vref, RX VrefLevel [Byte0]: 28
7796 23:55:03.480593 [Byte1]: 28
7797 23:55:03.485322
7798 23:55:03.485401 Set Vref, RX VrefLevel [Byte0]: 29
7799 23:55:03.488225 [Byte1]: 29
7800 23:55:03.492833
7801 23:55:03.492913 Set Vref, RX VrefLevel [Byte0]: 30
7802 23:55:03.495952 [Byte1]: 30
7803 23:55:03.500375
7804 23:55:03.500455 Set Vref, RX VrefLevel [Byte0]: 31
7805 23:55:03.503722 [Byte1]: 31
7806 23:55:03.507882
7807 23:55:03.507962 Set Vref, RX VrefLevel [Byte0]: 32
7808 23:55:03.511435 [Byte1]: 32
7809 23:55:03.515919
7810 23:55:03.515999 Set Vref, RX VrefLevel [Byte0]: 33
7811 23:55:03.518702 [Byte1]: 33
7812 23:55:03.523489
7813 23:55:03.523605 Set Vref, RX VrefLevel [Byte0]: 34
7814 23:55:03.526765 [Byte1]: 34
7815 23:55:03.530757
7816 23:55:03.530837 Set Vref, RX VrefLevel [Byte0]: 35
7817 23:55:03.533798 [Byte1]: 35
7818 23:55:03.538247
7819 23:55:03.538326 Set Vref, RX VrefLevel [Byte0]: 36
7820 23:55:03.541503 [Byte1]: 36
7821 23:55:03.545925
7822 23:55:03.546005 Set Vref, RX VrefLevel [Byte0]: 37
7823 23:55:03.548807 [Byte1]: 37
7824 23:55:03.553334
7825 23:55:03.553414 Set Vref, RX VrefLevel [Byte0]: 38
7826 23:55:03.556988 [Byte1]: 38
7827 23:55:03.561001
7828 23:55:03.561095 Set Vref, RX VrefLevel [Byte0]: 39
7829 23:55:03.564219 [Byte1]: 39
7830 23:55:03.568349
7831 23:55:03.568429 Set Vref, RX VrefLevel [Byte0]: 40
7832 23:55:03.571786 [Byte1]: 40
7833 23:55:03.576218
7834 23:55:03.576325 Set Vref, RX VrefLevel [Byte0]: 41
7835 23:55:03.582606 [Byte1]: 41
7836 23:55:03.582687
7837 23:55:03.586327 Set Vref, RX VrefLevel [Byte0]: 42
7838 23:55:03.589407 [Byte1]: 42
7839 23:55:03.589488
7840 23:55:03.592798 Set Vref, RX VrefLevel [Byte0]: 43
7841 23:55:03.596014 [Byte1]: 43
7842 23:55:03.596094
7843 23:55:03.599511 Set Vref, RX VrefLevel [Byte0]: 44
7844 23:55:03.602848 [Byte1]: 44
7845 23:55:03.606740
7846 23:55:03.606820 Set Vref, RX VrefLevel [Byte0]: 45
7847 23:55:03.610124 [Byte1]: 45
7848 23:55:03.614503
7849 23:55:03.614608 Set Vref, RX VrefLevel [Byte0]: 46
7850 23:55:03.617484 [Byte1]: 46
7851 23:55:03.622197
7852 23:55:03.622277 Set Vref, RX VrefLevel [Byte0]: 47
7853 23:55:03.625446 [Byte1]: 47
7854 23:55:03.629793
7855 23:55:03.629874 Set Vref, RX VrefLevel [Byte0]: 48
7856 23:55:03.633241 [Byte1]: 48
7857 23:55:03.637127
7858 23:55:03.637208 Set Vref, RX VrefLevel [Byte0]: 49
7859 23:55:03.640764 [Byte1]: 49
7860 23:55:03.644779
7861 23:55:03.644885 Set Vref, RX VrefLevel [Byte0]: 50
7862 23:55:03.648049 [Byte1]: 50
7863 23:55:03.652406
7864 23:55:03.652486 Set Vref, RX VrefLevel [Byte0]: 51
7865 23:55:03.656427 [Byte1]: 51
7866 23:55:03.660072
7867 23:55:03.660151 Set Vref, RX VrefLevel [Byte0]: 52
7868 23:55:03.663516 [Byte1]: 52
7869 23:55:03.667957
7870 23:55:03.668037 Set Vref, RX VrefLevel [Byte0]: 53
7871 23:55:03.671088 [Byte1]: 53
7872 23:55:03.675213
7873 23:55:03.675293 Set Vref, RX VrefLevel [Byte0]: 54
7874 23:55:03.678410 [Byte1]: 54
7875 23:55:03.683020
7876 23:55:03.683100 Set Vref, RX VrefLevel [Byte0]: 55
7877 23:55:03.686188 [Byte1]: 55
7878 23:55:03.690633
7879 23:55:03.690712 Set Vref, RX VrefLevel [Byte0]: 56
7880 23:55:03.693943 [Byte1]: 56
7881 23:55:03.698269
7882 23:55:03.698349 Set Vref, RX VrefLevel [Byte0]: 57
7883 23:55:03.701401 [Byte1]: 57
7884 23:55:03.705771
7885 23:55:03.705878 Set Vref, RX VrefLevel [Byte0]: 58
7886 23:55:03.709198 [Byte1]: 58
7887 23:55:03.713549
7888 23:55:03.713628 Set Vref, RX VrefLevel [Byte0]: 59
7889 23:55:03.716601 [Byte1]: 59
7890 23:55:03.720964
7891 23:55:03.721081 Set Vref, RX VrefLevel [Byte0]: 60
7892 23:55:03.724261 [Byte1]: 60
7893 23:55:03.728496
7894 23:55:03.728580 Set Vref, RX VrefLevel [Byte0]: 61
7895 23:55:03.732328 [Byte1]: 61
7896 23:55:03.736019
7897 23:55:03.736098 Set Vref, RX VrefLevel [Byte0]: 62
7898 23:55:03.739681 [Byte1]: 62
7899 23:55:03.743723
7900 23:55:03.743804 Set Vref, RX VrefLevel [Byte0]: 63
7901 23:55:03.746891 [Byte1]: 63
7902 23:55:03.751168
7903 23:55:03.751242 Set Vref, RX VrefLevel [Byte0]: 64
7904 23:55:03.754452 [Byte1]: 64
7905 23:55:03.758992
7906 23:55:03.759065 Set Vref, RX VrefLevel [Byte0]: 65
7907 23:55:03.762522 [Byte1]: 65
7908 23:55:03.766630
7909 23:55:03.766710 Set Vref, RX VrefLevel [Byte0]: 66
7910 23:55:03.769971 [Byte1]: 66
7911 23:55:03.774501
7912 23:55:03.774581 Set Vref, RX VrefLevel [Byte0]: 67
7913 23:55:03.777432 [Byte1]: 67
7914 23:55:03.781899
7915 23:55:03.781968 Set Vref, RX VrefLevel [Byte0]: 68
7916 23:55:03.785199 [Byte1]: 68
7917 23:55:03.789646
7918 23:55:03.789713 Set Vref, RX VrefLevel [Byte0]: 69
7919 23:55:03.792703 [Byte1]: 69
7920 23:55:03.797140
7921 23:55:03.797207 Set Vref, RX VrefLevel [Byte0]: 70
7922 23:55:03.800559 [Byte1]: 70
7923 23:55:03.804964
7924 23:55:03.805102 Set Vref, RX VrefLevel [Byte0]: 71
7925 23:55:03.808252 [Byte1]: 71
7926 23:55:03.812434
7927 23:55:03.812502 Set Vref, RX VrefLevel [Byte0]: 72
7928 23:55:03.815551 [Byte1]: 72
7929 23:55:03.819556
7930 23:55:03.819622 Set Vref, RX VrefLevel [Byte0]: 73
7931 23:55:03.822848 [Byte1]: 73
7932 23:55:03.827628
7933 23:55:03.827708 Set Vref, RX VrefLevel [Byte0]: 74
7934 23:55:03.831054 [Byte1]: 74
7935 23:55:03.835384
7936 23:55:03.835455 Set Vref, RX VrefLevel [Byte0]: 75
7937 23:55:03.839099 [Byte1]: 75
7938 23:55:03.842810
7939 23:55:03.842876 Set Vref, RX VrefLevel [Byte0]: 76
7940 23:55:03.845868 [Byte1]: 76
7941 23:55:03.850717
7942 23:55:03.850796 Set Vref, RX VrefLevel [Byte0]: 77
7943 23:55:03.853562 [Byte1]: 77
7944 23:55:03.857982
7945 23:55:03.858061 Final RX Vref Byte 0 = 59 to rank0
7946 23:55:03.861355 Final RX Vref Byte 1 = 61 to rank0
7947 23:55:03.864451 Final RX Vref Byte 0 = 59 to rank1
7948 23:55:03.868021 Final RX Vref Byte 1 = 61 to rank1==
7949 23:55:03.871074 Dram Type= 6, Freq= 0, CH_0, rank 0
7950 23:55:03.878047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 23:55:03.878128 ==
7952 23:55:03.878192 DQS Delay:
7953 23:55:03.878251 DQS0 = 0, DQS1 = 0
7954 23:55:03.881359 DQM Delay:
7955 23:55:03.881439 DQM0 = 129, DQM1 = 121
7956 23:55:03.884472 DQ Delay:
7957 23:55:03.887793 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7958 23:55:03.891153 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7959 23:55:03.894879 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7960 23:55:03.898153 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7961 23:55:03.898233
7962 23:55:03.898297
7963 23:55:03.898356
7964 23:55:03.901125 [DramC_TX_OE_Calibration] TA2
7965 23:55:03.904392 Original DQ_B0 (3 6) =30, OEN = 27
7966 23:55:03.908143 Original DQ_B1 (3 6) =30, OEN = 27
7967 23:55:03.911328 24, 0x0, End_B0=24 End_B1=24
7968 23:55:03.911397 25, 0x0, End_B0=25 End_B1=25
7969 23:55:03.914523 26, 0x0, End_B0=26 End_B1=26
7970 23:55:03.917787 27, 0x0, End_B0=27 End_B1=27
7971 23:55:03.921164 28, 0x0, End_B0=28 End_B1=28
7972 23:55:03.921247 29, 0x0, End_B0=29 End_B1=29
7973 23:55:03.924309 30, 0x0, End_B0=30 End_B1=30
7974 23:55:03.928106 31, 0x5151, End_B0=30 End_B1=30
7975 23:55:03.931295 Byte0 end_step=30 best_step=27
7976 23:55:03.934388 Byte1 end_step=30 best_step=27
7977 23:55:03.938358 Byte0 TX OE(2T, 0.5T) = (3, 3)
7978 23:55:03.938427 Byte1 TX OE(2T, 0.5T) = (3, 3)
7979 23:55:03.938491
7980 23:55:03.941228
7981 23:55:03.948317 [DQSOSCAuto] RK0, (LSB)MR18= 0x1206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7982 23:55:03.951211 CH0 RK0: MR19=303, MR18=1206
7983 23:55:03.957835 CH0_RK0: MR19=0x303, MR18=0x1206, DQSOSC=400, MR23=63, INC=23, DEC=15
7984 23:55:03.957907
7985 23:55:03.961097 ----->DramcWriteLeveling(PI) begin...
7986 23:55:03.961172 ==
7987 23:55:03.964303 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 23:55:03.967990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 23:55:03.968063 ==
7990 23:55:03.971249 Write leveling (Byte 0): 33 => 33
7991 23:55:03.974823 Write leveling (Byte 1): 27 => 27
7992 23:55:03.978246 DramcWriteLeveling(PI) end<-----
7993 23:55:03.978314
7994 23:55:03.978374 ==
7995 23:55:03.981311 Dram Type= 6, Freq= 0, CH_0, rank 1
7996 23:55:03.984790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 23:55:03.984858 ==
7998 23:55:03.988325 [Gating] SW mode calibration
7999 23:55:03.995131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8000 23:55:04.001167 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8001 23:55:04.004847 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 23:55:04.008163 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 23:55:04.014725 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 23:55:04.018147 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8005 23:55:04.021348 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8006 23:55:04.024678 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8007 23:55:04.031395 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 23:55:04.034580 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 23:55:04.038185 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 23:55:04.044762 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8011 23:55:04.047846 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8012 23:55:04.051415 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8013 23:55:04.058208 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8014 23:55:04.061428 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (0 1) (0 0)
8015 23:55:04.064640 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8016 23:55:04.071382 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 23:55:04.074457 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 23:55:04.078217 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 23:55:04.084734 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8020 23:55:04.087865 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8021 23:55:04.091290 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8022 23:55:04.098207 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8023 23:55:04.101328 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 23:55:04.104930 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 23:55:04.111088 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 23:55:04.114972 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 23:55:04.118247 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 23:55:04.124804 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 23:55:04.127938 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8030 23:55:04.131316 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8031 23:55:04.134570 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 23:55:04.141247 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 23:55:04.144572 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 23:55:04.148377 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:55:04.154810 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:55:04.158060 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:55:04.161398 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 23:55:04.168231 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:55:04.171085 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:55:04.174902 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:55:04.181665 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:55:04.184962 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8043 23:55:04.187620 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8044 23:55:04.194580 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 23:55:04.197705 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 23:55:04.201492 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 23:55:04.204843 Total UI for P1: 0, mck2ui 16
8048 23:55:04.207605 best dqsien dly found for B0: ( 1, 9, 10)
8049 23:55:04.214761 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 23:55:04.218241 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 23:55:04.221369 Total UI for P1: 0, mck2ui 16
8052 23:55:04.224139 best dqsien dly found for B1: ( 1, 9, 22)
8053 23:55:04.227687 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8054 23:55:04.230942 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8055 23:55:04.231008
8056 23:55:04.234577 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8057 23:55:04.238637 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8058 23:55:04.241044 [Gating] SW calibration Done
8059 23:55:04.241111 ==
8060 23:55:04.244578 Dram Type= 6, Freq= 0, CH_0, rank 1
8061 23:55:04.247842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 23:55:04.250892 ==
8063 23:55:04.250962 RX Vref Scan: 0
8064 23:55:04.251020
8065 23:55:04.254168 RX Vref 0 -> 0, step: 1
8066 23:55:04.254235
8067 23:55:04.254292 RX Delay 0 -> 252, step: 8
8068 23:55:04.261106 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8069 23:55:04.264333 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8070 23:55:04.267581 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8071 23:55:04.270827 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8072 23:55:04.274345 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8073 23:55:04.281304 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8074 23:55:04.284294 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8075 23:55:04.287920 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8076 23:55:04.291071 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8077 23:55:04.294148 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8078 23:55:04.301078 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8079 23:55:04.304190 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8080 23:55:04.307633 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8081 23:55:04.310544 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8082 23:55:04.314699 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8083 23:55:04.320649 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8084 23:55:04.320729 ==
8085 23:55:04.323988 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 23:55:04.327570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 23:55:04.327641 ==
8088 23:55:04.327702 DQS Delay:
8089 23:55:04.330751 DQS0 = 0, DQS1 = 0
8090 23:55:04.330818 DQM Delay:
8091 23:55:04.334372 DQM0 = 131, DQM1 = 123
8092 23:55:04.334440 DQ Delay:
8093 23:55:04.337678 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =131
8094 23:55:04.341101 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8095 23:55:04.344079 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8096 23:55:04.347724 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8097 23:55:04.347795
8098 23:55:04.347855
8099 23:55:04.351149 ==
8100 23:55:04.354319 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 23:55:04.357687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 23:55:04.357758 ==
8103 23:55:04.357824
8104 23:55:04.357882
8105 23:55:04.361299 TX Vref Scan disable
8106 23:55:04.361376 == TX Byte 0 ==
8107 23:55:04.363992 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8108 23:55:04.371428 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8109 23:55:04.371504 == TX Byte 1 ==
8110 23:55:04.374325 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8111 23:55:04.380927 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8112 23:55:04.381037 ==
8113 23:55:04.384656 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 23:55:04.387270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 23:55:04.387350 ==
8116 23:55:04.402770
8117 23:55:04.405535 TX Vref early break, caculate TX vref
8118 23:55:04.409072 TX Vref=16, minBit 1, minWin=22, winSum=368
8119 23:55:04.412673 TX Vref=18, minBit 0, minWin=23, winSum=383
8120 23:55:04.415973 TX Vref=20, minBit 1, minWin=23, winSum=389
8121 23:55:04.418859 TX Vref=22, minBit 1, minWin=24, winSum=392
8122 23:55:04.422708 TX Vref=24, minBit 1, minWin=24, winSum=401
8123 23:55:04.429206 TX Vref=26, minBit 0, minWin=25, winSum=415
8124 23:55:04.432889 TX Vref=28, minBit 1, minWin=25, winSum=418
8125 23:55:04.435745 TX Vref=30, minBit 1, minWin=25, winSum=415
8126 23:55:04.439210 TX Vref=32, minBit 0, minWin=25, winSum=412
8127 23:55:04.442520 TX Vref=34, minBit 4, minWin=24, winSum=403
8128 23:55:04.445735 TX Vref=36, minBit 7, minWin=23, winSum=393
8129 23:55:04.452994 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8130 23:55:04.453081
8131 23:55:04.456452 Final TX Range 0 Vref 28
8132 23:55:04.456527
8133 23:55:04.456586 ==
8134 23:55:04.459452 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 23:55:04.462962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 23:55:04.463039 ==
8137 23:55:04.463100
8138 23:55:04.463164
8139 23:55:04.466464 TX Vref Scan disable
8140 23:55:04.472234 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8141 23:55:04.472309 == TX Byte 0 ==
8142 23:55:04.475933 u2DelayCellOfst[0]=14 cells (4 PI)
8143 23:55:04.479063 u2DelayCellOfst[1]=21 cells (6 PI)
8144 23:55:04.482290 u2DelayCellOfst[2]=10 cells (3 PI)
8145 23:55:04.485492 u2DelayCellOfst[3]=10 cells (3 PI)
8146 23:55:04.488921 u2DelayCellOfst[4]=10 cells (3 PI)
8147 23:55:04.492719 u2DelayCellOfst[5]=0 cells (0 PI)
8148 23:55:04.495818 u2DelayCellOfst[6]=17 cells (5 PI)
8149 23:55:04.499172 u2DelayCellOfst[7]=17 cells (5 PI)
8150 23:55:04.501962 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8151 23:55:04.505579 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8152 23:55:04.508777 == TX Byte 1 ==
8153 23:55:04.512366 u2DelayCellOfst[8]=3 cells (1 PI)
8154 23:55:04.512435 u2DelayCellOfst[9]=0 cells (0 PI)
8155 23:55:04.515867 u2DelayCellOfst[10]=7 cells (2 PI)
8156 23:55:04.518852 u2DelayCellOfst[11]=0 cells (0 PI)
8157 23:55:04.521924 u2DelayCellOfst[12]=14 cells (4 PI)
8158 23:55:04.525662 u2DelayCellOfst[13]=10 cells (3 PI)
8159 23:55:04.529061 u2DelayCellOfst[14]=17 cells (5 PI)
8160 23:55:04.532272 u2DelayCellOfst[15]=10 cells (3 PI)
8161 23:55:04.535774 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8162 23:55:04.542155 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8163 23:55:04.542228 DramC Write-DBI on
8164 23:55:04.542290 ==
8165 23:55:04.545395 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 23:55:04.552090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 23:55:04.552163 ==
8168 23:55:04.552230
8169 23:55:04.552288
8170 23:55:04.552343 TX Vref Scan disable
8171 23:55:04.555634 == TX Byte 0 ==
8172 23:55:04.559092 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8173 23:55:04.562361 == TX Byte 1 ==
8174 23:55:04.566144 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8175 23:55:04.569240 DramC Write-DBI off
8176 23:55:04.569318
8177 23:55:04.569378 [DATLAT]
8178 23:55:04.569435 Freq=1600, CH0 RK1
8179 23:55:04.569490
8180 23:55:04.572800 DATLAT Default: 0xf
8181 23:55:04.572898 0, 0xFFFF, sum = 0
8182 23:55:04.575769 1, 0xFFFF, sum = 0
8183 23:55:04.575840 2, 0xFFFF, sum = 0
8184 23:55:04.579025 3, 0xFFFF, sum = 0
8185 23:55:04.582508 4, 0xFFFF, sum = 0
8186 23:55:04.582580 5, 0xFFFF, sum = 0
8187 23:55:04.586253 6, 0xFFFF, sum = 0
8188 23:55:04.586324 7, 0xFFFF, sum = 0
8189 23:55:04.589117 8, 0xFFFF, sum = 0
8190 23:55:04.589186 9, 0xFFFF, sum = 0
8191 23:55:04.592592 10, 0xFFFF, sum = 0
8192 23:55:04.592664 11, 0xFFFF, sum = 0
8193 23:55:04.596278 12, 0xFFFF, sum = 0
8194 23:55:04.596349 13, 0xFFFF, sum = 0
8195 23:55:04.599276 14, 0x0, sum = 1
8196 23:55:04.599342 15, 0x0, sum = 2
8197 23:55:04.602660 16, 0x0, sum = 3
8198 23:55:04.602731 17, 0x0, sum = 4
8199 23:55:04.605666 best_step = 15
8200 23:55:04.605734
8201 23:55:04.605792 ==
8202 23:55:04.609117 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 23:55:04.612603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 23:55:04.612679 ==
8205 23:55:04.612740 RX Vref Scan: 0
8206 23:55:04.615960
8207 23:55:04.616028 RX Vref 0 -> 0, step: 1
8208 23:55:04.616092
8209 23:55:04.619065 RX Delay 11 -> 252, step: 4
8210 23:55:04.622422 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8211 23:55:04.628892 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8212 23:55:04.632497 iDelay=195, Bit 2, Center 122 (67 ~ 178) 112
8213 23:55:04.635678 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8214 23:55:04.639299 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8215 23:55:04.642540 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8216 23:55:04.649082 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8217 23:55:04.652554 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8218 23:55:04.655682 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8219 23:55:04.659109 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8220 23:55:04.662840 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8221 23:55:04.669156 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8222 23:55:04.673456 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8223 23:55:04.675893 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8224 23:55:04.679799 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8225 23:55:04.682654 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8226 23:55:04.682737 ==
8227 23:55:04.685788 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 23:55:04.692422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 23:55:04.692505 ==
8230 23:55:04.692589 DQS Delay:
8231 23:55:04.695617 DQS0 = 0, DQS1 = 0
8232 23:55:04.695700 DQM Delay:
8233 23:55:04.699193 DQM0 = 127, DQM1 = 122
8234 23:55:04.699276 DQ Delay:
8235 23:55:04.702462 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8236 23:55:04.705762 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =136
8237 23:55:04.709032 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8238 23:55:04.712454 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8239 23:55:04.712536
8240 23:55:04.712627
8241 23:55:04.712705
8242 23:55:04.715510 [DramC_TX_OE_Calibration] TA2
8243 23:55:04.719246 Original DQ_B0 (3 6) =30, OEN = 27
8244 23:55:04.722319 Original DQ_B1 (3 6) =30, OEN = 27
8245 23:55:04.725794 24, 0x0, End_B0=24 End_B1=24
8246 23:55:04.725874 25, 0x0, End_B0=25 End_B1=25
8247 23:55:04.729520 26, 0x0, End_B0=26 End_B1=26
8248 23:55:04.732814 27, 0x0, End_B0=27 End_B1=27
8249 23:55:04.736080 28, 0x0, End_B0=28 End_B1=28
8250 23:55:04.739290 29, 0x0, End_B0=29 End_B1=29
8251 23:55:04.739374 30, 0x0, End_B0=30 End_B1=30
8252 23:55:04.742473 31, 0x4141, End_B0=30 End_B1=30
8253 23:55:04.746018 Byte0 end_step=30 best_step=27
8254 23:55:04.749311 Byte1 end_step=30 best_step=27
8255 23:55:04.752311 Byte0 TX OE(2T, 0.5T) = (3, 3)
8256 23:55:04.755865 Byte1 TX OE(2T, 0.5T) = (3, 3)
8257 23:55:04.755948
8258 23:55:04.756031
8259 23:55:04.762579 [DQSOSCAuto] RK1, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8260 23:55:04.765541 CH0 RK1: MR19=303, MR18=160C
8261 23:55:04.772829 CH0_RK1: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8262 23:55:04.775688 [RxdqsGatingPostProcess] freq 1600
8263 23:55:04.779711 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8264 23:55:04.782584 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 23:55:04.785385 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 23:55:04.789242 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 23:55:04.792374 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 23:55:04.795835 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 23:55:04.799011 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 23:55:04.802703 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 23:55:04.806140 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 23:55:04.808944 Pre-setting of DQS Precalculation
8273 23:55:04.812624 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8274 23:55:04.812706 ==
8275 23:55:04.815583 Dram Type= 6, Freq= 0, CH_1, rank 0
8276 23:55:04.819163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 23:55:04.819267 ==
8278 23:55:04.825458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8279 23:55:04.829360 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8280 23:55:04.835443 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8281 23:55:04.838741 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8282 23:55:04.848691 [CA 0] Center 42 (13~71) winsize 59
8283 23:55:04.852476 [CA 1] Center 42 (13~71) winsize 59
8284 23:55:04.855401 [CA 2] Center 37 (8~66) winsize 59
8285 23:55:04.859103 [CA 3] Center 36 (7~65) winsize 59
8286 23:55:04.862215 [CA 4] Center 37 (7~67) winsize 61
8287 23:55:04.865541 [CA 5] Center 36 (6~66) winsize 61
8288 23:55:04.865613
8289 23:55:04.868847 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8290 23:55:04.868921
8291 23:55:04.872298 [CATrainingPosCal] consider 1 rank data
8292 23:55:04.875702 u2DelayCellTimex100 = 275/100 ps
8293 23:55:04.879055 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8294 23:55:04.885875 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8295 23:55:04.889956 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8296 23:55:04.892334 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8297 23:55:04.895355 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8298 23:55:04.899088 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8299 23:55:04.899194
8300 23:55:04.902332 CA PerBit enable=1, Macro0, CA PI delay=36
8301 23:55:04.902402
8302 23:55:04.905967 [CBTSetCACLKResult] CA Dly = 36
8303 23:55:04.906038 CS Dly: 9 (0~40)
8304 23:55:04.912048 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8305 23:55:04.915969 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8306 23:55:04.916050 ==
8307 23:55:04.919552 Dram Type= 6, Freq= 0, CH_1, rank 1
8308 23:55:04.922359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 23:55:04.922459 ==
8310 23:55:04.929103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8311 23:55:04.932744 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8312 23:55:04.938852 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8313 23:55:04.942069 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8314 23:55:04.952011 [CA 0] Center 43 (14~72) winsize 59
8315 23:55:04.955184 [CA 1] Center 43 (14~72) winsize 59
8316 23:55:04.958510 [CA 2] Center 38 (9~67) winsize 59
8317 23:55:04.962366 [CA 3] Center 37 (8~67) winsize 60
8318 23:55:04.965330 [CA 4] Center 38 (9~68) winsize 60
8319 23:55:04.968430 [CA 5] Center 36 (7~66) winsize 60
8320 23:55:04.968498
8321 23:55:04.971861 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8322 23:55:04.971928
8323 23:55:04.975312 [CATrainingPosCal] consider 2 rank data
8324 23:55:04.978711 u2DelayCellTimex100 = 275/100 ps
8325 23:55:04.982040 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8326 23:55:04.988545 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8327 23:55:04.991647 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8328 23:55:04.995121 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8329 23:55:04.999326 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8330 23:55:05.002390 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8331 23:55:05.002461
8332 23:55:05.005480 CA PerBit enable=1, Macro0, CA PI delay=36
8333 23:55:05.005553
8334 23:55:05.008623 [CBTSetCACLKResult] CA Dly = 36
8335 23:55:05.012055 CS Dly: 11 (0~45)
8336 23:55:05.015416 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8337 23:55:05.018654 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8338 23:55:05.018724
8339 23:55:05.021736 ----->DramcWriteLeveling(PI) begin...
8340 23:55:05.021803 ==
8341 23:55:05.025410 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 23:55:05.028827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 23:55:05.031643 ==
8344 23:55:05.031718 Write leveling (Byte 0): 25 => 25
8345 23:55:05.035109 Write leveling (Byte 1): 26 => 26
8346 23:55:05.039038 DramcWriteLeveling(PI) end<-----
8347 23:55:05.039112
8348 23:55:05.039172 ==
8349 23:55:05.041630 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 23:55:05.048684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 23:55:05.048754 ==
8352 23:55:05.048821 [Gating] SW mode calibration
8353 23:55:05.058613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8354 23:55:05.061909 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8355 23:55:05.065388 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 23:55:05.071844 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 23:55:05.075189 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 23:55:05.078497 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 23:55:05.085382 1 4 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
8360 23:55:05.088954 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8361 23:55:05.091953 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 23:55:05.098717 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 23:55:05.101724 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 23:55:05.105197 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 23:55:05.111935 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 23:55:05.115030 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8367 23:55:05.119228 1 5 16 | B1->B0 | 3030 3333 | 1 1 | (1 0) (1 0)
8368 23:55:05.125340 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
8369 23:55:05.128906 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 23:55:05.132162 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 23:55:05.138695 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 23:55:05.142084 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:55:05.145019 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:55:05.148707 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 23:55:05.155234 1 6 16 | B1->B0 | 3939 3333 | 0 0 | (1 1) (0 0)
8376 23:55:05.158635 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 23:55:05.162123 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 23:55:05.168402 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 23:55:05.172375 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 23:55:05.175270 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 23:55:05.181980 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 23:55:05.185485 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8383 23:55:05.188741 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8384 23:55:05.195874 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8385 23:55:05.198798 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:55:05.202312 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:55:05.208448 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:55:05.212104 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:55:05.215278 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:55:05.222303 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:55:05.225586 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:55:05.228884 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:55:05.235613 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:55:05.239104 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:55:05.242297 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:55:05.245714 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:55:05.252545 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:55:05.255868 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8399 23:55:05.258840 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8400 23:55:05.265318 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8401 23:55:05.269199 Total UI for P1: 0, mck2ui 16
8402 23:55:05.272168 best dqsien dly found for B0: ( 1, 9, 14)
8403 23:55:05.275373 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 23:55:05.278944 Total UI for P1: 0, mck2ui 16
8405 23:55:05.282210 best dqsien dly found for B1: ( 1, 9, 18)
8406 23:55:05.285586 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8407 23:55:05.289093 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8408 23:55:05.289175
8409 23:55:05.292401 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8410 23:55:05.295367 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8411 23:55:05.298736 [Gating] SW calibration Done
8412 23:55:05.298816 ==
8413 23:55:05.302132 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 23:55:05.308744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 23:55:05.308826 ==
8416 23:55:05.308891 RX Vref Scan: 0
8417 23:55:05.308951
8418 23:55:05.312025 RX Vref 0 -> 0, step: 1
8419 23:55:05.312105
8420 23:55:05.312170 RX Delay 0 -> 252, step: 8
8421 23:55:05.319071 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8422 23:55:05.322482 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8423 23:55:05.325822 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8424 23:55:05.329162 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8425 23:55:05.332648 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8426 23:55:05.339334 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8427 23:55:05.342406 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8428 23:55:05.345573 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8429 23:55:05.349359 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8430 23:55:05.352402 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8431 23:55:05.358884 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8432 23:55:05.362103 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8433 23:55:05.365562 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8434 23:55:05.368861 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8435 23:55:05.371974 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8436 23:55:05.378910 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8437 23:55:05.378991 ==
8438 23:55:05.382463 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 23:55:05.385459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 23:55:05.385541 ==
8441 23:55:05.385605 DQS Delay:
8442 23:55:05.388913 DQS0 = 0, DQS1 = 0
8443 23:55:05.389019 DQM Delay:
8444 23:55:05.392271 DQM0 = 134, DQM1 = 127
8445 23:55:05.392351 DQ Delay:
8446 23:55:05.395458 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8447 23:55:05.398588 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8448 23:55:05.402030 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8449 23:55:05.405538 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8450 23:55:05.408750
8451 23:55:05.408831
8452 23:55:05.408895 ==
8453 23:55:05.412240 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 23:55:05.415442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 23:55:05.415524 ==
8456 23:55:05.415588
8457 23:55:05.415648
8458 23:55:05.418712 TX Vref Scan disable
8459 23:55:05.418792 == TX Byte 0 ==
8460 23:55:05.425209 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8461 23:55:05.429087 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8462 23:55:05.429168 == TX Byte 1 ==
8463 23:55:05.435191 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8464 23:55:05.438517 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8465 23:55:05.438615 ==
8466 23:55:05.442148 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 23:55:05.445130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 23:55:05.445227 ==
8469 23:55:05.458211
8470 23:55:05.462159 TX Vref early break, caculate TX vref
8471 23:55:05.465047 TX Vref=16, minBit 0, minWin=21, winSum=365
8472 23:55:05.468321 TX Vref=18, minBit 8, minWin=22, winSum=381
8473 23:55:05.471672 TX Vref=20, minBit 0, minWin=23, winSum=390
8474 23:55:05.475910 TX Vref=22, minBit 5, minWin=23, winSum=398
8475 23:55:05.478113 TX Vref=24, minBit 5, minWin=24, winSum=413
8476 23:55:05.485117 TX Vref=26, minBit 5, minWin=24, winSum=418
8477 23:55:05.488573 TX Vref=28, minBit 1, minWin=26, winSum=428
8478 23:55:05.491813 TX Vref=30, minBit 1, minWin=25, winSum=425
8479 23:55:05.494961 TX Vref=32, minBit 1, minWin=25, winSum=415
8480 23:55:05.498108 TX Vref=34, minBit 0, minWin=24, winSum=402
8481 23:55:05.504871 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
8482 23:55:05.504953
8483 23:55:05.508246 Final TX Range 0 Vref 28
8484 23:55:05.508327
8485 23:55:05.508392 ==
8486 23:55:05.511440 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 23:55:05.514837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 23:55:05.514919 ==
8489 23:55:05.514983
8490 23:55:05.515042
8491 23:55:05.518404 TX Vref Scan disable
8492 23:55:05.525272 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8493 23:55:05.525353 == TX Byte 0 ==
8494 23:55:05.528533 u2DelayCellOfst[0]=17 cells (5 PI)
8495 23:55:05.531688 u2DelayCellOfst[1]=10 cells (3 PI)
8496 23:55:05.535134 u2DelayCellOfst[2]=0 cells (0 PI)
8497 23:55:05.538248 u2DelayCellOfst[3]=7 cells (2 PI)
8498 23:55:05.541380 u2DelayCellOfst[4]=10 cells (3 PI)
8499 23:55:05.544791 u2DelayCellOfst[5]=21 cells (6 PI)
8500 23:55:05.548144 u2DelayCellOfst[6]=17 cells (5 PI)
8501 23:55:05.548224 u2DelayCellOfst[7]=7 cells (2 PI)
8502 23:55:05.555137 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8503 23:55:05.558539 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8504 23:55:05.558620 == TX Byte 1 ==
8505 23:55:05.561908 u2DelayCellOfst[8]=0 cells (0 PI)
8506 23:55:05.564706 u2DelayCellOfst[9]=3 cells (1 PI)
8507 23:55:05.568661 u2DelayCellOfst[10]=10 cells (3 PI)
8508 23:55:05.572062 u2DelayCellOfst[11]=7 cells (2 PI)
8509 23:55:05.575078 u2DelayCellOfst[12]=14 cells (4 PI)
8510 23:55:05.578119 u2DelayCellOfst[13]=17 cells (5 PI)
8511 23:55:05.581550 u2DelayCellOfst[14]=17 cells (5 PI)
8512 23:55:05.584913 u2DelayCellOfst[15]=14 cells (4 PI)
8513 23:55:05.588249 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8514 23:55:05.591676 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8515 23:55:05.594971 DramC Write-DBI on
8516 23:55:05.595052 ==
8517 23:55:05.597977 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 23:55:05.601501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 23:55:05.601583 ==
8520 23:55:05.601647
8521 23:55:05.604866
8522 23:55:05.604945 TX Vref Scan disable
8523 23:55:05.608143 == TX Byte 0 ==
8524 23:55:05.611449 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8525 23:55:05.615005 == TX Byte 1 ==
8526 23:55:05.618052 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8527 23:55:05.618133 DramC Write-DBI off
8528 23:55:05.618197
8529 23:55:05.621353 [DATLAT]
8530 23:55:05.621433 Freq=1600, CH1 RK0
8531 23:55:05.621498
8532 23:55:05.625140 DATLAT Default: 0xf
8533 23:55:05.625221 0, 0xFFFF, sum = 0
8534 23:55:05.628473 1, 0xFFFF, sum = 0
8535 23:55:05.628554 2, 0xFFFF, sum = 0
8536 23:55:05.631283 3, 0xFFFF, sum = 0
8537 23:55:05.631364 4, 0xFFFF, sum = 0
8538 23:55:05.634829 5, 0xFFFF, sum = 0
8539 23:55:05.634911 6, 0xFFFF, sum = 0
8540 23:55:05.638274 7, 0xFFFF, sum = 0
8541 23:55:05.641473 8, 0xFFFF, sum = 0
8542 23:55:05.641556 9, 0xFFFF, sum = 0
8543 23:55:05.644825 10, 0xFFFF, sum = 0
8544 23:55:05.644906 11, 0xFFFF, sum = 0
8545 23:55:05.648035 12, 0xFFFF, sum = 0
8546 23:55:05.648117 13, 0xFFFF, sum = 0
8547 23:55:05.651327 14, 0x0, sum = 1
8548 23:55:05.651409 15, 0x0, sum = 2
8549 23:55:05.654453 16, 0x0, sum = 3
8550 23:55:05.654535 17, 0x0, sum = 4
8551 23:55:05.654601 best_step = 15
8552 23:55:05.657997
8553 23:55:05.658077 ==
8554 23:55:05.661567 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 23:55:05.664746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 23:55:05.664828 ==
8557 23:55:05.664893 RX Vref Scan: 1
8558 23:55:05.664953
8559 23:55:05.668022 Set Vref Range= 24 -> 127
8560 23:55:05.668103
8561 23:55:05.671789 RX Vref 24 -> 127, step: 1
8562 23:55:05.671870
8563 23:55:05.674601 RX Delay 19 -> 252, step: 4
8564 23:55:05.674682
8565 23:55:05.678250 Set Vref, RX VrefLevel [Byte0]: 24
8566 23:55:05.681540 [Byte1]: 24
8567 23:55:05.681621
8568 23:55:05.684671 Set Vref, RX VrefLevel [Byte0]: 25
8569 23:55:05.688463 [Byte1]: 25
8570 23:55:05.688544
8571 23:55:05.691638 Set Vref, RX VrefLevel [Byte0]: 26
8572 23:55:05.694741 [Byte1]: 26
8573 23:55:05.697993
8574 23:55:05.698074 Set Vref, RX VrefLevel [Byte0]: 27
8575 23:55:05.701112 [Byte1]: 27
8576 23:55:05.706249
8577 23:55:05.706329 Set Vref, RX VrefLevel [Byte0]: 28
8578 23:55:05.709514 [Byte1]: 28
8579 23:55:05.713051
8580 23:55:05.713131 Set Vref, RX VrefLevel [Byte0]: 29
8581 23:55:05.716615 [Byte1]: 29
8582 23:55:05.721396
8583 23:55:05.721477 Set Vref, RX VrefLevel [Byte0]: 30
8584 23:55:05.724046 [Byte1]: 30
8585 23:55:05.728341
8586 23:55:05.728421 Set Vref, RX VrefLevel [Byte0]: 31
8587 23:55:05.731696 [Byte1]: 31
8588 23:55:05.735641
8589 23:55:05.735721 Set Vref, RX VrefLevel [Byte0]: 32
8590 23:55:05.739320 [Byte1]: 32
8591 23:55:05.743269
8592 23:55:05.743353 Set Vref, RX VrefLevel [Byte0]: 33
8593 23:55:05.746595 [Byte1]: 33
8594 23:55:05.751009
8595 23:55:05.751089 Set Vref, RX VrefLevel [Byte0]: 34
8596 23:55:05.754609 [Byte1]: 34
8597 23:55:05.758439
8598 23:55:05.758519 Set Vref, RX VrefLevel [Byte0]: 35
8599 23:55:05.761764 [Byte1]: 35
8600 23:55:05.766186
8601 23:55:05.766267 Set Vref, RX VrefLevel [Byte0]: 36
8602 23:55:05.769781 [Byte1]: 36
8603 23:55:05.774327
8604 23:55:05.774407 Set Vref, RX VrefLevel [Byte0]: 37
8605 23:55:05.777428 [Byte1]: 37
8606 23:55:05.781510
8607 23:55:05.781590 Set Vref, RX VrefLevel [Byte0]: 38
8608 23:55:05.785012 [Byte1]: 38
8609 23:55:05.789166
8610 23:55:05.789247 Set Vref, RX VrefLevel [Byte0]: 39
8611 23:55:05.792152 [Byte1]: 39
8612 23:55:05.796439
8613 23:55:05.796519 Set Vref, RX VrefLevel [Byte0]: 40
8614 23:55:05.799874 [Byte1]: 40
8615 23:55:05.804172
8616 23:55:05.804252 Set Vref, RX VrefLevel [Byte0]: 41
8617 23:55:05.807374 [Byte1]: 41
8618 23:55:05.811714
8619 23:55:05.811794 Set Vref, RX VrefLevel [Byte0]: 42
8620 23:55:05.814723 [Byte1]: 42
8621 23:55:05.819210
8622 23:55:05.819290 Set Vref, RX VrefLevel [Byte0]: 43
8623 23:55:05.822333 [Byte1]: 43
8624 23:55:05.826605
8625 23:55:05.826685 Set Vref, RX VrefLevel [Byte0]: 44
8626 23:55:05.830095 [Byte1]: 44
8627 23:55:05.834364
8628 23:55:05.834445 Set Vref, RX VrefLevel [Byte0]: 45
8629 23:55:05.837714 [Byte1]: 45
8630 23:55:05.842099
8631 23:55:05.842179 Set Vref, RX VrefLevel [Byte0]: 46
8632 23:55:05.845420 [Byte1]: 46
8633 23:55:05.849772
8634 23:55:05.849852 Set Vref, RX VrefLevel [Byte0]: 47
8635 23:55:05.852981 [Byte1]: 47
8636 23:55:05.857178
8637 23:55:05.857258 Set Vref, RX VrefLevel [Byte0]: 48
8638 23:55:05.860735 [Byte1]: 48
8639 23:55:05.864650
8640 23:55:05.864730 Set Vref, RX VrefLevel [Byte0]: 49
8641 23:55:05.867819 [Byte1]: 49
8642 23:55:05.872108
8643 23:55:05.872189 Set Vref, RX VrefLevel [Byte0]: 50
8644 23:55:05.875393 [Byte1]: 50
8645 23:55:05.879846
8646 23:55:05.879926 Set Vref, RX VrefLevel [Byte0]: 51
8647 23:55:05.883030 [Byte1]: 51
8648 23:55:05.887598
8649 23:55:05.887678 Set Vref, RX VrefLevel [Byte0]: 52
8650 23:55:05.890537 [Byte1]: 52
8651 23:55:05.895220
8652 23:55:05.895315 Set Vref, RX VrefLevel [Byte0]: 53
8653 23:55:05.898406 [Byte1]: 53
8654 23:55:05.902799
8655 23:55:05.902883 Set Vref, RX VrefLevel [Byte0]: 54
8656 23:55:05.905750 [Byte1]: 54
8657 23:55:05.910047
8658 23:55:05.910153 Set Vref, RX VrefLevel [Byte0]: 55
8659 23:55:05.913575 [Byte1]: 55
8660 23:55:05.917701
8661 23:55:05.917808 Set Vref, RX VrefLevel [Byte0]: 56
8662 23:55:05.920697 [Byte1]: 56
8663 23:55:05.925183
8664 23:55:05.925263 Set Vref, RX VrefLevel [Byte0]: 57
8665 23:55:05.928452 [Byte1]: 57
8666 23:55:05.932684
8667 23:55:05.932792 Set Vref, RX VrefLevel [Byte0]: 58
8668 23:55:05.936051 [Byte1]: 58
8669 23:55:05.940849
8670 23:55:05.940954 Set Vref, RX VrefLevel [Byte0]: 59
8671 23:55:05.943724 [Byte1]: 59
8672 23:55:05.948430
8673 23:55:05.948511 Set Vref, RX VrefLevel [Byte0]: 60
8674 23:55:05.951140 [Byte1]: 60
8675 23:55:05.955444
8676 23:55:05.955525 Set Vref, RX VrefLevel [Byte0]: 61
8677 23:55:05.958654 [Byte1]: 61
8678 23:55:05.963111
8679 23:55:05.963192 Set Vref, RX VrefLevel [Byte0]: 62
8680 23:55:05.966358 [Byte1]: 62
8681 23:55:05.970845
8682 23:55:05.970926 Set Vref, RX VrefLevel [Byte0]: 63
8683 23:55:05.974397 [Byte1]: 63
8684 23:55:05.977952
8685 23:55:05.978032 Set Vref, RX VrefLevel [Byte0]: 64
8686 23:55:05.981293 [Byte1]: 64
8687 23:55:05.985867
8688 23:55:05.985948 Set Vref, RX VrefLevel [Byte0]: 65
8689 23:55:05.989387 [Byte1]: 65
8690 23:55:05.993175
8691 23:55:05.993256 Set Vref, RX VrefLevel [Byte0]: 66
8692 23:55:05.996920 [Byte1]: 66
8693 23:55:06.001047
8694 23:55:06.001128 Set Vref, RX VrefLevel [Byte0]: 67
8695 23:55:06.004466 [Byte1]: 67
8696 23:55:06.008430
8697 23:55:06.008510 Set Vref, RX VrefLevel [Byte0]: 68
8698 23:55:06.012142 [Byte1]: 68
8699 23:55:06.015992
8700 23:55:06.016072 Set Vref, RX VrefLevel [Byte0]: 69
8701 23:55:06.019674 [Byte1]: 69
8702 23:55:06.023859
8703 23:55:06.023939 Set Vref, RX VrefLevel [Byte0]: 70
8704 23:55:06.027404 [Byte1]: 70
8705 23:55:06.031539
8706 23:55:06.031620 Set Vref, RX VrefLevel [Byte0]: 71
8707 23:55:06.034375 [Byte1]: 71
8708 23:55:06.038787
8709 23:55:06.038867 Set Vref, RX VrefLevel [Byte0]: 72
8710 23:55:06.042129 [Byte1]: 72
8711 23:55:06.046918
8712 23:55:06.046999 Set Vref, RX VrefLevel [Byte0]: 73
8713 23:55:06.049940 [Byte1]: 73
8714 23:55:06.054164
8715 23:55:06.054244 Set Vref, RX VrefLevel [Byte0]: 74
8716 23:55:06.057163 [Byte1]: 74
8717 23:55:06.061741
8718 23:55:06.061841 Set Vref, RX VrefLevel [Byte0]: 75
8719 23:55:06.065092 [Byte1]: 75
8720 23:55:06.068841
8721 23:55:06.068917 Set Vref, RX VrefLevel [Byte0]: 76
8722 23:55:06.072699 [Byte1]: 76
8723 23:55:06.076383
8724 23:55:06.076460 Set Vref, RX VrefLevel [Byte0]: 77
8725 23:55:06.079757 [Byte1]: 77
8726 23:55:06.084143
8727 23:55:06.084209 Final RX Vref Byte 0 = 58 to rank0
8728 23:55:06.087948 Final RX Vref Byte 1 = 55 to rank0
8729 23:55:06.090780 Final RX Vref Byte 0 = 58 to rank1
8730 23:55:06.094152 Final RX Vref Byte 1 = 55 to rank1==
8731 23:55:06.097635 Dram Type= 6, Freq= 0, CH_1, rank 0
8732 23:55:06.101067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 23:55:06.104051 ==
8734 23:55:06.104120 DQS Delay:
8735 23:55:06.104180 DQS0 = 0, DQS1 = 0
8736 23:55:06.107675 DQM Delay:
8737 23:55:06.107746 DQM0 = 131, DQM1 = 124
8738 23:55:06.111353 DQ Delay:
8739 23:55:06.114356 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8740 23:55:06.117505 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8741 23:55:06.121281 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8742 23:55:06.124510 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8743 23:55:06.124583
8744 23:55:06.124643
8745 23:55:06.124706
8746 23:55:06.127654 [DramC_TX_OE_Calibration] TA2
8747 23:55:06.130937 Original DQ_B0 (3 6) =30, OEN = 27
8748 23:55:06.134334 Original DQ_B1 (3 6) =30, OEN = 27
8749 23:55:06.134399 24, 0x0, End_B0=24 End_B1=24
8750 23:55:06.138079 25, 0x0, End_B0=25 End_B1=25
8751 23:55:06.141025 26, 0x0, End_B0=26 End_B1=26
8752 23:55:06.144537 27, 0x0, End_B0=27 End_B1=27
8753 23:55:06.147772 28, 0x0, End_B0=28 End_B1=28
8754 23:55:06.147841 29, 0x0, End_B0=29 End_B1=29
8755 23:55:06.151109 30, 0x0, End_B0=30 End_B1=30
8756 23:55:06.154503 31, 0x4141, End_B0=30 End_B1=30
8757 23:55:06.157794 Byte0 end_step=30 best_step=27
8758 23:55:06.161192 Byte1 end_step=30 best_step=27
8759 23:55:06.164731 Byte0 TX OE(2T, 0.5T) = (3, 3)
8760 23:55:06.164812 Byte1 TX OE(2T, 0.5T) = (3, 3)
8761 23:55:06.164876
8762 23:55:06.164936
8763 23:55:06.174360 [DQSOSCAuto] RK0, (LSB)MR18= 0x1400, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8764 23:55:06.177937 CH1 RK0: MR19=303, MR18=1400
8765 23:55:06.184129 CH1_RK0: MR19=0x303, MR18=0x1400, DQSOSC=399, MR23=63, INC=23, DEC=15
8766 23:55:06.184211
8767 23:55:06.187531 ----->DramcWriteLeveling(PI) begin...
8768 23:55:06.187613 ==
8769 23:55:06.190958 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 23:55:06.194883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 23:55:06.194964 ==
8772 23:55:06.198127 Write leveling (Byte 0): 28 => 28
8773 23:55:06.200862 Write leveling (Byte 1): 28 => 28
8774 23:55:06.204835 DramcWriteLeveling(PI) end<-----
8775 23:55:06.204916
8776 23:55:06.204985 ==
8777 23:55:06.207634 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 23:55:06.211131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 23:55:06.211212 ==
8780 23:55:06.214292 [Gating] SW mode calibration
8781 23:55:06.220908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8782 23:55:06.227821 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8783 23:55:06.231301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:55:06.234699 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:55:06.237748 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8786 23:55:06.244919 1 4 12 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
8787 23:55:06.248753 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 23:55:06.251410 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 23:55:06.258142 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 23:55:06.261276 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 23:55:06.264763 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 23:55:06.271353 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 23:55:06.274542 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8794 23:55:06.277938 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8795 23:55:06.284881 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:55:06.287793 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:55:06.291265 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 23:55:06.298599 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 23:55:06.301393 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 23:55:06.304600 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8801 23:55:06.311646 1 6 8 | B1->B0 | 2323 3838 | 1 0 | (0 0) (0 0)
8802 23:55:06.314616 1 6 12 | B1->B0 | 3636 4545 | 0 0 | (1 1) (0 0)
8803 23:55:06.317890 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 23:55:06.321468 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:55:06.328996 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 23:55:06.331360 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 23:55:06.335076 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 23:55:06.341707 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 23:55:06.345133 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8810 23:55:06.348090 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8811 23:55:06.354708 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8812 23:55:06.358058 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:55:06.361619 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:55:06.368062 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:55:06.371232 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:55:06.374396 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:55:06.381322 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:55:06.384883 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:55:06.388129 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:55:06.394514 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:55:06.398087 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:55:06.401344 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:55:06.407931 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:55:06.411666 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:55:06.414800 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8826 23:55:06.421137 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8827 23:55:06.421208 Total UI for P1: 0, mck2ui 16
8828 23:55:06.424670 best dqsien dly found for B0: ( 1, 9, 8)
8829 23:55:06.431562 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8830 23:55:06.434992 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 23:55:06.438390 Total UI for P1: 0, mck2ui 16
8832 23:55:06.441357 best dqsien dly found for B1: ( 1, 9, 14)
8833 23:55:06.444699 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8834 23:55:06.448164 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8835 23:55:06.448238
8836 23:55:06.451366 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8837 23:55:06.454949 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8838 23:55:06.457634 [Gating] SW calibration Done
8839 23:55:06.457702 ==
8840 23:55:06.460866 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 23:55:06.467617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 23:55:06.467700 ==
8843 23:55:06.467763 RX Vref Scan: 0
8844 23:55:06.467822
8845 23:55:06.471519 RX Vref 0 -> 0, step: 1
8846 23:55:06.471601
8847 23:55:06.474262 RX Delay 0 -> 252, step: 8
8848 23:55:06.477820 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8849 23:55:06.481021 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8850 23:55:06.484380 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8851 23:55:06.488068 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8852 23:55:06.494601 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8853 23:55:06.498059 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8854 23:55:06.501140 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8855 23:55:06.504433 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8856 23:55:06.507662 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8857 23:55:06.514581 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8858 23:55:06.518202 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8859 23:55:06.521723 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8860 23:55:06.524256 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8861 23:55:06.528005 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8862 23:55:06.534501 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8863 23:55:06.537787 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8864 23:55:06.537857 ==
8865 23:55:06.541281 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 23:55:06.544482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 23:55:06.544583 ==
8868 23:55:06.548117 DQS Delay:
8869 23:55:06.548188 DQS0 = 0, DQS1 = 0
8870 23:55:06.548277 DQM Delay:
8871 23:55:06.551164 DQM0 = 132, DQM1 = 127
8872 23:55:06.551256 DQ Delay:
8873 23:55:06.554726 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8874 23:55:06.557664 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8875 23:55:06.561135 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8876 23:55:06.567731 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8877 23:55:06.567816
8878 23:55:06.567880
8879 23:55:06.567940 ==
8880 23:55:06.571150 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 23:55:06.575214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 23:55:06.575295 ==
8883 23:55:06.575360
8884 23:55:06.575419
8885 23:55:06.578071 TX Vref Scan disable
8886 23:55:06.578151 == TX Byte 0 ==
8887 23:55:06.584452 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8888 23:55:06.587864 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8889 23:55:06.587944 == TX Byte 1 ==
8890 23:55:06.594663 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8891 23:55:06.598334 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8892 23:55:06.598415 ==
8893 23:55:06.601545 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 23:55:06.604783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 23:55:06.604864 ==
8896 23:55:06.619460
8897 23:55:06.622495 TX Vref early break, caculate TX vref
8898 23:55:06.625803 TX Vref=16, minBit 0, minWin=22, winSum=368
8899 23:55:06.628972 TX Vref=18, minBit 8, minWin=23, winSum=387
8900 23:55:06.632532 TX Vref=20, minBit 8, minWin=23, winSum=391
8901 23:55:06.636098 TX Vref=22, minBit 8, minWin=23, winSum=396
8902 23:55:06.639047 TX Vref=24, minBit 9, minWin=24, winSum=408
8903 23:55:06.645525 TX Vref=26, minBit 15, minWin=24, winSum=411
8904 23:55:06.649015 TX Vref=28, minBit 0, minWin=24, winSum=421
8905 23:55:06.652273 TX Vref=30, minBit 0, minWin=25, winSum=419
8906 23:55:06.655759 TX Vref=32, minBit 0, minWin=25, winSum=413
8907 23:55:06.659090 TX Vref=34, minBit 0, minWin=24, winSum=403
8908 23:55:06.662418 TX Vref=36, minBit 0, minWin=24, winSum=396
8909 23:55:06.669203 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 30
8910 23:55:06.669286
8911 23:55:06.672897 Final TX Range 0 Vref 30
8912 23:55:06.673000
8913 23:55:06.673080 ==
8914 23:55:06.675663 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 23:55:06.679348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 23:55:06.679429 ==
8917 23:55:06.679493
8918 23:55:06.679553
8919 23:55:06.682454 TX Vref Scan disable
8920 23:55:06.689190 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8921 23:55:06.689271 == TX Byte 0 ==
8922 23:55:06.692613 u2DelayCellOfst[0]=17 cells (5 PI)
8923 23:55:06.696195 u2DelayCellOfst[1]=10 cells (3 PI)
8924 23:55:06.699460 u2DelayCellOfst[2]=0 cells (0 PI)
8925 23:55:06.702517 u2DelayCellOfst[3]=7 cells (2 PI)
8926 23:55:06.705908 u2DelayCellOfst[4]=7 cells (2 PI)
8927 23:55:06.709480 u2DelayCellOfst[5]=21 cells (6 PI)
8928 23:55:06.712353 u2DelayCellOfst[6]=21 cells (6 PI)
8929 23:55:06.712434 u2DelayCellOfst[7]=7 cells (2 PI)
8930 23:55:06.719158 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8931 23:55:06.722572 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8932 23:55:06.722653 == TX Byte 1 ==
8933 23:55:06.725875 u2DelayCellOfst[8]=0 cells (0 PI)
8934 23:55:06.729266 u2DelayCellOfst[9]=3 cells (1 PI)
8935 23:55:06.733124 u2DelayCellOfst[10]=10 cells (3 PI)
8936 23:55:06.736022 u2DelayCellOfst[11]=7 cells (2 PI)
8937 23:55:06.739693 u2DelayCellOfst[12]=14 cells (4 PI)
8938 23:55:06.742527 u2DelayCellOfst[13]=14 cells (4 PI)
8939 23:55:06.745829 u2DelayCellOfst[14]=17 cells (5 PI)
8940 23:55:06.749153 u2DelayCellOfst[15]=17 cells (5 PI)
8941 23:55:06.752677 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8942 23:55:06.759312 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8943 23:55:06.759393 DramC Write-DBI on
8944 23:55:06.759457 ==
8945 23:55:06.762588 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 23:55:06.765972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 23:55:06.766053 ==
8948 23:55:06.769443
8949 23:55:06.769523
8950 23:55:06.769586 TX Vref Scan disable
8951 23:55:06.772568 == TX Byte 0 ==
8952 23:55:06.776290 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8953 23:55:06.779363 == TX Byte 1 ==
8954 23:55:06.782740 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8955 23:55:06.782824 DramC Write-DBI off
8956 23:55:06.785726
8957 23:55:06.785807 [DATLAT]
8958 23:55:06.785871 Freq=1600, CH1 RK1
8959 23:55:06.785931
8960 23:55:06.788943 DATLAT Default: 0xf
8961 23:55:06.789045 0, 0xFFFF, sum = 0
8962 23:55:06.792556 1, 0xFFFF, sum = 0
8963 23:55:06.792638 2, 0xFFFF, sum = 0
8964 23:55:06.795547 3, 0xFFFF, sum = 0
8965 23:55:06.795629 4, 0xFFFF, sum = 0
8966 23:55:06.799017 5, 0xFFFF, sum = 0
8967 23:55:06.802963 6, 0xFFFF, sum = 0
8968 23:55:06.803045 7, 0xFFFF, sum = 0
8969 23:55:06.805426 8, 0xFFFF, sum = 0
8970 23:55:06.805508 9, 0xFFFF, sum = 0
8971 23:55:06.808972 10, 0xFFFF, sum = 0
8972 23:55:06.809106 11, 0xFFFF, sum = 0
8973 23:55:06.812306 12, 0xFFFF, sum = 0
8974 23:55:06.812387 13, 0xFFFF, sum = 0
8975 23:55:06.815584 14, 0x0, sum = 1
8976 23:55:06.815666 15, 0x0, sum = 2
8977 23:55:06.819376 16, 0x0, sum = 3
8978 23:55:06.819458 17, 0x0, sum = 4
8979 23:55:06.822619 best_step = 15
8980 23:55:06.822700
8981 23:55:06.822763 ==
8982 23:55:06.825567 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 23:55:06.828889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 23:55:06.828971 ==
8985 23:55:06.829059 RX Vref Scan: 0
8986 23:55:06.829120
8987 23:55:06.832134 RX Vref 0 -> 0, step: 1
8988 23:55:06.832222
8989 23:55:06.835582 RX Delay 11 -> 252, step: 4
8990 23:55:06.838820 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8991 23:55:06.846535 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8992 23:55:06.849081 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8993 23:55:06.852234 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8994 23:55:06.855461 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8995 23:55:06.859271 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8996 23:55:06.862797 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8997 23:55:06.868792 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8998 23:55:06.872242 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8999 23:55:06.875451 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9000 23:55:06.879203 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9001 23:55:06.882144 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9002 23:55:06.889191 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9003 23:55:06.892697 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9004 23:55:06.895856 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9005 23:55:06.898787 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9006 23:55:06.898868 ==
9007 23:55:06.902576 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 23:55:06.909132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 23:55:06.909213 ==
9010 23:55:06.909277 DQS Delay:
9011 23:55:06.912088 DQS0 = 0, DQS1 = 0
9012 23:55:06.912169 DQM Delay:
9013 23:55:06.912232 DQM0 = 129, DQM1 = 126
9014 23:55:06.915568 DQ Delay:
9015 23:55:06.919161 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9016 23:55:06.922027 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =126
9017 23:55:06.925747 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9018 23:55:06.928997 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9019 23:55:06.929092
9020 23:55:06.929155
9021 23:55:06.929214
9022 23:55:06.932462 [DramC_TX_OE_Calibration] TA2
9023 23:55:06.935333 Original DQ_B0 (3 6) =30, OEN = 27
9024 23:55:06.939340 Original DQ_B1 (3 6) =30, OEN = 27
9025 23:55:06.942597 24, 0x0, End_B0=24 End_B1=24
9026 23:55:06.942679 25, 0x0, End_B0=25 End_B1=25
9027 23:55:06.945550 26, 0x0, End_B0=26 End_B1=26
9028 23:55:06.949265 27, 0x0, End_B0=27 End_B1=27
9029 23:55:06.952066 28, 0x0, End_B0=28 End_B1=28
9030 23:55:06.955504 29, 0x0, End_B0=29 End_B1=29
9031 23:55:06.955586 30, 0x0, End_B0=30 End_B1=30
9032 23:55:06.959204 31, 0x4141, End_B0=30 End_B1=30
9033 23:55:06.962347 Byte0 end_step=30 best_step=27
9034 23:55:06.965440 Byte1 end_step=30 best_step=27
9035 23:55:06.969097 Byte0 TX OE(2T, 0.5T) = (3, 3)
9036 23:55:06.972566 Byte1 TX OE(2T, 0.5T) = (3, 3)
9037 23:55:06.972646
9038 23:55:06.972709
9039 23:55:06.978828 [DQSOSCAuto] RK1, (LSB)MR18= 0xc12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9040 23:55:06.982481 CH1 RK1: MR19=303, MR18=C12
9041 23:55:06.988822 CH1_RK1: MR19=0x303, MR18=0xC12, DQSOSC=400, MR23=63, INC=23, DEC=15
9042 23:55:06.992863 [RxdqsGatingPostProcess] freq 1600
9043 23:55:06.995424 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9044 23:55:06.999160 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 23:55:07.002118 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 23:55:07.005926 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 23:55:07.009264 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 23:55:07.012151 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 23:55:07.016214 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 23:55:07.018967 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 23:55:07.022699 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 23:55:07.022779 Pre-setting of DQS Precalculation
9053 23:55:07.029153 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9054 23:55:07.035799 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9055 23:55:07.042347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9056 23:55:07.042428
9057 23:55:07.042491
9058 23:55:07.045788 [Calibration Summary] 3200 Mbps
9059 23:55:07.048719 CH 0, Rank 0
9060 23:55:07.048799 SW Impedance : PASS
9061 23:55:07.052315 DUTY Scan : NO K
9062 23:55:07.055434 ZQ Calibration : PASS
9063 23:55:07.055514 Jitter Meter : NO K
9064 23:55:07.058717 CBT Training : PASS
9065 23:55:07.058798 Write leveling : PASS
9066 23:55:07.062542 RX DQS gating : PASS
9067 23:55:07.065557 RX DQ/DQS(RDDQC) : PASS
9068 23:55:07.065637 TX DQ/DQS : PASS
9069 23:55:07.068984 RX DATLAT : PASS
9070 23:55:07.072116 RX DQ/DQS(Engine): PASS
9071 23:55:07.072196 TX OE : PASS
9072 23:55:07.075775 All Pass.
9073 23:55:07.075854
9074 23:55:07.075918 CH 0, Rank 1
9075 23:55:07.079018 SW Impedance : PASS
9076 23:55:07.079099 DUTY Scan : NO K
9077 23:55:07.082536 ZQ Calibration : PASS
9078 23:55:07.085602 Jitter Meter : NO K
9079 23:55:07.085682 CBT Training : PASS
9080 23:55:07.089546 Write leveling : PASS
9081 23:55:07.092104 RX DQS gating : PASS
9082 23:55:07.092184 RX DQ/DQS(RDDQC) : PASS
9083 23:55:07.095641 TX DQ/DQS : PASS
9084 23:55:07.099088 RX DATLAT : PASS
9085 23:55:07.099168 RX DQ/DQS(Engine): PASS
9086 23:55:07.102595 TX OE : PASS
9087 23:55:07.102675 All Pass.
9088 23:55:07.102739
9089 23:55:07.102798 CH 1, Rank 0
9090 23:55:07.105676 SW Impedance : PASS
9091 23:55:07.109169 DUTY Scan : NO K
9092 23:55:07.109249 ZQ Calibration : PASS
9093 23:55:07.112436 Jitter Meter : NO K
9094 23:55:07.115661 CBT Training : PASS
9095 23:55:07.115741 Write leveling : PASS
9096 23:55:07.118975 RX DQS gating : PASS
9097 23:55:07.122268 RX DQ/DQS(RDDQC) : PASS
9098 23:55:07.122347 TX DQ/DQS : PASS
9099 23:55:07.125699 RX DATLAT : PASS
9100 23:55:07.129003 RX DQ/DQS(Engine): PASS
9101 23:55:07.129097 TX OE : PASS
9102 23:55:07.132352 All Pass.
9103 23:55:07.132432
9104 23:55:07.132495 CH 1, Rank 1
9105 23:55:07.137088 SW Impedance : PASS
9106 23:55:07.137168 DUTY Scan : NO K
9107 23:55:07.139436 ZQ Calibration : PASS
9108 23:55:07.143442 Jitter Meter : NO K
9109 23:55:07.143523 CBT Training : PASS
9110 23:55:07.145609 Write leveling : PASS
9111 23:55:07.145689 RX DQS gating : PASS
9112 23:55:07.149063 RX DQ/DQS(RDDQC) : PASS
9113 23:55:07.152653 TX DQ/DQS : PASS
9114 23:55:07.152745 RX DATLAT : PASS
9115 23:55:07.155496 RX DQ/DQS(Engine): PASS
9116 23:55:07.159005 TX OE : PASS
9117 23:55:07.159087 All Pass.
9118 23:55:07.159151
9119 23:55:07.162305 DramC Write-DBI on
9120 23:55:07.162386 PER_BANK_REFRESH: Hybrid Mode
9121 23:55:07.165876 TX_TRACKING: ON
9122 23:55:07.172869 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9123 23:55:07.182188 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9124 23:55:07.189288 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9125 23:55:07.192382 [FAST_K] Save calibration result to emmc
9126 23:55:07.195262 sync common calibartion params.
9127 23:55:07.198966 sync cbt_mode0:1, 1:1
9128 23:55:07.199047 dram_init: ddr_geometry: 2
9129 23:55:07.202270 dram_init: ddr_geometry: 2
9130 23:55:07.205598 dram_init: ddr_geometry: 2
9131 23:55:07.208701 0:dram_rank_size:100000000
9132 23:55:07.208784 1:dram_rank_size:100000000
9133 23:55:07.215764 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9134 23:55:07.219056 DFS_SHUFFLE_HW_MODE: ON
9135 23:55:07.222365 dramc_set_vcore_voltage set vcore to 725000
9136 23:55:07.222446 Read voltage for 1600, 0
9137 23:55:07.225606 Vio18 = 0
9138 23:55:07.225686 Vcore = 725000
9139 23:55:07.225750 Vdram = 0
9140 23:55:07.228728 Vddq = 0
9141 23:55:07.228808 Vmddr = 0
9142 23:55:07.232105 switch to 3200 Mbps bootup
9143 23:55:07.232185 [DramcRunTimeConfig]
9144 23:55:07.232250 PHYPLL
9145 23:55:07.235337 DPM_CONTROL_AFTERK: ON
9146 23:55:07.238850 PER_BANK_REFRESH: ON
9147 23:55:07.238931 REFRESH_OVERHEAD_REDUCTION: ON
9148 23:55:07.241972 CMD_PICG_NEW_MODE: OFF
9149 23:55:07.245433 XRTWTW_NEW_MODE: ON
9150 23:55:07.245513 XRTRTR_NEW_MODE: ON
9151 23:55:07.248593 TX_TRACKING: ON
9152 23:55:07.248673 RDSEL_TRACKING: OFF
9153 23:55:07.252482 DQS Precalculation for DVFS: ON
9154 23:55:07.252562 RX_TRACKING: OFF
9155 23:55:07.255929 HW_GATING DBG: ON
9156 23:55:07.256010 ZQCS_ENABLE_LP4: ON
9157 23:55:07.258878 RX_PICG_NEW_MODE: ON
9158 23:55:07.262237 TX_PICG_NEW_MODE: ON
9159 23:55:07.262318 ENABLE_RX_DCM_DPHY: ON
9160 23:55:07.265543 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9161 23:55:07.268741 DUMMY_READ_FOR_TRACKING: OFF
9162 23:55:07.272225 !!! SPM_CONTROL_AFTERK: OFF
9163 23:55:07.275771 !!! SPM could not control APHY
9164 23:55:07.275852 IMPEDANCE_TRACKING: ON
9165 23:55:07.279275 TEMP_SENSOR: ON
9166 23:55:07.279356 HW_SAVE_FOR_SR: OFF
9167 23:55:07.282040 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9168 23:55:07.285343 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9169 23:55:07.288858 Read ODT Tracking: ON
9170 23:55:07.288938 Refresh Rate DeBounce: ON
9171 23:55:07.291983 DFS_NO_QUEUE_FLUSH: ON
9172 23:55:07.295713 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9173 23:55:07.298727 ENABLE_DFS_RUNTIME_MRW: OFF
9174 23:55:07.298808 DDR_RESERVE_NEW_MODE: ON
9175 23:55:07.302646 MR_CBT_SWITCH_FREQ: ON
9176 23:55:07.305575 =========================
9177 23:55:07.323426 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9178 23:55:07.326648 dram_init: ddr_geometry: 2
9179 23:55:07.345339 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9180 23:55:07.348561 dram_init: dram init end (result: 0)
9181 23:55:07.355570 DRAM-K: Full calibration passed in 24601 msecs
9182 23:55:07.358441 MRC: failed to locate region type 0.
9183 23:55:07.358529 DRAM rank0 size:0x100000000,
9184 23:55:07.361700 DRAM rank1 size=0x100000000
9185 23:55:07.371962 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9186 23:55:07.378775 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9187 23:55:07.384911 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9188 23:55:07.391699 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9189 23:55:07.395203 DRAM rank0 size:0x100000000,
9190 23:55:07.398213 DRAM rank1 size=0x100000000
9191 23:55:07.398294 CBMEM:
9192 23:55:07.401989 IMD: root @ 0xfffff000 254 entries.
9193 23:55:07.405666 IMD: root @ 0xffffec00 62 entries.
9194 23:55:07.408746 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9195 23:55:07.411806 WARNING: RO_VPD is uninitialized or empty.
9196 23:55:07.418603 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9197 23:55:07.425281 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9198 23:55:07.438016 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9199 23:55:07.448951 BS: romstage times (exec / console): total (unknown) / 24107 ms
9200 23:55:07.449071
9201 23:55:07.449135
9202 23:55:07.459582 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9203 23:55:07.462640 ARM64: Exception handlers installed.
9204 23:55:07.465782 ARM64: Testing exception
9205 23:55:07.469395 ARM64: Done test exception
9206 23:55:07.469477 Enumerating buses...
9207 23:55:07.472567 Show all devs... Before device enumeration.
9208 23:55:07.476309 Root Device: enabled 1
9209 23:55:07.478981 CPU_CLUSTER: 0: enabled 1
9210 23:55:07.479062 CPU: 00: enabled 1
9211 23:55:07.482618 Compare with tree...
9212 23:55:07.482698 Root Device: enabled 1
9213 23:55:07.485664 CPU_CLUSTER: 0: enabled 1
9214 23:55:07.489257 CPU: 00: enabled 1
9215 23:55:07.489340 Root Device scanning...
9216 23:55:07.493304 scan_static_bus for Root Device
9217 23:55:07.495821 CPU_CLUSTER: 0 enabled
9218 23:55:07.498931 scan_static_bus for Root Device done
9219 23:55:07.502768 scan_bus: bus Root Device finished in 8 msecs
9220 23:55:07.502849 done
9221 23:55:07.509271 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9222 23:55:07.512474 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9223 23:55:07.519131 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9224 23:55:07.522419 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9225 23:55:07.525845 Allocating resources...
9226 23:55:07.525926 Reading resources...
9227 23:55:07.532497 Root Device read_resources bus 0 link: 0
9228 23:55:07.532578 DRAM rank0 size:0x100000000,
9229 23:55:07.535662 DRAM rank1 size=0x100000000
9230 23:55:07.539427 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9231 23:55:07.542771 CPU: 00 missing read_resources
9232 23:55:07.545830 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9233 23:55:07.552478 Root Device read_resources bus 0 link: 0 done
9234 23:55:07.552559 Done reading resources.
9235 23:55:07.559128 Show resources in subtree (Root Device)...After reading.
9236 23:55:07.562483 Root Device child on link 0 CPU_CLUSTER: 0
9237 23:55:07.566206 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 23:55:07.575618 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 23:55:07.575701 CPU: 00
9240 23:55:07.579502 Root Device assign_resources, bus 0 link: 0
9241 23:55:07.582513 CPU_CLUSTER: 0 missing set_resources
9242 23:55:07.585734 Root Device assign_resources, bus 0 link: 0 done
9243 23:55:07.588926 Done setting resources.
9244 23:55:07.595401 Show resources in subtree (Root Device)...After assigning values.
9245 23:55:07.599508 Root Device child on link 0 CPU_CLUSTER: 0
9246 23:55:07.602350 CPU_CLUSTER: 0 child on link 0 CPU: 00
9247 23:55:07.612456 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9248 23:55:07.612538 CPU: 00
9249 23:55:07.615909 Done allocating resources.
9250 23:55:07.618964 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9251 23:55:07.622257 Enabling resources...
9252 23:55:07.622337 done.
9253 23:55:07.625929 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9254 23:55:07.629040 Initializing devices...
9255 23:55:07.632591 Root Device init
9256 23:55:07.632671 init hardware done!
9257 23:55:07.635905 0x00000018: ctrlr->caps
9258 23:55:07.639018 52.000 MHz: ctrlr->f_max
9259 23:55:07.639100 0.400 MHz: ctrlr->f_min
9260 23:55:07.642664 0x40ff8080: ctrlr->voltages
9261 23:55:07.642746 sclk: 390625
9262 23:55:07.645367 Bus Width = 1
9263 23:55:07.645447 sclk: 390625
9264 23:55:07.645511 Bus Width = 1
9265 23:55:07.649706 Early init status = 3
9266 23:55:07.655336 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9267 23:55:07.658509 in-header: 03 fc 00 00 01 00 00 00
9268 23:55:07.658589 in-data: 00
9269 23:55:07.665274 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9270 23:55:07.669079 in-header: 03 fd 00 00 00 00 00 00
9271 23:55:07.672340 in-data:
9272 23:55:07.676224 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9273 23:55:07.680353 in-header: 03 fc 00 00 01 00 00 00
9274 23:55:07.683093 in-data: 00
9275 23:55:07.686971 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9276 23:55:07.691985 in-header: 03 fd 00 00 00 00 00 00
9277 23:55:07.695664 in-data:
9278 23:55:07.698768 [SSUSB] Setting up USB HOST controller...
9279 23:55:07.702169 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9280 23:55:07.705264 [SSUSB] phy power-on done.
9281 23:55:07.708763 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9282 23:55:07.715843 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9283 23:55:07.719125 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9284 23:55:07.725875 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9285 23:55:07.732032 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9286 23:55:07.738869 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9287 23:55:07.745759 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9288 23:55:07.752314 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9289 23:55:07.752394 SPM: binary array size = 0x9dc
9290 23:55:07.759398 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9291 23:55:07.765622 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9292 23:55:07.772211 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9293 23:55:07.775642 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9294 23:55:07.779073 configure_display: Starting display init
9295 23:55:07.815455 anx7625_power_on_init: Init interface.
9296 23:55:07.818782 anx7625_disable_pd_protocol: Disabled PD feature.
9297 23:55:07.822559 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9298 23:55:07.849673 anx7625_start_dp_work: Secure OCM version=00
9299 23:55:07.853065 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9300 23:55:07.868400 sp_tx_get_edid_block: EDID Block = 1
9301 23:55:07.970507 Extracted contents:
9302 23:55:07.973740 header: 00 ff ff ff ff ff ff 00
9303 23:55:07.977478 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9304 23:55:07.980775 version: 01 04
9305 23:55:07.984045 basic params: 95 1f 11 78 0a
9306 23:55:07.987558 chroma info: 76 90 94 55 54 90 27 21 50 54
9307 23:55:07.990336 established: 00 00 00
9308 23:55:07.997411 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9309 23:55:08.000256 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9310 23:55:08.007385 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9311 23:55:08.014224 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9312 23:55:08.020266 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9313 23:55:08.023940 extensions: 00
9314 23:55:08.024077 checksum: fb
9315 23:55:08.024155
9316 23:55:08.027099 Manufacturer: IVO Model 57d Serial Number 0
9317 23:55:08.030452 Made week 0 of 2020
9318 23:55:08.030533 EDID version: 1.4
9319 23:55:08.033691 Digital display
9320 23:55:08.037282 6 bits per primary color channel
9321 23:55:08.037364 DisplayPort interface
9322 23:55:08.040137 Maximum image size: 31 cm x 17 cm
9323 23:55:08.043577 Gamma: 220%
9324 23:55:08.043657 Check DPMS levels
9325 23:55:08.047253 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9326 23:55:08.050310 First detailed timing is preferred timing
9327 23:55:08.053431 Established timings supported:
9328 23:55:08.056844 Standard timings supported:
9329 23:55:08.056950 Detailed timings
9330 23:55:08.063907 Hex of detail: 383680a07038204018303c0035ae10000019
9331 23:55:08.067129 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9332 23:55:08.070814 0780 0798 07c8 0820 hborder 0
9333 23:55:08.077131 0438 043b 0447 0458 vborder 0
9334 23:55:08.077211 -hsync -vsync
9335 23:55:08.080426 Did detailed timing
9336 23:55:08.084415 Hex of detail: 000000000000000000000000000000000000
9337 23:55:08.087381 Manufacturer-specified data, tag 0
9338 23:55:08.093854 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9339 23:55:08.093934 ASCII string: InfoVision
9340 23:55:08.100252 Hex of detail: 000000fe00523134304e574635205248200a
9341 23:55:08.100350 ASCII string: R140NWF5 RH
9342 23:55:08.103483 Checksum
9343 23:55:08.103563 Checksum: 0xfb (valid)
9344 23:55:08.110369 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9345 23:55:08.113529 DSI data_rate: 832800000 bps
9346 23:55:08.116957 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9347 23:55:08.120175 anx7625_parse_edid: pixelclock(138800).
9348 23:55:08.126822 hactive(1920), hsync(48), hfp(24), hbp(88)
9349 23:55:08.130130 vactive(1080), vsync(12), vfp(3), vbp(17)
9350 23:55:08.133955 anx7625_dsi_config: config dsi.
9351 23:55:08.140075 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9352 23:55:08.152557 anx7625_dsi_config: success to config DSI
9353 23:55:08.156380 anx7625_dp_start: MIPI phy setup OK.
9354 23:55:08.159537 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9355 23:55:08.162321 mtk_ddp_mode_set invalid vrefresh 60
9356 23:55:08.165714 main_disp_path_setup
9357 23:55:08.165794 ovl_layer_smi_id_en
9358 23:55:08.169149 ovl_layer_smi_id_en
9359 23:55:08.169229 ccorr_config
9360 23:55:08.169293 aal_config
9361 23:55:08.172650 gamma_config
9362 23:55:08.172730 postmask_config
9363 23:55:08.175852 dither_config
9364 23:55:08.179378 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9365 23:55:08.186242 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9366 23:55:08.189199 Root Device init finished in 554 msecs
9367 23:55:08.189306 CPU_CLUSTER: 0 init
9368 23:55:08.199458 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9369 23:55:08.202785 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9370 23:55:08.206050 APU_MBOX 0x190000b0 = 0x10001
9371 23:55:08.209250 APU_MBOX 0x190001b0 = 0x10001
9372 23:55:08.212678 APU_MBOX 0x190005b0 = 0x10001
9373 23:55:08.215968 APU_MBOX 0x190006b0 = 0x10001
9374 23:55:08.219475 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9375 23:55:08.231880 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9376 23:55:08.243836 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9377 23:55:08.250758 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9378 23:55:08.262437 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9379 23:55:08.271720 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9380 23:55:08.274773 CPU_CLUSTER: 0 init finished in 81 msecs
9381 23:55:08.277816 Devices initialized
9382 23:55:08.281812 Show all devs... After init.
9383 23:55:08.281893 Root Device: enabled 1
9384 23:55:08.285011 CPU_CLUSTER: 0: enabled 1
9385 23:55:08.288330 CPU: 00: enabled 1
9386 23:55:08.291476 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9387 23:55:08.294840 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9388 23:55:08.298379 ELOG: NV offset 0x57f000 size 0x1000
9389 23:55:08.304828 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9390 23:55:08.311286 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9391 23:55:08.315618 ELOG: Event(17) added with size 13 at 2024-05-29 23:55:08 UTC
9392 23:55:08.318182 out: cmd=0x121: 03 db 21 01 00 00 00 00
9393 23:55:08.322444 in-header: 03 ba 00 00 2c 00 00 00
9394 23:55:08.335523 in-data: a5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9395 23:55:08.342193 ELOG: Event(A1) added with size 10 at 2024-05-29 23:55:08 UTC
9396 23:55:08.348947 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9397 23:55:08.355960 ELOG: Event(A0) added with size 9 at 2024-05-29 23:55:08 UTC
9398 23:55:08.359417 elog_add_boot_reason: Logged dev mode boot
9399 23:55:08.362727 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9400 23:55:08.365387 Finalize devices...
9401 23:55:08.365468 Devices finalized
9402 23:55:08.372167 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9403 23:55:08.375927 Writing coreboot table at 0xffe64000
9404 23:55:08.379291 0. 000000000010a000-0000000000113fff: RAMSTAGE
9405 23:55:08.382168 1. 0000000040000000-00000000400fffff: RAM
9406 23:55:08.385863 2. 0000000040100000-000000004032afff: RAMSTAGE
9407 23:55:08.392379 3. 000000004032b000-00000000545fffff: RAM
9408 23:55:08.395730 4. 0000000054600000-000000005465ffff: BL31
9409 23:55:08.398932 5. 0000000054660000-00000000ffe63fff: RAM
9410 23:55:08.402300 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9411 23:55:08.408953 7. 0000000100000000-000000023fffffff: RAM
9412 23:55:08.409057 Passing 5 GPIOs to payload:
9413 23:55:08.415847 NAME | PORT | POLARITY | VALUE
9414 23:55:08.419008 EC in RW | 0x000000aa | low | undefined
9415 23:55:08.422524 EC interrupt | 0x00000005 | low | undefined
9416 23:55:08.429288 TPM interrupt | 0x000000ab | high | undefined
9417 23:55:08.432403 SD card detect | 0x00000011 | high | undefined
9418 23:55:08.439136 speaker enable | 0x00000093 | high | undefined
9419 23:55:08.442205 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9420 23:55:08.445740 in-header: 03 f9 00 00 02 00 00 00
9421 23:55:08.445821 in-data: 02 00
9422 23:55:08.448839 ADC[4]: Raw value=900221 ID=7
9423 23:55:08.452389 ADC[3]: Raw value=213336 ID=1
9424 23:55:08.452470 RAM Code: 0x71
9425 23:55:08.455604 ADC[6]: Raw value=74926 ID=0
9426 23:55:08.459073 ADC[5]: Raw value=212229 ID=1
9427 23:55:08.459156 SKU Code: 0x1
9428 23:55:08.465887 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a74a
9429 23:55:08.468922 coreboot table: 964 bytes.
9430 23:55:08.472708 IMD ROOT 0. 0xfffff000 0x00001000
9431 23:55:08.475938 IMD SMALL 1. 0xffffe000 0x00001000
9432 23:55:08.479095 RO MCACHE 2. 0xffffc000 0x00001104
9433 23:55:08.482304 CONSOLE 3. 0xfff7c000 0x00080000
9434 23:55:08.485993 FMAP 4. 0xfff7b000 0x00000452
9435 23:55:08.489385 TIME STAMP 5. 0xfff7a000 0x00000910
9436 23:55:08.492729 VBOOT WORK 6. 0xfff66000 0x00014000
9437 23:55:08.495635 RAMOOPS 7. 0xffe66000 0x00100000
9438 23:55:08.499381 COREBOOT 8. 0xffe64000 0x00002000
9439 23:55:08.499599 IMD small region:
9440 23:55:08.502045 IMD ROOT 0. 0xffffec00 0x00000400
9441 23:55:08.506025 VPD 1. 0xffffeb80 0x0000006c
9442 23:55:08.509348 MMC STATUS 2. 0xffffeb60 0x00000004
9443 23:55:08.515762 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9444 23:55:08.515864 Probing TPM: done!
9445 23:55:08.522966 Connected to device vid:did:rid of 1ae0:0028:00
9446 23:55:08.529658 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9447 23:55:08.533068 Initialized TPM device CR50 revision 0
9448 23:55:08.535987 Checking cr50 for pending updates
9449 23:55:08.541939 Reading cr50 TPM mode
9450 23:55:08.550124 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9451 23:55:08.557235 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9452 23:55:08.597187 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9453 23:55:08.600521 Checking segment from ROM address 0x40100000
9454 23:55:08.604171 Checking segment from ROM address 0x4010001c
9455 23:55:08.610723 Loading segment from ROM address 0x40100000
9456 23:55:08.610804 code (compression=0)
9457 23:55:08.617284 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9458 23:55:08.626976 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9459 23:55:08.627057 it's not compressed!
9460 23:55:08.633828 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9461 23:55:08.637134 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9462 23:55:08.657732 Loading segment from ROM address 0x4010001c
9463 23:55:08.657814 Entry Point 0x80000000
9464 23:55:08.660842 Loaded segments
9465 23:55:08.664440 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9466 23:55:08.671023 Jumping to boot code at 0x80000000(0xffe64000)
9467 23:55:08.677634 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9468 23:55:08.684375 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9469 23:55:08.692431 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9470 23:55:08.695266 Checking segment from ROM address 0x40100000
9471 23:55:08.698546 Checking segment from ROM address 0x4010001c
9472 23:55:08.705200 Loading segment from ROM address 0x40100000
9473 23:55:08.705282 code (compression=1)
9474 23:55:08.712217 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9475 23:55:08.722043 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9476 23:55:08.722124 using LZMA
9477 23:55:08.730344 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9478 23:55:08.737076 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9479 23:55:08.740193 Loading segment from ROM address 0x4010001c
9480 23:55:08.740273 Entry Point 0x54601000
9481 23:55:08.743404 Loaded segments
9482 23:55:08.746693 NOTICE: MT8192 bl31_setup
9483 23:55:08.754292 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9484 23:55:08.757430 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9485 23:55:08.760898 WARNING: region 0:
9486 23:55:08.763973 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 23:55:08.764054 WARNING: region 1:
9488 23:55:08.770581 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9489 23:55:08.774476 WARNING: region 2:
9490 23:55:08.777787 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9491 23:55:08.780860 WARNING: region 3:
9492 23:55:08.784817 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 23:55:08.787487 WARNING: region 4:
9494 23:55:08.791618 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 23:55:08.794496 WARNING: region 5:
9496 23:55:08.797570 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 23:55:08.800919 WARNING: region 6:
9498 23:55:08.804351 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 23:55:08.804431 WARNING: region 7:
9500 23:55:08.810845 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 23:55:08.817627 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9502 23:55:08.820842 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9503 23:55:08.824561 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9504 23:55:08.831191 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9505 23:55:08.834253 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9506 23:55:08.837833 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9507 23:55:08.844235 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9508 23:55:08.847699 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9509 23:55:08.851518 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9510 23:55:08.857998 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9511 23:55:08.861368 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9512 23:55:08.864431 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9513 23:55:08.871190 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9514 23:55:08.874823 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9515 23:55:08.881629 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9516 23:55:08.884502 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9517 23:55:08.888143 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9518 23:55:08.894629 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9519 23:55:08.898487 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9520 23:55:08.901711 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9521 23:55:08.908001 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9522 23:55:08.911384 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9523 23:55:08.918357 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9524 23:55:08.921775 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9525 23:55:08.924941 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9526 23:55:08.931423 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9527 23:55:08.935377 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9528 23:55:08.938598 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9529 23:55:08.944971 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9530 23:55:08.948368 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9531 23:55:08.955046 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9532 23:55:08.958461 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9533 23:55:08.962125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9534 23:55:08.965747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9535 23:55:08.971813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9536 23:55:08.974877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9537 23:55:08.978212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9538 23:55:08.981658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9539 23:55:08.988250 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9540 23:55:08.991769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9541 23:55:08.994892 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9542 23:55:08.998296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9543 23:55:09.004954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9544 23:55:09.008465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9545 23:55:09.011933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9546 23:55:09.015002 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9547 23:55:09.021718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9548 23:55:09.025126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9549 23:55:09.028638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9550 23:55:09.035266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9551 23:55:09.038703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9552 23:55:09.044986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9553 23:55:09.048796 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9554 23:55:09.052524 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9555 23:55:09.058729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9556 23:55:09.061934 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9557 23:55:09.068578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9558 23:55:09.071804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9559 23:55:09.079070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9560 23:55:09.082259 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9561 23:55:09.085502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9562 23:55:09.091994 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9563 23:55:09.095392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9564 23:55:09.102273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9565 23:55:09.105661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9566 23:55:09.112256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9567 23:55:09.115973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9568 23:55:09.118972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9569 23:55:09.125723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9570 23:55:09.128730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9571 23:55:09.135902 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9572 23:55:09.139598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9573 23:55:09.142605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9574 23:55:09.149069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9575 23:55:09.152336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9576 23:55:09.159408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9577 23:55:09.162935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9578 23:55:09.169589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9579 23:55:09.173128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9580 23:55:09.176272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9581 23:55:09.182995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9582 23:55:09.186003 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9583 23:55:09.192847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9584 23:55:09.196455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9585 23:55:09.202817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9586 23:55:09.206308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9587 23:55:09.209710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9588 23:55:09.216820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9589 23:55:09.219870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9590 23:55:09.226417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9591 23:55:09.229788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9592 23:55:09.233201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9593 23:55:09.239902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9594 23:55:09.243777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9595 23:55:09.250313 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9596 23:55:09.253284 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9597 23:55:09.256499 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9598 23:55:09.263572 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9599 23:55:09.267140 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9600 23:55:09.270147 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9601 23:55:09.273344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9602 23:55:09.280191 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9603 23:55:09.283617 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9604 23:55:09.290144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9605 23:55:09.293847 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9606 23:55:09.296963 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9607 23:55:09.303388 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9608 23:55:09.306915 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9609 23:55:09.313616 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9610 23:55:09.316773 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9611 23:55:09.320531 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9612 23:55:09.327797 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9613 23:55:09.330417 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9614 23:55:09.336827 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9615 23:55:09.340360 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9616 23:55:09.343550 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9617 23:55:09.347402 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9618 23:55:09.353783 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9619 23:55:09.357094 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9620 23:55:09.360245 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9621 23:55:09.367041 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9622 23:55:09.370378 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9623 23:55:09.373841 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9624 23:55:09.377354 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9625 23:55:09.383930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9626 23:55:09.387307 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9627 23:55:09.390508 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9628 23:55:09.397461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9629 23:55:09.400558 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9630 23:55:09.407854 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9631 23:55:09.411090 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9632 23:55:09.414232 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9633 23:55:09.420773 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9634 23:55:09.424119 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9635 23:55:09.427505 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9636 23:55:09.434467 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9637 23:55:09.438849 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9638 23:55:09.444181 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9639 23:55:09.447720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9640 23:55:09.450941 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9641 23:55:09.457921 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9642 23:55:09.461180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9643 23:55:09.464667 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9644 23:55:09.471186 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9645 23:55:09.474431 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9646 23:55:09.481249 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9647 23:55:09.484576 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9648 23:55:09.488175 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9649 23:55:09.495129 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9650 23:55:09.498295 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9651 23:55:09.501622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9652 23:55:09.508136 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9653 23:55:09.511607 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9654 23:55:09.518419 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9655 23:55:09.521684 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9656 23:55:09.525139 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9657 23:55:09.531903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9658 23:55:09.535316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9659 23:55:09.538788 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9660 23:55:09.545299 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9661 23:55:09.548700 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9662 23:55:09.555113 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9663 23:55:09.558430 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9664 23:55:09.561842 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9665 23:55:09.568190 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9666 23:55:09.571738 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9667 23:55:09.574970 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9668 23:55:09.582227 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9669 23:55:09.585022 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9670 23:55:09.591716 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9671 23:55:09.594712 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9672 23:55:09.598005 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9673 23:55:09.604752 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9674 23:55:09.608078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9675 23:55:09.615269 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9676 23:55:09.617995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9677 23:55:09.621843 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9678 23:55:09.628414 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9679 23:55:09.631684 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9680 23:55:09.635165 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9681 23:55:09.641654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9682 23:55:09.644989 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9683 23:55:09.651576 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9684 23:55:09.655192 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9685 23:55:09.658981 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9686 23:55:09.665100 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9687 23:55:09.668622 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9688 23:55:09.675886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9689 23:55:09.678862 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9690 23:55:09.682116 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9691 23:55:09.688713 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9692 23:55:09.691835 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9693 23:55:09.698488 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9694 23:55:09.701968 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9695 23:55:09.705127 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9696 23:55:09.712006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9697 23:55:09.715169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9698 23:55:09.721884 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9699 23:55:09.725341 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9700 23:55:09.731922 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9701 23:55:09.735518 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9702 23:55:09.738849 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9703 23:55:09.745343 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9704 23:55:09.748983 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9705 23:55:09.755466 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9706 23:55:09.758680 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9707 23:55:09.762030 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9708 23:55:09.768585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9709 23:55:09.772086 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9710 23:55:09.778419 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9711 23:55:09.781780 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9712 23:55:09.785833 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9713 23:55:09.792175 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9714 23:55:09.795317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9715 23:55:09.802221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9716 23:55:09.805731 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9717 23:55:09.808922 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9718 23:55:09.815240 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9719 23:55:09.819331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9720 23:55:09.825562 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9721 23:55:09.828752 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9722 23:55:09.832324 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9723 23:55:09.839070 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9724 23:55:09.842396 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9725 23:55:09.849143 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9726 23:55:09.852685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9727 23:55:09.855642 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9728 23:55:09.862464 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9729 23:55:09.865565 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9730 23:55:09.868935 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9731 23:55:09.875260 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9732 23:55:09.878901 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9733 23:55:09.882609 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9734 23:55:09.885935 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9735 23:55:09.892198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9736 23:55:09.895740 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9737 23:55:09.902125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9738 23:55:09.905267 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9739 23:55:09.908716 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9740 23:55:09.915454 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9741 23:55:09.918891 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9742 23:55:09.922286 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9743 23:55:09.928838 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9744 23:55:09.932573 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9745 23:55:09.935430 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9746 23:55:09.942000 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9747 23:55:09.946173 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9748 23:55:09.948993 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9749 23:55:09.955849 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9750 23:55:09.959373 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9751 23:55:09.962630 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9752 23:55:09.968795 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9753 23:55:09.972544 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9754 23:55:09.976016 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9755 23:55:09.982486 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9756 23:55:09.985745 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9757 23:55:09.992772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9758 23:55:09.996632 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9759 23:55:09.999169 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9760 23:55:10.005646 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9761 23:55:10.009282 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9762 23:55:10.013025 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9763 23:55:10.019142 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9764 23:55:10.022816 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9765 23:55:10.025762 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9766 23:55:10.033001 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9767 23:55:10.036297 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9768 23:55:10.042679 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9769 23:55:10.045982 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9770 23:55:10.048925 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9771 23:55:10.052160 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9772 23:55:10.055991 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9773 23:55:10.062550 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9774 23:55:10.065780 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9775 23:55:10.069149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9776 23:55:10.072479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9777 23:55:10.079521 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9778 23:55:10.082632 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9779 23:55:10.085971 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9780 23:55:10.088977 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9781 23:55:10.095659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9782 23:55:10.099094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9783 23:55:10.102143 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9784 23:55:10.109201 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9785 23:55:10.112563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9786 23:55:10.118748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9787 23:55:10.122524 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9788 23:55:10.129424 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9789 23:55:10.132421 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9790 23:55:10.135519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9791 23:55:10.142270 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9792 23:55:10.145530 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9793 23:55:10.152012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9794 23:55:10.155762 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9795 23:55:10.159026 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9796 23:55:10.165439 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9797 23:55:10.168795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9798 23:55:10.172191 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9799 23:55:10.178851 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9800 23:55:10.182656 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9801 23:55:10.189124 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9802 23:55:10.192338 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9803 23:55:10.198735 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9804 23:55:10.202091 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9805 23:55:10.205472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9806 23:55:10.212533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9807 23:55:10.215681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9808 23:55:10.222471 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9809 23:55:10.225540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9810 23:55:10.229016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9811 23:55:10.235661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9812 23:55:10.239535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9813 23:55:10.246011 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9814 23:55:10.249370 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9815 23:55:10.252762 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9816 23:55:10.259185 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9817 23:55:10.262367 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9818 23:55:10.269169 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9819 23:55:10.273224 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9820 23:55:10.275640 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9821 23:55:10.282467 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9822 23:55:10.286201 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9823 23:55:10.289314 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9824 23:55:10.295860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9825 23:55:10.299000 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9826 23:55:10.305741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9827 23:55:10.308936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9828 23:55:10.316022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9829 23:55:10.319369 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9830 23:55:10.322754 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9831 23:55:10.329330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9832 23:55:10.332334 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9833 23:55:10.339306 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9834 23:55:10.342562 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9835 23:55:10.345461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9836 23:55:10.352412 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9837 23:55:10.355675 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9838 23:55:10.362711 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9839 23:55:10.365827 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9840 23:55:10.369264 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9841 23:55:10.375743 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9842 23:55:10.379240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9843 23:55:10.385813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9844 23:55:10.389026 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9845 23:55:10.392457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9846 23:55:10.399066 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9847 23:55:10.402427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9848 23:55:10.409191 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9849 23:55:10.412676 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9850 23:55:10.415956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9851 23:55:10.423052 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9852 23:55:10.425931 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9853 23:55:10.432838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9854 23:55:10.435711 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9855 23:55:10.439247 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9856 23:55:10.445893 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9857 23:55:10.449225 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9858 23:55:10.455691 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9859 23:55:10.459434 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9860 23:55:10.465770 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9861 23:55:10.469560 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9862 23:55:10.472526 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9863 23:55:10.479494 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9864 23:55:10.482537 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9865 23:55:10.489365 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9866 23:55:10.492409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9867 23:55:10.499325 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9868 23:55:10.502643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9869 23:55:10.505956 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9870 23:55:10.512731 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9871 23:55:10.515703 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9872 23:55:10.522397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9873 23:55:10.526187 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9874 23:55:10.532550 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9875 23:55:10.535825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9876 23:55:10.539152 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9877 23:55:10.546143 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9878 23:55:10.549298 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9879 23:55:10.555944 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9880 23:55:10.559115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9881 23:55:10.566563 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9882 23:55:10.569691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9883 23:55:10.572921 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9884 23:55:10.579111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9885 23:55:10.582816 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9886 23:55:10.589603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9887 23:55:10.592536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9888 23:55:10.596137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9889 23:55:10.603346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9890 23:55:10.605910 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9891 23:55:10.612542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9892 23:55:10.616059 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9893 23:55:10.622852 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9894 23:55:10.626251 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9895 23:55:10.629438 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9896 23:55:10.635816 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9897 23:55:10.639771 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9898 23:55:10.646023 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9899 23:55:10.649242 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9900 23:55:10.656309 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9901 23:55:10.659597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9902 23:55:10.662954 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9903 23:55:10.669431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9904 23:55:10.672622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9905 23:55:10.679475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9906 23:55:10.682820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9907 23:55:10.689608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9908 23:55:10.692658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9909 23:55:10.699336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9910 23:55:10.703089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9911 23:55:10.706292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9912 23:55:10.713133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9913 23:55:10.716429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9914 23:55:10.722708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9915 23:55:10.726571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9916 23:55:10.733227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9917 23:55:10.736577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9918 23:55:10.742708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9919 23:55:10.746560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9920 23:55:10.752849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9921 23:55:10.756488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9922 23:55:10.762756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9923 23:55:10.766374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9924 23:55:10.773048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9925 23:55:10.776169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9926 23:55:10.782824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9927 23:55:10.785931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9928 23:55:10.792723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9929 23:55:10.795996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9930 23:55:10.802775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9931 23:55:10.806251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9932 23:55:10.812845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9933 23:55:10.816030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9934 23:55:10.822423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9935 23:55:10.826079 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9936 23:55:10.829259 INFO: [APUAPC] vio 0
9937 23:55:10.832581 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9938 23:55:10.836102 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9939 23:55:10.839497 INFO: [APUAPC] D0_APC_0: 0x400510
9940 23:55:10.842418 INFO: [APUAPC] D0_APC_1: 0x0
9941 23:55:10.845952 INFO: [APUAPC] D0_APC_2: 0x1540
9942 23:55:10.849377 INFO: [APUAPC] D0_APC_3: 0x0
9943 23:55:10.852555 INFO: [APUAPC] D1_APC_0: 0xffffffff
9944 23:55:10.855921 INFO: [APUAPC] D1_APC_1: 0xffffffff
9945 23:55:10.859211 INFO: [APUAPC] D1_APC_2: 0x3fffff
9946 23:55:10.862594 INFO: [APUAPC] D1_APC_3: 0x0
9947 23:55:10.865772 INFO: [APUAPC] D2_APC_0: 0xffffffff
9948 23:55:10.869683 INFO: [APUAPC] D2_APC_1: 0xffffffff
9949 23:55:10.872490 INFO: [APUAPC] D2_APC_2: 0x3fffff
9950 23:55:10.876568 INFO: [APUAPC] D2_APC_3: 0x0
9951 23:55:10.879667 INFO: [APUAPC] D3_APC_0: 0xffffffff
9952 23:55:10.883007 INFO: [APUAPC] D3_APC_1: 0xffffffff
9953 23:55:10.886067 INFO: [APUAPC] D3_APC_2: 0x3fffff
9954 23:55:10.889533 INFO: [APUAPC] D3_APC_3: 0x0
9955 23:55:10.893176 INFO: [APUAPC] D4_APC_0: 0xffffffff
9956 23:55:10.896107 INFO: [APUAPC] D4_APC_1: 0xffffffff
9957 23:55:10.899235 INFO: [APUAPC] D4_APC_2: 0x3fffff
9958 23:55:10.902951 INFO: [APUAPC] D4_APC_3: 0x0
9959 23:55:10.906190 INFO: [APUAPC] D5_APC_0: 0xffffffff
9960 23:55:10.909442 INFO: [APUAPC] D5_APC_1: 0xffffffff
9961 23:55:10.912567 INFO: [APUAPC] D5_APC_2: 0x3fffff
9962 23:55:10.915931 INFO: [APUAPC] D5_APC_3: 0x0
9963 23:55:10.919250 INFO: [APUAPC] D6_APC_0: 0xffffffff
9964 23:55:10.922700 INFO: [APUAPC] D6_APC_1: 0xffffffff
9965 23:55:10.926215 INFO: [APUAPC] D6_APC_2: 0x3fffff
9966 23:55:10.926296 INFO: [APUAPC] D6_APC_3: 0x0
9967 23:55:10.932762 INFO: [APUAPC] D7_APC_0: 0xffffffff
9968 23:55:10.936062 INFO: [APUAPC] D7_APC_1: 0xffffffff
9969 23:55:10.936148 INFO: [APUAPC] D7_APC_2: 0x3fffff
9970 23:55:10.939432 INFO: [APUAPC] D7_APC_3: 0x0
9971 23:55:10.943134 INFO: [APUAPC] D8_APC_0: 0xffffffff
9972 23:55:10.946210 INFO: [APUAPC] D8_APC_1: 0xffffffff
9973 23:55:10.949270 INFO: [APUAPC] D8_APC_2: 0x3fffff
9974 23:55:10.952894 INFO: [APUAPC] D8_APC_3: 0x0
9975 23:55:10.956153 INFO: [APUAPC] D9_APC_0: 0xffffffff
9976 23:55:10.959770 INFO: [APUAPC] D9_APC_1: 0xffffffff
9977 23:55:10.962635 INFO: [APUAPC] D9_APC_2: 0x3fffff
9978 23:55:10.966511 INFO: [APUAPC] D9_APC_3: 0x0
9979 23:55:10.969344 INFO: [APUAPC] D10_APC_0: 0xffffffff
9980 23:55:10.972788 INFO: [APUAPC] D10_APC_1: 0xffffffff
9981 23:55:10.976327 INFO: [APUAPC] D10_APC_2: 0x3fffff
9982 23:55:10.979812 INFO: [APUAPC] D10_APC_3: 0x0
9983 23:55:10.982844 INFO: [APUAPC] D11_APC_0: 0xffffffff
9984 23:55:10.986146 INFO: [APUAPC] D11_APC_1: 0xffffffff
9985 23:55:10.989843 INFO: [APUAPC] D11_APC_2: 0x3fffff
9986 23:55:10.993476 INFO: [APUAPC] D11_APC_3: 0x0
9987 23:55:10.996383 INFO: [APUAPC] D12_APC_0: 0xffffffff
9988 23:55:10.999703 INFO: [APUAPC] D12_APC_1: 0xffffffff
9989 23:55:11.003035 INFO: [APUAPC] D12_APC_2: 0x3fffff
9990 23:55:11.006704 INFO: [APUAPC] D12_APC_3: 0x0
9991 23:55:11.009867 INFO: [APUAPC] D13_APC_0: 0xffffffff
9992 23:55:11.013257 INFO: [APUAPC] D13_APC_1: 0xffffffff
9993 23:55:11.016391 INFO: [APUAPC] D13_APC_2: 0x3fffff
9994 23:55:11.019422 INFO: [APUAPC] D13_APC_3: 0x0
9995 23:55:11.023107 INFO: [APUAPC] D14_APC_0: 0xffffffff
9996 23:55:11.026005 INFO: [APUAPC] D14_APC_1: 0xffffffff
9997 23:55:11.029619 INFO: [APUAPC] D14_APC_2: 0x3fffff
9998 23:55:11.032834 INFO: [APUAPC] D14_APC_3: 0x0
9999 23:55:11.036498 INFO: [APUAPC] D15_APC_0: 0xffffffff
10000 23:55:11.039256 INFO: [APUAPC] D15_APC_1: 0xffffffff
10001 23:55:11.043122 INFO: [APUAPC] D15_APC_2: 0x3fffff
10002 23:55:11.046167 INFO: [APUAPC] D15_APC_3: 0x0
10003 23:55:11.049733 INFO: [APUAPC] APC_CON: 0x4
10004 23:55:11.052692 INFO: [NOCDAPC] D0_APC_0: 0x0
10005 23:55:11.056482 INFO: [NOCDAPC] D0_APC_1: 0x0
10006 23:55:11.059307 INFO: [NOCDAPC] D1_APC_0: 0x0
10007 23:55:11.062547 INFO: [NOCDAPC] D1_APC_1: 0xfff
10008 23:55:11.062627 INFO: [NOCDAPC] D2_APC_0: 0x0
10009 23:55:11.066202 INFO: [NOCDAPC] D2_APC_1: 0xfff
10010 23:55:11.069474 INFO: [NOCDAPC] D3_APC_0: 0x0
10011 23:55:11.072926 INFO: [NOCDAPC] D3_APC_1: 0xfff
10012 23:55:11.075943 INFO: [NOCDAPC] D4_APC_0: 0x0
10013 23:55:11.079792 INFO: [NOCDAPC] D4_APC_1: 0xfff
10014 23:55:11.082928 INFO: [NOCDAPC] D5_APC_0: 0x0
10015 23:55:11.086016 INFO: [NOCDAPC] D5_APC_1: 0xfff
10016 23:55:11.089313 INFO: [NOCDAPC] D6_APC_0: 0x0
10017 23:55:11.092943 INFO: [NOCDAPC] D6_APC_1: 0xfff
10018 23:55:11.096178 INFO: [NOCDAPC] D7_APC_0: 0x0
10019 23:55:11.096259 INFO: [NOCDAPC] D7_APC_1: 0xfff
10020 23:55:11.099690 INFO: [NOCDAPC] D8_APC_0: 0x0
10021 23:55:11.103014 INFO: [NOCDAPC] D8_APC_1: 0xfff
10022 23:55:11.106365 INFO: [NOCDAPC] D9_APC_0: 0x0
10023 23:55:11.109431 INFO: [NOCDAPC] D9_APC_1: 0xfff
10024 23:55:11.112785 INFO: [NOCDAPC] D10_APC_0: 0x0
10025 23:55:11.116009 INFO: [NOCDAPC] D10_APC_1: 0xfff
10026 23:55:11.119561 INFO: [NOCDAPC] D11_APC_0: 0x0
10027 23:55:11.122915 INFO: [NOCDAPC] D11_APC_1: 0xfff
10028 23:55:11.126750 INFO: [NOCDAPC] D12_APC_0: 0x0
10029 23:55:11.129749 INFO: [NOCDAPC] D12_APC_1: 0xfff
10030 23:55:11.132881 INFO: [NOCDAPC] D13_APC_0: 0x0
10031 23:55:11.132992 INFO: [NOCDAPC] D13_APC_1: 0xfff
10032 23:55:11.136285 INFO: [NOCDAPC] D14_APC_0: 0x0
10033 23:55:11.139777 INFO: [NOCDAPC] D14_APC_1: 0xfff
10034 23:55:11.143429 INFO: [NOCDAPC] D15_APC_0: 0x0
10035 23:55:11.146582 INFO: [NOCDAPC] D15_APC_1: 0xfff
10036 23:55:11.149526 INFO: [NOCDAPC] APC_CON: 0x4
10037 23:55:11.153266 INFO: [APUAPC] set_apusys_apc done
10038 23:55:11.156324 INFO: [DEVAPC] devapc_init done
10039 23:55:11.159884 INFO: GICv3 without legacy support detected.
10040 23:55:11.162858 INFO: ARM GICv3 driver initialized in EL3
10041 23:55:11.169376 INFO: Maximum SPI INTID supported: 639
10042 23:55:11.173200 INFO: BL31: Initializing runtime services
10043 23:55:11.179899 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10044 23:55:11.179980 INFO: SPM: enable CPC mode
10045 23:55:11.185876 INFO: mcdi ready for mcusys-off-idle and system suspend
10046 23:55:11.189697 INFO: BL31: Preparing for EL3 exit to normal world
10047 23:55:11.192728 INFO: Entry point address = 0x80000000
10048 23:55:11.196132 INFO: SPSR = 0x8
10049 23:55:11.201943
10050 23:55:11.202022
10051 23:55:11.202086
10052 23:55:11.205426 Starting depthcharge on Spherion...
10053 23:55:11.205506
10054 23:55:11.205569 Wipe memory regions:
10055 23:55:11.205628
10056 23:55:11.206297 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10057 23:55:11.206398 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10058 23:55:11.206481 Setting prompt string to ['asurada:']
10059 23:55:11.206558 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10060 23:55:11.208795 [0x00000040000000, 0x00000054600000)
10061 23:55:11.330895
10062 23:55:11.330999 [0x00000054660000, 0x00000080000000)
10063 23:55:11.591510
10064 23:55:11.591642 [0x000000821a7280, 0x000000ffe64000)
10065 23:55:12.336347
10066 23:55:12.336518 [0x00000100000000, 0x00000240000000)
10067 23:55:14.226150
10068 23:55:14.229863 Initializing XHCI USB controller at 0x11200000.
10069 23:55:15.267418
10070 23:55:15.270296 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10071 23:55:15.270403
10072 23:55:15.270502
10073 23:55:15.270813 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 23:55:15.371201 asurada: tftpboot 192.168.201.1 14084372/tftp-deploy-pcqix4nj/kernel/image.itb 14084372/tftp-deploy-pcqix4nj/kernel/cmdline
10076 23:55:15.371342 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 23:55:15.371458 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10078 23:55:15.375343 tftpboot 192.168.201.1 14084372/tftp-deploy-pcqix4nj/kernel/image.ittp-deploy-pcqix4nj/kernel/cmdline
10079 23:55:15.375455
10080 23:55:15.375547 Waiting for link
10081 23:55:15.535838
10082 23:55:15.535955 R8152: Initializing
10083 23:55:15.536023
10084 23:55:15.539722 Version 6 (ocp_data = 5c30)
10085 23:55:15.539798
10086 23:55:15.542713 R8152: Done initializing
10087 23:55:15.542794
10088 23:55:15.542858 Adding net device
10089 23:55:17.508758
10090 23:55:17.509268 done.
10091 23:55:17.509603
10092 23:55:17.509931 MAC: 00:24:32:30:78:52
10093 23:55:17.510235
10094 23:55:17.512454 Sending DHCP discover... done.
10095 23:55:17.512866
10096 23:55:17.515791 Waiting for reply... done.
10097 23:55:17.516254
10098 23:55:17.519188 Sending DHCP request... done.
10099 23:55:17.519600
10100 23:55:17.519927 Waiting for reply... done.
10101 23:55:17.520429
10102 23:55:17.521912 My ip is 192.168.201.14
10103 23:55:17.522322
10104 23:55:17.525399 The DHCP server ip is 192.168.201.1
10105 23:55:17.525811
10106 23:55:17.528750 TFTP server IP predefined by user: 192.168.201.1
10107 23:55:17.529251
10108 23:55:17.535773 Bootfile predefined by user: 14084372/tftp-deploy-pcqix4nj/kernel/image.itb
10109 23:55:17.536280
10110 23:55:17.538822 Sending tftp read request... done.
10111 23:55:17.539238
10112 23:55:17.547820 Waiting for the transfer...
10113 23:55:17.548237
10114 23:55:18.081487 00000000 ################################################################
10115 23:55:18.081628
10116 23:55:18.626116 00080000 ################################################################
10117 23:55:18.626255
10118 23:55:19.145784 00100000 ################################################################
10119 23:55:19.145920
10120 23:55:19.668449 00180000 ################################################################
10121 23:55:19.668583
10122 23:55:20.217076 00200000 ################################################################
10123 23:55:20.217211
10124 23:55:20.748585 00280000 ################################################################
10125 23:55:20.748719
10126 23:55:21.303254 00300000 ################################################################
10127 23:55:21.303386
10128 23:55:21.845163 00380000 ################################################################
10129 23:55:21.845290
10130 23:55:22.378762 00400000 ################################################################
10131 23:55:22.378899
10132 23:55:22.905743 00480000 ################################################################
10133 23:55:22.905881
10134 23:55:23.442826 00500000 ################################################################
10135 23:55:23.442985
10136 23:55:23.968939 00580000 ################################################################
10137 23:55:23.969092
10138 23:55:24.511403 00600000 ################################################################
10139 23:55:24.511536
10140 23:55:25.069040 00680000 ################################################################
10141 23:55:25.069187
10142 23:55:25.624003 00700000 ################################################################
10143 23:55:25.624140
10144 23:55:26.165047 00780000 ################################################################
10145 23:55:26.165186
10146 23:55:26.709389 00800000 ################################################################
10147 23:55:26.709534
10148 23:55:27.261143 00880000 ################################################################
10149 23:55:27.261284
10150 23:55:27.802910 00900000 ################################################################
10151 23:55:27.803058
10152 23:55:28.338824 00980000 ################################################################
10153 23:55:28.338955
10154 23:55:28.885222 00a00000 ################################################################
10155 23:55:28.885370
10156 23:55:29.423084 00a80000 ################################################################
10157 23:55:29.423231
10158 23:55:29.945230 00b00000 ################################################################
10159 23:55:29.945406
10160 23:55:30.471722 00b80000 ################################################################
10161 23:55:30.471856
10162 23:55:31.013530 00c00000 ################################################################
10163 23:55:31.013674
10164 23:55:31.542830 00c80000 ################################################################
10165 23:55:31.542969
10166 23:55:32.090250 00d00000 ################################################################
10167 23:55:32.090382
10168 23:55:32.645770 00d80000 ################################################################
10169 23:55:32.645906
10170 23:55:33.204054 00e00000 ################################################################
10171 23:55:33.204191
10172 23:55:33.759025 00e80000 ################################################################
10173 23:55:33.759170
10174 23:55:34.292382 00f00000 ################################################################
10175 23:55:34.292518
10176 23:55:34.834260 00f80000 ################################################################
10177 23:55:34.834409
10178 23:55:35.545775 01000000 ################################################################
10179 23:55:35.546296
10180 23:55:36.242278 01080000 ################################################################
10181 23:55:36.242852
10182 23:55:36.877266 01100000 ################################################################
10183 23:55:36.877758
10184 23:55:37.493729 01180000 ################################################################
10185 23:55:37.494332
10186 23:55:38.128010 01200000 ################################################################
10187 23:55:38.128389
10188 23:55:38.764828 01280000 ################################################################
10189 23:55:38.765342
10190 23:55:39.409612 01300000 ################################################################
10191 23:55:39.410026
10192 23:55:40.093546 01380000 ################################################################
10193 23:55:40.094109
10194 23:55:40.810627 01400000 ################################################################
10195 23:55:40.811113
10196 23:55:41.525171 01480000 ################################################################
10197 23:55:41.525739
10198 23:55:42.230573 01500000 ################################################################
10199 23:55:42.231086
10200 23:55:42.952346 01580000 ################################################################
10201 23:55:42.952920
10202 23:55:43.663406 01600000 ################################################################
10203 23:55:43.663916
10204 23:55:44.370716 01680000 ################################################################
10205 23:55:44.371212
10206 23:55:45.086473 01700000 ################################################################
10207 23:55:45.087013
10208 23:55:45.721507 01780000 ################################################################
10209 23:55:45.721744
10210 23:55:46.376708 01800000 ################################################################
10211 23:55:46.376844
10212 23:55:47.073883 01880000 ################################################################
10213 23:55:47.074433
10214 23:55:47.753219 01900000 ################################################################
10215 23:55:47.753708
10216 23:55:48.444411 01980000 ################################################################
10217 23:55:48.444550
10218 23:55:49.138879 01a00000 ################################################################
10219 23:55:49.139399
10220 23:55:49.855372 01a80000 ################################################################
10221 23:55:49.855898
10222 23:55:50.557702 01b00000 ################################################################
10223 23:55:50.557852
10224 23:55:51.181470 01b80000 ################################################################
10225 23:55:51.181627
10226 23:55:51.801112 01c00000 ################################################################
10227 23:55:51.801610
10228 23:55:52.473184 01c80000 ################################################################
10229 23:55:52.473685
10230 23:55:53.183857 01d00000 ################################################################
10231 23:55:53.184362
10232 23:55:53.896352 01d80000 ################################################################
10233 23:55:53.896885
10234 23:55:54.606031 01e00000 ################################################################
10235 23:55:54.606615
10236 23:55:55.333170 01e80000 ################################################################
10237 23:55:55.333675
10238 23:55:56.064175 01f00000 ################################################################
10239 23:55:56.064773
10240 23:55:56.789920 01f80000 ################################################################
10241 23:55:56.790428
10242 23:55:57.538150 02000000 ################################################################
10243 23:55:57.538656
10244 23:55:58.254278 02080000 ################################################################
10245 23:55:58.254874
10246 23:55:58.973807 02100000 ################################################################
10247 23:55:58.974338
10248 23:55:59.688651 02180000 ################################################################
10249 23:55:59.689322
10250 23:56:00.396724 02200000 ################################################################
10251 23:56:00.397325
10252 23:56:01.088754 02280000 ################################################################
10253 23:56:01.089311
10254 23:56:01.796027 02300000 ################################################################
10255 23:56:01.796555
10256 23:56:02.471682 02380000 ################################################################
10257 23:56:02.471845
10258 23:56:03.165422 02400000 ################################################################
10259 23:56:03.166032
10260 23:56:03.853765 02480000 ################################################################
10261 23:56:03.853948
10262 23:56:04.456937 02500000 ################################################################
10263 23:56:04.457144
10264 23:56:05.149625 02580000 ################################################################
10265 23:56:05.150143
10266 23:56:05.864425 02600000 ################################################################
10267 23:56:05.864972
10268 23:56:06.590589 02680000 ################################################################
10269 23:56:06.591109
10270 23:56:07.310128 02700000 ################################################################
10271 23:56:07.310681
10272 23:56:08.034629 02780000 ################################################################
10273 23:56:08.035171
10274 23:56:08.755535 02800000 ################################################################
10275 23:56:08.756052
10276 23:56:09.475180 02880000 ################################################################
10277 23:56:09.475694
10278 23:56:10.178264 02900000 ################################################################
10279 23:56:10.178779
10280 23:56:10.864757 02980000 ################################################################
10281 23:56:10.865332
10282 23:56:11.560805 02a00000 ################################################################
10283 23:56:11.561358
10284 23:56:12.288716 02a80000 ################################################################
10285 23:56:12.289396
10286 23:56:12.995611 02b00000 ################################################################
10287 23:56:12.996136
10288 23:56:13.702543 02b80000 ################################################################
10289 23:56:13.702695
10290 23:56:14.379790 02c00000 ################################################################
10291 23:56:14.380369
10292 23:56:15.062566 02c80000 ################################################################
10293 23:56:15.062702
10294 23:56:15.638127 02d00000 ################################################################
10295 23:56:15.638276
10296 23:56:16.207118 02d80000 ################################################################
10297 23:56:16.207265
10298 23:56:16.787353 02e00000 ################################################################
10299 23:56:16.787500
10300 23:56:17.376227 02e80000 ################################################################
10301 23:56:17.376367
10302 23:56:17.950681 02f00000 ################################################################
10303 23:56:17.950826
10304 23:56:18.521876 02f80000 ################################################################
10305 23:56:18.522045
10306 23:56:19.111761 03000000 ################################################################
10307 23:56:19.111910
10308 23:56:19.687988 03080000 ################################################################
10309 23:56:19.688134
10310 23:56:20.271108 03100000 ################################################################
10311 23:56:20.271261
10312 23:56:20.851891 03180000 ################################################################
10313 23:56:20.852039
10314 23:56:21.445564 03200000 ################################################################
10315 23:56:21.445709
10316 23:56:22.042274 03280000 ################################################################
10317 23:56:22.042419
10318 23:56:22.637730 03300000 ################################################################
10319 23:56:22.637886
10320 23:56:23.010980 03380000 ######################################## done.
10321 23:56:23.011129
10322 23:56:23.014204 The bootfile was 54324518 bytes long.
10323 23:56:23.014290
10324 23:56:23.017669 Sending tftp read request... done.
10325 23:56:23.017752
10326 23:56:23.017817 Waiting for the transfer...
10327 23:56:23.017878
10328 23:56:23.021319 00000000 # done.
10329 23:56:23.021403
10330 23:56:23.027451 Command line loaded dynamically from TFTP file: 14084372/tftp-deploy-pcqix4nj/kernel/cmdline
10331 23:56:23.027542
10332 23:56:23.040907 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10333 23:56:23.041101
10334 23:56:23.043714 Loading FIT.
10335 23:56:23.043799
10336 23:56:23.047663 Image ramdisk-1 has 41211737 bytes.
10337 23:56:23.047748
10338 23:56:23.050667 Image fdt-1 has 47258 bytes.
10339 23:56:23.050751
10340 23:56:23.050815 Image kernel-1 has 13063488 bytes.
10341 23:56:23.053982
10342 23:56:23.061097 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10343 23:56:23.061201
10344 23:56:23.076972 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10345 23:56:23.081453
10346 23:56:23.084428 Choosing best match conf-1 for compat google,spherion-rev2.
10347 23:56:23.088375
10348 23:56:23.093360 Connected to device vid:did:rid of 1ae0:0028:00
10349 23:56:23.099849
10350 23:56:23.102986 tpm_get_response: command 0x17b, return code 0x0
10351 23:56:23.103073
10352 23:56:23.106749 ec_init: CrosEC protocol v3 supported (256, 248)
10353 23:56:23.111156
10354 23:56:23.114625 tpm_cleanup: add release locality here.
10355 23:56:23.114707
10356 23:56:23.114772 Shutting down all USB controllers.
10357 23:56:23.114833
10358 23:56:23.117796 Removing current net device
10359 23:56:23.117877
10360 23:56:23.124774 Exiting depthcharge with code 4 at timestamp: 101347458
10361 23:56:23.124857
10362 23:56:23.127900 LZMA decompressing kernel-1 to 0x821a6718
10363 23:56:23.127982
10364 23:56:23.131391 LZMA decompressing kernel-1 to 0x40000000
10365 23:56:24.741813
10366 23:56:24.741967 jumping to kernel
10367 23:56:24.742490 end: 2.2.4 bootloader-commands (duration 00:01:14) [common]
10368 23:56:24.742592 start: 2.2.5 auto-login-action (timeout 00:03:12) [common]
10369 23:56:24.742671 Setting prompt string to ['Linux version [0-9]']
10370 23:56:24.742742 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10371 23:56:24.742812 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10372 23:56:24.824955
10373 23:56:24.828937 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10374 23:56:24.831562 start: 2.2.5.1 login-action (timeout 00:03:11) [common]
10375 23:56:24.831660 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10376 23:56:24.831732 Setting prompt string to []
10377 23:56:24.831809 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10378 23:56:24.831884 Using line separator: #'\n'#
10379 23:56:24.831944 No login prompt set.
10380 23:56:24.832005 Parsing kernel messages
10381 23:56:24.832060 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10382 23:56:24.832160 [login-action] Waiting for messages, (timeout 00:03:11)
10383 23:56:24.832225 Waiting using forced prompt support (timeout 00:01:36)
10384 23:56:24.851585 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j210753-arm64-gcc-10-defconfig-arm64-chromebook-lsmmd) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024
10385 23:56:24.854475 [ 0.000000] random: crng init done
10386 23:56:24.861198 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10387 23:56:24.864724 [ 0.000000] efi: UEFI not found.
10388 23:56:24.871209 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10389 23:56:24.878434 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10390 23:56:24.888449 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10391 23:56:24.897999 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10392 23:56:24.904242 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10393 23:56:24.911468 [ 0.000000] printk: bootconsole [mtk8250] enabled
10394 23:56:24.917444 [ 0.000000] NUMA: No NUMA configuration found
10395 23:56:24.924008 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10396 23:56:24.927318 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10397 23:56:24.931293 [ 0.000000] Zone ranges:
10398 23:56:24.937420 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10399 23:56:24.941191 [ 0.000000] DMA32 empty
10400 23:56:24.947419 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10401 23:56:24.950885 [ 0.000000] Movable zone start for each node
10402 23:56:24.954135 [ 0.000000] Early memory node ranges
10403 23:56:24.960900 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10404 23:56:24.967189 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10405 23:56:24.974090 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10406 23:56:24.980427 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10407 23:56:24.984438 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10408 23:56:24.993673 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10409 23:56:25.048913 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10410 23:56:25.056164 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10411 23:56:25.062166 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10412 23:56:25.065672 [ 0.000000] psci: probing for conduit method from DT.
10413 23:56:25.073158 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10414 23:56:25.075576 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10415 23:56:25.082367 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10416 23:56:25.085776 [ 0.000000] psci: SMC Calling Convention v1.2
10417 23:56:25.092983 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10418 23:56:25.095755 [ 0.000000] Detected VIPT I-cache on CPU0
10419 23:56:25.103766 [ 0.000000] CPU features: detected: GIC system register CPU interface
10420 23:56:25.109248 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10421 23:56:25.115984 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10422 23:56:25.123089 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10423 23:56:25.129103 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10424 23:56:25.135941 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10425 23:56:25.145005 [ 0.000000] alternatives: applying boot alternatives
10426 23:56:25.145725 [ 0.000000] Fallback order for Node 0: 0
10427 23:56:25.152206 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10428 23:56:25.156379 [ 0.000000] Policy zone: Normal
10429 23:56:25.172586 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10430 23:56:25.182134 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10431 23:56:25.193689 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10432 23:56:25.203803 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10433 23:56:25.210878 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10434 23:56:25.214087 <6>[ 0.000000] software IO TLB: area num 8.
10435 23:56:25.270085 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10436 23:56:25.419103 <6>[ 0.000000] Memory: 7923944K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 428824K reserved, 32768K cma-reserved)
10437 23:56:25.425732 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10438 23:56:25.432204 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10439 23:56:25.435866 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10440 23:56:25.442405 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10441 23:56:25.449135 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10442 23:56:25.452871 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10443 23:56:25.462772 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10444 23:56:25.469752 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10445 23:56:25.472526 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10446 23:56:25.479978 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10447 23:56:25.483566 <6>[ 0.000000] GICv3: 608 SPIs implemented
10448 23:56:25.491089 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10449 23:56:25.493329 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10450 23:56:25.496652 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10451 23:56:25.506297 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10452 23:56:25.516479 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10453 23:56:25.530397 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10454 23:56:25.536524 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10455 23:56:25.545572 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10456 23:56:25.558730 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10457 23:56:25.565324 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10458 23:56:25.572707 <6>[ 0.009176] Console: colour dummy device 80x25
10459 23:56:25.582221 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10460 23:56:25.585738 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10461 23:56:25.592434 <6>[ 0.029284] LSM: Security Framework initializing
10462 23:56:25.598680 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10463 23:56:25.609114 <6>[ 0.042036] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10464 23:56:25.615874 <6>[ 0.051515] cblist_init_generic: Setting adjustable number of callback queues.
10465 23:56:25.622826 <6>[ 0.058960] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 23:56:25.632110 <6>[ 0.065337] cblist_init_generic: Setting adjustable number of callback queues.
10467 23:56:25.636870 <6>[ 0.072764] cblist_init_generic: Setting shift to 3 and lim to 1.
10468 23:56:25.642654 <6>[ 0.079165] rcu: Hierarchical SRCU implementation.
10469 23:56:25.649398 <6>[ 0.084180] rcu: Max phase no-delay instances is 1000.
10470 23:56:25.655640 <6>[ 0.091210] EFI services will not be available.
10471 23:56:25.658547 <6>[ 0.096165] smp: Bringing up secondary CPUs ...
10472 23:56:25.666603 <6>[ 0.101241] Detected VIPT I-cache on CPU1
10473 23:56:25.673443 <6>[ 0.101313] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10474 23:56:25.680603 <6>[ 0.101345] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10475 23:56:25.683126 <6>[ 0.101682] Detected VIPT I-cache on CPU2
10476 23:56:25.689953 <6>[ 0.101736] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10477 23:56:25.696676 <6>[ 0.101754] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10478 23:56:25.702926 <6>[ 0.102014] Detected VIPT I-cache on CPU3
10479 23:56:25.710316 <6>[ 0.102062] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10480 23:56:25.716280 <6>[ 0.102077] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10481 23:56:25.719926 <6>[ 0.102383] CPU features: detected: Spectre-v4
10482 23:56:25.726687 <6>[ 0.102390] CPU features: detected: Spectre-BHB
10483 23:56:25.730062 <6>[ 0.102394] Detected PIPT I-cache on CPU4
10484 23:56:25.736379 <6>[ 0.102452] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10485 23:56:25.743837 <6>[ 0.102468] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10486 23:56:25.747001 <6>[ 0.102758] Detected PIPT I-cache on CPU5
10487 23:56:25.756537 <6>[ 0.102820] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10488 23:56:25.764590 <6>[ 0.102836] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10489 23:56:25.767248 <6>[ 0.103118] Detected PIPT I-cache on CPU6
10490 23:56:25.773253 <6>[ 0.103183] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10491 23:56:25.779828 <6>[ 0.103199] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10492 23:56:25.783466 <6>[ 0.103492] Detected PIPT I-cache on CPU7
10493 23:56:25.792901 <6>[ 0.103556] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10494 23:56:25.799906 <6>[ 0.103572] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10495 23:56:25.803174 <6>[ 0.103618] smp: Brought up 1 node, 8 CPUs
10496 23:56:25.806395 <6>[ 0.244982] SMP: Total of 8 processors activated.
10497 23:56:25.813318 <6>[ 0.249933] CPU features: detected: 32-bit EL0 Support
10498 23:56:25.823678 <6>[ 0.255330] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10499 23:56:25.829876 <6>[ 0.264131] CPU features: detected: Common not Private translations
10500 23:56:25.834054 <6>[ 0.270606] CPU features: detected: CRC32 instructions
10501 23:56:25.839760 <6>[ 0.275958] CPU features: detected: RCpc load-acquire (LDAPR)
10502 23:56:25.846714 <6>[ 0.281918] CPU features: detected: LSE atomic instructions
10503 23:56:25.850149 <6>[ 0.287700] CPU features: detected: Privileged Access Never
10504 23:56:25.856434 <6>[ 0.293515] CPU features: detected: RAS Extension Support
10505 23:56:25.863453 <6>[ 0.299123] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10506 23:56:25.870447 <6>[ 0.306345] CPU: All CPU(s) started at EL2
10507 23:56:25.873491 <6>[ 0.310662] alternatives: applying system-wide alternatives
10508 23:56:25.885200 <6>[ 0.321516] devtmpfs: initialized
10509 23:56:25.896887 <6>[ 0.330403] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10510 23:56:25.907022 <6>[ 0.340359] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10511 23:56:25.913657 <6>[ 0.348374] pinctrl core: initialized pinctrl subsystem
10512 23:56:25.916648 <6>[ 0.355027] DMI not present or invalid.
10513 23:56:25.923397 <6>[ 0.359433] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10514 23:56:25.930461 <6>[ 0.366287] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10515 23:56:25.940609 <6>[ 0.373858] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10516 23:56:25.947274 <6>[ 0.382077] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10517 23:56:25.953535 <6>[ 0.390322] audit: initializing netlink subsys (disabled)
10518 23:56:25.963278 <5>[ 0.396014] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10519 23:56:25.966662 <6>[ 0.396714] thermal_sys: Registered thermal governor 'step_wise'
10520 23:56:25.973450 <6>[ 0.403977] thermal_sys: Registered thermal governor 'power_allocator'
10521 23:56:25.980460 <6>[ 0.410235] cpuidle: using governor menu
10522 23:56:25.983059 <6>[ 0.421191] NET: Registered PF_QIPCRTR protocol family
10523 23:56:25.989781 <6>[ 0.426669] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10524 23:56:25.996422 <6>[ 0.433771] ASID allocator initialised with 32768 entries
10525 23:56:26.003749 <6>[ 0.440349] Serial: AMBA PL011 UART driver
10526 23:56:26.012220 <4>[ 0.449095] Trying to register duplicate clock ID: 134
10527 23:56:26.070477 <6>[ 0.510577] KASLR enabled
10528 23:56:26.084513 <6>[ 0.518354] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10529 23:56:26.091004 <6>[ 0.525369] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10530 23:56:26.097937 <6>[ 0.531856] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10531 23:56:26.104109 <6>[ 0.538861] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10532 23:56:26.111225 <6>[ 0.545349] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10533 23:56:26.117865 <6>[ 0.552351] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10534 23:56:26.124958 <6>[ 0.558837] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10535 23:56:26.131430 <6>[ 0.565839] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10536 23:56:26.134145 <6>[ 0.573373] ACPI: Interpreter disabled.
10537 23:56:26.142613 <6>[ 0.579805] iommu: Default domain type: Translated
10538 23:56:26.149714 <6>[ 0.584914] iommu: DMA domain TLB invalidation policy: strict mode
10539 23:56:26.152507 <5>[ 0.591559] SCSI subsystem initialized
10540 23:56:26.159280 <6>[ 0.595722] usbcore: registered new interface driver usbfs
10541 23:56:26.165769 <6>[ 0.601454] usbcore: registered new interface driver hub
10542 23:56:26.169178 <6>[ 0.607004] usbcore: registered new device driver usb
10543 23:56:26.175837 <6>[ 0.613100] pps_core: LinuxPPS API ver. 1 registered
10544 23:56:26.186122 <6>[ 0.618294] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10545 23:56:26.188956 <6>[ 0.627640] PTP clock support registered
10546 23:56:26.192735 <6>[ 0.631883] EDAC MC: Ver: 3.0.0
10547 23:56:26.199950 <6>[ 0.637025] FPGA manager framework
10548 23:56:26.203373 <6>[ 0.640711] Advanced Linux Sound Architecture Driver Initialized.
10549 23:56:26.207059 <6>[ 0.647482] vgaarb: loaded
10550 23:56:26.213350 <6>[ 0.650638] clocksource: Switched to clocksource arch_sys_counter
10551 23:56:26.220187 <5>[ 0.657079] VFS: Disk quotas dquot_6.6.0
10552 23:56:26.227433 <6>[ 0.661261] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10553 23:56:26.229924 <6>[ 0.668451] pnp: PnP ACPI: disabled
10554 23:56:26.238096 <6>[ 0.675183] NET: Registered PF_INET protocol family
10555 23:56:26.244551 <6>[ 0.680785] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10556 23:56:26.259217 <6>[ 0.693133] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10557 23:56:26.269355 <6>[ 0.701942] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10558 23:56:26.275791 <6>[ 0.709909] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10559 23:56:26.282382 <6>[ 0.718609] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10560 23:56:26.294631 <6>[ 0.728360] TCP: Hash tables configured (established 65536 bind 65536)
10561 23:56:26.300928 <6>[ 0.735228] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10562 23:56:26.308082 <6>[ 0.742424] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10563 23:56:26.314866 <6>[ 0.750126] NET: Registered PF_UNIX/PF_LOCAL protocol family
10564 23:56:26.320876 <6>[ 0.756208] RPC: Registered named UNIX socket transport module.
10565 23:56:26.324375 <6>[ 0.762358] RPC: Registered udp transport module.
10566 23:56:26.331009 <6>[ 0.767289] RPC: Registered tcp transport module.
10567 23:56:26.337768 <6>[ 0.772223] RPC: Registered tcp NFSv4.1 backchannel transport module.
10568 23:56:26.341846 <6>[ 0.778887] PCI: CLS 0 bytes, default 64
10569 23:56:26.344702 <6>[ 0.783233] Unpacking initramfs...
10570 23:56:26.368859 <6>[ 0.802751] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10571 23:56:26.378867 <6>[ 0.811400] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10572 23:56:26.382215 <6>[ 0.820235] kvm [1]: IPA Size Limit: 40 bits
10573 23:56:26.388932 <6>[ 0.824764] kvm [1]: GICv3: no GICV resource entry
10574 23:56:26.391954 <6>[ 0.829784] kvm [1]: disabling GICv2 emulation
10575 23:56:26.398869 <6>[ 0.834473] kvm [1]: GIC system register CPU interface enabled
10576 23:56:26.402407 <6>[ 0.840634] kvm [1]: vgic interrupt IRQ18
10577 23:56:26.408783 <6>[ 0.844990] kvm [1]: VHE mode initialized successfully
10578 23:56:26.415311 <5>[ 0.851451] Initialise system trusted keyrings
10579 23:56:26.421856 <6>[ 0.856293] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10580 23:56:26.428896 <6>[ 0.866326] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10581 23:56:26.435786 <5>[ 0.872715] NFS: Registering the id_resolver key type
10582 23:56:26.439069 <5>[ 0.878009] Key type id_resolver registered
10583 23:56:26.447018 <5>[ 0.882423] Key type id_legacy registered
10584 23:56:26.452329 <6>[ 0.886702] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10585 23:56:26.459032 <6>[ 0.893621] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10586 23:56:26.466954 <6>[ 0.901347] 9p: Installing v9fs 9p2000 file system support
10587 23:56:26.501397 <5>[ 0.938857] Key type asymmetric registered
10588 23:56:26.505377 <5>[ 0.943188] Asymmetric key parser 'x509' registered
10589 23:56:26.515084 <6>[ 0.948333] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10590 23:56:26.518425 <6>[ 0.955949] io scheduler mq-deadline registered
10591 23:56:26.521808 <6>[ 0.960711] io scheduler kyber registered
10592 23:56:26.540589 <6>[ 0.977755] EINJ: ACPI disabled.
10593 23:56:26.573180 <4>[ 1.003852] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 23:56:26.583527 <4>[ 1.014486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 23:56:26.598611 <6>[ 1.035654] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10596 23:56:26.606317 <6>[ 1.043654] printk: console [ttyS0] disabled
10597 23:56:26.634185 <6>[ 1.068292] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10598 23:56:26.641441 <6>[ 1.077753] printk: console [ttyS0] enabled
10599 23:56:26.644277 <6>[ 1.077753] printk: console [ttyS0] enabled
10600 23:56:26.651279 <6>[ 1.086647] printk: bootconsole [mtk8250] disabled
10601 23:56:26.654207 <6>[ 1.086647] printk: bootconsole [mtk8250] disabled
10602 23:56:26.661101 <6>[ 1.097640] SuperH (H)SCI(F) driver initialized
10603 23:56:26.664119 <6>[ 1.102932] msm_serial: driver initialized
10604 23:56:26.677899 <6>[ 1.111787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10605 23:56:26.687984 <6>[ 1.120335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10606 23:56:26.694572 <6>[ 1.128876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10607 23:56:26.704417 <6>[ 1.137503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10608 23:56:26.711452 <6>[ 1.146210] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10609 23:56:26.721319 <6>[ 1.154924] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10610 23:56:26.731288 <6>[ 1.163464] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10611 23:56:26.737795 <6>[ 1.172276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10612 23:56:26.747516 <6>[ 1.180817] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10613 23:56:26.759381 <6>[ 1.196252] loop: module loaded
10614 23:56:26.765344 <6>[ 1.202389] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10615 23:56:26.789118 <4>[ 1.225944] mtk-pmic-keys: Failed to locate of_node [id: -1]
10616 23:56:26.795461 <6>[ 1.232790] megasas: 07.719.03.00-rc1
10617 23:56:26.805123 <6>[ 1.242421] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10618 23:56:26.812966 <6>[ 1.250011] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10619 23:56:26.829275 <6>[ 1.266581] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10620 23:56:26.885140 <6>[ 1.316010] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10621 23:56:28.071369 <6>[ 2.508190] Freeing initrd memory: 40240K
10622 23:56:28.082838 <6>[ 2.520059] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10623 23:56:28.093979 <6>[ 2.531259] tun: Universal TUN/TAP device driver, 1.6
10624 23:56:28.096877 <6>[ 2.537334] thunder_xcv, ver 1.0
10625 23:56:28.100840 <6>[ 2.540842] thunder_bgx, ver 1.0
10626 23:56:28.104138 <6>[ 2.544335] nicpf, ver 1.0
10627 23:56:28.114094 <6>[ 2.548355] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10628 23:56:28.118500 <6>[ 2.555830] hns3: Copyright (c) 2017 Huawei Corporation.
10629 23:56:28.124197 <6>[ 2.561419] hclge is initializing
10630 23:56:28.127727 <6>[ 2.564999] e1000: Intel(R) PRO/1000 Network Driver
10631 23:56:28.134176 <6>[ 2.570128] e1000: Copyright (c) 1999-2006 Intel Corporation.
10632 23:56:28.137762 <6>[ 2.576142] e1000e: Intel(R) PRO/1000 Network Driver
10633 23:56:28.143986 <6>[ 2.581356] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10634 23:56:28.150983 <6>[ 2.587542] igb: Intel(R) Gigabit Ethernet Network Driver
10635 23:56:28.157178 <6>[ 2.593192] igb: Copyright (c) 2007-2014 Intel Corporation.
10636 23:56:28.163806 <6>[ 2.599027] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10637 23:56:28.170295 <6>[ 2.605544] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10638 23:56:28.174096 <6>[ 2.612011] sky2: driver version 1.30
10639 23:56:28.180538 <6>[ 2.616937] usbcore: registered new device driver r8152-cfgselector
10640 23:56:28.187204 <6>[ 2.623472] usbcore: registered new interface driver r8152
10641 23:56:28.194546 <6>[ 2.629292] VFIO - User Level meta-driver version: 0.3
10642 23:56:28.200369 <6>[ 2.637451] usbcore: registered new interface driver usb-storage
10643 23:56:28.206675 <6>[ 2.643900] usbcore: registered new device driver onboard-usb-hub
10644 23:56:28.215815 <6>[ 2.652997] mt6397-rtc mt6359-rtc: registered as rtc0
10645 23:56:28.225877 <6>[ 2.658458] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-29T23:56:28 UTC (1717026988)
10646 23:56:28.228746 <6>[ 2.668026] i2c_dev: i2c /dev entries driver
10647 23:56:28.245642 <6>[ 2.679851] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10648 23:56:28.252305 <4>[ 2.688578] cpu cpu0: supply cpu not found, using dummy regulator
10649 23:56:28.258984 <4>[ 2.695006] cpu cpu1: supply cpu not found, using dummy regulator
10650 23:56:28.266069 <4>[ 2.701409] cpu cpu2: supply cpu not found, using dummy regulator
10651 23:56:28.272368 <4>[ 2.707829] cpu cpu3: supply cpu not found, using dummy regulator
10652 23:56:28.278557 <4>[ 2.714224] cpu cpu4: supply cpu not found, using dummy regulator
10653 23:56:28.286118 <4>[ 2.720622] cpu cpu5: supply cpu not found, using dummy regulator
10654 23:56:28.292556 <4>[ 2.727018] cpu cpu6: supply cpu not found, using dummy regulator
10655 23:56:28.298353 <4>[ 2.733437] cpu cpu7: supply cpu not found, using dummy regulator
10656 23:56:28.316401 <6>[ 2.754081] cpu cpu0: EM: created perf domain
10657 23:56:28.319768 <6>[ 2.759001] cpu cpu4: EM: created perf domain
10658 23:56:28.326898 <6>[ 2.764631] sdhci: Secure Digital Host Controller Interface driver
10659 23:56:28.333766 <6>[ 2.771064] sdhci: Copyright(c) Pierre Ossman
10660 23:56:28.340385 <6>[ 2.776016] Synopsys Designware Multimedia Card Interface Driver
10661 23:56:28.347430 <6>[ 2.782683] sdhci-pltfm: SDHCI platform and OF driver helper
10662 23:56:28.350951 <6>[ 2.782756] mmc0: CQHCI version 5.10
10663 23:56:28.357085 <6>[ 2.792992] ledtrig-cpu: registered to indicate activity on CPUs
10664 23:56:28.363694 <6>[ 2.800043] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10665 23:56:28.370619 <6>[ 2.807116] usbcore: registered new interface driver usbhid
10666 23:56:28.374550 <6>[ 2.812939] usbhid: USB HID core driver
10667 23:56:28.380760 <6>[ 2.817159] spi_master spi0: will run message pump with realtime priority
10668 23:56:28.425162 <6>[ 2.855846] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10669 23:56:28.444907 <6>[ 2.872342] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10670 23:56:28.448335 <6>[ 2.886707] mmc0: Command Queue Engine enabled
10671 23:56:28.456361 <6>[ 2.891473] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10672 23:56:28.461740 <6>[ 2.898191] cros-ec-spi spi0.0: Chrome EC device registered
10673 23:56:28.464968 <6>[ 2.898700] mmcblk0: mmc0:0001 DA4128 116 GiB
10674 23:56:28.478484 <6>[ 2.916069] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10675 23:56:28.486029 <6>[ 2.923430] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10676 23:56:28.493091 <6>[ 2.929651] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10677 23:56:28.503219 <6>[ 2.934086] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10678 23:56:28.509139 <6>[ 2.935597] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10679 23:56:28.512888 <6>[ 2.945468] NET: Registered PF_PACKET protocol family
10680 23:56:28.519466 <6>[ 2.956083] 9pnet: Installing 9P2000 support
10681 23:56:28.522558 <5>[ 2.960641] Key type dns_resolver registered
10682 23:56:28.525646 <6>[ 2.965605] registered taskstats version 1
10683 23:56:28.532394 <5>[ 2.969989] Loading compiled-in X.509 certificates
10684 23:56:28.562554 <4>[ 2.993101] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 23:56:28.572209 <4>[ 3.003834] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10686 23:56:28.587446 <6>[ 3.024983] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10687 23:56:28.594735 <6>[ 3.031896] xhci-mtk 11200000.usb: xHCI Host Controller
10688 23:56:28.601066 <6>[ 3.037388] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10689 23:56:28.611120 <6>[ 3.045229] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10690 23:56:28.618035 <6>[ 3.054664] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10691 23:56:28.624368 <6>[ 3.060736] xhci-mtk 11200000.usb: xHCI Host Controller
10692 23:56:28.631019 <6>[ 3.066218] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10693 23:56:28.637783 <6>[ 3.073864] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10694 23:56:28.644307 <6>[ 3.081508] hub 1-0:1.0: USB hub found
10695 23:56:28.648083 <6>[ 3.085520] hub 1-0:1.0: 1 port detected
10696 23:56:28.654759 <6>[ 3.089780] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10697 23:56:28.660945 <6>[ 3.098276] hub 2-0:1.0: USB hub found
10698 23:56:28.664187 <6>[ 3.102293] hub 2-0:1.0: 1 port detected
10699 23:56:28.671761 <6>[ 3.109102] mtk-msdc 11f70000.mmc: Got CD GPIO
10700 23:56:28.683226 <6>[ 3.116968] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10701 23:56:28.689832 <6>[ 3.125001] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10702 23:56:28.699313 <4>[ 3.132917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10703 23:56:28.709187 <6>[ 3.142442] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10704 23:56:28.716725 <6>[ 3.150520] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10705 23:56:28.722815 <6>[ 3.158539] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10706 23:56:28.732709 <6>[ 3.166461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10707 23:56:28.739270 <6>[ 3.174278] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10708 23:56:28.749946 <6>[ 3.182094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10709 23:56:28.759475 <6>[ 3.192441] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10710 23:56:28.765742 <6>[ 3.200798] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10711 23:56:28.775820 <6>[ 3.209148] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10712 23:56:28.782356 <6>[ 3.217489] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10713 23:56:28.792518 <6>[ 3.225826] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10714 23:56:28.799772 <6>[ 3.234165] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10715 23:56:28.808653 <6>[ 3.242503] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10716 23:56:28.815922 <6>[ 3.250845] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10717 23:56:28.826035 <6>[ 3.259185] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10718 23:56:28.832737 <6>[ 3.267526] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10719 23:56:28.842200 <6>[ 3.275865] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10720 23:56:28.848870 <6>[ 3.284203] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10721 23:56:28.858657 <6>[ 3.292540] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10722 23:56:28.864982 <6>[ 3.300878] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10723 23:56:28.875556 <6>[ 3.309216] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10724 23:56:28.881854 <6>[ 3.317948] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10725 23:56:28.888541 <6>[ 3.325090] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10726 23:56:28.895089 <6>[ 3.331857] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10727 23:56:28.901672 <6>[ 3.338617] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10728 23:56:28.907870 <6>[ 3.345567] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10729 23:56:28.918322 <6>[ 3.352423] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10730 23:56:28.928775 <6>[ 3.361552] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10731 23:56:28.939145 <6>[ 3.370672] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10732 23:56:28.947889 <6>[ 3.379966] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10733 23:56:28.954701 <6>[ 3.389433] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10734 23:56:28.964657 <6>[ 3.398916] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10735 23:56:28.974510 <6>[ 3.408037] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10736 23:56:28.984887 <6>[ 3.417503] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10737 23:56:28.994844 <6>[ 3.426622] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10738 23:56:29.004463 <6>[ 3.435916] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10739 23:56:29.014469 <6>[ 3.446076] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10740 23:56:29.024412 <6>[ 3.457470] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10741 23:56:29.052895 <6>[ 3.487183] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10742 23:56:29.081325 <6>[ 3.518675] hub 2-1:1.0: USB hub found
10743 23:56:29.084943 <6>[ 3.523157] hub 2-1:1.0: 3 ports detected
10744 23:56:29.092905 <6>[ 3.530424] hub 2-1:1.0: USB hub found
10745 23:56:29.096145 <6>[ 3.534852] hub 2-1:1.0: 3 ports detected
10746 23:56:29.204527 <6>[ 3.638913] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10747 23:56:29.359323 <6>[ 3.796833] hub 1-1:1.0: USB hub found
10748 23:56:29.362900 <6>[ 3.801357] hub 1-1:1.0: 4 ports detected
10749 23:56:29.372616 <6>[ 3.809981] hub 1-1:1.0: USB hub found
10750 23:56:29.376115 <6>[ 3.814372] hub 1-1:1.0: 4 ports detected
10751 23:56:29.444607 <6>[ 3.879151] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10752 23:56:29.553608 <6>[ 3.987591] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10753 23:56:29.590665 <4>[ 4.024324] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10754 23:56:29.599762 <4>[ 4.033444] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10755 23:56:29.638179 <6>[ 4.075791] r8152 2-1.3:1.0 eth0: v1.12.13
10756 23:56:29.697608 <6>[ 4.130953] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10757 23:56:29.829629 <6>[ 4.266894] hub 1-1.4:1.0: USB hub found
10758 23:56:29.832322 <6>[ 4.271566] hub 1-1.4:1.0: 2 ports detected
10759 23:56:29.842088 <6>[ 4.279889] hub 1-1.4:1.0: USB hub found
10760 23:56:29.845430 <6>[ 4.284490] hub 1-1.4:1.0: 2 ports detected
10761 23:56:30.144669 <6>[ 4.578953] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10762 23:56:30.336910 <6>[ 4.770955] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10763 23:56:31.238280 <6>[ 5.675837] r8152 2-1.3:1.0 eth0: carrier on
10764 23:56:33.796840 <5>[ 5.706726] Sending DHCP requests .., OK
10765 23:56:33.803284 <6>[ 8.239087] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10766 23:56:33.806629 <6>[ 8.247377] IP-Config: Complete:
10767 23:56:33.820169 <6>[ 8.250873] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10768 23:56:33.826874 <6>[ 8.261579] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10769 23:56:33.833404 <6>[ 8.270195] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10770 23:56:33.839644 <6>[ 8.270204] nameserver0=192.168.201.1
10771 23:56:33.843147 <6>[ 8.282339] clk: Disabling unused clocks
10772 23:56:33.846762 <6>[ 8.288019] ALSA device list:
10773 23:56:33.852958 <6>[ 8.291259] No soundcards found.
10774 23:56:33.860913 <6>[ 8.298808] Freeing unused kernel memory: 8512K
10775 23:56:33.864027 <6>[ 8.303754] Run /init as init process
10776 23:56:33.893718 <6>[ 8.332091] NET: Registered PF_INET6 protocol family
10777 23:56:33.901085 <6>[ 8.338735] Segment Routing with IPv6
10778 23:56:33.903788 <6>[ 8.342678] In-situ OAM (IOAM) with IPv6
10779 23:56:33.948925 <30>[ 8.360202] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10780 23:56:33.955094 <30>[ 8.393273] systemd[1]: Detected architecture arm64.
10781 23:56:33.955175
10782 23:56:33.961958 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10783 23:56:33.962037
10784 23:56:33.976952 <30>[ 8.414964] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10785 23:56:34.106516 <30>[ 8.540942] systemd[1]: Queued start job for default target graphical.target.
10786 23:56:34.153667 <30>[ 8.588748] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10787 23:56:34.160492 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10788 23:56:34.181190 <30>[ 8.615798] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10789 23:56:34.190981 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10790 23:56:34.209996 <30>[ 8.644871] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10791 23:56:34.219692 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10792 23:56:34.237620 <30>[ 8.672191] systemd[1]: Created slice user.slice - User and Session Slice.
10793 23:56:34.243965 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10794 23:56:34.263698 <30>[ 8.695137] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10795 23:56:34.270234 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10796 23:56:34.291487 <30>[ 8.723093] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10797 23:56:34.298070 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10798 23:56:34.326503 <30>[ 8.751513] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10799 23:56:34.336652 <30>[ 8.771433] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10800 23:56:34.343298 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10801 23:56:34.360804 <30>[ 8.795335] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10802 23:56:34.368072 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10803 23:56:34.388216 <30>[ 8.823132] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10804 23:56:34.398010 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10805 23:56:34.413182 <30>[ 8.851089] systemd[1]: Reached target paths.target - Path Units.
10806 23:56:34.423119 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10807 23:56:34.440540 <30>[ 8.875338] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10808 23:56:34.447182 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10809 23:56:34.460923 <30>[ 8.898937] systemd[1]: Reached target slices.target - Slice Units.
10810 23:56:34.470690 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10811 23:56:34.485176 <30>[ 8.923436] systemd[1]: Reached target swap.target - Swaps.
10812 23:56:34.491721 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10813 23:56:34.512761 <30>[ 8.947463] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10814 23:56:34.522772 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10815 23:56:34.541448 <30>[ 8.975919] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10816 23:56:34.551448 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10817 23:56:34.571314 <30>[ 9.004911] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10818 23:56:34.579794 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10819 23:56:34.596460 <30>[ 9.031567] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10820 23:56:34.606806 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10821 23:56:34.624878 <30>[ 9.059550] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10822 23:56:34.631432 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10823 23:56:34.648747 <30>[ 9.083609] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10824 23:56:34.660609 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10825 23:56:34.677674 <30>[ 9.112389] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10826 23:56:34.687764 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10827 23:56:34.705129 <30>[ 9.139365] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10828 23:56:34.714434 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10829 23:56:34.756697 <30>[ 9.191233] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10830 23:56:34.763138 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10831 23:56:34.784362 <30>[ 9.219063] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10832 23:56:34.790801 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10833 23:56:34.812376 <30>[ 9.247463] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10834 23:56:34.819040 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10835 23:56:34.847324 <30>[ 9.275446] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10836 23:56:34.884351 <30>[ 9.319292] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10837 23:56:34.894351 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10838 23:56:34.917303 <30>[ 9.352175] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10839 23:56:34.923943 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10840 23:56:34.949706 <30>[ 9.384105] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10841 23:56:34.966418 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 9.398396] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10842 23:56:34.966500 .
10843 23:56:34.989158 <30>[ 9.424195] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10844 23:56:34.995959 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10845 23:56:35.056981 <30>[ 9.491701] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10846 23:56:35.066812 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10847 23:56:35.090142 <30>[ 9.524292] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10848 23:56:35.095923 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10849 23:56:35.144506 <30>[ 9.579294] systemd[1]: Starting systemd-journald.service - Journal Service...
10850 23:56:35.151158 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10851 23:56:35.171525 <30>[ 9.606022] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10852 23:56:35.177758 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10853 23:56:35.202936 <30>[ 9.634029] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10854 23:56:35.209315 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10855 23:56:35.232902 <30>[ 9.667999] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10856 23:56:35.242941 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10857 23:56:35.263408 <30>[ 9.698478] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10858 23:56:35.269958 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10859 23:56:35.293963 <30>[ 9.728672] systemd[1]: Started systemd-journald.service - Journal Service.
10860 23:56:35.300213 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10861 23:56:35.322928 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10862 23:56:35.341276 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10863 23:56:35.361458 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10864 23:56:35.381651 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10865 23:56:35.401738 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10866 23:56:35.422434 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10867 23:56:35.443202 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10868 23:56:35.463333 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10869 23:56:35.483297 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10870 23:56:35.505178 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10871 23:56:35.526571 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10872 23:56:35.547407 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10873 23:56:35.560941 See 'systemctl status systemd-remount-fs.service' for details.
10874 23:56:35.571217 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10875 23:56:35.590601 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10876 23:56:35.656898 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10877 23:56:35.681733 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10878 23:56:35.700539 <46>[ 10.135569] systemd-journald[192]: Received client request to flush runtime journal.
10879 23:56:35.708075 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10880 23:56:35.764936 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10881 23:56:35.789228 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10882 23:56:35.814035 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10883 23:56:35.833792 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10884 23:56:35.853272 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10885 23:56:35.873856 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10886 23:56:35.893533 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10887 23:56:35.953589 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10888 23:56:35.983528 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10889 23:56:36.001424 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10890 23:56:36.021296 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10891 23:56:36.077321 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10892 23:56:36.101922 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10893 23:56:36.124966 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10894 23:56:36.142252 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10895 23:56:36.209085 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10896 23:56:36.249821 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10897 23:56:36.277700 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10898 23:56:36.323300 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10899 23:56:36.343177 <5>[ 10.777628] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10900 23:56:36.353094 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10901 23:56:36.371807 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10902 23:56:36.377969 <5>[ 10.813109] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10903 23:56:36.388360 <5>[ 10.821787] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10904 23:56:36.398899 <4>[ 10.830768] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10905 23:56:36.401352 <6>[ 10.839804] cfg80211: failed to load regulatory.db
10906 23:56:36.421838 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10907 23:56:36.503715 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10908 23:56:36.529194 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m -<6>[ 10.965843] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10909 23:56:36.532858 System Initialization.
10910 23:56:36.543821 <6>[ 10.978595] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10911 23:56:36.550802 <6>[ 10.986405] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10912 23:56:36.561151 <6>[ 10.995771] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10913 23:56:36.568174 <6>[ 10.995827] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10914 23:56:36.575024 <6>[ 10.998407] remoteproc remoteproc0: scp is available
10915 23:56:36.581437 <6>[ 10.998546] remoteproc remoteproc0: powering up scp
10916 23:56:36.587905 <6>[ 10.998553] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10917 23:56:36.594316 <6>[ 10.998586] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10918 23:56:36.604373 [[0;32m OK [<3>[ 11.038236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10919 23:56:36.611449 0m] Started [0;<6>[ 11.041198] mc: Linux media interface: v0.10
10920 23:56:36.618433 1;39msystemd-tmp<3>[ 11.046906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 23:56:36.628227 files-c… Clean<3>[ 11.062127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 23:56:36.638202 up of Temporary <4>[ 11.064184] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10923 23:56:36.644708 <4>[ 11.064184] Fallback method does not support PEC.
10924 23:56:36.645274 Directories.
10925 23:56:36.654587 <3>[ 11.081326] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10926 23:56:36.661745 <4>[ 11.091307] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10927 23:56:36.668699 <3>[ 11.096221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 23:56:36.678186 <3>[ 11.104101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 23:56:36.685049 <4>[ 11.107464] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10930 23:56:36.691667 <3>[ 11.111510] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 23:56:36.702072 <3>[ 11.111533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10932 23:56:36.708343 <3>[ 11.111540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10933 23:56:36.719315 <3>[ 11.111690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10934 23:56:36.725269 <6>[ 11.119953] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10935 23:56:36.732091 <6>[ 11.119955] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10936 23:56:36.738867 <6>[ 11.119968] remoteproc remoteproc0: remote processor scp is now up
10937 23:56:36.745389 <6>[ 11.128050] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10938 23:56:36.752675 <3>[ 11.135767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10939 23:56:36.762072 <6>[ 11.136861] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10940 23:56:36.772288 <6>[ 11.138759] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10941 23:56:36.775925 <6>[ 11.143854] pci_bus 0000:00: root bus resource [bus 00-ff]
10942 23:56:36.785412 <3>[ 11.151907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 23:56:36.792721 <3>[ 11.151910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10944 23:56:36.802529 <3>[ 11.151943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 23:56:36.808692 <6>[ 11.160006] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10946 23:56:36.816149 <3>[ 11.168500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 23:56:36.822565 <3>[ 11.168503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 23:56:36.832832 <3>[ 11.168506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 23:56:36.843718 <6>[ 11.175552] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10950 23:56:36.850179 <3>[ 11.181965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10951 23:56:36.857037 <3>[ 11.181980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10952 23:56:36.864248 <6>[ 11.188965] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10953 23:56:36.874721 <6>[ 11.196233] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10954 23:56:36.883933 <3>[ 11.196524] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 23:56:36.894476 <6>[ 11.196816] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10956 23:56:36.901070 <3>[ 11.197175] power_supply sbs-5-000b: driver failed to report `status' property: -6
10957 23:56:36.907855 <6>[ 11.205443] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10958 23:56:36.917332 <6>[ 11.213751] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10959 23:56:36.920586 <6>[ 11.219513] pci 0000:00:00.0: supports D1 D2
10960 23:56:36.927763 <6>[ 11.219517] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10961 23:56:36.938093 <6>[ 11.220497] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10962 23:56:36.944370 <6>[ 11.244937] videodev: Linux video capture interface: v2.00
10963 23:56:36.947718 <6>[ 11.251556] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10964 23:56:36.955100 <6>[ 11.251847] Bluetooth: Core ver 2.22
10965 23:56:36.958570 <6>[ 11.251927] NET: Registered PF_BLUETOOTH protocol family
10966 23:56:36.965213 <6>[ 11.251928] Bluetooth: HCI device and connection manager initialized
10967 23:56:36.971493 <6>[ 11.251943] Bluetooth: HCI socket layer initialized
10968 23:56:36.975360 <6>[ 11.251947] Bluetooth: L2CAP socket layer initialized
10969 23:56:36.981930 <6>[ 11.251955] Bluetooth: SCO socket layer initialized
10970 23:56:36.988667 <3>[ 11.269692] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 23:56:36.998267 <3>[ 11.272279] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10972 23:56:37.005121 <6>[ 11.275411] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10973 23:56:37.015548 <3>[ 11.284580] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 23:56:37.022427 <6>[ 11.319588] usbcore: registered new interface driver btusb
10975 23:56:37.032494 <4>[ 11.320070] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10976 23:56:37.038794 <3>[ 11.320080] Bluetooth: hci0: Failed to load firmware file (-2)
10977 23:56:37.041981 <3>[ 11.320084] Bluetooth: hci0: Failed to set up firmware (-2)
10978 23:56:37.052537 <4>[ 11.320088] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10979 23:56:37.063062 <3>[ 11.321434] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 23:56:37.069382 <6>[ 11.326593] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10981 23:56:37.076318 <6>[ 11.337680] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10982 23:56:37.083299 <6>[ 11.343445] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10983 23:56:37.089889 <6>[ 11.343570] pci 0000:01:00.0: supports D1 D2
10984 23:56:37.096741 <6>[ 11.344128] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10985 23:56:37.106928 <6>[ 11.352449] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10986 23:56:37.113512 <6>[ 11.360209] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10987 23:56:37.123478 <3>[ 11.368981] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 23:56:37.130969 <6>[ 11.370431] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10989 23:56:37.138489 <6>[ 11.370464] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10990 23:56:37.148511 <6>[ 11.370467] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10991 23:56:37.153896 <6>[ 11.370477] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10992 23:56:37.160757 <6>[ 11.370491] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10993 23:56:37.171239 <6>[ 11.370504] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10994 23:56:37.174573 <6>[ 11.370516] pci 0000:00:00.0: PCI bridge to [bus 01]
10995 23:56:37.183712 <6>[ 11.370522] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10996 23:56:37.191160 <6>[ 11.370659] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10997 23:56:37.197180 <6>[ 11.371163] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10998 23:56:37.201116 <6>[ 11.371560] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10999 23:56:37.207362 <6>[ 11.372472] usbcore: registered new interface driver uvcvideo
11000 23:56:37.217607 <3>[ 11.402507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 23:56:37.223679 <6>[ 11.441591] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11002 23:56:37.233671 <3>[ 11.462394] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 23:56:37.240754 <6>[ 11.463885] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11004 23:56:37.246842 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11005 23:56:37.267685 [[0;32m OK [<6>[ 11.703389] mt7921e 0000:01:00.0: ASIC revision: 79610010
11006 23:56:37.274713 0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11007 23:56:37.292963 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11008 23:56:37.309926 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11009 23:56:37.325329 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11010 23:56:37.332659 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11011 23:56:37.370316 <6>[ 11.805090] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11012 23:56:37.373575 <6>[ 11.805090]
11013 23:56:37.398480 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11014 23:56:37.427435 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11015 23:56:37.451732 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11016 23:56:37.473244 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11017 23:56:37.506410 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11018 23:56:37.562381 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11019 23:56:37.583940 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11020 23:56:37.600282 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11021 23:56:37.617389 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11022 23:56:37.639123 <6>[ 12.073950] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11023 23:56:37.655476 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11024 23:56:37.678293 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11025 23:56:37.694848 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11026 23:56:37.712079 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11027 23:56:37.728356 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11028 23:56:37.791550 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11029 23:56:37.817133 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11030 23:56:37.842913 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11031 23:56:37.915634 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11032 23:56:37.935627 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11033 23:56:37.961596 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11034 23:56:37.993733
11035 23:56:37.997638 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11036 23:56:37.998161
11037 23:56:38.000561 debian-bookworm-arm64 login: root (automatic login)
11038 23:56:38.001125
11039 23:56:38.013743 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Wed May 29 23:36:28 UTC 2024 aarch64
11040 23:56:38.014342
11041 23:56:38.020957 The programs included with the Debian GNU/Linux system are free software;
11042 23:56:38.027471 the exact distribution terms for each program are described in the
11043 23:56:38.030757 individual files in /usr/share/doc/*/copyright.
11044 23:56:38.031176
11045 23:56:38.037500 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11046 23:56:38.040299 permitted by applicable law.
11047 23:56:38.041661 Matched prompt #10: / #
11049 23:56:38.042650 Setting prompt string to ['/ #']
11050 23:56:38.043074 end: 2.2.5.1 login-action (duration 00:00:13) [common]
11052 23:56:38.044028 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
11053 23:56:38.044469 start: 2.2.6 expect-shell-connection (timeout 00:02:58) [common]
11054 23:56:38.044818 Setting prompt string to ['/ #']
11055 23:56:38.045194 Forcing a shell prompt, looking for ['/ #']
11057 23:56:38.095992 / #
11058 23:56:38.096573 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11059 23:56:38.097071 Waiting using forced prompt support (timeout 00:02:30)
11060 23:56:38.102227
11061 23:56:38.102982 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11062 23:56:38.103437 start: 2.2.7 export-device-env (timeout 00:02:58) [common]
11063 23:56:38.103936 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11064 23:56:38.104364 end: 2.2 depthcharge-retry (duration 00:02:02) [common]
11065 23:56:38.104786 end: 2 depthcharge-action (duration 00:02:02) [common]
11066 23:56:38.105266 start: 3 lava-test-retry (timeout 00:07:37) [common]
11067 23:56:38.105756 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
11068 23:56:38.106145 Using namespace: common
11070 23:56:38.207195 / # #
11071 23:56:38.207798 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11072 23:56:38.214048 #
11073 23:56:38.214893 Using /lava-14084372
11075 23:56:38.315933 / # export SHELL=/bin/sh
11076 23:56:38.322448 export SHELL=/bin/sh
11078 23:56:38.424380 / # . /lava-14084372/environment
11079 23:56:38.431195 . /lava-14084372/environment
11081 23:56:38.532839 / # /lava-14084372/bin/lava-test-runner /lava-14084372/0
11082 23:56:38.533526 Test shell timeout: 10s (minimum of the action and connection timeout)
11083 23:56:38.535262 /lava-14084372/bin/lava-test-runner /lava-14084372/0<6>[ 12.943335] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11084 23:56:38.539206
11085 23:56:38.585632 + export TESTRUN_ID=0_v4l2-compliance-uvc
11086 23:56:38.586933 + cd /lava-14084372/0/tests/0_v4l2-compliance-uvc
11087 23:56:38.587403 + cat uuid
11088 23:56:38.590683 + UUID=14084372_1.5.2.3.1
11089 23:56:38.591240 + set +x
11090 23:56:38.597418 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14084372_1.5.2.3.1>
11091 23:56:38.598256 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14084372_1.5.2.3.1
11092 23:56:38.598669 Starting test lava.0_v4l2-compliance-uvc (14084372_1.5.2.3.1)
11093 23:56:38.599101 Skipping test definition patterns.
11094 23:56:38.600026 + /usr/bin/v4l2-parser.sh -d uvcvideo
11095 23:56:38.606952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11096 23:56:38.607497 device: /dev/video1
11097 23:56:38.608128 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11099 23:56:45.225056 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11100 23:56:45.237734 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11101 23:56:45.249030
11102 23:56:45.262791 Compliance test for uvcvideo device /dev/video1:
11103 23:56:45.273199
11104 23:56:45.282913 Driver Info:
11105 23:56:45.293133 Driver name : uvcvideo
11106 23:56:45.307795 Card type : HD User Facing: HD User Facing
11107 23:56:45.318906 Bus info : usb-11200000.usb-1.4.1
11108 23:56:45.326750 Driver version : 6.1.91
11109 23:56:45.336664 Capabilities : 0x84a00001
11110 23:56:45.349897 Metadata Capture
11111 23:56:45.361454 Streaming
11112 23:56:45.371391 Extended Pix Format
11113 23:56:45.382336 Device Capabilities
11114 23:56:45.392961 Device Caps : 0x04200001
11115 23:56:45.406435 Streaming
11116 23:56:45.421084 Extended Pix Format
11117 23:56:45.432502 Media Driver Info:
11118 23:56:45.446831 Driver name : uvcvideo
11119 23:56:45.460797 Model : HD User Facing: HD User Facing
11120 23:56:45.471933 Serial : 200901010001
11121 23:56:45.485844 Bus info : usb-11200000.usb-1.4.1
11122 23:56:45.497333 Media version : 6.1.91
11123 23:56:45.512028 Hardware revision: 0x00009758 (38744)
11124 23:56:45.522929 Driver version : 6.1.91
11125 23:56:45.535923 Interface Info:
11126 23:56:45.550106 <LAVA_SIGNAL_TESTSET START Interface-Info>
11127 23:56:45.550894 Received signal: <TESTSET> START Interface-Info
11128 23:56:45.551324 Starting test_set Interface-Info
11129 23:56:45.553238 ID : 0x03000002
11130 23:56:45.559645 Type : V4L Video
11131 23:56:45.570645 Entity Info:
11132 23:56:45.578168 <LAVA_SIGNAL_TESTSET STOP>
11133 23:56:45.579008 Received signal: <TESTSET> STOP
11134 23:56:45.579435 Closing test_set Interface-Info
11135 23:56:45.587893 <LAVA_SIGNAL_TESTSET START Entity-Info>
11136 23:56:45.588754 Received signal: <TESTSET> START Entity-Info
11137 23:56:45.589269 Starting test_set Entity-Info
11138 23:56:45.590691 ID : 0x00000001 (1)
11139 23:56:45.600635 Name : HD User Facing: HD User Facing
11140 23:56:45.609343 Function : V4L2 I/O
11141 23:56:45.623367 Flags : default
11142 23:56:45.632935 Pad 0x01000007 : 0: Sink
11143 23:56:45.655432 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11144 23:56:45.659344
11145 23:56:45.668776 Required ioctls:
11146 23:56:45.677671 <LAVA_SIGNAL_TESTSET STOP>
11147 23:56:45.678499 Received signal: <TESTSET> STOP
11148 23:56:45.678858 Closing test_set Entity-Info
11149 23:56:45.689331 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11150 23:56:45.690083 Received signal: <TESTSET> START Required-ioctls
11151 23:56:45.690437 Starting test_set Required-ioctls
11152 23:56:45.692720 test MC information (see 'Media Driver Info' above): OK
11153 23:56:45.717699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11154 23:56:45.718514 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11156 23:56:45.721150 test VIDIOC_QUERYCAP: OK
11157 23:56:45.739667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11158 23:56:45.740473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11160 23:56:45.742566 test invalid ioctls: OK
11161 23:56:45.767260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11162 23:56:45.767822
11163 23:56:45.768468 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11165 23:56:45.777362 Allow for multiple opens:
11166 23:56:45.785277 <LAVA_SIGNAL_TESTSET STOP>
11167 23:56:45.786141 Received signal: <TESTSET> STOP
11168 23:56:45.786566 Closing test_set Required-ioctls
11169 23:56:45.795725 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11170 23:56:45.796584 Received signal: <TESTSET> START Allow-for-multiple-opens
11171 23:56:45.797063 Starting test_set Allow-for-multiple-opens
11172 23:56:45.798866 test second /dev/video1 open: OK
11173 23:56:45.821903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video1-open RESULT=pass>
11174 23:56:45.822754 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video1-open RESULT=pass
11176 23:56:45.825154 test VIDIOC_QUERYCAP: OK
11177 23:56:45.848814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11178 23:56:45.849727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11180 23:56:45.851865 test VIDIOC_G/S_PRIORITY: OK
11181 23:56:45.878476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11182 23:56:45.879338 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11184 23:56:45.881972 test for unlimited opens: OK
11185 23:56:45.906244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11186 23:56:45.906821
11187 23:56:45.907588 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11189 23:56:45.915639 Debug ioctls:
11190 23:56:45.926078 <LAVA_SIGNAL_TESTSET STOP>
11191 23:56:45.926925 Received signal: <TESTSET> STOP
11192 23:56:45.927340 Closing test_set Allow-for-multiple-opens
11193 23:56:45.936314 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11194 23:56:45.937136 Received signal: <TESTSET> START Debug-ioctls
11195 23:56:45.937561 Starting test_set Debug-ioctls
11196 23:56:45.939697 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11197 23:56:45.961036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11198 23:56:45.961890 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11200 23:56:45.967796 test VIDIOC_LOG_STATUS: OK (Not Supported)
11201 23:56:45.984706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11202 23:56:45.985325
11203 23:56:45.986080 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11205 23:56:45.997133 Input ioctls:
11206 23:56:46.003512 <LAVA_SIGNAL_TESTSET STOP>
11207 23:56:46.004370 Received signal: <TESTSET> STOP
11208 23:56:46.004793 Closing test_set Debug-ioctls
11209 23:56:46.013672 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11210 23:56:46.014519 Received signal: <TESTSET> START Input-ioctls
11211 23:56:46.014944 Starting test_set Input-ioctls
11212 23:56:46.017064 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11213 23:56:46.045626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11214 23:56:46.046461 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11216 23:56:46.048505 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11217 23:56:46.067887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11218 23:56:46.068785 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11220 23:56:46.073683 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11221 23:56:46.092225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11222 23:56:46.093108 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11224 23:56:46.098211 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11225 23:56:46.120555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11226 23:56:46.121461 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11228 23:56:46.123571 test VIDIOC_G/S/ENUMINPUT: OK
11229 23:56:46.147632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11230 23:56:46.148503 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11232 23:56:46.150816 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11233 23:56:46.172099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11234 23:56:46.173061 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11236 23:56:46.174922 Inputs: 1 Audio Inputs: 0 Tuners: 0
11237 23:56:46.187269
11238 23:56:46.205659 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11239 23:56:46.229291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11240 23:56:46.230176 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11242 23:56:46.235732 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11243 23:56:46.254714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11244 23:56:46.255583 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11246 23:56:46.260498 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11247 23:56:46.283265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11248 23:56:46.284164 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11250 23:56:46.289320 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11251 23:56:46.310876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11252 23:56:46.311744 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11254 23:56:46.317329 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11255 23:56:46.336622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11256 23:56:46.337232
11257 23:56:46.337988 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11259 23:56:46.355564 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11260 23:56:46.376502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11261 23:56:46.377378 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11263 23:56:46.382774 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11264 23:56:46.405466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11265 23:56:46.406321 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11267 23:56:46.408158 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11268 23:56:46.426522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11269 23:56:46.427384 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11271 23:56:46.430012 test VIDIOC_G/S_EDID: OK (Not Supported)
11272 23:56:46.456445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11273 23:56:46.457039
11274 23:56:46.457797 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11276 23:56:46.469040 Control ioctls (Input 0):
11277 23:56:46.476720 <LAVA_SIGNAL_TESTSET STOP>
11278 23:56:46.477691 Received signal: <TESTSET> STOP
11279 23:56:46.478136 Closing test_set Input-ioctls
11280 23:56:46.485693 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11281 23:56:46.486541 Received signal: <TESTSET> START Control-ioctls-Input-0
11282 23:56:46.486976 Starting test_set Control-ioctls-Input-0
11283 23:56:46.489224 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11284 23:56:46.517911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11285 23:56:46.518490 test VIDIOC_QUERYCTRL: OK
11286 23:56:46.519131 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11288 23:56:46.538305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11289 23:56:46.539149 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11291 23:56:46.541770 test VIDIOC_G/S_CTRL: OK
11292 23:56:46.563360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11293 23:56:46.564166 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11295 23:56:46.566707 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11296 23:56:46.589280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11297 23:56:46.590076 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11299 23:56:46.598359 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11300 23:56:46.625889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11301 23:56:46.626714 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11303 23:56:46.629674 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11304 23:56:46.648230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11305 23:56:46.649106 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11307 23:56:46.652293 Standard Controls: 16 Private Controls: 0
11308 23:56:46.657980
11309 23:56:46.669330 Format ioctls (Input 0):
11310 23:56:46.676569 <LAVA_SIGNAL_TESTSET STOP>
11311 23:56:46.677457 Received signal: <TESTSET> STOP
11312 23:56:46.677851 Closing test_set Control-ioctls-Input-0
11313 23:56:46.686475 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11314 23:56:46.687294 Received signal: <TESTSET> START Format-ioctls-Input-0
11315 23:56:46.687684 Starting test_set Format-ioctls-Input-0
11316 23:56:46.689714 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11317 23:56:46.717958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11318 23:56:46.718768 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11320 23:56:46.721133 test VIDIOC_G/S_PARM: OK
11321 23:56:46.743863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11322 23:56:46.744780 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11324 23:56:46.747260 test VIDIOC_G_FBUF: OK (Not Supported)
11325 23:56:46.768297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11326 23:56:46.769135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11328 23:56:46.771985 test VIDIOC_G_FMT: OK
11329 23:56:46.794249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11330 23:56:46.795144 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11332 23:56:46.797073 test VIDIOC_TRY_FMT: OK
11333 23:56:46.819718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11334 23:56:46.820383 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11336 23:56:46.826384 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11337 23:56:46.831545 test VIDIOC_S_FMT: OK
11338 23:56:46.860448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11339 23:56:46.861233 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11341 23:56:46.864272 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11342 23:56:46.884439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11343 23:56:46.885196 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11345 23:56:46.888158 test Cropping: OK (Not Supported)
11346 23:56:46.914894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11347 23:56:46.915704 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11349 23:56:46.918077 test Composing: OK (Not Supported)
11350 23:56:46.940971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11351 23:56:46.941873 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11353 23:56:46.943155 test Scaling: OK (Not Supported)
11354 23:56:46.965366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11355 23:56:46.965921
11356 23:56:46.966554 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11358 23:56:46.975313 Codec ioctls (Input 0):
11359 23:56:46.982055 <LAVA_SIGNAL_TESTSET STOP>
11360 23:56:46.982875 Received signal: <TESTSET> STOP
11361 23:56:46.983311 Closing test_set Format-ioctls-Input-0
11362 23:56:46.991231 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11363 23:56:46.992063 Received signal: <TESTSET> START Codec-ioctls-Input-0
11364 23:56:46.992457 Starting test_set Codec-ioctls-Input-0
11365 23:56:46.994421 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11366 23:56:47.015830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11367 23:56:47.016671 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11369 23:56:47.022380 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11370 23:56:47.042449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11371 23:56:47.043280 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11373 23:56:47.048430 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11374 23:56:47.071088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11375 23:56:47.071632
11376 23:56:47.072264 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11378 23:56:47.081662 Buffer ioctls (Input 0):
11379 23:56:47.090649 <LAVA_SIGNAL_TESTSET STOP>
11380 23:56:47.091479 Received signal: <TESTSET> STOP
11381 23:56:47.091882 Closing test_set Codec-ioctls-Input-0
11382 23:56:47.101159 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11383 23:56:47.101980 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11384 23:56:47.102377 Starting test_set Buffer-ioctls-Input-0
11385 23:56:47.103900 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11386 23:56:47.130166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11387 23:56:47.131000 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11389 23:56:47.132830 test CREATE_BUFS maximum buffers: OK
11390 23:56:47.154734 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11392 23:56:47.157654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11393 23:56:47.158210 test VIDIOC_EXPBUF: OK
11394 23:56:47.177584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11395 23:56:47.178391 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11397 23:56:47.181247 test Requests: OK (Not Supported)
11398 23:56:47.210251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11399 23:56:47.210817
11400 23:56:47.211528 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11402 23:56:47.219795 Test input 0:
11403 23:56:47.231185
11404 23:56:47.241327 Streaming ioctls:
11405 23:56:47.251647 <LAVA_SIGNAL_TESTSET STOP>
11406 23:56:47.252480 Received signal: <TESTSET> STOP
11407 23:56:47.252877 Closing test_set Buffer-ioctls-Input-0
11408 23:56:47.262450 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11409 23:56:47.263293 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11410 23:56:47.263687 Starting test_set Streaming-ioctls_Test-input-0
11411 23:56:47.265730 test read/write: OK (Not Supported)
11412 23:56:47.287553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11413 23:56:47.288420 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11415 23:56:47.291119 test blocking wait: OK
11416 23:56:47.312095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11417 23:56:47.312936 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11419 23:56:47.318411 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11420 23:56:47.322611 test MMAP (no poll): FAIL
11421 23:56:47.351847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11422 23:56:47.352693 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11424 23:56:47.357945 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11425 23:56:47.362299 test MMAP (select): FAIL
11426 23:56:47.387328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11427 23:56:47.388143 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11429 23:56:47.393715 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11430 23:56:47.397779 test MMAP (epoll): FAIL
11431 23:56:47.423477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11432 23:56:47.424043
11433 23:56:47.424687 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11435 23:56:47.437334
11436 23:56:47.624951
11437 23:56:47.633611 test USERPTR (no poll): OK
11438 23:56:47.658695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11439 23:56:47.659218
11440 23:56:47.659821 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11442 23:56:47.673283
11443 23:56:47.856484
11444 23:56:47.864530 test USERPTR (select): OK
11445 23:56:47.892763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11446 23:56:47.893719 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11448 23:56:47.895913 test DMABUF: Cannot test, specify --expbuf-device
11449 23:56:47.904322
11450 23:56:47.920886 Total for uvcvideo device /dev/video1: 54, Succeeded: 51, Failed: 3, Warnings: 3
11451 23:56:47.925796 <LAVA_TEST_RUNNER EXIT>
11452 23:56:47.926701 ok: lava_test_shell seems to have completed
11453 23:56:47.927173 Marking unfinished test run as failed
11455 23:56:47.933760 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video1-open:
result: pass
set: Allow-for-multiple-opens
11456 23:56:47.934453 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11457 23:56:47.934936 end: 3 lava-test-retry (duration 00:00:10) [common]
11458 23:56:47.935432 start: 4 finalize (timeout 00:07:27) [common]
11459 23:56:47.935950 start: 4.1 power-off (timeout 00:00:30) [common]
11460 23:56:47.937238 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11461 23:56:48.049292 >> Command sent successfully.
11462 23:56:48.052473 Returned 0 in 0 seconds
11463 23:56:48.153303 end: 4.1 power-off (duration 00:00:00) [common]
11465 23:56:48.154872 start: 4.2 read-feedback (timeout 00:07:27) [common]
11466 23:56:48.156196 Listened to connection for namespace 'common' for up to 1s
11467 23:56:49.156815 Finalising connection for namespace 'common'
11468 23:56:49.157606 Disconnecting from shell: Finalise
11469 23:56:49.158016 / #
11470 23:56:49.258968 end: 4.2 read-feedback (duration 00:00:01) [common]
11471 23:56:49.259755 end: 4 finalize (duration 00:00:01) [common]
11472 23:56:49.260366 Cleaning after the job
11473 23:56:49.260887 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/ramdisk
11474 23:56:49.281550 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/kernel
11475 23:56:49.306967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/dtb
11476 23:56:49.307254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14084372/tftp-deploy-pcqix4nj/modules
11477 23:56:49.314320 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14084372
11478 23:56:49.378174 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14084372
11479 23:56:49.378342 Job finished correctly