[Enter `^Ec?' for help] [DL] 00000000 00000000 010701 F0: 102B 0000 F3: 1006 0033 [0200] F3: 4001 00E0 [0200] F3: 0000 0000 V0: 0000 0000 [0001] 00: 1027 0002 01: 0000 0000 BP: 0C00 0251 [0000] G0: 1182 0000 EC: 0004 0000 [0001] S7: 0000 0000 [0000] CC: 0000 0000 [0001] T0: 0000 00DB [000F] Jump to BL coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception WDT: Last reset was cold boot SPI0(PAD0) initialized at 992727 Hz FMAP: area RW_NVRAM found @ 554000 (8192 bytes) Manufacturer: ef SF: Detected W25Q64DW with sector size 0x1000, total 0x800000 Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 19 00 00 08 00 00 00 in-data: a2 e0 47 00 13 00 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 Phase 1 FMAP: area GBB found @ 3f5000 (12032 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 VB2:vb2_check_recovery() Recovery was requested manually VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0 Recovery requested (1009000e) tlcl_extend: response is 0 tlcl_extend: response is 0 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xea6b, sec=0x2020 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a [RTC]rtc_get_frequency_meter,134: input=0xf, output=860 [RTC]rtc_get_frequency_meter,134: input=0x7, output=731 [RTC]rtc_get_frequency_meter,134: input=0xb, output=799 [RTC]rtc_get_frequency_meter,134: input=0x9, output=765 [RTC]rtc_get_frequency_meter,134: input=0xa, output=783 [RTC]rtc_get_frequency_meter,134: input=0xa, output=782 [RTC]rtc_get_frequency_meter,134: input=0xb, output=800 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xea6b [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 19 00 00 08 00 00 00 in-data: a2 e0 47 00 13 00 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 Skip loading cached calibration data out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 ADC[3]: Raw value=1037476 ID=8 Manufacturer: ef SF: Detected W25Q64DW with sector size 0x1000, total 0x800000 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB' CBFS: Found @ offset 3c880 size 4b DRAM-K: Full Calibration FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/dram' CBFS: Found @ offset 24b00 size 12268 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps ddr_geometry: 1, config: 0x0 header.status = 0x0 header.magic = 0x44524d4b (expected: 0x44524d4b) header.version = 0x5 (expected: 0x5) header.size = 0x8f0 (expected: 0x8f0) header.config = 0x0 header.flags = 0x0 header.checksum = 0x0 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5 Set DRAM voltage: vdram1 = 1125000, vddq = 600000 Get DRAM voltage to vdram1 = 1125000, vddq = 600000 ddr_geometry:1 [EMI] new MDL number = 1 dram_cbt_mode_extern: 0 dram_cbt_mode [RK0]: 0, [RK1]: 0 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154] [Bianco] ETT version 0.0.0.1 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6 vSetVcoreByFreq with vcore:762500, freq=1600 [DramcInit] AutoRefreshCKEOff AutoREF OFF DDRPhyPLLSetting-CKEOFF DDRPhyPLLSetting-CKEON Enable WDQS [ModeRegInit_LP4] CH0 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH0 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 match AC timing 3 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0 [MiockJmeterHQA] vSetVcoreByFreq with vcore:762500, freq=1600 MIOCK jitter meter ch=0 1T = (100-18) = 82 dly cells Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 762/100 ps vSetVcoreByFreq with vcore:725000, freq=1200 MIOCK jitter meter ch=0 1T = (95-17) = 78 dly cells Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps vSetVcoreByFreq with vcore:725000, freq=800 MIOCK jitter meter ch=0 1T = (95-17) = 78 dly cells Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 801/100 ps vSetVcoreByFreq with vcore:762500, freq=1600 vSetVcoreByFreq with vcore:762500, freq=1600 K DRVP 1. OCD DRVP=0 CALOUT=0 1. OCD DRVP=1 CALOUT=0 1. OCD DRVP=2 CALOUT=0 1. OCD DRVP=3 CALOUT=0 1. OCD DRVP=4 CALOUT=0 1. OCD DRVP=5 CALOUT=0 1. OCD DRVP=6 CALOUT=0 1. OCD DRVP=7 CALOUT=0 1. OCD DRVP=8 CALOUT=0 1. OCD DRVP=9 CALOUT=1 1. OCD DRVP calibration OK! DRVP=9 K ODTN 3. OCD ODTN=0 ,CALOUT=1 3. OCD ODTN=1 ,CALOUT=1 3. OCD ODTN=2 ,CALOUT=1 3. OCD ODTN=3 ,CALOUT=1 3. OCD ODTN=4 ,CALOUT=1 3. OCD ODTN=5 ,CALOUT=1 3. OCD ODTN=6 ,CALOUT=1 3. OCD ODTN=7 ,CALOUT=0 3. OCD ODTN calibration OK! ODTN=7 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust) K DRVP 1. OCD DRVP=0 CALOUT=0 1. OCD DRVP=1 CALOUT=0 1. OCD DRVP=2 CALOUT=0 1. OCD DRVP=3 CALOUT=0 1. OCD DRVP=4 CALOUT=0 1. OCD DRVP=5 CALOUT=0 1. OCD DRVP=6 CALOUT=0 1. OCD DRVP=7 CALOUT=0 1. OCD DRVP=8 CALOUT=0 1. OCD DRVP=9 CALOUT=0 1. OCD DRVP=10 CALOUT=1 1. OCD DRVP calibration OK! DRVP=10 K ODTN 3. OCD ODTN=0 ,CALOUT=1 3. OCD ODTN=1 ,CALOUT=1 3. OCD ODTN=2 ,CALOUT=1 3. OCD ODTN=3 ,CALOUT=1 3. OCD ODTN=4 ,CALOUT=1 3. OCD ODTN=5 ,CALOUT=1 3. OCD ODTN=6 ,CALOUT=1 3. OCD ODTN=7 ,CALOUT=1 3. OCD ODTN=8 ,CALOUT=1 3. OCD ODTN=9 ,CALOUT=1 3. OCD ODTN=10 ,CALOUT=1 3. OCD ODTN=11 ,CALOUT=1 3. OCD ODTN=12 ,CALOUT=1 3. OCD ODTN=13 ,CALOUT=1 3. OCD ODTN=14 ,CALOUT=0 3. OCD ODTN calibration OK! ODTN=14 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=14 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=14 (After Adjust) [DramcInit] AutoRefreshCKEOff AutoREF OFF DDRPhyPLLSetting-CKEOFF DDRPhyPLLSetting-CKEON Enable WDQS == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [Duty_Offset_Calibration] =========================== B0:0 B1:1 CA:1 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [Duty_Offset_Calibration] =========================== B0:1 B1:2 CA:0 [ModeRegInit_LP4] CH0 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH0 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK0 Write Rank0 MR13 =0x18 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x1a Write Rank0 MR11 =0x0 Write Rank0 MR22 =0x38 Write Rank0 MR14 =0x5d Write Rank0 MR3 =0x30 Write Rank0 MR13 =0x58 Write Rank0 MR12 =0x5d Write Rank0 MR1 =0x56 Write Rank0 MR2 =0x2d Write Rank0 MR11 =0x23 Write Rank0 MR22 =0x34 Write Rank0 MR14 =0x10 Write Rank0 MR3 =0x30 Write Rank0 MR13 =0xd8 [ModeRegInit_LP4] CH1 RK1 Write Rank1 MR13 =0x18 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x1a Write Rank1 MR11 =0x0 Write Rank1 MR22 =0x38 Write Rank1 MR14 =0x5d Write Rank1 MR3 =0x30 Write Rank1 MR13 =0x58 Write Rank1 MR12 =0x5d Write Rank1 MR1 =0x56 Write Rank1 MR2 =0x2d Write Rank1 MR11 =0x23 Write Rank1 MR22 =0x34 Write Rank1 MR14 =0x10 Write Rank1 MR3 =0x30 Write Rank1 MR13 =0xd8 match AC timing 3 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0 DramC Write-DBI off DramC Read-DBI off Write Rank0 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x2d === u2Vref_new: 0x58 --> 0x38 === u2Vref_new: 0x5a --> 0x39 === u2Vref_new: 0x5c --> 0x3c === u2Vref_new: 0x5e --> 0x3d === u2Vref_new: 0x60 --> 0xa0 [CA 0] Center 33 (4~63) winsize 60 [CA 1] Center 34 (5~63) winsize 59 [CA 2] Center 29 (1~57) winsize 57 [CA 3] Center 24 (-3~51) winsize 55 [CA 4] Center 25 (-2~52) winsize 55 [CA 5] Center 29 (2~57) winsize 56 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 762/100 ps CA0 delay=33 (4~63),Diff = 9 PI (11 cell) CA1 delay=34 (5~63),Diff = 10 PI (12 cell) CA2 delay=29 (1~57),Diff = 5 PI (6 cell) CA3 delay=24 (-3~51),Diff = 0 PI (0 cell) CA4 delay=25 (-2~52),Diff = 1 PI (1 cell) CA5 delay=29 (2~57),Diff = 5 PI (6 cell) CA PerBit enable=1, Macro0, CA PI delay=24 === u2Vref_new: 0x56 --> 0x2d Vref(ca) range 1: 22 CS Dly= 10 (41-0-32) Write Rank0 MR13 =0xd8 Write Rank0 MR13 =0xd8 Write Rank0 MR12 =0x56 Write Rank1 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x2d === u2Vref_new: 0x58 --> 0x38 === u2Vref_new: 0x5a --> 0x39 === u2Vref_new: 0x5c --> 0x3c === u2Vref_new: 0x5e --> 0x3d === u2Vref_new: 0x60 --> 0xa0 [CA 0] Center 34 (5~63) winsize 59 [CA 1] Center 34 (6~63) winsize 58 [CA 2] Center 29 (0~58) winsize 59 [CA 3] Center 23 (-4~50) winsize 55 [CA 4] Center 24 (-3~52) winsize 56 [CA 5] Center 30 (1~59) winsize 59 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 762/100 ps CA0 delay=34 (5~63),Diff = 11 PI (14 cell) CA1 delay=34 (6~63),Diff = 11 PI (14 cell) CA2 delay=29 (1~57),Diff = 6 PI (7 cell) CA3 delay=23 (-3~50),Diff = 0 PI (0 cell) CA4 delay=25 (-2~52),Diff = 2 PI (2 cell) CA5 delay=29 (2~57),Diff = 6 PI (7 cell) CA PerBit enable=1, Macro0, CA PI delay=23 === u2Vref_new: 0x56 --> 0x2d Vref(ca) range 1: 22 CS Dly= 11 (42-0-32) Write Rank1 MR13 =0xd8 Write Rank1 MR13 =0xd8 Write Rank1 MR12 =0x56 [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 0 0 25 0 ff 26 0 ff 27 0 ff 28 0 ff 29 0 ff 30 0 ff 31 0 ff 32 0 ff 33 ff ff 34 ff ff 35 ff ff 36 ff ff 37 ff ff 38 ff ff 39 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 33 DQS1 dly: 25 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 28 |2c2c 2c2b |(11 10)(11 11) |(0 0)(1 0)| 0 3 2 0 |201f 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 4 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 28 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0 3 3 0 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 4 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 3 28 |807 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 4 0 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 5, 20) 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (2) [Byte 1] Lead/lag falling Transition (3, 5, 24) 3 5 28 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0 [Byte 1] Lead/lag Transition tap number (2) 3 6 0 |404 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 6, 4) 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 1]First pass (3, 6, 8) 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 5, 24) best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 24) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28) Write Rank0 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 2) best RODT dly(2T, 0.5T) = (2, 2) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxxxxxx xxxxxxxx [MSB] -1, [0] xxxxxxxx xxxxxxxx [MSB] 0, [0] xxxoxoxx xxxxxxxx [MSB] 1, [0] xxxoxoxx xxxoxxxx [MSB] 2, [0] xxxoxoxx xxxoxxxx [MSB] 3, [0] xxxoxooo oxxoxoox [MSB] 4, [0] xxxoxooo ooxoxooo [MSB] 5, [0] xxxoxooo ooxooooo [MSB] 6, [0] xxxoxooo ooxooooo [MSB] 7, [0] xooooooo ooxooooo [MSB] 8, [0] xooooooo oooooooo [MSB] 9, [0] xooooooo oooooooo [MSB] 10, [0] xooooooo oooooooo [MSB] 32, [0] oooxoooo oooooooo [MSB] 33, [0] oooxoooo oooooxoo [MSB] 34, [0] oooxoxxo oooooxxo [MSB] 35, [0] oooxoxxx xooooxxo [MSB] 36, [0] oooxoxxx xooxoxxo [MSB] 37, [0] oooxoxxx xxoxxxxx [MSB] 38, [0] oooxoxxx xxoxxxxx [MSB] 39, [0] oooxoxxx xxoxxxxx [MSB] 40, [0] oooxoxxx xxoxxxxx [MSB] 41, [0] xoxxxxxx xxoxxxxx [MSB] 42, [0] xxxxxxxx xxoxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 25 (11 ~ 40) 30 iDelay=43, Bit 1, Center 24 (7 ~ 41) 35 iDelay=43, Bit 2, Center 23 (7 ~ 40) 34 iDelay=43, Bit 3, Center 15 (0 ~ 31) 32 iDelay=43, Bit 4, Center 23 (7 ~ 40) 34 iDelay=43, Bit 5, Center 16 (0 ~ 33) 34 iDelay=43, Bit 6, Center 18 (3 ~ 33) 31 iDelay=43, Bit 7, Center 18 (3 ~ 34) 32 iDelay=43, Bit 8, Center 18 (3 ~ 34) 32 iDelay=43, Bit 9, Center 20 (4 ~ 36) 33 iDelay=43, Bit 10, Center 25 (8 ~ 42) 35 iDelay=43, Bit 11, Center 18 (1 ~ 35) 35 iDelay=43, Bit 12, Center 20 (5 ~ 36) 32 iDelay=43, Bit 13, Center 17 (3 ~ 32) 30 iDelay=43, Bit 14, Center 18 (3 ~ 33) 31 iDelay=43, Bit 15, Center 20 (4 ~ 36) 33 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =25, DQ1 =24, DQ2 =23, DQ3 =15 DQ4 =23, DQ5 =16, DQ6 =18, DQ7 =18 DQ8 =18, DQ9 =20, DQ10 =25, DQ11 =18 DQ12 =20, DQ13 =17, DQ14 =18, DQ15 =20 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 921~1177 TX Vref Scan disable 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB] 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB] 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB] 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB] 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB] 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB] 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB] 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB] 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB] 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx oxxoxoxx [MSB] 962 |3 6 2|[0] xxxxxxxx oxxoooxx [MSB] 963 |3 6 3|[0] xxxxxxxx ooxoooox [MSB] 964 |3 6 4|[0] xxxxxxxx ooxoooox [MSB] 965 |3 6 5|[0] xxxxxxxx ooxoooox [MSB] 966 |3 6 6|[0] xxxxxxxx ooxooooo [MSB] 967 |3 6 7|[0] xxxxxxxx oooooooo [MSB] 968 |3 6 8|[0] xxxxxxxx oooooooo [MSB] 969 |3 6 9|[0] xxxoxxxx oooooooo [MSB] 970 |3 6 10|[0] xxxoxoox oooooooo [MSB] 971 |3 6 11|[0] xxxoxoox oooooooo [MSB] 972 |3 6 12|[0] xxxoxoox oooooooo [MSB] 973 |3 6 13|[0] xxxooooo oooooooo [MSB] 974 |3 6 14|[0] xxxooooo oooooooo [MSB] 975 |3 6 15|[0] xooooooo oooooooo [MSB] 985 |3 6 25|[0] oooooooo oxxxxxxx [MSB] 986 |3 6 26|[0] oooooooo xxxxxxxx [MSB] 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB] 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB] 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB] 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB] 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB] 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB] 993 |3 6 33|[0] xoxxxxxx xxxxxxxx [MSB] 994 |3 6 34|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=982, DQM PI dly= 982 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22) Byte1, DQ PI dly=973, DQM PI dly= 973 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 13) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 13) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 949~1013 Write Rank0 MR14 =0x0 CH=0, VrefRange= 0, VrefLevel = 0 TX Bit0 (977~994) 18 985, Bit8 (963~982) 20 972, TX Bit1 (977~993) 17 985, Bit9 (966~982) 17 974, TX Bit2 (976~993) 18 984, Bit10 (969~987) 19 978, TX Bit3 (970~986) 17 978, Bit11 (964~982) 19 973, TX Bit4 (976~993) 18 984, Bit12 (966~982) 17 974, TX Bit5 (972~987) 16 979, Bit13 (965~982) 18 973, TX Bit6 (974~988) 15 981, Bit14 (966~983) 18 974, TX Bit7 (977~991) 15 984, Bit15 (968~983) 16 975, Write Rank0 MR14 =0x2 CH=0, VrefRange= 0, VrefLevel = 2 TX Bit0 (977~994) 18 985, Bit8 (962~983) 22 972, TX Bit1 (977~993) 17 985, Bit9 (966~982) 17 974, TX Bit2 (976~993) 18 984, Bit10 (969~988) 20 978, TX Bit3 (970~987) 18 978, Bit11 (963~982) 20 972, TX Bit4 (976~993) 18 984, Bit12 (965~983) 19 974, TX Bit5 (971~988) 18 979, Bit13 (965~982) 18 973, TX Bit6 (973~990) 18 981, Bit14 (966~983) 18 974, TX Bit7 (976~991) 16 983, Bit15 (968~983) 16 975, Write Rank0 MR14 =0x4 CH=0, VrefRange= 0, VrefLevel = 4 TX Bit0 (977~994) 18 985, Bit8 (962~983) 22 972, TX Bit1 (977~993) 17 985, Bit9 (966~983) 18 974, TX Bit2 (976~993) 18 984, Bit10 (968~988) 21 978, TX Bit3 (970~987) 18 978, Bit11 (963~982) 20 972, TX Bit4 (976~994) 19 985, Bit12 (965~983) 19 974, TX Bit5 (971~988) 18 979, Bit13 (965~982) 18 973, TX Bit6 (973~989) 17 981, Bit14 (966~983) 18 974, TX Bit7 (976~991) 16 983, Bit15 (968~983) 16 975, Write Rank0 MR14 =0x6 CH=0, VrefRange= 0, VrefLevel = 6 TX Bit0 (977~995) 19 986, Bit8 (962~983) 22 972, TX Bit1 (976~994) 19 985, Bit9 (965~983) 19 974, TX Bit2 (976~993) 18 984, Bit10 (968~989) 22 978, TX Bit3 (969~987) 19 978, Bit11 (963~982) 20 972, TX Bit4 (975~994) 20 984, Bit12 (964~983) 20 973, TX Bit5 (971~989) 19 980, Bit13 (964~982) 19 973, TX Bit6 (972~990) 19 981, Bit14 (965~984) 20 974, TX Bit7 (976~992) 17 984, Bit15 (968~984) 17 976, Write Rank0 MR14 =0x8 CH=0, VrefRange= 0, VrefLevel = 8 TX Bit0 (977~996) 20 986, Bit8 (962~983) 22 972, TX Bit1 (976~994) 19 985, Bit9 (964~983) 20 973, TX Bit2 (976~994) 19 985, Bit10 (968~989) 22 978, TX Bit3 (969~988) 20 978, Bit11 (962~983) 22 972, TX Bit4 (975~994) 20 984, Bit12 (964~983) 20 973, TX Bit5 (970~990) 21 980, Bit13 (963~983) 21 973, TX Bit6 (971~991) 21 981, Bit14 (965~984) 20 974, TX Bit7 (975~992) 18 983, Bit15 (967~984) 18 975, Write Rank0 MR14 =0xa CH=0, VrefRange= 0, VrefLevel = 10 TX Bit0 (976~996) 21 986, Bit8 (961~984) 24 972, TX Bit1 (976~995) 20 985, Bit9 (964~984) 21 974, TX Bit2 (975~994) 20 984, Bit10 (967~989) 23 978, TX Bit3 (969~989) 21 979, Bit11 (962~983) 22 972, TX Bit4 (974~995) 22 984, Bit12 (964~984) 21 974, TX Bit5 (970~990) 21 980, Bit13 (963~983) 21 973, TX Bit6 (971~991) 21 981, Bit14 (964~985) 22 974, TX Bit7 (975~992) 18 983, Bit15 (967~985) 19 976, Write Rank0 MR14 =0xc CH=0, VrefRange= 0, VrefLevel = 12 TX Bit0 (976~997) 22 986, Bit8 (962~984) 23 973, TX Bit1 (976~995) 20 985, Bit9 (964~984) 21 974, TX Bit2 (975~994) 20 984, Bit10 (967~990) 24 978, TX Bit3 (969~990) 22 979, Bit11 (962~983) 22 972, TX Bit4 (974~995) 22 984, Bit12 (964~984) 21 974, TX Bit5 (970~991) 22 980, Bit13 (962~983) 22 972, TX Bit6 (971~991) 21 981, Bit14 (964~985) 22 974, TX Bit7 (975~993) 19 984, Bit15 (967~985) 19 976, Write Rank0 MR14 =0xe CH=0, VrefRange= 0, VrefLevel = 14 TX Bit0 (976~997) 22 986, Bit8 (961~984) 24 972, TX Bit1 (975~995) 21 985, Bit9 (963~985) 23 974, TX Bit2 (975~995) 21 985, Bit10 (967~990) 24 978, TX Bit3 (969~990) 22 979, Bit11 (961~984) 24 972, TX Bit4 (974~996) 23 985, Bit12 (963~985) 23 974, TX Bit5 (970~991) 22 980, Bit13 (962~984) 23 973, TX Bit6 (970~991) 22 980, Bit14 (963~986) 24 974, TX Bit7 (974~993) 20 983, Bit15 (966~986) 21 976, Write Rank0 MR14 =0x10 CH=0, VrefRange= 0, VrefLevel = 16 TX Bit0 (976~998) 23 987, Bit8 (961~985) 25 973, TX Bit1 (976~995) 20 985, Bit9 (963~985) 23 974, TX Bit2 (975~995) 21 985, Bit10 (967~990) 24 978, TX Bit3 (968~990) 23 979, Bit11 (961~984) 24 972, TX Bit4 (974~996) 23 985, Bit12 (962~985) 24 973, TX Bit5 (969~991) 23 980, Bit13 (962~984) 23 973, TX Bit6 (970~992) 23 981, Bit14 (963~986) 24 974, TX Bit7 (973~993) 21 983, Bit15 (966~986) 21 976, Write Rank0 MR14 =0x12 CH=0, VrefRange= 0, VrefLevel = 18 TX Bit0 (976~998) 23 987, Bit8 (961~985) 25 973, TX Bit1 (975~996) 22 985, Bit9 (962~986) 25 974, TX Bit2 (974~996) 23 985, Bit10 (967~990) 24 978, TX Bit3 (968~991) 24 979, Bit11 (961~984) 24 972, TX Bit4 (973~997) 25 985, Bit12 (962~985) 24 973, TX Bit5 (969~992) 24 980, Bit13 (962~984) 23 973, TX Bit6 (970~993) 24 981, Bit14 (961~987) 27 974, TX Bit7 (973~993) 21 983, Bit15 (966~987) 22 976, Write Rank0 MR14 =0x14 CH=0, VrefRange= 0, VrefLevel = 20 TX Bit0 (975~998) 24 986, Bit8 (961~985) 25 973, TX Bit1 (975~996) 22 985, Bit9 (962~986) 25 974, TX Bit2 (975~996) 22 985, Bit10 (966~990) 25 978, TX Bit3 (968~991) 24 979, Bit11 (961~985) 25 973, TX Bit4 (973~998) 26 985, Bit12 (961~986) 26 973, TX Bit5 (969~992) 24 980, Bit13 (961~985) 25 973, TX Bit6 (969~993) 25 981, Bit14 (962~986) 25 974, TX Bit7 (972~994) 23 983, Bit15 (965~987) 23 976, Write Rank0 MR14 =0x16 CH=0, VrefRange= 0, VrefLevel = 22 TX Bit0 (976~999) 24 987, Bit8 (961~985) 25 973, TX Bit1 (974~997) 24 985, Bit9 (962~986) 25 974, TX Bit2 (974~996) 23 985, Bit10 (966~990) 25 978, TX Bit3 (968~992) 25 980, Bit11 (961~985) 25 973, TX Bit4 (972~998) 27 985, Bit12 (962~986) 25 974, TX Bit5 (969~992) 24 980, Bit13 (961~985) 25 973, TX Bit6 (969~993) 25 981, Bit14 (962~986) 25 974, TX Bit7 (972~995) 24 983, Bit15 (965~989) 25 977, Write Rank0 MR14 =0x18 CH=0, VrefRange= 0, VrefLevel = 24 TX Bit0 (975~999) 25 987, Bit8 (961~985) 25 973, TX Bit1 (974~997) 24 985, Bit9 (962~987) 26 974, TX Bit2 (974~997) 24 985, Bit10 (967~990) 24 978, TX Bit3 (968~992) 25 980, Bit11 (961~984) 24 972, TX Bit4 (973~998) 26 985, Bit12 (961~985) 25 973, TX Bit5 (969~992) 24 980, Bit13 (961~984) 24 972, TX Bit6 (969~993) 25 981, Bit14 (962~985) 24 973, TX Bit7 (971~995) 25 983, Bit15 (965~989) 25 977, Write Rank0 MR14 =0x1a CH=0, VrefRange= 0, VrefLevel = 26 TX Bit0 (975~999) 25 987, Bit8 (961~985) 25 973, TX Bit1 (974~997) 24 985, Bit9 (962~987) 26 974, TX Bit2 (974~998) 25 986, Bit10 (967~990) 24 978, TX Bit3 (968~992) 25 980, Bit11 (961~984) 24 972, TX Bit4 (974~997) 24 985, Bit12 (961~985) 25 973, TX Bit5 (968~992) 25 980, Bit13 (961~984) 24 972, TX Bit6 (969~993) 25 981, Bit14 (962~985) 24 973, TX Bit7 (971~995) 25 983, Bit15 (964~989) 26 976, Write Rank0 MR14 =0x1c CH=0, VrefRange= 0, VrefLevel = 28 TX Bit0 (975~999) 25 987, Bit8 (961~985) 25 973, TX Bit1 (974~997) 24 985, Bit9 (962~987) 26 974, TX Bit2 (974~998) 25 986, Bit10 (967~990) 24 978, TX Bit3 (968~992) 25 980, Bit11 (961~984) 24 972, TX Bit4 (974~997) 24 985, Bit12 (961~985) 25 973, TX Bit5 (968~992) 25 980, Bit13 (961~984) 24 972, TX Bit6 (969~993) 25 981, Bit14 (962~985) 24 973, TX Bit7 (971~995) 25 983, Bit15 (964~989) 26 976, Write Rank0 MR14 =0x1e CH=0, VrefRange= 0, VrefLevel = 30 TX Bit0 (975~999) 25 987, Bit8 (961~985) 25 973, TX Bit1 (974~997) 24 985, Bit9 (962~987) 26 974, TX Bit2 (974~998) 25 986, Bit10 (967~990) 24 978, TX Bit3 (968~992) 25 980, Bit11 (961~984) 24 972, TX Bit4 (974~997) 24 985, Bit12 (961~985) 25 973, TX Bit5 (968~992) 25 980, Bit13 (961~984) 24 972, TX Bit6 (969~993) 25 981, Bit14 (962~985) 24 973, TX Bit7 (971~995) 25 983, Bit15 (964~989) 26 976, TX Vref found, early break! 375< 376 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps u1DelayCellOfst[0]=8 cells (7 PI) u1DelayCellOfst[1]=6 cells (5 PI) u1DelayCellOfst[2]=7 cells (6 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=6 cells (5 PI) u1DelayCellOfst[5]=0 cells (0 PI) u1DelayCellOfst[6]=1 cells (1 PI) u1DelayCellOfst[7]=3 cells (3 PI) Byte0, DQ PI dly=980, DQM PI dly= 983 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20) u1DelayCellOfst[8]=1 cells (1 PI) u1DelayCellOfst[9]=2 cells (2 PI) u1DelayCellOfst[10]=7 cells (6 PI) u1DelayCellOfst[11]=0 cells (0 PI) u1DelayCellOfst[12]=1 cells (1 PI) u1DelayCellOfst[13]=0 cells (0 PI) u1DelayCellOfst[14]=1 cells (1 PI) u1DelayCellOfst[15]=5 cells (4 PI) Byte1, DQ PI dly=972, DQM PI dly= 975 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 12) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 12) Write Rank0 MR14 =0x1a Final TX Range 0 Vref 26 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 695~759 TX Vref Scan disable 695 |2 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 696 |2 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 705 |2 6 1|[0] xxxxxxxx oooooooo [MSB] 706 |2 6 2|[0] xxxxxxxx oooooooo [MSB] 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB] 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB] 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB] 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB] 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB] 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB] 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB] 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB] 731 |2 6 27|[0] oooooooo xxxxxxxx [MSB] 732 |2 6 28|[0] oooooooo xxxxxxxx [MSB] 733 |2 6 29|[0] oooooooo xxxxxxxx [MSB] 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB] 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB] 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB] 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB] 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB] 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB] 740 |2 6 36|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=727, DQM PI dly= 727 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 23) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 23) Byte1, DQ PI dly=717, DQM PI dly= 717 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 13) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 13) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank0 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK0, use_rxtx_scan=0 DATLAT Default: 0xf 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 1 RX Vref found, early break! Final RX Vref 12, apply to both rank0 and 1 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =25, DQ1 =25, DQ2 =24, DQ3 =15 DQ4 =23, DQ5 =16, DQ6 =18, DQ7 =18 DQ8 =18, DQ9 =20, DQ10 =24, DQ11 =16 DQ12 =20, DQ13 =16, DQ14 =18, DQ15 =20 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFF, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xaa, (MSB)MR19= 0x3, tDQSOscB0 = 335 ps tDQSOscB1 = 0 ps CH0_RK0: MR19=0x3, MR18=0xAA, DQSOSC=335, MR23=63, INC=21, DEC=32 Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xaa, (MSB)MR19= 0x3, tDQSOscB0 = 335 ps tDQSOscB1 = 0 ps CH0 RK0: MR19=3, MR18=AA [RankSwap] Rank num 2, (Multi 1), Rank 1 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 0 0 25 0 0 26 0 0 27 0 ff 28 0 ff 29 0 ff 30 0 ff 31 0 ff 32 0 ff 33 0 ff 34 0 ff 35 ff ff 36 ff ff 37 ff ff 38 ff ff 39 ff ff 40 ff ff 41 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 35 DQS1 dly: 27 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank1 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0 3 2 8 |c0b 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 12 |3534 404 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 16 |3534 3030 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 4 12 |707 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 16 |3d3d 707 |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 6, 0) 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (2) [Byte 1] Lead/lag Transition tap number (1) 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(0 0)(0 0)| 0 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 6, 12) 3 6 16 |4646 a0a |(0 0)(11 11) |(0 0)(0 0)| 0 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 1]First pass (3, 6, 20) 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4) best DQS1 dly(2T, 0.5T, PI) = (3, 6, 6) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 6) Write Rank1 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 3) best RODT dly(2T, 0.5T) = (2, 3) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxxxxxx xxxxxxxx [MSB] -1, [0] xxxxxxxx xxxxxxxx [MSB] 0, [0] xxxoxoxx oxxoxoxx [MSB] 1, [0] xxxoxoxx oxxoxoxx [MSB] 2, [0] xxxoxoxx oxxoxoox [MSB] 3, [0] xxxoxooo ooxoooox [MSB] 4, [0] xxxoxooo ooxooooo [MSB] 5, [0] xxxoxooo oooooooo [MSB] 6, [0] xxxoxooo oooooooo [MSB] 7, [0] xooooooo oooooooo [MSB] 8, [0] xooooooo oooooooo [MSB] 9, [0] xooooooo oooooooo [MSB] 33, [0] oooooooo oooooooo [MSB] 34, [0] oooxoooo oooooooo [MSB] 35, [0] oooxooxo oooooxxo [MSB] 36, [0] oooxooxx oooxoxxo [MSB] 37, [0] oooxoxxx xxoxxxxo [MSB] 38, [0] oooxoxxx xxoxxxxo [MSB] 39, [0] oooxoxxx xxoxxxxx [MSB] 40, [0] oooxoxxx xxoxxxxx [MSB] 41, [0] oooxxxxx xxoxxxxx [MSB] 42, [0] xoxxxxxx xxoxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 25 (10 ~ 41) 32 iDelay=43, Bit 1, Center 24 (7 ~ 42) 36 iDelay=43, Bit 2, Center 24 (7 ~ 41) 35 iDelay=43, Bit 3, Center 16 (0 ~ 33) 34 iDelay=43, Bit 4, Center 23 (7 ~ 40) 34 iDelay=43, Bit 5, Center 18 (0 ~ 36) 37 iDelay=43, Bit 6, Center 18 (3 ~ 34) 32 iDelay=43, Bit 7, Center 19 (3 ~ 35) 33 iDelay=43, Bit 8, Center 18 (0 ~ 36) 37 iDelay=43, Bit 9, Center 19 (3 ~ 36) 34 iDelay=43, Bit 10, Center 23 (5 ~ 42) 38 iDelay=43, Bit 11, Center 17 (0 ~ 35) 36 iDelay=43, Bit 12, Center 19 (3 ~ 36) 34 iDelay=43, Bit 13, Center 17 (0 ~ 34) 35 iDelay=43, Bit 14, Center 18 (2 ~ 34) 33 iDelay=43, Bit 15, Center 21 (4 ~ 38) 35 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =25, DQ1 =24, DQ2 =24, DQ3 =16 DQ4 =23, DQ5 =18, DQ6 =18, DQ7 =19 DQ8 =18, DQ9 =19, DQ10 =23, DQ11 =17 DQ12 =19, DQ13 =17, DQ14 =18, DQ15 =21 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 923~1179 TX Vref Scan disable 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB] 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB] 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB] 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB] 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB] 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB] 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB] 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB] 966 |3 6 6|[0] xxxxxxxx xxxoxoxx [MSB] 967 |3 6 7|[0] xxxxxxxx ooxoooox [MSB] 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB] 969 |3 6 9|[0] xxxxxxxx ooxooooo [MSB] 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB] 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB] 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB] 973 |3 6 13|[0] xxxoxxxx oooooooo [MSB] 974 |3 6 14|[0] xxxoxoox oooooooo [MSB] 975 |3 6 15|[0] xxxoxoox oooooooo [MSB] 976 |3 6 16|[0] xxxoxoox oooooooo [MSB] 977 |3 6 17|[0] xoxooooo oooooooo [MSB] 987 |3 6 27|[0] oooooooo oooooxoo [MSB] 988 |3 6 28|[0] oooooooo xooxoxoo [MSB] 989 |3 6 29|[0] oooooooo xxoxxxxo [MSB] 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB] 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB] 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB] 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB] 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB] 995 |3 6 35|[0] oooooxoo xxxxxxxx [MSB] 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB] 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB] 998 |3 6 38|[0] xxoxxxxx xxxxxxxx [MSB] 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=986, DQM PI dly= 986 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26) Byte1, DQ PI dly=977, DQM PI dly= 977 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 953~1017 Write Rank1 MR14 =0x0 CH=0, VrefRange= 0, VrefLevel = 0 TX Bit0 (980~999) 20 989, Bit8 (968~983) 16 975, TX Bit1 (979~998) 20 988, Bit9 (969~983) 15 976, TX Bit2 (979~997) 19 988, Bit10 (973~989) 17 981, TX Bit3 (974~991) 18 982, Bit11 (968~983) 16 975, TX Bit4 (979~997) 19 988, Bit12 (969~984) 16 976, TX Bit5 (977~991) 15 984, Bit13 (968~983) 16 975, TX Bit6 (977~992) 16 984, Bit14 (969~983) 15 976, TX Bit7 (978~993) 16 985, Bit15 (971~986) 16 978, Write Rank1 MR14 =0x2 CH=0, VrefRange= 0, VrefLevel = 2 TX Bit0 (980~999) 20 989, Bit8 (968~984) 17 976, TX Bit1 (978~998) 21 988, Bit9 (969~984) 16 976, TX Bit2 (979~998) 20 988, Bit10 (973~989) 17 981, TX Bit3 (974~992) 19 983, Bit11 (967~983) 17 975, TX Bit4 (979~998) 20 988, Bit12 (968~984) 17 976, TX Bit5 (976~991) 16 983, Bit13 (968~983) 16 975, TX Bit6 (977~992) 16 984, Bit14 (969~984) 16 976, TX Bit7 (978~994) 17 986, Bit15 (971~987) 17 979, Write Rank1 MR14 =0x4 CH=0, VrefRange= 0, VrefLevel = 4 TX Bit0 (980~999) 20 989, Bit8 (968~984) 17 976, TX Bit1 (979~998) 20 988, Bit9 (969~984) 16 976, TX Bit2 (979~998) 20 988, Bit10 (972~989) 18 980, TX Bit3 (973~992) 20 982, Bit11 (968~984) 17 976, TX Bit4 (979~998) 20 988, Bit12 (968~984) 17 976, TX Bit5 (976~991) 16 983, Bit13 (968~983) 16 975, TX Bit6 (976~993) 18 984, Bit14 (968~984) 17 976, TX Bit7 (978~995) 18 986, Bit15 (970~988) 19 979, Write Rank1 MR14 =0x6 CH=0, VrefRange= 0, VrefLevel = 6 TX Bit0 (979~1000) 22 989, Bit8 (968~985) 18 976, TX Bit1 (978~999) 22 988, Bit9 (968~985) 18 976, TX Bit2 (979~998) 20 988, Bit10 (972~989) 18 980, TX Bit3 (973~992) 20 982, Bit11 (967~984) 18 975, TX Bit4 (978~999) 22 988, Bit12 (968~985) 18 976, TX Bit5 (976~992) 17 984, Bit13 (968~984) 17 976, TX Bit6 (976~993) 18 984, Bit14 (968~985) 18 976, TX Bit7 (977~996) 20 986, Bit15 (971~988) 18 979, Write Rank1 MR14 =0x8 CH=0, VrefRange= 0, VrefLevel = 8 TX Bit0 (979~1000) 22 989, Bit8 (967~985) 19 976, TX Bit1 (978~999) 22 988, Bit9 (968~985) 18 976, TX Bit2 (978~998) 21 988, Bit10 (972~990) 19 981, TX Bit3 (973~993) 21 983, Bit11 (967~985) 19 976, TX Bit4 (978~999) 22 988, Bit12 (968~986) 19 977, TX Bit5 (975~992) 18 983, Bit13 (967~984) 18 975, TX Bit6 (975~994) 20 984, Bit14 (968~985) 18 976, TX Bit7 (977~997) 21 987, Bit15 (970~989) 20 979, Write Rank1 MR14 =0xa CH=0, VrefRange= 0, VrefLevel = 10 TX Bit0 (979~1000) 22 989, Bit8 (968~986) 19 977, TX Bit1 (978~999) 22 988, Bit9 (968~986) 19 977, TX Bit2 (978~999) 22 988, Bit10 (971~990) 20 980, TX Bit3 (972~993) 22 982, Bit11 (966~985) 20 975, TX Bit4 (978~999) 22 988, Bit12 (968~986) 19 977, TX Bit5 (975~992) 18 983, Bit13 (967~984) 18 975, TX Bit6 (975~995) 21 985, Bit14 (968~986) 19 977, TX Bit7 (977~997) 21 987, Bit15 (970~989) 20 979, Write Rank1 MR14 =0xc CH=0, VrefRange= 0, VrefLevel = 12 TX Bit0 (978~1000) 23 989, Bit8 (967~986) 20 976, TX Bit1 (978~999) 22 988, Bit9 (968~987) 20 977, TX Bit2 (978~999) 22 988, Bit10 (971~990) 20 980, TX Bit3 (971~994) 24 982, Bit11 (966~986) 21 976, TX Bit4 (978~999) 22 988, Bit12 (968~987) 20 977, TX Bit5 (974~993) 20 983, Bit13 (966~985) 20 975, TX Bit6 (975~995) 21 985, Bit14 (967~986) 20 976, TX Bit7 (977~997) 21 987, Bit15 (969~989) 21 979, Write Rank1 MR14 =0xe CH=0, VrefRange= 0, VrefLevel = 14 TX Bit0 (978~1001) 24 989, Bit8 (967~987) 21 977, TX Bit1 (978~999) 22 988, Bit9 (968~988) 21 978, TX Bit2 (978~999) 22 988, Bit10 (971~990) 20 980, TX Bit3 (971~995) 25 983, Bit11 (966~986) 21 976, TX Bit4 (978~1000) 23 989, Bit12 (967~987) 21 977, TX Bit5 (974~994) 21 984, Bit13 (966~985) 20 975, TX Bit6 (974~996) 23 985, Bit14 (967~987) 21 977, TX Bit7 (976~998) 23 987, Bit15 (969~989) 21 979, Write Rank1 MR14 =0x10 CH=0, VrefRange= 0, VrefLevel = 16 TX Bit0 (978~1001) 24 989, Bit8 (967~988) 22 977, TX Bit1 (978~1000) 23 989, Bit9 (968~988) 21 978, TX Bit2 (978~1000) 23 989, Bit10 (970~991) 22 980, TX Bit3 (970~995) 26 982, Bit11 (966~987) 22 976, TX Bit4 (978~1000) 23 989, Bit12 (967~988) 22 977, TX Bit5 (973~994) 22 983, Bit13 (966~986) 21 976, TX Bit6 (974~997) 24 985, Bit14 (967~988) 22 977, TX Bit7 (977~998) 22 987, Bit15 (969~990) 22 979, Write Rank1 MR14 =0x12 CH=0, VrefRange= 0, VrefLevel = 18 TX Bit0 (978~1001) 24 989, Bit8 (967~988) 22 977, TX Bit1 (977~1000) 24 988, Bit9 (968~989) 22 978, TX Bit2 (978~1000) 23 989, Bit10 (970~991) 22 980, TX Bit3 (971~996) 26 983, Bit11 (966~987) 22 976, TX Bit4 (977~1000) 24 988, Bit12 (967~988) 22 977, TX Bit5 (973~995) 23 984, Bit13 (966~987) 22 976, TX Bit6 (974~998) 25 986, Bit14 (967~988) 22 977, TX Bit7 (976~998) 23 987, Bit15 (969~990) 22 979, Write Rank1 MR14 =0x14 CH=0, VrefRange= 0, VrefLevel = 20 TX Bit0 (978~1002) 25 990, Bit8 (966~988) 23 977, TX Bit1 (977~1000) 24 988, Bit9 (967~989) 23 978, TX Bit2 (978~1000) 23 989, Bit10 (969~991) 23 980, TX Bit3 (970~996) 27 983, Bit11 (966~988) 23 977, TX Bit4 (977~1001) 25 989, Bit12 (967~989) 23 978, TX Bit5 (972~995) 24 983, Bit13 (965~987) 23 976, TX Bit6 (973~998) 26 985, Bit14 (966~989) 24 977, TX Bit7 (976~999) 24 987, Bit15 (969~990) 22 979, Write Rank1 MR14 =0x16 CH=0, VrefRange= 0, VrefLevel = 22 TX Bit0 (978~1002) 25 990, Bit8 (966~988) 23 977, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (977~1000) 24 988, Bit10 (969~991) 23 980, TX Bit3 (970~996) 27 983, Bit11 (965~988) 24 976, TX Bit4 (977~1001) 25 989, Bit12 (966~989) 24 977, TX Bit5 (972~996) 25 984, Bit13 (965~986) 22 975, TX Bit6 (973~998) 26 985, Bit14 (967~989) 23 978, TX Bit7 (976~999) 24 987, Bit15 (968~990) 23 979, Write Rank1 MR14 =0x18 CH=0, VrefRange= 0, VrefLevel = 24 TX Bit0 (977~1003) 27 990, Bit8 (966~988) 23 977, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (977~1001) 25 989, Bit10 (969~991) 23 980, TX Bit3 (970~995) 26 982, Bit11 (966~988) 23 977, TX Bit4 (976~1001) 26 988, Bit12 (966~989) 24 977, TX Bit5 (972~997) 26 984, Bit13 (964~986) 23 975, TX Bit6 (972~998) 27 985, Bit14 (967~988) 22 977, TX Bit7 (975~999) 25 987, Bit15 (968~990) 23 979, Write Rank1 MR14 =0x1a CH=0, VrefRange= 0, VrefLevel = 26 TX Bit0 (977~1003) 27 990, Bit8 (966~988) 23 977, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (977~1001) 25 989, Bit10 (969~991) 23 980, TX Bit3 (970~995) 26 982, Bit11 (966~988) 23 977, TX Bit4 (976~1001) 26 988, Bit12 (966~989) 24 977, TX Bit5 (972~997) 26 984, Bit13 (964~986) 23 975, TX Bit6 (972~998) 27 985, Bit14 (967~988) 22 977, TX Bit7 (975~999) 25 987, Bit15 (968~990) 23 979, Write Rank1 MR14 =0x1c CH=0, VrefRange= 0, VrefLevel = 28 TX Bit0 (977~1003) 27 990, Bit8 (966~988) 23 977, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (977~1001) 25 989, Bit10 (969~991) 23 980, TX Bit3 (970~995) 26 982, Bit11 (966~988) 23 977, TX Bit4 (976~1001) 26 988, Bit12 (966~989) 24 977, TX Bit5 (972~997) 26 984, Bit13 (964~986) 23 975, TX Bit6 (972~998) 27 985, Bit14 (967~988) 22 977, TX Bit7 (975~999) 25 987, Bit15 (968~990) 23 979, Write Rank1 MR14 =0x1e CH=0, VrefRange= 0, VrefLevel = 30 TX Bit0 (977~1003) 27 990, Bit8 (966~988) 23 977, TX Bit1 (977~1001) 25 989, Bit9 (967~989) 23 978, TX Bit2 (977~1001) 25 989, Bit10 (969~991) 23 980, TX Bit3 (970~995) 26 982, Bit11 (966~988) 23 977, TX Bit4 (976~1001) 26 988, Bit12 (966~989) 24 977, TX Bit5 (972~997) 26 984, Bit13 (964~986) 23 975, TX Bit6 (972~998) 27 985, Bit14 (967~988) 22 977, TX Bit7 (975~999) 25 987, Bit15 (968~990) 23 979, TX Vref found, early break! 366< 371 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps u1DelayCellOfst[0]=10 cells (8 PI) u1DelayCellOfst[1]=8 cells (7 PI) u1DelayCellOfst[2]=8 cells (7 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=7 cells (6 PI) u1DelayCellOfst[5]=2 cells (2 PI) u1DelayCellOfst[6]=3 cells (3 PI) u1DelayCellOfst[7]=6 cells (5 PI) Byte0, DQ PI dly=982, DQM PI dly= 986 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22) u1DelayCellOfst[8]=2 cells (2 PI) u1DelayCellOfst[9]=3 cells (3 PI) u1DelayCellOfst[10]=6 cells (5 PI) u1DelayCellOfst[11]=2 cells (2 PI) u1DelayCellOfst[12]=2 cells (2 PI) u1DelayCellOfst[13]=0 cells (0 PI) u1DelayCellOfst[14]=2 cells (2 PI) u1DelayCellOfst[15]=5 cells (4 PI) Byte1, DQ PI dly=975, DQM PI dly= 977 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15) Write Rank1 MR14 =0x18 Final TX Range 0 Vref 24 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 697~761 TX Vref Scan disable 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB] 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB] 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB] 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB] 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB] 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB] 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB] 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB] 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB] 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB] 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB] 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB] 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB] 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB] 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB] 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB] 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB] 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB] 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB] 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB] 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB] 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB] 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=731, DQM PI dly= 731 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27) Byte1, DQ PI dly=720, DQM PI dly= 720 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 16) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 16) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank1 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK1, use_rxtx_scan=0 DATLAT Default: 0x10 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxxxxxx xxxxxxxx [MSB] -1, [0] xxxoxxxx xxxxxxxx [MSB] 0, [0] xxxoxoxx xxxoxoxx [MSB] 1, [0] xxxoxoxx oxxoxoxx [MSB] 2, [0] xxxoxoxx ooxoooox [MSB] 3, [0] xxxoxooo ooxoooox [MSB] 4, [0] xxxoxooo ooxooooo [MSB] 5, [0] xxxoxooo ooxooooo [MSB] 6, [0] xxxooooo oooooooo [MSB] 7, [0] xoxooooo oooooooo [MSB] 8, [0] xooooooo oooooooo [MSB] 33, [0] oooxoooo oooooooo [MSB] 34, [0] oooxoooo oooooxoo [MSB] 35, [0] oooxoooo oooxoxoo [MSB] 36, [0] oooxoxoo oooxoxxo [MSB] 37, [0] oooxoxxx xooxoxxo [MSB] 38, [0] oooxoxxx xxoxxxxx [MSB] 39, [0] oooxoxxx xxoxxxxx [MSB] 40, [0] oooxoxxx xxoxxxxx [MSB] 41, [0] oooxxxxx xxoxxxxx [MSB] 42, [0] oooxxxxx xxoxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 25 (9 ~ 42) 34 iDelay=43, Bit 1, Center 24 (7 ~ 42) 36 iDelay=43, Bit 2, Center 25 (8 ~ 42) 35 iDelay=43, Bit 3, Center 15 (-1 ~ 32) 34 iDelay=43, Bit 4, Center 23 (6 ~ 40) 35 iDelay=43, Bit 5, Center 17 (0 ~ 35) 36 iDelay=43, Bit 6, Center 19 (3 ~ 36) 34 iDelay=43, Bit 7, Center 19 (3 ~ 36) 34 iDelay=43, Bit 8, Center 18 (1 ~ 36) 36 iDelay=43, Bit 9, Center 19 (2 ~ 37) 36 iDelay=43, Bit 10, Center 24 (6 ~ 42) 37 iDelay=43, Bit 11, Center 17 (0 ~ 34) 35 iDelay=43, Bit 12, Center 19 (2 ~ 37) 36 iDelay=43, Bit 13, Center 16 (0 ~ 33) 34 iDelay=43, Bit 14, Center 18 (2 ~ 35) 34 iDelay=43, Bit 15, Center 20 (4 ~ 37) 34 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 18 DQ Delay: DQ0 =25, DQ1 =24, DQ2 =25, DQ3 =15 DQ4 =23, DQ5 =17, DQ6 =19, DQ7 =19 DQ8 =18, DQ9 =19, DQ10 =24, DQ11 =17 DQ12 =19, DQ13 =16, DQ14 =18, DQ15 =20 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFE, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0x78, (MSB)MR19= 0x3, tDQSOscB0 = 354 ps tDQSOscB1 = 0 ps CH0_RK1: MR19=0x3, MR18=0x78, DQSOSC=354, MR23=63, INC=19, DEC=29 Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0x7c, (MSB)MR19= 0x3, tDQSOscB0 = 353 ps tDQSOscB1 = 0 ps CH0 RK1: MR19=3, MR18=7C [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 Rank: 0 best DQS0 dly(2T, 0.5T) = (2, 5) best DQS1 dly(2T, 0.5T) = (2, 5) best DQS0 P1 dly(2T, 0.5T) = (3, 1) best DQS1 P1 dly(2T, 0.5T) = (3, 1) Rank: 1 best DQS0 dly(2T, 0.5T) = (2, 6) best DQS1 dly(2T, 0.5T) = (2, 6) best DQS0 P1 dly(2T, 0.5T) = (3, 2) best DQS1 P1 dly(2T, 0.5T) = (3, 2) TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16 Write Rank0 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x3a === u2Vref_new: 0x58 --> 0x58 === u2Vref_new: 0x5a --> 0x5a === u2Vref_new: 0x5c --> 0x78 === u2Vref_new: 0x5e --> 0x7a === u2Vref_new: 0x60 --> 0x90 [CA 0] Center 36 (9~63) winsize 55 [CA 1] Center 35 (8~63) winsize 56 [CA 2] Center 32 (3~61) winsize 59 [CA 3] Center 33 (3~63) winsize 61 [CA 4] Center 33 (3~63) winsize 61 [CA 5] Center 26 (-1~53) winsize 55 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 762/100 ps CA0 delay=36 (9~63),Diff = 10 PI (12 cell) CA1 delay=35 (8~63),Diff = 9 PI (11 cell) CA2 delay=32 (3~61),Diff = 6 PI (7 cell) CA3 delay=33 (3~63),Diff = 7 PI (8 cell) CA4 delay=33 (3~63),Diff = 7 PI (8 cell) CA5 delay=26 (-1~53),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=26 === u2Vref_new: 0x58 --> 0x58 Vref(ca) range 1: 24 CS Dly= 10 (41-0-32) Write Rank0 MR13 =0xd8 Write Rank0 MR13 =0xd8 Write Rank0 MR12 =0x58 Write Rank1 MR13 =0x59 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == === u2Vref_new: 0x56 --> 0x3a === u2Vref_new: 0x58 --> 0x58 === u2Vref_new: 0x5a --> 0x5a === u2Vref_new: 0x5c --> 0x78 === u2Vref_new: 0x5e --> 0x7a === u2Vref_new: 0x60 --> 0x90 [CA 0] Center 36 (10~63) winsize 54 [CA 1] Center 35 (8~63) winsize 56 [CA 2] Center 33 (3~63) winsize 61 [CA 3] Center 33 (3~63) winsize 61 [CA 4] Center 34 (5~63) winsize 59 [CA 5] Center 25 (-2~53) winsize 56 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 762/100 ps CA0 delay=36 (10~63),Diff = 10 PI (12 cell) CA1 delay=35 (8~63),Diff = 9 PI (11 cell) CA2 delay=32 (3~61),Diff = 6 PI (7 cell) CA3 delay=33 (3~63),Diff = 7 PI (8 cell) CA4 delay=34 (5~63),Diff = 8 PI (10 cell) CA5 delay=26 (-1~53),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=26 === u2Vref_new: 0x58 --> 0x58 Vref(ca) range 1: 24 CS Dly= 11 (42-0-32) Write Rank1 MR13 =0xd8 Write Rank1 MR13 =0xd8 Write Rank1 MR12 =0x58 [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 0 0 25 0 0 26 0 0 27 0 0 28 0 0 29 0 0 30 0 0 31 0 ff 32 0 ff 33 0 ff 34 ff ff 35 ff ff 36 ff ff 37 ff ff 38 ff ff 39 ff ff 40 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 34 DQS1 dly: 31 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank0 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |2928 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 4 |707 3534 |(11 11)(11 11) |(0 1)(1 1)| 0 3 1 8 |2a29 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 1 12 |2f2e 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 1 16 |2d2d 3534 |(11 11)(11 11) |(1 0)(0 1)| 0 3 1 20 |1110 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 1 24 |3231 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0 3 2 0 |3736 403 |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 4 |4847 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 8 |100f 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 12 |3635 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 16 |3736 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 20 |3736 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 24 |3736 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 2 28 |3636 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 2, 28) 3 3 0 |504 3d3d |(11 11)(11 11) |(0 1)(1 1)| 0 3 3 4 |3534 1413 |(11 11)(11 11) |(0 1)(1 1)| 0 3 3 8 |3534 b0a |(11 11)(11 11) |(0 1)(1 1)| 0 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0 [Byte 1] Lead/lag falling Transition (3, 3, 12) 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 4 0 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 5, 16) 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (2) 3 5 24 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 [Byte 1] Lead/lag falling Transition (3, 5, 24) 3 5 28 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0 [Byte 1] Lead/lag Transition tap number (2) 3 6 0 |4646 807 |(0 0)(11 11) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 6, 0) 3 6 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 1]First pass (3, 6, 4) 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20) best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28) Write Rank0 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 2) best RODT dly(2T, 0.5T) = (2, 2) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxxxxxx xxxxxxxx [MSB] -1, [0] xxxxxxxx xxxxxxxx [MSB] 0, [0] xxxoxxxx xxxxxxxx [MSB] 1, [0] xxxoxxxx xxxxxxxo [MSB] 2, [0] xxooxxxo xxxxxxxo [MSB] 3, [0] xxoooxxo xxxxxxxo [MSB] 4, [0] xxoooxxo ooooooxo [MSB] 5, [0] xxoooxxo oooooooo [MSB] 6, [0] xooooxxo oooooooo [MSB] 7, [0] xoooooxo oooooooo [MSB] 8, [0] ooooooxo oooooooo [MSB] 32, [0] ooxxoooo oooooooo [MSB] 33, [0] ooxxoooo ooooooox [MSB] 34, [0] ooxxoooo ooooooox [MSB] 35, [0] ooxxxooo ooxoooox [MSB] 36, [0] ooxxxooo ooxoooox [MSB] 37, [0] ooxxxoox xxxxoxxx [MSB] 38, [0] ooxxxoox xxxxoxxx [MSB] 39, [0] ooxxxoox xxxxxxxx [MSB] 40, [0] oxxxxoox xxxxxxxx [MSB] 41, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=41, Bit 0, Center 24 (8 ~ 40) 33 iDelay=41, Bit 1, Center 22 (6 ~ 39) 34 iDelay=41, Bit 2, Center 16 (2 ~ 31) 30 iDelay=41, Bit 3, Center 15 (0 ~ 31) 32 iDelay=41, Bit 4, Center 18 (3 ~ 34) 32 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32 iDelay=41, Bit 7, Center 19 (2 ~ 36) 35 iDelay=41, Bit 8, Center 20 (4 ~ 36) 33 iDelay=41, Bit 9, Center 20 (4 ~ 36) 33 iDelay=41, Bit 10, Center 19 (4 ~ 34) 31 iDelay=41, Bit 11, Center 20 (4 ~ 36) 33 iDelay=41, Bit 12, Center 21 (4 ~ 38) 35 iDelay=41, Bit 13, Center 20 (4 ~ 36) 33 iDelay=41, Bit 14, Center 20 (5 ~ 36) 32 iDelay=41, Bit 15, Center 16 (1 ~ 32) 32 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =24, DQ1 =22, DQ2 =16, DQ3 =15 DQ4 =18, DQ5 =23, DQ6 =24, DQ7 =19 DQ8 =20, DQ9 =20, DQ10 =19, DQ11 =20 DQ12 =21, DQ13 =20, DQ14 =20, DQ15 =16 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 927~1183 TX Vref Scan disable 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB] 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB] 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB] 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB] 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB] 967 |3 6 7|[0] xxxxxxxx ooxxxxxo [MSB] 968 |3 6 8|[0] xxxxxxxx oooxxxxo [MSB] 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB] 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB] 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB] 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB] 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB] 974 |3 6 14|[0] xxooxxxo oooooooo [MSB] 975 |3 6 15|[0] xxoooxxo oooooooo [MSB] 976 |3 6 16|[0] xoooooxo oooooooo [MSB] 989 |3 6 29|[0] oooooooo ooooooox [MSB] 990 |3 6 30|[0] oooooooo xxooooox [MSB] 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB] 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB] 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB] 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB] 995 |3 6 35|[0] ooxxooox xxxxxxxx [MSB] 996 |3 6 36|[0] ooxxooox xxxxxxxx [MSB] 997 |3 6 37|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=984, DQM PI dly= 984 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24) Byte1, DQ PI dly=977, DQM PI dly= 977 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 953~1017 Write Rank0 MR14 =0x0 CH=1, VrefRange= 0, VrefLevel = 0 TX Bit0 (978~995) 18 986, Bit8 (969~985) 17 977, TX Bit1 (977~994) 18 985, Bit9 (969~985) 17 977, TX Bit2 (976~990) 15 983, Bit10 (969~985) 17 977, TX Bit3 (974~989) 16 981, Bit11 (971~988) 18 979, TX Bit4 (977~992) 16 984, Bit12 (970~988) 19 979, TX Bit5 (977~994) 18 985, Bit13 (971~988) 18 979, TX Bit6 (978~995) 18 986, Bit14 (970~986) 17 978, TX Bit7 (976~991) 16 983, Bit15 (967~985) 19 976, Write Rank0 MR14 =0x2 CH=1, VrefRange= 0, VrefLevel = 2 TX Bit0 (978~997) 20 987, Bit8 (969~985) 17 977, TX Bit1 (977~994) 18 985, Bit9 (969~985) 17 977, TX Bit2 (976~991) 16 983, Bit10 (969~986) 18 977, TX Bit3 (973~990) 18 981, Bit11 (971~988) 18 979, TX Bit4 (976~992) 17 984, Bit12 (970~988) 19 979, TX Bit5 (977~996) 20 986, Bit13 (972~988) 17 980, TX Bit6 (978~996) 19 987, Bit14 (970~987) 18 978, TX Bit7 (976~991) 16 983, Bit15 (967~985) 19 976, Write Rank0 MR14 =0x4 CH=1, VrefRange= 0, VrefLevel = 4 TX Bit0 (978~997) 20 987, Bit8 (968~986) 19 977, TX Bit1 (976~994) 19 985, Bit9 (968~986) 19 977, TX Bit2 (975~991) 17 983, Bit10 (969~986) 18 977, TX Bit3 (973~990) 18 981, Bit11 (970~989) 20 979, TX Bit4 (976~992) 17 984, Bit12 (970~989) 20 979, TX Bit5 (977~996) 20 986, Bit13 (972~989) 18 980, TX Bit6 (978~996) 19 987, Bit14 (970~987) 18 978, TX Bit7 (976~991) 16 983, Bit15 (966~985) 20 975, Write Rank0 MR14 =0x6 CH=1, VrefRange= 0, VrefLevel = 6 TX Bit0 (977~997) 21 987, Bit8 (968~986) 19 977, TX Bit1 (976~995) 20 985, Bit9 (968~986) 19 977, TX Bit2 (975~992) 18 983, Bit10 (969~987) 19 978, TX Bit3 (972~990) 19 981, Bit11 (970~990) 21 980, TX Bit4 (976~992) 17 984, Bit12 (969~990) 22 979, TX Bit5 (977~997) 21 987, Bit13 (971~990) 20 980, TX Bit6 (978~997) 20 987, Bit14 (970~988) 19 979, TX Bit7 (976~992) 17 984, Bit15 (966~986) 21 976, Write Rank0 MR14 =0x8 CH=1, VrefRange= 0, VrefLevel = 8 TX Bit0 (977~998) 22 987, Bit8 (968~987) 20 977, TX Bit1 (976~996) 21 986, Bit9 (968~987) 20 977, TX Bit2 (975~992) 18 983, Bit10 (969~987) 19 978, TX Bit3 (972~991) 20 981, Bit11 (970~990) 21 980, TX Bit4 (976~993) 18 984, Bit12 (969~990) 22 979, TX Bit5 (976~997) 22 986, Bit13 (971~990) 20 980, TX Bit6 (978~998) 21 988, Bit14 (970~988) 19 979, TX Bit7 (976~992) 17 984, Bit15 (966~986) 21 976, Write Rank0 MR14 =0xa CH=1, VrefRange= 0, VrefLevel = 10 TX Bit0 (977~998) 22 987, Bit8 (968~987) 20 977, TX Bit1 (976~996) 21 986, Bit9 (968~987) 20 977, TX Bit2 (974~992) 19 983, Bit10 (969~988) 20 978, TX Bit3 (971~991) 21 981, Bit11 (970~991) 22 980, TX Bit4 (975~994) 20 984, Bit12 (969~991) 23 980, TX Bit5 (976~997) 22 986, Bit13 (970~990) 21 980, TX Bit6 (977~997) 21 987, Bit14 (969~989) 21 979, TX Bit7 (975~993) 19 984, Bit15 (966~986) 21 976, Write Rank0 MR14 =0xc CH=1, VrefRange= 0, VrefLevel = 12 TX Bit0 (977~999) 23 988, Bit8 (968~988) 21 978, TX Bit1 (976~997) 22 986, Bit9 (968~987) 20 977, TX Bit2 (974~993) 20 983, Bit10 (968~989) 22 978, TX Bit3 (971~991) 21 981, Bit11 (970~991) 22 980, TX Bit4 (975~994) 20 984, Bit12 (969~991) 23 980, TX Bit5 (976~998) 23 987, Bit13 (970~991) 22 980, TX Bit6 (977~998) 22 987, Bit14 (969~990) 22 979, TX Bit7 (975~993) 19 984, Bit15 (965~987) 23 976, Write Rank0 MR14 =0xe CH=1, VrefRange= 0, VrefLevel = 14 TX Bit0 (977~999) 23 988, Bit8 (968~989) 22 978, TX Bit1 (975~997) 23 986, Bit9 (967~988) 22 977, TX Bit2 (974~993) 20 983, Bit10 (968~990) 23 979, TX Bit3 (970~991) 22 980, Bit11 (969~991) 23 980, TX Bit4 (975~995) 21 985, Bit12 (969~991) 23 980, TX Bit5 (976~998) 23 987, Bit13 (970~991) 22 980, TX Bit6 (977~998) 22 987, Bit14 (969~990) 22 979, TX Bit7 (975~994) 20 984, Bit15 (965~987) 23 976, Write Rank0 MR14 =0x10 CH=1, VrefRange= 0, VrefLevel = 16 TX Bit0 (977~999) 23 988, Bit8 (967~990) 24 978, TX Bit1 (975~998) 24 986, Bit9 (967~989) 23 978, TX Bit2 (974~994) 21 984, Bit10 (968~990) 23 979, TX Bit3 (970~992) 23 981, Bit11 (969~991) 23 980, TX Bit4 (974~996) 23 985, Bit12 (969~991) 23 980, TX Bit5 (976~999) 24 987, Bit13 (970~991) 22 980, TX Bit6 (977~999) 23 988, Bit14 (969~991) 23 980, TX Bit7 (974~994) 21 984, Bit15 (965~988) 24 976, Write Rank0 MR14 =0x12 CH=1, VrefRange= 0, VrefLevel = 18 TX Bit0 (977~999) 23 988, Bit8 (967~990) 24 978, TX Bit1 (975~998) 24 986, Bit9 (967~990) 24 978, TX Bit2 (973~994) 22 983, Bit10 (968~991) 24 979, TX Bit3 (970~992) 23 981, Bit11 (969~992) 24 980, TX Bit4 (974~997) 24 985, Bit12 (968~992) 25 980, TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980, TX Bit6 (977~999) 23 988, Bit14 (969~991) 23 980, TX Bit7 (974~995) 22 984, Bit15 (964~988) 25 976, Write Rank0 MR14 =0x14 CH=1, VrefRange= 0, VrefLevel = 20 TX Bit0 (976~999) 24 987, Bit8 (967~990) 24 978, TX Bit1 (975~998) 24 986, Bit9 (967~990) 24 978, TX Bit2 (972~995) 24 983, Bit10 (967~991) 25 979, TX Bit3 (970~993) 24 981, Bit11 (969~992) 24 980, TX Bit4 (974~997) 24 985, Bit12 (968~992) 25 980, TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980, TX Bit6 (976~999) 24 987, Bit14 (968~991) 24 979, TX Bit7 (974~996) 23 985, Bit15 (964~989) 26 976, Write Rank0 MR14 =0x16 CH=1, VrefRange= 0, VrefLevel = 22 TX Bit0 (976~999) 24 987, Bit8 (967~991) 25 979, TX Bit1 (975~998) 24 986, Bit9 (967~990) 24 978, TX Bit2 (971~995) 25 983, Bit10 (968~991) 24 979, TX Bit3 (970~993) 24 981, Bit11 (968~992) 25 980, TX Bit4 (973~997) 25 985, Bit12 (968~992) 25 980, TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980, TX Bit6 (976~999) 24 987, Bit14 (968~991) 24 979, TX Bit7 (974~996) 23 985, Bit15 (964~988) 25 976, Write Rank0 MR14 =0x18 CH=1, VrefRange= 0, VrefLevel = 24 TX Bit0 (976~1000) 25 988, Bit8 (966~991) 26 978, TX Bit1 (975~999) 25 987, Bit9 (966~990) 25 978, TX Bit2 (971~995) 25 983, Bit10 (967~991) 25 979, TX Bit3 (969~993) 25 981, Bit11 (968~992) 25 980, TX Bit4 (973~997) 25 985, Bit12 (968~992) 25 980, TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980, TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979, TX Bit7 (973~996) 24 984, Bit15 (963~988) 26 975, Write Rank0 MR14 =0x1a CH=1, VrefRange= 0, VrefLevel = 26 TX Bit0 (976~1000) 25 988, Bit8 (966~991) 26 978, TX Bit1 (975~999) 25 987, Bit9 (966~990) 25 978, TX Bit2 (971~995) 25 983, Bit10 (967~991) 25 979, TX Bit3 (969~993) 25 981, Bit11 (968~992) 25 980, TX Bit4 (973~997) 25 985, Bit12 (968~992) 25 980, TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980, TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979, TX Bit7 (973~996) 24 984, Bit15 (963~988) 26 975, Write Rank0 MR14 =0x1c CH=1, VrefRange= 0, VrefLevel = 28 TX Bit0 (976~1000) 25 988, Bit8 (966~991) 26 978, TX Bit1 (975~999) 25 987, Bit9 (966~990) 25 978, TX Bit2 (971~995) 25 983, Bit10 (967~991) 25 979, TX Bit3 (969~993) 25 981, Bit11 (968~992) 25 980, TX Bit4 (973~997) 25 985, Bit12 (968~992) 25 980, TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980, TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979, TX Bit7 (973~996) 24 984, Bit15 (963~988) 26 975, Write Rank0 MR14 =0x1e CH=1, VrefRange= 0, VrefLevel = 30 TX Bit0 (976~1000) 25 988, Bit8 (966~991) 26 978, TX Bit1 (975~999) 25 987, Bit9 (966~990) 25 978, TX Bit2 (971~995) 25 983, Bit10 (967~991) 25 979, TX Bit3 (969~993) 25 981, Bit11 (968~992) 25 980, TX Bit4 (973~997) 25 985, Bit12 (968~992) 25 980, TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980, TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979, TX Bit7 (973~996) 24 984, Bit15 (963~988) 26 975, TX Vref found, early break! 374< 378 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps u1DelayCellOfst[0]=8 cells (7 PI) u1DelayCellOfst[1]=7 cells (6 PI) u1DelayCellOfst[2]=2 cells (2 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=5 cells (4 PI) u1DelayCellOfst[5]=7 cells (6 PI) u1DelayCellOfst[6]=8 cells (7 PI) u1DelayCellOfst[7]=3 cells (3 PI) Byte0, DQ PI dly=981, DQM PI dly= 984 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21) u1DelayCellOfst[8]=3 cells (3 PI) u1DelayCellOfst[9]=3 cells (3 PI) u1DelayCellOfst[10]=5 cells (4 PI) u1DelayCellOfst[11]=6 cells (5 PI) u1DelayCellOfst[12]=6 cells (5 PI) u1DelayCellOfst[13]=6 cells (5 PI) u1DelayCellOfst[14]=5 cells (4 PI) u1DelayCellOfst[15]=0 cells (0 PI) Byte1, DQ PI dly=975, DQM PI dly= 977 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15) Write Rank0 MR14 =0x18 Final TX Range 0 Vref 24 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 697~761 TX Vref Scan disable 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 707 |2 6 3|[0] xxxxxxxx oooooooo [MSB] 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB] 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB] 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB] 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB] 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB] 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB] 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB] 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB] 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB] 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB] 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB] 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB] 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB] 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB] 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB] 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB] 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=729, DQM PI dly= 729 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25) Byte1, DQ PI dly=721, DQM PI dly= 721 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank0 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK0, use_rxtx_scan=0 DATLAT Default: 0xf 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 1 RX Vref found, early break! Final RX Vref 13, apply to both rank0 and 1 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 18 DQ Delay: DQ0 =24, DQ1 =22, DQ2 =16, DQ3 =15 DQ4 =19, DQ5 =24, DQ6 =25, DQ7 =19 DQ8 =19, DQ9 =19, DQ10 =18, DQ11 =19 DQ12 =20, DQ13 =19, DQ14 =19, DQ15 =17 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFF, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xbf, (MSB)MR19= 0x3, tDQSOscB0 = 328 ps tDQSOscB1 = 0 ps CH1_RK0: MR19=0x3, MR18=0xBF, DQSOSC=328, MR23=63, INC=22, DEC=34 Write Rank0 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK0, (LSB)MR18= 0xbb, (MSB)MR19= 0x3, tDQSOscB0 = 329 ps tDQSOscB1 = 0 ps CH1 RK0: MR19=3, MR18=BB [RankSwap] Rank num 2, (Multi 1), Rank 1 Write Rank0 MR2 =0xad [Write Leveling] delay byte0 byte1 byte2 byte3 10 0 0 11 0 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 0 0 25 0 0 26 0 0 27 0 0 28 0 0 29 0 0 30 0 0 31 0 ff 32 0 ff 33 0 ff 34 0 ff 35 ff ff 36 ff ff 37 ff ff 38 ff ff 39 ff ff 40 ff ff 41 ff ff pass bytecount = 0xff (0xff: all bytes pass) DQS0 dly: 35 DQS1 dly: 31 Write Rank0 MR2 =0x2d [RankSwap] Rank num 2, (Multi 1), Rank 0 Write Rank1 MR1 =0xd6 [Gating] == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == 3 1 0 |3333 3534 |(11 11)(11 11) |(1 1)(1 1)| 0 3 1 4 |2726 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 1 8 |2f2f 3534 |(0 0)(11 11) |(0 1)(0 1)| 0 3 1 12 |2e2d 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 1 16 |302f 3534 |(11 11)(11 11) |(1 0)(0 1)| 0 3 1 20 |605 3534 |(11 11)(11 11) |(1 0)(0 1)| 0 3 1 24 |2e2e 3534 |(0 11)(11 11) |(0 0)(0 1)| 0 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 0 |3838 201 |(11 11)(11 11) |(1 1)(1 1)| 0 3 2 4 |3837 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 3 2 8 |3636 3d3d |(0 0)(11 11) |(0 0)(1 1)| 0 3 2 12 |2827 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 2 16 |3b3b 3d3d |(0 0)(11 11) |(1 1)(1 1)| 0 3 2 20 |3a3a 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 2 24 |d0c 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 2 28 |e0d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 2, 28) 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 1)(1 1)| 0 3 3 4 |3534 1514 |(11 11)(11 11) |(0 1)(1 1)| 0 3 3 8 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0 [Byte 1] Lead/lag falling Transition (3, 3, 8) 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0 3 3 28 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0 3 4 0 |3d3d 100f |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0 [Byte 0] Lead/lag falling Transition (3, 5, 16) 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0 [Byte 0] Lead/lag Transition tap number (2) 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0 [Byte 1] Lead/lag falling Transition (3, 5, 24) 3 5 28 |404 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0 [Byte 1] Lead/lag Transition tap number (2) 3 6 0 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0 [Byte 0]First pass (3, 6, 0) 3 6 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 [Byte 1]First pass (3, 6, 4) 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0 All bytes gating window > 1UI, Early break! best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20) best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28) best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20) best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28) Write Rank1 MR1 =0x56 best RODT dly(2T, 0.5T) = (2, 2) best RODT dly(2T, 0.5T) = (2, 2) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =0 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxoxxxx xxxxxxxx [MSB] -1, [0] xxxoxxxx xxxxxxxo [MSB] 0, [0] xxooxxxx xxxxxxxo [MSB] 1, [0] xxooxxxo xxxxxxxo [MSB] 2, [0] xxoooxxo oooxxxxo [MSB] 3, [0] xxoooxxo ooooxooo [MSB] 4, [0] xxoooxxo ooooxooo [MSB] 5, [0] xoooooxo oooooooo [MSB] 6, [0] xoooooxo oooooooo [MSB] 34, [0] ooxxoooo oooooooo [MSB] 35, [0] ooxxoooo ooooooox [MSB] 36, [0] ooxxoooo ooooooox [MSB] 37, [0] ooxxoooo ooxoooox [MSB] 38, [0] ooxxxooo xoxooxxx [MSB] 39, [0] ooxxxoox xxxxoxxx [MSB] 40, [0] ooxxxoox xxxxoxxx [MSB] 41, [0] ooxxxoox xxxxxxxx [MSB] 42, [0] oxxxxxxx xxxxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 24 (7 ~ 42) 36 iDelay=43, Bit 1, Center 23 (5 ~ 41) 37 iDelay=43, Bit 2, Center 16 (0 ~ 33) 34 iDelay=43, Bit 3, Center 15 (-2 ~ 33) 36 iDelay=43, Bit 4, Center 19 (2 ~ 37) 36 iDelay=43, Bit 5, Center 23 (5 ~ 41) 37 iDelay=43, Bit 6, Center 24 (7 ~ 41) 35 iDelay=43, Bit 7, Center 19 (1 ~ 38) 38 iDelay=43, Bit 8, Center 19 (2 ~ 37) 36 iDelay=43, Bit 9, Center 20 (2 ~ 38) 37 iDelay=43, Bit 10, Center 19 (2 ~ 36) 35 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36 iDelay=43, Bit 12, Center 22 (5 ~ 40) 36 iDelay=43, Bit 13, Center 20 (3 ~ 37) 35 iDelay=43, Bit 14, Center 20 (3 ~ 37) 35 iDelay=43, Bit 15, Center 16 (-1 ~ 34) 36 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =24, DQ1 =23, DQ2 =16, DQ3 =15 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =19 DQ8 =19, DQ9 =20, DQ10 =19, DQ11 =20 DQ12 =22, DQ13 =20, DQ14 =20, DQ15 =16 DramC Write-DBI off == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=2, VrefScanEnable 0 Begin, DQ Scan Range 927~1183 TX Vref Scan disable 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB] 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB] 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB] 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB] 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB] 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB] 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB] 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB] 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB] 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB] 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB] 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB] 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB] 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB] 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB] 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB] 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB] 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB] 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB] 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB] 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB] 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB] 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB] 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB] 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB] 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB] 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB] 965 |3 6 5|[0] xxxxxxxx xxxxxxxo [MSB] 966 |3 6 6|[0] xxxxxxxx xxxxxxxo [MSB] 967 |3 6 7|[0] xxxxxxxx xoxxxxxo [MSB] 968 |3 6 8|[0] xxxxxxxx oooxxxxo [MSB] 969 |3 6 9|[0] xxxxxxxx oooooooo [MSB] 970 |3 6 10|[0] xxxxxxxx oooooooo [MSB] 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB] 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB] 973 |3 6 13|[0] xxooxxxx oooooooo [MSB] 974 |3 6 14|[0] xxooxxxx oooooooo [MSB] 975 |3 6 15|[0] xxoooxxx oooooooo [MSB] 976 |3 6 16|[0] xxoooxxo oooooooo [MSB] 987 |3 6 27|[0] oooooooo ooooooox [MSB] 988 |3 6 28|[0] oooooooo ooooooox [MSB] 989 |3 6 29|[0] oooooooo ooooooox [MSB] 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB] 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB] 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB] 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB] 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB] 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB] 996 |3 6 36|[0] ooxxoooo xxxxxxxx [MSB] 997 |3 6 37|[0] ooxxooox xxxxxxxx [MSB] 998 |3 6 38|[0] ooxxxoox xxxxxxxx [MSB] 999 |3 6 39|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=985, DQM PI dly= 985 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25) Byte1, DQ PI dly=977, DQM PI dly= 977 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17) == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=0, VrefScanEnable 1 Begin, DQ Scan Range 953~1017 Write Rank1 MR14 =0x0 CH=1, VrefRange= 0, VrefLevel = 0 TX Bit0 (979~997) 19 988, Bit8 (969~985) 17 977, TX Bit1 (978~996) 19 987, Bit9 (969~985) 17 977, TX Bit2 (976~991) 16 983, Bit10 (969~985) 17 977, TX Bit3 (975~990) 16 982, Bit11 (970~988) 19 979, TX Bit4 (976~992) 17 984, Bit12 (970~986) 17 978, TX Bit5 (978~997) 20 987, Bit13 (972~985) 14 978, TX Bit6 (978~997) 20 987, Bit14 (970~986) 17 978, TX Bit7 (977~991) 15 984, Bit15 (967~984) 18 975, Write Rank1 MR14 =0x2 CH=1, VrefRange= 0, VrefLevel = 2 TX Bit0 (979~998) 20 988, Bit8 (969~985) 17 977, TX Bit1 (978~996) 19 987, Bit9 (969~985) 17 977, TX Bit2 (975~991) 17 983, Bit10 (970~985) 16 977, TX Bit3 (974~991) 18 982, Bit11 (971~989) 19 980, TX Bit4 (976~993) 18 984, Bit12 (970~987) 18 978, TX Bit5 (978~997) 20 987, Bit13 (971~986) 16 978, TX Bit6 (978~997) 20 987, Bit14 (970~987) 18 978, TX Bit7 (977~992) 16 984, Bit15 (967~984) 18 975, Write Rank1 MR14 =0x4 CH=1, VrefRange= 0, VrefLevel = 4 TX Bit0 (978~998) 21 988, Bit8 (969~986) 18 977, TX Bit1 (978~997) 20 987, Bit9 (968~985) 18 976, TX Bit2 (975~992) 18 983, Bit10 (969~986) 18 977, TX Bit3 (974~991) 18 982, Bit11 (970~990) 21 980, TX Bit4 (976~993) 18 984, Bit12 (970~987) 18 978, TX Bit5 (978~997) 20 987, Bit13 (971~986) 16 978, TX Bit6 (978~998) 21 988, Bit14 (970~987) 18 978, TX Bit7 (977~992) 16 984, Bit15 (966~984) 19 975, Write Rank1 MR14 =0x6 CH=1, VrefRange= 0, VrefLevel = 6 TX Bit0 (978~999) 22 988, Bit8 (969~986) 18 977, TX Bit1 (978~997) 20 987, Bit9 (968~986) 19 977, TX Bit2 (975~992) 18 983, Bit10 (969~986) 18 977, TX Bit3 (974~992) 19 983, Bit11 (970~990) 21 980, TX Bit4 (976~994) 19 985, Bit12 (969~988) 20 978, TX Bit5 (978~998) 21 988, Bit13 (970~987) 18 978, TX Bit6 (978~999) 22 988, Bit14 (970~988) 19 979, TX Bit7 (977~993) 17 985, Bit15 (967~984) 18 975, Write Rank1 MR14 =0x8 CH=1, VrefRange= 0, VrefLevel = 8 TX Bit0 (978~999) 22 988, Bit8 (969~987) 19 978, TX Bit1 (978~998) 21 988, Bit9 (968~986) 19 977, TX Bit2 (975~992) 18 983, Bit10 (969~987) 19 978, TX Bit3 (973~992) 20 982, Bit11 (970~991) 22 980, TX Bit4 (976~995) 20 985, Bit12 (969~989) 21 979, TX Bit5 (977~998) 22 987, Bit13 (970~988) 19 979, TX Bit6 (977~998) 22 987, Bit14 (969~988) 20 978, TX Bit7 (977~994) 18 985, Bit15 (966~985) 20 975, Write Rank1 MR14 =0xa CH=1, VrefRange= 0, VrefLevel = 10 TX Bit0 (978~999) 22 988, Bit8 (969~988) 20 978, TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977, TX Bit2 (975~993) 19 984, Bit10 (968~988) 21 978, TX Bit3 (973~992) 20 982, Bit11 (970~991) 22 980, TX Bit4 (975~995) 21 985, Bit12 (969~990) 22 979, TX Bit5 (977~998) 22 987, Bit13 (969~988) 20 978, TX Bit6 (977~999) 23 988, Bit14 (969~989) 21 979, TX Bit7 (977~994) 18 985, Bit15 (966~985) 20 975, Write Rank1 MR14 =0xc CH=1, VrefRange= 0, VrefLevel = 12 TX Bit0 (977~1000) 24 988, Bit8 (968~988) 21 978, TX Bit1 (977~998) 22 987, Bit9 (968~988) 21 978, TX Bit2 (975~993) 19 984, Bit10 (969~988) 20 978, TX Bit3 (972~993) 22 982, Bit11 (969~991) 23 980, TX Bit4 (975~996) 22 985, Bit12 (969~990) 22 979, TX Bit5 (977~999) 23 988, Bit13 (970~989) 20 979, TX Bit6 (978~999) 22 988, Bit14 (969~990) 22 979, TX Bit7 (977~995) 19 986, Bit15 (966~985) 20 975, Write Rank1 MR14 =0xe CH=1, VrefRange= 0, VrefLevel = 14 TX Bit0 (978~1000) 23 989, Bit8 (968~989) 22 978, TX Bit1 (977~999) 23 988, Bit9 (968~988) 21 978, TX Bit2 (974~994) 21 984, Bit10 (968~989) 22 978, TX Bit3 (972~993) 22 982, Bit11 (969~991) 23 980, TX Bit4 (975~997) 23 986, Bit12 (969~990) 22 979, TX Bit5 (977~999) 23 988, Bit13 (969~990) 22 979, TX Bit6 (977~999) 23 988, Bit14 (969~990) 22 979, TX Bit7 (976~995) 20 985, Bit15 (965~986) 22 975, Write Rank1 MR14 =0x10 CH=1, VrefRange= 0, VrefLevel = 16 TX Bit0 (977~1000) 24 988, Bit8 (968~990) 23 979, TX Bit1 (977~999) 23 988, Bit9 (967~989) 23 978, TX Bit2 (974~994) 21 984, Bit10 (968~990) 23 979, TX Bit3 (971~994) 24 982, Bit11 (969~992) 24 980, TX Bit4 (975~997) 23 986, Bit12 (969~991) 23 980, TX Bit5 (977~999) 23 988, Bit13 (969~990) 22 979, TX Bit6 (977~1000) 24 988, Bit14 (969~990) 22 979, TX Bit7 (976~996) 21 986, Bit15 (965~986) 22 975, Write Rank1 MR14 =0x12 CH=1, VrefRange= 0, VrefLevel = 18 TX Bit0 (977~1000) 24 988, Bit8 (968~990) 23 979, TX Bit1 (977~999) 23 988, Bit9 (967~990) 24 978, TX Bit2 (973~995) 23 984, Bit10 (968~990) 23 979, TX Bit3 (971~994) 24 982, Bit11 (968~992) 25 980, TX Bit4 (975~997) 23 986, Bit12 (968~991) 24 979, TX Bit5 (977~999) 23 988, Bit13 (969~990) 22 979, TX Bit6 (977~1000) 24 988, Bit14 (968~991) 24 979, TX Bit7 (976~996) 21 986, Bit15 (965~987) 23 976, Write Rank1 MR14 =0x14 CH=1, VrefRange= 0, VrefLevel = 20 TX Bit0 (977~1001) 25 989, Bit8 (968~990) 23 979, TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978, TX Bit2 (973~996) 24 984, Bit10 (967~990) 24 978, TX Bit3 (971~995) 25 983, Bit11 (969~992) 24 980, TX Bit4 (974~998) 25 986, Bit12 (968~991) 24 979, TX Bit5 (976~999) 24 987, Bit13 (969~991) 23 980, TX Bit6 (976~1000) 25 988, Bit14 (968~991) 24 979, TX Bit7 (976~997) 22 986, Bit15 (964~987) 24 975, Write Rank1 MR14 =0x16 CH=1, VrefRange= 0, VrefLevel = 22 TX Bit0 (977~1001) 25 989, Bit8 (967~990) 24 978, TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978, TX Bit2 (972~996) 25 984, Bit10 (968~989) 22 978, TX Bit3 (970~995) 26 982, Bit11 (968~992) 25 980, TX Bit4 (974~998) 25 986, Bit12 (968~991) 24 979, TX Bit5 (976~1000) 25 988, Bit13 (968~991) 24 979, TX Bit6 (976~1001) 26 988, Bit14 (968~991) 24 979, TX Bit7 (975~997) 23 986, Bit15 (964~988) 25 976, Write Rank1 MR14 =0x18 CH=1, VrefRange= 0, VrefLevel = 24 TX Bit0 (977~1002) 26 989, Bit8 (967~990) 24 978, TX Bit1 (977~1000) 24 988, Bit9 (966~989) 24 977, TX Bit2 (972~997) 26 984, Bit10 (967~989) 23 978, TX Bit3 (970~995) 26 982, Bit11 (968~991) 24 979, TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980, TX Bit5 (976~1000) 25 988, Bit13 (968~990) 23 979, TX Bit6 (977~1001) 25 989, Bit14 (967~991) 25 979, TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975, Write Rank1 MR14 =0x1a CH=1, VrefRange= 0, VrefLevel = 26 TX Bit0 (977~1002) 26 989, Bit8 (967~990) 24 978, TX Bit1 (977~1000) 24 988, Bit9 (966~989) 24 977, TX Bit2 (972~997) 26 984, Bit10 (967~989) 23 978, TX Bit3 (970~995) 26 982, Bit11 (968~991) 24 979, TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980, TX Bit5 (976~1000) 25 988, Bit13 (968~990) 23 979, TX Bit6 (977~1001) 25 989, Bit14 (967~991) 25 979, TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975, Write Rank1 MR14 =0x1c CH=1, VrefRange= 0, VrefLevel = 28 TX Bit0 (977~1002) 26 989, Bit8 (967~990) 24 978, TX Bit1 (977~1000) 24 988, Bit9 (966~989) 24 977, TX Bit2 (972~997) 26 984, Bit10 (967~989) 23 978, TX Bit3 (970~995) 26 982, Bit11 (968~991) 24 979, TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980, TX Bit5 (976~1000) 25 988, Bit13 (968~990) 23 979, TX Bit6 (977~1001) 25 989, Bit14 (967~991) 25 979, TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975, Write Rank1 MR14 =0x1e CH=1, VrefRange= 0, VrefLevel = 30 TX Bit0 (977~1002) 26 989, Bit8 (967~990) 24 978, TX Bit1 (977~1000) 24 988, Bit9 (966~989) 24 977, TX Bit2 (972~997) 26 984, Bit10 (967~989) 23 978, TX Bit3 (970~995) 26 982, Bit11 (968~991) 24 979, TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980, TX Bit5 (976~1000) 25 988, Bit13 (968~990) 23 979, TX Bit6 (977~1001) 25 989, Bit14 (967~991) 25 979, TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975, Write Rank1 MR14 =0x20 CH=1, VrefRange= 0, VrefLevel = 32 TX Bit0 (977~1002) 26 989, Bit8 (967~990) 24 978, TX Bit1 (977~1000) 24 988, Bit9 (966~989) 24 977, TX Bit2 (972~997) 26 984, Bit10 (967~989) 23 978, TX Bit3 (970~995) 26 982, Bit11 (968~991) 24 979, TX Bit4 (974~998) 25 986, Bit12 (968~992) 25 980, TX Bit5 (976~1000) 25 988, Bit13 (968~990) 23 979, TX Bit6 (977~1001) 25 989, Bit14 (967~991) 25 979, TX Bit7 (975~998) 24 986, Bit15 (963~987) 25 975, TX Vref found, early break! 363< 374 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =762/100 ps u1DelayCellOfst[0]=8 cells (7 PI) u1DelayCellOfst[1]=7 cells (6 PI) u1DelayCellOfst[2]=2 cells (2 PI) u1DelayCellOfst[3]=0 cells (0 PI) u1DelayCellOfst[4]=5 cells (4 PI) u1DelayCellOfst[5]=7 cells (6 PI) u1DelayCellOfst[6]=8 cells (7 PI) u1DelayCellOfst[7]=5 cells (4 PI) Byte0, DQ PI dly=982, DQM PI dly= 985 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22) u1DelayCellOfst[8]=3 cells (3 PI) u1DelayCellOfst[9]=2 cells (2 PI) u1DelayCellOfst[10]=3 cells (3 PI) u1DelayCellOfst[11]=5 cells (4 PI) u1DelayCellOfst[12]=6 cells (5 PI) u1DelayCellOfst[13]=5 cells (4 PI) u1DelayCellOfst[14]=5 cells (4 PI) u1DelayCellOfst[15]=0 cells (0 PI) Byte1, DQ PI dly=975, DQM PI dly= 977 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15) OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15) Write Rank1 MR14 =0x18 Final TX Range 0 Vref 24 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 DramC Write-DBI on == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == [TxWindowPerbitCal] calType=1, VrefScanEnable 0 Begin, DQ Scan Range 697~761 TX Vref Scan disable 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB] 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB] 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB] 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB] 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB] 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB] 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB] 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB] 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB] 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB] 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB] 708 |2 6 4|[0] xxxxxxxx oooooooo [MSB] 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB] 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB] 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB] 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB] 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB] 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB] 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB] 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB] 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB] 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB] 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB] 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB] 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB] 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB] 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB] 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB] 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB] 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB] 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB] 745 |2 6 41|[0] xxxxxxxx xxxxxxxx [MSB] Byte0, DQ PI dly=731, DQM PI dly= 731 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27) Byte1, DQ PI dly=721, DQM PI dly= 721 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17) OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17) Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 Write Rank1 MR3 =0x30 DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK1, use_rxtx_scan=0 DATLAT Default: 0x10 7, 0xFFFF, sum=0 8, 0xFFFF, sum=0 9, 0xFFFF, sum=0 10, 0xFFFF, sum=0 11, 0xFFFF, sum=0 12, 0xFFFF, sum=0 13, 0xFFFF, sum=0 14, 0x0, sum=1 15, 0x0, sum=2 16, 0x0, sum=3 17, 0x0, sum=4 pattern=2 first_step=14 total pass=5 best_step=16 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == Start DQ dly to find pass range UseTestEngine =1 x-axis: bit #, y-axis: DQ dly (-127~63) RX Vref Scan = 0 -26, [0] xxxxxxxx xxxxxxxx [MSB] -25, [0] xxxxxxxx xxxxxxxx [MSB] -24, [0] xxxxxxxx xxxxxxxx [MSB] -23, [0] xxxxxxxx xxxxxxxx [MSB] -22, [0] xxxxxxxx xxxxxxxx [MSB] -21, [0] xxxxxxxx xxxxxxxx [MSB] -20, [0] xxxxxxxx xxxxxxxx [MSB] -19, [0] xxxxxxxx xxxxxxxx [MSB] -18, [0] xxxxxxxx xxxxxxxx [MSB] -17, [0] xxxxxxxx xxxxxxxx [MSB] -16, [0] xxxxxxxx xxxxxxxx [MSB] -15, [0] xxxxxxxx xxxxxxxx [MSB] -14, [0] xxxxxxxx xxxxxxxx [MSB] -13, [0] xxxxxxxx xxxxxxxx [MSB] -12, [0] xxxxxxxx xxxxxxxx [MSB] -11, [0] xxxxxxxx xxxxxxxx [MSB] -10, [0] xxxxxxxx xxxxxxxx [MSB] -9, [0] xxxxxxxx xxxxxxxx [MSB] -8, [0] xxxxxxxx xxxxxxxx [MSB] -7, [0] xxxxxxxx xxxxxxxx [MSB] -6, [0] xxxxxxxx xxxxxxxx [MSB] -5, [0] xxxxxxxx xxxxxxxx [MSB] -4, [0] xxxxxxxx xxxxxxxx [MSB] -3, [0] xxxxxxxx xxxxxxxx [MSB] -2, [0] xxxoxxxx xxxxxxxx [MSB] -1, [0] xxxoxxxx xxxxxxxx [MSB] 0, [0] xxooxxxx xxxxxxxo [MSB] 1, [0] xxooxxxx oxxxxxxo [MSB] 2, [0] xxoooxxo oooxxxxo [MSB] 3, [0] xxoooxxo ooooxooo [MSB] 4, [0] xxoooxxo oooooooo [MSB] 5, [0] xoooooxo oooooooo [MSB] 6, [0] xoooooxo oooooooo [MSB] 34, [0] oooxoooo oooooooo [MSB] 35, [0] oooxoooo ooooooox [MSB] 36, [0] ooxxoooo ooooooox [MSB] 37, [0] ooxxxoox ooxooxxx [MSB] 38, [0] ooxxxoox xxxooxxx [MSB] 39, [0] ooxxxoox xxxxoxxx [MSB] 40, [0] ooxxxoox xxxxxxxx [MSB] 41, [0] oxxxxoox xxxxxxxx [MSB] 42, [0] oxxxxxox xxxxxxxx [MSB] 43, [0] xxxxxxxx xxxxxxxx [MSB] iDelay=43, Bit 0, Center 24 (7 ~ 42) 36 iDelay=43, Bit 1, Center 22 (5 ~ 40) 36 iDelay=43, Bit 2, Center 17 (0 ~ 35) 36 iDelay=43, Bit 3, Center 15 (-2 ~ 33) 36 iDelay=43, Bit 4, Center 19 (2 ~ 36) 35 iDelay=43, Bit 5, Center 23 (5 ~ 41) 37 iDelay=43, Bit 6, Center 24 (7 ~ 42) 36 iDelay=43, Bit 7, Center 19 (2 ~ 36) 35 iDelay=43, Bit 8, Center 19 (1 ~ 37) 37 iDelay=43, Bit 9, Center 19 (2 ~ 37) 36 iDelay=43, Bit 10, Center 19 (2 ~ 36) 35 iDelay=43, Bit 11, Center 20 (3 ~ 38) 36 iDelay=43, Bit 12, Center 21 (4 ~ 39) 36 iDelay=43, Bit 13, Center 19 (3 ~ 36) 34 iDelay=43, Bit 14, Center 19 (3 ~ 36) 34 iDelay=43, Bit 15, Center 17 (0 ~ 34) 35 == Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 0 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 20, DQM1 = 19 DQ Delay: DQ0 =24, DQ1 =22, DQ2 =17, DQ3 =15 DQ4 =19, DQ5 =23, DQ6 =24, DQ7 =19 DQ8 =19, DQ9 =19, DQ10 =19, DQ11 =20 DQ12 =21, DQ13 =19, DQ14 =19, DQ15 =17 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 23, 0x0, End_B0=23 End_B1=23 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0xFFFF, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3) Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0xaf, (MSB)MR19= 0x3, tDQSOscB0 = 334 ps tDQSOscB1 = 0 ps CH1_RK1: MR19=0x3, MR18=0xAF, DQSOSC=334, MR23=63, INC=22, DEC=33 Write Rank1 MR23 =0x3f [DQSOSC] [DQSOSCAuto] RK1, (LSB)MR18= 0xb3, (MSB)MR19= 0x3, tDQSOscB0 = 332 ps tDQSOscB1 = 0 ps CH1 RK1: MR19=3, MR18=B3 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 Rank: 0 best DQS0 dly(2T, 0.5T) = (2, 5) best DQS1 dly(2T, 0.5T) = (2, 5) best DQS0 P1 dly(2T, 0.5T) = (3, 1) best DQS1 P1 dly(2T, 0.5T) = (3, 1) Rank: 1 best DQS0 dly(2T, 0.5T) = (2, 5) best DQS1 dly(2T, 0.5T) = (2, 5) best DQS0 P1 dly(2T, 0.5T) = (3, 1) best DQS1 P1 dly(2T, 0.5T) = (3, 1) TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16 [Calibration Summary] Freqency 1600 CH 0, Rank 0 All Pass. CH 0, Rank 1 All Pass. CH 1, Rank 0 All Pass. CH 1, Rank 1 All Pass. Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank0 MR3 =0xb0 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2 Write Rank1 MR3 =0xb0 DramC Write-DBI on [GetDramInforAfterCalByMRR] Vendor 1. [GetDramInforAfterCalByMRR] Revision 7. MR8 12 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000. MR8 12 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000. MR8 12 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000. MR8 12 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000. [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0 Write Rank0 MR13 =0xd0 Write Rank1 MR13 =0xd0 Write Rank0 MR13 =0xd0 Write Rank1 MR13 =0xd0 Save calibration result to emmc [DramcModeReg_Check] Freq_1600, FSP_1 FSP_1, CH_0, RK0 Write Rank0 MR13 =0xd8 MR12 = 0x56 (global = 0x56) match MR14 = 0x1a (global = 0x1a) match FSP_1, CH_0, RK1 Write Rank1 MR13 =0xd8 MR12 = 0x56 (global = 0x56) match MR14 = 0x18 (global = 0x18) match FSP_1, CH_1, RK0 Write Rank0 MR13 =0xd8 MR12 = 0x58 (global = 0x58) match MR14 = 0x18 (global = 0x18) match FSP_1, CH_1, RK1 Write Rank1 MR13 =0xd8 MR12 = 0x58 (global = 0x58) match MR14 = 0x18 (global = 0x18) match [MEM_TEST] 02: After DFS, before run time config [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0) [TA2_TEST] === TA2 HW TA2 PAT: XTALK HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0 Settings after calibration [DramcRunTimeConfig] TransferPLLToSPMControl - MODE SW PHYPLL TX_TRACKING: ON RX_TRACKING: ON HW_GATING: ON HW_GATING DBG: OFF ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 ddr_geometry:1 High Freq DUMMY_READ_FOR_TRACKING: ON ZQCS_ENABLE_LP4: OFF LOWPOWER_GOLDEN_SETTINGS(DCM): ON DUMMY_READ_FOR_DQS_GATING_RETRY: OFF SPM_CONTROL_AFTERK: ON IMPEDANCE_TRACKING: ON TEMP_SENSOR: ON PER_BANK_REFRESH: ON HW_SAVE_FOR_SR: ON SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON CLK_FREE_FUN_FOR_DRAMC_PSEL: ON PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON Read ODT Tracking: ON ========================= [TA2_TEST] === TA2 HW HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0 [MEM_TEST] 03: After run time config [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0) [complex_mem_test] start addr:0x40024000, len:131072 1st complex R/W mem test pass save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0 sync preloader write leveling sync preloader cbt_mr12 sync preloader cbt_clk_dly sync preloader cbt_cmd_dly sync preloader cbt_cs sync preloader cbt_ca_perbit_delay sync preloader clk_delay sync preloader dqs_delay sync preloader u1Gating2T_Save sync preloader u1Gating05T_Save sync preloader u1Gatingfine_tune_Save sync preloader u1Gatingucpass_count_Save sync preloader u1TxWindowPerbitVref_Save sync preloader u1TxCenter_min_Save sync preloader u1TxCenter_max_Save sync preloader u1Txwin_center_Save sync preloader u1Txfirst_pass_Save sync preloader u1Txlast_pass_Save sync preloader u1RxDatlat_Save sync preloader u1RxWinPerbitVref_Save sync preloader u1RxWinPerbitDQ_firsbypass_Save sync preloader u1RxWinPerbitDQ_lastbypass_Save sync preloader delay_cell_unit save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1 sync preloader write leveling sync preloader cbt_mr12 sync preloader cbt_clk_dly sync preloader cbt_cmd_dly sync preloader cbt_cs sync preloader cbt_ca_perbit_delay sync preloader clk_delay sync preloader dqs_delay sync preloader u1Gating2T_Save sync preloader u1Gating05T_Save sync preloader u1Gatingfine_tune_Save sync preloader u1Gatingucpass_count_Save sync preloader u1TxWindowPerbitVref_Save sync preloader u1TxCenter_min_Save sync preloader u1TxCenter_max_Save sync preloader u1Txwin_center_Save sync preloader u1Txfirst_pass_Save sync preloader u1Txlast_pass_Save sync preloader u1RxDatlat_Save sync preloader u1RxWinPerbitVref_Save sync preloader u1RxWinPerbitDQ_firsbypass_Save sync preloader u1RxWinPerbitDQ_lastbypass_Save sync preloader delay_cell_unit save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2 sync preloader write leveling sync preloader cbt_mr12 sync preloader cbt_clk_dly sync preloader cbt_cmd_dly sync preloader cbt_cs sync preloader cbt_ca_perbit_delay sync preloader clk_delay sync preloader dqs_delay sync preloader u1Gating2T_Save sync preloader u1Gating05T_Save sync preloader u1Gatingfine_tune_Save sync preloader u1Gatingucpass_count_Save sync preloader u1TxWindowPerbitVref_Save sync preloader u1TxCenter_min_Save sync preloader u1TxCenter_max_Save sync preloader u1Txwin_center_Save sync preloader u1Txfirst_pass_Save sync preloader u1Txlast_pass_Save sync preloader u1RxDatlat_Save sync preloader u1RxWinPerbitVref_Save sync preloader u1RxWinPerbitDQ_firsbypass_Save sync preloader u1RxWinPerbitDQ_lastbypass_Save sync preloader delay_cell_unit just_for_test_dump_coreboot_params dump all params dump source = 0x0 dump params frequency:1600 dump params rank number:2 dump params write leveling write leveling[0][0][0] = 0x21 write leveling[0][0][1] = 0x19 write leveling[0][1][0] = 0x23 write leveling[0][1][1] = 0x1b write leveling[1][0][0] = 0x22 write leveling[1][0][1] = 0x1f write leveling[1][1][0] = 0x23 write leveling[1][1][1] = 0x1f dump params cbt_cs cbt_cs[0][0] = 0xa cbt_cs[0][1] = 0xa cbt_cs[1][0] = 0xa cbt_cs[1][1] = 0xa dump params cbt_mr12 cbt_mr12[0][0] = 0x16 cbt_mr12[0][1] = 0x16 cbt_mr12[1][0] = 0x18 cbt_mr12[1][1] = 0x18 dump params tx window tx_center_min[0][0][0] = 980 tx_center_max[0][0][0] = 987 tx_center_min[0][0][1] = 972 tx_center_max[0][0][1] = 978 tx_center_min[0][1][0] = 982 tx_center_max[0][1][0] = 990 tx_center_min[0][1][1] = 975 tx_center_max[0][1][1] = 980 tx_center_min[1][0][0] = 981 tx_center_max[1][0][0] = 988 tx_center_min[1][0][1] = 975 tx_center_max[1][0][1] = 980 tx_center_min[1][1][0] = 982 tx_center_max[1][1][0] = 989 tx_center_min[1][1][1] = 975 tx_center_max[1][1][1] = 980 dump params tx window tx_win_center[0][0][0] = 987 tx_first_pass[0][0][0] = 975 tx_last_pass[0][0][0] = 999 tx_win_center[0][0][1] = 985 tx_first_pass[0][0][1] = 974 tx_last_pass[0][0][1] = 997 tx_win_center[0][0][2] = 986 tx_first_pass[0][0][2] = 974 tx_last_pass[0][0][2] = 998 tx_win_center[0][0][3] = 980 tx_first_pass[0][0][3] = 968 tx_last_pass[0][0][3] = 992 tx_win_center[0][0][4] = 985 tx_first_pass[0][0][4] = 974 tx_last_pass[0][0][4] = 997 tx_win_center[0][0][5] = 980 tx_first_pass[0][0][5] = 968 tx_last_pass[0][0][5] = 992 tx_win_center[0][0][6] = 981 tx_first_pass[0][0][6] = 969 tx_last_pass[0][0][6] = 993 tx_win_center[0][0][7] = 983 tx_first_pass[0][0][7] = 971 tx_last_pass[0][0][7] = 995 tx_win_center[0][0][8] = 973 tx_first_pass[0][0][8] = 961 tx_last_pass[0][0][8] = 985 tx_win_center[0][0][9] = 974 tx_first_pass[0][0][9] = 962 tx_last_pass[0][0][9] = 987 tx_win_center[0][0][10] = 978 tx_first_pass[0][0][10] = 967 tx_last_pass[0][0][10] = 990 tx_win_center[0][0][11] = 972 tx_first_pass[0][0][11] = 961 tx_last_pass[0][0][11] = 984 tx_win_center[0][0][12] = 973 tx_first_pass[0][0][12] = 961 tx_last_pass[0][0][12] = 985 tx_win_center[0][0][13] = 972 tx_first_pass[0][0][13] = 961 tx_last_pass[0][0][13] = 984 tx_win_center[0][0][14] = 973 tx_first_pass[0][0][14] = 962 tx_last_pass[0][0][14] = 985 tx_win_center[0][0][15] = 976 tx_first_pass[0][0][15] = 964 tx_last_pass[0][0][15] = 989 tx_win_center[0][1][0] = 990 tx_first_pass[0][1][0] = 977 tx_last_pass[0][1][0] = 1003 tx_win_center[0][1][1] = 989 tx_first_pass[0][1][1] = 977 tx_last_pass[0][1][1] = 1001 tx_win_center[0][1][2] = 989 tx_first_pass[0][1][2] = 977 tx_last_pass[0][1][2] = 1001 tx_win_center[0][1][3] = 982 tx_first_pass[0][1][3] = 970 tx_last_pass[0][1][3] = 995 tx_win_center[0][1][4] = 988 tx_first_pass[0][1][4] = 976 tx_last_pass[0][1][4] = 1001 tx_win_center[0][1][5] = 984 tx_first_pass[0][1][5] = 972 tx_last_pass[0][1][5] = 997 tx_win_center[0][1][6] = 985 tx_first_pass[0][1][6] = 972 tx_last_pass[0][1][6] = 998 tx_win_center[0][1][7] = 987 tx_first_pass[0][1][7] = 975 tx_last_pass[0][1][7] = 999 tx_win_center[0][1][8] = 977 tx_first_pass[0][1][8] = 966 tx_last_pass[0][1][8] = 988 tx_win_center[0][1][9] = 978 tx_first_pass[0][1][9] = 967 tx_last_pass[0][1][9] = 989 tx_win_center[0][1][10] = 980 tx_first_pass[0][1][10] = 969 tx_last_pass[0][1][10] = 991 tx_win_center[0][1][11] = 977 tx_first_pass[0][1][11] = 966 tx_last_pass[0][1][11] = 988 tx_win_center[0][1][12] = 977 tx_first_pass[0][1][12] = 966 tx_last_pass[0][1][12] = 989 tx_win_center[0][1][13] = 975 tx_first_pass[0][1][13] = 964 tx_last_pass[0][1][13] = 986 tx_win_center[0][1][14] = 977 tx_first_pass[0][1][14] = 967 tx_last_pass[0][1][14] = 988 tx_win_center[0][1][15] = 979 tx_first_pass[0][1][15] = 968 tx_last_pass[0][1][15] = 990 tx_win_center[1][0][0] = 988 tx_first_pass[1][0][0] = 976 tx_last_pass[1][0][0] = 1000 tx_win_center[1][0][1] = 987 tx_first_pass[1][0][1] = 975 tx_last_pass[1][0][1] = 999 tx_win_center[1][0][2] = 983 tx_first_pass[1][0][2] = 971 tx_last_pass[1][0][2] = 995 tx_win_center[1][0][3] = 981 tx_first_pass[1][0][3] = 969 tx_last_pass[1][0][3] = 993 tx_win_center[1][0][4] = 985 tx_first_pass[1][0][4] = 973 tx_last_pass[1][0][4] = 997 tx_win_center[1][0][5] = 987 tx_first_pass[1][0][5] = 975 tx_last_pass[1][0][5] = 999 tx_win_center[1][0][6] = 988 tx_first_pass[1][0][6] = 976 tx_last_pass[1][0][6] = 1000 tx_win_center[1][0][7] = 984 tx_first_pass[1][0][7] = 973 tx_last_pass[1][0][7] = 996 tx_win_center[1][0][8] = 978 tx_first_pass[1][0][8] = 966 tx_last_pass[1][0][8] = 991 tx_win_center[1][0][9] = 978 tx_first_pass[1][0][9] = 966 tx_last_pass[1][0][9] = 990 tx_win_center[1][0][10] = 979 tx_first_pass[1][0][10] = 967 tx_last_pass[1][0][10] = 991 tx_win_center[1][0][11] = 980 tx_first_pass[1][0][11] = 968 tx_last_pass[1][0][11] = 992 tx_win_center[1][0][12] = 980 tx_first_pass[1][0][12] = 968 tx_last_pass[1][0][12] = 992 tx_win_center[1][0][13] = 980 tx_first_pass[1][0][13] = 969 tx_last_pass[1][0][13] = 991 tx_win_center[1][0][14] = 979 tx_first_pass[1][0][14] = 968 tx_last_pass[1][0][14] = 991 tx_win_center[1][0][15] = 975 tx_first_pass[1][0][15] = 963 tx_last_pass[1][0][15] = 988 tx_win_center[1][1][0] = 989 tx_first_pass[1][1][0] = 977 tx_last_pass[1][1][0] = 1002 tx_win_center[1][1][1] = 988 tx_first_pass[1][1][1] = 977 tx_last_pass[1][1][1] = 1000 tx_win_center[1][1][2] = 984 tx_first_pass[1][1][2] = 972 tx_last_pass[1][1][2] = 997 tx_win_center[1][1][3] = 982 tx_first_pass[1][1][3] = 970 tx_last_pass[1][1][3] = 995 tx_win_center[1][1][4] = 986 tx_first_pass[1][1][4] = 974 tx_last_pass[1][1][4] = 998 tx_win_center[1][1][5] = 988 tx_first_pass[1][1][5] = 976 tx_last_pass[1][1][5] = 1000 tx_win_center[1][1][6] = 989 tx_first_pass[1][1][6] = 977 tx_last_pass[1][1][6] = 1001 tx_win_center[1][1][7] = 986 tx_first_pass[1][1][7] = 975 tx_last_pass[1][1][7] = 998 tx_win_center[1][1][8] = 978 tx_first_pass[1][1][8] = 967 tx_last_pass[1][1][8] = 990 tx_win_center[1][1][9] = 977 tx_first_pass[1][1][9] = 966 tx_last_pass[1][1][9] = 989 tx_win_center[1][1][10] = 978 tx_first_pass[1][1][10] = 967 tx_last_pass[1][1][10] = 989 tx_win_center[1][1][11] = 979 tx_first_pass[1][1][11] = 968 tx_last_pass[1][1][11] = 991 tx_win_center[1][1][12] = 980 tx_first_pass[1][1][12] = 968 tx_last_pass[1][1][12] = 992 tx_win_center[1][1][13] = 979 tx_first_pass[1][1][13] = 968 tx_last_pass[1][1][13] = 990 tx_win_center[1][1][14] = 979 tx_first_pass[1][1][14] = 967 tx_last_pass[1][1][14] = 991 tx_win_center[1][1][15] = 975 tx_first_pass[1][1][15] = 963 tx_last_pass[1][1][15] = 987 dump params rx window rx_firspass[0][0][0] = 8 rx_lastpass[0][0][0] = 42 rx_firspass[0][0][1] = 8 rx_lastpass[0][0][1] = 40 rx_firspass[0][0][2] = 8 rx_lastpass[0][0][2] = 40 rx_firspass[0][0][3] = -2 rx_lastpass[0][0][3] = 32 rx_firspass[0][0][4] = 7 rx_lastpass[0][0][4] = 40 rx_firspass[0][0][5] = 2 rx_lastpass[0][0][5] = 30 rx_firspass[0][0][6] = 1 rx_lastpass[0][0][6] = 34 rx_firspass[0][0][7] = 3 rx_lastpass[0][0][7] = 35 rx_firspass[0][0][8] = 1 rx_lastpass[0][0][8] = 35 rx_firspass[0][0][9] = 4 rx_lastpass[0][0][9] = 36 rx_firspass[0][0][10] = 8 rx_lastpass[0][0][10] = 39 rx_firspass[0][0][11] = 2 rx_lastpass[0][0][11] = 31 rx_firspass[0][0][12] = 4 rx_lastpass[0][0][12] = 36 rx_firspass[0][0][13] = 1 rx_lastpass[0][0][13] = 32 rx_firspass[0][0][14] = 2 rx_lastpass[0][0][14] = 34 rx_firspass[0][0][15] = 3 rx_lastpass[0][0][15] = 36 rx_firspass[0][1][0] = 9 rx_lastpass[0][1][0] = 42 rx_firspass[0][1][1] = 7 rx_lastpass[0][1][1] = 42 rx_firspass[0][1][2] = 8 rx_lastpass[0][1][2] = 42 rx_firspass[0][1][3] = -1 rx_lastpass[0][1][3] = 32 rx_firspass[0][1][4] = 6 rx_lastpass[0][1][4] = 40 rx_firspass[0][1][5] = 0 rx_lastpass[0][1][5] = 35 rx_firspass[0][1][6] = 3 rx_lastpass[0][1][6] = 36 rx_firspass[0][1][7] = 3 rx_lastpass[0][1][7] = 36 rx_firspass[0][1][8] = 1 rx_lastpass[0][1][8] = 36 rx_firspass[0][1][9] = 2 rx_lastpass[0][1][9] = 37 rx_firspass[0][1][10] = 6 rx_lastpass[0][1][10] = 42 rx_firspass[0][1][11] = 0 rx_lastpass[0][1][11] = 34 rx_firspass[0][1][12] = 2 rx_lastpass[0][1][12] = 37 rx_firspass[0][1][13] = 0 rx_lastpass[0][1][13] = 33 rx_firspass[0][1][14] = 2 rx_lastpass[0][1][14] = 35 rx_firspass[0][1][15] = 4 rx_lastpass[0][1][15] = 37 rx_firspass[1][0][0] = 7 rx_lastpass[1][0][0] = 42 rx_firspass[1][0][1] = 6 rx_lastpass[1][0][1] = 40 rx_firspass[1][0][2] = 0 rx_lastpass[1][0][2] = 33 rx_firspass[1][0][3] = -1 rx_lastpass[1][0][3] = 32 rx_firspass[1][0][4] = 3 rx_lastpass[1][0][4] = 34 rx_firspass[1][0][5] = 8 rx_lastpass[1][0][5] = 40 rx_firspass[1][0][6] = 9 rx_lastpass[1][0][6] = 41 rx_firspass[1][0][7] = 4 rx_lastpass[1][0][7] = 34 rx_firspass[1][0][8] = 2 rx_lastpass[1][0][8] = 36 rx_firspass[1][0][9] = 3 rx_lastpass[1][0][9] = 36 rx_firspass[1][0][10] = 2 rx_lastpass[1][0][10] = 35 rx_firspass[1][0][11] = 3 rx_lastpass[1][0][11] = 36 rx_firspass[1][0][12] = 4 rx_lastpass[1][0][12] = 36 rx_firspass[1][0][13] = 4 rx_lastpass[1][0][13] = 34 rx_firspass[1][0][14] = 3 rx_lastpass[1][0][14] = 35 rx_firspass[1][0][15] = 0 rx_lastpass[1][0][15] = 33 rx_firspass[1][1][0] = 7 rx_lastpass[1][1][0] = 42 rx_firspass[1][1][1] = 5 rx_lastpass[1][1][1] = 40 rx_firspass[1][1][2] = 0 rx_lastpass[1][1][2] = 35 rx_firspass[1][1][3] = -2 rx_lastpass[1][1][3] = 33 rx_firspass[1][1][4] = 2 rx_lastpass[1][1][4] = 36 rx_firspass[1][1][5] = 5 rx_lastpass[1][1][5] = 41 rx_firspass[1][1][6] = 7 rx_lastpass[1][1][6] = 42 rx_firspass[1][1][7] = 2 rx_lastpass[1][1][7] = 36 rx_firspass[1][1][8] = 1 rx_lastpass[1][1][8] = 37 rx_firspass[1][1][9] = 2 rx_lastpass[1][1][9] = 37 rx_firspass[1][1][10] = 2 rx_lastpass[1][1][10] = 36 rx_firspass[1][1][11] = 3 rx_lastpass[1][1][11] = 38 rx_firspass[1][1][12] = 4 rx_lastpass[1][1][12] = 39 rx_firspass[1][1][13] = 3 rx_lastpass[1][1][13] = 36 rx_firspass[1][1][14] = 3 rx_lastpass[1][1][14] = 36 rx_firspass[1][1][15] = 0 rx_lastpass[1][1][15] = 34 dump params clk_delay clk_delay[0] = -1 clk_delay[1] = 0 dump params dqs_delay dqs_delay[0][0] = 0 dqs_delay[0][1] = -1 dqs_delay[1][0] = -1 dqs_delay[1][1] = 0 dump params delay_cell_unit = 762 dump source = 0x0 dump params frequency:1200 dump params rank number:2 dump params write leveling write leveling[0][0][0] = 0x0 write leveling[0][0][1] = 0x0 write leveling[0][1][0] = 0x0 write leveling[0][1][1] = 0x0 write leveling[1][0][0] = 0x0 write leveling[1][0][1] = 0x0 write leveling[1][1][0] = 0x0 write leveling[1][1][1] = 0x0 dump params cbt_cs cbt_cs[0][0] = 0x0 cbt_cs[0][1] = 0x0 cbt_cs[1][0] = 0x0 cbt_cs[1][1] = 0x0 dump params cbt_mr12 cbt_mr12[0][0] = 0x0 cbt_mr12[0][1] = 0x0 cbt_mr12[1][0] = 0x0 cbt_mr12[1][1] = 0x0 dump params tx window tx_center_min[0][0][0] = 0 tx_center_max[0][0][0] = 0 tx_center_min[0][0][1] = 0 tx_center_max[0][0][1] = 0 tx_center_min[0][1][0] = 0 tx_center_max[0][1][0] = 0 tx_center_min[0][1][1] = 0 tx_center_max[0][1][1] = 0 tx_center_min[1][0][0] = 0 tx_center_max[1][0][0] = 0 tx_center_min[1][0][1] = 0 tx_center_max[1][0][1] = 0 tx_center_min[1][1][0] = 0 tx_center_max[1][1][0] = 0 tx_center_min[1][1][1] = 0 tx_center_max[1][1][1] = 0 dump params tx window tx_win_center[0][0][0] = 0 tx_first_pass[0][0][0] = 0 tx_last_pass[0][0][0] = 0 tx_win_center[0][0][1] = 0 tx_first_pass[0][0][1] = 0 tx_last_pass[0][0][1] = 0 tx_win_center[0][0][2] = 0 tx_first_pass[0][0][2] = 0 tx_last_pass[0][0][2] = 0 tx_win_center[0][0][3] = 0 tx_first_pass[0][0][3] = 0 tx_last_pass[0][0][3] = 0 tx_win_center[0][0][4] = 0 tx_first_pass[0][0][4] = 0 tx_last_pass[0][0][4] = 0 tx_win_center[0][0][5] = 0 tx_first_pass[0][0][5] = 0 tx_last_pass[0][0][5] = 0 tx_win_center[0][0][6] = 0 tx_first_pass[0][0][6] = 0 tx_last_pass[0][0][6] = 0 tx_win_center[0][0][7] = 0 tx_first_pass[0][0][7] = 0 tx_last_pass[0][0][7] = 0 tx_win_center[0][0][8] = 0 tx_first_pass[0][0][8] = 0 tx_last_pass[0][0][8] = 0 tx_win_center[0][0][9] = 0 tx_first_pass[0][0][9] = 0 tx_last_pass[0][0][9] = 0 tx_win_center[0][0][10] = 0 tx_first_pass[0][0][10] = 0 tx_last_pass[0][0][10] = 0 tx_win_center[0][0][11] = 0 tx_first_pass[0][0][11] = 0 tx_last_pass[0][0][11] = 0 tx_win_center[0][0][12] = 0 tx_first_pass[0][0][12] = 0 tx_last_pass[0][0][12] = 0 tx_win_center[0][0][13] = 0 tx_first_pass[0][0][13] = 0 tx_last_pass[0][0][13] = 0 tx_win_center[0][0][14] = 0 tx_first_pass[0][0][14] = 0 tx_last_pass[0][0][14] = 0 tx_win_center[0][0][15] = 0 tx_first_pass[0][0][15] = 0 tx_last_pass[0][0][15] = 0 tx_win_center[0][1][0] = 0 tx_first_pass[0][1][0] = 0 tx_last_pass[0][1][0] = 0 tx_win_center[0][1][1] = 0 tx_first_pass[0][1][1] = 0 tx_last_pass[0][1][1] = 0 tx_win_center[0][1][2] = 0 tx_first_pass[0][1][2] = 0 tx_last_pass[0][1][2] = 0 tx_win_center[0][1][3] = 0 tx_first_pass[0][1][3] = 0 tx_last_pass[0][1][3] = 0 tx_win_center[0][1][4] = 0 tx_first_pass[0][1][4] = 0 tx_last_pass[0][1][4] = 0 tx_win_center[0][1][5] = 0 tx_first_pass[0][1][5] = 0 tx_last_pass[0][1][5] = 0 tx_win_center[0][1][6] = 0 tx_first_pass[0][1][6] = 0 tx_last_pass[0][1][6] = 0 tx_win_center[0][1][7] = 0 tx_first_pass[0][1][7] = 0 tx_last_pass[0][1][7] = 0 tx_win_center[0][1][8] = 0 tx_first_pass[0][1][8] = 0 tx_last_pass[0][1][8] = 0 tx_win_center[0][1][9] = 0 tx_first_pass[0][1][9] = 0 tx_last_pass[0][1][9] = 0 tx_win_center[0][1][10] = 0 tx_first_pass[0][1][10] = 0 tx_last_pass[0][1][10] = 0 tx_win_center[0][1][11] = 0 tx_first_pass[0][1][11] = 0 tx_last_pass[0][1][11] = 0 tx_win_center[0][1][12] = 0 tx_first_pass[0][1][12] = 0 tx_last_pass[0][1][12] = 0 tx_win_center[0][1][13] = 0 tx_first_pass[0][1][13] = 0 tx_last_pass[0][1][13] = 0 tx_win_center[0][1][14] = 0 tx_first_pass[0][1][14] = 0 tx_last_pass[0][1][14] = 0 tx_win_center[0][1][15] = 0 tx_first_pass[0][1][15] = 0 tx_last_pass[0][1][15] = 0 tx_win_center[1][0][0] = 0 tx_first_pass[1][0][0] = 0 tx_last_pass[1][0][0] = 0 tx_win_center[1][0][1] = 0 tx_first_pass[1][0][1] = 0 tx_last_pass[1][0][1] = 0 tx_win_center[1][0][2] = 0 tx_first_pass[1][0][2] = 0 tx_last_pass[1][0][2] = 0 tx_win_center[1][0][3] = 0 tx_first_pass[1][0][3] = 0 tx_last_pass[1][0][3] = 0 tx_win_center[1][0][4] = 0 tx_first_pass[1][0][4] = 0 tx_last_pass[1][0][4] = 0 tx_win_center[1][0][5] = 0 tx_first_pass[1][0][5] = 0 tx_last_pass[1][0][5] = 0 tx_win_center[1][0][6] = 0 tx_first_pass[1][0][6] = 0 tx_last_pass[1][0][6] = 0 tx_win_center[1][0][7] = 0 tx_first_pass[1][0][7] = 0 tx_last_pass[1][0][7] = 0 tx_win_center[1][0][8] = 0 tx_first_pass[1][0][8] = 0 tx_last_pass[1][0][8] = 0 tx_win_center[1][0][9] = 0 tx_first_pass[1][0][9] = 0 tx_last_pass[1][0][9] = 0 tx_win_center[1][0][10] = 0 tx_first_pass[1][0][10] = 0 tx_last_pass[1][0][10] = 0 tx_win_center[1][0][11] = 0 tx_first_pass[1][0][11] = 0 tx_last_pass[1][0][11] = 0 tx_win_center[1][0][12] = 0 tx_first_pass[1][0][12] = 0 tx_last_pass[1][0][12] = 0 tx_win_center[1][0][13] = 0 tx_first_pass[1][0][13] = 0 tx_last_pass[1][0][13] = 0 tx_win_center[1][0][14] = 0 tx_first_pass[1][0][14] = 0 tx_last_pass[1][0][14] = 0 tx_win_center[1][0][15] = 0 tx_first_pass[1][0][15] = 0 tx_last_pass[1][0][15] = 0 tx_win_center[1][1][0] = 0 tx_first_pass[1][1][0] = 0 tx_last_pass[1][1][0] = 0 tx_win_center[1][1][1] = 0 tx_first_pass[1][1][1] = 0 tx_last_pass[1][1][1] = 0 tx_win_center[1][1][2] = 0 tx_first_pass[1][1][2] = 0 tx_last_pass[1][1][2] = 0 tx_win_center[1][1][3] = 0 tx_first_pass[1][1][3] = 0 tx_last_pass[1][1][3] = 0 tx_win_center[1][1][4] = 0 tx_first_pass[1][1][4] = 0 tx_last_pass[1][1][4] = 0 tx_win_center[1][1][5] = 0 tx_first_pass[1][1][5] = 0 tx_last_pass[1][1][5] = 0 tx_win_center[1][1][6] = 0 tx_first_pass[1][1][6] = 0 tx_last_pass[1][1][6] = 0 tx_win_center[1][1][7] = 0 tx_first_pass[1][1][7] = 0 tx_last_pass[1][1][7] = 0 tx_win_center[1][1][8] = 0 tx_first_pass[1][1][8] = 0 tx_last_pass[1][1][8] = 0 tx_win_center[1][1][9] = 0 tx_first_pass[1][1][9] = 0 tx_last_pass[1][1][9] = 0 tx_win_center[1][1][10] = 0 tx_first_pass[1][1][10] = 0 tx_last_pass[1][1][10] = 0 tx_win_center[1][1][11] = 0 tx_first_pass[1][1][11] = 0 tx_last_pass[1][1][11] = 0 tx_win_center[1][1][12] = 0 tx_first_pass[1][1][12] = 0 tx_last_pass[1][1][12] = 0 tx_win_center[1][1][13] = 0 tx_first_pass[1][1][13] = 0 tx_last_pass[1][1][13] = 0 tx_win_center[1][1][14] = 0 tx_first_pass[1][1][14] = 0 tx_last_pass[1][1][14] = 0 tx_win_center[1][1][15] = 0 tx_first_pass[1][1][15] = 0 tx_last_pass[1][1][15] = 0 dump params rx window rx_firspass[0][0][0] = 0 rx_lastpass[0][0][0] = 0 rx_firspass[0][0][1] = 0 rx_lastpass[0][0][1] = 0 rx_firspass[0][0][2] = 0 rx_lastpass[0][0][2] = 0 rx_firspass[0][0][3] = 0 rx_lastpass[0][0][3] = 0 rx_firspass[0][0][4] = 0 rx_lastpass[0][0][4] = 0 rx_firspass[0][0][5] = 0 rx_lastpass[0][0][5] = 0 rx_firspass[0][0][6] = 0 rx_lastpass[0][0][6] = 0 rx_firspass[0][0][7] = 0 rx_lastpass[0][0][7] = 0 rx_firspass[0][0][8] = 0 rx_lastpass[0][0][8] = 0 rx_firspass[0][0][9] = 0 rx_lastpass[0][0][9] = 0 rx_firspass[0][0][10] = 0 rx_lastpass[0][0][10] = 0 rx_firspass[0][0][11] = 0 rx_lastpass[0][0][11] = 0 rx_firspass[0][0][12] = 0 rx_lastpass[0][0][12] = 0 rx_firspass[0][0][13] = 0 rx_lastpass[0][0][13] = 0 rx_firspass[0][0][14] = 0 rx_lastpass[0][0][14] = 0 rx_firspass[0][0][15] = 0 rx_lastpass[0][0][15] = 0 rx_firspass[0][1][0] = 0 rx_lastpass[0][1][0] = 0 rx_firspass[0][1][1] = 0 rx_lastpass[0][1][1] = 0 rx_firspass[0][1][2] = 0 rx_lastpass[0][1][2] = 0 rx_firspass[0][1][3] = 0 rx_lastpass[0][1][3] = 0 rx_firspass[0][1][4] = 0 rx_lastpass[0][1][4] = 0 rx_firspass[0][1][5] = 0 rx_lastpass[0][1][5] = 0 rx_firspass[0][1][6] = 0 rx_lastpass[0][1][6] = 0 rx_firspass[0][1][7] = 0 rx_lastpass[0][1][7] = 0 rx_firspass[0][1][8] = 0 rx_lastpass[0][1][8] = 0 rx_firspass[0][1][9] = 0 rx_lastpass[0][1][9] = 0 rx_firspass[0][1][10] = 0 rx_lastpass[0][1][10] = 0 rx_firspass[0][1][11] = 0 rx_lastpass[0][1][11] = 0 rx_firspass[0][1][12] = 0 rx_lastpass[0][1][12] = 0 rx_firspass[0][1][13] = 0 rx_lastpass[0][1][13] = 0 rx_firspass[0][1][14] = 0 rx_lastpass[0][1][14] = 0 rx_firspass[0][1][15] = 0 rx_lastpass[0][1][15] = 0 rx_firspass[1][0][0] = 0 rx_lastpass[1][0][0] = 0 rx_firspass[1][0][1] = 0 rx_lastpass[1][0][1] = 0 rx_firspass[1][0][2] = 0 rx_lastpass[1][0][2] = 0 rx_firspass[1][0][3] = 0 rx_lastpass[1][0][3] = 0 rx_firspass[1][0][4] = 0 rx_lastpass[1][0][4] = 0 rx_firspass[1][0][5] = 0 rx_lastpass[1][0][5] = 0 rx_firspass[1][0][6] = 0 rx_lastpass[1][0][6] = 0 rx_firspass[1][0][7] = 0 rx_lastpass[1][0][7] = 0 rx_firspass[1][0][8] = 0 rx_lastpass[1][0][8] = 0 rx_firspass[1][0][9] = 0 rx_lastpass[1][0][9] = 0 rx_firspass[1][0][10] = 0 rx_lastpass[1][0][10] = 0 rx_firspass[1][0][11] = 0 rx_lastpass[1][0][11] = 0 rx_firspass[1][0][12] = 0 rx_lastpass[1][0][12] = 0 rx_firspass[1][0][13] = 0 rx_lastpass[1][0][13] = 0 rx_firspass[1][0][14] = 0 rx_lastpass[1][0][14] = 0 rx_firspass[1][0][15] = 0 rx_lastpass[1][0][15] = 0 rx_firspass[1][1][0] = 0 rx_lastpass[1][1][0] = 0 rx_firspass[1][1][1] = 0 rx_lastpass[1][1][1] = 0 rx_firspass[1][1][2] = 0 rx_lastpass[1][1][2] = 0 rx_firspass[1][1][3] = 0 rx_lastpass[1][1][3] = 0 rx_firspass[1][1][4] = 0 rx_lastpass[1][1][4] = 0 rx_firspass[1][1][5] = 0 rx_lastpass[1][1][5] = 0 rx_firspass[1][1][6] = 0 rx_lastpass[1][1][6] = 0 rx_firspass[1][1][7] = 0 rx_lastpass[1][1][7] = 0 rx_firspass[1][1][8] = 0 rx_lastpass[1][1][8] = 0 rx_firspass[1][1][9] = 0 rx_lastpass[1][1][9] = 0 rx_firspass[1][1][10] = 0 rx_lastpass[1][1][10] = 0 rx_firspass[1][1][11] = 0 rx_lastpass[1][1][11] = 0 rx_firspass[1][1][12] = 0 rx_lastpass[1][1][12] = 0 rx_firspass[1][1][13] = 0 rx_lastpass[1][1][13] = 0 rx_firspass[1][1][14] = 0 rx_lastpass[1][1][14] = 0 rx_firspass[1][1][15] = 0 rx_lastpass[1][1][15] = 0 dump params clk_delay clk_delay[0] = 0 clk_delay[1] = 0 dump params dqs_delay dqs_delay[0][0] = 0 dqs_delay[0][1] = 0 dqs_delay[1][0] = 0 dqs_delay[1][1] = 0 dump params delay_cell_unit = 762 dump source = 0x0 dump params frequency:800 dump params rank number:2 dump params write leveling write leveling[0][0][0] = 0x0 write leveling[0][0][1] = 0x0 write leveling[0][1][0] = 0x0 write leveling[0][1][1] = 0x0 write leveling[1][0][0] = 0x0 write leveling[1][0][1] = 0x0 write leveling[1][1][0] = 0x0 write leveling[1][1][1] = 0x0 dump params cbt_cs cbt_cs[0][0] = 0x0 cbt_cs[0][1] = 0x0 cbt_cs[1][0] = 0x0 cbt_cs[1][1] = 0x0 dump params cbt_mr12 cbt_mr12[0][0] = 0x0 cbt_mr12[0][1] = 0x0 cbt_mr12[1][0] = 0x0 cbt_mr12[1][1] = 0x0 dump params tx window tx_center_min[0][0][0] = 0 tx_center_max[0][0][0] = 0 tx_center_min[0][0][1] = 0 tx_center_max[0][0][1] = 0 tx_center_min[0][1][0] = 0 tx_center_max[0][1][0] = 0 tx_center_min[0][1][1] = 0 tx_center_max[0][1][1] = 0 tx_center_min[1][0][0] = 0 tx_center_max[1][0][0] = 0 tx_center_min[1][0][1] = 0 tx_center_max[1][0][1] = 0 tx_center_min[1][1][0] = 0 tx_center_max[1][1][0] = 0 tx_center_min[1][1][1] = 0 tx_center_max[1][1][1] = 0 dump params tx window tx_win_center[0][0][0] = 0 tx_first_pass[0][0][0] = 0 tx_last_pass[0][0][0] = 0 tx_win_center[0][0][1] = 0 tx_first_pass[0][0][1] = 0 tx_last_pass[0][0][1] = 0 tx_win_center[0][0][2] = 0 tx_first_pass[0][0][2] = 0 tx_last_pass[0][0][2] = 0 tx_win_center[0][0][3] = 0 tx_first_pass[0][0][3] = 0 tx_last_pass[0][0][3] = 0 tx_win_center[0][0][4] = 0 tx_first_pass[0][0][4] = 0 tx_last_pass[0][0][4] = 0 tx_win_center[0][0][5] = 0 tx_first_pass[0][0][5] = 0 tx_last_pass[0][0][5] = 0 tx_win_center[0][0][6] = 0 tx_first_pass[0][0][6] = 0 tx_last_pass[0][0][6] = 0 tx_win_center[0][0][7] = 0 tx_first_pass[0][0][7] = 0 tx_last_pass[0][0][7] = 0 tx_win_center[0][0][8] = 0 tx_first_pass[0][0][8] = 0 tx_last_pass[0][0][8] = 0 tx_win_center[0][0][9] = 0 tx_first_pass[0][0][9] = 0 tx_last_pass[0][0][9] = 0 tx_win_center[0][0][10] = 0 tx_first_pass[0][0][10] = 0 tx_last_pass[0][0][10] = 0 tx_win_center[0][0][11] = 0 tx_first_pass[0][0][11] = 0 tx_last_pass[0][0][11] = 0 tx_win_center[0][0][12] = 0 tx_first_pass[0][0][12] = 0 tx_last_pass[0][0][12] = 0 tx_win_center[0][0][13] = 0 tx_first_pass[0][0][13] = 0 tx_last_pass[0][0][13] = 0 tx_win_center[0][0][14] = 0 tx_first_pass[0][0][14] = 0 tx_last_pass[0][0][14] = 0 tx_win_center[0][0][15] = 0 tx_first_pass[0][0][15] = 0 tx_last_pass[0][0][15] = 0 tx_win_center[0][1][0] = 0 tx_first_pass[0][1][0] = 0 tx_last_pass[0][1][0] = 0 tx_win_center[0][1][1] = 0 tx_first_pass[0][1][1] = 0 tx_last_pass[0][1][1] = 0 tx_win_center[0][1][2] = 0 tx_first_pass[0][1][2] = 0 tx_last_pass[0][1][2] = 0 tx_win_center[0][1][3] = 0 tx_first_pass[0][1][3] = 0 tx_last_pass[0][1][3] = 0 tx_win_center[0][1][4] = 0 tx_first_pass[0][1][4] = 0 tx_last_pass[0][1][4] = 0 tx_win_center[0][1][5] = 0 tx_first_pass[0][1][5] = 0 tx_last_pass[0][1][5] = 0 tx_win_center[0][1][6] = 0 tx_first_pass[0][1][6] = 0 tx_last_pass[0][1][6] = 0 tx_win_center[0][1][7] = 0 tx_first_pass[0][1][7] = 0 tx_last_pass[0][1][7] = 0 tx_win_center[0][1][8] = 0 tx_first_pass[0][1][8] = 0 tx_last_pass[0][1][8] = 0 tx_win_center[0][1][9] = 0 tx_first_pass[0][1][9] = 0 tx_last_pass[0][1][9] = 0 tx_win_center[0][1][10] = 0 tx_first_pass[0][1][10] = 0 tx_last_pass[0][1][10] = 0 tx_win_center[0][1][11] = 0 tx_first_pass[0][1][11] = 0 tx_last_pass[0][1][11] = 0 tx_win_center[0][1][12] = 0 tx_first_pass[0][1][12] = 0 tx_last_pass[0][1][12] = 0 tx_win_center[0][1][13] = 0 tx_first_pass[0][1][13] = 0 tx_last_pass[0][1][13] = 0 tx_win_center[0][1][14] = 0 tx_first_pass[0][1][14] = 0 tx_last_pass[0][1][14] = 0 tx_win_center[0][1][15] = 0 tx_first_pass[0][1][15] = 0 tx_last_pass[0][1][15] = 0 tx_win_center[1][0][0] = 0 tx_first_pass[1][0][0] = 0 tx_last_pass[1][0][0] = 0 tx_win_center[1][0][1] = 0 tx_first_pass[1][0][1] = 0 tx_last_pass[1][0][1] = 0 tx_win_center[1][0][2] = 0 tx_first_pass[1][0][2] = 0 tx_last_pass[1][0][2] = 0 tx_win_center[1][0][3] = 0 tx_first_pass[1][0][3] = 0 tx_last_pass[1][0][3] = 0 tx_win_center[1][0][4] = 0 tx_first_pass[1][0][4] = 0 tx_last_pass[1][0][4] = 0 tx_win_center[1][0][5] = 0 tx_first_pass[1][0][5] = 0 tx_last_pass[1][0][5] = 0 tx_win_center[1][0][6] = 0 tx_first_pass[1][0][6] = 0 tx_last_pass[1][0][6] = 0 tx_win_center[1][0][7] = 0 tx_first_pass[1][0][7] = 0 tx_last_pass[1][0][7] = 0 tx_win_center[1][0][8] = 0 tx_first_pass[1][0][8] = 0 tx_last_pass[1][0][8] = 0 tx_win_center[1][0][9] = 0 tx_first_pass[1][0][9] = 0 tx_last_pass[1][0][9] = 0 tx_win_center[1][0][10] = 0 tx_first_pass[1][0][10] = 0 tx_last_pass[1][0][10] = 0 tx_win_center[1][0][11] = 0 tx_first_pass[1][0][11] = 0 tx_last_pass[1][0][11] = 0 tx_win_center[1][0][12] = 0 tx_first_pass[1][0][12] = 0 tx_last_pass[1][0][12] = 0 tx_win_center[1][0][13] = 0 tx_first_pass[1][0][13] = 0 tx_last_pass[1][0][13] = 0 tx_win_center[1][0][14] = 0 tx_first_pass[1][0][14] = 0 tx_last_pass[1][0][14] = 0 tx_win_center[1][0][15] = 0 tx_first_pass[1][0][15] = 0 tx_last_pass[1][0][15] = 0 tx_win_center[1][1][0] = 0 tx_first_pass[1][1][0] = 0 tx_last_pass[1][1][0] = 0 tx_win_center[1][1][1] = 0 tx_first_pass[1][1][1] = 0 tx_last_pass[1][1][1] = 0 tx_win_center[1][1][2] = 0 tx_first_pass[1][1][2] = 0 tx_last_pass[1][1][2] = 0 tx_win_center[1][1][3] = 0 tx_first_pass[1][1][3] = 0 tx_last_pass[1][1][3] = 0 tx_win_center[1][1][4] = 0 tx_first_pass[1][1][4] = 0 tx_last_pass[1][1][4] = 0 tx_win_center[1][1][5] = 0 tx_first_pass[1][1][5] = 0 tx_last_pass[1][1][5] = 0 tx_win_center[1][1][6] = 0 tx_first_pass[1][1][6] = 0 tx_last_pass[1][1][6] = 0 tx_win_center[1][1][7] = 0 tx_first_pass[1][1][7] = 0 tx_last_pass[1][1][7] = 0 tx_win_center[1][1][8] = 0 tx_first_pass[1][1][8] = 0 tx_last_pass[1][1][8] = 0 tx_win_center[1][1][9] = 0 tx_first_pass[1][1][9] = 0 tx_last_pass[1][1][9] = 0 tx_win_center[1][1][10] = 0 tx_first_pass[1][1][10] = 0 tx_last_pass[1][1][10] = 0 tx_win_center[1][1][11] = 0 tx_first_pass[1][1][11] = 0 tx_last_pass[1][1][11] = 0 tx_win_center[1][1][12] = 0 tx_first_pass[1][1][12] = 0 tx_last_pass[1][1][12] = 0 tx_win_center[1][1][13] = 0 tx_first_pass[1][1][13] = 0 tx_last_pass[1][1][13] = 0 tx_win_center[1][1][14] = 0 tx_first_pass[1][1][14] = 0 tx_last_pass[1][1][14] = 0 tx_win_center[1][1][15] = 0 tx_first_pass[1][1][15] = 0 tx_last_pass[1][1][15] = 0 dump params rx window rx_firspass[0][0][0] = 0 rx_lastpass[0][0][0] = 0 rx_firspass[0][0][1] = 0 rx_lastpass[0][0][1] = 0 rx_firspass[0][0][2] = 0 rx_lastpass[0][0][2] = 0 rx_firspass[0][0][3] = 0 rx_lastpass[0][0][3] = 0 rx_firspass[0][0][4] = 0 rx_lastpass[0][0][4] = 0 rx_firspass[0][0][5] = 0 rx_lastpass[0][0][5] = 0 rx_firspass[0][0][6] = 0 rx_lastpass[0][0][6] = 0 rx_firspass[0][0][7] = 0 rx_lastpass[0][0][7] = 0 rx_firspass[0][0][8] = 0 rx_lastpass[0][0][8] = 0 rx_firspass[0][0][9] = 0 rx_lastpass[0][0][9] = 0 rx_firspass[0][0][10] = 0 rx_lastpass[0][0][10] = 0 rx_firspass[0][0][11] = 0 rx_lastpass[0][0][11] = 0 rx_firspass[0][0][12] = 0 rx_lastpass[0][0][12] = 0 rx_firspass[0][0][13] = 0 rx_lastpass[0][0][13] = 0 rx_firspass[0][0][14] = 0 rx_lastpass[0][0][14] = 0 rx_firspass[0][0][15] = 0 rx_lastpass[0][0][15] = 0 rx_firspass[0][1][0] = 0 rx_lastpass[0][1][0] = 0 rx_firspass[0][1][1] = 0 rx_lastpass[0][1][1] = 0 rx_firspass[0][1][2] = 0 rx_lastpass[0][1][2] = 0 rx_firspass[0][1][3] = 0 rx_lastpass[0][1][3] = 0 rx_firspass[0][1][4] = 0 rx_lastpass[0][1][4] = 0 rx_firspass[0][1][5] = 0 rx_lastpass[0][1][5] = 0 rx_firspass[0][1][6] = 0 rx_lastpass[0][1][6] = 0 rx_firspass[0][1][7] = 0 rx_lastpass[0][1][7] = 0 rx_firspass[0][1][8] = 0 rx_lastpass[0][1][8] = 0 rx_firspass[0][1][9] = 0 rx_lastpass[0][1][9] = 0 rx_firspass[0][1][10] = 0 rx_lastpass[0][1][10] = 0 rx_firspass[0][1][11] = 0 rx_lastpass[0][1][11] = 0 rx_firspass[0][1][12] = 0 rx_lastpass[0][1][12] = 0 rx_firspass[0][1][13] = 0 rx_lastpass[0][1][13] = 0 rx_firspass[0][1][14] = 0 rx_lastpass[0][1][14] = 0 rx_firspass[0][1][15] = 0 rx_lastpass[0][1][15] = 0 rx_firspass[1][0][0] = 0 rx_lastpass[1][0][0] = 0 rx_firspass[1][0][1] = 0 rx_lastpass[1][0][1] = 0 rx_firspass[1][0][2] = 0 rx_lastpass[1][0][2] = 0 rx_firspass[1][0][3] = 0 rx_lastpass[1][0][3] = 0 rx_firspass[1][0][4] = 0 rx_lastpass[1][0][4] = 0 rx_firspass[1][0][5] = 0 rx_lastpass[1][0][5] = 0 rx_firspass[1][0][6] = 0 rx_lastpass[1][0][6] = 0 rx_firspass[1][0][7] = 0 rx_lastpass[1][0][7] = 0 rx_firspass[1][0][8] = 0 rx_lastpass[1][0][8] = 0 rx_firspass[1][0][9] = 0 rx_lastpass[1][0][9] = 0 rx_firspass[1][0][10] = 0 rx_lastpass[1][0][10] = 0 rx_firspass[1][0][11] = 0 rx_lastpass[1][0][11] = 0 rx_firspass[1][0][12] = 0 rx_lastpass[1][0][12] = 0 rx_firspass[1][0][13] = 0 rx_lastpass[1][0][13] = 0 rx_firspass[1][0][14] = 0 rx_lastpass[1][0][14] = 0 rx_firspass[1][0][15] = 0 rx_lastpass[1][0][15] = 0 rx_firspass[1][1][0] = 0 rx_lastpass[1][1][0] = 0 rx_firspass[1][1][1] = 0 rx_lastpass[1][1][1] = 0 rx_firspass[1][1][2] = 0 rx_lastpass[1][1][2] = 0 rx_firspass[1][1][3] = 0 rx_lastpass[1][1][3] = 0 rx_firspass[1][1][4] = 0 rx_lastpass[1][1][4] = 0 rx_firspass[1][1][5] = 0 rx_lastpass[1][1][5] = 0 rx_firspass[1][1][6] = 0 rx_lastpass[1][1][6] = 0 rx_firspass[1][1][7] = 0 rx_lastpass[1][1][7] = 0 rx_firspass[1][1][8] = 0 rx_lastpass[1][1][8] = 0 rx_firspass[1][1][9] = 0 rx_lastpass[1][1][9] = 0 rx_firspass[1][1][10] = 0 rx_lastpass[1][1][10] = 0 rx_firspass[1][1][11] = 0 rx_lastpass[1][1][11] = 0 rx_firspass[1][1][12] = 0 rx_lastpass[1][1][12] = 0 rx_firspass[1][1][13] = 0 rx_lastpass[1][1][13] = 0 rx_firspass[1][1][14] = 0 rx_lastpass[1][1][14] = 0 rx_firspass[1][1][15] = 0 rx_lastpass[1][1][15] = 0 dump params clk_delay clk_delay[0] = 0 clk_delay[1] = 0 dump params dqs_delay dqs_delay[0][0] = 0 dqs_delay[0][1] = 0 dqs_delay[1][0] = 0 dqs_delay[1][1] = 0 dump params delay_cell_unit = 762 mt_set_emi_preloader end [mt_mem_init] dram size: 0x100000000, rank number: 2 [complex_mem_test] start addr:0x40000000, len:20480 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0 [complex_mem_test] start addr:0x80000000, len:20480 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0 [complex_mem_test] start addr:0xc0000000, len:20480 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0 [complex_mem_test] start addr:0x56000000, len:8192 [MEM] 1st complex R/W mem test pass (start addr:0x56000000) ddr_geometry:1 [complex_mem_test] start addr:0x80000000, len:8192 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1) dram_init: dram init end (result: 0) Successfully loaded DRAM blobs and ran DRAM calibration Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal CBMEM: IMD: root @ 00000000fffff000 254 entries. IMD: root @ 00000000ffffec00 62 entries. VBOOT: copying vboot_working_data (256 bytes) to CBMEM... out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00 in-header: 03 a1 00 00 08 00 00 00 in-data: 84 60 60 10 00 00 00 00 Chrome EC: clear events_b mask to 0x0000000020004000 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00 in-header: 03 fd 00 00 00 00 00 00 in-data: FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 10d40 size d563 read SPI 0x31d94 0xd547: 16639 us, 3281 KB/s, 26.248 Mbps Accumulated console time in romstage 12830 ms coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception FMAP: area RO_VPD found @ 3f8000 (32768 bytes) Manufacturer: ef SF: Detected W25Q64DW with sector size 0x1000, total 0x800000 WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 550000 (16384 bytes) FMAP: area RW_VPD found @ 550000 (16384 bytes) read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 10689 usecs done BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0 Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Setting resources... Root Device assign_resources, bus 0 link: 0 CPU_CLUSTER: 0 missing set_resources Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Done allocating resources. BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0 Initializing devices... Root Device init ... mainboard_init: Starting display init. ADC[4]: Raw value=76850 ID=0 anx7625_power_on_init: Init interface. anx7625_disable_pd_protocol: Disabled PD feature. anx7625_power_on_init: Firmware: ver 0x13, rev 0x0. anx7625_start_dp_work: Secure OCM version=00 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91 sp_tx_get_edid_block: EDID Block = 1 Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 06 af 5c 14 00 00 00 00 00 1a version: 01 04 basic params: 95 1a 0e 78 02 chroma info: 99 85 95 55 56 92 28 22 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a extensions: 00 checksum: ae Manufacturer: AUO Model 145c Serial Number 0 Made week 0 of 2016 EDID version: 1.4 Digital display 6 bits per primary color channel DisplayPort interface Maximum image size: 26 cm x 14 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4 First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: ce1d56ea50001a3030204600009010000018 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm 0556 0586 05a6 0640 hborder 0 0300 0304 030a 031a vborder 0 -hsync -vsync Did detailed timing Hex of detail: 0000000f0000000000000000000000000020 Manufacturer-specified data, tag 15 Hex of detail: 000000fe0041554f0a202020202020202020 ASCII string: AUO Hex of detail: 000000fe004231313658414230312e34200a ASCII string: B116XAB01.4 Checksum Checksum: 0xae (valid) get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz DSI data_rate: 457800000 bps anx7625_parse_edid: set default k value to 0x3d for panel anx7625_parse_edid: pixelclock(76300). hactive(1366), hsync(32), hfp(48), hbp(154) vactive(768), vsync(6), vfp(4), vbp(16) anx7625_dsi_config: config dsi. anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8). anx7625_dsi_config: success to config DSI anx7625_dp_start: MIPI phy setup OK. [SSUSB] Setting up USB HOST controller... [SSUSB] u3phy_ports_enable u2p:1, u3p:0 [SSUSB] phy power-on done. out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00 in-header: 03 fc 01 00 00 00 00 00 in-data: handle_proto3_response: EC response with error code: 1 SPM: pcm index = 1 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'pcm_allinone_lp4_3200.bin' CBFS: Found @ offset 1e7c0 size 1026 read SPI 0x3f808 0x1026: 1272 us, 3250 KB/s, 26.000 Mbps SPM: binary array size = 2988 SPM: version = pcm_allinone_v1.17.2_20180829 SPM binary loaded in 32 msecs spm_kick_im_to_fetch: ptr = 000000004021eec2 spm_kick_im_to_fetch: len = 2988 SPM: spm_kick_pcm_to_run SPM: spm_kick_pcm_to_run done SPM: spm_init done in 52 msecs Root Device init finished in 494988 usecs CPU_CLUSTER: 0 init ... Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'sspm.bin' CBFS: Found @ offset 208c0 size 41cb read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps CPU_CLUSTER: 0 init finished in 42806 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0 FMAP: area RW_ELOG found @ 558000 (4096 bytes) ELOG: NV offset 0x558000 size 0x1000 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2024-06-05 00:39:20 UTC out: cmd=0x121: 03 db 21 01 00 00 00 00 in-header: 03 ec 00 00 2c 00 00 00 in-data: 1f 48 00 00 00 00 00 00 02 10 00 00 06 80 00 00 6f 25 01 00 06 80 00 00 88 93 02 00 06 80 00 00 6f 29 06 00 06 80 00 00 5a 7a 30 00 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 19 00 00 08 00 00 00 in-data: a2 e0 47 00 13 00 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00 in-header: 03 e1 00 00 08 00 00 00 in-data: 84 20 60 10 00 00 00 00 FMAP: area RW_NVRAM found @ 554000 (8192 bytes) out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00 in-header: 03 e1 00 00 08 00 00 00 in-data: 84 20 60 10 00 00 00 00 ELOG: Event(A1) added with size 10 at 2024-06-05 00:39:20 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02 ELOG: Event(A0) added with size 9 at 2024-06-05 00:39:20 UTC elog_add_boot_reason: Logged dev mode boot Finalize devices... Devices finalized BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0 ELOG: Event(91) added with size 10 at 2024-06-05 00:39:20 UTC Writing coreboot table at 0xffeda000 0. 0000000000114000-000000000011efff: RAMSTAGE 1. 0000000040000000-000000004023cfff: RAMSTAGE 2. 000000004023d000-00000000545fffff: RAM 3. 0000000054600000-000000005465ffff: BL31 4. 0000000054660000-00000000ffed9fff: RAM 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES 6. 0000000100000000-000000013fffffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE write protect | 0x00000096 | low | high EC in RW | 0x000000b1 | high | undefined EC interrupt | 0x00000097 | low | undefined TPM interrupt | 0x00000099 | high | undefined speaker enable | 0x000000af | high | undefined out: cmd=0x6: 03 f7 06 00 00 00 00 00 in-header: 03 f7 00 00 02 00 00 00 in-data: 04 00 Board ID: 4 ADC[3]: Raw value=1034629 ID=8 RAM code: 8 SKU ID: 16 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum bb1a coreboot table: 940 bytes. IMD ROOT 0. 00000000fffff000 00001000 IMD SMALL 1. 00000000ffffe000 00001000 CONSOLE 2. 00000000fffde000 00020000 FMAP 3. 00000000fffdd000 0000047c TIME STAMP 4. 00000000fffdc000 00000910 RAMOOPS 5. 00000000ffedc000 00100000 COREBOOT 6. 00000000ffeda000 00002000 IMD small region: IMD ROOT 0. 00000000ffffec00 00000400 VBOOT WORK 1. 00000000ffffeb00 00000100 EC HOSTEVENT 2. 00000000ffffeae0 00000008 VPD 3. 00000000ffffea60 0000006c BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00 in-header: 03 e1 00 00 08 00 00 00 in-data: 84 20 60 10 00 00 00 00 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset dc040 size 439a0 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps Checking segment from ROM address 0x0000000040003a00 Checking segment from ROM address 0x0000000040003a1c Loading segment from ROM address 0x0000000040003a00 code (compression=0) New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968 it's not compressed! [ 0x80000000, 80043968, 0x811994a0) <- 40003a38 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38 Loading segment from ROM address 0x0000000040003a1c Entry Point 0x0000000080000000 Loaded segments BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0 Jumping to boot code at 0000000080000000(00000000ffeda000) CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS @ 21000 size 3d4000 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 36dc0 size 5820 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps Checking segment from ROM address 0x0000000040003a00 Checking segment from ROM address 0x0000000040003a1c Loading segment from ROM address 0x0000000040003a00 code (compression=1) New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8 using LZMA [ 0x54600000, 5460f420, 0x54629000) <- 40003a38 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0 Loading segment from ROM address 0x0000000040003a1c Entry Point 0x0000000054601000 Loaded segments NOTICE: MT8183 bl31_setup NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022 INFO: [DEVAPC] dump DEVAPC registers: INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0 INFO: [DEVAPC] MAS_DOM_0 = 0x1 INFO: [DEVAPC] MAS_DOM_1 = 0x200 INFO: [DEVAPC] MAS_DOM_2 = 0x0 INFO: [DEVAPC] MAS_DOM_3 = 0x2000 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24 WARNING: region 0: WARNING: apc:0x168, sa:0x0, ea:0xfff WARNING: region 1: WARNING: apc:0x140, sa:0x1000, ea:0x128f WARNING: region 2: WARNING: apc:0x168, sa:0x1290, ea:0x1fff WARNING: region 3: WARNING: apc:0x168, sa:0x2000, ea:0xbfff WARNING: region 4: WARNING: apc:0x168, sa:0xc000, ea:0x1ffff WARNING: region 5: WARNING: apc:0x0, sa:0x0, ea:0x0 WARNING: region 6: WARNING: apc:0x0, sa:0x0, ea:0x0 WARNING: region 7: WARNING: apc:0x0, sa:0x0, ea:0x0 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3 INFO: SPM: enable SPMC mode NOTICE: spm_boot_init() start NOTICE: spm_boot_init() end INFO: BL31: Initializing runtime services INFO: BL31: cortex_a53: CPU workaround for 855873 was applied INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x80000000 INFO: SPSR = 0x8 Starting depthcharge on Juniper... vboot_handoff: creating legacy vboot_handoff structure ec_init(0): CrosEC protocol v3 supported (544, 544) Wipe memory regions: [0x00000040000000, 0x00000054600000) [0x00000054660000, 0x00000080000000) [0x000000811994a0, 0x000000ffeda000) [0x00000100000000, 0x00000140000000) Initializing XHCI USB controller at 0x11200000. [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54 jacuzzi: tftpboot 192.168.201.1 14173524/tftp-deploy-e3uml72i/kernel/image.itb 14173524/tftp-deploy-e3uml72i/kernel/cmdline tftpboot 192.168.201.1 14173524/tftp-deploy-e3uml72i/kernel/image.ittp-deploy-e3uml72i/kernel/cmdline Waiting for link R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device done. MAC: 00:e0:4c:71:a7:1f Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.23 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 14173524/tftp-deploy-e3uml72i/kernel/image.itb Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ################################################################ 00d00000 ################################################################ 00d80000 ################################################################ 00e00000 ################################################################ 00e80000 ################################################################ 00f00000 ################################################################ 00f80000 ################################################################ 01000000 ################################################################ 01080000 ################################################################ 01100000 ################################################################ 01180000 ################################################################ 01200000 ################################################################ 01280000 ################################################################ 01300000 ################################################################ 01380000 ################################################################ 01400000 ################################################################ 01480000 ################################################################ 01500000 ################################################################ 01580000 ################################################################ 01600000 ################################################################ 01680000 ################################################################ 01700000 ################################################################ 01780000 ################################################################ 01800000 ################################################################ 01880000 ################################################################ 01900000 ################################################################ 01980000 ################################################################ 01a00000 ################################################################ 01a80000 ################################################################ 01b00000 ################################################################ 01b80000 ################################################################ 01c00000 ################################################################ 01c80000 ################################################################ 01d00000 ################################################################ 01d80000 ################################################################ 01e00000 ################################################################ 01e80000 ################################################################ 01f00000 ################################################################ 01f80000 ################################################################ 02000000 ################################################################ 02080000 ################################################ done. The bootfile was 34466178 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 14173524/tftp-deploy-e3uml72i/kernel/cmdline The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 Loading FIT. Image ramdisk-1 has 21346514 bytes. Image fdt-1 has 57695 bytes. Image kernel-1 has 13059919 bytes. Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183 Choosing best match conf-1 for compat google,juniper-sku16. Connected to device vid:did:rid of 1ae0:0028:00 tpm_get_response: command 0x17b, return code 0x0 tpm_cleanup: add release locality here. Shutting down all USB controllers. Removing current net device Exiting depthcharge with code 4 at timestamp: 34158952 LZMA decompressing kernel-1 to 0x80193568 LZMA decompressing kernel-1 to 0x40000000 jumping to kernel [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024 [ 0.000000] random: crng init done [ 0.000000] Machine model: Google juniper sku16 board [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8') [ 0.000000] printk: bootconsole [mtk8250] enabled [ 0.000000] NUMA: No NUMA configuration found [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff] [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff] [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff] [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.1 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI) [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space. <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off <6>[ 0.000000] software IO TLB: area num 8. <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB) <6>[ 0.000000] Memory: 3894356K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 264108K reserved, 32768K cma-reserved) <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation. <6>[ 0.000000] rcu: RCU event tracing is enabled. <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8. <6>[ 0.000000] Trampoline variant of Tasks RCU enabled. <6>[ 0.000000] Tracing variant of Tasks RCU enabled. <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode <6>[ 0.000000] GICv3: 640 SPIs implemented <6>[ 0.000000] GICv3: 0 Extended SPIs implemented <6>[ 0.000000] Root IRQ handler: gic_handle_irq <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] } <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] } <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys). <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns <6>[ 0.009477] Console: colour dummy device 80x25 <6>[ 0.014501] printk: console [tty1] enabled <6>[ 0.018886] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000) <6>[ 0.029350] pid_max: default: 32768 minimum: 301 <6>[ 0.034231] LSM: Security Framework initializing <6>[ 0.039145] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.046769] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <4>[ 0.055640] cacheinfo: Unable to detect cache hierarchy for CPU 0 <6>[ 0.062263] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.069709] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.076061] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.083506] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.089965] printk: bootconsole [mtk8250] printing thread started <6>[ 0.089980] rcu: Hierarchical SRCU implementation. <6>[ 0.089982] rcu: Max phase no-delay instances is 1000. <6>[ 0.090012] printk: console [tty1] printing thread started <6>[ 0.092478] EFI services will not be available. <6>[ 0.092657] smp: Bringing up secondary CPUs ... <6>[ 0.093130] Detected VIPT I-cache on CPU1 <4>[ 0.093177] cacheinfo: Unable to detect cache hierarchy for CPU 1 <6>[ 0.093184] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000 <6>[ 0.093215] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] <6>[ 0.093697] Detected VIPT I-cache on CPU2 <4>[ 0.093729] cacheinfo: Unable to detect cache hierarchy for CPU 2 <6>[ 0.093734] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000 <6>[ 0.093745] CPU2: Booted secondary processor 0x0000000002 [0x410fd034] <6>[ 0.174924] Detected VIPT I-cache on CPU3 <4>[ 0.174954] cacheinfo: Unable to detect cache hierarchy for CPU 3 <6>[ 0.174958] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000 <6>[ 0.174969] CPU3: Booted secondary processor 0x0000000003 [0x410fd034] <6>[ 0.175544] CPU features: detected: Spectre-v2 <6>[ 0.175554] CPU features: detected: Spectre-BHB <6>[ 0.175557] CPU features: detected: ARM erratum 858921 <6>[ 0.175562] Detected VIPT I-cache on CPU4 <4>[ 0.175609] cacheinfo: Unable to detect cache hierarchy for CPU 4 <6>[ 0.175617] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000 <6>[ 0.175624] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.175634] arch_timer: CPU4: Trapping CNTVCT access <6>[ 0.175642] CPU4: Booted secondary processor 0x0000000100 [0x410fd092] <6>[ 0.176132] Detected VIPT I-cache on CPU5 <4>[ 0.176171] cacheinfo: Unable to detect cache hierarchy for CPU 5 <6>[ 0.176176] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000 <6>[ 0.176183] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.176189] arch_timer: CPU5: Trapping CNTVCT access <6>[ 0.176194] CPU5: Booted secondary processor 0x0000000101 [0x410fd092] <6>[ 0.176632] Detected VIPT I-cache on CPU6 <4>[ 0.176677] cacheinfo: Unable to detect cache hierarchy for CPU 6 <6>[ 0.176683] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000 <6>[ 0.176689] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.176695] arch_timer: CPU6: Trapping CNTVCT access <6>[ 0.176700] CPU6: Booted secondary processor 0x0000000102 [0x410fd092] <6>[ 0.177232] Detected VIPT I-cache on CPU7 <4>[ 0.177275] cacheinfo: Unable to detect cache hierarchy for CPU 7 <6>[ 0.177280] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000 <6>[ 0.177287] arch_timer: Enabling local workaround for ARM erratum 858921 <6>[ 0.177293] arch_timer: CPU7: Trapping CNTVCT access <6>[ 0.177298] CPU7: Booted secondary processor 0x0000000103 [0x410fd092] <6>[ 0.177345] smp: Brought up 1 node, 8 CPUs <6>[ 0.177350] SMP: Total of 8 processors activated. <6>[ 0.398260] printk: console [ttyS0]< printing thread started 6>[<6>[ 0.398286] printk: console [ttyS0] enabled 0.177353] CPU features: detected: 32-bit EL0 Support <6>[ 0.398290] printk: bootconsole [mtk8250] disabled <6>[ 0.413937] printk: bootconsole [mtk8250] printing thread stopped <3>[ 0.414363] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47 <3>[ 0.414368] mt6577-uart 11003000.serial: Error applying setting, reverse things back <6>[ 0.434715] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2 <6>[ 0.434876] serial serial0: tty port ttyS1 registered <6>[ 0.436123] SuperH (H)SCI(F) driver initialized <6>[ 0.436729] msm_serial: driver initialized <6>[ 0.442525] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000 <6>[ 0.442562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000 <6>[ 0.442589] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000 <6>[ 0.442613] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000 <6>[ 0.442637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000 <6>[ 0.442669] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000 <6>[ 0.442694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000 <6>[ 0.442719] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000 <6>[ 0.442742] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000 <6>[ 0.442813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000 <4>[ 0.454897] cacheinfo: Unable to detect cache hierarchy for CPU 0 <6>[ 0.457903] loop: module loaded <6>[ 0.466401] vsim1: Bringing 1800000uV into 2700000-2700000uV <6>[ 0.478326] megasas: 07.719.03.00-rc1 <6>[ 0.483050] spi-nor spi1.0: w25q64dw (8192 Kbytes) <6>[ 0.493071] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2 <6>[ 0.505008] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0) <6>[ 0.560472] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1d <6>[ 0.979122] Freeing initrd memory: 20844K <4>[ 0.990600] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m' <4>[ 0.990606] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22-rt12 #1 <4>[ 0.990613] Hardware name: Google juniper sku16 board (DT) <4>[ 0.990616] Call trace: <4>[ 0.990619] dump_backtrace.part.0+0xe0/0xf0 <4>[ 0.990634] show_stack+0x18/0x30 <4>[ 0.990641] dump_stack_lvl+0x68/0x84 <4>[ 0.990650] dump_stack+0x18/0x34 <4>[ 0.990655] sysfs_warn_dup+0x64/0x80 <4>[ 0.990661] sysfs_do_create_link_sd+0xf0/0x100 <4>[ 0.990665] sysfs_create_link+0x20/0x40 <4>[ 0.990668] bus_add_device+0x68/0x10c <4>[ 0.990675] device_add+0x340/0x7ac <4>[ 0.990680] of_device_add+0x44/0x60 <4>[ 0.990688] of_platform_device_create_pdata+0x90/0x120 <4>[ 0.990692] of_platform_bus_create+0x170/0x370 <4>[ 0.990696] of_platform_populate+0x50/0xfc <4>[ 0.990700] parse_mtd_partitions+0x1dc/0x510 <4>[ 0.990706] mtd_device_parse_register+0xf8/0x2e0 <4>[ 0.990710] spi_nor_probe+0x21c/0x2f0 <4>[ 0.990717] spi_mem_probe+0x6c/0xb0 <4>[ 0.990723] spi_probe+0x84/0xe4 <4>[ 0.990727] really_probe+0xbc/0x2e0 <4>[ 0.990732] __driver_probe_device+0x78/0x11c <4>[ 0.990737] driver_probe_device+0xd8/0x160 <4>[ 0.990742] __device_attach_driver+0xb8/0x134 <4>[ 0.990747] bus_for_each_drv+0x78/0xd0 <4>[ 0.990751] __device_attach+0xa8/0x1c0 <4>[ 0.990756] device_initial_probe+0x14/0x20 <4>[ 0.990761] bus_probe_device+0x9c/0xa4 <4>[ 0.990765] device_add+0x3ac/0x7ac <4>[ 0.990769] __spi_add_device+0x78/0x120 <4>[ 0.990774] spi_add_device+0x40/0x7c <4>[ 0.990779] spi_register_controller+0x610/0xad0 <4>[ 0.990784] devm_spi_register_controller+0x4c/0xa4 <4>[ 0.990790] mtk_spi_probe+0x3f8/0x650 <4>[ 0.990795] platform_probe+0x68/0xe0 <4>[ 0.990801] really_probe+0xbc/0x2e0 <4>[ 0.990805] __driver_probe_device+0x78/0x11c <4>[ 0.990810] driver_probe_device+0xd8/0x160 <4>[ 0.990815] __driver_attach+0x94/0x19c <4>[ 0.990819] bus_for_each_dev+0x70/0xd0 <4>[ 0.990823] driver_attach+0x24/0x30 <4>[ 0.990827] bus_add_driver+0x154/0x20c <4>[ 0.990832] driver_register+0x78/0x130 <4>[ 0.990837] __platform_driver_register+0x28/0x34 <4>[ 0.990843] mtk_spi_driver_init+0x1c/0x28 <4>[ 0.990850] do_one_initcall+0x50/0x1d0 <4>[ 0.990854] kernel_init_freeable+0x21c/0x288 <4>[ 0.990861] kernel_init+0x24/0x12c <4>[ 0.990867] ret_from_fork+0x10/0x20 <6>[ 0.995956] tun: Universal TUN/TAP device driver, 1.6 <6>[ 0.996901] thunder_xcv, ver 1.0 <6>[ 0.996920] thunder_bgx, ver 1.0 <6>[ 0.996936] nicpf, ver 1.0 <6>[ 0.998334] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version <6>[ 0.998339] hns3: Copyright (c) 2017 Huawei Corporation. <6>[ 0.998370] hclge is initializing <6>[ 0.998383] e1000: Intel(R) PRO/1000 Network Driver <6>[ 0.998386] e1000: Copyright (c) 1999-2006 Intel Corporation. <6>[ 0.998407] e1000e: Intel(R) PRO/1000 Network Driver <6>[ 0.998409] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. <6>[ 0.998430] igb: Intel(R) Gigabit Ethernet Network Driver <6>[ 0.998433] igb: Copyright (c) 2007-2014 Intel Corporation. <6>[ 0.998448] igbvf: Intel(R) Gigabit Virtual Function Network Driver <6>[ 0.998450] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. <6>[ 0.998821] sky2: driver version 1.30 <6>[ 1.000135] usbcore: registered new device driver r8152-cfgselector <6>[ 1.000152] usbcore: registered new interface driver r8152 <6>[ 1.000239] VFIO - User Level meta-driver version: 0.3 <6>[ 1.002609] mtu3 11201000.usb: uwk - reg:0x420, version:101 <4>[ 1.002641] mtu3 11201000.usb: supply vbus not found, using dummy regulator <6>[ 1.002694] mtu3 11201000.usb: dr_mode: 1, drd: auto <6>[ 1.002698] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0 <6>[ 1.002876] mtu3 11201000.usb: usb3-drd: 0 <6>[ 1.004040] mtu3 11201000.usb: xHCI platform device register success... <4>[ 1.005813] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator <6>[ 1.006170] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 1.006183] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1 <6>[ 1.006251] xhci-mtk 11200000.usb: USB3 root hub has no ports <6>[ 1.006256] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010 <6>[ 1.006293] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000 <6>[ 1.006366] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 1.006372] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2 <6>[ 1.006378] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed <6>[ 1.006681] hub 1-0:1.0: USB hub found <6>[ 1.006696] hub 1-0:1.0: 1 port detected <6>[ 1.007833] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. <6>[ 1.008080] hub 2-0:1.0: USB hub found <3>[ 1.008093] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19) <6>[ 1.008574] usbcore: registered new interface driver usb-storage <6>[ 1.008870] usbcore: registered new device driver onboard-usb-hub <4>[ 1.009164] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator <6>[ 1.012727] mt6397-rtc mt6358-rtc: registered as rtc0 <6>[ 1.012877] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-05T00:39:42 UTC (1717547982) <6>[ 1.013733] i2c_dev: i2c /dev entries driver <6>[ 1.015566] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58 <6>[ 1.015610] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58 <6>[ 1.015643] i2c 4-0058: Fixed dependency cycle(s) with /panel <6>[ 1.015670] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000 <3>[ 1.016159] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host. <6>[ 1.025248] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0) <6>[ 1.028587] cpu cpu0: EM: created perf domain <6>[ 1.029406] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz <6>[ 1.029629] cpu cpu4: EM: created perf domain <6>[ 1.034447] sdhci: Secure Digital Host Controller Interface driver <6>[ 1.034453] sdhci: Copyright(c) Pierre Ossman <6>[ 1.035164] Synopsys Designware Multimedia Card Interface Driver <6>[ 1.035643] mtk-msdc 11240000.mmc: allocated mmc-pwrseq <6>[ 1.036177] sdhci-pltfm: SDHCI platform and OF driver helper <6>[ 1.037978] ledtrig-cpu: registered to indicate activity on CPUs <6>[ 1.039473] usbcore: registered new interface driver usbhid <6>[ 1.039478] usbhid: USB HID core driver <6>[ 1.039679] spi_master spi2: will run message pump with realtime priority <4>[ 1.039909] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator <4>[ 1.040025] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator <6>[ 1.052975] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0 <6>[ 1.055144] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1 <6>[ 1.056137] cros-ec-spi spi2.0: Chrome EC device registered <4>[ 1.105345] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes) <6>[ 1.110654] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound <4>[ 1.112771] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes) <6>[ 1.113561] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <6>[ 1.114516] NET: Registered PF_PACKET protocol family <6>[ 1.114579] 9pnet: Installing 9P2000 support <5>[ 1.114606] Key type dns_resolver registered <6>[ 1.114957] registered taskstats version 1 <5>[ 1.114966] Loading compiled-in X.509 certificates <4>[ 1.116339] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes) <4>[ 1.116976] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes) <6>[ 1.120743] mmc1: new ultra high speed SDR104 SDIO card at address 0001 <6>[ 1.142882] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x11c14 <6>[ 1.143150] mmc0: new HS400 MMC card at address 0001 <6>[ 1.143762] mmcblk0: mmc0:0001 TB2932 29.2 GiB <3>[ 1.143868] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517 <6>[ 1.146228] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 <6>[ 1.147147] mmcblk0boot0: mmc0:0001 TB2932 4.00 MiB <6>[ 1.148365] mmcblk0boot1: mmc0:0001 TB2932 4.00 MiB <6>[ 1.149273] mmcblk0rpmb: mmc0:0001 TB2932 4.00 MiB, chardev (507:0) <4>[ 1.163771] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW <6>[ 1.164395] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20 <6>[ 1.167046] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19 <3>[ 1.167521] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present! <6>[ 1.186277] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input3 <6>[ 1.186755] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c <3>[ 1.200922] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t' <3>[ 1.201813] debugfs: File 'Playback' in directory 'dapm' already present! <3>[ 1.201821] debugfs: File 'Capture' in directory 'dapm' already present! <6>[ 1.204373] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input2 <6>[ 1.208404] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops) <6>[ 1.208424] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops) <6>[ 1.208431] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops) <6>[ 1.208437] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops) <6>[ 1.208443] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops) <6>[ 1.208449] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops) <6>[ 1.208456] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops) <6>[ 1.209249] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0 <6>[ 1.210498] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0 <6>[ 1.211409] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0 <6>[ 1.212202] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0 <6>[ 1.212936] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0 <6>[ 1.214916] panfrost 13040000.gpu: clock rate = 511999970 <6>[ 1.214935] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet <6>[ 1.215458] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0 <6>[ 1.215463] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400 <6>[ 1.215468] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7 <6>[ 1.215474] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1 <6>[ 1.217569] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0 <6>[ 1.218900] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 1.218918] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 1.218925] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 1.218932] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 1.218939] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 1.218946] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops) <6>[ 1.218954] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops) <6>[ 1.218961] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops) <6>[ 1.218968] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops) <6>[ 1.284336] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops) <6>[ 1.284510] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing <6>[ 1.285701] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1 <6>[ 1.429698] usb 1-1: new high-speed USB device number 2 using xhci-mtk <6>[ 1.582260] hub 1-1:1.0: USB hub found <6>[ 1.582798] hub 1-1:1.0: 3 ports detected <6>[ 1.959291] Console: switching to colour frame buffer device 170x48 <6>[ 1.975834] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device <6>[ 1.983635] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input5 <6>[ 1.984268] input: volume-buttons as /devices/platform/volume-buttons/input/input6 <6>[ 2.269724] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk <6>[ 2.466158] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk <4>[ 2.590275] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2 <4>[ 2.590292] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2) <6>[ 2.635614] r8152 1-1.2:1.0 eth0: v1.12.13 <6>[ 2.721835] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk <6>[ 4.482777] r8152 1-1.2:1.0 eth0: carrier on <5>[ 4.505720] Sending DHCP requests . <3>[ 5.622091] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[6596b4e5] <3>[ 5.626040] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[6596b4e5] <4>[ 7.405713] ., OK <6>[ 7.421758] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.23 <6>[ 7.421773] IP-Config: Complete: <6>[ 7.421775] device=eth0, hwaddr=00:e0:4c:71:a7:1f, ipaddr=192.168.201.23, mask=255.255.255.0, gw=192.168.201.1 <6>[ 7.421788] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-3, domain=lava-rack, nis-domain=(none) <6>[ 7.421795] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath= Starting syslogd<6>[ 7.421802] nameserver0=192.168.201.1 : OK<6>[ 7.422112] clk: Disabling unused clocks Starting klogd<6>[ 7.422915] ALSA device list: : OK <6>[ 7.422922] #0: mt8183_mt6358_ts3a227_max98357 Running sysctl: <6>[ 7.429479] Freeing unused kernel memory: 8512K OK <6>[ 7.429645] Run /init as init process Populating /dev using udev: <30>[ 7.505953] udevd[210]: starting version 3.2.9 <27>[ 7.507942] udevd[210]: specified user 'tss' unknown <27>[ 7.507968] udevd[210]: specified group 'tss' unknown <30>[ 7.509166] udevd[211]: starting eudev-3.2.9 <27>[ 7.533629] udevd[211]: specified user 'tss' unknown <27>[ 7.533792] udevd[211]: specified group 'tss' unknown <3>[ 7.681617] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015 <3>[ 7.681632] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22 <3>[ 7.681637] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris <3>[ 7.681643] elan_i2c 2-0015: Error applying setting, reverse things back <4>[ 7.710118] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator <4>[ 7.710421] elants_i2c 0-0010: supply vccio not found, using dummy regulator <3>[ 7.728296] thermal_sys: Failed to find 'trips' node <3>[ 7.728303] thermal_sys: Failed to find trip points for thermal-sensor1 id=0 <3>[ 7.728309] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22 <4>[ 7.728313] generic-adc-thermal: probe of thermal-sensor1 failed with error -22 <3>[ 7.729548] thermal_sys: Failed to find 'trips' node <3>[ 7.729552] thermal_sys: Failed to find trip points for thermal-sensor2 id=0 <3>[ 7.729558] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22 <4>[ 7.729561] generic-adc-thermal: probe of thermal-sensor2 failed with error -22 <6>[ 7.734040] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered <5>[ 7.746534] cfg80211: Loading compiled-in X.509 certificates for regulatory database <3>[ 7.753733] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753757] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753765] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753876] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753885] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753893] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753902] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753909] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <3>[ 7.753944] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0 <6>[ 7.754108] mc: Linux media interface: v0.10 <5>[ 7.765297] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' <5>[ 7.766358] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600' <4>[ 7.766423] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 <6>[ 7.766430] cfg80211: failed to load regulatory.db <6>[ 7.792073] videodev: Linux video capture interface: v2.00 <6>[ 7.801027] cs_system_cfg: CoreSight Configuration manager initialised <6>[ 7.808437] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized <6>[ 7.808528] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized <6>[ 7.808582] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized <6>[ 7.808635] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized <6>[ 7.816564] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized <6>[ 7.816685] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized <6>[ 7.816766] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized <6>[ 7.816826] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized <6>[ 7.861713] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7 <3>[ 7.891380] mtk-scp 10500000.scp: invalid resource <6>[ 7.891455] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000 <6>[ 7.905961] remoteproc remoteproc0: scp is available <4>[ 7.906062] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2 <6>[ 7.906071] remoteproc remoteproc0: powering up scp <4>[ 7.906094] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2 <3>[ 7.906099] remoteproc remoteproc0: request_firmware failed: -2 <6>[ 7.906641] Bluetooth: Core ver 2.22 <6>[ 7.906685] NET: Registered PF_BLUETOOTH protocol family <6>[ 7.906687] Bluetooth: HCI device and connection manager initialized <6>[ 7.906700] Bluetooth: HCI socket layer initialized <6>[ 7.906704] Bluetooth: L2CAP socket layer initialized <6>[ 7.906712] Bluetooth: SCO socket layer initialized <6>[ 7.956309] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567) <6>[ 7.962706] Bluetooth: HCI UART driver ver 2.3 <6>[ 7.962713] Bluetooth: HCI UART protocol H4 registered <6>[ 7.962750] Bluetooth: HCI UART protocol LL registered <6>[ 7.962762] Bluetooth: HCI UART protocol Three-wire (H5) registered <6>[ 7.963078] Bluetooth: HCI UART protocol Broadcom registered <6>[ 7.963113] Bluetooth: HCI UART protocol QCA registered <6>[ 7.963126] Bluetooth: HCI UART protocol Marvell registered <6>[ 7.963868] Bluetooth: hci0: setting up ROME/QCA6390 <6>[ 7.971196] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0 <6>[ 7.971263] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0 <6>[ 7.971800] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0) <6>[ 7.972272] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1 <6>[ 7.974853] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8 <6>[ 7.975238] usbcore: registered new interface driver uvcvideo <6>[ 7.982462] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000 <6>[ 7.982476] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0 <6>[ 7.982875] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77 <6>[ 8.131468] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91 <4>[ 8.141231] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA. <4>[ 8.141231] Fallback method does not support PEC. <3>[ 8.146749] power_supply sbs-12-000b: driver failed to report `technology' property: -5 <3>[ 8.154381] power_supply sbs-12-000b: driver failed to report `technology' property: -5 <3>[ 8.177304] Bluetooth: hci0: Frame reassembly failed (-84) done Saving random seed: OK Starting network: ip: RTNETLINK answers: File exists FAIL Starting dropbear sshd: <6>[ 8.363032] NET: Registered PF_INET6 protocol family <6>[ 8.364100] Segment Routing with IPv6 OK <6>[ 8.364114] In-situ OAM (IOAM) with IPv6 /bin/sh: can't access tty; job control turned off / # / # # <6>[ 8.456019] Bluetooth: hci0: QCA Product ID :0x00000008 <6>[ 8.456031] Bluetooth: hci0: QCA SOC Version :0x00000044 <6>[ 8.456034] Bluetooth: hci0: QCA ROM Version :0x00000302 <6>[ 8.456036] Bluetooth: hci0: QCA Patch Version:0x00000111 <6>[ 8.456039] Bluetooth: hci0: QCA controller version 0x00440302 <6>[ 8.456043] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin <4>[ 8.456090] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2 <3>[ 8.456098] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2) <3>[ 8.456101] Bluetooth: hci0: QCA Failed to download patch (-2) <6>[ 8.490768] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1 # / # export SHELL=/bin/sh <4>[ 8.561531] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes) <4>[ 8.570395] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes) <4>[ 8.573596] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes) <4>[ 8.574607] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes) export SHELL=/bin/sh / # . /lava-14173524/environment . /lava-14173524/environment / # /lava-14173524/bin/lava-test-runner /lava-14173524/0 /lava-14173524/bin/lava-test-runner /lava-14173524/0 + export 'TESTRUN_ID=0_dmesg' + cd /lava-14173524<8>[ 8.889377] /0/tests/0_dmesg + cat uuid + UUID=14173524_1.5.2.3.1 + set +x + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh <8>[ 8.905891] <8>[ 8.919325] + set +x