Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 28
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 22
1 00:42:15.440886 lava-dispatcher, installed at version: 2024.03
2 00:42:15.441100 start: 0 validate
3 00:42:15.441236 Start time: 2024-06-05 00:42:15.441229+00:00 (UTC)
4 00:42:15.441362 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:42:15.441491 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 00:42:15.699968 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:42:15.700143 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:42:47.210277 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:42:47.211016 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:42:47.464279 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:42:47.465009 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.92-cip22-168-g96fd74998d4ca%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:42:49.711417 validate duration: 34.27
14 00:42:49.711785 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:42:49.711944 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:42:49.712077 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:42:49.712264 Not decompressing ramdisk as can be used compressed.
18 00:42:49.712394 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 00:42:49.712504 saving as /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/ramdisk/rootfs.cpio.gz
20 00:42:49.712604 total size: 8181887 (7 MB)
21 00:42:49.970280 progress 0 % (0 MB)
22 00:42:49.974114 progress 5 % (0 MB)
23 00:42:49.977890 progress 10 % (0 MB)
24 00:42:49.981509 progress 15 % (1 MB)
25 00:42:49.985182 progress 20 % (1 MB)
26 00:42:49.988717 progress 25 % (1 MB)
27 00:42:49.992430 progress 30 % (2 MB)
28 00:42:49.996408 progress 35 % (2 MB)
29 00:42:49.999609 progress 40 % (3 MB)
30 00:42:50.003344 progress 45 % (3 MB)
31 00:42:50.006578 progress 50 % (3 MB)
32 00:42:50.010331 progress 55 % (4 MB)
33 00:42:50.013720 progress 60 % (4 MB)
34 00:42:50.017395 progress 65 % (5 MB)
35 00:42:50.020605 progress 70 % (5 MB)
36 00:42:50.024208 progress 75 % (5 MB)
37 00:42:50.027448 progress 80 % (6 MB)
38 00:42:50.031068 progress 85 % (6 MB)
39 00:42:50.034251 progress 90 % (7 MB)
40 00:42:50.037854 progress 95 % (7 MB)
41 00:42:50.041082 progress 100 % (7 MB)
42 00:42:50.041397 7 MB downloaded in 0.33 s (23.73 MB/s)
43 00:42:50.041609 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:42:50.041993 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:42:50.042136 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:42:50.042267 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:42:50.042437 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:42:50.042546 saving as /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/kernel/Image
50 00:42:50.042662 total size: 54682112 (52 MB)
51 00:42:50.042773 No compression specified
52 00:42:50.044711 progress 0 % (0 MB)
53 00:42:50.060795 progress 5 % (2 MB)
54 00:42:50.075237 progress 10 % (5 MB)
55 00:42:50.090716 progress 15 % (7 MB)
56 00:42:50.106015 progress 20 % (10 MB)
57 00:42:50.121369 progress 25 % (13 MB)
58 00:42:50.136620 progress 30 % (15 MB)
59 00:42:50.151732 progress 35 % (18 MB)
60 00:42:50.167033 progress 40 % (20 MB)
61 00:42:50.182058 progress 45 % (23 MB)
62 00:42:50.196706 progress 50 % (26 MB)
63 00:42:50.210927 progress 55 % (28 MB)
64 00:42:50.226097 progress 60 % (31 MB)
65 00:42:50.240661 progress 65 % (33 MB)
66 00:42:50.255458 progress 70 % (36 MB)
67 00:42:50.269703 progress 75 % (39 MB)
68 00:42:50.285227 progress 80 % (41 MB)
69 00:42:50.300693 progress 85 % (44 MB)
70 00:42:50.315656 progress 90 % (46 MB)
71 00:42:50.330621 progress 95 % (49 MB)
72 00:42:50.345166 progress 100 % (52 MB)
73 00:42:50.345437 52 MB downloaded in 0.30 s (172.24 MB/s)
74 00:42:50.345602 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:42:50.345849 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:42:50.345974 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:42:50.346091 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:42:50.346271 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:42:50.346374 saving as /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/dtb/mt8192-asurada-spherion-r0.dtb
81 00:42:50.346471 total size: 47258 (0 MB)
82 00:42:50.346559 No compression specified
83 00:42:50.348312 progress 69 % (0 MB)
84 00:42:50.348646 progress 100 % (0 MB)
85 00:42:50.348813 0 MB downloaded in 0.00 s (19.27 MB/s)
86 00:42:50.348957 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:42:50.349200 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:42:50.349286 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:42:50.349370 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:42:50.349506 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.92-cip22-168-g96fd74998d4ca/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:42:50.349574 saving as /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/modules/modules.tar
93 00:42:50.349635 total size: 8605984 (8 MB)
94 00:42:50.349697 Using unxz to decompress xz
95 00:42:50.354263 progress 0 % (0 MB)
96 00:42:50.375279 progress 5 % (0 MB)
97 00:42:50.404886 progress 10 % (0 MB)
98 00:42:50.437659 progress 15 % (1 MB)
99 00:42:50.463026 progress 20 % (1 MB)
100 00:42:50.489811 progress 25 % (2 MB)
101 00:42:50.517171 progress 30 % (2 MB)
102 00:42:50.543935 progress 35 % (2 MB)
103 00:42:50.573442 progress 40 % (3 MB)
104 00:42:50.598339 progress 45 % (3 MB)
105 00:42:50.624511 progress 50 % (4 MB)
106 00:42:50.651908 progress 55 % (4 MB)
107 00:42:50.679131 progress 60 % (4 MB)
108 00:42:50.706236 progress 65 % (5 MB)
109 00:42:50.734801 progress 70 % (5 MB)
110 00:42:50.761886 progress 75 % (6 MB)
111 00:42:50.793643 progress 80 % (6 MB)
112 00:42:50.821204 progress 85 % (7 MB)
113 00:42:50.848722 progress 90 % (7 MB)
114 00:42:50.875500 progress 95 % (7 MB)
115 00:42:50.902946 progress 100 % (8 MB)
116 00:42:50.908789 8 MB downloaded in 0.56 s (14.68 MB/s)
117 00:42:50.909247 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:42:50.909736 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:42:50.909883 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:42:50.910020 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:42:50.910201 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:42:50.910338 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:42:50.910670 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv
125 00:42:50.910878 makedir: /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin
126 00:42:50.911056 makedir: /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/tests
127 00:42:50.911249 makedir: /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/results
128 00:42:50.911451 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-add-keys
129 00:42:50.911694 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-add-sources
130 00:42:50.911882 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-background-process-start
131 00:42:50.912099 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-background-process-stop
132 00:42:50.912309 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-common-functions
133 00:42:50.912576 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-echo-ipv4
134 00:42:50.912800 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-install-packages
135 00:42:50.913055 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-installed-packages
136 00:42:50.913249 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-os-build
137 00:42:50.913432 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-probe-channel
138 00:42:50.913685 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-probe-ip
139 00:42:50.913867 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-target-ip
140 00:42:50.914075 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-target-mac
141 00:42:50.914290 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-target-storage
142 00:42:50.914514 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-case
143 00:42:50.914740 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-event
144 00:42:50.914938 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-feedback
145 00:42:50.915146 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-raise
146 00:42:50.915324 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-reference
147 00:42:50.915583 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-runner
148 00:42:50.915830 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-set
149 00:42:50.916107 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-test-shell
150 00:42:50.916295 Updating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-install-packages (oe)
151 00:42:50.916582 Updating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/bin/lava-installed-packages (oe)
152 00:42:50.916779 Creating /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/environment
153 00:42:50.916940 LAVA metadata
154 00:42:50.917060 - LAVA_JOB_ID=14173484
155 00:42:50.917223 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:42:50.917458 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:42:50.917559 skipped lava-vland-overlay
158 00:42:50.917757 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:42:50.917885 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:42:50.917990 skipped lava-multinode-overlay
161 00:42:50.918106 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:42:50.918247 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:42:50.918364 Loading test definitions
164 00:42:50.918517 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:42:50.918642 Using /lava-14173484 at stage 0
166 00:42:50.919146 uuid=14173484_1.5.2.3.1 testdef=None
167 00:42:50.919277 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:42:50.919413 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:42:50.920235 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:42:50.920594 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:42:50.921600 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:42:50.921966 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:42:50.922925 runner path: /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/0/tests/0_dmesg test_uuid 14173484_1.5.2.3.1
176 00:42:50.923180 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:42:50.923529 Creating lava-test-runner.conf files
179 00:42:50.923628 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14173484/lava-overlay-z8bc8xtv/lava-14173484/0 for stage 0
180 00:42:50.923762 - 0_dmesg
181 00:42:50.923908 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:42:50.924040 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:42:50.934854 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:42:50.935043 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:42:50.935187 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:42:50.935326 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:42:50.935474 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:42:51.197769 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 00:42:51.198179 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 00:42:51.198299 extracting modules file /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14173484/extract-overlay-ramdisk-7mr0nx9n/ramdisk
191 00:42:51.459751 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:42:51.459979 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:42:51.460132 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173484/compress-overlay-a3zwj3dh/overlay-1.5.2.4.tar.gz to ramdisk
194 00:42:51.460266 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14173484/compress-overlay-a3zwj3dh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14173484/extract-overlay-ramdisk-7mr0nx9n/ramdisk
195 00:42:51.471024 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:42:51.471237 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:42:51.471408 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:42:51.471551 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:42:51.471666 Building ramdisk /var/lib/lava/dispatcher/tmp/14173484/extract-overlay-ramdisk-7mr0nx9n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14173484/extract-overlay-ramdisk-7mr0nx9n/ramdisk
200 00:42:51.864104 >> 145130 blocks
201 00:42:54.392945 rename /var/lib/lava/dispatcher/tmp/14173484/extract-overlay-ramdisk-7mr0nx9n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/ramdisk/ramdisk.cpio.gz
202 00:42:54.393482 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 00:42:54.393668 start: 1.5.8 prepare-kernel (timeout 00:09:55) [common]
204 00:42:54.393809 start: 1.5.8.1 prepare-fit (timeout 00:09:55) [common]
205 00:42:54.393969 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/kernel/Image']
206 00:43:09.583717 Returned 0 in 15 seconds
207 00:43:09.684540 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/kernel/image.itb
208 00:43:10.080208 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:43:10.080662 output: Created: Wed Jun 5 01:43:09 2024
210 00:43:10.080809 output: Image 0 (kernel-1)
211 00:43:10.080937 output: Description:
212 00:43:10.081073 output: Created: Wed Jun 5 01:43:09 2024
213 00:43:10.081214 output: Type: Kernel Image
214 00:43:10.081310 output: Compression: lzma compressed
215 00:43:10.081406 output: Data Size: 13059919 Bytes = 12753.83 KiB = 12.45 MiB
216 00:43:10.081504 output: Architecture: AArch64
217 00:43:10.081599 output: OS: Linux
218 00:43:10.081694 output: Load Address: 0x00000000
219 00:43:10.081785 output: Entry Point: 0x00000000
220 00:43:10.081877 output: Hash algo: crc32
221 00:43:10.081971 output: Hash value: 4c96ec19
222 00:43:10.082065 output: Image 1 (fdt-1)
223 00:43:10.082158 output: Description: mt8192-asurada-spherion-r0
224 00:43:10.082246 output: Created: Wed Jun 5 01:43:09 2024
225 00:43:10.082338 output: Type: Flat Device Tree
226 00:43:10.082426 output: Compression: uncompressed
227 00:43:10.082513 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 00:43:10.082600 output: Architecture: AArch64
229 00:43:10.082686 output: Hash algo: crc32
230 00:43:10.082773 output: Hash value: 0f8e4d2e
231 00:43:10.082859 output: Image 2 (ramdisk-1)
232 00:43:10.082945 output: Description: unavailable
233 00:43:10.083031 output: Created: Wed Jun 5 01:43:09 2024
234 00:43:10.083118 output: Type: RAMDisk Image
235 00:43:10.083204 output: Compression: Unknown Compression
236 00:43:10.083291 output: Data Size: 21365579 Bytes = 20864.82 KiB = 20.38 MiB
237 00:43:10.083377 output: Architecture: AArch64
238 00:43:10.083472 output: OS: Linux
239 00:43:10.083560 output: Load Address: unavailable
240 00:43:10.083647 output: Entry Point: unavailable
241 00:43:10.083733 output: Hash algo: crc32
242 00:43:10.083819 output: Hash value: 50c44ba6
243 00:43:10.083905 output: Default Configuration: 'conf-1'
244 00:43:10.083991 output: Configuration 0 (conf-1)
245 00:43:10.084078 output: Description: mt8192-asurada-spherion-r0
246 00:43:10.084165 output: Kernel: kernel-1
247 00:43:10.084252 output: Init Ramdisk: ramdisk-1
248 00:43:10.084345 output: FDT: fdt-1
249 00:43:10.084433 output: Loadables: kernel-1
250 00:43:10.084518 output:
251 00:43:10.084796 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 00:43:10.084994 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 00:43:10.085170 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 00:43:10.085301 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 00:43:10.085453 No LXC device requested
256 00:43:10.085572 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:43:10.085730 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 00:43:10.085848 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:43:10.085963 Checking files for TFTP limit of 4294967296 bytes.
260 00:43:10.086722 end: 1 tftp-deploy (duration 00:00:20) [common]
261 00:43:10.086892 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:43:10.087018 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:43:10.087207 substitutions:
264 00:43:10.087311 - {DTB}: 14173484/tftp-deploy-4bm95gxy/dtb/mt8192-asurada-spherion-r0.dtb
265 00:43:10.087419 - {INITRD}: 14173484/tftp-deploy-4bm95gxy/ramdisk/ramdisk.cpio.gz
266 00:43:10.087509 - {KERNEL}: 14173484/tftp-deploy-4bm95gxy/kernel/Image
267 00:43:10.087611 - {LAVA_MAC}: None
268 00:43:10.087713 - {PRESEED_CONFIG}: None
269 00:43:10.087800 - {PRESEED_LOCAL}: None
270 00:43:10.087915 - {RAMDISK}: 14173484/tftp-deploy-4bm95gxy/ramdisk/ramdisk.cpio.gz
271 00:43:10.088003 - {ROOT_PART}: None
272 00:43:10.088090 - {ROOT}: None
273 00:43:10.088193 - {SERVER_IP}: 192.168.201.1
274 00:43:10.088282 - {TEE}: None
275 00:43:10.088377 Parsed boot commands:
276 00:43:10.088468 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:43:10.088765 Parsed boot commands: tftpboot 192.168.201.1 14173484/tftp-deploy-4bm95gxy/kernel/image.itb 14173484/tftp-deploy-4bm95gxy/kernel/cmdline
278 00:43:10.088895 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:43:10.089051 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:43:10.089183 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:43:10.089337 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:43:10.089444 Not connected, no need to disconnect.
283 00:43:10.089571 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:43:10.089705 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:43:10.089808 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 00:43:10.094494 Setting prompt string to ['lava-test: # ']
287 00:43:10.095032 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:43:10.095197 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:43:10.095351 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:43:10.095484 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:43:10.095776 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 00:43:15.239649 >> Command sent successfully.
293 00:43:15.242786 Returned 0 in 5 seconds
294 00:43:15.343237 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 00:43:15.343682 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 00:43:15.343825 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 00:43:15.343953 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:43:15.344059 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:43:15.344166 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:43:15.344771 [Enter `^Ec?' for help]
302 00:43:15.514631
303 00:43:15.514790
304 00:43:15.514868 F0: 102B 0000
305 00:43:15.514934
306 00:43:15.514995 F3: 1001 0000 [0200]
307 00:43:15.515055
308 00:43:15.518004 F3: 1001 0000
309 00:43:15.518123
310 00:43:15.518237 F7: 102D 0000
311 00:43:15.518333
312 00:43:15.518397 F1: 0000 0000
313 00:43:15.518458
314 00:43:15.522064 V0: 0000 0000 [0001]
315 00:43:15.522181
316 00:43:15.522261 00: 0007 8000
317 00:43:15.522359
318 00:43:15.525637 01: 0000 0000
319 00:43:15.525752
320 00:43:15.525821 BP: 0C00 0209 [0000]
321 00:43:15.525884
322 00:43:15.525942 G0: 1182 0000
323 00:43:15.526002
324 00:43:15.529224 EC: 0000 0021 [4000]
325 00:43:15.529363
326 00:43:15.529465 S7: 0000 0000 [0000]
327 00:43:15.529559
328 00:43:15.533011 CC: 0000 0000 [0001]
329 00:43:15.533138
330 00:43:15.533238 T0: 0000 0040 [010F]
331 00:43:15.533332
332 00:43:15.536018 Jump to BL
333 00:43:15.536140
334 00:43:15.560648
335 00:43:15.560836
336 00:43:15.567946 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 00:43:15.571796 ARM64: Exception handlers installed.
338 00:43:15.574970 ARM64: Testing exception
339 00:43:15.579001 ARM64: Done test exception
340 00:43:15.586079 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 00:43:15.596551 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 00:43:15.603124 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 00:43:15.613520 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 00:43:15.620210 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 00:43:15.626439 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 00:43:15.637755 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 00:43:15.644373 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 00:43:15.663234 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 00:43:15.667178 WDT: Last reset was cold boot
350 00:43:15.670243 SPI1(PAD0) initialized at 2873684 Hz
351 00:43:15.673626 SPI5(PAD0) initialized at 992727 Hz
352 00:43:15.676941 VBOOT: Loading verstage.
353 00:43:15.683267 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 00:43:15.686641 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 00:43:15.690023 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 00:43:15.693283 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 00:43:15.701186 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 00:43:15.708102 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 00:43:15.719206 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 00:43:15.719381
361 00:43:15.719480
362 00:43:15.729931 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 00:43:15.732816 ARM64: Exception handlers installed.
364 00:43:15.732994 ARM64: Testing exception
365 00:43:15.735771 ARM64: Done test exception
366 00:43:15.739353 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 00:43:15.746094 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 00:43:15.759697 Probing TPM: . done!
369 00:43:15.759921 TPM ready after 0 ms
370 00:43:15.766077 Connected to device vid:did:rid of 1ae0:0028:00
371 00:43:15.773160 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 00:43:15.846645 Initialized TPM device CR50 revision 0
373 00:43:15.855797 tlcl_send_startup: Startup return code is 0
374 00:43:15.855978 TPM: setup succeeded
375 00:43:15.867787 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 00:43:15.877622 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 00:43:15.888520 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 00:43:15.898772 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 00:43:15.901949 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 00:43:15.905944 in-header: 03 07 00 00 08 00 00 00
381 00:43:15.909781 in-data: aa e4 47 04 13 02 00 00
382 00:43:15.913736 Chrome EC: UHEPI supported
383 00:43:15.921016 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 00:43:15.924432 in-header: 03 95 00 00 08 00 00 00
385 00:43:15.927798 in-data: 18 20 20 08 00 00 00 00
386 00:43:15.927945 Phase 1
387 00:43:15.931847 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 00:43:15.935424 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 00:43:15.942634 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 00:43:15.946542 Recovery requested (1009000e)
391 00:43:15.954426 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 00:43:15.960238 tlcl_extend: response is 0
393 00:43:15.969531 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 00:43:15.975225 tlcl_extend: response is 0
395 00:43:15.982248 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 00:43:16.001861 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 00:43:16.008209 BS: bootblock times (exec / console): total (unknown) / 149 ms
398 00:43:16.008382
399 00:43:16.008456
400 00:43:16.018096 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 00:43:16.021587 ARM64: Exception handlers installed.
402 00:43:16.025289 ARM64: Testing exception
403 00:43:16.025411 ARM64: Done test exception
404 00:43:16.047487 pmic_efuse_setting: Set efuses in 11 msecs
405 00:43:16.050767 pmwrap_interface_init: Select PMIF_VLD_RDY
406 00:43:16.058141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 00:43:16.062216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 00:43:16.066366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 00:43:16.069608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 00:43:16.077492 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 00:43:16.081268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 00:43:16.085412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 00:43:16.088631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 00:43:16.096484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 00:43:16.099983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 00:43:16.103611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 00:43:16.107496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 00:43:16.114809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 00:43:16.118572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 00:43:16.125460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 00:43:16.129196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 00:43:16.136892 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 00:43:16.144848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 00:43:16.148584 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 00:43:16.152466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 00:43:16.159957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 00:43:16.163629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 00:43:16.170934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 00:43:16.174599 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 00:43:16.181740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 00:43:16.185637 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 00:43:16.192714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 00:43:16.196499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 00:43:16.200284 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 00:43:16.207781 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 00:43:16.211306 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 00:43:16.214971 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 00:43:16.222145 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 00:43:16.225999 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 00:43:16.229455 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 00:43:16.236961 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 00:43:16.240683 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 00:43:16.248284 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 00:43:16.251678 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 00:43:16.255808 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 00:43:16.259116 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 00:43:16.262734 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 00:43:16.270705 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 00:43:16.273928 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 00:43:16.277339 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 00:43:16.281359 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 00:43:16.285557 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 00:43:16.288747 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 00:43:16.296118 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 00:43:16.299975 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 00:43:16.303786 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 00:43:16.311808 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 00:43:16.318770 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 00:43:16.322267 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 00:43:16.332840 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 00:43:16.340806 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 00:43:16.344680 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 00:43:16.348533 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 00:43:16.351814 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:43:16.361120 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x36
466 00:43:16.364415 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 00:43:16.372739 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 00:43:16.375917 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 00:43:16.385179 [RTC]rtc_get_frequency_meter,154: input=15, output=759
470 00:43:16.394897 [RTC]rtc_get_frequency_meter,154: input=23, output=942
471 00:43:16.403927 [RTC]rtc_get_frequency_meter,154: input=19, output=849
472 00:43:16.414254 [RTC]rtc_get_frequency_meter,154: input=17, output=805
473 00:43:16.422514 [RTC]rtc_get_frequency_meter,154: input=16, output=783
474 00:43:16.432730 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 00:43:16.442489 [RTC]rtc_get_frequency_meter,154: input=17, output=805
476 00:43:16.446555 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 00:43:16.449919 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 00:43:16.454170 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 00:43:16.461333 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 00:43:16.465977 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 00:43:16.469495 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 00:43:16.469644 ADC[4]: Raw value=906203 ID=7
483 00:43:16.473344 ADC[3]: Raw value=213441 ID=1
484 00:43:16.473495 RAM Code: 0x71
485 00:43:16.481311 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 00:43:16.485293 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 00:43:16.492394 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 00:43:16.500394 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 00:43:16.503693 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 00:43:16.507597 in-header: 03 07 00 00 08 00 00 00
491 00:43:16.510839 in-data: aa e4 47 04 13 02 00 00
492 00:43:16.510999 Chrome EC: UHEPI supported
493 00:43:16.518071 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 00:43:16.522166 in-header: 03 95 00 00 08 00 00 00
495 00:43:16.525857 in-data: 18 20 20 08 00 00 00 00
496 00:43:16.529735 MRC: failed to locate region type 0.
497 00:43:16.536978 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 00:43:16.537158 DRAM-K: Running full calibration
499 00:43:16.544528 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 00:43:16.548319 header.status = 0x0
501 00:43:16.548467 header.version = 0x6 (expected: 0x6)
502 00:43:16.552196 header.size = 0xd00 (expected: 0xd00)
503 00:43:16.556049 header.flags = 0x0
504 00:43:16.559170 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 00:43:16.578773 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 00:43:16.586353 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 00:43:16.590074 dram_init: ddr_geometry: 2
508 00:43:16.590221 [EMI] MDL number = 2
509 00:43:16.593739 [EMI] Get MDL freq = 0
510 00:43:16.593887 dram_init: ddr_type: 0
511 00:43:16.597923 is_discrete_lpddr4: 1
512 00:43:16.601544 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 00:43:16.601727
514 00:43:16.601835
515 00:43:16.601929 [Bian_co] ETT version 0.0.0.1
516 00:43:16.609160 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 00:43:16.609356
518 00:43:16.613036 dramc_set_vcore_voltage set vcore to 650000
519 00:43:16.613222 Read voltage for 800, 4
520 00:43:16.613324 Vio18 = 0
521 00:43:16.616962 Vcore = 650000
522 00:43:16.617141 Vdram = 0
523 00:43:16.617246 Vddq = 0
524 00:43:16.617338 Vmddr = 0
525 00:43:16.620827 dram_init: config_dvfs: 1
526 00:43:16.624769 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 00:43:16.632349 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 00:43:16.635569 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
529 00:43:16.639237 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
530 00:43:16.642397 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
531 00:43:16.645689 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
532 00:43:16.649056 MEM_TYPE=3, freq_sel=18
533 00:43:16.652313 sv_algorithm_assistance_LP4_1600
534 00:43:16.656329 ============ PULL DRAM RESETB DOWN ============
535 00:43:16.660303 ========== PULL DRAM RESETB DOWN end =========
536 00:43:16.663910 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 00:43:16.666940 ===================================
538 00:43:16.670787 LPDDR4 DRAM CONFIGURATION
539 00:43:16.674437 ===================================
540 00:43:16.674606 EX_ROW_EN[0] = 0x0
541 00:43:16.677910 EX_ROW_EN[1] = 0x0
542 00:43:16.678044 LP4Y_EN = 0x0
543 00:43:16.680941 WORK_FSP = 0x0
544 00:43:16.681074 WL = 0x2
545 00:43:16.684564 RL = 0x2
546 00:43:16.687915 BL = 0x2
547 00:43:16.688063 RPST = 0x0
548 00:43:16.691380 RD_PRE = 0x0
549 00:43:16.691529 WR_PRE = 0x1
550 00:43:16.695355 WR_PST = 0x0
551 00:43:16.695516 DBI_WR = 0x0
552 00:43:16.695619 DBI_RD = 0x0
553 00:43:16.699346 OTF = 0x1
554 00:43:16.702019 ===================================
555 00:43:16.705428 ===================================
556 00:43:16.705591 ANA top config
557 00:43:16.708683 ===================================
558 00:43:16.712437 DLL_ASYNC_EN = 0
559 00:43:16.716010 ALL_SLAVE_EN = 1
560 00:43:16.716184 NEW_RANK_MODE = 1
561 00:43:16.720020 DLL_IDLE_MODE = 1
562 00:43:16.723296 LP45_APHY_COMB_EN = 1
563 00:43:16.726259 TX_ODT_DIS = 1
564 00:43:16.726387 NEW_8X_MODE = 1
565 00:43:16.729876 ===================================
566 00:43:16.732934 ===================================
567 00:43:16.736371 data_rate = 1600
568 00:43:16.739776 CKR = 1
569 00:43:16.742917 DQ_P2S_RATIO = 8
570 00:43:16.746597 ===================================
571 00:43:16.749900 CA_P2S_RATIO = 8
572 00:43:16.750038 DQ_CA_OPEN = 0
573 00:43:16.753191 DQ_SEMI_OPEN = 0
574 00:43:16.756508 CA_SEMI_OPEN = 0
575 00:43:16.759782 CA_FULL_RATE = 0
576 00:43:16.762908 DQ_CKDIV4_EN = 1
577 00:43:16.766483 CA_CKDIV4_EN = 1
578 00:43:16.766648 CA_PREDIV_EN = 0
579 00:43:16.769661 PH8_DLY = 0
580 00:43:16.772907 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 00:43:16.776519 DQ_AAMCK_DIV = 4
582 00:43:16.779603 CA_AAMCK_DIV = 4
583 00:43:16.783503 CA_ADMCK_DIV = 4
584 00:43:16.783634 DQ_TRACK_CA_EN = 0
585 00:43:16.787312 CA_PICK = 800
586 00:43:16.791063 CA_MCKIO = 800
587 00:43:16.794749 MCKIO_SEMI = 0
588 00:43:16.794896 PLL_FREQ = 3068
589 00:43:16.798236 DQ_UI_PI_RATIO = 32
590 00:43:16.801954 CA_UI_PI_RATIO = 0
591 00:43:16.806252 ===================================
592 00:43:16.809500 ===================================
593 00:43:16.809626 memory_type:LPDDR4
594 00:43:16.813388 GP_NUM : 10
595 00:43:16.813532 SRAM_EN : 1
596 00:43:16.816700 MD32_EN : 0
597 00:43:16.820019 ===================================
598 00:43:16.823398 [ANA_INIT] >>>>>>>>>>>>>>
599 00:43:16.826752 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 00:43:16.830662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 00:43:16.833746 ===================================
602 00:43:16.833897 data_rate = 1600,PCW = 0X7600
603 00:43:16.837006 ===================================
604 00:43:16.840277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 00:43:16.847089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 00:43:16.853681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:43:16.857049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 00:43:16.860163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 00:43:16.863713 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:43:16.867355 [ANA_INIT] flow start
611 00:43:16.867501 [ANA_INIT] PLL >>>>>>>>
612 00:43:16.870652 [ANA_INIT] PLL <<<<<<<<
613 00:43:16.873977 [ANA_INIT] MIDPI >>>>>>>>
614 00:43:16.874144 [ANA_INIT] MIDPI <<<<<<<<
615 00:43:16.877553 [ANA_INIT] DLL >>>>>>>>
616 00:43:16.880687 [ANA_INIT] flow end
617 00:43:16.884032 ============ LP4 DIFF to SE enter ============
618 00:43:16.887655 ============ LP4 DIFF to SE exit ============
619 00:43:16.890913 [ANA_INIT] <<<<<<<<<<<<<
620 00:43:16.894154 [Flow] Enable top DCM control >>>>>
621 00:43:16.897806 [Flow] Enable top DCM control <<<<<
622 00:43:16.900921 Enable DLL master slave shuffle
623 00:43:16.904003 ==============================================================
624 00:43:16.907703 Gating Mode config
625 00:43:16.914195 ==============================================================
626 00:43:16.914370 Config description:
627 00:43:16.923921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 00:43:16.930529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 00:43:16.933843 SELPH_MODE 0: By rank 1: By Phase
630 00:43:16.940429 ==============================================================
631 00:43:16.943687 GAT_TRACK_EN = 1
632 00:43:16.946999 RX_GATING_MODE = 2
633 00:43:16.951011 RX_GATING_TRACK_MODE = 2
634 00:43:16.954004 SELPH_MODE = 1
635 00:43:16.957350 PICG_EARLY_EN = 1
636 00:43:16.960599 VALID_LAT_VALUE = 1
637 00:43:16.963950 ==============================================================
638 00:43:16.967456 Enter into Gating configuration >>>>
639 00:43:16.970923 Exit from Gating configuration <<<<
640 00:43:16.973960 Enter into DVFS_PRE_config >>>>>
641 00:43:16.983869 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 00:43:16.987129 Exit from DVFS_PRE_config <<<<<
643 00:43:16.990602 Enter into PICG configuration >>>>
644 00:43:16.993933 Exit from PICG configuration <<<<
645 00:43:16.997188 [RX_INPUT] configuration >>>>>
646 00:43:17.001259 [RX_INPUT] configuration <<<<<
647 00:43:17.003761 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 00:43:17.010964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 00:43:17.017548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 00:43:17.024081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 00:43:17.031084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 00:43:17.037487 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 00:43:17.040784 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 00:43:17.044122 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 00:43:17.047227 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 00:43:17.050713 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 00:43:17.057478 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 00:43:17.060751 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 00:43:17.064038 ===================================
660 00:43:17.067489 LPDDR4 DRAM CONFIGURATION
661 00:43:17.070880 ===================================
662 00:43:17.071008 EX_ROW_EN[0] = 0x0
663 00:43:17.074314 EX_ROW_EN[1] = 0x0
664 00:43:17.074467 LP4Y_EN = 0x0
665 00:43:17.077370 WORK_FSP = 0x0
666 00:43:17.077513 WL = 0x2
667 00:43:17.080939 RL = 0x2
668 00:43:17.081113 BL = 0x2
669 00:43:17.084748 RPST = 0x0
670 00:43:17.084899 RD_PRE = 0x0
671 00:43:17.087736 WR_PRE = 0x1
672 00:43:17.087876 WR_PST = 0x0
673 00:43:17.090860 DBI_WR = 0x0
674 00:43:17.090993 DBI_RD = 0x0
675 00:43:17.093933 OTF = 0x1
676 00:43:17.097446 ===================================
677 00:43:17.101041 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 00:43:17.104242 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 00:43:17.111135 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 00:43:17.114357 ===================================
681 00:43:17.114561 LPDDR4 DRAM CONFIGURATION
682 00:43:17.117858 ===================================
683 00:43:17.120965 EX_ROW_EN[0] = 0x10
684 00:43:17.124047 EX_ROW_EN[1] = 0x0
685 00:43:17.124282 LP4Y_EN = 0x0
686 00:43:17.127909 WORK_FSP = 0x0
687 00:43:17.128071 WL = 0x2
688 00:43:17.131055 RL = 0x2
689 00:43:17.131220 BL = 0x2
690 00:43:17.134685 RPST = 0x0
691 00:43:17.134858 RD_PRE = 0x0
692 00:43:17.137690 WR_PRE = 0x1
693 00:43:17.137828 WR_PST = 0x0
694 00:43:17.141442 DBI_WR = 0x0
695 00:43:17.141610 DBI_RD = 0x0
696 00:43:17.144487 OTF = 0x1
697 00:43:17.148113 ===================================
698 00:43:17.154733 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 00:43:17.158089 nWR fixed to 40
700 00:43:17.158208 [ModeRegInit_LP4] CH0 RK0
701 00:43:17.161261 [ModeRegInit_LP4] CH0 RK1
702 00:43:17.164560 [ModeRegInit_LP4] CH1 RK0
703 00:43:17.164711 [ModeRegInit_LP4] CH1 RK1
704 00:43:17.168318 match AC timing 13
705 00:43:17.171309 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 00:43:17.174618 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 00:43:17.181074 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 00:43:17.184952 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 00:43:17.191452 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 00:43:17.191638 [EMI DOE] emi_dcm 0
711 00:43:17.194551 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 00:43:17.197953 ==
713 00:43:17.201633 Dram Type= 6, Freq= 0, CH_0, rank 0
714 00:43:17.204788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 00:43:17.204942 ==
716 00:43:17.207733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 00:43:17.215041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 00:43:17.224136 [CA 0] Center 36 (6~67) winsize 62
719 00:43:17.227417 [CA 1] Center 36 (6~67) winsize 62
720 00:43:17.231146 [CA 2] Center 34 (4~65) winsize 62
721 00:43:17.234495 [CA 3] Center 33 (3~64) winsize 62
722 00:43:17.237685 [CA 4] Center 33 (3~64) winsize 62
723 00:43:17.240996 [CA 5] Center 32 (3~62) winsize 60
724 00:43:17.241156
725 00:43:17.244822 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 00:43:17.244978
727 00:43:17.247448 [CATrainingPosCal] consider 1 rank data
728 00:43:17.251227 u2DelayCellTimex100 = 270/100 ps
729 00:43:17.254440 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
730 00:43:17.257975 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
731 00:43:17.264524 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
732 00:43:17.267664 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
733 00:43:17.270816 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
734 00:43:17.274894 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
735 00:43:17.275024
736 00:43:17.278036 CA PerBit enable=1, Macro0, CA PI delay=32
737 00:43:17.278183
738 00:43:17.281582 [CBTSetCACLKResult] CA Dly = 32
739 00:43:17.281738 CS Dly: 5 (0~36)
740 00:43:17.281849 ==
741 00:43:17.284704 Dram Type= 6, Freq= 0, CH_0, rank 1
742 00:43:17.291485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 00:43:17.291662 ==
744 00:43:17.294446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 00:43:17.300928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 00:43:17.311045 [CA 0] Center 36 (6~67) winsize 62
747 00:43:17.313943 [CA 1] Center 36 (6~67) winsize 62
748 00:43:17.317149 [CA 2] Center 34 (3~65) winsize 63
749 00:43:17.320470 [CA 3] Center 33 (3~64) winsize 62
750 00:43:17.323913 [CA 4] Center 33 (3~63) winsize 61
751 00:43:17.327173 [CA 5] Center 32 (2~63) winsize 62
752 00:43:17.327347
753 00:43:17.330614 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 00:43:17.330772
755 00:43:17.334160 [CATrainingPosCal] consider 2 rank data
756 00:43:17.337375 u2DelayCellTimex100 = 270/100 ps
757 00:43:17.340489 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
758 00:43:17.343920 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
759 00:43:17.350982 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
760 00:43:17.353988 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
761 00:43:17.357093 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
762 00:43:17.360923 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
763 00:43:17.361091
764 00:43:17.364626 CA PerBit enable=1, Macro0, CA PI delay=32
765 00:43:17.364781
766 00:43:17.368997 [CBTSetCACLKResult] CA Dly = 32
767 00:43:17.369181 CS Dly: 5 (0~36)
768 00:43:17.369288
769 00:43:17.372284 ----->DramcWriteLeveling(PI) begin...
770 00:43:17.372435 ==
771 00:43:17.375933 Dram Type= 6, Freq= 0, CH_0, rank 0
772 00:43:17.379093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 00:43:17.379242 ==
774 00:43:17.382619 Write leveling (Byte 0): 34 => 34
775 00:43:17.386091 Write leveling (Byte 1): 31 => 31
776 00:43:17.389474 DramcWriteLeveling(PI) end<-----
777 00:43:17.389592
778 00:43:17.389684 ==
779 00:43:17.393285 Dram Type= 6, Freq= 0, CH_0, rank 0
780 00:43:17.396699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:43:17.396823 ==
782 00:43:17.399884 [Gating] SW mode calibration
783 00:43:17.406646 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 00:43:17.413335 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 00:43:17.416609 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 00:43:17.420066 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 00:43:17.426771 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:43:17.430199 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:43:17.433377 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:43:17.440130 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:43:17.443463 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:43:17.446890 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:43:17.449994 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:43:17.456868 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:43:17.460265 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:43:17.463562 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:43:17.470338 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:43:17.473555 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:43:17.476785 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:43:17.483449 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:43:17.486931 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:43:17.490022 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 00:43:17.496705 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
804 00:43:17.500091 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:43:17.503970 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:43:17.510508 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:43:17.513902 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:43:17.516688 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:43:17.520577 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:43:17.527255 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:43:17.530564 0 9 8 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
812 00:43:17.533905 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
813 00:43:17.540389 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 00:43:17.543632 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:43:17.547040 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:43:17.553791 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:43:17.557052 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:43:17.560360 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
819 00:43:17.566722 0 10 8 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
820 00:43:17.570309 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 00:43:17.574082 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:43:17.580753 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:43:17.584118 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:43:17.587196 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:43:17.593745 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:43:17.597049 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
827 00:43:17.600254 0 11 8 | B1->B0 | 2c2c 3e3e | 0 0 | (0 0) (0 0)
828 00:43:17.603794 0 11 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
829 00:43:17.610407 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 00:43:17.613895 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:43:17.617406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:43:17.623937 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:43:17.627110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:43:17.630869 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:43:17.637286 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
836 00:43:17.640656 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:43:17.643933 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:43:17.650450 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:43:17.653947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:43:17.657280 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:43:17.664060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:43:17.667312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:43:17.670549 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:43:17.676932 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:43:17.680708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:43:17.684036 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:43:17.687531 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:43:17.693663 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:43:17.697765 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:43:17.700509 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:43:17.707162 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 00:43:17.710742 Total UI for P1: 0, mck2ui 16
853 00:43:17.714466 best dqsien dly found for B0: ( 0, 14, 6)
854 00:43:17.718397 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 00:43:17.721443 Total UI for P1: 0, mck2ui 16
856 00:43:17.724586 best dqsien dly found for B1: ( 0, 14, 8)
857 00:43:17.728092 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 00:43:17.731034 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 00:43:17.731262
860 00:43:17.734682 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 00:43:17.738290 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 00:43:17.741548 [Gating] SW calibration Done
863 00:43:17.741770 ==
864 00:43:17.744590 Dram Type= 6, Freq= 0, CH_0, rank 0
865 00:43:17.748514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 00:43:17.748744 ==
867 00:43:17.751612 RX Vref Scan: 0
868 00:43:17.751792
869 00:43:17.751931 RX Vref 0 -> 0, step: 1
870 00:43:17.752060
871 00:43:17.755006 RX Delay -130 -> 252, step: 16
872 00:43:17.761159 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
873 00:43:17.764670 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 00:43:17.767890 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 00:43:17.771247 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 00:43:17.774808 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 00:43:17.777899 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 00:43:17.785019 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
879 00:43:17.788271 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
880 00:43:17.791542 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
881 00:43:17.794809 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 00:43:17.798444 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 00:43:17.804799 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
884 00:43:17.808171 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
885 00:43:17.811849 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
886 00:43:17.815029 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
887 00:43:17.821712 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
888 00:43:17.821860 ==
889 00:43:17.824947 Dram Type= 6, Freq= 0, CH_0, rank 0
890 00:43:17.828506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 00:43:17.828667 ==
892 00:43:17.828783 DQS Delay:
893 00:43:17.831525 DQS0 = 0, DQS1 = 0
894 00:43:17.831689 DQM Delay:
895 00:43:17.834830 DQM0 = 90, DQM1 = 84
896 00:43:17.834989 DQ Delay:
897 00:43:17.838068 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
898 00:43:17.841239 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
899 00:43:17.844771 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
900 00:43:17.848468 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
901 00:43:17.848606
902 00:43:17.848679
903 00:43:17.848741 ==
904 00:43:17.851596 Dram Type= 6, Freq= 0, CH_0, rank 0
905 00:43:17.855044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 00:43:17.855233 ==
907 00:43:17.855342
908 00:43:17.855434
909 00:43:17.858479 TX Vref Scan disable
910 00:43:17.862052 == TX Byte 0 ==
911 00:43:17.865444 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
912 00:43:17.868840 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
913 00:43:17.871542 == TX Byte 1 ==
914 00:43:17.874976 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 00:43:17.878488 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 00:43:17.878604 ==
917 00:43:17.881896 Dram Type= 6, Freq= 0, CH_0, rank 0
918 00:43:17.885330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 00:43:17.885449 ==
920 00:43:17.899859 TX Vref=22, minBit 8, minWin=27, winSum=447
921 00:43:17.902995 TX Vref=24, minBit 11, minWin=27, winSum=452
922 00:43:17.906343 TX Vref=26, minBit 8, minWin=27, winSum=452
923 00:43:17.909539 TX Vref=28, minBit 4, minWin=28, winSum=456
924 00:43:17.913252 TX Vref=30, minBit 5, minWin=28, winSum=455
925 00:43:17.916190 TX Vref=32, minBit 2, minWin=28, winSum=452
926 00:43:17.923451 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 28
927 00:43:17.923584
928 00:43:17.926788 Final TX Range 1 Vref 28
929 00:43:17.926942
930 00:43:17.927049 ==
931 00:43:17.929783 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:43:17.933817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 00:43:17.934004 ==
934 00:43:17.934113
935 00:43:17.934207
936 00:43:17.937184 TX Vref Scan disable
937 00:43:17.939753 == TX Byte 0 ==
938 00:43:17.943210 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
939 00:43:17.946568 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
940 00:43:17.949869 == TX Byte 1 ==
941 00:43:17.953208 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 00:43:17.957006 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 00:43:17.957163
944 00:43:17.959987 [DATLAT]
945 00:43:17.960145 Freq=800, CH0 RK0
946 00:43:17.960251
947 00:43:17.963399 DATLAT Default: 0xa
948 00:43:17.963532 0, 0xFFFF, sum = 0
949 00:43:17.966960 1, 0xFFFF, sum = 0
950 00:43:17.967118 2, 0xFFFF, sum = 0
951 00:43:17.969813 3, 0xFFFF, sum = 0
952 00:43:17.969948 4, 0xFFFF, sum = 0
953 00:43:17.973496 5, 0xFFFF, sum = 0
954 00:43:17.973618 6, 0xFFFF, sum = 0
955 00:43:17.976505 7, 0xFFFF, sum = 0
956 00:43:17.976612 8, 0xFFFF, sum = 0
957 00:43:17.980271 9, 0x0, sum = 1
958 00:43:17.980422 10, 0x0, sum = 2
959 00:43:17.983520 11, 0x0, sum = 3
960 00:43:17.983624 12, 0x0, sum = 4
961 00:43:17.986859 best_step = 10
962 00:43:17.986969
963 00:43:17.987035 ==
964 00:43:17.990188 Dram Type= 6, Freq= 0, CH_0, rank 0
965 00:43:17.993480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 00:43:17.993603 ==
967 00:43:17.996778 RX Vref Scan: 1
968 00:43:17.996891
969 00:43:17.996958 Set Vref Range= 32 -> 127
970 00:43:17.997020
971 00:43:17.999988 RX Vref 32 -> 127, step: 1
972 00:43:18.000121
973 00:43:18.003424 RX Delay -95 -> 252, step: 8
974 00:43:18.003529
975 00:43:18.006755 Set Vref, RX VrefLevel [Byte0]: 32
976 00:43:18.009974 [Byte1]: 32
977 00:43:18.010099
978 00:43:18.013343 Set Vref, RX VrefLevel [Byte0]: 33
979 00:43:18.016808 [Byte1]: 33
980 00:43:18.020350
981 00:43:18.020485 Set Vref, RX VrefLevel [Byte0]: 34
982 00:43:18.023671 [Byte1]: 34
983 00:43:18.027740
984 00:43:18.027879 Set Vref, RX VrefLevel [Byte0]: 35
985 00:43:18.031339 [Byte1]: 35
986 00:43:18.035789
987 00:43:18.035947 Set Vref, RX VrefLevel [Byte0]: 36
988 00:43:18.039165 [Byte1]: 36
989 00:43:18.042933
990 00:43:18.043048 Set Vref, RX VrefLevel [Byte0]: 37
991 00:43:18.046630 [Byte1]: 37
992 00:43:18.050408
993 00:43:18.050566 Set Vref, RX VrefLevel [Byte0]: 38
994 00:43:18.053811 [Byte1]: 38
995 00:43:18.058219
996 00:43:18.058340 Set Vref, RX VrefLevel [Byte0]: 39
997 00:43:18.061338 [Byte1]: 39
998 00:43:18.066027
999 00:43:18.066165 Set Vref, RX VrefLevel [Byte0]: 40
1000 00:43:18.069222 [Byte1]: 40
1001 00:43:18.073092
1002 00:43:18.073224 Set Vref, RX VrefLevel [Byte0]: 41
1003 00:43:18.076470 [Byte1]: 41
1004 00:43:18.081194
1005 00:43:18.081321 Set Vref, RX VrefLevel [Byte0]: 42
1006 00:43:18.084172 [Byte1]: 42
1007 00:43:18.088277
1008 00:43:18.088408 Set Vref, RX VrefLevel [Byte0]: 43
1009 00:43:18.091511 [Byte1]: 43
1010 00:43:18.096227
1011 00:43:18.096395 Set Vref, RX VrefLevel [Byte0]: 44
1012 00:43:18.099647 [Byte1]: 44
1013 00:43:18.103387
1014 00:43:18.103550 Set Vref, RX VrefLevel [Byte0]: 45
1015 00:43:18.107244 [Byte1]: 45
1016 00:43:18.111409
1017 00:43:18.111532 Set Vref, RX VrefLevel [Byte0]: 46
1018 00:43:18.114861 [Byte1]: 46
1019 00:43:18.118702
1020 00:43:18.118867 Set Vref, RX VrefLevel [Byte0]: 47
1021 00:43:18.122122 [Byte1]: 47
1022 00:43:18.126195
1023 00:43:18.126325 Set Vref, RX VrefLevel [Byte0]: 48
1024 00:43:18.129545 [Byte1]: 48
1025 00:43:18.134332
1026 00:43:18.134463 Set Vref, RX VrefLevel [Byte0]: 49
1027 00:43:18.137149 [Byte1]: 49
1028 00:43:18.141807
1029 00:43:18.141942 Set Vref, RX VrefLevel [Byte0]: 50
1030 00:43:18.144886 [Byte1]: 50
1031 00:43:18.149466
1032 00:43:18.149594 Set Vref, RX VrefLevel [Byte0]: 51
1033 00:43:18.152869 [Byte1]: 51
1034 00:43:18.157001
1035 00:43:18.157136 Set Vref, RX VrefLevel [Byte0]: 52
1036 00:43:18.160102 [Byte1]: 52
1037 00:43:18.164428
1038 00:43:18.164589 Set Vref, RX VrefLevel [Byte0]: 53
1039 00:43:18.168086 [Byte1]: 53
1040 00:43:18.171836
1041 00:43:18.171992 Set Vref, RX VrefLevel [Byte0]: 54
1042 00:43:18.175102 [Byte1]: 54
1043 00:43:18.179519
1044 00:43:18.179671 Set Vref, RX VrefLevel [Byte0]: 55
1045 00:43:18.183044 [Byte1]: 55
1046 00:43:18.187181
1047 00:43:18.187331 Set Vref, RX VrefLevel [Byte0]: 56
1048 00:43:18.190512 [Byte1]: 56
1049 00:43:18.194677
1050 00:43:18.194839 Set Vref, RX VrefLevel [Byte0]: 57
1051 00:43:18.197978 [Byte1]: 57
1052 00:43:18.202562
1053 00:43:18.202690 Set Vref, RX VrefLevel [Byte0]: 58
1054 00:43:18.205668 [Byte1]: 58
1055 00:43:18.209778
1056 00:43:18.209910 Set Vref, RX VrefLevel [Byte0]: 59
1057 00:43:18.213490 [Byte1]: 59
1058 00:43:18.217576
1059 00:43:18.217704 Set Vref, RX VrefLevel [Byte0]: 60
1060 00:43:18.221127 [Byte1]: 60
1061 00:43:18.225223
1062 00:43:18.225351 Set Vref, RX VrefLevel [Byte0]: 61
1063 00:43:18.228219 [Byte1]: 61
1064 00:43:18.232993
1065 00:43:18.233126 Set Vref, RX VrefLevel [Byte0]: 62
1066 00:43:18.236319 [Byte1]: 62
1067 00:43:18.240461
1068 00:43:18.240617 Set Vref, RX VrefLevel [Byte0]: 63
1069 00:43:18.243893 [Byte1]: 63
1070 00:43:18.247904
1071 00:43:18.248032 Set Vref, RX VrefLevel [Byte0]: 64
1072 00:43:18.251393 [Byte1]: 64
1073 00:43:18.255421
1074 00:43:18.255550 Set Vref, RX VrefLevel [Byte0]: 65
1075 00:43:18.258784 [Byte1]: 65
1076 00:43:18.263602
1077 00:43:18.263736 Set Vref, RX VrefLevel [Byte0]: 66
1078 00:43:18.266626 [Byte1]: 66
1079 00:43:18.270989
1080 00:43:18.271156 Set Vref, RX VrefLevel [Byte0]: 67
1081 00:43:18.274334 [Byte1]: 67
1082 00:43:18.278657
1083 00:43:18.278821 Set Vref, RX VrefLevel [Byte0]: 68
1084 00:43:18.282046 [Byte1]: 68
1085 00:43:18.286059
1086 00:43:18.286181 Set Vref, RX VrefLevel [Byte0]: 69
1087 00:43:18.289091 [Byte1]: 69
1088 00:43:18.293950
1089 00:43:18.294076 Set Vref, RX VrefLevel [Byte0]: 70
1090 00:43:18.296678 [Byte1]: 70
1091 00:43:18.301529
1092 00:43:18.301657 Set Vref, RX VrefLevel [Byte0]: 71
1093 00:43:18.304261 [Byte1]: 71
1094 00:43:18.309105
1095 00:43:18.309255 Set Vref, RX VrefLevel [Byte0]: 72
1096 00:43:18.312391 [Byte1]: 72
1097 00:43:18.316287
1098 00:43:18.316433 Set Vref, RX VrefLevel [Byte0]: 73
1099 00:43:18.320099 [Byte1]: 73
1100 00:43:18.324163
1101 00:43:18.324318 Set Vref, RX VrefLevel [Byte0]: 74
1102 00:43:18.327083 [Byte1]: 74
1103 00:43:18.331349
1104 00:43:18.331500 Set Vref, RX VrefLevel [Byte0]: 75
1105 00:43:18.334980 [Byte1]: 75
1106 00:43:18.339190
1107 00:43:18.339317 Set Vref, RX VrefLevel [Byte0]: 76
1108 00:43:18.342560 [Byte1]: 76
1109 00:43:18.346791
1110 00:43:18.346914 Set Vref, RX VrefLevel [Byte0]: 77
1111 00:43:18.350185 [Byte1]: 77
1112 00:43:18.354312
1113 00:43:18.354432 Set Vref, RX VrefLevel [Byte0]: 78
1114 00:43:18.357668 [Byte1]: 78
1115 00:43:18.361845
1116 00:43:18.361956 Final RX Vref Byte 0 = 55 to rank0
1117 00:43:18.365181 Final RX Vref Byte 1 = 56 to rank0
1118 00:43:18.369124 Final RX Vref Byte 0 = 55 to rank1
1119 00:43:18.372328 Final RX Vref Byte 1 = 56 to rank1==
1120 00:43:18.375275 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 00:43:18.378440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 00:43:18.381961 ==
1123 00:43:18.382086 DQS Delay:
1124 00:43:18.382155 DQS0 = 0, DQS1 = 0
1125 00:43:18.385165 DQM Delay:
1126 00:43:18.385268 DQM0 = 91, DQM1 = 86
1127 00:43:18.388710 DQ Delay:
1128 00:43:18.392317 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1129 00:43:18.392448 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1130 00:43:18.395403 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
1131 00:43:18.402278 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1132 00:43:18.402418
1133 00:43:18.402490
1134 00:43:18.408713 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a40, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1135 00:43:18.412195 CH0 RK0: MR19=606, MR18=4A40
1136 00:43:18.418893 CH0_RK0: MR19=0x606, MR18=0x4A40, DQSOSC=391, MR23=63, INC=96, DEC=64
1137 00:43:18.419065
1138 00:43:18.422219 ----->DramcWriteLeveling(PI) begin...
1139 00:43:18.422345 ==
1140 00:43:18.425670 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 00:43:18.428942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 00:43:18.429092 ==
1143 00:43:18.432112 Write leveling (Byte 0): 32 => 32
1144 00:43:18.476374 Write leveling (Byte 1): 28 => 28
1145 00:43:18.476524 DramcWriteLeveling(PI) end<-----
1146 00:43:18.476598
1147 00:43:18.476664 ==
1148 00:43:18.476925 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 00:43:18.477029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 00:43:18.477130 ==
1151 00:43:18.477233 [Gating] SW mode calibration
1152 00:43:18.477334 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 00:43:18.477433 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 00:43:18.477715 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 00:43:18.477995 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 00:43:18.478087 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1157 00:43:18.520566 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:43:18.520719 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:43:18.521267 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:43:18.521535 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:43:18.521615 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:43:18.521864 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:43:18.521930 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:43:18.521990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:43:18.522461 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:43:18.522727 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:43:18.526913 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:43:18.527085 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:43:18.530196 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:43:18.537020 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:43:18.540280 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:43:18.543497 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1173 00:43:18.549891 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:43:18.553320 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:43:18.556747 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:43:18.563495 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:43:18.566536 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:43:18.570385 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:43:18.576628 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:43:18.579928 0 9 8 | B1->B0 | 2f2f 302f | 0 1 | (0 0) (0 0)
1181 00:43:18.583485 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:43:18.590313 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:43:18.593603 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:43:18.596841 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:43:18.600254 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 00:43:18.607094 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 00:43:18.611120 0 10 4 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
1188 00:43:18.614535 0 10 8 | B1->B0 | 2828 2d2d | 0 0 | (1 0) (0 1)
1189 00:43:18.618794 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1190 00:43:18.622084 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:43:18.629041 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:43:18.632235 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:43:18.636557 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:43:18.643010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:43:18.646608 0 11 4 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
1196 00:43:18.649864 0 11 8 | B1->B0 | 4040 3737 | 0 0 | (1 1) (0 0)
1197 00:43:18.653027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:43:18.659455 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:43:18.662884 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:43:18.666377 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:43:18.673221 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:43:18.676605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 00:43:18.679805 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 00:43:18.686921 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 00:43:18.689806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:43:18.693004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:43:18.699361 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:43:18.702719 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:43:18.706262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:43:18.713153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:43:18.716516 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:43:18.720052 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:43:18.726113 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:43:18.729432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:43:18.732762 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:43:18.739722 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:43:18.742850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:43:18.746475 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 00:43:18.749588 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 00:43:18.756530 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1221 00:43:18.759560 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:43:18.762996 Total UI for P1: 0, mck2ui 16
1223 00:43:18.766314 best dqsien dly found for B0: ( 0, 14, 8)
1224 00:43:18.769714 Total UI for P1: 0, mck2ui 16
1225 00:43:18.773067 best dqsien dly found for B1: ( 0, 14, 8)
1226 00:43:18.776424 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1227 00:43:18.779816 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 00:43:18.779963
1229 00:43:18.783498 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 00:43:18.786032 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 00:43:18.789359 [Gating] SW calibration Done
1232 00:43:18.789510 ==
1233 00:43:18.792829 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 00:43:18.796660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 00:43:18.799458 ==
1236 00:43:18.799601 RX Vref Scan: 0
1237 00:43:18.799697
1238 00:43:18.802876 RX Vref 0 -> 0, step: 1
1239 00:43:18.803007
1240 00:43:18.806199 RX Delay -130 -> 252, step: 16
1241 00:43:18.810011 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1242 00:43:18.813007 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1243 00:43:18.816147 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1244 00:43:18.819745 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1245 00:43:18.823259 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1246 00:43:18.830477 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1247 00:43:18.833664 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1248 00:43:18.836434 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1249 00:43:18.840201 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1250 00:43:18.843119 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1251 00:43:18.850363 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1252 00:43:18.853762 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1253 00:43:18.856996 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1254 00:43:18.860398 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1255 00:43:18.863236 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1256 00:43:18.869906 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1257 00:43:18.870078 ==
1258 00:43:18.873600 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 00:43:18.876605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 00:43:18.876756 ==
1261 00:43:18.876855 DQS Delay:
1262 00:43:18.880088 DQS0 = 0, DQS1 = 0
1263 00:43:18.880215 DQM Delay:
1264 00:43:18.883669 DQM0 = 92, DQM1 = 83
1265 00:43:18.883810 DQ Delay:
1266 00:43:18.886942 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1267 00:43:18.890251 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1268 00:43:18.893947 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1269 00:43:18.896348 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1270 00:43:18.896491
1271 00:43:18.896587
1272 00:43:18.896676 ==
1273 00:43:18.899765 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 00:43:18.903668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 00:43:18.903822 ==
1276 00:43:18.907135
1277 00:43:18.907275
1278 00:43:18.907371 TX Vref Scan disable
1279 00:43:18.909808 == TX Byte 0 ==
1280 00:43:18.913283 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1281 00:43:18.916789 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1282 00:43:18.919845 == TX Byte 1 ==
1283 00:43:18.923108 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1284 00:43:18.927062 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1285 00:43:18.927222 ==
1286 00:43:18.930117 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 00:43:18.936726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 00:43:18.936905 ==
1289 00:43:18.949114 TX Vref=22, minBit 8, minWin=27, winSum=448
1290 00:43:18.952435 TX Vref=24, minBit 1, minWin=28, winSum=453
1291 00:43:18.955682 TX Vref=26, minBit 8, minWin=27, winSum=454
1292 00:43:18.958861 TX Vref=28, minBit 4, minWin=28, winSum=457
1293 00:43:18.962506 TX Vref=30, minBit 7, minWin=28, winSum=457
1294 00:43:18.965841 TX Vref=32, minBit 4, minWin=28, winSum=456
1295 00:43:18.972477 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 28
1296 00:43:18.972625
1297 00:43:18.975819 Final TX Range 1 Vref 28
1298 00:43:18.975956
1299 00:43:18.976051 ==
1300 00:43:18.979051 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 00:43:18.982351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 00:43:18.982497 ==
1303 00:43:18.982595
1304 00:43:18.985817
1305 00:43:18.985955 TX Vref Scan disable
1306 00:43:18.988811 == TX Byte 0 ==
1307 00:43:18.992334 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1308 00:43:18.995574 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1309 00:43:18.999216 == TX Byte 1 ==
1310 00:43:19.002534 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1311 00:43:19.005795 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1312 00:43:19.008913
1313 00:43:19.009073 [DATLAT]
1314 00:43:19.009171 Freq=800, CH0 RK1
1315 00:43:19.009262
1316 00:43:19.012711 DATLAT Default: 0xa
1317 00:43:19.012858 0, 0xFFFF, sum = 0
1318 00:43:19.016044 1, 0xFFFF, sum = 0
1319 00:43:19.016180 2, 0xFFFF, sum = 0
1320 00:43:19.019373 3, 0xFFFF, sum = 0
1321 00:43:19.019514 4, 0xFFFF, sum = 0
1322 00:43:19.022571 5, 0xFFFF, sum = 0
1323 00:43:19.022719 6, 0xFFFF, sum = 0
1324 00:43:19.025782 7, 0xFFFF, sum = 0
1325 00:43:19.025919 8, 0xFFFF, sum = 0
1326 00:43:19.029054 9, 0x0, sum = 1
1327 00:43:19.029189 10, 0x0, sum = 2
1328 00:43:19.032303 11, 0x0, sum = 3
1329 00:43:19.032446 12, 0x0, sum = 4
1330 00:43:19.036275 best_step = 10
1331 00:43:19.036423
1332 00:43:19.036517 ==
1333 00:43:19.039443 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 00:43:19.042468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 00:43:19.042598 ==
1336 00:43:19.046141 RX Vref Scan: 0
1337 00:43:19.046269
1338 00:43:19.046363 RX Vref 0 -> 0, step: 1
1339 00:43:19.046451
1340 00:43:19.049439 RX Delay -79 -> 252, step: 8
1341 00:43:19.055846 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1342 00:43:19.059111 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1343 00:43:19.063055 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 00:43:19.066186 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1345 00:43:19.069271 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1346 00:43:19.072459 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1347 00:43:19.079753 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 00:43:19.083035 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 00:43:19.086350 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1350 00:43:19.089575 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1351 00:43:19.092825 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1352 00:43:19.099843 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1353 00:43:19.103049 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 00:43:19.106101 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1355 00:43:19.109542 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 00:43:19.113161 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1357 00:43:19.116277 ==
1358 00:43:19.119385 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 00:43:19.122772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 00:43:19.122924 ==
1361 00:43:19.123020 DQS Delay:
1362 00:43:19.126139 DQS0 = 0, DQS1 = 0
1363 00:43:19.126264 DQM Delay:
1364 00:43:19.129398 DQM0 = 93, DQM1 = 83
1365 00:43:19.129532 DQ Delay:
1366 00:43:19.132741 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1367 00:43:19.135984 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1368 00:43:19.139266 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1369 00:43:19.143177 DQ12 =84, DQ13 =92, DQ14 =92, DQ15 =92
1370 00:43:19.143330
1371 00:43:19.143424
1372 00:43:19.149729 [DQSOSCAuto] RK1, (LSB)MR18= 0x4314, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
1373 00:43:19.152888 CH0 RK1: MR19=606, MR18=4314
1374 00:43:19.159957 CH0_RK1: MR19=0x606, MR18=0x4314, DQSOSC=393, MR23=63, INC=95, DEC=63
1375 00:43:19.163107 [RxdqsGatingPostProcess] freq 800
1376 00:43:19.166383 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 00:43:19.169742 Pre-setting of DQS Precalculation
1378 00:43:19.176285 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 00:43:19.176507 ==
1380 00:43:19.179762 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 00:43:19.183027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 00:43:19.183182 ==
1383 00:43:19.189697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 00:43:19.196694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 00:43:19.204412 [CA 0] Center 36 (6~67) winsize 62
1386 00:43:19.208025 [CA 1] Center 36 (6~67) winsize 62
1387 00:43:19.210422 [CA 2] Center 34 (4~65) winsize 62
1388 00:43:19.214276 [CA 3] Center 34 (4~65) winsize 62
1389 00:43:19.217568 [CA 4] Center 35 (5~65) winsize 61
1390 00:43:19.220559 [CA 5] Center 34 (4~64) winsize 61
1391 00:43:19.220694
1392 00:43:19.224603 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 00:43:19.224742
1394 00:43:19.227461 [CATrainingPosCal] consider 1 rank data
1395 00:43:19.230879 u2DelayCellTimex100 = 270/100 ps
1396 00:43:19.234159 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 00:43:19.237354 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 00:43:19.244233 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 00:43:19.247971 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 00:43:19.250536 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1401 00:43:19.254128 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 00:43:19.254256
1403 00:43:19.257392 CA PerBit enable=1, Macro0, CA PI delay=34
1404 00:43:19.257481
1405 00:43:19.260869 [CBTSetCACLKResult] CA Dly = 34
1406 00:43:19.260957 CS Dly: 6 (0~37)
1407 00:43:19.261020 ==
1408 00:43:19.264234 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 00:43:19.271687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 00:43:19.271828 ==
1411 00:43:19.274785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 00:43:19.281831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 00:43:19.290199 [CA 0] Center 36 (6~67) winsize 62
1414 00:43:19.294212 [CA 1] Center 37 (6~68) winsize 63
1415 00:43:19.298160 [CA 2] Center 35 (5~66) winsize 62
1416 00:43:19.302182 [CA 3] Center 34 (4~65) winsize 62
1417 00:43:19.305319 [CA 4] Center 35 (5~66) winsize 62
1418 00:43:19.305436 [CA 5] Center 34 (4~65) winsize 62
1419 00:43:19.308940
1420 00:43:19.312147 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 00:43:19.312271
1422 00:43:19.315753 [CATrainingPosCal] consider 2 rank data
1423 00:43:19.319051 u2DelayCellTimex100 = 270/100 ps
1424 00:43:19.322311 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 00:43:19.325575 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 00:43:19.329093 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 00:43:19.332438 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 00:43:19.335683 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 00:43:19.338850 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 00:43:19.338972
1431 00:43:19.342038 CA PerBit enable=1, Macro0, CA PI delay=34
1432 00:43:19.342149
1433 00:43:19.345412 [CBTSetCACLKResult] CA Dly = 34
1434 00:43:19.348912 CS Dly: 7 (0~39)
1435 00:43:19.349036
1436 00:43:19.352141 ----->DramcWriteLeveling(PI) begin...
1437 00:43:19.352255 ==
1438 00:43:19.355495 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 00:43:19.358925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 00:43:19.359047 ==
1441 00:43:19.362371 Write leveling (Byte 0): 27 => 27
1442 00:43:19.365843 Write leveling (Byte 1): 28 => 28
1443 00:43:19.369385 DramcWriteLeveling(PI) end<-----
1444 00:43:19.369509
1445 00:43:19.369577 ==
1446 00:43:19.372865 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 00:43:19.375500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 00:43:19.375616 ==
1449 00:43:19.378825 [Gating] SW mode calibration
1450 00:43:19.386029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 00:43:19.392485 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 00:43:19.396064 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 00:43:19.399037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 00:43:19.405952 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:43:19.409308 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:43:19.412855 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:43:19.419257 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:43:19.422703 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:43:19.426135 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:43:19.432629 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:43:19.436246 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:43:19.439362 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:43:19.442887 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:43:19.449623 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:43:19.452800 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:43:19.456454 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:43:19.463060 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:43:19.466543 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:43:19.469938 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1470 00:43:19.476213 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:43:19.479536 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:43:19.482844 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:43:19.489671 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:43:19.492968 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:43:19.496268 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:43:19.502947 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:43:19.506250 0 9 4 | B1->B0 | 2323 2727 | 1 1 | (1 1) (1 1)
1478 00:43:19.509531 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1479 00:43:19.516151 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:43:19.519509 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:43:19.522905 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:43:19.526401 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:43:19.533038 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 00:43:19.536491 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1485 00:43:19.539850 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
1486 00:43:19.546589 0 10 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1487 00:43:19.549970 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:43:19.553235 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:43:19.559760 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:43:19.563533 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:43:19.566772 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:43:19.573136 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 00:43:19.576598 0 11 4 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
1494 00:43:19.579814 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1495 00:43:19.583330 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:43:19.590026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:43:19.593393 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:43:19.596733 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:43:19.603339 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 00:43:19.606628 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 00:43:19.609975 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 00:43:19.616485 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:43:19.620005 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:43:19.623192 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:43:19.630014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:43:19.633425 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:43:19.636927 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:43:19.643147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:43:19.646981 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:43:19.649945 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:43:19.656537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:43:19.659844 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:43:19.663403 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:43:19.666820 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:43:19.673386 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:43:19.676813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 00:43:19.679962 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 00:43:19.687061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 00:43:19.690401 Total UI for P1: 0, mck2ui 16
1520 00:43:19.693751 best dqsien dly found for B0: ( 0, 14, 4)
1521 00:43:19.693882 Total UI for P1: 0, mck2ui 16
1522 00:43:19.699837 best dqsien dly found for B1: ( 0, 14, 4)
1523 00:43:19.703190 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1524 00:43:19.706469 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 00:43:19.706613
1526 00:43:19.709779 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 00:43:19.713374 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 00:43:19.716447 [Gating] SW calibration Done
1529 00:43:19.716563 ==
1530 00:43:19.720502 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 00:43:19.723120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 00:43:19.723231 ==
1533 00:43:19.726651 RX Vref Scan: 0
1534 00:43:19.726758
1535 00:43:19.726825 RX Vref 0 -> 0, step: 1
1536 00:43:19.726885
1537 00:43:19.730045 RX Delay -130 -> 252, step: 16
1538 00:43:19.733440 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 00:43:19.740301 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1540 00:43:19.743158 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1541 00:43:19.746440 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1542 00:43:19.750006 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1543 00:43:19.753381 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1544 00:43:19.760223 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1545 00:43:19.763685 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1546 00:43:19.766559 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1547 00:43:19.770218 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1548 00:43:19.773733 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1549 00:43:19.780003 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1550 00:43:19.783471 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1551 00:43:19.786924 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1552 00:43:19.789838 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1553 00:43:19.793498 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1554 00:43:19.797319 ==
1555 00:43:19.799940 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 00:43:19.803793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 00:43:19.803916 ==
1558 00:43:19.804020 DQS Delay:
1559 00:43:19.806664 DQS0 = 0, DQS1 = 0
1560 00:43:19.806751 DQM Delay:
1561 00:43:19.810007 DQM0 = 94, DQM1 = 89
1562 00:43:19.810113 DQ Delay:
1563 00:43:19.813309 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1564 00:43:19.816506 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1565 00:43:19.819932 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1566 00:43:19.823310 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1567 00:43:19.823434
1568 00:43:19.823501
1569 00:43:19.823562 ==
1570 00:43:19.827104 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 00:43:19.830480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 00:43:19.830595 ==
1573 00:43:19.830664
1574 00:43:19.830725
1575 00:43:19.833836 TX Vref Scan disable
1576 00:43:19.840766 == TX Byte 0 ==
1577 00:43:19.840944 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1578 00:43:19.843308 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1579 00:43:19.846536 == TX Byte 1 ==
1580 00:43:19.850640 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1581 00:43:19.854095 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1582 00:43:19.854218 ==
1583 00:43:19.857627 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 00:43:19.860952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 00:43:19.861079 ==
1586 00:43:19.874484 TX Vref=22, minBit 0, minWin=26, winSum=437
1587 00:43:19.877888 TX Vref=24, minBit 3, minWin=26, winSum=439
1588 00:43:19.881154 TX Vref=26, minBit 1, minWin=27, winSum=445
1589 00:43:19.884843 TX Vref=28, minBit 2, minWin=27, winSum=449
1590 00:43:19.887866 TX Vref=30, minBit 0, minWin=27, winSum=448
1591 00:43:19.891174 TX Vref=32, minBit 0, minWin=27, winSum=447
1592 00:43:19.897947 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
1593 00:43:19.898075
1594 00:43:19.901653 Final TX Range 1 Vref 28
1595 00:43:19.901765
1596 00:43:19.901831 ==
1597 00:43:19.904774 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 00:43:19.908316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 00:43:19.908426 ==
1600 00:43:19.908493
1601 00:43:19.908553
1602 00:43:19.911639 TX Vref Scan disable
1603 00:43:19.914781 == TX Byte 0 ==
1604 00:43:19.917844 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1605 00:43:19.921488 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1606 00:43:19.925101 == TX Byte 1 ==
1607 00:43:19.928597 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1608 00:43:19.931231 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1609 00:43:19.931337
1610 00:43:19.934442 [DATLAT]
1611 00:43:19.934578 Freq=800, CH1 RK0
1612 00:43:19.934692
1613 00:43:19.937989 DATLAT Default: 0xa
1614 00:43:19.938101 0, 0xFFFF, sum = 0
1615 00:43:19.941786 1, 0xFFFF, sum = 0
1616 00:43:19.941905 2, 0xFFFF, sum = 0
1617 00:43:19.944459 3, 0xFFFF, sum = 0
1618 00:43:19.944557 4, 0xFFFF, sum = 0
1619 00:43:19.947950 5, 0xFFFF, sum = 0
1620 00:43:19.948084 6, 0xFFFF, sum = 0
1621 00:43:19.951503 7, 0xFFFF, sum = 0
1622 00:43:19.951632 8, 0xFFFF, sum = 0
1623 00:43:19.954685 9, 0x0, sum = 1
1624 00:43:19.954811 10, 0x0, sum = 2
1625 00:43:19.958060 11, 0x0, sum = 3
1626 00:43:19.958169 12, 0x0, sum = 4
1627 00:43:19.961749 best_step = 10
1628 00:43:19.961860
1629 00:43:19.961951 ==
1630 00:43:19.964889 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 00:43:19.967702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 00:43:19.967820 ==
1633 00:43:19.971358 RX Vref Scan: 1
1634 00:43:19.971469
1635 00:43:19.971534 Set Vref Range= 32 -> 127
1636 00:43:19.971594
1637 00:43:19.974593 RX Vref 32 -> 127, step: 1
1638 00:43:19.974720
1639 00:43:19.977813 RX Delay -63 -> 252, step: 8
1640 00:43:19.977927
1641 00:43:19.981161 Set Vref, RX VrefLevel [Byte0]: 32
1642 00:43:19.984484 [Byte1]: 32
1643 00:43:19.984624
1644 00:43:19.987843 Set Vref, RX VrefLevel [Byte0]: 33
1645 00:43:19.991032 [Byte1]: 33
1646 00:43:19.994956
1647 00:43:19.995106 Set Vref, RX VrefLevel [Byte0]: 34
1648 00:43:19.998235 [Byte1]: 34
1649 00:43:20.002035
1650 00:43:20.002158 Set Vref, RX VrefLevel [Byte0]: 35
1651 00:43:20.005394 [Byte1]: 35
1652 00:43:20.009787
1653 00:43:20.009916 Set Vref, RX VrefLevel [Byte0]: 36
1654 00:43:20.013145 [Byte1]: 36
1655 00:43:20.017058
1656 00:43:20.017191 Set Vref, RX VrefLevel [Byte0]: 37
1657 00:43:20.020995 [Byte1]: 37
1658 00:43:20.024542
1659 00:43:20.024698 Set Vref, RX VrefLevel [Byte0]: 38
1660 00:43:20.027668 [Byte1]: 38
1661 00:43:20.032393
1662 00:43:20.032523 Set Vref, RX VrefLevel [Byte0]: 39
1663 00:43:20.035677 [Byte1]: 39
1664 00:43:20.039495
1665 00:43:20.039618 Set Vref, RX VrefLevel [Byte0]: 40
1666 00:43:20.042918 [Byte1]: 40
1667 00:43:20.047069
1668 00:43:20.047223 Set Vref, RX VrefLevel [Byte0]: 41
1669 00:43:20.050368 [Byte1]: 41
1670 00:43:20.054786
1671 00:43:20.054914 Set Vref, RX VrefLevel [Byte0]: 42
1672 00:43:20.057783 [Byte1]: 42
1673 00:43:20.061868
1674 00:43:20.061996 Set Vref, RX VrefLevel [Byte0]: 43
1675 00:43:20.065331 [Byte1]: 43
1676 00:43:20.069588
1677 00:43:20.069732 Set Vref, RX VrefLevel [Byte0]: 44
1678 00:43:20.073072 [Byte1]: 44
1679 00:43:20.077520
1680 00:43:20.077653 Set Vref, RX VrefLevel [Byte0]: 45
1681 00:43:20.080690 [Byte1]: 45
1682 00:43:20.084785
1683 00:43:20.084907 Set Vref, RX VrefLevel [Byte0]: 46
1684 00:43:20.088120 [Byte1]: 46
1685 00:43:20.092389
1686 00:43:20.092527 Set Vref, RX VrefLevel [Byte0]: 47
1687 00:43:20.095623 [Byte1]: 47
1688 00:43:20.099754
1689 00:43:20.099880 Set Vref, RX VrefLevel [Byte0]: 48
1690 00:43:20.103111 [Byte1]: 48
1691 00:43:20.106829
1692 00:43:20.106989 Set Vref, RX VrefLevel [Byte0]: 49
1693 00:43:20.110745 [Byte1]: 49
1694 00:43:20.114769
1695 00:43:20.114902 Set Vref, RX VrefLevel [Byte0]: 50
1696 00:43:20.118344 [Byte1]: 50
1697 00:43:20.122182
1698 00:43:20.122306 Set Vref, RX VrefLevel [Byte0]: 51
1699 00:43:20.125399 [Byte1]: 51
1700 00:43:20.129479
1701 00:43:20.129605 Set Vref, RX VrefLevel [Byte0]: 52
1702 00:43:20.132712 [Byte1]: 52
1703 00:43:20.137071
1704 00:43:20.137203 Set Vref, RX VrefLevel [Byte0]: 53
1705 00:43:20.140360 [Byte1]: 53
1706 00:43:20.144327
1707 00:43:20.144459 Set Vref, RX VrefLevel [Byte0]: 54
1708 00:43:20.147941 [Byte1]: 54
1709 00:43:20.152104
1710 00:43:20.152258 Set Vref, RX VrefLevel [Byte0]: 55
1711 00:43:20.155603 [Byte1]: 55
1712 00:43:20.159530
1713 00:43:20.159676 Set Vref, RX VrefLevel [Byte0]: 56
1714 00:43:20.162847 [Byte1]: 56
1715 00:43:20.167205
1716 00:43:20.167364 Set Vref, RX VrefLevel [Byte0]: 57
1717 00:43:20.170270 [Byte1]: 57
1718 00:43:20.174504
1719 00:43:20.174669 Set Vref, RX VrefLevel [Byte0]: 58
1720 00:43:20.178078 [Byte1]: 58
1721 00:43:20.182071
1722 00:43:20.182199 Set Vref, RX VrefLevel [Byte0]: 59
1723 00:43:20.185350 [Byte1]: 59
1724 00:43:20.189375
1725 00:43:20.189510 Set Vref, RX VrefLevel [Byte0]: 60
1726 00:43:20.192880 [Byte1]: 60
1727 00:43:20.196784
1728 00:43:20.196934 Set Vref, RX VrefLevel [Byte0]: 61
1729 00:43:20.200082 [Byte1]: 61
1730 00:43:20.204819
1731 00:43:20.204951 Set Vref, RX VrefLevel [Byte0]: 62
1732 00:43:20.208200 [Byte1]: 62
1733 00:43:20.212380
1734 00:43:20.212528 Set Vref, RX VrefLevel [Byte0]: 63
1735 00:43:20.215171 [Byte1]: 63
1736 00:43:20.219608
1737 00:43:20.219743 Set Vref, RX VrefLevel [Byte0]: 64
1738 00:43:20.223034 [Byte1]: 64
1739 00:43:20.227163
1740 00:43:20.227321 Set Vref, RX VrefLevel [Byte0]: 65
1741 00:43:20.230588 [Byte1]: 65
1742 00:43:20.234951
1743 00:43:20.235108 Set Vref, RX VrefLevel [Byte0]: 66
1744 00:43:20.237936 [Byte1]: 66
1745 00:43:20.241873
1746 00:43:20.242020 Set Vref, RX VrefLevel [Byte0]: 67
1747 00:43:20.245111 [Byte1]: 67
1748 00:43:20.249982
1749 00:43:20.250149 Set Vref, RX VrefLevel [Byte0]: 68
1750 00:43:20.253180 [Byte1]: 68
1751 00:43:20.257202
1752 00:43:20.257369 Set Vref, RX VrefLevel [Byte0]: 69
1753 00:43:20.260622 [Byte1]: 69
1754 00:43:20.264725
1755 00:43:20.264876 Set Vref, RX VrefLevel [Byte0]: 70
1756 00:43:20.268153 [Byte1]: 70
1757 00:43:20.271661
1758 00:43:20.271778 Set Vref, RX VrefLevel [Byte0]: 71
1759 00:43:20.275060 [Byte1]: 71
1760 00:43:20.279701
1761 00:43:20.279857 Set Vref, RX VrefLevel [Byte0]: 72
1762 00:43:20.282879 [Byte1]: 72
1763 00:43:20.286920
1764 00:43:20.287044 Set Vref, RX VrefLevel [Byte0]: 73
1765 00:43:20.290195 [Byte1]: 73
1766 00:43:20.294642
1767 00:43:20.294764 Final RX Vref Byte 0 = 58 to rank0
1768 00:43:20.297846 Final RX Vref Byte 1 = 58 to rank0
1769 00:43:20.301457 Final RX Vref Byte 0 = 58 to rank1
1770 00:43:20.304765 Final RX Vref Byte 1 = 58 to rank1==
1771 00:43:20.308128 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 00:43:20.314378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 00:43:20.314510 ==
1774 00:43:20.314591 DQS Delay:
1775 00:43:20.314654 DQS0 = 0, DQS1 = 0
1776 00:43:20.317733 DQM Delay:
1777 00:43:20.317833 DQM0 = 95, DQM1 = 89
1778 00:43:20.321357 DQ Delay:
1779 00:43:20.324694 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1780 00:43:20.327861 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
1781 00:43:20.327983 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1782 00:43:20.334696 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1783 00:43:20.334830
1784 00:43:20.334899
1785 00:43:20.341466 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1786 00:43:20.344362 CH1 RK0: MR19=606, MR18=2F4C
1787 00:43:20.351606 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1788 00:43:20.351751
1789 00:43:20.354521 ----->DramcWriteLeveling(PI) begin...
1790 00:43:20.354628 ==
1791 00:43:20.358239 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 00:43:20.361533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 00:43:20.361651 ==
1794 00:43:20.364703 Write leveling (Byte 0): 27 => 27
1795 00:43:20.367955 Write leveling (Byte 1): 28 => 28
1796 00:43:20.371223 DramcWriteLeveling(PI) end<-----
1797 00:43:20.371351
1798 00:43:20.371419 ==
1799 00:43:20.374540 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 00:43:20.378279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 00:43:20.378389 ==
1802 00:43:20.381558 [Gating] SW mode calibration
1803 00:43:20.388135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 00:43:20.395037 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 00:43:20.398358 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 00:43:20.401663 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1807 00:43:20.408084 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:43:20.411228 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:43:20.414857 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:43:20.421588 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:43:20.425183 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:43:20.428002 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:43:20.431896 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:43:20.438219 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:43:20.441440 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:43:20.444807 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:43:20.451862 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:43:20.454907 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:43:20.458239 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:43:20.464672 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:43:20.468490 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1822 00:43:20.471748 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1823 00:43:20.478497 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:43:20.481697 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:43:20.485054 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 00:43:20.491734 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:43:20.494935 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:43:20.498170 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:43:20.505129 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:43:20.508396 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1831 00:43:20.511637 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1832 00:43:20.514981 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 00:43:20.521652 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 00:43:20.524930 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 00:43:20.528675 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 00:43:20.535435 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 00:43:20.538591 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1838 00:43:20.541957 0 10 4 | B1->B0 | 2b2b 2f2f | 0 1 | (1 1) (0 0)
1839 00:43:20.548599 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:43:20.551788 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 00:43:20.555068 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 00:43:20.562046 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:43:20.565389 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:43:20.568867 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:43:20.575524 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1846 00:43:20.578830 0 11 4 | B1->B0 | 3d3d 2d2d | 0 1 | (0 0) (0 0)
1847 00:43:20.582104 0 11 8 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)
1848 00:43:20.588678 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 00:43:20.592135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 00:43:20.595477 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 00:43:20.598678 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 00:43:20.605013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 00:43:20.608312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 00:43:20.612017 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1855 00:43:20.618881 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:43:20.622205 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:43:20.625481 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:43:20.632161 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:43:20.635490 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:43:20.638640 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:43:20.645839 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:43:20.649176 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:43:20.652581 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:43:20.658851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:43:20.662294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:43:20.665191 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:43:20.671829 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:43:20.675266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:43:20.678903 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:43:20.682026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 00:43:20.685715 Total UI for P1: 0, mck2ui 16
1872 00:43:20.689026 best dqsien dly found for B0: ( 0, 14, 2)
1873 00:43:20.692118 Total UI for P1: 0, mck2ui 16
1874 00:43:20.695461 best dqsien dly found for B1: ( 0, 14, 2)
1875 00:43:20.698934 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1876 00:43:20.702126 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1877 00:43:20.702246
1878 00:43:20.709140 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1879 00:43:20.712382 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1880 00:43:20.712501 [Gating] SW calibration Done
1881 00:43:20.715125 ==
1882 00:43:20.718979 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 00:43:20.722095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 00:43:20.722217 ==
1885 00:43:20.722287 RX Vref Scan: 0
1886 00:43:20.722389
1887 00:43:20.725513 RX Vref 0 -> 0, step: 1
1888 00:43:20.725625
1889 00:43:20.728814 RX Delay -130 -> 252, step: 16
1890 00:43:20.732180 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1891 00:43:20.735506 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1892 00:43:20.742350 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1893 00:43:20.745945 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1894 00:43:20.748692 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1895 00:43:20.752367 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1896 00:43:20.755595 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1897 00:43:20.758873 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1898 00:43:20.765571 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1899 00:43:20.768905 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1900 00:43:20.772098 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1901 00:43:20.775481 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1902 00:43:20.778834 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1903 00:43:20.785363 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1904 00:43:20.789017 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1905 00:43:20.792657 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1906 00:43:20.792820 ==
1907 00:43:20.795799 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 00:43:20.799043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 00:43:20.799198 ==
1910 00:43:20.802278 DQS Delay:
1911 00:43:20.802422 DQS0 = 0, DQS1 = 0
1912 00:43:20.805443 DQM Delay:
1913 00:43:20.805582 DQM0 = 94, DQM1 = 89
1914 00:43:20.808909 DQ Delay:
1915 00:43:20.809056 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =85
1916 00:43:20.812000 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1917 00:43:20.815723 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1918 00:43:20.819382 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1919 00:43:20.819535
1920 00:43:20.822490
1921 00:43:20.822625 ==
1922 00:43:20.825254 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 00:43:20.829124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 00:43:20.829275 ==
1925 00:43:20.829378
1926 00:43:20.829471
1927 00:43:20.832109 TX Vref Scan disable
1928 00:43:20.832231 == TX Byte 0 ==
1929 00:43:20.838693 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1930 00:43:20.842059 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1931 00:43:20.842210 == TX Byte 1 ==
1932 00:43:20.849157 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1933 00:43:20.852445 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1934 00:43:20.852601 ==
1935 00:43:20.856082 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 00:43:20.858966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 00:43:20.859111 ==
1938 00:43:20.872384 TX Vref=22, minBit 1, minWin=26, winSum=443
1939 00:43:20.876006 TX Vref=24, minBit 1, minWin=26, winSum=444
1940 00:43:20.879027 TX Vref=26, minBit 2, minWin=27, winSum=448
1941 00:43:20.882178 TX Vref=28, minBit 2, minWin=27, winSum=449
1942 00:43:20.885445 TX Vref=30, minBit 2, minWin=27, winSum=451
1943 00:43:20.888774 TX Vref=32, minBit 2, minWin=27, winSum=449
1944 00:43:20.895991 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1945 00:43:20.896179
1946 00:43:20.899062 Final TX Range 1 Vref 30
1947 00:43:20.899169
1948 00:43:20.899234 ==
1949 00:43:20.902448 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 00:43:20.905720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 00:43:20.905876 ==
1952 00:43:20.905973
1953 00:43:20.906069
1954 00:43:20.909381 TX Vref Scan disable
1955 00:43:20.912655 == TX Byte 0 ==
1956 00:43:20.916159 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1957 00:43:20.919416 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1958 00:43:20.922839 == TX Byte 1 ==
1959 00:43:20.926191 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1960 00:43:20.929211 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1961 00:43:20.929350
1962 00:43:20.932756 [DATLAT]
1963 00:43:20.932876 Freq=800, CH1 RK1
1964 00:43:20.932946
1965 00:43:20.936352 DATLAT Default: 0xa
1966 00:43:20.936506 0, 0xFFFF, sum = 0
1967 00:43:20.939353 1, 0xFFFF, sum = 0
1968 00:43:20.939506 2, 0xFFFF, sum = 0
1969 00:43:20.943386 3, 0xFFFF, sum = 0
1970 00:43:20.943534 4, 0xFFFF, sum = 0
1971 00:43:20.945854 5, 0xFFFF, sum = 0
1972 00:43:20.945953 6, 0xFFFF, sum = 0
1973 00:43:20.949758 7, 0xFFFF, sum = 0
1974 00:43:20.949908 8, 0xFFFF, sum = 0
1975 00:43:20.952381 9, 0x0, sum = 1
1976 00:43:20.952476 10, 0x0, sum = 2
1977 00:43:20.956336 11, 0x0, sum = 3
1978 00:43:20.956459 12, 0x0, sum = 4
1979 00:43:20.959322 best_step = 10
1980 00:43:20.959422
1981 00:43:20.959508 ==
1982 00:43:20.962954 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 00:43:20.965968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 00:43:20.966082 ==
1985 00:43:20.969218 RX Vref Scan: 0
1986 00:43:20.969326
1987 00:43:20.969394 RX Vref 0 -> 0, step: 1
1988 00:43:20.969454
1989 00:43:20.973102 RX Delay -63 -> 252, step: 8
1990 00:43:20.975864 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1991 00:43:20.982727 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1992 00:43:20.986085 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1993 00:43:20.989431 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1994 00:43:20.992808 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1995 00:43:20.995969 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1996 00:43:20.999888 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1997 00:43:21.006250 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1998 00:43:21.009521 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1999 00:43:21.012821 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2000 00:43:21.016622 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2001 00:43:21.020007 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2002 00:43:21.026408 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2003 00:43:21.029568 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2004 00:43:21.033498 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2005 00:43:21.036251 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2006 00:43:21.036431 ==
2007 00:43:21.039473 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 00:43:21.043049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 00:43:21.046472 ==
2010 00:43:21.046586 DQS Delay:
2011 00:43:21.046674 DQS0 = 0, DQS1 = 0
2012 00:43:21.049845 DQM Delay:
2013 00:43:21.049943 DQM0 = 97, DQM1 = 91
2014 00:43:21.053199 DQ Delay:
2015 00:43:21.053305 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2016 00:43:21.056527 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2017 00:43:21.059908 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2018 00:43:21.063205 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2019 00:43:21.066890
2020 00:43:21.067056
2021 00:43:21.072928 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2022 00:43:21.076649 CH1 RK1: MR19=606, MR18=4C14
2023 00:43:21.083246 CH1_RK1: MR19=0x606, MR18=0x4C14, DQSOSC=390, MR23=63, INC=97, DEC=64
2024 00:43:21.086314 [RxdqsGatingPostProcess] freq 800
2025 00:43:21.090027 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2026 00:43:21.093094 Pre-setting of DQS Precalculation
2027 00:43:21.099795 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2028 00:43:21.106357 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2029 00:43:21.113323 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2030 00:43:21.113472
2031 00:43:21.113540
2032 00:43:21.116544 [Calibration Summary] 1600 Mbps
2033 00:43:21.116645 CH 0, Rank 0
2034 00:43:21.119844 SW Impedance : PASS
2035 00:43:21.119939 DUTY Scan : NO K
2036 00:43:21.123080 ZQ Calibration : PASS
2037 00:43:21.126401 Jitter Meter : NO K
2038 00:43:21.126519 CBT Training : PASS
2039 00:43:21.129759 Write leveling : PASS
2040 00:43:21.133941 RX DQS gating : PASS
2041 00:43:21.134070 RX DQ/DQS(RDDQC) : PASS
2042 00:43:21.136832 TX DQ/DQS : PASS
2043 00:43:21.140055 RX DATLAT : PASS
2044 00:43:21.140170 RX DQ/DQS(Engine): PASS
2045 00:43:21.143303 TX OE : NO K
2046 00:43:21.143406 All Pass.
2047 00:43:21.143470
2048 00:43:21.146544 CH 0, Rank 1
2049 00:43:21.146641 SW Impedance : PASS
2050 00:43:21.150439 DUTY Scan : NO K
2051 00:43:21.153648 ZQ Calibration : PASS
2052 00:43:21.153771 Jitter Meter : NO K
2053 00:43:21.156777 CBT Training : PASS
2054 00:43:21.156878 Write leveling : PASS
2055 00:43:21.160127 RX DQS gating : PASS
2056 00:43:21.163404 RX DQ/DQS(RDDQC) : PASS
2057 00:43:21.163543 TX DQ/DQS : PASS
2058 00:43:21.166460 RX DATLAT : PASS
2059 00:43:21.169973 RX DQ/DQS(Engine): PASS
2060 00:43:21.170130 TX OE : NO K
2061 00:43:21.173561 All Pass.
2062 00:43:21.173689
2063 00:43:21.173787 CH 1, Rank 0
2064 00:43:21.176304 SW Impedance : PASS
2065 00:43:21.176442 DUTY Scan : NO K
2066 00:43:21.180190 ZQ Calibration : PASS
2067 00:43:21.183540 Jitter Meter : NO K
2068 00:43:21.183657 CBT Training : PASS
2069 00:43:21.186519 Write leveling : PASS
2070 00:43:21.189948 RX DQS gating : PASS
2071 00:43:21.190063 RX DQ/DQS(RDDQC) : PASS
2072 00:43:21.193226 TX DQ/DQS : PASS
2073 00:43:21.193329 RX DATLAT : PASS
2074 00:43:21.196773 RX DQ/DQS(Engine): PASS
2075 00:43:21.200035 TX OE : NO K
2076 00:43:21.200149 All Pass.
2077 00:43:21.200216
2078 00:43:21.200347 CH 1, Rank 1
2079 00:43:21.203175 SW Impedance : PASS
2080 00:43:21.206380 DUTY Scan : NO K
2081 00:43:21.206496 ZQ Calibration : PASS
2082 00:43:21.209727 Jitter Meter : NO K
2083 00:43:21.213558 CBT Training : PASS
2084 00:43:21.213679 Write leveling : PASS
2085 00:43:21.216619 RX DQS gating : PASS
2086 00:43:21.219754 RX DQ/DQS(RDDQC) : PASS
2087 00:43:21.219866 TX DQ/DQS : PASS
2088 00:43:21.223336 RX DATLAT : PASS
2089 00:43:21.227306 RX DQ/DQS(Engine): PASS
2090 00:43:21.227429 TX OE : NO K
2091 00:43:21.229711 All Pass.
2092 00:43:21.229805
2093 00:43:21.229870 DramC Write-DBI off
2094 00:43:21.233098 PER_BANK_REFRESH: Hybrid Mode
2095 00:43:21.233193 TX_TRACKING: ON
2096 00:43:21.236998 [GetDramInforAfterCalByMRR] Vendor 6.
2097 00:43:21.243617 [GetDramInforAfterCalByMRR] Revision 606.
2098 00:43:21.246897 [GetDramInforAfterCalByMRR] Revision 2 0.
2099 00:43:21.247025 MR0 0x3b3b
2100 00:43:21.247119 MR8 0x5151
2101 00:43:21.250121 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 00:43:21.250221
2103 00:43:21.253218 MR0 0x3b3b
2104 00:43:21.253319 MR8 0x5151
2105 00:43:21.256404 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 00:43:21.256545
2107 00:43:21.266659 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2108 00:43:21.269928 [FAST_K] Save calibration result to emmc
2109 00:43:21.273800 [FAST_K] Save calibration result to emmc
2110 00:43:21.277056 dram_init: config_dvfs: 1
2111 00:43:21.280384 dramc_set_vcore_voltage set vcore to 662500
2112 00:43:21.283625 Read voltage for 1200, 2
2113 00:43:21.283741 Vio18 = 0
2114 00:43:21.283809 Vcore = 662500
2115 00:43:21.283869 Vdram = 0
2116 00:43:21.286763 Vddq = 0
2117 00:43:21.286857 Vmddr = 0
2118 00:43:21.293616 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2119 00:43:21.296650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2120 00:43:21.300384 MEM_TYPE=3, freq_sel=15
2121 00:43:21.303457 sv_algorithm_assistance_LP4_1600
2122 00:43:21.306874 ============ PULL DRAM RESETB DOWN ============
2123 00:43:21.310152 ========== PULL DRAM RESETB DOWN end =========
2124 00:43:21.316764 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2125 00:43:21.320248 ===================================
2126 00:43:21.320408 LPDDR4 DRAM CONFIGURATION
2127 00:43:21.323608 ===================================
2128 00:43:21.327281 EX_ROW_EN[0] = 0x0
2129 00:43:21.327408 EX_ROW_EN[1] = 0x0
2130 00:43:21.330464 LP4Y_EN = 0x0
2131 00:43:21.330593 WORK_FSP = 0x0
2132 00:43:21.333518 WL = 0x4
2133 00:43:21.333645 RL = 0x4
2134 00:43:21.336873 BL = 0x2
2135 00:43:21.336975 RPST = 0x0
2136 00:43:21.340479 RD_PRE = 0x0
2137 00:43:21.343507 WR_PRE = 0x1
2138 00:43:21.343614 WR_PST = 0x0
2139 00:43:21.346851 DBI_WR = 0x0
2140 00:43:21.346949 DBI_RD = 0x0
2141 00:43:21.350760 OTF = 0x1
2142 00:43:21.353814 ===================================
2143 00:43:21.356919 ===================================
2144 00:43:21.357087 ANA top config
2145 00:43:21.361016 ===================================
2146 00:43:21.364214 DLL_ASYNC_EN = 0
2147 00:43:21.364396 ALL_SLAVE_EN = 0
2148 00:43:21.367537 NEW_RANK_MODE = 1
2149 00:43:21.370726 DLL_IDLE_MODE = 1
2150 00:43:21.373979 LP45_APHY_COMB_EN = 1
2151 00:43:21.377325 TX_ODT_DIS = 1
2152 00:43:21.377441 NEW_8X_MODE = 1
2153 00:43:21.381120 ===================================
2154 00:43:21.384018 ===================================
2155 00:43:21.387400 data_rate = 2400
2156 00:43:21.390597 CKR = 1
2157 00:43:21.393931 DQ_P2S_RATIO = 8
2158 00:43:21.397156 ===================================
2159 00:43:21.400276 CA_P2S_RATIO = 8
2160 00:43:21.403992 DQ_CA_OPEN = 0
2161 00:43:21.404138 DQ_SEMI_OPEN = 0
2162 00:43:21.407194 CA_SEMI_OPEN = 0
2163 00:43:21.410357 CA_FULL_RATE = 0
2164 00:43:21.413737 DQ_CKDIV4_EN = 0
2165 00:43:21.417044 CA_CKDIV4_EN = 0
2166 00:43:21.417161 CA_PREDIV_EN = 0
2167 00:43:21.420821 PH8_DLY = 17
2168 00:43:21.423781 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2169 00:43:21.427280 DQ_AAMCK_DIV = 4
2170 00:43:21.430537 CA_AAMCK_DIV = 4
2171 00:43:21.433983 CA_ADMCK_DIV = 4
2172 00:43:21.434131 DQ_TRACK_CA_EN = 0
2173 00:43:21.437051 CA_PICK = 1200
2174 00:43:21.440729 CA_MCKIO = 1200
2175 00:43:21.443536 MCKIO_SEMI = 0
2176 00:43:21.447421 PLL_FREQ = 2366
2177 00:43:21.450294 DQ_UI_PI_RATIO = 32
2178 00:43:21.453627 CA_UI_PI_RATIO = 0
2179 00:43:21.457532 ===================================
2180 00:43:21.460327 ===================================
2181 00:43:21.460480 memory_type:LPDDR4
2182 00:43:21.463630 GP_NUM : 10
2183 00:43:21.466941 SRAM_EN : 1
2184 00:43:21.467050 MD32_EN : 0
2185 00:43:21.470283 ===================================
2186 00:43:21.473628 [ANA_INIT] >>>>>>>>>>>>>>
2187 00:43:21.477237 <<<<<< [CONFIGURE PHASE]: ANA_TX
2188 00:43:21.480324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2189 00:43:21.483640 ===================================
2190 00:43:21.486971 data_rate = 2400,PCW = 0X5b00
2191 00:43:21.491018 ===================================
2192 00:43:21.494102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2193 00:43:21.497582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 00:43:21.503980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 00:43:21.507031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2196 00:43:21.510931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2197 00:43:21.514201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2198 00:43:21.517432 [ANA_INIT] flow start
2199 00:43:21.520770 [ANA_INIT] PLL >>>>>>>>
2200 00:43:21.520912 [ANA_INIT] PLL <<<<<<<<
2201 00:43:21.524044 [ANA_INIT] MIDPI >>>>>>>>
2202 00:43:21.527574 [ANA_INIT] MIDPI <<<<<<<<
2203 00:43:21.527695 [ANA_INIT] DLL >>>>>>>>
2204 00:43:21.530866 [ANA_INIT] DLL <<<<<<<<
2205 00:43:21.533896 [ANA_INIT] flow end
2206 00:43:21.537054 ============ LP4 DIFF to SE enter ============
2207 00:43:21.540301 ============ LP4 DIFF to SE exit ============
2208 00:43:21.543747 [ANA_INIT] <<<<<<<<<<<<<
2209 00:43:21.547609 [Flow] Enable top DCM control >>>>>
2210 00:43:21.550447 [Flow] Enable top DCM control <<<<<
2211 00:43:21.554038 Enable DLL master slave shuffle
2212 00:43:21.557044 ==============================================================
2213 00:43:21.560519 Gating Mode config
2214 00:43:21.567199 ==============================================================
2215 00:43:21.567338 Config description:
2216 00:43:21.577237 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2217 00:43:21.584182 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2218 00:43:21.587397 SELPH_MODE 0: By rank 1: By Phase
2219 00:43:21.594053 ==============================================================
2220 00:43:21.597427 GAT_TRACK_EN = 1
2221 00:43:21.600746 RX_GATING_MODE = 2
2222 00:43:21.604072 RX_GATING_TRACK_MODE = 2
2223 00:43:21.607276 SELPH_MODE = 1
2224 00:43:21.610482 PICG_EARLY_EN = 1
2225 00:43:21.610598 VALID_LAT_VALUE = 1
2226 00:43:21.617461 ==============================================================
2227 00:43:21.620764 Enter into Gating configuration >>>>
2228 00:43:21.624175 Exit from Gating configuration <<<<
2229 00:43:21.627420 Enter into DVFS_PRE_config >>>>>
2230 00:43:21.637783 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2231 00:43:21.640809 Exit from DVFS_PRE_config <<<<<
2232 00:43:21.644041 Enter into PICG configuration >>>>
2233 00:43:21.647522 Exit from PICG configuration <<<<
2234 00:43:21.650676 [RX_INPUT] configuration >>>>>
2235 00:43:21.654017 [RX_INPUT] configuration <<<<<
2236 00:43:21.657661 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2237 00:43:21.663955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2238 00:43:21.670684 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 00:43:21.677637 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 00:43:21.684102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 00:43:21.687876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 00:43:21.694263 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2243 00:43:21.697485 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2244 00:43:21.700906 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2245 00:43:21.704136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2246 00:43:21.707822 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2247 00:43:21.714532 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2248 00:43:21.717766 ===================================
2249 00:43:21.720805 LPDDR4 DRAM CONFIGURATION
2250 00:43:21.724388 ===================================
2251 00:43:21.724509 EX_ROW_EN[0] = 0x0
2252 00:43:21.727623 EX_ROW_EN[1] = 0x0
2253 00:43:21.727737 LP4Y_EN = 0x0
2254 00:43:21.730961 WORK_FSP = 0x0
2255 00:43:21.731063 WL = 0x4
2256 00:43:21.734176 RL = 0x4
2257 00:43:21.734298 BL = 0x2
2258 00:43:21.737515 RPST = 0x0
2259 00:43:21.737619 RD_PRE = 0x0
2260 00:43:21.740848 WR_PRE = 0x1
2261 00:43:21.740945 WR_PST = 0x0
2262 00:43:21.744657 DBI_WR = 0x0
2263 00:43:21.744765 DBI_RD = 0x0
2264 00:43:21.747323 OTF = 0x1
2265 00:43:21.750947 ===================================
2266 00:43:21.754043 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2267 00:43:21.757414 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2268 00:43:21.764239 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 00:43:21.767487 ===================================
2270 00:43:21.767606 LPDDR4 DRAM CONFIGURATION
2271 00:43:21.770819 ===================================
2272 00:43:21.774689 EX_ROW_EN[0] = 0x10
2273 00:43:21.777997 EX_ROW_EN[1] = 0x0
2274 00:43:21.778118 LP4Y_EN = 0x0
2275 00:43:21.781120 WORK_FSP = 0x0
2276 00:43:21.781218 WL = 0x4
2277 00:43:21.784464 RL = 0x4
2278 00:43:21.784562 BL = 0x2
2279 00:43:21.787659 RPST = 0x0
2280 00:43:21.787755 RD_PRE = 0x0
2281 00:43:21.791063 WR_PRE = 0x1
2282 00:43:21.791182 WR_PST = 0x0
2283 00:43:21.794323 DBI_WR = 0x0
2284 00:43:21.794424 DBI_RD = 0x0
2285 00:43:21.797606 OTF = 0x1
2286 00:43:21.800808 ===================================
2287 00:43:21.807556 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2288 00:43:21.807748 ==
2289 00:43:21.811055 Dram Type= 6, Freq= 0, CH_0, rank 0
2290 00:43:21.814477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2291 00:43:21.814595 ==
2292 00:43:21.817744 [Duty_Offset_Calibration]
2293 00:43:21.817875 B0:2 B1:1 CA:1
2294 00:43:21.817967
2295 00:43:21.820796 [DutyScan_Calibration_Flow] k_type=0
2296 00:43:21.830734
2297 00:43:21.830866 ==CLK 0==
2298 00:43:21.834431 Final CLK duty delay cell = 0
2299 00:43:21.837546 [0] MAX Duty = 5218%(X100), DQS PI = 24
2300 00:43:21.841063 [0] MIN Duty = 4813%(X100), DQS PI = 48
2301 00:43:21.841184 [0] AVG Duty = 5015%(X100)
2302 00:43:21.844213
2303 00:43:21.847717 CH0 CLK Duty spec in!! Max-Min= 405%
2304 00:43:21.851063 [DutyScan_Calibration_Flow] ====Done====
2305 00:43:21.851177
2306 00:43:21.854034 [DutyScan_Calibration_Flow] k_type=1
2307 00:43:21.869417
2308 00:43:21.869609 ==DQS 0 ==
2309 00:43:21.872534 Final DQS duty delay cell = -4
2310 00:43:21.875929 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2311 00:43:21.879838 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2312 00:43:21.883109 [-4] AVG Duty = 4937%(X100)
2313 00:43:21.883248
2314 00:43:21.883340 ==DQS 1 ==
2315 00:43:21.886397 Final DQS duty delay cell = 0
2316 00:43:21.889717 [0] MAX Duty = 5156%(X100), DQS PI = 0
2317 00:43:21.893051 [0] MIN Duty = 5000%(X100), DQS PI = 34
2318 00:43:21.896468 [0] AVG Duty = 5078%(X100)
2319 00:43:21.896601
2320 00:43:21.899897 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2321 00:43:21.900026
2322 00:43:21.903049 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2323 00:43:21.906379 [DutyScan_Calibration_Flow] ====Done====
2324 00:43:21.906525
2325 00:43:21.909731 [DutyScan_Calibration_Flow] k_type=3
2326 00:43:21.926269
2327 00:43:21.926428 ==DQM 0 ==
2328 00:43:21.929907 Final DQM duty delay cell = 0
2329 00:43:21.933049 [0] MAX Duty = 5156%(X100), DQS PI = 30
2330 00:43:21.936219 [0] MIN Duty = 4906%(X100), DQS PI = 2
2331 00:43:21.936400 [0] AVG Duty = 5031%(X100)
2332 00:43:21.939873
2333 00:43:21.939970 ==DQM 1 ==
2334 00:43:21.943164 Final DQM duty delay cell = 0
2335 00:43:21.946245 [0] MAX Duty = 5124%(X100), DQS PI = 8
2336 00:43:21.949378 [0] MIN Duty = 5031%(X100), DQS PI = 50
2337 00:43:21.949497 [0] AVG Duty = 5077%(X100)
2338 00:43:21.952946
2339 00:43:21.956192 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2340 00:43:21.956326
2341 00:43:21.959947 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2342 00:43:21.963027 [DutyScan_Calibration_Flow] ====Done====
2343 00:43:21.963132
2344 00:43:21.966430 [DutyScan_Calibration_Flow] k_type=2
2345 00:43:21.982908
2346 00:43:21.983053 ==DQ 0 ==
2347 00:43:21.986068 Final DQ duty delay cell = 0
2348 00:43:21.989332 [0] MAX Duty = 5031%(X100), DQS PI = 26
2349 00:43:21.992698 [0] MIN Duty = 4875%(X100), DQS PI = 0
2350 00:43:21.992824 [0] AVG Duty = 4953%(X100)
2351 00:43:21.992895
2352 00:43:21.996037 ==DQ 1 ==
2353 00:43:21.999283 Final DQ duty delay cell = 0
2354 00:43:22.002484 [0] MAX Duty = 5093%(X100), DQS PI = 10
2355 00:43:22.005876 [0] MIN Duty = 4907%(X100), DQS PI = 36
2356 00:43:22.006045 [0] AVG Duty = 5000%(X100)
2357 00:43:22.006158
2358 00:43:22.009135 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2359 00:43:22.009237
2360 00:43:22.013032 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2361 00:43:22.019527 [DutyScan_Calibration_Flow] ====Done====
2362 00:43:22.019659 ==
2363 00:43:22.022809 Dram Type= 6, Freq= 0, CH_1, rank 0
2364 00:43:22.026024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 00:43:22.026142 ==
2366 00:43:22.029356 [Duty_Offset_Calibration]
2367 00:43:22.029482 B0:1 B1:0 CA:0
2368 00:43:22.029579
2369 00:43:22.032502 [DutyScan_Calibration_Flow] k_type=0
2370 00:43:22.041862
2371 00:43:22.042114 ==CLK 0==
2372 00:43:22.045636 Final CLK duty delay cell = -4
2373 00:43:22.048541 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2374 00:43:22.051883 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2375 00:43:22.055186 [-4] AVG Duty = 4969%(X100)
2376 00:43:22.055321
2377 00:43:22.058552 CH1 CLK Duty spec in!! Max-Min= 124%
2378 00:43:22.062003 [DutyScan_Calibration_Flow] ====Done====
2379 00:43:22.062123
2380 00:43:22.065176 [DutyScan_Calibration_Flow] k_type=1
2381 00:43:22.081727
2382 00:43:22.081869 ==DQS 0 ==
2383 00:43:22.084798 Final DQS duty delay cell = 0
2384 00:43:22.087935 [0] MAX Duty = 5062%(X100), DQS PI = 14
2385 00:43:22.091585 [0] MIN Duty = 4844%(X100), DQS PI = 0
2386 00:43:22.094897 [0] AVG Duty = 4953%(X100)
2387 00:43:22.095019
2388 00:43:22.095085 ==DQS 1 ==
2389 00:43:22.098153 Final DQS duty delay cell = 0
2390 00:43:22.101844 [0] MAX Duty = 5187%(X100), DQS PI = 18
2391 00:43:22.105165 [0] MIN Duty = 4938%(X100), DQS PI = 12
2392 00:43:22.105286 [0] AVG Duty = 5062%(X100)
2393 00:43:22.108148
2394 00:43:22.111491 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2395 00:43:22.111608
2396 00:43:22.114749 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2397 00:43:22.118066 [DutyScan_Calibration_Flow] ====Done====
2398 00:43:22.118185
2399 00:43:22.121199 [DutyScan_Calibration_Flow] k_type=3
2400 00:43:22.138140
2401 00:43:22.138286 ==DQM 0 ==
2402 00:43:22.141405 Final DQM duty delay cell = 0
2403 00:43:22.144701 [0] MAX Duty = 5187%(X100), DQS PI = 10
2404 00:43:22.147912 [0] MIN Duty = 5031%(X100), DQS PI = 0
2405 00:43:22.148055 [0] AVG Duty = 5109%(X100)
2406 00:43:22.151530
2407 00:43:22.151668 ==DQM 1 ==
2408 00:43:22.155167 Final DQM duty delay cell = 0
2409 00:43:22.158457 [0] MAX Duty = 5031%(X100), DQS PI = 24
2410 00:43:22.161708 [0] MIN Duty = 4907%(X100), DQS PI = 36
2411 00:43:22.161832 [0] AVG Duty = 4969%(X100)
2412 00:43:22.165032
2413 00:43:22.168328 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2414 00:43:22.168454
2415 00:43:22.171738 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2416 00:43:22.174925 [DutyScan_Calibration_Flow] ====Done====
2417 00:43:22.175035
2418 00:43:22.178223 [DutyScan_Calibration_Flow] k_type=2
2419 00:43:22.193784
2420 00:43:22.193919 ==DQ 0 ==
2421 00:43:22.197315 Final DQ duty delay cell = -4
2422 00:43:22.200370 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2423 00:43:22.204297 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2424 00:43:22.207336 [-4] AVG Duty = 5000%(X100)
2425 00:43:22.207464
2426 00:43:22.207530 ==DQ 1 ==
2427 00:43:22.210484 Final DQ duty delay cell = 0
2428 00:43:22.214180 [0] MAX Duty = 5125%(X100), DQS PI = 20
2429 00:43:22.217491 [0] MIN Duty = 4969%(X100), DQS PI = 12
2430 00:43:22.220732 [0] AVG Duty = 5047%(X100)
2431 00:43:22.220852
2432 00:43:22.223700 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2433 00:43:22.223799
2434 00:43:22.227021 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2435 00:43:22.230474 [DutyScan_Calibration_Flow] ====Done====
2436 00:43:22.233449 nWR fixed to 30
2437 00:43:22.237409 [ModeRegInit_LP4] CH0 RK0
2438 00:43:22.237568 [ModeRegInit_LP4] CH0 RK1
2439 00:43:22.240237 [ModeRegInit_LP4] CH1 RK0
2440 00:43:22.244011 [ModeRegInit_LP4] CH1 RK1
2441 00:43:22.244170 match AC timing 7
2442 00:43:22.250481 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2443 00:43:22.253799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2444 00:43:22.256949 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2445 00:43:22.263759 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2446 00:43:22.267448 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2447 00:43:22.267600 ==
2448 00:43:22.270815 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 00:43:22.274067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 00:43:22.274213 ==
2451 00:43:22.280814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2452 00:43:22.287280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2453 00:43:22.294377 [CA 0] Center 39 (8~70) winsize 63
2454 00:43:22.297559 [CA 1] Center 39 (8~70) winsize 63
2455 00:43:22.300920 [CA 2] Center 35 (4~66) winsize 63
2456 00:43:22.304766 [CA 3] Center 34 (4~65) winsize 62
2457 00:43:22.308026 [CA 4] Center 33 (3~64) winsize 62
2458 00:43:22.311257 [CA 5] Center 32 (3~62) winsize 60
2459 00:43:22.311403
2460 00:43:22.314416 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2461 00:43:22.314577
2462 00:43:22.318162 [CATrainingPosCal] consider 1 rank data
2463 00:43:22.321128 u2DelayCellTimex100 = 270/100 ps
2464 00:43:22.324211 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 00:43:22.327496 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2466 00:43:22.330968 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2467 00:43:22.337940 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2468 00:43:22.341042 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2469 00:43:22.344720 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2470 00:43:22.344865
2471 00:43:22.348246 CA PerBit enable=1, Macro0, CA PI delay=32
2472 00:43:22.348403
2473 00:43:22.351453 [CBTSetCACLKResult] CA Dly = 32
2474 00:43:22.351574 CS Dly: 6 (0~37)
2475 00:43:22.351666 ==
2476 00:43:22.354796 Dram Type= 6, Freq= 0, CH_0, rank 1
2477 00:43:22.361056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2478 00:43:22.361217 ==
2479 00:43:22.364808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2480 00:43:22.371490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2481 00:43:22.380068 [CA 0] Center 38 (8~69) winsize 62
2482 00:43:22.383692 [CA 1] Center 38 (8~69) winsize 62
2483 00:43:22.386836 [CA 2] Center 35 (5~66) winsize 62
2484 00:43:22.389901 [CA 3] Center 34 (4~65) winsize 62
2485 00:43:22.393703 [CA 4] Center 33 (3~64) winsize 62
2486 00:43:22.397035 [CA 5] Center 32 (3~62) winsize 60
2487 00:43:22.397183
2488 00:43:22.400333 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2489 00:43:22.400491
2490 00:43:22.403780 [CATrainingPosCal] consider 2 rank data
2491 00:43:22.406906 u2DelayCellTimex100 = 270/100 ps
2492 00:43:22.410166 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 00:43:22.413456 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2494 00:43:22.419875 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2495 00:43:22.423589 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2496 00:43:22.426745 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2497 00:43:22.430448 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2498 00:43:22.430569
2499 00:43:22.433709 CA PerBit enable=1, Macro0, CA PI delay=32
2500 00:43:22.433814
2501 00:43:22.437040 [CBTSetCACLKResult] CA Dly = 32
2502 00:43:22.437142 CS Dly: 6 (0~38)
2503 00:43:22.437207
2504 00:43:22.440286 ----->DramcWriteLeveling(PI) begin...
2505 00:43:22.443622 ==
2506 00:43:22.443735 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 00:43:22.450143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 00:43:22.450279 ==
2509 00:43:22.453463 Write leveling (Byte 0): 31 => 31
2510 00:43:22.456743 Write leveling (Byte 1): 31 => 31
2511 00:43:22.460075 DramcWriteLeveling(PI) end<-----
2512 00:43:22.460196
2513 00:43:22.460267 ==
2514 00:43:22.463143 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 00:43:22.466850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 00:43:22.466974 ==
2517 00:43:22.469973 [Gating] SW mode calibration
2518 00:43:22.476737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2519 00:43:22.480197 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2520 00:43:22.486813 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2521 00:43:22.490557 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2522 00:43:22.493692 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 00:43:22.500549 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 00:43:22.503763 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 00:43:22.507015 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 00:43:22.513498 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2527 00:43:22.516723 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
2528 00:43:22.520031 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2529 00:43:22.526497 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 00:43:22.529903 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 00:43:22.533600 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 00:43:22.540056 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 00:43:22.543492 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 00:43:22.546725 1 0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2535 00:43:22.553465 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
2536 00:43:22.556764 1 1 0 | B1->B0 | 3534 4646 | 1 0 | (0 0) (0 0)
2537 00:43:22.560049 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 00:43:22.566570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 00:43:22.570284 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 00:43:22.573409 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 00:43:22.576619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 00:43:22.583779 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 00:43:22.587168 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2544 00:43:22.589891 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2545 00:43:22.597031 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:43:22.600209 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:43:22.603350 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:43:22.610795 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:43:22.613545 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:43:22.616830 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:43:22.623435 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:43:22.626968 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:43:22.630048 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:43:22.636947 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:43:22.640016 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:43:22.643096 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:43:22.649956 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:43:22.653110 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 00:43:22.656447 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2560 00:43:22.663604 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2561 00:43:22.663744 Total UI for P1: 0, mck2ui 16
2562 00:43:22.666783 best dqsien dly found for B0: ( 1, 3, 26)
2563 00:43:22.673287 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 00:43:22.676839 Total UI for P1: 0, mck2ui 16
2565 00:43:22.679947 best dqsien dly found for B1: ( 1, 3, 30)
2566 00:43:22.683226 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2567 00:43:22.686536 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2568 00:43:22.686655
2569 00:43:22.689779 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2570 00:43:22.693082 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2571 00:43:22.696405 [Gating] SW calibration Done
2572 00:43:22.696518 ==
2573 00:43:22.700136 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 00:43:22.703336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 00:43:22.703460 ==
2576 00:43:22.707038 RX Vref Scan: 0
2577 00:43:22.707171
2578 00:43:22.707260 RX Vref 0 -> 0, step: 1
2579 00:43:22.710344
2580 00:43:22.710441 RX Delay -40 -> 252, step: 8
2581 00:43:22.716847 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2582 00:43:22.719876 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2583 00:43:22.723176 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2584 00:43:22.726959 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2585 00:43:22.730115 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2586 00:43:22.733194 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2587 00:43:22.740599 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2588 00:43:22.743804 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2589 00:43:22.747052 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2590 00:43:22.750390 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2591 00:43:22.753648 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2592 00:43:22.760626 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2593 00:43:22.764000 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2594 00:43:22.767251 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2595 00:43:22.770431 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2596 00:43:22.773717 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2597 00:43:22.777036 ==
2598 00:43:22.777156 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 00:43:22.783931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 00:43:22.784065 ==
2601 00:43:22.784136 DQS Delay:
2602 00:43:22.786954 DQS0 = 0, DQS1 = 0
2603 00:43:22.787050 DQM Delay:
2604 00:43:22.790472 DQM0 = 121, DQM1 = 113
2605 00:43:22.790577 DQ Delay:
2606 00:43:22.793475 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2607 00:43:22.797374 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2608 00:43:22.800034 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2609 00:43:22.804003 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2610 00:43:22.804127
2611 00:43:22.804197
2612 00:43:22.804255 ==
2613 00:43:22.807319 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 00:43:22.813589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 00:43:22.813730 ==
2616 00:43:22.813796
2617 00:43:22.813854
2618 00:43:22.813910 TX Vref Scan disable
2619 00:43:22.816773 == TX Byte 0 ==
2620 00:43:22.820718 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2621 00:43:22.823849 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2622 00:43:22.826934 == TX Byte 1 ==
2623 00:43:22.830787 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2624 00:43:22.834100 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2625 00:43:22.837464 ==
2626 00:43:22.837603 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 00:43:22.843655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 00:43:22.843809 ==
2629 00:43:22.854502 TX Vref=22, minBit 12, minWin=24, winSum=403
2630 00:43:22.858221 TX Vref=24, minBit 0, minWin=25, winSum=412
2631 00:43:22.861288 TX Vref=26, minBit 0, minWin=25, winSum=413
2632 00:43:22.864633 TX Vref=28, minBit 10, minWin=25, winSum=421
2633 00:43:22.867991 TX Vref=30, minBit 12, minWin=25, winSum=424
2634 00:43:22.874472 TX Vref=32, minBit 10, minWin=25, winSum=421
2635 00:43:22.878075 [TxChooseVref] Worse bit 12, Min win 25, Win sum 424, Final Vref 30
2636 00:43:22.878221
2637 00:43:22.881093 Final TX Range 1 Vref 30
2638 00:43:22.881210
2639 00:43:22.881319 ==
2640 00:43:22.884909 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 00:43:22.887682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 00:43:22.891445 ==
2643 00:43:22.891657
2644 00:43:22.891794
2645 00:43:22.891892 TX Vref Scan disable
2646 00:43:22.894480 == TX Byte 0 ==
2647 00:43:22.897887 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2648 00:43:22.901318 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2649 00:43:22.904854 == TX Byte 1 ==
2650 00:43:22.908070 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2651 00:43:22.911522 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2652 00:43:22.911634
2653 00:43:22.915173 [DATLAT]
2654 00:43:22.915279 Freq=1200, CH0 RK0
2655 00:43:22.915424
2656 00:43:22.918239 DATLAT Default: 0xd
2657 00:43:22.918336 0, 0xFFFF, sum = 0
2658 00:43:22.922035 1, 0xFFFF, sum = 0
2659 00:43:22.922132 2, 0xFFFF, sum = 0
2660 00:43:22.925044 3, 0xFFFF, sum = 0
2661 00:43:22.925128 4, 0xFFFF, sum = 0
2662 00:43:22.928526 5, 0xFFFF, sum = 0
2663 00:43:22.928666 6, 0xFFFF, sum = 0
2664 00:43:22.931766 7, 0xFFFF, sum = 0
2665 00:43:22.931850 8, 0xFFFF, sum = 0
2666 00:43:22.934930 9, 0xFFFF, sum = 0
2667 00:43:22.938182 10, 0xFFFF, sum = 0
2668 00:43:22.938332 11, 0xFFFF, sum = 0
2669 00:43:22.941678 12, 0x0, sum = 1
2670 00:43:22.941797 13, 0x0, sum = 2
2671 00:43:22.941891 14, 0x0, sum = 3
2672 00:43:22.945066 15, 0x0, sum = 4
2673 00:43:22.945150 best_step = 13
2674 00:43:22.945212
2675 00:43:22.948180 ==
2676 00:43:22.948281 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 00:43:22.954748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 00:43:22.954866 ==
2679 00:43:22.954932 RX Vref Scan: 1
2680 00:43:22.954993
2681 00:43:22.958036 Set Vref Range= 32 -> 127
2682 00:43:22.958130
2683 00:43:22.961487 RX Vref 32 -> 127, step: 1
2684 00:43:22.961619
2685 00:43:22.964830 RX Delay -13 -> 252, step: 4
2686 00:43:22.964922
2687 00:43:22.968202 Set Vref, RX VrefLevel [Byte0]: 32
2688 00:43:22.971580 [Byte1]: 32
2689 00:43:22.971674
2690 00:43:22.975155 Set Vref, RX VrefLevel [Byte0]: 33
2691 00:43:22.978248 [Byte1]: 33
2692 00:43:22.978383
2693 00:43:22.981549 Set Vref, RX VrefLevel [Byte0]: 34
2694 00:43:22.984596 [Byte1]: 34
2695 00:43:22.988921
2696 00:43:22.989031 Set Vref, RX VrefLevel [Byte0]: 35
2697 00:43:22.991948 [Byte1]: 35
2698 00:43:22.996681
2699 00:43:22.996791 Set Vref, RX VrefLevel [Byte0]: 36
2700 00:43:23.000115 [Byte1]: 36
2701 00:43:23.004664
2702 00:43:23.004779 Set Vref, RX VrefLevel [Byte0]: 37
2703 00:43:23.008060 [Byte1]: 37
2704 00:43:23.012689
2705 00:43:23.012824 Set Vref, RX VrefLevel [Byte0]: 38
2706 00:43:23.015724 [Byte1]: 38
2707 00:43:23.020400
2708 00:43:23.020537 Set Vref, RX VrefLevel [Byte0]: 39
2709 00:43:23.023622 [Byte1]: 39
2710 00:43:23.028193
2711 00:43:23.028331 Set Vref, RX VrefLevel [Byte0]: 40
2712 00:43:23.031945 [Byte1]: 40
2713 00:43:23.036442
2714 00:43:23.036561 Set Vref, RX VrefLevel [Byte0]: 41
2715 00:43:23.039907 [Byte1]: 41
2716 00:43:23.044398
2717 00:43:23.044547 Set Vref, RX VrefLevel [Byte0]: 42
2718 00:43:23.047665 [Byte1]: 42
2719 00:43:23.051710
2720 00:43:23.051815 Set Vref, RX VrefLevel [Byte0]: 43
2721 00:43:23.055654 [Byte1]: 43
2722 00:43:23.060016
2723 00:43:23.060119 Set Vref, RX VrefLevel [Byte0]: 44
2724 00:43:23.063159 [Byte1]: 44
2725 00:43:23.068150
2726 00:43:23.068271 Set Vref, RX VrefLevel [Byte0]: 45
2727 00:43:23.071358 [Byte1]: 45
2728 00:43:23.075362
2729 00:43:23.075471 Set Vref, RX VrefLevel [Byte0]: 46
2730 00:43:23.078816 [Byte1]: 46
2731 00:43:23.083913
2732 00:43:23.084037 Set Vref, RX VrefLevel [Byte0]: 47
2733 00:43:23.087169 [Byte1]: 47
2734 00:43:23.091151
2735 00:43:23.091256 Set Vref, RX VrefLevel [Byte0]: 48
2736 00:43:23.094437 [Byte1]: 48
2737 00:43:23.099059
2738 00:43:23.099175 Set Vref, RX VrefLevel [Byte0]: 49
2739 00:43:23.102958 [Byte1]: 49
2740 00:43:23.107282
2741 00:43:23.107426 Set Vref, RX VrefLevel [Byte0]: 50
2742 00:43:23.110767 [Byte1]: 50
2743 00:43:23.114942
2744 00:43:23.115090 Set Vref, RX VrefLevel [Byte0]: 51
2745 00:43:23.118264 [Byte1]: 51
2746 00:43:23.122830
2747 00:43:23.122951 Set Vref, RX VrefLevel [Byte0]: 52
2748 00:43:23.126551 [Byte1]: 52
2749 00:43:23.131114
2750 00:43:23.131244 Set Vref, RX VrefLevel [Byte0]: 53
2751 00:43:23.134504 [Byte1]: 53
2752 00:43:23.139178
2753 00:43:23.139298 Set Vref, RX VrefLevel [Byte0]: 54
2754 00:43:23.142265 [Byte1]: 54
2755 00:43:23.146595
2756 00:43:23.146708 Set Vref, RX VrefLevel [Byte0]: 55
2757 00:43:23.149753 [Byte1]: 55
2758 00:43:23.154525
2759 00:43:23.154654 Set Vref, RX VrefLevel [Byte0]: 56
2760 00:43:23.157767 [Byte1]: 56
2761 00:43:23.162284
2762 00:43:23.162392 Set Vref, RX VrefLevel [Byte0]: 57
2763 00:43:23.165580 [Byte1]: 57
2764 00:43:23.170973
2765 00:43:23.171082 Set Vref, RX VrefLevel [Byte0]: 58
2766 00:43:23.173853 [Byte1]: 58
2767 00:43:23.178367
2768 00:43:23.178478 Set Vref, RX VrefLevel [Byte0]: 59
2769 00:43:23.181721 [Byte1]: 59
2770 00:43:23.186077
2771 00:43:23.186185 Set Vref, RX VrefLevel [Byte0]: 60
2772 00:43:23.189407 [Byte1]: 60
2773 00:43:23.194191
2774 00:43:23.194326 Set Vref, RX VrefLevel [Byte0]: 61
2775 00:43:23.197295 [Byte1]: 61
2776 00:43:23.202050
2777 00:43:23.202167 Set Vref, RX VrefLevel [Byte0]: 62
2778 00:43:23.205283 [Byte1]: 62
2779 00:43:23.210113
2780 00:43:23.210245 Set Vref, RX VrefLevel [Byte0]: 63
2781 00:43:23.213420 [Byte1]: 63
2782 00:43:23.217379
2783 00:43:23.217481 Set Vref, RX VrefLevel [Byte0]: 64
2784 00:43:23.220871 [Byte1]: 64
2785 00:43:23.225542
2786 00:43:23.225714 Set Vref, RX VrefLevel [Byte0]: 65
2787 00:43:23.228703 [Byte1]: 65
2788 00:43:23.233496
2789 00:43:23.233633 Set Vref, RX VrefLevel [Byte0]: 66
2790 00:43:23.237096 [Byte1]: 66
2791 00:43:23.241354
2792 00:43:23.241460 Set Vref, RX VrefLevel [Byte0]: 67
2793 00:43:23.244527 [Byte1]: 67
2794 00:43:23.249122
2795 00:43:23.249223 Set Vref, RX VrefLevel [Byte0]: 68
2796 00:43:23.252681 [Byte1]: 68
2797 00:43:23.257486
2798 00:43:23.257611 Set Vref, RX VrefLevel [Byte0]: 69
2799 00:43:23.260959 [Byte1]: 69
2800 00:43:23.264811
2801 00:43:23.264921 Final RX Vref Byte 0 = 56 to rank0
2802 00:43:23.268116 Final RX Vref Byte 1 = 47 to rank0
2803 00:43:23.271510 Final RX Vref Byte 0 = 56 to rank1
2804 00:43:23.274915 Final RX Vref Byte 1 = 47 to rank1==
2805 00:43:23.278153 Dram Type= 6, Freq= 0, CH_0, rank 0
2806 00:43:23.284827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2807 00:43:23.284953 ==
2808 00:43:23.285023 DQS Delay:
2809 00:43:23.285094 DQS0 = 0, DQS1 = 0
2810 00:43:23.288582 DQM Delay:
2811 00:43:23.288670 DQM0 = 121, DQM1 = 110
2812 00:43:23.291987 DQ Delay:
2813 00:43:23.294871 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =120
2814 00:43:23.298111 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2815 00:43:23.301695 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =104
2816 00:43:23.305000 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2817 00:43:23.305100
2818 00:43:23.305166
2819 00:43:23.311930 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2820 00:43:23.315371 CH0 RK0: MR19=404, MR18=140D
2821 00:43:23.322040 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2822 00:43:23.322157
2823 00:43:23.325321 ----->DramcWriteLeveling(PI) begin...
2824 00:43:23.325443 ==
2825 00:43:23.328946 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 00:43:23.331939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 00:43:23.332035 ==
2828 00:43:23.335006 Write leveling (Byte 0): 33 => 33
2829 00:43:23.338889 Write leveling (Byte 1): 30 => 30
2830 00:43:23.342189 DramcWriteLeveling(PI) end<-----
2831 00:43:23.342277
2832 00:43:23.342341 ==
2833 00:43:23.345470 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 00:43:23.349087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 00:43:23.352101 ==
2836 00:43:23.352186 [Gating] SW mode calibration
2837 00:43:23.361984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2838 00:43:23.365098 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2839 00:43:23.368717 0 15 0 | B1->B0 | 3333 3131 | 0 1 | (0 0) (1 1)
2840 00:43:23.375005 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 00:43:23.378340 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 00:43:23.382180 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 00:43:23.388452 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 00:43:23.391811 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 00:43:23.395341 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 00:43:23.402320 0 15 28 | B1->B0 | 2e2e 3131 | 0 0 | (1 0) (0 1)
2847 00:43:23.405872 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2848 00:43:23.408578 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 00:43:23.411957 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 00:43:23.419188 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 00:43:23.422386 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 00:43:23.425584 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 00:43:23.432720 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 00:43:23.436050 1 0 28 | B1->B0 | 3d3d 3b3b | 1 0 | (0 0) (0 0)
2855 00:43:23.439188 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2856 00:43:23.445568 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 00:43:23.449086 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 00:43:23.452434 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 00:43:23.459440 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 00:43:23.462479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 00:43:23.465739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 00:43:23.472284 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2863 00:43:23.475532 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:43:23.478731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 00:43:23.485617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 00:43:23.488751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 00:43:23.492104 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 00:43:23.495926 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 00:43:23.502618 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 00:43:23.505774 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 00:43:23.508984 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 00:43:23.515654 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 00:43:23.518910 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 00:43:23.522349 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 00:43:23.528957 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 00:43:23.532173 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 00:43:23.535475 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 00:43:23.542406 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2879 00:43:23.545772 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2880 00:43:23.549435 Total UI for P1: 0, mck2ui 16
2881 00:43:23.552361 best dqsien dly found for B1: ( 1, 3, 28)
2882 00:43:23.555583 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 00:43:23.559070 Total UI for P1: 0, mck2ui 16
2884 00:43:23.562362 best dqsien dly found for B0: ( 1, 4, 0)
2885 00:43:23.565740 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2886 00:43:23.569214 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2887 00:43:23.569318
2888 00:43:23.572437 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2889 00:43:23.578927 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2890 00:43:23.579056 [Gating] SW calibration Done
2891 00:43:23.579127 ==
2892 00:43:23.582330 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 00:43:23.589101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 00:43:23.589231 ==
2895 00:43:23.589299 RX Vref Scan: 0
2896 00:43:23.589360
2897 00:43:23.592540 RX Vref 0 -> 0, step: 1
2898 00:43:23.592633
2899 00:43:23.595764 RX Delay -40 -> 252, step: 8
2900 00:43:23.598974 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2901 00:43:23.602357 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2902 00:43:23.605732 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2903 00:43:23.608949 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2904 00:43:23.616110 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2905 00:43:23.619674 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2906 00:43:23.622901 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2907 00:43:23.626222 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2908 00:43:23.629464 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2909 00:43:23.636029 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2910 00:43:23.639330 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2911 00:43:23.642456 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2912 00:43:23.646060 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2913 00:43:23.649452 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2914 00:43:23.656070 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2915 00:43:23.659193 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2916 00:43:23.659302 ==
2917 00:43:23.662399 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 00:43:23.666131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 00:43:23.666237 ==
2920 00:43:23.666304 DQS Delay:
2921 00:43:23.669466 DQS0 = 0, DQS1 = 0
2922 00:43:23.669559 DQM Delay:
2923 00:43:23.672876 DQM0 = 122, DQM1 = 112
2924 00:43:23.672979 DQ Delay:
2925 00:43:23.676144 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2926 00:43:23.679282 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2927 00:43:23.682879 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2928 00:43:23.686170 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2929 00:43:23.689510
2930 00:43:23.689648
2931 00:43:23.689752 ==
2932 00:43:23.692959 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 00:43:23.696141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 00:43:23.696240 ==
2935 00:43:23.696308
2936 00:43:23.696381
2937 00:43:23.699435 TX Vref Scan disable
2938 00:43:23.699548 == TX Byte 0 ==
2939 00:43:23.706005 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2940 00:43:23.709942 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2941 00:43:23.710066 == TX Byte 1 ==
2942 00:43:23.716182 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2943 00:43:23.719506 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2944 00:43:23.719614 ==
2945 00:43:23.722739 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 00:43:23.725959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 00:43:23.726070 ==
2948 00:43:23.738396 TX Vref=22, minBit 1, minWin=25, winSum=415
2949 00:43:23.741727 TX Vref=24, minBit 2, minWin=25, winSum=417
2950 00:43:23.745696 TX Vref=26, minBit 3, minWin=25, winSum=423
2951 00:43:23.748985 TX Vref=28, minBit 1, minWin=26, winSum=427
2952 00:43:23.752252 TX Vref=30, minBit 7, minWin=26, winSum=431
2953 00:43:23.755509 TX Vref=32, minBit 0, minWin=26, winSum=427
2954 00:43:23.762208 [TxChooseVref] Worse bit 7, Min win 26, Win sum 431, Final Vref 30
2955 00:43:23.762343
2956 00:43:23.765428 Final TX Range 1 Vref 30
2957 00:43:23.765543
2958 00:43:23.765607 ==
2959 00:43:23.768754 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 00:43:23.771991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 00:43:23.772172 ==
2962 00:43:23.772277
2963 00:43:23.772391
2964 00:43:23.775196 TX Vref Scan disable
2965 00:43:23.779015 == TX Byte 0 ==
2966 00:43:23.782357 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2967 00:43:23.785247 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2968 00:43:23.788841 == TX Byte 1 ==
2969 00:43:23.792242 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2970 00:43:23.795650 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2971 00:43:23.795778
2972 00:43:23.798953 [DATLAT]
2973 00:43:23.799084 Freq=1200, CH0 RK1
2974 00:43:23.799178
2975 00:43:23.802358 DATLAT Default: 0xd
2976 00:43:23.802449 0, 0xFFFF, sum = 0
2977 00:43:23.805221 1, 0xFFFF, sum = 0
2978 00:43:23.805382 2, 0xFFFF, sum = 0
2979 00:43:23.808695 3, 0xFFFF, sum = 0
2980 00:43:23.808790 4, 0xFFFF, sum = 0
2981 00:43:23.812322 5, 0xFFFF, sum = 0
2982 00:43:23.812479 6, 0xFFFF, sum = 0
2983 00:43:23.815615 7, 0xFFFF, sum = 0
2984 00:43:23.815766 8, 0xFFFF, sum = 0
2985 00:43:23.818919 9, 0xFFFF, sum = 0
2986 00:43:23.819058 10, 0xFFFF, sum = 0
2987 00:43:23.822310 11, 0xFFFF, sum = 0
2988 00:43:23.822429 12, 0x0, sum = 1
2989 00:43:23.826331 13, 0x0, sum = 2
2990 00:43:23.826455 14, 0x0, sum = 3
2991 00:43:23.829002 15, 0x0, sum = 4
2992 00:43:23.829129 best_step = 13
2993 00:43:23.829223
2994 00:43:23.829314 ==
2995 00:43:23.832772 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 00:43:23.838725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 00:43:23.838881 ==
2998 00:43:23.838951 RX Vref Scan: 0
2999 00:43:23.839013
3000 00:43:23.842383 RX Vref 0 -> 0, step: 1
3001 00:43:23.842502
3002 00:43:23.846007 RX Delay -13 -> 252, step: 4
3003 00:43:23.848828 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3004 00:43:23.852060 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3005 00:43:23.858845 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3006 00:43:23.862055 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3007 00:43:23.865419 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3008 00:43:23.868786 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3009 00:43:23.872010 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3010 00:43:23.879182 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3011 00:43:23.882458 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3012 00:43:23.885794 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3013 00:43:23.888807 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3014 00:43:23.892015 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3015 00:43:23.898668 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3016 00:43:23.902412 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3017 00:43:23.905784 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3018 00:43:23.909021 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3019 00:43:23.909149 ==
3020 00:43:23.912362 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 00:43:23.915579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 00:43:23.918681 ==
3023 00:43:23.918829 DQS Delay:
3024 00:43:23.918925 DQS0 = 0, DQS1 = 0
3025 00:43:23.922286 DQM Delay:
3026 00:43:23.922385 DQM0 = 121, DQM1 = 109
3027 00:43:23.925788 DQ Delay:
3028 00:43:23.929210 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3029 00:43:23.932285 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3030 00:43:23.935757 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3031 00:43:23.938745 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3032 00:43:23.938858
3033 00:43:23.938924
3034 00:43:23.945785 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3035 00:43:23.948750 CH0 RK1: MR19=403, MR18=11F3
3036 00:43:23.955542 CH0_RK1: MR19=0x403, MR18=0x11F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3037 00:43:23.959090 [RxdqsGatingPostProcess] freq 1200
3038 00:43:23.965724 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3039 00:43:23.968941 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 00:43:23.969073 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 00:43:23.972710 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 00:43:23.976026 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 00:43:23.979321 best DQS0 dly(2T, 0.5T) = (0, 12)
3044 00:43:23.982595 best DQS1 dly(2T, 0.5T) = (0, 11)
3045 00:43:23.986060 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3046 00:43:23.989539 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3047 00:43:23.992547 Pre-setting of DQS Precalculation
3048 00:43:23.995527 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3049 00:43:23.998919 ==
3050 00:43:24.002181 Dram Type= 6, Freq= 0, CH_1, rank 0
3051 00:43:24.006038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 00:43:24.006138 ==
3053 00:43:24.009206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3054 00:43:24.015809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3055 00:43:24.025207 [CA 0] Center 37 (7~68) winsize 62
3056 00:43:24.028714 [CA 1] Center 37 (7~68) winsize 62
3057 00:43:24.031320 [CA 2] Center 35 (5~65) winsize 61
3058 00:43:24.034839 [CA 3] Center 34 (4~64) winsize 61
3059 00:43:24.038117 [CA 4] Center 34 (4~64) winsize 61
3060 00:43:24.041464 [CA 5] Center 33 (3~63) winsize 61
3061 00:43:24.041679
3062 00:43:24.045291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3063 00:43:24.045424
3064 00:43:24.048281 [CATrainingPosCal] consider 1 rank data
3065 00:43:24.051985 u2DelayCellTimex100 = 270/100 ps
3066 00:43:24.054944 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3067 00:43:24.058243 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3068 00:43:24.065278 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3069 00:43:24.068478 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3070 00:43:24.071436 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3071 00:43:24.075054 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3072 00:43:24.075254
3073 00:43:24.078455 CA PerBit enable=1, Macro0, CA PI delay=33
3074 00:43:24.078634
3075 00:43:24.081633 [CBTSetCACLKResult] CA Dly = 33
3076 00:43:24.081809 CS Dly: 7 (0~38)
3077 00:43:24.081952 ==
3078 00:43:24.084971 Dram Type= 6, Freq= 0, CH_1, rank 1
3079 00:43:24.091702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 00:43:24.091871 ==
3081 00:43:24.095143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3082 00:43:24.101286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3083 00:43:24.110398 [CA 0] Center 37 (7~68) winsize 62
3084 00:43:24.113671 [CA 1] Center 37 (7~68) winsize 62
3085 00:43:24.117042 [CA 2] Center 35 (5~65) winsize 61
3086 00:43:24.120300 [CA 3] Center 34 (4~65) winsize 62
3087 00:43:24.123841 [CA 4] Center 34 (4~65) winsize 62
3088 00:43:24.127160 [CA 5] Center 34 (4~64) winsize 61
3089 00:43:24.127312
3090 00:43:24.130512 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3091 00:43:24.130646
3092 00:43:24.133881 [CATrainingPosCal] consider 2 rank data
3093 00:43:24.137330 u2DelayCellTimex100 = 270/100 ps
3094 00:43:24.140732 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 00:43:24.144089 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3096 00:43:24.147422 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3097 00:43:24.154004 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 00:43:24.157269 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3099 00:43:24.160431 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3100 00:43:24.160582
3101 00:43:24.164089 CA PerBit enable=1, Macro0, CA PI delay=33
3102 00:43:24.164232
3103 00:43:24.167435 [CBTSetCACLKResult] CA Dly = 33
3104 00:43:24.167560 CS Dly: 9 (0~42)
3105 00:43:24.167656
3106 00:43:24.170675 ----->DramcWriteLeveling(PI) begin...
3107 00:43:24.170792 ==
3108 00:43:24.173941 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 00:43:24.180895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 00:43:24.181042 ==
3111 00:43:24.184097 Write leveling (Byte 0): 24 => 24
3112 00:43:24.187471 Write leveling (Byte 1): 27 => 27
3113 00:43:24.187573 DramcWriteLeveling(PI) end<-----
3114 00:43:24.190890
3115 00:43:24.190981 ==
3116 00:43:24.193975 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 00:43:24.197184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 00:43:24.197298 ==
3119 00:43:24.201096 [Gating] SW mode calibration
3120 00:43:24.207584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3121 00:43:24.210847 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3122 00:43:24.217272 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 00:43:24.220780 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 00:43:24.224226 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 00:43:24.230914 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 00:43:24.234015 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 00:43:24.237534 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 00:43:24.244509 0 15 24 | B1->B0 | 3232 2c2c | 1 0 | (1 1) (0 0)
3129 00:43:24.247783 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3130 00:43:24.250980 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 00:43:24.257594 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 00:43:24.261104 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 00:43:24.263923 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 00:43:24.267987 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 00:43:24.274356 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 00:43:24.277470 1 0 24 | B1->B0 | 3838 4444 | 1 0 | (0 0) (0 0)
3137 00:43:24.280617 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 00:43:24.287333 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 00:43:24.290722 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 00:43:24.294458 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 00:43:24.301181 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 00:43:24.304507 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 00:43:24.307848 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 00:43:24.314765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3145 00:43:24.317702 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3146 00:43:24.320995 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:43:24.327423 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 00:43:24.330689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 00:43:24.334409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 00:43:24.340913 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 00:43:24.344422 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 00:43:24.347629 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 00:43:24.350908 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 00:43:24.357709 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 00:43:24.361154 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 00:43:24.364467 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 00:43:24.371051 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 00:43:24.374626 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 00:43:24.377832 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 00:43:24.384453 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3161 00:43:24.387957 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3162 00:43:24.390852 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 00:43:24.394995 Total UI for P1: 0, mck2ui 16
3164 00:43:24.397654 best dqsien dly found for B0: ( 1, 3, 28)
3165 00:43:24.401592 Total UI for P1: 0, mck2ui 16
3166 00:43:24.404290 best dqsien dly found for B1: ( 1, 3, 26)
3167 00:43:24.407825 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3168 00:43:24.411088 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3169 00:43:24.411242
3170 00:43:24.414479 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3171 00:43:24.421255 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3172 00:43:24.421396 [Gating] SW calibration Done
3173 00:43:24.424753 ==
3174 00:43:24.424858 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 00:43:24.431329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 00:43:24.431494 ==
3177 00:43:24.431567 RX Vref Scan: 0
3178 00:43:24.431629
3179 00:43:24.434592 RX Vref 0 -> 0, step: 1
3180 00:43:24.434716
3181 00:43:24.437636 RX Delay -40 -> 252, step: 8
3182 00:43:24.441490 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3183 00:43:24.444858 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3184 00:43:24.448009 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3185 00:43:24.454694 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3186 00:43:24.457962 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3187 00:43:24.461320 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3188 00:43:24.464537 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3189 00:43:24.467774 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3190 00:43:24.474702 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3191 00:43:24.477692 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3192 00:43:24.481274 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3193 00:43:24.484383 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3194 00:43:24.487778 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3195 00:43:24.494620 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3196 00:43:24.498012 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3197 00:43:24.501000 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3198 00:43:24.501151 ==
3199 00:43:24.504813 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 00:43:24.507884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 00:43:24.508005 ==
3202 00:43:24.511562 DQS Delay:
3203 00:43:24.511676 DQS0 = 0, DQS1 = 0
3204 00:43:24.511771 DQM Delay:
3205 00:43:24.514908 DQM0 = 119, DQM1 = 116
3206 00:43:24.515007 DQ Delay:
3207 00:43:24.518265 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3208 00:43:24.521482 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3209 00:43:24.528041 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3210 00:43:24.531224 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3211 00:43:24.531383
3212 00:43:24.531501
3213 00:43:24.531607 ==
3214 00:43:24.534587 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 00:43:24.538259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 00:43:24.538419 ==
3217 00:43:24.538515
3218 00:43:24.538593
3219 00:43:24.541392 TX Vref Scan disable
3220 00:43:24.541501 == TX Byte 0 ==
3221 00:43:24.547998 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3222 00:43:24.551274 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3223 00:43:24.551396 == TX Byte 1 ==
3224 00:43:24.557836 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3225 00:43:24.561687 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3226 00:43:24.561824 ==
3227 00:43:24.564937 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 00:43:24.568172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 00:43:24.568330 ==
3230 00:43:24.581094 TX Vref=22, minBit 11, minWin=24, winSum=409
3231 00:43:24.584324 TX Vref=24, minBit 9, minWin=25, winSum=417
3232 00:43:24.587894 TX Vref=26, minBit 9, minWin=25, winSum=420
3233 00:43:24.591034 TX Vref=28, minBit 9, minWin=25, winSum=429
3234 00:43:24.594782 TX Vref=30, minBit 2, minWin=26, winSum=425
3235 00:43:24.598054 TX Vref=32, minBit 11, minWin=25, winSum=427
3236 00:43:24.604718 [TxChooseVref] Worse bit 2, Min win 26, Win sum 425, Final Vref 30
3237 00:43:24.604884
3238 00:43:24.607743 Final TX Range 1 Vref 30
3239 00:43:24.607874
3240 00:43:24.607971 ==
3241 00:43:24.611222 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 00:43:24.614520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 00:43:24.614665 ==
3244 00:43:24.614740
3245 00:43:24.618243
3246 00:43:24.618359 TX Vref Scan disable
3247 00:43:24.621170 == TX Byte 0 ==
3248 00:43:24.624725 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3249 00:43:24.627892 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3250 00:43:24.630924 == TX Byte 1 ==
3251 00:43:24.634416 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3252 00:43:24.637633 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3253 00:43:24.637796
3254 00:43:24.641295 [DATLAT]
3255 00:43:24.641431 Freq=1200, CH1 RK0
3256 00:43:24.641502
3257 00:43:24.644465 DATLAT Default: 0xd
3258 00:43:24.644579 0, 0xFFFF, sum = 0
3259 00:43:24.648141 1, 0xFFFF, sum = 0
3260 00:43:24.648291 2, 0xFFFF, sum = 0
3261 00:43:24.650921 3, 0xFFFF, sum = 0
3262 00:43:24.651031 4, 0xFFFF, sum = 0
3263 00:43:24.654634 5, 0xFFFF, sum = 0
3264 00:43:24.654764 6, 0xFFFF, sum = 0
3265 00:43:24.657844 7, 0xFFFF, sum = 0
3266 00:43:24.657965 8, 0xFFFF, sum = 0
3267 00:43:24.661210 9, 0xFFFF, sum = 0
3268 00:43:24.661329 10, 0xFFFF, sum = 0
3269 00:43:24.665023 11, 0xFFFF, sum = 0
3270 00:43:24.665149 12, 0x0, sum = 1
3271 00:43:24.667695 13, 0x0, sum = 2
3272 00:43:24.667803 14, 0x0, sum = 3
3273 00:43:24.671459 15, 0x0, sum = 4
3274 00:43:24.671584 best_step = 13
3275 00:43:24.671651
3276 00:43:24.671711 ==
3277 00:43:24.674644 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 00:43:24.681268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 00:43:24.681413 ==
3280 00:43:24.681487 RX Vref Scan: 1
3281 00:43:24.681548
3282 00:43:24.684529 Set Vref Range= 32 -> 127
3283 00:43:24.684644
3284 00:43:24.687813 RX Vref 32 -> 127, step: 1
3285 00:43:24.687937
3286 00:43:24.691293 RX Delay -5 -> 252, step: 4
3287 00:43:24.691409
3288 00:43:24.694865 Set Vref, RX VrefLevel [Byte0]: 32
3289 00:43:24.694990 [Byte1]: 32
3290 00:43:24.699638
3291 00:43:24.699776 Set Vref, RX VrefLevel [Byte0]: 33
3292 00:43:24.702818 [Byte1]: 33
3293 00:43:24.707184
3294 00:43:24.707354 Set Vref, RX VrefLevel [Byte0]: 34
3295 00:43:24.710092 [Byte1]: 34
3296 00:43:24.714740
3297 00:43:24.714914 Set Vref, RX VrefLevel [Byte0]: 35
3298 00:43:24.718034 [Byte1]: 35
3299 00:43:24.723154
3300 00:43:24.723326 Set Vref, RX VrefLevel [Byte0]: 36
3301 00:43:24.726456 [Byte1]: 36
3302 00:43:24.730440
3303 00:43:24.730597 Set Vref, RX VrefLevel [Byte0]: 37
3304 00:43:24.733698 [Byte1]: 37
3305 00:43:24.738746
3306 00:43:24.738903 Set Vref, RX VrefLevel [Byte0]: 38
3307 00:43:24.741818 [Byte1]: 38
3308 00:43:24.746371
3309 00:43:24.746536 Set Vref, RX VrefLevel [Byte0]: 39
3310 00:43:24.749627 [Byte1]: 39
3311 00:43:24.754075
3312 00:43:24.754235 Set Vref, RX VrefLevel [Byte0]: 40
3313 00:43:24.757335 [Byte1]: 40
3314 00:43:24.761750
3315 00:43:24.761904 Set Vref, RX VrefLevel [Byte0]: 41
3316 00:43:24.765493 [Byte1]: 41
3317 00:43:24.769679
3318 00:43:24.769834 Set Vref, RX VrefLevel [Byte0]: 42
3319 00:43:24.773442 [Byte1]: 42
3320 00:43:24.777917
3321 00:43:24.778068 Set Vref, RX VrefLevel [Byte0]: 43
3322 00:43:24.781308 [Byte1]: 43
3323 00:43:24.785626
3324 00:43:24.785796 Set Vref, RX VrefLevel [Byte0]: 44
3325 00:43:24.788666 [Byte1]: 44
3326 00:43:24.793080
3327 00:43:24.793240 Set Vref, RX VrefLevel [Byte0]: 45
3328 00:43:24.797020 [Byte1]: 45
3329 00:43:24.800980
3330 00:43:24.801116 Set Vref, RX VrefLevel [Byte0]: 46
3331 00:43:24.804313 [Byte1]: 46
3332 00:43:24.808965
3333 00:43:24.809123 Set Vref, RX VrefLevel [Byte0]: 47
3334 00:43:24.812349 [Byte1]: 47
3335 00:43:24.817053
3336 00:43:24.817223 Set Vref, RX VrefLevel [Byte0]: 48
3337 00:43:24.820400 [Byte1]: 48
3338 00:43:24.825133
3339 00:43:24.825288 Set Vref, RX VrefLevel [Byte0]: 49
3340 00:43:24.828527 [Byte1]: 49
3341 00:43:24.833039
3342 00:43:24.833190 Set Vref, RX VrefLevel [Byte0]: 50
3343 00:43:24.835642 [Byte1]: 50
3344 00:43:24.840438
3345 00:43:24.840562 Set Vref, RX VrefLevel [Byte0]: 51
3346 00:43:24.843753 [Byte1]: 51
3347 00:43:24.848576
3348 00:43:24.848764 Set Vref, RX VrefLevel [Byte0]: 52
3349 00:43:24.851643 [Byte1]: 52
3350 00:43:24.856186
3351 00:43:24.856356 Set Vref, RX VrefLevel [Byte0]: 53
3352 00:43:24.859614 [Byte1]: 53
3353 00:43:24.864317
3354 00:43:24.864530 Set Vref, RX VrefLevel [Byte0]: 54
3355 00:43:24.867724 [Byte1]: 54
3356 00:43:24.872300
3357 00:43:24.872463 Set Vref, RX VrefLevel [Byte0]: 55
3358 00:43:24.875066 [Byte1]: 55
3359 00:43:24.879880
3360 00:43:24.880044 Set Vref, RX VrefLevel [Byte0]: 56
3361 00:43:24.882837 [Byte1]: 56
3362 00:43:24.887312
3363 00:43:24.887448 Set Vref, RX VrefLevel [Byte0]: 57
3364 00:43:24.890623 [Byte1]: 57
3365 00:43:24.895464
3366 00:43:24.895598 Set Vref, RX VrefLevel [Byte0]: 58
3367 00:43:24.898998 [Byte1]: 58
3368 00:43:24.903465
3369 00:43:24.903601 Set Vref, RX VrefLevel [Byte0]: 59
3370 00:43:24.906521 [Byte1]: 59
3371 00:43:24.911125
3372 00:43:24.911361 Set Vref, RX VrefLevel [Byte0]: 60
3373 00:43:24.914589 [Byte1]: 60
3374 00:43:24.918842
3375 00:43:24.919000 Set Vref, RX VrefLevel [Byte0]: 61
3376 00:43:24.922347 [Byte1]: 61
3377 00:43:24.927089
3378 00:43:24.927256 Set Vref, RX VrefLevel [Byte0]: 62
3379 00:43:24.929983 [Byte1]: 62
3380 00:43:24.934663
3381 00:43:24.934830 Set Vref, RX VrefLevel [Byte0]: 63
3382 00:43:24.938136 [Byte1]: 63
3383 00:43:24.942807
3384 00:43:24.942960 Set Vref, RX VrefLevel [Byte0]: 64
3385 00:43:24.946023 [Byte1]: 64
3386 00:43:24.950778
3387 00:43:24.950925 Set Vref, RX VrefLevel [Byte0]: 65
3388 00:43:24.954244 [Byte1]: 65
3389 00:43:24.958249
3390 00:43:24.958389 Set Vref, RX VrefLevel [Byte0]: 66
3391 00:43:24.961617 [Byte1]: 66
3392 00:43:24.965993
3393 00:43:24.966143 Set Vref, RX VrefLevel [Byte0]: 67
3394 00:43:24.969640 [Byte1]: 67
3395 00:43:24.974333
3396 00:43:24.974454 Set Vref, RX VrefLevel [Byte0]: 68
3397 00:43:24.977460 [Byte1]: 68
3398 00:43:24.982187
3399 00:43:24.982309 Final RX Vref Byte 0 = 52 to rank0
3400 00:43:24.985434 Final RX Vref Byte 1 = 54 to rank0
3401 00:43:24.988469 Final RX Vref Byte 0 = 52 to rank1
3402 00:43:24.991698 Final RX Vref Byte 1 = 54 to rank1==
3403 00:43:24.995345 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 00:43:25.001692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 00:43:25.001810 ==
3406 00:43:25.001878 DQS Delay:
3407 00:43:25.001939 DQS0 = 0, DQS1 = 0
3408 00:43:25.004879 DQM Delay:
3409 00:43:25.004992 DQM0 = 120, DQM1 = 117
3410 00:43:25.008271 DQ Delay:
3411 00:43:25.011737 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3412 00:43:25.015125 DQ4 =120, DQ5 =130, DQ6 =130, DQ7 =120
3413 00:43:25.018559 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3414 00:43:25.022125 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3415 00:43:25.022224
3416 00:43:25.022291
3417 00:43:25.028346 [DQSOSCAuto] RK0, (LSB)MR18= 0x12, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3418 00:43:25.032011 CH1 RK0: MR19=404, MR18=12
3419 00:43:25.038922 CH1_RK0: MR19=0x404, MR18=0x12, DQSOSC=403, MR23=63, INC=40, DEC=26
3420 00:43:25.039061
3421 00:43:25.041778 ----->DramcWriteLeveling(PI) begin...
3422 00:43:25.041901 ==
3423 00:43:25.045203 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 00:43:25.048907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 00:43:25.049034 ==
3426 00:43:25.052293 Write leveling (Byte 0): 24 => 24
3427 00:43:25.055504 Write leveling (Byte 1): 29 => 29
3428 00:43:25.058834 DramcWriteLeveling(PI) end<-----
3429 00:43:25.058954
3430 00:43:25.059049 ==
3431 00:43:25.062467 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 00:43:25.065625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 00:43:25.065743 ==
3434 00:43:25.068771 [Gating] SW mode calibration
3435 00:43:25.075584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 00:43:25.081990 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 00:43:25.085472 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3438 00:43:25.091988 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 00:43:25.095329 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 00:43:25.098591 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 00:43:25.102177 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 00:43:25.108883 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3443 00:43:25.112533 0 15 24 | B1->B0 | 2424 3232 | 0 1 | (1 0) (1 0)
3444 00:43:25.115898 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3445 00:43:25.122612 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 00:43:25.125855 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 00:43:25.129105 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 00:43:25.135659 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 00:43:25.138969 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 00:43:25.142048 1 0 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3451 00:43:25.149260 1 0 24 | B1->B0 | 4040 2828 | 0 0 | (0 0) (0 0)
3452 00:43:25.152134 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 00:43:25.155910 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 00:43:25.162646 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 00:43:25.165722 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 00:43:25.168854 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 00:43:25.176081 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 00:43:25.178717 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3459 00:43:25.182043 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3460 00:43:25.189464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3461 00:43:25.192127 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 00:43:25.195499 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 00:43:25.198760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:43:25.205438 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:43:25.208822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:43:25.212090 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:43:25.218876 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 00:43:25.221668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 00:43:25.225086 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 00:43:25.232044 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 00:43:25.235315 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:43:25.238712 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:43:25.245394 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:43:25.248714 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3475 00:43:25.251479 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 00:43:25.258035 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3477 00:43:25.261779 Total UI for P1: 0, mck2ui 16
3478 00:43:25.264986 best dqsien dly found for B1: ( 1, 3, 22)
3479 00:43:25.268169 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 00:43:25.271370 Total UI for P1: 0, mck2ui 16
3481 00:43:25.274890 best dqsien dly found for B0: ( 1, 3, 26)
3482 00:43:25.278499 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 00:43:25.281208 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3484 00:43:25.281295
3485 00:43:25.284727 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 00:43:25.288002 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3487 00:43:25.291963 [Gating] SW calibration Done
3488 00:43:25.292060 ==
3489 00:43:25.294753 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 00:43:25.301785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 00:43:25.301925 ==
3492 00:43:25.302027 RX Vref Scan: 0
3493 00:43:25.302116
3494 00:43:25.304959 RX Vref 0 -> 0, step: 1
3495 00:43:25.305040
3496 00:43:25.308280 RX Delay -40 -> 252, step: 8
3497 00:43:25.311743 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3498 00:43:25.315060 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3499 00:43:25.317863 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3500 00:43:25.321278 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3501 00:43:25.327907 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3502 00:43:25.331867 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 00:43:25.334606 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3504 00:43:25.338130 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3505 00:43:25.341523 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3506 00:43:25.348085 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3507 00:43:25.351610 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3508 00:43:25.354818 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3509 00:43:25.357671 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3510 00:43:25.361126 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3511 00:43:25.367756 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3512 00:43:25.371047 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3513 00:43:25.371169 ==
3514 00:43:25.374317 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 00:43:25.377744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 00:43:25.377833 ==
3517 00:43:25.381526 DQS Delay:
3518 00:43:25.381625 DQS0 = 0, DQS1 = 0
3519 00:43:25.381695 DQM Delay:
3520 00:43:25.384677 DQM0 = 121, DQM1 = 118
3521 00:43:25.384764 DQ Delay:
3522 00:43:25.387714 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3523 00:43:25.391405 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3524 00:43:25.398089 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3525 00:43:25.401654 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3526 00:43:25.401750
3527 00:43:25.401829
3528 00:43:25.401891 ==
3529 00:43:25.404124 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 00:43:25.407941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 00:43:25.408068 ==
3532 00:43:25.408163
3533 00:43:25.408254
3534 00:43:25.411209 TX Vref Scan disable
3535 00:43:25.411297 == TX Byte 0 ==
3536 00:43:25.417553 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3537 00:43:25.421014 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3538 00:43:25.424276 == TX Byte 1 ==
3539 00:43:25.427591 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3540 00:43:25.431060 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3541 00:43:25.431150 ==
3542 00:43:25.434610 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 00:43:25.437655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 00:43:25.437752 ==
3545 00:43:25.451061 TX Vref=22, minBit 9, minWin=25, winSum=420
3546 00:43:25.454720 TX Vref=24, minBit 1, minWin=26, winSum=426
3547 00:43:25.457440 TX Vref=26, minBit 2, minWin=26, winSum=433
3548 00:43:25.461023 TX Vref=28, minBit 2, minWin=26, winSum=432
3549 00:43:25.464258 TX Vref=30, minBit 9, minWin=26, winSum=433
3550 00:43:25.467506 TX Vref=32, minBit 9, minWin=26, winSum=434
3551 00:43:25.474299 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3552 00:43:25.474428
3553 00:43:25.477423 Final TX Range 1 Vref 32
3554 00:43:25.477543
3555 00:43:25.477637 ==
3556 00:43:25.480841 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 00:43:25.484423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 00:43:25.484525 ==
3559 00:43:25.484592
3560 00:43:25.487628
3561 00:43:25.487716 TX Vref Scan disable
3562 00:43:25.490980 == TX Byte 0 ==
3563 00:43:25.494368 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3564 00:43:25.497467 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3565 00:43:25.500837 == TX Byte 1 ==
3566 00:43:25.504166 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3567 00:43:25.507454 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3568 00:43:25.510913
3569 00:43:25.511057 [DATLAT]
3570 00:43:25.511140 Freq=1200, CH1 RK1
3571 00:43:25.511202
3572 00:43:25.514253 DATLAT Default: 0xd
3573 00:43:25.514390 0, 0xFFFF, sum = 0
3574 00:43:25.517729 1, 0xFFFF, sum = 0
3575 00:43:25.517852 2, 0xFFFF, sum = 0
3576 00:43:25.520424 3, 0xFFFF, sum = 0
3577 00:43:25.520544 4, 0xFFFF, sum = 0
3578 00:43:25.523837 5, 0xFFFF, sum = 0
3579 00:43:25.527671 6, 0xFFFF, sum = 0
3580 00:43:25.527782 7, 0xFFFF, sum = 0
3581 00:43:25.531114 8, 0xFFFF, sum = 0
3582 00:43:25.531213 9, 0xFFFF, sum = 0
3583 00:43:25.534062 10, 0xFFFF, sum = 0
3584 00:43:25.534157 11, 0xFFFF, sum = 0
3585 00:43:25.537579 12, 0x0, sum = 1
3586 00:43:25.537706 13, 0x0, sum = 2
3587 00:43:25.540528 14, 0x0, sum = 3
3588 00:43:25.540640 15, 0x0, sum = 4
3589 00:43:25.540706 best_step = 13
3590 00:43:25.544082
3591 00:43:25.544207 ==
3592 00:43:25.546965 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 00:43:25.550288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 00:43:25.550398 ==
3595 00:43:25.550467 RX Vref Scan: 0
3596 00:43:25.550527
3597 00:43:25.553628 RX Vref 0 -> 0, step: 1
3598 00:43:25.553716
3599 00:43:25.557740 RX Delay -5 -> 252, step: 4
3600 00:43:25.560492 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3601 00:43:25.567786 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3602 00:43:25.570490 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3603 00:43:25.573543 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3604 00:43:25.576914 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3605 00:43:25.580287 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3606 00:43:25.587040 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3607 00:43:25.590411 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3608 00:43:25.593720 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3609 00:43:25.597161 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3610 00:43:25.600418 iDelay=195, Bit 10, Center 120 (59 ~ 182) 124
3611 00:43:25.606961 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3612 00:43:25.610314 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3613 00:43:25.613768 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3614 00:43:25.616714 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3615 00:43:25.620222 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3616 00:43:25.623529 ==
3617 00:43:25.623630 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 00:43:25.630205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 00:43:25.630325 ==
3620 00:43:25.630396 DQS Delay:
3621 00:43:25.633650 DQS0 = 0, DQS1 = 0
3622 00:43:25.633749 DQM Delay:
3623 00:43:25.637020 DQM0 = 120, DQM1 = 118
3624 00:43:25.637138 DQ Delay:
3625 00:43:25.640310 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3626 00:43:25.643498 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3627 00:43:25.646872 DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112
3628 00:43:25.650334 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3629 00:43:25.650440
3630 00:43:25.650510
3631 00:43:25.660537 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3632 00:43:25.663539 CH1 RK1: MR19=403, MR18=12EF
3633 00:43:25.666814 CH1_RK1: MR19=0x403, MR18=0x12EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3634 00:43:25.670070 [RxdqsGatingPostProcess] freq 1200
3635 00:43:25.677002 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 00:43:25.679857 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 00:43:25.683471 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 00:43:25.686659 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 00:43:25.689786 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 00:43:25.693023 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 00:43:25.696456 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 00:43:25.699780 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 00:43:25.703181 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 00:43:25.703289 Pre-setting of DQS Precalculation
3645 00:43:25.710122 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 00:43:25.716194 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 00:43:25.723261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 00:43:25.723421
3649 00:43:25.723519
3650 00:43:25.726410 [Calibration Summary] 2400 Mbps
3651 00:43:25.729397 CH 0, Rank 0
3652 00:43:25.729537 SW Impedance : PASS
3653 00:43:25.733396 DUTY Scan : NO K
3654 00:43:25.736663 ZQ Calibration : PASS
3655 00:43:25.736771 Jitter Meter : NO K
3656 00:43:25.739963 CBT Training : PASS
3657 00:43:25.743292 Write leveling : PASS
3658 00:43:25.743399 RX DQS gating : PASS
3659 00:43:25.746567 RX DQ/DQS(RDDQC) : PASS
3660 00:43:25.749721 TX DQ/DQS : PASS
3661 00:43:25.749847 RX DATLAT : PASS
3662 00:43:25.753170 RX DQ/DQS(Engine): PASS
3663 00:43:25.753313 TX OE : NO K
3664 00:43:25.756498 All Pass.
3665 00:43:25.756613
3666 00:43:25.756711 CH 0, Rank 1
3667 00:43:25.759852 SW Impedance : PASS
3668 00:43:25.759952 DUTY Scan : NO K
3669 00:43:25.763037 ZQ Calibration : PASS
3670 00:43:25.766203 Jitter Meter : NO K
3671 00:43:25.766352 CBT Training : PASS
3672 00:43:25.769404 Write leveling : PASS
3673 00:43:25.773058 RX DQS gating : PASS
3674 00:43:25.773222 RX DQ/DQS(RDDQC) : PASS
3675 00:43:25.776045 TX DQ/DQS : PASS
3676 00:43:25.779344 RX DATLAT : PASS
3677 00:43:25.779498 RX DQ/DQS(Engine): PASS
3678 00:43:25.782599 TX OE : NO K
3679 00:43:25.782742 All Pass.
3680 00:43:25.782843
3681 00:43:25.786015 CH 1, Rank 0
3682 00:43:25.786160 SW Impedance : PASS
3683 00:43:25.789317 DUTY Scan : NO K
3684 00:43:25.793060 ZQ Calibration : PASS
3685 00:43:25.793257 Jitter Meter : NO K
3686 00:43:25.796194 CBT Training : PASS
3687 00:43:25.799684 Write leveling : PASS
3688 00:43:25.799887 RX DQS gating : PASS
3689 00:43:25.802831 RX DQ/DQS(RDDQC) : PASS
3690 00:43:25.806262 TX DQ/DQS : PASS
3691 00:43:25.806468 RX DATLAT : PASS
3692 00:43:25.809568 RX DQ/DQS(Engine): PASS
3693 00:43:25.809767 TX OE : NO K
3694 00:43:25.812871 All Pass.
3695 00:43:25.813064
3696 00:43:25.813207 CH 1, Rank 1
3697 00:43:25.816065 SW Impedance : PASS
3698 00:43:25.816230 DUTY Scan : NO K
3699 00:43:25.819390 ZQ Calibration : PASS
3700 00:43:25.822843 Jitter Meter : NO K
3701 00:43:25.823013 CBT Training : PASS
3702 00:43:25.825822 Write leveling : PASS
3703 00:43:25.829088 RX DQS gating : PASS
3704 00:43:25.829195 RX DQ/DQS(RDDQC) : PASS
3705 00:43:25.832414 TX DQ/DQS : PASS
3706 00:43:25.835645 RX DATLAT : PASS
3707 00:43:25.835760 RX DQ/DQS(Engine): PASS
3708 00:43:25.839372 TX OE : NO K
3709 00:43:25.839498 All Pass.
3710 00:43:25.839574
3711 00:43:25.842752 DramC Write-DBI off
3712 00:43:25.846067 PER_BANK_REFRESH: Hybrid Mode
3713 00:43:25.846213 TX_TRACKING: ON
3714 00:43:25.855849 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 00:43:25.859421 [FAST_K] Save calibration result to emmc
3716 00:43:25.862720 dramc_set_vcore_voltage set vcore to 650000
3717 00:43:25.865934 Read voltage for 600, 5
3718 00:43:25.866053 Vio18 = 0
3719 00:43:25.866127 Vcore = 650000
3720 00:43:25.869294 Vdram = 0
3721 00:43:25.869434 Vddq = 0
3722 00:43:25.869536 Vmddr = 0
3723 00:43:25.876052 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 00:43:25.878823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 00:43:25.882372 MEM_TYPE=3, freq_sel=19
3726 00:43:25.886172 sv_algorithm_assistance_LP4_1600
3727 00:43:25.888832 ============ PULL DRAM RESETB DOWN ============
3728 00:43:25.892449 ========== PULL DRAM RESETB DOWN end =========
3729 00:43:25.898763 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 00:43:25.902156 ===================================
3731 00:43:25.905474 LPDDR4 DRAM CONFIGURATION
3732 00:43:25.905595 ===================================
3733 00:43:25.909226 EX_ROW_EN[0] = 0x0
3734 00:43:25.912040 EX_ROW_EN[1] = 0x0
3735 00:43:25.912156 LP4Y_EN = 0x0
3736 00:43:25.915435 WORK_FSP = 0x0
3737 00:43:25.915567 WL = 0x2
3738 00:43:25.919076 RL = 0x2
3739 00:43:25.919197 BL = 0x2
3740 00:43:25.922460 RPST = 0x0
3741 00:43:25.922611 RD_PRE = 0x0
3742 00:43:25.925840 WR_PRE = 0x1
3743 00:43:25.925991 WR_PST = 0x0
3744 00:43:25.928851 DBI_WR = 0x0
3745 00:43:25.928995 DBI_RD = 0x0
3746 00:43:25.932293 OTF = 0x1
3747 00:43:25.935753 ===================================
3748 00:43:25.939160 ===================================
3749 00:43:25.939296 ANA top config
3750 00:43:25.942336 ===================================
3751 00:43:25.945528 DLL_ASYNC_EN = 0
3752 00:43:25.949148 ALL_SLAVE_EN = 1
3753 00:43:25.952614 NEW_RANK_MODE = 1
3754 00:43:25.952764 DLL_IDLE_MODE = 1
3755 00:43:25.955653 LP45_APHY_COMB_EN = 1
3756 00:43:25.958856 TX_ODT_DIS = 1
3757 00:43:25.962128 NEW_8X_MODE = 1
3758 00:43:25.965754 ===================================
3759 00:43:25.968970 ===================================
3760 00:43:25.972354 data_rate = 1200
3761 00:43:25.972531 CKR = 1
3762 00:43:25.975302 DQ_P2S_RATIO = 8
3763 00:43:25.978959 ===================================
3764 00:43:25.982266 CA_P2S_RATIO = 8
3765 00:43:25.985626 DQ_CA_OPEN = 0
3766 00:43:25.988938 DQ_SEMI_OPEN = 0
3767 00:43:25.992200 CA_SEMI_OPEN = 0
3768 00:43:25.992390 CA_FULL_RATE = 0
3769 00:43:25.995487 DQ_CKDIV4_EN = 1
3770 00:43:25.998698 CA_CKDIV4_EN = 1
3771 00:43:26.001859 CA_PREDIV_EN = 0
3772 00:43:26.005324 PH8_DLY = 0
3773 00:43:26.008840 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 00:43:26.008998 DQ_AAMCK_DIV = 4
3775 00:43:26.011925 CA_AAMCK_DIV = 4
3776 00:43:26.015314 CA_ADMCK_DIV = 4
3777 00:43:26.018448 DQ_TRACK_CA_EN = 0
3778 00:43:26.021732 CA_PICK = 600
3779 00:43:26.025049 CA_MCKIO = 600
3780 00:43:26.028362 MCKIO_SEMI = 0
3781 00:43:26.028483 PLL_FREQ = 2288
3782 00:43:26.031806 DQ_UI_PI_RATIO = 32
3783 00:43:26.034810 CA_UI_PI_RATIO = 0
3784 00:43:26.038154 ===================================
3785 00:43:26.041749 ===================================
3786 00:43:26.044784 memory_type:LPDDR4
3787 00:43:26.044889 GP_NUM : 10
3788 00:43:26.048079 SRAM_EN : 1
3789 00:43:26.051846 MD32_EN : 0
3790 00:43:26.054900 ===================================
3791 00:43:26.055049 [ANA_INIT] >>>>>>>>>>>>>>
3792 00:43:26.058185 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 00:43:26.061554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 00:43:26.064915 ===================================
3795 00:43:26.068032 data_rate = 1200,PCW = 0X5800
3796 00:43:26.071986 ===================================
3797 00:43:26.075329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 00:43:26.082000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 00:43:26.085275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 00:43:26.091420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 00:43:26.094697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 00:43:26.097983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 00:43:26.098114 [ANA_INIT] flow start
3804 00:43:26.101937 [ANA_INIT] PLL >>>>>>>>
3805 00:43:26.104628 [ANA_INIT] PLL <<<<<<<<
3806 00:43:26.108125 [ANA_INIT] MIDPI >>>>>>>>
3807 00:43:26.108254 [ANA_INIT] MIDPI <<<<<<<<
3808 00:43:26.111450 [ANA_INIT] DLL >>>>>>>>
3809 00:43:26.114788 [ANA_INIT] flow end
3810 00:43:26.118595 ============ LP4 DIFF to SE enter ============
3811 00:43:26.121656 ============ LP4 DIFF to SE exit ============
3812 00:43:26.124841 [ANA_INIT] <<<<<<<<<<<<<
3813 00:43:26.128065 [Flow] Enable top DCM control >>>>>
3814 00:43:26.131290 [Flow] Enable top DCM control <<<<<
3815 00:43:26.134909 Enable DLL master slave shuffle
3816 00:43:26.137915 ==============================================================
3817 00:43:26.141359 Gating Mode config
3818 00:43:26.144704 ==============================================================
3819 00:43:26.147950 Config description:
3820 00:43:26.157590 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 00:43:26.164419 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 00:43:26.168096 SELPH_MODE 0: By rank 1: By Phase
3823 00:43:26.174362 ==============================================================
3824 00:43:26.177428 GAT_TRACK_EN = 1
3825 00:43:26.181324 RX_GATING_MODE = 2
3826 00:43:26.184718 RX_GATING_TRACK_MODE = 2
3827 00:43:26.188007 SELPH_MODE = 1
3828 00:43:26.191288 PICG_EARLY_EN = 1
3829 00:43:26.193950 VALID_LAT_VALUE = 1
3830 00:43:26.197975 ==============================================================
3831 00:43:26.201258 Enter into Gating configuration >>>>
3832 00:43:26.204571 Exit from Gating configuration <<<<
3833 00:43:26.207298 Enter into DVFS_PRE_config >>>>>
3834 00:43:26.217472 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 00:43:26.220904 Exit from DVFS_PRE_config <<<<<
3836 00:43:26.224360 Enter into PICG configuration >>>>
3837 00:43:26.227355 Exit from PICG configuration <<<<
3838 00:43:26.230779 [RX_INPUT] configuration >>>>>
3839 00:43:26.233998 [RX_INPUT] configuration <<<<<
3840 00:43:26.240728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 00:43:26.243743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 00:43:26.250622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 00:43:26.257017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 00:43:26.263743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 00:43:26.270888 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 00:43:26.273602 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 00:43:26.277151 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 00:43:26.280451 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 00:43:26.286875 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 00:43:26.290220 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 00:43:26.293571 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 00:43:26.296883 ===================================
3853 00:43:26.300245 LPDDR4 DRAM CONFIGURATION
3854 00:43:26.303495 ===================================
3855 00:43:26.303592 EX_ROW_EN[0] = 0x0
3856 00:43:26.306895 EX_ROW_EN[1] = 0x0
3857 00:43:26.310231 LP4Y_EN = 0x0
3858 00:43:26.310348 WORK_FSP = 0x0
3859 00:43:26.313705 WL = 0x2
3860 00:43:26.313820 RL = 0x2
3861 00:43:26.317128 BL = 0x2
3862 00:43:26.317236 RPST = 0x0
3863 00:43:26.320550 RD_PRE = 0x0
3864 00:43:26.320627 WR_PRE = 0x1
3865 00:43:26.324069 WR_PST = 0x0
3866 00:43:26.324157 DBI_WR = 0x0
3867 00:43:26.326756 DBI_RD = 0x0
3868 00:43:26.326861 OTF = 0x1
3869 00:43:26.330119 ===================================
3870 00:43:26.333161 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 00:43:26.339796 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 00:43:26.343210 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 00:43:26.346429 ===================================
3874 00:43:26.349705 LPDDR4 DRAM CONFIGURATION
3875 00:43:26.353181 ===================================
3876 00:43:26.353311 EX_ROW_EN[0] = 0x10
3877 00:43:26.356180 EX_ROW_EN[1] = 0x0
3878 00:43:26.359917 LP4Y_EN = 0x0
3879 00:43:26.360027 WORK_FSP = 0x0
3880 00:43:26.363123 WL = 0x2
3881 00:43:26.363228 RL = 0x2
3882 00:43:26.366384 BL = 0x2
3883 00:43:26.366493 RPST = 0x0
3884 00:43:26.369914 RD_PRE = 0x0
3885 00:43:26.370048 WR_PRE = 0x1
3886 00:43:26.373375 WR_PST = 0x0
3887 00:43:26.373520 DBI_WR = 0x0
3888 00:43:26.376265 DBI_RD = 0x0
3889 00:43:26.376390 OTF = 0x1
3890 00:43:26.379880 ===================================
3891 00:43:26.386000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 00:43:26.390544 nWR fixed to 30
3893 00:43:26.394231 [ModeRegInit_LP4] CH0 RK0
3894 00:43:26.394361 [ModeRegInit_LP4] CH0 RK1
3895 00:43:26.397410 [ModeRegInit_LP4] CH1 RK0
3896 00:43:26.400609 [ModeRegInit_LP4] CH1 RK1
3897 00:43:26.400702 match AC timing 17
3898 00:43:26.407086 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 00:43:26.410373 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 00:43:26.413934 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 00:43:26.420471 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 00:43:26.423734 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 00:43:26.423872 ==
3904 00:43:26.426932 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 00:43:26.430238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 00:43:26.430347 ==
3907 00:43:26.437343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 00:43:26.443821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3909 00:43:26.447145 [CA 0] Center 35 (5~66) winsize 62
3910 00:43:26.450376 [CA 1] Center 35 (5~66) winsize 62
3911 00:43:26.453676 [CA 2] Center 33 (3~64) winsize 62
3912 00:43:26.456956 [CA 3] Center 33 (2~64) winsize 63
3913 00:43:26.460198 [CA 4] Center 33 (2~64) winsize 63
3914 00:43:26.463526 [CA 5] Center 32 (2~63) winsize 62
3915 00:43:26.463628
3916 00:43:26.467404 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3917 00:43:26.467502
3918 00:43:26.470343 [CATrainingPosCal] consider 1 rank data
3919 00:43:26.473526 u2DelayCellTimex100 = 270/100 ps
3920 00:43:26.476956 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3921 00:43:26.480118 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3922 00:43:26.483943 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3923 00:43:26.486976 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 00:43:26.490311 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3925 00:43:26.493260 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3926 00:43:26.497257
3927 00:43:26.500462 CA PerBit enable=1, Macro0, CA PI delay=32
3928 00:43:26.500582
3929 00:43:26.503804 [CBTSetCACLKResult] CA Dly = 32
3930 00:43:26.503892 CS Dly: 4 (0~35)
3931 00:43:26.503991 ==
3932 00:43:26.507056 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 00:43:26.510188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 00:43:26.510307 ==
3935 00:43:26.516961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 00:43:26.523509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 00:43:26.527072 [CA 0] Center 35 (5~66) winsize 62
3938 00:43:26.530097 [CA 1] Center 35 (5~66) winsize 62
3939 00:43:26.533326 [CA 2] Center 34 (3~65) winsize 63
3940 00:43:26.536674 [CA 3] Center 33 (3~64) winsize 62
3941 00:43:26.539971 [CA 4] Center 32 (2~63) winsize 62
3942 00:43:26.543588 [CA 5] Center 32 (2~63) winsize 62
3943 00:43:26.543695
3944 00:43:26.546798 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 00:43:26.546916
3946 00:43:26.550033 [CATrainingPosCal] consider 2 rank data
3947 00:43:26.553380 u2DelayCellTimex100 = 270/100 ps
3948 00:43:26.556583 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 00:43:26.559770 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3950 00:43:26.563062 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 00:43:26.566895 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3952 00:43:26.573380 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3953 00:43:26.576533 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3954 00:43:26.576692
3955 00:43:26.579709 CA PerBit enable=1, Macro0, CA PI delay=32
3956 00:43:26.579830
3957 00:43:26.582817 [CBTSetCACLKResult] CA Dly = 32
3958 00:43:26.582940 CS Dly: 4 (0~36)
3959 00:43:26.583045
3960 00:43:26.586713 ----->DramcWriteLeveling(PI) begin...
3961 00:43:26.586851 ==
3962 00:43:26.589729 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 00:43:26.596694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 00:43:26.596872 ==
3965 00:43:26.599663 Write leveling (Byte 0): 35 => 35
3966 00:43:26.599789 Write leveling (Byte 1): 32 => 32
3967 00:43:26.603248 DramcWriteLeveling(PI) end<-----
3968 00:43:26.603395
3969 00:43:26.606390 ==
3970 00:43:26.606523 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 00:43:26.612984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 00:43:26.613124 ==
3973 00:43:26.616274 [Gating] SW mode calibration
3974 00:43:26.623370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 00:43:26.626609 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 00:43:26.633137 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 00:43:26.636300 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 00:43:26.639522 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 00:43:26.646719 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
3980 00:43:26.649917 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
3981 00:43:26.652949 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 00:43:26.659504 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 00:43:26.662590 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 00:43:26.666628 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 00:43:26.673032 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 00:43:26.676319 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 00:43:26.679552 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
3988 00:43:26.682841 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
3989 00:43:26.689674 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 00:43:26.693213 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 00:43:26.696207 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 00:43:26.702951 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 00:43:26.706244 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 00:43:26.709350 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 00:43:26.715799 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3996 00:43:26.719383 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 00:43:26.722660 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:43:26.729707 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:43:26.733074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:43:26.736298 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:43:26.742773 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:43:26.746003 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:43:26.749303 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:43:26.756058 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 00:43:26.759365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 00:43:26.763005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 00:43:26.769726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:43:26.772954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:43:26.776009 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:43:26.782502 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:43:26.786026 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:43:26.789386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 00:43:26.792428 Total UI for P1: 0, mck2ui 16
4014 00:43:26.796206 best dqsien dly found for B0: ( 0, 13, 14)
4015 00:43:26.799260 Total UI for P1: 0, mck2ui 16
4016 00:43:26.802597 best dqsien dly found for B1: ( 0, 13, 14)
4017 00:43:26.805897 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4018 00:43:26.809194 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4019 00:43:26.809342
4020 00:43:26.812428 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4021 00:43:26.818963 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4022 00:43:26.819121 [Gating] SW calibration Done
4023 00:43:26.819219 ==
4024 00:43:26.822676 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 00:43:26.828949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 00:43:26.829113 ==
4027 00:43:26.829224 RX Vref Scan: 0
4028 00:43:26.829306
4029 00:43:26.832530 RX Vref 0 -> 0, step: 1
4030 00:43:26.832658
4031 00:43:26.835587 RX Delay -230 -> 252, step: 16
4032 00:43:26.838851 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4033 00:43:26.842160 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 00:43:26.849302 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 00:43:26.852581 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 00:43:26.855841 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4037 00:43:26.859150 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 00:43:26.861941 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4039 00:43:26.868976 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4040 00:43:26.872158 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 00:43:26.875586 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4042 00:43:26.878892 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 00:43:26.885177 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4044 00:43:26.888969 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4045 00:43:26.891899 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4046 00:43:26.895455 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4047 00:43:26.901893 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4048 00:43:26.902027 ==
4049 00:43:26.905655 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 00:43:26.908977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 00:43:26.909080 ==
4052 00:43:26.909150 DQS Delay:
4053 00:43:26.912120 DQS0 = 0, DQS1 = 0
4054 00:43:26.912263 DQM Delay:
4055 00:43:26.915257 DQM0 = 49, DQM1 = 44
4056 00:43:26.915412 DQ Delay:
4057 00:43:26.918470 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4058 00:43:26.921768 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4059 00:43:26.925089 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4060 00:43:26.928303 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4061 00:43:26.928424
4062 00:43:26.928502
4063 00:43:26.928566 ==
4064 00:43:26.931661 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 00:43:26.934829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 00:43:26.934980 ==
4067 00:43:26.935086
4068 00:43:26.938427
4069 00:43:26.938586 TX Vref Scan disable
4070 00:43:26.941828 == TX Byte 0 ==
4071 00:43:26.945158 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4072 00:43:26.948829 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4073 00:43:26.951866 == TX Byte 1 ==
4074 00:43:26.954992 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 00:43:26.958365 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 00:43:26.958481 ==
4077 00:43:26.961613 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 00:43:26.968350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 00:43:26.968486 ==
4080 00:43:26.968557
4081 00:43:26.968618
4082 00:43:26.968692 TX Vref Scan disable
4083 00:43:26.973086 == TX Byte 0 ==
4084 00:43:26.976219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4085 00:43:26.983366 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4086 00:43:26.983496 == TX Byte 1 ==
4087 00:43:26.986197 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4088 00:43:26.992868 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4089 00:43:26.992981
4090 00:43:26.993063 [DATLAT]
4091 00:43:26.993126 Freq=600, CH0 RK0
4092 00:43:26.993185
4093 00:43:26.996187 DATLAT Default: 0x9
4094 00:43:26.996301 0, 0xFFFF, sum = 0
4095 00:43:26.999335 1, 0xFFFF, sum = 0
4096 00:43:27.002519 2, 0xFFFF, sum = 0
4097 00:43:27.002639 3, 0xFFFF, sum = 0
4098 00:43:27.006320 4, 0xFFFF, sum = 0
4099 00:43:27.006415 5, 0xFFFF, sum = 0
4100 00:43:27.009252 6, 0xFFFF, sum = 0
4101 00:43:27.009378 7, 0xFFFF, sum = 0
4102 00:43:27.012586 8, 0x0, sum = 1
4103 00:43:27.012705 9, 0x0, sum = 2
4104 00:43:27.012818 10, 0x0, sum = 3
4105 00:43:27.016117 11, 0x0, sum = 4
4106 00:43:27.016232 best_step = 9
4107 00:43:27.016324
4108 00:43:27.016425 ==
4109 00:43:27.019058 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 00:43:27.025827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 00:43:27.025994 ==
4112 00:43:27.026116 RX Vref Scan: 1
4113 00:43:27.026204
4114 00:43:27.029449 RX Vref 0 -> 0, step: 1
4115 00:43:27.029567
4116 00:43:27.032365 RX Delay -179 -> 252, step: 8
4117 00:43:27.032458
4118 00:43:27.035923 Set Vref, RX VrefLevel [Byte0]: 56
4119 00:43:27.039346 [Byte1]: 47
4120 00:43:27.039481
4121 00:43:27.042784 Final RX Vref Byte 0 = 56 to rank0
4122 00:43:27.046105 Final RX Vref Byte 1 = 47 to rank0
4123 00:43:27.049177 Final RX Vref Byte 0 = 56 to rank1
4124 00:43:27.052709 Final RX Vref Byte 1 = 47 to rank1==
4125 00:43:27.055711 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 00:43:27.058857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 00:43:27.059024 ==
4128 00:43:27.062404 DQS Delay:
4129 00:43:27.062555 DQS0 = 0, DQS1 = 0
4130 00:43:27.065430 DQM Delay:
4131 00:43:27.065554 DQM0 = 52, DQM1 = 46
4132 00:43:27.065656 DQ Delay:
4133 00:43:27.069248 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4134 00:43:27.072592 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4135 00:43:27.075774 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4136 00:43:27.078968 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4137 00:43:27.079065
4138 00:43:27.079132
4139 00:43:27.089050 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4140 00:43:27.092307 CH0 RK0: MR19=808, MR18=6E61
4141 00:43:27.095679 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4142 00:43:27.099006
4143 00:43:27.102324 ----->DramcWriteLeveling(PI) begin...
4144 00:43:27.102477 ==
4145 00:43:27.105692 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 00:43:27.108932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 00:43:27.109080 ==
4148 00:43:27.112946 Write leveling (Byte 0): 35 => 35
4149 00:43:27.115910 Write leveling (Byte 1): 31 => 31
4150 00:43:27.118983 DramcWriteLeveling(PI) end<-----
4151 00:43:27.119110
4152 00:43:27.119219 ==
4153 00:43:27.122127 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 00:43:27.126084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 00:43:27.126195 ==
4156 00:43:27.129202 [Gating] SW mode calibration
4157 00:43:27.135694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 00:43:27.139437 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 00:43:27.145818 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 00:43:27.149323 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 00:43:27.152495 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 00:43:27.158768 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 0)
4163 00:43:27.162282 0 9 16 | B1->B0 | 2f2f 2828 | 0 1 | (1 1) (1 0)
4164 00:43:27.165688 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 00:43:27.172522 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 00:43:27.175771 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 00:43:27.179196 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 00:43:27.185751 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 00:43:27.188749 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 00:43:27.192298 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4171 00:43:27.198871 0 10 16 | B1->B0 | 3f3f 4141 | 0 0 | (0 0) (0 0)
4172 00:43:27.202278 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 00:43:27.205607 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 00:43:27.212175 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 00:43:27.215577 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 00:43:27.218933 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 00:43:27.225768 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 00:43:27.228963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 00:43:27.232168 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 00:43:27.238488 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:43:27.241976 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:43:27.245031 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:43:27.252248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:43:27.255392 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:43:27.258464 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:43:27.265580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:43:27.268719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 00:43:27.272246 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 00:43:27.275630 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 00:43:27.282323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:43:27.285333 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:43:27.288589 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:43:27.295080 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:43:27.298796 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4195 00:43:27.301734 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 00:43:27.305491 Total UI for P1: 0, mck2ui 16
4197 00:43:27.308511 best dqsien dly found for B0: ( 0, 13, 12)
4198 00:43:27.311538 Total UI for P1: 0, mck2ui 16
4199 00:43:27.314760 best dqsien dly found for B1: ( 0, 13, 12)
4200 00:43:27.318697 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4201 00:43:27.325379 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4202 00:43:27.325525
4203 00:43:27.328418 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4204 00:43:27.331519 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4205 00:43:27.335234 [Gating] SW calibration Done
4206 00:43:27.335359 ==
4207 00:43:27.338360 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 00:43:27.341620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 00:43:27.341754 ==
4210 00:43:27.344843 RX Vref Scan: 0
4211 00:43:27.344957
4212 00:43:27.345054 RX Vref 0 -> 0, step: 1
4213 00:43:27.345149
4214 00:43:27.347907 RX Delay -230 -> 252, step: 16
4215 00:43:27.351162 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4216 00:43:27.357930 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4217 00:43:27.361203 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4218 00:43:27.365110 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4219 00:43:27.368257 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4220 00:43:27.374599 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4221 00:43:27.378017 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4222 00:43:27.381134 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4223 00:43:27.384787 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4224 00:43:27.387855 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4225 00:43:27.394812 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4226 00:43:27.397767 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4227 00:43:27.401654 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4228 00:43:27.404908 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4229 00:43:27.411375 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4230 00:43:27.414649 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4231 00:43:27.414742 ==
4232 00:43:27.417951 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 00:43:27.421675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 00:43:27.421803 ==
4235 00:43:27.421890 DQS Delay:
4236 00:43:27.424920 DQS0 = 0, DQS1 = 0
4237 00:43:27.425044 DQM Delay:
4238 00:43:27.428286 DQM0 = 53, DQM1 = 43
4239 00:43:27.428424 DQ Delay:
4240 00:43:27.431487 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4241 00:43:27.434653 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4242 00:43:27.437946 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4243 00:43:27.441036 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4244 00:43:27.441136
4245 00:43:27.441220
4246 00:43:27.441335 ==
4247 00:43:27.444218 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 00:43:27.447709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 00:43:27.451426 ==
4250 00:43:27.451563
4251 00:43:27.451674
4252 00:43:27.451764 TX Vref Scan disable
4253 00:43:27.454656 == TX Byte 0 ==
4254 00:43:27.457874 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4255 00:43:27.461260 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4256 00:43:27.464573 == TX Byte 1 ==
4257 00:43:27.467819 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4258 00:43:27.474343 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4259 00:43:27.474466 ==
4260 00:43:27.477708 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 00:43:27.481026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 00:43:27.481184 ==
4263 00:43:27.481291
4264 00:43:27.481382
4265 00:43:27.484220 TX Vref Scan disable
4266 00:43:27.487709 == TX Byte 0 ==
4267 00:43:27.491168 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4268 00:43:27.494340 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4269 00:43:27.497564 == TX Byte 1 ==
4270 00:43:27.500789 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4271 00:43:27.504735 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4272 00:43:27.504852
4273 00:43:27.504939 [DATLAT]
4274 00:43:27.507728 Freq=600, CH0 RK1
4275 00:43:27.507840
4276 00:43:27.507931 DATLAT Default: 0x9
4277 00:43:27.510892 0, 0xFFFF, sum = 0
4278 00:43:27.514160 1, 0xFFFF, sum = 0
4279 00:43:27.514290 2, 0xFFFF, sum = 0
4280 00:43:27.517773 3, 0xFFFF, sum = 0
4281 00:43:27.517938 4, 0xFFFF, sum = 0
4282 00:43:27.520946 5, 0xFFFF, sum = 0
4283 00:43:27.521033 6, 0xFFFF, sum = 0
4284 00:43:27.524176 7, 0xFFFF, sum = 0
4285 00:43:27.524313 8, 0x0, sum = 1
4286 00:43:27.527516 9, 0x0, sum = 2
4287 00:43:27.527637 10, 0x0, sum = 3
4288 00:43:27.527750 11, 0x0, sum = 4
4289 00:43:27.531144 best_step = 9
4290 00:43:27.531236
4291 00:43:27.531300 ==
4292 00:43:27.534312 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 00:43:27.537487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 00:43:27.537607 ==
4295 00:43:27.540659 RX Vref Scan: 0
4296 00:43:27.540753
4297 00:43:27.540849 RX Vref 0 -> 0, step: 1
4298 00:43:27.540924
4299 00:43:27.544476 RX Delay -163 -> 252, step: 8
4300 00:43:27.551345 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4301 00:43:27.555086 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4302 00:43:27.558427 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4303 00:43:27.561679 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4304 00:43:27.565047 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4305 00:43:27.571662 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4306 00:43:27.574872 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4307 00:43:27.578134 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4308 00:43:27.581456 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4309 00:43:27.588057 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4310 00:43:27.591348 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4311 00:43:27.594667 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4312 00:43:27.597933 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4313 00:43:27.601201 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4314 00:43:27.608200 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4315 00:43:27.611257 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4316 00:43:27.611358 ==
4317 00:43:27.614668 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 00:43:27.618037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 00:43:27.618137 ==
4320 00:43:27.621540 DQS Delay:
4321 00:43:27.621631 DQS0 = 0, DQS1 = 0
4322 00:43:27.621696 DQM Delay:
4323 00:43:27.624298 DQM0 = 53, DQM1 = 45
4324 00:43:27.624404 DQ Delay:
4325 00:43:27.627860 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4326 00:43:27.630889 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4327 00:43:27.634640 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4328 00:43:27.638362 DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =52
4329 00:43:27.638473
4330 00:43:27.638542
4331 00:43:27.647660 [DQSOSCAuto] RK1, (LSB)MR18= 0x6627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4332 00:43:27.647801 CH0 RK1: MR19=808, MR18=6627
4333 00:43:27.654662 CH0_RK1: MR19=0x808, MR18=0x6627, DQSOSC=390, MR23=63, INC=172, DEC=114
4334 00:43:27.658028 [RxdqsGatingPostProcess] freq 600
4335 00:43:27.664796 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4336 00:43:27.668293 Pre-setting of DQS Precalculation
4337 00:43:27.671366 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4338 00:43:27.671491 ==
4339 00:43:27.674591 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 00:43:27.681262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 00:43:27.681441 ==
4342 00:43:27.684601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4343 00:43:27.691197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4344 00:43:27.694632 [CA 0] Center 36 (5~67) winsize 63
4345 00:43:27.698008 [CA 1] Center 36 (5~67) winsize 63
4346 00:43:27.701315 [CA 2] Center 34 (4~65) winsize 62
4347 00:43:27.704620 [CA 3] Center 34 (4~65) winsize 62
4348 00:43:27.707480 [CA 4] Center 34 (4~65) winsize 62
4349 00:43:27.711242 [CA 5] Center 33 (3~64) winsize 62
4350 00:43:27.711407
4351 00:43:27.713956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4352 00:43:27.714084
4353 00:43:27.717345 [CATrainingPosCal] consider 1 rank data
4354 00:43:27.721188 u2DelayCellTimex100 = 270/100 ps
4355 00:43:27.724519 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4356 00:43:27.727767 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4357 00:43:27.730955 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 00:43:27.737532 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4359 00:43:27.740688 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 00:43:27.744394 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 00:43:27.744552
4362 00:43:27.747822 CA PerBit enable=1, Macro0, CA PI delay=33
4363 00:43:27.747956
4364 00:43:27.750699 [CBTSetCACLKResult] CA Dly = 33
4365 00:43:27.750826 CS Dly: 6 (0~37)
4366 00:43:27.750922 ==
4367 00:43:27.754645 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 00:43:27.760669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 00:43:27.760834 ==
4370 00:43:27.764703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 00:43:27.770488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4372 00:43:27.774078 [CA 0] Center 36 (5~67) winsize 63
4373 00:43:27.777485 [CA 1] Center 36 (5~67) winsize 63
4374 00:43:27.780996 [CA 2] Center 34 (4~65) winsize 62
4375 00:43:27.783998 [CA 3] Center 34 (4~65) winsize 62
4376 00:43:27.787235 [CA 4] Center 34 (4~65) winsize 62
4377 00:43:27.791011 [CA 5] Center 34 (3~65) winsize 63
4378 00:43:27.791119
4379 00:43:27.794091 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4380 00:43:27.794206
4381 00:43:27.797474 [CATrainingPosCal] consider 2 rank data
4382 00:43:27.800738 u2DelayCellTimex100 = 270/100 ps
4383 00:43:27.804154 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4384 00:43:27.807563 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4385 00:43:27.814290 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 00:43:27.817670 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 00:43:27.821124 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 00:43:27.824287 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 00:43:27.824409
4390 00:43:27.827265 CA PerBit enable=1, Macro0, CA PI delay=33
4391 00:43:27.827399
4392 00:43:27.830996 [CBTSetCACLKResult] CA Dly = 33
4393 00:43:27.831125 CS Dly: 7 (0~39)
4394 00:43:27.831225
4395 00:43:27.834272 ----->DramcWriteLeveling(PI) begin...
4396 00:43:27.837541 ==
4397 00:43:27.840778 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 00:43:27.843853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 00:43:27.843996 ==
4400 00:43:27.847496 Write leveling (Byte 0): 31 => 31
4401 00:43:27.850809 Write leveling (Byte 1): 31 => 31
4402 00:43:27.854023 DramcWriteLeveling(PI) end<-----
4403 00:43:27.854172
4404 00:43:27.854274 ==
4405 00:43:27.857411 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 00:43:27.860613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 00:43:27.860739 ==
4408 00:43:27.863730 [Gating] SW mode calibration
4409 00:43:27.870850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 00:43:27.877140 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4411 00:43:27.880715 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 00:43:27.884285 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 00:43:27.887370 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 00:43:27.893907 0 9 12 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
4415 00:43:27.897346 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 00:43:27.900475 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 00:43:27.907081 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 00:43:27.910730 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 00:43:27.914069 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 00:43:27.920370 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 00:43:27.923694 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 00:43:27.927142 0 10 12 | B1->B0 | 3535 3e3e | 1 0 | (0 0) (0 0)
4423 00:43:27.933954 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 00:43:27.937268 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 00:43:27.940555 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 00:43:27.947233 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 00:43:27.950481 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 00:43:27.953630 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 00:43:27.960415 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 00:43:27.963457 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4431 00:43:27.966812 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:43:27.973731 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:43:27.976979 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:43:27.980533 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:43:27.986911 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:43:27.989937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:43:27.993587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:43:28.000206 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:43:28.003490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 00:43:28.006876 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 00:43:28.010145 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 00:43:28.016558 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:43:28.019898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:43:28.023434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:43:28.030296 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4446 00:43:28.033122 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4447 00:43:28.036797 Total UI for P1: 0, mck2ui 16
4448 00:43:28.040204 best dqsien dly found for B0: ( 0, 13, 8)
4449 00:43:28.043381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 00:43:28.046686 Total UI for P1: 0, mck2ui 16
4451 00:43:28.050035 best dqsien dly found for B1: ( 0, 13, 12)
4452 00:43:28.053338 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4453 00:43:28.056574 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4454 00:43:28.059631
4455 00:43:28.063442 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4456 00:43:28.066627 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4457 00:43:28.069952 [Gating] SW calibration Done
4458 00:43:28.070052 ==
4459 00:43:28.073330 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 00:43:28.076534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 00:43:28.076633 ==
4462 00:43:28.076702 RX Vref Scan: 0
4463 00:43:28.076763
4464 00:43:28.079769 RX Vref 0 -> 0, step: 1
4465 00:43:28.079888
4466 00:43:28.083166 RX Delay -230 -> 252, step: 16
4467 00:43:28.086333 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4468 00:43:28.092894 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4469 00:43:28.096195 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4470 00:43:28.100062 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4471 00:43:28.103079 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4472 00:43:28.106294 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4473 00:43:28.112970 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4474 00:43:28.116179 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4475 00:43:28.119911 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4476 00:43:28.123311 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4477 00:43:28.126357 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4478 00:43:28.133161 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4479 00:43:28.136513 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4480 00:43:28.139728 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4481 00:43:28.142822 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4482 00:43:28.149766 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4483 00:43:28.149916 ==
4484 00:43:28.153250 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 00:43:28.156086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 00:43:28.156211 ==
4487 00:43:28.156313 DQS Delay:
4488 00:43:28.159351 DQS0 = 0, DQS1 = 0
4489 00:43:28.159439 DQM Delay:
4490 00:43:28.162864 DQM0 = 49, DQM1 = 49
4491 00:43:28.162988 DQ Delay:
4492 00:43:28.165924 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4493 00:43:28.169766 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4494 00:43:28.173087 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4495 00:43:28.176321 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4496 00:43:28.176448
4497 00:43:28.176548
4498 00:43:28.176641 ==
4499 00:43:28.179568 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 00:43:28.182814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 00:43:28.182929 ==
4502 00:43:28.183026
4503 00:43:28.186037
4504 00:43:28.186150 TX Vref Scan disable
4505 00:43:28.189320 == TX Byte 0 ==
4506 00:43:28.193018 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4507 00:43:28.196249 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4508 00:43:28.199903 == TX Byte 1 ==
4509 00:43:28.202573 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4510 00:43:28.206616 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4511 00:43:28.206751 ==
4512 00:43:28.209578 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 00:43:28.216094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 00:43:28.216237 ==
4515 00:43:28.216349
4516 00:43:28.216441
4517 00:43:28.216513 TX Vref Scan disable
4518 00:43:28.220786 == TX Byte 0 ==
4519 00:43:28.223824 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4520 00:43:28.227277 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4521 00:43:28.230826 == TX Byte 1 ==
4522 00:43:28.234126 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4523 00:43:28.240644 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4524 00:43:28.240777
4525 00:43:28.240852 [DATLAT]
4526 00:43:28.240914 Freq=600, CH1 RK0
4527 00:43:28.240977
4528 00:43:28.243705 DATLAT Default: 0x9
4529 00:43:28.243815 0, 0xFFFF, sum = 0
4530 00:43:28.246991 1, 0xFFFF, sum = 0
4531 00:43:28.247104 2, 0xFFFF, sum = 0
4532 00:43:28.250360 3, 0xFFFF, sum = 0
4533 00:43:28.253664 4, 0xFFFF, sum = 0
4534 00:43:28.253748 5, 0xFFFF, sum = 0
4535 00:43:28.256720 6, 0xFFFF, sum = 0
4536 00:43:28.256806 7, 0xFFFF, sum = 0
4537 00:43:28.260351 8, 0x0, sum = 1
4538 00:43:28.260438 9, 0x0, sum = 2
4539 00:43:28.260501 10, 0x0, sum = 3
4540 00:43:28.263236 11, 0x0, sum = 4
4541 00:43:28.263338 best_step = 9
4542 00:43:28.263431
4543 00:43:28.263517 ==
4544 00:43:28.266636 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 00:43:28.273638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 00:43:28.273765 ==
4547 00:43:28.273834 RX Vref Scan: 1
4548 00:43:28.273894
4549 00:43:28.276738 RX Vref 0 -> 0, step: 1
4550 00:43:28.276821
4551 00:43:28.280260 RX Delay -163 -> 252, step: 8
4552 00:43:28.280397
4553 00:43:28.283556 Set Vref, RX VrefLevel [Byte0]: 52
4554 00:43:28.286231 [Byte1]: 54
4555 00:43:28.286350
4556 00:43:28.290185 Final RX Vref Byte 0 = 52 to rank0
4557 00:43:28.293456 Final RX Vref Byte 1 = 54 to rank0
4558 00:43:28.296747 Final RX Vref Byte 0 = 52 to rank1
4559 00:43:28.299981 Final RX Vref Byte 1 = 54 to rank1==
4560 00:43:28.303252 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 00:43:28.306658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 00:43:28.306797 ==
4563 00:43:28.309887 DQS Delay:
4564 00:43:28.310015 DQS0 = 0, DQS1 = 0
4565 00:43:28.313031 DQM Delay:
4566 00:43:28.313152 DQM0 = 48, DQM1 = 44
4567 00:43:28.313243 DQ Delay:
4568 00:43:28.316846 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4569 00:43:28.320038 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4570 00:43:28.323322 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4571 00:43:28.326523 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4572 00:43:28.326661
4573 00:43:28.326752
4574 00:43:28.336295 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4575 00:43:28.339871 CH1 RK0: MR19=808, MR18=4A70
4576 00:43:28.342865 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4577 00:43:28.346665
4578 00:43:28.349901 ----->DramcWriteLeveling(PI) begin...
4579 00:43:28.350058 ==
4580 00:43:28.353372 Dram Type= 6, Freq= 0, CH_1, rank 1
4581 00:43:28.356856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 00:43:28.356990 ==
4583 00:43:28.359881 Write leveling (Byte 0): 31 => 31
4584 00:43:28.363141 Write leveling (Byte 1): 29 => 29
4585 00:43:28.366317 DramcWriteLeveling(PI) end<-----
4586 00:43:28.366439
4587 00:43:28.366534 ==
4588 00:43:28.369471 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 00:43:28.373037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 00:43:28.373165 ==
4591 00:43:28.376368 [Gating] SW mode calibration
4592 00:43:28.383310 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4593 00:43:28.389600 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4594 00:43:28.392791 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 00:43:28.396377 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 00:43:28.403443 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 00:43:28.406337 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
4598 00:43:28.409628 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 00:43:28.416283 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 00:43:28.419685 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 00:43:28.422854 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 00:43:28.426086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 00:43:28.432994 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 00:43:28.436147 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 00:43:28.439503 0 10 12 | B1->B0 | 3b3b 3636 | 0 0 | (0 0) (0 0)
4606 00:43:28.446200 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 00:43:28.449555 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 00:43:28.452807 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 00:43:28.459768 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 00:43:28.463047 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 00:43:28.466348 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 00:43:28.472968 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4613 00:43:28.476237 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 00:43:28.479524 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 00:43:28.486509 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:43:28.489672 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:43:28.493207 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 00:43:28.499349 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:43:28.503135 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:43:28.505879 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:43:28.512427 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:43:28.516222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 00:43:28.519201 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 00:43:28.525883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 00:43:28.529051 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:43:28.532737 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:43:28.538929 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:43:28.542853 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:43:28.546131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4630 00:43:28.548927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 00:43:28.552224 Total UI for P1: 0, mck2ui 16
4632 00:43:28.555577 best dqsien dly found for B0: ( 0, 13, 12)
4633 00:43:28.559381 Total UI for P1: 0, mck2ui 16
4634 00:43:28.562504 best dqsien dly found for B1: ( 0, 13, 12)
4635 00:43:28.565861 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4636 00:43:28.572479 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4637 00:43:28.572627
4638 00:43:28.575882 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4639 00:43:28.579259 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4640 00:43:28.582764 [Gating] SW calibration Done
4641 00:43:28.582895 ==
4642 00:43:28.585738 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 00:43:28.589486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 00:43:28.589587 ==
4645 00:43:28.589660 RX Vref Scan: 0
4646 00:43:28.592432
4647 00:43:28.592551 RX Vref 0 -> 0, step: 1
4648 00:43:28.592649
4649 00:43:28.596308 RX Delay -230 -> 252, step: 16
4650 00:43:28.599650 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4651 00:43:28.605624 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4652 00:43:28.608969 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4653 00:43:28.612763 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4654 00:43:28.615991 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4655 00:43:28.619118 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4656 00:43:28.625910 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4657 00:43:28.629259 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4658 00:43:28.632615 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4659 00:43:28.635838 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4660 00:43:28.642054 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4661 00:43:28.645671 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4662 00:43:28.648742 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4663 00:43:28.652756 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4664 00:43:28.655821 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4665 00:43:28.662135 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4666 00:43:28.662285 ==
4667 00:43:28.665303 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 00:43:28.669474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 00:43:28.669609 ==
4670 00:43:28.669714 DQS Delay:
4671 00:43:28.672026 DQS0 = 0, DQS1 = 0
4672 00:43:28.672138 DQM Delay:
4673 00:43:28.675198 DQM0 = 49, DQM1 = 47
4674 00:43:28.675320 DQ Delay:
4675 00:43:28.679115 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4676 00:43:28.682446 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4677 00:43:28.685443 DQ8 =33, DQ9 =41, DQ10 =41, DQ11 =41
4678 00:43:28.689175 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4679 00:43:28.689320
4680 00:43:28.689423
4681 00:43:28.689553 ==
4682 00:43:28.692019 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 00:43:28.695472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 00:43:28.698652 ==
4685 00:43:28.698774
4686 00:43:28.698870
4687 00:43:28.698961 TX Vref Scan disable
4688 00:43:28.701771 == TX Byte 0 ==
4689 00:43:28.705368 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4690 00:43:28.708645 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4691 00:43:28.712115 == TX Byte 1 ==
4692 00:43:28.714995 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4693 00:43:28.721867 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4694 00:43:28.722025 ==
4695 00:43:28.725123 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 00:43:28.728280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 00:43:28.728415 ==
4698 00:43:28.728511
4699 00:43:28.728605
4700 00:43:28.731636 TX Vref Scan disable
4701 00:43:28.734850 == TX Byte 0 ==
4702 00:43:28.738391 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4703 00:43:28.742068 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4704 00:43:28.745514 == TX Byte 1 ==
4705 00:43:28.748451 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4706 00:43:28.751615 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4707 00:43:28.751748
4708 00:43:28.751844 [DATLAT]
4709 00:43:28.754812 Freq=600, CH1 RK1
4710 00:43:28.754897
4711 00:43:28.754970 DATLAT Default: 0x9
4712 00:43:28.758826 0, 0xFFFF, sum = 0
4713 00:43:28.758945 1, 0xFFFF, sum = 0
4714 00:43:28.761525 2, 0xFFFF, sum = 0
4715 00:43:28.765386 3, 0xFFFF, sum = 0
4716 00:43:28.765516 4, 0xFFFF, sum = 0
4717 00:43:28.768175 5, 0xFFFF, sum = 0
4718 00:43:28.768287 6, 0xFFFF, sum = 0
4719 00:43:28.771702 7, 0xFFFF, sum = 0
4720 00:43:28.771818 8, 0x0, sum = 1
4721 00:43:28.771916 9, 0x0, sum = 2
4722 00:43:28.774948 10, 0x0, sum = 3
4723 00:43:28.775058 11, 0x0, sum = 4
4724 00:43:28.778372 best_step = 9
4725 00:43:28.778488
4726 00:43:28.778581 ==
4727 00:43:28.781809 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 00:43:28.784871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 00:43:28.784994 ==
4730 00:43:28.788294 RX Vref Scan: 0
4731 00:43:28.788422
4732 00:43:28.788525 RX Vref 0 -> 0, step: 1
4733 00:43:28.788631
4734 00:43:28.791650 RX Delay -163 -> 252, step: 8
4735 00:43:28.798892 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4736 00:43:28.802308 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4737 00:43:28.805454 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4738 00:43:28.808689 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4739 00:43:28.812437 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4740 00:43:28.819058 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4741 00:43:28.822356 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4742 00:43:28.825663 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4743 00:43:28.829034 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4744 00:43:28.832350 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4745 00:43:28.839030 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4746 00:43:28.842254 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4747 00:43:28.845707 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4748 00:43:28.848927 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4749 00:43:28.855764 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4750 00:43:28.858883 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4751 00:43:28.859025 ==
4752 00:43:28.862123 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 00:43:28.865348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 00:43:28.865476 ==
4755 00:43:28.868730 DQS Delay:
4756 00:43:28.868855 DQS0 = 0, DQS1 = 0
4757 00:43:28.868951 DQM Delay:
4758 00:43:28.872169 DQM0 = 48, DQM1 = 45
4759 00:43:28.872288 DQ Delay:
4760 00:43:28.875498 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4761 00:43:28.878712 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4762 00:43:28.881923 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4763 00:43:28.885228 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4764 00:43:28.885364
4765 00:43:28.885462
4766 00:43:28.895601 [DQSOSCAuto] RK1, (LSB)MR18= 0x681f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4767 00:43:28.895759 CH1 RK1: MR19=808, MR18=681F
4768 00:43:28.901935 CH1_RK1: MR19=0x808, MR18=0x681F, DQSOSC=390, MR23=63, INC=172, DEC=114
4769 00:43:28.905807 [RxdqsGatingPostProcess] freq 600
4770 00:43:28.912458 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4771 00:43:28.915737 Pre-setting of DQS Precalculation
4772 00:43:28.918999 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4773 00:43:28.925605 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4774 00:43:28.935772 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4775 00:43:28.935923
4776 00:43:28.936025
4777 00:43:28.936127 [Calibration Summary] 1200 Mbps
4778 00:43:28.939179 CH 0, Rank 0
4779 00:43:28.939292 SW Impedance : PASS
4780 00:43:28.941922 DUTY Scan : NO K
4781 00:43:28.945687 ZQ Calibration : PASS
4782 00:43:28.945785 Jitter Meter : NO K
4783 00:43:28.949100 CBT Training : PASS
4784 00:43:28.952070 Write leveling : PASS
4785 00:43:28.952186 RX DQS gating : PASS
4786 00:43:28.955562 RX DQ/DQS(RDDQC) : PASS
4787 00:43:28.958806 TX DQ/DQS : PASS
4788 00:43:28.958919 RX DATLAT : PASS
4789 00:43:28.961966 RX DQ/DQS(Engine): PASS
4790 00:43:28.965881 TX OE : NO K
4791 00:43:28.965980 All Pass.
4792 00:43:28.966047
4793 00:43:28.966108 CH 0, Rank 1
4794 00:43:28.968765 SW Impedance : PASS
4795 00:43:28.971996 DUTY Scan : NO K
4796 00:43:28.972110 ZQ Calibration : PASS
4797 00:43:28.975342 Jitter Meter : NO K
4798 00:43:28.978711 CBT Training : PASS
4799 00:43:28.978820 Write leveling : PASS
4800 00:43:28.981776 RX DQS gating : PASS
4801 00:43:28.981861 RX DQ/DQS(RDDQC) : PASS
4802 00:43:28.985536 TX DQ/DQS : PASS
4803 00:43:28.989012 RX DATLAT : PASS
4804 00:43:28.989137 RX DQ/DQS(Engine): PASS
4805 00:43:28.991927 TX OE : NO K
4806 00:43:28.992048 All Pass.
4807 00:43:28.992161
4808 00:43:28.995299 CH 1, Rank 0
4809 00:43:28.995415 SW Impedance : PASS
4810 00:43:28.998782 DUTY Scan : NO K
4811 00:43:29.002003 ZQ Calibration : PASS
4812 00:43:29.002132 Jitter Meter : NO K
4813 00:43:29.005217 CBT Training : PASS
4814 00:43:29.008817 Write leveling : PASS
4815 00:43:29.008935 RX DQS gating : PASS
4816 00:43:29.011838 RX DQ/DQS(RDDQC) : PASS
4817 00:43:29.014995 TX DQ/DQS : PASS
4818 00:43:29.015106 RX DATLAT : PASS
4819 00:43:29.018702 RX DQ/DQS(Engine): PASS
4820 00:43:29.021869 TX OE : NO K
4821 00:43:29.022003 All Pass.
4822 00:43:29.022107
4823 00:43:29.022206 CH 1, Rank 1
4824 00:43:29.024917 SW Impedance : PASS
4825 00:43:29.028521 DUTY Scan : NO K
4826 00:43:29.028645 ZQ Calibration : PASS
4827 00:43:29.031897 Jitter Meter : NO K
4828 00:43:29.034786 CBT Training : PASS
4829 00:43:29.034901 Write leveling : PASS
4830 00:43:29.038743 RX DQS gating : PASS
4831 00:43:29.038857 RX DQ/DQS(RDDQC) : PASS
4832 00:43:29.042326 TX DQ/DQS : PASS
4833 00:43:29.044758 RX DATLAT : PASS
4834 00:43:29.044874 RX DQ/DQS(Engine): PASS
4835 00:43:29.048111 TX OE : NO K
4836 00:43:29.048216 All Pass.
4837 00:43:29.048308
4838 00:43:29.051485 DramC Write-DBI off
4839 00:43:29.054764 PER_BANK_REFRESH: Hybrid Mode
4840 00:43:29.054875 TX_TRACKING: ON
4841 00:43:29.064667 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4842 00:43:29.068661 [FAST_K] Save calibration result to emmc
4843 00:43:29.071935 dramc_set_vcore_voltage set vcore to 662500
4844 00:43:29.075198 Read voltage for 933, 3
4845 00:43:29.075294 Vio18 = 0
4846 00:43:29.075361 Vcore = 662500
4847 00:43:29.078559 Vdram = 0
4848 00:43:29.078650 Vddq = 0
4849 00:43:29.078716 Vmddr = 0
4850 00:43:29.084980 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4851 00:43:29.088076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4852 00:43:29.091379 MEM_TYPE=3, freq_sel=17
4853 00:43:29.094710 sv_algorithm_assistance_LP4_1600
4854 00:43:29.097976 ============ PULL DRAM RESETB DOWN ============
4855 00:43:29.101286 ========== PULL DRAM RESETB DOWN end =========
4856 00:43:29.108063 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 00:43:29.111366 ===================================
4858 00:43:29.114641 LPDDR4 DRAM CONFIGURATION
4859 00:43:29.118342 ===================================
4860 00:43:29.118468 EX_ROW_EN[0] = 0x0
4861 00:43:29.121722 EX_ROW_EN[1] = 0x0
4862 00:43:29.121845 LP4Y_EN = 0x0
4863 00:43:29.124974 WORK_FSP = 0x0
4864 00:43:29.125065 WL = 0x3
4865 00:43:29.128320 RL = 0x3
4866 00:43:29.128411 BL = 0x2
4867 00:43:29.131684 RPST = 0x0
4868 00:43:29.131794 RD_PRE = 0x0
4869 00:43:29.134950 WR_PRE = 0x1
4870 00:43:29.135054 WR_PST = 0x0
4871 00:43:29.138058 DBI_WR = 0x0
4872 00:43:29.138166 DBI_RD = 0x0
4873 00:43:29.141686 OTF = 0x1
4874 00:43:29.145111 ===================================
4875 00:43:29.147861 ===================================
4876 00:43:29.147973 ANA top config
4877 00:43:29.151670 ===================================
4878 00:43:29.155071 DLL_ASYNC_EN = 0
4879 00:43:29.158474 ALL_SLAVE_EN = 1
4880 00:43:29.161702 NEW_RANK_MODE = 1
4881 00:43:29.161817 DLL_IDLE_MODE = 1
4882 00:43:29.164694 LP45_APHY_COMB_EN = 1
4883 00:43:29.167918 TX_ODT_DIS = 1
4884 00:43:29.171972 NEW_8X_MODE = 1
4885 00:43:29.175065 ===================================
4886 00:43:29.178255 ===================================
4887 00:43:29.181319 data_rate = 1866
4888 00:43:29.181426 CKR = 1
4889 00:43:29.184696 DQ_P2S_RATIO = 8
4890 00:43:29.187955 ===================================
4891 00:43:29.191756 CA_P2S_RATIO = 8
4892 00:43:29.194844 DQ_CA_OPEN = 0
4893 00:43:29.198036 DQ_SEMI_OPEN = 0
4894 00:43:29.201373 CA_SEMI_OPEN = 0
4895 00:43:29.201468 CA_FULL_RATE = 0
4896 00:43:29.204861 DQ_CKDIV4_EN = 1
4897 00:43:29.207956 CA_CKDIV4_EN = 1
4898 00:43:29.211193 CA_PREDIV_EN = 0
4899 00:43:29.214585 PH8_DLY = 0
4900 00:43:29.217802 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4901 00:43:29.217903 DQ_AAMCK_DIV = 4
4902 00:43:29.221493 CA_AAMCK_DIV = 4
4903 00:43:29.224595 CA_ADMCK_DIV = 4
4904 00:43:29.227821 DQ_TRACK_CA_EN = 0
4905 00:43:29.231123 CA_PICK = 933
4906 00:43:29.235011 CA_MCKIO = 933
4907 00:43:29.235112 MCKIO_SEMI = 0
4908 00:43:29.238293 PLL_FREQ = 3732
4909 00:43:29.241682 DQ_UI_PI_RATIO = 32
4910 00:43:29.244934 CA_UI_PI_RATIO = 0
4911 00:43:29.248271 ===================================
4912 00:43:29.251606 ===================================
4913 00:43:29.254800 memory_type:LPDDR4
4914 00:43:29.254897 GP_NUM : 10
4915 00:43:29.258367 SRAM_EN : 1
4916 00:43:29.261360 MD32_EN : 0
4917 00:43:29.264803 ===================================
4918 00:43:29.264899 [ANA_INIT] >>>>>>>>>>>>>>
4919 00:43:29.267743 <<<<<< [CONFIGURE PHASE]: ANA_TX
4920 00:43:29.271203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4921 00:43:29.275002 ===================================
4922 00:43:29.277927 data_rate = 1866,PCW = 0X8f00
4923 00:43:29.281247 ===================================
4924 00:43:29.284742 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4925 00:43:29.291180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 00:43:29.294607 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 00:43:29.301142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4928 00:43:29.304319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4929 00:43:29.307671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4930 00:43:29.307766 [ANA_INIT] flow start
4931 00:43:29.311051 [ANA_INIT] PLL >>>>>>>>
4932 00:43:29.314311 [ANA_INIT] PLL <<<<<<<<
4933 00:43:29.314425 [ANA_INIT] MIDPI >>>>>>>>
4934 00:43:29.318225 [ANA_INIT] MIDPI <<<<<<<<
4935 00:43:29.320869 [ANA_INIT] DLL >>>>>>>>
4936 00:43:29.320980 [ANA_INIT] flow end
4937 00:43:29.327627 ============ LP4 DIFF to SE enter ============
4938 00:43:29.330817 ============ LP4 DIFF to SE exit ============
4939 00:43:29.333950 [ANA_INIT] <<<<<<<<<<<<<
4940 00:43:29.338006 [Flow] Enable top DCM control >>>>>
4941 00:43:29.341317 [Flow] Enable top DCM control <<<<<
4942 00:43:29.341441 Enable DLL master slave shuffle
4943 00:43:29.348047 ==============================================================
4944 00:43:29.350744 Gating Mode config
4945 00:43:29.354784 ==============================================================
4946 00:43:29.357605 Config description:
4947 00:43:29.367844 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4948 00:43:29.374177 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4949 00:43:29.377546 SELPH_MODE 0: By rank 1: By Phase
4950 00:43:29.384103 ==============================================================
4951 00:43:29.387435 GAT_TRACK_EN = 1
4952 00:43:29.390754 RX_GATING_MODE = 2
4953 00:43:29.394120 RX_GATING_TRACK_MODE = 2
4954 00:43:29.397580 SELPH_MODE = 1
4955 00:43:29.397706 PICG_EARLY_EN = 1
4956 00:43:29.400990 VALID_LAT_VALUE = 1
4957 00:43:29.407333 ==============================================================
4958 00:43:29.411073 Enter into Gating configuration >>>>
4959 00:43:29.414469 Exit from Gating configuration <<<<
4960 00:43:29.417322 Enter into DVFS_PRE_config >>>>>
4961 00:43:29.427733 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4962 00:43:29.430869 Exit from DVFS_PRE_config <<<<<
4963 00:43:29.433812 Enter into PICG configuration >>>>
4964 00:43:29.437155 Exit from PICG configuration <<<<
4965 00:43:29.440484 [RX_INPUT] configuration >>>>>
4966 00:43:29.443856 [RX_INPUT] configuration <<<<<
4967 00:43:29.447654 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4968 00:43:29.453704 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4969 00:43:29.460363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 00:43:29.467096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 00:43:29.473915 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 00:43:29.477008 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 00:43:29.483561 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4974 00:43:29.486894 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4975 00:43:29.490344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4976 00:43:29.493718 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4977 00:43:29.500636 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4978 00:43:29.503996 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 00:43:29.507021 ===================================
4980 00:43:29.510279 LPDDR4 DRAM CONFIGURATION
4981 00:43:29.513642 ===================================
4982 00:43:29.513757 EX_ROW_EN[0] = 0x0
4983 00:43:29.516875 EX_ROW_EN[1] = 0x0
4984 00:43:29.516980 LP4Y_EN = 0x0
4985 00:43:29.520479 WORK_FSP = 0x0
4986 00:43:29.520585 WL = 0x3
4987 00:43:29.523543 RL = 0x3
4988 00:43:29.523653 BL = 0x2
4989 00:43:29.527179 RPST = 0x0
4990 00:43:29.527297 RD_PRE = 0x0
4991 00:43:29.530376 WR_PRE = 0x1
4992 00:43:29.533432 WR_PST = 0x0
4993 00:43:29.533555 DBI_WR = 0x0
4994 00:43:29.537050 DBI_RD = 0x0
4995 00:43:29.537173 OTF = 0x1
4996 00:43:29.540030 ===================================
4997 00:43:29.543340 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4998 00:43:29.549774 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4999 00:43:29.553395 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 00:43:29.556867 ===================================
5001 00:43:29.559998 LPDDR4 DRAM CONFIGURATION
5002 00:43:29.563219 ===================================
5003 00:43:29.563319 EX_ROW_EN[0] = 0x10
5004 00:43:29.566502 EX_ROW_EN[1] = 0x0
5005 00:43:29.566589 LP4Y_EN = 0x0
5006 00:43:29.570414 WORK_FSP = 0x0
5007 00:43:29.570509 WL = 0x3
5008 00:43:29.573601 RL = 0x3
5009 00:43:29.573694 BL = 0x2
5010 00:43:29.576726 RPST = 0x0
5011 00:43:29.576848 RD_PRE = 0x0
5012 00:43:29.580026 WR_PRE = 0x1
5013 00:43:29.580138 WR_PST = 0x0
5014 00:43:29.583569 DBI_WR = 0x0
5015 00:43:29.583681 DBI_RD = 0x0
5016 00:43:29.586689 OTF = 0x1
5017 00:43:29.590023 ===================================
5018 00:43:29.596742 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5019 00:43:29.600120 nWR fixed to 30
5020 00:43:29.603832 [ModeRegInit_LP4] CH0 RK0
5021 00:43:29.603952 [ModeRegInit_LP4] CH0 RK1
5022 00:43:29.607016 [ModeRegInit_LP4] CH1 RK0
5023 00:43:29.610221 [ModeRegInit_LP4] CH1 RK1
5024 00:43:29.610339 match AC timing 9
5025 00:43:29.616794 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5026 00:43:29.620128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5027 00:43:29.623461 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5028 00:43:29.629908 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5029 00:43:29.633129 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5030 00:43:29.633266 ==
5031 00:43:29.636902 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 00:43:29.639866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 00:43:29.639984 ==
5034 00:43:29.646616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 00:43:29.653026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5036 00:43:29.656287 [CA 0] Center 37 (6~68) winsize 63
5037 00:43:29.659686 [CA 1] Center 37 (6~68) winsize 63
5038 00:43:29.663336 [CA 2] Center 34 (4~65) winsize 62
5039 00:43:29.666399 [CA 3] Center 34 (3~65) winsize 63
5040 00:43:29.670337 [CA 4] Center 33 (3~64) winsize 62
5041 00:43:29.673400 [CA 5] Center 32 (2~62) winsize 61
5042 00:43:29.673496
5043 00:43:29.676466 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5044 00:43:29.676554
5045 00:43:29.679946 [CATrainingPosCal] consider 1 rank data
5046 00:43:29.683292 u2DelayCellTimex100 = 270/100 ps
5047 00:43:29.686399 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5048 00:43:29.689695 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5049 00:43:29.693021 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5050 00:43:29.696716 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5051 00:43:29.699644 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5052 00:43:29.703352 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5053 00:43:29.703480
5054 00:43:29.709855 CA PerBit enable=1, Macro0, CA PI delay=32
5055 00:43:29.709991
5056 00:43:29.713407 [CBTSetCACLKResult] CA Dly = 32
5057 00:43:29.713532 CS Dly: 5 (0~36)
5058 00:43:29.713633 ==
5059 00:43:29.716645 Dram Type= 6, Freq= 0, CH_0, rank 1
5060 00:43:29.720082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 00:43:29.720201 ==
5062 00:43:29.726578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 00:43:29.733053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5064 00:43:29.736336 [CA 0] Center 37 (6~68) winsize 63
5065 00:43:29.739646 [CA 1] Center 37 (7~68) winsize 62
5066 00:43:29.743065 [CA 2] Center 34 (4~65) winsize 62
5067 00:43:29.746272 [CA 3] Center 34 (4~65) winsize 62
5068 00:43:29.749583 [CA 4] Center 32 (2~63) winsize 62
5069 00:43:29.752666 [CA 5] Center 32 (2~62) winsize 61
5070 00:43:29.752785
5071 00:43:29.756540 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5072 00:43:29.756660
5073 00:43:29.760022 [CATrainingPosCal] consider 2 rank data
5074 00:43:29.762686 u2DelayCellTimex100 = 270/100 ps
5075 00:43:29.766019 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5076 00:43:29.769299 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5077 00:43:29.772705 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5078 00:43:29.775987 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 00:43:29.779288 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5080 00:43:29.786263 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5081 00:43:29.786375
5082 00:43:29.789503 CA PerBit enable=1, Macro0, CA PI delay=32
5083 00:43:29.789591
5084 00:43:29.792628 [CBTSetCACLKResult] CA Dly = 32
5085 00:43:29.792715 CS Dly: 6 (0~38)
5086 00:43:29.792799
5087 00:43:29.796005 ----->DramcWriteLeveling(PI) begin...
5088 00:43:29.796118 ==
5089 00:43:29.799313 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 00:43:29.805925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 00:43:29.806020 ==
5092 00:43:29.809336 Write leveling (Byte 0): 33 => 33
5093 00:43:29.809422 Write leveling (Byte 1): 29 => 29
5094 00:43:29.812486 DramcWriteLeveling(PI) end<-----
5095 00:43:29.812571
5096 00:43:29.812636 ==
5097 00:43:29.816148 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 00:43:29.822740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 00:43:29.822855 ==
5100 00:43:29.826034 [Gating] SW mode calibration
5101 00:43:29.832796 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 00:43:29.836071 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5103 00:43:29.842611 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (1 1) (1 1)
5104 00:43:29.845949 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5105 00:43:29.849346 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 00:43:29.855952 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 00:43:29.859295 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 00:43:29.862669 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 00:43:29.869284 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5110 00:43:29.872640 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 0) (0 0)
5111 00:43:29.876241 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5112 00:43:29.879477 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 00:43:29.885492 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 00:43:29.888807 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 00:43:29.892556 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 00:43:29.898970 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 00:43:29.902371 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5118 00:43:29.905896 0 15 28 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
5119 00:43:29.912389 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5120 00:43:29.915700 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 00:43:29.919292 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 00:43:29.925588 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 00:43:29.929292 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 00:43:29.932289 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 00:43:29.939067 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 00:43:29.942448 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5127 00:43:29.945883 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5128 00:43:29.952658 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:43:29.955960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:43:29.959331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:43:29.966112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:43:29.969334 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:43:29.972621 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 00:43:29.975945 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 00:43:29.982751 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 00:43:29.985912 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 00:43:29.989099 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 00:43:29.995729 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 00:43:29.998952 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 00:43:30.002692 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:43:30.008970 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5142 00:43:30.012033 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 00:43:30.015786 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 00:43:30.019026 Total UI for P1: 0, mck2ui 16
5145 00:43:30.022273 best dqsien dly found for B0: ( 1, 2, 26)
5146 00:43:30.029030 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 00:43:30.029133 Total UI for P1: 0, mck2ui 16
5148 00:43:30.035362 best dqsien dly found for B1: ( 1, 3, 0)
5149 00:43:30.039102 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5150 00:43:30.042471 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5151 00:43:30.042582
5152 00:43:30.045887 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5153 00:43:30.048954 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5154 00:43:30.052164 [Gating] SW calibration Done
5155 00:43:30.052285 ==
5156 00:43:30.055963 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 00:43:30.059459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 00:43:30.059567 ==
5159 00:43:30.062173 RX Vref Scan: 0
5160 00:43:30.062255
5161 00:43:30.062319 RX Vref 0 -> 0, step: 1
5162 00:43:30.062379
5163 00:43:30.065642 RX Delay -80 -> 252, step: 8
5164 00:43:30.068594 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5165 00:43:30.075237 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5166 00:43:30.078832 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5167 00:43:30.081929 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5168 00:43:30.085324 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5169 00:43:30.088502 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5170 00:43:30.094939 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5171 00:43:30.098225 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5172 00:43:30.101566 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5173 00:43:30.104896 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5174 00:43:30.108360 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5175 00:43:30.111461 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5176 00:43:30.118377 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5177 00:43:30.122058 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5178 00:43:30.124987 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5179 00:43:30.127943 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5180 00:43:30.128057 ==
5181 00:43:30.131146 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 00:43:30.134750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 00:43:30.138265 ==
5184 00:43:30.138379 DQS Delay:
5185 00:43:30.138482 DQS0 = 0, DQS1 = 0
5186 00:43:30.141361 DQM Delay:
5187 00:43:30.141469 DQM0 = 106, DQM1 = 93
5188 00:43:30.144629 DQ Delay:
5189 00:43:30.147742 DQ0 =107, DQ1 =111, DQ2 =99, DQ3 =99
5190 00:43:30.151020 DQ4 =111, DQ5 =95, DQ6 =111, DQ7 =115
5191 00:43:30.154375 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5192 00:43:30.157626 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5193 00:43:30.157705
5194 00:43:30.157771
5195 00:43:30.157831 ==
5196 00:43:30.161397 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 00:43:30.164566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 00:43:30.164653 ==
5199 00:43:30.164718
5200 00:43:30.164777
5201 00:43:30.167866 TX Vref Scan disable
5202 00:43:30.167965 == TX Byte 0 ==
5203 00:43:30.174712 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5204 00:43:30.177693 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5205 00:43:30.177780 == TX Byte 1 ==
5206 00:43:30.184451 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5207 00:43:30.188089 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5208 00:43:30.188183 ==
5209 00:43:30.191346 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 00:43:30.194319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 00:43:30.194437 ==
5212 00:43:30.197571
5213 00:43:30.197681
5214 00:43:30.197772 TX Vref Scan disable
5215 00:43:30.200832 == TX Byte 0 ==
5216 00:43:30.204211 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5217 00:43:30.210877 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5218 00:43:30.210974 == TX Byte 1 ==
5219 00:43:30.214212 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5220 00:43:30.220857 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5221 00:43:30.220943
5222 00:43:30.221007 [DATLAT]
5223 00:43:30.221065 Freq=933, CH0 RK0
5224 00:43:30.221122
5225 00:43:30.223993 DATLAT Default: 0xd
5226 00:43:30.227135 0, 0xFFFF, sum = 0
5227 00:43:30.227213 1, 0xFFFF, sum = 0
5228 00:43:30.230336 2, 0xFFFF, sum = 0
5229 00:43:30.230442 3, 0xFFFF, sum = 0
5230 00:43:30.233621 4, 0xFFFF, sum = 0
5231 00:43:30.233699 5, 0xFFFF, sum = 0
5232 00:43:30.237067 6, 0xFFFF, sum = 0
5233 00:43:30.237171 7, 0xFFFF, sum = 0
5234 00:43:30.240553 8, 0xFFFF, sum = 0
5235 00:43:30.240657 9, 0xFFFF, sum = 0
5236 00:43:30.243624 10, 0x0, sum = 1
5237 00:43:30.243718 11, 0x0, sum = 2
5238 00:43:30.247142 12, 0x0, sum = 3
5239 00:43:30.247252 13, 0x0, sum = 4
5240 00:43:30.247366 best_step = 11
5241 00:43:30.250303
5242 00:43:30.250413 ==
5243 00:43:30.253621 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 00:43:30.256998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 00:43:30.257107 ==
5246 00:43:30.257213 RX Vref Scan: 1
5247 00:43:30.257315
5248 00:43:30.260443 RX Vref 0 -> 0, step: 1
5249 00:43:30.260563
5250 00:43:30.264057 RX Delay -53 -> 252, step: 4
5251 00:43:30.264168
5252 00:43:30.267165 Set Vref, RX VrefLevel [Byte0]: 56
5253 00:43:30.270095 [Byte1]: 47
5254 00:43:30.273386
5255 00:43:30.273496 Final RX Vref Byte 0 = 56 to rank0
5256 00:43:30.276712 Final RX Vref Byte 1 = 47 to rank0
5257 00:43:30.279948 Final RX Vref Byte 0 = 56 to rank1
5258 00:43:30.283162 Final RX Vref Byte 1 = 47 to rank1==
5259 00:43:30.286874 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 00:43:30.293489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 00:43:30.293610 ==
5262 00:43:30.293716 DQS Delay:
5263 00:43:30.293816 DQS0 = 0, DQS1 = 0
5264 00:43:30.296706 DQM Delay:
5265 00:43:30.296781 DQM0 = 105, DQM1 = 95
5266 00:43:30.299942 DQ Delay:
5267 00:43:30.303195 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =104
5268 00:43:30.307040 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =112
5269 00:43:30.309766 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5270 00:43:30.313670 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5271 00:43:30.313855
5272 00:43:30.313960
5273 00:43:30.319782 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5274 00:43:30.323629 CH0 RK0: MR19=505, MR18=322A
5275 00:43:30.330191 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5276 00:43:30.330340
5277 00:43:30.333176 ----->DramcWriteLeveling(PI) begin...
5278 00:43:30.333302 ==
5279 00:43:30.336496 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 00:43:30.340080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 00:43:30.340195 ==
5282 00:43:30.343265 Write leveling (Byte 0): 32 => 32
5283 00:43:30.346604 Write leveling (Byte 1): 27 => 27
5284 00:43:30.349885 DramcWriteLeveling(PI) end<-----
5285 00:43:30.350003
5286 00:43:30.350071 ==
5287 00:43:30.353178 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 00:43:30.360147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 00:43:30.360302 ==
5290 00:43:30.360395 [Gating] SW mode calibration
5291 00:43:30.370222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5292 00:43:30.373190 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5293 00:43:30.376586 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5294 00:43:30.383282 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 00:43:30.386457 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 00:43:30.389595 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 00:43:30.396592 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 00:43:30.400014 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 00:43:30.402992 0 14 24 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
5300 00:43:30.409653 0 14 28 | B1->B0 | 2929 2a2a | 0 0 | (1 0) (1 0)
5301 00:43:30.412873 0 15 0 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5302 00:43:30.416243 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 00:43:30.423005 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 00:43:30.426183 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 00:43:30.429460 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 00:43:30.436040 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 00:43:30.439782 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5308 00:43:30.443003 0 15 28 | B1->B0 | 3636 3433 | 0 1 | (0 0) (0 0)
5309 00:43:30.449940 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5310 00:43:30.452981 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 00:43:30.456478 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 00:43:30.462911 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 00:43:30.466496 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 00:43:30.469463 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 00:43:30.475838 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 00:43:30.479869 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5317 00:43:30.482992 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5318 00:43:30.489120 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 00:43:30.492483 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 00:43:30.495970 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:43:30.502347 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:43:30.506199 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:43:30.509626 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:43:30.512917 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 00:43:30.518982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 00:43:30.522277 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 00:43:30.525868 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 00:43:30.532704 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 00:43:30.536005 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:43:30.539297 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:43:30.545901 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:43:30.549532 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5333 00:43:30.552828 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 00:43:30.556049 Total UI for P1: 0, mck2ui 16
5335 00:43:30.559323 best dqsien dly found for B0: ( 1, 2, 28)
5336 00:43:30.562893 Total UI for P1: 0, mck2ui 16
5337 00:43:30.566063 best dqsien dly found for B1: ( 1, 2, 28)
5338 00:43:30.569277 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5339 00:43:30.572522 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5340 00:43:30.572605
5341 00:43:30.579097 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5342 00:43:30.582536 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 00:43:30.585895 [Gating] SW calibration Done
5344 00:43:30.585977 ==
5345 00:43:30.588818 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 00:43:30.592079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 00:43:30.592196 ==
5348 00:43:30.592289 RX Vref Scan: 0
5349 00:43:30.592384
5350 00:43:30.595312 RX Vref 0 -> 0, step: 1
5351 00:43:30.595423
5352 00:43:30.599142 RX Delay -80 -> 252, step: 8
5353 00:43:30.602273 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5354 00:43:30.605571 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5355 00:43:30.612180 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5356 00:43:30.615657 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5357 00:43:30.618827 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5358 00:43:30.622038 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5359 00:43:30.625398 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5360 00:43:30.628581 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5361 00:43:30.632351 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5362 00:43:30.638660 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5363 00:43:30.642094 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5364 00:43:30.645382 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5365 00:43:30.648723 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5366 00:43:30.652077 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5367 00:43:30.658709 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5368 00:43:30.662183 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5369 00:43:30.662310 ==
5370 00:43:30.665476 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 00:43:30.668864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 00:43:30.668977 ==
5373 00:43:30.669080 DQS Delay:
5374 00:43:30.672276 DQS0 = 0, DQS1 = 0
5375 00:43:30.672393 DQM Delay:
5376 00:43:30.674996 DQM0 = 105, DQM1 = 94
5377 00:43:30.675101 DQ Delay:
5378 00:43:30.678276 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5379 00:43:30.681790 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5380 00:43:30.685156 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5381 00:43:30.688306 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5382 00:43:30.688470
5383 00:43:30.688569
5384 00:43:30.688658 ==
5385 00:43:30.692158 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 00:43:30.698686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 00:43:30.698842 ==
5388 00:43:30.698936
5389 00:43:30.699029
5390 00:43:30.699122 TX Vref Scan disable
5391 00:43:30.702170 == TX Byte 0 ==
5392 00:43:30.705325 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5393 00:43:30.709221 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5394 00:43:30.712010 == TX Byte 1 ==
5395 00:43:30.715404 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5396 00:43:30.719126 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5397 00:43:30.722368 ==
5398 00:43:30.725428 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 00:43:30.729003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 00:43:30.729085 ==
5401 00:43:30.729169
5402 00:43:30.729230
5403 00:43:30.732182 TX Vref Scan disable
5404 00:43:30.732285 == TX Byte 0 ==
5405 00:43:30.739089 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5406 00:43:30.741751 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5407 00:43:30.741880 == TX Byte 1 ==
5408 00:43:30.749019 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5409 00:43:30.751849 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5410 00:43:30.751968
5411 00:43:30.752061 [DATLAT]
5412 00:43:30.755288 Freq=933, CH0 RK1
5413 00:43:30.755385
5414 00:43:30.755448 DATLAT Default: 0xb
5415 00:43:30.758932 0, 0xFFFF, sum = 0
5416 00:43:30.759034 1, 0xFFFF, sum = 0
5417 00:43:30.761862 2, 0xFFFF, sum = 0
5418 00:43:30.761970 3, 0xFFFF, sum = 0
5419 00:43:30.765386 4, 0xFFFF, sum = 0
5420 00:43:30.768410 5, 0xFFFF, sum = 0
5421 00:43:30.768491 6, 0xFFFF, sum = 0
5422 00:43:30.771810 7, 0xFFFF, sum = 0
5423 00:43:30.771913 8, 0xFFFF, sum = 0
5424 00:43:30.775172 9, 0xFFFF, sum = 0
5425 00:43:30.775276 10, 0x0, sum = 1
5426 00:43:30.778407 11, 0x0, sum = 2
5427 00:43:30.778485 12, 0x0, sum = 3
5428 00:43:30.778550 13, 0x0, sum = 4
5429 00:43:30.781799 best_step = 11
5430 00:43:30.781876
5431 00:43:30.781945 ==
5432 00:43:30.785235 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 00:43:30.788707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 00:43:30.788799 ==
5435 00:43:30.792352 RX Vref Scan: 0
5436 00:43:30.792432
5437 00:43:30.792501 RX Vref 0 -> 0, step: 1
5438 00:43:30.794858
5439 00:43:30.794961 RX Delay -45 -> 252, step: 4
5440 00:43:30.802206 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5441 00:43:30.805991 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5442 00:43:30.809195 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5443 00:43:30.812398 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5444 00:43:30.815641 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5445 00:43:30.822685 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5446 00:43:30.825399 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5447 00:43:30.828888 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5448 00:43:30.832285 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5449 00:43:30.835742 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5450 00:43:30.842025 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5451 00:43:30.845469 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5452 00:43:30.848646 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5453 00:43:30.851932 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5454 00:43:30.855760 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5455 00:43:30.862292 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5456 00:43:30.862400 ==
5457 00:43:30.865456 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 00:43:30.868809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 00:43:30.868898 ==
5460 00:43:30.868963 DQS Delay:
5461 00:43:30.872269 DQS0 = 0, DQS1 = 0
5462 00:43:30.872370 DQM Delay:
5463 00:43:30.875704 DQM0 = 104, DQM1 = 94
5464 00:43:30.875823 DQ Delay:
5465 00:43:30.878552 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =102
5466 00:43:30.881896 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5467 00:43:30.885173 DQ8 =86, DQ9 =82, DQ10 =96, DQ11 =86
5468 00:43:30.888658 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5469 00:43:30.888762
5470 00:43:30.888831
5471 00:43:30.898815 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5472 00:43:30.902001 CH0 RK1: MR19=505, MR18=2801
5473 00:43:30.905343 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5474 00:43:30.908729 [RxdqsGatingPostProcess] freq 933
5475 00:43:30.915495 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5476 00:43:30.918551 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 00:43:30.922357 best DQS1 dly(2T, 0.5T) = (0, 11)
5478 00:43:30.925440 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 00:43:30.928638 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5480 00:43:30.931943 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 00:43:30.935218 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 00:43:30.938464 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 00:43:30.941729 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 00:43:30.941823 Pre-setting of DQS Precalculation
5485 00:43:30.948566 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5486 00:43:30.948666 ==
5487 00:43:30.952452 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 00:43:30.955119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 00:43:30.955203 ==
5490 00:43:30.962404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5491 00:43:30.968359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5492 00:43:30.972351 [CA 0] Center 36 (6~67) winsize 62
5493 00:43:30.975086 [CA 1] Center 37 (6~68) winsize 63
5494 00:43:30.978411 [CA 2] Center 35 (5~65) winsize 61
5495 00:43:30.981625 [CA 3] Center 34 (4~65) winsize 62
5496 00:43:30.984965 [CA 4] Center 34 (4~64) winsize 61
5497 00:43:30.988973 [CA 5] Center 33 (3~64) winsize 62
5498 00:43:30.989056
5499 00:43:30.991670 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5500 00:43:30.991750
5501 00:43:30.995010 [CATrainingPosCal] consider 1 rank data
5502 00:43:30.998621 u2DelayCellTimex100 = 270/100 ps
5503 00:43:31.001796 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 00:43:31.005030 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5505 00:43:31.008510 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5506 00:43:31.011847 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 00:43:31.015429 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5508 00:43:31.018441 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5509 00:43:31.018537
5510 00:43:31.025204 CA PerBit enable=1, Macro0, CA PI delay=33
5511 00:43:31.025290
5512 00:43:31.025355 [CBTSetCACLKResult] CA Dly = 33
5513 00:43:31.028600 CS Dly: 7 (0~38)
5514 00:43:31.028673 ==
5515 00:43:31.031838 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 00:43:31.034870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 00:43:31.034968 ==
5518 00:43:31.041666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 00:43:31.048253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5520 00:43:31.051402 [CA 0] Center 36 (6~67) winsize 62
5521 00:43:31.054616 [CA 1] Center 37 (6~68) winsize 63
5522 00:43:31.058229 [CA 2] Center 35 (5~65) winsize 61
5523 00:43:31.061276 [CA 3] Center 34 (4~65) winsize 62
5524 00:43:31.064600 [CA 4] Center 34 (4~65) winsize 62
5525 00:43:31.067987 [CA 5] Center 33 (3~64) winsize 62
5526 00:43:31.068087
5527 00:43:31.071418 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5528 00:43:31.071516
5529 00:43:31.074742 [CATrainingPosCal] consider 2 rank data
5530 00:43:31.078193 u2DelayCellTimex100 = 270/100 ps
5531 00:43:31.080965 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 00:43:31.084271 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5533 00:43:31.087995 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5534 00:43:31.091277 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5535 00:43:31.094735 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5536 00:43:31.101466 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 00:43:31.101556
5538 00:43:31.104510 CA PerBit enable=1, Macro0, CA PI delay=33
5539 00:43:31.104593
5540 00:43:31.107827 [CBTSetCACLKResult] CA Dly = 33
5541 00:43:31.107911 CS Dly: 8 (0~40)
5542 00:43:31.107975
5543 00:43:31.110952 ----->DramcWriteLeveling(PI) begin...
5544 00:43:31.111036 ==
5545 00:43:31.114932 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 00:43:31.117701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 00:43:31.120899 ==
5548 00:43:31.120982 Write leveling (Byte 0): 30 => 30
5549 00:43:31.124825 Write leveling (Byte 1): 29 => 29
5550 00:43:31.127625 DramcWriteLeveling(PI) end<-----
5551 00:43:31.127704
5552 00:43:31.127794 ==
5553 00:43:31.131000 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 00:43:31.137658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 00:43:31.137769 ==
5556 00:43:31.140964 [Gating] SW mode calibration
5557 00:43:31.148094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 00:43:31.150800 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5559 00:43:31.157841 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 00:43:31.161226 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 00:43:31.164564 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 00:43:31.170875 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 00:43:31.174459 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 00:43:31.177979 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 00:43:31.184244 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (0 1)
5566 00:43:31.187744 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5567 00:43:31.190941 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 00:43:31.197815 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 00:43:31.200619 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 00:43:31.203966 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 00:43:31.207240 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 00:43:31.214160 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 00:43:31.217182 0 15 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5574 00:43:31.220910 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5575 00:43:31.227509 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 00:43:31.230724 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 00:43:31.234009 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 00:43:31.240853 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 00:43:31.244280 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 00:43:31.247787 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 00:43:31.254213 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5582 00:43:31.257220 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5583 00:43:31.260882 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:43:31.267556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:43:31.270681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:43:31.274103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:43:31.280839 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:43:31.284791 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:43:31.287554 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 00:43:31.290751 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 00:43:31.297753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 00:43:31.300920 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 00:43:31.304074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 00:43:31.310842 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:43:31.314165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:43:31.317432 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:43:31.324388 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5598 00:43:31.327488 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5599 00:43:31.330591 Total UI for P1: 0, mck2ui 16
5600 00:43:31.333879 best dqsien dly found for B1: ( 1, 2, 24)
5601 00:43:31.337115 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 00:43:31.340585 Total UI for P1: 0, mck2ui 16
5603 00:43:31.343952 best dqsien dly found for B0: ( 1, 2, 26)
5604 00:43:31.347263 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5605 00:43:31.350681 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5606 00:43:31.350792
5607 00:43:31.357293 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5608 00:43:31.360689 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 00:43:31.363981 [Gating] SW calibration Done
5610 00:43:31.364089 ==
5611 00:43:31.367158 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 00:43:31.370215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 00:43:31.370296 ==
5614 00:43:31.370362 RX Vref Scan: 0
5615 00:43:31.370423
5616 00:43:31.373814 RX Vref 0 -> 0, step: 1
5617 00:43:31.373922
5618 00:43:31.377288 RX Delay -80 -> 252, step: 8
5619 00:43:31.380449 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5620 00:43:31.384209 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5621 00:43:31.387281 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5622 00:43:31.394010 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5623 00:43:31.397058 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5624 00:43:31.400305 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5625 00:43:31.403740 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5626 00:43:31.407053 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5627 00:43:31.410204 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5628 00:43:31.416841 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5629 00:43:31.420185 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 00:43:31.423560 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5631 00:43:31.426583 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5632 00:43:31.430483 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5633 00:43:31.436759 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5634 00:43:31.439999 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5635 00:43:31.440109 ==
5636 00:43:31.443175 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 00:43:31.446589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 00:43:31.446704 ==
5639 00:43:31.450043 DQS Delay:
5640 00:43:31.450149 DQS0 = 0, DQS1 = 0
5641 00:43:31.450240 DQM Delay:
5642 00:43:31.453312 DQM0 = 103, DQM1 = 98
5643 00:43:31.453415 DQ Delay:
5644 00:43:31.456683 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5645 00:43:31.459937 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5646 00:43:31.463309 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5647 00:43:31.466627 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5648 00:43:31.466731
5649 00:43:31.469969
5650 00:43:31.470074 ==
5651 00:43:31.473466 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 00:43:31.476665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 00:43:31.476760 ==
5654 00:43:31.476824
5655 00:43:31.476884
5656 00:43:31.479895 TX Vref Scan disable
5657 00:43:31.479995 == TX Byte 0 ==
5658 00:43:31.486613 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5659 00:43:31.489686 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5660 00:43:31.489797 == TX Byte 1 ==
5661 00:43:31.496180 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5662 00:43:31.499746 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5663 00:43:31.499825 ==
5664 00:43:31.503250 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 00:43:31.506366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 00:43:31.506473 ==
5667 00:43:31.506565
5668 00:43:31.506656
5669 00:43:31.509978 TX Vref Scan disable
5670 00:43:31.513304 == TX Byte 0 ==
5671 00:43:31.516467 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5672 00:43:31.519680 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5673 00:43:31.522837 == TX Byte 1 ==
5674 00:43:31.526240 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5675 00:43:31.529646 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5676 00:43:31.529754
5677 00:43:31.532936 [DATLAT]
5678 00:43:31.533040 Freq=933, CH1 RK0
5679 00:43:31.533132
5680 00:43:31.536618 DATLAT Default: 0xd
5681 00:43:31.536697 0, 0xFFFF, sum = 0
5682 00:43:31.539846 1, 0xFFFF, sum = 0
5683 00:43:31.539935 2, 0xFFFF, sum = 0
5684 00:43:31.542963 3, 0xFFFF, sum = 0
5685 00:43:31.543072 4, 0xFFFF, sum = 0
5686 00:43:31.546266 5, 0xFFFF, sum = 0
5687 00:43:31.546382 6, 0xFFFF, sum = 0
5688 00:43:31.550030 7, 0xFFFF, sum = 0
5689 00:43:31.550116 8, 0xFFFF, sum = 0
5690 00:43:31.553322 9, 0xFFFF, sum = 0
5691 00:43:31.553405 10, 0x0, sum = 1
5692 00:43:31.556675 11, 0x0, sum = 2
5693 00:43:31.556758 12, 0x0, sum = 3
5694 00:43:31.559913 13, 0x0, sum = 4
5695 00:43:31.560023 best_step = 11
5696 00:43:31.560115
5697 00:43:31.560202 ==
5698 00:43:31.563322 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 00:43:31.566502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 00:43:31.569293 ==
5701 00:43:31.569375 RX Vref Scan: 1
5702 00:43:31.569439
5703 00:43:31.572775 RX Vref 0 -> 0, step: 1
5704 00:43:31.572857
5705 00:43:31.575932 RX Delay -45 -> 252, step: 4
5706 00:43:31.576013
5707 00:43:31.579362 Set Vref, RX VrefLevel [Byte0]: 52
5708 00:43:31.579444 [Byte1]: 54
5709 00:43:31.584711
5710 00:43:31.584827 Final RX Vref Byte 0 = 52 to rank0
5711 00:43:31.587987 Final RX Vref Byte 1 = 54 to rank0
5712 00:43:31.591289 Final RX Vref Byte 0 = 52 to rank1
5713 00:43:31.594415 Final RX Vref Byte 1 = 54 to rank1==
5714 00:43:31.597914 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 00:43:31.604714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 00:43:31.604797 ==
5717 00:43:31.604862 DQS Delay:
5718 00:43:31.604921 DQS0 = 0, DQS1 = 0
5719 00:43:31.608066 DQM Delay:
5720 00:43:31.608147 DQM0 = 103, DQM1 = 99
5721 00:43:31.610865 DQ Delay:
5722 00:43:31.614737 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5723 00:43:31.617951 DQ4 =104, DQ5 =114, DQ6 =112, DQ7 =102
5724 00:43:31.621047 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5725 00:43:31.624539 DQ12 =104, DQ13 =106, DQ14 =110, DQ15 =106
5726 00:43:31.624647
5727 00:43:31.624739
5728 00:43:31.630788 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5729 00:43:31.634294 CH1 RK0: MR19=505, MR18=172F
5730 00:43:31.640632 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5731 00:43:31.640722
5732 00:43:31.644586 ----->DramcWriteLeveling(PI) begin...
5733 00:43:31.644675 ==
5734 00:43:31.647779 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 00:43:31.651056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 00:43:31.654211 ==
5737 00:43:31.654296 Write leveling (Byte 0): 27 => 27
5738 00:43:31.657599 Write leveling (Byte 1): 29 => 29
5739 00:43:31.660916 DramcWriteLeveling(PI) end<-----
5740 00:43:31.660999
5741 00:43:31.661062 ==
5742 00:43:31.664253 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 00:43:31.670982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 00:43:31.671065 ==
5745 00:43:31.671129 [Gating] SW mode calibration
5746 00:43:31.680946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 00:43:31.683752 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 00:43:31.687222 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 00:43:31.693863 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 00:43:31.697690 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 00:43:31.701213 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 00:43:31.707634 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 00:43:31.710922 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 00:43:31.714001 0 14 24 | B1->B0 | 3030 3434 | 1 0 | (0 1) (0 1)
5755 00:43:31.720739 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5756 00:43:31.723859 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 00:43:31.727296 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 00:43:31.733912 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 00:43:31.736965 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 00:43:31.740758 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 00:43:31.747308 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5762 00:43:31.750520 0 15 24 | B1->B0 | 3939 2828 | 0 0 | (0 0) (0 0)
5763 00:43:31.753810 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5764 00:43:31.760383 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 00:43:31.764007 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 00:43:31.767157 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 00:43:31.773699 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 00:43:31.777037 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 00:43:31.780985 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5770 00:43:31.787068 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5771 00:43:31.790406 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 00:43:31.793679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 00:43:31.800246 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:43:31.803576 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:43:31.807246 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:43:31.810636 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:43:31.817050 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 00:43:31.820445 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 00:43:31.823790 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 00:43:31.830310 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 00:43:31.833810 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 00:43:31.836973 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 00:43:31.843854 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:43:31.846702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:43:31.850082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:43:31.857257 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5787 00:43:31.860158 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5788 00:43:31.863789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 00:43:31.866845 Total UI for P1: 0, mck2ui 16
5790 00:43:31.869899 best dqsien dly found for B0: ( 1, 2, 28)
5791 00:43:31.873271 Total UI for P1: 0, mck2ui 16
5792 00:43:31.876786 best dqsien dly found for B1: ( 1, 2, 26)
5793 00:43:31.879658 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5794 00:43:31.883183 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5795 00:43:31.883291
5796 00:43:31.889593 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5797 00:43:31.893644 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5798 00:43:31.896312 [Gating] SW calibration Done
5799 00:43:31.896407 ==
5800 00:43:31.899822 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 00:43:31.902977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 00:43:31.903058 ==
5803 00:43:31.903120 RX Vref Scan: 0
5804 00:43:31.903179
5805 00:43:31.906304 RX Vref 0 -> 0, step: 1
5806 00:43:31.906377
5807 00:43:31.910305 RX Delay -80 -> 252, step: 8
5808 00:43:31.913349 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5809 00:43:31.916555 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5810 00:43:31.920067 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5811 00:43:31.926405 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5812 00:43:31.929790 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5813 00:43:31.933135 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5814 00:43:31.936724 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5815 00:43:31.940033 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5816 00:43:31.943318 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5817 00:43:31.949464 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5818 00:43:31.952790 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5819 00:43:31.956283 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5820 00:43:31.959671 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5821 00:43:31.962934 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5822 00:43:31.969380 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5823 00:43:31.973034 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5824 00:43:31.973139 ==
5825 00:43:31.976448 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 00:43:31.979329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 00:43:31.979433 ==
5828 00:43:31.979530 DQS Delay:
5829 00:43:31.983195 DQS0 = 0, DQS1 = 0
5830 00:43:31.983272 DQM Delay:
5831 00:43:31.986320 DQM0 = 102, DQM1 = 98
5832 00:43:31.986421 DQ Delay:
5833 00:43:31.989341 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5834 00:43:31.992900 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5835 00:43:31.995813 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5836 00:43:31.999556 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5837 00:43:31.999631
5838 00:43:31.999693
5839 00:43:32.002433 ==
5840 00:43:32.002555 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 00:43:32.009003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 00:43:32.009148 ==
5843 00:43:32.009224
5844 00:43:32.009288
5845 00:43:32.012264 TX Vref Scan disable
5846 00:43:32.012401 == TX Byte 0 ==
5847 00:43:32.016304 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5848 00:43:32.022703 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5849 00:43:32.022831 == TX Byte 1 ==
5850 00:43:32.025612 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5851 00:43:32.032401 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5852 00:43:32.032527 ==
5853 00:43:32.035707 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 00:43:32.039015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 00:43:32.039128 ==
5856 00:43:32.039224
5857 00:43:32.039310
5858 00:43:32.042235 TX Vref Scan disable
5859 00:43:32.045644 == TX Byte 0 ==
5860 00:43:32.048976 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5861 00:43:32.052309 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5862 00:43:32.055661 == TX Byte 1 ==
5863 00:43:32.059115 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5864 00:43:32.062743 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5865 00:43:32.062823
5866 00:43:32.062886 [DATLAT]
5867 00:43:32.065934 Freq=933, CH1 RK1
5868 00:43:32.066010
5869 00:43:32.066072 DATLAT Default: 0xb
5870 00:43:32.069289 0, 0xFFFF, sum = 0
5871 00:43:32.072638 1, 0xFFFF, sum = 0
5872 00:43:32.072715 2, 0xFFFF, sum = 0
5873 00:43:32.075362 3, 0xFFFF, sum = 0
5874 00:43:32.075439 4, 0xFFFF, sum = 0
5875 00:43:32.078662 5, 0xFFFF, sum = 0
5876 00:43:32.078764 6, 0xFFFF, sum = 0
5877 00:43:32.081943 7, 0xFFFF, sum = 0
5878 00:43:32.082024 8, 0xFFFF, sum = 0
5879 00:43:32.085666 9, 0xFFFF, sum = 0
5880 00:43:32.085746 10, 0x0, sum = 1
5881 00:43:32.088537 11, 0x0, sum = 2
5882 00:43:32.088618 12, 0x0, sum = 3
5883 00:43:32.092079 13, 0x0, sum = 4
5884 00:43:32.092158 best_step = 11
5885 00:43:32.092221
5886 00:43:32.092283 ==
5887 00:43:32.095389 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 00:43:32.098627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 00:43:32.102246 ==
5890 00:43:32.102358 RX Vref Scan: 0
5891 00:43:32.102453
5892 00:43:32.105561 RX Vref 0 -> 0, step: 1
5893 00:43:32.105636
5894 00:43:32.108705 RX Delay -45 -> 252, step: 4
5895 00:43:32.111919 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5896 00:43:32.114949 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5897 00:43:32.118637 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5898 00:43:32.125166 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5899 00:43:32.128786 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5900 00:43:32.131914 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5901 00:43:32.135415 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5902 00:43:32.138317 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5903 00:43:32.145460 iDelay=199, Bit 8, Center 88 (3 ~ 174) 172
5904 00:43:32.148859 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5905 00:43:32.151548 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5906 00:43:32.155521 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5907 00:43:32.158251 iDelay=199, Bit 12, Center 110 (23 ~ 198) 176
5908 00:43:32.164970 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5909 00:43:32.168508 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5910 00:43:32.171895 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5911 00:43:32.171970 ==
5912 00:43:32.175236 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 00:43:32.178573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 00:43:32.178648 ==
5915 00:43:32.181832 DQS Delay:
5916 00:43:32.181902 DQS0 = 0, DQS1 = 0
5917 00:43:32.185221 DQM Delay:
5918 00:43:32.185298 DQM0 = 104, DQM1 = 99
5919 00:43:32.185359 DQ Delay:
5920 00:43:32.188671 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5921 00:43:32.195251 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5922 00:43:32.198455 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =94
5923 00:43:32.201388 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5924 00:43:32.201465
5925 00:43:32.201528
5926 00:43:32.208374 [DQSOSCAuto] RK1, (LSB)MR18= 0x3002, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5927 00:43:32.211336 CH1 RK1: MR19=505, MR18=3002
5928 00:43:32.218630 CH1_RK1: MR19=0x505, MR18=0x3002, DQSOSC=406, MR23=63, INC=65, DEC=43
5929 00:43:32.221266 [RxdqsGatingPostProcess] freq 933
5930 00:43:32.224664 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5931 00:43:32.228469 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 00:43:32.231766 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 00:43:32.234786 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 00:43:32.238579 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 00:43:32.241614 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 00:43:32.244843 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 00:43:32.248098 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 00:43:32.251422 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 00:43:32.254867 Pre-setting of DQS Precalculation
5940 00:43:32.258523 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5941 00:43:32.267914 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5942 00:43:32.274575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5943 00:43:32.274660
5944 00:43:32.274727
5945 00:43:32.278112 [Calibration Summary] 1866 Mbps
5946 00:43:32.278188 CH 0, Rank 0
5947 00:43:32.281274 SW Impedance : PASS
5948 00:43:32.281345 DUTY Scan : NO K
5949 00:43:32.284656 ZQ Calibration : PASS
5950 00:43:32.287933 Jitter Meter : NO K
5951 00:43:32.288038 CBT Training : PASS
5952 00:43:32.291398 Write leveling : PASS
5953 00:43:32.294687 RX DQS gating : PASS
5954 00:43:32.294779 RX DQ/DQS(RDDQC) : PASS
5955 00:43:32.298040 TX DQ/DQS : PASS
5956 00:43:32.301346 RX DATLAT : PASS
5957 00:43:32.301432 RX DQ/DQS(Engine): PASS
5958 00:43:32.304925 TX OE : NO K
5959 00:43:32.305004 All Pass.
5960 00:43:32.305067
5961 00:43:32.307825 CH 0, Rank 1
5962 00:43:32.307928 SW Impedance : PASS
5963 00:43:32.311034 DUTY Scan : NO K
5964 00:43:32.314772 ZQ Calibration : PASS
5965 00:43:32.314855 Jitter Meter : NO K
5966 00:43:32.317693 CBT Training : PASS
5967 00:43:32.317775 Write leveling : PASS
5968 00:43:32.321021 RX DQS gating : PASS
5969 00:43:32.324679 RX DQ/DQS(RDDQC) : PASS
5970 00:43:32.324761 TX DQ/DQS : PASS
5971 00:43:32.328110 RX DATLAT : PASS
5972 00:43:32.331351 RX DQ/DQS(Engine): PASS
5973 00:43:32.331432 TX OE : NO K
5974 00:43:32.334666 All Pass.
5975 00:43:32.334749
5976 00:43:32.334813 CH 1, Rank 0
5977 00:43:32.338035 SW Impedance : PASS
5978 00:43:32.338117 DUTY Scan : NO K
5979 00:43:32.341570 ZQ Calibration : PASS
5980 00:43:32.344756 Jitter Meter : NO K
5981 00:43:32.344869 CBT Training : PASS
5982 00:43:32.347483 Write leveling : PASS
5983 00:43:32.351371 RX DQS gating : PASS
5984 00:43:32.351476 RX DQ/DQS(RDDQC) : PASS
5985 00:43:32.354434 TX DQ/DQS : PASS
5986 00:43:32.357618 RX DATLAT : PASS
5987 00:43:32.357720 RX DQ/DQS(Engine): PASS
5988 00:43:32.360853 TX OE : NO K
5989 00:43:32.360956 All Pass.
5990 00:43:32.361050
5991 00:43:32.364139 CH 1, Rank 1
5992 00:43:32.364242 SW Impedance : PASS
5993 00:43:32.367922 DUTY Scan : NO K
5994 00:43:32.368038 ZQ Calibration : PASS
5995 00:43:32.370990 Jitter Meter : NO K
5996 00:43:32.374192 CBT Training : PASS
5997 00:43:32.374371 Write leveling : PASS
5998 00:43:32.377626 RX DQS gating : PASS
5999 00:43:32.380842 RX DQ/DQS(RDDQC) : PASS
6000 00:43:32.380979 TX DQ/DQS : PASS
6001 00:43:32.384414 RX DATLAT : PASS
6002 00:43:32.387196 RX DQ/DQS(Engine): PASS
6003 00:43:32.387337 TX OE : NO K
6004 00:43:32.390700 All Pass.
6005 00:43:32.390817
6006 00:43:32.390923 DramC Write-DBI off
6007 00:43:32.394018 PER_BANK_REFRESH: Hybrid Mode
6008 00:43:32.394139 TX_TRACKING: ON
6009 00:43:32.404116 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6010 00:43:32.407483 [FAST_K] Save calibration result to emmc
6011 00:43:32.410833 dramc_set_vcore_voltage set vcore to 650000
6012 00:43:32.414076 Read voltage for 400, 6
6013 00:43:32.414183 Vio18 = 0
6014 00:43:32.417437 Vcore = 650000
6015 00:43:32.417516 Vdram = 0
6016 00:43:32.417582 Vddq = 0
6017 00:43:32.420811 Vmddr = 0
6018 00:43:32.424111 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6019 00:43:32.430970 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6020 00:43:32.431079 MEM_TYPE=3, freq_sel=20
6021 00:43:32.434144 sv_algorithm_assistance_LP4_800
6022 00:43:32.440482 ============ PULL DRAM RESETB DOWN ============
6023 00:43:32.443890 ========== PULL DRAM RESETB DOWN end =========
6024 00:43:32.447275 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6025 00:43:32.450658 ===================================
6026 00:43:32.453993 LPDDR4 DRAM CONFIGURATION
6027 00:43:32.457407 ===================================
6028 00:43:32.457496 EX_ROW_EN[0] = 0x0
6029 00:43:32.460669 EX_ROW_EN[1] = 0x0
6030 00:43:32.463952 LP4Y_EN = 0x0
6031 00:43:32.464058 WORK_FSP = 0x0
6032 00:43:32.467319 WL = 0x2
6033 00:43:32.467396 RL = 0x2
6034 00:43:32.470530 BL = 0x2
6035 00:43:32.470632 RPST = 0x0
6036 00:43:32.473969 RD_PRE = 0x0
6037 00:43:32.474044 WR_PRE = 0x1
6038 00:43:32.477487 WR_PST = 0x0
6039 00:43:32.477591 DBI_WR = 0x0
6040 00:43:32.480804 DBI_RD = 0x0
6041 00:43:32.480885 OTF = 0x1
6042 00:43:32.484248 ===================================
6043 00:43:32.487412 ===================================
6044 00:43:32.490535 ANA top config
6045 00:43:32.494203 ===================================
6046 00:43:32.494308 DLL_ASYNC_EN = 0
6047 00:43:32.497097 ALL_SLAVE_EN = 1
6048 00:43:32.500495 NEW_RANK_MODE = 1
6049 00:43:32.503993 DLL_IDLE_MODE = 1
6050 00:43:32.504100 LP45_APHY_COMB_EN = 1
6051 00:43:32.507330 TX_ODT_DIS = 1
6052 00:43:32.510829 NEW_8X_MODE = 1
6053 00:43:32.513669 ===================================
6054 00:43:32.516959 ===================================
6055 00:43:32.520721 data_rate = 800
6056 00:43:32.524077 CKR = 1
6057 00:43:32.526849 DQ_P2S_RATIO = 4
6058 00:43:32.530367 ===================================
6059 00:43:32.530448 CA_P2S_RATIO = 4
6060 00:43:32.533771 DQ_CA_OPEN = 0
6061 00:43:32.537060 DQ_SEMI_OPEN = 1
6062 00:43:32.540535 CA_SEMI_OPEN = 1
6063 00:43:32.543825 CA_FULL_RATE = 0
6064 00:43:32.546923 DQ_CKDIV4_EN = 0
6065 00:43:32.547004 CA_CKDIV4_EN = 1
6066 00:43:32.550671 CA_PREDIV_EN = 0
6067 00:43:32.553806 PH8_DLY = 0
6068 00:43:32.556943 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6069 00:43:32.560175 DQ_AAMCK_DIV = 0
6070 00:43:32.563504 CA_AAMCK_DIV = 0
6071 00:43:32.563599 CA_ADMCK_DIV = 4
6072 00:43:32.567057 DQ_TRACK_CA_EN = 0
6073 00:43:32.570318 CA_PICK = 800
6074 00:43:32.573652 CA_MCKIO = 400
6075 00:43:32.576921 MCKIO_SEMI = 400
6076 00:43:32.580199 PLL_FREQ = 3016
6077 00:43:32.583555 DQ_UI_PI_RATIO = 32
6078 00:43:32.583634 CA_UI_PI_RATIO = 32
6079 00:43:32.587057 ===================================
6080 00:43:32.590400 ===================================
6081 00:43:32.593148 memory_type:LPDDR4
6082 00:43:32.596514 GP_NUM : 10
6083 00:43:32.596634 SRAM_EN : 1
6084 00:43:32.599934 MD32_EN : 0
6085 00:43:32.603329 ===================================
6086 00:43:32.606771 [ANA_INIT] >>>>>>>>>>>>>>
6087 00:43:32.609886 <<<<<< [CONFIGURE PHASE]: ANA_TX
6088 00:43:32.613116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6089 00:43:32.616798 ===================================
6090 00:43:32.616870 data_rate = 800,PCW = 0X7400
6091 00:43:32.619892 ===================================
6092 00:43:32.623271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6093 00:43:32.629833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 00:43:32.642896 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 00:43:32.646427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6096 00:43:32.649757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6097 00:43:32.653210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6098 00:43:32.656730 [ANA_INIT] flow start
6099 00:43:32.656804 [ANA_INIT] PLL >>>>>>>>
6100 00:43:32.660026 [ANA_INIT] PLL <<<<<<<<
6101 00:43:32.662927 [ANA_INIT] MIDPI >>>>>>>>
6102 00:43:32.663025 [ANA_INIT] MIDPI <<<<<<<<
6103 00:43:32.666720 [ANA_INIT] DLL >>>>>>>>
6104 00:43:32.669720 [ANA_INIT] flow end
6105 00:43:32.673027 ============ LP4 DIFF to SE enter ============
6106 00:43:32.676166 ============ LP4 DIFF to SE exit ============
6107 00:43:32.679714 [ANA_INIT] <<<<<<<<<<<<<
6108 00:43:32.682972 [Flow] Enable top DCM control >>>>>
6109 00:43:32.686405 [Flow] Enable top DCM control <<<<<
6110 00:43:32.692537 Enable DLL master slave shuffle
6111 00:43:32.693065 ==============================================================
6112 00:43:32.696554 Gating Mode config
6113 00:43:32.702734 ==============================================================
6114 00:43:32.702817 Config description:
6115 00:43:32.713019 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6116 00:43:32.719793 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6117 00:43:32.726282 SELPH_MODE 0: By rank 1: By Phase
6118 00:43:32.729708 ==============================================================
6119 00:43:32.732890 GAT_TRACK_EN = 0
6120 00:43:32.736179 RX_GATING_MODE = 2
6121 00:43:32.739257 RX_GATING_TRACK_MODE = 2
6122 00:43:32.742991 SELPH_MODE = 1
6123 00:43:32.746133 PICG_EARLY_EN = 1
6124 00:43:32.749271 VALID_LAT_VALUE = 1
6125 00:43:32.752720 ==============================================================
6126 00:43:32.756168 Enter into Gating configuration >>>>
6127 00:43:32.759664 Exit from Gating configuration <<<<
6128 00:43:32.763008 Enter into DVFS_PRE_config >>>>>
6129 00:43:32.775921 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6130 00:43:32.776025 Exit from DVFS_PRE_config <<<<<
6131 00:43:32.779613 Enter into PICG configuration >>>>
6132 00:43:32.782680 Exit from PICG configuration <<<<
6133 00:43:32.785772 [RX_INPUT] configuration >>>>>
6134 00:43:32.789447 [RX_INPUT] configuration <<<<<
6135 00:43:32.796132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6136 00:43:32.799505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6137 00:43:32.805807 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 00:43:32.812606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 00:43:32.819454 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 00:43:32.826183 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 00:43:32.828755 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6142 00:43:32.832108 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6143 00:43:32.835549 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6144 00:43:32.842340 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6145 00:43:32.845618 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6146 00:43:32.849076 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 00:43:32.852240 ===================================
6148 00:43:32.855277 LPDDR4 DRAM CONFIGURATION
6149 00:43:32.859233 ===================================
6150 00:43:32.862307 EX_ROW_EN[0] = 0x0
6151 00:43:32.862383 EX_ROW_EN[1] = 0x0
6152 00:43:32.865565 LP4Y_EN = 0x0
6153 00:43:32.865639 WORK_FSP = 0x0
6154 00:43:32.868835 WL = 0x2
6155 00:43:32.868911 RL = 0x2
6156 00:43:32.872140 BL = 0x2
6157 00:43:32.872246 RPST = 0x0
6158 00:43:32.875365 RD_PRE = 0x0
6159 00:43:32.875469 WR_PRE = 0x1
6160 00:43:32.878773 WR_PST = 0x0
6161 00:43:32.878870 DBI_WR = 0x0
6162 00:43:32.882032 DBI_RD = 0x0
6163 00:43:32.882107 OTF = 0x1
6164 00:43:32.885860 ===================================
6165 00:43:32.888489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6166 00:43:32.895410 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6167 00:43:32.899041 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 00:43:32.902493 ===================================
6169 00:43:32.905551 LPDDR4 DRAM CONFIGURATION
6170 00:43:32.908694 ===================================
6171 00:43:32.908784 EX_ROW_EN[0] = 0x10
6172 00:43:32.912201 EX_ROW_EN[1] = 0x0
6173 00:43:32.915648 LP4Y_EN = 0x0
6174 00:43:32.915730 WORK_FSP = 0x0
6175 00:43:32.919120 WL = 0x2
6176 00:43:32.919217 RL = 0x2
6177 00:43:32.922377 BL = 0x2
6178 00:43:32.922474 RPST = 0x0
6179 00:43:32.925156 RD_PRE = 0x0
6180 00:43:32.925253 WR_PRE = 0x1
6181 00:43:32.928693 WR_PST = 0x0
6182 00:43:32.928775 DBI_WR = 0x0
6183 00:43:32.932171 DBI_RD = 0x0
6184 00:43:32.932253 OTF = 0x1
6185 00:43:32.935436 ===================================
6186 00:43:32.942026 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6187 00:43:32.946037 nWR fixed to 30
6188 00:43:32.949930 [ModeRegInit_LP4] CH0 RK0
6189 00:43:32.950038 [ModeRegInit_LP4] CH0 RK1
6190 00:43:32.952756 [ModeRegInit_LP4] CH1 RK0
6191 00:43:32.956242 [ModeRegInit_LP4] CH1 RK1
6192 00:43:32.956354 match AC timing 19
6193 00:43:32.963208 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6194 00:43:32.966631 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6195 00:43:32.969960 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6196 00:43:32.976742 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6197 00:43:32.980057 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6198 00:43:32.980193 ==
6199 00:43:32.983034 Dram Type= 6, Freq= 0, CH_0, rank 0
6200 00:43:32.986374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6201 00:43:32.986449 ==
6202 00:43:32.992891 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6203 00:43:32.999544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6204 00:43:33.002928 [CA 0] Center 36 (8~64) winsize 57
6205 00:43:33.006362 [CA 1] Center 36 (8~64) winsize 57
6206 00:43:33.006443 [CA 2] Center 36 (8~64) winsize 57
6207 00:43:33.009914 [CA 3] Center 36 (8~64) winsize 57
6208 00:43:33.013057 [CA 4] Center 36 (8~64) winsize 57
6209 00:43:33.016565 [CA 5] Center 36 (8~64) winsize 57
6210 00:43:33.016647
6211 00:43:33.019617 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6212 00:43:33.019698
6213 00:43:33.025981 [CATrainingPosCal] consider 1 rank data
6214 00:43:33.026094 u2DelayCellTimex100 = 270/100 ps
6215 00:43:33.032804 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 00:43:33.036107 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 00:43:33.039301 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 00:43:33.042819 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 00:43:33.045977 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 00:43:33.049472 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 00:43:33.049552
6222 00:43:33.052785 CA PerBit enable=1, Macro0, CA PI delay=36
6223 00:43:33.052932
6224 00:43:33.055964 [CBTSetCACLKResult] CA Dly = 36
6225 00:43:33.059435 CS Dly: 1 (0~32)
6226 00:43:33.059515 ==
6227 00:43:33.062921 Dram Type= 6, Freq= 0, CH_0, rank 1
6228 00:43:33.066154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 00:43:33.066251 ==
6230 00:43:33.072733 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 00:43:33.076134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6232 00:43:33.079447 [CA 0] Center 36 (8~64) winsize 57
6233 00:43:33.082775 [CA 1] Center 36 (8~64) winsize 57
6234 00:43:33.086096 [CA 2] Center 36 (8~64) winsize 57
6235 00:43:33.089251 [CA 3] Center 36 (8~64) winsize 57
6236 00:43:33.092502 [CA 4] Center 36 (8~64) winsize 57
6237 00:43:33.095830 [CA 5] Center 36 (8~64) winsize 57
6238 00:43:33.095931
6239 00:43:33.099235 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6240 00:43:33.099338
6241 00:43:33.102897 [CATrainingPosCal] consider 2 rank data
6242 00:43:33.105638 u2DelayCellTimex100 = 270/100 ps
6243 00:43:33.109032 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 00:43:33.112406 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 00:43:33.115754 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 00:43:33.122552 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 00:43:33.126044 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 00:43:33.129127 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 00:43:33.129208
6250 00:43:33.132892 CA PerBit enable=1, Macro0, CA PI delay=36
6251 00:43:33.132972
6252 00:43:33.136008 [CBTSetCACLKResult] CA Dly = 36
6253 00:43:33.136105 CS Dly: 1 (0~32)
6254 00:43:33.136174
6255 00:43:33.139100 ----->DramcWriteLeveling(PI) begin...
6256 00:43:33.139213 ==
6257 00:43:33.142651 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 00:43:33.148992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 00:43:33.149076 ==
6260 00:43:33.152232 Write leveling (Byte 0): 40 => 8
6261 00:43:33.152329 Write leveling (Byte 1): 40 => 8
6262 00:43:33.155628 DramcWriteLeveling(PI) end<-----
6263 00:43:33.155708
6264 00:43:33.155770 ==
6265 00:43:33.159630 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 00:43:33.165705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 00:43:33.165804 ==
6268 00:43:33.169071 [Gating] SW mode calibration
6269 00:43:33.175650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6270 00:43:33.179013 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6271 00:43:33.185687 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 00:43:33.189218 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 00:43:33.192531 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 00:43:33.199220 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 00:43:33.202180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 00:43:33.205889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 00:43:33.212687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 00:43:33.215374 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 00:43:33.218838 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 00:43:33.222150 Total UI for P1: 0, mck2ui 16
6281 00:43:33.225628 best dqsien dly found for B0: ( 0, 14, 24)
6282 00:43:33.229108 Total UI for P1: 0, mck2ui 16
6283 00:43:33.231941 best dqsien dly found for B1: ( 0, 14, 24)
6284 00:43:33.235375 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6285 00:43:33.238753 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6286 00:43:33.238833
6287 00:43:33.241959 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 00:43:33.248617 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 00:43:33.248700 [Gating] SW calibration Done
6290 00:43:33.248794 ==
6291 00:43:33.251941 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 00:43:33.258575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 00:43:33.258658 ==
6294 00:43:33.258722 RX Vref Scan: 0
6295 00:43:33.258781
6296 00:43:33.262419 RX Vref 0 -> 0, step: 1
6297 00:43:33.262525
6298 00:43:33.265349 RX Delay -410 -> 252, step: 16
6299 00:43:33.269051 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6300 00:43:33.272508 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6301 00:43:33.278966 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6302 00:43:33.282180 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6303 00:43:33.285545 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6304 00:43:33.289048 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6305 00:43:33.295275 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6306 00:43:33.298686 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6307 00:43:33.302112 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6308 00:43:33.305638 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6309 00:43:33.311729 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6310 00:43:33.315066 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6311 00:43:33.318921 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6312 00:43:33.321924 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6313 00:43:33.328698 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6314 00:43:33.331754 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6315 00:43:33.331837 ==
6316 00:43:33.335164 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 00:43:33.338548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 00:43:33.338629 ==
6319 00:43:33.341929 DQS Delay:
6320 00:43:33.342009 DQS0 = 27, DQS1 = 35
6321 00:43:33.345152 DQM Delay:
6322 00:43:33.345232 DQM0 = 11, DQM1 = 12
6323 00:43:33.345295 DQ Delay:
6324 00:43:33.348517 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6325 00:43:33.352020 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6326 00:43:33.355411 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6327 00:43:33.358998 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6328 00:43:33.359078
6329 00:43:33.359141
6330 00:43:33.359199 ==
6331 00:43:33.362247 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 00:43:33.364988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 00:43:33.368245 ==
6334 00:43:33.368325
6335 00:43:33.368410
6336 00:43:33.368471 TX Vref Scan disable
6337 00:43:33.372163 == TX Byte 0 ==
6338 00:43:33.375267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 00:43:33.378165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 00:43:33.381907 == TX Byte 1 ==
6341 00:43:33.384923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 00:43:33.388571 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 00:43:33.388651 ==
6344 00:43:33.391826 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 00:43:33.398419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 00:43:33.398500 ==
6347 00:43:33.398563
6348 00:43:33.398621
6349 00:43:33.398676 TX Vref Scan disable
6350 00:43:33.401525 == TX Byte 0 ==
6351 00:43:33.404912 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 00:43:33.408315 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 00:43:33.411700 == TX Byte 1 ==
6354 00:43:33.415115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 00:43:33.418671 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 00:43:33.418750
6357 00:43:33.421876 [DATLAT]
6358 00:43:33.421952 Freq=400, CH0 RK0
6359 00:43:33.422012
6360 00:43:33.425243 DATLAT Default: 0xf
6361 00:43:33.425315 0, 0xFFFF, sum = 0
6362 00:43:33.428644 1, 0xFFFF, sum = 0
6363 00:43:33.428721 2, 0xFFFF, sum = 0
6364 00:43:33.431257 3, 0xFFFF, sum = 0
6365 00:43:33.431331 4, 0xFFFF, sum = 0
6366 00:43:33.435304 5, 0xFFFF, sum = 0
6367 00:43:33.435404 6, 0xFFFF, sum = 0
6368 00:43:33.438168 7, 0xFFFF, sum = 0
6369 00:43:33.438239 8, 0xFFFF, sum = 0
6370 00:43:33.441798 9, 0xFFFF, sum = 0
6371 00:43:33.441898 10, 0xFFFF, sum = 0
6372 00:43:33.444981 11, 0xFFFF, sum = 0
6373 00:43:33.448435 12, 0xFFFF, sum = 0
6374 00:43:33.448538 13, 0x0, sum = 1
6375 00:43:33.448638 14, 0x0, sum = 2
6376 00:43:33.451766 15, 0x0, sum = 3
6377 00:43:33.451849 16, 0x0, sum = 4
6378 00:43:33.455074 best_step = 14
6379 00:43:33.455157
6380 00:43:33.455239 ==
6381 00:43:33.458432 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 00:43:33.461832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 00:43:33.461914 ==
6384 00:43:33.464557 RX Vref Scan: 1
6385 00:43:33.464640
6386 00:43:33.464722 RX Vref 0 -> 0, step: 1
6387 00:43:33.464800
6388 00:43:33.467943 RX Delay -311 -> 252, step: 8
6389 00:43:33.468028
6390 00:43:33.471351 Set Vref, RX VrefLevel [Byte0]: 56
6391 00:43:33.474758 [Byte1]: 47
6392 00:43:33.479500
6393 00:43:33.479582 Final RX Vref Byte 0 = 56 to rank0
6394 00:43:33.482915 Final RX Vref Byte 1 = 47 to rank0
6395 00:43:33.486390 Final RX Vref Byte 0 = 56 to rank1
6396 00:43:33.489812 Final RX Vref Byte 1 = 47 to rank1==
6397 00:43:33.492983 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 00:43:33.499264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 00:43:33.499371 ==
6400 00:43:33.499478 DQS Delay:
6401 00:43:33.502439 DQS0 = 28, DQS1 = 36
6402 00:43:33.502558 DQM Delay:
6403 00:43:33.502702 DQM0 = 11, DQM1 = 13
6404 00:43:33.505986 DQ Delay:
6405 00:43:33.509336 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6406 00:43:33.509418 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6407 00:43:33.513105 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6408 00:43:33.516145 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6409 00:43:33.516227
6410 00:43:33.519477
6411 00:43:33.525892 [DQSOSCAuto] RK0, (LSB)MR18= 0xd5c2, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6412 00:43:33.529403 CH0 RK0: MR19=C0C, MR18=D5C2
6413 00:43:33.536028 CH0_RK0: MR19=0xC0C, MR18=0xD5C2, DQSOSC=383, MR23=63, INC=402, DEC=268
6414 00:43:33.536137 ==
6415 00:43:33.539419 Dram Type= 6, Freq= 0, CH_0, rank 1
6416 00:43:33.542887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 00:43:33.542971 ==
6418 00:43:33.545963 [Gating] SW mode calibration
6419 00:43:33.552524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6420 00:43:33.556137 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6421 00:43:33.562423 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 00:43:33.566065 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 00:43:33.569380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 00:43:33.576092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 00:43:33.579356 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 00:43:33.582940 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 00:43:33.589395 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 00:43:33.592742 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 00:43:33.595609 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 00:43:33.599028 Total UI for P1: 0, mck2ui 16
6431 00:43:33.602435 best dqsien dly found for B0: ( 0, 14, 24)
6432 00:43:33.605682 Total UI for P1: 0, mck2ui 16
6433 00:43:33.609063 best dqsien dly found for B1: ( 0, 14, 24)
6434 00:43:33.612400 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6435 00:43:33.618844 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6436 00:43:33.618927
6437 00:43:33.622207 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 00:43:33.625478 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 00:43:33.629167 [Gating] SW calibration Done
6440 00:43:33.629290 ==
6441 00:43:33.632151 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 00:43:33.635980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 00:43:33.636083 ==
6444 00:43:33.636173 RX Vref Scan: 0
6445 00:43:33.636259
6446 00:43:33.638920 RX Vref 0 -> 0, step: 1
6447 00:43:33.639021
6448 00:43:33.642695 RX Delay -410 -> 252, step: 16
6449 00:43:33.645964 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6450 00:43:33.651986 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6451 00:43:33.655632 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6452 00:43:33.659269 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6453 00:43:33.662447 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6454 00:43:33.668769 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6455 00:43:33.671750 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6456 00:43:33.675414 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6457 00:43:33.678654 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6458 00:43:33.685397 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6459 00:43:33.688871 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6460 00:43:33.692329 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6461 00:43:33.695200 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6462 00:43:33.701977 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6463 00:43:33.705404 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6464 00:43:33.708842 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6465 00:43:33.708922 ==
6466 00:43:33.712131 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 00:43:33.715590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 00:43:33.719026 ==
6469 00:43:33.719105 DQS Delay:
6470 00:43:33.719190 DQS0 = 27, DQS1 = 35
6471 00:43:33.722261 DQM Delay:
6472 00:43:33.722342 DQM0 = 12, DQM1 = 12
6473 00:43:33.725664 DQ Delay:
6474 00:43:33.725743 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6475 00:43:33.728920 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6476 00:43:33.732288 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6477 00:43:33.735479 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6478 00:43:33.735557
6479 00:43:33.735654
6480 00:43:33.735732 ==
6481 00:43:33.738841 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 00:43:33.745503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 00:43:33.745585 ==
6484 00:43:33.745649
6485 00:43:33.745708
6486 00:43:33.745765 TX Vref Scan disable
6487 00:43:33.748840 == TX Byte 0 ==
6488 00:43:33.752175 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6489 00:43:33.755723 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6490 00:43:33.758583 == TX Byte 1 ==
6491 00:43:33.762077 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6492 00:43:33.765133 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6493 00:43:33.768946 ==
6494 00:43:33.769027 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 00:43:33.775076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 00:43:33.775158 ==
6497 00:43:33.775222
6498 00:43:33.775281
6499 00:43:33.778729 TX Vref Scan disable
6500 00:43:33.778811 == TX Byte 0 ==
6501 00:43:33.781668 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6502 00:43:33.788528 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6503 00:43:33.788625 == TX Byte 1 ==
6504 00:43:33.791501 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6505 00:43:33.795401 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6506 00:43:33.798835
6507 00:43:33.798943 [DATLAT]
6508 00:43:33.799034 Freq=400, CH0 RK1
6509 00:43:33.799128
6510 00:43:33.802094 DATLAT Default: 0xe
6511 00:43:33.802166 0, 0xFFFF, sum = 0
6512 00:43:33.805725 1, 0xFFFF, sum = 0
6513 00:43:33.805832 2, 0xFFFF, sum = 0
6514 00:43:33.808874 3, 0xFFFF, sum = 0
6515 00:43:33.808946 4, 0xFFFF, sum = 0
6516 00:43:33.811710 5, 0xFFFF, sum = 0
6517 00:43:33.811781 6, 0xFFFF, sum = 0
6518 00:43:33.814953 7, 0xFFFF, sum = 0
6519 00:43:33.815036 8, 0xFFFF, sum = 0
6520 00:43:33.818345 9, 0xFFFF, sum = 0
6521 00:43:33.821757 10, 0xFFFF, sum = 0
6522 00:43:33.821837 11, 0xFFFF, sum = 0
6523 00:43:33.825161 12, 0xFFFF, sum = 0
6524 00:43:33.825241 13, 0x0, sum = 1
6525 00:43:33.828452 14, 0x0, sum = 2
6526 00:43:33.828532 15, 0x0, sum = 3
6527 00:43:33.831660 16, 0x0, sum = 4
6528 00:43:33.831740 best_step = 14
6529 00:43:33.831803
6530 00:43:33.831861 ==
6531 00:43:33.834964 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 00:43:33.838368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 00:43:33.838448 ==
6534 00:43:33.841669 RX Vref Scan: 0
6535 00:43:33.841748
6536 00:43:33.841810 RX Vref 0 -> 0, step: 1
6537 00:43:33.844885
6538 00:43:33.845009 RX Delay -311 -> 252, step: 8
6539 00:43:33.853698 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6540 00:43:33.857086 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6541 00:43:33.859926 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6542 00:43:33.863501 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6543 00:43:33.870048 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6544 00:43:33.873370 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6545 00:43:33.876709 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6546 00:43:33.880120 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6547 00:43:33.887064 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6548 00:43:33.890275 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6549 00:43:33.893311 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6550 00:43:33.896900 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6551 00:43:33.903242 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6552 00:43:33.906796 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6553 00:43:33.909719 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6554 00:43:33.916525 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6555 00:43:33.916606 ==
6556 00:43:33.919764 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 00:43:33.923022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 00:43:33.923102 ==
6559 00:43:33.923165 DQS Delay:
6560 00:43:33.926703 DQS0 = 24, DQS1 = 36
6561 00:43:33.926783 DQM Delay:
6562 00:43:33.929931 DQM0 = 9, DQM1 = 13
6563 00:43:33.930010 DQ Delay:
6564 00:43:33.933424 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6565 00:43:33.936736 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6566 00:43:33.939975 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6567 00:43:33.943299 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6568 00:43:33.943379
6569 00:43:33.943441
6570 00:43:33.949753 [DQSOSCAuto] RK1, (LSB)MR18= 0xc161, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 385 ps
6571 00:43:33.952945 CH0 RK1: MR19=C0C, MR18=C161
6572 00:43:33.959740 CH0_RK1: MR19=0xC0C, MR18=0xC161, DQSOSC=385, MR23=63, INC=398, DEC=265
6573 00:43:33.963081 [RxdqsGatingPostProcess] freq 400
6574 00:43:33.969762 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6575 00:43:33.969858 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 00:43:33.973124 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 00:43:33.976275 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 00:43:33.979792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 00:43:33.983082 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 00:43:33.986427 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 00:43:33.989810 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 00:43:33.992529 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 00:43:33.995886 Pre-setting of DQS Precalculation
6584 00:43:33.999230 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6585 00:43:34.002488 ==
6586 00:43:34.005812 Dram Type= 6, Freq= 0, CH_1, rank 0
6587 00:43:34.009163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 00:43:34.009257 ==
6589 00:43:34.012945 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6590 00:43:34.019156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6591 00:43:34.022860 [CA 0] Center 36 (8~64) winsize 57
6592 00:43:34.025934 [CA 1] Center 36 (8~64) winsize 57
6593 00:43:34.029624 [CA 2] Center 36 (8~64) winsize 57
6594 00:43:34.032453 [CA 3] Center 36 (8~64) winsize 57
6595 00:43:34.035823 [CA 4] Center 36 (8~64) winsize 57
6596 00:43:34.039359 [CA 5] Center 36 (8~64) winsize 57
6597 00:43:34.039452
6598 00:43:34.042698 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6599 00:43:34.042777
6600 00:43:34.045898 [CATrainingPosCal] consider 1 rank data
6601 00:43:34.049312 u2DelayCellTimex100 = 270/100 ps
6602 00:43:34.052597 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 00:43:34.055800 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 00:43:34.059046 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 00:43:34.062405 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 00:43:34.069758 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 00:43:34.072556 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 00:43:34.072635
6609 00:43:34.075697 CA PerBit enable=1, Macro0, CA PI delay=36
6610 00:43:34.075777
6611 00:43:34.078842 [CBTSetCACLKResult] CA Dly = 36
6612 00:43:34.078950 CS Dly: 1 (0~32)
6613 00:43:34.079015 ==
6614 00:43:34.082461 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 00:43:34.085909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 00:43:34.089181 ==
6617 00:43:34.092804 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 00:43:34.099528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6619 00:43:34.102202 [CA 0] Center 36 (8~64) winsize 57
6620 00:43:34.105876 [CA 1] Center 36 (8~64) winsize 57
6621 00:43:34.108969 [CA 2] Center 36 (8~64) winsize 57
6622 00:43:34.112255 [CA 3] Center 36 (8~64) winsize 57
6623 00:43:34.115531 [CA 4] Center 36 (8~64) winsize 57
6624 00:43:34.118907 [CA 5] Center 36 (8~64) winsize 57
6625 00:43:34.118998
6626 00:43:34.122064 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6627 00:43:34.122143
6628 00:43:34.125363 [CATrainingPosCal] consider 2 rank data
6629 00:43:34.128778 u2DelayCellTimex100 = 270/100 ps
6630 00:43:34.132187 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 00:43:34.135322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 00:43:34.139374 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 00:43:34.142194 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 00:43:34.145774 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 00:43:34.148855 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 00:43:34.148938
6637 00:43:34.155469 CA PerBit enable=1, Macro0, CA PI delay=36
6638 00:43:34.155553
6639 00:43:34.155635 [CBTSetCACLKResult] CA Dly = 36
6640 00:43:34.158725 CS Dly: 1 (0~32)
6641 00:43:34.158806
6642 00:43:34.161949 ----->DramcWriteLeveling(PI) begin...
6643 00:43:34.162030 ==
6644 00:43:34.165741 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 00:43:34.169063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 00:43:34.169143 ==
6647 00:43:34.172418 Write leveling (Byte 0): 40 => 8
6648 00:43:34.175372 Write leveling (Byte 1): 40 => 8
6649 00:43:34.178500 DramcWriteLeveling(PI) end<-----
6650 00:43:34.178581
6651 00:43:34.178662 ==
6652 00:43:34.181773 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 00:43:34.185644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 00:43:34.185724 ==
6655 00:43:34.189297 [Gating] SW mode calibration
6656 00:43:34.195192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6657 00:43:34.202000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6658 00:43:34.205365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 00:43:34.212019 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 00:43:34.215444 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 00:43:34.219268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 00:43:34.225834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 00:43:34.228892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 00:43:34.232227 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 00:43:34.235390 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 00:43:34.242229 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 00:43:34.245722 Total UI for P1: 0, mck2ui 16
6668 00:43:34.249001 best dqsien dly found for B0: ( 0, 14, 24)
6669 00:43:34.252140 Total UI for P1: 0, mck2ui 16
6670 00:43:34.255281 best dqsien dly found for B1: ( 0, 14, 24)
6671 00:43:34.258822 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6672 00:43:34.262599 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6673 00:43:34.262683
6674 00:43:34.265364 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 00:43:34.268944 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 00:43:34.272034 [Gating] SW calibration Done
6677 00:43:34.272128 ==
6678 00:43:34.275532 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 00:43:34.279083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 00:43:34.279164 ==
6681 00:43:34.282447 RX Vref Scan: 0
6682 00:43:34.282527
6683 00:43:34.285523 RX Vref 0 -> 0, step: 1
6684 00:43:34.285602
6685 00:43:34.285696 RX Delay -410 -> 252, step: 16
6686 00:43:34.292091 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6687 00:43:34.295647 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6688 00:43:34.299076 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6689 00:43:34.301911 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6690 00:43:34.308689 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6691 00:43:34.312017 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6692 00:43:34.315375 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6693 00:43:34.318864 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6694 00:43:34.325701 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6695 00:43:34.328647 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6696 00:43:34.331864 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6697 00:43:34.334857 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6698 00:43:34.341887 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6699 00:43:34.345316 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6700 00:43:34.348649 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6701 00:43:34.354919 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6702 00:43:34.355003 ==
6703 00:43:34.358429 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 00:43:34.361642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 00:43:34.361725 ==
6706 00:43:34.361788 DQS Delay:
6707 00:43:34.365036 DQS0 = 35, DQS1 = 35
6708 00:43:34.365118 DQM Delay:
6709 00:43:34.368313 DQM0 = 18, DQM1 = 13
6710 00:43:34.368405 DQ Delay:
6711 00:43:34.371457 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6712 00:43:34.374698 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6713 00:43:34.378300 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6714 00:43:34.381853 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6715 00:43:34.381936
6716 00:43:34.382001
6717 00:43:34.382060 ==
6718 00:43:34.385064 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 00:43:34.387970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 00:43:34.388052 ==
6721 00:43:34.388116
6722 00:43:34.388176
6723 00:43:34.391532 TX Vref Scan disable
6724 00:43:34.395006 == TX Byte 0 ==
6725 00:43:34.397898 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 00:43:34.401855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 00:43:34.405022 == TX Byte 1 ==
6728 00:43:34.407917 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 00:43:34.411732 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 00:43:34.411814 ==
6731 00:43:34.414477 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 00:43:34.417966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 00:43:34.418060 ==
6734 00:43:34.418126
6735 00:43:34.418187
6736 00:43:34.421301 TX Vref Scan disable
6737 00:43:34.424681 == TX Byte 0 ==
6738 00:43:34.428137 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 00:43:34.431474 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 00:43:34.434947 == TX Byte 1 ==
6741 00:43:34.438244 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 00:43:34.441591 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 00:43:34.441675
6744 00:43:34.441739 [DATLAT]
6745 00:43:34.445201 Freq=400, CH1 RK0
6746 00:43:34.445286
6747 00:43:34.445386 DATLAT Default: 0xf
6748 00:43:34.447768 0, 0xFFFF, sum = 0
6749 00:43:34.447853 1, 0xFFFF, sum = 0
6750 00:43:34.451702 2, 0xFFFF, sum = 0
6751 00:43:34.454460 3, 0xFFFF, sum = 0
6752 00:43:34.454544 4, 0xFFFF, sum = 0
6753 00:43:34.457966 5, 0xFFFF, sum = 0
6754 00:43:34.458049 6, 0xFFFF, sum = 0
6755 00:43:34.461442 7, 0xFFFF, sum = 0
6756 00:43:34.461525 8, 0xFFFF, sum = 0
6757 00:43:34.464787 9, 0xFFFF, sum = 0
6758 00:43:34.464871 10, 0xFFFF, sum = 0
6759 00:43:34.468286 11, 0xFFFF, sum = 0
6760 00:43:34.468376 12, 0xFFFF, sum = 0
6761 00:43:34.471690 13, 0x0, sum = 1
6762 00:43:34.471772 14, 0x0, sum = 2
6763 00:43:34.474445 15, 0x0, sum = 3
6764 00:43:34.474527 16, 0x0, sum = 4
6765 00:43:34.474592 best_step = 14
6766 00:43:34.477943
6767 00:43:34.478023 ==
6768 00:43:34.481306 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 00:43:34.484708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 00:43:34.484791 ==
6771 00:43:34.484855 RX Vref Scan: 1
6772 00:43:34.484924
6773 00:43:34.487988 RX Vref 0 -> 0, step: 1
6774 00:43:34.488069
6775 00:43:34.491466 RX Delay -311 -> 252, step: 8
6776 00:43:34.491546
6777 00:43:34.494322 Set Vref, RX VrefLevel [Byte0]: 52
6778 00:43:34.498030 [Byte1]: 54
6779 00:43:34.501434
6780 00:43:34.501514 Final RX Vref Byte 0 = 52 to rank0
6781 00:43:34.504851 Final RX Vref Byte 1 = 54 to rank0
6782 00:43:34.508351 Final RX Vref Byte 0 = 52 to rank1
6783 00:43:34.511608 Final RX Vref Byte 1 = 54 to rank1==
6784 00:43:34.514818 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 00:43:34.521561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 00:43:34.521643 ==
6787 00:43:34.521708 DQS Delay:
6788 00:43:34.524869 DQS0 = 32, DQS1 = 32
6789 00:43:34.524950 DQM Delay:
6790 00:43:34.525014 DQM0 = 13, DQM1 = 9
6791 00:43:34.528045 DQ Delay:
6792 00:43:34.531726 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6793 00:43:34.531837 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6794 00:43:34.534899 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6795 00:43:34.538381 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6796 00:43:34.538462
6797 00:43:34.538525
6798 00:43:34.548519 [DQSOSCAuto] RK0, (LSB)MR18= 0x91ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6799 00:43:34.551961 CH1 RK0: MR19=C0C, MR18=91CA
6800 00:43:34.558302 CH1_RK0: MR19=0xC0C, MR18=0x91CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6801 00:43:34.558385 ==
6802 00:43:34.561548 Dram Type= 6, Freq= 0, CH_1, rank 1
6803 00:43:34.565218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 00:43:34.565300 ==
6805 00:43:34.568371 [Gating] SW mode calibration
6806 00:43:34.574975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6807 00:43:34.578428 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6808 00:43:34.584602 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 00:43:34.587985 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 00:43:34.591355 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 00:43:34.598010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 00:43:34.601214 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 00:43:34.604936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 00:43:34.611301 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 00:43:34.615177 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 00:43:34.618015 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 00:43:34.621463 Total UI for P1: 0, mck2ui 16
6818 00:43:34.624868 best dqsien dly found for B0: ( 0, 14, 24)
6819 00:43:34.628303 Total UI for P1: 0, mck2ui 16
6820 00:43:34.631582 best dqsien dly found for B1: ( 0, 14, 24)
6821 00:43:34.634830 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6822 00:43:34.637871 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6823 00:43:34.637952
6824 00:43:34.644532 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 00:43:34.648091 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 00:43:34.651760 [Gating] SW calibration Done
6827 00:43:34.651839 ==
6828 00:43:34.654959 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 00:43:34.658016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 00:43:34.658094 ==
6831 00:43:34.658160 RX Vref Scan: 0
6832 00:43:34.658219
6833 00:43:34.661298 RX Vref 0 -> 0, step: 1
6834 00:43:34.661395
6835 00:43:34.664554 RX Delay -410 -> 252, step: 16
6836 00:43:34.667950 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6837 00:43:34.674439 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6838 00:43:34.678159 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6839 00:43:34.681195 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6840 00:43:34.684453 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6841 00:43:34.687722 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6842 00:43:34.694686 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6843 00:43:34.697989 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6844 00:43:34.701353 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6845 00:43:34.704133 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6846 00:43:34.710952 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6847 00:43:34.714295 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6848 00:43:34.717390 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6849 00:43:34.723970 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6850 00:43:34.727433 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6851 00:43:34.730848 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6852 00:43:34.730955 ==
6853 00:43:34.734317 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 00:43:34.737627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 00:43:34.741034 ==
6856 00:43:34.741110 DQS Delay:
6857 00:43:34.741172 DQS0 = 35, DQS1 = 35
6858 00:43:34.744397 DQM Delay:
6859 00:43:34.744478 DQM0 = 18, DQM1 = 15
6860 00:43:34.747817 DQ Delay:
6861 00:43:34.750499 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6862 00:43:34.750580 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6863 00:43:34.753874 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6864 00:43:34.757153 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6865 00:43:34.757226
6866 00:43:34.761135
6867 00:43:34.761214 ==
6868 00:43:34.764026 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 00:43:34.767347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 00:43:34.767450 ==
6871 00:43:34.767549
6872 00:43:34.767637
6873 00:43:34.771037 TX Vref Scan disable
6874 00:43:34.771141 == TX Byte 0 ==
6875 00:43:34.773837 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6876 00:43:34.780829 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6877 00:43:34.780909 == TX Byte 1 ==
6878 00:43:34.783929 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6879 00:43:34.787572 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6880 00:43:34.790647 ==
6881 00:43:34.794065 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 00:43:34.797472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 00:43:34.797547 ==
6884 00:43:34.797609
6885 00:43:34.797667
6886 00:43:34.800732 TX Vref Scan disable
6887 00:43:34.800816 == TX Byte 0 ==
6888 00:43:34.804012 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6889 00:43:34.810838 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6890 00:43:34.810926 == TX Byte 1 ==
6891 00:43:34.814266 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6892 00:43:34.820484 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6893 00:43:34.820588
6894 00:43:34.820683 [DATLAT]
6895 00:43:34.820771 Freq=400, CH1 RK1
6896 00:43:34.820866
6897 00:43:34.823660 DATLAT Default: 0xe
6898 00:43:34.823760 0, 0xFFFF, sum = 0
6899 00:43:34.827301 1, 0xFFFF, sum = 0
6900 00:43:34.827402 2, 0xFFFF, sum = 0
6901 00:43:34.830518 3, 0xFFFF, sum = 0
6902 00:43:34.834134 4, 0xFFFF, sum = 0
6903 00:43:34.834210 5, 0xFFFF, sum = 0
6904 00:43:34.837450 6, 0xFFFF, sum = 0
6905 00:43:34.837524 7, 0xFFFF, sum = 0
6906 00:43:34.840194 8, 0xFFFF, sum = 0
6907 00:43:34.840296 9, 0xFFFF, sum = 0
6908 00:43:34.844134 10, 0xFFFF, sum = 0
6909 00:43:34.844235 11, 0xFFFF, sum = 0
6910 00:43:34.846881 12, 0xFFFF, sum = 0
6911 00:43:34.846954 13, 0x0, sum = 1
6912 00:43:34.850152 14, 0x0, sum = 2
6913 00:43:34.850255 15, 0x0, sum = 3
6914 00:43:34.853783 16, 0x0, sum = 4
6915 00:43:34.853869 best_step = 14
6916 00:43:34.853931
6917 00:43:34.853989 ==
6918 00:43:34.856942 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 00:43:34.860329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 00:43:34.863768 ==
6921 00:43:34.863867 RX Vref Scan: 0
6922 00:43:34.863956
6923 00:43:34.867079 RX Vref 0 -> 0, step: 1
6924 00:43:34.867174
6925 00:43:34.870716 RX Delay -311 -> 252, step: 8
6926 00:43:34.873776 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6927 00:43:34.880393 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6928 00:43:34.883651 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6929 00:43:34.886586 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6930 00:43:34.890274 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6931 00:43:34.896752 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6932 00:43:34.899919 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6933 00:43:34.903107 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6934 00:43:34.906868 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6935 00:43:34.913281 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6936 00:43:34.916360 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6937 00:43:34.919770 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6938 00:43:34.923166 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6939 00:43:34.930105 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6940 00:43:34.933287 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6941 00:43:34.936311 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6942 00:43:34.936422 ==
6943 00:43:34.939889 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 00:43:34.946539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 00:43:34.946619 ==
6946 00:43:34.946705 DQS Delay:
6947 00:43:34.949807 DQS0 = 28, DQS1 = 36
6948 00:43:34.949909 DQM Delay:
6949 00:43:34.950000 DQM0 = 10, DQM1 = 14
6950 00:43:34.953147 DQ Delay:
6951 00:43:34.956677 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6952 00:43:34.959440 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6953 00:43:34.959538 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6954 00:43:34.962872 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6955 00:43:34.966291
6956 00:43:34.966363
6957 00:43:34.973206 [DQSOSCAuto] RK1, (LSB)MR18= 0xc453, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6958 00:43:34.976374 CH1 RK1: MR19=C0C, MR18=C453
6959 00:43:34.982896 CH1_RK1: MR19=0xC0C, MR18=0xC453, DQSOSC=385, MR23=63, INC=398, DEC=265
6960 00:43:34.986509 [RxdqsGatingPostProcess] freq 400
6961 00:43:34.989509 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6962 00:43:34.992832 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 00:43:34.996474 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 00:43:34.999934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 00:43:35.002633 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 00:43:35.006509 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 00:43:35.010000 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 00:43:35.012655 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 00:43:35.016024 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 00:43:35.019947 Pre-setting of DQS Precalculation
6971 00:43:35.022787 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6972 00:43:35.029361 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6973 00:43:35.039286 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6974 00:43:35.039370
6975 00:43:35.039434
6976 00:43:35.042699 [Calibration Summary] 800 Mbps
6977 00:43:35.042774 CH 0, Rank 0
6978 00:43:35.045935 SW Impedance : PASS
6979 00:43:35.046014 DUTY Scan : NO K
6980 00:43:35.049719 ZQ Calibration : PASS
6981 00:43:35.049793 Jitter Meter : NO K
6982 00:43:35.052729 CBT Training : PASS
6983 00:43:35.056177 Write leveling : PASS
6984 00:43:35.056305 RX DQS gating : PASS
6985 00:43:35.059372 RX DQ/DQS(RDDQC) : PASS
6986 00:43:35.062818 TX DQ/DQS : PASS
6987 00:43:35.062918 RX DATLAT : PASS
6988 00:43:35.066351 RX DQ/DQS(Engine): PASS
6989 00:43:35.069127 TX OE : NO K
6990 00:43:35.069193 All Pass.
6991 00:43:35.069256
6992 00:43:35.069340 CH 0, Rank 1
6993 00:43:35.072598 SW Impedance : PASS
6994 00:43:35.075927 DUTY Scan : NO K
6995 00:43:35.075992 ZQ Calibration : PASS
6996 00:43:35.079255 Jitter Meter : NO K
6997 00:43:35.082665 CBT Training : PASS
6998 00:43:35.082737 Write leveling : NO K
6999 00:43:35.085848 RX DQS gating : PASS
7000 00:43:35.089183 RX DQ/DQS(RDDQC) : PASS
7001 00:43:35.089253 TX DQ/DQS : PASS
7002 00:43:35.092509 RX DATLAT : PASS
7003 00:43:35.092607 RX DQ/DQS(Engine): PASS
7004 00:43:35.095879 TX OE : NO K
7005 00:43:35.095975 All Pass.
7006 00:43:35.096065
7007 00:43:35.099261 CH 1, Rank 0
7008 00:43:35.099351 SW Impedance : PASS
7009 00:43:35.102480 DUTY Scan : NO K
7010 00:43:35.105704 ZQ Calibration : PASS
7011 00:43:35.105800 Jitter Meter : NO K
7012 00:43:35.108996 CBT Training : PASS
7013 00:43:35.112234 Write leveling : PASS
7014 00:43:35.112330 RX DQS gating : PASS
7015 00:43:35.115658 RX DQ/DQS(RDDQC) : PASS
7016 00:43:35.119572 TX DQ/DQS : PASS
7017 00:43:35.119646 RX DATLAT : PASS
7018 00:43:35.122352 RX DQ/DQS(Engine): PASS
7019 00:43:35.126167 TX OE : NO K
7020 00:43:35.126238 All Pass.
7021 00:43:35.126297
7022 00:43:35.126353 CH 1, Rank 1
7023 00:43:35.129367 SW Impedance : PASS
7024 00:43:35.132817 DUTY Scan : NO K
7025 00:43:35.132893 ZQ Calibration : PASS
7026 00:43:35.136215 Jitter Meter : NO K
7027 00:43:35.139365 CBT Training : PASS
7028 00:43:35.139450 Write leveling : NO K
7029 00:43:35.142733 RX DQS gating : PASS
7030 00:43:35.142804 RX DQ/DQS(RDDQC) : PASS
7031 00:43:35.145760 TX DQ/DQS : PASS
7032 00:43:35.148901 RX DATLAT : PASS
7033 00:43:35.149000 RX DQ/DQS(Engine): PASS
7034 00:43:35.152599 TX OE : NO K
7035 00:43:35.152701 All Pass.
7036 00:43:35.152773
7037 00:43:35.155940 DramC Write-DBI off
7038 00:43:35.159305 PER_BANK_REFRESH: Hybrid Mode
7039 00:43:35.159378 TX_TRACKING: ON
7040 00:43:35.168639 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7041 00:43:35.172440 [FAST_K] Save calibration result to emmc
7042 00:43:35.175581 dramc_set_vcore_voltage set vcore to 725000
7043 00:43:35.179035 Read voltage for 1600, 0
7044 00:43:35.179120 Vio18 = 0
7045 00:43:35.182309 Vcore = 725000
7046 00:43:35.182376 Vdram = 0
7047 00:43:35.182438 Vddq = 0
7048 00:43:35.182493 Vmddr = 0
7049 00:43:35.188740 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7050 00:43:35.195303 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7051 00:43:35.195378 MEM_TYPE=3, freq_sel=13
7052 00:43:35.198854 sv_algorithm_assistance_LP4_3733
7053 00:43:35.201846 ============ PULL DRAM RESETB DOWN ============
7054 00:43:35.208422 ========== PULL DRAM RESETB DOWN end =========
7055 00:43:35.211877 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7056 00:43:35.215659 ===================================
7057 00:43:35.218936 LPDDR4 DRAM CONFIGURATION
7058 00:43:35.222363 ===================================
7059 00:43:35.222436 EX_ROW_EN[0] = 0x0
7060 00:43:35.225583 EX_ROW_EN[1] = 0x0
7061 00:43:35.225651 LP4Y_EN = 0x0
7062 00:43:35.228953 WORK_FSP = 0x1
7063 00:43:35.229048 WL = 0x5
7064 00:43:35.231697 RL = 0x5
7065 00:43:35.231790 BL = 0x2
7066 00:43:35.235115 RPST = 0x0
7067 00:43:35.238460 RD_PRE = 0x0
7068 00:43:35.238530 WR_PRE = 0x1
7069 00:43:35.241894 WR_PST = 0x1
7070 00:43:35.241964 DBI_WR = 0x0
7071 00:43:35.245234 DBI_RD = 0x0
7072 00:43:35.245304 OTF = 0x1
7073 00:43:35.248573 ===================================
7074 00:43:35.251990 ===================================
7075 00:43:35.252087 ANA top config
7076 00:43:35.255075 ===================================
7077 00:43:35.258946 DLL_ASYNC_EN = 0
7078 00:43:35.261990 ALL_SLAVE_EN = 0
7079 00:43:35.265078 NEW_RANK_MODE = 1
7080 00:43:35.268741 DLL_IDLE_MODE = 1
7081 00:43:35.268830 LP45_APHY_COMB_EN = 1
7082 00:43:35.272108 TX_ODT_DIS = 0
7083 00:43:35.275435 NEW_8X_MODE = 1
7084 00:43:35.278658 ===================================
7085 00:43:35.281625 ===================================
7086 00:43:35.285253 data_rate = 3200
7087 00:43:35.288779 CKR = 1
7088 00:43:35.288881 DQ_P2S_RATIO = 8
7089 00:43:35.291847 ===================================
7090 00:43:35.295093 CA_P2S_RATIO = 8
7091 00:43:35.298491 DQ_CA_OPEN = 0
7092 00:43:35.301955 DQ_SEMI_OPEN = 0
7093 00:43:35.305301 CA_SEMI_OPEN = 0
7094 00:43:35.308795 CA_FULL_RATE = 0
7095 00:43:35.308868 DQ_CKDIV4_EN = 0
7096 00:43:35.311556 CA_CKDIV4_EN = 0
7097 00:43:35.314981 CA_PREDIV_EN = 0
7098 00:43:35.318181 PH8_DLY = 12
7099 00:43:35.321955 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7100 00:43:35.325258 DQ_AAMCK_DIV = 4
7101 00:43:35.325337 CA_AAMCK_DIV = 4
7102 00:43:35.328468 CA_ADMCK_DIV = 4
7103 00:43:35.331895 DQ_TRACK_CA_EN = 0
7104 00:43:35.335304 CA_PICK = 1600
7105 00:43:35.338659 CA_MCKIO = 1600
7106 00:43:35.342036 MCKIO_SEMI = 0
7107 00:43:35.345343 PLL_FREQ = 3068
7108 00:43:35.345414 DQ_UI_PI_RATIO = 32
7109 00:43:35.348714 CA_UI_PI_RATIO = 0
7110 00:43:35.352034 ===================================
7111 00:43:35.355202 ===================================
7112 00:43:35.358685 memory_type:LPDDR4
7113 00:43:35.361998 GP_NUM : 10
7114 00:43:35.362079 SRAM_EN : 1
7115 00:43:35.365200 MD32_EN : 0
7116 00:43:35.368607 ===================================
7117 00:43:35.371985 [ANA_INIT] >>>>>>>>>>>>>>
7118 00:43:35.372065 <<<<<< [CONFIGURE PHASE]: ANA_TX
7119 00:43:35.375179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7120 00:43:35.378322 ===================================
7121 00:43:35.381862 data_rate = 3200,PCW = 0X7600
7122 00:43:35.385227 ===================================
7123 00:43:35.388632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7124 00:43:35.395010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 00:43:35.401935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 00:43:35.405025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7127 00:43:35.408207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7128 00:43:35.411791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7129 00:43:35.415010 [ANA_INIT] flow start
7130 00:43:35.415106 [ANA_INIT] PLL >>>>>>>>
7131 00:43:35.418360 [ANA_INIT] PLL <<<<<<<<
7132 00:43:35.421745 [ANA_INIT] MIDPI >>>>>>>>
7133 00:43:35.421825 [ANA_INIT] MIDPI <<<<<<<<
7134 00:43:35.424978 [ANA_INIT] DLL >>>>>>>>
7135 00:43:35.428234 [ANA_INIT] DLL <<<<<<<<
7136 00:43:35.428348 [ANA_INIT] flow end
7137 00:43:35.434709 ============ LP4 DIFF to SE enter ============
7138 00:43:35.437907 ============ LP4 DIFF to SE exit ============
7139 00:43:35.441237 [ANA_INIT] <<<<<<<<<<<<<
7140 00:43:35.444994 [Flow] Enable top DCM control >>>>>
7141 00:43:35.445075 [Flow] Enable top DCM control <<<<<
7142 00:43:35.448075 Enable DLL master slave shuffle
7143 00:43:35.454936 ==============================================================
7144 00:43:35.458251 Gating Mode config
7145 00:43:35.461712 ==============================================================
7146 00:43:35.465112 Config description:
7147 00:43:35.475076 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7148 00:43:35.481790 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7149 00:43:35.485010 SELPH_MODE 0: By rank 1: By Phase
7150 00:43:35.491326 ==============================================================
7151 00:43:35.494861 GAT_TRACK_EN = 1
7152 00:43:35.497948 RX_GATING_MODE = 2
7153 00:43:35.501251 RX_GATING_TRACK_MODE = 2
7154 00:43:35.501325 SELPH_MODE = 1
7155 00:43:35.504666 PICG_EARLY_EN = 1
7156 00:43:35.508079 VALID_LAT_VALUE = 1
7157 00:43:35.514896 ==============================================================
7158 00:43:35.517827 Enter into Gating configuration >>>>
7159 00:43:35.521511 Exit from Gating configuration <<<<
7160 00:43:35.524632 Enter into DVFS_PRE_config >>>>>
7161 00:43:35.535066 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7162 00:43:35.538273 Exit from DVFS_PRE_config <<<<<
7163 00:43:35.541648 Enter into PICG configuration >>>>
7164 00:43:35.544801 Exit from PICG configuration <<<<
7165 00:43:35.548103 [RX_INPUT] configuration >>>>>
7166 00:43:35.551547 [RX_INPUT] configuration <<<<<
7167 00:43:35.554880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7168 00:43:35.560919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7169 00:43:35.567721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 00:43:35.574596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 00:43:35.577889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 00:43:35.584611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 00:43:35.587883 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7174 00:43:35.594625 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7175 00:43:35.598087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7176 00:43:35.601291 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7177 00:43:35.604230 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7178 00:43:35.610965 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 00:43:35.614855 ===================================
7180 00:43:35.614939 LPDDR4 DRAM CONFIGURATION
7181 00:43:35.617723 ===================================
7182 00:43:35.621102 EX_ROW_EN[0] = 0x0
7183 00:43:35.624261 EX_ROW_EN[1] = 0x0
7184 00:43:35.624380 LP4Y_EN = 0x0
7185 00:43:35.627698 WORK_FSP = 0x1
7186 00:43:35.627767 WL = 0x5
7187 00:43:35.630896 RL = 0x5
7188 00:43:35.630967 BL = 0x2
7189 00:43:35.634703 RPST = 0x0
7190 00:43:35.634779 RD_PRE = 0x0
7191 00:43:35.637703 WR_PRE = 0x1
7192 00:43:35.637771 WR_PST = 0x1
7193 00:43:35.641140 DBI_WR = 0x0
7194 00:43:35.641204 DBI_RD = 0x0
7195 00:43:35.644068 OTF = 0x1
7196 00:43:35.647941 ===================================
7197 00:43:35.651085 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7198 00:43:35.654248 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7199 00:43:35.660741 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 00:43:35.664560 ===================================
7201 00:43:35.664642 LPDDR4 DRAM CONFIGURATION
7202 00:43:35.667951 ===================================
7203 00:43:35.670769 EX_ROW_EN[0] = 0x10
7204 00:43:35.674141 EX_ROW_EN[1] = 0x0
7205 00:43:35.674238 LP4Y_EN = 0x0
7206 00:43:35.677607 WORK_FSP = 0x1
7207 00:43:35.677688 WL = 0x5
7208 00:43:35.680982 RL = 0x5
7209 00:43:35.681063 BL = 0x2
7210 00:43:35.684315 RPST = 0x0
7211 00:43:35.684417 RD_PRE = 0x0
7212 00:43:35.687647 WR_PRE = 0x1
7213 00:43:35.687744 WR_PST = 0x1
7214 00:43:35.690993 DBI_WR = 0x0
7215 00:43:35.691074 DBI_RD = 0x0
7216 00:43:35.693843 OTF = 0x1
7217 00:43:35.697374 ===================================
7218 00:43:35.704348 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7219 00:43:35.704469 ==
7220 00:43:35.707857 Dram Type= 6, Freq= 0, CH_0, rank 0
7221 00:43:35.710911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7222 00:43:35.710993 ==
7223 00:43:35.714232 [Duty_Offset_Calibration]
7224 00:43:35.714313 B0:2 B1:1 CA:1
7225 00:43:35.714401
7226 00:43:35.717362 [DutyScan_Calibration_Flow] k_type=0
7227 00:43:35.728079
7228 00:43:35.728198 ==CLK 0==
7229 00:43:35.731052 Final CLK duty delay cell = 0
7230 00:43:35.734407 [0] MAX Duty = 5187%(X100), DQS PI = 22
7231 00:43:35.737818 [0] MIN Duty = 4907%(X100), DQS PI = 0
7232 00:43:35.737902 [0] AVG Duty = 5047%(X100)
7233 00:43:35.737967
7234 00:43:35.741278 CH0 CLK Duty spec in!! Max-Min= 280%
7235 00:43:35.748181 [DutyScan_Calibration_Flow] ====Done====
7236 00:43:35.748301
7237 00:43:35.751559 [DutyScan_Calibration_Flow] k_type=1
7238 00:43:35.767032
7239 00:43:35.767120 ==DQS 0 ==
7240 00:43:35.770230 Final DQS duty delay cell = -4
7241 00:43:35.773791 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7242 00:43:35.776844 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7243 00:43:35.780213 [-4] AVG Duty = 4891%(X100)
7244 00:43:35.780324
7245 00:43:35.780410 ==DQS 1 ==
7246 00:43:35.783806 Final DQS duty delay cell = 0
7247 00:43:35.786626 [0] MAX Duty = 5187%(X100), DQS PI = 20
7248 00:43:35.790027 [0] MIN Duty = 5031%(X100), DQS PI = 32
7249 00:43:35.793497 [0] AVG Duty = 5109%(X100)
7250 00:43:35.793606
7251 00:43:35.797016 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7252 00:43:35.797099
7253 00:43:35.800375 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7254 00:43:35.803158 [DutyScan_Calibration_Flow] ====Done====
7255 00:43:35.803273
7256 00:43:35.806881 [DutyScan_Calibration_Flow] k_type=3
7257 00:43:35.823903
7258 00:43:35.823988 ==DQM 0 ==
7259 00:43:35.827352 Final DQM duty delay cell = 0
7260 00:43:35.829978 [0] MAX Duty = 5187%(X100), DQS PI = 26
7261 00:43:35.833892 [0] MIN Duty = 4876%(X100), DQS PI = 62
7262 00:43:35.836623 [0] AVG Duty = 5031%(X100)
7263 00:43:35.836701
7264 00:43:35.836765 ==DQM 1 ==
7265 00:43:35.840294 Final DQM duty delay cell = -4
7266 00:43:35.843479 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7267 00:43:35.847050 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7268 00:43:35.850671 [-4] AVG Duty = 4922%(X100)
7269 00:43:35.850759
7270 00:43:35.853300 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7271 00:43:35.853382
7272 00:43:35.856697 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7273 00:43:35.860084 [DutyScan_Calibration_Flow] ====Done====
7274 00:43:35.860192
7275 00:43:35.863709 [DutyScan_Calibration_Flow] k_type=2
7276 00:43:35.881311
7277 00:43:35.881411 ==DQ 0 ==
7278 00:43:35.884476 Final DQ duty delay cell = 0
7279 00:43:35.888042 [0] MAX Duty = 5062%(X100), DQS PI = 26
7280 00:43:35.891438 [0] MIN Duty = 4907%(X100), DQS PI = 0
7281 00:43:35.891523 [0] AVG Duty = 4984%(X100)
7282 00:43:35.891588
7283 00:43:35.895006 ==DQ 1 ==
7284 00:43:35.897654 Final DQ duty delay cell = 0
7285 00:43:35.901090 [0] MAX Duty = 5156%(X100), DQS PI = 22
7286 00:43:35.904900 [0] MIN Duty = 4907%(X100), DQS PI = 34
7287 00:43:35.904984 [0] AVG Duty = 5031%(X100)
7288 00:43:35.905077
7289 00:43:35.907561 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7290 00:43:35.911230
7291 00:43:35.914628 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7292 00:43:35.918150 [DutyScan_Calibration_Flow] ====Done====
7293 00:43:35.918268 ==
7294 00:43:35.920937 Dram Type= 6, Freq= 0, CH_1, rank 0
7295 00:43:35.924636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 00:43:35.924742 ==
7297 00:43:35.928093 [Duty_Offset_Calibration]
7298 00:43:35.928203 B0:1 B1:0 CA:0
7299 00:43:35.928299
7300 00:43:35.931229 [DutyScan_Calibration_Flow] k_type=0
7301 00:43:35.940761
7302 00:43:35.940882 ==CLK 0==
7303 00:43:35.943677 Final CLK duty delay cell = -4
7304 00:43:35.947078 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7305 00:43:35.950586 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7306 00:43:35.953888 [-4] AVG Duty = 4922%(X100)
7307 00:43:35.953963
7308 00:43:35.956908 CH1 CLK Duty spec in!! Max-Min= 156%
7309 00:43:35.960087 [DutyScan_Calibration_Flow] ====Done====
7310 00:43:35.960194
7311 00:43:35.963708 [DutyScan_Calibration_Flow] k_type=1
7312 00:43:35.981133
7313 00:43:35.981256 ==DQS 0 ==
7314 00:43:35.984041 Final DQS duty delay cell = 0
7315 00:43:35.987449 [0] MAX Duty = 5094%(X100), DQS PI = 32
7316 00:43:35.990846 [0] MIN Duty = 4844%(X100), DQS PI = 48
7317 00:43:35.993566 [0] AVG Duty = 4969%(X100)
7318 00:43:35.993645
7319 00:43:35.993718 ==DQS 1 ==
7320 00:43:35.996817 Final DQS duty delay cell = 0
7321 00:43:36.000665 [0] MAX Duty = 5249%(X100), DQS PI = 16
7322 00:43:36.003856 [0] MIN Duty = 4938%(X100), DQS PI = 8
7323 00:43:36.006968 [0] AVG Duty = 5093%(X100)
7324 00:43:36.007043
7325 00:43:36.010155 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7326 00:43:36.010229
7327 00:43:36.013786 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7328 00:43:36.017001 [DutyScan_Calibration_Flow] ====Done====
7329 00:43:36.017124
7330 00:43:36.020172 [DutyScan_Calibration_Flow] k_type=3
7331 00:43:36.037544
7332 00:43:36.037665 ==DQM 0 ==
7333 00:43:36.040799 Final DQM duty delay cell = 0
7334 00:43:36.044435 [0] MAX Duty = 5187%(X100), DQS PI = 8
7335 00:43:36.047405 [0] MIN Duty = 4969%(X100), DQS PI = 48
7336 00:43:36.047512 [0] AVG Duty = 5078%(X100)
7337 00:43:36.050732
7338 00:43:36.050834 ==DQM 1 ==
7339 00:43:36.054251 Final DQM duty delay cell = 0
7340 00:43:36.057585 [0] MAX Duty = 5093%(X100), DQS PI = 16
7341 00:43:36.060739 [0] MIN Duty = 4907%(X100), DQS PI = 34
7342 00:43:36.060822 [0] AVG Duty = 5000%(X100)
7343 00:43:36.063958
7344 00:43:36.067675 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7345 00:43:36.067757
7346 00:43:36.070700 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7347 00:43:36.074222 [DutyScan_Calibration_Flow] ====Done====
7348 00:43:36.074316
7349 00:43:36.077021 [DutyScan_Calibration_Flow] k_type=2
7350 00:43:36.093982
7351 00:43:36.094092 ==DQ 0 ==
7352 00:43:36.096790 Final DQ duty delay cell = -4
7353 00:43:36.100059 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7354 00:43:36.103979 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7355 00:43:36.107329 [-4] AVG Duty = 4953%(X100)
7356 00:43:36.107430
7357 00:43:36.107527 ==DQ 1 ==
7358 00:43:36.110609 Final DQ duty delay cell = 0
7359 00:43:36.113415 [0] MAX Duty = 5124%(X100), DQS PI = 18
7360 00:43:36.116725 [0] MIN Duty = 4938%(X100), DQS PI = 8
7361 00:43:36.116826 [0] AVG Duty = 5031%(X100)
7362 00:43:36.120693
7363 00:43:36.123586 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7364 00:43:36.123660
7365 00:43:36.126795 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7366 00:43:36.130561 [DutyScan_Calibration_Flow] ====Done====
7367 00:43:36.133709 nWR fixed to 30
7368 00:43:36.133793 [ModeRegInit_LP4] CH0 RK0
7369 00:43:36.136729 [ModeRegInit_LP4] CH0 RK1
7370 00:43:36.140461 [ModeRegInit_LP4] CH1 RK0
7371 00:43:36.143376 [ModeRegInit_LP4] CH1 RK1
7372 00:43:36.143486 match AC timing 5
7373 00:43:36.146927 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7374 00:43:36.153816 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7375 00:43:36.157344 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7376 00:43:36.163749 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7377 00:43:36.166617 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7378 00:43:36.166733 [MiockJmeterHQA]
7379 00:43:36.166826
7380 00:43:36.170024 [DramcMiockJmeter] u1RxGatingPI = 0
7381 00:43:36.173460 0 : 4255, 4029
7382 00:43:36.173570 4 : 4252, 4027
7383 00:43:36.173675 8 : 4253, 4026
7384 00:43:36.176811 12 : 4363, 4140
7385 00:43:36.176897 16 : 4253, 4027
7386 00:43:36.180034 20 : 4253, 4026
7387 00:43:36.180147 24 : 4252, 4027
7388 00:43:36.183497 28 : 4363, 4137
7389 00:43:36.183599 32 : 4253, 4026
7390 00:43:36.186943 36 : 4363, 4138
7391 00:43:36.187031 40 : 4253, 4026
7392 00:43:36.187095 44 : 4252, 4027
7393 00:43:36.190214 48 : 4249, 4027
7394 00:43:36.190289 52 : 4255, 4029
7395 00:43:36.193427 56 : 4360, 4137
7396 00:43:36.193506 60 : 4250, 4027
7397 00:43:36.197110 64 : 4360, 4138
7398 00:43:36.197215 68 : 4250, 4027
7399 00:43:36.200481 72 : 4250, 4027
7400 00:43:36.200560 76 : 4250, 4027
7401 00:43:36.200624 80 : 4361, 4137
7402 00:43:36.203768 84 : 4250, 4027
7403 00:43:36.203856 88 : 4361, 238
7404 00:43:36.207044 92 : 4252, 0
7405 00:43:36.207122 96 : 4252, 0
7406 00:43:36.207186 100 : 4250, 0
7407 00:43:36.210383 104 : 4250, 0
7408 00:43:36.210462 108 : 4252, 0
7409 00:43:36.213108 112 : 4361, 0
7410 00:43:36.213190 116 : 4361, 0
7411 00:43:36.213253 120 : 4250, 0
7412 00:43:36.216476 124 : 4250, 0
7413 00:43:36.216555 128 : 4361, 0
7414 00:43:36.219901 132 : 4250, 0
7415 00:43:36.219977 136 : 4250, 0
7416 00:43:36.220040 140 : 4250, 0
7417 00:43:36.223377 144 : 4250, 0
7418 00:43:36.223454 148 : 4250, 0
7419 00:43:36.223518 152 : 4360, 0
7420 00:43:36.226798 156 : 4250, 0
7421 00:43:36.226909 160 : 4250, 0
7422 00:43:36.229670 164 : 4250, 0
7423 00:43:36.229772 168 : 4361, 0
7424 00:43:36.229864 172 : 4250, 0
7425 00:43:36.233102 176 : 4250, 0
7426 00:43:36.233176 180 : 4250, 0
7427 00:43:36.236578 184 : 4360, 0
7428 00:43:36.236664 188 : 4250, 0
7429 00:43:36.236731 192 : 4250, 0
7430 00:43:36.239894 196 : 4250, 0
7431 00:43:36.239994 200 : 4250, 0
7432 00:43:36.243348 204 : 4360, 1334
7433 00:43:36.243458 208 : 4250, 3958
7434 00:43:36.246792 212 : 4361, 4137
7435 00:43:36.246895 216 : 4250, 4027
7436 00:43:36.246988 220 : 4250, 4027
7437 00:43:36.250139 224 : 4250, 4026
7438 00:43:36.250223 228 : 4253, 4029
7439 00:43:36.253501 232 : 4250, 4027
7440 00:43:36.253610 236 : 4250, 4027
7441 00:43:36.256556 240 : 4250, 4026
7442 00:43:36.256669 244 : 4253, 4029
7443 00:43:36.260105 248 : 4250, 4027
7444 00:43:36.260213 252 : 4361, 4138
7445 00:43:36.263222 256 : 4360, 4137
7446 00:43:36.263326 260 : 4250, 4026
7447 00:43:36.266648 264 : 4363, 4139
7448 00:43:36.266762 268 : 4250, 4027
7449 00:43:36.269606 272 : 4250, 4027
7450 00:43:36.269720 276 : 4250, 4026
7451 00:43:36.269822 280 : 4253, 4029
7452 00:43:36.273024 284 : 4250, 4027
7453 00:43:36.273102 288 : 4250, 4027
7454 00:43:36.276625 292 : 4250, 4026
7455 00:43:36.276702 296 : 4253, 4029
7456 00:43:36.280146 300 : 4250, 4027
7457 00:43:36.280256 304 : 4361, 4138
7458 00:43:36.282938 308 : 4360, 4049
7459 00:43:36.283027 312 : 4250, 1858
7460 00:43:36.283092
7461 00:43:36.286541 MIOCK jitter meter ch=0
7462 00:43:36.286648
7463 00:43:36.289959 1T = (312-88) = 224 dly cells
7464 00:43:36.292854 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7465 00:43:36.296601 ==
7466 00:43:36.299551 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 00:43:36.302993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7468 00:43:36.303110 ==
7469 00:43:36.306052 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7470 00:43:36.312954 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7471 00:43:36.316033 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7472 00:43:36.323156 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7473 00:43:36.331386 [CA 0] Center 42 (12~73) winsize 62
7474 00:43:36.334314 [CA 1] Center 42 (12~73) winsize 62
7475 00:43:36.337863 [CA 2] Center 38 (8~68) winsize 61
7476 00:43:36.341284 [CA 3] Center 37 (8~67) winsize 60
7477 00:43:36.344686 [CA 4] Center 36 (6~66) winsize 61
7478 00:43:36.348088 [CA 5] Center 35 (6~64) winsize 59
7479 00:43:36.348191
7480 00:43:36.350824 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7481 00:43:36.350931
7482 00:43:36.354396 [CATrainingPosCal] consider 1 rank data
7483 00:43:36.357733 u2DelayCellTimex100 = 290/100 ps
7484 00:43:36.361091 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7485 00:43:36.367962 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7486 00:43:36.371322 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7487 00:43:36.374607 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7488 00:43:36.377888 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7489 00:43:36.380857 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7490 00:43:36.380951
7491 00:43:36.384548 CA PerBit enable=1, Macro0, CA PI delay=35
7492 00:43:36.384646
7493 00:43:36.387448 [CBTSetCACLKResult] CA Dly = 35
7494 00:43:36.390943 CS Dly: 9 (0~40)
7495 00:43:36.394340 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7496 00:43:36.397927 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7497 00:43:36.398043 ==
7498 00:43:36.401371 Dram Type= 6, Freq= 0, CH_0, rank 1
7499 00:43:36.404148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7500 00:43:36.404261 ==
7501 00:43:36.411307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7502 00:43:36.414657 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7503 00:43:36.420632 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7504 00:43:36.423897 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7505 00:43:36.434322 [CA 0] Center 42 (12~73) winsize 62
7506 00:43:36.438030 [CA 1] Center 42 (12~73) winsize 62
7507 00:43:36.441012 [CA 2] Center 38 (8~68) winsize 61
7508 00:43:36.444736 [CA 3] Center 38 (8~68) winsize 61
7509 00:43:36.447784 [CA 4] Center 35 (6~65) winsize 60
7510 00:43:36.451064 [CA 5] Center 35 (5~65) winsize 61
7511 00:43:36.451184
7512 00:43:36.454661 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7513 00:43:36.454750
7514 00:43:36.458084 [CATrainingPosCal] consider 2 rank data
7515 00:43:36.461051 u2DelayCellTimex100 = 290/100 ps
7516 00:43:36.464414 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7517 00:43:36.471305 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7518 00:43:36.474683 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7519 00:43:36.477947 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7520 00:43:36.481289 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7521 00:43:36.484882 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7522 00:43:36.484967
7523 00:43:36.488042 CA PerBit enable=1, Macro0, CA PI delay=35
7524 00:43:36.488142
7525 00:43:36.490730 [CBTSetCACLKResult] CA Dly = 35
7526 00:43:36.494440 CS Dly: 10 (0~42)
7527 00:43:36.497356 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7528 00:43:36.500906 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7529 00:43:36.500995
7530 00:43:36.504071 ----->DramcWriteLeveling(PI) begin...
7531 00:43:36.504163 ==
7532 00:43:36.507529 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 00:43:36.510937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 00:43:36.514357 ==
7535 00:43:36.514443 Write leveling (Byte 0): 35 => 35
7536 00:43:36.517756 Write leveling (Byte 1): 29 => 29
7537 00:43:36.521001 DramcWriteLeveling(PI) end<-----
7538 00:43:36.521086
7539 00:43:36.521152 ==
7540 00:43:36.524594 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 00:43:36.531395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 00:43:36.531483 ==
7543 00:43:36.533933 [Gating] SW mode calibration
7544 00:43:36.540844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7545 00:43:36.544241 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7546 00:43:36.550603 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 00:43:36.554371 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 00:43:36.557175 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
7549 00:43:36.564228 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7550 00:43:36.567492 1 4 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7551 00:43:36.570748 1 4 20 | B1->B0 | 3333 3737 | 1 0 | (1 1) (0 0)
7552 00:43:36.577283 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7553 00:43:36.580608 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7554 00:43:36.583603 1 5 0 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (0 0)
7555 00:43:36.590387 1 5 4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7556 00:43:36.593903 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 1)
7557 00:43:36.596818 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7558 00:43:36.600238 1 5 16 | B1->B0 | 3333 2c2b | 0 1 | (0 1) (0 0)
7559 00:43:36.607282 1 5 20 | B1->B0 | 2525 2727 | 0 0 | (0 1) (0 0)
7560 00:43:36.610390 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7561 00:43:36.613597 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7562 00:43:36.620720 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7563 00:43:36.624058 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7564 00:43:36.626850 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7565 00:43:36.633913 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7566 00:43:36.637238 1 6 16 | B1->B0 | 2a29 4646 | 1 0 | (1 1) (0 0)
7567 00:43:36.640422 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7568 00:43:36.647264 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7569 00:43:36.650645 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 00:43:36.653379 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 00:43:36.660252 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 00:43:36.663695 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 00:43:36.666833 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 00:43:36.673355 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7575 00:43:36.676951 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7576 00:43:36.680095 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 00:43:36.687083 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 00:43:36.690417 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 00:43:36.693767 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 00:43:36.700045 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 00:43:36.703387 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 00:43:36.706819 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 00:43:36.713702 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 00:43:36.716905 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 00:43:36.720163 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 00:43:36.726532 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 00:43:36.729945 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 00:43:36.733316 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 00:43:36.736867 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 00:43:36.743454 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7591 00:43:36.746291 Total UI for P1: 0, mck2ui 16
7592 00:43:36.749777 best dqsien dly found for B0: ( 1, 9, 10)
7593 00:43:36.753166 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7594 00:43:36.756487 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 00:43:36.759844 Total UI for P1: 0, mck2ui 16
7596 00:43:36.763317 best dqsien dly found for B1: ( 1, 9, 20)
7597 00:43:36.766125 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7598 00:43:36.773237 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7599 00:43:36.773356
7600 00:43:36.776735 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7601 00:43:36.780004 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7602 00:43:36.783124 [Gating] SW calibration Done
7603 00:43:36.783208 ==
7604 00:43:36.786532 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 00:43:36.789817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 00:43:36.789927 ==
7607 00:43:36.793151 RX Vref Scan: 0
7608 00:43:36.793234
7609 00:43:36.793300 RX Vref 0 -> 0, step: 1
7610 00:43:36.793362
7611 00:43:36.796737 RX Delay 0 -> 252, step: 8
7612 00:43:36.799993 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7613 00:43:36.802854 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7614 00:43:36.809753 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7615 00:43:36.812680 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7616 00:43:36.816242 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7617 00:43:36.819662 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7618 00:43:36.823060 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7619 00:43:36.829444 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7620 00:43:36.832854 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7621 00:43:36.835990 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7622 00:43:36.839864 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7623 00:43:36.842798 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7624 00:43:36.849696 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7625 00:43:36.852680 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7626 00:43:36.856368 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7627 00:43:36.859647 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7628 00:43:36.859725 ==
7629 00:43:36.863075 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 00:43:36.869334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 00:43:36.869417 ==
7632 00:43:36.869482 DQS Delay:
7633 00:43:36.869541 DQS0 = 0, DQS1 = 0
7634 00:43:36.872875 DQM Delay:
7635 00:43:36.872974 DQM0 = 137, DQM1 = 131
7636 00:43:36.876287 DQ Delay:
7637 00:43:36.879835 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7638 00:43:36.882618 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7639 00:43:36.885949 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7640 00:43:36.889278 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7641 00:43:36.889355
7642 00:43:36.889418
7643 00:43:36.889481 ==
7644 00:43:36.892772 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 00:43:36.895943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 00:43:36.896020 ==
7647 00:43:36.899274
7648 00:43:36.899349
7649 00:43:36.899410 TX Vref Scan disable
7650 00:43:36.903118 == TX Byte 0 ==
7651 00:43:36.906229 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7652 00:43:36.909239 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7653 00:43:36.912834 == TX Byte 1 ==
7654 00:43:36.916294 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7655 00:43:36.919964 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7656 00:43:36.920047 ==
7657 00:43:36.922710 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 00:43:36.929589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 00:43:36.929693 ==
7660 00:43:36.940779
7661 00:43:36.943501 TX Vref early break, caculate TX vref
7662 00:43:36.946848 TX Vref=16, minBit 1, minWin=22, winSum=378
7663 00:43:36.950269 TX Vref=18, minBit 0, minWin=24, winSum=390
7664 00:43:36.954174 TX Vref=20, minBit 7, minWin=23, winSum=398
7665 00:43:36.956919 TX Vref=22, minBit 0, minWin=24, winSum=411
7666 00:43:36.960101 TX Vref=24, minBit 1, minWin=25, winSum=415
7667 00:43:36.966902 TX Vref=26, minBit 2, minWin=25, winSum=429
7668 00:43:36.970595 TX Vref=28, minBit 8, minWin=24, winSum=424
7669 00:43:36.973721 TX Vref=30, minBit 1, minWin=25, winSum=414
7670 00:43:36.976966 TX Vref=32, minBit 6, minWin=23, winSum=404
7671 00:43:36.983823 [TxChooseVref] Worse bit 2, Min win 25, Win sum 429, Final Vref 26
7672 00:43:36.983936
7673 00:43:36.986669 Final TX Range 0 Vref 26
7674 00:43:36.986746
7675 00:43:36.986850 ==
7676 00:43:36.990174 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 00:43:36.993557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 00:43:36.993664 ==
7679 00:43:36.993763
7680 00:43:36.993866
7681 00:43:36.997116 TX Vref Scan disable
7682 00:43:36.999915 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7683 00:43:37.003445 == TX Byte 0 ==
7684 00:43:37.006996 u2DelayCellOfst[0]=10 cells (3 PI)
7685 00:43:37.010470 u2DelayCellOfst[1]=13 cells (4 PI)
7686 00:43:37.013256 u2DelayCellOfst[2]=10 cells (3 PI)
7687 00:43:37.016824 u2DelayCellOfst[3]=10 cells (3 PI)
7688 00:43:37.019936 u2DelayCellOfst[4]=6 cells (2 PI)
7689 00:43:37.020054 u2DelayCellOfst[5]=0 cells (0 PI)
7690 00:43:37.023622 u2DelayCellOfst[6]=16 cells (5 PI)
7691 00:43:37.026675 u2DelayCellOfst[7]=13 cells (4 PI)
7692 00:43:37.033559 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7693 00:43:37.036520 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7694 00:43:37.036644 == TX Byte 1 ==
7695 00:43:37.040297 u2DelayCellOfst[8]=0 cells (0 PI)
7696 00:43:37.043771 u2DelayCellOfst[9]=0 cells (0 PI)
7697 00:43:37.047037 u2DelayCellOfst[10]=10 cells (3 PI)
7698 00:43:37.050362 u2DelayCellOfst[11]=3 cells (1 PI)
7699 00:43:37.053233 u2DelayCellOfst[12]=10 cells (3 PI)
7700 00:43:37.056644 u2DelayCellOfst[13]=13 cells (4 PI)
7701 00:43:37.060002 u2DelayCellOfst[14]=16 cells (5 PI)
7702 00:43:37.063576 u2DelayCellOfst[15]=10 cells (3 PI)
7703 00:43:37.066629 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7704 00:43:37.070480 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7705 00:43:37.073562 DramC Write-DBI on
7706 00:43:37.073659 ==
7707 00:43:37.076747 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 00:43:37.079937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 00:43:37.080040 ==
7710 00:43:37.080131
7711 00:43:37.080219
7712 00:43:37.083232 TX Vref Scan disable
7713 00:43:37.086831 == TX Byte 0 ==
7714 00:43:37.090040 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7715 00:43:37.093209 == TX Byte 1 ==
7716 00:43:37.096629 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7717 00:43:37.096716 DramC Write-DBI off
7718 00:43:37.096821
7719 00:43:37.100111 [DATLAT]
7720 00:43:37.100218 Freq=1600, CH0 RK0
7721 00:43:37.100311
7722 00:43:37.102846 DATLAT Default: 0xf
7723 00:43:37.102920 0, 0xFFFF, sum = 0
7724 00:43:37.106368 1, 0xFFFF, sum = 0
7725 00:43:37.106455 2, 0xFFFF, sum = 0
7726 00:43:37.109696 3, 0xFFFF, sum = 0
7727 00:43:37.109811 4, 0xFFFF, sum = 0
7728 00:43:37.113030 5, 0xFFFF, sum = 0
7729 00:43:37.113114 6, 0xFFFF, sum = 0
7730 00:43:37.116477 7, 0xFFFF, sum = 0
7731 00:43:37.119868 8, 0xFFFF, sum = 0
7732 00:43:37.119979 9, 0xFFFF, sum = 0
7733 00:43:37.122654 10, 0xFFFF, sum = 0
7734 00:43:37.122738 11, 0xFFFF, sum = 0
7735 00:43:37.126162 12, 0xFFFF, sum = 0
7736 00:43:37.126246 13, 0xFFFF, sum = 0
7737 00:43:37.129575 14, 0x0, sum = 1
7738 00:43:37.129681 15, 0x0, sum = 2
7739 00:43:37.132916 16, 0x0, sum = 3
7740 00:43:37.133026 17, 0x0, sum = 4
7741 00:43:37.136193 best_step = 15
7742 00:43:37.136302
7743 00:43:37.136415 ==
7744 00:43:37.139496 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 00:43:37.143034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 00:43:37.143109 ==
7747 00:43:37.143171 RX Vref Scan: 1
7748 00:43:37.143230
7749 00:43:37.146076 Set Vref Range= 24 -> 127
7750 00:43:37.146178
7751 00:43:37.149788 RX Vref 24 -> 127, step: 1
7752 00:43:37.149870
7753 00:43:37.152818 RX Delay 27 -> 252, step: 4
7754 00:43:37.152901
7755 00:43:37.156200 Set Vref, RX VrefLevel [Byte0]: 24
7756 00:43:37.159219 [Byte1]: 24
7757 00:43:37.159303
7758 00:43:37.163034 Set Vref, RX VrefLevel [Byte0]: 25
7759 00:43:37.166466 [Byte1]: 25
7760 00:43:37.166550
7761 00:43:37.169473 Set Vref, RX VrefLevel [Byte0]: 26
7762 00:43:37.172542 [Byte1]: 26
7763 00:43:37.176393
7764 00:43:37.176501 Set Vref, RX VrefLevel [Byte0]: 27
7765 00:43:37.179429 [Byte1]: 27
7766 00:43:37.183746
7767 00:43:37.183838 Set Vref, RX VrefLevel [Byte0]: 28
7768 00:43:37.187300 [Byte1]: 28
7769 00:43:37.191320
7770 00:43:37.191433 Set Vref, RX VrefLevel [Byte0]: 29
7771 00:43:37.194556 [Byte1]: 29
7772 00:43:37.199169
7773 00:43:37.199258 Set Vref, RX VrefLevel [Byte0]: 30
7774 00:43:37.202270 [Byte1]: 30
7775 00:43:37.206223
7776 00:43:37.206344 Set Vref, RX VrefLevel [Byte0]: 31
7777 00:43:37.209740 [Byte1]: 31
7778 00:43:37.214029
7779 00:43:37.214129 Set Vref, RX VrefLevel [Byte0]: 32
7780 00:43:37.217343 [Byte1]: 32
7781 00:43:37.221356
7782 00:43:37.221476 Set Vref, RX VrefLevel [Byte0]: 33
7783 00:43:37.225036 [Byte1]: 33
7784 00:43:37.229100
7785 00:43:37.229201 Set Vref, RX VrefLevel [Byte0]: 34
7786 00:43:37.232473 [Byte1]: 34
7787 00:43:37.236601
7788 00:43:37.236695 Set Vref, RX VrefLevel [Byte0]: 35
7789 00:43:37.239933 [Byte1]: 35
7790 00:43:37.243952
7791 00:43:37.244046 Set Vref, RX VrefLevel [Byte0]: 36
7792 00:43:37.247327 [Byte1]: 36
7793 00:43:37.251300
7794 00:43:37.251394 Set Vref, RX VrefLevel [Byte0]: 37
7795 00:43:37.254697 [Byte1]: 37
7796 00:43:37.259381
7797 00:43:37.259501 Set Vref, RX VrefLevel [Byte0]: 38
7798 00:43:37.262722 [Byte1]: 38
7799 00:43:37.266503
7800 00:43:37.266617 Set Vref, RX VrefLevel [Byte0]: 39
7801 00:43:37.270938 [Byte1]: 39
7802 00:43:37.274448
7803 00:43:37.274561 Set Vref, RX VrefLevel [Byte0]: 40
7804 00:43:37.277587 [Byte1]: 40
7805 00:43:37.281704
7806 00:43:37.281793 Set Vref, RX VrefLevel [Byte0]: 41
7807 00:43:37.285188 [Byte1]: 41
7808 00:43:37.289635
7809 00:43:37.289759 Set Vref, RX VrefLevel [Byte0]: 42
7810 00:43:37.292644 [Byte1]: 42
7811 00:43:37.296848
7812 00:43:37.296941 Set Vref, RX VrefLevel [Byte0]: 43
7813 00:43:37.300103 [Byte1]: 43
7814 00:43:37.304329
7815 00:43:37.304465 Set Vref, RX VrefLevel [Byte0]: 44
7816 00:43:37.307576 [Byte1]: 44
7817 00:43:37.311886
7818 00:43:37.311971 Set Vref, RX VrefLevel [Byte0]: 45
7819 00:43:37.314994 [Byte1]: 45
7820 00:43:37.319276
7821 00:43:37.319392 Set Vref, RX VrefLevel [Byte0]: 46
7822 00:43:37.322769 [Byte1]: 46
7823 00:43:37.326767
7824 00:43:37.326879 Set Vref, RX VrefLevel [Byte0]: 47
7825 00:43:37.330194 [Byte1]: 47
7826 00:43:37.334311
7827 00:43:37.334417 Set Vref, RX VrefLevel [Byte0]: 48
7828 00:43:37.337648 [Byte1]: 48
7829 00:43:37.342330
7830 00:43:37.342427 Set Vref, RX VrefLevel [Byte0]: 49
7831 00:43:37.345039 [Byte1]: 49
7832 00:43:37.349269
7833 00:43:37.349356 Set Vref, RX VrefLevel [Byte0]: 50
7834 00:43:37.352602 [Byte1]: 50
7835 00:43:37.357182
7836 00:43:37.357321 Set Vref, RX VrefLevel [Byte0]: 51
7837 00:43:37.360356 [Byte1]: 51
7838 00:43:37.364496
7839 00:43:37.364611 Set Vref, RX VrefLevel [Byte0]: 52
7840 00:43:37.368054 [Byte1]: 52
7841 00:43:37.371983
7842 00:43:37.372109 Set Vref, RX VrefLevel [Byte0]: 53
7843 00:43:37.375266 [Byte1]: 53
7844 00:43:37.380059
7845 00:43:37.380171 Set Vref, RX VrefLevel [Byte0]: 54
7846 00:43:37.382854 [Byte1]: 54
7847 00:43:37.387461
7848 00:43:37.387570 Set Vref, RX VrefLevel [Byte0]: 55
7849 00:43:37.390522 [Byte1]: 55
7850 00:43:37.395173
7851 00:43:37.395288 Set Vref, RX VrefLevel [Byte0]: 56
7852 00:43:37.397958 [Byte1]: 56
7853 00:43:37.402059
7854 00:43:37.402155 Set Vref, RX VrefLevel [Byte0]: 57
7855 00:43:37.405772 [Byte1]: 57
7856 00:43:37.409849
7857 00:43:37.409940 Set Vref, RX VrefLevel [Byte0]: 58
7858 00:43:37.412846 [Byte1]: 58
7859 00:43:37.417323
7860 00:43:37.417416 Set Vref, RX VrefLevel [Byte0]: 59
7861 00:43:37.420652 [Byte1]: 59
7862 00:43:37.425102
7863 00:43:37.425198 Set Vref, RX VrefLevel [Byte0]: 60
7864 00:43:37.428423 [Byte1]: 60
7865 00:43:37.432876
7866 00:43:37.432995 Set Vref, RX VrefLevel [Byte0]: 61
7867 00:43:37.435870 [Byte1]: 61
7868 00:43:37.440072
7869 00:43:37.440183 Set Vref, RX VrefLevel [Byte0]: 62
7870 00:43:37.443417 [Byte1]: 62
7871 00:43:37.447833
7872 00:43:37.447949 Set Vref, RX VrefLevel [Byte0]: 63
7873 00:43:37.451215 [Byte1]: 63
7874 00:43:37.454661
7875 00:43:37.454796 Set Vref, RX VrefLevel [Byte0]: 64
7876 00:43:37.458016 [Byte1]: 64
7877 00:43:37.462586
7878 00:43:37.462705 Set Vref, RX VrefLevel [Byte0]: 65
7879 00:43:37.465911 [Byte1]: 65
7880 00:43:37.469911
7881 00:43:37.470011 Set Vref, RX VrefLevel [Byte0]: 66
7882 00:43:37.473437 [Byte1]: 66
7883 00:43:37.477370
7884 00:43:37.477500 Set Vref, RX VrefLevel [Byte0]: 67
7885 00:43:37.480642 [Byte1]: 67
7886 00:43:37.484798
7887 00:43:37.484885 Set Vref, RX VrefLevel [Byte0]: 68
7888 00:43:37.488179 [Byte1]: 68
7889 00:43:37.492324
7890 00:43:37.492455 Set Vref, RX VrefLevel [Byte0]: 69
7891 00:43:37.495723 [Byte1]: 69
7892 00:43:37.499914
7893 00:43:37.500038 Set Vref, RX VrefLevel [Byte0]: 70
7894 00:43:37.503489 [Byte1]: 70
7895 00:43:37.507879
7896 00:43:37.508002 Set Vref, RX VrefLevel [Byte0]: 71
7897 00:43:37.511153 [Byte1]: 71
7898 00:43:37.515163
7899 00:43:37.515298 Set Vref, RX VrefLevel [Byte0]: 72
7900 00:43:37.518669 [Byte1]: 72
7901 00:43:37.522952
7902 00:43:37.523074 Set Vref, RX VrefLevel [Byte0]: 73
7903 00:43:37.526023 [Byte1]: 73
7904 00:43:37.530025
7905 00:43:37.530118 Set Vref, RX VrefLevel [Byte0]: 74
7906 00:43:37.533601 [Byte1]: 74
7907 00:43:37.537674
7908 00:43:37.537798 Final RX Vref Byte 0 = 58 to rank0
7909 00:43:37.541374 Final RX Vref Byte 1 = 62 to rank0
7910 00:43:37.544675 Final RX Vref Byte 0 = 58 to rank1
7911 00:43:37.548194 Final RX Vref Byte 1 = 62 to rank1==
7912 00:43:37.550952 Dram Type= 6, Freq= 0, CH_0, rank 0
7913 00:43:37.557612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7914 00:43:37.557746 ==
7915 00:43:37.557847 DQS Delay:
7916 00:43:37.557935 DQS0 = 0, DQS1 = 0
7917 00:43:37.560972 DQM Delay:
7918 00:43:37.561093 DQM0 = 134, DQM1 = 127
7919 00:43:37.564500 DQ Delay:
7920 00:43:37.567629 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7921 00:43:37.570906 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =140
7922 00:43:37.574416 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7923 00:43:37.577899 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7924 00:43:37.578014
7925 00:43:37.578113
7926 00:43:37.578205
7927 00:43:37.580649 [DramC_TX_OE_Calibration] TA2
7928 00:43:37.583952 Original DQ_B0 (3 6) =30, OEN = 27
7929 00:43:37.587903 Original DQ_B1 (3 6) =30, OEN = 27
7930 00:43:37.590674 24, 0x0, End_B0=24 End_B1=24
7931 00:43:37.590788 25, 0x0, End_B0=25 End_B1=25
7932 00:43:37.594024 26, 0x0, End_B0=26 End_B1=26
7933 00:43:37.597777 27, 0x0, End_B0=27 End_B1=27
7934 00:43:37.600960 28, 0x0, End_B0=28 End_B1=28
7935 00:43:37.603815 29, 0x0, End_B0=29 End_B1=29
7936 00:43:37.603920 30, 0x0, End_B0=30 End_B1=30
7937 00:43:37.607249 31, 0x4141, End_B0=30 End_B1=30
7938 00:43:37.610667 Byte0 end_step=30 best_step=27
7939 00:43:37.614192 Byte1 end_step=30 best_step=27
7940 00:43:37.617414 Byte0 TX OE(2T, 0.5T) = (3, 3)
7941 00:43:37.620945 Byte1 TX OE(2T, 0.5T) = (3, 3)
7942 00:43:37.621034
7943 00:43:37.621121
7944 00:43:37.627025 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7945 00:43:37.630474 CH0 RK0: MR19=303, MR18=2521
7946 00:43:37.637372 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7947 00:43:37.637573
7948 00:43:37.640517 ----->DramcWriteLeveling(PI) begin...
7949 00:43:37.640701 ==
7950 00:43:37.643869 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 00:43:37.647022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 00:43:37.647142 ==
7953 00:43:37.650783 Write leveling (Byte 0): 34 => 34
7954 00:43:37.653895 Write leveling (Byte 1): 27 => 27
7955 00:43:37.657671 DramcWriteLeveling(PI) end<-----
7956 00:43:37.657816
7957 00:43:37.657902 ==
7958 00:43:37.660814 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 00:43:37.664139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 00:43:37.664221 ==
7961 00:43:37.667584 [Gating] SW mode calibration
7962 00:43:37.674021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7963 00:43:37.680712 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7964 00:43:37.684103 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7965 00:43:37.687620 1 4 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7966 00:43:37.694157 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 00:43:37.696929 1 4 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7968 00:43:37.700348 1 4 16 | B1->B0 | 3030 303 | 1 1 | (1 1) (0 0)
7969 00:43:37.707091 1 4 20 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7970 00:43:37.710611 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7971 00:43:37.713347 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7972 00:43:37.720260 1 5 0 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7973 00:43:37.723584 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7974 00:43:37.726705 1 5 8 | B1->B0 | 3434 3938 | 1 1 | (1 1) (1 1)
7975 00:43:37.733802 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
7976 00:43:37.737129 1 5 16 | B1->B0 | 2f2f 3030 | 0 1 | (0 1) (0 1)
7977 00:43:37.739836 1 5 20 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7978 00:43:37.747110 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7979 00:43:37.750357 1 5 28 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7980 00:43:37.753447 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7981 00:43:37.760141 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7982 00:43:37.763813 1 6 8 | B1->B0 | 2323 404 | 0 1 | (0 0) (0 0)
7983 00:43:37.766800 1 6 12 | B1->B0 | 2525 3736 | 1 1 | (0 0) (1 1)
7984 00:43:37.773907 1 6 16 | B1->B0 | 3b3b 4645 | 0 1 | (0 0) (0 0)
7985 00:43:37.776851 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7986 00:43:37.780142 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 00:43:37.786824 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 00:43:37.789780 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 00:43:37.793198 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 00:43:37.796429 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 00:43:37.803624 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7992 00:43:37.806397 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7993 00:43:37.810410 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 00:43:37.816541 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 00:43:37.820124 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 00:43:37.823540 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 00:43:37.829804 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 00:43:37.833445 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 00:43:37.836547 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 00:43:37.843274 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 00:43:37.846778 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 00:43:37.850178 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 00:43:37.856759 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 00:43:37.859795 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 00:43:37.863381 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 00:43:37.869987 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 00:43:37.873186 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8008 00:43:37.876379 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8009 00:43:37.879566 Total UI for P1: 0, mck2ui 16
8010 00:43:37.882778 best dqsien dly found for B0: ( 1, 9, 12)
8011 00:43:37.889653 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 00:43:37.889759 Total UI for P1: 0, mck2ui 16
8013 00:43:37.896302 best dqsien dly found for B1: ( 1, 9, 14)
8014 00:43:37.900012 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8015 00:43:37.903404 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8016 00:43:37.903509
8017 00:43:37.906034 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8018 00:43:37.909943 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8019 00:43:37.912663 [Gating] SW calibration Done
8020 00:43:37.912742 ==
8021 00:43:37.916174 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 00:43:37.919838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 00:43:37.919940 ==
8024 00:43:37.923007 RX Vref Scan: 0
8025 00:43:37.923120
8026 00:43:37.923217 RX Vref 0 -> 0, step: 1
8027 00:43:37.923315
8028 00:43:37.926274 RX Delay 0 -> 252, step: 8
8029 00:43:37.929729 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8030 00:43:37.935903 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8031 00:43:37.939428 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8032 00:43:37.942609 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8033 00:43:37.946397 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8034 00:43:37.949222 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8035 00:43:37.956322 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8036 00:43:37.959609 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8037 00:43:37.962965 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8038 00:43:37.966385 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8039 00:43:37.969371 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8040 00:43:37.976157 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8041 00:43:37.979277 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8042 00:43:37.982663 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8043 00:43:37.985867 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8044 00:43:37.989927 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8045 00:43:37.990023 ==
8046 00:43:37.992663 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 00:43:37.999311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 00:43:37.999424 ==
8049 00:43:37.999519 DQS Delay:
8050 00:43:38.002694 DQS0 = 0, DQS1 = 0
8051 00:43:38.002769 DQM Delay:
8052 00:43:38.005952 DQM0 = 137, DQM1 = 129
8053 00:43:38.006028 DQ Delay:
8054 00:43:38.009012 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8055 00:43:38.012818 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8056 00:43:38.015956 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8057 00:43:38.019046 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8058 00:43:38.019150
8059 00:43:38.019249
8060 00:43:38.019339 ==
8061 00:43:38.022365 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 00:43:38.029298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 00:43:38.029404 ==
8064 00:43:38.029499
8065 00:43:38.029588
8066 00:43:38.029682 TX Vref Scan disable
8067 00:43:38.032800 == TX Byte 0 ==
8068 00:43:38.036373 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8069 00:43:38.042340 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8070 00:43:38.042449 == TX Byte 1 ==
8071 00:43:38.045890 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8072 00:43:38.052738 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8073 00:43:38.052828 ==
8074 00:43:38.056001 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 00:43:38.059371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 00:43:38.059475 ==
8077 00:43:38.073668
8078 00:43:38.076788 TX Vref early break, caculate TX vref
8079 00:43:38.080634 TX Vref=16, minBit 0, minWin=23, winSum=390
8080 00:43:38.083680 TX Vref=18, minBit 1, minWin=22, winSum=399
8081 00:43:38.086903 TX Vref=20, minBit 0, minWin=24, winSum=406
8082 00:43:38.090103 TX Vref=22, minBit 0, minWin=25, winSum=415
8083 00:43:38.093843 TX Vref=24, minBit 3, minWin=25, winSum=423
8084 00:43:38.100106 TX Vref=26, minBit 1, minWin=26, winSum=428
8085 00:43:38.103917 TX Vref=28, minBit 1, minWin=26, winSum=423
8086 00:43:38.106695 TX Vref=30, minBit 0, minWin=25, winSum=416
8087 00:43:38.110147 TX Vref=32, minBit 0, minWin=25, winSum=408
8088 00:43:38.113494 TX Vref=34, minBit 0, minWin=25, winSum=408
8089 00:43:38.117183 TX Vref=36, minBit 0, minWin=23, winSum=390
8090 00:43:38.123526 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 26
8091 00:43:38.123634
8092 00:43:38.126618 Final TX Range 0 Vref 26
8093 00:43:38.126721
8094 00:43:38.126811 ==
8095 00:43:38.130200 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 00:43:38.133363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 00:43:38.133486 ==
8098 00:43:38.133580
8099 00:43:38.133679
8100 00:43:38.136705 TX Vref Scan disable
8101 00:43:38.143679 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8102 00:43:38.143789 == TX Byte 0 ==
8103 00:43:38.147032 u2DelayCellOfst[0]=13 cells (4 PI)
8104 00:43:38.149817 u2DelayCellOfst[1]=16 cells (5 PI)
8105 00:43:38.153497 u2DelayCellOfst[2]=10 cells (3 PI)
8106 00:43:38.156680 u2DelayCellOfst[3]=10 cells (3 PI)
8107 00:43:38.160041 u2DelayCellOfst[4]=6 cells (2 PI)
8108 00:43:38.163904 u2DelayCellOfst[5]=0 cells (0 PI)
8109 00:43:38.166679 u2DelayCellOfst[6]=13 cells (4 PI)
8110 00:43:38.169918 u2DelayCellOfst[7]=16 cells (5 PI)
8111 00:43:38.173300 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8112 00:43:38.176652 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8113 00:43:38.179924 == TX Byte 1 ==
8114 00:43:38.183278 u2DelayCellOfst[8]=0 cells (0 PI)
8115 00:43:38.183380 u2DelayCellOfst[9]=0 cells (0 PI)
8116 00:43:38.186572 u2DelayCellOfst[10]=6 cells (2 PI)
8117 00:43:38.189878 u2DelayCellOfst[11]=3 cells (1 PI)
8118 00:43:38.193151 u2DelayCellOfst[12]=10 cells (3 PI)
8119 00:43:38.196825 u2DelayCellOfst[13]=10 cells (3 PI)
8120 00:43:38.199863 u2DelayCellOfst[14]=16 cells (5 PI)
8121 00:43:38.203469 u2DelayCellOfst[15]=10 cells (3 PI)
8122 00:43:38.206717 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8123 00:43:38.213147 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8124 00:43:38.213227 DramC Write-DBI on
8125 00:43:38.213293 ==
8126 00:43:38.216790 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 00:43:38.223543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 00:43:38.223623 ==
8129 00:43:38.223688
8130 00:43:38.223747
8131 00:43:38.223803 TX Vref Scan disable
8132 00:43:38.227305 == TX Byte 0 ==
8133 00:43:38.230552 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8134 00:43:38.233798 == TX Byte 1 ==
8135 00:43:38.237047 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8136 00:43:38.240050 DramC Write-DBI off
8137 00:43:38.240150
8138 00:43:38.240248 [DATLAT]
8139 00:43:38.240336 Freq=1600, CH0 RK1
8140 00:43:38.240408
8141 00:43:38.243580 DATLAT Default: 0xf
8142 00:43:38.243681 0, 0xFFFF, sum = 0
8143 00:43:38.247169 1, 0xFFFF, sum = 0
8144 00:43:38.247280 2, 0xFFFF, sum = 0
8145 00:43:38.250598 3, 0xFFFF, sum = 0
8146 00:43:38.253941 4, 0xFFFF, sum = 0
8147 00:43:38.254054 5, 0xFFFF, sum = 0
8148 00:43:38.257383 6, 0xFFFF, sum = 0
8149 00:43:38.257491 7, 0xFFFF, sum = 0
8150 00:43:38.260631 8, 0xFFFF, sum = 0
8151 00:43:38.260735 9, 0xFFFF, sum = 0
8152 00:43:38.263923 10, 0xFFFF, sum = 0
8153 00:43:38.264031 11, 0xFFFF, sum = 0
8154 00:43:38.266777 12, 0xFFFF, sum = 0
8155 00:43:38.266862 13, 0xFFFF, sum = 0
8156 00:43:38.270091 14, 0x0, sum = 1
8157 00:43:38.270173 15, 0x0, sum = 2
8158 00:43:38.273586 16, 0x0, sum = 3
8159 00:43:38.273668 17, 0x0, sum = 4
8160 00:43:38.276989 best_step = 15
8161 00:43:38.277070
8162 00:43:38.277135 ==
8163 00:43:38.280359 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 00:43:38.283611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 00:43:38.283693 ==
8166 00:43:38.283757 RX Vref Scan: 0
8167 00:43:38.286909
8168 00:43:38.286991 RX Vref 0 -> 0, step: 1
8169 00:43:38.287055
8170 00:43:38.290281 RX Delay 19 -> 252, step: 4
8171 00:43:38.293606 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8172 00:43:38.300561 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8173 00:43:38.303830 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8174 00:43:38.307098 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8175 00:43:38.310330 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8176 00:43:38.313450 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8177 00:43:38.320049 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8178 00:43:38.323140 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8179 00:43:38.326815 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8180 00:43:38.330176 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8181 00:43:38.333390 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8182 00:43:38.340432 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8183 00:43:38.343255 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8184 00:43:38.346598 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8185 00:43:38.349825 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8186 00:43:38.353532 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8187 00:43:38.356793 ==
8188 00:43:38.356886 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 00:43:38.363484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 00:43:38.363597 ==
8191 00:43:38.363666 DQS Delay:
8192 00:43:38.366474 DQS0 = 0, DQS1 = 0
8193 00:43:38.366556 DQM Delay:
8194 00:43:38.369914 DQM0 = 134, DQM1 = 127
8195 00:43:38.369995 DQ Delay:
8196 00:43:38.373200 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8197 00:43:38.376454 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8198 00:43:38.380035 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8199 00:43:38.383263 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8200 00:43:38.383375
8201 00:43:38.383468
8202 00:43:38.383554
8203 00:43:38.386605 [DramC_TX_OE_Calibration] TA2
8204 00:43:38.389885 Original DQ_B0 (3 6) =30, OEN = 27
8205 00:43:38.393261 Original DQ_B1 (3 6) =30, OEN = 27
8206 00:43:38.396708 24, 0x0, End_B0=24 End_B1=24
8207 00:43:38.399993 25, 0x0, End_B0=25 End_B1=25
8208 00:43:38.400076 26, 0x0, End_B0=26 End_B1=26
8209 00:43:38.403354 27, 0x0, End_B0=27 End_B1=27
8210 00:43:38.406479 28, 0x0, End_B0=28 End_B1=28
8211 00:43:38.409878 29, 0x0, End_B0=29 End_B1=29
8212 00:43:38.409962 30, 0x0, End_B0=30 End_B1=30
8213 00:43:38.413117 31, 0x4545, End_B0=30 End_B1=30
8214 00:43:38.416383 Byte0 end_step=30 best_step=27
8215 00:43:38.419536 Byte1 end_step=30 best_step=27
8216 00:43:38.422867 Byte0 TX OE(2T, 0.5T) = (3, 3)
8217 00:43:38.426063 Byte1 TX OE(2T, 0.5T) = (3, 3)
8218 00:43:38.426145
8219 00:43:38.426209
8220 00:43:38.433164 [DQSOSCAuto] RK1, (LSB)MR18= 0x230b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8221 00:43:38.436390 CH0 RK1: MR19=303, MR18=230B
8222 00:43:38.443015 CH0_RK1: MR19=0x303, MR18=0x230B, DQSOSC=392, MR23=63, INC=24, DEC=16
8223 00:43:38.446485 [RxdqsGatingPostProcess] freq 1600
8224 00:43:38.453084 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8225 00:43:38.453201 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 00:43:38.456168 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 00:43:38.459317 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 00:43:38.463117 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 00:43:38.466182 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 00:43:38.469323 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 00:43:38.473224 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 00:43:38.476358 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 00:43:38.479597 Pre-setting of DQS Precalculation
8234 00:43:38.483052 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8235 00:43:38.483132 ==
8236 00:43:38.486592 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 00:43:38.492610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 00:43:38.492696 ==
8239 00:43:38.495844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8240 00:43:38.499245 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8241 00:43:38.505980 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8242 00:43:38.512728 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8243 00:43:38.520067 [CA 0] Center 42 (12~72) winsize 61
8244 00:43:38.523605 [CA 1] Center 42 (13~72) winsize 60
8245 00:43:38.526706 [CA 2] Center 38 (9~68) winsize 60
8246 00:43:38.529771 [CA 3] Center 37 (8~67) winsize 60
8247 00:43:38.533024 [CA 4] Center 38 (9~68) winsize 60
8248 00:43:38.536564 [CA 5] Center 37 (8~67) winsize 60
8249 00:43:38.536673
8250 00:43:38.539806 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8251 00:43:38.539922
8252 00:43:38.543160 [CATrainingPosCal] consider 1 rank data
8253 00:43:38.546218 u2DelayCellTimex100 = 290/100 ps
8254 00:43:38.552771 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8255 00:43:38.556606 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8256 00:43:38.559945 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8257 00:43:38.563279 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8258 00:43:38.566846 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8259 00:43:38.569513 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8260 00:43:38.569600
8261 00:43:38.573020 CA PerBit enable=1, Macro0, CA PI delay=37
8262 00:43:38.573114
8263 00:43:38.576428 [CBTSetCACLKResult] CA Dly = 37
8264 00:43:38.580240 CS Dly: 10 (0~41)
8265 00:43:38.583180 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8266 00:43:38.586039 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8267 00:43:38.586116 ==
8268 00:43:38.589669 Dram Type= 6, Freq= 0, CH_1, rank 1
8269 00:43:38.592882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 00:43:38.596200 ==
8271 00:43:38.599431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 00:43:38.602914 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 00:43:38.609664 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 00:43:38.616318 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 00:43:38.623600 [CA 0] Center 42 (12~72) winsize 61
8276 00:43:38.626256 [CA 1] Center 42 (12~72) winsize 61
8277 00:43:38.629728 [CA 2] Center 38 (9~68) winsize 60
8278 00:43:38.632963 [CA 3] Center 38 (8~68) winsize 61
8279 00:43:38.636721 [CA 4] Center 38 (8~69) winsize 62
8280 00:43:38.639865 [CA 5] Center 37 (8~66) winsize 59
8281 00:43:38.639964
8282 00:43:38.643190 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8283 00:43:38.643274
8284 00:43:38.646670 [CATrainingPosCal] consider 2 rank data
8285 00:43:38.650173 u2DelayCellTimex100 = 290/100 ps
8286 00:43:38.652815 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8287 00:43:38.659758 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8288 00:43:38.663172 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8289 00:43:38.666637 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8290 00:43:38.669933 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8291 00:43:38.673125 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8292 00:43:38.673202
8293 00:43:38.676316 CA PerBit enable=1, Macro0, CA PI delay=37
8294 00:43:38.676404
8295 00:43:38.679756 [CBTSetCACLKResult] CA Dly = 37
8296 00:43:38.683120 CS Dly: 12 (0~45)
8297 00:43:38.686175 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 00:43:38.689405 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 00:43:38.689488
8300 00:43:38.692778 ----->DramcWriteLeveling(PI) begin...
8301 00:43:38.692862 ==
8302 00:43:38.696639 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 00:43:38.699397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 00:43:38.702992 ==
8305 00:43:38.706396 Write leveling (Byte 0): 28 => 28
8306 00:43:38.706478 Write leveling (Byte 1): 29 => 29
8307 00:43:38.709716 DramcWriteLeveling(PI) end<-----
8308 00:43:38.709797
8309 00:43:38.709861 ==
8310 00:43:38.712499 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 00:43:38.719614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 00:43:38.719698 ==
8313 00:43:38.723150 [Gating] SW mode calibration
8314 00:43:38.729300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8315 00:43:38.732659 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8316 00:43:38.739329 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 00:43:38.742725 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 00:43:38.745889 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (1 1) (1 1)
8319 00:43:38.752471 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8320 00:43:38.755674 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 00:43:38.759618 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 00:43:38.765605 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 00:43:38.769026 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 00:43:38.772379 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 00:43:38.779029 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 00:43:38.782354 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
8327 00:43:38.785669 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8328 00:43:38.788826 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 00:43:38.795837 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 00:43:38.798905 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 00:43:38.802587 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 00:43:38.808877 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 00:43:38.812713 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 00:43:38.815781 1 6 8 | B1->B0 | 2626 3d3d | 0 0 | (0 0) (0 0)
8335 00:43:38.822188 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8336 00:43:38.825918 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 00:43:38.828905 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 00:43:38.835932 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 00:43:38.838674 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 00:43:38.842068 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 00:43:38.848915 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 00:43:38.852178 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8343 00:43:38.855874 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 00:43:38.862068 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 00:43:38.865424 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 00:43:38.868978 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 00:43:38.875755 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 00:43:38.879176 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 00:43:38.882536 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 00:43:38.888755 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 00:43:38.891960 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 00:43:38.895401 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 00:43:38.901801 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 00:43:38.905172 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 00:43:38.908839 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 00:43:38.915444 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 00:43:38.918616 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 00:43:38.922109 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8359 00:43:38.925609 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 00:43:38.932197 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 00:43:38.935463 Total UI for P1: 0, mck2ui 16
8362 00:43:38.938666 best dqsien dly found for B0: ( 1, 9, 10)
8363 00:43:38.941823 Total UI for P1: 0, mck2ui 16
8364 00:43:38.944977 best dqsien dly found for B1: ( 1, 9, 10)
8365 00:43:38.948496 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8366 00:43:38.951941 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8367 00:43:38.952024
8368 00:43:38.955305 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8369 00:43:38.958633 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 00:43:38.961855 [Gating] SW calibration Done
8371 00:43:38.961937 ==
8372 00:43:38.965063 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 00:43:38.968628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 00:43:38.968711 ==
8375 00:43:38.972018 RX Vref Scan: 0
8376 00:43:38.972101
8377 00:43:38.974740 RX Vref 0 -> 0, step: 1
8378 00:43:38.974842
8379 00:43:38.974911 RX Delay 0 -> 252, step: 8
8380 00:43:38.981658 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8381 00:43:38.985081 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8382 00:43:38.988463 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8383 00:43:38.991874 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8384 00:43:38.995225 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8385 00:43:39.001312 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8386 00:43:39.004604 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8387 00:43:39.008043 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8388 00:43:39.011426 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8389 00:43:39.014682 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8390 00:43:39.021456 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8391 00:43:39.024583 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8392 00:43:39.027693 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8393 00:43:39.031492 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8394 00:43:39.034875 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8395 00:43:39.041221 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8396 00:43:39.041343 ==
8397 00:43:39.044618 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 00:43:39.048111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 00:43:39.048195 ==
8400 00:43:39.048260 DQS Delay:
8401 00:43:39.051593 DQS0 = 0, DQS1 = 0
8402 00:43:39.051674 DQM Delay:
8403 00:43:39.055083 DQM0 = 137, DQM1 = 134
8404 00:43:39.055166 DQ Delay:
8405 00:43:39.058102 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8406 00:43:39.061311 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8407 00:43:39.064526 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8408 00:43:39.067719 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =147
8409 00:43:39.067802
8410 00:43:39.067909
8411 00:43:39.071552 ==
8412 00:43:39.071653 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 00:43:39.079352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 00:43:39.079445 ==
8415 00:43:39.079511
8416 00:43:39.079572
8417 00:43:39.081470 TX Vref Scan disable
8418 00:43:39.081569 == TX Byte 0 ==
8419 00:43:39.084748 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8420 00:43:39.091617 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8421 00:43:39.091702 == TX Byte 1 ==
8422 00:43:39.094317 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8423 00:43:39.101309 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8424 00:43:39.101392 ==
8425 00:43:39.104588 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 00:43:39.108013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 00:43:39.108088 ==
8428 00:43:39.120254
8429 00:43:39.123694 TX Vref early break, caculate TX vref
8430 00:43:39.127064 TX Vref=16, minBit 0, minWin=23, winSum=376
8431 00:43:39.130334 TX Vref=18, minBit 0, minWin=23, winSum=383
8432 00:43:39.133796 TX Vref=20, minBit 0, minWin=24, winSum=394
8433 00:43:39.136909 TX Vref=22, minBit 1, minWin=23, winSum=403
8434 00:43:39.140792 TX Vref=24, minBit 0, minWin=25, winSum=411
8435 00:43:39.146998 TX Vref=26, minBit 0, minWin=25, winSum=418
8436 00:43:39.150581 TX Vref=28, minBit 0, minWin=25, winSum=424
8437 00:43:39.154073 TX Vref=30, minBit 1, minWin=24, winSum=415
8438 00:43:39.156847 TX Vref=32, minBit 0, minWin=24, winSum=409
8439 00:43:39.160238 TX Vref=34, minBit 0, minWin=24, winSum=399
8440 00:43:39.167018 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8441 00:43:39.167105
8442 00:43:39.170237 Final TX Range 0 Vref 28
8443 00:43:39.170321
8444 00:43:39.170386 ==
8445 00:43:39.173653 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 00:43:39.176821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 00:43:39.176905 ==
8448 00:43:39.176970
8449 00:43:39.177029
8450 00:43:39.180473 TX Vref Scan disable
8451 00:43:39.186737 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8452 00:43:39.186823 == TX Byte 0 ==
8453 00:43:39.190283 u2DelayCellOfst[0]=16 cells (5 PI)
8454 00:43:39.193728 u2DelayCellOfst[1]=10 cells (3 PI)
8455 00:43:39.197142 u2DelayCellOfst[2]=0 cells (0 PI)
8456 00:43:39.200141 u2DelayCellOfst[3]=6 cells (2 PI)
8457 00:43:39.203598 u2DelayCellOfst[4]=6 cells (2 PI)
8458 00:43:39.206969 u2DelayCellOfst[5]=16 cells (5 PI)
8459 00:43:39.207086 u2DelayCellOfst[6]=16 cells (5 PI)
8460 00:43:39.210256 u2DelayCellOfst[7]=6 cells (2 PI)
8461 00:43:39.217027 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8462 00:43:39.220516 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 00:43:39.220600 == TX Byte 1 ==
8464 00:43:39.223783 u2DelayCellOfst[8]=0 cells (0 PI)
8465 00:43:39.227210 u2DelayCellOfst[9]=6 cells (2 PI)
8466 00:43:39.230001 u2DelayCellOfst[10]=13 cells (4 PI)
8467 00:43:39.233400 u2DelayCellOfst[11]=3 cells (1 PI)
8468 00:43:39.236931 u2DelayCellOfst[12]=16 cells (5 PI)
8469 00:43:39.240089 u2DelayCellOfst[13]=16 cells (5 PI)
8470 00:43:39.243187 u2DelayCellOfst[14]=20 cells (6 PI)
8471 00:43:39.247429 u2DelayCellOfst[15]=16 cells (5 PI)
8472 00:43:39.250076 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8473 00:43:39.256848 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8474 00:43:39.256928 DramC Write-DBI on
8475 00:43:39.257001 ==
8476 00:43:39.259716 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 00:43:39.262952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 00:43:39.263056 ==
8479 00:43:39.266658
8480 00:43:39.266770
8481 00:43:39.266861 TX Vref Scan disable
8482 00:43:39.270130 == TX Byte 0 ==
8483 00:43:39.273632 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8484 00:43:39.276782 == TX Byte 1 ==
8485 00:43:39.280302 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8486 00:43:39.280397 DramC Write-DBI off
8487 00:43:39.280460
8488 00:43:39.282928 [DATLAT]
8489 00:43:39.283000 Freq=1600, CH1 RK0
8490 00:43:39.283064
8491 00:43:39.286837 DATLAT Default: 0xf
8492 00:43:39.286938 0, 0xFFFF, sum = 0
8493 00:43:39.290251 1, 0xFFFF, sum = 0
8494 00:43:39.290335 2, 0xFFFF, sum = 0
8495 00:43:39.293239 3, 0xFFFF, sum = 0
8496 00:43:39.293313 4, 0xFFFF, sum = 0
8497 00:43:39.296301 5, 0xFFFF, sum = 0
8498 00:43:39.299902 6, 0xFFFF, sum = 0
8499 00:43:39.300013 7, 0xFFFF, sum = 0
8500 00:43:39.303287 8, 0xFFFF, sum = 0
8501 00:43:39.303405 9, 0xFFFF, sum = 0
8502 00:43:39.306764 10, 0xFFFF, sum = 0
8503 00:43:39.306883 11, 0xFFFF, sum = 0
8504 00:43:39.309469 12, 0xFFFF, sum = 0
8505 00:43:39.309581 13, 0xFFFF, sum = 0
8506 00:43:39.312878 14, 0x0, sum = 1
8507 00:43:39.312972 15, 0x0, sum = 2
8508 00:43:39.316209 16, 0x0, sum = 3
8509 00:43:39.316333 17, 0x0, sum = 4
8510 00:43:39.319685 best_step = 15
8511 00:43:39.319805
8512 00:43:39.319901 ==
8513 00:43:39.323078 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 00:43:39.326638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 00:43:39.326759 ==
8516 00:43:39.326863 RX Vref Scan: 1
8517 00:43:39.329337
8518 00:43:39.329419 Set Vref Range= 24 -> 127
8519 00:43:39.329484
8520 00:43:39.332791 RX Vref 24 -> 127, step: 1
8521 00:43:39.332904
8522 00:43:39.336313 RX Delay 27 -> 252, step: 4
8523 00:43:39.336439
8524 00:43:39.339802 Set Vref, RX VrefLevel [Byte0]: 24
8525 00:43:39.342577 [Byte1]: 24
8526 00:43:39.342660
8527 00:43:39.346074 Set Vref, RX VrefLevel [Byte0]: 25
8528 00:43:39.349403 [Byte1]: 25
8529 00:43:39.349518
8530 00:43:39.353148 Set Vref, RX VrefLevel [Byte0]: 26
8531 00:43:39.355897 [Byte1]: 26
8532 00:43:39.359650
8533 00:43:39.359767 Set Vref, RX VrefLevel [Byte0]: 27
8534 00:43:39.363259 [Byte1]: 27
8535 00:43:39.367080
8536 00:43:39.367162 Set Vref, RX VrefLevel [Byte0]: 28
8537 00:43:39.370728 [Byte1]: 28
8538 00:43:39.375095
8539 00:43:39.375177 Set Vref, RX VrefLevel [Byte0]: 29
8540 00:43:39.378130 [Byte1]: 29
8541 00:43:39.382602
8542 00:43:39.382684 Set Vref, RX VrefLevel [Byte0]: 30
8543 00:43:39.385997 [Byte1]: 30
8544 00:43:39.390077
8545 00:43:39.390195 Set Vref, RX VrefLevel [Byte0]: 31
8546 00:43:39.393400 [Byte1]: 31
8547 00:43:39.397334
8548 00:43:39.397415 Set Vref, RX VrefLevel [Byte0]: 32
8549 00:43:39.400720 [Byte1]: 32
8550 00:43:39.405185
8551 00:43:39.405267 Set Vref, RX VrefLevel [Byte0]: 33
8552 00:43:39.408531 [Byte1]: 33
8553 00:43:39.412739
8554 00:43:39.412820 Set Vref, RX VrefLevel [Byte0]: 34
8555 00:43:39.416065 [Byte1]: 34
8556 00:43:39.419960
8557 00:43:39.420061 Set Vref, RX VrefLevel [Byte0]: 35
8558 00:43:39.423297 [Byte1]: 35
8559 00:43:39.427384
8560 00:43:39.427465 Set Vref, RX VrefLevel [Byte0]: 36
8561 00:43:39.430619 [Byte1]: 36
8562 00:43:39.435492
8563 00:43:39.435572 Set Vref, RX VrefLevel [Byte0]: 37
8564 00:43:39.438192 [Byte1]: 37
8565 00:43:39.443125
8566 00:43:39.443236 Set Vref, RX VrefLevel [Byte0]: 38
8567 00:43:39.445737 [Byte1]: 38
8568 00:43:39.450372
8569 00:43:39.450480 Set Vref, RX VrefLevel [Byte0]: 39
8570 00:43:39.453322 [Byte1]: 39
8571 00:43:39.457902
8572 00:43:39.457973 Set Vref, RX VrefLevel [Byte0]: 40
8573 00:43:39.461335 [Byte1]: 40
8574 00:43:39.465407
8575 00:43:39.465482 Set Vref, RX VrefLevel [Byte0]: 41
8576 00:43:39.468704 [Byte1]: 41
8577 00:43:39.473063
8578 00:43:39.473160 Set Vref, RX VrefLevel [Byte0]: 42
8579 00:43:39.475949 [Byte1]: 42
8580 00:43:39.480666
8581 00:43:39.480742 Set Vref, RX VrefLevel [Byte0]: 43
8582 00:43:39.483866 [Byte1]: 43
8583 00:43:39.487705
8584 00:43:39.487800 Set Vref, RX VrefLevel [Byte0]: 44
8585 00:43:39.490849 [Byte1]: 44
8586 00:43:39.495216
8587 00:43:39.495293 Set Vref, RX VrefLevel [Byte0]: 45
8588 00:43:39.498667 [Byte1]: 45
8589 00:43:39.502733
8590 00:43:39.502835 Set Vref, RX VrefLevel [Byte0]: 46
8591 00:43:39.506018 [Byte1]: 46
8592 00:43:39.510760
8593 00:43:39.510858 Set Vref, RX VrefLevel [Byte0]: 47
8594 00:43:39.513523 [Byte1]: 47
8595 00:43:39.518099
8596 00:43:39.518175 Set Vref, RX VrefLevel [Byte0]: 48
8597 00:43:39.521222 [Byte1]: 48
8598 00:43:39.525609
8599 00:43:39.525680 Set Vref, RX VrefLevel [Byte0]: 49
8600 00:43:39.528620 [Byte1]: 49
8601 00:43:39.533084
8602 00:43:39.533167 Set Vref, RX VrefLevel [Byte0]: 50
8603 00:43:39.536480 [Byte1]: 50
8604 00:43:39.540582
8605 00:43:39.540654 Set Vref, RX VrefLevel [Byte0]: 51
8606 00:43:39.544036 [Byte1]: 51
8607 00:43:39.548106
8608 00:43:39.548176 Set Vref, RX VrefLevel [Byte0]: 52
8609 00:43:39.551662 [Byte1]: 52
8610 00:43:39.555626
8611 00:43:39.555711 Set Vref, RX VrefLevel [Byte0]: 53
8612 00:43:39.559137 [Byte1]: 53
8613 00:43:39.563293
8614 00:43:39.563395 Set Vref, RX VrefLevel [Byte0]: 54
8615 00:43:39.566460 [Byte1]: 54
8616 00:43:39.570527
8617 00:43:39.570597 Set Vref, RX VrefLevel [Byte0]: 55
8618 00:43:39.573988 [Byte1]: 55
8619 00:43:39.578029
8620 00:43:39.578102 Set Vref, RX VrefLevel [Byte0]: 56
8621 00:43:39.581326 [Byte1]: 56
8622 00:43:39.585930
8623 00:43:39.586002 Set Vref, RX VrefLevel [Byte0]: 57
8624 00:43:39.588926 [Byte1]: 57
8625 00:43:39.593438
8626 00:43:39.593541 Set Vref, RX VrefLevel [Byte0]: 58
8627 00:43:39.596705 [Byte1]: 58
8628 00:43:39.600577
8629 00:43:39.600657 Set Vref, RX VrefLevel [Byte0]: 59
8630 00:43:39.604510 [Byte1]: 59
8631 00:43:39.607988
8632 00:43:39.608063 Set Vref, RX VrefLevel [Byte0]: 60
8633 00:43:39.611875 [Byte1]: 60
8634 00:43:39.616006
8635 00:43:39.616087 Set Vref, RX VrefLevel [Byte0]: 61
8636 00:43:39.619332 [Byte1]: 61
8637 00:43:39.623464
8638 00:43:39.623538 Set Vref, RX VrefLevel [Byte0]: 62
8639 00:43:39.626838 [Byte1]: 62
8640 00:43:39.630707
8641 00:43:39.630812 Set Vref, RX VrefLevel [Byte0]: 63
8642 00:43:39.634149 [Byte1]: 63
8643 00:43:39.638602
8644 00:43:39.638676 Set Vref, RX VrefLevel [Byte0]: 64
8645 00:43:39.641606 [Byte1]: 64
8646 00:43:39.646301
8647 00:43:39.646407 Set Vref, RX VrefLevel [Byte0]: 65
8648 00:43:39.649081 [Byte1]: 65
8649 00:43:39.653902
8650 00:43:39.653985 Set Vref, RX VrefLevel [Byte0]: 66
8651 00:43:39.656778 [Byte1]: 66
8652 00:43:39.660923
8653 00:43:39.661005 Set Vref, RX VrefLevel [Byte0]: 67
8654 00:43:39.664298 [Byte1]: 67
8655 00:43:39.668902
8656 00:43:39.669022 Set Vref, RX VrefLevel [Byte0]: 68
8657 00:43:39.671706 [Byte1]: 68
8658 00:43:39.676431
8659 00:43:39.676513 Set Vref, RX VrefLevel [Byte0]: 69
8660 00:43:39.679240 [Byte1]: 69
8661 00:43:39.683610
8662 00:43:39.683692 Set Vref, RX VrefLevel [Byte0]: 70
8663 00:43:39.686769 [Byte1]: 70
8664 00:43:39.690890
8665 00:43:39.690965 Set Vref, RX VrefLevel [Byte0]: 71
8666 00:43:39.694187 [Byte1]: 71
8667 00:43:39.698422
8668 00:43:39.698498 Set Vref, RX VrefLevel [Byte0]: 72
8669 00:43:39.702167 [Byte1]: 72
8670 00:43:39.705980
8671 00:43:39.706063 Set Vref, RX VrefLevel [Byte0]: 73
8672 00:43:39.709849 [Byte1]: 73
8673 00:43:39.713675
8674 00:43:39.713757 Set Vref, RX VrefLevel [Byte0]: 74
8675 00:43:39.716903 [Byte1]: 74
8676 00:43:39.721455
8677 00:43:39.721537 Set Vref, RX VrefLevel [Byte0]: 75
8678 00:43:39.724780 [Byte1]: 75
8679 00:43:39.728778
8680 00:43:39.728860 Set Vref, RX VrefLevel [Byte0]: 76
8681 00:43:39.732083 [Byte1]: 76
8682 00:43:39.736449
8683 00:43:39.736531 Final RX Vref Byte 0 = 59 to rank0
8684 00:43:39.739950 Final RX Vref Byte 1 = 56 to rank0
8685 00:43:39.743315 Final RX Vref Byte 0 = 59 to rank1
8686 00:43:39.746561 Final RX Vref Byte 1 = 56 to rank1==
8687 00:43:39.749849 Dram Type= 6, Freq= 0, CH_1, rank 0
8688 00:43:39.756153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8689 00:43:39.756236 ==
8690 00:43:39.756302 DQS Delay:
8691 00:43:39.756374 DQS0 = 0, DQS1 = 0
8692 00:43:39.759481 DQM Delay:
8693 00:43:39.759581 DQM0 = 134, DQM1 = 131
8694 00:43:39.762843 DQ Delay:
8695 00:43:39.766182 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8696 00:43:39.769770 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8697 00:43:39.773074 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8698 00:43:39.776638 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8699 00:43:39.776737
8700 00:43:39.776827
8701 00:43:39.776917
8702 00:43:39.780039 [DramC_TX_OE_Calibration] TA2
8703 00:43:39.782898 Original DQ_B0 (3 6) =30, OEN = 27
8704 00:43:39.786338 Original DQ_B1 (3 6) =30, OEN = 27
8705 00:43:39.789940 24, 0x0, End_B0=24 End_B1=24
8706 00:43:39.790024 25, 0x0, End_B0=25 End_B1=25
8707 00:43:39.793372 26, 0x0, End_B0=26 End_B1=26
8708 00:43:39.796113 27, 0x0, End_B0=27 End_B1=27
8709 00:43:39.799600 28, 0x0, End_B0=28 End_B1=28
8710 00:43:39.799684 29, 0x0, End_B0=29 End_B1=29
8711 00:43:39.802942 30, 0x0, End_B0=30 End_B1=30
8712 00:43:39.806213 31, 0x4141, End_B0=30 End_B1=30
8713 00:43:39.809444 Byte0 end_step=30 best_step=27
8714 00:43:39.813248 Byte1 end_step=30 best_step=27
8715 00:43:39.816713 Byte0 TX OE(2T, 0.5T) = (3, 3)
8716 00:43:39.816830 Byte1 TX OE(2T, 0.5T) = (3, 3)
8717 00:43:39.816896
8718 00:43:39.819701
8719 00:43:39.826342 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8720 00:43:39.829411 CH1 RK0: MR19=303, MR18=1724
8721 00:43:39.836624 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8722 00:43:39.836707
8723 00:43:39.839728 ----->DramcWriteLeveling(PI) begin...
8724 00:43:39.839833 ==
8725 00:43:39.842850 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 00:43:39.846254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 00:43:39.846353 ==
8728 00:43:39.849769 Write leveling (Byte 0): 27 => 27
8729 00:43:39.852489 Write leveling (Byte 1): 30 => 30
8730 00:43:39.855922 DramcWriteLeveling(PI) end<-----
8731 00:43:39.856022
8732 00:43:39.856109 ==
8733 00:43:39.859856 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 00:43:39.862971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 00:43:39.863045 ==
8736 00:43:39.865955 [Gating] SW mode calibration
8737 00:43:39.872641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8738 00:43:39.879224 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8739 00:43:39.882738 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 00:43:39.886289 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 00:43:39.893160 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8742 00:43:39.895769 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8743 00:43:39.899437 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 00:43:39.905773 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 00:43:39.909386 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 00:43:39.912705 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 00:43:39.919215 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 00:43:39.922876 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8749 00:43:39.926198 1 5 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 1) (1 0)
8750 00:43:39.932650 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8751 00:43:39.935642 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 00:43:39.939393 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 00:43:39.946125 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 00:43:39.949211 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 00:43:39.952371 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 00:43:39.956291 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 00:43:39.962548 1 6 8 | B1->B0 | 3535 2323 | 1 0 | (0 0) (0 0)
8758 00:43:39.966010 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8759 00:43:39.969193 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 00:43:39.975687 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 00:43:39.979465 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 00:43:39.982894 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 00:43:39.989221 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 00:43:39.992672 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8765 00:43:39.996146 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8766 00:43:40.002316 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 00:43:40.005833 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8768 00:43:40.009317 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 00:43:40.015580 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 00:43:40.018872 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 00:43:40.022243 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 00:43:40.028808 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 00:43:40.032570 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 00:43:40.035852 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:43:40.042564 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:43:40.045404 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:43:40.048627 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:43:40.055369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:43:40.059106 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:43:40.062107 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8781 00:43:40.069115 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 00:43:40.072563 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8783 00:43:40.075778 Total UI for P1: 0, mck2ui 16
8784 00:43:40.078644 best dqsien dly found for B1: ( 1, 9, 6)
8785 00:43:40.081887 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 00:43:40.085847 Total UI for P1: 0, mck2ui 16
8787 00:43:40.089114 best dqsien dly found for B0: ( 1, 9, 12)
8788 00:43:40.092431 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8789 00:43:40.095693 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8790 00:43:40.095768
8791 00:43:40.098816 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8792 00:43:40.105729 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8793 00:43:40.105807 [Gating] SW calibration Done
8794 00:43:40.105870 ==
8795 00:43:40.108577 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 00:43:40.115499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 00:43:40.115584 ==
8798 00:43:40.115649 RX Vref Scan: 0
8799 00:43:40.115711
8800 00:43:40.119023 RX Vref 0 -> 0, step: 1
8801 00:43:40.119106
8802 00:43:40.122111 RX Delay 0 -> 252, step: 8
8803 00:43:40.125583 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8804 00:43:40.128947 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8805 00:43:40.132290 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8806 00:43:40.135686 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8807 00:43:40.142024 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8808 00:43:40.145131 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8809 00:43:40.148953 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8810 00:43:40.152280 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8811 00:43:40.155110 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8812 00:43:40.161831 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8813 00:43:40.165600 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8814 00:43:40.168775 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8815 00:43:40.171948 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8816 00:43:40.175158 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8817 00:43:40.182086 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8818 00:43:40.185605 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8819 00:43:40.185685 ==
8820 00:43:40.188933 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 00:43:40.191647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 00:43:40.191722 ==
8823 00:43:40.195317 DQS Delay:
8824 00:43:40.195420 DQS0 = 0, DQS1 = 0
8825 00:43:40.195515 DQM Delay:
8826 00:43:40.198584 DQM0 = 136, DQM1 = 133
8827 00:43:40.198683 DQ Delay:
8828 00:43:40.201961 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8829 00:43:40.205238 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8830 00:43:40.212113 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8831 00:43:40.214852 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8832 00:43:40.214954
8833 00:43:40.215051
8834 00:43:40.215139 ==
8835 00:43:40.218260 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 00:43:40.221659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 00:43:40.221733 ==
8838 00:43:40.221794
8839 00:43:40.221852
8840 00:43:40.224985 TX Vref Scan disable
8841 00:43:40.228313 == TX Byte 0 ==
8842 00:43:40.231989 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8843 00:43:40.235250 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8844 00:43:40.238642 == TX Byte 1 ==
8845 00:43:40.241306 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8846 00:43:40.244685 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8847 00:43:40.244764 ==
8848 00:43:40.248043 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 00:43:40.251336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 00:43:40.254741 ==
8851 00:43:40.266488
8852 00:43:40.270265 TX Vref early break, caculate TX vref
8853 00:43:40.273682 TX Vref=16, minBit 0, minWin=22, winSum=383
8854 00:43:40.277035 TX Vref=18, minBit 0, minWin=23, winSum=386
8855 00:43:40.279782 TX Vref=20, minBit 0, minWin=24, winSum=399
8856 00:43:40.283171 TX Vref=22, minBit 0, minWin=24, winSum=409
8857 00:43:40.287067 TX Vref=24, minBit 0, minWin=25, winSum=415
8858 00:43:40.293689 TX Vref=26, minBit 0, minWin=26, winSum=425
8859 00:43:40.296927 TX Vref=28, minBit 0, minWin=25, winSum=423
8860 00:43:40.300246 TX Vref=30, minBit 1, minWin=25, winSum=416
8861 00:43:40.303417 TX Vref=32, minBit 6, minWin=24, winSum=410
8862 00:43:40.307032 TX Vref=34, minBit 0, minWin=24, winSum=405
8863 00:43:40.310357 TX Vref=36, minBit 0, minWin=24, winSum=397
8864 00:43:40.316675 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8865 00:43:40.316754
8866 00:43:40.320151 Final TX Range 0 Vref 26
8867 00:43:40.320252
8868 00:43:40.320349 ==
8869 00:43:40.323515 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 00:43:40.326885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 00:43:40.326956 ==
8872 00:43:40.327020
8873 00:43:40.327077
8874 00:43:40.330204 TX Vref Scan disable
8875 00:43:40.336955 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8876 00:43:40.337034 == TX Byte 0 ==
8877 00:43:40.340542 u2DelayCellOfst[0]=13 cells (4 PI)
8878 00:43:40.343253 u2DelayCellOfst[1]=10 cells (3 PI)
8879 00:43:40.346606 u2DelayCellOfst[2]=0 cells (0 PI)
8880 00:43:40.349951 u2DelayCellOfst[3]=6 cells (2 PI)
8881 00:43:40.353395 u2DelayCellOfst[4]=6 cells (2 PI)
8882 00:43:40.356821 u2DelayCellOfst[5]=16 cells (5 PI)
8883 00:43:40.360250 u2DelayCellOfst[6]=16 cells (5 PI)
8884 00:43:40.363674 u2DelayCellOfst[7]=6 cells (2 PI)
8885 00:43:40.366888 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8886 00:43:40.370170 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8887 00:43:40.373232 == TX Byte 1 ==
8888 00:43:40.373311 u2DelayCellOfst[8]=0 cells (0 PI)
8889 00:43:40.376431 u2DelayCellOfst[9]=3 cells (1 PI)
8890 00:43:40.379790 u2DelayCellOfst[10]=10 cells (3 PI)
8891 00:43:40.383268 u2DelayCellOfst[11]=3 cells (1 PI)
8892 00:43:40.386717 u2DelayCellOfst[12]=13 cells (4 PI)
8893 00:43:40.389918 u2DelayCellOfst[13]=16 cells (5 PI)
8894 00:43:40.393386 u2DelayCellOfst[14]=16 cells (5 PI)
8895 00:43:40.396627 u2DelayCellOfst[15]=16 cells (5 PI)
8896 00:43:40.399800 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8897 00:43:40.406590 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8898 00:43:40.406696 DramC Write-DBI on
8899 00:43:40.406793 ==
8900 00:43:40.409889 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 00:43:40.413251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 00:43:40.416321 ==
8903 00:43:40.416405
8904 00:43:40.416465
8905 00:43:40.416523 TX Vref Scan disable
8906 00:43:40.419900 == TX Byte 0 ==
8907 00:43:40.423179 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8908 00:43:40.426899 == TX Byte 1 ==
8909 00:43:40.430012 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8910 00:43:40.433268 DramC Write-DBI off
8911 00:43:40.433356
8912 00:43:40.433456 [DATLAT]
8913 00:43:40.433548 Freq=1600, CH1 RK1
8914 00:43:40.433634
8915 00:43:40.436822 DATLAT Default: 0xf
8916 00:43:40.436891 0, 0xFFFF, sum = 0
8917 00:43:40.439656 1, 0xFFFF, sum = 0
8918 00:43:40.442992 2, 0xFFFF, sum = 0
8919 00:43:40.443093 3, 0xFFFF, sum = 0
8920 00:43:40.446328 4, 0xFFFF, sum = 0
8921 00:43:40.446434 5, 0xFFFF, sum = 0
8922 00:43:40.449914 6, 0xFFFF, sum = 0
8923 00:43:40.449996 7, 0xFFFF, sum = 0
8924 00:43:40.453220 8, 0xFFFF, sum = 0
8925 00:43:40.453291 9, 0xFFFF, sum = 0
8926 00:43:40.456582 10, 0xFFFF, sum = 0
8927 00:43:40.456664 11, 0xFFFF, sum = 0
8928 00:43:40.459988 12, 0xFFFF, sum = 0
8929 00:43:40.460062 13, 0xFFFF, sum = 0
8930 00:43:40.463364 14, 0x0, sum = 1
8931 00:43:40.463439 15, 0x0, sum = 2
8932 00:43:40.466823 16, 0x0, sum = 3
8933 00:43:40.466902 17, 0x0, sum = 4
8934 00:43:40.469532 best_step = 15
8935 00:43:40.469634
8936 00:43:40.469723 ==
8937 00:43:40.472828 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 00:43:40.476822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 00:43:40.476925 ==
8940 00:43:40.477015 RX Vref Scan: 0
8941 00:43:40.479868
8942 00:43:40.479940 RX Vref 0 -> 0, step: 1
8943 00:43:40.480000
8944 00:43:40.482944 RX Delay 19 -> 252, step: 4
8945 00:43:40.486621 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8946 00:43:40.493265 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8947 00:43:40.496649 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8948 00:43:40.499992 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8949 00:43:40.502714 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8950 00:43:40.506620 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8951 00:43:40.509780 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8952 00:43:40.516229 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8953 00:43:40.519674 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8954 00:43:40.523074 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8955 00:43:40.526316 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8956 00:43:40.529389 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8957 00:43:40.536563 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8958 00:43:40.539596 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8959 00:43:40.543046 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8960 00:43:40.546045 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8961 00:43:40.546130 ==
8962 00:43:40.549648 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 00:43:40.556184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 00:43:40.556295 ==
8965 00:43:40.556390 DQS Delay:
8966 00:43:40.559377 DQS0 = 0, DQS1 = 0
8967 00:43:40.559475 DQM Delay:
8968 00:43:40.562896 DQM0 = 134, DQM1 = 131
8969 00:43:40.563001 DQ Delay:
8970 00:43:40.566434 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8971 00:43:40.569848 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8972 00:43:40.572594 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8973 00:43:40.576125 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
8974 00:43:40.576225
8975 00:43:40.576313
8976 00:43:40.576394
8977 00:43:40.579706 [DramC_TX_OE_Calibration] TA2
8978 00:43:40.582491 Original DQ_B0 (3 6) =30, OEN = 27
8979 00:43:40.585958 Original DQ_B1 (3 6) =30, OEN = 27
8980 00:43:40.589481 24, 0x0, End_B0=24 End_B1=24
8981 00:43:40.589585 25, 0x0, End_B0=25 End_B1=25
8982 00:43:40.592613 26, 0x0, End_B0=26 End_B1=26
8983 00:43:40.595915 27, 0x0, End_B0=27 End_B1=27
8984 00:43:40.599468 28, 0x0, End_B0=28 End_B1=28
8985 00:43:40.602923 29, 0x0, End_B0=29 End_B1=29
8986 00:43:40.603037 30, 0x0, End_B0=30 End_B1=30
8987 00:43:40.605773 31, 0x4141, End_B0=30 End_B1=30
8988 00:43:40.609221 Byte0 end_step=30 best_step=27
8989 00:43:40.612689 Byte1 end_step=30 best_step=27
8990 00:43:40.616181 Byte0 TX OE(2T, 0.5T) = (3, 3)
8991 00:43:40.619443 Byte1 TX OE(2T, 0.5T) = (3, 3)
8992 00:43:40.619528
8993 00:43:40.619614
8994 00:43:40.626117 [DQSOSCAuto] RK1, (LSB)MR18= 0x2508, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8995 00:43:40.628977 CH1 RK1: MR19=303, MR18=2508
8996 00:43:40.635803 CH1_RK1: MR19=0x303, MR18=0x2508, DQSOSC=391, MR23=63, INC=24, DEC=16
8997 00:43:40.639074 [RxdqsGatingPostProcess] freq 1600
8998 00:43:40.642406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8999 00:43:40.645943 best DQS0 dly(2T, 0.5T) = (1, 1)
9000 00:43:40.649168 best DQS1 dly(2T, 0.5T) = (1, 1)
9001 00:43:40.653007 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9002 00:43:40.655683 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9003 00:43:40.659379 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 00:43:40.662522 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 00:43:40.665819 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 00:43:40.669086 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 00:43:40.672678 Pre-setting of DQS Precalculation
9008 00:43:40.675490 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9009 00:43:40.682448 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9010 00:43:40.692820 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9011 00:43:40.692906
9012 00:43:40.692993
9013 00:43:40.693073 [Calibration Summary] 3200 Mbps
9014 00:43:40.695627 CH 0, Rank 0
9015 00:43:40.695712 SW Impedance : PASS
9016 00:43:40.699025 DUTY Scan : NO K
9017 00:43:40.702286 ZQ Calibration : PASS
9018 00:43:40.702372 Jitter Meter : NO K
9019 00:43:40.705624 CBT Training : PASS
9020 00:43:40.709171 Write leveling : PASS
9021 00:43:40.709257 RX DQS gating : PASS
9022 00:43:40.712114 RX DQ/DQS(RDDQC) : PASS
9023 00:43:40.716036 TX DQ/DQS : PASS
9024 00:43:40.716122 RX DATLAT : PASS
9025 00:43:40.718695 RX DQ/DQS(Engine): PASS
9026 00:43:40.722098 TX OE : PASS
9027 00:43:40.722183 All Pass.
9028 00:43:40.722269
9029 00:43:40.722350 CH 0, Rank 1
9030 00:43:40.725370 SW Impedance : PASS
9031 00:43:40.729170 DUTY Scan : NO K
9032 00:43:40.729255 ZQ Calibration : PASS
9033 00:43:40.732394 Jitter Meter : NO K
9034 00:43:40.735962 CBT Training : PASS
9035 00:43:40.736069 Write leveling : PASS
9036 00:43:40.739306 RX DQS gating : PASS
9037 00:43:40.739415 RX DQ/DQS(RDDQC) : PASS
9038 00:43:40.742037 TX DQ/DQS : PASS
9039 00:43:40.745948 RX DATLAT : PASS
9040 00:43:40.746033 RX DQ/DQS(Engine): PASS
9041 00:43:40.749114 TX OE : PASS
9042 00:43:40.749200 All Pass.
9043 00:43:40.749286
9044 00:43:40.752165 CH 1, Rank 0
9045 00:43:40.752250 SW Impedance : PASS
9046 00:43:40.755980 DUTY Scan : NO K
9047 00:43:40.758704 ZQ Calibration : PASS
9048 00:43:40.758789 Jitter Meter : NO K
9049 00:43:40.762110 CBT Training : PASS
9050 00:43:40.765407 Write leveling : PASS
9051 00:43:40.765492 RX DQS gating : PASS
9052 00:43:40.768685 RX DQ/DQS(RDDQC) : PASS
9053 00:43:40.772140 TX DQ/DQS : PASS
9054 00:43:40.772251 RX DATLAT : PASS
9055 00:43:40.775653 RX DQ/DQS(Engine): PASS
9056 00:43:40.778745 TX OE : PASS
9057 00:43:40.778823 All Pass.
9058 00:43:40.778891
9059 00:43:40.778959 CH 1, Rank 1
9060 00:43:40.782252 SW Impedance : PASS
9061 00:43:40.785166 DUTY Scan : NO K
9062 00:43:40.785240 ZQ Calibration : PASS
9063 00:43:40.788924 Jitter Meter : NO K
9064 00:43:40.792453 CBT Training : PASS
9065 00:43:40.792528 Write leveling : PASS
9066 00:43:40.795160 RX DQS gating : PASS
9067 00:43:40.795229 RX DQ/DQS(RDDQC) : PASS
9068 00:43:40.798654 TX DQ/DQS : PASS
9069 00:43:40.802093 RX DATLAT : PASS
9070 00:43:40.802169 RX DQ/DQS(Engine): PASS
9071 00:43:40.805254 TX OE : PASS
9072 00:43:40.805335 All Pass.
9073 00:43:40.805397
9074 00:43:40.808691 DramC Write-DBI on
9075 00:43:40.812081 PER_BANK_REFRESH: Hybrid Mode
9076 00:43:40.812197 TX_TRACKING: ON
9077 00:43:40.821554 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9078 00:43:40.828227 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9079 00:43:40.838401 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9080 00:43:40.841710 [FAST_K] Save calibration result to emmc
9081 00:43:40.841788 sync common calibartion params.
9082 00:43:40.845075 sync cbt_mode0:1, 1:1
9083 00:43:40.848640 dram_init: ddr_geometry: 2
9084 00:43:40.848749 dram_init: ddr_geometry: 2
9085 00:43:40.851892 dram_init: ddr_geometry: 2
9086 00:43:40.855220 0:dram_rank_size:100000000
9087 00:43:40.858623 1:dram_rank_size:100000000
9088 00:43:40.861930 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9089 00:43:40.865331 DFS_SHUFFLE_HW_MODE: ON
9090 00:43:40.868096 dramc_set_vcore_voltage set vcore to 725000
9091 00:43:40.871574 Read voltage for 1600, 0
9092 00:43:40.871685 Vio18 = 0
9093 00:43:40.874891 Vcore = 725000
9094 00:43:40.875004 Vdram = 0
9095 00:43:40.875099 Vddq = 0
9096 00:43:40.875188 Vmddr = 0
9097 00:43:40.878228 switch to 3200 Mbps bootup
9098 00:43:40.881676 [DramcRunTimeConfig]
9099 00:43:40.881786 PHYPLL
9100 00:43:40.885011 DPM_CONTROL_AFTERK: ON
9101 00:43:40.885113 PER_BANK_REFRESH: ON
9102 00:43:40.888256 REFRESH_OVERHEAD_REDUCTION: ON
9103 00:43:40.891558 CMD_PICG_NEW_MODE: OFF
9104 00:43:40.891662 XRTWTW_NEW_MODE: ON
9105 00:43:40.894775 XRTRTR_NEW_MODE: ON
9106 00:43:40.894871 TX_TRACKING: ON
9107 00:43:40.898119 RDSEL_TRACKING: OFF
9108 00:43:40.898229 DQS Precalculation for DVFS: ON
9109 00:43:40.901141 RX_TRACKING: OFF
9110 00:43:40.901255 HW_GATING DBG: ON
9111 00:43:40.904878 ZQCS_ENABLE_LP4: ON
9112 00:43:40.908149 RX_PICG_NEW_MODE: ON
9113 00:43:40.908279 TX_PICG_NEW_MODE: ON
9114 00:43:40.911533 ENABLE_RX_DCM_DPHY: ON
9115 00:43:40.914877 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9116 00:43:40.914985 DUMMY_READ_FOR_TRACKING: OFF
9117 00:43:40.918301 !!! SPM_CONTROL_AFTERK: OFF
9118 00:43:40.921115 !!! SPM could not control APHY
9119 00:43:40.924679 IMPEDANCE_TRACKING: ON
9120 00:43:40.924765 TEMP_SENSOR: ON
9121 00:43:40.928073 HW_SAVE_FOR_SR: OFF
9122 00:43:40.931122 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9123 00:43:40.934797 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9124 00:43:40.934975 Read ODT Tracking: ON
9125 00:43:40.937939 Refresh Rate DeBounce: ON
9126 00:43:40.941279 DFS_NO_QUEUE_FLUSH: ON
9127 00:43:40.944653 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9128 00:43:40.944752 ENABLE_DFS_RUNTIME_MRW: OFF
9129 00:43:40.948133 DDR_RESERVE_NEW_MODE: ON
9130 00:43:40.951516 MR_CBT_SWITCH_FREQ: ON
9131 00:43:40.951624 =========================
9132 00:43:40.971279 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9133 00:43:40.974750 dram_init: ddr_geometry: 2
9134 00:43:40.992260 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9135 00:43:40.996370 dram_init: dram init end (result: 0)
9136 00:43:41.002715 DRAM-K: Full calibration passed in 24452 msecs
9137 00:43:41.006017 MRC: failed to locate region type 0.
9138 00:43:41.006119 DRAM rank0 size:0x100000000,
9139 00:43:41.009264 DRAM rank1 size=0x100000000
9140 00:43:41.019306 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9141 00:43:41.025921 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9142 00:43:41.032160 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9143 00:43:41.038998 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9144 00:43:41.042467 DRAM rank0 size:0x100000000,
9145 00:43:41.046014 DRAM rank1 size=0x100000000
9146 00:43:41.046165 CBMEM:
9147 00:43:41.048769 IMD: root @ 0xfffff000 254 entries.
9148 00:43:41.052588 IMD: root @ 0xffffec00 62 entries.
9149 00:43:41.055705 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9150 00:43:41.059217 WARNING: RO_VPD is uninitialized or empty.
9151 00:43:41.065265 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9152 00:43:41.072516 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9153 00:43:41.085236 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9154 00:43:41.096720 BS: romstage times (exec / console): total (unknown) / 23986 ms
9155 00:43:41.096802
9156 00:43:41.096870
9157 00:43:41.106766 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9158 00:43:41.110247 ARM64: Exception handlers installed.
9159 00:43:41.113065 ARM64: Testing exception
9160 00:43:41.116605 ARM64: Done test exception
9161 00:43:41.116685 Enumerating buses...
9162 00:43:41.119932 Show all devs... Before device enumeration.
9163 00:43:41.123297 Root Device: enabled 1
9164 00:43:41.126898 CPU_CLUSTER: 0: enabled 1
9165 00:43:41.127015 CPU: 00: enabled 1
9166 00:43:41.129903 Compare with tree...
9167 00:43:41.129988 Root Device: enabled 1
9168 00:43:41.133354 CPU_CLUSTER: 0: enabled 1
9169 00:43:41.136236 CPU: 00: enabled 1
9170 00:43:41.136349 Root Device scanning...
9171 00:43:41.139705 scan_static_bus for Root Device
9172 00:43:41.143165 CPU_CLUSTER: 0 enabled
9173 00:43:41.146748 scan_static_bus for Root Device done
9174 00:43:41.149652 scan_bus: bus Root Device finished in 8 msecs
9175 00:43:41.149742 done
9176 00:43:41.156695 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9177 00:43:41.159437 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9178 00:43:41.166301 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9179 00:43:41.169571 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9180 00:43:41.172648 Allocating resources...
9181 00:43:41.175726 Reading resources...
9182 00:43:41.179371 Root Device read_resources bus 0 link: 0
9183 00:43:41.182313 DRAM rank0 size:0x100000000,
9184 00:43:41.182416 DRAM rank1 size=0x100000000
9185 00:43:41.185774 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9186 00:43:41.189202 CPU: 00 missing read_resources
9187 00:43:41.195462 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9188 00:43:41.198925 Root Device read_resources bus 0 link: 0 done
9189 00:43:41.202417 Done reading resources.
9190 00:43:41.205459 Show resources in subtree (Root Device)...After reading.
9191 00:43:41.209278 Root Device child on link 0 CPU_CLUSTER: 0
9192 00:43:41.212115 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 00:43:41.222319 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 00:43:41.222424 CPU: 00
9195 00:43:41.225768 Root Device assign_resources, bus 0 link: 0
9196 00:43:41.228993 CPU_CLUSTER: 0 missing set_resources
9197 00:43:41.235679 Root Device assign_resources, bus 0 link: 0 done
9198 00:43:41.235792 Done setting resources.
9199 00:43:41.242123 Show resources in subtree (Root Device)...After assigning values.
9200 00:43:41.245432 Root Device child on link 0 CPU_CLUSTER: 0
9201 00:43:41.248849 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 00:43:41.259245 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 00:43:41.259329 CPU: 00
9204 00:43:41.262113 Done allocating resources.
9205 00:43:41.268988 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9206 00:43:41.269070 Enabling resources...
9207 00:43:41.269140 done.
9208 00:43:41.275820 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9209 00:43:41.275929 Initializing devices...
9210 00:43:41.278965 Root Device init
9211 00:43:41.282308 init hardware done!
9212 00:43:41.282388 0x00000018: ctrlr->caps
9213 00:43:41.285736 52.000 MHz: ctrlr->f_max
9214 00:43:41.285812 0.400 MHz: ctrlr->f_min
9215 00:43:41.289036 0x40ff8080: ctrlr->voltages
9216 00:43:41.292374 sclk: 390625
9217 00:43:41.292451 Bus Width = 1
9218 00:43:41.292513 sclk: 390625
9219 00:43:41.295890 Bus Width = 1
9220 00:43:41.295993 Early init status = 3
9221 00:43:41.302055 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9222 00:43:41.305397 in-header: 03 fc 00 00 01 00 00 00
9223 00:43:41.308752 in-data: 00
9224 00:43:41.311796 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9225 00:43:41.317208 in-header: 03 fd 00 00 00 00 00 00
9226 00:43:41.321032 in-data:
9227 00:43:41.323995 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9228 00:43:41.328691 in-header: 03 fc 00 00 01 00 00 00
9229 00:43:41.331993 in-data: 00
9230 00:43:41.335332 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9231 00:43:41.340950 in-header: 03 fd 00 00 00 00 00 00
9232 00:43:41.344410 in-data:
9233 00:43:41.347645 [SSUSB] Setting up USB HOST controller...
9234 00:43:41.350964 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9235 00:43:41.354191 [SSUSB] phy power-on done.
9236 00:43:41.357444 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9237 00:43:41.363605 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9238 00:43:41.367124 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9239 00:43:41.374034 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9240 00:43:41.380245 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9241 00:43:41.386772 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9242 00:43:41.393545 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9243 00:43:41.400308 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9244 00:43:41.403730 SPM: binary array size = 0x9dc
9245 00:43:41.406989 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9246 00:43:41.413621 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9247 00:43:41.420691 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9248 00:43:41.426950 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9249 00:43:41.430145 configure_display: Starting display init
9250 00:43:41.463980 anx7625_power_on_init: Init interface.
9251 00:43:41.467621 anx7625_disable_pd_protocol: Disabled PD feature.
9252 00:43:41.470731 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9253 00:43:41.498463 anx7625_start_dp_work: Secure OCM version=00
9254 00:43:41.501858 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9255 00:43:41.516514 sp_tx_get_edid_block: EDID Block = 1
9256 00:43:41.619117 Extracted contents:
9257 00:43:41.622405 header: 00 ff ff ff ff ff ff 00
9258 00:43:41.625958 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9259 00:43:41.628731 version: 01 04
9260 00:43:41.632102 basic params: 95 1f 11 78 0a
9261 00:43:41.635727 chroma info: 76 90 94 55 54 90 27 21 50 54
9262 00:43:41.638992 established: 00 00 00
9263 00:43:41.645705 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9264 00:43:41.648872 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9265 00:43:41.655616 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9266 00:43:41.661796 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9267 00:43:41.668640 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9268 00:43:41.672200 extensions: 00
9269 00:43:41.672305 checksum: fb
9270 00:43:41.672417
9271 00:43:41.675539 Manufacturer: IVO Model 57d Serial Number 0
9272 00:43:41.678268 Made week 0 of 2020
9273 00:43:41.678344 EDID version: 1.4
9274 00:43:41.681704 Digital display
9275 00:43:41.684991 6 bits per primary color channel
9276 00:43:41.685096 DisplayPort interface
9277 00:43:41.688763 Maximum image size: 31 cm x 17 cm
9278 00:43:41.691768 Gamma: 220%
9279 00:43:41.691848 Check DPMS levels
9280 00:43:41.694890 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9281 00:43:41.701791 First detailed timing is preferred timing
9282 00:43:41.701903 Established timings supported:
9283 00:43:41.705086 Standard timings supported:
9284 00:43:41.708357 Detailed timings
9285 00:43:41.711792 Hex of detail: 383680a07038204018303c0035ae10000019
9286 00:43:41.715126 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9287 00:43:41.721884 0780 0798 07c8 0820 hborder 0
9288 00:43:41.725157 0438 043b 0447 0458 vborder 0
9289 00:43:41.728116 -hsync -vsync
9290 00:43:41.728194 Did detailed timing
9291 00:43:41.734674 Hex of detail: 000000000000000000000000000000000000
9292 00:43:41.738022 Manufacturer-specified data, tag 0
9293 00:43:41.741260 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9294 00:43:41.744741 ASCII string: InfoVision
9295 00:43:41.748248 Hex of detail: 000000fe00523134304e574635205248200a
9296 00:43:41.751572 ASCII string: R140NWF5 RH
9297 00:43:41.751648 Checksum
9298 00:43:41.754739 Checksum: 0xfb (valid)
9299 00:43:41.757732 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9300 00:43:41.761245 DSI data_rate: 832800000 bps
9301 00:43:41.767987 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9302 00:43:41.771410 anx7625_parse_edid: pixelclock(138800).
9303 00:43:41.774854 hactive(1920), hsync(48), hfp(24), hbp(88)
9304 00:43:41.778257 vactive(1080), vsync(12), vfp(3), vbp(17)
9305 00:43:41.781161 anx7625_dsi_config: config dsi.
9306 00:43:41.788147 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9307 00:43:41.801143 anx7625_dsi_config: success to config DSI
9308 00:43:41.804688 anx7625_dp_start: MIPI phy setup OK.
9309 00:43:41.807901 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9310 00:43:41.811052 mtk_ddp_mode_set invalid vrefresh 60
9311 00:43:41.814311 main_disp_path_setup
9312 00:43:41.814383 ovl_layer_smi_id_en
9313 00:43:41.817590 ovl_layer_smi_id_en
9314 00:43:41.817677 ccorr_config
9315 00:43:41.817737 aal_config
9316 00:43:41.821336 gamma_config
9317 00:43:41.821406 postmask_config
9318 00:43:41.821466 dither_config
9319 00:43:41.828130 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9320 00:43:41.834884 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9321 00:43:41.838126 Root Device init finished in 555 msecs
9322 00:43:41.838199 CPU_CLUSTER: 0 init
9323 00:43:41.847963 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9324 00:43:41.850909 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9325 00:43:41.854662 APU_MBOX 0x190000b0 = 0x10001
9326 00:43:41.858031 APU_MBOX 0x190001b0 = 0x10001
9327 00:43:41.861414 APU_MBOX 0x190005b0 = 0x10001
9328 00:43:41.864392 APU_MBOX 0x190006b0 = 0x10001
9329 00:43:41.867394 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9330 00:43:41.880236 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9331 00:43:41.892694 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9332 00:43:41.899095 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9333 00:43:41.910723 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9334 00:43:41.919961 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9335 00:43:41.923286 CPU_CLUSTER: 0 init finished in 81 msecs
9336 00:43:41.926777 Devices initialized
9337 00:43:41.930313 Show all devs... After init.
9338 00:43:41.930415 Root Device: enabled 1
9339 00:43:41.933002 CPU_CLUSTER: 0: enabled 1
9340 00:43:41.936425 CPU: 00: enabled 1
9341 00:43:41.939863 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9342 00:43:41.943152 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9343 00:43:41.946217 ELOG: NV offset 0x57f000 size 0x1000
9344 00:43:41.952720 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9345 00:43:41.959403 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9346 00:43:41.963236 ELOG: Event(17) added with size 13 at 2024-06-05 00:39:00 UTC
9347 00:43:41.969361 out: cmd=0x121: 03 db 21 01 00 00 00 00
9348 00:43:41.972661 in-header: 03 d9 00 00 2c 00 00 00
9349 00:43:41.982988 in-data: 86 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 00:43:41.989118 ELOG: Event(A1) added with size 10 at 2024-06-05 00:39:00 UTC
9351 00:43:41.995952 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9352 00:43:42.002915 ELOG: Event(A0) added with size 9 at 2024-06-05 00:39:00 UTC
9353 00:43:42.006257 elog_add_boot_reason: Logged dev mode boot
9354 00:43:42.009701 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9355 00:43:42.012864 Finalize devices...
9356 00:43:42.016246 Devices finalized
9357 00:43:42.019074 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9358 00:43:42.022954 Writing coreboot table at 0xffe64000
9359 00:43:42.025726 0. 000000000010a000-0000000000113fff: RAMSTAGE
9360 00:43:42.029117 1. 0000000040000000-00000000400fffff: RAM
9361 00:43:42.035887 2. 0000000040100000-000000004032afff: RAMSTAGE
9362 00:43:42.039221 3. 000000004032b000-00000000545fffff: RAM
9363 00:43:42.042815 4. 0000000054600000-000000005465ffff: BL31
9364 00:43:42.046035 5. 0000000054660000-00000000ffe63fff: RAM
9365 00:43:42.052299 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9366 00:43:42.055797 7. 0000000100000000-000000023fffffff: RAM
9367 00:43:42.058736 Passing 5 GPIOs to payload:
9368 00:43:42.062048 NAME | PORT | POLARITY | VALUE
9369 00:43:42.068483 EC in RW | 0x000000aa | low | undefined
9370 00:43:42.071811 EC interrupt | 0x00000005 | low | undefined
9371 00:43:42.075148 TPM interrupt | 0x000000ab | high | undefined
9372 00:43:42.081797 SD card detect | 0x00000011 | high | undefined
9373 00:43:42.085191 speaker enable | 0x00000093 | high | undefined
9374 00:43:42.088475 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9375 00:43:42.091666 in-header: 03 f9 00 00 02 00 00 00
9376 00:43:42.095150 in-data: 02 00
9377 00:43:42.098666 ADC[4]: Raw value=904357 ID=7
9378 00:43:42.098766 ADC[3]: Raw value=213441 ID=1
9379 00:43:42.102036 RAM Code: 0x71
9380 00:43:42.104946 ADC[6]: Raw value=75701 ID=0
9381 00:43:42.105019 ADC[5]: Raw value=213072 ID=1
9382 00:43:42.108662 SKU Code: 0x1
9383 00:43:42.112102 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3b2d
9384 00:43:42.115346 coreboot table: 964 bytes.
9385 00:43:42.118857 IMD ROOT 0. 0xfffff000 0x00001000
9386 00:43:42.121595 IMD SMALL 1. 0xffffe000 0x00001000
9387 00:43:42.124957 RO MCACHE 2. 0xffffc000 0x00001104
9388 00:43:42.128189 CONSOLE 3. 0xfff7c000 0x00080000
9389 00:43:42.131643 FMAP 4. 0xfff7b000 0x00000452
9390 00:43:42.134979 TIME STAMP 5. 0xfff7a000 0x00000910
9391 00:43:42.138235 VBOOT WORK 6. 0xfff66000 0x00014000
9392 00:43:42.141725 RAMOOPS 7. 0xffe66000 0x00100000
9393 00:43:42.144624 COREBOOT 8. 0xffe64000 0x00002000
9394 00:43:42.148101 IMD small region:
9395 00:43:42.151455 IMD ROOT 0. 0xffffec00 0x00000400
9396 00:43:42.154894 VPD 1. 0xffffeb80 0x0000006c
9397 00:43:42.158334 MMC STATUS 2. 0xffffeb60 0x00000004
9398 00:43:42.161144 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9399 00:43:42.164621 Probing TPM: done!
9400 00:43:42.168529 Connected to device vid:did:rid of 1ae0:0028:00
9401 00:43:42.178936 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9402 00:43:42.182645 Initialized TPM device CR50 revision 0
9403 00:43:42.185918 Checking cr50 for pending updates
9404 00:43:42.189484 Reading cr50 TPM mode
9405 00:43:42.198058 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9406 00:43:42.204910 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9407 00:43:42.245295 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9408 00:43:42.248600 Checking segment from ROM address 0x40100000
9409 00:43:42.251424 Checking segment from ROM address 0x4010001c
9410 00:43:42.258338 Loading segment from ROM address 0x40100000
9411 00:43:42.258448 code (compression=0)
9412 00:43:42.268577 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9413 00:43:42.275422 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9414 00:43:42.275522 it's not compressed!
9415 00:43:42.281667 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9416 00:43:42.285186 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9417 00:43:42.305571 Loading segment from ROM address 0x4010001c
9418 00:43:42.305677 Entry Point 0x80000000
9419 00:43:42.309014 Loaded segments
9420 00:43:42.311809 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9421 00:43:42.318996 Jumping to boot code at 0x80000000(0xffe64000)
9422 00:43:42.325448 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9423 00:43:42.332152 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9424 00:43:42.339975 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9425 00:43:42.343116 Checking segment from ROM address 0x40100000
9426 00:43:42.346794 Checking segment from ROM address 0x4010001c
9427 00:43:42.353232 Loading segment from ROM address 0x40100000
9428 00:43:42.353305 code (compression=1)
9429 00:43:42.359979 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9430 00:43:42.370312 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9431 00:43:42.370395 using LZMA
9432 00:43:42.378401 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9433 00:43:42.385333 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9434 00:43:42.388077 Loading segment from ROM address 0x4010001c
9435 00:43:42.388157 Entry Point 0x54601000
9436 00:43:42.391609 Loaded segments
9437 00:43:42.394918 NOTICE: MT8192 bl31_setup
9438 00:43:42.401727 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9439 00:43:42.404922 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9440 00:43:42.408736 WARNING: region 0:
9441 00:43:42.412092 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 00:43:42.412173 WARNING: region 1:
9443 00:43:42.418900 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9444 00:43:42.421637 WARNING: region 2:
9445 00:43:42.425485 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9446 00:43:42.428215 WARNING: region 3:
9447 00:43:42.431650 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 00:43:42.435053 WARNING: region 4:
9449 00:43:42.441841 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 00:43:42.441948 WARNING: region 5:
9451 00:43:42.445178 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 00:43:42.448363 WARNING: region 6:
9453 00:43:42.451878 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 00:43:42.455353 WARNING: region 7:
9455 00:43:42.458733 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 00:43:42.465336 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9457 00:43:42.468266 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9458 00:43:42.471794 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9459 00:43:42.478493 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9460 00:43:42.481707 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9461 00:43:42.485342 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9462 00:43:42.492205 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9463 00:43:42.494953 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9464 00:43:42.498375 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9465 00:43:42.505306 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9466 00:43:42.508814 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9467 00:43:42.515466 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9468 00:43:42.518655 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9469 00:43:42.521721 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9470 00:43:42.528325 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9471 00:43:42.532382 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9472 00:43:42.535596 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9473 00:43:42.542067 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9474 00:43:42.545742 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9475 00:43:42.548960 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9476 00:43:42.555597 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9477 00:43:42.559056 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9478 00:43:42.565281 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9479 00:43:42.568704 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9480 00:43:42.572110 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9481 00:43:42.578971 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9482 00:43:42.582009 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9483 00:43:42.589132 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9484 00:43:42.592182 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9485 00:43:42.595962 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9486 00:43:42.602025 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9487 00:43:42.605848 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9488 00:43:42.609332 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9489 00:43:42.615485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9490 00:43:42.618898 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9491 00:43:42.622260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9492 00:43:42.625483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9493 00:43:42.632648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9494 00:43:42.635862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9495 00:43:42.639141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9496 00:43:42.642816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9497 00:43:42.645806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9498 00:43:42.652736 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9499 00:43:42.656065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9500 00:43:42.659142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9501 00:43:42.665835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9502 00:43:42.669406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9503 00:43:42.672748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9504 00:43:42.676244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9505 00:43:42.682349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9506 00:43:42.685787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9507 00:43:42.692597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9508 00:43:42.695685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9509 00:43:42.702679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9510 00:43:42.705864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9511 00:43:42.709215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9512 00:43:42.716120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9513 00:43:42.719316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9514 00:43:42.726399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9515 00:43:42.729714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9516 00:43:42.736234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9517 00:43:42.738990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9518 00:43:42.742386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9519 00:43:42.749372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9520 00:43:42.752614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9521 00:43:42.759570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9522 00:43:42.762487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9523 00:43:42.769814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9524 00:43:42.772915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9525 00:43:42.776293 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9526 00:43:42.783095 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9527 00:43:42.785899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9528 00:43:42.792975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9529 00:43:42.796366 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9530 00:43:42.802901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9531 00:43:42.806339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9532 00:43:42.809649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9533 00:43:42.816356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9534 00:43:42.819738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9535 00:43:42.826276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9536 00:43:42.829307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9537 00:43:42.836031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9538 00:43:42.839899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9539 00:43:42.843287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9540 00:43:42.850098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9541 00:43:42.852946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9542 00:43:42.860015 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9543 00:43:42.863353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9544 00:43:42.866738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9545 00:43:42.873326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9546 00:43:42.876411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9547 00:43:42.883743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9548 00:43:42.886691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9549 00:43:42.893629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9550 00:43:42.896600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9551 00:43:42.903680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9552 00:43:42.907119 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9553 00:43:42.910281 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9554 00:43:42.913445 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9555 00:43:42.916785 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9556 00:43:42.923403 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9557 00:43:42.926766 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9558 00:43:42.933768 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9559 00:43:42.937080 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9560 00:43:42.940354 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9561 00:43:42.947019 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9562 00:43:42.950121 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9563 00:43:42.953954 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9564 00:43:42.960229 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9565 00:43:42.963987 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9566 00:43:42.970422 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9567 00:43:42.973830 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9568 00:43:42.976648 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9569 00:43:42.983554 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9570 00:43:42.987269 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9571 00:43:42.993468 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9572 00:43:42.997287 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9573 00:43:43.000323 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9574 00:43:43.003644 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9575 00:43:43.010417 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9576 00:43:43.013848 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9577 00:43:43.017303 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9578 00:43:43.020511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9579 00:43:43.026760 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9580 00:43:43.030765 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9581 00:43:43.034116 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9582 00:43:43.040179 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9583 00:43:43.043548 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9584 00:43:43.050260 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9585 00:43:43.054067 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9586 00:43:43.057454 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9587 00:43:43.063711 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9588 00:43:43.067330 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9589 00:43:43.073975 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9590 00:43:43.077349 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9591 00:43:43.080288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9592 00:43:43.087067 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9593 00:43:43.090468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9594 00:43:43.094027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9595 00:43:43.100622 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9596 00:43:43.103932 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9597 00:43:43.110351 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9598 00:43:43.113296 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9599 00:43:43.119988 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9600 00:43:43.123800 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9601 00:43:43.126996 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9602 00:43:43.133925 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9603 00:43:43.137215 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9604 00:43:43.140394 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9605 00:43:43.147153 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9606 00:43:43.149905 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9607 00:43:43.153355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9608 00:43:43.160184 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9609 00:43:43.163433 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9610 00:43:43.170443 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9611 00:43:43.173594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9612 00:43:43.176759 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9613 00:43:43.183631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9614 00:43:43.187141 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9615 00:43:43.193393 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9616 00:43:43.196771 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9617 00:43:43.199977 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9618 00:43:43.206814 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9619 00:43:43.210282 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9620 00:43:43.216642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9621 00:43:43.219867 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9622 00:43:43.223603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9623 00:43:43.230091 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9624 00:43:43.233462 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9625 00:43:43.240336 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9626 00:43:43.243676 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9627 00:43:43.246987 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9628 00:43:43.253017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9629 00:43:43.256603 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9630 00:43:43.259822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9631 00:43:43.285268 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9632 00:43:43.285448 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9633 00:43:43.285579 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9634 00:43:43.285676 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9635 00:43:43.285749 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9636 00:43:43.290106 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9637 00:43:43.293267 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9638 00:43:43.299855 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9639 00:43:43.303222 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9640 00:43:43.306580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9641 00:43:43.313297 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9642 00:43:43.316690 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9643 00:43:43.320050 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9644 00:43:43.326342 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9645 00:43:43.329671 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9646 00:43:43.336773 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9647 00:43:43.339839 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9648 00:43:43.346574 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9649 00:43:43.349926 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9650 00:43:43.353233 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9651 00:43:43.360004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9652 00:43:43.362818 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9653 00:43:43.369653 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9654 00:43:43.372980 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9655 00:43:43.379964 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9656 00:43:43.382560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9657 00:43:43.385931 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9658 00:43:43.392673 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9659 00:43:43.396467 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9660 00:43:43.402974 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9661 00:43:43.406172 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9662 00:43:43.409625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9663 00:43:43.416580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9664 00:43:43.419329 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9665 00:43:43.426307 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9666 00:43:43.429606 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9667 00:43:43.432901 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9668 00:43:43.439582 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9669 00:43:43.442864 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9670 00:43:43.449587 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9671 00:43:43.453045 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9672 00:43:43.456479 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9673 00:43:43.463053 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9674 00:43:43.466440 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9675 00:43:43.472832 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9676 00:43:43.476201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9677 00:43:43.483026 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9678 00:43:43.486325 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9679 00:43:43.489666 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9680 00:43:43.495829 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9681 00:43:43.499291 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9682 00:43:43.505996 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9683 00:43:43.509194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9684 00:43:43.512569 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9685 00:43:43.519640 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9686 00:43:43.522849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9687 00:43:43.526108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9688 00:43:43.529619 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9689 00:43:43.535597 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9690 00:43:43.538945 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9691 00:43:43.542421 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9692 00:43:43.549062 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9693 00:43:43.552217 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9694 00:43:43.555423 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9695 00:43:43.562194 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9696 00:43:43.565519 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9697 00:43:43.572202 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9698 00:43:43.575633 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9699 00:43:43.579034 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9700 00:43:43.585819 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9701 00:43:43.589195 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9702 00:43:43.592525 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9703 00:43:43.599242 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9704 00:43:43.601988 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9705 00:43:43.605819 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9706 00:43:43.611796 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9707 00:43:43.615209 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9708 00:43:43.621994 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9709 00:43:43.625787 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9710 00:43:43.628989 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9711 00:43:43.635219 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9712 00:43:43.638717 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9713 00:43:43.641932 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9714 00:43:43.648831 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9715 00:43:43.652325 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9716 00:43:43.655593 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9717 00:43:43.662293 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9718 00:43:43.665609 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9719 00:43:43.668910 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9720 00:43:43.675440 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9721 00:43:43.678900 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9722 00:43:43.685466 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9723 00:43:43.688888 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9724 00:43:43.692405 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9725 00:43:43.699141 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9726 00:43:43.701801 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9727 00:43:43.705195 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9728 00:43:43.708529 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9729 00:43:43.712290 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9730 00:43:43.718965 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9731 00:43:43.721737 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9732 00:43:43.725184 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9733 00:43:43.728695 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9734 00:43:43.735463 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9735 00:43:43.738811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9736 00:43:43.741997 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9737 00:43:43.745130 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9738 00:43:43.752043 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9739 00:43:43.755631 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9740 00:43:43.761587 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9741 00:43:43.764853 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9742 00:43:43.771657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9743 00:43:43.775023 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9744 00:43:43.781911 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9745 00:43:43.784962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9746 00:43:43.788174 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9747 00:43:43.794865 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9748 00:43:43.798348 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9749 00:43:43.801836 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9750 00:43:43.808396 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9751 00:43:43.811784 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9752 00:43:43.818500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9753 00:43:43.821628 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9754 00:43:43.824862 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9755 00:43:43.831536 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9756 00:43:43.834989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9757 00:43:43.841869 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9758 00:43:43.844570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9759 00:43:43.851210 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9760 00:43:43.855095 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9761 00:43:43.858122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9762 00:43:43.864885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9763 00:43:43.868287 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9764 00:43:43.874448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9765 00:43:43.877756 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9766 00:43:43.881754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9767 00:43:43.887965 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9768 00:43:43.891149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9769 00:43:43.897725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9770 00:43:43.901019 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9771 00:43:43.904291 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9772 00:43:43.911429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9773 00:43:43.914779 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9774 00:43:43.920891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9775 00:43:43.924326 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9776 00:43:43.931253 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9777 00:43:43.934670 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9778 00:43:43.938023 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9779 00:43:43.944483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9780 00:43:43.947769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9781 00:43:43.954367 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9782 00:43:43.957888 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9783 00:43:43.961225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9784 00:43:43.967384 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9785 00:43:43.970801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9786 00:43:43.977522 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9787 00:43:43.980643 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9788 00:43:43.984352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9789 00:43:43.990920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9790 00:43:43.994165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9791 00:43:44.000973 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9792 00:43:44.004115 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9793 00:43:44.007352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9794 00:43:44.014069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9795 00:43:44.017474 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9796 00:43:44.024248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9797 00:43:44.026973 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9798 00:43:44.033589 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9799 00:43:44.037453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9800 00:43:44.040619 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9801 00:43:44.047295 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9802 00:43:44.050650 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9803 00:43:44.054123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9804 00:43:44.060300 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9805 00:43:44.063855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9806 00:43:44.070548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9807 00:43:44.073898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9808 00:43:44.080633 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9809 00:43:44.083941 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9810 00:43:44.087707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9811 00:43:44.093575 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9812 00:43:44.096729 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9813 00:43:44.103749 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9814 00:43:44.106828 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9815 00:43:44.113638 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9816 00:43:44.116904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9817 00:43:44.120297 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9818 00:43:44.126997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9819 00:43:44.130343 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9820 00:43:44.136639 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9821 00:43:44.140044 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9822 00:43:44.146599 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9823 00:43:44.150371 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9824 00:43:44.157141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9825 00:43:44.160628 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9826 00:43:44.163286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9827 00:43:44.170031 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9828 00:43:44.173494 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9829 00:43:44.179914 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9830 00:43:44.183303 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9831 00:43:44.190077 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9832 00:43:44.193723 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9833 00:43:44.197134 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9834 00:43:44.203684 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9835 00:43:44.206476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9836 00:43:44.213262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9837 00:43:44.216733 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9838 00:43:44.223357 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9839 00:43:44.226490 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9840 00:43:44.229803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9841 00:43:44.236653 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9842 00:43:44.239944 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9843 00:43:44.246587 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9844 00:43:44.249982 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9845 00:43:44.256569 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9846 00:43:44.260061 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9847 00:43:44.266149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9848 00:43:44.269603 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9849 00:43:44.272958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9850 00:43:44.279639 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9851 00:43:44.282984 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9852 00:43:44.289674 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9853 00:43:44.293088 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9854 00:43:44.296632 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9855 00:43:44.303325 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9856 00:43:44.306156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9857 00:43:44.312919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9858 00:43:44.316321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9859 00:43:44.319611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9860 00:43:44.326590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9861 00:43:44.329860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9862 00:43:44.336144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9863 00:43:44.339208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9864 00:43:44.345963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9865 00:43:44.349705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9866 00:43:44.356349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9867 00:43:44.359693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9868 00:43:44.366432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9869 00:43:44.369682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9870 00:43:44.376266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9871 00:43:44.379060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9872 00:43:44.386010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9873 00:43:44.389018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9874 00:43:44.395597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9875 00:43:44.398966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9876 00:43:44.405654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9877 00:43:44.409074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9878 00:43:44.416006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9879 00:43:44.419396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9880 00:43:44.426087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9881 00:43:44.429386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9882 00:43:44.435645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9883 00:43:44.439143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9884 00:43:44.445915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9885 00:43:44.449070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9886 00:43:44.456061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9887 00:43:44.459095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9888 00:43:44.465685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9889 00:43:44.469212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9890 00:43:44.472070 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9891 00:43:44.475718 INFO: [APUAPC] vio 0
9892 00:43:44.482453 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9893 00:43:44.485716 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9894 00:43:44.489240 INFO: [APUAPC] D0_APC_0: 0x400510
9895 00:43:44.492466 INFO: [APUAPC] D0_APC_1: 0x0
9896 00:43:44.495838 INFO: [APUAPC] D0_APC_2: 0x1540
9897 00:43:44.499406 INFO: [APUAPC] D0_APC_3: 0x0
9898 00:43:44.502678 INFO: [APUAPC] D1_APC_0: 0xffffffff
9899 00:43:44.505515 INFO: [APUAPC] D1_APC_1: 0xffffffff
9900 00:43:44.508738 INFO: [APUAPC] D1_APC_2: 0x3fffff
9901 00:43:44.508815 INFO: [APUAPC] D1_APC_3: 0x0
9902 00:43:44.512311 INFO: [APUAPC] D2_APC_0: 0xffffffff
9903 00:43:44.518621 INFO: [APUAPC] D2_APC_1: 0xffffffff
9904 00:43:44.522070 INFO: [APUAPC] D2_APC_2: 0x3fffff
9905 00:43:44.522179 INFO: [APUAPC] D2_APC_3: 0x0
9906 00:43:44.525322 INFO: [APUAPC] D3_APC_0: 0xffffffff
9907 00:43:44.528786 INFO: [APUAPC] D3_APC_1: 0xffffffff
9908 00:43:44.532275 INFO: [APUAPC] D3_APC_2: 0x3fffff
9909 00:43:44.535702 INFO: [APUAPC] D3_APC_3: 0x0
9910 00:43:44.539090 INFO: [APUAPC] D4_APC_0: 0xffffffff
9911 00:43:44.541945 INFO: [APUAPC] D4_APC_1: 0xffffffff
9912 00:43:44.545218 INFO: [APUAPC] D4_APC_2: 0x3fffff
9913 00:43:44.548594 INFO: [APUAPC] D4_APC_3: 0x0
9914 00:43:44.551929 INFO: [APUAPC] D5_APC_0: 0xffffffff
9915 00:43:44.555310 INFO: [APUAPC] D5_APC_1: 0xffffffff
9916 00:43:44.558723 INFO: [APUAPC] D5_APC_2: 0x3fffff
9917 00:43:44.562128 INFO: [APUAPC] D5_APC_3: 0x0
9918 00:43:44.565322 INFO: [APUAPC] D6_APC_0: 0xffffffff
9919 00:43:44.568794 INFO: [APUAPC] D6_APC_1: 0xffffffff
9920 00:43:44.572198 INFO: [APUAPC] D6_APC_2: 0x3fffff
9921 00:43:44.575460 INFO: [APUAPC] D6_APC_3: 0x0
9922 00:43:44.578746 INFO: [APUAPC] D7_APC_0: 0xffffffff
9923 00:43:44.581822 INFO: [APUAPC] D7_APC_1: 0xffffffff
9924 00:43:44.585298 INFO: [APUAPC] D7_APC_2: 0x3fffff
9925 00:43:44.588837 INFO: [APUAPC] D7_APC_3: 0x0
9926 00:43:44.591750 INFO: [APUAPC] D8_APC_0: 0xffffffff
9927 00:43:44.595174 INFO: [APUAPC] D8_APC_1: 0xffffffff
9928 00:43:44.598567 INFO: [APUAPC] D8_APC_2: 0x3fffff
9929 00:43:44.602175 INFO: [APUAPC] D8_APC_3: 0x0
9930 00:43:44.605089 INFO: [APUAPC] D9_APC_0: 0xffffffff
9931 00:43:44.608469 INFO: [APUAPC] D9_APC_1: 0xffffffff
9932 00:43:44.611905 INFO: [APUAPC] D9_APC_2: 0x3fffff
9933 00:43:44.615258 INFO: [APUAPC] D9_APC_3: 0x0
9934 00:43:44.618677 INFO: [APUAPC] D10_APC_0: 0xffffffff
9935 00:43:44.622008 INFO: [APUAPC] D10_APC_1: 0xffffffff
9936 00:43:44.624876 INFO: [APUAPC] D10_APC_2: 0x3fffff
9937 00:43:44.628231 INFO: [APUAPC] D10_APC_3: 0x0
9938 00:43:44.632277 INFO: [APUAPC] D11_APC_0: 0xffffffff
9939 00:43:44.635091 INFO: [APUAPC] D11_APC_1: 0xffffffff
9940 00:43:44.638455 INFO: [APUAPC] D11_APC_2: 0x3fffff
9941 00:43:44.641929 INFO: [APUAPC] D11_APC_3: 0x0
9942 00:43:44.644699 INFO: [APUAPC] D12_APC_0: 0xffffffff
9943 00:43:44.647994 INFO: [APUAPC] D12_APC_1: 0xffffffff
9944 00:43:44.651577 INFO: [APUAPC] D12_APC_2: 0x3fffff
9945 00:43:44.654996 INFO: [APUAPC] D12_APC_3: 0x0
9946 00:43:44.658393 INFO: [APUAPC] D13_APC_0: 0xffffffff
9947 00:43:44.661766 INFO: [APUAPC] D13_APC_1: 0xffffffff
9948 00:43:44.665123 INFO: [APUAPC] D13_APC_2: 0x3fffff
9949 00:43:44.668150 INFO: [APUAPC] D13_APC_3: 0x0
9950 00:43:44.671499 INFO: [APUAPC] D14_APC_0: 0xffffffff
9951 00:43:44.674838 INFO: [APUAPC] D14_APC_1: 0xffffffff
9952 00:43:44.678309 INFO: [APUAPC] D14_APC_2: 0x3fffff
9953 00:43:44.681803 INFO: [APUAPC] D14_APC_3: 0x0
9954 00:43:44.685096 INFO: [APUAPC] D15_APC_0: 0xffffffff
9955 00:43:44.688680 INFO: [APUAPC] D15_APC_1: 0xffffffff
9956 00:43:44.691395 INFO: [APUAPC] D15_APC_2: 0x3fffff
9957 00:43:44.694665 INFO: [APUAPC] D15_APC_3: 0x0
9958 00:43:44.698454 INFO: [APUAPC] APC_CON: 0x4
9959 00:43:44.701441 INFO: [NOCDAPC] D0_APC_0: 0x0
9960 00:43:44.704984 INFO: [NOCDAPC] D0_APC_1: 0x0
9961 00:43:44.705056 INFO: [NOCDAPC] D1_APC_0: 0x0
9962 00:43:44.708449 INFO: [NOCDAPC] D1_APC_1: 0xfff
9963 00:43:44.711480 INFO: [NOCDAPC] D2_APC_0: 0x0
9964 00:43:44.715091 INFO: [NOCDAPC] D2_APC_1: 0xfff
9965 00:43:44.718246 INFO: [NOCDAPC] D3_APC_0: 0x0
9966 00:43:44.721495 INFO: [NOCDAPC] D3_APC_1: 0xfff
9967 00:43:44.724522 INFO: [NOCDAPC] D4_APC_0: 0x0
9968 00:43:44.728172 INFO: [NOCDAPC] D4_APC_1: 0xfff
9969 00:43:44.731273 INFO: [NOCDAPC] D5_APC_0: 0x0
9970 00:43:44.734686 INFO: [NOCDAPC] D5_APC_1: 0xfff
9971 00:43:44.738009 INFO: [NOCDAPC] D6_APC_0: 0x0
9972 00:43:44.738081 INFO: [NOCDAPC] D6_APC_1: 0xfff
9973 00:43:44.740881 INFO: [NOCDAPC] D7_APC_0: 0x0
9974 00:43:44.744296 INFO: [NOCDAPC] D7_APC_1: 0xfff
9975 00:43:44.747676 INFO: [NOCDAPC] D8_APC_0: 0x0
9976 00:43:44.751046 INFO: [NOCDAPC] D8_APC_1: 0xfff
9977 00:43:44.754448 INFO: [NOCDAPC] D9_APC_0: 0x0
9978 00:43:44.757913 INFO: [NOCDAPC] D9_APC_1: 0xfff
9979 00:43:44.761263 INFO: [NOCDAPC] D10_APC_0: 0x0
9980 00:43:44.764609 INFO: [NOCDAPC] D10_APC_1: 0xfff
9981 00:43:44.767489 INFO: [NOCDAPC] D11_APC_0: 0x0
9982 00:43:44.770845 INFO: [NOCDAPC] D11_APC_1: 0xfff
9983 00:43:44.774106 INFO: [NOCDAPC] D12_APC_0: 0x0
9984 00:43:44.777345 INFO: [NOCDAPC] D12_APC_1: 0xfff
9985 00:43:44.777441 INFO: [NOCDAPC] D13_APC_0: 0x0
9986 00:43:44.781360 INFO: [NOCDAPC] D13_APC_1: 0xfff
9987 00:43:44.784613 INFO: [NOCDAPC] D14_APC_0: 0x0
9988 00:43:44.787378 INFO: [NOCDAPC] D14_APC_1: 0xfff
9989 00:43:44.790735 INFO: [NOCDAPC] D15_APC_0: 0x0
9990 00:43:44.794189 INFO: [NOCDAPC] D15_APC_1: 0xfff
9991 00:43:44.797708 INFO: [NOCDAPC] APC_CON: 0x4
9992 00:43:44.801358 INFO: [APUAPC] set_apusys_apc done
9993 00:43:44.804393 INFO: [DEVAPC] devapc_init done
9994 00:43:44.807814 INFO: GICv3 without legacy support detected.
9995 00:43:44.810983 INFO: ARM GICv3 driver initialized in EL3
9996 00:43:44.817271 INFO: Maximum SPI INTID supported: 639
9997 00:43:44.820696 INFO: BL31: Initializing runtime services
9998 00:43:44.823964 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9999 00:43:44.827085 INFO: SPM: enable CPC mode
10000 00:43:44.834198 INFO: mcdi ready for mcusys-off-idle and system suspend
10001 00:43:44.837514 INFO: BL31: Preparing for EL3 exit to normal world
10002 00:43:44.840958 INFO: Entry point address = 0x80000000
10003 00:43:44.844055 INFO: SPSR = 0x8
10004 00:43:44.849491
10005 00:43:44.849569
10006 00:43:44.849638
10007 00:43:44.852619 Starting depthcharge on Spherion...
10008 00:43:44.852737
10009 00:43:44.852829 Wipe memory regions:
10010 00:43:44.852924
10011 00:43:44.853787 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10012 00:43:44.853920 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10013 00:43:44.854029 Setting prompt string to ['asurada:']
10014 00:43:44.854142 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10015 00:43:44.856020 [0x00000040000000, 0x00000054600000)
10016 00:43:44.978615
10017 00:43:44.978742 [0x00000054660000, 0x00000080000000)
10018 00:43:45.239087
10019 00:43:45.239226 [0x000000821a7280, 0x000000ffe64000)
10020 00:43:45.983803
10021 00:43:45.983934 [0x00000100000000, 0x00000240000000)
10022 00:43:47.874769
10023 00:43:47.877585 Initializing XHCI USB controller at 0x11200000.
10024 00:43:48.916616
10025 00:43:48.920011 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10026 00:43:48.920118
10027 00:43:48.920183
10028 00:43:48.920464 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 00:43:49.020815 asurada: tftpboot 192.168.201.1 14173484/tftp-deploy-4bm95gxy/kernel/image.itb 14173484/tftp-deploy-4bm95gxy/kernel/cmdline
10031 00:43:49.020991 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 00:43:49.021115 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10033 00:43:49.025829 tftpboot 192.168.201.1 14173484/tftp-deploy-4bm95gxy/kernel/image.ittp-deploy-4bm95gxy/kernel/cmdline
10034 00:43:49.025933
10035 00:43:49.026026 Waiting for link
10036 00:43:49.186227
10037 00:43:49.186390 R8152: Initializing
10038 00:43:49.186485
10039 00:43:49.189595 Version 9 (ocp_data = 6010)
10040 00:43:49.189678
10041 00:43:49.192807 R8152: Done initializing
10042 00:43:49.192900
10043 00:43:49.192966 Adding net device
10044 00:43:51.064856
10045 00:43:51.065020 done.
10046 00:43:51.065133
10047 00:43:51.065224 MAC: 00:e0:4c:78:7a:aa
10048 00:43:51.065328
10049 00:43:51.068208 Sending DHCP discover... done.
10050 00:43:51.068323
10051 00:43:51.071594 Waiting for reply... done.
10052 00:43:51.071670
10053 00:43:51.075001 Sending DHCP request... done.
10054 00:43:51.075114
10055 00:43:51.075208 Waiting for reply... done.
10056 00:43:51.075307
10057 00:43:51.078299 My ip is 192.168.201.12
10058 00:43:51.078406
10059 00:43:51.081400 The DHCP server ip is 192.168.201.1
10060 00:43:51.081497
10061 00:43:51.084759 TFTP server IP predefined by user: 192.168.201.1
10062 00:43:51.084836
10063 00:43:51.091539 Bootfile predefined by user: 14173484/tftp-deploy-4bm95gxy/kernel/image.itb
10064 00:43:51.091617
10065 00:43:51.094620 Sending tftp read request... done.
10066 00:43:51.094733
10067 00:43:51.097835 Waiting for the transfer...
10068 00:43:51.097945
10069 00:43:51.361277 00000000 ################################################################
10070 00:43:51.361428
10071 00:43:51.620127 00080000 ################################################################
10072 00:43:51.620264
10073 00:43:51.881273 00100000 ################################################################
10074 00:43:51.881451
10075 00:43:52.135159 00180000 ################################################################
10076 00:43:52.135300
10077 00:43:52.392013 00200000 ################################################################
10078 00:43:52.392235
10079 00:43:52.641276 00280000 ################################################################
10080 00:43:52.641411
10081 00:43:52.887340 00300000 ################################################################
10082 00:43:52.887518
10083 00:43:53.135463 00380000 ################################################################
10084 00:43:53.135601
10085 00:43:53.381533 00400000 ################################################################
10086 00:43:53.381675
10087 00:43:53.630078 00480000 ################################################################
10088 00:43:53.630224
10089 00:43:53.880616 00500000 ################################################################
10090 00:43:53.880780
10091 00:43:54.132732 00580000 ################################################################
10092 00:43:54.132864
10093 00:43:54.396073 00600000 ################################################################
10094 00:43:54.396242
10095 00:43:54.655937 00680000 ################################################################
10096 00:43:54.656071
10097 00:43:54.912003 00700000 ################################################################
10098 00:43:54.912166
10099 00:43:55.168838 00780000 ################################################################
10100 00:43:55.169013
10101 00:43:55.428644 00800000 ################################################################
10102 00:43:55.428778
10103 00:43:55.681843 00880000 ################################################################
10104 00:43:55.681985
10105 00:43:55.934350 00900000 ################################################################
10106 00:43:55.934517
10107 00:43:56.186763 00980000 ################################################################
10108 00:43:56.186945
10109 00:43:56.439098 00a00000 ################################################################
10110 00:43:56.439266
10111 00:43:56.684682 00a80000 ################################################################
10112 00:43:56.684852
10113 00:43:56.943907 00b00000 ################################################################
10114 00:43:56.944066
10115 00:43:57.202205 00b80000 ################################################################
10116 00:43:57.202371
10117 00:43:57.456590 00c00000 ################################################################
10118 00:43:57.456719
10119 00:43:57.707824 00c80000 ################################################################
10120 00:43:57.707987
10121 00:43:57.958210 00d00000 ################################################################
10122 00:43:57.958340
10123 00:43:58.220352 00d80000 ################################################################
10124 00:43:58.220487
10125 00:43:58.472443 00e00000 ################################################################
10126 00:43:58.472590
10127 00:43:58.725594 00e80000 ################################################################
10128 00:43:58.725733
10129 00:43:58.976761 00f00000 ################################################################
10130 00:43:58.976921
10131 00:43:59.224190 00f80000 ################################################################
10132 00:43:59.224366
10133 00:43:59.469520 01000000 ################################################################
10134 00:43:59.469654
10135 00:43:59.711092 01080000 ################################################################
10136 00:43:59.711258
10137 00:43:59.954878 01100000 ################################################################
10138 00:43:59.955068
10139 00:44:00.191239 01180000 ################################################################
10140 00:44:00.191418
10141 00:44:00.444519 01200000 ################################################################
10142 00:44:00.444681
10143 00:44:00.692798 01280000 ################################################################
10144 00:44:00.692962
10145 00:44:00.945624 01300000 ################################################################
10146 00:44:00.945759
10147 00:44:01.201291 01380000 ################################################################
10148 00:44:01.201457
10149 00:44:01.452195 01400000 ################################################################
10150 00:44:01.452366
10151 00:44:01.699655 01480000 ################################################################
10152 00:44:01.699813
10153 00:44:01.961758 01500000 ################################################################
10154 00:44:01.961898
10155 00:44:02.220836 01580000 ################################################################
10156 00:44:02.220995
10157 00:44:02.479597 01600000 ################################################################
10158 00:44:02.479761
10159 00:44:02.742540 01680000 ################################################################
10160 00:44:02.742703
10161 00:44:02.992987 01700000 ################################################################
10162 00:44:02.993126
10163 00:44:03.241626 01780000 ################################################################
10164 00:44:03.241781
10165 00:44:03.489209 01800000 ################################################################
10166 00:44:03.489354
10167 00:44:03.741865 01880000 ################################################################
10168 00:44:03.742045
10169 00:44:03.991652 01900000 ################################################################
10170 00:44:03.991822
10171 00:44:04.244411 01980000 ################################################################
10172 00:44:04.244573
10173 00:44:04.498896 01a00000 ################################################################
10174 00:44:04.499063
10175 00:44:04.756187 01a80000 ################################################################
10176 00:44:04.756385
10177 00:44:05.005097 01b00000 ################################################################
10178 00:44:05.005271
10179 00:44:05.260691 01b80000 ################################################################
10180 00:44:05.260860
10181 00:44:05.519181 01c00000 ################################################################
10182 00:44:05.519388
10183 00:44:05.775198 01c80000 ################################################################
10184 00:44:05.775377
10185 00:44:06.026658 01d00000 ################################################################
10186 00:44:06.026811
10187 00:44:06.281157 01d80000 ################################################################
10188 00:44:06.281298
10189 00:44:06.528799 01e00000 ################################################################
10190 00:44:06.528977
10191 00:44:06.779564 01e80000 ################################################################
10192 00:44:06.779750
10193 00:44:07.034097 01f00000 ################################################################
10194 00:44:07.034275
10195 00:44:07.296497 01f80000 ################################################################
10196 00:44:07.296637
10197 00:44:07.546074 02000000 ################################################################
10198 00:44:07.546209
10199 00:44:07.747299 02080000 ################################################# done.
10200 00:44:07.747439
10201 00:44:07.750023 The bootfile was 34474790 bytes long.
10202 00:44:07.750110
10203 00:44:07.753604 Sending tftp read request... done.
10204 00:44:07.753693
10205 00:44:07.756742 Waiting for the transfer...
10206 00:44:07.756831
10207 00:44:07.756917 00000000 # done.
10208 00:44:07.756998
10209 00:44:07.766706 Command line loaded dynamically from TFTP file: 14173484/tftp-deploy-4bm95gxy/kernel/cmdline
10210 00:44:07.766800
10211 00:44:07.780200 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10212 00:44:07.780288
10213 00:44:07.780396 Loading FIT.
10214 00:44:07.780480
10215 00:44:07.783364 Image ramdisk-1 has 21365579 bytes.
10216 00:44:07.783450
10217 00:44:07.787170 Image fdt-1 has 47258 bytes.
10218 00:44:07.787255
10219 00:44:07.790505 Image kernel-1 has 13059919 bytes.
10220 00:44:07.790587
10221 00:44:07.800212 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10222 00:44:07.800304
10223 00:44:07.816619 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10224 00:44:07.816719
10225 00:44:07.819926 Choosing best match conf-1 for compat google,spherion-rev2.
10226 00:44:07.823167
10227 00:44:07.826572 Connected to device vid:did:rid of 1ae0:0028:00
10228 00:44:07.837048
10229 00:44:07.840283 tpm_get_response: command 0x17b, return code 0x0
10230 00:44:07.840371
10231 00:44:07.843737 ec_init: CrosEC protocol v3 supported (256, 248)
10232 00:44:07.848717
10233 00:44:07.851981 tpm_cleanup: add release locality here.
10234 00:44:07.852065
10235 00:44:07.852148 Shutting down all USB controllers.
10236 00:44:07.855394
10237 00:44:07.855472 Removing current net device
10238 00:44:07.855560
10239 00:44:07.861877 Exiting depthcharge with code 4 at timestamp: 52297443
10240 00:44:07.861990
10241 00:44:07.865089 LZMA decompressing kernel-1 to 0x821a6718
10242 00:44:07.865171
10243 00:44:07.868401 LZMA decompressing kernel-1 to 0x40000000
10244 00:44:09.478578
10245 00:44:09.478712 jumping to kernel
10246 00:44:09.479408 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10247 00:44:09.479546 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10248 00:44:09.479664 Setting prompt string to ['Linux version [0-9]']
10249 00:44:09.479772 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10250 00:44:09.479890 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10251 00:44:09.561533
10252 00:44:09.564721 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10253 00:44:09.568367 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10254 00:44:09.568494 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10255 00:44:09.568579 Setting prompt string to []
10256 00:44:09.568684 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10257 00:44:09.568798 Using line separator: #'\n'#
10258 00:44:09.568892 No login prompt set.
10259 00:44:09.569002 Parsing kernel messages
10260 00:44:09.569099 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10261 00:44:09.569286 [login-action] Waiting for messages, (timeout 00:04:01)
10262 00:44:09.569387 Waiting using forced prompt support (timeout 00:02:00)
10263 00:44:09.587734 [ 0.000000] Linux version 6.1.92-cip22-rt12 (KernelCI@build-j217237-arm64-gcc-10-defconfig-arm64-chromebook-pmq2q) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 5 00:22:12 UTC 2024
10264 00:44:09.590847 [ 0.000000] random: crng init done
10265 00:44:09.597536 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10266 00:44:09.600774 [ 0.000000] efi: UEFI not found.
10267 00:44:09.607221 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10268 00:44:09.617100 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10269 00:44:09.627637 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10270 00:44:09.634231 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10271 00:44:09.640861 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10272 00:44:09.647125 [ 0.000000] printk: bootconsole [mtk8250] enabled
10273 00:44:09.654119 [ 0.000000] NUMA: No NUMA configuration found
10274 00:44:09.660049 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10275 00:44:09.666881 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10276 00:44:09.666993 [ 0.000000] Zone ranges:
10277 00:44:09.673384 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10278 00:44:09.676964 [ 0.000000] DMA32 empty
10279 00:44:09.683421 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10280 00:44:09.686911 [ 0.000000] Movable zone start for each node
10281 00:44:09.690451 [ 0.000000] Early memory node ranges
10282 00:44:09.696643 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10283 00:44:09.703606 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10284 00:44:09.710299 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10285 00:44:09.716672 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10286 00:44:09.723368 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10287 00:44:09.729791 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10288 00:44:09.786395 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10289 00:44:09.793273 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10290 00:44:09.799287 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10291 00:44:09.802719 [ 0.000000] psci: probing for conduit method from DT.
10292 00:44:09.809319 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10293 00:44:09.812815 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10294 00:44:09.819059 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10295 00:44:09.822492 [ 0.000000] psci: SMC Calling Convention v1.2
10296 00:44:09.829058 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10297 00:44:09.832125 [ 0.000000] Detected VIPT I-cache on CPU0
10298 00:44:09.839321 [ 0.000000] CPU features: detected: GIC system register CPU interface
10299 00:44:09.846026 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10300 00:44:09.852480 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10301 00:44:09.859059 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10302 00:44:09.865762 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10303 00:44:09.875451 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10304 00:44:09.879245 [ 0.000000] alternatives: applying boot alternatives
10305 00:44:09.885563 [ 0.000000] Fallback order for Node 0: 0
10306 00:44:09.892555 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10307 00:44:09.895765 [ 0.000000] Policy zone: Normal
10308 00:44:09.908546 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10309 00:44:09.918868 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10310 00:44:09.930529 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10311 00:44:09.940489 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10312 00:44:09.947066 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10313 00:44:09.950336 <6>[ 0.000000] software IO TLB: area num 8.
10314 00:44:10.006813 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10315 00:44:10.156103 <6>[ 0.000000] Memory: 7943324K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 409444K reserved, 32768K cma-reserved)
10316 00:44:10.162782 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10317 00:44:10.169059 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10318 00:44:10.172887 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10319 00:44:10.179403 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10320 00:44:10.185586 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10321 00:44:10.188769 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10322 00:44:10.199102 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10323 00:44:10.205794 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10324 00:44:10.212145 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10325 00:44:10.218515 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10326 00:44:10.222029 <6>[ 0.000000] GICv3: 608 SPIs implemented
10327 00:44:10.225688 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10328 00:44:10.232269 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10329 00:44:10.235431 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10330 00:44:10.241875 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10331 00:44:10.255738 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10332 00:44:10.265696 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10333 00:44:10.275165 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10334 00:44:10.282989 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10335 00:44:10.295962 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10336 00:44:10.302497 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10337 00:44:10.309004 <6>[ 0.009179] Console: colour dummy device 80x25
10338 00:44:10.319181 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10339 00:44:10.325600 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10340 00:44:10.329175 <6>[ 0.029285] LSM: Security Framework initializing
10341 00:44:10.335888 <6>[ 0.034224] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10342 00:44:10.345634 <6>[ 0.042040] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10343 00:44:10.352749 <6>[ 0.051454] cblist_init_generic: Setting adjustable number of callback queues.
10344 00:44:10.359511 <6>[ 0.058944] cblist_init_generic: Setting shift to 3 and lim to 1.
10345 00:44:10.369201 <6>[ 0.065281] cblist_init_generic: Setting adjustable number of callback queues.
10346 00:44:10.372563 <6>[ 0.072708] cblist_init_generic: Setting shift to 3 and lim to 1.
10347 00:44:10.379173 <6>[ 0.079148] rcu: Hierarchical SRCU implementation.
10348 00:44:10.385824 <6>[ 0.079149] rcu: Max phase no-delay instances is 1000.
10349 00:44:10.392243 <6>[ 0.079173] printk: bootconsole [mtk8250] printing thread started
10350 00:44:10.398776 <6>[ 0.097503] EFI services will not be available.
10351 00:44:10.402353 <6>[ 0.097711] smp: Bringing up secondary CPUs ...
10352 00:44:10.405429 <6>[ 0.098018] Detected VIPT I-cache on CPU1
10353 00:44:10.412466 <6>[ 0.098087] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10354 00:44:10.422019 <6>[ 0.098120] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10355 00:44:10.431058 <6>[ 0.125944] Detected VIPT I-cache on CPU2
10356 00:44:10.440840 <6>[ 0.125996] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10357 00:44:10.447975 <6>[ 0.126015] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10358 00:44:10.451215 <6>[ 0.126273] Detected VIPT I-cache on CPU3
10359 00:44:10.457585 <6>[ 0.126322] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10360 00:44:10.464456 <6>[ 0.126337] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10361 00:44:10.467922 <6>[ 0.126648] CPU features: detected: Spectre-v4
10362 00:44:10.474377 <6>[ 0.126654] CPU features: detected: Spectre-BHB
10363 00:44:10.477667 <6>[ 0.126659] Detected PIPT I-cache on CPU4
10364 00:44:10.484038 <6>[ 0.126718] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10365 00:44:10.490877 <6>[ 0.126734] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10366 00:44:10.497054 <6>[ 0.127024] Detected PIPT I-cache on CPU5
10367 00:44:10.504191 <6>[ 0.127084] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10368 00:44:10.510701 <6>[ 0.127099] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10369 00:44:10.513626 <6>[ 0.127370] Detected PIPT I-cache on CPU6
10370 00:44:10.520702 <6>[ 0.127434] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10371 00:44:10.530862 <6>[ 0.127450] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10372 00:44:10.534138 <6>[ 0.127739] Detected PIPT I-cache on CPU7
10373 00:44:10.540375 <6>[ 0.127804] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10374 00:44:10.547078 <6>[ 0.127820] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10375 00:44:10.550980 <6>[ 0.127865] smp: Brought up 1 node, 8 CPUs
10376 00:44:10.557328 <6>[ 0.127870] SMP: Total of 8 processors activated.
10377 00:44:10.560710 <6>[ 0.127873] CPU features: detected: 32-bit EL0 Support
10378 00:44:10.570567 <6>[ 0.127875] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10379 00:44:10.577146 <6>[ 0.127877] CPU features: detected: Common not Private translations
10380 00:44:10.583906 <6>[ 0.127879] CPU features: detected: CRC32 instructions
10381 00:44:10.586910 <6>[ 0.127882] CPU features: detected: RCpc load-acquire (LDAPR)
10382 00:44:10.594077 <6>[ 0.127883] CPU features: detected: LSE atomic instructions
10383 00:44:10.600245 <6>[ 0.127885] CPU features: detected: Privileged Access Never
10384 00:44:10.607105 <6>[ 0.127886] CPU features: detected: RAS Extension Support
10385 00:44:10.613982 <6>[ 0.127890] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10386 00:44:10.617152 <6>[ 0.127956] CPU: All CPU(s) started at EL2
10387 00:44:10.623563 <6>[ 0.127958] alternatives: applying system-wide alternatives
10388 00:44:10.627013 <6>[ 0.141139] devtmpfs: initialized
10389 00:44:10.637494 <6>[ 0.147464] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10390 00:44:10.643412 <6>[ 0.147478] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10391 00:44:10.650477 <6>[ 0.148344] pinctrl core: initialized pinctrl subsystem
10392 00:44:10.674946 <6>[ 0.374623] printk: c<onsole [ttyS0] printing thread started
10393 00:44:10.678208 6>[ 0.149519] DMI not present or invalid.
10394 00:44:10.685112 <6>[ 0.374632] printk: console [ttyS0] enabled
10395 00:44:10.688269 <6>[ 0.374638] printk: bootconsole [mtk8250] disabled
10396 00:44:10.695077 <6>[ 0.384566] printk: bootconsole [mtk8250] printing thread stopped
10397 00:44:10.701158 <6>[ 0.385869] SuperH (H)SCI(F) driver initialized
10398 00:44:10.704833 <6>[ 0.386346] msm_serial: driver initialized
10399 00:44:10.714804 <6>[ 0.390898] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10400 00:44:10.721243 <6>[ 0.390927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10401 00:44:10.738039 <6>[ 0.390956] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10402 00:44:10.744850 <6>[ 0.390985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10403 00:44:10.756299 <6>[ 0.391008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10404 00:44:10.756655 <6>[ 0.391036] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10405 00:44:10.773501 <6>[ 0.391064] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10406 00:44:10.773594 <6>[ 0.391183] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10407 00:44:10.787489 <6>[ 0.391212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10408 00:44:10.794846 <6>[ 0.398110] loop: module loaded
10409 00:44:10.795175 <6>[ 0.400599] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10410 00:44:10.798278 <4>[ 0.417698] mtk-pmic-keys: Failed to locate of_node [id: -1]
10411 00:44:10.802130 <6>[ 0.418605] megasas: 07.719.03.00-rc1
10412 00:44:10.805182 <6>[ 0.428188] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10413 00:44:10.811675 <6>[ 0.436214] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10414 00:44:10.818456 <6>[ 0.448165] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10415 00:44:10.832016 <6>[ 0.502049] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10416 00:44:11.472811 <6>[ 1.172221] Freeing initrd memory: 20860K
10417 00:44:11.484610 <6>[ 1.183801] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10418 00:44:11.491365 <6>[ 1.188385] tun: Universal TUN/TAP device driver, 1.6
10419 00:44:11.494463 <6>[ 1.189132] thunder_xcv, ver 1.0
10420 00:44:11.498108 <6>[ 1.189149] thunder_bgx, ver 1.0
10421 00:44:11.501200 <6>[ 1.189166] nicpf, ver 1.0
10422 00:44:11.507789 <6>[ 1.190213] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10423 00:44:11.514471 <6>[ 1.190216] hns3: Copyright (c) 2017 Huawei Corporation.
10424 00:44:11.517884 <6>[ 1.190242] hclge is initializing
10425 00:44:11.521069 <6>[ 1.190254] e1000: Intel(R) PRO/1000 Network Driver
10426 00:44:11.528031 <6>[ 1.190256] e1000: Copyright (c) 1999-2006 Intel Corporation.
10427 00:44:11.535840 <6>[ 1.190272] e1000e: Intel(R) PRO/1000 Network Driver
10428 00:44:11.538934 <6>[ 1.190274] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10429 00:44:11.546094 <6>[ 1.190289] igb: Intel(R) Gigabit Ethernet Network Driver
10430 00:44:11.553275 <6>[ 1.190291] igb: Copyright (c) 2007-2014 Intel Corporation.
10431 00:44:11.559508 <6>[ 1.190304] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10432 00:44:11.563220 <6>[ 1.190306] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10433 00:44:11.570237 <6>[ 1.190592] sky2: driver version 1.30
10434 00:44:11.573136 <6>[ 1.191589] usbcore: registered new device driver r8152-cfgselector
10435 00:44:11.579608 <6>[ 1.191607] usbcore: registered new interface driver r8152
10436 00:44:11.586570 <6>[ 1.191682] VFIO - User Level meta-driver version: 0.3
10437 00:44:11.592961 <6>[ 1.194465] usbcore: registered new interface driver usb-storage
10438 00:44:11.599679 <6>[ 1.194643] usbcore: registered new device driver onboard-usb-hub
10439 00:44:11.603139 <6>[ 1.197394] mt6397-rtc mt6359-rtc: registered as rtc0
10440 00:44:11.613114 <6>[ 1.197541] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-05T00:39:30 UTC (1717547970)
10441 00:44:11.616633 <6>[ 1.198143] i2c_dev: i2c /dev entries driver
10442 00:44:11.626232 <6>[ 1.205175] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10443 00:44:11.633430 <4>[ 1.205890] cpu cpu0: supply cpu not found, using dummy regulator
10444 00:44:11.636459 <4>[ 1.205963] cpu cpu1: supply cpu not found, using dummy regulator
10445 00:44:11.642847 <4>[ 1.206041] cpu cpu2: supply cpu not found, using dummy regulator
10446 00:44:11.650114 <4>[ 1.206095] cpu cpu3: supply cpu not found, using dummy regulator
10447 00:44:11.656733 <4>[ 1.206144] cpu cpu4: supply cpu not found, using dummy regulator
10448 00:44:11.663070 <4>[ 1.206192] cpu cpu5: supply cpu not found, using dummy regulator
10449 00:44:11.670242 <4>[ 1.206241] cpu cpu6: supply cpu not found, using dummy regulator
10450 00:44:11.676876 <4>[ 1.206315] cpu cpu7: supply cpu not found, using dummy regulator
10451 00:44:11.679739 <6>[ 1.220982] cpu cpu0: EM: created perf domain
10452 00:44:11.686743 <6>[ 1.221294] cpu cpu4: EM: created perf domain
10453 00:44:11.693113 <6>[ 1.223045] sdhci: Secure Digital Host Controller Interface driver
10454 00:44:11.696333 <6>[ 1.223047] sdhci: Copyright(c) Pierre Ossman
10455 00:44:11.703498 <6>[ 1.223402] Synopsys Designware Multimedia Card Interface Driver
10456 00:44:11.709626 <6>[ 1.223763] sdhci-pltfm: SDHCI platform and OF driver helper
10457 00:44:11.713228 <6>[ 1.228036] ledtrig-cpu: registered to indicate activity on CPUs
10458 00:44:11.719596 <6>[ 1.228743] mmc0: CQHCI version 5.10
10459 00:44:11.726471 <6>[ 1.228800] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10460 00:44:11.729924 <6>[ 1.229102] usbcore: registered new interface driver usbhid
10461 00:44:11.736320 <6>[ 1.229103] usbhid: USB HID core driver
10462 00:44:11.743202 <6>[ 1.229215] spi_master spi0: will run message pump with realtime priority
10463 00:44:11.753472 <6>[ 1.262577] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10464 00:44:11.766912 <6>[ 1.265118] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10465 00:44:11.773473 <6>[ 1.266558] cros-ec-spi spi0.0: Chrome EC device registered
10466 00:44:11.783444 <6>[ 1.287698] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10467 00:44:11.789639 <6>[ 1.290901] NET: Registered PF_PACKET protocol family
10468 00:44:11.793070 <6>[ 1.291032] 9pnet: Installing 9P2000 support
10469 00:44:11.796692 <5>[ 1.291074] Key type dns_resolver registered
10470 00:44:11.803027 <6>[ 1.291499] registered taskstats version 1
10471 00:44:11.806111 <5>[ 1.291524] Loading compiled-in X.509 certificates
10472 00:44:11.816030 <4>[ 1.308715] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10473 00:44:11.829692 <4>[ 1.308988] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10474 00:44:11.832850 <3>[ 1.320411] mtk-msdc 11f60000.mmc: phase error: [map:0]
10475 00:44:11.839700 <3>[ 1.320418] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10476 00:44:11.846200 <3>[ 1.320421] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10477 00:44:11.852584 <3>[ 1.320430] mmc0: error -5 whilst initialising MMC card
10478 00:44:11.856253 <6>[ 1.322529] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10479 00:44:11.862454 <6>[ 1.323106] xhci-mtk 11200000.usb: xHCI Host Controller
10480 00:44:11.869564 <6>[ 1.323128] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10481 00:44:11.879170 <6>[ 1.323356] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10482 00:44:11.885660 <6>[ 1.323407] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10483 00:44:11.892212 <6>[ 1.323508] xhci-mtk 11200000.usb: xHCI Host Controller
10484 00:44:11.899139 <6>[ 1.323521] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10485 00:44:11.905754 <6>[ 1.323529] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10486 00:44:11.908691 <6>[ 1.324064] hub 1-0:1.0: USB hub found
10487 00:44:11.915733 <6>[ 1.324084] hub 1-0:1.0: 1 port detected
10488 00:44:11.922180 <6>[ 1.324309] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10489 00:44:11.925795 <6>[ 1.324588] hub 2-0:1.0: USB hub found
10490 00:44:11.932269 <6>[ 1.324606] hub 2-0:1.0: 1 port detected
10491 00:44:11.935424 <6>[ 1.328258] mtk-msdc 11f70000.mmc: Got CD GPIO
10492 00:44:11.942059 <6>[ 1.345834] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10493 00:44:11.952479 <6>[ 1.345843] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10494 00:44:11.958790 <4>[ 1.346031] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10495 00:44:11.968771 <6>[ 1.346717] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10496 00:44:11.975206 <6>[ 1.346722] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10497 00:44:11.985588 <6>[ 1.346853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10498 00:44:11.992064 <6>[ 1.346867] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10499 00:44:11.998485 <6>[ 1.346872] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10500 00:44:12.008132 <6>[ 1.346884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10501 00:44:12.018115 <6>[ 1.348540] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10502 00:44:12.024783 <6>[ 1.348561] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10503 00:44:12.034974 <6>[ 1.348568] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10504 00:44:12.041695 <6>[ 1.348576] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10505 00:44:12.051183 <6>[ 1.348583] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10506 00:44:12.058244 <6>[ 1.348590] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10507 00:44:12.068634 <6>[ 1.348597] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10508 00:44:12.074885 <6>[ 1.348604] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10509 00:44:12.084484 <6>[ 1.348611] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10510 00:44:12.091473 <6>[ 1.348618] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10511 00:44:12.101054 <6>[ 1.348625] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10512 00:44:12.107505 <6>[ 1.348632] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10513 00:44:12.117817 <6>[ 1.348639] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10514 00:44:12.124258 <6>[ 1.348646] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10515 00:44:12.134046 <6>[ 1.348653] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10516 00:44:12.140603 <6>[ 1.349433] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10517 00:44:12.146947 <6>[ 1.350545] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10518 00:44:12.154027 <6>[ 1.351247] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10519 00:44:12.160596 <6>[ 1.352030] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10520 00:44:12.166941 <6>[ 1.352847] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10521 00:44:12.177108 <6>[ 1.353138] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10522 00:44:12.183721 <6>[ 1.353158] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10523 00:44:12.193870 <6>[ 1.353166] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10524 00:44:12.203681 <6>[ 1.353174] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10525 00:44:12.214051 <6>[ 1.353182] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10526 00:44:12.223615 <6>[ 1.353190] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10527 00:44:12.230275 <6>[ 1.353197] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10528 00:44:12.240311 <6>[ 1.353204] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10529 00:44:12.250441 <6>[ 1.353211] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10530 00:44:12.260694 <6>[ 1.353220] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10531 00:44:12.270719 <6>[ 1.353226] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10532 00:44:12.280329 <6>[ 1.354175] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10533 00:44:12.283870 <6>[ 1.417076] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10534 00:44:12.290792 <6>[ 1.423703] mmc0: Command Queue Engine enabled
10535 00:44:12.297258 <6>[ 1.423712] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10536 00:44:12.300593 <6>[ 1.424161] mmcblk0: mmc0:0001 DA4128 116 GiB
10537 00:44:12.306905 <6>[ 1.427361] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10538 00:44:12.313313 <6>[ 1.428427] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10539 00:44:12.316744 <6>[ 1.428985] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10540 00:44:12.323644 <6>[ 1.429623] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10541 00:44:12.330050 <6>[ 1.732969] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10542 00:44:12.333241 <6>[ 1.888744] hub 1-1:1.0: USB hub found
10543 00:44:12.339876 <6>[ 1.889118] hub 1-1:1.0: 4 ports detected
10544 00:44:12.343112 <6>[ 1.892638] hub 1-1:1.0: USB hub found
10545 00:44:12.346359 <6>[ 1.892960] hub 1-1:1.0: 4 ports detected
10546 00:44:12.353300 <6>[ 2.021198] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10547 00:44:12.356247 <6>[ 2.045222] hub 2-1:1.0: USB hub found
10548 00:44:12.362873 <6>[ 2.045617] hub 2-1:1.0: 3 ports detected
10549 00:44:12.366137 <6>[ 2.048365] hub 2-1:1.0: USB hub found
10550 00:44:12.369338 <6>[ 2.048721] hub 2-1:1.0: 3 ports detected
10551 00:44:12.511609 <6>[ 2.205104] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10552 00:44:12.632750 <6>[ 2.331924] hub 1-1.4:1.0: USB hub found
10553 00:44:12.635697 <6>[ 2.332234] hub 1-1.4:1.0: 2 ports detected
10554 00:44:12.638904 <6>[ 2.334814] hub 1-1.4:1.0: USB hub found
10555 00:44:12.645868 <6>[ 2.335099] hub 1-1.4:1.0: 2 ports detected
10556 00:44:12.715909 <6>[ 2.409203] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10557 00:44:12.819837 <6>[ 2.513468] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10558 00:44:12.839917 <4>[ 2.536748] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10559 00:44:12.849552 <4>[ 2.536767] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10560 00:44:12.876229 <6>[ 2.574144] r8152 2-1.3:1.0 eth0: v1.12.13
10561 00:44:12.928229 <6>[ 2.621121] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10562 00:44:13.111840 <6>[ 2.805120] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10563 00:44:14.588272 <6>[ 4.288386] r8152 2-1.3:1.0 eth0: carrier on
10564 00:44:16.944490 <5>[ 4.316979] Sending DHCP requests .
10565 00:44:16.951426 <3>[ 6.645274] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[52f87a54]
10566 00:44:16.958009 <3>[ 6.649303] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[52f87a54]
10567 00:44:17.296887 <4>[ 6.981110] ., OK
10568 00:44:17.306844 <6>[ 6.997034] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10569 00:44:17.310222 <6>[ 6.997050] IP-Config: Complete:
10570 00:44:17.320057 <6>[ 6.997053] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10571 00:44:17.330350 <6>[ 6.997064] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10572 00:44:17.336792 <6>[ 6.997070] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10573 00:44:17.343505 Starting syslogd<6>[ 6.997075] nameserver0=192.168.201.1
10574 00:44:17.346829 : <6>[ 6.997358] clk: Disabling unused clocks
10575 00:44:17.346935 OK
10576 00:44:17.350085 Starting klo<6>[ 6.998928] ALSA device list:
10577 00:44:17.353265 gd: OK
10578 00:44:17.356531 <6>[ 6.998941] No soundcards found.
10579 00:44:17.360239 <6>[ 7.003203] Freeing unused kernel memory: 8512K
10580 00:44:17.366425 Running sysctl: <6>[ 7.003397] Run /init as init process
10581 00:44:17.366509 OK
10582 00:44:17.376708 Populating /dev using udev: <30>[ 7.075927] udevd[190]: starting version 3.2.9
10583 00:44:17.380031 <27>[ 7.077910] udevd[190]: specified user 'tss' unknown
10584 00:44:17.386430 <27>[ 7.077934] udevd[190]: specified group 'tss' unknown
10585 00:44:17.389603 <30>[ 7.078965] udevd[191]: starting eudev-3.2.9
10586 00:44:17.495056 <6>[ 7.191732] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10587 00:44:17.504165 <6>[ 7.201331] remoteproc remoteproc0: scp is available
10588 00:44:17.511062 <6>[ 7.201468] remoteproc remoteproc0: powering up scp
10589 00:44:17.517534 <6>[ 7.201481] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10590 00:44:17.524006 <6>[ 7.201560] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10591 00:44:17.535907 <6>[ 7.227485] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10592 00:44:17.542492 <6>[ 7.227572] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10593 00:44:17.552374 <6>[ 7.227588] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10594 00:44:17.567252 <3>[ 7.263794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10595 00:44:17.573772 <3>[ 7.263830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10596 00:44:17.583621 <3>[ 7.263835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10597 00:44:17.590765 <3>[ 7.264134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10598 00:44:17.600511 <3>[ 7.264139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10599 00:44:17.607659 <3>[ 7.264141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 00:44:17.614257 <3>[ 7.264146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10601 00:44:17.624322 <3>[ 7.264149] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10602 00:44:17.630850 <3>[ 7.264287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10603 00:44:17.641490 <3>[ 7.264412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10604 00:44:17.648279 <3>[ 7.264417] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10605 00:44:17.654584 <3>[ 7.264420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10606 00:44:17.664949 <3>[ 7.264490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10607 00:44:17.671082 <3>[ 7.264498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 00:44:17.681390 <3>[ 7.264502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 00:44:17.687566 <3>[ 7.264507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 00:44:17.697943 <3>[ 7.264510] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10611 00:44:17.704504 <3>[ 7.264554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 00:44:17.711035 <6>[ 7.277882] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10613 00:44:17.717602 <6>[ 7.289971] mc: Linux media interface: v0.10
10614 00:44:17.724061 <4>[ 7.301781] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10615 00:44:17.730604 <4>[ 7.301781] Fallback method does not support PEC.
10616 00:44:17.737692 <6>[ 7.306420] videodev: Linux video capture interface: v2.00
10617 00:44:17.743828 <3>[ 7.318843] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10618 00:44:17.754077 <6>[ 7.327804] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10619 00:44:17.760983 <6>[ 7.327806] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10620 00:44:17.767597 <6>[ 7.327817] remoteproc remoteproc0: remote processor scp is now up
10621 00:44:17.774252 <4>[ 7.339949] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10622 00:44:17.781034 <4>[ 7.341322] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10623 00:44:17.790569 <3>[ 7.346403] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 00:44:17.797343 <6>[ 7.354531] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10625 00:44:17.803964 <6>[ 7.354542] pci_bus 0000:00: root bus resource [bus 00-ff]
10626 00:44:17.810485 <6>[ 7.354547] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10627 00:44:17.820277 <6>[ 7.354549] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10628 00:44:17.827309 <6>[ 7.354581] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10629 00:44:17.833705 <6>[ 7.354595] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10630 00:44:17.836838 <6>[ 7.354668] pci 0000:00:00.0: supports D1 D2
10631 00:44:17.843796 <6>[ 7.354669] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10632 00:44:17.853934 <6>[ 7.355726] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10633 00:44:17.860516 <6>[ 7.355913] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10634 00:44:17.866939 <6>[ 7.355940] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10635 00:44:17.873570 <6>[ 7.355960] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10636 00:44:17.883847 <6>[ 7.355976] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10637 00:44:17.886812 <6>[ 7.356097] pci 0000:01:00.0: supports D1 D2
10638 00:44:17.893247 <6>[ 7.356100] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10639 00:44:17.900501 <6>[ 7.364965] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10640 00:44:17.910293 <6>[ 7.365028] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10641 00:44:17.916800 <6>[ 7.365031] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10642 00:44:17.923374 <6>[ 7.365040] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10643 00:44:17.933149 <6>[ 7.365053] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10644 00:44:17.939771 <6>[ 7.365066] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10645 00:44:17.946705 <6>[ 7.365078] pci 0000:00:00.0: PCI bridge to [bus 01]
10646 00:44:17.952980 <6>[ 7.365083] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10647 00:44:17.960044 <6>[ 7.365279] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10648 00:44:17.966536 <6>[ 7.366600] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10649 00:44:17.973182 <6>[ 7.369367] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10650 00:44:17.979804 <6>[ 7.423966] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10651 00:44:17.989279 <6>[ 7.426290] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10652 00:44:17.996305 <6>[ 7.448704] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10653 00:44:18.009636 <6>[ 7.490641] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10654 00:44:18.015898 <6>[ 7.490934] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10655 00:44:18.019596 <6>[ 7.509639] Bluetooth: Core ver 2.22
10656 00:44:18.026143 <6>[ 7.509772] NET: Registered PF_BLUETOOTH protocol family
10657 00:44:18.032710 <6>[ 7.509776] Bluetooth: HCI device and connection manager initialized
10658 00:44:18.039286 <6>[ 7.509807] Bluetooth: HCI socket layer initialized
10659 00:44:18.043029 <6>[ 7.509815] Bluetooth: L2CAP socket layer initialized
10660 00:44:18.049528 <6>[ 7.509823] Bluetooth: SCO socket layer initialized
10661 00:44:18.055699 <5>[ 7.517819] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10662 00:44:18.062285 <6>[ 7.518137] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10663 00:44:18.075693 <6>[ 7.519442] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10664 00:44:18.082349 <6>[ 7.519631] usbcore: registered new interface driver uvcvideo
10665 00:44:18.089037 <6>[ 7.541005] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10666 00:44:18.095911 <5>[ 7.546780] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10667 00:44:18.102267 <5>[ 7.547022] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10668 00:44:18.112614 <4>[ 7.547095] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10669 00:44:18.118707 <6>[ 7.547102] cfg80211: failed to load regulatory.db
10670 00:44:18.122237 <6>[ 7.566784] usbcore: registered new interface driver btusb
10671 00:44:18.131844 <4>[ 7.568041] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10672 00:44:18.138487 <3>[ 7.568057] Bluetooth: hci0: Failed to load firmware file (-2)
10673 00:44:18.145132 <3>[ 7.568061] Bluetooth: hci0: Failed to set up firmware (-2)
10674 00:44:18.155434 <4>[ 7.568066] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10675 00:44:18.161682 <6>[ 7.641141] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10676 00:44:18.168751 <6>[ 7.641239] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10677 00:44:18.174802 <6>[ 7.661013] mt7921e 0000:01:00.0: ASIC revision: 79610010
10678 00:44:18.184881 <6>[ 7.755713] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10679 00:44:18.184981 <6>[ 7.755713]
10680 00:44:18.253217 done
10681 00:44:18.264939 Saving random seed: OK
10682 00:44:18.277097 Starting network: ip: RTNETLINK answers: File exists
10683 00:44:18.281045 FAIL
10684 00:44:18.319794 Starting dropbear sshd: <6>[ 8.015513] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10685 00:44:18.328329 OK
10686 00:44:18.332000 <6>[ 8.029554] NET: Registered PF_INET6 protocol family
10687 00:44:18.335163 <6>[ 8.030867] Segment Routing with IPv6
10688 00:44:18.341876 <6>[ 8.030879] In-situ OAM (IOAM) with IPv6
10689 00:44:18.345165 /bin/sh: can't access tty; job control turned off
10690 00:44:18.345520 Matched prompt #10: / #
10692 00:44:18.345826 Setting prompt string to ['/ #']
10693 00:44:18.345950 end: 2.2.5.1 login-action (duration 00:00:09) [common]
10695 00:44:18.346183 end: 2.2.5 auto-login-action (duration 00:00:09) [common]
10696 00:44:18.346273 start: 2.2.6 expect-shell-connection (timeout 00:03:52) [common]
10697 00:44:18.346343 Setting prompt string to ['/ #']
10698 00:44:18.346403 Forcing a shell prompt, looking for ['/ #']
10700 00:44:18.396604 / #
10701 00:44:18.396762 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10702 00:44:18.396844 Waiting using forced prompt support (timeout 00:02:30)
10703 00:44:18.401954
10704 00:44:18.402237 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10705 00:44:18.402333 start: 2.2.7 export-device-env (timeout 00:03:52) [common]
10706 00:44:18.402462 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10707 00:44:18.402549 end: 2.2 depthcharge-retry (duration 00:01:08) [common]
10708 00:44:18.402630 end: 2 depthcharge-action (duration 00:01:08) [common]
10709 00:44:18.402740 start: 3 lava-test-retry (timeout 00:01:00) [common]
10710 00:44:18.402838 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10711 00:44:18.402911 Using namespace: common
10713 00:44:18.503338 / # #
10714 00:44:18.503512 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10715 00:44:18.508597 #
10716 00:44:18.508865 Using /lava-14173484
10718 00:44:18.609226 / # export SHELL=/bin/sh
10719 00:44:18.614620 export SHELL=/bin/sh
10721 00:44:18.715272 / # . /lava-14173484/environment
10722 00:44:18.720698 . /lava-14173484/environment
10724 00:44:18.821247 / # /lava-14173484/bin/lava-test-runner /lava-14173484/0
10725 00:44:18.821414 Test shell timeout: 10s (minimum of the action and connection timeout)
10726 00:44:18.826568 /lava-14173484/bin/lava-test-runner /lava-14173484/0
10727 00:44:18.847379 + export 'TESTRUN_ID=0_dmesg'
10728 00:44:18.857708 + cd /lava-14173484/0/tests/0_dme<8>[ 8.554319] <LAVA_SIGNAL_STARTRUN 0_dmesg 14173484_1.5.2.3.1>
10729 00:44:18.857812 sg
10730 00:44:18.857878 + cat uuid
10731 00:44:18.858145 Received signal: <STARTRUN> 0_dmesg 14173484_1.5.2.3.1
10732 00:44:18.858214 Starting test lava.0_dmesg (14173484_1.5.2.3.1)
10733 00:44:18.858291 Skipping test definition patterns.
10734 00:44:18.861212 + UUID=14173484_1.5.2.3.1
10735 00:44:18.861294 + set +x
10736 00:44:18.870934 + KERNELCI_<8>[ 8.567046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10737 00:44:18.871189 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10739 00:44:18.874370 LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10740 00:44:18.884276 <8>[ 8.579930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10741 00:44:18.884587 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10743 00:44:18.890201 + set +x
10744 00:44:18.900600 <LAVA_TEST_RUNNE<8>[ 8.593805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10745 00:44:18.900891 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10747 00:44:18.906616 <8>[ 8.594633] <LAVA_SIGNAL_ENDRUN 0_dmesg 14173484_1.5.2.3.1>
10748 00:44:18.906725 R EXIT>
10749 00:44:18.906989 Received signal: <ENDRUN> 0_dmesg 14173484_1.5.2.3.1
10750 00:44:18.907096 Ending use of test pattern.
10751 00:44:18.907183 Ending test lava.0_dmesg (14173484_1.5.2.3.1), duration 0.05
10753 00:44:19.148032 / # <6>[ 8.848463] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10754 00:44:48.185217 <6>[ 37.889171] vpu: disabling
10755 00:44:48.188905 <6>[ 37.889301] vproc2: disabling
10756 00:44:48.192228 <6>[ 37.889355] vproc1: disabling
10757 00:44:48.195463 <6>[ 37.889409] vaud18: disabling
10758 00:44:48.198581 <6>[ 37.889659] vsram_others: disabling
10759 00:44:48.201673 <6>[ 37.889839] va09: disabling
10760 00:44:48.205246 <6>[ 37.889916] vsram_md: disabling
10761 00:44:48.208318 <6>[ 37.890047] Vgpu: disabling
10763 00:45:18.403205 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10765 00:45:18.403681 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10767 00:45:18.404022 end: 3 lava-test-retry (duration 00:01:00) [common]
10769 00:45:18.404537 Cleaning after the job
10770 00:45:18.404724 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/ramdisk
10771 00:45:18.409048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/kernel
10772 00:45:18.428309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/dtb
10773 00:45:18.428710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14173484/tftp-deploy-4bm95gxy/modules
10774 00:45:18.438429 start: 4.1 power-off (timeout 00:00:30) [common]
10775 00:45:18.438870 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
10776 00:45:18.518440 >> Command sent successfully.
10777 00:45:18.521296 Returned 0 in 0 seconds
10778 00:45:18.621756 end: 4.1 power-off (duration 00:00:00) [common]
10780 00:45:18.622205 start: 4.2 read-feedback (timeout 00:10:00) [common]
10781 00:45:18.622512 Listened to connection for namespace 'common' for up to 1s
10782 00:45:19.623028 Finalising connection for namespace 'common'
10783 00:45:19.623236 Disconnecting from shell: Finalise
10784 00:45:19.723572 end: 4.2 read-feedback (duration 00:00:01) [common]
10785 00:45:19.723732 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14173484
10786 00:45:19.767717 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14173484
10787 00:45:19.767908 TestError: A test failed to run, look at the error message.